| blob | 07c55b132a7a8c4ceeaf9f406ac8c3c9d7b6bb20 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
75 /* This file should be included last. */
78 /* Defined for convenience. */
79 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
81 /* Classifies an address.
83 ADDRESS_REG_IMM
84 A simple base register plus immediate offset.
86 ADDRESS_REG_WB
87 A base register indexed by immediate offset with writeback.
89 ADDRESS_REG_REG
90 A base register indexed by (optionally scaled) register.
92 ADDRESS_REG_UXTW
93 A base register indexed by (optionally scaled) zero-extended register.
95 ADDRESS_REG_SXTW
96 A base register indexed by (optionally scaled) sign-extended register.
98 ADDRESS_LO_SUM
99 A LO_SUM rtx with a base register and "LO12" symbol relocation.
101 ADDRESS_SYMBOLIC:
102 A constant symbolic address, in pc-relative literal pool. */
105 ADDRESS_REG_IMM,
106 ADDRESS_REG_WB,
107 ADDRESS_REG_REG,
108 ADDRESS_REG_UXTW,
109 ADDRESS_REG_SXTW,
110 ADDRESS_LO_SUM,
111 ADDRESS_SYMBOLIC
112 };
116 rtx base;
117 rtx offset;
118 poly_int64 const_offset;
121 };
123 /* Information about a legitimate vector immediate operand. */
124 struct simd_immediate_info
125 {
136 /* The mode of the elements. */
137 scalar_mode elt_mode;
139 /* The value of each element if all elements are the same, or the
140 first value if the constant is a series. */
141 rtx value;
143 /* The value of the step if the constant is a series, null otherwise. */
144 rtx step;
146 /* The instruction to use to move the immediate into a vector. */
147 insn_type insn;
149 /* The kind of shift modifier to use, and the number of bits to shift.
150 This is (LSL, 0) if no shift is needed. */
151 modifier_type modifier;
153 };
155 /* Construct a floating-point immediate in which each element has mode
156 ELT_MODE_IN and value VALUE_IN. */
157 inline simd_immediate_info
161 {}
163 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
164 and value VALUE_IN. The other parameters are as for the structure
165 fields. */
166 inline simd_immediate_info
173 {}
175 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
176 and where element I is equal to VALUE_IN + I * STEP_IN. */
177 inline simd_immediate_info
181 {}
183 /* The current code model. */
186 /* The number of 64-bit elements in an SVE vector. */
187 poly_uint16 aarch64_sve_vg;
189 #ifdef HAVE_AS_TLS
190 #undef TARGET_HAVE_TLS
191 #define TARGET_HAVE_TLS 1
192 #endif
196 const_tree,
205 const_tree type,
211 /* Major revision number of the ARM Architecture implemented by the target. */
214 /* The processor for which instructions should be scheduled. */
217 /* Mask to specify which instruction scheduling options should be used. */
220 /* Global flag for PC relative loads. */
223 /* Support for command line parsing of boolean flags in the tuning
224 structures. */
225 struct aarch64_flag_desc
226 {
229 };
231 #define AARCH64_FUSION_PAIR(name, internal_name) \
232 { name, AARCH64_FUSE_##internal_name },
234 {
239 };
241 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
242 { name, AARCH64_EXTRA_TUNE_##internal_name },
244 {
249 };
251 /* Tuning parameters. */
254 {
255 {
260 },
267 };
270 {
271 {
276 },
283 };
286 {
287 {
292 },
299 };
302 {
303 {
308 },
315 };
318 {
320 /* Avoid the use of slow int<->fp moves for spilling by setting
321 their cost higher than memmov_cost. */
325 };
328 {
330 /* Avoid the use of slow int<->fp moves for spilling by setting
331 their cost higher than memmov_cost. */
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of slow int<->fp moves for spilling by setting
351 their cost higher than memmov_cost (actual, 4 and 9). */
355 };
358 {
363 };
366 {
368 /* Avoid the use of slow int<->fp moves for spilling by setting
369 their cost higher than memmov_cost. */
373 };
376 {
378 /* Avoid the use of int<->fp moves for spilling. */
382 };
385 {
387 /* Avoid the use of int<->fp moves for spilling. */
391 };
393 /* Generic costs for vector insn classes. */
395 {
411 };
413 /* ThunderX costs for vector insn classes. */
415 {
431 };
433 /* Generic costs for vector insn classes. */
435 {
451 };
454 {
470 };
472 /* Generic costs for vector insn classes. */
474 {
490 };
492 /* Costs for vector insn classes for Vulcan. */
494 {
510 };
512 /* Generic costs for branch instructions. */
514 {
517 };
519 /* Generic approximation modes. */
521 {
524 AARCH64_APPROX_NONE /* recip_sqrt */
525 };
527 /* Approximation modes for Exynos M1. */
529 {
532 AARCH64_APPROX_ALL /* recip_sqrt */
533 };
535 /* Approximation modes for X-Gene 1. */
537 {
540 AARCH64_APPROX_ALL /* recip_sqrt */
541 };
543 /* Generic prefetch settings (which disable prefetch). */
545 {
551 };
554 {
560 };
563 {
569 };
572 {
578 };
581 {
587 };
590 {
596 };
599 {
620 &generic_prefetch_tune
621 };
624 {
646 &generic_prefetch_tune
647 };
650 {
672 &generic_prefetch_tune
673 };
676 {
698 &generic_prefetch_tune
699 };
702 {
724 &generic_prefetch_tune
725 };
728 {
750 &generic_prefetch_tune
751 };
756 {
777 &exynosm1_prefetch_tune
778 };
781 {
802 &thunderxt88_prefetch_tune
803 };
806 {
826 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
828 &thunderx_prefetch_tune
829 };
832 {
853 &generic_prefetch_tune
854 };
857 {
879 &qdf24xx_prefetch_tune
880 };
882 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
883 for now. */
885 {
907 &generic_prefetch_tune
908 };
911 {
933 &thunderx2t99_prefetch_tune
934 };
936 /* Support for fine-grained override of the tuning structures. */
937 struct aarch64_tuning_override_function
938 {
941 };
946 static const struct aarch64_tuning_override_function
947 aarch64_tuning_override_functions[] =
948 {
952 };
954 /* A processor implementing AArch64. */
955 struct processor
956 {
964 };
966 /* Architectures implementing AArch64. */
968 {
969 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
970 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
973 };
975 /* Processor cores implementing AArch64. */
977 {
978 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
979 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
980 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
981 FLAGS, &COSTS##_tunings},
986 };
989 /* Target specification. These are populated by the -march, -mtune, -mcpu
990 handling code or by target attributes. */
995 /* The current tuning set. */
998 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
1000 /* An ISA extension in the co-processor and main instruction set space. */
1001 struct aarch64_option_extension
1002 {
1006 };
1009 {
1013 }
1014 aarch64_cc;
1016 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
1018 /* The condition codes of the processor, and the inverse function. */
1020 {
1023 };
1025 /* Generate code to enable conditional branches in functions over 1 MiB. */
1029 {
1046 }
1048 void
1050 {
1054 else
1056 }
1058 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1059 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
1060 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
1061 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
1062 cost (in this case the best class is the lowest cost one). Using ALL_REGS
1063 irrespectively of its cost results in bad allocations with many redundant
1064 int<->FP moves which are expensive on various cores.
1065 To avoid this we don't allow ALL_REGS as the allocno class, but force a
1066 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
1067 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
1068 Otherwise set the allocno class depending on the mode.
1069 The result of this is that it is no longer inefficient to have a higher
1070 memory move cost than the register move cost.
1071 */
1073 static reg_class_t
1075 reg_class_t best_class)
1076 {
1077 machine_mode mode;
1087 }
1089 static unsigned int
1091 {
1095 }
1097 /* Return the reassociation width of treeop OPC with mode MODE. */
1098 static int
1100 {
1105 /* Avoid reassociating floating point addition so we emit more FMAs. */
1109 }
1111 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1112 unsigned
1114 {
1126 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1127 equivalent DWARF register. */
1129 }
1131 /* Return true if MODE is any of the Advanced SIMD structure modes. */
1132 static bool
1134 {
1137 }
1139 /* Return true if MODE is an SVE predicate mode. */
1140 static bool
1142 {
1148 }
1150 /* Three mutually-exclusive flags describing a vector or predicate type. */
1154 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
1155 a structure of 2, 3 or 4 vectors. */
1157 /* Useful combinations of the above. */
1161 /* Return a set of flags describing the vector properties of mode MODE.
1162 Ignore modes that are not supported by the current target. */
1163 static unsigned int
1165 {
1181 {
1183 {
1190 }
1192 /* This includes V1DF but not V1DI (which doesn't exist). */
1197 }
1200 }
1202 /* Return true if MODE is any of the data vector modes, including
1203 structure modes. */
1204 static bool
1206 {
1208 }
1210 /* Return true if MODE is an SVE data vector mode; either a single vector
1211 or a structure of vectors. */
1212 static bool
1214 {
1216 }
1218 /* Implement target hook TARGET_ARRAY_MODE. */
1219 static opt_machine_mode
1221 {
1228 }
1230 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1231 static bool
1234 {
1242 }
1244 /* Return the SVE predicate mode to use for elements that have
1245 ELEM_NBYTES bytes, if such a mode exists. */
1247 opt_machine_mode
1249 {
1251 {
1260 }
1262 }
1264 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
1266 static opt_machine_mode
1268 {
1270 {
1272 machine_mode pred_mode;
1275 }
1278 }
1280 /* Implement TARGET_HARD_REGNO_NREGS. */
1282 static unsigned int
1284 {
1285 /* ??? Logically we should only need to provide a value when
1286 HARD_REGNO_MODE_OK says that the combination is valid,
1287 but at the moment we need to handle all modes. Just ignore
1288 any runtime parts for registers that can't store them. */
1291 {
1304 }
1306 }
1308 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1310 static bool
1312 {
1317 /* This must have the same size as _Unwind_Word. */
1328 /* The purpose of comparing with ptr_mode is to support the
1329 global register variable associated with the stack pointer
1330 register via the syntax of asm ("wsp") in ILP32. */
1340 {
1343 else
1345 }
1348 }
1350 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1351 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1352 clobbers the top 64 bits when restoring the bottom 64 bits. */
1354 static bool
1356 {
1358 }
1360 /* Implement REGMODE_NATURAL_SIZE. */
1361 poly_uint64
1363 {
1364 /* The natural size for SVE data modes is one SVE data vector,
1365 and similarly for predicates. We can't independently modify
1366 anything smaller than that. */
1367 /* ??? For now, only do this for variable-width SVE registers.
1368 Doing it for constant-sized registers breaks lower-subreg.c. */
1369 /* ??? And once that's fixed, we should probably have similar
1370 code for Advanced SIMD. */
1372 {
1378 }
1380 }
1382 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1383 machine_mode
1385 machine_mode mode)
1386 {
1387 /* The predicate mode determines which bits are significant and
1388 which are "don't care". Decreasing the number of lanes would
1389 lose data while increasing the number of lanes would make bits
1390 unnecessarily significant. */
1395 else
1397 }
1399 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1400 that strcpy from constants will be faster. */
1402 static HOST_WIDE_INT
1404 {
1408 }
1410 /* Return true if calls to DECL should be treated as
1411 long-calls (ie called via a register). */
1412 static bool
1414 {
1416 }
1418 /* Return true if calls to symbol-ref SYM should be treated as
1419 long-calls (ie called via a register). */
1420 bool
1422 {
1424 }
1426 /* Return true if calls to symbol-ref SYM should not go through
1427 plt stubs. */
1429 bool
1431 {
1435 && decl
1436 && (!flag_plt
1442 }
1444 /* Return true if the offsets to a zero/sign-extract operation
1445 represent an expression that matches an extend operation. The
1446 operands represent the paramters from
1448 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1449 bool
1451 rtx extract_imm)
1452 {
1469 }
1471 /* Emit an insn that's a simple single-set. Both the operands must be
1472 known to be valid. */
1475 {
1477 }
1479 /* X and Y are two things to compare using CODE. Emit the compare insn and
1480 return the rtx for register 0 in the proper mode. */
1481 rtx
1483 {
1489 }
1491 /* Build the SYMBOL_REF for __tls_get_addr. */
1495 rtx
1497 {
1501 }
1503 /* Return the TLS model to use for ADDR. */
1505 static enum tls_model
1507 {
1510 {
1511 poly_int64 addend;
1515 }
1520 }
1522 /* We'll allow lo_sum's in addresses in our legitimate addresses
1523 so that combine would take care of combining addresses where
1524 necessary, but for generation purposes, we'll generate the address
1525 as :
1526 RTL Absolute
1527 tmp = hi (symbol_ref); adrp x1, foo
1528 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1529 nop
1531 PIC TLS
1532 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1533 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1534 bl __tls_get_addr
1535 nop
1537 Load TLS symbol, depending on TLS mechanism and TLS access model.
1539 Global Dynamic - Traditional TLS:
1540 adrp tmp, :tlsgd:imm
1541 add dest, tmp, #:tlsgd_lo12:imm
1542 bl __tls_get_addr
1544 Global Dynamic - TLS Descriptors:
1545 adrp dest, :tlsdesc:imm
1546 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1547 add dest, dest, #:tlsdesc_lo12:imm
1548 blr tmp
1549 mrs tp, tpidr_el0
1550 add dest, dest, tp
1552 Initial Exec:
1553 mrs tp, tpidr_el0
1554 adrp tmp, :gottprel:imm
1555 ldr dest, [tmp, #:gottprel_lo12:imm]
1556 add dest, dest, tp
1558 Local Exec:
1559 mrs tp, tpidr_el0
1560 add t0, tp, #:tprel_hi12:imm, lsl #12
1561 add t0, t0, #:tprel_lo12_nc:imm
1562 */
1564 static void
1567 {
1569 {
1571 {
1572 /* In ILP32, the mode of dest can be either SImode or DImode. */
1584 }
1591 {
1594 rtx insn;
1595 rtx mem;
1597 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1598 here before rtl expand. Tree IVOPT will generate rtl pattern to
1599 decide rtx costs, in which case pic_offset_table_rtx is not
1600 initialized. For that case no need to generate the first adrp
1601 instruction as the final cost for global variable access is
1602 one instruction. */
1604 {
1605 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1606 using the page base as GOT base, the first page may be wasted,
1607 in the worst scenario, there is only 28K space for GOT).
1609 The generate instruction sequence for accessing global variable
1610 is:
1612 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1614 Only one instruction needed. But we must initialize
1615 pic_offset_table_rtx properly. We generate initialize insn for
1616 every global access, and allow CSE to remove all redundant.
1618 The final instruction sequences will look like the following
1619 for multiply global variables access.
1621 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1623 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1624 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1625 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1626 ... */
1635 }
1638 {
1641 else
1645 }
1646 else
1647 {
1652 }
1654 /* The operand is expected to be MEM. Whenever the related insn
1655 pattern changed, above code which calculate mem should be
1656 updated. */
1662 }
1665 {
1666 /* In ILP32, the mode of dest can be either SImode or DImode,
1667 while the got entry is always of SImode size. The mode of
1668 dest depends on how dest is used: if dest is assigned to a
1669 pointer (e.g. in the memory), it has SImode; it may have
1670 DImode if dest is dereferenced to access the memeory.
1671 This is why we have to handle three different ldr_got_small
1672 patterns here (two patterns for ILP32). */
1674 rtx insn;
1675 rtx mem;
1684 {
1687 else
1691 }
1692 else
1693 {
1698 }
1705 }
1708 {
1716 else
1724 }
1727 {
1730 rtx tp;
1734 /* In ILP32, the got entry is always of SImode size. Unlike
1735 small GOT, the dest is fixed at reg 0. */
1738 else
1749 }
1752 {
1753 /* In ILP32, the mode of dest can be either SImode or DImode,
1754 while the got entry is always of SImode size. The mode of
1755 dest depends on how dest is used: if dest is assigned to a
1756 pointer (e.g. in the memory), it has SImode; it may have
1757 DImode if dest is dereferenced to access the memeory.
1758 This is why we have to handle three different tlsie_small
1759 patterns here (two patterns for ILP32). */
1765 {
1768 else
1769 {
1772 }
1773 }
1774 else
1775 {
1778 }
1784 }
1790 {
1798 {
1821 }
1826 }
1833 {
1838 {
1841 else
1842 {
1845 }
1846 }
1847 else
1848 {
1851 }
1856 }
1860 }
1861 }
1863 /* Emit a move from SRC to DEST. Assume that the move expanders can
1864 handle all moves if !can_create_pseudo_p (). The distinction is
1865 important because, unlike emit_move_insn, the move expanders know
1866 how to force Pmode objects into the constant pool even when the
1867 constant pool address is not itself legitimate. */
1868 static rtx
1870 {
1874 }
1876 /* Split a 128-bit move operation into two 64-bit move operations,
1877 taking care to handle partial overlap of register to register
1878 copies. Special cases are needed when moving between GP regs and
1879 FP regs. SRC can be a register, constant or memory; DST a register
1880 or memory. If either operand is memory it must not have any side
1881 effects. */
1882 void
1884 {
1895 {
1899 /* Handle FP <-> GP regs. */
1901 {
1906 {
1909 }
1910 else
1911 {
1914 }
1916 }
1918 {
1923 {
1926 }
1927 else
1928 {
1931 }
1933 }
1934 }
1941 /* At most one pairing may overlap. */
1943 {
1946 }
1947 else
1948 {
1951 }
1952 }
1954 bool
1956 {
1959 }
1961 /* Split a complex SIMD combine. */
1963 void
1965 {
1977 {
2001 }
2005 }
2007 /* Split a complex SIMD move. */
2009 void
2011 {
2018 {
2024 {
2048 }
2052 }
2053 }
2055 bool
2058 {
2062 }
2065 static rtx
2067 {
2070 else
2071 {
2075 }
2076 }
2078 /* Return true if we can move VALUE into a register using a single
2079 CNT[BHWD] instruction. */
2081 static bool
2083 {
2085 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
2090 }
2092 /* Likewise for rtx X. */
2094 bool
2096 {
2097 poly_int64 value;
2099 }
2101 /* Return the asm string for an instruction with a CNT-like vector size
2102 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2103 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2104 first part of the operands template (the part that comes before the
2105 vector size itself). FACTOR is the number of quadwords.
2106 NELTS_PER_VQ, if nonzero, is the number of elements in each quadword.
2107 If it is zero, we can use any element size. */
2113 {
2117 /* There is some overlap in the ranges of the four CNT instructions.
2118 Here we always use the smallest possible element size, so that the
2119 multiplier is 1 whereever possible. */
2130 else
2135 }
2137 /* Return the asm string for an instruction with a CNT-like vector size
2138 operand (a vector pattern followed by a multiplier in the range [1, 16]).
2139 PREFIX is the mnemonic without the size suffix and OPERANDS is the
2140 first part of the operands template (the part that comes before the
2141 vector size itself). X is the value of the vector size operand,
2142 as a polynomial integer rtx. */
2146 rtx x)
2147 {
2152 }
2154 /* Return true if we can add VALUE to a register using a single ADDVL
2155 or ADDPL instruction. */
2157 static bool
2159 {
2163 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
2164 and a value of 16 is one vector width. */
2167 }
2169 /* Likewise for rtx X. */
2171 bool
2173 {
2174 poly_int64 value;
2177 }
2179 /* Return the asm string for adding ADDVL or ADDPL immediate X to operand 1
2180 and storing the result in operand 0. */
2184 {
2189 /* Use INC or DEC if possible. */
2191 {
2198 }
2203 else
2206 }
2208 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2209 instruction. If it is, store the number of elements in each vector
2210 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
2211 factor in *FACTOR_OUT (if nonnull). */
2213 bool
2216 {
2217 rtx elt;
2218 poly_int64 value;
2226 /* There's no vector INCB. */
2233 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
2243 }
2245 /* Return true if X is a valid immediate for an SVE vector INC or DEC
2246 instruction. */
2248 bool
2250 {
2252 }
2254 /* Return the asm template for an SVE vector INC or DEC instruction.
2255 OPERANDS gives the operands before the vector count and X is the
2256 value of the vector count operand itself. */
2260 {
2267 nelts_per_vq);
2268 else
2270 nelts_per_vq);
2271 }
2273 static int
2275 scalar_int_mode mode)
2276 {
2285 {
2289 }
2291 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
2292 (with XXXX non-zero). In that case check to see if the move can be done in
2293 a smaller mode. */
2298 {
2302 /* Check if we have to emit a second instruction by checking to see
2303 if any of the upper 32 bits of the original DI mode value is set. */
2314 }
2317 {
2319 {
2324 else
2327 }
2329 }
2331 /* Remaining cases are all for DImode. */
2340 {
2341 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
2342 For a 64-bit bitmask try whether changing 16 bits to all ones or
2343 zeroes creates a valid bitmask. To check any repeated bitmask,
2344 try using 16 bits from the other 32-bit half of val. */
2347 {
2358 }
2360 {
2362 {
2366 }
2368 }
2369 }
2371 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
2372 are emitted by the initial mov. If one_match > zero_match, skip set bits,
2373 otherwise skip zero bits. */
2385 {
2391 num_insns ++;
2392 }
2395 }
2397 /* Return whether imm is a 128-bit immediate which is simple enough to
2398 expand inline. */
2399 bool
2401 {
2412 }
2415 /* Return the number of temporary registers that aarch64_add_offset_1
2416 would need to add OFFSET to a register. */
2418 static unsigned int
2420 {
2422 }
2424 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
2425 a non-polynomial OFFSET. MODE is the mode of the addition.
2426 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2427 be set and CFA adjustments added to the generated instructions.
2429 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2430 temporary if register allocation is already complete. This temporary
2431 register may overlap DEST but must not overlap SRC. If TEMP1 is known
2432 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
2433 the immediate again.
2435 Since this function may be used to adjust the stack pointer, we must
2436 ensure that it cannot cause transient stack deallocation (for example
2437 by first incrementing SP and then decrementing when adjusting by a
2438 large immediate). */
2440 static void
2444 {
2452 {
2454 {
2457 }
2459 }
2461 /* Single instruction adjustment. */
2463 {
2467 }
2469 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
2470 and either:
2472 a) the offset cannot be loaded by a 16-bit move or
2473 b) there is no spare register into which we can move it. */
2477 {
2486 }
2488 /* Emit a move immediate if required and an addition/subtraction. */
2490 {
2493 }
2498 {
2502 }
2503 }
2505 /* Return the number of temporary registers that aarch64_add_offset
2506 would need to move OFFSET into a register or add OFFSET to a register;
2507 ADD_P is true if we want the latter rather than the former. */
2509 static unsigned int
2511 {
2512 /* This follows the same structure as aarch64_add_offset. */
2521 /* Need one register for the ADDVL/ADDPL result. */
2524 {
2527 /* Need one register for the CNT result and one for the multiplication
2528 factor. If necessary, the second temporary can be reused for the
2529 constant part of the offset. */
2531 /* Need one register for the CNT result (which might then
2532 be shifted). */
2534 }
2536 }
2538 /* If X can be represented as a poly_int64, return the number
2539 of temporaries that are required to add it to a register.
2540 Return -1 otherwise. */
2542 int
2544 {
2545 poly_int64 offset;
2549 }
2551 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
2552 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
2553 be set and CFA adjustments added to the generated instructions.
2555 TEMP1, if nonnull, is a register of mode MODE that can be used as a
2556 temporary if register allocation is already complete. This temporary
2557 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
2558 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
2559 false to avoid emitting the immediate again.
2561 TEMP2, if nonnull, is a second temporary register that doesn't
2562 overlap either DEST or REG.
2564 Since this function may be used to adjust the stack pointer, we must
2565 ensure that it cannot cause transient stack deallocation (for example
2566 by first incrementing SP and then decrementing when adjusting by a
2567 large immediate). */
2569 static void
2573 {
2577 || !frame_related_p
2581 /* Try using ADDVL or ADDPL to add the whole value. */
2583 {
2588 }
2590 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
2591 SVE vector register, over and above the minimum size of 128 bits.
2592 This is equivalent to half the value returned by CNTD with a
2593 vector shape of ALL. */
2597 /* Try using ADDVL or ADDPL to add the VG-based part. */
2601 {
2604 {
2608 }
2609 else
2610 {
2615 }
2616 }
2617 /* Otherwise use a CNT-based sequence. */
2619 {
2620 /* Use a subtraction if we have a negative factor. */
2623 {
2626 }
2628 /* Calculate CNTD * FACTOR / 2. First try to fold the division
2629 into the multiplication. */
2630 rtx val;
2633 /* Use a right shift by 1. */
2635 else
2639 {
2641 {
2642 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
2643 the value with the minimum multiplier and shift it into
2644 position. */
2648 }
2650 }
2651 else
2652 {
2653 /* Use CNTD, then multiply it by FACTOR. */
2657 /* Go back to using a negative multiplication factor if we have
2658 no register from which to subtract. */
2660 {
2663 }
2667 }
2670 {
2671 /* Multiply by 1 << SHIFT. */
2674 }
2676 {
2677 /* Divide by 2. */
2680 }
2682 /* Calculate SRC +/- CNTD * FACTOR / 2. */
2684 {
2687 }
2689 {
2692 }
2695 {
2698 {
2702 poly_offset)));
2703 }
2707 }
2708 else
2709 {
2713 }
2716 }
2720 }
2722 /* Like aarch64_add_offset, but the offset is given as an rtx rather
2723 than a poly_int64. */
2725 void
2728 {
2731 }
2733 /* Add DELTA to the stack pointer, marking the instructions frame-related.
2734 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
2735 if TEMP1 already contains abs (DELTA). */
2739 {
2742 }
2744 /* Subtract DELTA from the stack pointer, marking the instructions
2745 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
2746 if nonnull. */
2750 {
2753 }
2755 /* Set DEST to (vec_series BASE STEP). */
2757 static void
2759 {
2763 /* Each operand can be a register or an immediate in the range [-16, 15]. */
2770 }
2772 /* Try to duplicate SRC into SVE register DEST, given that SRC is an
2773 integer of mode INT_MODE. Return true on success. */
2775 static bool
2777 rtx src)
2778 {
2779 /* If the constant is smaller than 128 bits, we can do the move
2780 using a vector of SRC_MODEs. */
2782 {
2789 }
2791 /* Use LD1RQ[BHWD] to load the 128 bits from memory. */
2796 /* Make sure that the address is legitimate. */
2798 {
2801 }
2810 }
2812 /* Expand a move of general CONST_VECTOR SRC into DEST, given that it
2813 isn't a simple duplicate or series. */
2815 static void
2817 {
2824 {
2825 /* The constant is a repeating seqeuence of at least two elements,
2826 where the repeating elements occupy no more than 128 bits.
2827 Get an integer representation of the replicated value. */
2828 scalar_int_mode int_mode;
2830 /* For now, always use LD1RQ to load the value on big-endian
2831 targets, since the handling of smaller integers includes a
2832 subreg that is semantically an element reverse. */
2834 else
2835 {
2839 }
2844 }
2846 /* Expand each pattern individually. */
2847 rtx_vector_builder builder;
2850 {
2855 }
2857 /* Use permutes to interleave the separate vectors. */
2859 {
2862 {
2867 }
2868 }
2870 }
2872 /* Set DEST to immediate IMM. For SVE vector modes, GEN_VEC_DUPLICATE
2873 is a pattern that can be used to set DEST to a replicated scalar
2874 element. */
2876 void
2879 {
2882 /* Check on what type of symbol it is. */
2883 scalar_int_mode int_mode;
2889 {
2890 rtx mem;
2891 poly_int64 offset;
2892 HOST_WIDE_INT const_offset;
2895 /* If we have (const (plus symbol offset)), separate out the offset
2896 before we start classifying the symbol. */
2899 /* We must always add an offset involving VL separately, rather than
2900 folding it into the relocation. */
2902 {
2905 else
2906 {
2907 /* Do arithmetic on 32-bit values if the result is smaller
2908 than that. */
2910 {
2911 /* It is invalid to do symbol calculations in modes
2912 narrower than SImode. */
2916 }
2918 {
2922 }
2923 else
2926 }
2928 }
2932 {
2936 {
2942 }
2947 /* If we aren't generating PC relative literals, then
2948 we need to expand the literal pool access carefully.
2949 This is something that needs to be done in a number
2950 of places, so could well live as a separate function. */
2952 {
2959 }
2976 {
2982 }
2983 /* FALLTHRU */
2996 }
2997 }
3000 {
3008 {
3009 /* If the constant is out of range of an SVE vector move,
3010 load it from memory if we can, otherwise move it into
3011 a register and use a DUP. */
3017 {
3020 }
3022 }
3026 else
3027 {
3031 }
3034 }
3038 }
3040 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
3041 that is known to contain PTRUE. */
3043 void
3045 {
3048 UNSPEC_MERGE_PTRUE)));
3049 }
3051 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
3052 operand is in memory. In this case we need to use the predicated LD1
3053 and ST1 instead of LDR and STR, both for correctness on big-endian
3054 targets and because LD1 and ST1 support a wider range of addressing modes.
3055 PRED_MODE is the mode of the predicate.
3057 See the comment at the head of aarch64-sve.md for details about the
3058 big-endian handling. */
3060 void
3062 {
3067 {
3071 else
3074 }
3076 }
3078 /* Called only on big-endian targets. See whether an SVE vector move
3079 from SRC to DEST is effectively a REV[BHW] instruction, because at
3080 least one operand is a subreg of an SVE vector that has wider or
3081 narrower elements. Return true and emit the instruction if so.
3083 For example:
3085 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
3087 represents a VIEW_CONVERT between the following vectors, viewed
3088 in memory order:
3090 R2: { [0].high, [0].low, [1].high, [1].low, ... }
3091 R1: { [0], [1], [2], [3], ... }
3093 The high part of lane X in R2 should therefore correspond to lane X*2
3094 of R1, but the register representations are:
3096 msb lsb
3097 R2: ...... [1].high [1].low [0].high [0].low
3098 R1: ...... [3] [2] [1] [0]
3100 where the low part of lane X in R2 corresponds to lane X*2 in R1.
3101 We therefore need a reverse operation to swap the high and low values
3102 around.
3104 This is purely an optimization. Without it we would spill the
3105 subreg operand to the stack in one mode and reload it in the
3106 other mode, which has the same effect as the REV. */
3108 bool
3110 {
3117 /* The optimization handles two single SVE REGs with different element
3118 sizes. */
3127 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
3130 UNSPEC_REV_SUBREG);
3133 }
3135 /* Return a copy of X with mode MODE, without changing its other
3136 attributes. Unlike gen_lowpart, this doesn't care whether the
3137 mode change is valid. */
3139 static rtx
3141 {
3148 }
3150 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
3151 operands. */
3153 void
3155 {
3156 /* Decide which REV operation we need. The mode with narrower elements
3157 determines the mode of the operands and the mode with the wider
3158 elements determines the reverse width. */
3173 else
3177 /* Emit:
3179 (set DEST (unspec [PTRUE (unspec [SRC] UNSPEC_REV<nn>)]
3180 UNSPEC_MERGE_PTRUE))
3182 with the appropriate modes. */
3188 UNSPEC_MERGE_PTRUE);
3190 }
3192 static bool
3194 tree exp ATTRIBUTE_UNUSED)
3195 {
3196 /* Currently, always true. */
3198 }
3200 /* Implement TARGET_PASS_BY_REFERENCE. */
3202 static bool
3204 machine_mode mode,
3205 const_tree type,
3207 {
3208 HOST_WIDE_INT size;
3209 machine_mode dummymode;
3212 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
3215 else
3216 /* No frontends can create types with variable-sized modes, so we
3217 shouldn't be asked to pass or return them. */
3220 /* Aggregates are passed by reference based on their size. */
3222 {
3224 }
3226 /* Variable sized arguments are always returned by reference. */
3230 /* Can this be a candidate to be passed in fp/simd register(s)? */
3233 NULL))
3236 /* Arguments which are variable sized or larger than 2 registers are
3237 passed by reference unless they are a homogenous floating point
3238 aggregate. */
3240 }
3242 /* Return TRUE if VALTYPE is padded to its least significant bits. */
3243 static bool
3245 {
3246 machine_mode dummy_mode;
3249 /* Never happens in little-endian mode. */
3253 /* Only composite types smaller than or equal to 16 bytes can
3254 be potentially returned in registers. */
3260 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
3261 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
3262 is always passed/returned in the least significant bits of fp/simd
3263 register(s). */
3269 }
3271 /* Implement TARGET_FUNCTION_VALUE.
3272 Define how to find the value returned by a function. */
3274 static rtx
3277 {
3278 machine_mode mode;
3281 machine_mode ag_mode;
3288 {
3292 {
3295 }
3296 }
3300 {
3302 {
3305 }
3306 else
3307 {
3309 rtx par;
3313 {
3318 }
3320 }
3321 }
3322 else
3324 }
3326 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
3327 Return true if REGNO is the number of a hard register in which the values
3328 of called function may come back. */
3330 static bool
3332 {
3333 /* Maximum of 16 bytes can be returned in the general registers. Examples
3334 of 16-byte return values are: 128-bit integers and 16-byte small
3335 structures (excluding homogeneous floating-point aggregates). */
3339 /* Up to four fp/simd registers can return a function value, e.g. a
3340 homogeneous floating-point aggregate having four members. */
3345 }
3347 /* Implement TARGET_RETURN_IN_MEMORY.
3349 If the type T of the result of a function is such that
3350 void func (T arg)
3351 would require that arg be passed as a value in a register (or set of
3352 registers) according to the parameter passing rules, then the result
3353 is returned in the same registers as would be used for such an
3354 argument. */
3356 static bool
3358 {
3359 HOST_WIDE_INT size;
3360 machine_mode ag_mode;
3366 /* Simple scalar types always returned in registers. */
3370 type,
3373 NULL))
3376 /* Types larger than 2 registers returned in memory. */
3379 }
3381 static bool
3384 {
3387 type,
3389 nregs,
3390 NULL);
3391 }
3393 /* Given MODE and TYPE of a function argument, return the alignment in
3394 bits. The idea is to suppress any stronger alignment requested by
3395 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
3396 This is a helper function for local use only. */
3398 static unsigned int
3400 {
3421 }
3423 /* Layout a function argument according to the AAPCS64 rules. The rule
3424 numbers refer to the rule numbers in the AAPCS64. */
3426 static void
3428 const_tree type,
3430 {
3434 HOST_WIDE_INT size;
3436 /* We need to do this once per argument. */
3442 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
3445 else
3446 /* No frontends can create types with variable-sized modes, so we
3447 shouldn't be asked to pass or return them. */
3453 mode,
3454 type,
3457 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
3458 The following code thus handles passing by SIMD/FP registers first. */
3462 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
3463 and homogenous short-vector aggregates (HVA). */
3465 {
3470 {
3473 {
3476 }
3477 else
3478 {
3479 rtx par;
3483 {
3486 rtx offset = gen_int_mode
3490 }
3492 }
3494 }
3495 else
3496 {
3497 /* C.3 NSRN is set to 8. */
3500 }
3501 }
3506 /* C6 - C9. though the sign and zero extension semantics are
3507 handled elsewhere. This is the case where the argument fits
3508 entirely general registers. */
3510 {
3514 /* C.8 if the argument has an alignment of 16 then the NGRN is
3515 rounded up to the next even number. */
3518 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
3519 comparison is there because for > 16 * BITS_PER_UNIT
3520 alignment nregs should be > 2 and therefore it should be
3521 passed by reference rather than value. */
3523 {
3526 }
3528 /* NREGS can be 0 when e.g. an empty structure is to be passed.
3529 A reg is still generated for it, but the caller should be smart
3530 enough not to use it. */
3533 else
3534 {
3535 rtx par;
3540 {
3545 }
3547 }
3551 }
3553 /* C.11 */
3556 /* The argument is passed on stack; record the needed number of words for
3557 this argument and align the total size if necessary. */
3558 on_stack:
3565 }
3567 /* Implement TARGET_FUNCTION_ARG. */
3569 static rtx
3572 {
3581 }
3583 void
3585 const_tree fntype ATTRIBUTE_UNUSED,
3586 rtx libname ATTRIBUTE_UNUSED,
3587 const_tree fndecl ATTRIBUTE_UNUSED,
3589 {
3603 {
3610 }
3612 }
3614 static void
3616 machine_mode mode,
3617 const_tree type,
3619 {
3622 {
3632 }
3633 }
3635 bool
3637 {
3640 }
3642 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3643 PARM_BOUNDARY bits of alignment, but will be given anything up
3644 to STACK_BOUNDARY bits if the type requires it. This makes sure
3645 that both before and after the layout of each argument, the Next
3646 Stacked Argument Address (NSAA) will have a minimum alignment of
3647 8 bytes. */
3649 static unsigned int
3651 {
3654 }
3656 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
3658 static fixed_size_mode
3660 {
3662 /* Don't use the SVE part of the register for __builtin_apply and
3663 __builtin_return. The SVE registers aren't used by the normal PCS,
3664 so using them there would be a waste of time. The PCS extensions
3665 for SVE types are fundamentally incompatible with the
3666 __builtin_return/__builtin_apply interface. */
3669 }
3671 /* Implement TARGET_FUNCTION_ARG_PADDING.
3673 Small aggregate types are placed in the lowest memory address.
3675 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
3677 static pad_direction
3679 {
3680 /* On little-endian targets, the least significant byte of every stack
3681 argument is passed at the lowest byte address of the stack slot. */
3685 /* Otherwise, integral, floating-point and pointer types are padded downward:
3686 the least significant byte of a stack argument is passed at the highest
3687 byte address of the stack slot. */
3694 /* Everything else padded upward, i.e. data in first byte of stack slot. */
3696 }
3698 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
3700 It specifies padding for the last (may also be the only)
3701 element of a block move between registers and memory. If
3702 assuming the block is in the memory, padding upward means that
3703 the last element is padded after its highest significant byte,
3704 while in downward padding, the last element is padded at the
3705 its least significant byte side.
3707 Small aggregates and small complex types are always padded
3708 upwards.
3710 We don't need to worry about homogeneous floating-point or
3711 short-vector aggregates; their move is not affected by the
3712 padding direction determined here. Regardless of endianness,
3713 each element of such an aggregate is put in the least
3714 significant bits of a fp/simd register.
3716 Return !BYTES_BIG_ENDIAN if the least significant byte of the
3717 register has useful data, and return the opposite if the most
3718 significant byte does. */
3720 bool
3723 {
3725 /* Small composite types are always padded upward. */
3727 {
3728 HOST_WIDE_INT size;
3731 else
3732 /* No frontends can create types with variable-sized modes, so we
3733 shouldn't be asked to pass or return them. */
3737 }
3739 /* Otherwise, use the default padding. */
3741 }
3743 static scalar_int_mode
3745 {
3747 }
3749 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
3751 /* We use the 12-bit shifted immediate arithmetic instructions so values
3752 must be multiple of (1 << 12), i.e. 4096. */
3753 #define ARITH_FACTOR 4096
3755 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
3756 #error Cannot use simple address calculation for stack probing
3757 #endif
3759 /* The pair of scratch registers used for stack probing. */
3760 #define PROBE_STACK_FIRST_REG 9
3761 #define PROBE_STACK_SECOND_REG 10
3763 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
3764 inclusive. These are offsets from the current stack pointer. */
3766 static void
3768 {
3769 HOST_WIDE_INT size;
3771 {
3774 }
3778 /* See the same assertion on PROBE_INTERVAL above. */
3781 /* See if we have a constant small number of probes to generate. If so,
3782 that's the easy case. */
3784 {
3791 }
3793 /* The run-time loop is made up of 8 insns in the generic case while the
3794 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
3796 {
3801 stack_pointer_rtx,
3805 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
3806 it exceeds SIZE. If only two probes are needed, this will not
3807 generate any code. Then probe at FIRST + SIZE. */
3809 {
3813 }
3817 {
3822 }
3823 else
3825 }
3827 /* Otherwise, do the same as above, but in a loop. Note that we must be
3828 extra careful with variables wrapping around because we might be at
3829 the very top (or the very bottom) of the address space and we have
3830 to be able to handle this case properly; in particular, we use an
3831 equality test for the loop condition. */
3832 else
3833 {
3836 /* Step 1: round SIZE to the previous multiple of the interval. */
3841 /* Step 2: compute initial and final value of the loop counter. */
3843 /* TEST_ADDR = SP + FIRST. */
3847 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
3850 {
3854 }
3855 else
3859 /* Step 3: the loop
3861 do
3862 {
3863 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
3864 probe at TEST_ADDR
3865 }
3866 while (TEST_ADDR != LAST_ADDR)
3868 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
3869 until it is equal to ROUNDED_SIZE. */
3874 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
3875 that SIZE is equal to ROUNDED_SIZE. */
3878 {
3882 {
3887 }
3888 else
3890 }
3891 }
3893 /* Make sure nothing is scheduled before we are done. */
3895 }
3897 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
3898 absolute addresses. */
3902 {
3909 /* Loop. */
3912 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
3917 /* Probe at TEST_ADDR. */
3920 /* Test if TEST_ADDR == LAST_ADDR. */
3924 /* Branch. */
3930 }
3932 /* Mark the registers that need to be saved by the callee and calculate
3933 the size of the callee-saved registers area and frame record (both FP
3934 and LR may be omitted). */
3935 static void
3937 {
3944 /* Force a frame chain for EH returns so the return address is at FP+8. */
3948 /* Emit a frame chain if the frame pointer is enabled.
3949 If -momit-leaf-frame-pointer is used, do not use a frame chain
3950 in leaf functions which do not use LR. */
3956 #define SLOT_NOT_REQUIRED (-2)
3957 #define SLOT_REQUIRED (-1)
3962 /* First mark all the registers that really need to be saved... */
3969 /* ... that includes the eh data registers (if needed)... */
3975 /* ... and any callee saved register that dataflow says is live. */
3985 {
3988 }
3991 {
3992 /* FP and LR are placed in the linkage record. */
3998 }
4000 /* Now assign stack slots for them. */
4003 {
4010 }
4018 {
4019 /* If there is an alignment gap between integer and fp callee-saves,
4020 allocate the last fp register to it if possible. */
4022 {
4025 }
4034 }
4040 HOST_WIDE_INT varargs_and_saved_regs_size
4048 /* Both these values are already aligned. */
4072 {
4073 /* Simple, small frame with no outgoing arguments:
4074 stp reg1, reg2, [sp, -frame_size]!
4075 stp reg3, reg4, [sp, 16] */
4077 }
4082 max_push_offset)))
4083 {
4084 /* Frame with small outgoing arguments:
4085 sub sp, sp, frame_size
4086 stp reg1, reg2, [sp, outgoing_args_size]
4087 stp reg3, reg4, [sp, outgoing_args_size + 16] */
4091 }
4094 {
4095 /* Frame with large outgoing arguments but a small local area:
4096 stp reg1, reg2, [sp, -hard_fp_offset]!
4097 stp reg3, reg4, [sp, 16]
4098 sub sp, sp, outgoing_args_size */
4102 }
4103 else
4104 {
4105 /* Frame with large local area and outgoing arguments using frame pointer:
4106 sub sp, sp, hard_fp_offset
4107 stp x29, x30, [sp, 0]
4108 add x29, sp, 0
4109 stp reg3, reg4, [sp, 16]
4110 sub sp, sp, outgoing_args_size */
4114 }
4117 }
4119 /* Return true if the register REGNO is saved on entry to
4120 the current function. */
4122 static bool
4124 {
4126 }
4128 /* Return the next register up from REGNO up to LIMIT for the callee
4129 to save. */
4131 static unsigned
4133 {
4135 regno ++;
4137 }
4139 /* Push the register number REGNO of mode MODE to the stack with write-back
4140 adjusting the stack by ADJUSTMENT. */
4142 static void
4144 HOST_WIDE_INT adjustment)
4145 {
4156 }
4158 /* Generate and return an instruction to store the pair of registers
4159 REG and REG2 of mode MODE to location BASE with write-back adjusting
4160 the stack location BASE by ADJUSTMENT. */
4162 static rtx
4164 HOST_WIDE_INT adjustment)
4165 {
4167 {
4178 }
4179 }
4181 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
4182 stack pointer by ADJUSTMENT. */
4184 static void
4186 {
4201 }
4203 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
4204 adjusting it by ADJUSTMENT afterwards. */
4206 static rtx
4208 HOST_WIDE_INT adjustment)
4209 {
4211 {
4220 }
4221 }
4223 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
4224 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
4225 into CFI_OPS. */
4227 static void
4230 {
4237 {
4241 }
4242 else
4243 {
4248 }
4249 }
4251 /* Generate and return a store pair instruction of mode MODE to store
4252 register REG1 to MEM1 and register REG2 to MEM2. */
4254 static rtx
4256 rtx reg2)
4257 {
4259 {
4268 }
4269 }
4271 /* Generate and regurn a load pair isntruction of mode MODE to load register
4272 REG1 from MEM1 and register REG2 from MEM2. */
4274 static rtx
4276 rtx mem2)
4277 {
4279 {
4288 }
4289 }
4291 /* Return TRUE if return address signing should be enabled for the current
4292 function, otherwise return FALSE. */
4294 bool
4296 {
4297 /* This function should only be called after frame laid out. */
4300 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
4301 if it's LR is pushed onto stack. */
4305 }
4307 /* Emit code to save the callee-saved registers from register number START
4308 to LIMIT to the stack at the location starting at offset START_OFFSET,
4309 skipping any write-back candidates if SKIP_WB is true. */
4311 static void
4314 {
4322 {
4324 poly_int64 offset;
4337 offset));
4346 {
4348 rtx mem2;
4352 offset));
4354 reg2));
4356 /* The first part of a frame-related parallel insn is
4357 always assumed to be relevant to the frame
4358 calculations; subsequent parts, are only
4359 frame-related if explicitly marked. */
4362 }
4363 else
4367 }
4368 }
4370 /* Emit code to restore the callee registers of mode MODE from register
4371 number START up to and including LIMIT. Restore from the stack offset
4372 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
4373 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
4375 static void
4379 {
4383 poly_int64 offset;
4388 {
4409 {
4411 rtx mem2;
4419 }
4420 else
4423 }
4424 }
4426 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
4427 of MODE. */
4431 {
4432 HOST_WIDE_INT multiple;
4435 }
4437 /* Return true if OFFSET is a unsigned 6-bit value multiplied by the size
4438 of MODE. */
4442 {
4443 HOST_WIDE_INT multiple;
4446 }
4448 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
4449 of MODE. */
4451 bool
4453 {
4454 HOST_WIDE_INT multiple;
4457 }
4459 /* Return true if OFFSET is a signed 9-bit value. */
4463 poly_int64 offset)
4464 {
4465 HOST_WIDE_INT const_offset;
4468 }
4470 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
4471 of MODE. */
4475 {
4476 HOST_WIDE_INT multiple;
4479 }
4481 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
4482 of MODE. */
4486 {
4487 HOST_WIDE_INT multiple;
4490 }
4492 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
4494 static sbitmap
4496 {
4502 /* The registers we need saved to the frame. */
4505 {
4510 /* Check that we can access the stack slot of the register with one
4511 direct load with no adjustments needed. */
4514 }
4516 /* Don't mess with the hard frame pointer. */
4522 /* If aarch64_layout_frame has chosen registers to store/restore with
4523 writeback don't interfere with them to avoid having to output explicit
4524 stack adjustment instructions. */
4534 }
4536 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
4538 static sbitmap
4540 {
4548 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
4554 {
4558 /* If there is a callee-save at an adjacent offset, add it too
4559 to increase the use of LDP/STP. */
4564 {
4568 }
4569 }
4572 }
4574 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
4575 Nothing to do for aarch64. */
4577 static void
4579 {
4580 }
4582 /* Return the next set bit in BMP from START onwards. Return the total number
4583 of bits in BMP if no set bit is found at or after START. */
4585 static unsigned int
4587 {
4598 }
4600 /* Do the work for aarch64_emit_prologue_components and
4601 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
4602 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
4603 for these components or the epilogue sequence. That is, it determines
4604 whether we should emit stores or loads and what kind of CFA notes to attach
4605 to the insns. Otherwise the logic for the two sequences is very
4606 similar. */
4608 static void
4610 {
4612 ? HARD_FRAME_POINTER_REGNUM
4620 {
4621 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
4622 so DFmode for the vector registers is enough. */
4634 /* No more registers to handle after REGNO.
4635 Emit a single save/restore and exit. */
4637 {
4642 else
4645 }
4648 /* The next register is not of the same class or its offset is not
4649 mergeable with the current one into a pair. */
4654 {
4659 else
4664 }
4666 /* REGNO2 can be saved/restored in a pair with REGNO. */
4678 else
4683 {
4686 }
4687 else
4688 {
4691 }
4694 }
4695 }
4697 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
4699 static void
4701 {
4703 }
4705 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
4707 static void
4709 {
4711 }
4713 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
4715 static void
4717 {
4721 }
4723 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
4724 is saved at BASE + OFFSET. */
4726 static void
4729 {
4733 }
4735 /* AArch64 stack frames generated by this compiler look like:
4737 +-------------------------------+
4738 | |
4739 | incoming stack arguments |
4740 | |
4741 +-------------------------------+
4742 | | <-- incoming stack pointer (aligned)
4743 | callee-allocated save area |
4744 | for register varargs |
4745 | |
4746 +-------------------------------+
4747 | local variables | <-- frame_pointer_rtx
4748 | |
4749 +-------------------------------+
4750 | padding0 | \
4751 +-------------------------------+ |
4752 | callee-saved registers | | frame.saved_regs_size
4753 +-------------------------------+ |
4754 | LR' | |
4755 +-------------------------------+ |
4756 | FP' | / <- hard_frame_pointer_rtx (aligned)
4757 +-------------------------------+
4758 | dynamic allocation |
4759 +-------------------------------+
4760 | padding |
4761 +-------------------------------+
4762 | outgoing stack arguments | <-- arg_pointer
4763 | |
4764 +-------------------------------+
4765 | | <-- stack_pointer_rtx (aligned)
4767 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
4768 but leave frame_pointer_rtx and hard_frame_pointer_rtx
4769 unchanged. */
4771 /* Generate the prologue instructions for entry into a function.
4772 Establish the stack frame by decreasing the stack pointer with a
4773 properly calculated size and, if necessary, create a frame record
4774 filled with the values of LR and previous frame pointer. The
4775 current FP is also set up if it is in use. */
4777 void
4779 {
4792 /* Sign return address for functions. */
4794 {
4798 }
4804 {
4806 {
4810 (frame_size
4812 }
4815 }
4826 {
4829 {
4834 }
4839 {
4840 /* Variable-sized frames need to describe the save slot
4841 address using DW_CFA_expression rather than DW_CFA_offset.
4842 This means that, without taking further action, the
4843 locations of the registers that we've already saved would
4844 remain based on the stack pointer even after we redefine
4845 the CFA based on the frame pointer. We therefore need new
4846 DW_CFA_expressions to re-express the save slots with addresses
4847 based on the frame pointer. */
4851 /* Add an explicit CFA definition if this was previously
4852 implicit. */
4854 {
4856 callee_offset);
4859 }
4861 /* Change the save slot expressions for the registers that
4862 we've already saved. */
4867 reg_offset);
4868 }
4870 }
4877 }
4879 /* Return TRUE if we can use a simple_return insn.
4881 This function checks whether the callee saved stack is empty, which
4882 means no restore actions are need. The pro_and_epilogue will use
4883 this to check whether shrink-wrapping opt is feasible. */
4885 bool
4887 {
4897 }
4899 /* Generate the epilogue instructions for returning from a function.
4900 This is almost exactly the reverse of the prolog sequence, except
4901 that we need to insert barriers to avoid scheduling loads that read
4902 from a deallocated stack, and we optimize the unwind records by
4903 emitting them all together if possible. */
4904 void
4906 {
4917 /* A stack clash protection prologue may not have left IP0_REGNUM or
4918 IP1_REGNUM in a usable state. The same is true for allocations
4919 with an SVE component, since we then need both temporary registers
4920 for each allocation. */
4925 /* We need to add memory barrier to prevent read from deallocated stack. */
4926 bool need_barrier_p
4930 /* Emit a barrier to prevent loads from a deallocated stack. */
4934 {
4937 }
4939 /* Restore the stack pointer from the frame pointer if it may not
4940 be the same as the stack pointer. */
4945 /* If writeback is used when restoring callee-saves, the CFA
4946 is restored on the instruction doing the writeback. */
4950 else
4966 {
4967 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
4973 }
4979 {
4980 /* Emit delayed restores and reset the CFA to be SP. */
4985 }
4987 /* We prefer to emit the combined return/authenticate instruction RETAA,
4988 however there are three cases in which we must instead emit an explicit
4989 authentication instruction.
4991 1) Sibcalls don't return in a normal way, so if we're about to call one
4992 we must authenticate.
4994 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
4995 generating code for !TARGET_ARMV8_3 we can't use it and must
4996 explicitly authenticate.
4998 3) On an eh_return path we make extra stack adjustments to update the
4999 canonical frame address to be the exception handler's CFA. We want
5000 to authenticate using the CFA of the function which calls eh_return.
5001 */
5004 {
5008 }
5010 /* Stack adjustment for exception handler. */
5012 {
5013 /* We need to unwind the stack by the offset computed by
5014 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
5015 to be SP; letting the CFA move during this adjustment
5016 is just as correct as retaining the CFA from the body
5017 of the function. Therefore, do nothing special. */
5019 }
5024 }
5026 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
5027 normally or return to a previous frame after unwinding.
5029 An EH return uses a single shared return sequence. The epilogue is
5030 exactly like a normal epilogue except that it has an extra input
5031 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
5032 that must be applied after the frame has been destroyed. An extra label
5033 is inserted before the epilogue which initializes this register to zero,
5034 and this is the entry point for a normal return.
5036 An actual EH return updates the return address, initializes the stack
5037 adjustment and jumps directly into the epilogue (bypassing the zeroing
5038 of the adjustment). Since the return address is typically saved on the
5039 stack when a function makes a call, the saved LR must be updated outside
5040 the epilogue.
5042 This poses problems as the store is generated well before the epilogue,
5043 so the offset of LR is not known yet. Also optimizations will remove the
5044 store as it appears dead, even after the epilogue is generated (as the
5045 base or offset for loading LR is different in many cases).
5047 To avoid these problems this implementation forces the frame pointer
5048 in eh_return functions so that the location of LR is fixed and known early.
5049 It also marks the store volatile, so no optimization is permitted to
5050 remove the store. */
5051 rtx
5053 {
5057 /* Mark the store volatile, so no optimization is permitted to remove it. */
5060 }
5062 /* Output code to add DELTA to the first argument, and then jump
5063 to FUNCTION. Used for C++ multiple inheritance. */
5064 static void
5066 HOST_WIDE_INT delta,
5067 HOST_WIDE_INT vcall_offset,
5068 tree function)
5069 {
5070 /* The this pointer is always in x0. Note that this differs from
5071 Arm where the this pointer maybe bumped to r1 if r0 is required
5072 to return a pointer to an aggregate. On AArch64 a result value
5073 pointer will be in x8. */
5087 else
5088 {
5093 {
5097 else
5100 }
5104 else
5111 else
5112 {
5114 Pmode);
5116 }
5120 else
5126 }
5128 /* Generate a tail call to the target function. */
5130 {
5133 }
5145 /* Stop pretending to be a post-reload pass. */
5147 }
5149 static bool
5151 {
5156 {
5160 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
5161 TLS offsets, not real symbol references. */
5164 }
5166 }
5169 /* Return true if val can be encoded as a 12-bit unsigned immediate with
5170 a left shift of 0 or 12 bits. */
5171 bool
5173 {
5176 );
5177 }
5180 /* Return true if val is an immediate that can be loaded into a
5181 register by a MOVZ instruction. */
5182 static bool
5184 {
5186 {
5190 }
5191 else
5192 {
5193 /* Ignore sign extension. */
5195 }
5198 }
5200 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
5201 64-bit (DImode) integer. */
5203 static unsigned HOST_WIDE_INT
5205 {
5208 {
5212 }
5214 }
5216 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
5219 {
5225 };
5228 /* Return true if val is a valid bitmask immediate. */
5230 bool
5232 {
5236 /* Check for a single sequence of one bits and return quickly if so.
5237 The special cases of all ones and all zeroes returns false. */
5244 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
5248 /* Invert if the immediate doesn't start with a zero bit - this means we
5249 only need to search for sequences of one bits. */
5253 /* Find the first set bit and set tmp to val with the first sequence of one
5254 bits removed. Return success if there is a single sequence of ones. */
5261 /* Find the next set bit and compute the difference in bit position. */
5266 /* Check the bit position difference is a power of 2, and that the first
5267 sequence of one bits fits within 'bits' bits. */
5271 /* Check the sequence of one bits is repeated 64/bits times. */
5273 }
5275 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
5276 Assumed precondition: VAL_IN Is not zero. */
5278 unsigned HOST_WIDE_INT
5280 {
5287 }
5289 /* Create constant where bits outside of lowest bit set to highest bit set
5290 are set to 1. */
5292 unsigned HOST_WIDE_INT
5294 {
5296 }
5298 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
5300 bool
5302 {
5303 scalar_int_mode int_mode;
5316 }
5318 /* Return true if val is an immediate that can be loaded into a
5319 register in a single instruction. */
5320 bool
5322 {
5323 scalar_int_mode int_mode;
5330 }
5332 static bool
5334 {
5340 /* There's no way to calculate VL-based values using relocations. */
5348 {
5352 else
5353 /* Avoid generating a 64-bit relocation in ILP32; leave
5354 to aarch64_expand_mov_immediate to handle it properly. */
5356 }
5359 }
5361 /* Implement TARGET_CASE_VALUES_THRESHOLD.
5362 The expansion for a table switch is quite expensive due to the number
5363 of instructions, the table lookup and hard to predict indirect jump.
5364 When optimizing for speed, and -O3 enabled, use the per-core tuning if
5365 set, otherwise use tables for > 16 cases as a tradeoff between size and
5366 performance. When optimizing for size, use the default setting. */
5368 static unsigned int
5370 {
5371 /* Use the specified limit for the number of cases before using jump
5372 tables at higher optimization levels. */
5376 else
5378 }
5380 /* Return true if register REGNO is a valid index register.
5381 STRICT_P is true if REG_OK_STRICT is in effect. */
5383 bool
5385 {
5387 {
5395 }
5397 }
5399 /* Return true if register REGNO is a valid base register for mode MODE.
5400 STRICT_P is true if REG_OK_STRICT is in effect. */
5402 bool
5404 {
5406 {
5414 }
5416 /* The fake registers will be eliminated to either the stack or
5417 hard frame pointer, both of which are usually valid base registers.
5418 Reload deals with the cases where the eliminated form isn't valid. */
5423 }
5425 /* Return true if X is a valid base register for mode MODE.
5426 STRICT_P is true if REG_OK_STRICT is in effect. */
5428 static bool
5430 {
5437 }
5439 /* Return true if address offset is a valid index. If it is, fill in INFO
5440 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
5442 static bool
5445 {
5447 rtx index;
5450 /* (reg:P) */
5453 {
5457 }
5458 /* (sign_extend:DI (reg:SI)) */
5463 {
5468 }
5469 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
5476 {
5481 }
5482 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
5489 {
5494 }
5495 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
5502 {
5510 }
5511 /* (and:DI (mult:DI (reg:DI) (const_int scale))
5512 (const_int 0xffffffff<<shift)) */
5519 {
5525 }
5526 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
5533 {
5541 }
5542 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
5543 (const_int 0xffffffff<<shift)) */
5550 {
5556 }
5557 /* (mult:P (reg:P) (const_int scale)) */
5562 {
5566 }
5567 /* (ashift:P (reg:P) (const_int shift)) */
5572 {
5576 }
5577 else
5586 {
5590 }
5591 else
5592 {
5597 }
5601 {
5606 }
5609 }
5611 /* Return true if MODE is one of the modes for which we
5612 support LDP/STP operations. */
5614 static bool
5616 {
5621 }
5623 /* Return true if REGNO is a virtual pointer register, or an eliminable
5624 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
5625 include stack_pointer or hard_frame_pointer. */
5626 static bool
5628 {
5633 }
5635 /* Return true if X is a valid address of type TYPE for machine mode MODE.
5636 If it is, fill in INFO appropriately. STRICT_P is true if
5637 REG_OK_STRICT is in effect. */
5639 static bool
5643 {
5646 poly_int64 offset;
5648 HOST_WIDE_INT const_size;
5650 /* On BE, we use load/store pair for all large int mode load/stores.
5651 TI/TFmode may also use a load/store pair. */
5664 /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
5665 [Rn, #offset, MUL VL]. */
5670 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
5671 REG addressing. */
5673 && !BYTES_BIG_ENDIAN
5681 {
5698 {
5705 }
5710 {
5716 /* TImode and TFmode values are allowed in both pairs of X
5717 registers and individual Q registers. The available
5718 address modes are:
5719 X,X: 7-bit signed scaled offset
5720 Q: 9-bit signed offset
5721 We conservatively require an offset representable in either mode.
5722 When performing the check for pairs of X registers i.e. LDP/STP
5723 pass down DImode since that is the natural size of the LDP/STP
5724 instruction memory accesses. */
5730 /* A 7bit offset check because OImode will emit a ldp/stp
5731 instruction (only big endian will get here).
5732 For ldp/stp instructions, the offset is scaled for the size of a
5733 single element of the pair. */
5737 /* Three 9/12 bit offsets checks because CImode will emit three
5738 ldr/str instructions (only big endian will get here). */
5745 /* Two 7bit offsets checks because XImode will emit two ldp/stp
5746 instructions (only big endian will get here). */
5752 /* Make "m" use the LD1 offset range for SVE data modes, so
5753 that pre-RTL optimizers like ivopts will work to that
5754 instead of the wider LDR/STR range. */
5761 {
5762 poly_int64 end_offset = (offset
5769 end_offset)));
5770 }
5779 else
5782 }
5785 {
5786 /* Look for base + (scaled/extended) index register. */
5789 {
5792 }
5795 {
5798 }
5799 }
5820 {
5824 /* TImode and TFmode values are allowed in both pairs of X
5825 registers and individual Q registers. The available
5826 address modes are:
5827 X,X: 7-bit signed scaled offset
5828 Q: 9-bit signed offset
5829 We conservatively require an offset representable in either mode.
5830 */
5839 else
5841 }
5847 /* load literal: pc-relative constant pool entry. Only supported
5848 for SI mode or larger. */
5854 {
5862 }
5871 {
5877 {
5878 /* The symbol and offset must be aligned to the access size. */
5884 {
5888 }
5894 else
5903 }
5904 }
5909 }
5910 }
5912 /* Return true if the address X is valid for a PRFM instruction.
5913 STRICT_P is true if we should do strict checking with
5914 aarch64_classify_address. */
5916 bool
5918 {
5921 /* PRFM accepts the same addresses as DImode... */
5926 /* ... except writeback forms. */
5928 }
5930 bool
5932 {
5933 rtx offset;
5937 }
5939 /* Classify the base of symbolic expression X. */
5941 enum aarch64_symbol_type
5943 {
5944 rtx offset;
5948 }
5951 /* Return TRUE if X is a legitimate address for accessing memory in
5952 mode MODE. */
5953 static bool
5955 {
5959 }
5961 /* Return TRUE if X is a legitimate address of type TYPE for accessing
5962 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
5963 bool
5965 aarch64_addr_query_type type)
5966 {
5970 }
5972 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
5974 static bool
5976 poly_int64 orig_offset,
5977 machine_mode mode)
5978 {
5979 HOST_WIDE_INT size;
5981 {
5984 /* A general SVE offset is A * VQ + B. Remove the A component from
5985 coefficient 0 in order to get the constant B. */
5988 /* Split an out-of-range address displacement into a base and
5989 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
5990 range otherwise to increase opportunities for sharing the base
5991 address of different sizes. Unaligned accesses use the signed
5992 9-bit range, TImode/TFmode use the intersection of signed
5993 scaled 7-bit and signed 9-bit offset. */
5998 else
6004 /* Split the offset into second_offset and the rest. */
6008 }
6009 else
6010 {
6011 /* Get the mode we should use as the basis of the range. For structure
6012 modes this is the mode of one vector. */
6014 machine_mode step_mode
6017 /* Get the "mul vl" multiplier we'd like to use. */
6021 /* LDR supports a 9-bit range, but the move patterns for
6022 structure modes require all vectors to be in range of the
6023 same base. The simplest way of accomodating that while still
6024 promoting reuse of anchor points between different modes is
6025 to use an 8-bit range unconditionally. */
6027 else
6028 /* Predicates are only handled singly, so we might as well use
6029 the full range. */
6034 /* Convert the "mul vl" multiplier into a byte offset. */
6039 /* Split the offset into second_offset and the rest. */
6043 }
6044 }
6046 /* Return the binary representation of floating point constant VALUE in INTVAL.
6047 If the value cannot be converted, return false without setting INTVAL.
6048 The conversion is done in the given MODE. */
6049 bool
6051 {
6053 /* We make a general exception for 0. */
6055 {
6058 }
6060 scalar_float_mode mode;
6064 /* Only support up to DF mode. */
6076 {
6080 }
6081 else
6086 }
6088 /* Return TRUE if rtx X is an immediate constant that can be moved using a
6089 single MOV(+MOVK) followed by an FMOV. */
6090 bool
6092 {
6097 /* Determine whether it's cheaper to write float constants as
6098 mov/movk pairs over ldr/adrp pairs. */
6104 {
6106 ? SImode
6111 }
6114 }
6116 /* Return TRUE if rtx X is immediate constant 0.0 */
6117 bool
6119 {
6126 }
6128 /* Return TRUE if rtx X is immediate constant that fits in a single
6129 MOVI immediate operation. */
6130 bool
6132 {
6136 machine_mode vmode;
6137 scalar_int_mode imode;
6142 {
6146 /* We make a general exception for 0. */
6151 }
6155 else
6158 /* use a 64 bit mode for everything except for DI/DF mode, where we use
6159 a 128 bit vector mode. */
6166 }
6169 /* Return the fixed registers used for condition codes. */
6171 static bool
6173 {
6177 }
6179 /* This function is used by the call expanders of the machine description.
6180 RESULT is the register in which the result is returned. It's NULL for
6181 "call" and "sibcall".
6182 MEM is the location of the function call.
6183 SIBCALL indicates whether this function call is normal call or sibling call.
6184 It will generate different pattern accordingly. */
6186 void
6188 {
6190 rtvec vec;
6191 machine_mode mode;
6198 /* Decide if we should generate indirect calls by loading the
6199 address of the callee into a register before performing
6200 the branch-and-link. */
6214 else
6221 }
6223 /* Emit call insn with PAT and do aarch64-specific handling. */
6225 void
6227 {
6233 }
6235 machine_mode
6237 {
6238 /* All floating point compares return CCFP if it is an equality
6239 comparison, and CCFPE otherwise. */
6241 {
6243 {
6264 }
6265 }
6267 /* Equality comparisons of short modes against zero can be performed
6268 using the TST instruction with the appropriate bitmask. */
6274 /* Similarly, comparisons of zero_extends from shorter modes can
6275 be performed using an ANDS with an immediate mask. */
6291 /* A compare with a shifted operand. Because of canonicalization,
6292 the comparison will have to be swapped when we emit the assembly
6293 code. */
6301 /* Similarly for a negated operand, but we can only do this for
6302 equalities. */
6309 /* A test for unsigned overflow. */
6316 /* For everything else, return CCmode. */
6318 }
6320 static int
6323 int
6325 {
6332 }
6334 static int
6336 {
6338 {
6342 {
6356 }
6361 {
6373 }
6378 {
6390 }
6395 {
6401 }
6406 {
6410 }
6415 {
6419 }
6424 }
6427 }
6429 bool
6431 HOST_WIDE_INT minval,
6432 HOST_WIDE_INT maxval)
6433 {
6434 rtx elt;
6438 }
6440 bool
6442 {
6444 }
6446 /* Return true if VEC is a constant in which every element is in the range
6447 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
6449 static bool
6451 HOST_WIDE_INT minval,
6452 HOST_WIDE_INT maxval)
6453 {
6465 {
6470 }
6472 }
6474 /* N Z C V. */
6475 #define AARCH64_CC_V 1
6476 #define AARCH64_CC_C (1 << 1)
6477 #define AARCH64_CC_Z (1 << 2)
6478 #define AARCH64_CC_N (1 << 3)
6480 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
6482 {
6499 };
6501 /* Print floating-point vector immediate operand X to F, negating it
6502 first if NEGATE is true. Return true on success, false if it isn't
6503 a constant we can handle. */
6505 static bool
6507 {
6508 rtx elt;
6517 /* We only handle the SVE single-bit immediates here. */
6524 else
6528 }
6530 /* Return the equivalent letter for size. */
6531 static char
6533 {
6535 {
6541 }
6542 }
6544 /* Print operand X to file F in a target specific manner according to CODE.
6545 The acceptable formatting commands given by CODE are:
6546 'c': An integer or symbol address without a preceding #
6547 sign.
6548 'C': Take the duplicated element in a vector constant
6549 and print it in hex.
6550 'D': Take the duplicated element in a vector constant
6551 and print it as an unsigned integer, in decimal.
6552 'e': Print the sign/zero-extend size as a character 8->b,
6553 16->h, 32->w.
6554 'p': Prints N such that 2^N == X (X must be power of 2 and
6555 const int).
6556 'P': Print the number of non-zero bits in X (a const_int).
6557 'H': Print the higher numbered register of a pair (TImode)
6558 of regs.
6559 'm': Print a condition (eq, ne, etc).
6560 'M': Same as 'm', but invert condition.
6561 'N': Take the duplicated element in a vector constant
6562 and print the negative of it in decimal.
6563 'b/h/s/d/q': Print a scalar FP/SIMD register name.
6564 'S/T/U/V': Print a FP/SIMD register name for a register list.
6565 The register printed is the FP/SIMD register name
6566 of X + 0/1/2/3 for S/T/U/V.
6567 'R': Print a scalar FP/SIMD register name + 1.
6568 'X': Print bottom 16 bits of integer constant in hex.
6569 'w/x': Print a general register name or the zero register
6570 (32-bit or 64-bit).
6571 '0': Print a normal operand, if it's a general register,
6572 then we assume DImode.
6573 'k': Print NZCV for conditional compare instructions.
6574 'A': Output address constant representing the first
6575 argument of X, specifying a relocation offset
6576 if appropriate.
6577 'L': Output constant address specified by X
6578 with a relocation offset if appropriate.
6579 'G': Prints address of X, specifying a PC relative
6580 relocation mode if appropriate.
6581 'y': Output address of LDP or STP - this is used for
6582 some LDP/STPs which don't use a PARALLEL in their
6583 pattern (so the mode needs to be adjusted).
6584 'z': Output address of a typical LDP or STP. */
6586 static void
6588 {
6589 rtx elt;
6591 {
6594 {
6606 {
6609 }
6610 /* Fall through. */
6614 }
6618 {
6623 {
6626 }
6629 {
6642 }
6643 }
6647 {
6651 {
6654 }
6657 }
6662 {
6665 }
6672 {
6675 }
6682 {
6684 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
6686 {
6690 }
6693 {
6696 }
6703 }
6708 {
6711 }
6717 ;
6718 else
6719 {
6722 }
6731 {
6732 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6734 }
6743 {
6744 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6746 }
6754 {
6755 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
6757 }
6763 {
6766 }
6771 {
6772 /* Print a replicated constant in hex. */
6774 {
6777 }
6780 }
6784 {
6785 /* Print a replicated constant in decimal, treating it as
6786 unsigned. */
6788 {
6791 }
6794 }
6801 {
6804 }
6807 {
6810 }
6813 {
6816 }
6818 /* Fall through */
6822 {
6825 }
6828 {
6831 {
6834 else
6835 {
6836 char suffix
6841 }
6842 }
6843 else
6862 {
6865 }
6866 /* fall through */
6870 {
6873 }
6879 ;
6880 else
6881 {
6884 }
6888 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
6889 be getting CONST_DOUBLEs holding integers. */
6892 {
6895 }
6897 {
6898 #define buf_size 20
6906 #undef buf_size
6907 }
6913 }
6921 {
6948 }
6954 {
6989 }
6995 {
7001 }
7006 {
7007 HOST_WIDE_INT cond_code;
7010 {
7013 }
7018 }
7023 {
7028 {
7031 }
7034 /* LDP/STP which uses a single double-width memory operand.
7035 Adjust the mode to appear like a typical LDP/STP.
7036 Currently this is supported for 16-byte accesses only. */
7041 }
7047 }
7048 }
7050 /* Print address 'x' of a memory access with mode 'mode'.
7051 'op' is the context required by aarch64_classify_address. It can either be
7052 MEM for a normal memory access or PARALLEL for LDP/STP. */
7053 static bool
7055 aarch64_addr_query_type type)
7056 {
7060 /* Check all addresses are Pmode - including ILP32. */
7066 {
7071 {
7072 HOST_WIDE_INT vnum
7077 }
7079 {
7080 HOST_WIDE_INT vnum
7085 }
7086 else
7095 else
7104 else
7113 else
7119 /* Writeback is only supported for fixed-width modes. */
7122 {
7145 }
7157 }
7160 }
7162 /* Print address 'x' of a LDP/STP with mode 'mode'. */
7163 static bool
7165 {
7167 }
7169 /* Print address 'x' of a memory access with mode 'mode'. */
7170 static void
7172 {
7175 }
7177 bool
7179 {
7186 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
7187 referencing instruction, but they are constant offsets, not
7188 symbols. */
7194 {
7196 {
7202 }
7205 }
7208 }
7210 /* Implement REGNO_REG_CLASS. */
7212 enum reg_class
7214 {
7232 }
7234 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
7235 If OFFSET is out of range, return an offset of an anchor point
7236 that is in range. Return 0 otherwise. */
7238 static HOST_WIDE_INT
7240 machine_mode mode)
7241 {
7242 /* Does it look like we'll need a 16-byte load/store-pair operation? */
7246 /* For offsets that aren't a multiple of the access size, the limit is
7247 -256...255. */
7249 {
7250 /* BLKmode typically uses LDP of X-registers. */
7254 }
7256 /* Small negative offsets are supported. */
7263 /* Use 12-bit offset by access size. */
7265 }
7267 static rtx
7269 {
7270 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
7271 where mask is selected by alignment and size of the offset.
7272 We try to pick as large a range for the offset as possible to
7273 maximize the chance of a CSE. However, for aligned addresses
7274 we limit the range to 4k so that structures with different sized
7275 elements are likely to use the same base. We need to be careful
7276 not to split a CONST for some forms of address expression, otherwise
7277 it will generate sub-optimal code. */
7280 {
7286 {
7290 /* Force any scaling into a temp for CSE. */
7294 /* Let the pointer register be in op0. */
7298 /* If the pointer is virtual or frame related, then we know that
7299 virtual register instantiation or register elimination is going
7300 to apply a second constant. We want the two constants folded
7301 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
7303 {
7307 }
7309 /* Otherwise, in order to encourage CSE (and thence loop strength
7310 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
7314 }
7316 HOST_WIDE_INT size;
7318 {
7320 mode);
7322 {
7326 }
7327 }
7328 }
7331 }
7333 /* Return the reload icode required for a constant pool in mode. */
7334 static enum insn_code
7336 {
7338 {
7374 }
7377 }
7378 static reg_class_t
7380 reg_class_t rclass,
7381 machine_mode mode,
7383 {
7384 /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled
7385 directly by the *aarch64_sve_mov<mode>_be move pattern. See the
7386 comment at the head of aarch64-sve.md for more details about the
7387 big-endian handling. */
7393 {
7396 }
7398 /* If we have to disable direct literal pool loads and stores because the
7399 function is too big, then we need a scratch register. */
7404 {
7407 }
7409 /* Without the TARGET_SIMD instructions we cannot move a Q register
7410 to a Q register directly. We need a scratch. */
7414 {
7420 }
7422 /* A TFmode or TImode memory access should be handled via an FP_REGS
7423 because AArch64 has richer addressing modes for LDR/STR instructions
7424 than LDP/STP instructions. */
7433 }
7435 static bool
7437 {
7440 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
7441 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
7445 }
7447 poly_int64
7449 {
7453 {
7460 }
7463 {
7467 }
7470 }
7472 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7473 previous frame. */
7475 rtx
7477 {
7481 }
7484 static void
7486 {
7488 {
7491 }
7492 else
7493 {
7496 }
7501 }
7503 static void
7505 {
7509 /* Don't need to copy the trailing D-words, we fill those in below. */
7521 /* XXX We should really define a "clear_cache" pattern and use
7522 gen_clear_cache(). */
7527 ptr_mode);
7528 }
7530 static unsigned char
7532 {
7533 /* ??? Logically we should only need to provide a value when
7534 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
7535 can hold MODE, but at the moment we need to handle all modes.
7536 Just ignore any runtime parts for registers that can't store them. */
7540 {
7566 }
7568 }
7570 static reg_class_t
7572 {
7577 {
7583 }
7585 /* Register eliminiation can result in a request for
7586 SP+constant->FP_REGS. We cannot support such operations which
7587 use SP as source and an FP_REG as destination, so reject out
7588 right now. */
7590 {
7593 /* Look through a possible SUBREG introduced by ILP32. */
7599 POINTER_REGS));
7601 }
7604 }
7606 void
7608 {
7610 }
7612 static void
7614 {
7617 else
7618 {
7620 /* While priority is known to be in range [0, 65535], so 18 bytes
7621 would be enough, the compiler might not know that. To avoid
7622 -Wformat-truncation false positive, use a larger size. */
7629 }
7630 }
7632 static void
7634 {
7637 else
7638 {
7640 /* While priority is known to be in range [0, 65535], so 18 bytes
7641 would be enough, the compiler might not know that. To avoid
7642 -Wformat-truncation false positive, use a larger size. */
7649 }
7650 }
7654 {
7660 {
7661 {
7664 },
7665 {
7668 },
7669 {
7672 },
7673 /* We assume that DImode is only generated when not optimizing and
7674 that we don't really need 64-bit address offsets. That would
7675 imply an object file with 8GB of code in a single function! */
7676 {
7679 }
7680 };
7689 /* Need to implement table size reduction, by chaning the code below. */
7699 }
7702 /* Return size in bits of an arithmetic operand which is shifted/scaled and
7703 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
7704 operator. */
7706 int
7708 {
7710 {
7713 {
7717 }
7718 }
7720 }
7722 /* Constant pools are per function only when PC relative
7723 literal loads are true or we are in the large memory
7724 model. */
7728 {
7731 }
7733 static bool
7735 {
7736 /* Fixme:: In an ideal world this would work similar
7737 to the logic in aarch64_select_rtx_section but this
7738 breaks bootstrap in gcc go. For now we workaround
7739 this by returning false here. */
7741 }
7743 /* Select appropriate section for constants depending
7744 on where we place literal pools. */
7748 rtx x,
7750 {
7755 }
7757 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
7758 void
7760 HOST_WIDE_INT offset)
7761 {
7762 /* When using per-function literal pools, we must ensure that any code
7763 section is aligned to the minimal instruction length, lest we get
7764 errors from the assembler re "unaligned instructions". */
7767 }
7769 /* Costs. */
7771 /* Helper function for rtx cost calculation. Strip a shift expression
7772 from X. Returns the inner operand if successful, or the original
7773 expression on failure. */
7774 static rtx
7776 {
7779 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
7780 we can convert both to ROR during final output. */
7795 }
7797 /* Helper function for rtx cost calculation. Strip an extend
7798 expression from X. Returns the inner operand if successful, or the
7799 original expression on failure. We deal with a number of possible
7800 canonicalization variations here. If STRIP_SHIFT is true, then
7801 we can strip off a shift also. */
7802 static rtx
7804 {
7805 scalar_int_mode mode;
7811 /* Zero and sign extraction of a widened value. */
7819 /* It can also be represented (for zero-extend) as an AND with an
7820 immediate. */
7829 /* Now handle extended register, as this may also have an optional
7830 left shift by 1..4. */
7845 }
7847 /* Return true iff CODE is a shift supported in combination
7848 with arithmetic instructions. */
7850 static bool
7852 {
7854 }
7857 /* Return true iff X is a cheap shift without a sign extend. */
7859 static bool
7861 {
7887 }
7889 /* Helper function for rtx cost calculation. Calculate the cost of
7890 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
7891 Return the calculated cost of the expression, recursing manually in to
7892 operands where needed. */
7894 static int
7896 {
7912 /* Integer multiply/fma. */
7914 {
7915 /* The multiply will be canonicalized as a shift, cost it as such. */
7919 {
7923 {
7925 {
7926 /* If the shift is considered cheap,
7927 then don't add any cost. */
7929 ;
7931 /* ARITH + shift-by-register. */
7934 /* ARITH + extended register. We don't have a cost field
7935 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
7937 else
7938 /* ARITH + shift-by-immediate. */
7940 }
7941 else
7942 /* LSL (immediate). */
7945 }
7946 /* Strip extends as we will have costed them in the case above. */
7953 }
7955 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
7956 compound and let the below cases handle it. After all, MNEG is a
7957 special-case alias of MSUB. */
7959 {
7962 }
7964 /* Integer multiplies or FMAs have zero/sign extending variants. */
7969 {
7974 {
7976 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
7978 else
7979 /* MUL/SMULL/UMULL. */
7981 }
7984 }
7986 /* This is either an integer multiply or a MADD. In both cases
7987 we want to recurse and cost the operands. */
7992 {
7994 /* MADD/MSUB. */
7996 else
7997 /* MUL. */
7999 }
8002 }
8003 else
8004 {
8006 {
8007 /* Floating-point FMA/FMUL can also support negations of the
8008 operands, unless the rounding mode is upward or downward in
8009 which case FNMUL is different than FMUL with operand negation. */
8013 {
8018 }
8021 /* FMADD/FNMADD/FNMSUB/FMSUB. */
8023 else
8024 /* FMUL/FNMUL. */
8026 }
8031 }
8032 }
8034 static int
8036 machine_mode mode,
8037 addr_space_t as ATTRIBUTE_UNUSED,
8039 {
8047 {
8049 {
8050 /* This is a CONST or SYMBOL ref which will be split
8051 in a different way depending on the code model in use.
8052 Cost it through the generic infrastructure. */
8054 /* Divide through by the cost of one instruction to
8055 bring it to the same units as the address costs. */
8057 /* The cost is then the cost of preparing the address,
8058 followed by an immediate (possibly 0) offset. */
8060 }
8061 else
8062 {
8063 /* This is most likely a jump table from a case
8064 statement. */
8066 }
8067 }
8070 {
8082 else
8101 }
8105 {
8106 /* For the sake of calculating the cost of the shifted register
8107 component, we can treat same sized modes in the same way. */
8114 else
8115 /* We can't tell, or this is a 128-bit vector. */
8117 }
8120 }
8122 /* Return the cost of a branch. If SPEED_P is true then the compiler is
8123 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
8124 to be taken. */
8126 int
8128 {
8129 /* When optimizing for speed, use the cost of unpredictable branches. */
8135 else
8137 }
8139 /* Return true if the RTX X in mode MODE is a zero or sign extract
8140 usable in an ADD or SUB (extended register) instruction. */
8141 static bool
8143 {
8144 /* Catch add with a sign extract.
8145 This is add_<optab><mode>_multp2. */
8148 {
8159 op1))
8160 {
8162 }
8163 }
8164 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
8165 No shift. */
8171 }
8173 static bool
8175 {
8177 {
8189 }
8190 }
8192 /* Return true iff X is an rtx that will match an extr instruction
8193 i.e. as described in the *extr<mode>5_insn family of patterns.
8194 OP0 and OP1 will be set to the operands of the shifts involved
8195 on success and will be NULL_RTX otherwise. */
8197 static bool
8199 {
8201 scalar_int_mode mode;
8216 {
8217 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
8229 {
8233 }
8234 }
8237 }
8239 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
8240 storing it in *COST. Result is true if the total cost of the operation
8241 has now been calculated. */
8242 static bool
8244 {
8245 rtx inner;
8246 rtx comparator;
8250 {
8254 }
8255 else
8256 {
8260 }
8263 {
8264 /* Conditional branch. */
8267 else
8268 {
8270 {
8272 {
8273 /* TBZ/TBNZ/CBZ/CBNZ. */
8275 /* TBZ/TBNZ. */
8278 else
8279 /* CBZ/CBNZ. */
8283 }
8284 }
8286 {
8287 /* TBZ/TBNZ. */
8290 }
8291 }
8292 }
8294 {
8295 /* CCMP. */
8297 {
8298 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
8302 {
8309 else
8311 }
8313 }
8315 /* It's a conditional operation based on the status flags,
8316 so it must be some flavor of CSEL. */
8318 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
8324 {
8325 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
8328 }
8333 }
8335 /* We don't know what this is, cost all operands. */
8337 }
8339 /* Check whether X is a bitfield operation of the form shift + extend that
8340 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
8341 operand to which the bitfield operation is applied. Otherwise return
8342 NULL_RTX. */
8344 static rtx
8346 {
8360 {
8378 }
8381 }
8383 /* Return true if the mask and a shift amount from an RTX of the form
8384 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
8385 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
8387 bool
8389 rtx shft_amnt)
8390 {
8395 }
8397 /* Calculate the cost of calculating X, storing it in *COST. Result
8398 is true if the total cost of the operation has now been calculated. */
8399 static bool
8402 {
8407 scalar_int_mode int_mode;
8409 /* By default, assume that everything has equivalent cost to the
8410 cheapest instruction. Any additional costs are applied as a delta
8411 above this default. */
8415 {
8417 /* The cost depends entirely on the operands to SET. */
8423 {
8426 {
8440 }
8449 /* Fall through. */
8451 /* The cost is one per vector-register copied. */
8453 {
8456 }
8457 /* const0_rtx is in general free, but we will use an
8458 instruction to set a register to 0. */
8460 {
8461 /* The cost is 1 per register copied. */
8464 }
8465 else
8466 /* Cost is just the cost of the RHS of the set. */
8472 /* Bit-field insertion. Strip any redundant widening of
8473 the RHS to meet the width of the target. */
8484 {
8485 /* MOV immediate is assumed to always be cheap. */
8487 }
8488 else
8489 {
8490 /* BFM. */
8494 }
8499 /* We can't make sense of this, assume default cost. */
8502 }
8506 /* If an instruction can incorporate a constant within the
8507 instruction, the instruction's expression avoids calling
8508 rtx_cost() on the constant. If rtx_cost() is called on a
8509 constant, then it is usually because the constant must be
8510 moved into a register by one or more instructions.
8512 The exception is constant 0, which can be expressed
8513 as XZR/WZR and is therefore free. The exception to this is
8514 if we have (set (reg) (const0_rtx)) in which case we must cost
8515 the move. However, we can catch that when we cost the SET, so
8516 we don't need to consider that here. */
8519 else
8520 {
8521 /* To an approximation, building any other constant is
8522 proportionally expensive to the number of instructions
8523 required to build that constant. This is true whether we
8524 are compiling for SPEED or otherwise. */
8529 }
8534 /* First determine number of instructions to do the move
8535 as an integer constant. */
8539 {
8545 ? SImode
8551 }
8554 {
8555 /* mov[df,sf]_aarch64. */
8557 /* FMOV (scalar immediate). */
8560 {
8561 /* This will be a load from memory. */
8564 else
8566 }
8567 else
8568 /* Otherwise this is +0.0. We get this using MOVI d0, #0
8569 or MOV v0.s[0], wzr - neither of which are modeled by the
8570 cost tables. Just use the default cost. */
8571 {
8572 }
8573 }
8579 {
8580 /* For loads we want the base cost of a load, plus an
8581 approximation for the additional cost of the addressing
8582 mode. */
8596 }
8604 {
8606 {
8607 /* FNEG. */
8609 }
8611 }
8614 {
8617 {
8618 /* CSETM. */
8621 }
8623 /* Cost this as SUB wzr, X. */
8627 }
8630 {
8631 /* Support (neg(fma...)) as a single instruction only if
8632 sign of zeros is unimportant. This matches the decision
8633 making in aarch64.md. */
8635 {
8636 /* FNMADD. */
8639 }
8641 {
8642 /* FNMUL. */
8645 }
8647 /* FNEG. */
8650 }
8657 {
8660 else
8662 }
8672 {
8676 }
8679 {
8680 /* TODO: A write to the CC flags possibly costs extra, this
8681 needs encoding in the cost tables. */
8684 /* ANDS. */
8686 {
8689 }
8692 {
8693 /* ADDS (and CMN alias). */
8696 }
8699 {
8700 /* SUBS. */
8703 }
8708 {
8709 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
8710 Handle it here directly rather than going to cost_logic
8711 since we know the immediate generated for the TST is valid
8712 so we can avoid creating an intermediate rtx for it only
8713 for costing purposes. */
8720 }
8723 {
8724 /* CMN. */
8731 }
8733 /* CMP.
8735 Compare can freely swap the order of operands, and
8736 canonicalization puts the more complex operation first.
8737 But the integer MINUS logic expects the shift/extend
8738 operation in op1. */
8741 {
8744 }
8746 }
8749 {
8750 /* FCMP. */
8755 {
8757 /* FCMP supports constant 0.0 for no extra cost. */
8759 }
8761 }
8764 {
8765 /* Vector compare. */
8770 {
8771 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
8772 cost. */
8774 }
8776 }
8780 {
8784 cost_minus:
8787 /* Detect valid immediates. */
8793 {
8795 /* SUB(S) (immediate). */
8798 }
8800 /* Look for SUB (extended register). */
8803 {
8811 }
8815 /* Cost this as an FMA-alike operation. */
8819 {
8822 speed);
8824 }
8829 {
8831 {
8832 /* Vector SUB. */
8834 }
8836 {
8837 /* SUB(S). */
8839 }
8841 {
8842 /* FSUB. */
8844 }
8845 }
8847 }
8850 {
8851 rtx new_op0;
8856 cost_plus:
8859 {
8860 /* CSINC. */
8864 }
8869 {
8873 /* ADD (immediate). */
8876 }
8880 /* Look for ADD (extended register). */
8883 {
8891 }
8893 /* Strip any extend, leave shifts behind as we will
8894 cost them through mult_cost. */
8899 {
8901 speed);
8903 }
8908 {
8910 {
8911 /* Vector ADD. */
8913 }
8915 {
8916 /* ADD. */
8918 }
8920 {
8921 /* FADD. */
8923 }
8924 }
8926 }
8932 {
8935 else
8937 }
8942 {
8946 {
8949 else
8951 }
8953 }
8956 {
8963 }
8964 /* Fall through. */
8967 cost_logic:
8972 {
8976 }
8984 {
8985 /* This is a UBFM/SBFM. */
8990 }
8993 {
8995 {
8996 /* We have a mask + shift version of a UBFIZ
8997 i.e. the *andim_ashift<mode>_bfiz pattern. */
9001 {
9008 }
9010 {
9011 /* We possibly get the immediate for free, this is not
9012 modelled. */
9019 }
9020 }
9021 else
9022 {
9025 /* Handle ORN, EON, or BIC. */
9031 /* If we had a shift on op0 then this is a logical-shift-
9032 by-register/immediate operation. Otherwise, this is just
9033 a logical operation. */
9035 {
9037 {
9038 /* Shift by immediate. */
9041 else
9043 }
9044 else
9046 }
9048 /* In both cases we want to cost both operands. */
9055 }
9056 }
9064 {
9065 /* Vector NOT. */
9068 }
9070 /* MVN-shifted-reg. */
9072 {
9079 }
9080 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
9081 Handle the second form here taking care that 'a' in the above can
9082 be a shift. */
9084 {
9093 {
9096 else
9098 }
9101 }
9102 /* MVN. */
9111 /* If a value is written in SI mode, then zero extended to DI
9112 mode, the operation will in general be free as a write to
9113 a 'w' register implicitly zeroes the upper bits of an 'x'
9114 register. However, if this is
9116 (set (reg) (zero_extend (reg)))
9118 we must cost the explicit register move. */
9122 {
9125 /* If OP_COST is non-zero, then the cost of the zero extend
9126 is effectively the cost of the inner operation. Otherwise
9127 we have a MOV instruction and we take the cost from the MOV
9128 itself. This is true independently of whether we are
9129 optimizing for space or time. */
9134 }
9136 {
9137 /* All loads can zero extend to any size for free. */
9140 }
9144 {
9149 }
9152 {
9154 {
9155 /* UMOV. */
9157 }
9158 else
9159 {
9160 /* We generate an AND instead of UXTB/UXTH. */
9162 }
9163 }
9168 {
9169 /* LDRSH. */
9171 {
9178 }
9180 }
9184 {
9189 }
9192 {
9195 else
9197 }
9205 {
9207 {
9209 {
9210 /* Vector shift (immediate). */
9212 }
9213 else
9214 {
9215 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
9216 aliases. */
9218 }
9219 }
9221 /* We can incorporate zero/sign extend for free. */
9228 }
9229 else
9230 {
9232 {
9234 /* Vector shift (register). */
9236 }
9237 else
9238 {
9240 /* LSLV. */
9247 {
9249 /* We already demanded XEXP (op1, 0) to be REG_P, so
9250 don't recurse into it. */
9252 }
9253 }
9255 }
9265 {
9266 /* ASR (immediate) and friends. */
9268 {
9271 else
9273 }
9277 }
9278 else
9279 {
9281 {
9283 /* Vector shift (register). */
9285 }
9286 else
9287 {
9289 /* ASR (register) and friends. */
9296 {
9298 /* We already demanded XEXP (op1, 0) to be REG_P, so
9299 don't recurse into it. */
9301 }
9302 }
9304 }
9310 {
9311 /* LDR. */
9314 }
9317 {
9318 /* ADRP, followed by ADD. */
9322 }
9325 {
9326 /* ADR. */
9329 }
9332 {
9333 /* One extra load instruction, after accessing the GOT. */
9337 }
9342 /* ADRP/ADD (immediate). */
9349 /* UBFX/SBFX. */
9351 {
9354 else
9356 }
9358 /* We can trust that the immediates used will be correct (there
9359 are no by-register forms), so we need only cost op0. */
9365 /* aarch64_rtx_mult_cost always handles recursion to its
9366 operands. */
9370 /* We can expand signed mod by power of 2 using a NEGS, two parallel
9371 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
9372 an unconditional negate. This case should only ever be reached through
9373 the set_smod_pow2_cheap check in expmed.c. */
9377 {
9378 /* We expand to 4 instructions. Reset the baseline. */
9386 }
9388 /* Fall-through. */
9391 {
9392 /* Slighly prefer UMOD over SMOD. */
9399 }
9406 {
9410 /* There is no integer SQRT, so only DIV and UDIV can get
9411 here. */
9413 /* Slighly prefer UDIV over SDIV. */
9415 else
9417 }
9443 {
9446 else
9448 }
9450 /* FMSUB, FNMADD, and FNMSUB are free. */
9457 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
9458 and the by-element operand as operand 0. */
9462 /* Catch vector-by-element operations. The by-element operand can
9463 either be (vec_duplicate (vec_select (x))) or just
9464 (vec_select (x)), depending on whether we are multiplying by
9465 a vector or a scalar.
9467 Canonicalization is not very good in these cases, FMA4 will put the
9468 by-element operand as operand 0, FNMA4 will have it as operand 1. */
9479 /* If the remaining parameters are not registers,
9480 get the cost to put them into registers. */
9494 {
9496 {
9497 /*Vector truncate. */
9499 }
9500 else
9502 }
9507 {
9509 {
9510 /*Vector conversion. */
9512 }
9513 else
9515 }
9521 /* Strip the rounding part. They will all be implemented
9522 by the fcvt* family of instructions anyway. */
9524 {
9533 }
9536 {
9539 else
9541 }
9543 /* We can combine fmul by a power of 2 followed by a fcvt into a single
9544 fixed-point fcvt. */
9549 {
9553 }
9560 {
9561 /* ABS (vector). */
9564 }
9566 {
9569 /* FABD, which is analogous to FADD. */
9571 {
9578 }
9579 /* Simple FABS is analogous to FNEG. */
9582 }
9583 else
9584 {
9585 /* Integer ABS will either be split to
9586 two arithmetic instructions, or will be an ABS
9587 (scalar), which we don't model. */
9591 }
9597 {
9600 else
9601 {
9602 /* FMAXNM/FMINNM/FMAX/FMIN.
9603 TODO: This may not be accurate for all implementations, but
9604 we do not model this in the cost tables. */
9606 }
9607 }
9611 /* The floating point round to integer frint* instructions. */
9613 {
9618 }
9621 {
9626 }
9631 /* Decompose <su>muldi3_highpart. */
9633 mode == DImode
9634 /* (lshiftrt:TI */
9637 /* (mult:TI */
9639 /* (ANY_EXTEND:TI (reg:DI))
9640 (ANY_EXTEND:TI (reg:DI))) */
9647 /* (const_int 64) */
9650 {
9651 /* UMULH/SMULH. */
9659 }
9661 /* Fall through. */
9664 }
9672 }
9674 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
9675 calculated for X. This cost is stored in *COST. Returns true
9676 if the total cost of X was calculated. */
9677 static bool
9680 {
9685 {
9690 }
9693 }
9695 static int
9698 {
9704 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
9711 /* Moving between GPR and stack cost is the same as GP2GP. */
9716 /* To/From the stack register, we move via the gprs. */
9722 {
9723 /* 128-bit operations on general registers require 2 instructions. */
9731 /* When AdvSIMD instructions are disabled it is not possible to move
9732 a 128-bit value directly between Q registers. This is handled in
9733 secondary reload. A general register is used as a scratch to move
9734 the upper DI value and the lower DI value is moved directly,
9735 hence the cost is the sum of three moves. */
9740 }
9750 }
9752 static int
9754 reg_class_t rclass ATTRIBUTE_UNUSED,
9756 {
9758 }
9760 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
9761 to optimize 1.0/sqrt. */
9763 static bool
9765 {
9767 && flag_unsafe_math_optimizations
9771 }
9773 /* Function to decide when to use the approximate reciprocal square root
9774 builtin. */
9776 static tree
9778 {
9784 }
9788 /* Select reciprocal square root initial estimate insn depending on machine
9789 mode. */
9791 static rsqrte_type
9793 {
9795 {
9802 }
9803 }
9807 /* Select reciprocal square root series step insn depending on machine mode. */
9809 static rsqrts_type
9811 {
9813 {
9820 }
9821 }
9823 /* Emit instruction sequence to compute either the approximate square root
9824 or its approximate reciprocal, depending on the flag RECP, and return
9825 whether the sequence was emitted or not. */
9827 bool
9829 {
9833 {
9836 }
9839 {
9846 || flag_trapping_math
9847 || !flag_unsafe_math_optimizations
9850 }
9851 else
9852 /* Caller assumes we cannot fail. */
9858 /* When calculating the approximate square root, compare the
9859 argument with 0.0 and create a mask. */
9865 /* Estimate the approximate reciprocal square root. */
9869 /* Iterate over the series twice for SF and thrice for DF. */
9872 /* Optionally iterate over the series once less for faster performance
9873 while sacrificing the accuracy. */
9876 iterations--;
9878 /* Iterate over the series to calculate the approximate reciprocal square
9879 root. */
9882 {
9890 }
9893 {
9894 /* Qualify the approximate reciprocal square root when the argument is
9895 0.0 by squashing the intermediary result to 0.0. */
9901 /* Calculate the approximate square root. */
9903 }
9905 /* Finalize the approximation. */
9909 }
9913 /* Select reciprocal initial estimate insn depending on machine mode. */
9915 static recpe_type
9917 {
9919 {
9926 }
9927 }
9931 /* Select reciprocal series step insn depending on machine mode. */
9933 static recps_type
9935 {
9937 {
9944 }
9945 }
9947 /* Emit the instruction sequence to compute the approximation for the division
9948 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
9950 bool
9952 {
9963 || flag_trapping_math
9964 || !flag_unsafe_math_optimizations
9972 /* Estimate the approximate reciprocal. */
9976 /* Iterate over the series twice for SF and thrice for DF. */
9979 /* Optionally iterate over the series once less for faster performance,
9980 while sacrificing the accuracy. */
9982 iterations--;
9984 /* Iterate over the series to calculate the approximate reciprocal. */
9987 {
9992 }
9995 {
9996 /* As the approximate reciprocal of DEN is already calculated, only
9997 calculate the approximate division when NUM is not 1.0. */
10000 }
10002 /* Finalize the approximation. */
10005 }
10007 /* Return the number of instructions that can be issued per cycle. */
10008 static int
10010 {
10012 }
10014 static int
10016 {
10020 }
10023 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
10024 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
10025 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
10027 static int
10030 {
10032 }
10035 /* Vectorizer cost model target hooks. */
10037 /* Implement targetm.vectorize.builtin_vectorization_cost. */
10038 static int
10040 tree vectype,
10042 {
10051 {
10102 }
10103 }
10105 /* Implement targetm.vectorize.add_stmt_cost. */
10106 static unsigned
10110 {
10115 {
10120 /* Statements in an inner loop relative to the loop being
10121 vectorized are weighted more heavily. The value here is
10122 arbitrary and could potentially be improved with analysis. */
10128 }
10131 }
10135 /* Parse the TO_PARSE string and put the architecture struct that it
10136 selects into RES and the architectural features into ISA_FLAGS.
10137 Return an aarch64_parse_opt_result describing the parse result.
10138 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
10140 static enum aarch64_parse_opt_result
10143 {
10155 else
10162 /* Loop through the list of supported ARCHes to find a match. */
10164 {
10166 {
10170 {
10171 /* TO_PARSE string contains at least one extension. */
10172 enum aarch64_parse_opt_result ext_res
10177 }
10178 /* Extension parsing was successful. Confirm the result
10179 arch and ISA flags. */
10183 }
10184 }
10186 /* ARCH name not found in list. */
10188 }
10190 /* Parse the TO_PARSE string and put the result tuning in RES and the
10191 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
10192 describing the parse result. If there is an error parsing, RES and
10193 ISA_FLAGS are left unchanged. */
10195 static enum aarch64_parse_opt_result
10198 {
10210 else
10217 /* Loop through the list of supported CPUs to find a match. */
10219 {
10221 {
10226 {
10227 /* TO_PARSE string contains at least one extension. */
10228 enum aarch64_parse_opt_result ext_res
10233 }
10234 /* Extension parsing was successfull. Confirm the result
10235 cpu and ISA flags. */
10239 }
10240 }
10242 /* CPU name not found in list. */
10244 }
10246 /* Parse the TO_PARSE string and put the cpu it selects into RES.
10247 Return an aarch64_parse_opt_result describing the parse result.
10248 If the parsing fails the RES does not change. */
10250 static enum aarch64_parse_opt_result
10252 {
10258 /* Loop through the list of supported CPUs to find a match. */
10260 {
10262 {
10265 }
10266 }
10268 /* CPU name not found in list. */
10270 }
10272 /* Parse TOKEN, which has length LENGTH to see if it is an option
10273 described in FLAG. If it is, return the index bit for that fusion type.
10274 If not, error (printing OPTION_NAME) and return zero. */
10276 static unsigned int
10281 {
10283 {
10287 }
10291 }
10293 /* Parse OPTION which is a comma-separated list of flags to enable.
10294 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
10295 default state we inherit from the CPU tuning structures. OPTION_NAME
10296 gives the top-level option we are parsing in the -moverride string,
10297 for use in error messages. */
10299 static unsigned int
10304 {
10311 {
10314 token_length,
10315 flags,
10316 option_name);
10317 /* If we find "none" (or, for simplicity's sake, an error) anywhere
10318 in the token stream, reset the supported operations. So:
10320 adrp+add.cmp+branch.none.adrp+add
10322 would have the result of turning on only adrp+add fusion. */
10328 }
10330 /* We ended with a comma, print something. */
10332 {
10335 }
10337 /* We still have one more token to parse. */
10340 token_length,
10341 flags,
10342 option_name);
10348 }
10350 /* Support for overriding instruction fusion. */
10352 static void
10355 {
10357 aarch64_fusible_pairs,
10360 }
10362 /* Support for overriding other tuning flags. */
10364 static void
10367 {
10368 tune->extra_tuning_flags
10370 aarch64_tuning_flags,
10373 }
10375 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
10376 we understand. If it is, extract the option string and handoff to
10377 the appropriate function. */
10379 void
10383 {
10389 {
10392 }
10394 /* Get the length of the option name. */
10396 /* Skip the '=' to get to the option string. */
10397 option_part++;
10400 {
10402 {
10405 }
10406 }
10410 }
10412 /* A checking mechanism for the implementation of the tls size. */
10414 static void
10416 {
10421 {
10423 /* Both the default and maximum TLS size allowed under tiny is 1M which
10424 needs two instructions to address, so we clamp the size to 24. */
10429 /* The maximum TLS size allowed under small is 4G. */
10434 /* The maximum TLS size allowed under large is 16E.
10435 FIXME: 16E should be 64bit, we only support 48bit offset now. */
10441 }
10444 }
10446 /* Parse STRING looking for options in the format:
10447 string :: option:string
10448 option :: name=substring
10449 name :: {a-z}
10450 substring :: defined by option. */
10452 static void
10455 {
10466 {
10468 /* Make this substring look like a string. */
10472 }
10474 /* One last option to parse. */
10477 }
10480 static void
10482 {
10483 /* PR 70044: We have to be careful about being called multiple times for the
10484 same function. This means all changes should be repeatable. */
10486 /* If the frame pointer is enabled, set it to a special value that behaves
10487 similar to frame pointer omission. If we don't do this all leaf functions
10488 will get a frame pointer even if flag_omit_leaf_frame_pointer is set.
10489 If flag_omit_frame_pointer has this special value, we must force the
10490 frame pointer if not in a leaf function. We also need to force it in a
10491 leaf function if flag_omit_frame_pointer is not set or if LR is used. */
10495 /* If not optimizing for size, set the default
10496 alignment to what the target wants. */
10498 {
10505 }
10507 /* We default to no pc-relative literal loads. */
10511 /* If -mpc-relative-literal-loads is set on the command line, this
10512 implies that the user asked for PC relative literal loads. */
10516 /* In the tiny memory model it makes no sense to disallow PC relative
10517 literal pool loads. */
10522 /* When enabling the lower precision Newton series for the square root, also
10523 enable it for the reciprocal square root, since the latter is an
10524 intermediary step for the former. */
10527 }
10529 /* 'Unpack' up the internal tuning structs and update the options
10530 in OPTS. The caller must have set up selected_tune and selected_arch
10531 as all the other target-specific codegen decisions are
10532 derived from them. */
10534 void
10536 {
10539 /* Make a copy of the tuning parameters attached to the core, which
10540 we may later overwrite. */
10548 /* This target defaults to strict volatile bitfields. */
10557 {
10569 }
10571 /* We don't mind passing in global_options_set here as we don't use
10572 the *options_set structs anyway. */
10574 queue_depth,
10578 /* Set up parameters to be used in prefetching algorithm. Do not
10579 override the defaults unless we are tuning for a core we have
10580 researched values for. */
10602 /* Use the alternative scheduling-pressure algorithm by default. */
10607 /* Enable sw prefetching at specified optimization level for
10608 CPUS that have prefetch. Lower optimization level threshold by 1
10609 when profiling is enabled. */
10617 }
10619 /* Print a hint with a suggestion for a core or architecture name that
10620 most closely resembles what the user passed in STR. ARCH is true if
10621 the user is asking for an architecture name. ARCH is false if the user
10622 is asking for a core name. */
10624 static void
10626 {
10632 #ifdef HAVE_LOCAL_CPU_DETECT
10633 /* Add also "native" as possible value. */
10636 #endif
10643 else
10647 }
10649 /* Print a hint with a suggestion for a core name that most closely resembles
10650 what the user passed in STR. */
10654 {
10656 }
10658 /* Print a hint with a suggestion for an architecture name that most closely
10659 resembles what the user passed in STR. */
10663 {
10665 }
10667 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
10668 specified in STR and throw errors if appropriate. Put the results if
10669 they are valid in RES and ISA_FLAGS. Return whether the option is
10670 valid. */
10672 static bool
10675 {
10676 enum aarch64_parse_opt_result parse_res
10683 {
10696 }
10699 }
10701 /* Validate a command-line -march option. Parse the arch and extensions
10702 (if any) specified in STR and throw errors if appropriate. Put the
10703 results, if they are valid, in RES and ISA_FLAGS. Return whether the
10704 option is valid. */
10706 static bool
10709 {
10710 enum aarch64_parse_opt_result parse_res
10717 {
10730 }
10733 }
10735 /* Validate a command-line -mtune option. Parse the cpu
10736 specified in STR and throw errors if appropriate. Put the
10737 result, if it is valid, in RES. Return whether the option is
10738 valid. */
10740 static bool
10742 {
10743 enum aarch64_parse_opt_result parse_res
10750 {
10760 }
10762 }
10764 /* Return the CPU corresponding to the enum CPU.
10765 If it doesn't specify a cpu, return the default. */
10769 {
10773 /* The & 0x3f is to extract the bottom 6 bits that encode the
10774 default cpu as selected by the --with-cpu GCC configure option
10775 in config.gcc.
10776 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
10777 flags mechanism should be reworked to make it more sane. */
10779 }
10781 /* Return the architecture corresponding to the enum ARCH.
10782 If it doesn't specify a valid architecture, return the default. */
10786 {
10793 }
10795 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
10797 static poly_uint16
10799 {
10800 /* For now generate vector-length agnostic code for -msve-vector-bits=128.
10801 This ensures we can clearly distinguish SVE and Advanced SIMD modes when
10802 deciding which .md file patterns to use and when deciding whether
10803 something is a legitimate address or constant. */
10806 else
10808 }
10810 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
10811 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
10812 tuning structs. In particular it must set selected_tune and
10813 aarch64_isa_flags that define the available ISA features and tuning
10814 decisions. It must also set selected_arch as this will be used to
10815 output the .arch asm tags for each function. */
10817 static void
10819 {
10832 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
10833 If either of -march or -mtune is given, they override their
10834 respective component of -mcpu. */
10846 /* If the user did not specify a processor, choose the default
10847 one for them. This will be the CPU set during configuration using
10848 --with-cpu, otherwise it is "generic". */
10850 {
10852 {
10856 }
10857 else
10858 {
10859 /* Get default configure-time CPU. */
10862 }
10866 }
10867 /* If both -mcpu and -march are specified check that they are architecturally
10868 compatible, warn if they're not and prefer the -march ISA flags. */
10870 {
10872 {
10876 }
10881 }
10882 else
10883 {
10884 /* -mcpu but no -march. */
10891 }
10893 /* Set the arch as well as we will need it when outputing
10894 the .arch directive in assembly. */
10896 {
10899 }
10904 #ifndef HAVE_AS_MABI_OPTION
10905 /* The compiler may have been configured with 2.23.* binutils, which does
10906 not have support for ILP32. */
10909 #endif
10911 /* Convert -msve-vector-bits to a VG count. */
10917 /* Make sure we properly set up the explicit options. */
10928 /* Save these options as the default ones in case we push and pop them later
10929 while processing functions with potential target attributes. */
10930 target_option_default_node = target_option_current_node
10932 }
10934 /* Implement targetm.override_options_after_change. */
10936 static void
10938 {
10940 }
10944 {
10948 }
10950 void
10952 {
10954 }
10956 /* A checking mechanism for the implementation of the various code models. */
10957 static void
10959 {
10961 {
10963 {
10968 #ifdef HAVE_AS_SMALL_PIC_RELOCS
10970 ? AARCH64_CMODEL_SMALL_PIC
10972 #else
10974 #endif
10982 }
10983 }
10984 else
10986 }
10988 /* Implement TARGET_OPTION_SAVE. */
10990 static void
10992 {
10994 }
10996 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
10997 using the information saved in PTR. */
10999 static void
11001 {
11009 }
11011 /* Implement TARGET_OPTION_PRINT. */
11013 static void
11015 {
11026 }
11030 void
11032 {
11034 }
11036 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
11037 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
11038 make sure optab availability predicates are recomputed when necessary. */
11040 void
11042 {
11047 else
11049 }
11051 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
11052 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
11053 of the function, if such exists. This function may be called multiple
11054 times on a single function so use aarch64_previous_fndecl to avoid
11055 setting up identical state. */
11057 static void
11059 {
11063 tree old_tree = (aarch64_previous_fndecl
11069 /* If current function has no attributes but the previous one did,
11070 use the default node. */
11074 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
11075 the default have been handled by aarch64_save_restore_target_globals from
11076 aarch64_pragma_target_parse. */
11082 /* First set the target options. */
11086 }
11088 /* Enum describing the various ways we can handle attributes.
11089 In many cases we can reuse the generic option handling machinery. */
11091 enum aarch64_attr_opt_type
11092 {
11096 aarch64_attr_custom /* Attribute requires a custom handling function. */
11097 };
11099 /* All the information needed to handle a target attribute.
11100 NAME is the name of the attribute.
11101 ATTR_TYPE specifies the type of behavior of the attribute as described
11102 in the definition of enum aarch64_attr_opt_type.
11103 ALLOW_NEG is true if the attribute supports a "no-" form.
11104 HANDLER is the function that takes the attribute string as an argument
11105 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
11106 OPT_NUM is the enum specifying the option that the attribute modifies.
11107 This is needed for attributes that mirror the behavior of a command-line
11108 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
11109 aarch64_attr_enum. */
11111 struct aarch64_attribute_info
11112 {
11118 };
11120 /* Handle the ARCH_STR argument to the arch= target attribute. */
11122 static bool
11124 {
11126 enum aarch64_parse_opt_result parse_res
11130 {
11135 }
11138 {
11151 }
11154 }
11156 /* Handle the argument CPU_STR to the cpu= target attribute. */
11158 static bool
11160 {
11162 enum aarch64_parse_opt_result parse_res
11166 {
11174 }
11177 {
11190 }
11193 }
11195 /* Handle the argument STR to the tune= target attribute. */
11197 static bool
11199 {
11201 enum aarch64_parse_opt_result parse_res
11205 {
11210 }
11213 {
11220 }
11223 }
11225 /* Parse an architecture extensions target attribute string specified in STR.
11226 For example "+fp+nosimd". Show any errors if needed. Return TRUE
11227 if successful. Update aarch64_isa_flags to reflect the ISA features
11228 modified. */
11230 static bool
11232 {
11236 /* We allow "+nothing" in the beginning to clear out all architectural
11237 features if the user wants to handpick specific features. */
11239 {
11242 }
11247 {
11250 }
11253 {
11264 }
11267 }
11269 /* The target attributes that we support. On top of these we also support just
11270 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
11271 handled explicitly in aarch64_process_one_target_attr. */
11274 {
11276 OPT_mgeneral_regs_only },
11278 OPT_mfix_cortex_a53_835769 },
11280 OPT_mfix_cortex_a53_843419 },
11284 OPT_momit_leaf_frame_pointer },
11287 OPT_march_ },
11290 OPT_mtune_ },
11292 OPT_msign_return_address_ },
11294 };
11296 /* Parse ARG_STR which contains the definition of one target attribute.
11297 Show appropriate errors if any or return true if the attribute is valid. */
11299 static bool
11301 {
11307 {
11310 }
11315 /* Skip leading whitespace. */
11317 str_to_check++;
11319 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
11320 It is easier to detect and handle it explicitly here rather than going
11321 through the machinery for the rest of the target attributes in this
11322 function. */
11327 {
11330 }
11333 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
11334 and point ARG to "foo". */
11336 {
11338 arg++;
11339 }
11343 {
11344 /* If the names don't match up, or the user has given an argument
11345 to an attribute that doesn't accept one, or didn't give an argument
11346 to an attribute that expects one, fail to match. */
11355 {
11358 }
11360 /* If the name matches but the attribute does not allow "no-" versions
11361 then we can't match. */
11363 {
11366 }
11369 {
11370 /* Has a custom handler registered.
11371 For example, cpu=, arch=, tune=. */
11378 /* Either set or unset a boolean option. */
11380 {
11388 }
11389 /* Set or unset a bit in the target_flags. aarch64_handle_option
11390 should know what mask to apply given the option number. */
11392 {
11394 /* We only need to specify the option number.
11395 aarch64_handle_option will know which mask to apply. */
11401 }
11402 /* Use the option setting machinery to set an option to an enum. */
11404 {
11411 {
11414 global_dc);
11415 }
11416 else
11417 {
11419 }
11421 }
11424 }
11425 }
11427 /* If we reached here we either have found an attribute and validated
11428 it or didn't match any. If we matched an attribute but its arguments
11429 were malformed we will have returned false already. */
11431 }
11433 /* Count how many times the character C appears in
11434 NULL-terminated string STR. */
11436 static unsigned int
11438 {
11441 {
11443 res++;
11445 str++;
11446 }
11449 }
11451 /* Parse the tree in ARGS that contains the target attribute information
11452 and update the global target options space. */
11454 bool
11456 {
11458 {
11459 do
11460 {
11463 {
11466 }
11471 }
11474 {
11477 }
11484 {
11487 }
11489 /* Used to catch empty spaces between commas i.e.
11490 attribute ((target ("attr1,,attr2"))). */
11493 /* Handle multiple target attributes separated by ','. */
11498 {
11499 num_attrs++;
11501 {
11504 }
11507 }
11510 {
11513 }
11516 }
11518 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
11519 process attribute ((target ("..."))). */
11521 static bool
11523 {
11526 tree old_optimize;
11530 /* If what we're processing is the current pragma string then the
11531 target option node is already stored in target_option_current_node
11532 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
11533 having to re-parse the string. This is especially useful to keep
11534 arm_neon.h compile times down since that header contains a lot
11535 of intrinsics enclosed in pragmas. */
11537 {
11540 }
11546 /* If the function changed the optimization levels as well as setting
11547 target options, start with the optimizations specified. */
11552 /* Save the current target options to restore at the end. */
11555 /* If fndecl already has some target attributes applied to it, unpack
11556 them so that we add this attribute on top of them, rather than
11557 overwriting them. */
11559 {
11565 }
11566 else
11572 /* Set up any additional state. */
11574 {
11576 /* Initialize SIMD builtins if we haven't already.
11577 Set current_target_pragma to NULL for the duration so that
11578 the builtin initialization code doesn't try to tag the functions
11579 being built with the attributes specified by any current pragma, thus
11580 going into an infinite recursion. */
11582 {
11587 }
11589 }
11590 else
11596 {
11601 }
11609 }
11611 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
11612 tri-bool options (yes, no, don't care) and the default value is
11613 DEF, determine whether to reject inlining. */
11615 static bool
11618 {
11619 /* If the callee doesn't care, always allow inlining. */
11623 /* If the caller doesn't care, always allow inlining. */
11627 /* Otherwise, allow inlining if either the callee and caller values
11628 agree, or if the callee is using the default value. */
11630 }
11632 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
11633 to inline CALLEE into CALLER based on target-specific info.
11634 Make sure that the caller and callee have compatible architectural
11635 features. Then go through the other possible target attributes
11636 and see if they can block inlining. Try not to reject always_inline
11637 callees unless they are incompatible architecturally. */
11639 static bool
11641 {
11645 /* If callee has no option attributes, then it is ok to inline. */
11656 /* Callee's ISA flags should be a subset of the caller's. */
11661 /* Allow non-strict aligned functions inlining into strict
11662 aligned ones. */
11672 /* If the architectural features match up and the callee is always_inline
11673 then the other attributes don't matter. */
11685 /* Honour explicit requests to workaround errata. */
11698 /* If the user explicitly specified -momit-leaf-frame-pointer for the
11699 caller and calle and they don't match up, reject inlining. */
11706 /* If the callee has specific tuning overrides, respect them. */
11711 /* If the user specified tuning override strings for the
11712 caller and callee and they don't match up, reject inlining.
11713 We just do a string compare here, we don't analyze the meaning
11714 of the string, as it would be too costly for little gain. */
11722 }
11724 /* Return true if SYMBOL_REF X binds locally. */
11726 static bool
11728 {
11732 }
11734 /* Return true if SYMBOL_REF X is thread local */
11735 static bool
11737 {
11745 }
11747 /* Classify a TLS symbol into one of the TLS kinds. */
11748 enum aarch64_symbol_type
11750 {
11754 {
11761 {
11767 }
11778 else
11787 }
11788 }
11790 /* Return the correct method for accessing X + OFFSET, where X is either
11791 a SYMBOL_REF or LABEL_REF. */
11793 enum aarch64_symbol_type
11795 {
11797 {
11799 {
11814 }
11815 }
11818 {
11823 {
11825 /* When we retrieve symbol + offset address, we have to make sure
11826 the offset does not cause overflow of the final address. But
11827 we have no way of knowing the address of symbol at compile time
11828 so we can't accurately say if the distance between the PC and
11829 symbol + offset is outside the addressible range of +/-1M in the
11830 TINY code model. So we rely on images not being greater than
11831 1M and cap the offset at 1M and anything beyond 1M will have to
11832 be loaded using an alternative mechanism. Furthermore if the
11833 symbol is a weak reference to something that isn't known to
11834 resolve to a symbol in this module, then force to memory. */
11842 /* Same reasoning as the tiny code model, but the offset cap here is
11843 4G. */
11864 /* This is alright even in PIC code as the constant
11865 pool reference is always PC relative and within
11866 the same translation unit. */
11869 else
11874 }
11875 }
11877 /* By default push everything into the constant pool. */
11879 }
11881 bool
11883 {
11885 }
11887 bool
11889 {
11897 }
11899 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
11900 that should be rematerialized rather than spilled. */
11902 static bool
11904 {
11905 /* Support CSE and rematerialization of common constants. */
11911 /* Do not allow vector struct mode constants for Advanced SIMD.
11912 We could support 0 and -1 easily, but they need support in
11913 aarch64-simd.md. */
11918 /* Only accept variable-length vector constants if they can be
11919 handled directly.
11921 ??? It would be possible to handle rematerialization of other
11922 constants via secondary reloads. */
11929 /* Accept polynomial constants that can be calculated by using the
11930 destination of a move as the sole temporary. Constants that
11931 require a second temporary cannot be rematerialized (they can't be
11932 forced to memory and also aren't legitimate constants). */
11933 poly_int64 offset;
11937 /* If an offset is being added to something else, we need to allow the
11938 base to be moved into the destination register, meaning that there
11939 are no free temporaries for the offset. */
11944 /* Do not allow const (plus (anchor_symbol, const_int)). */
11948 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
11949 so spilling them is better than rematerialization. */
11953 /* Label references are always constant. */
11958 }
11960 rtx
11962 {
11968 /* Can return in any reg. */
11971 }
11973 /* On AAPCS systems, this is the "struct __va_list". */
11976 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
11977 Return the type to use as __builtin_va_list.
11979 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
11981 struct __va_list
11982 {
11983 void *__stack;
11984 void *__gr_top;
11985 void *__vr_top;
11986 int __gr_offs;
11987 int __vr_offs;
11988 }; */
11990 static tree
11992 {
11993 tree va_list_name;
11996 /* Create the type. */
11998 /* Give it the required name. */
12000 TYPE_DECL,
12002 va_list_type);
12007 /* Create the fields. */
12010 ptr_type_node);
12013 ptr_type_node);
12016 ptr_type_node);
12019 integer_type_node);
12022 integer_type_node);
12024 /* Tell tree-stdarg pass about our internal offset fields.
12025 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
12026 purpose to identify whether the code is updating va_list internal
12027 offset fields through irregular way. */
12049 /* Compute its layout. */
12053 }
12055 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
12056 static void
12058 {
12062 tree t;
12076 {
12079 }
12088 NULL_TREE);
12090 NULL_TREE);
12092 NULL_TREE);
12094 NULL_TREE);
12096 NULL_TREE);
12098 /* Emit code to initialize STACK, which points to the next varargs stack
12099 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
12100 by named arguments. STACK is 8-byte aligned. */
12107 /* Emit code to initialize GRTOP, the top of the GR save area.
12108 virtual_incoming_args_rtx should have been 16 byte aligned. */
12113 /* Emit code to initialize VRTOP, the top of the VR save area.
12114 This address is gr_save_area_bytes below GRTOP, rounded
12115 down to the next 16-byte boundary. */
12125 /* Emit code to initialize GROFF, the offset from GRTOP of the
12126 next GPR argument. */
12131 /* Likewise emit code to initialize VROFF, the offset from FTOP
12132 of the next VR argument. */
12136 }
12138 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
12140 static tree
12143 {
12144 tree addr;
12150 machine_mode mode;
12177 type,
12181 {
12182 /* No frontends can create types with variable-sized modes, so we
12183 shouldn't be asked to pass or return them. */
12186 /* TYPE passed in fp/simd registers. */
12198 {
12201 }
12204 {
12206 }
12207 }
12208 else
12209 {
12210 /* TYPE passed in general registers. */
12223 {
12225 }
12226 }
12228 /* Get a local temporary for the field value. */
12231 /* Emit code to branch if off >= 0. */
12237 {
12238 /* Emit: offs = (offs + 15) & -16. */
12244 }
12245 else
12248 /* Update ap.__[g|v]r_offs */
12253 /* String up. */
12257 /* [cond2] if (ap.__[g|v]r_offs > 0) */
12262 /* String up: make sure the assignment happens before the use. */
12266 /* Prepare the trees handling the argument that is passed on the stack;
12267 the top level node will store in ON_STACK. */
12270 {
12271 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
12279 }
12280 else
12282 /* Advance ap.__stack */
12290 /* String up roundup and advance. */
12293 /* String up with arg */
12295 /* Big-endianness related address adjustment. */
12298 {
12302 }
12307 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
12317 {
12318 /* type ha; // treat as "struct {ftype field[n];}"
12319 ... [computing offs]
12320 for (i = 0; i <nregs; ++i, offs += 16)
12321 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
12322 return ha; */
12326 /* Declare a local variable. */
12330 /* Establish the base type. */
12332 {
12351 {
12355 }
12359 }
12361 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
12369 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
12371 {
12381 }
12385 }
12395 }
12397 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
12399 static void
12403 {
12405 CUMULATIVE_ARGS local_cum;
12409 /* The caller has advanced CUM up to, but not beyond, the last named
12410 argument. Advance a local copy of CUM past the last "real" named
12411 argument, to find out how many registers are left over. */
12415 /* Found out how many registers we need to save.
12416 Honor tree-stdvar analysis results. */
12425 {
12428 }
12431 {
12433 {
12436 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
12444 }
12446 {
12447 /* We can't use move_block_from_reg, because it will use
12448 the wrong mode, storing D regs only. */
12452 /* Set OFF to the offset from virtual_incoming_args_rtx of
12453 the first vector register. The VR save area lies below
12454 the GR one, and is aligned to 16 bytes. */
12461 {
12469 }
12470 }
12471 }
12473 /* We don't save the size into *PRETEND_SIZE because we want to avoid
12474 any complication of having crtl->args.pretend_args_size changed. */
12479 }
12481 static void
12483 {
12486 {
12488 {
12491 }
12492 }
12495 {
12498 }
12499 }
12501 /* Walk down the type tree of TYPE counting consecutive base elements.
12502 If *MODEP is VOIDmode, then set it to the first valid floating point
12503 type. If a non-floating point type is found, or if a floating point
12504 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
12505 otherwise return the count in the sub-tree. */
12506 static int
12508 {
12509 machine_mode mode;
12510 HOST_WIDE_INT size;
12513 {
12543 /* Use V2SImode and V4SImode as representatives of all 64-bit
12544 and 128-bit vector types. */
12547 {
12556 }
12561 /* Vector modes are considered to be opaque: two vectors are
12562 equivalent for the purposes of being homogeneous aggregates
12563 if they are the same size. */
12570 {
12574 /* Can't handle incomplete types nor sizes that are not
12575 fixed. */
12582 || !index
12593 /* There must be no padding. */
12599 }
12602 {
12605 tree field;
12607 /* Can't handle incomplete types nor sizes that are not
12608 fixed. */
12614 {
12622 }
12624 /* There must be no padding. */
12630 }
12634 {
12635 /* These aren't very interesting except in a degenerate case. */
12638 tree field;
12640 /* Can't handle incomplete types nor sizes that are not
12641 fixed. */
12647 {
12655 }
12657 /* There must be no padding. */
12663 }
12667 }
12670 }
12672 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
12673 type as described in AAPCS64 \S 4.1.2.
12675 See the comment above aarch64_composite_type_p for the notes on MODE. */
12677 static bool
12679 machine_mode mode)
12680 {
12690 }
12692 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
12693 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
12694 array types. The C99 floating-point complex types are also considered
12695 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
12696 types, which are GCC extensions and out of the scope of AAPCS64, are
12697 treated as composite types here as well.
12699 Note that MODE itself is not sufficient in determining whether a type
12700 is such a composite type or not. This is because
12701 stor-layout.c:compute_record_mode may have already changed the MODE
12702 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
12703 structure with only one field may have its MODE set to the mode of the
12704 field. Also an integer mode whose size matches the size of the
12705 RECORD_TYPE type may be used to substitute the original mode
12706 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
12707 solely relied on. */
12709 static bool
12711 machine_mode mode)
12712 {
12725 }
12727 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
12728 shall be passed or returned in simd/fp register(s) (providing these
12729 parameter passing registers are available).
12731 Upon successful return, *COUNT returns the number of needed registers,
12732 *BASE_MODE returns the mode of the individual register and when IS_HAF
12733 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
12734 floating-point aggregate or a homogeneous short-vector aggregate. */
12736 static bool
12738 const_tree type,
12742 {
12750 {
12753 }
12755 {
12759 }
12761 {
12765 {
12768 }
12769 else
12771 }
12772 else
12777 }
12779 /* Implement TARGET_STRUCT_VALUE_RTX. */
12781 static rtx
12784 {
12786 }
12788 /* Implements target hook vector_mode_supported_p. */
12789 static bool
12791 {
12794 }
12796 /* Return appropriate SIMD container
12797 for MODE within a vector of WIDTH bits. */
12798 static machine_mode
12800 {
12803 {
12820 }
12824 {
12827 {
12844 }
12845 else
12847 {
12860 }
12861 }
12863 }
12865 /* Return 128-bit container as the preferred SIMD mode for MODE. */
12866 static machine_mode
12868 {
12871 }
12873 /* Return a list of possible vector sizes for the vectorizer
12874 to iterate over. */
12875 static void
12877 {
12882 }
12884 /* Implement TARGET_MANGLE_TYPE. */
12888 {
12889 /* The AArch64 ABI documents say that "__va_list" has to be
12890 managled as if it is in the "std" namespace. */
12894 /* Half-precision float. */
12898 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
12899 builtin types. */
12903 /* Use the default mangling. */
12905 }
12907 /* Find the first rtx_insn before insn that will generate an assembly
12908 instruction. */
12912 {
12916 do
12917 {
12919 }
12923 }
12925 static bool
12927 {
12929 /* A number of these may be AArch32 only. */
12934 };
12937 {
12940 }
12943 }
12945 /* Check if there is a register dependency between a load and the insn
12946 for which we hold recog_data. */
12948 static bool
12950 {
12951 rtx load_reg;
12961 {
12967 }
12969 }
12972 /* When working around the Cortex-A53 erratum 835769,
12973 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
12974 instruction and has a preceding memory instruction such that a NOP
12975 should be inserted between them. */
12977 bool
12979 {
12982 rtx body;
12995 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
12996 Restore recog state to INSN to avoid state corruption. */
13004 /* If the previous insn is a memory op and there is no dependency between
13005 it and the DImode madd, emit a NOP between them. If body is NULL then we
13006 have a complex memory operation, probably a load/store pair.
13007 Be conservative for now and emit a NOP. */
13014 }
13017 /* Implement FINAL_PRESCAN_INSN. */
13019 void
13021 {
13024 }
13027 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
13028 instruction. */
13030 bool
13032 {
13035 }
13037 /* Return true if X is a valid immediate for the SVE ADD and SUB
13038 instructions. Negate X first if NEGATE_P is true. */
13040 bool
13042 {
13043 rtx elt;
13057 }
13059 /* Return true if X is a valid immediate operand for an SVE logical
13060 instruction such as AND. */
13062 bool
13064 {
13065 rtx elt;
13071 }
13073 /* Return true if X is a valid immediate for the SVE DUP and CPY
13074 instructions. */
13076 bool
13078 {
13079 rtx elt;
13089 }
13091 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
13092 SIGNED_P says whether the operand is signed rather than unsigned. */
13094 bool
13096 {
13097 rtx elt;
13101 && (signed_p
13104 }
13106 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
13107 instruction. Negate X first if NEGATE_P is true. */
13109 bool
13111 {
13112 rtx elt;
13113 REAL_VALUE_TYPE r;
13129 }
13131 /* Return true if X is a valid immediate operand for an SVE FMUL
13132 instruction. */
13134 bool
13136 {
13137 rtx elt;
13139 /* GCC will never generate a multiply with an immediate of 2, so there is no
13140 point testing for it (even though it is a valid constant). */
13144 }
13146 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
13147 for the Advanced SIMD operation described by WHICH and INSN. If INFO
13148 is nonnull, use it to describe valid immediates. */
13149 static bool
13154 {
13155 /* Try a 4-byte immediate with LSL. */
13158 {
13163 }
13165 /* Try a 2-byte immediate with LSL. */
13170 {
13175 }
13177 /* Try a 4-byte immediate with MSL, except for cases that MVN
13178 can handle. */
13181 {
13184 {
13189 }
13190 }
13193 }
13195 /* Return true if replicating VAL64 is a valid immediate for the
13196 Advanced SIMD operation described by WHICH. If INFO is nonnull,
13197 use it to describe valid immediates. */
13198 static bool
13202 {
13208 {
13219 /* Try using a replicated byte. */
13223 {
13227 }
13228 }
13230 /* Try using a bit-to-bytemask. */
13232 {
13235 {
13239 }
13241 {
13245 }
13246 }
13248 }
13250 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
13251 instruction. If INFO is nonnull, use it to describe valid immediates. */
13253 static bool
13256 {
13260 {
13264 {
13269 }
13270 }
13273 {
13274 /* DUP with no shift. */
13278 }
13280 {
13281 /* DUP with LSL #8. */
13285 }
13287 {
13288 /* DUPM. */
13292 }
13294 }
13296 /* Return true if OP is a valid SIMD immediate for the operation
13297 described by WHICH. If INFO is nonnull, use it to describe valid
13298 immediates. */
13299 bool
13302 {
13316 {
13325 }
13329 else
13332 /* Handle PFALSE and PTRUE. */
13337 scalar_float_mode elt_float_mode;
13340 {
13344 {
13348 }
13349 }
13357 /* Expand the vector constant out into a byte vector, with the least
13358 significant byte of the register first. */
13362 {
13363 /* The vector is provided in gcc endian-neutral fashion.
13364 For aarch64_be Advanced SIMD, it must be laid out in the vector
13365 register in reverse order. */
13377 {
13380 }
13381 }
13383 /* The immediate must repeat every eight bytes. */
13389 /* Get the repeating 8-byte value as an integer. No endian correction
13390 is needed here because bytes is already in lsb-first order. */
13398 else
13400 }
13402 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
13403 has a step in the range of INDEX. Return the index expression if so,
13404 otherwise return null. */
13405 rtx
13407 {
13414 }
13416 /* Check of immediate shift constants are within range. */
13417 bool
13419 {
13423 else
13425 }
13427 /* Return the bitmask CONST_INT to select the bits required by a zero extract
13428 operation of width WIDTH at bit position POS. */
13430 rtx
13432 {
13436 unsigned HOST_WIDE_INT mask
13439 }
13441 bool
13443 {
13462 }
13464 /* Return a const_int vector of VAL. */
13465 rtx
13467 {
13470 }
13472 /* Check OP is a legal scalar immediate for the MOVI instruction. */
13474 bool
13476 {
13477 machine_mode vmode;
13482 }
13484 /* Construct and return a PARALLEL RTX vector with elements numbering the
13485 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
13486 the vector - from the perspective of the architecture. This does not
13487 line up with GCC's perspective on lane numbers, so we end up with
13488 different masks depending on our target endian-ness. The diagram
13489 below may help. We must draw the distinction when building masks
13490 which select one half of the vector. An instruction selecting
13491 architectural low-lanes for a big-endian target, must be described using
13492 a mask selecting GCC high-lanes.
13494 Big-Endian Little-Endian
13496 GCC 0 1 2 3 3 2 1 0
13497 | x | x | x | x | | x | x | x | x |
13498 Architecture 3 2 1 0 3 2 1 0
13500 Low Mask: { 2, 3 } { 0, 1 }
13501 High Mask: { 0, 1 } { 2, 3 }
13503 MODE Is the mode of the vector and NUNITS is the number of units in it. */
13505 rtx
13507 {
13512 rtx t1;
13517 else
13525 }
13527 /* Check OP for validity as a PARALLEL RTX vector with elements
13528 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
13529 from the perspective of the architecture. See the diagram above
13530 aarch64_simd_vect_par_cnst_half for more details. */
13532 bool
13535 {
13549 {
13556 }
13558 }
13560 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
13561 HIGH (exclusive). */
13562 void
13564 const_tree exp)
13565 {
13566 HOST_WIDE_INT lane;
13571 {
13574 else
13576 }
13577 }
13579 /* Peform endian correction on lane number N, which indexes a vector
13580 of mode MODE, and return the result as an SImode rtx. */
13582 rtx
13584 {
13586 }
13588 /* Return TRUE if OP is a valid vector addressing mode. */
13590 bool
13592 {
13595 }
13597 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
13599 bool
13601 {
13603 scalar_mode mode;
13610 }
13612 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
13613 The conditions for STR are the same. */
13614 bool
13616 {
13623 }
13625 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
13626 We need to be able to access the individual pieces, so the range
13627 is different from LD[234] and ST[234]. */
13628 bool
13630 {
13637 ADDR_QUERY_ANY)
13645 }
13647 /* Emit a register copy from operand to operand, taking care not to
13648 early-clobber source registers in the process.
13650 COUNT is the number of components into which the copy needs to be
13651 decomposed. */
13652 void
13655 {
13665 else
13669 }
13671 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
13672 one of VSTRUCT modes: OI, CI, or XI. */
13673 int
13675 {
13676 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
13678 }
13680 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
13681 alignment of a vector to 128 bits. SVE predicates have an alignment of
13682 16 bits. */
13683 static HOST_WIDE_INT
13685 {
13687 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
13688 be set for non-predicate vectors of booleans. Modes are the most
13689 direct way we have of identifying real SVE predicate types. */
13693 }
13695 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
13696 static HOST_WIDE_INT
13698 {
13700 {
13701 /* If the length of the vector is fixed, try to align to that length,
13702 otherwise don't try to align at all. */
13703 HOST_WIDE_INT result;
13707 }
13709 }
13711 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
13712 static bool
13714 {
13718 /* For fixed-length vectors, check that the vectorizer will aim for
13719 full-vector alignment. This isn't true for generic GCC vectors
13720 that are wider than the ABI maximum of 128 bits. */
13726 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
13728 }
13730 /* Return true if the vector misalignment factor is supported by the
13731 target. */
13732 static bool
13736 {
13738 {
13739 /* Return if movmisalign pattern is not supported for this mode. */
13743 /* Misalignment factor is unknown at compile time. */
13746 }
13748 is_packed);
13749 }
13751 /* If VALS is a vector constant that can be loaded into a register
13752 using DUP, generate instructions to do so and return an RTX to
13753 assign to the register. Otherwise return NULL_RTX. */
13754 static rtx
13756 {
13759 rtx x;
13764 /* We can load this constant by using DUP and a constant in a
13765 single ARM register. This will be cheaper than a vector
13766 load. */
13769 }
13772 /* Generate code to load VALS, which is a PARALLEL containing only
13773 constants (for vec_init) or CONST_VECTOR, efficiently into a
13774 register. Returns an RTX to copy into the register, or NULL_RTX
13775 for a PARALLEL that can not be converted into a CONST_VECTOR. */
13776 static rtx
13778 {
13780 rtx const_dup;
13788 {
13789 /* A CONST_VECTOR must contain only CONST_INTs and
13790 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
13791 Only store valid constants in a CONST_VECTOR. */
13794 {
13797 n_const++;
13798 }
13801 }
13802 else
13807 /* Load using MOVI/MVNI. */
13810 /* Loaded using DUP. */
13813 /* Load from constant pool. We can not take advantage of single-cycle
13814 LD1 because we need a PC-relative addressing mode. */
13816 else
13817 /* A PARALLEL containing something not valid inside CONST_VECTOR.
13818 We can not construct an initializer. */
13820 }
13822 /* Expand a vector initialisation sequence, such that TARGET is
13823 initialised to contain VALS. */
13825 void
13827 {
13830 /* The number of vector elements. */
13832 /* The number of vector elements which are not constant. */
13835 /* The first element of vals. */
13839 /* Count the number of variable elements to initialise. */
13841 {
13845 else
13849 }
13851 /* No variable elements, hand off to aarch64_simd_make_constant which knows
13852 how best to handle this. */
13854 {
13857 {
13860 }
13861 }
13863 /* Splat a single non-constant element if we can. */
13865 {
13869 }
13874 /* If there are only variable elements, try to optimize
13875 the insertion using dup for the most common element
13876 followed by insertions. */
13878 /* The algorithm will fill matches[*][0] with the earliest matching element,
13879 and matches[X][1] with the count of duplicate elements (if X is the
13880 earliest element which has duplicates). */
13883 {
13886 {
13888 {
13890 {
13894 }
13895 }
13896 }
13901 {
13904 }
13906 /* Create a duplicate of the most common element. */
13910 /* Insert the rest. */
13912 {
13918 }
13920 }
13922 /* Initialise a vector which is part-variable. We want to first try
13923 to build those lanes which are constant in the most efficient way we
13924 can. */
13926 {
13929 /* Load constant part of vector. We really don't care what goes into the
13930 parts we will overwrite, but we're more likely to be able to load the
13931 constant efficiently if it has fewer, larger, repeating parts
13932 (see aarch64_simd_valid_immediate). */
13934 {
13940 {
13941 /* Look in the copied vector, as more elements are const. */
13944 {
13947 }
13948 }
13950 }
13952 }
13954 /* Insert the variable lanes directly. */
13956 {
13962 }
13963 }
13965 static unsigned HOST_WIDE_INT
13967 {
13971 }
13973 /* Select a format to encode pointers in exception handling data. */
13974 int
13976 {
13979 {
13985 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
13986 for everything. */
13990 /* No assumptions here. 8-byte relocs required. */
13993 }
13995 }
13997 /* The last .arch and .tune assembly strings that we printed. */
14001 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
14002 by the function fndecl. */
14004 void
14006 tree fndecl)
14007 {
14013 else
14024 /* Only update the assembler .arch string if it is distinct from the last
14025 such string we printed. */
14028 {
14031 }
14033 /* Print the cpu name we're tuning for in the comments, might be
14034 useful to readers of the generated asm. Do it only when it changes
14035 from function to function and verbose assembly is requested. */
14040 {
14044 }
14046 /* Don't forget the type directive for ELF. */
14049 }
14051 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
14053 static void
14055 {
14072 }
14074 /* Emit load exclusive. */
14076 static void
14079 {
14083 {
14090 }
14093 }
14095 /* Emit store exclusive. */
14097 static void
14100 {
14104 {
14111 }
14114 }
14116 /* Mark the previous jump instruction as unlikely. */
14118 static void
14120 {
14123 }
14125 /* Expand a compare and swap pattern. */
14127 void
14129 {
14134 gen_cas_fn gen;
14136 {
14137 gen_aarch64_compare_and_swapqi,
14138 gen_aarch64_compare_and_swaphi,
14139 gen_aarch64_compare_and_swapsi,
14140 gen_aarch64_compare_and_swapdi
14141 };
14143 {
14144 gen_aarch64_compare_and_swapqi_lse,
14145 gen_aarch64_compare_and_swaphi_lse,
14146 gen_aarch64_compare_and_swapsi_lse,
14147 gen_aarch64_compare_and_swapdi_lse
14148 };
14161 /* Normally the succ memory model must be stronger than fail, but in the
14162 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
14163 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
14170 {
14173 /* For short modes, we're going to perform the comparison in SImode,
14174 so do the zero-extension now. */
14178 /* Fall through. */
14182 /* Force the value into a register if needed. */
14189 }
14192 {
14199 }
14202 else
14213 }
14215 /* Test whether the target supports using a atomic load-operate instruction.
14216 CODE is the operation and AFTER is TRUE if the data in memory after the
14217 operation should be returned and FALSE if the data before the operation
14218 should be returned. Returns FALSE if the operation isn't supported by the
14219 architecture. */
14221 bool
14223 {
14228 {
14238 }
14239 }
14241 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
14242 sequence implementing an atomic operation. */
14244 static void
14246 {
14253 {
14255 }
14256 }
14258 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
14259 for the data in memory. EXPECTED is the value expected to be in memory.
14260 DESIRED is the value to store to memory. MEM is the memory location. MODEL
14261 is the memory ordering to use. */
14263 void
14266 rtx model)
14267 {
14269 machine_mode mode;
14274 {
14281 }
14283 /* Move the expected value into the CAS destination register. */
14286 /* Emit the CAS. */
14289 /* Compare the expected value with the value loaded by the CAS, to establish
14290 whether the swap was made. */
14292 }
14294 /* Split a compare and swap pattern. */
14296 void
14298 {
14300 machine_mode mode;
14305 rtx model_rtx;
14317 /* When OLDVAL is zero and we want the strong version we can emit a tighter
14318 loop:
14319 .label1:
14320 LD[A]XR rval, [mem]
14321 CBNZ rval, .label2
14322 ST[L]XR scratch, newval, [mem]
14323 CBNZ scratch, .label1
14324 .label2:
14325 CMP rval, 0. */
14330 {
14333 }
14336 /* The initial load can be relaxed for a __sync operation since a final
14337 barrier will be emitted to stop code hoisting. */
14341 else
14345 {
14350 }
14351 else
14352 {
14358 }
14363 {
14368 }
14369 else
14370 {
14374 }
14377 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
14378 to set the condition flags. If this is not used it will be removed by
14379 later passes. */
14381 {
14385 }
14386 /* Emit any final barrier needed for a __sync operation. */
14389 }
14391 /* Emit a BIC instruction. */
14393 static void
14395 {
14400 {
14405 }
14408 }
14410 /* Emit an atomic swap. */
14412 static void
14415 {
14419 {
14426 }
14429 }
14431 /* Operations supported by aarch64_emit_atomic_load_op. */
14433 enum aarch64_atomic_load_op_code
14434 {
14438 AARCH64_LDOP_BIC /* A & ~B */
14439 };
14441 /* Emit an atomic load-operate. */
14443 static void
14447 {
14450 {
14451 gen_aarch64_atomic_loadaddqi,
14452 gen_aarch64_atomic_loadaddhi,
14453 gen_aarch64_atomic_loadaddsi,
14454 gen_aarch64_atomic_loadadddi
14455 };
14457 {
14458 gen_aarch64_atomic_loadeorqi,
14459 gen_aarch64_atomic_loadeorhi,
14460 gen_aarch64_atomic_loadeorsi,
14461 gen_aarch64_atomic_loadeordi
14462 };
14464 {
14465 gen_aarch64_atomic_loadsetqi,
14466 gen_aarch64_atomic_loadsethi,
14467 gen_aarch64_atomic_loadsetsi,
14468 gen_aarch64_atomic_loadsetdi
14469 };
14471 {
14472 gen_aarch64_atomic_loadclrqi,
14473 gen_aarch64_atomic_loadclrhi,
14474 gen_aarch64_atomic_loadclrsi,
14475 gen_aarch64_atomic_loadclrdi
14476 };
14477 aarch64_atomic_load_op_fn gen;
14481 {
14488 }
14491 {
14498 }
14501 }
14503 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
14504 location to store the data read from memory. OUT_RESULT is the location to
14505 store the result of the operation. MEM is the memory location to read and
14506 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
14507 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
14508 be NULL. */
14510 void
14513 {
14517 aarch64_atomic_load_op_code ldop_code;
14518 rtx src;
14519 rtx x;
14527 /* Make sure the value is in a register, putting it into a destination
14528 register if it needs to be manipulated. */
14531 {
14534 }
14535 else
14539 /* Preprocess the data for the operation as necessary. If the operation is
14540 a SET then emit a swap instruction and finish. */
14542 {
14548 /* Negate the value and treat it as a PLUS. */
14549 {
14550 rtx neg_src;
14552 /* Resize the value if necessary. */
14561 }
14562 /* Fall-through. */
14576 {
14577 rtx not_src;
14579 /* Resize the value if necessary. */
14588 }
14593 /* The operation can't be done with atomic instructions. */
14595 }
14599 /* If necessary, calculate the data in memory after the update by redoing the
14600 operation from values in registers. */
14605 {
14609 }
14614 {
14630 }
14635 }
14637 /* Split an atomic operation. */
14639 void
14642 {
14648 rtx x;
14650 /* Split the atomic operation into a sequence. */
14658 else
14662 /* The initial load can be relaxed for a __sync operation since a final
14663 barrier will be emitted to stop code hoisting. */
14667 else
14671 {
14685 {
14688 }
14689 /* Fall through. */
14695 }
14705 /* Emit any final barrier needed for a __sync operation. */
14708 }
14710 static void
14712 {
14713 /* Half-precision float operations. The compiler handles all operations
14714 with NULL libfuncs by converting to SFmode. */
14716 /* Conversions. */
14720 /* Arithmetic. */
14727 /* Comparisons. */
14735 }
14737 /* Target hook for c_mode_for_suffix. */
14738 static machine_mode
14740 {
14745 }
14747 /* We can only represent floating point constants which will fit in
14748 "quarter-precision" values. These values are characterised by
14749 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
14750 by:
14752 (-1)^s * (n/16) * 2^r
14754 Where:
14755 's' is the sign bit.
14756 'n' is an integer in the range 16 <= n <= 31.
14757 'r' is an integer in the range -3 <= r <= 4. */
14759 /* Return true iff X can be represented by a quarter-precision
14760 floating point immediate operand X. Note, we cannot represent 0.0. */
14761 bool
14763 {
14764 /* This represents our current view of how many bits
14765 make up the mantissa. */
14775 /* We don't support HFmode constants yet. */
14781 /* We cannot represent infinities, NaNs or +/-zero. We won't
14782 know if we have +zero until we analyse the mantissa, but we
14783 can reject the other invalid values. */
14788 /* Extract exponent. */
14792 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
14793 highest (sign) bit, with a fixed binary point at bit point_pos.
14794 m1 holds the low part of the mantissa, m2 the high part.
14795 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
14796 bits for the mantissa, this can fail (low bits will be lost). */
14800 /* If the low part of the mantissa has bits set we cannot represent
14801 the value. */
14804 /* We have rejected the lower HOST_WIDE_INT, so update our
14805 understanding of how many bits lie in the mantissa and
14806 look only at the high HOST_WIDE_INT. */
14810 /* We can only represent values with a mantissa of the form 1.xxxx. */
14815 /* Having filtered unrepresentable values, we may now remove all
14816 but the highest 5 bits. */
14819 /* We cannot represent the value 0.0, so reject it. This is handled
14820 elsewhere. */
14824 /* Then, as bit 4 is always set, we can mask it off, leaving
14825 the mantissa in the range [0, 15]. */
14829 /* GCC internally does not use IEEE754-like encoding (where normalized
14830 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
14831 Our mantissa values are shifted 4 places to the left relative to
14832 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
14833 by 5 places to correct for GCC's representation. */
14837 }
14839 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
14840 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
14841 output MOVI/MVNI, ORR or BIC immediate. */
14845 {
14855 /* This will return true to show const_vector is legal for use as either
14856 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
14857 It will also update INFO to show how the immediate should be generated.
14858 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
14866 {
14868 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
14869 move immediate path. */
14872 else
14873 {
14882 else
14886 }
14887 }
14892 {
14902 else
14906 }
14907 else
14908 {
14909 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
14915 else
14919 }
14921 }
14925 {
14927 /* If a floating point number was passed and we desire to use it in an
14928 integer mode do the conversion to integer. */
14930 {
14935 }
14937 machine_mode vmode;
14938 /* use a 64 bit mode for everything except for DI/DF mode, where we use
14939 a 128 bit vector mode. */
14945 }
14947 /* Return the output string to use for moving immediate CONST_VECTOR
14948 into an SVE register. */
14952 {
14963 {
14968 }
14971 {
14974 else
14975 {
14985 }
14986 }
14991 }
14993 /* Return the asm format for a PTRUE instruction whose destination has
14994 mode MODE. SUFFIX is the element size suffix. */
14998 {
15003 else
15006 }
15008 /* Split operands into moves from op[1] + op[2] into op[0]. */
15010 void
15012 {
15023 {
15024 /* No-op move. Can't split to nothing; emit something. */
15027 }
15029 /* Preserve register attributes for variable tracking. */
15034 /* Special case of reversed high/low parts. */
15037 {
15041 }
15043 {
15044 /* Try to avoid unnecessary moves if part of the result
15045 is in the right place already. */
15050 }
15051 else
15052 {
15057 }
15058 }
15060 /* vec_perm support. */
15062 struct expand_vec_perm_d
15063 {
15065 vec_perm_indices perm;
15066 machine_mode vmode;
15070 };
15072 /* Generate a variable permutation. */
15074 static void
15076 {
15087 {
15089 {
15090 /* Expand the argument to a V16QI mode by duplicating it. */
15094 }
15095 else
15096 {
15098 }
15099 }
15100 else
15101 {
15102 rtx pair;
15105 {
15109 }
15110 else
15111 {
15115 }
15116 }
15117 }
15119 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
15120 NELT is the number of elements in the vector. */
15122 void
15125 {
15128 rtx mask;
15130 /* The TBL instruction does not use a modulo index, so we must take care
15131 of that ourselves. */
15136 /* For big-endian, we also need to reverse the index within the vector
15137 (but not which vector). */
15139 {
15140 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
15145 }
15147 }
15149 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
15151 static void
15153 {
15157 }
15159 /* Expand an SVE vec_perm with the given operands. */
15161 void
15163 {
15166 /* Enforced by the pattern condition. */
15169 /* Note: vec_perm indices are supposed to wrap when they go beyond the
15170 size of the two value vectors, i.e. the upper bits of the indices
15171 are effectively ignored. SVE TBL instead produces 0 for any
15172 out-of-range indices, so we need to modulo all the vec_perm indices
15173 to ensure they are all in range. */
15176 /* Check if the sel only references the first values vector. */
15179 {
15182 }
15184 /* Check if the two values vectors are the same. */
15186 {
15192 }
15194 /* Run TBL on for each value vector and combine the results. */
15201 {
15206 }
15213 else
15215 }
15217 /* Recognize patterns suitable for the TRN instructions. */
15218 static bool
15220 {
15221 HOST_WIDE_INT odd;
15229 /* Note that these are little-endian tests.
15230 We correct for big-endian later. */
15237 /* Success! */
15243 /* We don't need a big-endian lane correction for SVE; see the comment
15244 at the head of aarch64-sve.md for details. */
15246 {
15249 }
15255 }
15257 /* Recognize patterns suitable for the UZP instructions. */
15258 static bool
15260 {
15261 HOST_WIDE_INT odd;
15268 /* Note that these are little-endian tests.
15269 We correct for big-endian later. */
15275 /* Success! */
15281 /* We don't need a big-endian lane correction for SVE; see the comment
15282 at the head of aarch64-sve.md for details. */
15284 {
15287 }
15293 }
15295 /* Recognize patterns suitable for the ZIP instructions. */
15296 static bool
15298 {
15307 /* Note that these are little-endian tests.
15308 We correct for big-endian later. */
15316 /* Success! */
15322 /* We don't need a big-endian lane correction for SVE; see the comment
15323 at the head of aarch64-sve.md for details. */
15325 {
15328 }
15334 }
15336 /* Recognize patterns for the EXT insn. */
15338 static bool
15340 {
15341 HOST_WIDE_INT location;
15342 rtx offset;
15344 /* The first element always refers to the first vector.
15345 Check if the extracted indices are increasing by one. */
15351 /* Success! */
15355 /* The case where (location == 0) is a no-op for both big- and little-endian,
15356 and is removed by the mid-end at optimization levels -O1 and higher.
15358 We don't need a big-endian lane correction for SVE; see the comment
15359 at the head of aarch64-sve.md for details. */
15361 {
15362 /* After setup, we want the high elements of the first vector (stored
15363 at the LSB end of the register), and the low elements of the second
15364 vector (stored at the MSB end of the register). So swap. */
15366 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
15367 to_constant () is safe since this is restricted to Advanced SIMD
15368 vectors. */
15370 }
15376 UNSPEC_EXT));
15378 }
15380 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
15381 within each 64-bit, 32-bit or 16-bit granule. */
15383 static bool
15385 {
15386 HOST_WIDE_INT diff;
15388 machine_mode pred_mode;
15397 {
15400 }
15402 {
15405 }
15407 {
15410 }
15411 else
15419 /* Success! */
15425 {
15428 UNSPEC_MERGE_PTRUE);
15429 }
15432 }
15434 /* Recognize patterns for the REV insn, which reverses elements within
15435 a full vector. */
15437 static bool
15439 {
15448 /* Success! */
15455 }
15457 static bool
15459 {
15461 rtx in0;
15462 HOST_WIDE_INT elt;
15464 rtx lane;
15474 /* Success! */
15478 /* The generic preparation in aarch64_expand_vec_perm_const_1
15479 swaps the operand order and the permute indices if it finds
15480 d->perm[0] to be in the second operand. Thus, we can always
15481 use d->op0 and need not do any extra arithmetic to get the
15482 correct lane number. */
15490 }
15492 static bool
15494 {
15498 /* Make sure that the indices are constant. */
15507 /* Generic code will try constant permutation twice. Once with the
15508 original mode and again with the elements lowered to QImode.
15509 So wait and don't do the selector expansion ourselves. */
15513 /* to_constant is safe since this routine is specific to Advanced SIMD
15514 vectors. */
15517 /* If big-endian and two vectors we end up with a weird mixed-endian
15518 mode on NEON. Reverse the index within each word but not the word
15519 itself. to_constant is safe because we checked is_constant above. */
15529 }
15531 /* Try to implement D using an SVE TBL instruction. */
15533 static bool
15535 {
15538 /* Permuting two variable-length vectors could overflow the
15539 index range. */
15550 }
15552 static bool
15554 {
15555 /* The pattern matching functions above are written to look for a small
15556 number to begin the sequence (0, 1, N/2). If we begin with an index
15557 from the second operand, we can swap the operands. */
15560 {
15563 }
15569 {
15588 }
15590 }
15592 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
15594 static bool
15597 {
15600 /* Check whether the mask can be applied to a single vector. */
15604 {
15607 }
15609 {
15612 }
15613 else
15633 }
15635 /* Generate a byte permute mask for a register of mode MODE,
15636 which has NUNITS units. */
15638 rtx
15640 {
15641 /* We have to reverse each vector because we dont have
15642 a permuted load that can reverse-load according to ABI rules. */
15643 rtx mask;
15656 }
15658 /* Return true if X is a valid second operand for the SVE instruction
15659 that implements integer comparison OP_CODE. */
15661 static bool
15663 {
15668 {
15683 }
15684 }
15686 /* Return the UNSPEC_COND_* code for comparison CODE. */
15688 static unsigned int
15690 {
15692 {
15717 }
15718 }
15720 /* Return an (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>) expression,
15721 where <X> is the operation associated with comparison CODE. */
15723 static rtx
15726 {
15729 }
15731 /* Expand an SVE integer comparison:
15733 TARGET = CODE (OP0, OP1). */
15735 void
15737 {
15747 }
15749 /* Emit an instruction:
15751 (set TARGET (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>))
15753 where <X> is the operation associated with comparison CODE. */
15755 static void
15758 {
15761 }
15763 /* Emit:
15765 (set TMP1 (unspec:PRED_MODE [PTRUE OP0 OP1] UNSPEC_COND_<X1>))
15766 (set TMP2 (unspec:PRED_MODE [PTRUE OP0 OP1] UNSPEC_COND_<X2>))
15767 (set TARGET (and:PRED_MODE (ior:PRED_MODE TMP1 TMP2) PTRUE))
15769 where <Xi> is the operation associated with comparison CODEi. */
15771 static void
15775 {
15782 ptrue));
15783 }
15785 /* If CAN_INVERT_P, emit an instruction:
15787 (set TARGET (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>))
15789 where <X> is the operation associated with comparison CODE. Otherwise
15790 emit:
15792 (set TMP (unspec:PRED_MODE [PRED OP0 OP1] UNSPEC_COND_<X>))
15793 (set TARGET (and:PRED_MODE (not:PRED_MODE TMP) PTRUE))
15795 where the second instructions sets TARGET to the inverse of TMP. */
15797 static void
15801 {
15804 else
15805 {
15810 ptrue));
15811 }
15812 }
15814 /* Expand an SVE floating-point comparison:
15816 TARGET = CODE (OP0, OP1)
15818 If CAN_INVERT_P is true, the caller can also handle inverted results;
15819 return true if the result is in fact inverted. */
15821 bool
15824 {
15830 {
15832 /* UNORDERED has no immediate form. */
15843 /* There is native support for the comparison. */
15848 /* There is native support for the inverse comparison. */
15852 can_invert_p);
15856 /* This is a trapping operation (LT or GT). */
15862 {
15863 /* This would trap for signaling NaNs. */
15868 }
15869 /* fall through */
15875 {
15878 {
15879 /* Only compare the elements that are known to be ordered. */
15884 }
15887 else
15892 }
15896 }
15897 }
15899 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
15900 of the data being selected and CMP_MODE is the mode of the values being
15901 compared. */
15903 void
15906 {
15907 machine_mode pred_mode
15912 {
15916 }
15917 else
15922 }
15924 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
15925 true. However due to issues with register allocation it is preferable
15926 to avoid tieing integer scalar and FP scalar modes. Executing integer
15927 operations in general registers is better than treating them as scalar
15928 vector operations. This reduces latency and avoids redundant int<->FP
15929 moves. So tie modes if they are either the same class, or vector modes
15930 with other vector modes, vector structs or any scalar mode. */
15932 static bool
15934 {
15938 /* We specifically want to allow elements of "structure" modes to
15939 be tieable to the structure. This more general condition allows
15940 other rarer situations too. The reason we don't extend this to
15941 predicate modes is that there are no predicate structure modes
15942 nor any specific instructions for extracting part of a predicate
15943 register. */
15948 /* Also allow any scalar modes with vectors. */
15954 }
15956 /* Return a new RTX holding the result of moving POINTER forward by
15957 AMOUNT bytes. */
15959 static rtx
15961 {
15966 }
15968 /* Return a new RTX holding the result of moving POINTER forward by the
15969 size of the mode it points to. */
15971 static rtx
15973 {
15975 }
15977 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
15978 MODE bytes. */
15980 static void
15982 machine_mode mode)
15983 {
15986 /* "Cast" the pointers to the correct mode. */
15989 /* Emit the memcpy. */
15992 /* Move the pointers forward. */
15995 }
15997 /* Expand movmem, as if from a __builtin_memcpy. Return true if
15998 we succeed, otherwise return false. */
16000 bool
16002 {
16006 rtx base;
16009 /* When optimizing for size, give a better estimate of the length of a
16010 memcpy call, but use the default otherwise. */
16013 /* We can't do anything smart if the amount to copy is not constant. */
16019 /* Try to keep the number of instructions low. For cases below 16 bytes we
16020 need to make at most two moves. For cases above 16 bytes it will be one
16021 move for each 16 byte chunk, then at most two additional moves. */
16031 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
16032 1-byte chunk. */
16034 {
16036 {
16039 }
16045 }
16047 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
16048 4-byte chunk, partially overlapping with the previously copied chunk. */
16050 {
16054 {
16060 }
16062 }
16064 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
16065 them, then (if applicable) an 8-byte chunk. */
16067 {
16069 {
16072 }
16073 else
16074 {
16077 }
16078 }
16080 /* Finish the final bytes of the copy. We can always do this in one
16081 instruction. We either copy the exact amount we need, or partially
16082 overlap with the previous chunk we copied and copy 8-bytes. */
16091 else
16092 {
16094 {
16098 }
16099 else
16100 {
16106 }
16107 }
16110 }
16112 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
16113 SImode stores. Handle the case when the constant has identical
16114 bottom and top halves. This is beneficial when the two stores can be
16115 merged into an STP and we avoid synthesising potentially expensive
16116 immediates twice. Return true if such a split is possible. */
16118 bool
16120 {
16129 unsigned int orig_cost
16131 unsigned int lo_cost
16134 /* We want to transform:
16135 MOV x1, 49370
16136 MOVK x1, 0x140, lsl 16
16137 MOVK x1, 0xc0da, lsl 32
16138 MOVK x1, 0x140, lsl 48
16139 STR x1, [x0]
16140 into:
16141 MOV w1, 49370
16142 MOVK w1, 0x140, lsl 16
16143 STP w1, w1, [x0]
16144 So we want to perform this only when we save two instructions
16145 or more. When optimizing for size, however, accept any code size
16146 savings we can. */
16161 /* Don't emit an explicit store pair as this may not be always profitable.
16162 Let the sched-fusion logic decide whether to merge them. */
16167 }
16169 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
16171 static unsigned HOST_WIDE_INT
16173 {
16175 }
16177 static rtx
16180 {
16184 insn_code icode;
16195 {
16223 }
16228 {
16231 }
16240 {
16243 }
16249 }
16251 static rtx
16254 {
16258 insn_code icode;
16270 {
16298 }
16303 {
16306 }
16314 {
16319 }
16330 {
16333 }
16339 }
16341 #undef TARGET_GEN_CCMP_FIRST
16342 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
16344 #undef TARGET_GEN_CCMP_NEXT
16345 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
16347 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
16348 instruction fusion of some sort. */
16350 static bool
16352 {
16354 }
16357 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
16358 should be kept together during scheduling. */
16360 static bool
16362 {
16363 rtx set_dest;
16366 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
16373 {
16374 /* We are trying to match:
16375 prev (mov) == (set (reg r0) (const_int imm16))
16376 curr (movk) == (set (zero_extract (reg r0)
16377 (const_int 16)
16378 (const_int 16))
16379 (const_int imm16_1)) */
16391 {
16393 }
16394 }
16397 {
16399 /* We're trying to match:
16400 prev (adrp) == (set (reg r1)
16401 (high (symbol_ref ("SYM"))))
16402 curr (add) == (set (reg r0)
16403 (lo_sum (reg r1)
16404 (symbol_ref ("SYM"))))
16405 Note that r0 need not necessarily be the same as r1, especially
16406 during pre-regalloc scheduling. */
16410 {
16418 }
16419 }
16422 {
16424 /* We're trying to match:
16425 prev (movk) == (set (zero_extract (reg r0)
16426 (const_int 16)
16427 (const_int 32))
16428 (const_int imm16_1))
16429 curr (movk) == (set (zero_extract (reg r0)
16430 (const_int 16)
16431 (const_int 48))
16432 (const_int imm16_2)) */
16448 }
16450 {
16451 /* We're trying to match:
16452 prev (adrp) == (set (reg r0)
16453 (high (symbol_ref ("SYM"))))
16454 curr (ldr) == (set (reg r1)
16455 (mem (lo_sum (reg r0)
16456 (symbol_ref ("SYM")))))
16457 or
16458 curr (ldr) == (set (reg r1)
16459 (zero_extend (mem
16460 (lo_sum (reg r0)
16461 (symbol_ref ("SYM")))))) */
16464 {
16477 }
16478 }
16486 {
16490 rtx cc_reg_1;
16495 && prev
16497 {
16498 /* FIXME: this misses some which is considered simple arthematic
16499 instructions for ThunderX. Simple shifts are missed here. */
16505 }
16506 }
16509 && curr_set
16512 {
16513 /* We're trying to match:
16514 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
16515 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
16516 (const_int 0))
16517 (label_ref ("SYM"))
16518 (pc)) */
16525 {
16526 /* Fuse ALU operations followed by conditional branch instruction. */
16528 {
16549 }
16550 }
16551 }
16554 }
16556 /* Return true iff the instruction fusion described by OP is enabled. */
16558 bool
16560 {
16562 }
16564 /* If MEM is in the form of [base+offset], extract the two parts
16565 of address and set to BASE and OFFSET, otherwise return false
16566 after clearing BASE and OFFSET. */
16568 bool
16570 {
16571 rtx addr;
16578 {
16582 }
16586 {
16590 }
16596 }
16598 /* Types for scheduling fusion. */
16599 enum sched_fusion_type
16600 {
16602 SCHED_FUSION_LD_SIGN_EXTEND,
16603 SCHED_FUSION_LD_ZERO_EXTEND,
16604 SCHED_FUSION_LD,
16605 SCHED_FUSION_ST,
16606 SCHED_FUSION_NUM
16607 };
16609 /* If INSN is a load or store of address in the form of [base+offset],
16610 extract the two parts and set to BASE and OFFSET. Return scheduling
16611 fusion type this INSN is. */
16613 static enum sched_fusion_type
16615 {
16633 {
16638 }
16640 {
16645 }
16650 {
16653 }
16654 else
16661 }
16663 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
16665 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
16666 and PRI are only calculated for these instructions. For other instruction,
16667 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
16668 type instruction fusion can be added by returning different priorities.
16670 It's important that irrelevant instructions get the largest FUSION_PRI. */
16672 static void
16675 {
16685 {
16689 }
16691 /* Set FUSION_PRI according to fusion type and base register. */
16694 /* Calculate PRI. */
16697 /* INSN with smaller offset goes first. */
16701 else
16706 }
16708 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
16709 Adjust priority of sha1h instructions so they are scheduled before
16710 other SHA1 instructions. */
16712 static int
16714 {
16718 {
16723 }
16726 }
16728 /* Given OPERANDS of consecutive load/store, check if we can merge
16729 them into ldp/stp. LOAD is true if they are load instructions.
16730 MODE is the mode of memory operands. */
16732 bool
16734 machine_mode mode)
16735 {
16741 {
16749 }
16750 else
16751 {
16756 }
16758 /* The mems cannot be volatile. */
16762 /* If we have SImode and slow unaligned ldp,
16763 check the alignment to be at least 8 byte. */
16767 && !optimize_size
16771 /* Check if the addresses are in the form of [base+offset]. */
16779 /* Check if the bases are same. */
16785 /* We should only be trying this for fixed-sized modes. There is no
16786 SVE LDP/STP instruction. */
16788 /* Check if the offsets are consecutive. */
16792 /* Check if the addresses are clobbered by load. */
16794 {
16798 /* In increasing order, the last load can clobber the address. */
16801 }
16805 else
16810 else
16813 /* Check if the registers are of same class. */
16818 }
16820 /* Given OPERANDS of consecutive load/store, check if we can merge
16821 them into ldp/stp by adjusting the offset. LOAD is true if they
16822 are load instructions. MODE is the mode of memory operands.
16824 Given below consecutive stores:
16826 str w1, [xb, 0x100]
16827 str w1, [xb, 0x104]
16828 str w1, [xb, 0x108]
16829 str w1, [xb, 0x10c]
16831 Though the offsets are out of the range supported by stp, we can
16832 still pair them after adjusting the offset, like:
16834 add scratch, xb, 0x100
16835 stp w1, w1, [scratch]
16836 stp w1, w1, [scratch, 0x8]
16838 The peephole patterns detecting this opportunity should guarantee
16839 the scratch register is avaliable. */
16841 bool
16843 scalar_mode mode)
16844 {
16851 {
16864 }
16865 else
16866 {
16875 }
16876 /* Skip if memory operand is by itslef valid for ldp/stp. */
16880 /* The mems cannot be volatile. */
16885 /* Check if the addresses are in the form of [base+offset]. */
16899 /* Check if the bases are same. */
16910 /* Check if the offsets are consecutive. */
16919 /* Check if the addresses are clobbered by load. */
16921 {
16927 /* In increasing order, the last load can clobber the address. */
16930 }
16932 /* If we have SImode and slow unaligned ldp,
16933 check the alignment to be at least 8 byte. */
16937 && !optimize_size
16943 else
16948 else
16953 else
16958 else
16961 /* Check if the registers are of same class. */
16966 }
16968 /* Given OPERANDS of consecutive load/store, this function pairs them
16969 into ldp/stp after adjusting the offset. It depends on the fact
16970 that addresses of load/store instructions are in increasing order.
16971 MODE is the mode of memory operands. CODE is the rtl operator
16972 which should be applied to all memory operands, it's SIGN_EXTEND,
16973 ZERO_EXTEND or UNKNOWN. */
16975 bool
16978 {
16984 {
16989 }
16990 else
16991 {
16997 }
17002 /* Adjust offset thus it can fit in ldp/stp instruction. */
17010 /* Further adjust to make sure all offsets are OK. */
17012 {
17015 }
17017 /* Make sure the adjustment can be done with ADD/SUB instructions. */
17022 {
17025 }
17027 /* Create new memory references. */
17031 /* Check if the adjusted address is OK for ldp/stp. */
17050 {
17055 }
17057 {
17062 }
17065 {
17070 }
17071 else
17072 {
17077 }
17079 /* Emit adjusting instruction. */
17081 /* Emit ldp/stp instructions. */
17089 }
17091 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
17092 it isn't worth branching around empty masked ops (including masked
17093 stores). */
17095 static bool
17097 {
17099 }
17101 /* Return 1 if pseudo register should be created and used to hold
17102 GOT address for PIC code. */
17104 bool
17106 {
17108 }
17110 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
17112 static int
17114 {
17116 {
17123 }
17126 }
17129 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
17130 return the log2 of that value. Otherwise return -1. */
17132 int
17134 {
17149 }
17151 /* If X is a vector of equal CONST_DOUBLE values and that value is
17152 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
17154 int
17156 {
17174 }
17176 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
17177 to float.
17179 __fp16 always promotes through this hook.
17180 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
17181 through the generic excess precision logic rather than here. */
17183 static tree
17185 {
17191 }
17193 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
17195 static bool
17197 optimization_type opt_type)
17198 {
17200 {
17206 }
17207 }
17209 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
17211 static unsigned int
17214 {
17215 /* Polynomial invariant 1 == (VG / 2) - 1. */
17220 }
17222 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
17223 if MODE is HFmode, and punt to the generic implementation otherwise. */
17225 static bool
17227 {
17231 }
17233 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
17234 if MODE is HFmode, and punt to the generic implementation otherwise. */
17236 static bool
17238 {
17242 }
17244 /* Set the value of FLT_EVAL_METHOD.
17245 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
17247 0: evaluate all operations and constants, whose semantic type has at
17248 most the range and precision of type float, to the range and
17249 precision of float; evaluate all other operations and constants to
17250 the range and precision of the semantic type;
17252 N, where _FloatN is a supported interchange floating type
17253 evaluate all operations and constants, whose semantic type has at
17254 most the range and precision of _FloatN type, to the range and
17255 precision of the _FloatN type; evaluate all other operations and
17256 constants to the range and precision of the semantic type;
17258 If we have the ARMv8.2-A extensions then we support _Float16 in native
17259 precision, so we should set this to 16. Otherwise, we support the type,
17260 but want to evaluate expressions in float precision, so set this to
17261 0. */
17263 static enum flt_eval_method
17265 {
17267 {
17270 /* We can calculate either in 16-bit range and precision or
17271 32-bit range and precision. Make that decision based on whether
17272 we have native support for the ARMv8.2-A 16-bit floating-point
17273 instructions or not. */
17275 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
17281 }
17283 }
17285 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
17286 scheduled for speculative execution. Reject the long-running division
17287 and square-root instructions. */
17289 static bool
17291 {
17293 {
17311 }
17312 }
17314 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
17316 static int
17318 {
17322 /* PR_REGS isn't a useful pressure class because many predicate pseudo
17323 registers need to go in PR_LO_REGS at some point during their
17324 lifetime. Splitting it into two halves has the effect of making
17325 all predicates count against PR_LO_REGS, so that we try whenever
17326 possible to restrict the number of live predicates to 8. This
17327 greatly reduces the amount of spilling in certain loops. */
17331 }
17333 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
17335 static bool
17338 {
17340 {
17344 /* Don't allow changes between SVE data modes and non-SVE modes.
17345 See the comment at the head of aarch64-sve.md for details. */
17349 /* Don't allow changes in element size: lane 0 of the new vector
17350 would not then be lane 0 of the old vector. See the comment
17351 above aarch64_maybe_expand_sve_subreg_move for a more detailed
17352 description.
17354 In the worst case, this forces a register to be spilled in
17355 one mode and reloaded in the other, which handles the
17356 endianness correctly. */
17359 }
17361 }
17363 /* Implement TARGET_EARLY_REMAT_MODES. */
17365 static void
17367 {
17368 /* SVE values are not normally live across a call, so it should be
17369 worth doing early rematerialization even in VL-specific mode. */
17371 {
17376 }
17377 }
17379 /* Target-specific selftests. */
17381 #if CHECKING_P
17385 /* Selftest for the RTL loader.
17386 Verify that the RTL loader copes with a dump from
17387 print_rtx_function. This is essentially just a test that class
17388 function_reader can handle a real dump, but it also verifies
17389 that lookup_reg_by_dump_name correctly handles hard regs.
17390 The presence of hard reg names in the dump means that the test is
17391 target-specific, hence it is in this file. */
17393 static void
17395 {
17407 /* Verify crtl->return_rtx. */
17411 }
17413 /* Run all target-specific selftests. */
17415 static void
17417 {
17419 }
17425 #undef TARGET_ADDRESS_COST
17426 #define TARGET_ADDRESS_COST aarch64_address_cost
17428 /* This hook will determines whether unnamed bitfields affect the alignment
17429 of the containing structure. The hook returns true if the structure
17430 should inherit the alignment requirements of an unnamed bitfield's
17431 type. */
17432 #undef TARGET_ALIGN_ANON_BITFIELD
17433 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
17435 #undef TARGET_ASM_ALIGNED_DI_OP
17438 #undef TARGET_ASM_ALIGNED_HI_OP
17441 #undef TARGET_ASM_ALIGNED_SI_OP
17444 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
17445 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
17446 hook_bool_const_tree_hwi_hwi_const_tree_true
17448 #undef TARGET_ASM_FILE_START
17449 #define TARGET_ASM_FILE_START aarch64_start_file
17451 #undef TARGET_ASM_OUTPUT_MI_THUNK
17452 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
17454 #undef TARGET_ASM_SELECT_RTX_SECTION
17455 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
17457 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
17458 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
17460 #undef TARGET_BUILD_BUILTIN_VA_LIST
17461 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
17463 #undef TARGET_CALLEE_COPIES
17464 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
17466 #undef TARGET_CAN_ELIMINATE
17467 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
17469 #undef TARGET_CAN_INLINE_P
17470 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
17472 #undef TARGET_CANNOT_FORCE_CONST_MEM
17473 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
17475 #undef TARGET_CASE_VALUES_THRESHOLD
17476 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
17478 #undef TARGET_CONDITIONAL_REGISTER_USAGE
17479 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
17481 /* Only the least significant bit is used for initialization guard
17482 variables. */
17483 #undef TARGET_CXX_GUARD_MASK_BIT
17484 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
17486 #undef TARGET_C_MODE_FOR_SUFFIX
17487 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
17489 #ifdef TARGET_BIG_ENDIAN_DEFAULT
17490 #undef TARGET_DEFAULT_TARGET_FLAGS
17491 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
17492 #endif
17494 #undef TARGET_CLASS_MAX_NREGS
17495 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
17497 #undef TARGET_BUILTIN_DECL
17498 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
17500 #undef TARGET_BUILTIN_RECIPROCAL
17501 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
17503 #undef TARGET_C_EXCESS_PRECISION
17504 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
17506 #undef TARGET_EXPAND_BUILTIN
17507 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
17509 #undef TARGET_EXPAND_BUILTIN_VA_START
17510 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
17512 #undef TARGET_FOLD_BUILTIN
17513 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
17515 #undef TARGET_FUNCTION_ARG
17516 #define TARGET_FUNCTION_ARG aarch64_function_arg
17518 #undef TARGET_FUNCTION_ARG_ADVANCE
17519 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
17521 #undef TARGET_FUNCTION_ARG_BOUNDARY
17522 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
17524 #undef TARGET_FUNCTION_ARG_PADDING
17525 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
17527 #undef TARGET_GET_RAW_RESULT_MODE
17528 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
17529 #undef TARGET_GET_RAW_ARG_MODE
17530 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
17532 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17533 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
17535 #undef TARGET_FUNCTION_VALUE
17536 #define TARGET_FUNCTION_VALUE aarch64_function_value
17538 #undef TARGET_FUNCTION_VALUE_REGNO_P
17539 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
17541 #undef TARGET_GIMPLE_FOLD_BUILTIN
17542 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
17544 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17545 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
17547 #undef TARGET_INIT_BUILTINS
17548 #define TARGET_INIT_BUILTINS aarch64_init_builtins
17550 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
17551 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
17552 aarch64_ira_change_pseudo_allocno_class
17554 #undef TARGET_LEGITIMATE_ADDRESS_P
17555 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
17557 #undef TARGET_LEGITIMATE_CONSTANT_P
17558 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
17560 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
17561 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
17562 aarch64_legitimize_address_displacement
17564 #undef TARGET_LIBGCC_CMP_RETURN_MODE
17565 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
17567 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
17568 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
17569 aarch64_libgcc_floating_mode_supported_p
17571 #undef TARGET_MANGLE_TYPE
17572 #define TARGET_MANGLE_TYPE aarch64_mangle_type
17574 #undef TARGET_MEMORY_MOVE_COST
17575 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
17577 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
17578 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
17580 #undef TARGET_MUST_PASS_IN_STACK
17581 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
17583 /* This target hook should return true if accesses to volatile bitfields
17584 should use the narrowest mode possible. It should return false if these
17585 accesses should use the bitfield container type. */
17586 #undef TARGET_NARROW_VOLATILE_BITFIELD
17587 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
17589 #undef TARGET_OPTION_OVERRIDE
17590 #define TARGET_OPTION_OVERRIDE aarch64_override_options
17592 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
17593 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
17594 aarch64_override_options_after_change
17596 #undef TARGET_OPTION_SAVE
17597 #define TARGET_OPTION_SAVE aarch64_option_save
17599 #undef TARGET_OPTION_RESTORE
17600 #define TARGET_OPTION_RESTORE aarch64_option_restore
17602 #undef TARGET_OPTION_PRINT
17603 #define TARGET_OPTION_PRINT aarch64_option_print
17605 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
17606 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
17608 #undef TARGET_SET_CURRENT_FUNCTION
17609 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
17611 #undef TARGET_PASS_BY_REFERENCE
17612 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
17614 #undef TARGET_PREFERRED_RELOAD_CLASS
17615 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
17617 #undef TARGET_SCHED_REASSOCIATION_WIDTH
17618 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
17620 #undef TARGET_PROMOTED_TYPE
17621 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
17623 #undef TARGET_SECONDARY_RELOAD
17624 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
17626 #undef TARGET_SHIFT_TRUNCATION_MASK
17627 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
17629 #undef TARGET_SETUP_INCOMING_VARARGS
17630 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
17632 #undef TARGET_STRUCT_VALUE_RTX
17633 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
17635 #undef TARGET_REGISTER_MOVE_COST
17636 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
17638 #undef TARGET_RETURN_IN_MEMORY
17639 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
17641 #undef TARGET_RETURN_IN_MSB
17642 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
17644 #undef TARGET_RTX_COSTS
17645 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
17647 #undef TARGET_SCALAR_MODE_SUPPORTED_P
17648 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
17650 #undef TARGET_SCHED_ISSUE_RATE
17651 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
17653 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17654 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17655 aarch64_sched_first_cycle_multipass_dfa_lookahead
17657 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
17658 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
17659 aarch64_first_cycle_multipass_dfa_lookahead_guard
17661 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
17662 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
17663 aarch64_get_separate_components
17665 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
17666 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
17667 aarch64_components_for_bb
17669 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
17670 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
17671 aarch64_disqualify_components
17673 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
17674 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
17675 aarch64_emit_prologue_components
17677 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
17678 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
17679 aarch64_emit_epilogue_components
17681 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
17682 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
17683 aarch64_set_handled_components
17685 #undef TARGET_TRAMPOLINE_INIT
17686 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
17688 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
17689 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
17691 #undef TARGET_VECTOR_MODE_SUPPORTED_P
17692 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
17694 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
17695 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
17696 aarch64_builtin_support_vector_misalignment
17698 #undef TARGET_ARRAY_MODE
17699 #define TARGET_ARRAY_MODE aarch64_array_mode
17701 #undef TARGET_ARRAY_MODE_SUPPORTED_P
17702 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
17704 #undef TARGET_VECTORIZE_ADD_STMT_COST
17705 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
17707 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
17708 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
17709 aarch64_builtin_vectorization_cost
17711 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
17712 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
17714 #undef TARGET_VECTORIZE_BUILTINS
17715 #define TARGET_VECTORIZE_BUILTINS
17717 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
17718 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
17719 aarch64_builtin_vectorized_function
17721 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
17722 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
17723 aarch64_autovectorize_vector_sizes
17725 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
17726 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
17727 aarch64_atomic_assign_expand_fenv
17729 /* Section anchor support. */
17731 #undef TARGET_MIN_ANCHOR_OFFSET
17732 #define TARGET_MIN_ANCHOR_OFFSET -256
17734 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
17735 byte offset; we can do much more for larger data types, but have no way
17736 to determine the size of the access. We assume accesses are aligned. */
17737 #undef TARGET_MAX_ANCHOR_OFFSET
17738 #define TARGET_MAX_ANCHOR_OFFSET 4095
17740 #undef TARGET_VECTOR_ALIGNMENT
17741 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
17743 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
17744 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
17745 aarch64_vectorize_preferred_vector_alignment
17746 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
17747 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
17748 aarch64_simd_vector_alignment_reachable
17750 /* vec_perm support. */
17752 #undef TARGET_VECTORIZE_VEC_PERM_CONST
17753 #define TARGET_VECTORIZE_VEC_PERM_CONST \
17754 aarch64_vectorize_vec_perm_const
17756 #undef TARGET_VECTORIZE_GET_MASK_MODE
17757 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
17758 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
17759 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
17760 aarch64_empty_mask_is_expensive
17762 #undef TARGET_INIT_LIBFUNCS
17763 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
17765 #undef TARGET_FIXED_CONDITION_CODE_REGS
17766 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
17768 #undef TARGET_FLAGS_REGNUM
17769 #define TARGET_FLAGS_REGNUM CC_REGNUM
17771 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
17772 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
17774 #undef TARGET_ASAN_SHADOW_OFFSET
17775 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
17777 #undef TARGET_LEGITIMIZE_ADDRESS
17778 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
17780 #undef TARGET_SCHED_CAN_SPECULATE_INSN
17781 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
17783 #undef TARGET_CAN_USE_DOLOOP_P
17784 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
17786 #undef TARGET_SCHED_ADJUST_PRIORITY
17787 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
17789 #undef TARGET_SCHED_MACRO_FUSION_P
17790 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
17792 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
17793 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
17795 #undef TARGET_SCHED_FUSION_PRIORITY
17796 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
17798 #undef TARGET_UNSPEC_MAY_TRAP_P
17799 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
17801 #undef TARGET_USE_PSEUDO_PIC_REG
17802 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
17804 #undef TARGET_PRINT_OPERAND
17805 #define TARGET_PRINT_OPERAND aarch64_print_operand
17807 #undef TARGET_PRINT_OPERAND_ADDRESS
17808 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
17810 #undef TARGET_OPTAB_SUPPORTED_P
17811 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
17813 #undef TARGET_OMIT_STRUCT_RETURN_REG
17814 #define TARGET_OMIT_STRUCT_RETURN_REG true
17816 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
17817 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
17818 aarch64_dwarf_poly_indeterminate_value
17820 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
17821 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
17822 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
17824 #undef TARGET_HARD_REGNO_NREGS
17825 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
17826 #undef TARGET_HARD_REGNO_MODE_OK
17827 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
17829 #undef TARGET_MODES_TIEABLE_P
17830 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
17832 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
17833 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
17834 aarch64_hard_regno_call_part_clobbered
17836 #undef TARGET_CONSTANT_ALIGNMENT
17837 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
17839 #undef TARGET_COMPUTE_PRESSURE_CLASSES
17840 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
17842 #undef TARGET_CAN_CHANGE_MODE_CLASS
17843 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
17845 #undef TARGET_SELECT_EARLY_REMAT_MODES
17846 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
17848 #if CHECKING_P
17849 #undef TARGET_RUN_TARGET_SELFTESTS
17850 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests