?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Turn CANNOT_CHANGE_MODE_CLASS into a hook
[official-gcc.git] / gcc / config / s390 / s390.h
blob0f6ea874983e08935a23d0fe4846b282cf20e6f6
1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999-2017 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com).
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #ifndef _S390_H
24 #define _S390_H
25
26 /* Optional architectural facilities supported by the processor. */
27
28 enum processor_flags
29 {
30 PF_IEEE_FLOAT = 1,
31 PF_ZARCH = 2,
32 PF_LONG_DISPLACEMENT = 4,
33 PF_EXTIMM = 8,
34 PF_DFP = 16,
35 PF_Z10 = 32,
36 PF_Z196 = 64,
37 PF_ZEC12 = 128,
38 PF_TX = 256,
39 PF_Z13 = 512,
40 PF_VX = 1024,
41 PF_ARCH12 = 2048,
42 PF_VXE = 4096
43 };
44
45 /* This is necessary to avoid a warning about comparing different enum
46 types. */
47 #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_2964_Z13 ? PROCESSOR_2964_Z13 : s390_tune ))
48
49 /* These flags indicate that the generated code should run on a cpu
50 providing the respective hardware facility regardless of the
51 current cpu mode (ESA or z/Architecture). */
52
53 #define TARGET_CPU_IEEE_FLOAT \
54 (s390_arch_flags & PF_IEEE_FLOAT)
55 #define TARGET_CPU_IEEE_FLOAT_P(opts) \
56 (opts->x_s390_arch_flags & PF_IEEE_FLOAT)
57 #define TARGET_CPU_ZARCH \
58 (s390_arch_flags & PF_ZARCH)
59 #define TARGET_CPU_ZARCH_P(opts) \
60 (opts->x_s390_arch_flags & PF_ZARCH)
61 #define TARGET_CPU_LONG_DISPLACEMENT \
62 (s390_arch_flags & PF_LONG_DISPLACEMENT)
63 #define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \
64 (opts->x_s390_arch_flags & PF_LONG_DISPLACEMENT)
65 #define TARGET_CPU_EXTIMM \
66 (s390_arch_flags & PF_EXTIMM)
67 #define TARGET_CPU_EXTIMM_P(opts) \
68 (opts->x_s390_arch_flags & PF_EXTIMM)
69 #define TARGET_CPU_DFP \
70 (s390_arch_flags & PF_DFP)
71 #define TARGET_CPU_DFP_P(opts) \
72 (opts->x_s390_arch_flags & PF_DFP)
73 #define TARGET_CPU_Z10 \
74 (s390_arch_flags & PF_Z10)
75 #define TARGET_CPU_Z10_P(opts) \
76 (opts->x_s390_arch_flags & PF_Z10)
77 #define TARGET_CPU_Z196 \
78 (s390_arch_flags & PF_Z196)
79 #define TARGET_CPU_Z196_P(opts) \
80 (opts->x_s390_arch_flags & PF_Z196)
81 #define TARGET_CPU_ZEC12 \
82 (s390_arch_flags & PF_ZEC12)
83 #define TARGET_CPU_ZEC12_P(opts) \
84 (opts->x_s390_arch_flags & PF_ZEC12)
85 #define TARGET_CPU_HTM \
86 (s390_arch_flags & PF_TX)
87 #define TARGET_CPU_HTM_P(opts) \
88 (opts->x_s390_arch_flags & PF_TX)
89 #define TARGET_CPU_Z13 \
90 (s390_arch_flags & PF_Z13)
91 #define TARGET_CPU_Z13_P(opts) \
92 (opts->x_s390_arch_flags & PF_Z13)
93 #define TARGET_CPU_VX \
94 (s390_arch_flags & PF_VX)
95 #define TARGET_CPU_VX_P(opts) \
96 (opts->x_s390_arch_flags & PF_VX)
97 #define TARGET_CPU_ARCH12 \
98 (s390_arch_flags & PF_ARCH12)
99 #define TARGET_CPU_ARCH12_P(opts) \
100 (opts->x_s390_arch_flags & PF_ARCH12)
101 #define TARGET_CPU_VXE \
102 (s390_arch_flags & PF_VXE)
103 #define TARGET_CPU_VXE_P(opts) \
104 (opts->x_s390_arch_flags & PF_VXE)
105
106 #define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts))
107
108 /* These flags indicate that the generated code should run on a cpu
109 providing the respective hardware facility when run in
110 z/Architecture mode. */
111
112 #define TARGET_LONG_DISPLACEMENT \
113 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
114 #define TARGET_LONG_DISPLACEMENT_P(opts) \
115 (TARGET_ZARCH_P (opts->x_target_flags) \
116 && TARGET_CPU_LONG_DISPLACEMENT_P (opts))
117 #define TARGET_EXTIMM \
118 (TARGET_ZARCH && TARGET_CPU_EXTIMM)
119 #define TARGET_EXTIMM_P(opts) \
120 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts))
121 #define TARGET_DFP \
122 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
123 #define TARGET_DFP_P(opts) \
124 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \
125 && TARGET_HARD_FLOAT_P (opts->x_target_flags))
126 #define TARGET_Z10 \
127 (TARGET_ZARCH && TARGET_CPU_Z10)
128 #define TARGET_Z10_P(opts) \
129 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts))
130 #define TARGET_Z196 \
131 (TARGET_ZARCH && TARGET_CPU_Z196)
132 #define TARGET_Z196_P(opts) \
133 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts))
134 #define TARGET_ZEC12 \
135 (TARGET_ZARCH && TARGET_CPU_ZEC12)
136 #define TARGET_ZEC12_P(opts) \
137 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts))
138 #define TARGET_HTM (TARGET_OPT_HTM)
139 #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags))
140 #define TARGET_Z13 \
141 (TARGET_ZARCH && TARGET_CPU_Z13)
142 #define TARGET_Z13_P(opts) \
143 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts))
144 #define TARGET_VX \
145 (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT)
146 #define TARGET_VX_P(opts) \
147 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \
148 && TARGET_OPT_VX_P (opts->x_target_flags) \
149 && TARGET_HARD_FLOAT_P (opts->x_target_flags))
150 #define TARGET_ARCH12 (TARGET_ZARCH && TARGET_CPU_ARCH12)
151 #define TARGET_ARCH12_P(opts) \
152 (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ARCH12_P (opts))
153 #define TARGET_VXE \
154 (TARGET_VX && TARGET_CPU_VXE)
155 #define TARGET_VXE_P(opts) \
156 (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts))
157
158 #ifdef HAVE_AS_MACHINE_MACHINEMODE
159 #define S390_USE_TARGET_ATTRIBUTE 1
160 #else
161 #define S390_USE_TARGET_ATTRIBUTE 0
162 #endif
163
164 #ifdef HAVE_AS_ARCHITECTURE_MODIFIERS
165 #define S390_USE_ARCHITECTURE_MODIFIERS 1
166 #else
167 #define S390_USE_ARCHITECTURE_MODIFIERS 0
168 #endif
169
170 #if S390_USE_TARGET_ATTRIBUTE
171 /* For switching between functions with different target attributes. */
172 #define SWITCHABLE_TARGET 1
173 #endif
174
175 #define TARGET_SUPPORTS_WIDE_INT 1
176
177 /* Use the ABI introduced with IBM z13:
178 - pass vector arguments <= 16 bytes in VRs
179 - align *all* vector types to 8 bytes */
180 #define TARGET_VX_ABI TARGET_VX
181
182 #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196)
183
184 /* Run-time target specification. */
185
186 /* Defaults for option flags defined only on some subtargets. */
187 #ifndef TARGET_TPF_PROFILING
188 #define TARGET_TPF_PROFILING 0
189 #endif
190
191 /* This will be overridden by OS headers. */
192 #define TARGET_TPF 0
193
194 /* Target CPU builtins. */
195 #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile)
196
197 #ifdef DEFAULT_TARGET_64BIT
198 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \
199 | MASK_OPT_HTM | MASK_OPT_VX)
200 #else
201 #define TARGET_DEFAULT 0
202 #endif
203
204 /* Support for configure-time defaults. */
205 #define OPTION_DEFAULT_SPECS \
206 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \
207 { "arch", "%{!march=*:-march=%(VALUE)}" }, \
208 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
209
210 #ifdef __s390__
211 extern const char *s390_host_detect_local_cpu (int argc, const char **argv);
212 # define EXTRA_SPEC_FUNCTIONS \
213 { "local_cpu_detect", s390_host_detect_local_cpu },
214
215 #define MARCH_MTUNE_NATIVE_SPECS \
216 "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \
217 "%{march=native:%<march=native" \
218 " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}"
219 #else
220 # define MARCH_MTUNE_NATIVE_SPECS ""
221 #endif
222
223 #ifdef DEFAULT_TARGET_64BIT
224 #define S390_TARGET_BITS_STRING "64"
225 #else
226 #define S390_TARGET_BITS_STRING "31"
227 #endif
228
229 /* Defaulting rules. */
230 #define DRIVER_SELF_SPECS \
231 MARCH_MTUNE_NATIVE_SPECS, \
232 "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \
233 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
234 "%{!march=*:-march=z900}"
235
236 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */
237 #define S390_TDC_POSITIVE_ZERO (1 << 11)
238 #define S390_TDC_NEGATIVE_ZERO (1 << 10)
239 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9)
240 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8)
241 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7)
242 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6)
243 #define S390_TDC_POSITIVE_INFINITY (1 << 5)
244 #define S390_TDC_NEGATIVE_INFINITY (1 << 4)
245 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3)
246 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2)
247 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1)
248 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0)
249
250 /* The following values are different for DFP. */
251 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
252 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
253 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7)
254 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6)
255
256 /* For signbit, the BFP-DFP-difference makes no difference. */
257 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
258 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
259 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
260 | S390_TDC_NEGATIVE_INFINITY \
261 | S390_TDC_NEGATIVE_QUIET_NAN \
262 | S390_TDC_NEGATIVE_SIGNALING_NAN )
263
264 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
265 | S390_TDC_NEGATIVE_INFINITY )
266
267 /* Target machine storage layout. */
268
269 /* Everything is big-endian. */
270 #define BITS_BIG_ENDIAN 1
271 #define BYTES_BIG_ENDIAN 1
272 #define WORDS_BIG_ENDIAN 1
273
274 #define STACK_SIZE_MODE (Pmode)
275
276 #ifndef IN_LIBGCC2
277
278 /* Width of a word, in units (bytes). */
279 #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
280
281 /* Width of a pointer. To be used instead of UNITS_PER_WORD in
282 ABI-relevant contexts. This always matches
283 GET_MODE_SIZE (Pmode). */
284 #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
285 #define MIN_UNITS_PER_WORD 4
286 #define MAX_BITS_PER_WORD 64
287 #else
288
289 /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
290 the library should export TImode functions or not. Thus, we have
291 to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */
292 #ifdef __s390x__
293 #define UNITS_PER_WORD 8
294 #else
295 #define UNITS_PER_WORD 4
296 #endif
297 #endif
298
299 /* Width of a pointer, in bits. */
300 #define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
301
302 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
303 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
304
305 /* Boundary (in *bits*) on which stack pointer should be aligned. */
306 #define STACK_BOUNDARY 64
307
308 /* Allocation boundary (in *bits*) for the code of a function. */
309 #define FUNCTION_BOUNDARY 64
310
311 /* There is no point aligning anything to a rounder boundary than this. */
312 #define BIGGEST_ALIGNMENT 64
313
314 /* Alignment of field after `int : 0' in a structure. */
315 #define EMPTY_FIELD_BOUNDARY 32
316
317 /* Alignment on even addresses for LARL instruction. */
318 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
319 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
320
321 /* Alignment is not required by the hardware. */
322 #define STRICT_ALIGNMENT 0
323
324 /* Mode of stack savearea.
325 FUNCTION is VOIDmode because calling convention maintains SP.
326 BLOCK needs Pmode for SP.
327 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
328 #define STACK_SAVEAREA_MODE(LEVEL) \
329 ((LEVEL) == SAVE_FUNCTION ? VOIDmode \
330 : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
331
332
333 /* Type layout. */
334
335 /* Sizes in bits of the source language data types. */
336 #define SHORT_TYPE_SIZE 16
337 #define INT_TYPE_SIZE 32
338 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
339 #define LONG_LONG_TYPE_SIZE 64
340 #define FLOAT_TYPE_SIZE 32
341 #define DOUBLE_TYPE_SIZE 64
342 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
343
344 /* Work around target_flags dependency in ada/targtyps.c. */
345 #define WIDEST_HARDWARE_FP_SIZE 64
346
347 /* We use "unsigned char" as default. */
348 #define DEFAULT_SIGNED_CHAR 0
349
350
351 /* Register usage. */
352
353 /* We have 16 general purpose registers (registers 0-15),
354 and 16 floating point registers (registers 16-31).
355 (On non-IEEE machines, we have only 4 fp registers.)
356
357 Amongst the general purpose registers, some are used
358 for specific purposes:
359 GPR 11: Hard frame pointer (if needed)
360 GPR 12: Global offset table pointer (if needed)
361 GPR 13: Literal pool base register
362 GPR 14: Return address register
363 GPR 15: Stack pointer
364
365 Registers 32-35 are 'fake' hard registers that do not
366 correspond to actual hardware:
367 Reg 32: Argument pointer
368 Reg 33: Condition code
369 Reg 34: Frame pointer
370 Reg 35: Return address pointer
371
372 Registers 36 and 37 are mapped to access registers
373 0 and 1, used to implement thread-local storage.
374
375 Reg 38-53: Vector registers v16-v31 */
376
377 #define FIRST_PSEUDO_REGISTER 54
378
379 /* Standard register usage. */
380 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
381 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
382 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32)
383 #define CC_REGNO_P(N) ((N) == 33)
384 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35)
385 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37)
386 #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53)
387 #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N))
388
389 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
390 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
391 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
392 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
393 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
394 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
395 #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X)))
396 #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X)))
397
398 /* Set up fixed registers and calling convention:
399
400 GPRs 0-5 are always call-clobbered,
401 GPRs 6-15 are always call-saved.
402 GPR 12 is fixed if used as GOT pointer.
403 GPR 13 is always fixed (as literal pool pointer).
404 GPR 14 is always fixed on S/390 machines (as return address).
405 GPR 15 is always fixed (as stack pointer).
406 The 'fake' hard registers are call-clobbered and fixed.
407 The access registers are call-saved and fixed.
408
409 On 31-bit, FPRs 18-19 are call-clobbered;
410 on 64-bit, FPRs 24-31 are call-clobbered.
411 The remaining FPRs are call-saved.
412
413 All non-FP vector registers are call-clobbered v16-v31. */
414
415 #define FIXED_REGISTERS \
416 { 0, 0, 0, 0, \
417 0, 0, 0, 0, \
418 0, 0, 0, 0, \
419 0, 1, 1, 1, \
420 0, 0, 0, 0, \
421 0, 0, 0, 0, \
422 0, 0, 0, 0, \
423 0, 0, 0, 0, \
424 1, 1, 1, 1, \
425 1, 1, \
426 0, 0, 0, 0, \
427 0, 0, 0, 0, \
428 0, 0, 0, 0, \
429 0, 0, 0, 0 }
430
431 #define CALL_USED_REGISTERS \
432 { 1, 1, 1, 1, \
433 1, 1, 0, 0, \
434 0, 0, 0, 0, \
435 0, 1, 1, 1, \
436 1, 1, 1, 1, \
437 1, 1, 1, 1, \
438 1, 1, 1, 1, \
439 1, 1, 1, 1, \
440 1, 1, 1, 1, \
441 1, 1, \
442 1, 1, 1, 1, \
443 1, 1, 1, 1, \
444 1, 1, 1, 1, \
445 1, 1, 1, 1 }
446
447 #define CALL_REALLY_USED_REGISTERS \
448 { 1, 1, 1, 1, /* r0 - r15 */ \
449 1, 1, 0, 0, \
450 0, 0, 0, 0, \
451 0, 0, 0, 0, \
452 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \
453 1, 1, 1, 1, \
454 1, 1, 1, 1, \
455 1, 1, 1, 1, \
456 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \
457 0, 0, /* a0 (36), a1 (37) */ \
458 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \
459 1, 1, 1, 1, \
460 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \
461 1, 1, 1, 1 }
462
463 /* Preferred register allocation order. */
464 #define REG_ALLOC_ORDER \
465 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \
466 16, 17, 18, 19, 20, 21, 22, 23, \
467 24, 25, 26, 27, 28, 29, 30, 31, \
468 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \
469 15, 32, 33, 34, 35, 36, 37 }
470
471
472 #define HARD_REGNO_RENAME_OK(FROM, TO) \
473 s390_hard_regno_rename_ok ((FROM), (TO))
474
475 /* Maximum number of registers to represent a value of mode MODE
476 in a register of class CLASS. */
477 #define CLASS_MAX_NREGS(CLASS, MODE) \
478 s390_class_max_nregs ((CLASS), (MODE))
479
480 /* We can reverse a CC mode safely if we know whether it comes from a
481 floating point compare or not. With the vector modes it is encoded
482 as part of the mode.
483 FIXME: It might make sense to do this for other cc modes as well. */
484 #define REVERSIBLE_CC_MODE(MODE) \
485 ((MODE) == CCVIALLmode || (MODE) == CCVIANYmode \
486 || (MODE) == CCVFALLmode || (MODE) == CCVFANYmode)
487
488 /* Given a condition code and a mode, return the inverse condition. */
489 #define REVERSE_CONDITION(CODE, MODE) s390_reverse_condition (MODE, CODE)
490
491
492 /* Register classes. */
493
494 /* We use the following register classes:
495 GENERAL_REGS All general purpose registers
496 ADDR_REGS All general purpose registers except %r0
497 (These registers can be used in address generation)
498 FP_REGS All floating point registers
499 CC_REGS The condition code register
500 ACCESS_REGS The access registers
501
502 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
503 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
504 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS
505 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS
506
507 NO_REGS No registers
508 ALL_REGS All registers
509
510 Note that the 'fake' frame pointer and argument pointer registers
511 are included amongst the address registers here. */
512
513 enum reg_class
514 {
515 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
516 ADDR_CC_REGS, GENERAL_CC_REGS,
517 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
518 VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS,
519 ALL_REGS, LIM_REG_CLASSES
520 };
521 #define N_REG_CLASSES (int) LIM_REG_CLASSES
522
523 #define REG_CLASS_NAMES \
524 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \
525 "ADDR_CC_REGS", "GENERAL_CC_REGS", \
526 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \
527 "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \
528 "ALL_REGS" }
529
530 /* Class -> register mapping. */
531 #define REG_CLASS_CONTENTS \
532 { \
533 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
534 { 0x00000000, 0x00000002 }, /* CC_REGS */ \
535 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \
536 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \
537 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \
538 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \
539 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \
540 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
541 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \
542 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \
543 { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \
544 { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \
545 { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \
546 { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \
547 }
548
549 /* In some case register allocation order is not enough for IRA to
550 generate a good code. The following macro (if defined) increases
551 cost of REGNO for a pseudo approximately by pseudo usage frequency
552 multiplied by the macro value.
553
554 We avoid usage of BASE_REGNUM by nonzero macro value because the
555 reload can decide not to use the hard register because some
556 constant was forced to be in memory. */
557 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \
558 ((regno) != BASE_REGNUM ? 0.0 : 0.5)
559
560 /* Register -> class mapping. */
561 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
562 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
563
564 /* ADDR_REGS can be used as base or index register. */
565 #define INDEX_REG_CLASS ADDR_REGS
566 #define BASE_REG_CLASS ADDR_REGS
567
568 /* Check whether REGNO is a hard register of the suitable class
569 or a pseudo register currently allocated to one such. */
570 #define REGNO_OK_FOR_INDEX_P(REGNO) \
571 (((REGNO) < FIRST_PSEUDO_REGISTER \
572 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
573 || ADDR_REGNO_P (reg_renumber[REGNO]))
574 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
575
576
577 /* Stack layout and calling conventions. */
578
579 /* Our stack grows from higher to lower addresses. However, local variables
580 are accessed by positive offsets, and function arguments are stored at
581 increasing addresses. */
582 #define STACK_GROWS_DOWNWARD 1
583 #define FRAME_GROWS_DOWNWARD 1
584 /* #undef ARGS_GROW_DOWNWARD */
585
586 /* The basic stack layout looks like this: the stack pointer points
587 to the register save area for called functions. Above that area
588 is the location to place outgoing arguments. Above those follow
589 dynamic allocations (alloca), and finally the local variables. */
590
591 /* Offset from stack-pointer to first location of outgoing args. */
592 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
593
594 /* Offset within stack frame to start allocating local variables at. */
595 #define STARTING_FRAME_OFFSET 0
596
597 /* Offset from the stack pointer register to an item dynamically
598 allocated on the stack, e.g., by `alloca'. */
599 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
600 (STACK_POINTER_OFFSET + crtl->outgoing_args_size)
601
602 /* Offset of first parameter from the argument pointer register value.
603 We have a fake argument pointer register that points directly to
604 the argument area. */
605 #define FIRST_PARM_OFFSET(FNDECL) 0
606
607 /* Defining this macro makes __builtin_frame_address(0) and
608 __builtin_return_address(0) work with -fomit-frame-pointer. */
609 #define INITIAL_FRAME_ADDRESS_RTX \
610 (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET))
611
612 /* The return address of the current frame is retrieved
613 from the initial value of register RETURN_REGNUM.
614 For frames farther back, we use the stack slot where
615 the corresponding RETURN_REGNUM register was saved. */
616 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
617 (TARGET_PACKED_STACK ? \
618 plus_constant (Pmode, (FRAME), \
619 STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
620
621 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
622 builtin_frame_address. Otherwise arg pointer -
623 STACK_POINTER_OFFSET would be returned for
624 __builtin_frame_address(0) what might result in an address pointing
625 somewhere into the middle of the local variables since the packed
626 stack layout generally does not need all the bytes in the register
627 save area. */
628 #define FRAME_ADDR_RTX(FRAME) \
629 DYNAMIC_CHAIN_ADDRESS ((FRAME))
630
631 #define RETURN_ADDR_RTX(COUNT, FRAME) \
632 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
633
634 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
635 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
636
637
638 /* Exception handling. */
639
640 /* Describe calling conventions for DWARF-2 exception handling. */
641 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
642 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
643 #define DWARF_FRAME_RETURN_COLUMN 14
644
645 /* Describe how we implement __builtin_eh_return. */
646 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
647 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
648
649 /* Select a format to encode pointers in exception handling data. */
650 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
651 (flag_pic \
652 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
653 : DW_EH_PE_absptr)
654
655 /* Register save slot alignment. */
656 #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
657
658 /* Let the assembler generate debug line info. */
659 #define DWARF2_ASM_LINE_DEBUG_INFO 1
660
661 /* Define the dwarf register mapping.
662 v16-v31 -> 68-83
663 rX -> X otherwise */
664 #define DBX_REGISTER_NUMBER(regno) \
665 (((regno) >= 38 && (regno) <= 53) ? (regno) + 30 : (regno))
666
667 /* Frame registers. */
668
669 #define STACK_POINTER_REGNUM 15
670 #define FRAME_POINTER_REGNUM 34
671 #define HARD_FRAME_POINTER_REGNUM 11
672 #define ARG_POINTER_REGNUM 32
673 #define RETURN_ADDRESS_POINTER_REGNUM 35
674
675 /* The static chain must be call-clobbered, but not used for
676 function argument passing. As register 1 is clobbered by
677 the trampoline code, we only have one option. */
678 #define STATIC_CHAIN_REGNUM 0
679
680 /* Number of hardware registers that go into the DWARF-2 unwind info.
681 To avoid ABI incompatibility, this number must not change even as
682 'fake' hard registers are added or removed. */
683 #define DWARF_FRAME_REGISTERS 34
684
685
686 /* Frame pointer and argument pointer elimination. */
687
688 #define ELIMINABLE_REGS \
689 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
690 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
691 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
692 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
693 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
694 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
695 { BASE_REGNUM, BASE_REGNUM }}
696
697 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
698 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
699
700
701 /* Stack arguments. */
702
703 /* We need current_function_outgoing_args to be valid. */
704 #define ACCUMULATE_OUTGOING_ARGS 1
705
706
707 /* Register arguments. */
708
709 typedef struct s390_arg_structure
710 {
711 int gprs; /* gpr so far */
712 int fprs; /* fpr so far */
713 int vrs; /* vr so far */
714 }
715 CUMULATIVE_ARGS;
716
717 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
718 ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0)
719
720 #define FIRST_VEC_ARG_REGNO 46
721 #define LAST_VEC_ARG_REGNO 53
722
723 /* Arguments can be placed in general registers 2 to 6, or in floating
724 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64
725 bit. */
726 #define FUNCTION_ARG_REGNO_P(N) \
727 (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \
728 || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \
729 || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO)))
730
731
732 /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */
733 #define FUNCTION_VALUE_REGNO_P(N) \
734 ((N) == 2 || (N) == 16 \
735 || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO))
736
737
738 /* Function entry and exit. */
739
740 /* When returning from a function, the stack pointer does not matter. */
741 #define EXIT_IGNORE_STACK 1
742
743
744 /* Profiling. */
745
746 #define FUNCTION_PROFILER(FILE, LABELNO) \
747 s390_function_profiler ((FILE), ((LABELNO)))
748
749 #define PROFILE_BEFORE_PROLOGUE 1
750
751
752 /* Trampolines for nested functions. */
753
754 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16)
755 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD
756
757 /* Addressing modes, and classification of registers for them. */
758
759 /* Recognize any constant value that is a valid address. */
760 #define CONSTANT_ADDRESS_P(X) 0
761
762 /* Maximum number of registers that can appear in a valid memory address. */
763 #define MAX_REGS_PER_ADDRESS 2
764
765 /* This definition replaces the formerly used 'm' constraint with a
766 different constraint letter in order to avoid changing semantics of
767 the 'm' constraint when accepting new address formats in
768 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here
769 must not be used in insn definitions or inline assemblies. */
770 #define TARGET_MEM_CONSTRAINT 'e'
771
772 /* Try a machine-dependent way of reloading an illegitimate address
773 operand. If we find one, push the reload and jump to WIN. This
774 macro is used in only one place: `find_reloads_address' in reload.c. */
775 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
776 do { \
777 rtx new_rtx = legitimize_reload_address ((AD), (MODE), \
778 (OPNUM), (int)(TYPE)); \
779 if (new_rtx) \
780 { \
781 (AD) = new_rtx; \
782 goto WIN; \
783 } \
784 } while (0)
785
786 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
787 #define SYMBOLIC_CONST(X) \
788 (GET_CODE (X) == SYMBOL_REF \
789 || GET_CODE (X) == LABEL_REF \
790 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
791
792 #define TLS_SYMBOLIC_CONST(X) \
793 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
794 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
795
796
797 /* Condition codes. */
798
799 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
800 return the mode to be used for the comparison. */
801 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
802
803 /* Relative costs of operations. */
804
805 /* A C expression for the cost of a branch instruction. A value of 1
806 is the default; other values are interpreted relative to that. */
807 #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost
808
809 /* Nonzero if access to memory by bytes is slow and undesirable. */
810 #define SLOW_BYTE_ACCESS 1
811
812 /* An integer expression for the size in bits of the largest integer machine
813 mode that should actually be used. We allow pairs of registers. */
814 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
815
816 /* The maximum number of bytes that a single instruction can move quickly
817 between memory and registers or between two memory locations. */
818 #define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
819 #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
820 #define MAX_MOVE_MAX 16
821
822 /* Don't perform CSE on function addresses. */
823 #define NO_FUNCTION_CSE 1
824
825 /* This value is used in tree-sra to decide whether it might benefical
826 to split a struct move into several word-size moves. For S/390
827 only small values make sense here since struct moves are relatively
828 cheap thanks to mvc so the small default value chosen for archs
829 with memmove patterns should be ok. But this value is multiplied
830 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
831 here to compensate for that factor since mvc costs exactly the same
832 on 31 and 64 bit. */
833 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4)
834
835
836 /* Sections. */
837
838 /* Output before read-only data. */
839 #define TEXT_SECTION_ASM_OP ".text"
840
841 /* Output before writable (initialized) data. */
842 #define DATA_SECTION_ASM_OP ".data"
843
844 /* Output before writable (uninitialized) data. */
845 #define BSS_SECTION_ASM_OP ".bss"
846
847 /* S/390 constant pool breaks the devices in crtstuff.c to control section
848 in where code resides. We have to write it as asm code. */
849 #ifndef __s390x__
850 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
851 asm (SECTION_OP "\n\
852 bras\t%r2,1f\n\
853 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
854 1: l\t%r3,0(%r2)\n\
855 bas\t%r14,0(%r3,%r2)\n\
856 .previous");
857 #endif
858
859
860 /* Position independent code. */
861
862 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
863
864 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
865
866 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE
867 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1
868 #endif
869
870
871 /* Assembler file format. */
872
873 /* Character to start a comment. */
874 #define ASM_COMMENT_START "#"
875
876 /* Declare an uninitialized external linkage data object. */
877 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
878 asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
879
880 /* Globalizing directive for a label. */
881 #define GLOBAL_ASM_OP ".globl "
882
883 /* Advance the location counter to a multiple of 2**LOG bytes. */
884 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
885 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
886
887 /* Advance the location counter by SIZE bytes. */
888 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
889 fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
890
891 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
892 #define LOCAL_LABEL_PREFIX "."
893
894 #define LABEL_ALIGN(LABEL) \
895 s390_label_align ((LABEL))
896
897 /* How to refer to registers in assembler output. This sequence is
898 indexed by compiler's hard-register-number (see above). */
899 #define REGISTER_NAMES \
900 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
901 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
902 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
903 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
904 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \
905 "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \
906 "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \
907 }
908
909 #define ADDITIONAL_REGISTER_NAMES \
910 { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \
911 { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \
912 { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \
913 { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } };
914
915 /* Print operand X (an rtx) in assembler syntax to file FILE. */
916 #define PRINT_OPERAND(FILE, X, CODE) print_operand ((FILE), (X), (CODE))
917 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address ((FILE), (ADDR))
918
919 /* Output an element of a case-vector that is absolute. */
920 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
921 do { \
922 char buf[32]; \
923 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
924 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
925 assemble_name ((FILE), buf); \
926 fputc ('\n', (FILE)); \
927 } while (0)
928
929 /* Output an element of a case-vector that is relative. */
930 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
931 do { \
932 char buf[32]; \
933 fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \
934 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
935 assemble_name ((FILE), buf); \
936 fputc ('-', (FILE)); \
937 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
938 assemble_name ((FILE), buf); \
939 fputc ('\n', (FILE)); \
940 } while (0)
941
942 /* Mark the return register as used by the epilogue so that we can
943 use it in unadorned (return) and (simple_return) instructions. */
944 #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM)
945
946 #undef ASM_OUTPUT_FUNCTION_LABEL
947 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
948 s390_asm_output_function_label ((FILE), (NAME), (DECL))
949
950 #if S390_USE_TARGET_ATTRIBUTE
951 /* Hook to output .machine and .machinemode at start of function. */
952 #undef ASM_OUTPUT_FUNCTION_PREFIX
953 #define ASM_OUTPUT_FUNCTION_PREFIX s390_asm_output_function_prefix
954
955 /* Hook to output .machine and .machinemode at end of function. */
956 #undef ASM_DECLARE_FUNCTION_SIZE
957 #define ASM_DECLARE_FUNCTION_SIZE s390_asm_declare_function_size
958 #endif
959
960 /* Miscellaneous parameters. */
961
962 /* Specify the machine mode that this machine uses for the index in the
963 tablejump instruction. */
964 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
965
966 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
967 is done just by pretending it is already truncated. */
968 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
969
970 /* Specify the machine mode that pointers have.
971 After generation of rtl, the compiler makes no further distinction
972 between pointers and any other objects of this machine mode. */
973 #define Pmode (TARGET_64BIT ? DImode : SImode)
974
975 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */
976 #define POINTERS_EXTEND_UNSIGNED -1
977
978 /* A function address in a call instruction is a byte address (for
979 indexing purposes) so give the MEM rtx a byte's mode. */
980 #define FUNCTION_MODE QImode
981
982 /* Specify the value which is used when clz operand is zero. */
983 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
984
985 /* Machine-specific symbol_ref flags. */
986 #define SYMBOL_FLAG_ALIGN_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
987 #define SYMBOL_FLAG_ALIGN_MASK \
988 ((SYMBOL_FLAG_MACH_DEP << 0) | (SYMBOL_FLAG_MACH_DEP << 1))
989
990 #define SYMBOL_FLAG_SET_ALIGN(X, A) \
991 (SYMBOL_REF_FLAGS (X) = (SYMBOL_REF_FLAGS (X) & ~SYMBOL_FLAG_ALIGN_MASK) \
992 | (A << SYMBOL_FLAG_ALIGN_SHIFT))
993
994 #define SYMBOL_FLAG_GET_ALIGN(X) \
995 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN_MASK) >> SYMBOL_FLAG_ALIGN_SHIFT)
996
997 /* Helpers to access symbol_ref flags. They are used in
998 check_symref_alignment() and larl_operand to detect if the
999 available alignment matches the required one. We do not use
1000 a positive check like _ALIGN2 because in that case we would have
1001 to annotate every symbol_ref. However, we only want to touch
1002 the symbol_refs that can be misaligned and assume that the others
1003 are correctly aligned. Hence, if a symbol_ref does not have
1004 a _NOTALIGN flag it is supposed to be correctly aligned. */
1005 #define SYMBOL_FLAG_SET_NOTALIGN2(X) SYMBOL_FLAG_SET_ALIGN((X), 1)
1006 #define SYMBOL_FLAG_SET_NOTALIGN4(X) SYMBOL_FLAG_SET_ALIGN((X), 2)
1007 #define SYMBOL_FLAG_SET_NOTALIGN8(X) SYMBOL_FLAG_SET_ALIGN((X), 3)
1008
1009 #define SYMBOL_FLAG_NOTALIGN2_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 1)
1010 #define SYMBOL_FLAG_NOTALIGN4_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 2 \
1011 || SYMBOL_FLAG_GET_ALIGN(X) == 1)
1012 #define SYMBOL_FLAG_NOTALIGN8_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 3 \
1013 || SYMBOL_FLAG_GET_ALIGN(X) == 2 \
1014 || SYMBOL_FLAG_GET_ALIGN(X) == 1)
1015
1016 /* Check whether integer displacement is in range for a short displacement. */
1017 #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095)
1018
1019 /* Check whether integer displacement is in range. */
1020 #define DISP_IN_RANGE(d) \
1021 (TARGET_LONG_DISPLACEMENT \
1022 ? ((d) >= -524288 && (d) <= 524287) \
1023 : SHORT_DISP_IN_RANGE(d))
1024
1025 /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */
1026 #define READ_CAN_USE_WRITE_PREFETCH 1
1027
1028 extern const int processor_flags_table[];
1029
1030 /* The truth element value for vector comparisons. Our instructions
1031 always generate -1 in that case. */
1032 #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE))
1033
1034 /* Target pragma. */
1035
1036 /* resolve_overloaded_builtin can not be defined the normal way since
1037 it is defined in code which technically belongs to the
1038 front-end. */
1039 #define REGISTER_TARGET_PRAGMAS() \
1040 do { \
1041 s390_register_target_pragmas (); \
1042 } while (0)
1043
1044 #endif /* S390_H */
Mirror of the offical gcc git repository hosted at gcc.gnu.org