1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-flags.h"
36 #include "insn-attr.h"
45 /* 1 if the caller has placed an "unimp" insn immediately after the call.
46 This is used in v8 code when calling a function that returns a structure.
47 v9 doesn't have this. Be careful to have this test be the same as that
50 #define SKIP_CALLERS_UNIMP_P \
51 (!TARGET_ARCH64 && current_function_returns_struct \
52 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
53 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
56 /* Global variables for machine-dependent things. */
58 /* Size of frame. Need to know this to emit return insns from leaf procedures.
59 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
60 reload pass. This is important as the value is later used in insn
61 scheduling (to see what can go in a delay slot).
62 APPARENT_FSIZE is the size of the stack less the register save area and less
63 the outgoing argument area. It is used when saving call preserved regs. */
64 static int apparent_fsize
;
65 static int actual_fsize
;
67 /* Number of live general or floating point registers needed to be saved
68 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
69 static int num_gfregs
;
71 /* Save the operands last given to a compare for use when we
72 generate a scc or bcc insn. */
74 rtx sparc_compare_op0
, sparc_compare_op1
;
76 /* We may need an epilogue if we spill too many registers.
77 If this is non-zero, then we branch here for the epilogue. */
78 static rtx leaf_label
;
82 /* Vector to say how input registers are mapped to output
83 registers. FRAME_POINTER_REGNUM cannot be remapped by
84 this function to eliminate it. You must use -fomit-frame-pointer
86 char leaf_reg_remap
[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs
[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
122 /* Name of where we pretend to think the frame pointer points.
123 Normally, this is "%fp", but if we are in a leaf procedure,
124 this is "%sp+something". We record "something" separately as it may be
125 too big for reg+constant addressing. */
127 static const char *frame_base_name
;
128 static int frame_base_offset
;
130 static void sparc_init_modes
PARAMS ((void));
131 static int save_regs
PARAMS ((FILE *, int, int, const char *,
133 static int restore_regs
PARAMS ((FILE *, int, int, const char *, int, int));
134 static void build_big_number
PARAMS ((FILE *, int, const char *));
135 static int function_arg_slotno
PARAMS ((const CUMULATIVE_ARGS
*,
136 enum machine_mode
, tree
, int, int,
139 static int supersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
140 static int hypersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
141 static int ultrasparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
143 static void sparc_output_addr_vec
PARAMS ((rtx
));
144 static void sparc_output_addr_diff_vec
PARAMS ((rtx
));
145 static void sparc_output_deferred_case_vectors
PARAMS ((void));
146 static void sparc_add_gc_roots
PARAMS ((void));
147 static void mark_ultrasparc_pipeline_state
PARAMS ((void *));
148 static int check_return_regs
PARAMS ((rtx
));
149 static int epilogue_renumber
PARAMS ((rtx
*, int));
150 static int ultra_cmove_results_ready_p
PARAMS ((rtx
));
151 static int ultra_fpmode_conflict_exists
PARAMS ((enum machine_mode
));
152 static rtx
*ultra_find_type
PARAMS ((int, rtx
*, int));
153 static void ultra_build_types_avail
PARAMS ((rtx
*, int));
154 static void ultra_flush_pipeline
PARAMS ((void));
155 static void ultra_rescan_pipeline_state
PARAMS ((rtx
*, int));
156 static int set_extends
PARAMS ((rtx
, rtx
));
157 static void output_restore_regs
PARAMS ((FILE *, int));
159 /* Option handling. */
161 /* Code model option as passed by user. */
162 const char *sparc_cmodel_string
;
164 enum cmodel sparc_cmodel
;
166 char sparc_hard_reg_printed
[8];
168 struct sparc_cpu_select sparc_select
[] =
170 /* switch name, tune arch */
171 { (char *)0, "default", 1, 1 },
172 { (char *)0, "-mcpu=", 1, 1 },
173 { (char *)0, "-mtune=", 1, 0 },
177 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
178 enum processor_type sparc_cpu
;
180 /* Validate and override various options, and do some machine dependent
184 sparc_override_options ()
186 static struct code_model
{
191 { "medlow", CM_MEDLOW
},
192 { "medmid", CM_MEDMID
},
193 { "medany", CM_MEDANY
},
194 { "embmedany", CM_EMBMEDANY
},
197 struct code_model
*cmodel
;
198 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
199 static struct cpu_default
{
203 /* There must be one entry here for each TARGET_CPU value. */
204 { TARGET_CPU_sparc
, "cypress" },
205 { TARGET_CPU_sparclet
, "tsc701" },
206 { TARGET_CPU_sparclite
, "f930" },
207 { TARGET_CPU_v8
, "v8" },
208 { TARGET_CPU_hypersparc
, "hypersparc" },
209 { TARGET_CPU_sparclite86x
, "sparclite86x" },
210 { TARGET_CPU_supersparc
, "supersparc" },
211 { TARGET_CPU_v9
, "v9" },
212 { TARGET_CPU_ultrasparc
, "ultrasparc" },
215 struct cpu_default
*def
;
216 /* Table of values for -m{cpu,tune}=. */
217 static struct cpu_table
{
219 enum processor_type processor
;
223 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
224 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
225 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
226 /* TI TMS390Z55 supersparc */
227 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
228 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
229 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
230 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
231 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
232 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
233 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
234 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
236 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
238 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
239 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
240 /* TI ultrasparc I, II, IIi */
241 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
242 /* Although insns using %y are deprecated, it is a clear win on current
244 |MASK_DEPRECATED_V8_INSNS
},
247 struct cpu_table
*cpu
;
248 struct sparc_cpu_select
*sel
;
251 #ifndef SPARC_BI_ARCH
252 /* Check for unsupported architecture size. */
253 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
255 error ("%s is not supported by this configuration",
256 DEFAULT_ARCH32_P
? "-m64" : "-m32");
260 /* At the moment we don't allow different pointer size and architecture */
261 if (! TARGET_64BIT
!= ! TARGET_PTR64
)
263 error ("-mptr%d not allowed on -m%d",
264 TARGET_PTR64
? 64 : 32, TARGET_64BIT
? 64 : 32);
266 target_flags
|= MASK_PTR64
;
268 target_flags
&= ~MASK_PTR64
;
271 /* We force all 64bit archs to use 128 bit long double */
272 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
274 error ("-mlong-double-64 not allowed with -m64");
275 target_flags
|= MASK_LONG_DOUBLE_128
;
278 /* Code model selection. */
279 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
283 sparc_cmodel
= CM_32
;
286 if (sparc_cmodel_string
!= NULL
)
290 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
291 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
293 if (cmodel
->name
== NULL
)
294 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
296 sparc_cmodel
= cmodel
->value
;
299 error ("-mcmodel= is not supported on 32 bit systems");
302 fpu
= TARGET_FPU
; /* save current -mfpu status */
304 /* Set the default CPU. */
305 for (def
= &cpu_default
[0]; def
->name
; ++def
)
306 if (def
->cpu
== TARGET_CPU_DEFAULT
)
310 sparc_select
[0].string
= def
->name
;
312 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
316 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
317 if (! strcmp (sel
->string
, cpu
->name
))
320 sparc_cpu
= cpu
->processor
;
324 target_flags
&= ~cpu
->disable
;
325 target_flags
|= cpu
->enable
;
331 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
335 /* If -mfpu or -mno-fpu was explicitly used, don't override with
336 the processor default. Clear MASK_FPU_SET to avoid confusing
337 the reverse mapping from switch values to names. */
340 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
341 target_flags
&= ~MASK_FPU_SET
;
344 /* Don't allow -mvis if FPU is disabled. */
346 target_flags
&= ~MASK_VIS
;
348 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
350 -m64 also implies v9. */
351 if (TARGET_VIS
|| TARGET_ARCH64
)
352 target_flags
|= MASK_V9
;
354 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
355 if (TARGET_V9
&& TARGET_ARCH32
)
356 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
358 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
359 if (! TARGET_V9
|| TARGET_ARCH64
)
360 target_flags
&= ~MASK_V8PLUS
;
362 /* Don't use stack biasing in 32 bit mode. */
364 target_flags
&= ~MASK_STACK_BIAS
;
366 /* Supply a default value for align_functions. */
367 if (align_functions
== 0 && sparc_cpu
== PROCESSOR_ULTRASPARC
)
368 align_functions
= 32;
370 /* Validate PCC_STRUCT_RETURN. */
371 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
372 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
374 /* Do various machine dependent initializations. */
377 if ((profile_flag
|| profile_block_flag
)
378 && sparc_cmodel
!= CM_32
&& sparc_cmodel
!= CM_MEDLOW
)
380 error ("profiling does not support code models other than medlow");
383 /* Register global variables with the garbage collector. */
384 sparc_add_gc_roots ();
387 /* Miscellaneous utilities. */
389 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
390 or branch on register contents instructions. */
396 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
397 || code
== LE
|| code
== GT
);
401 /* Operand constraints. */
403 /* Return non-zero only if OP is a register of mode MODE,
407 reg_or_0_operand (op
, mode
)
409 enum machine_mode mode
;
411 if (register_operand (op
, mode
))
413 if (op
== const0_rtx
)
415 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
416 && CONST_DOUBLE_HIGH (op
) == 0
417 && CONST_DOUBLE_LOW (op
) == 0)
419 if (fp_zero_operand (op
, mode
))
424 /* Nonzero if OP is a floating point value with value 0.0. */
427 fp_zero_operand (op
, mode
)
429 enum machine_mode mode
;
431 if (GET_MODE_CLASS (GET_MODE (op
)) != MODE_FLOAT
)
433 return op
== CONST0_RTX (mode
);
436 /* Nonzero if OP is a floating point constant which can
437 be loaded into an integer register using a single
438 sethi instruction. */
444 if (GET_CODE (op
) == CONST_DOUBLE
)
449 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
450 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
451 ! REAL_VALUE_MINUS_ZERO (r
))
453 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
454 if (SPARC_SETHI_P (i
))
461 /* Nonzero if OP is a floating point constant which can
462 be loaded into an integer register using a single
469 if (GET_CODE (op
) == CONST_DOUBLE
)
474 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
475 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
476 ! REAL_VALUE_MINUS_ZERO (r
))
478 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
479 if (SPARC_SIMM13_P (i
))
486 /* Nonzero if OP is a floating point constant which can
487 be loaded into an integer register using a high/losum
488 instruction sequence. */
494 /* The constraints calling this should only be in
495 SFmode move insns, so any constant which cannot
496 be moved using a single insn will do. */
497 if (GET_CODE (op
) == CONST_DOUBLE
)
502 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
503 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
504 ! REAL_VALUE_MINUS_ZERO (r
))
506 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
507 if (! SPARC_SETHI_P (i
)
508 && ! SPARC_SIMM13_P (i
))
515 /* Nonzero if OP is an integer register. */
518 intreg_operand (op
, mode
)
520 enum machine_mode mode ATTRIBUTE_UNUSED
;
522 return (register_operand (op
, SImode
)
523 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
526 /* Nonzero if OP is a floating point condition code register. */
529 fcc_reg_operand (op
, mode
)
531 enum machine_mode mode
;
533 /* This can happen when recog is called from combine. Op may be a MEM.
534 Fail instead of calling abort in this case. */
535 if (GET_CODE (op
) != REG
)
538 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
541 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
544 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
545 if (reg_renumber
== 0)
546 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
547 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
549 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
553 /* Nonzero if OP is an integer or floating point condition code register. */
556 icc_or_fcc_reg_operand (op
, mode
)
558 enum machine_mode mode
;
560 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
562 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
565 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
570 return fcc_reg_operand (op
, mode
);
573 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
575 restore_operand (op
, mode
)
577 enum machine_mode mode
;
579 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
580 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
583 /* Call insn on SPARC can take a PC-relative constant address, or any regular
587 call_operand (op
, mode
)
589 enum machine_mode mode
;
591 if (GET_CODE (op
) != MEM
)
594 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
598 call_operand_address (op
, mode
)
600 enum machine_mode mode
;
602 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
605 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
606 reference and a constant. */
609 symbolic_operand (op
, mode
)
611 enum machine_mode mode
;
613 enum machine_mode omode
= GET_MODE (op
);
615 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
618 switch (GET_CODE (op
))
626 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
627 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
628 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
635 /* Return truth value of statement that OP is a symbolic memory
636 operand of mode MODE. */
639 symbolic_memory_operand (op
, mode
)
641 enum machine_mode mode ATTRIBUTE_UNUSED
;
643 if (GET_CODE (op
) == SUBREG
)
644 op
= SUBREG_REG (op
);
645 if (GET_CODE (op
) != MEM
)
648 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
649 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
652 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
655 label_ref_operand (op
, mode
)
657 enum machine_mode mode
;
659 if (GET_CODE (op
) != LABEL_REF
)
661 if (GET_MODE (op
) != mode
)
666 /* Return 1 if the operand is an argument used in generating pic references
667 in either the medium/low or medium/anywhere code models of sparc64. */
670 sp64_medium_pic_operand (op
, mode
)
672 enum machine_mode mode ATTRIBUTE_UNUSED
;
674 /* Check for (const (minus (symbol_ref:GOT)
675 (const (minus (label) (pc))))). */
676 if (GET_CODE (op
) != CONST
)
679 if (GET_CODE (op
) != MINUS
)
681 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
683 /* ??? Ensure symbol is GOT. */
684 if (GET_CODE (XEXP (op
, 1)) != CONST
)
686 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
691 /* Return 1 if the operand is a data segment reference. This includes
692 the readonly data segment, or in other words anything but the text segment.
693 This is needed in the medium/anywhere code model on v9. These values
694 are accessed with EMBMEDANY_BASE_REG. */
697 data_segment_operand (op
, mode
)
699 enum machine_mode mode ATTRIBUTE_UNUSED
;
701 switch (GET_CODE (op
))
704 return ! SYMBOL_REF_FLAG (op
);
706 /* Assume canonical format of symbol + constant.
709 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
715 /* Return 1 if the operand is a text segment reference.
716 This is needed in the medium/anywhere code model on v9. */
719 text_segment_operand (op
, mode
)
721 enum machine_mode mode ATTRIBUTE_UNUSED
;
723 switch (GET_CODE (op
))
728 return SYMBOL_REF_FLAG (op
);
730 /* Assume canonical format of symbol + constant.
733 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
739 /* Return 1 if the operand is either a register or a memory operand that is
743 reg_or_nonsymb_mem_operand (op
, mode
)
745 enum machine_mode mode
;
747 if (register_operand (op
, mode
))
750 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
757 splittable_symbolic_memory_operand (op
, mode
)
759 enum machine_mode mode ATTRIBUTE_UNUSED
;
761 if (GET_CODE (op
) != MEM
)
763 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
769 splittable_immediate_memory_operand (op
, mode
)
771 enum machine_mode mode ATTRIBUTE_UNUSED
;
773 if (GET_CODE (op
) != MEM
)
775 if (! immediate_operand (XEXP (op
, 0), Pmode
))
780 /* Return truth value of whether OP is EQ or NE. */
785 enum machine_mode mode ATTRIBUTE_UNUSED
;
787 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
790 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
791 or LTU for non-floating-point. We handle those specially. */
794 normal_comp_operator (op
, mode
)
796 enum machine_mode mode ATTRIBUTE_UNUSED
;
798 enum rtx_code code
= GET_CODE (op
);
800 if (GET_RTX_CLASS (code
) != '<')
803 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
804 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
807 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
810 /* Return 1 if this is a comparison operator. This allows the use of
811 MATCH_OPERATOR to recognize all the branch insns. */
814 noov_compare_op (op
, mode
)
816 enum machine_mode mode ATTRIBUTE_UNUSED
;
818 enum rtx_code code
= GET_CODE (op
);
820 if (GET_RTX_CLASS (code
) != '<')
823 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
)
824 /* These are the only branches which work with CC_NOOVmode. */
825 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
829 /* Nonzero if OP is a comparison operator suitable for use in v9
830 conditional move or branch on register contents instructions. */
833 v9_regcmp_op (op
, mode
)
835 enum machine_mode mode ATTRIBUTE_UNUSED
;
837 enum rtx_code code
= GET_CODE (op
);
839 if (GET_RTX_CLASS (code
) != '<')
842 return v9_regcmp_p (code
);
845 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
850 enum machine_mode mode ATTRIBUTE_UNUSED
;
852 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
855 /* Return nonzero if OP is an operator of mode MODE which can set
856 the condition codes explicitly. We do not include PLUS and MINUS
857 because these require CC_NOOVmode, which we handle explicitly. */
860 cc_arithop (op
, mode
)
862 enum machine_mode mode ATTRIBUTE_UNUSED
;
864 if (GET_CODE (op
) == AND
865 || GET_CODE (op
) == IOR
866 || GET_CODE (op
) == XOR
)
872 /* Return nonzero if OP is an operator of mode MODE which can bitwise
873 complement its second operand and set the condition codes explicitly. */
876 cc_arithopn (op
, mode
)
878 enum machine_mode mode ATTRIBUTE_UNUSED
;
880 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
881 and (xor ... (not ...)) to (not (xor ...)). */
882 return (GET_CODE (op
) == AND
883 || GET_CODE (op
) == IOR
);
886 /* Return true if OP is a register, or is a CONST_INT that can fit in a
887 signed 13 bit immediate field. This is an acceptable SImode operand for
888 most 3 address instructions. */
891 arith_operand (op
, mode
)
893 enum machine_mode mode
;
896 if (register_operand (op
, mode
))
898 if (GET_CODE (op
) != CONST_INT
)
900 val
= INTVAL (op
) & 0xffffffff;
901 return SPARC_SIMM13_P (val
);
904 /* Return true if OP is a constant 4096 */
907 arith_4096_operand (op
, mode
)
909 enum machine_mode mode ATTRIBUTE_UNUSED
;
912 if (GET_CODE (op
) != CONST_INT
)
914 val
= INTVAL (op
) & 0xffffffff;
918 /* Return true if OP is suitable as second operand for add/sub */
921 arith_add_operand (op
, mode
)
923 enum machine_mode mode
;
925 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
928 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
929 immediate field of OR and XOR instructions. Used for 64-bit
930 constant formation patterns. */
932 const64_operand (op
, mode
)
934 enum machine_mode mode ATTRIBUTE_UNUSED
;
936 return ((GET_CODE (op
) == CONST_INT
937 && SPARC_SIMM13_P (INTVAL (op
)))
938 #if HOST_BITS_PER_WIDE_INT != 64
939 || (GET_CODE (op
) == CONST_DOUBLE
940 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
941 && (CONST_DOUBLE_HIGH (op
) ==
942 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
943 (HOST_WIDE_INT
)0xffffffff : 0)))
948 /* The same, but only for sethi instructions. */
950 const64_high_operand (op
, mode
)
952 enum machine_mode mode ATTRIBUTE_UNUSED
;
954 return ((GET_CODE (op
) == CONST_INT
955 && (INTVAL (op
) & 0xfffffc00) != 0
956 && SPARC_SETHI_P (INTVAL (op
))
957 #if HOST_BITS_PER_WIDE_INT != 64
958 /* Must be positive on non-64bit host else the
959 optimizer is fooled into thinking that sethi
960 sign extends, even though it does not. */
964 || (GET_CODE (op
) == CONST_DOUBLE
965 && CONST_DOUBLE_HIGH (op
) == 0
966 && (CONST_DOUBLE_LOW (op
) & 0xfffffc00) != 0
967 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
970 /* Return true if OP is a register, or is a CONST_INT that can fit in a
971 signed 11 bit immediate field. This is an acceptable SImode operand for
972 the movcc instructions. */
975 arith11_operand (op
, mode
)
977 enum machine_mode mode
;
979 return (register_operand (op
, mode
)
980 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
983 /* Return true if OP is a register, or is a CONST_INT that can fit in a
984 signed 10 bit immediate field. This is an acceptable SImode operand for
985 the movrcc instructions. */
988 arith10_operand (op
, mode
)
990 enum machine_mode mode
;
992 return (register_operand (op
, mode
)
993 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
996 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
997 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
999 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1000 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1001 for most 3 address instructions. */
1004 arith_double_operand (op
, mode
)
1006 enum machine_mode mode
;
1008 return (register_operand (op
, mode
)
1009 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1011 && GET_CODE (op
) == CONST_DOUBLE
1012 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1013 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1015 && GET_CODE (op
) == CONST_DOUBLE
1016 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1017 && ((CONST_DOUBLE_HIGH (op
) == -1
1018 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1019 || (CONST_DOUBLE_HIGH (op
) == 0
1020 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1023 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1026 arith_double_4096_operand (op
, mode
)
1028 enum machine_mode mode ATTRIBUTE_UNUSED
;
1030 return (TARGET_ARCH64
&&
1031 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1032 (GET_CODE (op
) == CONST_DOUBLE
&&
1033 CONST_DOUBLE_LOW (op
) == 4096 &&
1034 CONST_DOUBLE_HIGH (op
) == 0)));
1037 /* Return true if OP is suitable as second operand for add/sub in DImode */
1040 arith_double_add_operand (op
, mode
)
1042 enum machine_mode mode
;
1044 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1047 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1048 can fit in an 11 bit immediate field. This is an acceptable DImode
1049 operand for the movcc instructions. */
1050 /* ??? Replace with arith11_operand? */
1053 arith11_double_operand (op
, mode
)
1055 enum machine_mode mode
;
1057 return (register_operand (op
, mode
)
1058 || (GET_CODE (op
) == CONST_DOUBLE
1059 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1060 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1061 && ((CONST_DOUBLE_HIGH (op
) == -1
1062 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1063 || (CONST_DOUBLE_HIGH (op
) == 0
1064 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1065 || (GET_CODE (op
) == CONST_INT
1066 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1067 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1070 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1071 can fit in an 10 bit immediate field. This is an acceptable DImode
1072 operand for the movrcc instructions. */
1073 /* ??? Replace with arith10_operand? */
1076 arith10_double_operand (op
, mode
)
1078 enum machine_mode mode
;
1080 return (register_operand (op
, mode
)
1081 || (GET_CODE (op
) == CONST_DOUBLE
1082 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1083 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1084 && ((CONST_DOUBLE_HIGH (op
) == -1
1085 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1086 || (CONST_DOUBLE_HIGH (op
) == 0
1087 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1088 || (GET_CODE (op
) == CONST_INT
1089 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1090 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1093 /* Return truth value of whether OP is a integer which fits the
1094 range constraining immediate operands in most three-address insns,
1095 which have a 13 bit immediate field. */
1098 small_int (op
, mode
)
1100 enum machine_mode mode ATTRIBUTE_UNUSED
;
1102 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1106 small_int_or_double (op
, mode
)
1108 enum machine_mode mode ATTRIBUTE_UNUSED
;
1110 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1111 || (GET_CODE (op
) == CONST_DOUBLE
1112 && CONST_DOUBLE_HIGH (op
) == 0
1113 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1116 /* Recognize operand values for the umul instruction. That instruction sign
1117 extends immediate values just like all other sparc instructions, but
1118 interprets the extended result as an unsigned number. */
1121 uns_small_int (op
, mode
)
1123 enum machine_mode mode ATTRIBUTE_UNUSED
;
1125 #if HOST_BITS_PER_WIDE_INT > 32
1126 /* All allowed constants will fit a CONST_INT. */
1127 return (GET_CODE (op
) == CONST_INT
1128 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1129 || (INTVAL (op
) >= 0xFFFFF000
1130 && INTVAL (op
) < 0x100000000)));
1132 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1133 || (GET_CODE (op
) == CONST_DOUBLE
1134 && CONST_DOUBLE_HIGH (op
) == 0
1135 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1140 uns_arith_operand (op
, mode
)
1142 enum machine_mode mode
;
1144 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1147 /* Return truth value of statement that OP is a call-clobbered register. */
1149 clobbered_register (op
, mode
)
1151 enum machine_mode mode ATTRIBUTE_UNUSED
;
1153 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1156 /* Return 1 if OP is a valid operand for the source of a move insn. */
1159 input_operand (op
, mode
)
1161 enum machine_mode mode
;
1163 /* If both modes are non-void they must be the same. */
1164 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1167 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1168 if (GET_CODE (op
) == CONST
&& GET_CODE (XEXP (op
, 0)) == CONSTANT_P_RTX
)
1171 /* Allow any one instruction integer constant, and all CONST_INT
1172 variants when we are working in DImode and !arch64. */
1173 if (GET_MODE_CLASS (mode
) == MODE_INT
1174 && ((GET_CODE (op
) == CONST_INT
1175 && ((SPARC_SETHI_P (INTVAL (op
))
1177 || (INTVAL (op
) >= 0)
1181 || SPARC_SIMM13_P (INTVAL (op
))
1183 && ! TARGET_ARCH64
)))
1185 && GET_CODE (op
) == CONST_DOUBLE
1186 && ((CONST_DOUBLE_HIGH (op
) == 0
1187 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1189 #if HOST_BITS_PER_WIDE_INT == 64
1190 (CONST_DOUBLE_HIGH (op
) == 0
1191 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1193 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1194 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1195 && CONST_DOUBLE_HIGH (op
) == 0)
1196 || (CONST_DOUBLE_HIGH (op
) == -1)))
1201 /* If !arch64 and this is a DImode const, allow it so that
1202 the splits can be generated. */
1205 && GET_CODE (op
) == CONST_DOUBLE
)
1208 if (register_operand (op
, mode
))
1211 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1212 && GET_CODE (op
) == CONST_DOUBLE
)
1215 /* If this is a SUBREG, look inside so that we handle
1216 paradoxical ones. */
1217 if (GET_CODE (op
) == SUBREG
)
1218 op
= SUBREG_REG (op
);
1220 /* Check for valid MEM forms. */
1221 if (GET_CODE (op
) == MEM
)
1223 rtx inside
= XEXP (op
, 0);
1225 if (GET_CODE (inside
) == LO_SUM
)
1227 /* We can't allow these because all of the splits
1228 (eventually as they trickle down into DFmode
1229 splits) require offsettable memory references. */
1231 && GET_MODE (op
) == TFmode
)
1234 return (register_operand (XEXP (inside
, 0), Pmode
)
1235 && CONSTANT_P (XEXP (inside
, 1)));
1237 return memory_address_p (mode
, inside
);
1244 /* We know it can't be done in one insn when we get here,
1245 the movsi expander guarentees this. */
1247 sparc_emit_set_const32 (op0
, op1
)
1251 enum machine_mode mode
= GET_MODE (op0
);
1254 if (GET_CODE (op1
) == CONST_INT
)
1256 HOST_WIDE_INT value
= INTVAL (op1
);
1258 if (SPARC_SETHI_P (value
)
1259 || SPARC_SIMM13_P (value
))
1263 /* Full 2-insn decomposition is needed. */
1264 if (reload_in_progress
|| reload_completed
)
1267 temp
= gen_reg_rtx (mode
);
1269 if (GET_CODE (op1
) == CONST_INT
)
1271 /* Emit them as real moves instead of a HIGH/LO_SUM,
1272 this way CSE can see everything and reuse intermediate
1273 values if it wants. */
1275 && HOST_BITS_PER_WIDE_INT
!= 64
1276 && (INTVAL (op1
) & 0x80000000) != 0)
1278 emit_insn (gen_rtx_SET (VOIDmode
,
1280 gen_rtx_CONST_DOUBLE (VOIDmode
, const0_rtx
,
1281 INTVAL (op1
) & 0xfffffc00, 0)));
1285 emit_insn (gen_rtx_SET (VOIDmode
,
1287 GEN_INT (INTVAL (op1
) & 0xfffffc00)));
1289 emit_insn (gen_rtx_SET (VOIDmode
,
1293 GEN_INT (INTVAL (op1
) & 0x3ff))));
1297 /* A symbol, emit in the traditional way. */
1298 emit_insn (gen_rtx_SET (VOIDmode
,
1302 emit_insn (gen_rtx_SET (VOIDmode
,
1304 gen_rtx_LO_SUM (mode
,
1312 /* Sparc-v9 code-model support. */
1314 sparc_emit_set_symbolic_const64 (op0
, op1
, temp1
)
1319 switch (sparc_cmodel
)
1322 /* The range spanned by all instructions in the object is less
1323 than 2^31 bytes (2GB) and the distance from any instruction
1324 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1325 than 2^31 bytes (2GB).
1327 The executable must be in the low 4TB of the virtual address
1330 sethi %hi(symbol), %temp
1331 or %temp, %lo(symbol), %reg */
1332 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1333 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1337 /* The range spanned by all instructions in the object is less
1338 than 2^31 bytes (2GB) and the distance from any instruction
1339 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1340 than 2^31 bytes (2GB).
1342 The executable must be in the low 16TB of the virtual address
1345 sethi %h44(symbol), %temp1
1346 or %temp1, %m44(symbol), %temp2
1347 sllx %temp2, 12, %temp3
1348 or %temp3, %l44(symbol), %reg */
1349 emit_insn (gen_seth44 (op0
, op1
));
1350 emit_insn (gen_setm44 (op0
, op0
, op1
));
1351 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1352 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1353 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1357 /* The range spanned by all instructions in the object is less
1358 than 2^31 bytes (2GB) and the distance from any instruction
1359 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1360 than 2^31 bytes (2GB).
1362 The executable can be placed anywhere in the virtual address
1365 sethi %hh(symbol), %temp1
1366 sethi %lm(symbol), %temp2
1367 or %temp1, %hm(symbol), %temp3
1368 or %temp2, %lo(symbol), %temp4
1369 sllx %temp3, 32, %temp5
1370 or %temp4, %temp5, %reg */
1372 /* Getting this right wrt. reloading is really tricky.
1373 We _MUST_ have a separate temporary at this point,
1374 if we don't barf immediately instead of generating
1379 emit_insn (gen_sethh (op0
, op1
));
1380 emit_insn (gen_setlm (temp1
, op1
));
1381 emit_insn (gen_sethm (op0
, op0
, op1
));
1382 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1383 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1384 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1385 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1386 emit_insn (gen_setlo (op0
, op0
, op1
));
1390 /* Old old old backwards compatibility kruft here.
1391 Essentially it is MEDLOW with a fixed 64-bit
1392 virtual base added to all data segment addresses.
1393 Text-segment stuff is computed like MEDANY, we can't
1394 reuse the code above because the relocation knobs
1397 Data segment: sethi %hi(symbol), %temp1
1398 or %temp1, %lo(symbol), %temp2
1399 add %temp2, EMBMEDANY_BASE_REG, %reg
1401 Text segment: sethi %uhi(symbol), %temp1
1402 sethi %hi(symbol), %temp2
1403 or %temp1, %ulo(symbol), %temp3
1404 or %temp2, %lo(symbol), %temp4
1405 sllx %temp3, 32, %temp5
1406 or %temp4, %temp5, %reg */
1407 if (data_segment_operand (op1
, GET_MODE (op1
)))
1409 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1410 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1411 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1415 /* Getting this right wrt. reloading is really tricky.
1416 We _MUST_ have a separate temporary at this point,
1417 so we barf immediately instead of generating
1422 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1423 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1424 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1425 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1426 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1427 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1428 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1429 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1438 /* These avoid problems when cross compiling. If we do not
1439 go through all this hair then the optimizer will see
1440 invalid REG_EQUAL notes or in some cases none at all. */
1441 static void sparc_emit_set_safe_HIGH64
PARAMS ((rtx
, HOST_WIDE_INT
));
1442 static rtx gen_safe_SET64
PARAMS ((rtx
, HOST_WIDE_INT
));
1443 static rtx gen_safe_OR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1444 static rtx gen_safe_XOR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1446 #if HOST_BITS_PER_WIDE_INT == 64
1447 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1448 #define GEN_INT64(__x) GEN_INT (__x)
1450 #define GEN_HIGHINT64(__x) \
1451 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1452 (__x) & 0xfffffc00, 0)
1453 #define GEN_INT64(__x) \
1454 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1455 (__x) & 0xffffffff, \
1456 ((__x) & 0x80000000 \
1460 /* The optimizer is not to assume anything about exactly
1461 which bits are set for a HIGH, they are unspecified.
1462 Unfortunately this leads to many missed optimizations
1463 during CSE. We mask out the non-HIGH bits, and matches
1464 a plain movdi, to alleviate this problem. */
1466 sparc_emit_set_safe_HIGH64 (dest
, val
)
1470 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1474 gen_safe_SET64 (dest
, val
)
1478 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1482 gen_safe_OR64 (src
, val
)
1486 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1490 gen_safe_XOR64 (src
, val
)
1494 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1497 /* Worker routines for 64-bit constant formation on arch64.
1498 One of the key things to be doing in these emissions is
1499 to create as many temp REGs as possible. This makes it
1500 possible for half-built constants to be used later when
1501 such values are similar to something required later on.
1502 Without doing this, the optimizer cannot see such
1505 static void sparc_emit_set_const64_quick1
1506 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, int));
1509 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
, is_neg
)
1512 unsigned HOST_WIDE_INT low_bits
;
1515 unsigned HOST_WIDE_INT high_bits
;
1518 high_bits
= (~low_bits
) & 0xffffffff;
1520 high_bits
= low_bits
;
1522 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1525 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1526 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1530 /* If we are XOR'ing with -1, then we should emit a one's complement
1531 instead. This way the combiner will notice logical operations
1532 such as ANDN later on and substitute. */
1533 if ((low_bits
& 0x3ff) == 0x3ff)
1535 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1536 gen_rtx_NOT (DImode
, temp
)));
1540 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1541 gen_safe_XOR64 (temp
,
1542 (-0x400 | (low_bits
& 0x3ff)))));
1547 static void sparc_emit_set_const64_quick2
1548 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
,
1549 unsigned HOST_WIDE_INT
, int));
1552 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_immediate
, shift_count
)
1555 unsigned HOST_WIDE_INT high_bits
;
1556 unsigned HOST_WIDE_INT low_immediate
;
1561 if ((high_bits
& 0xfffffc00) != 0)
1563 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1564 if ((high_bits
& ~0xfffffc00) != 0)
1565 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1566 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1572 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1576 /* Now shift it up into place. */
1577 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1578 gen_rtx_ASHIFT (DImode
, temp2
,
1579 GEN_INT (shift_count
))));
1581 /* If there is a low immediate part piece, finish up by
1582 putting that in as well. */
1583 if (low_immediate
!= 0)
1584 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1585 gen_safe_OR64 (op0
, low_immediate
)));
1588 static void sparc_emit_set_const64_longway
1589 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1591 /* Full 64-bit constant decomposition. Even though this is the
1592 'worst' case, we still optimize a few things away. */
1594 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
)
1597 unsigned HOST_WIDE_INT high_bits
;
1598 unsigned HOST_WIDE_INT low_bits
;
1602 if (reload_in_progress
|| reload_completed
)
1605 sub_temp
= gen_reg_rtx (DImode
);
1607 if ((high_bits
& 0xfffffc00) != 0)
1609 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1610 if ((high_bits
& ~0xfffffc00) != 0)
1611 emit_insn (gen_rtx_SET (VOIDmode
,
1613 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1619 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1623 if (!reload_in_progress
&& !reload_completed
)
1625 rtx temp2
= gen_reg_rtx (DImode
);
1626 rtx temp3
= gen_reg_rtx (DImode
);
1627 rtx temp4
= gen_reg_rtx (DImode
);
1629 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1630 gen_rtx_ASHIFT (DImode
, sub_temp
,
1633 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1634 if ((low_bits
& ~0xfffffc00) != 0)
1636 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1637 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1638 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1639 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1643 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1644 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1649 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1650 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1651 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1654 /* We are in the middle of reload, so this is really
1655 painful. However we do still make an attempt to
1656 avoid emitting truly stupid code. */
1657 if (low1
!= const0_rtx
)
1659 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1660 gen_rtx_ASHIFT (DImode
, sub_temp
,
1661 GEN_INT (to_shift
))));
1662 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1663 gen_rtx_IOR (DImode
, op0
, low1
)));
1671 if (low2
!= const0_rtx
)
1673 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1674 gen_rtx_ASHIFT (DImode
, sub_temp
,
1675 GEN_INT (to_shift
))));
1676 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1677 gen_rtx_IOR (DImode
, op0
, low2
)));
1685 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1686 gen_rtx_ASHIFT (DImode
, sub_temp
,
1687 GEN_INT (to_shift
))));
1688 if (low3
!= const0_rtx
)
1689 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1690 gen_rtx_IOR (DImode
, op0
, low3
)));
1695 /* Analyze a 64-bit constant for certain properties. */
1696 static void analyze_64bit_constant
1697 PARAMS ((unsigned HOST_WIDE_INT
,
1698 unsigned HOST_WIDE_INT
,
1699 int *, int *, int *));
1702 analyze_64bit_constant (high_bits
, low_bits
, hbsp
, lbsp
, abbasp
)
1703 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1704 int *hbsp
, *lbsp
, *abbasp
;
1706 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1709 lowest_bit_set
= highest_bit_set
= -1;
1713 if ((lowest_bit_set
== -1)
1714 && ((low_bits
>> i
) & 1))
1716 if ((highest_bit_set
== -1)
1717 && ((high_bits
>> (32 - i
- 1)) & 1))
1718 highest_bit_set
= (64 - i
- 1);
1721 && ((highest_bit_set
== -1)
1722 || (lowest_bit_set
== -1)));
1728 if ((lowest_bit_set
== -1)
1729 && ((high_bits
>> i
) & 1))
1730 lowest_bit_set
= i
+ 32;
1731 if ((highest_bit_set
== -1)
1732 && ((low_bits
>> (32 - i
- 1)) & 1))
1733 highest_bit_set
= 32 - i
- 1;
1736 && ((highest_bit_set
== -1)
1737 || (lowest_bit_set
== -1)));
1739 /* If there are no bits set this should have gone out
1740 as one instruction! */
1741 if (lowest_bit_set
== -1
1742 || highest_bit_set
== -1)
1744 all_bits_between_are_set
= 1;
1745 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1749 if ((low_bits
& (1 << i
)) != 0)
1754 if ((high_bits
& (1 << (i
- 32))) != 0)
1757 all_bits_between_are_set
= 0;
1760 *hbsp
= highest_bit_set
;
1761 *lbsp
= lowest_bit_set
;
1762 *abbasp
= all_bits_between_are_set
;
1765 static int const64_is_2insns
1766 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1769 const64_is_2insns (high_bits
, low_bits
)
1770 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1772 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1775 || high_bits
== 0xffffffff)
1778 analyze_64bit_constant (high_bits
, low_bits
,
1779 &highest_bit_set
, &lowest_bit_set
,
1780 &all_bits_between_are_set
);
1782 if ((highest_bit_set
== 63
1783 || lowest_bit_set
== 0)
1784 && all_bits_between_are_set
!= 0)
1787 if ((highest_bit_set
- lowest_bit_set
) < 21)
1793 static unsigned HOST_WIDE_INT create_simple_focus_bits
1794 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
,
1797 static unsigned HOST_WIDE_INT
1798 create_simple_focus_bits (high_bits
, low_bits
, lowest_bit_set
, shift
)
1799 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1800 int lowest_bit_set
, shift
;
1802 HOST_WIDE_INT hi
, lo
;
1804 if (lowest_bit_set
< 32)
1806 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1807 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1812 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1819 /* Here we are sure to be arch64 and this is an integer constant
1820 being loaded into a register. Emit the most efficient
1821 insn sequence possible. Detection of all the 1-insn cases
1822 has been done already. */
1824 sparc_emit_set_const64 (op0
, op1
)
1828 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1829 int lowest_bit_set
, highest_bit_set
;
1830 int all_bits_between_are_set
;
1833 /* Sanity check that we know what we are working with. */
1834 if (! TARGET_ARCH64
)
1837 if (GET_CODE (op0
) != SUBREG
)
1839 if (GET_CODE (op0
) != REG
1840 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1841 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1845 if (reload_in_progress
|| reload_completed
)
1848 temp
= gen_reg_rtx (DImode
);
1850 if (GET_CODE (op1
) != CONST_DOUBLE
1851 && GET_CODE (op1
) != CONST_INT
)
1853 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1857 if (GET_CODE (op1
) == CONST_DOUBLE
)
1859 #if HOST_BITS_PER_WIDE_INT == 64
1860 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1861 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1863 high_bits
= CONST_DOUBLE_HIGH (op1
);
1864 low_bits
= CONST_DOUBLE_LOW (op1
);
1869 #if HOST_BITS_PER_WIDE_INT == 64
1870 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1871 low_bits
= (INTVAL (op1
) & 0xffffffff);
1873 high_bits
= ((INTVAL (op1
) < 0) ?
1876 low_bits
= INTVAL (op1
);
1880 /* low_bits bits 0 --> 31
1881 high_bits bits 32 --> 63 */
1883 analyze_64bit_constant (high_bits
, low_bits
,
1884 &highest_bit_set
, &lowest_bit_set
,
1885 &all_bits_between_are_set
);
1887 /* First try for a 2-insn sequence. */
1889 /* These situations are preferred because the optimizer can
1890 * do more things with them:
1892 * sllx %reg, shift, %reg
1894 * srlx %reg, shift, %reg
1895 * 3) mov some_small_const, %reg
1896 * sllx %reg, shift, %reg
1898 if (((highest_bit_set
== 63
1899 || lowest_bit_set
== 0)
1900 && all_bits_between_are_set
!= 0)
1901 || ((highest_bit_set
- lowest_bit_set
) < 12))
1903 HOST_WIDE_INT the_const
= -1;
1904 int shift
= lowest_bit_set
;
1906 if ((highest_bit_set
!= 63
1907 && lowest_bit_set
!= 0)
1908 || all_bits_between_are_set
== 0)
1911 create_simple_focus_bits (high_bits
, low_bits
,
1914 else if (lowest_bit_set
== 0)
1915 shift
= -(63 - highest_bit_set
);
1917 if (! SPARC_SIMM13_P (the_const
))
1920 emit_insn (gen_safe_SET64 (temp
, the_const
));
1922 emit_insn (gen_rtx_SET (VOIDmode
,
1924 gen_rtx_ASHIFT (DImode
,
1928 emit_insn (gen_rtx_SET (VOIDmode
,
1930 gen_rtx_LSHIFTRT (DImode
,
1932 GEN_INT (-shift
))));
1938 /* Now a range of 22 or less bits set somewhere.
1939 * 1) sethi %hi(focus_bits), %reg
1940 * sllx %reg, shift, %reg
1941 * 2) sethi %hi(focus_bits), %reg
1942 * srlx %reg, shift, %reg
1944 if ((highest_bit_set
- lowest_bit_set
) < 21)
1946 unsigned HOST_WIDE_INT focus_bits
=
1947 create_simple_focus_bits (high_bits
, low_bits
,
1948 lowest_bit_set
, 10);
1950 if (! SPARC_SETHI_P (focus_bits
))
1953 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
1955 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1956 if (lowest_bit_set
< 10)
1957 emit_insn (gen_rtx_SET (VOIDmode
,
1959 gen_rtx_LSHIFTRT (DImode
, temp
,
1960 GEN_INT (10 - lowest_bit_set
))));
1961 else if (lowest_bit_set
> 10)
1962 emit_insn (gen_rtx_SET (VOIDmode
,
1964 gen_rtx_ASHIFT (DImode
, temp
,
1965 GEN_INT (lowest_bit_set
- 10))));
1971 /* 1) sethi %hi(low_bits), %reg
1972 * or %reg, %lo(low_bits), %reg
1973 * 2) sethi %hi(~low_bits), %reg
1974 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1977 || high_bits
== 0xffffffff)
1979 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1980 (high_bits
== 0xffffffff));
1984 /* Now, try 3-insn sequences. */
1986 /* 1) sethi %hi(high_bits), %reg
1987 * or %reg, %lo(high_bits), %reg
1988 * sllx %reg, 32, %reg
1992 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1996 /* We may be able to do something quick
1997 when the constant is negated, so try that. */
1998 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1999 (~low_bits
) & 0xfffffc00))
2001 /* NOTE: The trailing bits get XOR'd so we need the
2002 non-negated bits, not the negated ones. */
2003 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2005 if ((((~high_bits
) & 0xffffffff) == 0
2006 && ((~low_bits
) & 0x80000000) == 0)
2007 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2008 && ((~low_bits
) & 0x80000000) != 0))
2010 int fast_int
= (~low_bits
& 0xffffffff);
2012 if ((SPARC_SETHI_P (fast_int
)
2013 && (~high_bits
& 0xffffffff) == 0)
2014 || SPARC_SIMM13_P (fast_int
))
2015 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2017 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2022 #if HOST_BITS_PER_WIDE_INT == 64
2023 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2024 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2026 negated_const
= gen_rtx_CONST_DOUBLE (DImode
, const0_rtx
,
2027 (~low_bits
) & 0xfffffc00,
2028 (~high_bits
) & 0xffffffff);
2030 sparc_emit_set_const64 (temp
, negated_const
);
2033 /* If we are XOR'ing with -1, then we should emit a one's complement
2034 instead. This way the combiner will notice logical operations
2035 such as ANDN later on and substitute. */
2036 if (trailing_bits
== 0x3ff)
2038 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2039 gen_rtx_NOT (DImode
, temp
)));
2043 emit_insn (gen_rtx_SET (VOIDmode
,
2045 gen_safe_XOR64 (temp
,
2046 (-0x400 | trailing_bits
))));
2051 /* 1) sethi %hi(xxx), %reg
2052 * or %reg, %lo(xxx), %reg
2053 * sllx %reg, yyy, %reg
2055 * ??? This is just a generalized version of the low_bits==0
2056 * thing above, FIXME...
2058 if ((highest_bit_set
- lowest_bit_set
) < 32)
2060 unsigned HOST_WIDE_INT focus_bits
=
2061 create_simple_focus_bits (high_bits
, low_bits
,
2064 /* We can't get here in this state. */
2065 if (highest_bit_set
< 32
2066 || lowest_bit_set
>= 32)
2069 /* So what we know is that the set bits straddle the
2070 middle of the 64-bit word. */
2071 sparc_emit_set_const64_quick2 (op0
, temp
,
2077 /* 1) sethi %hi(high_bits), %reg
2078 * or %reg, %lo(high_bits), %reg
2079 * sllx %reg, 32, %reg
2080 * or %reg, low_bits, %reg
2082 if (SPARC_SIMM13_P(low_bits
)
2083 && ((int)low_bits
> 0))
2085 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2089 /* The easiest way when all else fails, is full decomposition. */
2091 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2092 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2094 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2097 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2098 return the mode to be used for the comparison. For floating-point,
2099 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2100 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2101 processing is needed. */
2104 select_cc_mode (op
, x
, y
)
2107 rtx y ATTRIBUTE_UNUSED
;
2109 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2135 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2136 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2138 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2139 return CCX_NOOVmode
;
2145 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2152 /* X and Y are two things to compare using CODE. Emit the compare insn and
2153 return the rtx for the cc reg in the proper mode. */
2156 gen_compare_reg (code
, x
, y
)
2160 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2163 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2164 fcc regs (cse can't tell they're really call clobbered regs and will
2165 remove a duplicate comparison even if there is an intervening function
2166 call - it will then try to reload the cc reg via an int reg which is why
2167 we need the movcc patterns). It is possible to provide the movcc
2168 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2169 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2170 to tell cse that CCFPE mode registers (even pseudos) are call
2173 /* ??? This is an experiment. Rather than making changes to cse which may
2174 or may not be easy/clean, we do our own cse. This is possible because
2175 we will generate hard registers. Cse knows they're call clobbered (it
2176 doesn't know the same thing about pseudos). If we guess wrong, no big
2177 deal, but if we win, great! */
2179 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2180 #if 1 /* experiment */
2183 /* We cycle through the registers to ensure they're all exercised. */
2184 static int next_fcc_reg
= 0;
2185 /* Previous x,y for each fcc reg. */
2186 static rtx prev_args
[4][2];
2188 /* Scan prev_args for x,y. */
2189 for (reg
= 0; reg
< 4; reg
++)
2190 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2195 prev_args
[reg
][0] = x
;
2196 prev_args
[reg
][1] = y
;
2197 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2199 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2202 cc_reg
= gen_reg_rtx (mode
);
2203 #endif /* ! experiment */
2204 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2205 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2207 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2209 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2210 gen_rtx_COMPARE (mode
, x
, y
)));
2215 /* This function is used for v9 only.
2216 CODE is the code for an Scc's comparison.
2217 OPERANDS[0] is the target of the Scc insn.
2218 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2219 been generated yet).
2221 This function is needed to turn
2224 (gt (reg:CCX 100 %icc)
2228 (gt:DI (reg:CCX 100 %icc)
2231 IE: The instruction recognizer needs to see the mode of the comparison to
2232 find the right instruction. We could use "gt:DI" right in the
2233 define_expand, but leaving it out allows us to handle DI, SI, etc.
2235 We refer to the global sparc compare operands sparc_compare_op0 and
2236 sparc_compare_op1. */
2239 gen_v9_scc (compare_code
, operands
)
2240 enum rtx_code compare_code
;
2241 register rtx
*operands
;
2246 && (GET_MODE (sparc_compare_op0
) == DImode
2247 || GET_MODE (operands
[0]) == DImode
))
2250 /* Handle the case where operands[0] == sparc_compare_op0.
2251 We "early clobber" the result. */
2252 if (REGNO (operands
[0]) == REGNO (sparc_compare_op0
))
2254 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2255 emit_move_insn (op0
, sparc_compare_op0
);
2258 op0
= sparc_compare_op0
;
2259 /* For consistency in the following. */
2260 op1
= sparc_compare_op1
;
2262 /* Try to use the movrCC insns. */
2264 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2265 && op1
== const0_rtx
2266 && v9_regcmp_p (compare_code
))
2268 /* Special case for op0 != 0. This can be done with one instruction if
2269 operands[0] == sparc_compare_op0. We don't assume they are equal
2272 if (compare_code
== NE
2273 && GET_MODE (operands
[0]) == DImode
2274 && GET_MODE (op0
) == DImode
)
2276 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], op0
));
2277 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2278 gen_rtx_IF_THEN_ELSE (DImode
,
2279 gen_rtx_fmt_ee (compare_code
, DImode
,
2286 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2287 if (GET_MODE (op0
) != DImode
)
2289 temp
= gen_reg_rtx (DImode
);
2290 convert_move (temp
, op0
, 0);
2294 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2295 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2296 gen_rtx_fmt_ee (compare_code
, DImode
,
2304 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2306 switch (GET_MODE (operands
[1]))
2316 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2317 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2318 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2319 gen_rtx_fmt_ee (compare_code
,
2320 GET_MODE (operands
[1]),
2321 operands
[1], const0_rtx
),
2322 const1_rtx
, operands
[0])));
2327 /* Emit a conditional jump insn for the v9 architecture using comparison code
2328 CODE and jump target LABEL.
2329 This function exists to take advantage of the v9 brxx insns. */
2332 emit_v9_brxx_insn (code
, op0
, label
)
2336 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2338 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2339 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2341 gen_rtx_LABEL_REF (VOIDmode
, label
),
2345 /* Generate a DFmode part of a hard TFmode register.
2346 REG is the TFmode hard register, LOW is 1 for the
2347 low 64bit of the register and 0 otherwise.
2350 gen_df_reg (reg
, low
)
2354 int regno
= REGNO (reg
);
2356 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2357 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2358 return gen_rtx_REG (DFmode
, regno
);
2361 /* Return nonzero if a return peephole merging return with
2362 setting of output register is ok. */
2364 leaf_return_peephole_ok ()
2366 return (actual_fsize
== 0);
2369 /* Return nonzero if TRIAL can go into the function epilogue's
2370 delay slot. SLOT is the slot we are trying to fill. */
2373 eligible_for_epilogue_delay (trial
, slot
)
2382 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2385 if (get_attr_length (trial
) != 1)
2388 /* If there are any call-saved registers, we should scan TRIAL if it
2389 does not reference them. For now just make it easy. */
2393 /* In the case of a true leaf function, anything can go into the delay slot.
2394 A delay slot only exists however if the frame size is zero, otherwise
2395 we will put an insn to adjust the stack after the return. */
2396 if (current_function_uses_only_leaf_regs
)
2398 if (leaf_return_peephole_ok ())
2399 return ((get_attr_in_uncond_branch_delay (trial
)
2400 == IN_BRANCH_DELAY_TRUE
));
2404 pat
= PATTERN (trial
);
2406 /* Otherwise, only operations which can be done in tandem with
2407 a `restore' or `return' insn can go into the delay slot. */
2408 if (GET_CODE (SET_DEST (pat
)) != REG
2409 || REGNO (SET_DEST (pat
)) < 24)
2412 /* If this instruction sets up floating point register and we have a return
2413 instruction, it can probably go in. But restore will not work
2415 if (REGNO (SET_DEST (pat
)) >= 32)
2417 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2418 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2423 /* The set of insns matched here must agree precisely with the set of
2424 patterns paired with a RETURN in sparc.md. */
2426 src
= SET_SRC (pat
);
2428 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2429 if (arith_operand (src
, GET_MODE (src
)))
2432 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2434 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2437 /* This matches "*return_di". */
2438 else if (arith_double_operand (src
, GET_MODE (src
)))
2439 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2441 /* This matches "*return_sf_no_fpu". */
2442 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2443 && register_operand (src
, SFmode
))
2446 /* If we have return instruction, anything that does not use
2447 local or output registers and can go into a delay slot wins. */
2448 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2449 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2452 /* This matches "*return_addsi". */
2453 else if (GET_CODE (src
) == PLUS
2454 && arith_operand (XEXP (src
, 0), SImode
)
2455 && arith_operand (XEXP (src
, 1), SImode
)
2456 && (register_operand (XEXP (src
, 0), SImode
)
2457 || register_operand (XEXP (src
, 1), SImode
)))
2460 /* This matches "*return_adddi". */
2461 else if (GET_CODE (src
) == PLUS
2462 && arith_double_operand (XEXP (src
, 0), DImode
)
2463 && arith_double_operand (XEXP (src
, 1), DImode
)
2464 && (register_operand (XEXP (src
, 0), DImode
)
2465 || register_operand (XEXP (src
, 1), DImode
)))
2468 /* This can match "*return_losum_[sd]i".
2469 Catch only some cases, so that return_losum* don't have
2471 else if (GET_CODE (src
) == LO_SUM
2472 && ! TARGET_CM_MEDMID
2473 && ((register_operand (XEXP (src
, 0), SImode
)
2474 && immediate_operand (XEXP (src
, 1), SImode
))
2476 && register_operand (XEXP (src
, 0), DImode
)
2477 && immediate_operand (XEXP (src
, 1), DImode
))))
2480 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2481 else if (GET_CODE (src
) == ASHIFT
2482 && (register_operand (XEXP (src
, 0), SImode
)
2483 || register_operand (XEXP (src
, 0), DImode
))
2484 && XEXP (src
, 1) == const1_rtx
)
2490 /* Return nonzero if TRIAL can go into the sibling call
2494 eligible_for_sibcall_delay (trial
)
2499 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2502 if (get_attr_length (trial
) != 1 || profile_block_flag
== 2)
2505 pat
= PATTERN (trial
);
2507 if (current_function_uses_only_leaf_regs
)
2509 /* If the tail call is done using the call instruction,
2510 we have to restore %o7 in the delay slot. */
2511 if ((TARGET_ARCH64
&& ! TARGET_CM_MEDLOW
) || flag_pic
)
2514 /* %g1 is used to build the function address */
2515 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2521 /* Otherwise, only operations which can be done in tandem with
2522 a `restore' insn can go into the delay slot. */
2523 if (GET_CODE (SET_DEST (pat
)) != REG
2524 || REGNO (SET_DEST (pat
)) < 24
2525 || REGNO (SET_DEST (pat
)) >= 32)
2528 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2530 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2533 src
= SET_SRC (pat
);
2535 if (arith_operand (src
, GET_MODE (src
)))
2538 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2540 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2543 else if (arith_double_operand (src
, GET_MODE (src
)))
2544 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2546 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2547 && register_operand (src
, SFmode
))
2550 else if (GET_CODE (src
) == PLUS
2551 && arith_operand (XEXP (src
, 0), SImode
)
2552 && arith_operand (XEXP (src
, 1), SImode
)
2553 && (register_operand (XEXP (src
, 0), SImode
)
2554 || register_operand (XEXP (src
, 1), SImode
)))
2557 else if (GET_CODE (src
) == PLUS
2558 && arith_double_operand (XEXP (src
, 0), DImode
)
2559 && arith_double_operand (XEXP (src
, 1), DImode
)
2560 && (register_operand (XEXP (src
, 0), DImode
)
2561 || register_operand (XEXP (src
, 1), DImode
)))
2564 else if (GET_CODE (src
) == LO_SUM
2565 && ! TARGET_CM_MEDMID
2566 && ((register_operand (XEXP (src
, 0), SImode
)
2567 && immediate_operand (XEXP (src
, 1), SImode
))
2569 && register_operand (XEXP (src
, 0), DImode
)
2570 && immediate_operand (XEXP (src
, 1), DImode
))))
2573 else if (GET_CODE (src
) == ASHIFT
2574 && (register_operand (XEXP (src
, 0), SImode
)
2575 || register_operand (XEXP (src
, 0), DImode
))
2576 && XEXP (src
, 1) == const1_rtx
)
2583 check_return_regs (x
)
2586 switch (GET_CODE (x
))
2589 return IN_OR_GLOBAL_P (x
);
2604 if (check_return_regs (XEXP (x
, 1)) == 0)
2609 return check_return_regs (XEXP (x
, 0));
2617 /* Return 1 if TRIAL references only in and global registers. */
2619 eligible_for_return_delay (trial
)
2622 if (GET_CODE (PATTERN (trial
)) != SET
)
2625 return check_return_regs (PATTERN (trial
));
2629 short_branch (uid1
, uid2
)
2632 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2634 /* Leave a few words of "slop". */
2635 if (delta
>= -1023 && delta
<= 1022)
2641 /* Return non-zero if REG is not used after INSN.
2642 We assume REG is a reload reg, and therefore does
2643 not live past labels or calls or jumps. */
2645 reg_unused_after (reg
, insn
)
2649 enum rtx_code code
, prev_code
= UNKNOWN
;
2651 while ((insn
= NEXT_INSN (insn
)))
2653 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2656 code
= GET_CODE (insn
);
2657 if (GET_CODE (insn
) == CODE_LABEL
)
2660 if (GET_RTX_CLASS (code
) == 'i')
2662 rtx set
= single_set (insn
);
2663 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2666 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2668 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2676 /* The table we use to reference PIC data. */
2677 static rtx global_offset_table
;
2679 /* The function we use to get at it. */
2680 static rtx get_pc_symbol
;
2681 static char get_pc_symbol_name
[256];
2683 /* Ensure that we are not using patterns that are not OK with PIC. */
2692 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
2693 || (GET_CODE (recog_data
.operand
[i
]) == CONST
2694 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
2695 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
2696 == global_offset_table
)
2697 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
2706 /* Return true if X is an address which needs a temporary register when
2707 reloaded while generating PIC code. */
2710 pic_address_needs_scratch (x
)
2713 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2714 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2715 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2716 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2717 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2723 /* Legitimize PIC addresses. If the address is already position-independent,
2724 we return ORIG. Newly generated position-independent addresses go into a
2725 reg. This is REG if non zero, otherwise we allocate register(s) as
2729 legitimize_pic_address (orig
, mode
, reg
)
2731 enum machine_mode mode ATTRIBUTE_UNUSED
;
2734 if (GET_CODE (orig
) == SYMBOL_REF
)
2736 rtx pic_ref
, address
;
2741 if (reload_in_progress
|| reload_completed
)
2744 reg
= gen_reg_rtx (Pmode
);
2749 /* If not during reload, allocate another temp reg here for loading
2750 in the address, so that these instructions can be optimized
2752 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
2753 ? reg
: gen_reg_rtx (Pmode
));
2755 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2756 won't get confused into thinking that these two instructions
2757 are loading in the true address of the symbol. If in the
2758 future a PIC rtx exists, that should be used instead. */
2759 if (Pmode
== SImode
)
2761 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
2762 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
2766 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
2767 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
2774 pic_ref
= gen_rtx_MEM (Pmode
,
2775 gen_rtx_PLUS (Pmode
,
2776 pic_offset_table_rtx
, address
));
2777 current_function_uses_pic_offset_table
= 1;
2778 RTX_UNCHANGING_P (pic_ref
) = 1;
2779 insn
= emit_move_insn (reg
, pic_ref
);
2780 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2782 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2786 else if (GET_CODE (orig
) == CONST
)
2790 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2791 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2796 if (reload_in_progress
|| reload_completed
)
2799 reg
= gen_reg_rtx (Pmode
);
2802 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2804 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2805 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2806 base
== reg
? 0 : reg
);
2811 if (GET_CODE (offset
) == CONST_INT
)
2813 if (SMALL_INT (offset
))
2814 return plus_constant_for_output (base
, INTVAL (offset
));
2815 else if (! reload_in_progress
&& ! reload_completed
)
2816 offset
= force_reg (Pmode
, offset
);
2818 /* If we reach here, then something is seriously wrong. */
2821 return gen_rtx_PLUS (Pmode
, base
, offset
);
2823 else if (GET_CODE (orig
) == LABEL_REF
)
2824 /* ??? Why do we do this? */
2825 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2826 the register is live instead, in case it is eliminated. */
2827 current_function_uses_pic_offset_table
= 1;
2832 /* Emit special PIC prologues. */
2835 load_pic_register ()
2837 /* Labels to get the PC in the prologue of this function. */
2838 int orig_flag_pic
= flag_pic
;
2843 /* If we havn't emitted the special get_pc helper function, do so now. */
2844 if (get_pc_symbol_name
[0] == 0)
2848 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
2851 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
2853 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
2854 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LGETPC", 0);
2855 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file
);
2858 /* Initialize every time through, since we can't easily
2859 know this to be permanent. */
2860 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2861 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
2864 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
2867 flag_pic
= orig_flag_pic
;
2869 /* Need to emit this whether or not we obey regdecls,
2870 since setjmp/longjmp can cause life info to screw up.
2871 ??? In the case where we don't obey regdecls, this is not sufficient
2872 since we may not fall out the bottom. */
2873 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2876 /* Return 1 if RTX is a MEM which is known to be aligned to at
2877 least an 8 byte boundary. */
2880 mem_min_alignment (mem
, desired
)
2884 rtx addr
, base
, offset
;
2886 /* If it's not a MEM we can't accept it. */
2887 if (GET_CODE (mem
) != MEM
)
2890 addr
= XEXP (mem
, 0);
2891 base
= offset
= NULL_RTX
;
2892 if (GET_CODE (addr
) == PLUS
)
2894 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2896 base
= XEXP (addr
, 0);
2898 /* What we are saying here is that if the base
2899 REG is aligned properly, the compiler will make
2900 sure any REG based index upon it will be so
2902 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2903 offset
= XEXP (addr
, 1);
2905 offset
= const0_rtx
;
2908 else if (GET_CODE (addr
) == REG
)
2911 offset
= const0_rtx
;
2914 if (base
!= NULL_RTX
)
2916 int regno
= REGNO (base
);
2918 if (regno
!= FRAME_POINTER_REGNUM
2919 && regno
!= STACK_POINTER_REGNUM
)
2921 /* Check if the compiler has recorded some information
2922 about the alignment of the base REG. If reload has
2923 completed, we already matched with proper alignments.
2924 If not running global_alloc, reload might give us
2925 unaligned pointer to local stack though. */
2927 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
2928 || (optimize
&& reload_completed
))
2929 && (INTVAL (offset
) & (desired
- 1)) == 0)
2934 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
2938 else if (! TARGET_UNALIGNED_DOUBLES
2939 || CONSTANT_P (addr
)
2940 || GET_CODE (addr
) == LO_SUM
)
2942 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2943 is true, in which case we can only assume that an access is aligned if
2944 it is to a constant address, or the address involves a LO_SUM. */
2948 /* An obviously unaligned address. */
2953 /* Vectors to keep interesting information about registers where it can easily
2954 be got. We use to use the actual mode value as the bit number, but there
2955 are more than 32 modes now. Instead we use two tables: one indexed by
2956 hard register number, and one indexed by mode. */
2958 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2959 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2960 mapped into one sparc_mode_class mode. */
2962 enum sparc_mode_class
{
2963 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
2964 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
2968 /* Modes for single-word and smaller quantities. */
2969 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2971 /* Modes for double-word and smaller quantities. */
2972 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2974 /* Modes for quad-word and smaller quantities. */
2975 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2977 /* Modes for 8-word and smaller quantities. */
2978 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
2980 /* Modes for single-float quantities. We must allow any single word or
2981 smaller quantity. This is because the fix/float conversion instructions
2982 take integer inputs/outputs from the float registers. */
2983 #define SF_MODES (S_MODES)
2985 /* Modes for double-float and smaller quantities. */
2986 #define DF_MODES (S_MODES | D_MODES)
2988 /* Modes for double-float only quantities. */
2989 #define DF_MODES_NO_S (D_MODES)
2991 /* Modes for quad-float only quantities. */
2992 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2994 /* Modes for quad-float and smaller quantities. */
2995 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2997 /* Modes for quad-float and double-float quantities. */
2998 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3000 /* Modes for quad-float pair only quantities. */
3001 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3003 /* Modes for quad-float pairs and smaller quantities. */
3004 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3006 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3008 /* Modes for condition codes. */
3009 #define CC_MODES (1 << (int) CC_MODE)
3010 #define CCFP_MODES (1 << (int) CCFP_MODE)
3012 /* Value is 1 if register/mode pair is acceptable on sparc.
3013 The funny mixture of D and T modes is because integer operations
3014 do not specially operate on tetra quantities, so non-quad-aligned
3015 registers can hold quadword quantities (except %o4 and %i4 because
3016 they cross fixed registers). */
3018 /* This points to either the 32 bit or the 64 bit version. */
3019 int *hard_regno_mode_classes
;
3021 static int hard_32bit_mode_classes
[] = {
3022 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3023 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3024 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3025 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3027 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3028 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3029 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3030 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3032 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3033 and none can hold SFmode/SImode values. */
3034 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3035 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3036 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3037 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3040 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3046 static int hard_64bit_mode_classes
[] = {
3047 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3048 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3049 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3050 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3052 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3053 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3054 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3055 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3057 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3058 and none can hold SFmode/SImode values. */
3059 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3060 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3061 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3062 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3065 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3071 int sparc_mode_class
[NUM_MACHINE_MODES
];
3073 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3080 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3082 switch (GET_MODE_CLASS (i
))
3085 case MODE_PARTIAL_INT
:
3086 case MODE_COMPLEX_INT
:
3087 if (GET_MODE_SIZE (i
) <= 4)
3088 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3089 else if (GET_MODE_SIZE (i
) == 8)
3090 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3091 else if (GET_MODE_SIZE (i
) == 16)
3092 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3093 else if (GET_MODE_SIZE (i
) == 32)
3094 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3096 sparc_mode_class
[i
] = 0;
3099 case MODE_COMPLEX_FLOAT
:
3100 if (GET_MODE_SIZE (i
) <= 4)
3101 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3102 else if (GET_MODE_SIZE (i
) == 8)
3103 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3104 else if (GET_MODE_SIZE (i
) == 16)
3105 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3106 else if (GET_MODE_SIZE (i
) == 32)
3107 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3109 sparc_mode_class
[i
] = 0;
3113 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3114 we must explicitly check for them here. */
3115 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3116 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3117 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3118 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3119 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3121 sparc_mode_class
[i
] = 0;
3127 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3129 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3131 /* Initialize the array used by REGNO_REG_CLASS. */
3132 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3134 if (i
< 16 && TARGET_V8PLUS
)
3135 sparc_regno_reg_class
[i
] = I64_REGS
;
3137 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3139 sparc_regno_reg_class
[i
] = FP_REGS
;
3141 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3143 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3145 sparc_regno_reg_class
[i
] = NO_REGS
;
3149 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3150 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3151 v9 int regs as it simplifies the code. */
3154 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3164 if (TARGET_ARCH64
&& high
<= 32)
3166 for (i
= low
; i
< high
; i
++)
3168 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3170 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
3171 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3172 if (dwarf2out_do_frame ())
3173 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3180 for (i
= low
; i
< high
; i
+= 2)
3182 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3184 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3186 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
3187 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3188 if (dwarf2out_do_frame ())
3190 char *l
= dwarf2out_cfi_label ();
3191 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3192 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3198 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3199 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3200 if (dwarf2out_do_frame ())
3201 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3207 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3209 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3210 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3211 if (dwarf2out_do_frame ())
3212 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3221 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3223 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3224 v9 int regs as it simplifies the code. */
3227 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3236 if (TARGET_ARCH64
&& high
<= 32)
3238 for (i
= low
; i
< high
; i
++)
3240 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3241 fprintf (file
, "\tldx\t[%s+%d], %s\n",
3242 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3248 for (i
= low
; i
< high
; i
+= 2)
3250 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3251 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3252 fprintf (file
, "\tldd\t[%s+%d], %s\n",
3253 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3256 fprintf (file
, "\tld\t[%s+%d],%s\n",
3257 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3259 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3260 fprintf (file
, "\tld\t[%s+%d],%s\n",
3261 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3268 /* Compute the frame size required by the function. This function is called
3269 during the reload pass and also by output_function_prologue(). */
3272 compute_frame_size (size
, leaf_function
)
3277 int outgoing_args_size
= (current_function_outgoing_args_size
3278 + REG_PARM_STACK_SPACE (current_function_decl
));
3280 if (TARGET_EPILOGUE
)
3282 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3283 even to v9 int regs to be consistent with save_regs/restore_regs. */
3287 for (i
= 0; i
< 8; i
++)
3288 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3293 for (i
= 0; i
< 8; i
+= 2)
3294 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3295 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3299 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3300 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3301 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3305 /* Set up values for use in `function_epilogue'. */
3306 num_gfregs
= n_regs
;
3308 if (leaf_function
&& n_regs
== 0
3309 && size
== 0 && current_function_outgoing_args_size
== 0)
3311 actual_fsize
= apparent_fsize
= 0;
3315 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3316 The stack bias (if any) is taken out to undo its effects. */
3317 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ SPARC_STACK_BIAS
+ 7) & -8;
3318 apparent_fsize
+= n_regs
* 4;
3319 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3322 /* Make sure nothing can clobber our register windows.
3323 If a SAVE must be done, or there is a stack-local variable,
3324 the register window area must be allocated.
3325 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3326 if (leaf_function
== 0 || size
> 0)
3327 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3329 return SPARC_STACK_ALIGN (actual_fsize
);
3332 /* Build a (32 bit) big number in a register. */
3333 /* ??? We may be able to use the set macro here too. */
3336 build_big_number (file
, num
, reg
)
3341 if (num
>= 0 || ! TARGET_ARCH64
)
3343 fprintf (file
, "\tsethi\t%%hi(%d), %s\n", num
, reg
);
3344 if ((num
& 0x3ff) != 0)
3345 fprintf (file
, "\tor\t%s, %%lo(%d), %s\n", reg
, num
, reg
);
3347 else /* num < 0 && TARGET_ARCH64 */
3349 /* Sethi does not sign extend, so we must use a little trickery
3350 to use it for negative numbers. Invert the constant before
3351 loading it in, then use xor immediate to invert the loaded bits
3352 (along with the upper 32 bits) to the desired constant. This
3353 works because the sethi and immediate fields overlap. */
3356 int low
= -0x400 + (asize
& 0x3FF);
3358 fprintf (file
, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3359 inv
, reg
, reg
, low
, reg
);
3363 /* Output any necessary .register pseudo-ops. */
3365 sparc_output_scratch_registers (file
)
3366 FILE *file ATTRIBUTE_UNUSED
;
3368 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3374 /* Check if %g[2367] were used without
3375 .register being printed for them already. */
3376 for (i
= 2; i
< 8; i
++)
3378 if (regs_ever_live
[i
]
3379 && ! sparc_hard_reg_printed
[i
])
3381 sparc_hard_reg_printed
[i
] = 1;
3382 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3389 /* Output code for the function prologue. */
3392 output_function_prologue (file
, size
, leaf_function
)
3397 sparc_output_scratch_registers (file
);
3399 /* Need to use actual_fsize, since we are also allocating
3400 space for our callee (and our own register save area). */
3401 actual_fsize
= compute_frame_size (size
, leaf_function
);
3405 frame_base_name
= "%sp";
3406 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3410 frame_base_name
= "%fp";
3411 frame_base_offset
= SPARC_STACK_BIAS
;
3414 /* This is only for the human reader. */
3415 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3417 if (actual_fsize
== 0)
3419 else if (! leaf_function
)
3421 if (actual_fsize
<= 4096)
3422 fprintf (file
, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize
);
3423 else if (actual_fsize
<= 8192)
3425 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
3426 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3430 build_big_number (file
, -actual_fsize
, "%g1");
3431 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
3434 else /* leaf function */
3436 if (actual_fsize
<= 4096)
3437 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
);
3438 else if (actual_fsize
<= 8192)
3440 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
3441 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3445 build_big_number (file
, -actual_fsize
, "%g1");
3446 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
3450 if (dwarf2out_do_frame () && actual_fsize
)
3452 char *label
= dwarf2out_cfi_label ();
3454 /* The canonical frame address refers to the top of the frame. */
3455 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3456 : FRAME_POINTER_REGNUM
),
3459 if (! leaf_function
)
3461 /* Note the register window save. This tells the unwinder that
3462 it needs to restore the window registers from the previous
3463 frame's window save area at 0(cfa). */
3464 dwarf2out_window_save (label
);
3466 /* The return address (-8) is now in %i7. */
3467 dwarf2out_return_reg (label
, 31);
3471 /* If doing anything with PIC, do it now. */
3473 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3475 /* Call saved registers are saved just above the outgoing argument area. */
3478 int offset
, real_offset
, n_regs
;
3481 real_offset
= -apparent_fsize
;
3482 offset
= -apparent_fsize
+ frame_base_offset
;
3483 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3485 /* ??? This might be optimized a little as %g1 might already have a
3486 value close enough that a single add insn will do. */
3487 /* ??? Although, all of this is probably only a temporary fix
3488 because if %g1 can hold a function result, then
3489 output_function_epilogue will lose (the result will get
3491 build_big_number (file
, offset
, "%g1");
3492 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3498 base
= frame_base_name
;
3502 if (TARGET_EPILOGUE
&& ! leaf_function
)
3503 /* ??? Originally saved regs 0-15 here. */
3504 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3505 else if (leaf_function
)
3506 /* ??? Originally saved regs 0-31 here. */
3507 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3508 if (TARGET_EPILOGUE
)
3509 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3514 if (leaf_function
&& actual_fsize
!= 0)
3516 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3517 if (! TARGET_EPILOGUE
)
3518 leaf_label
= gen_label_rtx ();
3522 /* Output code to restore any call saved registers. */
3525 output_restore_regs (file
, leaf_function
)
3532 offset
= -apparent_fsize
+ frame_base_offset
;
3533 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3535 build_big_number (file
, offset
, "%g1");
3536 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3542 base
= frame_base_name
;
3546 if (TARGET_EPILOGUE
&& ! leaf_function
)
3547 /* ??? Originally saved regs 0-15 here. */
3548 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3549 else if (leaf_function
)
3550 /* ??? Originally saved regs 0-31 here. */
3551 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3552 if (TARGET_EPILOGUE
)
3553 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
3556 /* Output code for the function epilogue. */
3559 output_function_epilogue (file
, size
, leaf_function
)
3561 int size ATTRIBUTE_UNUSED
;
3568 emit_label_after (leaf_label
, get_last_insn ());
3569 final_scan_insn (get_last_insn (), file
, 0, 0, 1);
3572 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3573 else if (profile_block_flag
== 2)
3575 FUNCTION_BLOCK_PROFILER_EXIT(file
);
3579 else if (current_function_epilogue_delay_list
== 0)
3581 /* If code does not drop into the epilogue, we need
3582 do nothing except output pending case vectors. */
3583 rtx insn
= get_last_insn ();
3584 if (GET_CODE (insn
) == NOTE
)
3585 insn
= prev_nonnote_insn (insn
);
3586 if (insn
&& GET_CODE (insn
) == BARRIER
)
3587 goto output_vectors
;
3591 output_restore_regs (file
, leaf_function
);
3593 /* Work out how to skip the caller's unimp instruction if required. */
3595 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
3597 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
3599 if (TARGET_EPILOGUE
|| leaf_label
)
3601 int old_target_epilogue
= TARGET_EPILOGUE
;
3602 target_flags
&= ~old_target_epilogue
;
3604 if (! leaf_function
)
3606 /* If we wound up with things in our delay slot, flush them here. */
3607 if (current_function_epilogue_delay_list
)
3609 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
3611 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
3613 epilogue_renumber (&delay
, 0);
3614 fputs (SKIP_CALLERS_UNIMP_P
3615 ? "\treturn\t%i7+12\n"
3616 : "\treturn\t%i7+8\n", file
);
3617 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0), file
, 1, 0, 0);
3621 rtx insn
= emit_jump_insn_after (gen_rtx_RETURN (VOIDmode
),
3625 if (GET_CODE (delay
) != SET
)
3628 src
= SET_SRC (delay
);
3629 if (GET_CODE (src
) == ASHIFT
)
3631 if (XEXP (src
, 1) != const1_rtx
)
3633 SET_SRC (delay
) = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
3637 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
,
3638 gen_rtvec (2, delay
, PATTERN (insn
)));
3639 final_scan_insn (insn
, file
, 1, 0, 1);
3642 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
3643 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
3645 fprintf (file
, "\t%s\n\trestore\n", ret
);
3647 /* All of the following cases are for leaf functions. */
3648 else if (current_function_epilogue_delay_list
)
3650 /* eligible_for_epilogue_delay_slot ensures that if this is a
3651 leaf function, then we will only have insn in the delay slot
3652 if the frame size is zero, thus no adjust for the stack is
3654 if (actual_fsize
!= 0)
3656 fprintf (file
, "\t%s\n", ret
);
3657 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
3660 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3661 avoid generating confusing assembly language output. */
3662 else if (actual_fsize
== 0)
3663 fprintf (file
, "\t%s\n\tnop\n", ret
);
3664 else if (actual_fsize
<= 4096)
3665 fprintf (file
, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret
, actual_fsize
);
3666 else if (actual_fsize
<= 8192)
3667 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3668 ret
, actual_fsize
- 4096);
3669 else if ((actual_fsize
& 0x3ff) == 0)
3670 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3673 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3674 actual_fsize
, actual_fsize
, ret
);
3675 target_flags
|= old_target_epilogue
;
3679 sparc_output_deferred_case_vectors ();
3682 /* Output a sibling call. */
3685 output_sibcall (insn
, call_operand
)
3686 rtx insn
, call_operand
;
3688 int leaf_regs
= current_function_uses_only_leaf_regs
;
3690 int delay_slot
= dbr_sequence_length () > 0;
3694 /* Call to restore global regs might clobber
3695 the delay slot. Instead of checking for this
3696 output the delay slot now. */
3699 rtx delay
= NEXT_INSN (insn
);
3704 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
3705 PATTERN (delay
) = gen_blockage ();
3706 INSN_CODE (delay
) = -1;
3709 output_restore_regs (asm_out_file
, leaf_regs
);
3712 operands
[0] = call_operand
;
3716 #ifdef HAVE_AS_RELAX_OPTION
3717 /* If as and ld are relaxing tail call insns into branch always,
3718 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
3719 be optimized. With sethi/jmpl as nor ld has no easy way how to
3720 find out if somebody does not branch between the sethi and jmpl. */
3723 int spare_slot
= ((TARGET_ARCH32
|| TARGET_CM_MEDLOW
) && ! flag_pic
);
3727 if ((actual_fsize
|| ! spare_slot
) && delay_slot
)
3729 rtx delay
= NEXT_INSN (insn
);
3734 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
3735 PATTERN (delay
) = gen_blockage ();
3736 INSN_CODE (delay
) = -1;
3741 if (actual_fsize
<= 4096)
3742 size
= actual_fsize
;
3743 else if (actual_fsize
<= 8192)
3745 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file
);
3746 size
= actual_fsize
- 4096;
3748 else if ((actual_fsize
& 0x3ff) == 0)
3749 fprintf (asm_out_file
,
3750 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
3754 fprintf (asm_out_file
,
3755 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
3756 actual_fsize
, actual_fsize
);
3757 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file
);
3762 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands
);
3763 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands
);
3765 fprintf (asm_out_file
, "\t sub\t%%sp, -%d, %%sp\n", size
);
3766 else if (! delay_slot
)
3767 fputs ("\t nop\n", asm_out_file
);
3772 fprintf (asm_out_file
, "\tsub\t%%sp, -%d, %%sp\n", size
);
3773 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
3774 it into branch if possible. */
3775 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands
);
3776 output_asm_insn ("call\t%a0, 0", operands
);
3777 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands
);
3782 output_asm_insn ("call\t%a0, 0", operands
);
3785 rtx delay
= NEXT_INSN (insn
), pat
;
3790 pat
= PATTERN (delay
);
3791 if (GET_CODE (pat
) != SET
)
3794 operands
[0] = SET_DEST (pat
);
3795 pat
= SET_SRC (pat
);
3796 switch (GET_CODE (pat
))
3799 operands
[1] = XEXP (pat
, 0);
3800 operands
[2] = XEXP (pat
, 1);
3801 output_asm_insn (" restore %r1, %2, %Y0", operands
);
3804 operands
[1] = XEXP (pat
, 0);
3805 operands
[2] = XEXP (pat
, 1);
3806 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
3809 operands
[1] = XEXP (pat
, 0);
3810 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
3814 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
3817 PATTERN (delay
) = gen_blockage ();
3818 INSN_CODE (delay
) = -1;
3821 fputs ("\t restore\n", asm_out_file
);
3825 /* Functions for handling argument passing.
3827 For v8 the first six args are normally in registers and the rest are
3828 pushed. Any arg that starts within the first 6 words is at least
3829 partially passed in a register unless its data type forbids.
3831 For v9, the argument registers are laid out as an array of 16 elements
3832 and arguments are added sequentially. The first 6 int args and up to the
3833 first 16 fp args (depending on size) are passed in regs.
3835 Slot Stack Integral Float Float in structure Double Long Double
3836 ---- ----- -------- ----- ------------------ ------ -----------
3837 15 [SP+248] %f31 %f30,%f31 %d30
3838 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3839 13 [SP+232] %f27 %f26,%f27 %d26
3840 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3841 11 [SP+216] %f23 %f22,%f23 %d22
3842 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3843 9 [SP+200] %f19 %f18,%f19 %d18
3844 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3845 7 [SP+184] %f15 %f14,%f15 %d14
3846 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3847 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3848 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3849 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3850 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3851 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3852 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3854 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3856 Integral arguments are always passed as 64 bit quantities appropriately
3859 Passing of floating point values is handled as follows.
3860 If a prototype is in scope:
3861 If the value is in a named argument (i.e. not a stdarg function or a
3862 value not part of the `...') then the value is passed in the appropriate
3864 If the value is part of the `...' and is passed in one of the first 6
3865 slots then the value is passed in the appropriate int reg.
3866 If the value is part of the `...' and is not passed in one of the first 6
3867 slots then the value is passed in memory.
3868 If a prototype is not in scope:
3869 If the value is one of the first 6 arguments the value is passed in the
3870 appropriate integer reg and the appropriate fp reg.
3871 If the value is not one of the first 6 arguments the value is passed in
3872 the appropriate fp reg and in memory.
3875 /* Maximum number of int regs for args. */
3876 #define SPARC_INT_ARG_MAX 6
3877 /* Maximum number of fp regs for args. */
3878 #define SPARC_FP_ARG_MAX 16
3880 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3882 /* Handle the INIT_CUMULATIVE_ARGS macro.
3883 Initialize a variable CUM of type CUMULATIVE_ARGS
3884 for a call to a function whose data type is FNTYPE.
3885 For a library call, FNTYPE is 0. */
3888 init_cumulative_args (cum
, fntype
, libname
, indirect
)
3889 CUMULATIVE_ARGS
*cum
;
3891 rtx libname ATTRIBUTE_UNUSED
;
3892 int indirect ATTRIBUTE_UNUSED
;
3895 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
3896 cum
->libcall_p
= fntype
== 0;
3899 /* Compute the slot number to pass an argument in.
3900 Returns the slot number or -1 if passing on the stack.
3902 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3903 the preceding args and about the function being called.
3904 MODE is the argument's machine mode.
3905 TYPE is the data type of the argument (as a tree).
3906 This is null for libcalls where that information may
3908 NAMED is nonzero if this argument is a named parameter
3909 (otherwise it is an extra parameter matching an ellipsis).
3910 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3911 *PREGNO records the register number to use if scalar type.
3912 *PPADDING records the amount of padding needed in words. */
3915 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
3916 const CUMULATIVE_ARGS
*cum
;
3917 enum machine_mode mode
;
3924 int regbase
= (incoming_p
3925 ? SPARC_INCOMING_INT_ARG_FIRST
3926 : SPARC_OUTGOING_INT_ARG_FIRST
);
3927 int slotno
= cum
->words
;
3932 if (type
!= 0 && TREE_ADDRESSABLE (type
))
3935 && type
!= 0 && mode
== BLKmode
3936 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
3942 /* MODE is VOIDmode when generating the actual call.
3946 case QImode
: case CQImode
:
3947 case HImode
: case CHImode
:
3948 case SImode
: case CSImode
:
3949 case DImode
: case CDImode
:
3950 case TImode
: case CTImode
:
3951 if (slotno
>= SPARC_INT_ARG_MAX
)
3953 regno
= regbase
+ slotno
;
3956 case SFmode
: case SCmode
:
3957 case DFmode
: case DCmode
:
3958 case TFmode
: case TCmode
:
3961 if (slotno
>= SPARC_INT_ARG_MAX
)
3963 regno
= regbase
+ slotno
;
3967 if ((mode
== TFmode
|| mode
== TCmode
)
3968 && (slotno
& 1) != 0)
3969 slotno
++, *ppadding
= 1;
3970 if (TARGET_FPU
&& named
)
3972 if (slotno
>= SPARC_FP_ARG_MAX
)
3974 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
3980 if (slotno
>= SPARC_INT_ARG_MAX
)
3982 regno
= regbase
+ slotno
;
3988 /* For sparc64, objects requiring 16 byte alignment get it. */
3991 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
3992 slotno
++, *ppadding
= 1;
3996 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
3998 if (slotno
>= SPARC_INT_ARG_MAX
)
4000 regno
= regbase
+ slotno
;
4005 int intregs_p
= 0, fpregs_p
= 0;
4006 /* The ABI obviously doesn't specify how packed
4007 structures are passed. These are defined to be passed
4008 in int regs if possible, otherwise memory. */
4011 /* First see what kinds of registers we need. */
4012 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4014 if (TREE_CODE (field
) == FIELD_DECL
)
4016 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4021 if (DECL_PACKED (field
))
4025 if (packed_p
|| !named
)
4026 fpregs_p
= 0, intregs_p
= 1;
4028 /* If all arg slots are filled, then must pass on stack. */
4029 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4031 /* If there are only int args and all int arg slots are filled,
4032 then must pass on stack. */
4033 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4035 /* Note that even if all int arg slots are filled, fp members may
4036 still be passed in regs if such regs are available.
4037 *PREGNO isn't set because there may be more than one, it's up
4038 to the caller to compute them. */
4051 /* Handle recursive register counting for structure field layout. */
4053 struct function_arg_record_value_parms
4056 int slotno
, named
, regbase
;
4061 static void function_arg_record_value_3
4062 PARAMS ((HOST_WIDE_INT
, struct function_arg_record_value_parms
*));
4063 static void function_arg_record_value_2
4064 PARAMS ((tree
, HOST_WIDE_INT
,
4065 struct function_arg_record_value_parms
*));
4066 static void function_arg_record_value_1
4067 PARAMS ((tree
, HOST_WIDE_INT
,
4068 struct function_arg_record_value_parms
*));
4069 static rtx function_arg_record_value
4070 PARAMS ((tree
, enum machine_mode
, int, int, int));
4073 function_arg_record_value_1 (type
, startbitpos
, parms
)
4075 HOST_WIDE_INT startbitpos
;
4076 struct function_arg_record_value_parms
*parms
;
4080 /* The ABI obviously doesn't specify how packed structures are
4081 passed. These are defined to be passed in int regs if possible,
4082 otherwise memory. */
4085 /* We need to compute how many registers are needed so we can
4086 allocate the PARALLEL but before we can do that we need to know
4087 whether there are any packed fields. If there are, int regs are
4088 used regardless of whether there are fp values present. */
4089 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4091 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4098 /* Compute how many registers we need. */
4099 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4101 if (TREE_CODE (field
) == FIELD_DECL
)
4103 HOST_WIDE_INT bitpos
= startbitpos
;
4105 if (DECL_SIZE (field
) != 0
4106 && host_integerp (bit_position (field
), 1))
4107 bitpos
+= int_bit_position (field
);
4109 /* ??? FIXME: else assume zero offset. */
4111 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4112 function_arg_record_value_1 (TREE_TYPE (field
), bitpos
, parms
);
4113 else if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4118 if (parms
->intoffset
!= -1)
4120 int intslots
, this_slotno
;
4122 intslots
= (bitpos
- parms
->intoffset
+ BITS_PER_WORD
- 1)
4124 this_slotno
= parms
->slotno
+ parms
->intoffset
4127 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4128 intslots
= MAX (intslots
, 0);
4129 parms
->nregs
+= intslots
;
4130 parms
->intoffset
= -1;
4133 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4134 If it wasn't true we wouldn't be here. */
4139 if (parms
->intoffset
== -1)
4140 parms
->intoffset
= bitpos
;
4146 /* Handle recursive structure field register assignment. */
4149 function_arg_record_value_3 (bitpos
, parms
)
4150 HOST_WIDE_INT bitpos
;
4151 struct function_arg_record_value_parms
*parms
;
4153 enum machine_mode mode
;
4155 int this_slotno
, intslots
, intoffset
;
4158 if (parms
->intoffset
== -1)
4161 intoffset
= parms
->intoffset
;
4162 parms
->intoffset
= -1;
4164 intslots
= (bitpos
- intoffset
+ BITS_PER_WORD
- 1) / BITS_PER_WORD
;
4165 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4167 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4171 /* If this is the trailing part of a word, only load that much into
4172 the register. Otherwise load the whole register. Note that in
4173 the latter case we may pick up unwanted bits. It's not a problem
4174 at the moment but may wish to revisit. */
4176 if (intoffset
% BITS_PER_WORD
!= 0)
4177 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4182 intoffset
/= BITS_PER_UNIT
;
4185 regno
= parms
->regbase
+ this_slotno
;
4186 reg
= gen_rtx_REG (mode
, regno
);
4187 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4188 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4191 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4195 while (intslots
> 0);
4199 function_arg_record_value_2 (type
, startbitpos
, parms
)
4201 HOST_WIDE_INT startbitpos
;
4202 struct function_arg_record_value_parms
*parms
;
4207 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4209 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4216 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4218 if (TREE_CODE (field
) == FIELD_DECL
)
4220 HOST_WIDE_INT bitpos
= startbitpos
;
4222 if (DECL_SIZE (field
) != 0
4223 && host_integerp (bit_position (field
), 1))
4224 bitpos
+= int_bit_position (field
);
4226 /* ??? FIXME: else assume zero offset. */
4228 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4229 function_arg_record_value_2 (TREE_TYPE (field
), bitpos
, parms
);
4230 else if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4235 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4238 function_arg_record_value_3 (bitpos
, parms
);
4240 reg
= gen_rtx_REG (DECL_MODE (field
),
4241 (SPARC_FP_ARG_FIRST
+ this_slotno
* 2
4242 + (DECL_MODE (field
) == SFmode
4243 && (bitpos
& 32) != 0)));
4244 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4245 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4246 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4251 if (parms
->intoffset
== -1)
4252 parms
->intoffset
= bitpos
;
4259 function_arg_record_value (type
, mode
, slotno
, named
, regbase
)
4261 enum machine_mode mode
;
4262 int slotno
, named
, regbase
;
4264 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4265 struct function_arg_record_value_parms parms
;
4268 parms
.ret
= NULL_RTX
;
4269 parms
.slotno
= slotno
;
4270 parms
.named
= named
;
4271 parms
.regbase
= regbase
;
4273 /* Compute how many registers we need. */
4275 parms
.intoffset
= 0;
4276 function_arg_record_value_1 (type
, 0, &parms
);
4278 if (parms
.intoffset
!= -1)
4280 int intslots
, this_slotno
;
4282 intslots
= (typesize
*BITS_PER_UNIT
- parms
.intoffset
+ BITS_PER_WORD
- 1)
4284 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4286 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4287 intslots
= MAX (intslots
, 0);
4289 parms
.nregs
+= intslots
;
4291 nregs
= parms
.nregs
;
4293 /* Allocate the vector and handle some annoying special cases. */
4296 /* ??? Empty structure has no value? Duh? */
4299 /* Though there's nothing really to store, return a word register
4300 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4301 leads to breakage due to the fact that there are zero bytes to
4303 return gen_rtx_REG (mode
, regbase
);
4307 /* ??? C++ has structures with no fields, and yet a size. Give up
4308 for now and pass everything back in integer registers. */
4309 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4311 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4312 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4317 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nregs
));
4319 /* Fill in the entries. */
4321 parms
.intoffset
= 0;
4322 function_arg_record_value_2 (type
, 0, &parms
);
4323 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4325 if (parms
.nregs
!= nregs
)
4331 /* Handle the FUNCTION_ARG macro.
4332 Determine where to put an argument to a function.
4333 Value is zero to push the argument on the stack,
4334 or a hard register in which to store the argument.
4336 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4337 the preceding args and about the function being called.
4338 MODE is the argument's machine mode.
4339 TYPE is the data type of the argument (as a tree).
4340 This is null for libcalls where that information may
4342 NAMED is nonzero if this argument is a named parameter
4343 (otherwise it is an extra parameter matching an ellipsis).
4344 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4347 function_arg (cum
, mode
, type
, named
, incoming_p
)
4348 const CUMULATIVE_ARGS
*cum
;
4349 enum machine_mode mode
;
4354 int regbase
= (incoming_p
4355 ? SPARC_INCOMING_INT_ARG_FIRST
4356 : SPARC_OUTGOING_INT_ARG_FIRST
);
4357 int slotno
, regno
, padding
;
4360 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
4368 reg
= gen_rtx_REG (mode
, regno
);
4372 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4373 but also have the slot allocated for them.
4374 If no prototype is in scope fp values in register slots get passed
4375 in two places, either fp regs and int regs or fp regs and memory. */
4376 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4377 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4378 && SPARC_FP_REG_P (regno
))
4380 reg
= gen_rtx_REG (mode
, regno
);
4381 if (cum
->prototype_p
|| cum
->libcall_p
)
4383 /* "* 2" because fp reg numbers are recorded in 4 byte
4386 /* ??? This will cause the value to be passed in the fp reg and
4387 in the stack. When a prototype exists we want to pass the
4388 value in the reg but reserve space on the stack. That's an
4389 optimization, and is deferred [for a bit]. */
4390 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
4391 return gen_rtx_PARALLEL (mode
,
4393 gen_rtx_EXPR_LIST (VOIDmode
,
4394 NULL_RTX
, const0_rtx
),
4395 gen_rtx_EXPR_LIST (VOIDmode
,
4399 /* ??? It seems that passing back a register even when past
4400 the area declared by REG_PARM_STACK_SPACE will allocate
4401 space appropriately, and will not copy the data onto the
4402 stack, exactly as we desire.
4404 This is due to locate_and_pad_parm being called in
4405 expand_call whenever reg_parm_stack_space > 0, which
4406 while benefical to our example here, would seem to be
4407 in error from what had been intended. Ho hum... -- r~ */
4415 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
4419 /* On incoming, we don't need to know that the value
4420 is passed in %f0 and %i0, and it confuses other parts
4421 causing needless spillage even on the simplest cases. */
4425 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
4426 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
4428 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4429 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
4431 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4435 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4436 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4437 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4441 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
4443 /* Structures up to 16 bytes in size are passed in arg slots on the
4444 stack and are promoted to registers where possible. */
4446 if (int_size_in_bytes (type
) > 16)
4447 abort (); /* shouldn't get here */
4449 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
4451 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4453 enum machine_mode mode
;
4454 int bytes
= int_size_in_bytes (type
);
4459 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4460 reg
= gen_rtx_REG (mode
, regno
);
4464 /* Scalar or complex int. */
4465 reg
= gen_rtx_REG (mode
, regno
);
4471 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4472 For an arg passed partly in registers and partly in memory,
4473 this is the number of registers used.
4474 For args passed entirely in registers or entirely in memory, zero.
4476 Any arg that starts in the first 6 regs but won't entirely fit in them
4477 needs partial registers on v8. On v9, structures with integer
4478 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4479 values that begin in the last fp reg [where "last fp reg" varies with the
4480 mode] will be split between that reg and memory. */
4483 function_arg_partial_nregs (cum
, mode
, type
, named
)
4484 const CUMULATIVE_ARGS
*cum
;
4485 enum machine_mode mode
;
4489 int slotno
, regno
, padding
;
4491 /* We pass 0 for incoming_p here, it doesn't matter. */
4492 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4499 if ((slotno
+ (mode
== BLKmode
4500 ? ROUND_ADVANCE (int_size_in_bytes (type
))
4501 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
4502 > NPARM_REGS (SImode
))
4503 return NPARM_REGS (SImode
) - slotno
;
4508 if (type
&& AGGREGATE_TYPE_P (type
))
4510 int size
= int_size_in_bytes (type
);
4511 int align
= TYPE_ALIGN (type
);
4514 slotno
+= slotno
& 1;
4515 if (size
> 8 && size
<= 16
4516 && slotno
== SPARC_INT_ARG_MAX
- 1)
4519 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
4520 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4523 if (GET_MODE_ALIGNMENT (mode
) == 128)
4525 slotno
+= slotno
& 1;
4526 if (slotno
== SPARC_INT_ARG_MAX
- 2)
4531 if (slotno
== SPARC_INT_ARG_MAX
- 1)
4535 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4537 if (GET_MODE_ALIGNMENT (mode
) == 128)
4538 slotno
+= slotno
& 1;
4539 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
4547 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4548 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4549 quad-precision floats by invisible reference.
4550 v9: Aggregates greater than 16 bytes are passed by reference.
4551 For Pascal, also pass arrays by reference. */
4554 function_arg_pass_by_reference (cum
, mode
, type
, named
)
4555 const CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
4556 enum machine_mode mode
;
4558 int named ATTRIBUTE_UNUSED
;
4562 return ((type
&& AGGREGATE_TYPE_P (type
))
4563 || mode
== TFmode
|| mode
== TCmode
);
4567 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
4568 /* Consider complex values as aggregates, so care for TCmode. */
4569 || GET_MODE_SIZE (mode
) > 16
4570 || (type
&& AGGREGATE_TYPE_P (type
)
4571 && int_size_in_bytes (type
) > 16));
4575 /* Handle the FUNCTION_ARG_ADVANCE macro.
4576 Update the data in CUM to advance over an argument
4577 of mode MODE and data type TYPE.
4578 TYPE is null for libcalls where that information may not be available. */
4581 function_arg_advance (cum
, mode
, type
, named
)
4582 CUMULATIVE_ARGS
*cum
;
4583 enum machine_mode mode
;
4587 int slotno
, regno
, padding
;
4589 /* We pass 0 for incoming_p here, it doesn't matter. */
4590 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4592 /* If register required leading padding, add it. */
4594 cum
->words
+= padding
;
4598 cum
->words
+= (mode
!= BLKmode
4599 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4600 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4604 if (type
&& AGGREGATE_TYPE_P (type
))
4606 int size
= int_size_in_bytes (type
);
4610 else if (size
<= 16)
4612 else /* passed by reference */
4615 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
4619 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4621 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4625 cum
->words
+= (mode
!= BLKmode
4626 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4627 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4632 /* Handle the FUNCTION_ARG_PADDING macro.
4633 For the 64 bit ABI structs are always stored left shifted in their
4637 function_arg_padding (mode
, type
)
4638 enum machine_mode mode
;
4641 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
4644 /* This is the default definition. */
4645 return (! BYTES_BIG_ENDIAN
4648 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
4649 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
4650 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
4651 ? downward
: upward
));
4654 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4655 For v9, function return values are subject to the same rules as arguments,
4656 except that up to 32-bytes may be returned in registers. */
4659 function_value (type
, mode
, incoming_p
)
4661 enum machine_mode mode
;
4665 int regbase
= (incoming_p
4666 ? SPARC_OUTGOING_INT_ARG_FIRST
4667 : SPARC_INCOMING_INT_ARG_FIRST
);
4669 if (TARGET_ARCH64
&& type
)
4671 if (TREE_CODE (type
) == RECORD_TYPE
)
4673 /* Structures up to 32 bytes in size are passed in registers,
4674 promoted to fp registers where possible. */
4676 if (int_size_in_bytes (type
) > 32)
4677 abort (); /* shouldn't get here */
4679 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
4681 else if (TREE_CODE (type
) == UNION_TYPE
)
4683 int bytes
= int_size_in_bytes (type
);
4688 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4693 && GET_MODE_CLASS (mode
) == MODE_INT
4694 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
4695 && type
&& TREE_CODE (type
) != UNION_TYPE
)
4699 regno
= BASE_RETURN_VALUE_REG (mode
);
4701 regno
= BASE_OUTGOING_VALUE_REG (mode
);
4703 return gen_rtx_REG (mode
, regno
);
4706 /* Do what is necessary for `va_start'. We look at the current function
4707 to determine if stdarg or varargs is used and return the address of
4708 the first unnamed parameter. */
4711 sparc_builtin_saveregs ()
4713 int first_reg
= current_function_args_info
.words
;
4717 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
4718 emit_move_insn (gen_rtx_MEM (word_mode
,
4719 gen_rtx_PLUS (Pmode
,
4721 GEN_INT (STACK_POINTER_OFFSET
4722 + UNITS_PER_WORD
* regno
))),
4723 gen_rtx_REG (word_mode
,
4724 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
4726 address
= gen_rtx_PLUS (Pmode
,
4728 GEN_INT (STACK_POINTER_OFFSET
4729 + UNITS_PER_WORD
* first_reg
));
4731 if (current_function_check_memory_usage
4732 && first_reg
< NPARM_REGS (word_mode
))
4733 emit_library_call (chkr_set_right_libfunc
, 1, VOIDmode
, 3,
4735 GEN_INT (UNITS_PER_WORD
4736 * (NPARM_REGS (word_mode
) - first_reg
)),
4737 TYPE_MODE (sizetype
), GEN_INT (MEMORY_USE_RW
),
4738 TYPE_MODE (integer_type_node
));
4743 /* Implement `va_start' for varargs and stdarg. */
4746 sparc_va_start (stdarg_p
, valist
, nextarg
)
4747 int stdarg_p ATTRIBUTE_UNUSED
;
4751 nextarg
= expand_builtin_saveregs ();
4752 std_expand_builtin_va_start (1, valist
, nextarg
);
4755 /* Implement `va_arg'. */
4758 sparc_va_arg (valist
, type
)
4761 HOST_WIDE_INT size
, rsize
, align
;
4766 /* Round up sizeof(type) to a word. */
4767 size
= int_size_in_bytes (type
);
4768 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4773 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
4774 align
= 2 * UNITS_PER_WORD
;
4776 if (AGGREGATE_TYPE_P (type
))
4781 size
= rsize
= UNITS_PER_WORD
;
4789 if (AGGREGATE_TYPE_P (type
)
4790 || TYPE_MODE (type
) == TFmode
4791 || TYPE_MODE (type
) == TCmode
)
4794 size
= rsize
= UNITS_PER_WORD
;
4798 /* ??? The old va-sparc.h implementation, for 8 byte objects
4799 copied stuff to a temporary -- I don't see that that
4800 provides any more alignment than the stack slot did. */
4807 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
4808 build_int_2 (align
- 1, 0)));
4809 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
4810 build_int_2 (-align
, -1)));
4813 addr
= incr
= save_expr (incr
);
4814 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
4816 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
4817 build_int_2 (rsize
- size
, 0)));
4819 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
4820 build_int_2 (rsize
, 0)));
4822 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
4823 TREE_SIDE_EFFECTS (incr
) = 1;
4824 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4826 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
4830 addr_rtx
= force_reg (Pmode
, addr_rtx
);
4831 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
4832 MEM_ALIAS_SET (addr_rtx
) = get_varargs_alias_set ();
4838 /* Return the string to output a conditional branch to LABEL, which is
4839 the operand number of the label. OP is the conditional expression.
4840 XEXP (OP, 0) is assumed to be a condition code register (integer or
4841 floating point) and its mode specifies what kind of comparison we made.
4843 REVERSED is non-zero if we should reverse the sense of the comparison.
4845 ANNUL is non-zero if we should generate an annulling branch.
4847 NOOP is non-zero if we have to follow this branch by a noop.
4849 INSN, if set, is the insn. */
4852 output_cbranch (op
, label
, reversed
, annul
, noop
, insn
)
4855 int reversed
, annul
, noop
;
4858 static char string
[32];
4859 enum rtx_code code
= GET_CODE (op
);
4860 rtx cc_reg
= XEXP (op
, 0);
4861 enum machine_mode mode
= GET_MODE (cc_reg
);
4862 static char v8_labelno
[] = "%lX";
4863 static char v9_icc_labelno
[] = "%%icc, %lX";
4864 static char v9_xcc_labelno
[] = "%%xcc, %lX";
4865 static char v9_fcc_labelno
[] = "%%fccX, %lY";
4868 int labeloff
, spaces
= 8;
4872 /* Reversal of FP compares takes care -- an ordered compare
4873 becomes an unordered compare and vice versa. */
4874 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4875 code
= reverse_condition_maybe_unordered (code
);
4877 code
= reverse_condition (code
);
4880 /* Start by writing the branch condition. */
4881 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4932 /* ??? !v9: FP branches cannot be preceded by another floating point
4933 insn. Because there is currently no concept of pre-delay slots,
4934 we can fix this only by always emitting a nop before a floating
4939 strcpy (string
, "nop\n\t");
4940 strcat (string
, branch
);
4953 if (mode
== CC_NOOVmode
)
4965 if (mode
== CC_NOOVmode
)
4986 strcpy (string
, branch
);
4988 spaces
-= strlen (branch
);
4990 /* Now add the annulling, the label, and a possible noop. */
4993 strcat (string
, ",a");
5000 labelno
= v8_labelno
;
5006 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PRED
, NULL_RTX
)))
5009 INTVAL (XEXP (note
, 0)) & ATTR_FLAG_likely
? ",pt" : ",pn");
5014 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5017 labelno
= v9_fcc_labelno
;
5018 /* Set the char indicating the number of the fcc reg to use. */
5019 labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5021 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5022 labelno
= v9_xcc_labelno
;
5024 labelno
= v9_icc_labelno
;
5026 /* Set the char indicating the number of the operand containing the
5028 labelno
[labeloff
] = label
+ '0';
5030 strcat (string
, "\t");
5032 strcat (string
, " ");
5033 strcat (string
, labelno
);
5036 strcat (string
, "\n\tnop");
5041 /* Emit a library call comparison between floating point X and Y.
5042 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5043 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5044 values as arguments instead of the TFmode registers themselves,
5045 that's why we cannot call emit_float_lib_cmp. */
5047 sparc_emit_float_lib_cmp (x
, y
, comparison
)
5049 enum rtx_code comparison
;
5052 rtx slot0
, slot1
, result
, tem
, tem2
;
5053 enum machine_mode mode
;
5058 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5062 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5066 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5070 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5074 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5078 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5089 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5099 if (GET_CODE (x
) != MEM
)
5101 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5102 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
5107 if (GET_CODE (y
) != MEM
)
5109 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5110 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
5115 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), 1,
5117 XEXP (slot0
, 0), Pmode
,
5118 XEXP (slot1
, 0), Pmode
);
5124 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), 1,
5126 x
, TFmode
, y
, TFmode
);
5132 /* Immediately move the result of the libcall into a pseudo
5133 register so reload doesn't clobber the value if it needs
5134 the return register for a spill reg. */
5135 result
= gen_reg_rtx (mode
);
5136 emit_move_insn (result
, hard_libcall_value (mode
));
5141 emit_cmp_insn (result
, const0_rtx
, NE
,
5142 NULL_RTX
, mode
, 0, 0);
5146 emit_cmp_insn (result
, GEN_INT(3),
5147 (comparison
== UNORDERED
) ? EQ
: NE
,
5148 NULL_RTX
, mode
, 0, 0);
5152 emit_cmp_insn (result
, const1_rtx
,
5153 (comparison
== UNGT
) ? GT
: NE
,
5154 NULL_RTX
, mode
, 0, 0);
5157 emit_cmp_insn (result
, const2_rtx
, NE
,
5158 NULL_RTX
, mode
, 0, 0);
5161 tem
= gen_reg_rtx (mode
);
5163 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
5165 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
5166 emit_cmp_insn (tem
, const0_rtx
, NE
,
5167 NULL_RTX
, mode
, 0, 0);
5171 tem
= gen_reg_rtx (mode
);
5173 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
5175 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
5176 tem2
= gen_reg_rtx (mode
);
5178 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
5180 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
5181 emit_cmp_insn (tem2
, const0_rtx
,
5182 (comparison
== UNEQ
) ? EQ
: NE
,
5183 NULL_RTX
, mode
, 0, 0);
5188 /* Return the string to output a conditional branch to LABEL, testing
5189 register REG. LABEL is the operand number of the label; REG is the
5190 operand number of the reg. OP is the conditional expression. The mode
5191 of REG says what kind of comparison we made.
5193 REVERSED is non-zero if we should reverse the sense of the comparison.
5195 ANNUL is non-zero if we should generate an annulling branch.
5197 NOOP is non-zero if we have to follow this branch by a noop. */
5200 output_v9branch (op
, reg
, label
, reversed
, annul
, noop
, insn
)
5203 int reversed
, annul
, noop
;
5206 static char string
[20];
5207 enum rtx_code code
= GET_CODE (op
);
5208 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
5209 static char labelno
[] = "%X, %lX";
5213 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5215 code
= reverse_condition (code
), reversed
= 0;
5217 /* Only 64 bit versions of these instructions exist. */
5221 /* Start by writing the branch condition. */
5226 strcpy (string
, "brnz");
5231 strcpy (string
, "brz");
5236 strcpy (string
, "brgez");
5241 strcpy (string
, "brlz");
5246 strcpy (string
, "brlez");
5251 strcpy (string
, "brgz");
5259 /* Now add the annulling, reg, label, and nop. */
5262 strcat (string
, ",a");
5266 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PRED
, NULL_RTX
)))
5269 INTVAL (XEXP (note
, 0)) & ATTR_FLAG_likely
? ",pt" : ",pn");
5273 labelno
[1] = reg
+ '0';
5274 labelno
[6] = label
+ '0';
5276 strcat (string
, "\t");
5278 strcat (string
, " ");
5279 strcat (string
, labelno
);
5282 strcat (string
, "\n\tnop");
5287 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5288 Such instructions cannot be used in the delay slot of return insn on v9.
5289 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5293 epilogue_renumber (where
, test
)
5294 register rtx
*where
;
5297 register const char *fmt
;
5299 register enum rtx_code code
;
5304 code
= GET_CODE (*where
);
5309 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
5311 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
5312 *where
= gen_rtx (REG
, GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
5324 fmt
= GET_RTX_FORMAT (code
);
5326 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5331 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5332 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
5335 else if (fmt
[i
] == 'e'
5336 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
5342 /* Output assembler code to return from a function. */
5345 output_return (operands
)
5348 rtx delay
= final_sequence
? XVECEXP (final_sequence
, 0, 1) : 0;
5352 operands
[0] = leaf_label
;
5355 else if (current_function_uses_only_leaf_regs
)
5357 /* No delay slot in a leaf function. */
5361 /* If we didn't allocate a frame pointer for the current function,
5362 the stack pointer might have been adjusted. Output code to
5365 operands
[0] = GEN_INT (actual_fsize
);
5367 /* Use sub of negated value in first two cases instead of add to
5368 allow actual_fsize == 4096. */
5370 if (actual_fsize
<= 4096)
5372 if (SKIP_CALLERS_UNIMP_P
)
5373 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5375 return "retl\n\tsub\t%%sp, -%0, %%sp";
5377 else if (actual_fsize
<= 8192)
5379 operands
[0] = GEN_INT (actual_fsize
- 4096);
5380 if (SKIP_CALLERS_UNIMP_P
)
5381 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
5383 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
5385 else if (SKIP_CALLERS_UNIMP_P
)
5387 if ((actual_fsize
& 0x3ff) != 0)
5388 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5390 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
5394 if ((actual_fsize
& 0x3ff) != 0)
5395 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
5397 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
5404 epilogue_renumber (&SET_DEST (PATTERN (delay
)), 0);
5405 epilogue_renumber (&SET_SRC (PATTERN (delay
)), 0);
5407 if (SKIP_CALLERS_UNIMP_P
)
5408 return "return\t%%i7+12%#";
5410 return "return\t%%i7+8%#";
5416 if (SKIP_CALLERS_UNIMP_P
)
5417 return "jmp\t%%i7+12\n\trestore";
5419 return "ret\n\trestore";
5423 /* Leaf functions and non-leaf functions have different needs. */
5426 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
5429 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
5431 static int *reg_alloc_orders
[] = {
5432 reg_leaf_alloc_order
,
5433 reg_nonleaf_alloc_order
};
5436 order_regs_for_local_alloc ()
5438 static int last_order_nonleaf
= 1;
5440 if (regs_ever_live
[15] != last_order_nonleaf
)
5442 last_order_nonleaf
= !last_order_nonleaf
;
5443 memcpy ((char *) reg_alloc_order
,
5444 (char *) reg_alloc_orders
[last_order_nonleaf
],
5445 FIRST_PSEUDO_REGISTER
* sizeof (int));
5449 /* Return 1 if REG and MEM are legitimate enough to allow the various
5450 mem<-->reg splits to be run. */
5453 sparc_splitdi_legitimate (reg
, mem
)
5457 /* Punt if we are here by mistake. */
5458 if (! reload_completed
)
5461 /* We must have an offsettable memory reference. */
5462 if (! offsettable_memref_p (mem
))
5465 /* If we have legitimate args for ldd/std, we do not want
5466 the split to happen. */
5467 if ((REGNO (reg
) % 2) == 0
5468 && mem_min_alignment (mem
, 8))
5475 /* Return 1 if x and y are some kind of REG and they refer to
5476 different hard registers. This test is guarenteed to be
5477 run after reload. */
5480 sparc_absnegfloat_split_legitimate (x
, y
)
5483 if (GET_CODE (x
) == SUBREG
)
5484 x
= alter_subreg (x
);
5485 if (GET_CODE (x
) != REG
)
5487 if (GET_CODE (y
) == SUBREG
)
5488 y
= alter_subreg (y
);
5489 if (GET_CODE (y
) != REG
)
5491 if (REGNO (x
) == REGNO (y
))
5496 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
5497 This makes them candidates for using ldd and std insns.
5499 Note reg1 and reg2 *must* be hard registers. */
5502 registers_ok_for_ldd_peep (reg1
, reg2
)
5505 /* We might have been passed a SUBREG. */
5506 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
5509 if (REGNO (reg1
) % 2 != 0)
5512 /* Integer ldd is deprecated in SPARC V9 */
5513 if (TARGET_V9
&& REGNO (reg1
) < 32)
5516 return (REGNO (reg1
) == REGNO (reg2
) - 1);
5519 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
5522 This can only happen when addr1 and addr2 are consecutive memory
5523 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
5524 64 bit boundary (addr1 % 8 == 0).
5526 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
5527 registers are assumed to *never* be properly aligned and are
5530 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
5531 need only check that the offset for addr1 % 8 == 0. */
5534 addrs_ok_for_ldd_peep (addr1
, addr2
)
5539 /* Extract a register number and offset (if used) from the first addr. */
5540 if (GET_CODE (addr1
) == PLUS
)
5542 /* If not a REG, return zero. */
5543 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
5547 reg1
= REGNO (XEXP (addr1
, 0));
5548 /* The offset must be constant! */
5549 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
5551 offset1
= INTVAL (XEXP (addr1
, 1));
5554 else if (GET_CODE (addr1
) != REG
)
5558 reg1
= REGNO (addr1
);
5559 /* This was a simple (mem (reg)) expression. Offset is 0. */
5563 /* Make sure the second address is a (mem (plus (reg) (const_int). */
5564 if (GET_CODE (addr2
) != PLUS
)
5567 if (GET_CODE (XEXP (addr2
, 0)) != REG
5568 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
5571 /* Only %fp and %sp are allowed. Additionally both addresses must
5572 use the same register. */
5573 if (reg1
!= FRAME_POINTER_REGNUM
&& reg1
!= STACK_POINTER_REGNUM
)
5576 if (reg1
!= REGNO (XEXP (addr2
, 0)))
5579 /* The first offset must be evenly divisible by 8 to ensure the
5580 address is 64 bit aligned. */
5581 if (offset1
% 8 != 0)
5584 /* The offset for the second addr must be 4 more than the first addr. */
5585 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
5588 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5593 /* Return 1 if reg is a pseudo, or is the first register in
5594 a hard register pair. This makes it a candidate for use in
5595 ldd and std insns. */
5598 register_ok_for_ldd (reg
)
5601 /* We might have been passed a SUBREG. */
5602 if (GET_CODE (reg
) != REG
)
5605 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
5606 return (REGNO (reg
) % 2 == 0);
5611 /* Print operand X (an rtx) in assembler syntax to file FILE.
5612 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5613 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5616 print_operand (file
, x
, code
)
5624 /* Output a 'nop' if there's nothing for the delay slot. */
5625 if (dbr_sequence_length () == 0)
5626 fputs ("\n\t nop", file
);
5629 /* Output an annul flag if there's nothing for the delay slot and we
5630 are optimizing. This is always used with '(' below. */
5631 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5632 this is a dbx bug. So, we only do this when optimizing. */
5633 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5634 Always emit a nop in case the next instruction is a branch. */
5635 if (dbr_sequence_length () == 0
5636 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
5640 /* Output a 'nop' if there's nothing for the delay slot and we are
5641 not optimizing. This is always used with '*' above. */
5642 if (dbr_sequence_length () == 0
5643 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
5644 fputs ("\n\t nop", file
);
5647 /* Output the Embedded Medium/Anywhere code model base register. */
5648 fputs (EMBMEDANY_BASE_REG
, file
);
5651 /* Print out what we are using as the frame pointer. This might
5652 be %fp, or might be %sp+offset. */
5653 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5654 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
5657 /* Adjust the operand to take into account a RESTORE operation. */
5658 if (GET_CODE (x
) == CONST_INT
)
5660 else if (GET_CODE (x
) != REG
)
5661 output_operand_lossage ("Invalid %%Y operand");
5662 else if (REGNO (x
) < 8)
5663 fputs (reg_names
[REGNO (x
)], file
);
5664 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
5665 fputs (reg_names
[REGNO (x
)-16], file
);
5667 output_operand_lossage ("Invalid %%Y operand");
5670 /* Print out the low order register name of a register pair. */
5671 if (WORDS_BIG_ENDIAN
)
5672 fputs (reg_names
[REGNO (x
)+1], file
);
5674 fputs (reg_names
[REGNO (x
)], file
);
5677 /* Print out the high order register name of a register pair. */
5678 if (WORDS_BIG_ENDIAN
)
5679 fputs (reg_names
[REGNO (x
)], file
);
5681 fputs (reg_names
[REGNO (x
)+1], file
);
5684 /* Print out the second register name of a register pair or quad.
5685 I.e., R (%o0) => %o1. */
5686 fputs (reg_names
[REGNO (x
)+1], file
);
5689 /* Print out the third register name of a register quad.
5690 I.e., S (%o0) => %o2. */
5691 fputs (reg_names
[REGNO (x
)+2], file
);
5694 /* Print out the fourth register name of a register quad.
5695 I.e., T (%o0) => %o3. */
5696 fputs (reg_names
[REGNO (x
)+3], file
);
5699 /* Print a condition code register. */
5700 if (REGNO (x
) == SPARC_ICC_REG
)
5702 /* We don't handle CC[X]_NOOVmode because they're not supposed
5704 if (GET_MODE (x
) == CCmode
)
5705 fputs ("%icc", file
);
5706 else if (GET_MODE (x
) == CCXmode
)
5707 fputs ("%xcc", file
);
5712 /* %fccN register */
5713 fputs (reg_names
[REGNO (x
)], file
);
5716 /* Print the operand's address only. */
5717 output_address (XEXP (x
, 0));
5720 /* In this case we need a register. Use %g0 if the
5721 operand is const0_rtx. */
5723 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
5725 fputs ("%g0", file
);
5732 switch (GET_CODE (x
))
5734 case IOR
: fputs ("or", file
); break;
5735 case AND
: fputs ("and", file
); break;
5736 case XOR
: fputs ("xor", file
); break;
5737 default: output_operand_lossage ("Invalid %%A operand");
5742 switch (GET_CODE (x
))
5744 case IOR
: fputs ("orn", file
); break;
5745 case AND
: fputs ("andn", file
); break;
5746 case XOR
: fputs ("xnor", file
); break;
5747 default: output_operand_lossage ("Invalid %%B operand");
5751 /* These are used by the conditional move instructions. */
5755 enum rtx_code rc
= GET_CODE (x
);
5759 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
5760 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5761 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
5763 rc
= reverse_condition (GET_CODE (x
));
5767 case NE
: fputs ("ne", file
); break;
5768 case EQ
: fputs ("e", file
); break;
5769 case GE
: fputs ("ge", file
); break;
5770 case GT
: fputs ("g", file
); break;
5771 case LE
: fputs ("le", file
); break;
5772 case LT
: fputs ("l", file
); break;
5773 case GEU
: fputs ("geu", file
); break;
5774 case GTU
: fputs ("gu", file
); break;
5775 case LEU
: fputs ("leu", file
); break;
5776 case LTU
: fputs ("lu", file
); break;
5777 case LTGT
: fputs ("lg", file
); break;
5778 case UNORDERED
: fputs ("u", file
); break;
5779 case ORDERED
: fputs ("o", file
); break;
5780 case UNLT
: fputs ("ul", file
); break;
5781 case UNLE
: fputs ("ule", file
); break;
5782 case UNGT
: fputs ("ug", file
); break;
5783 case UNGE
: fputs ("uge", file
); break;
5784 case UNEQ
: fputs ("ue", file
); break;
5785 default: output_operand_lossage (code
== 'c'
5786 ? "Invalid %%c operand"
5787 : "Invalid %%C operand");
5792 /* These are used by the movr instruction pattern. */
5796 enum rtx_code rc
= (code
== 'd'
5797 ? reverse_condition (GET_CODE (x
))
5801 case NE
: fputs ("ne", file
); break;
5802 case EQ
: fputs ("e", file
); break;
5803 case GE
: fputs ("gez", file
); break;
5804 case LT
: fputs ("lz", file
); break;
5805 case LE
: fputs ("lez", file
); break;
5806 case GT
: fputs ("gz", file
); break;
5807 default: output_operand_lossage (code
== 'd'
5808 ? "Invalid %%d operand"
5809 : "Invalid %%D operand");
5816 /* Print a sign-extended character. */
5817 int i
= INTVAL (x
) & 0xff;
5820 fprintf (file
, "%d", i
);
5825 /* Operand must be a MEM; write its address. */
5826 if (GET_CODE (x
) != MEM
)
5827 output_operand_lossage ("Invalid %%f operand");
5828 output_address (XEXP (x
, 0));
5832 /* Do nothing special. */
5836 /* Undocumented flag. */
5837 output_operand_lossage ("invalid operand output code");
5840 if (GET_CODE (x
) == REG
)
5841 fputs (reg_names
[REGNO (x
)], file
);
5842 else if (GET_CODE (x
) == MEM
)
5845 /* Poor Sun assembler doesn't understand absolute addressing. */
5846 if (CONSTANT_P (XEXP (x
, 0)))
5847 fputs ("%g0+", file
);
5848 output_address (XEXP (x
, 0));
5851 else if (GET_CODE (x
) == HIGH
)
5853 fputs ("%hi(", file
);
5854 output_addr_const (file
, XEXP (x
, 0));
5857 else if (GET_CODE (x
) == LO_SUM
)
5859 print_operand (file
, XEXP (x
, 0), 0);
5860 if (TARGET_CM_MEDMID
)
5861 fputs ("+%l44(", file
);
5863 fputs ("+%lo(", file
);
5864 output_addr_const (file
, XEXP (x
, 1));
5867 else if (GET_CODE (x
) == CONST_DOUBLE
5868 && (GET_MODE (x
) == VOIDmode
5869 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
5871 if (CONST_DOUBLE_HIGH (x
) == 0)
5872 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
5873 else if (CONST_DOUBLE_HIGH (x
) == -1
5874 && CONST_DOUBLE_LOW (x
) < 0)
5875 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
5877 output_operand_lossage ("long long constant not a valid immediate operand");
5879 else if (GET_CODE (x
) == CONST_DOUBLE
)
5880 output_operand_lossage ("floating point constant not a valid immediate operand");
5881 else { output_addr_const (file
, x
); }
5884 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5885 a 64 bit (DImode) value. */
5887 /* ??? If there is a 64 bit counterpart to .word that the assembler
5888 understands, then using that would simply this code greatly. */
5889 /* ??? We only output .xword's for symbols and only then in environments
5890 where the assembler can handle them. */
5893 output_double_int (file
, value
)
5897 if (GET_CODE (value
) == CONST_INT
)
5899 /* ??? This has endianness issues. */
5900 #if HOST_BITS_PER_WIDE_INT == 64
5901 HOST_WIDE_INT xword
= INTVAL (value
);
5902 HOST_WIDE_INT high
, low
;
5904 high
= (xword
>> 32) & 0xffffffff;
5905 low
= xword
& 0xffffffff;
5906 ASM_OUTPUT_INT (file
, GEN_INT (high
));
5907 ASM_OUTPUT_INT (file
, GEN_INT (low
));
5909 if (INTVAL (value
) < 0)
5910 ASM_OUTPUT_INT (file
, constm1_rtx
);
5912 ASM_OUTPUT_INT (file
, const0_rtx
);
5913 ASM_OUTPUT_INT (file
, value
);
5916 else if (GET_CODE (value
) == CONST_DOUBLE
)
5918 ASM_OUTPUT_INT (file
, GEN_INT (CONST_DOUBLE_HIGH (value
)));
5919 ASM_OUTPUT_INT (file
, GEN_INT (CONST_DOUBLE_LOW (value
)));
5921 else if (GET_CODE (value
) == SYMBOL_REF
5922 || GET_CODE (value
) == CONST
5923 || GET_CODE (value
) == PLUS
5924 || (TARGET_ARCH64
&&
5925 (GET_CODE (value
) == LABEL_REF
5926 || GET_CODE (value
) == CODE_LABEL
5927 || GET_CODE (value
) == MINUS
)))
5931 ASM_OUTPUT_INT (file
, const0_rtx
);
5932 ASM_OUTPUT_INT (file
, value
);
5936 fprintf (file
, "\t%s\t", ASM_LONGLONG
);
5937 output_addr_const (file
, value
);
5938 fprintf (file
, "\n");
5945 /* Return the value of a code used in the .proc pseudo-op that says
5946 what kind of result this function returns. For non-C types, we pick
5947 the closest C type. */
5949 #ifndef CHAR_TYPE_SIZE
5950 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5953 #ifndef SHORT_TYPE_SIZE
5954 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5957 #ifndef INT_TYPE_SIZE
5958 #define INT_TYPE_SIZE BITS_PER_WORD
5961 #ifndef LONG_TYPE_SIZE
5962 #define LONG_TYPE_SIZE BITS_PER_WORD
5965 #ifndef LONG_LONG_TYPE_SIZE
5966 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5969 #ifndef FLOAT_TYPE_SIZE
5970 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5973 #ifndef DOUBLE_TYPE_SIZE
5974 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5977 #ifndef LONG_DOUBLE_TYPE_SIZE
5978 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5982 sparc_type_code (type
)
5985 register unsigned long qualifiers
= 0;
5986 register unsigned shift
;
5988 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5989 setting more, since some assemblers will give an error for this. Also,
5990 we must be careful to avoid shifts of 32 bits or more to avoid getting
5991 unpredictable results. */
5993 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
5995 switch (TREE_CODE (type
))
6001 qualifiers
|= (3 << shift
);
6006 qualifiers
|= (2 << shift
);
6010 case REFERENCE_TYPE
:
6012 qualifiers
|= (1 << shift
);
6016 return (qualifiers
| 8);
6019 case QUAL_UNION_TYPE
:
6020 return (qualifiers
| 9);
6023 return (qualifiers
| 10);
6026 return (qualifiers
| 16);
6029 /* If this is a range type, consider it to be the underlying
6031 if (TREE_TYPE (type
) != 0)
6034 /* Carefully distinguish all the standard types of C,
6035 without messing up if the language is not C. We do this by
6036 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6037 look at both the names and the above fields, but that's redundant.
6038 Any type whose size is between two C types will be considered
6039 to be the wider of the two types. Also, we do not have a
6040 special code to use for "long long", so anything wider than
6041 long is treated the same. Note that we can't distinguish
6042 between "int" and "long" in this code if they are the same
6043 size, but that's fine, since neither can the assembler. */
6045 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6046 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
6048 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6049 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
6051 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6052 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
6055 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
6058 /* If this is a range type, consider it to be the underlying
6060 if (TREE_TYPE (type
) != 0)
6063 /* Carefully distinguish all the standard types of C,
6064 without messing up if the language is not C. */
6066 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
6067 return (qualifiers
| 6);
6070 return (qualifiers
| 7);
6072 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
6073 /* ??? We need to distinguish between double and float complex types,
6074 but I don't know how yet because I can't reach this code from
6075 existing front-ends. */
6076 return (qualifiers
| 7); /* Who knows? */
6078 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
6079 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
6080 case FILE_TYPE
: /* GNU Pascal FILE type. */
6081 case SET_TYPE
: /* GNU Pascal SET type. */
6082 case LANG_TYPE
: /* ? */
6086 abort (); /* Not a type! */
6093 /* Nested function support. */
6095 /* Emit RTL insns to initialize the variable parts of a trampoline.
6096 FNADDR is an RTX for the address of the function's pure code.
6097 CXT is an RTX for the static chain value for the function.
6099 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6100 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6101 (to store insns). This is a bit excessive. Perhaps a different
6102 mechanism would be better here.
6104 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6107 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
6108 rtx tramp
, fnaddr
, cxt
;
6110 /* SPARC 32 bit trampoline:
6113 sethi %hi(static), %g2
6115 or %g2, %lo(static), %g2
6117 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6118 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6120 #ifdef TRANSFER_FROM_TRAMPOLINE
6121 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6122 0, VOIDmode
, 1, tramp
, Pmode
);
6125 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
6126 expand_binop (SImode
, ior_optab
,
6127 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
6128 size_int (10), 0, 1),
6129 GEN_INT (0x03000000),
6130 NULL_RTX
, 1, OPTAB_DIRECT
));
6132 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6133 expand_binop (SImode
, ior_optab
,
6134 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
6135 size_int (10), 0, 1),
6136 GEN_INT (0x05000000),
6137 NULL_RTX
, 1, OPTAB_DIRECT
));
6139 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6140 expand_binop (SImode
, ior_optab
,
6141 expand_and (fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
6142 GEN_INT (0x81c06000),
6143 NULL_RTX
, 1, OPTAB_DIRECT
));
6145 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6146 expand_binop (SImode
, ior_optab
,
6147 expand_and (cxt
, GEN_INT (0x3ff), NULL_RTX
),
6148 GEN_INT (0x8410a000),
6149 NULL_RTX
, 1, OPTAB_DIRECT
));
6151 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
6152 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6153 aligned on a 16 byte boundary so one flush clears it all. */
6154 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
)
6155 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
6156 plus_constant (tramp
, 8)))));
6159 /* The 64 bit version is simpler because it makes more sense to load the
6160 values as "immediate" data out of the trampoline. It's also easier since
6161 we can read the PC without clobbering a register. */
6164 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
6165 rtx tramp
, fnaddr
, cxt
;
6167 #ifdef TRANSFER_FROM_TRAMPOLINE
6168 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6169 0, VOIDmode
, 1, tramp
, Pmode
);
6180 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
6181 GEN_INT (0x83414000));
6182 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6183 GEN_INT (0xca586018));
6184 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6185 GEN_INT (0x81c14000));
6186 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6187 GEN_INT (0xca586010));
6188 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
6189 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
6190 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
6192 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
)
6193 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
6196 /* Subroutines to support a flat (single) register window calling
6199 /* Single-register window sparc stack frames look like:
6201 Before call After call
6202 +-----------------------+ +-----------------------+
6204 mem | caller's temps. | | caller's temps. |
6206 +-----------------------+ +-----------------------+
6208 | arguments on stack. | | arguments on stack. |
6210 +-----------------------+FP+92->+-----------------------+
6211 | 6 words to save | | 6 words to save |
6212 | arguments passed | | arguments passed |
6213 | in registers, even | | in registers, even |
6214 | if not passed. | | if not passed. |
6215 SP+68->+-----------------------+FP+68->+-----------------------+
6216 | 1 word struct addr | | 1 word struct addr |
6217 +-----------------------+FP+64->+-----------------------+
6219 | 16 word reg save area | | 16 word reg save area |
6221 SP->+-----------------------+ FP->+-----------------------+
6223 | fp/alu reg moves |
6224 FP-16->+-----------------------+
6228 +-----------------------+
6230 | fp register save |
6232 +-----------------------+
6234 | gp register save |
6236 +-----------------------+
6238 | alloca allocations |
6240 +-----------------------+
6242 | arguments on stack |
6244 SP+92->+-----------------------+
6246 | arguments passed |
6247 | in registers, even |
6248 low | if not passed. |
6249 memory SP+68->+-----------------------+
6250 | 1 word struct addr |
6251 SP+64->+-----------------------+
6253 I 16 word reg save area |
6255 SP->+-----------------------+ */
6257 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6258 save masks, and offsets for the current function. */
6260 struct sparc_frame_info
6262 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6263 unsigned long var_size
; /* # bytes that variables take up. */
6264 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6265 unsigned long extra_size
; /* # bytes of extra gunk. */
6266 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6267 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6268 unsigned long gmask
; /* Mask of saved gp registers. */
6269 unsigned long fmask
; /* Mask of saved fp registers. */
6270 unsigned long reg_offset
; /* Offset from new sp to store regs. */
6271 int initialized
; /* Nonzero if frame size already calculated. */
6274 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6275 struct sparc_frame_info current_frame_info
;
6277 /* Zero structure to initialize current_frame_info. */
6278 struct sparc_frame_info zero_frame_info
;
6280 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6282 #define RETURN_ADDR_REGNUM 15
6283 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
6284 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6286 #define MUST_SAVE_REGISTER(regno) \
6287 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6288 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
6289 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6291 /* Return the bytes needed to compute the frame pointer from the current
6295 sparc_flat_compute_frame_size (size
)
6296 int size
; /* # of var. bytes allocated. */
6299 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6300 unsigned long var_size
; /* # bytes that variables take up. */
6301 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6302 unsigned long extra_size
; /* # extra bytes. */
6303 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6304 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6305 unsigned long gmask
; /* Mask of saved gp registers. */
6306 unsigned long fmask
; /* Mask of saved fp registers. */
6307 unsigned long reg_offset
; /* Offset to register save area. */
6308 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
6310 /* This is the size of the 16 word reg save area, 1 word struct addr
6311 area, and 4 word fp/alu register copy area. */
6312 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
6322 if (!leaf_function_p ())
6324 /* Also include the size needed for the 6 parameter registers. */
6325 args_size
= current_function_outgoing_args_size
+ 24;
6327 total_size
= var_size
+ args_size
;
6329 /* Calculate space needed for gp registers. */
6330 for (regno
= 1; regno
<= 31; regno
++)
6332 if (MUST_SAVE_REGISTER (regno
))
6334 /* If we need to save two regs in a row, ensure there's room to bump
6335 up the address to align it to a doubleword boundary. */
6336 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
6338 if (gp_reg_size
% 8 != 0)
6340 gp_reg_size
+= 2 * UNITS_PER_WORD
;
6341 gmask
|= 3 << regno
;
6347 gp_reg_size
+= UNITS_PER_WORD
;
6348 gmask
|= 1 << regno
;
6353 /* Calculate space needed for fp registers. */
6354 for (regno
= 32; regno
<= 63; regno
++)
6356 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6358 fp_reg_size
+= UNITS_PER_WORD
;
6359 fmask
|= 1 << (regno
- 32);
6366 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
6367 /* Ensure save area is 8 byte aligned if we need it. */
6369 if (need_aligned_p
&& n
!= 0)
6371 total_size
+= 8 - n
;
6372 reg_offset
+= 8 - n
;
6374 total_size
+= gp_reg_size
+ fp_reg_size
;
6377 /* If we must allocate a stack frame at all, we must also allocate
6378 room for register window spillage, so as to be binary compatible
6379 with libraries and operating systems that do not use -mflat. */
6381 total_size
+= extra_size
;
6385 total_size
= SPARC_STACK_ALIGN (total_size
);
6387 /* Save other computed information. */
6388 current_frame_info
.total_size
= total_size
;
6389 current_frame_info
.var_size
= var_size
;
6390 current_frame_info
.args_size
= args_size
;
6391 current_frame_info
.extra_size
= extra_size
;
6392 current_frame_info
.gp_reg_size
= gp_reg_size
;
6393 current_frame_info
.fp_reg_size
= fp_reg_size
;
6394 current_frame_info
.gmask
= gmask
;
6395 current_frame_info
.fmask
= fmask
;
6396 current_frame_info
.reg_offset
= reg_offset
;
6397 current_frame_info
.initialized
= reload_completed
;
6399 /* Ok, we're done. */
6403 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
6406 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
6407 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
6408 [BASE_REG+OFFSET] will always be a valid address.
6410 WORD_OP is either "st" for save, "ld" for restore.
6411 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
6414 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
6415 doubleword_op
, base_offset
)
6417 const char *base_reg
;
6418 unsigned int offset
;
6419 unsigned long gmask
;
6420 unsigned long fmask
;
6421 const char *word_op
;
6422 const char *doubleword_op
;
6423 unsigned long base_offset
;
6427 if (gmask
== 0 && fmask
== 0)
6430 /* Save registers starting from high to low. We've already saved the
6431 previous frame pointer and previous return address for the debugger's
6432 sake. The debugger allows us to not need a nop in the epilog if at least
6433 one register is reloaded in addition to return address. */
6437 for (regno
= 1; regno
<= 31; regno
++)
6439 if ((gmask
& (1L << regno
)) != 0)
6441 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
6443 /* We can save two registers in a row. If we're not at a
6444 double word boundary, move to one.
6445 sparc_flat_compute_frame_size ensures there's room to do
6447 if (offset
% 8 != 0)
6448 offset
+= UNITS_PER_WORD
;
6450 if (word_op
[0] == 's')
6452 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
6453 doubleword_op
, reg_names
[regno
],
6455 if (dwarf2out_do_frame ())
6457 char *l
= dwarf2out_cfi_label ();
6458 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
6460 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
6464 fprintf (file
, "\t%s\t[%s+%d], %s\n",
6465 doubleword_op
, base_reg
, offset
,
6468 offset
+= 2 * UNITS_PER_WORD
;
6473 if (word_op
[0] == 's')
6475 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
6476 word_op
, reg_names
[regno
],
6478 if (dwarf2out_do_frame ())
6479 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
6482 fprintf (file
, "\t%s\t[%s+%d], %s\n",
6483 word_op
, base_reg
, offset
, reg_names
[regno
]);
6485 offset
+= UNITS_PER_WORD
;
6493 for (regno
= 32; regno
<= 63; regno
++)
6495 if ((fmask
& (1L << (regno
- 32))) != 0)
6497 if (word_op
[0] == 's')
6499 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
6500 word_op
, reg_names
[regno
],
6502 if (dwarf2out_do_frame ())
6503 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
6506 fprintf (file
, "\t%s\t[%s+%d], %s\n",
6507 word_op
, base_reg
, offset
, reg_names
[regno
]);
6509 offset
+= UNITS_PER_WORD
;
6515 /* Set up the stack and frame (if desired) for the function. */
6518 sparc_flat_output_function_prologue (file
, size
)
6522 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
6523 unsigned long gmask
= current_frame_info
.gmask
;
6525 sparc_output_scratch_registers (file
);
6527 /* This is only for the human reader. */
6528 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
6529 fprintf (file
, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6531 current_frame_info
.var_size
,
6532 current_frame_info
.gp_reg_size
/ 4,
6533 current_frame_info
.fp_reg_size
/ 4,
6534 current_function_outgoing_args_size
,
6535 current_frame_info
.extra_size
);
6537 size
= SPARC_STACK_ALIGN (size
);
6538 size
= (! current_frame_info
.initialized
6539 ? sparc_flat_compute_frame_size (size
)
6540 : current_frame_info
.total_size
);
6542 /* These cases shouldn't happen. Catch them now. */
6543 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
6546 /* Allocate our stack frame by decrementing %sp.
6547 At present, the only algorithm gdb can use to determine if this is a
6548 flat frame is if we always set %i7 if we set %sp. This can be optimized
6549 in the future by putting in some sort of debugging information that says
6550 this is a `flat' function. However, there is still the case of debugging
6551 code without such debugging information (including cases where most fns
6552 have such info, but there is one that doesn't). So, always do this now
6553 so we don't get a lot of code out there that gdb can't handle.
6554 If the frame pointer isn't needn't then that's ok - gdb won't be able to
6555 distinguish us from a non-flat function but there won't (and shouldn't)
6556 be any differences anyway. The return pc is saved (if necessary) right
6557 after %i7 so gdb won't have to look too far to find it. */
6560 unsigned int reg_offset
= current_frame_info
.reg_offset
;
6561 const char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
6562 const char *t1_str
= "%g1";
6564 /* Things get a little tricky if local variables take up more than ~4096
6565 bytes and outgoing arguments take up more than ~4096 bytes. When that
6566 happens, the register save area can't be accessed from either end of
6567 the frame. Handle this by decrementing %sp to the start of the gp
6568 register save area, save the regs, update %i7, and then set %sp to its
6569 final value. Given that we only have one scratch register to play
6570 with it is the cheapest solution, and it helps gdb out as it won't
6571 slow down recognition of flat functions.
6572 Don't change the order of insns emitted here without checking with
6573 the gdb folk first. */
6575 /* Is the entire register save area offsettable from %sp? */
6576 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
6580 fprintf (file
, "\tadd\t%s, %d, %s\n",
6581 sp_str
, -size
, sp_str
);
6582 if (gmask
& FRAME_POINTER_MASK
)
6584 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6585 fp_str
, sp_str
, reg_offset
);
6586 fprintf (file
, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6587 sp_str
, -size
, fp_str
, ASM_COMMENT_START
);
6593 fprintf (file
, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6594 size
, t1_str
, sp_str
, t1_str
, sp_str
);
6595 if (gmask
& FRAME_POINTER_MASK
)
6597 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6598 fp_str
, sp_str
, reg_offset
);
6599 fprintf (file
, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6600 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
6604 if (dwarf2out_do_frame ())
6606 char *l
= dwarf2out_cfi_label ();
6607 if (gmask
& FRAME_POINTER_MASK
)
6609 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
6610 reg_offset
- 4 - size
);
6611 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
6614 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
6616 if (gmask
& RETURN_ADDR_MASK
)
6618 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6619 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
6620 if (dwarf2out_do_frame ())
6621 dwarf2out_return_save ("", reg_offset
- size
);
6624 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
6625 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
6626 current_frame_info
.fmask
,
6627 "st", "std", -size
);
6631 /* Subtract %sp in two steps, but make sure there is always a
6632 64 byte register save area, and %sp is properly aligned. */
6633 /* Amount to decrement %sp by, the first time. */
6634 unsigned int size1
= ((size
- reg_offset
+ 64) + 15) & -16;
6635 /* Offset to register save area from %sp. */
6636 unsigned int offset
= size1
- (size
- reg_offset
);
6640 fprintf (file
, "\tadd\t%s, %d, %s\n",
6641 sp_str
, -size1
, sp_str
);
6642 if (gmask
& FRAME_POINTER_MASK
)
6644 fprintf (file
, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6645 fp_str
, sp_str
, offset
, sp_str
, -size1
, fp_str
,
6652 fprintf (file
, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6653 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
6654 if (gmask
& FRAME_POINTER_MASK
)
6656 fprintf (file
, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6657 fp_str
, sp_str
, offset
, sp_str
, t1_str
, fp_str
,
6662 if (dwarf2out_do_frame ())
6664 char *l
= dwarf2out_cfi_label ();
6665 if (gmask
& FRAME_POINTER_MASK
)
6667 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
6668 offset
- 4 - size1
);
6669 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
6672 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
6674 if (gmask
& RETURN_ADDR_MASK
)
6676 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6677 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, offset
);
6678 if (dwarf2out_do_frame ())
6679 /* offset - size1 == reg_offset - size
6680 if reg_offset were updated above like offset. */
6681 dwarf2out_return_save ("", offset
- size1
);
6684 sparc_flat_save_restore (file
, sp_str
, offset
,
6685 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
6686 current_frame_info
.fmask
,
6687 "st", "std", -size1
);
6688 fprintf (file
, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6689 size
- size1
, t1_str
, sp_str
, t1_str
, sp_str
);
6690 if (dwarf2out_do_frame ())
6691 if (! (gmask
& FRAME_POINTER_MASK
))
6692 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
6696 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
6699 /* Do any necessary cleanup after a function to restore stack, frame,
6703 sparc_flat_output_function_epilogue (file
, size
)
6707 rtx epilogue_delay
= current_function_epilogue_delay_list
;
6708 int noepilogue
= FALSE
;
6710 /* This is only for the human reader. */
6711 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
6713 /* The epilogue does not depend on any registers, but the stack
6714 registers, so we assume that if we have 1 pending nop, it can be
6715 ignored, and 2 it must be filled (2 nops occur for integer
6716 multiply and divide). */
6718 size
= SPARC_STACK_ALIGN (size
);
6719 size
= (!current_frame_info
.initialized
6720 ? sparc_flat_compute_frame_size (size
)
6721 : current_frame_info
.total_size
);
6723 if (size
== 0 && epilogue_delay
== 0)
6725 rtx insn
= get_last_insn ();
6727 /* If the last insn was a BARRIER, we don't have to write any code
6728 because a jump (aka return) was put there. */
6729 if (GET_CODE (insn
) == NOTE
)
6730 insn
= prev_nonnote_insn (insn
);
6731 if (insn
&& GET_CODE (insn
) == BARRIER
)
6737 unsigned int reg_offset
= current_frame_info
.reg_offset
;
6739 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
6740 const char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
6741 const char *t1_str
= "%g1";
6743 /* In the reload sequence, we don't need to fill the load delay
6744 slots for most of the loads, also see if we can fill the final
6745 delay slot if not otherwise filled by the reload sequence. */
6748 fprintf (file
, "\tset\t%d, %s\n", size
, t1_str
);
6750 if (frame_pointer_needed
)
6753 fprintf (file
,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6754 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
6756 fprintf (file
,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6757 fp_str
, size
, sp_str
, ASM_COMMENT_START
);
6760 /* Is the entire register save area offsettable from %sp? */
6761 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
6767 /* Restore %sp in two steps, but make sure there is always a
6768 64 byte register save area, and %sp is properly aligned. */
6769 /* Amount to increment %sp by, the first time. */
6770 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
6771 /* Offset to register save area from %sp. */
6772 reg_offset
= size1
- reg_offset
;
6774 fprintf (file
, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6775 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
6778 /* We must restore the frame pointer and return address reg first
6779 because they are treated specially by the prologue output code. */
6780 if (current_frame_info
.gmask
& FRAME_POINTER_MASK
)
6782 fprintf (file
, "\tld\t[%s+%d], %s\n",
6783 sp_str
, reg_offset
, fp_str
);
6786 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
6788 fprintf (file
, "\tld\t[%s+%d], %s\n",
6789 sp_str
, reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
6793 /* Restore any remaining saved registers. */
6794 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
6795 current_frame_info
.gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
6796 current_frame_info
.fmask
,
6799 /* If we had to increment %sp in two steps, record it so the second
6800 restoration in the epilogue finishes up. */
6805 fprintf (file
, "\tset\t%d, %s\n",
6809 if (current_function_returns_struct
)
6810 fprintf (file
, "\tjmp\t%%o7+12\n");
6812 fprintf (file
, "\tretl\n");
6814 /* If the only register saved is the return address, we need a
6815 nop, unless we have an instruction to put into it. Otherwise
6816 we don't since reloading multiple registers doesn't reference
6817 the register being loaded. */
6823 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
6826 else if (size
> 4095)
6827 fprintf (file
, "\tadd\t%s, %s, %s\n", sp_str
, t1_str
, sp_str
);
6830 fprintf (file
, "\tadd\t%s, %d, %s\n", sp_str
, size
, sp_str
);
6833 fprintf (file
, "\tnop\n");
6836 /* Reset state info for each function. */
6837 current_frame_info
= zero_frame_info
;
6839 sparc_output_deferred_case_vectors ();
6842 /* Define the number of delay slots needed for the function epilogue.
6844 On the sparc, we need a slot if either no stack has been allocated,
6845 or the only register saved is the return register. */
6848 sparc_flat_epilogue_delay_slots ()
6850 if (!current_frame_info
.initialized
)
6851 (void) sparc_flat_compute_frame_size (get_frame_size ());
6853 if (current_frame_info
.total_size
== 0)
6859 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6860 Any single length instruction which doesn't reference the stack or frame
6864 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
6866 int slot ATTRIBUTE_UNUSED
;
6868 rtx pat
= PATTERN (trial
);
6870 if (get_attr_length (trial
) != 1)
6873 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
6874 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
6880 /* Adjust the cost of a scheduling dependency. Return the new cost of
6881 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6884 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
6890 enum attr_type insn_type
;
6892 if (! recog_memoized (insn
))
6895 insn_type
= get_attr_type (insn
);
6897 if (REG_NOTE_KIND (link
) == 0)
6899 /* Data dependency; DEP_INSN writes a register that INSN reads some
6902 /* if a load, then the dependence must be on the memory address;
6903 add an extra "cycle". Note that the cost could be two cycles
6904 if the reg was written late in an instruction group; we ca not tell
6906 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
6909 /* Get the delay only if the address of the store is the dependence. */
6910 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
6912 rtx pat
= PATTERN(insn
);
6913 rtx dep_pat
= PATTERN (dep_insn
);
6915 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
6916 return cost
; /* This should not happen! */
6918 /* The dependency between the two instructions was on the data that
6919 is being stored. Assume that this implies that the address of the
6920 store is not dependent. */
6921 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
6924 return cost
+ 3; /* An approximation. */
6927 /* A shift instruction cannot receive its data from an instruction
6928 in the same cycle; add a one cycle penalty. */
6929 if (insn_type
== TYPE_SHIFT
)
6930 return cost
+ 3; /* Split before cascade into shift. */
6934 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6935 INSN writes some cycles later. */
6937 /* These are only significant for the fpu unit; writing a fp reg before
6938 the fpu has finished with it stalls the processor. */
6940 /* Reusing an integer register causes no problems. */
6941 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
6949 hypersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
6955 enum attr_type insn_type
, dep_type
;
6956 rtx pat
= PATTERN(insn
);
6957 rtx dep_pat
= PATTERN (dep_insn
);
6959 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
6962 insn_type
= get_attr_type (insn
);
6963 dep_type
= get_attr_type (dep_insn
);
6965 switch (REG_NOTE_KIND (link
))
6968 /* Data dependency; DEP_INSN writes a register that INSN reads some
6975 /* Get the delay iff the address of the store is the dependence. */
6976 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
6979 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
6986 /* If a load, then the dependence must be on the memory address. If
6987 the addresses aren't equal, then it might be a false dependency */
6988 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
6990 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
6991 || GET_CODE (SET_DEST (dep_pat
)) != MEM
6992 || GET_CODE (SET_SRC (pat
)) != MEM
6993 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
6994 XEXP (SET_SRC (pat
), 0)))
7002 /* Compare to branch latency is 0. There is no benefit from
7003 separating compare and branch. */
7004 if (dep_type
== TYPE_COMPARE
)
7006 /* Floating point compare to branch latency is less than
7007 compare to conditional move. */
7008 if (dep_type
== TYPE_FPCMP
)
7017 /* Anti-dependencies only penalize the fpu unit. */
7018 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7030 ultrasparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7036 enum attr_type insn_type
, dep_type
;
7037 rtx pat
= PATTERN(insn
);
7038 rtx dep_pat
= PATTERN (dep_insn
);
7040 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7043 insn_type
= get_attr_type (insn
);
7044 dep_type
= get_attr_type (dep_insn
);
7046 /* Nothing issues in parallel with integer multiplies, so
7047 mark as zero cost since the scheduler can not do anything
7049 if (insn_type
== TYPE_IMUL
)
7052 #define SLOW_FP(dep_type) \
7053 (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
7054 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
7056 switch (REG_NOTE_KIND (link
))
7059 /* Data dependency; DEP_INSN writes a register that INSN reads some
7062 if (dep_type
== TYPE_CMOVE
)
7064 /* Instructions that read the result of conditional moves cannot
7065 be in the same group or the following group. */
7071 /* UltraSPARC can dual issue a store and an instruction setting
7072 the value stored, except for divide and square root. */
7074 if (! SLOW_FP (dep_type
))
7079 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7082 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7083 /* The dependency between the two instructions is on the data
7084 that is being stored. Assume that the address of the store
7085 is not also dependent. */
7092 /* A load does not return data until at least 11 cycles after
7093 a store to the same location. 3 cycles are accounted for
7094 in the load latency; add the other 8 here. */
7095 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7097 /* If the addresses are not equal this may be a false
7098 dependency because pointer aliasing could not be
7099 determined. Add only 2 cycles in that case. 2 is
7100 an arbitrary compromise between 8, which would cause
7101 the scheduler to generate worse code elsewhere to
7102 compensate for a dependency which might not really
7104 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7105 || GET_CODE (SET_SRC (pat
)) != MEM
7106 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7107 || ! rtx_equal_p (XEXP (SET_SRC (pat
), 0),
7108 XEXP (SET_DEST (dep_pat
), 0)))
7116 /* Compare to branch latency is 0. There is no benefit from
7117 separating compare and branch. */
7118 if (dep_type
== TYPE_COMPARE
)
7120 /* Floating point compare to branch latency is less than
7121 compare to conditional move. */
7122 if (dep_type
== TYPE_FPCMP
)
7127 /* FMOVR class instructions can not issue in the same cycle
7128 or the cycle after an instruction which writes any
7129 integer register. Model this as cost 2 for dependent
7131 if ((dep_type
== TYPE_IALU
|| dep_type
== TYPE_UNARY
7132 || dep_type
== TYPE_BINARY
)
7135 /* Otherwise check as for integer conditional moves. */
7138 /* Conditional moves involving integer registers wait until
7139 3 cycles after loads return data. The interlock applies
7140 to all loads, not just dependent loads, but that is hard
7142 if (dep_type
== TYPE_LOAD
|| dep_type
== TYPE_SLOAD
)
7152 /* Divide and square root lock destination registers for full latency. */
7153 if (! SLOW_FP (dep_type
))
7157 case REG_DEP_OUTPUT
:
7158 /* IEU and FPU instruction that have the same destination
7159 register cannot be grouped together. */
7166 /* Other costs not accounted for:
7167 - Single precision floating point loads lock the other half of
7168 the even/odd register pair.
7169 - Several hazards associated with ldd/std are ignored because these
7170 instructions are rarely generated for V9.
7171 - The floating point pipeline can not have both a single and double
7172 precision operation active at the same time. Format conversions
7173 and graphics instructions are given honorary double precision status.
7174 - call and jmpl are always the first instruction in a group. */
7182 sparc_adjust_cost(insn
, link
, dep
, cost
)
7190 case PROCESSOR_SUPERSPARC
:
7191 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7193 case PROCESSOR_HYPERSPARC
:
7194 case PROCESSOR_SPARCLITE86X
:
7195 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7197 case PROCESSOR_ULTRASPARC
:
7198 cost
= ultrasparc_adjust_cost (insn
, link
, dep
, cost
);
7206 /* This describes the state of the UltraSPARC pipeline during
7207 instruction scheduling. */
7209 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
7210 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
7212 enum ultra_code
{ NONE
=0, /* no insn at all */
7213 IEU0
, /* shifts and conditional moves */
7214 IEU1
, /* condition code setting insns, calls+jumps */
7215 IEUN
, /* all other single cycle ieu insns */
7216 LSU
, /* loads and stores */
7218 FPM
, /* FPU pipeline 1, multiplies and divides */
7219 FPA
, /* FPU pipeline 2, all other operations */
7220 SINGLE
, /* single issue instructions */
7223 static enum ultra_code ultra_code_from_mask
PARAMS ((int));
7224 static void ultra_schedule_insn
PARAMS ((rtx
*, rtx
*, int, enum ultra_code
));
7226 static const char *ultra_code_names
[NUM_ULTRA_CODES
] = {
7227 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
7228 "FPM", "FPA", "SINGLE" };
7230 struct ultrasparc_pipeline_state
{
7231 /* The insns in this group. */
7234 /* The code for each insn. */
7235 enum ultra_code codes
[4];
7237 /* Which insns in this group have been committed by the
7238 scheduler. This is how we determine how many more
7239 can issue this cycle. */
7242 /* How many insns in this group. */
7245 /* Mask of free slots still in this group. */
7246 char free_slot_mask
;
7248 /* The slotter uses the following to determine what other
7249 insn types can still make their way into this group. */
7250 char contents
[NUM_ULTRA_CODES
];
7254 #define ULTRA_NUM_HIST 8
7255 static struct ultrasparc_pipeline_state ultra_pipe_hist
[ULTRA_NUM_HIST
];
7256 static int ultra_cur_hist
;
7257 static int ultra_cycles_elapsed
;
7259 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
7261 /* Given TYPE_MASK compute the ultra_code it has. */
7262 static enum ultra_code
7263 ultra_code_from_mask (type_mask
)
7266 if (type_mask
& (TMASK (TYPE_SHIFT
) | TMASK (TYPE_CMOVE
)))
7268 else if (type_mask
& (TMASK (TYPE_COMPARE
) |
7270 TMASK (TYPE_SIBCALL
) |
7271 TMASK (TYPE_UNCOND_BRANCH
)))
7273 else if (type_mask
& (TMASK (TYPE_IALU
) | TMASK (TYPE_BINARY
) |
7274 TMASK (TYPE_MOVE
) | TMASK (TYPE_UNARY
)))
7276 else if (type_mask
& (TMASK (TYPE_LOAD
) | TMASK (TYPE_SLOAD
) |
7277 TMASK (TYPE_STORE
) | TMASK (TYPE_FPLOAD
) |
7278 TMASK (TYPE_FPSTORE
)))
7280 else if (type_mask
& (TMASK (TYPE_FPMUL
) | TMASK (TYPE_FPDIVS
) |
7281 TMASK (TYPE_FPDIVD
) | TMASK (TYPE_FPSQRTS
) |
7282 TMASK (TYPE_FPSQRTD
)))
7284 else if (type_mask
& (TMASK (TYPE_FPMOVE
) | TMASK (TYPE_FPCMOVE
) |
7285 TMASK (TYPE_FP
) | TMASK (TYPE_FPCMP
)))
7287 else if (type_mask
& TMASK (TYPE_BRANCH
))
7293 /* Check INSN (a conditional move) and make sure that it's
7294 results are available at this cycle. Return 1 if the
7295 results are in fact ready. */
7297 ultra_cmove_results_ready_p (insn
)
7300 struct ultrasparc_pipeline_state
*up
;
7303 /* If this got dispatched in the previous
7304 group, the results are not ready. */
7305 entry
= (ultra_cur_hist
- 1) & (ULTRA_NUM_HIST
- 1);
7306 up
= &ultra_pipe_hist
[entry
];
7309 if (up
->group
[slot
] == insn
)
7315 /* Walk backwards in pipeline history looking for FPU
7316 operations which use a mode different than FPMODE and
7317 will create a stall if an insn using FPMODE were to be
7318 dispatched this cycle. */
7320 ultra_fpmode_conflict_exists (fpmode
)
7321 enum machine_mode fpmode
;
7326 hist_ent
= (ultra_cur_hist
- 1) & (ULTRA_NUM_HIST
- 1);
7327 if (ultra_cycles_elapsed
< 4)
7328 hist_lim
= ultra_cycles_elapsed
;
7331 while (hist_lim
> 0)
7333 struct ultrasparc_pipeline_state
*up
= &ultra_pipe_hist
[hist_ent
];
7338 rtx insn
= up
->group
[slot
];
7339 enum machine_mode this_mode
;
7343 || GET_CODE (insn
) != INSN
7344 || (pat
= PATTERN (insn
)) == 0
7345 || GET_CODE (pat
) != SET
)
7348 this_mode
= GET_MODE (SET_DEST (pat
));
7349 if ((this_mode
!= SFmode
7350 && this_mode
!= DFmode
)
7351 || this_mode
== fpmode
)
7354 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
7355 we will get a stall. Loads and stores are independant
7357 if (GET_CODE (SET_SRC (pat
)) != ABS
7358 && GET_CODE (SET_SRC (pat
)) != NEG
7359 && ((TMASK (get_attr_type (insn
)) &
7360 (TMASK (TYPE_FPDIVS
) | TMASK (TYPE_FPDIVD
) |
7361 TMASK (TYPE_FPMOVE
) | TMASK (TYPE_FPSQRTS
) |
7362 TMASK (TYPE_FPSQRTD
) |
7363 TMASK (TYPE_LOAD
) | TMASK (TYPE_STORE
))) == 0))
7367 hist_ent
= (hist_ent
- 1) & (ULTRA_NUM_HIST
- 1);
7370 /* No conflicts, safe to dispatch. */
7374 /* Find an instruction in LIST which has one of the
7375 type attributes enumerated in TYPE_MASK. START
7376 says where to begin the search.
7378 NOTE: This scheme depends upon the fact that we
7379 have less than 32 distinct type attributes. */
7381 static int ultra_types_avail
;
7384 ultra_find_type (type_mask
, list
, start
)
7391 /* Short circuit if no such insn exists in the ready
7393 if ((type_mask
& ultra_types_avail
) == 0)
7396 for (i
= start
; i
>= 0; i
--)
7400 if (recog_memoized (insn
) >= 0
7401 && (TMASK(get_attr_type (insn
)) & type_mask
))
7403 enum machine_mode fpmode
= SFmode
;
7406 int check_depend
= 0;
7407 int check_fpmode_conflict
= 0;
7409 if (GET_CODE (insn
) == INSN
7410 && (pat
= PATTERN(insn
)) != 0
7411 && GET_CODE (pat
) == SET
7412 && !(type_mask
& (TMASK (TYPE_STORE
) |
7413 TMASK (TYPE_FPSTORE
))))
7416 if (GET_MODE (SET_DEST (pat
)) == SFmode
7417 || GET_MODE (SET_DEST (pat
)) == DFmode
)
7419 fpmode
= GET_MODE (SET_DEST (pat
));
7420 check_fpmode_conflict
= 1;
7427 rtx slot_insn
= ultra_pipe
.group
[slot
];
7430 /* Already issued, bad dependency, or FPU
7433 && (slot_pat
= PATTERN (slot_insn
)) != 0
7434 && ((insn
== slot_insn
)
7435 || (check_depend
== 1
7436 && GET_CODE (slot_insn
) == INSN
7437 && GET_CODE (slot_pat
) == SET
7438 && ((GET_CODE (SET_DEST (slot_pat
)) == REG
7439 && GET_CODE (SET_SRC (pat
)) == REG
7440 && REGNO (SET_DEST (slot_pat
)) ==
7441 REGNO (SET_SRC (pat
)))
7442 || (GET_CODE (SET_DEST (slot_pat
)) == SUBREG
7443 && GET_CODE (SET_SRC (pat
)) == SUBREG
7444 && REGNO (SUBREG_REG (SET_DEST (slot_pat
))) ==
7445 REGNO (SUBREG_REG (SET_SRC (pat
)))
7446 && SUBREG_WORD (SET_DEST (slot_pat
)) ==
7447 SUBREG_WORD (SET_SRC (pat
)))))
7448 || (check_fpmode_conflict
== 1
7449 && GET_CODE (slot_insn
) == INSN
7450 && GET_CODE (slot_pat
) == SET
7451 && (GET_MODE (SET_DEST (slot_pat
)) == SFmode
7452 || GET_MODE (SET_DEST (slot_pat
)) == DFmode
)
7453 && GET_MODE (SET_DEST (slot_pat
)) != fpmode
)))
7457 /* Check for peculiar result availability and dispatch
7458 interference situations. */
7460 && ultra_cycles_elapsed
> 0)
7464 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
7466 rtx link_insn
= XEXP (link
, 0);
7467 if (GET_CODE (link_insn
) == INSN
7468 && recog_memoized (link_insn
) >= 0
7469 && (TMASK (get_attr_type (link_insn
)) &
7470 (TMASK (TYPE_CMOVE
) | TMASK (TYPE_FPCMOVE
)))
7471 && ! ultra_cmove_results_ready_p (link_insn
))
7475 if (check_fpmode_conflict
7476 && ultra_fpmode_conflict_exists (fpmode
))
7489 ultra_build_types_avail (ready
, n_ready
)
7493 int i
= n_ready
- 1;
7495 ultra_types_avail
= 0;
7498 rtx insn
= ready
[i
];
7500 if (recog_memoized (insn
) >= 0)
7501 ultra_types_avail
|= TMASK (get_attr_type (insn
));
7507 /* Place insn pointed to my IP into the pipeline.
7508 Make element THIS of READY be that insn if it
7509 is not already. TYPE indicates the pipeline class
7510 this insn falls into. */
7512 ultra_schedule_insn (ip
, ready
, this, type
)
7516 enum ultra_code type
;
7519 char mask
= ultra_pipe
.free_slot_mask
;
7522 /* Obtain free slot. */
7523 for (pipe_slot
= 0; pipe_slot
< 4; pipe_slot
++)
7524 if ((mask
& (1 << pipe_slot
)) != 0)
7529 /* In it goes, and it hasn't been committed yet. */
7530 ultra_pipe
.group
[pipe_slot
] = *ip
;
7531 ultra_pipe
.codes
[pipe_slot
] = type
;
7532 ultra_pipe
.contents
[type
] = 1;
7534 (UMASK (IEUN
) | UMASK (IEU0
) | UMASK (IEU1
)))
7535 ultra_pipe
.num_ieu_insns
+= 1;
7537 ultra_pipe
.free_slot_mask
= (mask
& ~(1 << pipe_slot
));
7538 ultra_pipe
.group_size
+= 1;
7539 ultra_pipe
.commit
[pipe_slot
] = 0;
7541 /* Update ready list. */
7543 while (ip
!= &ready
[this])
7551 /* Advance to the next pipeline group. */
7553 ultra_flush_pipeline ()
7555 ultra_cur_hist
= (ultra_cur_hist
+ 1) & (ULTRA_NUM_HIST
- 1);
7556 ultra_cycles_elapsed
+= 1;
7557 memset ((char *) &ultra_pipe
, 0, sizeof ultra_pipe
);
7558 ultra_pipe
.free_slot_mask
= 0xf;
7561 /* Init our data structures for this current block. */
7563 ultrasparc_sched_init (dump
, sched_verbose
)
7564 FILE *dump ATTRIBUTE_UNUSED
;
7565 int sched_verbose ATTRIBUTE_UNUSED
;
7567 memset ((char *) ultra_pipe_hist
, 0, sizeof ultra_pipe_hist
);
7569 ultra_cycles_elapsed
= 0;
7570 ultra_pipe
.free_slot_mask
= 0xf;
7573 /* INSN has been scheduled, update pipeline commit state
7574 and return how many instructions are still to be
7575 scheduled in this group. */
7577 ultrasparc_variable_issue (insn
)
7580 struct ultrasparc_pipeline_state
*up
= &ultra_pipe
;
7581 int i
, left_to_fire
;
7584 for (i
= 0; i
< 4; i
++)
7586 if (up
->group
[i
] == 0)
7589 if (up
->group
[i
] == insn
)
7593 else if (! up
->commit
[i
])
7597 return left_to_fire
;
7600 /* In actual_hazard_this_instance, we may have yanked some
7601 instructions from the ready list due to conflict cost
7602 adjustments. If so, and such an insn was in our pipeline
7603 group, remove it and update state. */
7605 ultra_rescan_pipeline_state (ready
, n_ready
)
7609 struct ultrasparc_pipeline_state
*up
= &ultra_pipe
;
7612 for (i
= 0; i
< 4; i
++)
7614 rtx insn
= up
->group
[i
];
7620 /* If it has been committed, then it was removed from
7621 the ready list because it was actually scheduled,
7622 and that is not the case we are searching for here. */
7623 if (up
->commit
[i
] != 0)
7626 for (j
= n_ready
- 1; j
>= 0; j
--)
7627 if (ready
[j
] == insn
)
7630 /* If we didn't find it, toss it. */
7633 enum ultra_code ucode
= up
->codes
[i
];
7636 up
->codes
[i
] = NONE
;
7637 up
->contents
[ucode
] = 0;
7639 (UMASK (IEUN
) | UMASK (IEU0
) | UMASK (IEU1
)))
7640 up
->num_ieu_insns
-= 1;
7642 up
->free_slot_mask
|= (1 << i
);
7643 up
->group_size
-= 1;
7650 ultrasparc_sched_reorder (dump
, sched_verbose
, ready
, n_ready
)
7656 struct ultrasparc_pipeline_state
*up
= &ultra_pipe
;
7663 fprintf (dump
, "\n;;\tUltraSPARC Looking at [");
7664 for (n
= n_ready
- 1; n
>= 0; n
--)
7666 rtx insn
= ready
[n
];
7667 enum ultra_code ucode
;
7669 if (recog_memoized (insn
) < 0)
7671 ucode
= ultra_code_from_mask (TMASK (get_attr_type (insn
)));
7673 fprintf (dump
, "%s(%d) ",
7674 ultra_code_names
[ucode
],
7677 fprintf (dump
, "%s(%d)",
7678 ultra_code_names
[ucode
],
7681 fprintf (dump
, "]\n");
7684 this_insn
= n_ready
- 1;
7686 /* Skip over junk we don't understand. */
7687 while ((this_insn
>= 0)
7688 && recog_memoized (ready
[this_insn
]) < 0)
7691 ultra_build_types_avail (ready
, this_insn
+ 1);
7693 while (this_insn
>= 0) {
7694 int old_group_size
= up
->group_size
;
7696 if (up
->group_size
!= 0)
7700 num_committed
= (up
->commit
[0] + up
->commit
[1] +
7701 up
->commit
[2] + up
->commit
[3]);
7702 /* If nothing has been commited from our group, or all of
7703 them have. Clear out the (current cycle's) pipeline
7704 state and start afresh. */
7705 if (num_committed
== 0
7706 || num_committed
== up
->group_size
)
7708 ultra_flush_pipeline ();
7714 /* OK, some ready list insns got requeued and thus removed
7715 from the ready list. Account for this fact. */
7716 ultra_rescan_pipeline_state (ready
, n_ready
);
7718 /* Something "changed", make this look like a newly
7719 formed group so the code at the end of the loop
7720 knows that progress was in fact made. */
7721 if (up
->group_size
!= old_group_size
)
7726 if (up
->group_size
== 0)
7728 /* If the pipeline is (still) empty and we have any single
7729 group insns, get them out now as this is a good time. */
7730 rtx
*ip
= ultra_find_type ((TMASK (TYPE_RETURN
) | TMASK (TYPE_ADDRESS
) |
7731 TMASK (TYPE_IMUL
) | TMASK (TYPE_CMOVE
) |
7732 TMASK (TYPE_MULTI
) | TMASK (TYPE_MISC
)),
7736 ultra_schedule_insn (ip
, ready
, this_insn
, SINGLE
);
7740 /* If we are not in the process of emptying out the pipe, try to
7741 obtain an instruction which must be the first in it's group. */
7742 ip
= ultra_find_type ((TMASK (TYPE_CALL
) |
7743 TMASK (TYPE_SIBCALL
) |
7744 TMASK (TYPE_CALL_NO_DELAY_SLOT
) |
7745 TMASK (TYPE_UNCOND_BRANCH
)),
7749 ultra_schedule_insn (ip
, ready
, this_insn
, IEU1
);
7752 else if ((ip
= ultra_find_type ((TMASK (TYPE_FPDIVS
) |
7753 TMASK (TYPE_FPDIVD
) |
7754 TMASK (TYPE_FPSQRTS
) |
7755 TMASK (TYPE_FPSQRTD
)),
7756 ready
, this_insn
)) != 0)
7758 ultra_schedule_insn (ip
, ready
, this_insn
, FPM
);
7763 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7764 operation. We can't do more IEU operations if the first 3 slots are
7765 all full or we have dispatched two IEU insns already. */
7766 if ((up
->free_slot_mask
& 0x7) != 0
7767 && up
->num_ieu_insns
< 2
7768 && up
->contents
[IEU0
] == 0
7769 && up
->contents
[IEUN
] == 0)
7771 rtx
*ip
= ultra_find_type (TMASK(TYPE_SHIFT
), ready
, this_insn
);
7774 ultra_schedule_insn (ip
, ready
, this_insn
, IEU0
);
7779 /* If we can, try to find an IEU1 specific or an unnamed
7781 if ((up
->free_slot_mask
& 0x7) != 0
7782 && up
->num_ieu_insns
< 2)
7784 rtx
*ip
= ultra_find_type ((TMASK (TYPE_IALU
) | TMASK (TYPE_BINARY
) |
7785 TMASK (TYPE_MOVE
) | TMASK (TYPE_UNARY
) |
7786 (up
->contents
[IEU1
] == 0 ? TMASK (TYPE_COMPARE
) : 0)),
7792 ultra_schedule_insn (ip
, ready
, this_insn
,
7793 (!up
->contents
[IEU1
]
7794 && get_attr_type (insn
) == TYPE_COMPARE
)
7800 /* If only one IEU insn has been found, try to find another unnamed
7801 IEU operation or an IEU1 specific one. */
7802 if ((up
->free_slot_mask
& 0x7) != 0
7803 && up
->num_ieu_insns
< 2)
7806 int tmask
= (TMASK (TYPE_IALU
) | TMASK (TYPE_BINARY
) |
7807 TMASK (TYPE_MOVE
) | TMASK (TYPE_UNARY
));
7809 if (!up
->contents
[IEU1
])
7810 tmask
|= TMASK (TYPE_COMPARE
);
7811 ip
= ultra_find_type (tmask
, ready
, this_insn
);
7816 ultra_schedule_insn (ip
, ready
, this_insn
,
7817 (!up
->contents
[IEU1
]
7818 && get_attr_type (insn
) == TYPE_COMPARE
)
7824 /* Try for a load or store, but such an insn can only be issued
7825 if it is within' one of the first 3 slots. */
7826 if ((up
->free_slot_mask
& 0x7) != 0
7827 && up
->contents
[LSU
] == 0)
7829 rtx
*ip
= ultra_find_type ((TMASK (TYPE_LOAD
) | TMASK (TYPE_SLOAD
) |
7830 TMASK (TYPE_STORE
) | TMASK (TYPE_FPLOAD
) |
7831 TMASK (TYPE_FPSTORE
)), ready
, this_insn
);
7834 ultra_schedule_insn (ip
, ready
, this_insn
, LSU
);
7839 /* Now find FPU operations, first FPM class. But not divisions or
7840 square-roots because those will break the group up. Unlike all
7841 the previous types, these can go in any slot. */
7842 if (up
->free_slot_mask
!= 0
7843 && up
->contents
[FPM
] == 0)
7845 rtx
*ip
= ultra_find_type (TMASK (TYPE_FPMUL
), ready
, this_insn
);
7848 ultra_schedule_insn (ip
, ready
, this_insn
, FPM
);
7853 /* Continue on with FPA class if we have not filled the group already. */
7854 if (up
->free_slot_mask
!= 0
7855 && up
->contents
[FPA
] == 0)
7857 rtx
*ip
= ultra_find_type ((TMASK (TYPE_FPMOVE
) | TMASK (TYPE_FPCMOVE
) |
7858 TMASK (TYPE_FP
) | TMASK (TYPE_FPCMP
)),
7862 ultra_schedule_insn (ip
, ready
, this_insn
, FPA
);
7867 /* Finally, maybe stick a branch in here. */
7868 if (up
->free_slot_mask
!= 0
7869 && up
->contents
[CTI
] == 0)
7871 rtx
*ip
= ultra_find_type (TMASK (TYPE_BRANCH
), ready
, this_insn
);
7873 /* Try to slip in a branch only if it is one of the
7874 next 2 in the ready list. */
7875 if (ip
&& ((&ready
[this_insn
] - ip
) < 2))
7877 ultra_schedule_insn (ip
, ready
, this_insn
, CTI
);
7883 for (i
= 0; i
< 4; i
++)
7884 if ((up
->free_slot_mask
& (1 << i
)) == 0)
7887 /* See if we made any progress... */
7888 if (old_group_size
!= up
->group_size
)
7891 /* Clean out the (current cycle's) pipeline state
7892 and try once more. If we placed no instructions
7893 into the pipeline at all, it means a real hard
7894 conflict exists with some earlier issued instruction
7895 so we must advance to the next cycle to clear it up. */
7896 if (up
->group_size
== 0)
7898 ultra_flush_pipeline ();
7903 memset ((char *) &ultra_pipe
, 0, sizeof ultra_pipe
);
7904 ultra_pipe
.free_slot_mask
= 0xf;
7912 fprintf (dump
, ";;\tUltraSPARC Launched [");
7913 gsize
= up
->group_size
;
7914 for (n
= 0; n
< 4; n
++)
7916 rtx insn
= up
->group
[n
];
7923 fprintf (dump
, "%s(%d) ",
7924 ultra_code_names
[up
->codes
[n
]],
7927 fprintf (dump
, "%s(%d)",
7928 ultra_code_names
[up
->codes
[n
]],
7931 fprintf (dump
, "]\n");
7943 /* Assume V9 processors are capable of at least dual-issue. */
7945 case PROCESSOR_SUPERSPARC
:
7947 case PROCESSOR_HYPERSPARC
:
7948 case PROCESSOR_SPARCLITE86X
:
7950 case PROCESSOR_ULTRASPARC
:
7956 set_extends(x
, insn
)
7959 register rtx pat
= PATTERN (insn
);
7961 switch (GET_CODE (SET_SRC (pat
)))
7963 /* Load and some shift instructions zero extend. */
7966 /* sethi clears the high bits */
7968 /* LO_SUM is used with sethi. sethi cleared the high
7969 bits and the values used with lo_sum are positive */
7971 /* Store flag stores 0 or 1 */
7981 rtx op1
= XEXP (SET_SRC (pat
), 1);
7982 if (GET_CODE (op1
) == CONST_INT
)
7983 return INTVAL (op1
) >= 0;
7984 if (GET_CODE (XEXP (SET_SRC (pat
), 0)) == REG
7985 && sparc_check_64 (XEXP (SET_SRC (pat
), 0), insn
) == 1)
7987 if (GET_CODE (op1
) == REG
7988 && sparc_check_64 ((op1
), insn
) == 1)
7993 return GET_MODE (SET_SRC (pat
)) == SImode
;
7994 /* Positive integers leave the high bits zero. */
7996 return ! (CONST_DOUBLE_LOW (x
) & 0x80000000);
7998 return ! (INTVAL (x
) & 0x80000000);
8001 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8007 /* We _ought_ to have only one kind per function, but... */
8008 static rtx sparc_addr_diff_list
;
8009 static rtx sparc_addr_list
;
8012 sparc_defer_case_vector (lab
, vec
, diff
)
8016 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8018 sparc_addr_diff_list
8019 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8021 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8025 sparc_output_addr_vec (vec
)
8028 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8029 int idx
, vlen
= XVECLEN (body
, 0);
8031 #ifdef ASM_OUTPUT_ADDR_VEC_START
8032 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8035 #ifdef ASM_OUTPUT_CASE_LABEL
8036 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8039 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8042 for (idx
= 0; idx
< vlen
; idx
++)
8044 ASM_OUTPUT_ADDR_VEC_ELT
8045 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8048 #ifdef ASM_OUTPUT_ADDR_VEC_END
8049 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8054 sparc_output_addr_diff_vec (vec
)
8057 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8058 rtx base
= XEXP (XEXP (body
, 0), 0);
8059 int idx
, vlen
= XVECLEN (body
, 1);
8061 #ifdef ASM_OUTPUT_ADDR_VEC_START
8062 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8065 #ifdef ASM_OUTPUT_CASE_LABEL
8066 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8069 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8072 for (idx
= 0; idx
< vlen
; idx
++)
8074 ASM_OUTPUT_ADDR_DIFF_ELT
8077 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8078 CODE_LABEL_NUMBER (base
));
8081 #ifdef ASM_OUTPUT_ADDR_VEC_END
8082 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8087 sparc_output_deferred_case_vectors ()
8092 if (sparc_addr_list
== NULL_RTX
8093 && sparc_addr_diff_list
== NULL_RTX
)
8096 /* Align to cache line in the function's code section. */
8097 function_section (current_function_decl
);
8099 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8101 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8103 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8104 sparc_output_addr_vec (XEXP (t
, 0));
8105 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8106 sparc_output_addr_diff_vec (XEXP (t
, 0));
8108 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8111 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8112 unknown. Return 1 if the high bits are zero, -1 if the register is
8115 sparc_check_64 (x
, insn
)
8118 /* If a register is set only once it is safe to ignore insns this
8119 code does not know how to handle. The loop will either recognize
8120 the single set and return the correct value or fail to recognize
8124 if (GET_CODE (x
) == REG
8125 && flag_expensive_optimizations
8126 && REG_N_SETS (REGNO (x
)) == 1)
8132 insn
= get_last_insn_anywhere ();
8137 while ((insn
= PREV_INSN (insn
)))
8139 switch (GET_CODE (insn
))
8152 rtx pat
= PATTERN (insn
);
8153 if (GET_CODE (pat
) != SET
)
8155 if (rtx_equal_p (x
, SET_DEST (pat
)))
8156 return set_extends (x
, insn
);
8157 if (reg_overlap_mentioned_p (SET_DEST (pat
), x
))
8166 sparc_v8plus_shift (operands
, insn
, opcode
)
8171 static char asm_code
[60];
8173 if (GET_CODE (operands
[3]) == SCRATCH
)
8174 operands
[3] = operands
[0];
8175 if (GET_CODE (operands
[1]) == CONST_INT
)
8177 output_asm_insn ("mov %1,%3", operands
);
8181 output_asm_insn ("sllx %H1,32,%3", operands
);
8182 if (sparc_check_64 (operands
[1], insn
) <= 0)
8183 output_asm_insn ("srl %L1,0,%L1", operands
);
8184 output_asm_insn ("or %L1,%3,%3", operands
);
8187 strcpy(asm_code
, opcode
);
8188 if (which_alternative
!= 2)
8189 return strcat (asm_code
, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
8191 return strcat (asm_code
, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
8195 /* Return 1 if DEST and SRC reference only global and in registers. */
8198 sparc_return_peephole_ok (dest
, src
)
8203 if (current_function_uses_only_leaf_regs
)
8205 if (GET_CODE (src
) != CONST_INT
8206 && (GET_CODE (src
) != REG
|| ! IN_OR_GLOBAL_P (src
)))
8208 return IN_OR_GLOBAL_P (dest
);
8211 /* Output assembler code to FILE to increment profiler label # LABELNO
8212 for profiling a function entry.
8214 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
8215 during profiling so we need to save/restore it around the call to mcount.
8216 We're guaranteed that a save has just been done, and we use the space
8217 allocated for intreg/fpreg value passing. */
8220 sparc_function_profiler (file
, labelno
)
8225 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8227 if (! TARGET_ARCH64
)
8228 fputs ("\tst\t%g2,[%fp-4]\n", file
);
8230 fputs ("\tsethi\t%hi(", file
);
8231 assemble_name (file
, buf
);
8232 fputs ("),%o0\n", file
);
8234 fputs ("\tcall\t", file
);
8235 assemble_name (file
, MCOUNT_FUNCTION
);
8238 fputs ("\t or\t%o0,%lo(", file
);
8239 assemble_name (file
, buf
);
8240 fputs ("),%o0\n", file
);
8242 if (! TARGET_ARCH64
)
8243 fputs ("\tld\t[%fp-4],%g2\n", file
);
8247 /* The following macro shall output assembler code to FILE
8248 to initialize basic-block profiling.
8250 If profile_block_flag == 2
8252 Output code to call the subroutine `__bb_init_trace_func'
8253 and pass two parameters to it. The first parameter is
8254 the address of a block allocated in the object module.
8255 The second parameter is the number of the first basic block
8258 The name of the block is a local symbol made with this statement:
8260 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8262 Of course, since you are writing the definition of
8263 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8264 can take a short cut in the definition of this macro and use the
8265 name that you know will result.
8267 The number of the first basic block of the function is
8268 passed to the macro in BLOCK_OR_LABEL.
8270 If described in a virtual assembler language the code to be
8274 parameter2 <- BLOCK_OR_LABEL
8275 call __bb_init_trace_func
8277 else if profile_block_flag != 0
8279 Output code to call the subroutine `__bb_init_func'
8280 and pass one single parameter to it, which is the same
8281 as the first parameter to `__bb_init_trace_func'.
8283 The first word of this parameter is a flag which will be nonzero if
8284 the object module has already been initialized. So test this word
8285 first, and do not call `__bb_init_func' if the flag is nonzero.
8286 Note: When profile_block_flag == 2 the test need not be done
8287 but `__bb_init_trace_func' *must* be called.
8289 BLOCK_OR_LABEL may be used to generate a label number as a
8290 branch destination in case `__bb_init_func' will not be called.
8292 If described in a virtual assembler language the code to be
8304 sparc_function_block_profiler(file
, block_or_label
)
8309 ASM_GENERATE_INTERNAL_LABEL (LPBX
, "LPBX", 0);
8311 if (profile_block_flag
== 2)
8313 fputs ("\tsethi\t%hi(", file
);
8314 assemble_name (file
, LPBX
);
8315 fputs ("),%o0\n", file
);
8317 fprintf (file
, "\tsethi\t%%hi(%d),%%o1\n", block_or_label
);
8319 fputs ("\tor\t%o0,%lo(", file
);
8320 assemble_name (file
, LPBX
);
8321 fputs ("),%o0\n", file
);
8323 fprintf (file
, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix
);
8325 fprintf (file
, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label
);
8327 else if (profile_block_flag
!= 0)
8330 ASM_GENERATE_INTERNAL_LABEL (LPBY
, "LPBY", block_or_label
);
8332 fputs ("\tsethi\t%hi(", file
);
8333 assemble_name (file
, LPBX
);
8334 fputs ("),%o0\n", file
);
8336 fputs ("\tld\t[%lo(", file
);
8337 assemble_name (file
, LPBX
);
8338 fputs (")+%o0],%o1\n", file
);
8340 fputs ("\ttst\t%o1\n", file
);
8344 fputs ("\tbne,pn\t%icc,", file
);
8345 assemble_name (file
, LPBY
);
8350 fputs ("\tbne\t", file
);
8351 assemble_name (file
, LPBY
);
8355 fputs ("\t or\t%o0,%lo(", file
);
8356 assemble_name (file
, LPBX
);
8357 fputs ("),%o0\n", file
);
8359 fprintf (file
, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix
);
8361 ASM_OUTPUT_INTERNAL_LABEL (file
, "LPBY", block_or_label
);
8365 /* The following macro shall output assembler code to FILE
8366 to increment a counter associated with basic block number BLOCKNO.
8368 If profile_block_flag == 2
8370 Output code to initialize the global structure `__bb' and
8371 call the function `__bb_trace_func' which will increment the
8374 `__bb' consists of two words. In the first word the number
8375 of the basic block has to be stored. In the second word
8376 the address of a block allocated in the object module
8379 The basic block number is given by BLOCKNO.
8381 The address of the block is given by the label created with
8383 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
8385 by FUNCTION_BLOCK_PROFILER.
8387 Of course, since you are writing the definition of
8388 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8389 can take a short cut in the definition of this macro and use the
8390 name that you know will result.
8392 If described in a virtual assembler language the code to be
8395 move BLOCKNO -> (__bb)
8396 move LPBX0 -> (__bb+4)
8397 call __bb_trace_func
8399 Note that function `__bb_trace_func' must not change the
8400 machine state, especially the flag register. To grant
8401 this, you must output code to save and restore registers
8402 either in this macro or in the macros MACHINE_STATE_SAVE
8403 and MACHINE_STATE_RESTORE. The last two macros will be
8404 used in the function `__bb_trace_func', so you must make
8405 sure that the function prologue does not change any
8406 register prior to saving it with MACHINE_STATE_SAVE.
8408 else if profile_block_flag != 0
8410 Output code to increment the counter directly.
8411 Basic blocks are numbered separately from zero within each
8412 compiled object module. The count associated with block number
8413 BLOCKNO is at index BLOCKNO in an array of words; the name of
8414 this array is a local symbol made with this statement:
8416 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
8418 Of course, since you are writing the definition of
8419 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
8420 can take a short cut in the definition of this macro and use the
8421 name that you know will result.
8423 If described in a virtual assembler language, the code to be
8426 inc (LPBX2+4*BLOCKNO)
8431 sparc_block_profiler(file
, blockno
)
8436 int bbreg
= TARGET_ARCH64
? 4 : 2;
8438 if (profile_block_flag
== 2)
8440 ASM_GENERATE_INTERNAL_LABEL (LPBX
, "LPBX", 0);
8442 fprintf (file
, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix
);
8443 fprintf (file
, "\tsethi\t%%hi(%d),%%g%d\n", blockno
, bbreg
);
8444 fprintf (file
, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix
);
8445 fprintf (file
, "\tor\t%%g%d,%%lo(%d),%%g%d\n", bbreg
, blockno
, bbreg
);
8447 fprintf (file
, "\tst\t%%g%d,[%%g1]\n", bbreg
);
8449 fputs ("\tsethi\t%hi(", file
);
8450 assemble_name (file
, LPBX
);
8451 fprintf (file
, "),%%g%d\n", bbreg
);
8453 fputs ("\tor\t%o2,%lo(", file
);
8454 assemble_name (file
, LPBX
);
8455 fprintf (file
, "),%%g%d\n", bbreg
);
8457 fprintf (file
, "\tst\t%%g%d,[%%g1+4]\n", bbreg
);
8458 fprintf (file
, "\tmov\t%%o7,%%g%d\n", bbreg
);
8460 fprintf (file
, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix
);
8462 fprintf (file
, "\tmov\t%%g%d,%%o7\n", bbreg
);
8464 else if (profile_block_flag
!= 0)
8466 ASM_GENERATE_INTERNAL_LABEL (LPBX
, "LPBX", 2);
8468 fputs ("\tsethi\t%hi(", file
);
8469 assemble_name (file
, LPBX
);
8470 fprintf (file
, "+%d),%%g1\n", blockno
*4);
8472 fputs ("\tld\t[%g1+%lo(", file
);
8473 assemble_name (file
, LPBX
);
8474 if (TARGET_ARCH64
&& USE_AS_OFFSETABLE_LO10
)
8475 fprintf (file
, ")+%d],%%g%d\n", blockno
*4, bbreg
);
8477 fprintf (file
, "+%d)],%%g%d\n", blockno
*4, bbreg
);
8479 fprintf (file
, "\tadd\t%%g%d,1,%%g%d\n", bbreg
, bbreg
);
8481 fprintf (file
, "\tst\t%%g%d,[%%g1+%%lo(", bbreg
);
8482 assemble_name (file
, LPBX
);
8483 if (TARGET_ARCH64
&& USE_AS_OFFSETABLE_LO10
)
8484 fprintf (file
, ")+%d]\n", blockno
*4);
8486 fprintf (file
, "+%d)]\n", blockno
*4);
8490 /* The following macro shall output assembler code to FILE
8491 to indicate a return from function during basic-block profiling.
8493 If profile_block_flag == 2:
8495 Output assembler code to call function `__bb_trace_ret'.
8497 Note that function `__bb_trace_ret' must not change the
8498 machine state, especially the flag register. To grant
8499 this, you must output code to save and restore registers
8500 either in this macro or in the macros MACHINE_STATE_SAVE_RET
8501 and MACHINE_STATE_RESTORE_RET. The last two macros will be
8502 used in the function `__bb_trace_ret', so you must make
8503 sure that the function prologue does not change any
8504 register prior to saving it with MACHINE_STATE_SAVE_RET.
8506 else if profile_block_flag != 0:
8508 The macro will not be used, so it need not distinguish
8513 sparc_function_block_profiler_exit(file
)
8516 if (profile_block_flag
== 2)
8517 fprintf (file
, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix
);
8522 /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
8526 mark_ultrasparc_pipeline_state (arg
)
8529 struct ultrasparc_pipeline_state
*ups
;
8532 ups
= (struct ultrasparc_pipeline_state
*) arg
;
8533 for (i
= 0; i
< sizeof (ups
->group
) / sizeof (rtx
); ++i
)
8534 ggc_mark_rtx (ups
->group
[i
]);
8537 /* Called to register all of our global variables with the garbage
8541 sparc_add_gc_roots ()
8543 ggc_add_rtx_root (&sparc_compare_op0
, 1);
8544 ggc_add_rtx_root (&sparc_compare_op1
, 1);
8545 ggc_add_rtx_root (&leaf_label
, 1);
8546 ggc_add_rtx_root (&global_offset_table
, 1);
8547 ggc_add_rtx_root (&get_pc_symbol
, 1);
8548 ggc_add_rtx_root (&sparc_addr_diff_list
, 1);
8549 ggc_add_rtx_root (&sparc_addr_list
, 1);
8550 ggc_add_root (ultra_pipe_hist
, ARRAY_SIZE (ultra_pipe_hist
),
8551 sizeof (ultra_pipe_hist
[0]), &mark_ultrasparc_pipeline_state
);