gcc/config/ia64/ia64.c

   1 /* Definitions of target machine for GNU compiler.
   2    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
   3    Contributed by James E. Wilson <wilson@cygnus.com> and
   4                   David Mosberger <davidm@hpl.hp.com>.
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "rtl.h"
  26 #include "tree.h"
  27 #include "tm_p.h"
  28 #include "regs.h"
  29 #include "hard-reg-set.h"
  30 #include "real.h"
  31 #include "insn-config.h"
  32 #include "conditions.h"
  33 #include "insn-flags.h"
  34 #include "output.h"
  35 #include "insn-attr.h"
  36 #include "flags.h"
  37 #include "recog.h"
  38 #include "expr.h"
  39 #include "obstack.h"
  40 #include "except.h"
  41 #include "function.h"
  42 #include "ggc.h"
  43 #include "basic-block.h"
  44 #include "toplev.h"
  45
  46 /* This is used for communication between ASM_OUTPUT_LABEL and
  47    ASM_OUTPUT_LABELREF.  */
  48 int ia64_asm_output_label = 0;
  49
  50 /* Define the information needed to generate branch and scc insns.  This is
  51    stored from the compare operation.  */
  52 struct rtx_def * ia64_compare_op0;
  53 struct rtx_def * ia64_compare_op1;
  54
  55 /* Register names for ia64_expand_prologue.  */
  56 static const char * const ia64_reg_numbers[96] =
  57 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  58   "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  59   "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
  60   "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
  61   "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
  62   "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  63   "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
  64   "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
  65   "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
  66   "r104","r105","r106","r107","r108","r109","r110","r111",
  67   "r112","r113","r114","r115","r116","r117","r118","r119",
  68   "r120","r121","r122","r123","r124","r125","r126","r127"};
  69
  70 /* ??? These strings could be shared with REGISTER_NAMES.  */
  71 static const char * const ia64_input_reg_names[8] =
  72 { "in0",  "in1",  "in2",  "in3",  "in4",  "in5",  "in6",  "in7" };
  73
  74 /* ??? These strings could be shared with REGISTER_NAMES.  */
  75 static const char * const ia64_local_reg_names[80] =
  76 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
  77   "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
  78   "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
  79   "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
  80   "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
  81   "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
  82   "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
  83   "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
  84   "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
  85   "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
  86
  87 /* ??? These strings could be shared with REGISTER_NAMES.  */
  88 static const char * const ia64_output_reg_names[8] =
  89 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
  90
  91 /* String used with the -mfixed-range= option.  */
  92 const char *ia64_fixed_range_string;
  93
  94 /* Variables which are this size or smaller are put in the sdata/sbss
  95    sections.  */
  96
  97 unsigned int ia64_section_threshold;
  98 \f
  99 static int find_gr_spill PARAMS ((int));
 100 static int next_scratch_gr_reg PARAMS ((void));
 101 static void mark_reg_gr_used_mask PARAMS ((rtx, void *));
 102 static void ia64_compute_frame_size PARAMS ((HOST_WIDE_INT));
 103 static void setup_spill_pointers PARAMS ((int, rtx, HOST_WIDE_INT));
 104 static void finish_spill_pointers PARAMS ((void));
 105 static rtx spill_restore_mem PARAMS ((rtx, HOST_WIDE_INT));
 106 static void do_spill PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx));
 107 static void do_restore PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT));
 108 static rtx gen_movdi_x PARAMS ((rtx, rtx, rtx));
 109 static rtx gen_fr_spill_x PARAMS ((rtx, rtx, rtx));
 110 static rtx gen_fr_restore_x PARAMS ((rtx, rtx, rtx));
 111
 112 static enum machine_mode hfa_element_mode PARAMS ((tree, int));
 113 static void fix_range PARAMS ((const char *));
 114 static void ia64_add_gc_roots PARAMS ((void));
 115 static void ia64_init_machine_status PARAMS ((struct function *));
 116 static void ia64_mark_machine_status PARAMS ((struct function *));
 117 static void emit_insn_group_barriers PARAMS ((rtx));
 118 static void emit_predicate_relation_info PARAMS ((void));
 119 static int process_set PARAMS ((FILE *, rtx));
 120
 121 static rtx ia64_expand_fetch_and_op PARAMS ((optab, enum machine_mode,
 122                                              tree, rtx));
 123 static rtx ia64_expand_op_and_fetch PARAMS ((optab, enum machine_mode,
 124                                              tree, rtx));
 125 static rtx ia64_expand_compare_and_swap PARAMS ((enum machine_mode, int,
 126                                                  tree, rtx));
 127 static rtx ia64_expand_lock_test_and_set PARAMS ((enum machine_mode,
 128                                                   tree, rtx));
 129 static rtx ia64_expand_lock_release PARAMS ((enum machine_mode, tree, rtx));
 130
 131 \f
 132 /* Return 1 if OP is a valid operand for the MEM of a CALL insn.  */
 133
 134 int
 135 call_operand (op, mode)
 136      rtx op;
 137      enum machine_mode mode;
 138 {
 139   if (mode != GET_MODE (op))
 140     return 0;
 141
 142   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG
 143           || (GET_CODE (op) == SUBREG && GET_CODE (XEXP (op, 0)) == REG));
 144 }
 145
 146 /* Return 1 if OP refers to a symbol in the sdata section.  */
 147
 148 int
 149 sdata_symbolic_operand (op, mode)
 150      rtx op;
 151      enum machine_mode mode ATTRIBUTE_UNUSED;
 152 {
 153   switch (GET_CODE (op))
 154     {
 155     case CONST:
 156       if (GET_CODE (XEXP (op, 0)) != PLUS
 157           || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
 158         break;
 159       op = XEXP (XEXP (op, 0), 0);
 160       /* FALLTHRU */
 161
 162     case SYMBOL_REF:
 163       if (CONSTANT_POOL_ADDRESS_P (op))
 164         return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
 165       else
 166         return XSTR (op, 0)[0] == SDATA_NAME_FLAG_CHAR;
 167
 168     default:
 169       break;
 170     }
 171
 172   return 0;
 173 }
 174
 175 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load.  */
 176
 177 int
 178 got_symbolic_operand (op, mode)
 179      rtx op;
 180      enum machine_mode mode ATTRIBUTE_UNUSED;
 181 {
 182   switch (GET_CODE (op))
 183     {
 184     case CONST:
 185       op = XEXP (op, 0);
 186       if (GET_CODE (op) != PLUS)
 187         return 0;
 188       if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
 189         return 0;
 190       op = XEXP (op, 1);
 191       if (GET_CODE (op) != CONST_INT)
 192         return 0;
 193
 194         return 1;
 195
 196       /* Ok if we're not using GOT entries at all.  */
 197       if (TARGET_NO_PIC || TARGET_AUTO_PIC)
 198         return 1;
 199
 200       /* "Ok" while emitting rtl, since otherwise we won't be provided
 201          with the entire offset during emission, which makes it very
 202          hard to split the offset into high and low parts.  */
 203       if (rtx_equal_function_value_matters)
 204         return 1;
 205
 206       /* Force the low 14 bits of the constant to zero so that we do not
 207          use up so many GOT entries.  */
 208       return (INTVAL (op) & 0x3fff) == 0;
 209
 210     case SYMBOL_REF:
 211     case LABEL_REF:
 212       return 1;
 213
 214     default:
 215       break;
 216     }
 217   return 0;
 218 }
 219
 220 /* Return 1 if OP refers to a symbol.  */
 221
 222 int
 223 symbolic_operand (op, mode)
 224      rtx op;
 225      enum machine_mode mode ATTRIBUTE_UNUSED;
 226 {
 227   switch (GET_CODE (op))
 228     {
 229     case CONST:
 230     case SYMBOL_REF:
 231     case LABEL_REF:
 232       return 1;
 233
 234     default:
 235       break;
 236     }
 237   return 0;
 238 }
 239
 240 /* Return 1 if OP refers to a function.  */
 241
 242 int
 243 function_operand (op, mode)
 244      rtx op;
 245      enum machine_mode mode ATTRIBUTE_UNUSED;
 246 {
 247   if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FLAG (op))
 248     return 1;
 249   else
 250     return 0;
 251 }
 252
 253 /* Return 1 if OP is setjmp or a similar function.  */
 254
 255 /* ??? This is an unsatisfying solution.  Should rethink.  */
 256
 257 int
 258 setjmp_operand (op, mode)
 259      rtx op;
 260      enum machine_mode mode ATTRIBUTE_UNUSED;
 261 {
 262   const char *name;
 263   int retval = 0;
 264
 265   if (GET_CODE (op) != SYMBOL_REF)
 266     return 0;
 267
 268   name = XSTR (op, 0);
 269
 270   /* The following code is borrowed from special_function_p in calls.c.  */
 271
 272   /* Disregard prefix _, __ or __x.  */
 273   if (name[0] == '_')
 274     {
 275       if (name[1] == '_' && name[2] == 'x')
 276         name += 3;
 277       else if (name[1] == '_')
 278         name += 2;
 279       else
 280         name += 1;
 281     }
 282
 283   if (name[0] == 's')
 284     {
 285       retval
 286         = ((name[1] == 'e'
 287             && (! strcmp (name, "setjmp")
 288                 || ! strcmp (name, "setjmp_syscall")))
 289            || (name[1] == 'i'
 290                && ! strcmp (name, "sigsetjmp"))
 291            || (name[1] == 'a'
 292                && ! strcmp (name, "savectx")));
 293     }
 294   else if ((name[0] == 'q' && name[1] == 's'
 295             && ! strcmp (name, "qsetjmp"))
 296            || (name[0] == 'v' && name[1] == 'f'
 297                && ! strcmp (name, "vfork")))
 298     retval = 1;
 299
 300   return retval;
 301 }
 302
 303 /* Return 1 if OP is a general operand, but when pic exclude symbolic
 304    operands.  */
 305
 306 /* ??? If we drop no-pic support, can delete SYMBOL_REF, CONST, and LABEL_REF
 307    from PREDICATE_CODES.  */
 308
 309 int
 310 move_operand (op, mode)
 311      rtx op;
 312      enum machine_mode mode;
 313 {
 314   if (! TARGET_NO_PIC && symbolic_operand (op, mode))
 315     return 0;
 316
 317   return general_operand (op, mode);
 318 }
 319
 320 /* Return 1 if OP is a register operand that is (or could be) a GR reg.  */
 321
 322 int
 323 gr_register_operand (op, mode)
 324      rtx op;
 325      enum machine_mode mode;
 326 {
 327   if (! register_operand (op, mode))
 328     return 0;
 329   if (GET_CODE (op) == SUBREG)
 330     op = SUBREG_REG (op);
 331   if (GET_CODE (op) == REG)
 332     {
 333       unsigned int regno = REGNO (op);
 334       if (regno < FIRST_PSEUDO_REGISTER)
 335         return GENERAL_REGNO_P (regno);
 336     }
 337   return 1;
 338 }
 339
 340 /* Return 1 if OP is a register operand that is (or could be) an FR reg.  */
 341
 342 int
 343 fr_register_operand (op, mode)
 344      rtx op;
 345      enum machine_mode mode;
 346 {
 347   if (! register_operand (op, mode))
 348     return 0;
 349   if (GET_CODE (op) == SUBREG)
 350     op = SUBREG_REG (op);
 351   if (GET_CODE (op) == REG)
 352     {
 353       unsigned int regno = REGNO (op);
 354       if (regno < FIRST_PSEUDO_REGISTER)
 355         return FR_REGNO_P (regno);
 356     }
 357   return 1;
 358 }
 359
 360 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg.  */
 361
 362 int
 363 grfr_register_operand (op, mode)
 364      rtx op;
 365      enum machine_mode mode;
 366 {
 367   if (! register_operand (op, mode))
 368     return 0;
 369   if (GET_CODE (op) == SUBREG)
 370     op = SUBREG_REG (op);
 371   if (GET_CODE (op) == REG)
 372     {
 373       unsigned int regno = REGNO (op);
 374       if (regno < FIRST_PSEUDO_REGISTER)
 375         return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
 376     }
 377   return 1;
 378 }
 379
 380 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg.  */
 381
 382 int
 383 gr_nonimmediate_operand (op, mode)
 384      rtx op;
 385      enum machine_mode mode;
 386 {
 387   if (! nonimmediate_operand (op, mode))
 388     return 0;
 389   if (GET_CODE (op) == SUBREG)
 390     op = SUBREG_REG (op);
 391   if (GET_CODE (op) == REG)
 392     {
 393       unsigned int regno = REGNO (op);
 394       if (regno < FIRST_PSEUDO_REGISTER)
 395         return GENERAL_REGNO_P (regno);
 396     }
 397   return 1;
 398 }
 399
 400 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg.  */
 401
 402 int
 403 fr_nonimmediate_operand (op, mode)
 404      rtx op;
 405      enum machine_mode mode;
 406 {
 407   if (! nonimmediate_operand (op, mode))
 408     return 0;
 409   if (GET_CODE (op) == SUBREG)
 410     op = SUBREG_REG (op);
 411   if (GET_CODE (op) == REG)
 412     {
 413       unsigned int regno = REGNO (op);
 414       if (regno < FIRST_PSEUDO_REGISTER)
 415         return FR_REGNO_P (regno);
 416     }
 417   return 1;
 418 }
 419
 420 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg.  */
 421
 422 int
 423 grfr_nonimmediate_operand (op, mode)
 424      rtx op;
 425      enum machine_mode mode;
 426 {
 427   if (! nonimmediate_operand (op, mode))
 428     return 0;
 429   if (GET_CODE (op) == SUBREG)
 430     op = SUBREG_REG (op);
 431   if (GET_CODE (op) == REG)
 432     {
 433       unsigned int regno = REGNO (op);
 434       if (regno < FIRST_PSEUDO_REGISTER)
 435         return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
 436     }
 437   return 1;
 438 }
 439
 440 /* Return 1 if OP is a GR register operand, or zero.  */
 441
 442 int
 443 gr_reg_or_0_operand (op, mode)
 444      rtx op;
 445      enum machine_mode mode;
 446 {
 447   return (op == const0_rtx || gr_register_operand (op, mode));
 448 }
 449
 450 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand.  */
 451
 452 int
 453 gr_reg_or_5bit_operand (op, mode)
 454      rtx op;
 455      enum machine_mode mode;
 456 {
 457   return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
 458           || GET_CODE (op) == CONSTANT_P_RTX
 459           || gr_register_operand (op, mode));
 460 }
 461
 462 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand.  */
 463
 464 int
 465 gr_reg_or_6bit_operand (op, mode)
 466      rtx op;
 467      enum machine_mode mode;
 468 {
 469   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
 470           || GET_CODE (op) == CONSTANT_P_RTX
 471           || gr_register_operand (op, mode));
 472 }
 473
 474 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand.  */
 475
 476 int
 477 gr_reg_or_8bit_operand (op, mode)
 478      rtx op;
 479      enum machine_mode mode;
 480 {
 481   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
 482           || GET_CODE (op) == CONSTANT_P_RTX
 483           || gr_register_operand (op, mode));
 484 }
 485
 486 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate.  */
 487
 488 int
 489 grfr_reg_or_8bit_operand (op, mode)
 490      rtx op;
 491      enum machine_mode mode;
 492 {
 493   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
 494           || GET_CODE (op) == CONSTANT_P_RTX
 495           || grfr_register_operand (op, mode));
 496 }
 497
 498 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
 499    operand.  */
 500
 501 int
 502 gr_reg_or_8bit_adjusted_operand (op, mode)
 503      rtx op;
 504      enum machine_mode mode;
 505 {
 506   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
 507           || GET_CODE (op) == CONSTANT_P_RTX
 508           || gr_register_operand (op, mode));
 509 }
 510
 511 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
 512    immediate and an 8 bit adjusted immediate operand.  This is necessary
 513    because when we emit a compare, we don't know what the condition will be,
 514    so we need the union of the immediates accepted by GT and LT.  */
 515
 516 int
 517 gr_reg_or_8bit_and_adjusted_operand (op, mode)
 518      rtx op;
 519      enum machine_mode mode;
 520 {
 521   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
 522            && CONST_OK_FOR_L (INTVAL (op)))
 523           || GET_CODE (op) == CONSTANT_P_RTX
 524           || gr_register_operand (op, mode));
 525 }
 526
 527 /* Return 1 if OP is a register operand, or a 14 bit immediate operand.  */
 528
 529 int
 530 gr_reg_or_14bit_operand (op, mode)
 531      rtx op;
 532      enum machine_mode mode;
 533 {
 534   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
 535           || GET_CODE (op) == CONSTANT_P_RTX
 536           || gr_register_operand (op, mode));
 537 }
 538
 539 /* Return 1 if OP is a register operand, or a 22 bit immediate operand.  */
 540
 541 int
 542 gr_reg_or_22bit_operand (op, mode)
 543      rtx op;
 544      enum machine_mode mode;
 545 {
 546   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
 547           || GET_CODE (op) == CONSTANT_P_RTX
 548           || gr_register_operand (op, mode));
 549 }
 550
 551 /* Return 1 if OP is a 6 bit immediate operand.  */
 552
 553 int
 554 shift_count_operand (op, mode)
 555      rtx op;
 556      enum machine_mode mode ATTRIBUTE_UNUSED;
 557 {
 558   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
 559           || GET_CODE (op) == CONSTANT_P_RTX);
 560 }
 561
 562 /* Return 1 if OP is a 5 bit immediate operand.  */
 563
 564 int
 565 shift_32bit_count_operand (op, mode)
 566      rtx op;
 567      enum machine_mode mode ATTRIBUTE_UNUSED;
 568 {
 569   return ((GET_CODE (op) == CONST_INT
 570            && (INTVAL (op) >= 0 && INTVAL (op) < 32))
 571           || GET_CODE (op) == CONSTANT_P_RTX);
 572 }
 573
 574 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand.  */
 575
 576 int
 577 shladd_operand (op, mode)
 578      rtx op;
 579      enum machine_mode mode ATTRIBUTE_UNUSED;
 580 {
 581   return (GET_CODE (op) == CONST_INT
 582           && (INTVAL (op) == 2 || INTVAL (op) == 4
 583               || INTVAL (op) == 8 || INTVAL (op) == 16));
 584 }
 585
 586 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
 587
 588 int
 589 fetchadd_operand (op, mode)
 590      rtx op;
 591      enum machine_mode mode ATTRIBUTE_UNUSED;
 592 {
 593   return (GET_CODE (op) == CONST_INT
 594           && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
 595               INTVAL (op) == -4  || INTVAL (op) == -1 ||
 596               INTVAL (op) == 1   || INTVAL (op) == 4  ||
 597               INTVAL (op) == 8   || INTVAL (op) == 16));
 598 }
 599
 600 /* Return 1 if OP is a floating-point constant zero, one, or a register.  */
 601
 602 int
 603 fr_reg_or_fp01_operand (op, mode)
 604      rtx op;
 605      enum machine_mode mode;
 606 {
 607   return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
 608           || fr_register_operand (op, mode));
 609 }
 610
 611 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
 612    POST_MODIFY with a REG as displacement.  */
 613
 614 int
 615 destination_operand (op, mode)
 616      rtx op;
 617      enum machine_mode mode;
 618 {
 619   if (! nonimmediate_operand (op, mode))
 620     return 0;
 621   if (GET_CODE (op) == MEM
 622       && GET_CODE (XEXP (op, 0)) == POST_MODIFY
 623       && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) == REG)
 624     return 0;
 625   return 1;
 626 }
 627
 628 /* Like memory_operand, but don't allow post-increments.  */
 629
 630 int
 631 not_postinc_memory_operand (op, mode)
 632      rtx op;
 633      enum machine_mode mode;
 634 {
 635   return (memory_operand (op, mode)
 636           && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
 637 }
 638
 639 /* Return 1 if this is a comparison operator, which accepts an normal 8-bit
 640    signed immediate operand.  */
 641
 642 int
 643 normal_comparison_operator (op, mode)
 644     register rtx op;
 645     enum machine_mode mode;
 646 {
 647   enum rtx_code code = GET_CODE (op);
 648   return ((mode == VOIDmode || GET_MODE (op) == mode)
 649           && (code == EQ || code == NE
 650               || code == GT || code == LE || code == GTU || code == LEU));
 651 }
 652
 653 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
 654    signed immediate operand.  */
 655
 656 int
 657 adjusted_comparison_operator (op, mode)
 658     register rtx op;
 659     enum machine_mode mode;
 660 {
 661   enum rtx_code code = GET_CODE (op);
 662   return ((mode == VOIDmode || GET_MODE (op) == mode)
 663           && (code == LT || code == GE || code == LTU || code == GEU));
 664 }
 665
 666 /* Return 1 if this is a signed inequality operator.  */
 667
 668 int
 669 signed_inequality_operator (op, mode)
 670     register rtx op;
 671     enum machine_mode mode;
 672 {
 673   enum rtx_code code = GET_CODE (op);
 674   return ((mode == VOIDmode || GET_MODE (op) == mode)
 675           && (code == GE || code == GT
 676               || code == LE || code == LT));
 677 }
 678
 679 /* Return 1 if this operator is valid for predication.  */
 680
 681 int
 682 predicate_operator (op, mode)
 683     register rtx op;
 684     enum machine_mode mode;
 685 {
 686   enum rtx_code code = GET_CODE (op);
 687   return ((GET_MODE (op) == mode || mode == VOIDmode)
 688           && (code == EQ || code == NE));
 689 }
 690
 691 /* Return 1 if this is the ar.lc register.  */
 692
 693 int
 694 ar_lc_reg_operand (op, mode)
 695      register rtx op;
 696      enum machine_mode mode;
 697 {
 698   return (GET_MODE (op) == DImode
 699           && (mode == DImode || mode == VOIDmode)
 700           && GET_CODE (op) == REG
 701           && REGNO (op) == AR_LC_REGNUM);
 702 }
 703
 704 /* Return 1 if this is the ar.ccv register.  */
 705
 706 int
 707 ar_ccv_reg_operand (op, mode)
 708      register rtx op;
 709      enum machine_mode mode;
 710 {
 711   return ((GET_MODE (op) == mode || mode == VOIDmode)
 712           && GET_CODE (op) == REG
 713           && REGNO (op) == AR_CCV_REGNUM);
 714 }
 715
 716 /* Like general_operand, but don't allow (mem (addressof)).  */
 717
 718 int
 719 general_tfmode_operand (op, mode)
 720      rtx op;
 721      enum machine_mode mode;
 722 {
 723   if (! general_operand (op, mode))
 724     return 0;
 725   if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
 726     return 0;
 727   return 1;
 728 }
 729
 730 /* Similarly.  */
 731
 732 int
 733 destination_tfmode_operand (op, mode)
 734      rtx op;
 735      enum machine_mode mode;
 736 {
 737   if (! destination_operand (op, mode))
 738     return 0;
 739   if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
 740     return 0;
 741   return 1;
 742 }
 743
 744 /* Similarly.  */
 745
 746 int
 747 tfreg_or_fp01_operand (op, mode)
 748      rtx op;
 749      enum machine_mode mode;
 750 {
 751   if (GET_CODE (op) == SUBREG)
 752     return 0;
 753   return fr_reg_or_fp01_operand (op, mode);
 754 }
 755 \f
 756 /* Return 1 if the operands of a move are ok.  */
 757
 758 int
 759 ia64_move_ok (dst, src)
 760      rtx dst, src;
 761 {
 762   /* If we're under init_recog_no_volatile, we'll not be able to use
 763      memory_operand.  So check the code directly and don't worry about
 764      the validity of the underlying address, which should have been
 765      checked elsewhere anyway.  */
 766   if (GET_CODE (dst) != MEM)
 767     return 1;
 768   if (GET_CODE (src) == MEM)
 769     return 0;
 770   if (register_operand (src, VOIDmode))
 771     return 1;
 772
 773   /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0.  */
 774   if (INTEGRAL_MODE_P (GET_MODE (dst)))
 775     return src == const0_rtx;
 776   else
 777     return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
 778 }
 779
 780 /* Check if OP is a mask suitible for use with SHIFT in a dep.z instruction.
 781    Return the length of the field, or <= 0 on failure.  */
 782
 783 int
 784 ia64_depz_field_mask (rop, rshift)
 785      rtx rop, rshift;
 786 {
 787   unsigned HOST_WIDE_INT op = INTVAL (rop);
 788   unsigned HOST_WIDE_INT shift = INTVAL (rshift);
 789
 790   /* Get rid of the zero bits we're shifting in.  */
 791   op >>= shift;
 792
 793   /* We must now have a solid block of 1's at bit 0.  */
 794   return exact_log2 (op + 1);
 795 }
 796
 797 /* Expand a symbolic constant load.  */
 798 /* ??? Should generalize this, so that we can also support 32 bit pointers.  */
 799
 800 void
 801 ia64_expand_load_address (dest, src)
 802       rtx dest, src;
 803 {
 804   rtx temp;
 805
 806   /* The destination could be a MEM during initial rtl generation,
 807      which isn't a valid destination for the PIC load address patterns.  */
 808   if (! register_operand (dest, DImode))
 809     temp = gen_reg_rtx (DImode);
 810   else
 811     temp = dest;
 812
 813   if (TARGET_AUTO_PIC)
 814     emit_insn (gen_load_gprel64 (temp, src));
 815   else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FLAG (src))
 816     emit_insn (gen_load_fptr (temp, src));
 817   else if (sdata_symbolic_operand (src, DImode))
 818     emit_insn (gen_load_gprel (temp, src));
 819   else if (GET_CODE (src) == CONST
 820            && GET_CODE (XEXP (src, 0)) == PLUS
 821            && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
 822            && (INTVAL (XEXP (XEXP (src, 0), 1)) & 0x1fff) != 0)
 823     {
 824       rtx subtarget = no_new_pseudos ? temp : gen_reg_rtx (DImode);
 825       rtx sym = XEXP (XEXP (src, 0), 0);
 826       HOST_WIDE_INT ofs, hi, lo;
 827
 828       /* Split the offset into a sign extended 14-bit low part
 829          and a complementary high part.  */
 830       ofs = INTVAL (XEXP (XEXP (src, 0), 1));
 831       lo = ((ofs & 0x3fff) ^ 0x2000) - 0x2000;
 832       hi = ofs - lo;
 833
 834       emit_insn (gen_load_symptr (subtarget, plus_constant (sym, hi)));
 835       emit_insn (gen_adddi3 (temp, subtarget, GEN_INT (lo)));
 836     }
 837   else
 838     emit_insn (gen_load_symptr (temp, src));
 839
 840   if (temp != dest)
 841     emit_move_insn (dest, temp);
 842 }
 843
 844 rtx
 845 ia64_gp_save_reg (setjmp_p)
 846      int setjmp_p;
 847 {
 848   rtx save = cfun->machine->ia64_gp_save;
 849
 850   if (save != NULL)
 851     {
 852       /* We can't save GP in a pseudo if we are calling setjmp, because
 853          pseudos won't be restored by longjmp.  For now, we save it in r4.  */
 854       /* ??? It would be more efficient to save this directly into a stack
 855          slot.  Unfortunately, the stack slot address gets cse'd across
 856          the setjmp call because the NOTE_INSN_SETJMP note is in the wrong
 857          place.  */
 858
 859       /* ??? Get the barf bag, Virginia.  We've got to replace this thing
 860          in place, since this rtx is used in exception handling receivers.
 861          Moreover, we must get this rtx out of regno_reg_rtx or reload
 862          will do the wrong thing.  */
 863       unsigned int old_regno = REGNO (save);
 864       if (setjmp_p && old_regno != GR_REG (4))
 865         {
 866           REGNO (save) = GR_REG (4);
 867           regno_reg_rtx[old_regno] = gen_rtx_raw_REG (DImode, old_regno);
 868         }
 869     }
 870   else
 871     {
 872       if (setjmp_p)
 873         save = gen_rtx_REG (DImode, GR_REG (4));
 874       else if (! optimize)
 875         save = gen_rtx_REG (DImode, LOC_REG (0));
 876       else
 877         save = gen_reg_rtx (DImode);
 878       cfun->machine->ia64_gp_save = save;
 879     }
 880
 881   return save;
 882 }
 883
 884 /* Split a post-reload TImode reference into two DImode components.  */
 885
 886 rtx
 887 ia64_split_timode (out, in, scratch)
 888      rtx out[2];
 889      rtx in, scratch;
 890 {
 891   switch (GET_CODE (in))
 892     {
 893     case REG:
 894       out[0] = gen_rtx_REG (DImode, REGNO (in));
 895       out[1] = gen_rtx_REG (DImode, REGNO (in) + 1);
 896       return NULL_RTX;
 897
 898     case MEM:
 899       {
 900         rtx base = XEXP (in, 0);
 901
 902         switch (GET_CODE (base))
 903           {
 904           case REG:
 905             out[0] = change_address (in, DImode, NULL_RTX);
 906             break;
 907           case POST_MODIFY:
 908             base = XEXP (base, 0);
 909             out[0] = change_address (in, DImode, NULL_RTX);
 910             break;
 911
 912           /* Since we're changing the mode, we need to change to POST_MODIFY
 913              as well to preserve the size of the increment.  Either that or
 914              do the update in two steps, but we've already got this scratch
 915              register handy so let's use it.  */
 916           case POST_INC:
 917             base = XEXP (base, 0);
 918             out[0] = change_address (in, DImode,
 919               gen_rtx_POST_MODIFY (Pmode, base,plus_constant (base, 16)));
 920             break;
 921           case POST_DEC:
 922             base = XEXP (base, 0);
 923             out[0] = change_address (in, DImode,
 924               gen_rtx_POST_MODIFY (Pmode, base,plus_constant (base, -16)));
 925             break;
 926           default:
 927             abort ();
 928           }
 929
 930         if (scratch == NULL_RTX)
 931           abort ();
 932         out[1] = change_address (in, DImode, scratch);
 933         return gen_adddi3 (scratch, base, GEN_INT (8));
 934       }
 935
 936     case CONST_INT:
 937     case CONST_DOUBLE:
 938       split_double (in, &out[0], &out[1]);
 939       return NULL_RTX;
 940
 941     default:
 942       abort ();
 943     }
 944 }
 945
 946 /* ??? Fixing GR->FR TFmode moves during reload is hard.  You need to go
 947    through memory plus an extra GR scratch register.  Except that you can
 948    either get the first from SECONDARY_MEMORY_NEEDED or the second from
 949    SECONDARY_RELOAD_CLASS, but not both.
 950
 951    We got into problems in the first place by allowing a construct like
 952    (subreg:TF (reg:TI)), which we got from a union containing a long double.
 953    This solution attempts to prevent this situation from ocurring.  When
 954    we see something like the above, we spill the inner register to memory.  */
 955
 956 rtx
 957 spill_tfmode_operand (in, force)
 958      rtx in;
 959      int force;
 960 {
 961   if (GET_CODE (in) == SUBREG
 962       && GET_MODE (SUBREG_REG (in)) == TImode
 963       && GET_CODE (SUBREG_REG (in)) == REG)
 964     {
 965       rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE);
 966       return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
 967     }
 968   else if (force && GET_CODE (in) == REG)
 969     {
 970       rtx mem = gen_mem_addressof (in, NULL_TREE);
 971       return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
 972     }
 973   else if (GET_CODE (in) == MEM
 974            && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
 975     {
 976       return change_address (in, TFmode, copy_to_reg (XEXP (in, 0)));
 977     }
 978   else
 979     return in;
 980 }
 981
 982 /* Emit comparison instruction if necessary, returning the expression
 983    that holds the compare result in the proper mode.  */
 984
 985 rtx
 986 ia64_expand_compare (code, mode)
 987      enum rtx_code code;
 988      enum machine_mode mode;
 989 {
 990   rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
 991   rtx cmp;
 992
 993   /* If we have a BImode input, then we already have a compare result, and
 994      do not need to emit another comparison.  */
 995   if (GET_MODE (op0) == BImode)
 996     {
 997       if ((code == NE || code == EQ) && op1 == const0_rtx)
 998         cmp = op0;
 999       else
1000         abort ();
1001     }
1002   else
1003     {
1004       cmp = gen_reg_rtx (BImode);
1005       emit_insn (gen_rtx_SET (VOIDmode, cmp,
1006                               gen_rtx_fmt_ee (code, BImode, op0, op1)));
1007       code = NE;
1008     }
1009
1010   return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1011 }
1012
1013 /* Emit the appropriate sequence for a call.  */
1014
1015 void
1016 ia64_expand_call (retval, addr, nextarg, sibcall_p)
1017      rtx retval;
1018      rtx addr;
1019      rtx nextarg;
1020      int sibcall_p;
1021 {
1022   rtx insn, b0, gp_save, narg_rtx;
1023   int narg;
1024
1025   addr = XEXP (addr, 0);
1026   b0 = gen_rtx_REG (DImode, R_BR (0));
1027
1028   if (! nextarg)
1029     narg = 0;
1030   else if (IN_REGNO_P (REGNO (nextarg)))
1031     narg = REGNO (nextarg) - IN_REG (0);
1032   else
1033     narg = REGNO (nextarg) - OUT_REG (0);
1034   narg_rtx = GEN_INT (narg);
1035
1036   if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1037     {
1038       if (sibcall_p)
1039         insn = gen_sibcall_nopic (addr, narg_rtx, b0);
1040       else if (! retval)
1041         insn = gen_call_nopic (addr, narg_rtx, b0);
1042       else
1043         insn = gen_call_value_nopic (retval, addr, narg_rtx, b0);
1044       emit_call_insn (insn);
1045       return;
1046     }
1047
1048   if (sibcall_p)
1049     gp_save = NULL_RTX;
1050   else
1051     gp_save = ia64_gp_save_reg (setjmp_operand (addr, VOIDmode));
1052
1053   /* If this is an indirect call, then we have the address of a descriptor.  */
1054   if (! symbolic_operand (addr, VOIDmode))
1055     {
1056       rtx dest;
1057
1058       if (! sibcall_p)
1059         emit_move_insn (gp_save, pic_offset_table_rtx);
1060
1061       dest = force_reg (DImode, gen_rtx_MEM (DImode, addr));
1062       emit_move_insn (pic_offset_table_rtx,
1063                       gen_rtx_MEM (DImode, plus_constant (addr, 8)));
1064
1065       if (sibcall_p)
1066         insn = gen_sibcall_pic (dest, narg_rtx, b0);
1067       else if (! retval)
1068         insn = gen_call_pic (dest, narg_rtx, b0);
1069       else
1070         insn = gen_call_value_pic (retval, dest, narg_rtx, b0);
1071       emit_call_insn (insn);
1072
1073       if (! sibcall_p)
1074         emit_move_insn (pic_offset_table_rtx, gp_save);
1075     }
1076   else if (TARGET_CONST_GP)
1077     {
1078       if (sibcall_p)
1079         insn = gen_sibcall_nopic (addr, narg_rtx, b0);
1080       else if (! retval)
1081         insn = gen_call_nopic (addr, narg_rtx, b0);
1082       else
1083         insn = gen_call_value_nopic (retval, addr, narg_rtx, b0);
1084       emit_call_insn (insn);
1085     }
1086   else
1087     {
1088       if (sibcall_p)
1089         emit_call_insn (gen_sibcall_pic (addr, narg_rtx, b0));
1090       else
1091         {
1092           emit_move_insn (gp_save, pic_offset_table_rtx);
1093
1094           if (! retval)
1095             insn = gen_call_pic (addr, narg_rtx, b0);
1096           else
1097             insn = gen_call_value_pic (retval, addr, narg_rtx, b0);
1098           emit_call_insn (insn);
1099
1100           emit_move_insn (pic_offset_table_rtx, gp_save);
1101         }
1102     }
1103 }
1104 \f
1105 /* Begin the assembly file.  */
1106
1107 void
1108 emit_safe_across_calls (f)
1109      FILE *f;
1110 {
1111   unsigned int rs, re;
1112   int out_state;
1113
1114   rs = 1;
1115   out_state = 0;
1116   while (1)
1117     {
1118       while (rs < 64 && call_used_regs[PR_REG (rs)])
1119         rs++;
1120       if (rs >= 64)
1121         break;
1122       for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1123         continue;
1124       if (out_state == 0)
1125         {
1126           fputs ("\t.pred.safe_across_calls ", f);
1127           out_state = 1;
1128         }
1129       else
1130         fputc (',', f);
1131       if (re == rs + 1)
1132         fprintf (f, "p%u", rs);
1133       else
1134         fprintf (f, "p%u-p%u", rs, re - 1);
1135       rs = re + 1;
1136     }
1137   if (out_state)
1138     fputc ('\n', f);
1139 }
1140
1141
1142 /* Structure to be filled in by ia64_compute_frame_size with register
1143    save masks and offsets for the current function.  */
1144
1145 struct ia64_frame_info
1146 {
1147   HOST_WIDE_INT total_size;     /* size of the stack frame, not including
1148                                    the caller's scratch area.  */
1149   HOST_WIDE_INT spill_cfa_off;  /* top of the reg spill area from the cfa.  */
1150   HOST_WIDE_INT spill_size;     /* size of the gr/br/fr spill area.  */
1151   HOST_WIDE_INT extra_spill_size;  /* size of spill area for others.  */
1152   HARD_REG_SET mask;            /* mask of saved registers.  */
1153   unsigned int gr_used_mask;    /* mask of registers in use as gr spill
1154                                    registers or long-term scratches.  */
1155   int n_spilled;                /* number of spilled registers.  */
1156   int reg_fp;                   /* register for fp.  */
1157   int reg_save_b0;              /* save register for b0.  */
1158   int reg_save_pr;              /* save register for prs.  */
1159   int reg_save_ar_pfs;          /* save register for ar.pfs.  */
1160   int reg_save_ar_unat;         /* save register for ar.unat.  */
1161   int reg_save_ar_lc;           /* save register for ar.lc.  */
1162   int n_input_regs;             /* number of input registers used.  */
1163   int n_local_regs;             /* number of local registers used.  */
1164   int n_output_regs;            /* number of output registers used.  */
1165   int n_rotate_regs;            /* number of rotating registers used.  */
1166
1167   char need_regstk;             /* true if a .regstk directive needed.  */
1168   char initialized;             /* true if the data is finalized.  */
1169 };
1170
1171 /* Current frame information calculated by ia64_compute_frame_size.  */
1172 static struct ia64_frame_info current_frame_info;
1173
1174 /* Helper function for ia64_compute_frame_size: find an appropriate general
1175    register to spill some special register to.  SPECIAL_SPILL_MASK contains
1176    bits in GR0 to GR31 that have already been allocated by this routine.
1177    TRY_LOCALS is true if we should attempt to locate a local regnum.  */
1178
1179 static int
1180 find_gr_spill (try_locals)
1181      int try_locals;
1182 {
1183   int regno;
1184
1185   /* If this is a leaf function, first try an otherwise unused
1186      call-clobbered register.  */
1187   if (current_function_is_leaf)
1188     {
1189       for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1190         if (! regs_ever_live[regno]
1191             && call_used_regs[regno]
1192             && ! fixed_regs[regno]
1193             && ! global_regs[regno]
1194             && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1195           {
1196             current_frame_info.gr_used_mask |= 1 << regno;
1197             return regno;
1198           }
1199     }
1200
1201   if (try_locals)
1202     {
1203       regno = current_frame_info.n_local_regs;
1204       if (regno < 80)
1205         {
1206           current_frame_info.n_local_regs = regno + 1;
1207           return LOC_REG (0) + regno;
1208         }
1209     }
1210
1211   /* Failed to find a general register to spill to.  Must use stack.  */
1212   return 0;
1213 }
1214
1215 /* In order to make for nice schedules, we try to allocate every temporary
1216    to a different register.  We must of course stay away from call-saved,
1217    fixed, and global registers.  We must also stay away from registers
1218    allocated in current_frame_info.gr_used_mask, since those include regs
1219    used all through the prologue.
1220
1221    Any register allocated here must be used immediately.  The idea is to
1222    aid scheduling, not to solve data flow problems.  */
1223
1224 static int last_scratch_gr_reg;
1225
1226 static int
1227 next_scratch_gr_reg ()
1228 {
1229   int i, regno;
1230
1231   for (i = 0; i < 32; ++i)
1232     {
1233       regno = (last_scratch_gr_reg + i + 1) & 31;
1234       if (call_used_regs[regno]
1235           && ! fixed_regs[regno]
1236           && ! global_regs[regno]
1237           && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1238         {
1239           last_scratch_gr_reg = regno;
1240           return regno;
1241         }
1242     }
1243
1244   /* There must be _something_ available.  */
1245   abort ();
1246 }
1247
1248 /* Helper function for ia64_compute_frame_size, called through
1249    diddle_return_value.  Mark REG in current_frame_info.gr_used_mask.  */
1250
1251 static void
1252 mark_reg_gr_used_mask (reg, data)
1253      rtx reg;
1254      void *data ATTRIBUTE_UNUSED;
1255 {
1256   unsigned int regno = REGNO (reg);
1257   if (regno < 32)
1258     current_frame_info.gr_used_mask |= 1 << regno;
1259 }
1260
1261 /* Returns the number of bytes offset between the frame pointer and the stack
1262    pointer for the current function.  SIZE is the number of bytes of space
1263    needed for local variables.  */
1264
1265 static void
1266 ia64_compute_frame_size (size)
1267      HOST_WIDE_INT size;
1268 {
1269   HOST_WIDE_INT total_size;
1270   HOST_WIDE_INT spill_size = 0;
1271   HOST_WIDE_INT extra_spill_size = 0;
1272   HOST_WIDE_INT pretend_args_size;
1273   HARD_REG_SET mask;
1274   int n_spilled = 0;
1275   int spilled_gr_p = 0;
1276   int spilled_fr_p = 0;
1277   unsigned int regno;
1278   int i;
1279
1280   if (current_frame_info.initialized)
1281     return;
1282
1283   memset (&current_frame_info, 0, sizeof current_frame_info);
1284   CLEAR_HARD_REG_SET (mask);
1285
1286   /* Don't allocate scratches to the return register.  */
1287   diddle_return_value (mark_reg_gr_used_mask, NULL);
1288
1289   /* Don't allocate scratches to the EH scratch registers.  */
1290   if (cfun->machine->ia64_eh_epilogue_sp)
1291     mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
1292   if (cfun->machine->ia64_eh_epilogue_bsp)
1293     mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
1294
1295   /* Find the size of the register stack frame.  We have only 80 local
1296      registers, because we reserve 8 for the inputs and 8 for the
1297      outputs.  */
1298
1299   /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1300      since we'll be adjusting that down later.  */
1301   regno = LOC_REG (78) + ! frame_pointer_needed;
1302   for (; regno >= LOC_REG (0); regno--)
1303     if (regs_ever_live[regno])
1304       break;
1305   current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
1306
1307   if (cfun->machine->n_varargs > 0)
1308     current_frame_info.n_input_regs = 8;
1309   else
1310     {
1311       for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
1312         if (regs_ever_live[regno])
1313           break;
1314       current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
1315     }
1316
1317   for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
1318     if (regs_ever_live[regno])
1319       break;
1320   i = regno - OUT_REG (0) + 1;
1321
1322   /* When -p profiling, we need one output register for the mcount argument.
1323      Likwise for -a profiling for the bb_init_func argument.  For -ax
1324      profiling, we need two output registers for the two bb_init_trace_func
1325      arguments.  */
1326   if (profile_flag || profile_block_flag == 1)
1327     i = MAX (i, 1);
1328   else if (profile_block_flag == 2)
1329     i = MAX (i, 2);
1330   current_frame_info.n_output_regs = i;
1331
1332   /* ??? No rotating register support yet.  */
1333   current_frame_info.n_rotate_regs = 0;
1334
1335   /* Discover which registers need spilling, and how much room that
1336      will take.  Begin with floating point and general registers,
1337      which will always wind up on the stack.  */
1338
1339   for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
1340     if (regs_ever_live[regno] && ! call_used_regs[regno])
1341       {
1342         SET_HARD_REG_BIT (mask, regno);
1343         spill_size += 16;
1344         n_spilled += 1;
1345         spilled_fr_p = 1;
1346       }
1347
1348   for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1349     if (regs_ever_live[regno] && ! call_used_regs[regno])
1350       {
1351         SET_HARD_REG_BIT (mask, regno);
1352         spill_size += 8;
1353         n_spilled += 1;
1354         spilled_gr_p = 1;
1355       }
1356
1357   for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
1358     if (regs_ever_live[regno] && ! call_used_regs[regno])
1359       {
1360         SET_HARD_REG_BIT (mask, regno);
1361         spill_size += 8;
1362         n_spilled += 1;
1363       }
1364
1365   /* Now come all special registers that might get saved in other
1366      general registers.  */
1367
1368   if (frame_pointer_needed)
1369     {
1370       current_frame_info.reg_fp = find_gr_spill (1);
1371       /* We should have gotten at least LOC79, since that's what
1372          HARD_FRAME_POINTER_REGNUM is.  */
1373       if (current_frame_info.reg_fp == 0)
1374         abort ();
1375     }
1376
1377   if (! current_function_is_leaf)
1378     {
1379       /* Emit a save of BR0 if we call other functions.  Do this even
1380          if this function doesn't return, as EH depends on this to be
1381          able to unwind the stack.  */
1382       SET_HARD_REG_BIT (mask, BR_REG (0));
1383
1384       current_frame_info.reg_save_b0 = find_gr_spill (1);
1385       if (current_frame_info.reg_save_b0 == 0)
1386         {
1387           spill_size += 8;
1388           n_spilled += 1;
1389         }
1390
1391       /* Similarly for ar.pfs.  */
1392       SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
1393       current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
1394       if (current_frame_info.reg_save_ar_pfs == 0)
1395         {
1396           extra_spill_size += 8;
1397           n_spilled += 1;
1398         }
1399     }
1400   else
1401     {
1402       if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
1403         {
1404           SET_HARD_REG_BIT (mask, BR_REG (0));
1405           spill_size += 8;
1406           n_spilled += 1;
1407         }
1408     }
1409
1410   /* Unwind descriptor hackery: things are most efficient if we allocate
1411      consecutive GR save registers for RP, PFS, FP in that order. However,
1412      it is absolutely critical that FP get the only hard register that's
1413      guaranteed to be free, so we allocated it first.  If all three did
1414      happen to be allocated hard regs, and are consecutive, rearrange them
1415      into the preferred order now.  */
1416   if (current_frame_info.reg_fp != 0
1417       && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
1418       && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
1419     {
1420       current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
1421       current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
1422       current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
1423     }
1424
1425   /* See if we need to store the predicate register block.  */
1426   for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1427     if (regs_ever_live[regno] && ! call_used_regs[regno])
1428       break;
1429   if (regno <= PR_REG (63))
1430     {
1431       SET_HARD_REG_BIT (mask, PR_REG (0));
1432       current_frame_info.reg_save_pr = find_gr_spill (1);
1433       if (current_frame_info.reg_save_pr == 0)
1434         {
1435           extra_spill_size += 8;
1436           n_spilled += 1;
1437         }
1438
1439       /* ??? Mark them all as used so that register renaming and such
1440          are free to use them.  */
1441       for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1442         regs_ever_live[regno] = 1;
1443     }
1444
1445   /* If we're forced to use st8.spill, we're forced to save and restore
1446      ar.unat as well.  */
1447   if (spilled_gr_p || cfun->machine->n_varargs)
1448     {
1449       SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
1450       current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
1451       if (current_frame_info.reg_save_ar_unat == 0)
1452         {
1453           extra_spill_size += 8;
1454           n_spilled += 1;
1455         }
1456     }
1457
1458   if (regs_ever_live[AR_LC_REGNUM])
1459     {
1460       SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
1461       current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
1462       if (current_frame_info.reg_save_ar_lc == 0)
1463         {
1464           extra_spill_size += 8;
1465           n_spilled += 1;
1466         }
1467     }
1468
1469   /* If we have an odd number of words of pretend arguments written to
1470      the stack, then the FR save area will be unaligned.  We round the
1471      size of this area up to keep things 16 byte aligned.  */
1472   if (spilled_fr_p)
1473     pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
1474   else
1475     pretend_args_size = current_function_pretend_args_size;
1476
1477   total_size = (spill_size + extra_spill_size + size + pretend_args_size
1478                 + current_function_outgoing_args_size);
1479   total_size = IA64_STACK_ALIGN (total_size);
1480
1481   /* We always use the 16-byte scratch area provided by the caller, but
1482      if we are a leaf function, there's no one to which we need to provide
1483      a scratch area.  */
1484   if (current_function_is_leaf)
1485     total_size = MAX (0, total_size - 16);
1486
1487   current_frame_info.total_size = total_size;
1488   current_frame_info.spill_cfa_off = pretend_args_size - 16;
1489   current_frame_info.spill_size = spill_size;
1490   current_frame_info.extra_spill_size = extra_spill_size;
1491   COPY_HARD_REG_SET (current_frame_info.mask, mask);
1492   current_frame_info.n_spilled = n_spilled;
1493   current_frame_info.initialized = reload_completed;
1494 }
1495
1496 /* Compute the initial difference between the specified pair of registers.  */
1497
1498 HOST_WIDE_INT
1499 ia64_initial_elimination_offset (from, to)
1500      int from, to;
1501 {
1502   HOST_WIDE_INT offset;
1503
1504   ia64_compute_frame_size (get_frame_size ());
1505   switch (from)
1506     {
1507     case FRAME_POINTER_REGNUM:
1508       if (to == HARD_FRAME_POINTER_REGNUM)
1509         {
1510           if (current_function_is_leaf)
1511             offset = -current_frame_info.total_size;
1512           else
1513             offset = -(current_frame_info.total_size
1514                        - current_function_outgoing_args_size - 16);
1515         }
1516       else if (to == STACK_POINTER_REGNUM)
1517         {
1518           if (current_function_is_leaf)
1519             offset = 0;
1520           else
1521             offset = 16 + current_function_outgoing_args_size;
1522         }
1523       else
1524         abort ();
1525       break;
1526
1527     case ARG_POINTER_REGNUM:
1528       /* Arguments start above the 16 byte save area, unless stdarg
1529          in which case we store through the 16 byte save area.  */
1530       if (to == HARD_FRAME_POINTER_REGNUM)
1531         offset = 16 - current_function_pretend_args_size;
1532       else if (to == STACK_POINTER_REGNUM)
1533         offset = (current_frame_info.total_size
1534                   + 16 - current_function_pretend_args_size);
1535       else
1536         abort ();
1537       break;
1538
1539     case RETURN_ADDRESS_POINTER_REGNUM:
1540       offset = 0;
1541       break;
1542
1543     default:
1544       abort ();
1545     }
1546
1547   return offset;
1548 }
1549
1550 /* If there are more than a trivial number of register spills, we use
1551    two interleaved iterators so that we can get two memory references
1552    per insn group.
1553
1554    In order to simplify things in the prologue and epilogue expanders,
1555    we use helper functions to fix up the memory references after the
1556    fact with the appropriate offsets to a POST_MODIFY memory mode.
1557    The following data structure tracks the state of the two iterators
1558    while insns are being emitted.  */
1559
1560 struct spill_fill_data
1561 {
1562   rtx init_after;               /* point at which to emit intializations */
1563   rtx init_reg[2];              /* initial base register */
1564   rtx iter_reg[2];              /* the iterator registers */
1565   rtx *prev_addr[2];            /* address of last memory use */
1566   HOST_WIDE_INT prev_off[2];    /* last offset */
1567   int n_iter;                   /* number of iterators in use */
1568   int next_iter;                /* next iterator to use */
1569   unsigned int save_gr_used_mask;
1570 };
1571
1572 static struct spill_fill_data spill_fill_data;
1573
1574 static void
1575 setup_spill_pointers (n_spills, init_reg, cfa_off)
1576      int n_spills;
1577      rtx init_reg;
1578      HOST_WIDE_INT cfa_off;
1579 {
1580   int i;
1581
1582   spill_fill_data.init_after = get_last_insn ();
1583   spill_fill_data.init_reg[0] = init_reg;
1584   spill_fill_data.init_reg[1] = init_reg;
1585   spill_fill_data.prev_addr[0] = NULL;
1586   spill_fill_data.prev_addr[1] = NULL;
1587   spill_fill_data.prev_off[0] = cfa_off;
1588   spill_fill_data.prev_off[1] = cfa_off;
1589   spill_fill_data.next_iter = 0;
1590   spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
1591
1592   spill_fill_data.n_iter = 1 + (n_spills > 2);
1593   for (i = 0; i < spill_fill_data.n_iter; ++i)
1594     {
1595       int regno = next_scratch_gr_reg ();
1596       spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
1597       current_frame_info.gr_used_mask |= 1 << regno;
1598     }
1599 }
1600
1601 static void
1602 finish_spill_pointers ()
1603 {
1604   current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
1605 }
1606
1607 static rtx
1608 spill_restore_mem (reg, cfa_off)
1609      rtx reg;
1610      HOST_WIDE_INT cfa_off;
1611 {
1612   int iter = spill_fill_data.next_iter;
1613   HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
1614   rtx disp_rtx = GEN_INT (disp);
1615   rtx mem;
1616
1617   if (spill_fill_data.prev_addr[iter])
1618     {
1619       if (CONST_OK_FOR_N (disp))
1620         *spill_fill_data.prev_addr[iter]
1621           = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
1622                                  gen_rtx_PLUS (DImode,
1623                                                spill_fill_data.iter_reg[iter],
1624                                                disp_rtx));
1625       else
1626         {
1627           /* ??? Could use register post_modify for loads.  */
1628           if (! CONST_OK_FOR_I (disp))
1629             {
1630               rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
1631               emit_move_insn (tmp, disp_rtx);
1632               disp_rtx = tmp;
1633             }
1634           emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
1635                                  spill_fill_data.iter_reg[iter], disp_rtx));
1636         }
1637     }
1638   /* Micro-optimization: if we've created a frame pointer, it's at
1639      CFA 0, which may allow the real iterator to be initialized lower,
1640      slightly increasing parallelism.  Also, if there are few saves
1641      it may eliminate the iterator entirely.  */
1642   else if (disp == 0
1643            && spill_fill_data.init_reg[iter] == stack_pointer_rtx
1644            && frame_pointer_needed)
1645     {
1646       mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
1647       MEM_ALIAS_SET (mem) = get_varargs_alias_set ();
1648       return mem;
1649     }
1650   else
1651     {
1652       rtx seq;
1653
1654       if (disp == 0)
1655         seq = gen_movdi (spill_fill_data.iter_reg[iter],
1656                          spill_fill_data.init_reg[iter]);
1657       else
1658         {
1659           start_sequence ();
1660
1661           if (! CONST_OK_FOR_I (disp))
1662             {
1663               rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
1664               emit_move_insn (tmp, disp_rtx);
1665               disp_rtx = tmp;
1666             }
1667
1668           emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
1669                                  spill_fill_data.init_reg[iter],
1670                                  disp_rtx));
1671
1672           seq = gen_sequence ();
1673           end_sequence ();
1674         }
1675
1676       /* Careful for being the first insn in a sequence.  */
1677       if (spill_fill_data.init_after)
1678         spill_fill_data.init_after
1679           = emit_insn_after (seq, spill_fill_data.init_after);
1680       else
1681         {
1682           rtx first = get_insns ();
1683           if (first)
1684             spill_fill_data.init_after
1685               = emit_insn_before (seq, first);
1686           else
1687             spill_fill_data.init_after = emit_insn (seq);
1688         }
1689     }
1690
1691   mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
1692
1693   /* ??? Not all of the spills are for varargs, but some of them are.
1694      The rest of the spills belong in an alias set of their own.  But
1695      it doesn't actually hurt to include them here.  */
1696   MEM_ALIAS_SET (mem) = get_varargs_alias_set ();
1697
1698   spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
1699   spill_fill_data.prev_off[iter] = cfa_off;
1700
1701   if (++iter >= spill_fill_data.n_iter)
1702     iter = 0;
1703   spill_fill_data.next_iter = iter;
1704
1705   return mem;
1706 }
1707
1708 static void
1709 do_spill (move_fn, reg, cfa_off, frame_reg)
1710      rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
1711      rtx reg, frame_reg;
1712      HOST_WIDE_INT cfa_off;
1713 {
1714   rtx mem, insn;
1715
1716   mem = spill_restore_mem (reg, cfa_off);
1717   insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
1718
1719   if (frame_reg)
1720     {
1721       rtx base;
1722       HOST_WIDE_INT off;
1723
1724       RTX_FRAME_RELATED_P (insn) = 1;
1725
1726       /* Don't even pretend that the unwind code can intuit its way
1727          through a pair of interleaved post_modify iterators.  Just
1728          provide the correct answer.  */
1729
1730       if (frame_pointer_needed)
1731         {
1732           base = hard_frame_pointer_rtx;
1733           off = - cfa_off;
1734         }
1735       else
1736         {
1737           base = stack_pointer_rtx;
1738           off = current_frame_info.total_size - cfa_off;
1739         }
1740
1741       REG_NOTES (insn)
1742         = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1743                 gen_rtx_SET (VOIDmode,
1744                              gen_rtx_MEM (GET_MODE (reg),
1745                                           plus_constant (base, off)),
1746                              frame_reg),
1747                 REG_NOTES (insn));
1748     }
1749 }
1750
1751 static void
1752 do_restore (move_fn, reg, cfa_off)
1753      rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
1754      rtx reg;
1755      HOST_WIDE_INT cfa_off;
1756 {
1757   emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
1758                          GEN_INT (cfa_off)));
1759 }
1760
1761 /* Wrapper functions that discards the CONST_INT spill offset.  These
1762    exist so that we can give gr_spill/gr_fill the offset they need and
1763    use a consistant function interface.  */
1764
1765 static rtx
1766 gen_movdi_x (dest, src, offset)
1767      rtx dest, src;
1768      rtx offset ATTRIBUTE_UNUSED;
1769 {
1770   return gen_movdi (dest, src);
1771 }
1772
1773 static rtx
1774 gen_fr_spill_x (dest, src, offset)
1775      rtx dest, src;
1776      rtx offset ATTRIBUTE_UNUSED;
1777 {
1778   return gen_fr_spill (dest, src);
1779 }
1780
1781 static rtx
1782 gen_fr_restore_x (dest, src, offset)
1783      rtx dest, src;
1784      rtx offset ATTRIBUTE_UNUSED;
1785 {
1786   return gen_fr_restore (dest, src);
1787 }
1788
1789 /* Called after register allocation to add any instructions needed for the
1790    prologue.  Using a prologue insn is favored compared to putting all of the
1791    instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1792    to intermix instructions with the saves of the caller saved registers.  In
1793    some cases, it might be necessary to emit a barrier instruction as the last
1794    insn to prevent such scheduling.
1795
1796    Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1797    so that the debug info generation code can handle them properly.
1798
1799    The register save area is layed out like so:
1800    cfa+16
1801         [ varargs spill area ]
1802         [ fr register spill area ]
1803         [ br register spill area ]
1804         [ ar register spill area ]
1805         [ pr register spill area ]
1806         [ gr register spill area ] */
1807
1808 /* ??? Get inefficient code when the frame size is larger than can fit in an
1809    adds instruction.  */
1810
1811 void
1812 ia64_expand_prologue ()
1813 {
1814   rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
1815   int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
1816   rtx reg, alt_reg;
1817
1818   ia64_compute_frame_size (get_frame_size ());
1819   last_scratch_gr_reg = 15;
1820
1821   /* If there is no epilogue, then we don't need some prologue insns.
1822      We need to avoid emitting the dead prologue insns, because flow
1823      will complain about them.  */
1824   if (optimize)
1825     {
1826       edge e;
1827
1828       for (e = EXIT_BLOCK_PTR->pred; e ; e = e->pred_next)
1829         if ((e->flags & EDGE_FAKE) == 0
1830             && (e->flags & EDGE_FALLTHRU) != 0)
1831           break;
1832       epilogue_p = (e != NULL);
1833     }
1834   else
1835     epilogue_p = 1;
1836
1837   /* Set the local, input, and output register names.  We need to do this
1838      for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
1839      half.  If we use in/loc/out register names, then we get assembler errors
1840      in crtn.S because there is no alloc insn or regstk directive in there.  */
1841   if (! TARGET_REG_NAMES)
1842     {
1843       int inputs = current_frame_info.n_input_regs;
1844       int locals = current_frame_info.n_local_regs;
1845       int outputs = current_frame_info.n_output_regs;
1846
1847       for (i = 0; i < inputs; i++)
1848         reg_names[IN_REG (i)] = ia64_reg_numbers[i];
1849       for (i = 0; i < locals; i++)
1850         reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
1851       for (i = 0; i < outputs; i++)
1852         reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
1853     }
1854
1855   /* Set the frame pointer register name.  The regnum is logically loc79,
1856      but of course we'll not have allocated that many locals.  Rather than
1857      worrying about renumbering the existing rtxs, we adjust the name.  */
1858   if (current_frame_info.reg_fp)
1859     {
1860       const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
1861       reg_names[HARD_FRAME_POINTER_REGNUM]
1862         = reg_names[current_frame_info.reg_fp];
1863       reg_names[current_frame_info.reg_fp] = tmp;
1864     }
1865
1866   /* Fix up the return address placeholder.  */
1867   /* ??? We can fail if __builtin_return_address is used, and we didn't
1868      allocate a register in which to save b0.  I can't think of a way to
1869      eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
1870      then be sure that I got the right one.  Further, reload doesn't seem
1871      to care if an eliminable register isn't used, and "eliminates" it
1872      anyway.  */
1873   if (regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM]
1874       && current_frame_info.reg_save_b0 != 0)
1875     XINT (return_address_pointer_rtx, 0) = current_frame_info.reg_save_b0;
1876
1877   /* We don't need an alloc instruction if we've used no outputs or locals.  */
1878   if (current_frame_info.n_local_regs == 0
1879       && current_frame_info.n_output_regs == 0
1880       && current_frame_info.n_input_regs <= current_function_args_info.words)
1881     {
1882       /* If there is no alloc, but there are input registers used, then we
1883          need a .regstk directive.  */
1884       current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
1885       ar_pfs_save_reg = NULL_RTX;
1886     }
1887   else
1888     {
1889       current_frame_info.need_regstk = 0;
1890
1891       if (current_frame_info.reg_save_ar_pfs)
1892         regno = current_frame_info.reg_save_ar_pfs;
1893       else
1894         regno = next_scratch_gr_reg ();
1895       ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
1896
1897       insn = emit_insn (gen_alloc (ar_pfs_save_reg,
1898                                    GEN_INT (current_frame_info.n_input_regs),
1899                                    GEN_INT (current_frame_info.n_local_regs),
1900                                    GEN_INT (current_frame_info.n_output_regs),
1901                                    GEN_INT (current_frame_info.n_rotate_regs)));
1902       RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
1903     }
1904
1905   /* Set up frame pointer, stack pointer, and spill iterators.  */
1906
1907   n_varargs = cfun->machine->n_varargs;
1908   setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
1909                         stack_pointer_rtx, 0);
1910
1911   if (frame_pointer_needed)
1912     {
1913       insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
1914       RTX_FRAME_RELATED_P (insn) = 1;
1915     }
1916
1917   if (current_frame_info.total_size != 0)
1918     {
1919       rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
1920       rtx offset;
1921
1922       if (CONST_OK_FOR_I (- current_frame_info.total_size))
1923         offset = frame_size_rtx;
1924       else
1925         {
1926           regno = next_scratch_gr_reg ();
1927           offset = gen_rtx_REG (DImode, regno);
1928           emit_move_insn (offset, frame_size_rtx);
1929         }
1930
1931       insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
1932                                     stack_pointer_rtx, offset));
1933
1934       if (! frame_pointer_needed)
1935         {
1936           RTX_FRAME_RELATED_P (insn) = 1;
1937           if (GET_CODE (offset) != CONST_INT)
1938             {
1939               REG_NOTES (insn)
1940                 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1941                         gen_rtx_SET (VOIDmode,
1942                                      stack_pointer_rtx,
1943                                      gen_rtx_PLUS (DImode,
1944                                                    stack_pointer_rtx,
1945                                                    frame_size_rtx)),
1946                         REG_NOTES (insn));
1947             }
1948         }
1949
1950       /* ??? At this point we must generate a magic insn that appears to
1951          modify the stack pointer, the frame pointer, and all spill
1952          iterators.  This would allow the most scheduling freedom.  For
1953          now, just hard stop.  */
1954       emit_insn (gen_blockage ());
1955     }
1956
1957   /* Must copy out ar.unat before doing any integer spills.  */
1958   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
1959     {
1960       if (current_frame_info.reg_save_ar_unat)
1961         ar_unat_save_reg
1962           = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
1963       else
1964         {
1965           alt_regno = next_scratch_gr_reg ();
1966           ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
1967           current_frame_info.gr_used_mask |= 1 << alt_regno;
1968         }
1969
1970       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
1971       insn = emit_move_insn (ar_unat_save_reg, reg);
1972       RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
1973
1974       /* Even if we're not going to generate an epilogue, we still
1975          need to save the register so that EH works.  */
1976       if (! epilogue_p && current_frame_info.reg_save_ar_unat)
1977         emit_insn (gen_rtx_USE (VOIDmode, ar_unat_save_reg));
1978     }
1979   else
1980     ar_unat_save_reg = NULL_RTX;
1981
1982   /* Spill all varargs registers.  Do this before spilling any GR registers,
1983      since we want the UNAT bits for the GR registers to override the UNAT
1984      bits from varargs, which we don't care about.  */
1985
1986   cfa_off = -16;
1987   for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
1988     {
1989       reg = gen_rtx_REG (DImode, regno);
1990       do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
1991     }
1992
1993   /* Locate the bottom of the register save area.  */
1994   cfa_off = (current_frame_info.spill_cfa_off
1995              + current_frame_info.spill_size
1996              + current_frame_info.extra_spill_size);
1997
1998   /* Save the predicate register block either in a register or in memory.  */
1999   if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2000     {
2001       reg = gen_rtx_REG (DImode, PR_REG (0));
2002       if (current_frame_info.reg_save_pr != 0)
2003         {
2004           alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2005           insn = emit_move_insn (alt_reg, reg);
2006
2007           /* ??? Denote pr spill/fill by a DImode move that modifies all
2008              64 hard registers.  */
2009           RTX_FRAME_RELATED_P (insn) = 1;
2010           REG_NOTES (insn)
2011             = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2012                         gen_rtx_SET (VOIDmode, alt_reg, reg),
2013                         REG_NOTES (insn));
2014
2015           /* Even if we're not going to generate an epilogue, we still
2016              need to save the register so that EH works.  */
2017           if (! epilogue_p)
2018             emit_insn (gen_rtx_USE (VOIDmode, alt_reg));
2019         }
2020       else
2021         {
2022           alt_regno = next_scratch_gr_reg ();
2023           alt_reg = gen_rtx_REG (DImode, alt_regno);
2024           insn = emit_move_insn (alt_reg, reg);
2025           do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2026           cfa_off -= 8;
2027         }
2028     }
2029
2030   /* Handle AR regs in numerical order.  All of them get special handling.  */
2031   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2032       && current_frame_info.reg_save_ar_unat == 0)
2033     {
2034       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2035       do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2036       cfa_off -= 8;
2037     }
2038
2039   /* The alloc insn already copied ar.pfs into a general register.  The
2040      only thing we have to do now is copy that register to a stack slot
2041      if we'd not allocated a local register for the job.  */
2042   if (current_frame_info.reg_save_ar_pfs == 0
2043       && ! current_function_is_leaf)
2044     {
2045       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2046       do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2047       cfa_off -= 8;
2048     }
2049
2050   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2051     {
2052       reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2053       if (current_frame_info.reg_save_ar_lc != 0)
2054         {
2055           alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2056           insn = emit_move_insn (alt_reg, reg);
2057           RTX_FRAME_RELATED_P (insn) = 1;
2058
2059           /* Even if we're not going to generate an epilogue, we still
2060              need to save the register so that EH works.  */
2061           if (! epilogue_p)
2062             emit_insn (gen_rtx_USE (VOIDmode, alt_reg));
2063         }
2064       else
2065         {
2066           alt_regno = next_scratch_gr_reg ();
2067           alt_reg = gen_rtx_REG (DImode, alt_regno);
2068           emit_move_insn (alt_reg, reg);
2069           do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2070           cfa_off -= 8;
2071         }
2072     }
2073
2074   /* We should now be at the base of the gr/br/fr spill area.  */
2075   if (cfa_off != (current_frame_info.spill_cfa_off
2076                   + current_frame_info.spill_size))
2077     abort ();
2078
2079   /* Spill all general registers.  */
2080   for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2081     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2082       {
2083         reg = gen_rtx_REG (DImode, regno);
2084         do_spill (gen_gr_spill, reg, cfa_off, reg);
2085         cfa_off -= 8;
2086       }
2087
2088   /* Handle BR0 specially -- it may be getting stored permanently in
2089      some GR register.  */
2090   if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2091     {
2092       reg = gen_rtx_REG (DImode, BR_REG (0));
2093       if (current_frame_info.reg_save_b0 != 0)
2094         {
2095           alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2096           insn = emit_move_insn (alt_reg, reg);
2097           RTX_FRAME_RELATED_P (insn) = 1;
2098
2099           /* Even if we're not going to generate an epilogue, we still
2100              need to save the register so that EH works.  */
2101           if (! epilogue_p)
2102             emit_insn (gen_rtx_USE (VOIDmode, alt_reg));
2103         }
2104       else
2105         {
2106           alt_regno = next_scratch_gr_reg ();
2107           alt_reg = gen_rtx_REG (DImode, alt_regno);
2108           emit_move_insn (alt_reg, reg);
2109           do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2110           cfa_off -= 8;
2111         }
2112     }
2113
2114   /* Spill the rest of the BR registers.  */
2115   for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2116     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2117       {
2118         alt_regno = next_scratch_gr_reg ();
2119         alt_reg = gen_rtx_REG (DImode, alt_regno);
2120         reg = gen_rtx_REG (DImode, regno);
2121         emit_move_insn (alt_reg, reg);
2122         do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2123         cfa_off -= 8;
2124       }
2125
2126   /* Align the frame and spill all FR registers.  */
2127   for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2128     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2129       {
2130         if (cfa_off & 15)
2131           abort ();
2132         reg = gen_rtx_REG (TFmode, regno);
2133         do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2134         cfa_off -= 16;
2135       }
2136
2137   if (cfa_off != current_frame_info.spill_cfa_off)
2138     abort ();
2139
2140   finish_spill_pointers ();
2141 }
2142
2143 /* Called after register allocation to add any instructions needed for the
2144    epilogue.  Using a epilogue insn is favored compared to putting all of the
2145    instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
2146    to intermix instructions with the saves of the caller saved registers.  In
2147    some cases, it might be necessary to emit a barrier instruction as the last
2148    insn to prevent such scheduling.  */
2149
2150 void
2151 ia64_expand_epilogue (sibcall_p)
2152      int sibcall_p;
2153 {
2154   rtx insn, reg, alt_reg, ar_unat_save_reg;
2155   int regno, alt_regno, cfa_off;
2156
2157   ia64_compute_frame_size (get_frame_size ());
2158
2159   /* If there is a frame pointer, then we use it instead of the stack
2160      pointer, so that the stack pointer does not need to be valid when
2161      the epilogue starts.  See EXIT_IGNORE_STACK.  */
2162   if (frame_pointer_needed)
2163     setup_spill_pointers (current_frame_info.n_spilled,
2164                           hard_frame_pointer_rtx, 0);
2165   else
2166     setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2167                           current_frame_info.total_size);
2168
2169   if (current_frame_info.total_size != 0)
2170     {
2171       /* ??? At this point we must generate a magic insn that appears to
2172          modify the spill iterators and the frame pointer.  This would
2173          allow the most scheduling freedom.  For now, just hard stop.  */
2174       emit_insn (gen_blockage ());
2175     }
2176
2177   /* Locate the bottom of the register save area.  */
2178   cfa_off = (current_frame_info.spill_cfa_off
2179              + current_frame_info.spill_size
2180              + current_frame_info.extra_spill_size);
2181
2182   /* Restore the predicate registers.  */
2183   if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2184     {
2185       if (current_frame_info.reg_save_pr != 0)
2186         alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2187       else
2188         {
2189           alt_regno = next_scratch_gr_reg ();
2190           alt_reg = gen_rtx_REG (DImode, alt_regno);
2191           do_restore (gen_movdi_x, alt_reg, cfa_off);
2192           cfa_off -= 8;
2193         }
2194       reg = gen_rtx_REG (DImode, PR_REG (0));
2195       emit_move_insn (reg, alt_reg);
2196     }
2197
2198   /* Restore the application registers.  */
2199
2200   /* Load the saved unat from the stack, but do not restore it until
2201      after the GRs have been restored.  */
2202   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2203     {
2204       if (current_frame_info.reg_save_ar_unat != 0)
2205         ar_unat_save_reg
2206           = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2207       else
2208         {
2209           alt_regno = next_scratch_gr_reg ();
2210           ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2211           current_frame_info.gr_used_mask |= 1 << alt_regno;
2212           do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
2213           cfa_off -= 8;
2214         }
2215     }
2216   else
2217     ar_unat_save_reg = NULL_RTX;
2218
2219   if (current_frame_info.reg_save_ar_pfs != 0)
2220     {
2221       alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
2222       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2223       emit_move_insn (reg, alt_reg);
2224     }
2225   else if (! current_function_is_leaf)
2226     {
2227       alt_regno = next_scratch_gr_reg ();
2228       alt_reg = gen_rtx_REG (DImode, alt_regno);
2229       do_restore (gen_movdi_x, alt_reg, cfa_off);
2230       cfa_off -= 8;
2231       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2232       emit_move_insn (reg, alt_reg);
2233     }
2234
2235   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2236     {
2237       if (current_frame_info.reg_save_ar_lc != 0)
2238         alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2239       else
2240         {
2241           alt_regno = next_scratch_gr_reg ();
2242           alt_reg = gen_rtx_REG (DImode, alt_regno);
2243           do_restore (gen_movdi_x, alt_reg, cfa_off);
2244           cfa_off -= 8;
2245         }
2246       reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2247       emit_move_insn (reg, alt_reg);
2248     }
2249
2250   /* We should now be at the base of the gr/br/fr spill area.  */
2251   if (cfa_off != (current_frame_info.spill_cfa_off
2252                   + current_frame_info.spill_size))
2253     abort ();
2254
2255   /* Restore all general registers.  */
2256   for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2257     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2258       {
2259         reg = gen_rtx_REG (DImode, regno);
2260         do_restore (gen_gr_restore, reg, cfa_off);
2261         cfa_off -= 8;
2262       }
2263
2264   /* Restore the branch registers.  Handle B0 specially, as it may
2265      have gotten stored in some GR register.  */
2266   if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2267     {
2268       if (current_frame_info.reg_save_b0 != 0)
2269         alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2270       else
2271         {
2272           alt_regno = next_scratch_gr_reg ();
2273           alt_reg = gen_rtx_REG (DImode, alt_regno);
2274           do_restore (gen_movdi_x, alt_reg, cfa_off);
2275           cfa_off -= 8;
2276         }
2277       reg = gen_rtx_REG (DImode, BR_REG (0));
2278       emit_move_insn (reg, alt_reg);
2279     }
2280
2281   for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2282     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2283       {
2284         alt_regno = next_scratch_gr_reg ();
2285         alt_reg = gen_rtx_REG (DImode, alt_regno);
2286         do_restore (gen_movdi_x, alt_reg, cfa_off);
2287         cfa_off -= 8;
2288         reg = gen_rtx_REG (DImode, regno);
2289         emit_move_insn (reg, alt_reg);
2290       }
2291
2292   /* Restore floating point registers.  */
2293   for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2294     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2295       {
2296         if (cfa_off & 15)
2297           abort ();
2298         reg = gen_rtx_REG (TFmode, regno);
2299         do_restore (gen_fr_restore_x, reg, cfa_off);
2300         cfa_off -= 16;
2301       }
2302
2303   /* Restore ar.unat for real.  */
2304   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2305     {
2306       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2307       emit_move_insn (reg, ar_unat_save_reg);
2308     }
2309
2310   if (cfa_off != current_frame_info.spill_cfa_off)
2311     abort ();
2312
2313   finish_spill_pointers ();
2314
2315   if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
2316     {
2317       /* ??? At this point we must generate a magic insn that appears to
2318          modify the spill iterators, the stack pointer, and the frame
2319          pointer.  This would allow the most scheduling freedom.  For now,
2320          just hard stop.  */
2321       emit_insn (gen_blockage ());
2322     }
2323
2324   if (cfun->machine->ia64_eh_epilogue_sp)
2325     emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
2326   else if (frame_pointer_needed)
2327     {
2328       insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
2329       RTX_FRAME_RELATED_P (insn) = 1;
2330     }
2331   else if (current_frame_info.total_size)
2332     {
2333       rtx offset, frame_size_rtx;
2334
2335       frame_size_rtx = GEN_INT (current_frame_info.total_size);
2336       if (CONST_OK_FOR_I (current_frame_info.total_size))
2337         offset = frame_size_rtx;
2338       else
2339         {
2340           regno = next_scratch_gr_reg ();
2341           offset = gen_rtx_REG (DImode, regno);
2342           emit_move_insn (offset, frame_size_rtx);
2343         }
2344
2345       insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
2346                                     offset));
2347
2348       RTX_FRAME_RELATED_P (insn) = 1;
2349       if (GET_CODE (offset) != CONST_INT)
2350         {
2351           REG_NOTES (insn)
2352             = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2353                         gen_rtx_SET (VOIDmode,
2354                                      stack_pointer_rtx,
2355                                      gen_rtx_PLUS (DImode,
2356                                                    stack_pointer_rtx,
2357                                                    frame_size_rtx)),
2358                         REG_NOTES (insn));
2359         }
2360     }
2361
2362   if (cfun->machine->ia64_eh_epilogue_bsp)
2363     emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
2364
2365   if (! sibcall_p)
2366     emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
2367 }
2368
2369 /* Return 1 if br.ret can do all the work required to return from a
2370    function.  */
2371
2372 int
2373 ia64_direct_return ()
2374 {
2375   if (reload_completed && ! frame_pointer_needed)
2376     {
2377       ia64_compute_frame_size (get_frame_size ());
2378
2379       return (current_frame_info.total_size == 0
2380               && current_frame_info.n_spilled == 0
2381               && current_frame_info.reg_save_b0 == 0
2382               && current_frame_info.reg_save_pr == 0
2383               && current_frame_info.reg_save_ar_pfs == 0
2384               && current_frame_info.reg_save_ar_unat == 0
2385               && current_frame_info.reg_save_ar_lc == 0);
2386     }
2387   return 0;
2388 }
2389
2390 int
2391 ia64_hard_regno_rename_ok (from, to)
2392      int from;
2393      int to;
2394 {
2395   /* Don't clobber any of the registers we reserved for the prologue.  */
2396   if (to == current_frame_info.reg_fp
2397       || to == current_frame_info.reg_save_b0
2398       || to == current_frame_info.reg_save_pr
2399       || to == current_frame_info.reg_save_ar_pfs
2400       || to == current_frame_info.reg_save_ar_unat
2401       || to == current_frame_info.reg_save_ar_lc)
2402     return 0;
2403
2404   /* Don't use output registers outside the register frame.  */
2405   if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
2406     return 0;
2407
2408   /* Retain even/oddness on predicate register pairs.  */
2409   if (PR_REGNO_P (from) && PR_REGNO_P (to))
2410     return (from & 1) == (to & 1);
2411
2412   return 1;
2413 }
2414
2415 /* Emit the function prologue.  */
2416
2417 void
2418 ia64_function_prologue (file, size)
2419      FILE *file;
2420      int size ATTRIBUTE_UNUSED;
2421 {
2422   int mask, grsave, grsave_prev;
2423
2424   if (current_frame_info.need_regstk)
2425     fprintf (file, "\t.regstk %d, %d, %d, %d\n",
2426              current_frame_info.n_input_regs,
2427              current_frame_info.n_local_regs,
2428              current_frame_info.n_output_regs,
2429              current_frame_info.n_rotate_regs);
2430
2431   if (!flag_unwind_tables && (!flag_exceptions || exceptions_via_longjmp))
2432     return;
2433
2434   /* Emit the .prologue directive.  */
2435
2436   mask = 0;
2437   grsave = grsave_prev = 0;
2438   if (current_frame_info.reg_save_b0 != 0)
2439     {
2440       mask |= 8;
2441       grsave = grsave_prev = current_frame_info.reg_save_b0;
2442     }
2443   if (current_frame_info.reg_save_ar_pfs != 0
2444       && (grsave_prev == 0
2445           || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
2446     {
2447       mask |= 4;
2448       if (grsave_prev == 0)
2449         grsave = current_frame_info.reg_save_ar_pfs;
2450       grsave_prev = current_frame_info.reg_save_ar_pfs;
2451     }
2452   if (current_frame_info.reg_fp != 0
2453       && (grsave_prev == 0
2454           || current_frame_info.reg_fp == grsave_prev + 1))
2455     {
2456       mask |= 2;
2457       if (grsave_prev == 0)
2458         grsave = HARD_FRAME_POINTER_REGNUM;
2459       grsave_prev = current_frame_info.reg_fp;
2460     }
2461   if (current_frame_info.reg_save_pr != 0
2462       && (grsave_prev == 0
2463           || current_frame_info.reg_save_pr == grsave_prev + 1))
2464     {
2465       mask |= 1;
2466       if (grsave_prev == 0)
2467         grsave = current_frame_info.reg_save_pr;
2468     }
2469
2470   if (mask)
2471     fprintf (file, "\t.prologue %d, %d\n", mask,
2472              ia64_dbx_register_number (grsave));
2473   else
2474     fputs ("\t.prologue\n", file);
2475
2476   /* Emit a .spill directive, if necessary, to relocate the base of
2477      the register spill area.  */
2478   if (current_frame_info.spill_cfa_off != -16)
2479     fprintf (file, "\t.spill %ld\n",
2480              (long) (current_frame_info.spill_cfa_off
2481                      + current_frame_info.spill_size));
2482 }
2483
2484 /* Emit the .body directive at the scheduled end of the prologue.  */
2485
2486 void
2487 ia64_output_end_prologue (file)
2488      FILE *file;
2489 {
2490   if (!flag_unwind_tables && (!flag_exceptions || exceptions_via_longjmp))
2491     return;
2492
2493   fputs ("\t.body\n", file);
2494 }
2495
2496 /* Emit the function epilogue.  */
2497
2498 void
2499 ia64_function_epilogue (file, size)
2500      FILE *file ATTRIBUTE_UNUSED;
2501      int size ATTRIBUTE_UNUSED;
2502 {
2503   int i;
2504
2505   /* Reset from the function's potential modifications.  */
2506   XINT (return_address_pointer_rtx, 0) = RETURN_ADDRESS_POINTER_REGNUM;
2507
2508   if (current_frame_info.reg_fp)
2509     {
2510       const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2511       reg_names[HARD_FRAME_POINTER_REGNUM]
2512         = reg_names[current_frame_info.reg_fp];
2513       reg_names[current_frame_info.reg_fp] = tmp;
2514     }
2515   if (! TARGET_REG_NAMES)
2516     {
2517       for (i = 0; i < current_frame_info.n_input_regs; i++)
2518         reg_names[IN_REG (i)] = ia64_input_reg_names[i];
2519       for (i = 0; i < current_frame_info.n_local_regs; i++)
2520         reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
2521       for (i = 0; i < current_frame_info.n_output_regs; i++)
2522         reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
2523     }
2524
2525   current_frame_info.initialized = 0;
2526 }
2527
2528 int
2529 ia64_dbx_register_number (regno)
2530      int regno;
2531 {
2532   /* In ia64_expand_prologue we quite literally renamed the frame pointer
2533      from its home at loc79 to something inside the register frame.  We
2534      must perform the same renumbering here for the debug info.  */
2535   if (current_frame_info.reg_fp)
2536     {
2537       if (regno == HARD_FRAME_POINTER_REGNUM)
2538         regno = current_frame_info.reg_fp;
2539       else if (regno == current_frame_info.reg_fp)
2540         regno = HARD_FRAME_POINTER_REGNUM;
2541     }
2542
2543   if (IN_REGNO_P (regno))
2544     return 32 + regno - IN_REG (0);
2545   else if (LOC_REGNO_P (regno))
2546     return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
2547   else if (OUT_REGNO_P (regno))
2548     return (32 + current_frame_info.n_input_regs
2549             + current_frame_info.n_local_regs + regno - OUT_REG (0));
2550   else
2551     return regno;
2552 }
2553
2554 void
2555 ia64_initialize_trampoline (addr, fnaddr, static_chain)
2556      rtx addr, fnaddr, static_chain;
2557 {
2558   rtx addr_reg, eight = GEN_INT (8);
2559
2560   /* Load up our iterator.  */
2561   addr_reg = gen_reg_rtx (Pmode);
2562   emit_move_insn (addr_reg, addr);
2563
2564   /* The first two words are the fake descriptor:
2565      __ia64_trampoline, ADDR+16.  */
2566   emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
2567                   gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
2568   emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
2569
2570   emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
2571                   copy_to_reg (plus_constant (addr, 16)));
2572   emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
2573
2574   /* The third word is the target descriptor.  */
2575   emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
2576   emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
2577
2578   /* The fourth word is the static chain.  */
2579   emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
2580 }
2581 \f
2582 /* Do any needed setup for a variadic function.  CUM has not been updated
2583    for the last named argument which has type TYPE and mode MODE.
2584
2585    We generate the actual spill instructions during prologue generation.  */
2586
2587 void
2588 ia64_setup_incoming_varargs (cum, int_mode, type, pretend_size, second_time)
2589      CUMULATIVE_ARGS cum;
2590      int             int_mode;
2591      tree            type;
2592      int *           pretend_size;
2593      int             second_time ATTRIBUTE_UNUSED;
2594 {
2595   /* If this is a stdarg function, then skip the current argument.  */
2596   if (! current_function_varargs)
2597     ia64_function_arg_advance (&cum, int_mode, type, 1);
2598
2599   if (cum.words < MAX_ARGUMENT_SLOTS)
2600     {
2601       int n = MAX_ARGUMENT_SLOTS - cum.words;
2602       *pretend_size = n * UNITS_PER_WORD;
2603       cfun->machine->n_varargs = n;
2604     }
2605 }
2606
2607 /* Check whether TYPE is a homogeneous floating point aggregate.  If
2608    it is, return the mode of the floating point type that appears
2609    in all leafs.  If it is not, return VOIDmode.
2610
2611    An aggregate is a homogeneous floating point aggregate is if all
2612    fields/elements in it have the same floating point type (e.g,
2613    SFmode).  128-bit quad-precision floats are excluded.  */
2614
2615 static enum machine_mode
2616 hfa_element_mode (type, nested)
2617      tree type;
2618      int nested;
2619 {
2620   enum machine_mode element_mode = VOIDmode;
2621   enum machine_mode mode;
2622   enum tree_code code = TREE_CODE (type);
2623   int know_element_mode = 0;
2624   tree t;
2625
2626   switch (code)
2627     {
2628     case VOID_TYPE:     case INTEGER_TYPE:      case ENUMERAL_TYPE:
2629     case BOOLEAN_TYPE:  case CHAR_TYPE:         case POINTER_TYPE:
2630     case OFFSET_TYPE:   case REFERENCE_TYPE:    case METHOD_TYPE:
2631     case FILE_TYPE:     case SET_TYPE:          case LANG_TYPE:
2632     case FUNCTION_TYPE:
2633       return VOIDmode;
2634
2635       /* Fortran complex types are supposed to be HFAs, so we need to handle
2636          gcc's COMPLEX_TYPEs as HFAs.  We need to exclude the integral complex
2637          types though.  */
2638     case COMPLEX_TYPE:
2639       if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT)
2640         return mode_for_size (GET_MODE_UNIT_SIZE (TYPE_MODE (type))
2641                               * BITS_PER_UNIT, MODE_FLOAT, 0);
2642       else
2643         return VOIDmode;
2644
2645     case REAL_TYPE:
2646       /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
2647          mode if this is contained within an aggregate.  */
2648       if (nested)
2649         return TYPE_MODE (type);
2650       else
2651         return VOIDmode;
2652
2653     case ARRAY_TYPE:
2654       return TYPE_MODE (TREE_TYPE (type));
2655
2656     case RECORD_TYPE:
2657     case UNION_TYPE:
2658     case QUAL_UNION_TYPE:
2659       for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
2660         {
2661           if (TREE_CODE (t) != FIELD_DECL)
2662             continue;
2663
2664           mode = hfa_element_mode (TREE_TYPE (t), 1);
2665           if (know_element_mode)
2666             {
2667               if (mode != element_mode)
2668                 return VOIDmode;
2669             }
2670           else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2671             return VOIDmode;
2672           else
2673             {
2674               know_element_mode = 1;
2675               element_mode = mode;
2676             }
2677         }
2678       return element_mode;
2679
2680     default:
2681       /* If we reach here, we probably have some front-end specific type
2682          that the backend doesn't know about.  This can happen via the
2683          aggregate_value_p call in init_function_start.  All we can do is
2684          ignore unknown tree types.  */
2685       return VOIDmode;
2686     }
2687
2688   return VOIDmode;
2689 }
2690
2691 /* Return rtx for register where argument is passed, or zero if it is passed
2692    on the stack.  */
2693
2694 /* ??? 128-bit quad-precision floats are always passed in general
2695    registers.  */
2696
2697 rtx
2698 ia64_function_arg (cum, mode, type, named, incoming)
2699      CUMULATIVE_ARGS *cum;
2700      enum machine_mode mode;
2701      tree type;
2702      int named;
2703      int incoming;
2704 {
2705   int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
2706   int words = (((mode == BLKmode ? int_size_in_bytes (type)
2707                  : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
2708                / UNITS_PER_WORD);
2709   int offset = 0;
2710   enum machine_mode hfa_mode = VOIDmode;
2711
2712   /* Integer and float arguments larger than 8 bytes start at the next even
2713      boundary.  Aggregates larger than 8 bytes start at the next even boundary
2714      if the aggregate has 16 byte alignment.  Net effect is that types with
2715      alignment greater than 8 start at the next even boundary.  */
2716   /* ??? The ABI does not specify how to handle aggregates with alignment from
2717      9 to 15 bytes, or greater than 16.   We handle them all as if they had
2718      16 byte alignment.  Such aggregates can occur only if gcc extensions are
2719      used.  */
2720   if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
2721        : (words > 1))
2722       && (cum->words & 1))
2723     offset = 1;
2724
2725   /* If all argument slots are used, then it must go on the stack.  */
2726   if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
2727     return 0;
2728
2729   /* Check for and handle homogeneous FP aggregates.  */
2730   if (type)
2731     hfa_mode = hfa_element_mode (type, 0);
2732
2733   /* Unnamed prototyped hfas are passed as usual.  Named prototyped hfas
2734      and unprototyped hfas are passed specially.  */
2735   if (hfa_mode != VOIDmode && (! cum->prototype || named))
2736     {
2737       rtx loc[16];
2738       int i = 0;
2739       int fp_regs = cum->fp_regs;
2740       int int_regs = cum->words + offset;
2741       int hfa_size = GET_MODE_SIZE (hfa_mode);
2742       int byte_size;
2743       int args_byte_size;
2744
2745       /* If prototyped, pass it in FR regs then GR regs.
2746          If not prototyped, pass it in both FR and GR regs.
2747
2748          If this is an SFmode aggregate, then it is possible to run out of
2749          FR regs while GR regs are still left.  In that case, we pass the
2750          remaining part in the GR regs.  */
2751
2752       /* Fill the FP regs.  We do this always.  We stop if we reach the end
2753          of the argument, the last FP register, or the last argument slot.  */
2754
2755       byte_size = ((mode == BLKmode)
2756                    ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
2757       args_byte_size = int_regs * UNITS_PER_WORD;
2758       offset = 0;
2759       for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
2760               && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
2761         {
2762           loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
2763                                       gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
2764                                                               + fp_regs)),
2765                                       GEN_INT (offset));
2766           offset += hfa_size;
2767           args_byte_size += hfa_size;
2768           fp_regs++;
2769         }
2770
2771       /* If no prototype, then the whole thing must go in GR regs.  */
2772       if (! cum->prototype)
2773         offset = 0;
2774       /* If this is an SFmode aggregate, then we might have some left over
2775          that needs to go in GR regs.  */
2776       else if (byte_size != offset)
2777         int_regs += offset / UNITS_PER_WORD;
2778
2779       /* Fill in the GR regs.  We must use DImode here, not the hfa mode.  */
2780
2781       for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
2782         {
2783           enum machine_mode gr_mode = DImode;
2784
2785           /* If we have an odd 4 byte hunk because we ran out of FR regs,
2786              then this goes in a GR reg left adjusted/little endian, right
2787              adjusted/big endian.  */
2788           /* ??? Currently this is handled wrong, because 4-byte hunks are
2789              always right adjusted/little endian.  */
2790           if (offset & 0x4)
2791             gr_mode = SImode;
2792           /* If we have an even 4 byte hunk because the aggregate is a
2793              multiple of 4 bytes in size, then this goes in a GR reg right
2794              adjusted/little endian.  */
2795           else if (byte_size - offset == 4)
2796             gr_mode = SImode;
2797
2798           loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
2799                                       gen_rtx_REG (gr_mode, (basereg
2800                                                              + int_regs)),
2801                                       GEN_INT (offset));
2802           offset += GET_MODE_SIZE (gr_mode);
2803           int_regs++;
2804         }
2805
2806       /* If we ended up using just one location, just return that one loc.  */
2807       if (i == 1)
2808         return XEXP (loc[0], 0);
2809       else
2810         return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
2811     }
2812
2813   /* Integral and aggregates go in general registers.  If we have run out of
2814      FR registers, then FP values must also go in general registers.  This can
2815      happen when we have a SFmode HFA.  */
2816   else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
2817     return gen_rtx_REG (mode, basereg + cum->words + offset);
2818
2819   /* If there is a prototype, then FP values go in a FR register when
2820      named, and in a GR registeer when unnamed.  */
2821   else if (cum->prototype)
2822     {
2823       if (! named)
2824         return gen_rtx_REG (mode, basereg + cum->words + offset);
2825       else
2826         return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
2827     }
2828   /* If there is no prototype, then FP values go in both FR and GR
2829      registers.  */
2830   else
2831     {
2832       rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
2833                                       gen_rtx_REG (mode, (FR_ARG_FIRST
2834                                                           + cum->fp_regs)),
2835                                       const0_rtx);
2836       rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
2837                                       gen_rtx_REG (mode,
2838                                                    (basereg + cum->words
2839                                                     + offset)),
2840                                       const0_rtx);
2841
2842       return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
2843     }
2844 }
2845
2846 /* Return number of words, at the beginning of the argument, that must be
2847    put in registers.  0 is the argument is entirely in registers or entirely
2848    in memory.  */
2849
2850 int
2851 ia64_function_arg_partial_nregs (cum, mode, type, named)
2852      CUMULATIVE_ARGS *cum;
2853      enum machine_mode mode;
2854      tree type;
2855      int named ATTRIBUTE_UNUSED;
2856 {
2857   int words = (((mode == BLKmode ? int_size_in_bytes (type)
2858                  : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
2859                / UNITS_PER_WORD);
2860   int offset = 0;
2861
2862   /* Arguments with alignment larger than 8 bytes start at the next even
2863      boundary.  */
2864   if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
2865        : (words > 1))
2866       && (cum->words & 1))
2867     offset = 1;
2868
2869   /* If all argument slots are used, then it must go on the stack.  */
2870   if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
2871     return 0;
2872
2873   /* It doesn't matter whether the argument goes in FR or GR regs.  If
2874      it fits within the 8 argument slots, then it goes entirely in
2875      registers.  If it extends past the last argument slot, then the rest
2876      goes on the stack.  */
2877
2878   if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
2879     return 0;
2880
2881   return MAX_ARGUMENT_SLOTS - cum->words - offset;
2882 }
2883
2884 /* Update CUM to point after this argument.  This is patterned after
2885    ia64_function_arg.  */
2886
2887 void
2888 ia64_function_arg_advance (cum, mode, type, named)
2889      CUMULATIVE_ARGS *cum;
2890      enum machine_mode mode;
2891      tree type;
2892      int named;
2893 {
2894   int words = (((mode == BLKmode ? int_size_in_bytes (type)
2895                  : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
2896                / UNITS_PER_WORD);
2897   int offset = 0;
2898   enum machine_mode hfa_mode = VOIDmode;
2899
2900   /* If all arg slots are already full, then there is nothing to do.  */
2901   if (cum->words >= MAX_ARGUMENT_SLOTS)
2902     return;
2903
2904   /* Arguments with alignment larger than 8 bytes start at the next even
2905      boundary.  */
2906   if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
2907        : (words > 1))
2908       && (cum->words & 1))
2909     offset = 1;
2910
2911   cum->words += words + offset;
2912
2913   /* Check for and handle homogeneous FP aggregates.  */
2914   if (type)
2915     hfa_mode = hfa_element_mode (type, 0);
2916
2917   /* Unnamed prototyped hfas are passed as usual.  Named prototyped hfas
2918      and unprototyped hfas are passed specially.  */
2919   if (hfa_mode != VOIDmode && (! cum->prototype || named))
2920     {
2921       int fp_regs = cum->fp_regs;
2922       /* This is the original value of cum->words + offset.  */
2923       int int_regs = cum->words - words;
2924       int hfa_size = GET_MODE_SIZE (hfa_mode);
2925       int byte_size;
2926       int args_byte_size;
2927
2928       /* If prototyped, pass it in FR regs then GR regs.
2929          If not prototyped, pass it in both FR and GR regs.
2930
2931          If this is an SFmode aggregate, then it is possible to run out of
2932          FR regs while GR regs are still left.  In that case, we pass the
2933          remaining part in the GR regs.  */
2934
2935       /* Fill the FP regs.  We do this always.  We stop if we reach the end
2936          of the argument, the last FP register, or the last argument slot.  */
2937
2938       byte_size = ((mode == BLKmode)
2939                    ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
2940       args_byte_size = int_regs * UNITS_PER_WORD;
2941       offset = 0;
2942       for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
2943               && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
2944         {
2945           offset += hfa_size;
2946           args_byte_size += hfa_size;
2947           fp_regs++;
2948         }
2949
2950       cum->fp_regs = fp_regs;
2951     }
2952
2953   /* Integral and aggregates go in general registers.  If we have run out of
2954      FR registers, then FP values must also go in general registers.  This can
2955      happen when we have a SFmode HFA.  */
2956   else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
2957     return;
2958
2959   /* If there is a prototype, then FP values go in a FR register when
2960      named, and in a GR registeer when unnamed.  */
2961   else if (cum->prototype)
2962     {
2963       if (! named)
2964         return;
2965       else
2966         /* ??? Complex types should not reach here.  */
2967         cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
2968     }
2969   /* If there is no prototype, then FP values go in both FR and GR
2970      registers.  */
2971   else
2972     /* ??? Complex types should not reach here.  */
2973     cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
2974
2975   return;
2976 }
2977 \f
2978 /* Implement va_start.  */
2979
2980 void
2981 ia64_va_start (stdarg_p, valist, nextarg)
2982      int stdarg_p;
2983      tree valist;
2984      rtx nextarg;
2985 {
2986   int arg_words;
2987   int ofs;
2988
2989   arg_words = current_function_args_info.words;
2990
2991   if (stdarg_p)
2992     ofs = 0;
2993   else
2994     ofs = (arg_words >= MAX_ARGUMENT_SLOTS ? -UNITS_PER_WORD : 0);
2995
2996   nextarg = plus_constant (nextarg, ofs);
2997   std_expand_builtin_va_start (1, valist, nextarg);
2998 }
2999
3000 /* Implement va_arg.  */
3001
3002 rtx
3003 ia64_va_arg (valist, type)
3004      tree valist, type;
3005 {
3006   tree t;
3007
3008   /* Arguments with alignment larger than 8 bytes start at the next even
3009      boundary.  */
3010   if (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3011     {
3012       t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
3013                  build_int_2 (2 * UNITS_PER_WORD - 1, 0));
3014       t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
3015                  build_int_2 (-2 * UNITS_PER_WORD, -1));
3016       t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
3017       TREE_SIDE_EFFECTS (t) = 1;
3018       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3019     }
3020
3021   return std_expand_builtin_va_arg (valist, type);
3022 }
3023 \f
3024 /* Return 1 if function return value returned in memory.  Return 0 if it is
3025    in a register.  */
3026
3027 int
3028 ia64_return_in_memory (valtype)
3029      tree valtype;
3030 {
3031   enum machine_mode mode;
3032   enum machine_mode hfa_mode;
3033   int byte_size;
3034
3035   mode = TYPE_MODE (valtype);
3036   byte_size = ((mode == BLKmode)
3037                ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
3038
3039   /* Hfa's with up to 8 elements are returned in the FP argument registers.  */
3040
3041   hfa_mode = hfa_element_mode (valtype, 0);
3042   if (hfa_mode != VOIDmode)
3043     {
3044       int hfa_size = GET_MODE_SIZE (hfa_mode);
3045
3046       if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
3047         return 1;
3048       else
3049         return 0;
3050     }
3051
3052   else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
3053     return 1;
3054   else
3055     return 0;
3056 }
3057
3058 /* Return rtx for register that holds the function return value.  */
3059
3060 rtx
3061 ia64_function_value (valtype, func)
3062      tree valtype;
3063      tree func ATTRIBUTE_UNUSED;
3064 {
3065   enum machine_mode mode;
3066   enum machine_mode hfa_mode;
3067
3068   mode = TYPE_MODE (valtype);
3069   hfa_mode = hfa_element_mode (valtype, 0);
3070
3071   if (hfa_mode != VOIDmode)
3072     {
3073       rtx loc[8];
3074       int i;
3075       int hfa_size;
3076       int byte_size;
3077       int offset;
3078
3079       hfa_size = GET_MODE_SIZE (hfa_mode);
3080       byte_size = ((mode == BLKmode)
3081                    ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
3082       offset = 0;
3083       for (i = 0; offset < byte_size; i++)
3084         {
3085           loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3086                                       gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
3087                                       GEN_INT (offset));
3088           offset += hfa_size;
3089         }
3090
3091       if (i == 1)
3092         return XEXP (loc[0], 0);
3093       else
3094         return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3095     }
3096   else if (FLOAT_TYPE_P (valtype))
3097     return gen_rtx_REG (mode, FR_ARG_FIRST);
3098   else
3099     return gen_rtx_REG (mode, GR_RET_FIRST);
3100 }
3101
3102 /* Print a memory address as an operand to reference that memory location.  */
3103
3104 /* ??? Do we need this?  It gets used only for 'a' operands.  We could perhaps
3105    also call this from ia64_print_operand for memory addresses.  */
3106
3107 void
3108 ia64_print_operand_address (stream, address)
3109      FILE * stream ATTRIBUTE_UNUSED;
3110      rtx    address ATTRIBUTE_UNUSED;
3111 {
3112 }
3113
3114 /* Print an operand to a assembler instruction.
3115    B    Work arounds for hardware bugs.
3116    C    Swap and print a comparison operator.
3117    D    Print an FP comparison operator.
3118    E    Print 32 - constant, for SImode shifts as extract.
3119    e    Print 64 - constant, for DImode rotates.
3120    F    A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3121         a floating point register emitted normally.
3122    I    Invert a predicate register by adding 1.
3123    J    Select the proper predicate register for a condition.
3124    j    Select the inverse predicate register for a condition.
3125    O    Append .acq for volatile load.
3126    P    Postincrement of a MEM.
3127    Q    Append .rel for volatile store.
3128    S    Shift amount for shladd instruction.
3129    T    Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3130         for Intel assembler.
3131    U    Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3132         for Intel assembler.
3133    r    Print register name, or constant 0 as r0.  HP compatibility for
3134         Linux kernel.  */
3135 void
3136 ia64_print_operand (file, x, code)
3137      FILE * file;
3138      rtx    x;
3139      int    code;
3140 {
3141   const char *str;
3142
3143   switch (code)
3144     {
3145     case 0:
3146       /* Handled below.  */
3147       break;
3148
3149     case 'B':
3150       if (TARGET_A_STEP)
3151         fputs (" ;; nop 0 ;; nop 0 ;;", file);
3152       return;
3153
3154     case 'C':
3155       {
3156         enum rtx_code c = swap_condition (GET_CODE (x));
3157         fputs (GET_RTX_NAME (c), file);
3158         return;
3159       }
3160
3161     case 'D':
3162       switch (GET_CODE (x))
3163         {
3164         case NE:
3165           str = "neq";
3166           break;
3167         case UNORDERED:
3168           str = "unord";
3169           break;
3170         case ORDERED:
3171           str = "ord";
3172           break;
3173         default:
3174           str = GET_RTX_NAME (GET_CODE (x));
3175           break;
3176         }
3177       fputs (str, file);
3178       return;
3179
3180     case 'E':
3181       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
3182       return;
3183
3184     case 'e':
3185       fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
3186       return;
3187
3188     case 'F':
3189       if (x == CONST0_RTX (GET_MODE (x)))
3190         str = reg_names [FR_REG (0)];
3191       else if (x == CONST1_RTX (GET_MODE (x)))
3192         str = reg_names [FR_REG (1)];
3193       else if (GET_CODE (x) == REG)
3194         str = reg_names [REGNO (x)];
3195       else
3196         abort ();
3197       fputs (str, file);
3198       return;
3199
3200     case 'I':
3201       fputs (reg_names [REGNO (x) + 1], file);
3202       return;
3203
3204     case 'J':
3205     case 'j':
3206       {
3207         unsigned int regno = REGNO (XEXP (x, 0));
3208         if (GET_CODE (x) == EQ)
3209           regno += 1;
3210         if (code == 'j')
3211           regno ^= 1;
3212         fputs (reg_names [regno], file);
3213       }
3214       return;
3215
3216     case 'O':
3217       if (MEM_VOLATILE_P (x))
3218         fputs(".acq", file);
3219       return;
3220
3221     case 'P':
3222       {
3223         HOST_WIDE_INT value;
3224
3225         switch (GET_CODE (XEXP (x, 0)))
3226           {
3227           default:
3228             return;
3229
3230           case POST_MODIFY:
3231             x = XEXP (XEXP (XEXP (x, 0), 1), 1);
3232             if (GET_CODE (x) == CONST_INT)
3233               value = INTVAL (x);
3234             else if (GET_CODE (x) == REG)
3235               {
3236                 fprintf (file, ", %s", reg_names[REGNO (x)]);
3237                 return;
3238               }
3239             else
3240               abort ();
3241             break;
3242
3243           case POST_INC:
3244             value = GET_MODE_SIZE (GET_MODE (x));
3245             break;
3246
3247           case POST_DEC:
3248             value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
3249             break;
3250           }
3251
3252         putc (',', file);
3253         putc (' ', file);
3254         fprintf (file, HOST_WIDE_INT_PRINT_DEC, value);
3255         return;
3256       }
3257
3258     case 'Q':
3259       if (MEM_VOLATILE_P (x))
3260         fputs(".rel", file);
3261       return;
3262
3263     case 'S':
3264       fprintf (file, "%d", exact_log2 (INTVAL (x)));
3265       return;
3266
3267     case 'T':
3268       if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3269         {
3270           fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
3271           return;
3272         }
3273       break;
3274
3275     case 'U':
3276       if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3277         {
3278           const char *prefix = "0x";
3279           if (INTVAL (x) & 0x80000000)
3280             {
3281               fprintf (file, "0xffffffff");
3282               prefix = "";
3283             }
3284           fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
3285           return;
3286         }
3287       break;
3288
3289     case 'r':
3290       /* If this operand is the constant zero, write it as register zero.
3291          Any register, zero, or CONST_INT value is OK here.  */
3292       if (GET_CODE (x) == REG)
3293         fputs (reg_names[REGNO (x)], file);
3294       else if (x == CONST0_RTX (GET_MODE (x)))
3295         fputs ("r0", file);
3296       else if (GET_CODE (x) == CONST_INT)
3297         output_addr_const (file, x);
3298       else
3299         output_operand_lossage ("invalid %%r value");
3300       return;
3301
3302     case '+':
3303       {
3304         const char *which;
3305
3306         /* For conditional branches, returns or calls, substitute
3307            sptk, dptk, dpnt, or spnt for %s.  */
3308         x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
3309         if (x)
3310           {
3311             int pred_val = INTVAL (XEXP (x, 0));
3312
3313             /* Guess top and bottom 10% statically predicted.  */
3314             if (pred_val < REG_BR_PROB_BASE / 50)
3315               which = ".spnt";
3316             else if (pred_val < REG_BR_PROB_BASE / 2)
3317               which = ".dpnt";
3318             else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
3319               which = ".dptk";
3320             else
3321               which = ".sptk";
3322           }
3323         else if (GET_CODE (current_output_insn) == CALL_INSN)
3324           which = ".sptk";
3325         else
3326           which = ".dptk";
3327
3328         fputs (which, file);
3329         return;
3330       }
3331
3332     case ',':
3333       x = current_insn_predicate;
3334       if (x)
3335         {
3336           unsigned int regno = REGNO (XEXP (x, 0));
3337           if (GET_CODE (x) == EQ)
3338             regno += 1;
3339           fprintf (file, "(%s) ", reg_names [regno]);
3340         }
3341       return;
3342
3343     default:
3344       output_operand_lossage ("ia64_print_operand: unknown code");
3345       return;
3346     }
3347
3348   switch (GET_CODE (x))
3349     {
3350       /* This happens for the spill/restore instructions.  */
3351     case POST_INC:
3352     case POST_DEC:
3353     case POST_MODIFY:
3354       x = XEXP (x, 0);
3355       /* ... fall through ... */
3356
3357     case REG:
3358       fputs (reg_names [REGNO (x)], file);
3359       break;
3360
3361     case MEM:
3362       {
3363         rtx addr = XEXP (x, 0);
3364         if (GET_RTX_CLASS (GET_CODE (addr)) == 'a')
3365           addr = XEXP (addr, 0);
3366         fprintf (file, "[%s]", reg_names [REGNO (addr)]);
3367         break;
3368       }
3369
3370     default:
3371       output_addr_const (file, x);
3372       break;
3373     }
3374
3375   return;
3376 }
3377 \f
3378 /* Calulate the cost of moving data from a register in class FROM to
3379    one in class TO.  */
3380
3381 int
3382 ia64_register_move_cost (from, to)
3383      enum reg_class from, to;
3384 {
3385   int from_hard, to_hard;
3386   int from_gr, to_gr;
3387   int from_fr, to_fr;
3388   int from_pr, to_pr;
3389
3390   from_hard = (from == BR_REGS || from == AR_M_REGS || from == AR_I_REGS);
3391   to_hard = (to == BR_REGS || to == AR_M_REGS || to == AR_I_REGS);
3392   from_gr = (from == GENERAL_REGS);
3393   to_gr = (to == GENERAL_REGS);
3394   from_fr = (from == FR_REGS);
3395   to_fr = (to == FR_REGS);
3396   from_pr = (from == PR_REGS);
3397   to_pr = (to == PR_REGS);
3398
3399   if (from_hard && to_hard)
3400     return 8;
3401   else if ((from_hard && !to_gr) || (!from_gr && to_hard))
3402     return 6;
3403
3404   /* Moving between PR registers takes two insns.  */
3405   else if (from_pr && to_pr)
3406     return 3;
3407   /* Moving between PR and anything but GR is impossible.  */
3408   else if ((from_pr && !to_gr) || (!from_gr && to_pr))
3409     return 6;
3410
3411   /* ??? Moving from FR<->GR must be more expensive than 2, so that we get
3412      secondary memory reloads for TFmode moves.  Unfortunately, we don't
3413      have the mode here, so we can't check that.  */
3414   /* Moreover, we have to make this at least as high as MEMORY_MOVE_COST
3415      to avoid spectacularly poor register class preferencing for TFmode.  */
3416   else if (from_fr != to_fr)
3417     return 5;
3418
3419   return 2;
3420 }
3421
3422 /* This function returns the register class required for a secondary
3423    register when copying between one of the registers in CLASS, and X,
3424    using MODE.  A return value of NO_REGS means that no secondary register
3425    is required.  */
3426
3427 enum reg_class
3428 ia64_secondary_reload_class (class, mode, x)
3429      enum reg_class class;
3430      enum machine_mode mode ATTRIBUTE_UNUSED;
3431      rtx x;
3432 {
3433   int regno = -1;
3434
3435   if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
3436     regno = true_regnum (x);
3437
3438   switch (class)
3439     {
3440     case BR_REGS:
3441       /* ??? This is required because of a bad gcse/cse/global interaction.
3442          We end up with two pseudos with overlapping lifetimes both of which
3443          are equiv to the same constant, and both which need to be in BR_REGS.
3444          This results in a BR_REGS to BR_REGS copy which doesn't exist.  To
3445          reproduce, return NO_REGS here, and compile divdi3 in libgcc2.c.
3446          This seems to be a cse bug.  cse_basic_block_end changes depending
3447          on the path length, which means the qty_first_reg check in
3448          make_regs_eqv can give different answers at different times.  */
3449       /* ??? At some point I'll probably need a reload_indi pattern to handle
3450          this.  */
3451       if (BR_REGNO_P (regno))
3452         return GR_REGS;
3453
3454       /* This is needed if a pseudo used as a call_operand gets spilled to a
3455          stack slot.  */
3456       if (GET_CODE (x) == MEM)
3457         return GR_REGS;
3458       break;
3459
3460     case FR_REGS:
3461       /* This can happen when a paradoxical subreg is an operand to the
3462          muldi3 pattern.  */
3463       /* ??? This shouldn't be necessary after instruction scheduling is
3464          enabled, because paradoxical subregs are not accepted by
3465          register_operand when INSN_SCHEDULING is defined.  Or alternatively,
3466          stop the paradoxical subreg stupidity in the *_operand functions
3467          in recog.c.  */
3468       if (GET_CODE (x) == MEM
3469           && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
3470               || GET_MODE (x) == QImode))
3471         return GR_REGS;
3472
3473       /* This can happen because of the ior/and/etc patterns that accept FP
3474          registers as operands.  If the third operand is a constant, then it
3475          needs to be reloaded into a FP register.  */
3476       if (GET_CODE (x) == CONST_INT)
3477         return GR_REGS;
3478
3479       /* This can happen because of register elimination in a muldi3 insn.
3480          E.g. `26107 * (unsigned long)&u'.  */
3481       if (GET_CODE (x) == PLUS)
3482         return GR_REGS;
3483       break;
3484
3485     case PR_REGS:
3486       /* ??? This happens if we cse/gcse a BImode value across a call,
3487          and the function has a nonlocal goto.  This is because global
3488          does not allocate call crossing pseudos to hard registers when
3489          current_function_has_nonlocal_goto is true.  This is relatively
3490          common for C++ programs that use exceptions.  To reproduce,
3491          return NO_REGS and compile libstdc++.  */
3492       if (GET_CODE (x) == MEM)
3493         return GR_REGS;
3494
3495       /* This can happen when we take a BImode subreg of a DImode value,
3496          and that DImode value winds up in some non-GR register.  */
3497       if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
3498         return GR_REGS;
3499       break;
3500
3501     case GR_REGS:
3502       /* Since we have no offsettable memory addresses, we need a temporary
3503          to hold the address of the second word.  */
3504       if (mode == TImode)
3505         return GR_REGS;
3506       break;
3507
3508     default:
3509       break;
3510     }
3511
3512   return NO_REGS;
3513 }
3514
3515 \f
3516 /* Emit text to declare externally defined variables and functions, because
3517    the Intel assembler does not support undefined externals.  */
3518
3519 void
3520 ia64_asm_output_external (file, decl, name)
3521      FILE *file;
3522      tree decl;
3523      const char *name;
3524 {
3525   int save_referenced;
3526
3527   /* GNU as does not need anything here.  */
3528   if (TARGET_GNU_AS)
3529     return;
3530
3531   /* ??? The Intel assembler creates a reference that needs to be satisfied by
3532      the linker when we do this, so we need to be careful not to do this for
3533      builtin functions which have no library equivalent.  Unfortunately, we
3534      can't tell here whether or not a function will actually be called by
3535      expand_expr, so we pull in library functions even if we may not need
3536      them later.  */
3537   if (! strcmp (name, "__builtin_next_arg")
3538       || ! strcmp (name, "alloca")
3539       || ! strcmp (name, "__builtin_constant_p")
3540       || ! strcmp (name, "__builtin_args_info"))
3541     return;
3542
3543   /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
3544      restore it.  */
3545   save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
3546   if (TREE_CODE (decl) == FUNCTION_DECL)
3547     {
3548       fprintf (file, "%s", TYPE_ASM_OP);
3549       assemble_name (file, name);
3550       putc (',', file);
3551       fprintf (file, TYPE_OPERAND_FMT, "function");
3552       putc ('\n', file);
3553     }
3554   ASM_GLOBALIZE_LABEL (file, name);
3555   TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
3556 }
3557 \f
3558 /* Parse the -mfixed-range= option string.  */
3559
3560 static void
3561 fix_range (const_str)
3562      const char *const_str;
3563 {
3564   int i, first, last;
3565   char *str, *dash, *comma;
3566
3567   /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
3568      REG2 are either register names or register numbers.  The effect
3569      of this option is to mark the registers in the range from REG1 to
3570      REG2 as ``fixed'' so they won't be used by the compiler.  This is
3571      used, e.g., to ensure that kernel mode code doesn't use f32-f127.  */
3572
3573   i = strlen (const_str);
3574   str = (char *) alloca (i + 1);
3575   memcpy (str, const_str, i + 1);
3576
3577   while (1)
3578     {
3579       dash = strchr (str, '-');
3580       if (!dash)
3581         {
3582           warning ("value of -mfixed-range must have form REG1-REG2");
3583           return;
3584         }
3585       *dash = '\0';
3586
3587       comma = strchr (dash + 1, ',');
3588       if (comma)
3589         *comma = '\0';
3590
3591       first = decode_reg_name (str);
3592       if (first < 0)
3593         {
3594           warning ("unknown register name: %s", str);
3595           return;
3596         }
3597
3598       last = decode_reg_name (dash + 1);
3599       if (last < 0)
3600         {
3601           warning ("unknown register name: %s", dash + 1);
3602           return;
3603         }
3604
3605       *dash = '-';
3606
3607       if (first > last)
3608         {
3609           warning ("%s-%s is an empty range", str, dash + 1);
3610           return;
3611         }
3612
3613       for (i = first; i <= last; ++i)
3614         fixed_regs[i] = call_used_regs[i] = 1;
3615
3616       if (!comma)
3617         break;
3618
3619       *comma = ',';
3620       str = comma + 1;
3621     }
3622 }
3623
3624 /* Called to register all of our global variables with the garbage
3625    collector.  */
3626
3627 static void
3628 ia64_add_gc_roots ()
3629 {
3630   ggc_add_rtx_root (&ia64_compare_op0, 1);
3631   ggc_add_rtx_root (&ia64_compare_op1, 1);
3632 }
3633
3634 static void
3635 ia64_init_machine_status (p)
3636      struct function *p;
3637 {
3638   p->machine =
3639     (struct machine_function *) xcalloc (1, sizeof (struct machine_function));
3640 }
3641
3642 static void
3643 ia64_mark_machine_status (p)
3644      struct function *p;
3645 {
3646   ggc_mark_rtx (p->machine->ia64_eh_epilogue_sp);
3647   ggc_mark_rtx (p->machine->ia64_eh_epilogue_bsp);
3648   ggc_mark_rtx (p->machine->ia64_gp_save);
3649 }
3650
3651
3652 /* Handle TARGET_OPTIONS switches.  */
3653
3654 void
3655 ia64_override_options ()
3656 {
3657   if (TARGET_AUTO_PIC)
3658     target_flags |= MASK_CONST_GP;
3659
3660   if (TARGET_INLINE_DIV_LAT && TARGET_INLINE_DIV_THR)
3661     {
3662       warning ("cannot optimize division for both latency and throughput");
3663       target_flags &= ~MASK_INLINE_DIV_THR;
3664     }
3665
3666   if (ia64_fixed_range_string)
3667     fix_range (ia64_fixed_range_string);
3668
3669   ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
3670
3671   init_machine_status = ia64_init_machine_status;
3672   mark_machine_status = ia64_mark_machine_status;
3673
3674   ia64_add_gc_roots ();
3675 }
3676 \f
3677 /* The following collection of routines emit instruction group stop bits as
3678    necessary to avoid dependencies.  */
3679
3680 /* Need to track some additional registers as far as serialization is
3681    concerned so we can properly handle br.call and br.ret.  We could
3682    make these registers visible to gcc, but since these registers are
3683    never explicitly used in gcc generated code, it seems wasteful to
3684    do so (plus it would make the call and return patterns needlessly
3685    complex).  */
3686 #define REG_GP          (GR_REG (1))
3687 #define REG_RP          (BR_REG (0))
3688 #define REG_AR_CFM      (FIRST_PSEUDO_REGISTER + 1)
3689 /* This is used for volatile asms which may require a stop bit immediately
3690    before and after them.  */
3691 #define REG_VOLATILE    (FIRST_PSEUDO_REGISTER + 2)
3692 #define AR_UNAT_BIT_0   (FIRST_PSEUDO_REGISTER + 3)
3693 #define NUM_REGS        (AR_UNAT_BIT_0 + 64)
3694
3695 /* For each register, we keep track of how it has been written in the
3696    current instruction group.
3697
3698    If a register is written unconditionally (no qualifying predicate),
3699    WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
3700
3701    If a register is written if its qualifying predicate P is true, we
3702    set WRITE_COUNT to 1 and FIRST_PRED to P.  Later on, the same register
3703    may be written again by the complement of P (P^1) and when this happens,
3704    WRITE_COUNT gets set to 2.
3705
3706    The result of this is that whenever an insn attempts to write a register
3707    whose WRITE_COUNT is two, we need to issue a insn group barrier first.
3708
3709    If a predicate register is written by a floating-point insn, we set
3710    WRITTEN_BY_FP to true.
3711
3712    If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
3713    to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true.  */
3714
3715 struct reg_write_state
3716 {
3717   unsigned int write_count : 2;
3718   unsigned int first_pred : 16;
3719   unsigned int written_by_fp : 1;
3720   unsigned int written_by_and : 1;
3721   unsigned int written_by_or : 1;
3722 };
3723
3724 /* Cumulative info for the current instruction group.  */
3725 struct reg_write_state rws_sum[NUM_REGS];
3726 /* Info for the current instruction.  This gets copied to rws_sum after a
3727    stop bit is emitted.  */
3728 struct reg_write_state rws_insn[NUM_REGS];
3729
3730 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
3731    RTL for one instruction.  */
3732 struct reg_flags
3733 {
3734   unsigned int is_write : 1;    /* Is register being written?  */
3735   unsigned int is_fp : 1;       /* Is register used as part of an fp op?  */
3736   unsigned int is_branch : 1;   /* Is register used as part of a branch?  */
3737   unsigned int is_and : 1;      /* Is register used as part of and.orcm?  */
3738   unsigned int is_or : 1;       /* Is register used as part of or.andcm?  */
3739   unsigned int is_sibcall : 1;  /* Is this a sibling or normal call?  */
3740 };
3741
3742 static void rws_update PARAMS ((struct reg_write_state *, int,
3743                                 struct reg_flags, int));
3744 static int rws_access_regno PARAMS ((int, struct reg_flags, int));
3745 static int rws_access_reg PARAMS ((rtx, struct reg_flags, int));
3746 static int rtx_needs_barrier PARAMS ((rtx, struct reg_flags, int));
3747
3748 /* Update *RWS for REGNO, which is being written by the current instruction,
3749    with predicate PRED, and associated register flags in FLAGS.  */
3750
3751 static void
3752 rws_update (rws, regno, flags, pred)
3753      struct reg_write_state *rws;
3754      int regno;
3755      struct reg_flags flags;
3756      int pred;
3757 {
3758   rws[regno].write_count += pred ? 1 : 2;
3759   rws[regno].written_by_fp |= flags.is_fp;
3760   /* ??? Not tracking and/or across differing predicates.  */
3761   rws[regno].written_by_and = flags.is_and;
3762   rws[regno].written_by_or = flags.is_or;
3763   rws[regno].first_pred = pred;
3764 }
3765
3766 /* Handle an access to register REGNO of type FLAGS using predicate register
3767    PRED.  Update rws_insn and rws_sum arrays.  Return 1 if this access creates
3768    a dependency with an earlier instruction in the same group.  */
3769
3770 static int
3771 rws_access_regno (regno, flags, pred)
3772      int regno;
3773      struct reg_flags flags;
3774      int pred;
3775 {
3776   int need_barrier = 0;
3777
3778   if (regno >= NUM_REGS)
3779     abort ();
3780
3781   if (! PR_REGNO_P (regno))
3782     flags.is_and = flags.is_or = 0;
3783
3784   if (flags.is_write)
3785     {
3786       int write_count;
3787
3788       /* One insn writes same reg multiple times?  */
3789       if (rws_insn[regno].write_count > 0)
3790         abort ();
3791
3792       /* Update info for current instruction.  */
3793       rws_update (rws_insn, regno, flags, pred);
3794       write_count = rws_sum[regno].write_count;
3795
3796       switch (write_count)
3797         {
3798         case 0:
3799           /* The register has not been written yet.  */
3800           rws_update (rws_sum, regno, flags, pred);
3801           break;
3802
3803         case 1:
3804           /* The register has been written via a predicate.  If this is
3805              not a complementary predicate, then we need a barrier.  */
3806           /* ??? This assumes that P and P+1 are always complementary
3807              predicates for P even.  */
3808           if (flags.is_and && rws_sum[regno].written_by_and)
3809             ;
3810           else if (flags.is_or && rws_sum[regno].written_by_or)
3811             ;
3812           else if ((rws_sum[regno].first_pred ^ 1) != pred)
3813             need_barrier = 1;
3814           rws_update (rws_sum, regno, flags, pred);
3815           break;
3816
3817         case 2:
3818           /* The register has been unconditionally written already.  We
3819              need a barrier.  */
3820           if (flags.is_and && rws_sum[regno].written_by_and)
3821             ;
3822           else if (flags.is_or && rws_sum[regno].written_by_or)
3823             ;
3824           else
3825             need_barrier = 1;
3826           rws_sum[regno].written_by_and = flags.is_and;
3827           rws_sum[regno].written_by_or = flags.is_or;
3828           break;
3829
3830         default:
3831           abort ();
3832         }
3833     }
3834   else
3835     {
3836       if (flags.is_branch)
3837         {
3838           /* Branches have several RAW exceptions that allow to avoid
3839              barriers.  */
3840
3841           if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
3842             /* RAW dependencies on branch regs are permissible as long
3843                as the writer is a non-branch instruction.  Since we
3844                never generate code that uses a branch register written
3845                by a branch instruction, handling this case is
3846                easy.  */
3847             return 0;
3848
3849           if (REGNO_REG_CLASS (regno) == PR_REGS
3850               && ! rws_sum[regno].written_by_fp)
3851             /* The predicates of a branch are available within the
3852                same insn group as long as the predicate was written by
3853                something other than a floating-point instruction.   */
3854             return 0;
3855         }
3856
3857       if (flags.is_and && rws_sum[regno].written_by_and)
3858         return 0;
3859       if (flags.is_or && rws_sum[regno].written_by_or)
3860         return 0;
3861
3862       switch (rws_sum[regno].write_count)
3863         {
3864         case 0:
3865           /* The register has not been written yet.  */
3866           break;
3867
3868         case 1:
3869           /* The register has been written via a predicate.  If this is
3870              not a complementary predicate, then we need a barrier.  */
3871           /* ??? This assumes that P and P+1 are always complementary
3872              predicates for P even.  */
3873           if ((rws_sum[regno].first_pred ^ 1) != pred)
3874             need_barrier = 1;
3875           break;
3876
3877         case 2:
3878           /* The register has been unconditionally written already.  We
3879              need a barrier.  */
3880           need_barrier = 1;
3881           break;
3882
3883         default:
3884           abort ();
3885         }
3886     }
3887
3888   return need_barrier;
3889 }
3890
3891 static int
3892 rws_access_reg (reg, flags, pred)
3893      rtx reg;
3894      struct reg_flags flags;
3895      int pred;
3896 {
3897   int regno = REGNO (reg);
3898   int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
3899
3900   if (n == 1)
3901     return rws_access_regno (regno, flags, pred);
3902   else
3903     {
3904       int need_barrier = 0;
3905       while (--n >= 0)
3906         need_barrier |= rws_access_regno (regno + n, flags, pred);
3907       return need_barrier;
3908     }
3909 }
3910
3911 /* Handle an access to rtx X of type FLAGS using predicate register PRED.
3912    Return 1 is this access creates a dependency with an earlier instruction
3913    in the same group.  */
3914
3915 static int
3916 rtx_needs_barrier (x, flags, pred)
3917      rtx x;
3918      struct reg_flags flags;
3919      int pred;
3920 {
3921   int i, j;
3922   int is_complemented = 0;
3923   int need_barrier = 0;
3924   const char *format_ptr;
3925   struct reg_flags new_flags;
3926   rtx src, dst;
3927   rtx cond = 0;
3928
3929   if (! x)
3930     return 0;
3931
3932   new_flags = flags;
3933
3934   switch (GET_CODE (x))
3935     {
3936     case SET:
3937       src = SET_SRC (x);
3938       switch (GET_CODE (src))
3939         {
3940         case CALL:
3941           /* We don't need to worry about the result registers that
3942              get written by subroutine call.  */
3943           need_barrier = rtx_needs_barrier (src, flags, pred);
3944           return need_barrier;
3945
3946         case IF_THEN_ELSE:
3947           if (SET_DEST (x) == pc_rtx)
3948             {
3949               /* X is a conditional branch.  */
3950               /* ??? This seems redundant, as the caller sets this bit for
3951                  all JUMP_INSNs.  */
3952               new_flags.is_branch = 1;
3953               need_barrier = rtx_needs_barrier (src, new_flags, pred);
3954               return need_barrier;
3955             }
3956           else
3957             {
3958               /* X is a conditional move.  */
3959               cond = XEXP (src, 0);
3960               if (GET_CODE (cond) == EQ)
3961                 is_complemented = 1;
3962               cond = XEXP (cond, 0);
3963               if (GET_CODE (cond) != REG
3964                   && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
3965                 abort ();
3966
3967               if (XEXP (src, 1) == SET_DEST (x)
3968                   || XEXP (src, 2) == SET_DEST (x))
3969                 {
3970                   /* X is a conditional move that conditionally writes the
3971                      destination.  */
3972
3973                   /* We need another complement in this case.  */
3974                   if (XEXP (src, 1) == SET_DEST (x))
3975                     is_complemented = ! is_complemented;
3976
3977                   pred = REGNO (cond);
3978                   if (is_complemented)
3979                     ++pred;
3980                 }
3981
3982               /* ??? If this is a conditional write to the dest, then this
3983                  instruction does not actually read one source.  This probably
3984                  doesn't matter, because that source is also the dest.  */
3985               /* ??? Multiple writes to predicate registers are allowed
3986                  if they are all AND type compares, or if they are all OR
3987                  type compares.  We do not generate such instructions
3988                  currently.  */
3989             }
3990           /* ... fall through ... */
3991
3992         default:
3993           if (GET_RTX_CLASS (GET_CODE (src)) == '<'
3994                && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
3995             /* Set new_flags.is_fp to 1 so that we know we're dealing
3996                with a floating point comparison when processing the
3997                destination of the SET.  */
3998             new_flags.is_fp = 1;
3999
4000           /* Discover if this is a parallel comparison.  We only handle
4001              and.orcm and or.andcm at present, since we must retain a
4002              strict inverse on the predicate pair.  */
4003           else if (GET_CODE (src) == AND)
4004             new_flags.is_and = flags.is_and = 1;
4005           else if (GET_CODE (src) == IOR)
4006             new_flags.is_or = flags.is_or = 1;
4007
4008           break;
4009         }
4010       need_barrier = rtx_needs_barrier (src, flags, pred);
4011
4012       /* This instruction unconditionally uses a predicate register.  */
4013       if (cond)
4014         need_barrier |= rws_access_reg (cond, flags, 0);
4015
4016       dst = SET_DEST (x);
4017       if (GET_CODE (dst) == ZERO_EXTRACT)
4018         {
4019           need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
4020           need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
4021           dst = XEXP (dst, 0);
4022         }
4023       new_flags.is_write = 1;
4024       need_barrier |= rtx_needs_barrier (dst, new_flags, pred);
4025       break;
4026
4027     case CALL:
4028       new_flags.is_write = 0;
4029       need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
4030
4031       /* Avoid multiple register writes, in case this is a pattern with
4032          multiple CALL rtx.  This avoids an abort in rws_access_reg.  */
4033       if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
4034         {
4035           new_flags.is_write = 1;
4036           need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
4037           need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
4038           need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
4039         }
4040       break;
4041
4042     case COND_EXEC:
4043       /* X is a predicated instruction.  */
4044
4045       cond = COND_EXEC_TEST (x);
4046       if (pred)
4047         abort ();
4048       need_barrier = rtx_needs_barrier (cond, flags, 0);
4049
4050       if (GET_CODE (cond) == EQ)
4051         is_complemented = 1;
4052       cond = XEXP (cond, 0);
4053       if (GET_CODE (cond) != REG
4054           && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4055         abort ();
4056       pred = REGNO (cond);
4057       if (is_complemented)
4058         ++pred;
4059
4060       need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
4061       return need_barrier;
4062
4063     case CLOBBER:
4064     case USE:
4065       /* Clobber & use are for earlier compiler-phases only.  */
4066       break;
4067
4068     case ASM_OPERANDS:
4069     case ASM_INPUT:
4070       /* We always emit stop bits for traditional asms.  We emit stop bits
4071          for volatile extended asms if TARGET_VOL_ASM_STOP is true.  */
4072       if (GET_CODE (x) != ASM_OPERANDS
4073           || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
4074         {
4075           /* Avoid writing the register multiple times if we have multiple
4076              asm outputs.  This avoids an abort in rws_access_reg.  */
4077           if (! rws_insn[REG_VOLATILE].write_count)
4078             {
4079               new_flags.is_write = 1;
4080               rws_access_regno (REG_VOLATILE, new_flags, pred);
4081             }
4082           return 1;
4083         }
4084
4085       /* For all ASM_OPERANDS, we must traverse the vector of input operands.
4086          We can not just fall through here since then we would be confused
4087          by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
4088          traditional asms unlike their normal usage.  */
4089
4090       for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
4091         if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
4092           need_barrier = 1;
4093       break;
4094
4095     case PARALLEL:
4096       for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
4097         if (rtx_needs_barrier (XVECEXP (x, 0, i), flags, pred))
4098           need_barrier = 1;
4099       break;
4100
4101     case SUBREG:
4102       x = SUBREG_REG (x);
4103       /* FALLTHRU */
4104     case REG:
4105       if (REGNO (x) == AR_UNAT_REGNUM)
4106         {
4107           for (i = 0; i < 64; ++i)
4108             need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
4109         }
4110       else
4111         need_barrier = rws_access_reg (x, flags, pred);
4112       break;
4113
4114     case MEM:
4115       /* Find the regs used in memory address computation.  */
4116       new_flags.is_write = 0;
4117       need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
4118       break;
4119
4120     case CONST_INT:   case CONST_DOUBLE:
4121     case SYMBOL_REF:  case LABEL_REF:     case CONST:
4122       break;
4123
4124       /* Operators with side-effects.  */
4125     case POST_INC:    case POST_DEC:
4126       if (GET_CODE (XEXP (x, 0)) != REG)
4127         abort ();
4128
4129       new_flags.is_write = 0;
4130       need_barrier  = rws_access_reg (XEXP (x, 0), new_flags, pred);
4131       new_flags.is_write = 1;
4132       need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
4133       break;
4134
4135     case POST_MODIFY:
4136       if (GET_CODE (XEXP (x, 0)) != REG)
4137         abort ();
4138
4139       new_flags.is_write = 0;
4140       need_barrier  = rws_access_reg (XEXP (x, 0), new_flags, pred);
4141       need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
4142       new_flags.is_write = 1;
4143       need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
4144       break;
4145
4146       /* Handle common unary and binary ops for efficiency.  */
4147     case COMPARE:  case PLUS:    case MINUS:   case MULT:      case DIV:
4148     case MOD:      case UDIV:    case UMOD:    case AND:       case IOR:
4149     case XOR:      case ASHIFT:  case ROTATE:  case ASHIFTRT:  case LSHIFTRT:
4150     case ROTATERT: case SMIN:    case SMAX:    case UMIN:      case UMAX:
4151     case NE:       case EQ:      case GE:      case GT:        case LE:
4152     case LT:       case GEU:     case GTU:     case LEU:       case LTU:
4153       need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
4154       need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
4155       break;
4156
4157     case NEG:      case NOT:            case SIGN_EXTEND:     case ZERO_EXTEND:
4158     case TRUNCATE: case FLOAT_EXTEND:   case FLOAT_TRUNCATE:  case FLOAT:
4159     case FIX:      case UNSIGNED_FLOAT: case UNSIGNED_FIX:    case ABS:
4160     case SQRT:     case FFS:
4161       need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
4162       break;
4163
4164     case UNSPEC:
4165       switch (XINT (x, 1))
4166         {
4167         case 1: /* st8.spill */
4168         case 2: /* ld8.fill */
4169           {
4170             HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
4171             HOST_WIDE_INT bit = (offset >> 3) & 63;
4172
4173             need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
4174             new_flags.is_write = (XINT (x, 1) == 1);
4175             need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
4176                                               new_flags, pred);
4177             break;
4178           }
4179
4180         case 3: /* stf.spill */
4181         case 4: /* ldf.spill */
4182         case 8: /* popcnt */
4183           need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
4184           break;
4185
4186         case 7: /* pred_rel_mutex */
4187         case 9: /* pic call */
4188         case 12: /* mf */
4189         case 19: /* fetchadd_acq */
4190         case 20: /* mov = ar.bsp */
4191         case 21: /* flushrs */
4192           break;
4193
4194         case 5: /* recip_approx */
4195           need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
4196           need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
4197           break;
4198
4199         case 13: /* cmpxchg_acq */
4200           need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
4201           need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
4202           break;
4203
4204         default:
4205           abort ();
4206         }
4207       break;
4208
4209     case UNSPEC_VOLATILE:
4210       switch (XINT (x, 1))
4211         {
4212         case 0: /* alloc */
4213           /* Alloc must always be the first instruction.  Currently, we
4214              only emit it at the function start, so we don't need to worry
4215              about emitting a stop bit before it.  */
4216           need_barrier = rws_access_regno (AR_PFS_REGNUM, flags, pred);
4217
4218           new_flags.is_write = 1;
4219           need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
4220           return need_barrier;
4221
4222         case 1: /* blockage */
4223         case 2: /* insn group barrier */
4224           return 0;
4225
4226         case 5: /* set_bsp  */
4227           need_barrier = 1;
4228           break;
4229
4230         case 7: /* pred.rel.mutex */
4231         case 8: /* safe_across_calls all */
4232         case 9: /* safe_across_calls normal */
4233           return 0;
4234
4235         default:
4236           abort ();
4237         }
4238       break;
4239
4240     case RETURN:
4241       new_flags.is_write = 0;
4242       need_barrier  = rws_access_regno (REG_RP, flags, pred);
4243       need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
4244
4245       new_flags.is_write = 1;
4246       need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
4247       need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
4248       break;
4249
4250     default:
4251       format_ptr = GET_RTX_FORMAT (GET_CODE (x));
4252       for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4253         switch (format_ptr[i])
4254           {
4255           case '0':     /* unused field */
4256           case 'i':     /* integer */
4257           case 'n':     /* note */
4258           case 'w':     /* wide integer */
4259           case 's':     /* pointer to string */
4260           case 'S':     /* optional pointer to string */
4261             break;
4262
4263           case 'e':
4264             if (rtx_needs_barrier (XEXP (x, i), flags, pred))
4265               need_barrier = 1;
4266             break;
4267
4268           case 'E':
4269             for (j = XVECLEN (x, i) - 1; j >= 0; --j)
4270               if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
4271                 need_barrier = 1;
4272             break;
4273
4274           default:
4275             abort ();
4276           }
4277       break;
4278     }
4279   return need_barrier;
4280 }
4281
4282 /* INSNS is an chain of instructions.  Scan the chain, and insert stop bits
4283    as necessary to eliminate dependendencies.  */
4284
4285 static void
4286 emit_insn_group_barriers (insns)
4287      rtx insns;
4288 {
4289   rtx insn, prev_insn;
4290
4291   memset (rws_sum, 0, sizeof (rws_sum));
4292
4293   prev_insn = 0;
4294   for (insn = insns; insn; insn = NEXT_INSN (insn))
4295     {
4296       int need_barrier = 0;
4297       struct reg_flags flags;
4298
4299       memset (&flags, 0, sizeof (flags));
4300       switch (GET_CODE (insn))
4301         {
4302         case NOTE:
4303           /* For very small loops we can wind up with extra stop bits
4304              inside the loop because of not putting a stop after the
4305              assignment to ar.lc before the loop label.  */
4306           /* ??? Ideally we'd do this for any register used in the first
4307              insn group that's been written recently.  */
4308           if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
4309             {
4310               need_barrier = rws_access_regno (AR_LC_REGNUM, flags, 0);
4311               if (need_barrier)
4312                 {
4313                   emit_insn_after (gen_insn_group_barrier (), insn);
4314                   memset (rws_sum, 0, sizeof(rws_sum));
4315                   prev_insn = NULL_RTX;
4316                 }
4317             }
4318           break;
4319
4320         case CALL_INSN:
4321           flags.is_branch = 1;
4322           flags.is_sibcall = SIBLING_CALL_P (insn);
4323           memset (rws_insn, 0, sizeof (rws_insn));
4324           need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
4325
4326           if (need_barrier)
4327             {
4328               /* PREV_INSN null can happen if the very first insn is a
4329                  volatile asm.  */
4330               if (prev_insn)
4331                 emit_insn_after (gen_insn_group_barrier (), prev_insn);
4332               memcpy (rws_sum, rws_insn, sizeof (rws_sum));
4333             }
4334
4335           /* A call must end a group, otherwise the assembler might pack
4336              it in with a following branch and then the function return
4337              goes to the wrong place.  Do this unconditionally for
4338              unconditional calls, simply because it (1) looks nicer and
4339              (2) keeps the data structures more accurate for the insns
4340              following the call.  */
4341
4342           need_barrier = 1;
4343           if (GET_CODE (PATTERN (insn)) == COND_EXEC)
4344             {
4345               rtx next_insn = insn;
4346               do
4347                 next_insn = next_nonnote_insn (next_insn);
4348               while (next_insn
4349                      && GET_CODE (next_insn) == INSN
4350                      && (GET_CODE (PATTERN (next_insn)) == USE
4351                          || GET_CODE (PATTERN (next_insn)) == CLOBBER));
4352               if (next_insn && GET_CODE (next_insn) != JUMP_INSN)
4353                 need_barrier = 0;
4354             }
4355           if (need_barrier)
4356             {
4357               emit_insn_after (gen_insn_group_barrier (), insn);
4358               memset (rws_sum, 0, sizeof (rws_sum));
4359               prev_insn = NULL_RTX;
4360             }
4361           else
4362             prev_insn = insn;
4363           break;
4364
4365         case JUMP_INSN:
4366           flags.is_branch = 1;
4367           /* FALLTHRU */
4368
4369         case INSN:
4370           if (GET_CODE (PATTERN (insn)) == USE)
4371             /* Don't care about USE "insns"---those are used to
4372                indicate to the optimizer that it shouldn't get rid of
4373                certain operations.  */
4374             break;
4375           else
4376             {
4377               rtx pat = PATTERN (insn);
4378
4379               /* Ug.  Hack hacks hacked elsewhere.  */
4380               switch (recog_memoized (insn))
4381                 {
4382                   /* We play dependency tricks with the epilogue in order
4383                      to get proper schedules.  Undo this for dv analysis.  */
4384                 case CODE_FOR_epilogue_deallocate_stack:
4385                   pat = XVECEXP (pat, 0, 0);
4386                   break;
4387
4388                   /* The pattern we use for br.cloop confuses the code above.
4389                      The second element of the vector is representative.  */
4390                 case CODE_FOR_doloop_end_internal:
4391                   pat = XVECEXP (pat, 0, 1);
4392                   break;
4393
4394                   /* Doesn't generate code.  */
4395                 case CODE_FOR_pred_rel_mutex:
4396                   continue;
4397
4398                 default:
4399                   break;
4400                 }
4401
4402               memset (rws_insn, 0, sizeof (rws_insn));
4403               need_barrier |= rtx_needs_barrier (pat, flags, 0);
4404
4405               /* Check to see if the previous instruction was a volatile
4406                  asm.  */
4407               if (! need_barrier)
4408                 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
4409
4410               if (need_barrier)
4411                 {
4412                   /* PREV_INSN null can happen if the very first insn is a
4413                      volatile asm.  */
4414                   if (prev_insn)
4415                     emit_insn_after (gen_insn_group_barrier (), prev_insn);
4416                   memcpy (rws_sum, rws_insn, sizeof (rws_sum));
4417                 }
4418               prev_insn = insn;
4419             }
4420           break;
4421
4422         case BARRIER:
4423           /* A barrier doesn't imply an instruction group boundary.  */
4424           break;
4425
4426         case CODE_LABEL:
4427           /* Leave prev_insn alone so the barrier gets generated in front
4428              of the label, if one is needed.  */
4429           break;
4430
4431         default:
4432           abort ();
4433         }
4434     }
4435 }
4436
4437 /* Emit pseudo-ops for the assembler to describe predicate relations.
4438    At present this assumes that we only consider predicate pairs to
4439    be mutex, and that the assembler can deduce proper values from
4440    straight-line code.  */
4441
4442 static void
4443 emit_predicate_relation_info ()
4444 {
4445   int i;
4446
4447   for (i = n_basic_blocks - 1; i >= 0; --i)
4448     {
4449       basic_block bb = BASIC_BLOCK (i);
4450       int r;
4451       rtx head = bb->head;
4452
4453       /* We only need such notes at code labels.  */
4454       if (GET_CODE (head) != CODE_LABEL)
4455         continue;
4456       if (GET_CODE (NEXT_INSN (head)) == NOTE
4457           && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
4458         head = NEXT_INSN (head);
4459
4460       for (r = PR_REG (0); r < PR_REG (64); r += 2)
4461         if (REGNO_REG_SET_P (bb->global_live_at_start, r))
4462           {
4463             rtx p = gen_rtx_REG (BImode, r);
4464             rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
4465             if (head == bb->end)
4466               bb->end = n;
4467             head = n;
4468           }
4469     }
4470
4471   /* Look for conditional calls that do not return, and protect predicate
4472      relations around them.  Otherwise the assembler will assume the call
4473      returns, and complain about uses of call-clobbered predicates after
4474      the call.  */
4475   for (i = n_basic_blocks - 1; i >= 0; --i)
4476     {
4477       basic_block bb = BASIC_BLOCK (i);
4478       rtx insn = bb->head;
4479
4480       while (1)
4481         {
4482           if (GET_CODE (insn) == CALL_INSN
4483               && GET_CODE (PATTERN (insn)) == COND_EXEC
4484               && find_reg_note (insn, REG_NORETURN, NULL_RTX))
4485             {
4486               rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
4487               rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
4488               if (bb->head == insn)
4489                 bb->head = b;
4490               if (bb->end == insn)
4491                 bb->end = a;
4492             }
4493
4494           if (insn == bb->end)
4495             break;
4496           insn = NEXT_INSN (insn);
4497         }
4498     }
4499 }
4500
4501 /* Perform machine dependent operations on the rtl chain INSNS.  */
4502
4503 void
4504 ia64_reorg (insns)
4505      rtx insns;
4506 {
4507   /* If optimizing, we'll have split before scheduling.  */
4508   if (optimize == 0)
4509     split_all_insns (0);
4510
4511   /* Make sure the CFG and global_live_at_start are correct
4512      for emit_predicate_relation_info.  */
4513   find_basic_blocks (insns, max_reg_num (), NULL);
4514   life_analysis (insns, NULL, 0);
4515
4516   emit_insn_group_barriers (insns);
4517   emit_predicate_relation_info ();
4518 }
4519 \f
4520 /* Return true if REGNO is used by the epilogue.  */
4521
4522 int
4523 ia64_epilogue_uses (regno)
4524      int regno;
4525 {
4526   /* When a function makes a call through a function descriptor, we
4527      will write a (potentially) new value to "gp".  After returning
4528      from such a call, we need to make sure the function restores the
4529      original gp-value, even if the function itself does not use the
4530      gp anymore.  */
4531   if (regno == R_GR (1)
4532       && TARGET_CONST_GP
4533       && !(TARGET_AUTO_PIC || TARGET_NO_PIC))
4534     return 1;
4535
4536   /* For functions defined with the syscall_linkage attribute, all input
4537      registers are marked as live at all function exits.  This prevents the
4538      register allocator from using the input registers, which in turn makes it
4539      possible to restart a system call after an interrupt without having to
4540      save/restore the input registers.  */
4541
4542   if (IN_REGNO_P (regno)
4543       && (regno < IN_REG (current_function_args_info.words))
4544       && lookup_attribute ("syscall_linkage",
4545                            TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4546     return 1;
4547
4548   /* Conditional return patterns can't represent the use of `b0' as
4549      the return address, so we force the value live this way.  */
4550   if (regno == R_BR (0))
4551     return 1;
4552
4553   if (regs_ever_live[AR_LC_REGNUM] && regno == AR_LC_REGNUM)
4554     return 1;
4555   if (! current_function_is_leaf && regno == AR_PFS_REGNUM)
4556     return 1;
4557   if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
4558       && regno == AR_UNAT_REGNUM)
4559     return 1;
4560
4561   return 0;
4562 }
4563
4564 /* Return true if IDENTIFIER is a valid attribute for TYPE.  */
4565
4566 int
4567 ia64_valid_type_attribute (type, attributes, identifier, args)
4568      tree type;
4569      tree attributes ATTRIBUTE_UNUSED;
4570      tree identifier;
4571      tree args;
4572 {
4573   /* We only support an attribute for function calls.  */
4574
4575   if (TREE_CODE (type) != FUNCTION_TYPE
4576       && TREE_CODE (type) != METHOD_TYPE)
4577     return 0;
4578
4579   /* The "syscall_linkage" attribute says the callee is a system call entry
4580      point.  This affects ia64_epilogue_uses.  */
4581
4582   if (is_attribute_p ("syscall_linkage", identifier))
4583     return args == NULL_TREE;
4584
4585   return 0;
4586 }
4587 \f
4588 /* For ia64, SYMBOL_REF_FLAG set means that it is a function.
4589
4590    We add @ to the name if this goes in small data/bss.  We can only put
4591    a variable in small data/bss if it is defined in this module or a module
4592    that we are statically linked with.  We can't check the second condition,
4593    but TREE_STATIC gives us the first one.  */
4594
4595 /* ??? If we had IPA, we could check the second condition.  We could support
4596    programmer added section attributes if the variable is not defined in this
4597    module.  */
4598
4599 /* ??? See the v850 port for a cleaner way to do this.  */
4600
4601 /* ??? We could also support own long data here.  Generating movl/add/ld8
4602    instead of addl,ld8/ld8.  This makes the code bigger, but should make the
4603    code faster because there is one less load.  This also includes incomplete
4604    types which can't go in sdata/sbss.  */
4605
4606 /* ??? See select_section.  We must put short own readonly variables in
4607    sdata/sbss instead of the more natural rodata, because we can't perform
4608    the DECL_READONLY_SECTION test here.  */
4609
4610 extern struct obstack * saveable_obstack;
4611
4612 void
4613 ia64_encode_section_info (decl)
4614      tree decl;
4615 {
4616   const char *symbol_str;
4617
4618   if (TREE_CODE (decl) == FUNCTION_DECL)
4619     {
4620       SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
4621       return;
4622     }
4623
4624   /* Careful not to prod global register variables.  */
4625   if (TREE_CODE (decl) != VAR_DECL
4626       || GET_CODE (DECL_RTL (decl)) != MEM
4627       || GET_CODE (XEXP (DECL_RTL (decl), 0)) != SYMBOL_REF)
4628     return;
4629
4630   symbol_str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
4631
4632   /* We assume that -fpic is used only to create a shared library (dso).
4633      With -fpic, no global data can ever be sdata.
4634      Without -fpic, global common uninitialized data can never be sdata, since
4635      it can unify with a real definition in a dso.  */
4636   /* ??? Actually, we can put globals in sdata, as long as we don't use gprel
4637      to access them.  The linker may then be able to do linker relaxation to
4638      optimize references to them.  Currently sdata implies use of gprel.  */
4639   if (! TARGET_NO_SDATA
4640       && TREE_STATIC (decl)
4641       && ! (DECL_ONE_ONLY (decl) || DECL_WEAK (decl))
4642       && ! (TREE_PUBLIC (decl)
4643             && (flag_pic
4644                 || (DECL_COMMON (decl)
4645                     && (DECL_INITIAL (decl) == 0
4646                         || DECL_INITIAL (decl) == error_mark_node))))
4647       /* Either the variable must be declared without a section attribute,
4648          or the section must be sdata or sbss.  */
4649       && (DECL_SECTION_NAME (decl) == 0
4650           || ! strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
4651                        ".sdata")
4652           || ! strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
4653                        ".sbss")))
4654     {
4655       HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
4656
4657       /* If the variable has already been defined in the output file, then it
4658          is too late to put it in sdata if it wasn't put there in the first
4659          place.  The test is here rather than above, because if it is already
4660          in sdata, then it can stay there.  */
4661
4662       if (TREE_ASM_WRITTEN (decl))
4663         ;
4664
4665       /* If this is an incomplete type with size 0, then we can't put it in
4666          sdata because it might be too big when completed.  */
4667       else if (size > 0
4668                && size <= (HOST_WIDE_INT) ia64_section_threshold
4669                && symbol_str[0] != SDATA_NAME_FLAG_CHAR)
4670         {
4671           size_t len = strlen (symbol_str);
4672           char *newstr;
4673
4674           newstr = ggc_alloc_string (NULL, len + 1);
4675           *newstr = SDATA_NAME_FLAG_CHAR;
4676           memcpy (newstr + 1, symbol_str, len + 1);
4677
4678           XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
4679         }
4680     }
4681   /* This decl is marked as being in small data/bss but it shouldn't
4682      be; one likely explanation for this is that the decl has been
4683      moved into a different section from the one it was in when
4684      ENCODE_SECTION_INFO was first called.  Remove the '@'.*/
4685   else if (symbol_str[0] == SDATA_NAME_FLAG_CHAR)
4686     {
4687       XSTR (XEXP (DECL_RTL (decl), 0), 0)
4688         = ggc_alloc_string (symbol_str + 1, -1);
4689     }
4690 }
4691 \f
4692 /* Output assmebly directives for prologue regions.  */
4693
4694 /* This function processes a SET pattern looking for specific patterns
4695    which result in emitting an assembly directive required for unwinding.  */
4696
4697 static int
4698 process_set (asm_out_file, pat)
4699      FILE *asm_out_file;
4700      rtx pat;
4701 {
4702   rtx src = SET_SRC (pat);
4703   rtx dest = SET_DEST (pat);
4704   int src_regno, dest_regno;
4705
4706   /* Look for the ALLOC insn.  */
4707   if (GET_CODE (src) == UNSPEC_VOLATILE
4708       && XINT (src, 1) == 0
4709       && GET_CODE (dest) == REG)
4710     {
4711       dest_regno = REGNO (dest);
4712
4713       /* If this isn't the final destination for ar.pfs, the alloc
4714          shouldn't have been marked frame related.  */
4715       if (dest_regno != current_frame_info.reg_save_ar_pfs)
4716         abort ();
4717
4718       fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
4719                ia64_dbx_register_number (dest_regno));
4720       return 1;
4721     }
4722
4723   /* Look for SP = .... */
4724   if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
4725     {
4726       if (GET_CODE (src) == PLUS)
4727         {
4728           rtx op0 = XEXP (src, 0);
4729           rtx op1 = XEXP (src, 1);
4730           if (op0 == dest && GET_CODE (op1) == CONST_INT)
4731             {
4732               if (INTVAL (op1) < 0)
4733                 {
4734                   fputs ("\t.fframe ", asm_out_file);
4735                   fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC,
4736                            -INTVAL (op1));
4737                   fputc ('\n', asm_out_file);
4738                 }
4739               else
4740                 fprintf (asm_out_file, "\t.restore sp\n");
4741             }
4742           else
4743             abort ();
4744         }
4745       else if (GET_CODE (src) == REG
4746                && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
4747         fprintf (asm_out_file, "\t.restore sp\n");
4748       else
4749         abort ();
4750
4751       return 1;
4752     }
4753
4754   /* Register move we need to look at.  */
4755   if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
4756     {
4757       src_regno = REGNO (src);
4758       dest_regno = REGNO (dest);
4759
4760       switch (src_regno)
4761         {
4762         case BR_REG (0):
4763           /* Saving return address pointer.  */
4764           if (dest_regno != current_frame_info.reg_save_b0)
4765             abort ();
4766           fprintf (asm_out_file, "\t.save rp, r%d\n",
4767                    ia64_dbx_register_number (dest_regno));
4768           return 1;
4769
4770         case PR_REG (0):
4771           if (dest_regno != current_frame_info.reg_save_pr)
4772             abort ();
4773           fprintf (asm_out_file, "\t.save pr, r%d\n",
4774                    ia64_dbx_register_number (dest_regno));
4775           return 1;
4776
4777         case AR_UNAT_REGNUM:
4778           if (dest_regno != current_frame_info.reg_save_ar_unat)
4779             abort ();
4780           fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
4781                    ia64_dbx_register_number (dest_regno));
4782           return 1;
4783
4784         case AR_LC_REGNUM:
4785           if (dest_regno != current_frame_info.reg_save_ar_lc)
4786             abort ();
4787           fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
4788                    ia64_dbx_register_number (dest_regno));
4789           return 1;
4790
4791         case STACK_POINTER_REGNUM:
4792           if (dest_regno != HARD_FRAME_POINTER_REGNUM
4793               || ! frame_pointer_needed)
4794             abort ();
4795           fprintf (asm_out_file, "\t.vframe r%d\n",
4796                    ia64_dbx_register_number (dest_regno));
4797           return 1;
4798
4799         default:
4800           /* Everything else should indicate being stored to memory.  */
4801           abort ();
4802         }
4803     }
4804
4805   /* Memory store we need to look at.  */
4806   if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
4807     {
4808       long off;
4809       rtx base;
4810       const char *saveop;
4811
4812       if (GET_CODE (XEXP (dest, 0)) == REG)
4813         {
4814           base = XEXP (dest, 0);
4815           off = 0;
4816         }
4817       else if (GET_CODE (XEXP (dest, 0)) == PLUS
4818                && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT)
4819         {
4820           base = XEXP (XEXP (dest, 0), 0);
4821           off = INTVAL (XEXP (XEXP (dest, 0), 1));
4822         }
4823       else
4824         abort ();
4825
4826       if (base == hard_frame_pointer_rtx)
4827         {
4828           saveop = ".savepsp";
4829           off = - off;
4830         }
4831       else if (base == stack_pointer_rtx)
4832         saveop = ".savesp";
4833       else
4834         abort ();
4835
4836       src_regno = REGNO (src);
4837       switch (src_regno)
4838         {
4839         case BR_REG (0):
4840           if (current_frame_info.reg_save_b0 != 0)
4841             abort ();
4842           fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
4843           return 1;
4844
4845         case PR_REG (0):
4846           if (current_frame_info.reg_save_pr != 0)
4847             abort ();
4848           fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
4849           return 1;
4850
4851         case AR_LC_REGNUM:
4852           if (current_frame_info.reg_save_ar_lc != 0)
4853             abort ();
4854           fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
4855           return 1;
4856
4857         case AR_PFS_REGNUM:
4858           if (current_frame_info.reg_save_ar_pfs != 0)
4859             abort ();
4860           fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
4861           return 1;
4862
4863         case AR_UNAT_REGNUM:
4864           if (current_frame_info.reg_save_ar_unat != 0)
4865             abort ();
4866           fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
4867           return 1;
4868
4869         case GR_REG (4):
4870         case GR_REG (5):
4871         case GR_REG (6):
4872         case GR_REG (7):
4873           fprintf (asm_out_file, "\t.save.g 0x%x\n",
4874                    1 << (src_regno - GR_REG (4)));
4875           return 1;
4876
4877         case BR_REG (1):
4878         case BR_REG (2):
4879         case BR_REG (3):
4880         case BR_REG (4):
4881         case BR_REG (5):
4882           fprintf (asm_out_file, "\t.save.b 0x%x\n",
4883                    1 << (src_regno - BR_REG (1)));
4884           return 1;
4885
4886         case FR_REG (2):
4887         case FR_REG (3):
4888         case FR_REG (4):
4889         case FR_REG (5):
4890           fprintf (asm_out_file, "\t.save.f 0x%x\n",
4891                    1 << (src_regno - FR_REG (2)));
4892           return 1;
4893
4894         case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
4895         case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
4896         case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
4897         case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
4898           fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
4899                    1 << (src_regno - FR_REG (12)));
4900           return 1;
4901
4902         default:
4903           return 0;
4904         }
4905     }
4906
4907   return 0;
4908 }
4909
4910
4911 /* This function looks at a single insn and emits any directives
4912    required to unwind this insn.  */
4913 void
4914 process_for_unwind_directive (asm_out_file, insn)
4915      FILE *asm_out_file;
4916      rtx insn;
4917 {
4918   if ((flag_unwind_tables
4919        || (flag_exceptions && !exceptions_via_longjmp))
4920       && RTX_FRAME_RELATED_P (insn))
4921     {
4922       rtx pat;
4923
4924       pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
4925       if (pat)
4926         pat = XEXP (pat, 0);
4927       else
4928         pat = PATTERN (insn);
4929
4930       switch (GET_CODE (pat))
4931         {
4932         case SET:
4933           process_set (asm_out_file, pat);
4934           break;
4935
4936         case PARALLEL:
4937           {
4938             int par_index;
4939             int limit = XVECLEN (pat, 0);
4940             for (par_index = 0; par_index < limit; par_index++)
4941               {
4942                 rtx x = XVECEXP (pat, 0, par_index);
4943                 if (GET_CODE (x) == SET)
4944                   process_set (asm_out_file, x);
4945               }
4946             break;
4947           }
4948
4949         default:
4950           abort ();
4951         }
4952     }
4953 }
4954
4955 \f
4956 void
4957 ia64_init_builtins ()
4958 {
4959   tree psi_type_node = build_pointer_type (integer_type_node);
4960   tree pdi_type_node = build_pointer_type (long_integer_type_node);
4961   tree endlink = tree_cons (NULL_TREE, void_type_node, NULL_TREE);
4962
4963   /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
4964   tree si_ftype_psi_si_si
4965     = build_function_type (integer_type_node,
4966                            tree_cons (NULL_TREE, psi_type_node,
4967                                       tree_cons (NULL_TREE, integer_type_node,
4968                                                  tree_cons (NULL_TREE,
4969                                                             integer_type_node,
4970                                                             endlink))));
4971
4972   /* __sync_val_compare_and_swap_di, __sync_bool_compare_and_swap_di */
4973   tree di_ftype_pdi_di_di
4974     = build_function_type (long_integer_type_node,
4975                            tree_cons (NULL_TREE, pdi_type_node,
4976                                       tree_cons (NULL_TREE,
4977                                                  long_integer_type_node,
4978                                                  tree_cons (NULL_TREE,
4979                                                         long_integer_type_node,
4980                                                         endlink))));
4981   /* __sync_synchronize */
4982   tree void_ftype_void
4983     = build_function_type (void_type_node, endlink);
4984
4985   /* __sync_lock_test_and_set_si */
4986   tree si_ftype_psi_si
4987     = build_function_type (integer_type_node,
4988                            tree_cons (NULL_TREE, psi_type_node,
4989                            tree_cons (NULL_TREE, integer_type_node, endlink)));
4990
4991   /* __sync_lock_test_and_set_di */
4992   tree di_ftype_pdi_di
4993     = build_function_type (long_integer_type_node,
4994                            tree_cons (NULL_TREE, pdi_type_node,
4995                            tree_cons (NULL_TREE, long_integer_type_node,
4996                                       endlink)));
4997
4998   /* __sync_lock_release_si */
4999   tree void_ftype_psi
5000     = build_function_type (void_type_node, tree_cons (NULL_TREE, psi_type_node,
5001                                                       endlink));
5002
5003   /* __sync_lock_release_di */
5004   tree void_ftype_pdi
5005     = build_function_type (void_type_node, tree_cons (NULL_TREE, pdi_type_node,
5006                                                       endlink));
5007
5008 #define def_builtin(name, type, code) \
5009   builtin_function ((name), (type), (code), BUILT_IN_MD, NULL_PTR)
5010
5011   def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si,
5012                IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI);
5013   def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di,
5014                IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI);
5015   def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si,
5016                IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI);
5017   def_builtin ("__sync_bool_compare_and_swap_di", di_ftype_pdi_di_di,
5018                IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI);
5019
5020   def_builtin ("__sync_synchronize", void_ftype_void,
5021                IA64_BUILTIN_SYNCHRONIZE);
5022
5023   def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si,
5024                IA64_BUILTIN_LOCK_TEST_AND_SET_SI);
5025   def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di,
5026                IA64_BUILTIN_LOCK_TEST_AND_SET_DI);
5027   def_builtin ("__sync_lock_release_si", void_ftype_psi,
5028                IA64_BUILTIN_LOCK_RELEASE_SI);
5029   def_builtin ("__sync_lock_release_di", void_ftype_pdi,
5030                IA64_BUILTIN_LOCK_RELEASE_DI);
5031
5032   def_builtin ("__builtin_ia64_bsp",
5033                build_function_type (ptr_type_node, endlink),
5034                IA64_BUILTIN_BSP);
5035
5036   def_builtin ("__builtin_ia64_flushrs",
5037                build_function_type (void_type_node, endlink),
5038                IA64_BUILTIN_FLUSHRS);
5039
5040   def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
5041                IA64_BUILTIN_FETCH_AND_ADD_SI);
5042   def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si,
5043                IA64_BUILTIN_FETCH_AND_SUB_SI);
5044   def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si,
5045                IA64_BUILTIN_FETCH_AND_OR_SI);
5046   def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si,
5047                IA64_BUILTIN_FETCH_AND_AND_SI);
5048   def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si,
5049                IA64_BUILTIN_FETCH_AND_XOR_SI);
5050   def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si,
5051                IA64_BUILTIN_FETCH_AND_NAND_SI);
5052
5053   def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si,
5054                IA64_BUILTIN_ADD_AND_FETCH_SI);
5055   def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si,
5056                IA64_BUILTIN_SUB_AND_FETCH_SI);
5057   def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si,
5058                IA64_BUILTIN_OR_AND_FETCH_SI);
5059   def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si,
5060                IA64_BUILTIN_AND_AND_FETCH_SI);
5061   def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si,
5062                IA64_BUILTIN_XOR_AND_FETCH_SI);
5063   def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si,
5064                IA64_BUILTIN_NAND_AND_FETCH_SI);
5065
5066   def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di,
5067                IA64_BUILTIN_FETCH_AND_ADD_DI);
5068   def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di,
5069                IA64_BUILTIN_FETCH_AND_SUB_DI);
5070   def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di,
5071                IA64_BUILTIN_FETCH_AND_OR_DI);
5072   def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di,
5073                IA64_BUILTIN_FETCH_AND_AND_DI);
5074   def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di,
5075                IA64_BUILTIN_FETCH_AND_XOR_DI);
5076   def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di,
5077                IA64_BUILTIN_FETCH_AND_NAND_DI);
5078
5079   def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di,
5080                IA64_BUILTIN_ADD_AND_FETCH_DI);
5081   def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di,
5082                IA64_BUILTIN_SUB_AND_FETCH_DI);
5083   def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di,
5084                IA64_BUILTIN_OR_AND_FETCH_DI);
5085   def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di,
5086                IA64_BUILTIN_AND_AND_FETCH_DI);
5087   def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di,
5088                IA64_BUILTIN_XOR_AND_FETCH_DI);
5089   def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di,
5090                IA64_BUILTIN_NAND_AND_FETCH_DI);
5091
5092 #undef def_builtin
5093 }
5094
5095 /* Expand fetch_and_op intrinsics.  The basic code sequence is:
5096
5097      mf
5098      tmp = [ptr];
5099      do {
5100        ret = tmp;
5101        ar.ccv = tmp;
5102        tmp <op>= value;
5103        cmpxchgsz.acq tmp = [ptr], tmp
5104      } while (tmp != ret)
5105 */
5106
5107 static rtx
5108 ia64_expand_fetch_and_op (binoptab, mode, arglist, target)
5109      optab binoptab;
5110      enum machine_mode mode;
5111      tree arglist;
5112      rtx target;
5113 {
5114   rtx ret, label, tmp, ccv, insn, mem, value;
5115   tree arg0, arg1;
5116
5117   arg0 = TREE_VALUE (arglist);
5118   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5119   mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
5120   value = expand_expr (arg1, NULL_RTX, mode, 0);
5121
5122   mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
5123   MEM_VOLATILE_P (mem) = 1;
5124
5125   if (target && register_operand (target, mode))
5126     ret = target;
5127   else
5128     ret = gen_reg_rtx (mode);
5129
5130   emit_insn (gen_mf ());
5131
5132   /* Special case for fetchadd instructions.  */
5133   if (binoptab == add_optab && fetchadd_operand (value, VOIDmode))
5134     {
5135       if (mode == SImode)
5136         insn = gen_fetchadd_acq_si (ret, mem, value);
5137       else
5138         insn = gen_fetchadd_acq_di (ret, mem, value);
5139       emit_insn (insn);
5140       return ret;
5141     }
5142
5143   tmp = gen_reg_rtx (mode);
5144   ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
5145   emit_move_insn (tmp, mem);
5146
5147   label = gen_label_rtx ();
5148   emit_label (label);
5149   emit_move_insn (ret, tmp);
5150   emit_move_insn (ccv, tmp);
5151
5152   /* Perform the specific operation.  Special case NAND by noticing
5153      one_cmpl_optab instead.  */
5154   if (binoptab == one_cmpl_optab)
5155     {
5156       tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
5157       binoptab = and_optab;
5158     }
5159   tmp = expand_binop (mode, binoptab, tmp, value, tmp, 1, OPTAB_WIDEN);
5160
5161   if (mode == SImode)
5162     insn = gen_cmpxchg_acq_si (tmp, mem, tmp, ccv);
5163   else
5164     insn = gen_cmpxchg_acq_di (tmp, mem, tmp, ccv);
5165   emit_insn (insn);
5166
5167   emit_cmp_and_jump_insns (tmp, ret, NE, 0, mode, 1, 0, label);
5168
5169   return ret;
5170 }
5171
5172 /* Expand op_and_fetch intrinsics.  The basic code sequence is:
5173
5174      mf
5175      tmp = [ptr];
5176      do {
5177        old = tmp;
5178        ar.ccv = tmp;
5179        ret = tmp + value;
5180        cmpxchgsz.acq tmp = [ptr], ret
5181      } while (tmp != old)
5182 */
5183
5184 static rtx
5185 ia64_expand_op_and_fetch (binoptab, mode, arglist, target)
5186      optab binoptab;
5187      enum machine_mode mode;
5188      tree arglist;
5189      rtx target;
5190 {
5191   rtx old, label, tmp, ret, ccv, insn, mem, value;
5192   tree arg0, arg1;
5193
5194   arg0 = TREE_VALUE (arglist);
5195   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5196   mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
5197   value = expand_expr (arg1, NULL_RTX, mode, 0);
5198
5199   mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
5200   MEM_VOLATILE_P (mem) = 1;
5201
5202   if (target && ! register_operand (target, mode))
5203     target = NULL_RTX;
5204
5205   emit_insn (gen_mf ());
5206   tmp = gen_reg_rtx (mode);
5207   old = gen_reg_rtx (mode);
5208   ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
5209
5210   emit_move_insn (tmp, mem);
5211
5212   label = gen_label_rtx ();
5213   emit_label (label);
5214   emit_move_insn (old, tmp);
5215   emit_move_insn (ccv, tmp);
5216
5217   /* Perform the specific operation.  Special case NAND by noticing
5218      one_cmpl_optab instead.  */
5219   if (binoptab == one_cmpl_optab)
5220     {
5221       tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
5222       binoptab = and_optab;
5223     }
5224   ret = expand_binop (mode, binoptab, tmp, value, target, 1, OPTAB_WIDEN);
5225
5226   if (mode == SImode)
5227     insn = gen_cmpxchg_acq_si (tmp, mem, ret, ccv);
5228   else
5229     insn = gen_cmpxchg_acq_di (tmp, mem, ret, ccv);
5230   emit_insn (insn);
5231
5232   emit_cmp_and_jump_insns (tmp, old, NE, 0, mode, 1, 0, label);
5233
5234   return ret;
5235 }
5236
5237 /* Expand val_ and bool_compare_and_swap.  For val_ we want:
5238
5239      ar.ccv = oldval
5240      mf
5241      cmpxchgsz.acq ret = [ptr], newval, ar.ccv
5242      return ret
5243
5244    For bool_ it's the same except return ret == oldval.
5245 */
5246
5247 static rtx
5248 ia64_expand_compare_and_swap (mode, boolp, arglist, target)
5249      enum machine_mode mode;
5250      int boolp;
5251      tree arglist;
5252      rtx target;
5253 {
5254   tree arg0, arg1, arg2;
5255   rtx mem, old, new, ccv, tmp, insn;
5256
5257   arg0 = TREE_VALUE (arglist);
5258   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5259   arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5260   mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
5261   old = expand_expr (arg1, NULL_RTX, mode, 0);
5262   new = expand_expr (arg2, NULL_RTX, mode, 0);
5263
5264   mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
5265   MEM_VOLATILE_P (mem) = 1;
5266
5267   if (! register_operand (old, mode))
5268     old = copy_to_mode_reg (mode, old);
5269   if (! register_operand (new, mode))
5270     new = copy_to_mode_reg (mode, new);
5271
5272   if (! boolp && target && register_operand (target, mode))
5273     tmp = target;
5274   else
5275     tmp = gen_reg_rtx (mode);
5276
5277   ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
5278   emit_move_insn (ccv, old);
5279   emit_insn (gen_mf ());
5280   if (mode == SImode)
5281     insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);
5282   else
5283     insn = gen_cmpxchg_acq_di (tmp, mem, new, ccv);
5284   emit_insn (insn);
5285
5286   if (boolp)
5287     {
5288       if (! target)
5289         target = gen_reg_rtx (mode);
5290       return emit_store_flag_force (target, EQ, tmp, old, mode, 1, 1);
5291     }
5292   else
5293     return tmp;
5294 }
5295
5296 /* Expand lock_test_and_set.  I.e. `xchgsz ret = [ptr], new'.  */
5297
5298 static rtx
5299 ia64_expand_lock_test_and_set (mode, arglist, target)
5300      enum machine_mode mode;
5301      tree arglist;
5302      rtx target;
5303 {
5304   tree arg0, arg1;
5305   rtx mem, new, ret, insn;
5306
5307   arg0 = TREE_VALUE (arglist);
5308   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5309   mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
5310   new = expand_expr (arg1, NULL_RTX, mode, 0);
5311
5312   mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
5313   MEM_VOLATILE_P (mem) = 1;
5314   if (! register_operand (new, mode))
5315     new = copy_to_mode_reg (mode, new);
5316
5317   if (target && register_operand (target, mode))
5318     ret = target;
5319   else
5320     ret = gen_reg_rtx (mode);
5321
5322   if (mode == SImode)
5323     insn = gen_xchgsi (ret, mem, new);
5324   else
5325     insn = gen_xchgdi (ret, mem, new);
5326   emit_insn (insn);
5327
5328   return ret;
5329 }
5330
5331 /* Expand lock_release.  I.e. `stsz.rel [ptr] = r0'.  */
5332
5333 static rtx
5334 ia64_expand_lock_release (mode, arglist, target)
5335      enum machine_mode mode;
5336      tree arglist;
5337      rtx target ATTRIBUTE_UNUSED;
5338 {
5339   tree arg0;
5340   rtx mem;
5341
5342   arg0 = TREE_VALUE (arglist);
5343   mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
5344
5345   mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
5346   MEM_VOLATILE_P (mem) = 1;
5347
5348   emit_move_insn (mem, const0_rtx);
5349
5350   return const0_rtx;
5351 }
5352
5353 rtx
5354 ia64_expand_builtin (exp, target, subtarget, mode, ignore)
5355      tree exp;
5356      rtx target;
5357      rtx subtarget ATTRIBUTE_UNUSED;
5358      enum machine_mode mode ATTRIBUTE_UNUSED;
5359      int ignore ATTRIBUTE_UNUSED;
5360 {
5361   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5362   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5363   tree arglist = TREE_OPERAND (exp, 1);
5364
5365   switch (fcode)
5366     {
5367     case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
5368     case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
5369     case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
5370     case IA64_BUILTIN_LOCK_RELEASE_SI:
5371     case IA64_BUILTIN_FETCH_AND_ADD_SI:
5372     case IA64_BUILTIN_FETCH_AND_SUB_SI:
5373     case IA64_BUILTIN_FETCH_AND_OR_SI:
5374     case IA64_BUILTIN_FETCH_AND_AND_SI:
5375     case IA64_BUILTIN_FETCH_AND_XOR_SI:
5376     case IA64_BUILTIN_FETCH_AND_NAND_SI:
5377     case IA64_BUILTIN_ADD_AND_FETCH_SI:
5378     case IA64_BUILTIN_SUB_AND_FETCH_SI:
5379     case IA64_BUILTIN_OR_AND_FETCH_SI:
5380     case IA64_BUILTIN_AND_AND_FETCH_SI:
5381     case IA64_BUILTIN_XOR_AND_FETCH_SI:
5382     case IA64_BUILTIN_NAND_AND_FETCH_SI:
5383       mode = SImode;
5384       break;
5385
5386     case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
5387     case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
5388     case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
5389     case IA64_BUILTIN_LOCK_RELEASE_DI:
5390     case IA64_BUILTIN_FETCH_AND_ADD_DI:
5391     case IA64_BUILTIN_FETCH_AND_SUB_DI:
5392     case IA64_BUILTIN_FETCH_AND_OR_DI:
5393     case IA64_BUILTIN_FETCH_AND_AND_DI:
5394     case IA64_BUILTIN_FETCH_AND_XOR_DI:
5395     case IA64_BUILTIN_FETCH_AND_NAND_DI:
5396     case IA64_BUILTIN_ADD_AND_FETCH_DI:
5397     case IA64_BUILTIN_SUB_AND_FETCH_DI:
5398     case IA64_BUILTIN_OR_AND_FETCH_DI:
5399     case IA64_BUILTIN_AND_AND_FETCH_DI:
5400     case IA64_BUILTIN_XOR_AND_FETCH_DI:
5401     case IA64_BUILTIN_NAND_AND_FETCH_DI:
5402       mode = DImode;
5403       break;
5404
5405     default:
5406       break;
5407     }
5408
5409   switch (fcode)
5410     {
5411     case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
5412     case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
5413       return ia64_expand_compare_and_swap (mode, 1, arglist, target);
5414
5415     case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
5416     case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
5417       return ia64_expand_compare_and_swap (mode, 0, arglist, target);
5418
5419     case IA64_BUILTIN_SYNCHRONIZE:
5420       emit_insn (gen_mf ());
5421       return const0_rtx;
5422
5423     case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
5424     case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
5425       return ia64_expand_lock_test_and_set (mode, arglist, target);
5426
5427     case IA64_BUILTIN_LOCK_RELEASE_SI:
5428     case IA64_BUILTIN_LOCK_RELEASE_DI:
5429       return ia64_expand_lock_release (mode, arglist, target);
5430
5431     case IA64_BUILTIN_BSP:
5432       if (! target || ! register_operand (target, DImode))
5433         target = gen_reg_rtx (DImode);
5434       emit_insn (gen_bsp_value (target));
5435       return target;
5436
5437     case IA64_BUILTIN_FLUSHRS:
5438       emit_insn (gen_flushrs ());
5439       return const0_rtx;
5440
5441     case IA64_BUILTIN_FETCH_AND_ADD_SI:
5442     case IA64_BUILTIN_FETCH_AND_ADD_DI:
5443       return ia64_expand_fetch_and_op (add_optab, mode, arglist, target);
5444
5445     case IA64_BUILTIN_FETCH_AND_SUB_SI:
5446     case IA64_BUILTIN_FETCH_AND_SUB_DI:
5447       return ia64_expand_fetch_and_op (sub_optab, mode, arglist, target);
5448
5449     case IA64_BUILTIN_FETCH_AND_OR_SI:
5450     case IA64_BUILTIN_FETCH_AND_OR_DI:
5451       return ia64_expand_fetch_and_op (ior_optab, mode, arglist, target);
5452
5453     case IA64_BUILTIN_FETCH_AND_AND_SI:
5454     case IA64_BUILTIN_FETCH_AND_AND_DI:
5455       return ia64_expand_fetch_and_op (and_optab, mode, arglist, target);
5456
5457     case IA64_BUILTIN_FETCH_AND_XOR_SI:
5458     case IA64_BUILTIN_FETCH_AND_XOR_DI:
5459       return ia64_expand_fetch_and_op (xor_optab, mode, arglist, target);
5460
5461     case IA64_BUILTIN_FETCH_AND_NAND_SI:
5462     case IA64_BUILTIN_FETCH_AND_NAND_DI:
5463       return ia64_expand_fetch_and_op (one_cmpl_optab, mode, arglist, target);
5464
5465     case IA64_BUILTIN_ADD_AND_FETCH_SI:
5466     case IA64_BUILTIN_ADD_AND_FETCH_DI:
5467       return ia64_expand_op_and_fetch (add_optab, mode, arglist, target);
5468
5469     case IA64_BUILTIN_SUB_AND_FETCH_SI:
5470     case IA64_BUILTIN_SUB_AND_FETCH_DI:
5471       return ia64_expand_op_and_fetch (sub_optab, mode, arglist, target);
5472
5473     case IA64_BUILTIN_OR_AND_FETCH_SI:
5474     case IA64_BUILTIN_OR_AND_FETCH_DI:
5475       return ia64_expand_op_and_fetch (ior_optab, mode, arglist, target);
5476
5477     case IA64_BUILTIN_AND_AND_FETCH_SI:
5478     case IA64_BUILTIN_AND_AND_FETCH_DI:
5479       return ia64_expand_op_and_fetch (and_optab, mode, arglist, target);
5480
5481     case IA64_BUILTIN_XOR_AND_FETCH_SI:
5482     case IA64_BUILTIN_XOR_AND_FETCH_DI:
5483       return ia64_expand_op_and_fetch (xor_optab, mode, arglist, target);
5484
5485     case IA64_BUILTIN_NAND_AND_FETCH_SI:
5486     case IA64_BUILTIN_NAND_AND_FETCH_DI:
5487       return ia64_expand_op_and_fetch (one_cmpl_optab, mode, arglist, target);
5488
5489     default:
5490       break;
5491     }
5492
5493   return NULL_RTX;
5494 }