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* config/i386/i386.md (mmx_pinsrw): Output operands in correct
[official-gcc.git] / gcc / config / arm / arm.h
blob3078a03f49f3692849e3639b1c8cbbb0a644e431
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #ifndef __ARM_H__
26 #define __ARM_H__
27
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify. */
52 #define TARGET_CPU_generic 0x8000
53
54 typedef enum arm_cond_code
55 {
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
58 }
59 arm_cc;
60
61 extern arm_cc arm_current_cc;
62 extern const char * arm_condition_codes[];
63
64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
65
66 extern int arm_target_label;
67 extern int arm_ccfsm_state;
68 extern struct rtx_def * arm_target_insn;
69 /* Run-time compilation parameters selecting different hardware subsets. */
70 extern int target_flags;
71 /* The floating point instruction architecture, can be 2 or 3 */
72 extern const char * target_fp_name;
73 /* Define the information needed to generate branch insns. This is
74 stored from the compare operation. Note that we can't use "rtx" here
75 since it hasn't been defined! */
76 extern struct rtx_def * arm_compare_op0;
77 extern struct rtx_def * arm_compare_op1;
78 /* The label of the current constant pool. */
79 extern struct rtx_def * pool_vector_label;
80 /* Set to 1 when a return insn is output, this means that the epilogue
81 is not needed. */
82 extern int return_used_this_function;
83 /* Nonzero if the prologue must setup `fp'. */
84 extern int current_function_anonymous_args;
85 \f
86 /* Just in case configure has failed to define anything. */
87 #ifndef TARGET_CPU_DEFAULT
88 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
89 #endif
90
91 /* If the configuration file doesn't specify the cpu, the subtarget may
92 override it. If it doesn't, then default to an ARM6. */
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
94 #undef TARGET_CPU_DEFAULT
95 #ifdef SUBTARGET_CPU_DEFAULT
96 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
97 #else
98 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
99 #endif
100 #endif
101
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
107 #else
108 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
109 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
110 #else
111 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
112 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
113 #else
114 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
115 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
116 #else
117 Unrecognized value in TARGET_CPU_DEFAULT.
118 #endif
119 #endif
120 #endif
121 #endif
122 #endif
123
124 #ifndef CPP_PREDEFINES
125 #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
126 #endif
127
128 #define CPP_SPEC "\
129 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
130 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
131
132 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
133
134 /* Set the architecture define -- if -march= is set, then it overrides
135 the -mcpu= setting. */
136 #define CPP_CPU_ARCH_SPEC "\
137 %{march=arm2:-D__ARM_ARCH_2__} \
138 %{march=arm250:-D__ARM_ARCH_2__} \
139 %{march=arm3:-D__ARM_ARCH_2__} \
140 %{march=arm6:-D__ARM_ARCH_3__} \
141 %{march=arm600:-D__ARM_ARCH_3__} \
142 %{march=arm610:-D__ARM_ARCH_3__} \
143 %{march=arm7:-D__ARM_ARCH_3__} \
144 %{march=arm700:-D__ARM_ARCH_3__} \
145 %{march=arm710:-D__ARM_ARCH_3__} \
146 %{march=arm720:-D__ARM_ARCH_3__} \
147 %{march=arm7100:-D__ARM_ARCH_3__} \
148 %{march=arm7500:-D__ARM_ARCH_3__} \
149 %{march=arm7500fe:-D__ARM_ARCH_3__} \
150 %{march=arm7m:-D__ARM_ARCH_3M__} \
151 %{march=arm7dm:-D__ARM_ARCH_3M__} \
152 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
153 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
154 %{march=arm8:-D__ARM_ARCH_4__} \
155 %{march=arm810:-D__ARM_ARCH_4__} \
156 %{march=arm9:-D__ARM_ARCH_4T__} \
157 %{march=arm920:-D__ARM_ARCH_4__} \
158 %{march=arm920t:-D__ARM_ARCH_4T__} \
159 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
160 %{march=strongarm:-D__ARM_ARCH_4__} \
161 %{march=strongarm110:-D__ARM_ARCH_4__} \
162 %{march=strongarm1100:-D__ARM_ARCH_4__} \
163 %{march=armv2:-D__ARM_ARCH_2__} \
164 %{march=armv2a:-D__ARM_ARCH_2__} \
165 %{march=armv3:-D__ARM_ARCH_3__} \
166 %{march=armv3m:-D__ARM_ARCH_3M__} \
167 %{march=armv4:-D__ARM_ARCH_4__} \
168 %{march=armv4t:-D__ARM_ARCH_4T__} \
169 %{march=armv5:-D__ARM_ARCH_5__} \
170 %{march=armv5t:-D__ARM_ARCH_5T__} \
171 %{march=armv5e:-D__ARM_ARCH_5E__} \
172 %{march=armv5te:-D__ARM_ARCH_5TE__} \
173 %{!march=*: \
174 %{mcpu=arm2:-D__ARM_ARCH_2__} \
175 %{mcpu=arm250:-D__ARM_ARCH_2__} \
176 %{mcpu=arm3:-D__ARM_ARCH_2__} \
177 %{mcpu=arm6:-D__ARM_ARCH_3__} \
178 %{mcpu=arm600:-D__ARM_ARCH_3__} \
179 %{mcpu=arm610:-D__ARM_ARCH_3__} \
180 %{mcpu=arm7:-D__ARM_ARCH_3__} \
181 %{mcpu=arm700:-D__ARM_ARCH_3__} \
182 %{mcpu=arm710:-D__ARM_ARCH_3__} \
183 %{mcpu=arm720:-D__ARM_ARCH_3__} \
184 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
185 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
186 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
187 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
188 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
189 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
190 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
191 %{mcpu=arm8:-D__ARM_ARCH_4__} \
192 %{mcpu=arm810:-D__ARM_ARCH_4__} \
193 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
194 %{mcpu=arm920:-D__ARM_ARCH_4__} \
195 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
196 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
197 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
198 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
199 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
200 %{!mcpu*:%(cpp_cpu_arch_default)}} \
201 "
202
203 /* Define __APCS_26__ if the PC also contains the PSR */
204 #define CPP_APCS_PC_SPEC "\
205 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
206 -D__APCS_32__} \
207 %{mapcs-26:-D__APCS_26__} \
208 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
209 "
210
211 #ifndef CPP_APCS_PC_DEFAULT_SPEC
212 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
213 #endif
214
215 #define CPP_FLOAT_SPEC "\
216 %{msoft-float:\
217 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
218 -D__SOFTFP__} \
219 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
220 "
221
222 /* Default is hard float, which doesn't define anything */
223 #define CPP_FLOAT_DEFAULT_SPEC ""
224
225 #define CPP_ENDIAN_SPEC "\
226 %{mbig-endian: \
227 %{mlittle-endian: \
228 %e-mbig-endian and -mlittle-endian may not be used together} \
229 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
230 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
231 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
232 "
233
234 /* Default is little endian. */
235 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
236
237 /* Add a define for interworking. Needed when building libgcc.a.
238 This must define __THUMB_INTERWORK__ to the pre-processor if
239 interworking is enabled by default. */
240 #ifndef CPP_INTERWORK_DEFAULT_SPEC
241 #define CPP_INTERWORK_DEFAULT_SPEC ""
242 #endif
243
244 #define CPP_INTERWORK_SPEC " \
245 %{mthumb-interwork: \
246 %{mno-thumb-interwork: %eIncompatible interworking options} \
247 -D__THUMB_INTERWORK__} \
248 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
249 "
250
251 #define CC1_SPEC ""
252
253 /* This macro defines names of additional specifications to put in the specs
254 that can be used in various specifications like CC1_SPEC. Its definition
255 is an initializer with a subgrouping for each command option.
256
257 Each subgrouping contains a string constant, that defines the
258 specification name, and a string constant that used by the GNU CC driver
259 program.
260
261 Do not define this macro if it does not need to do anything. */
262 #define EXTRA_SPECS \
263 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
264 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
265 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
266 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
267 { "cpp_float", CPP_FLOAT_SPEC }, \
268 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
269 { "cpp_endian", CPP_ENDIAN_SPEC }, \
270 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
271 { "cpp_isa", CPP_ISA_SPEC }, \
272 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
273 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
274 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
275 SUBTARGET_EXTRA_SPECS
276
277 #ifndef SUBTARGET_EXTRA_SPECS
278 #define SUBTARGET_EXTRA_SPECS
279 #endif
280
281 #ifndef SUBTARGET_CPP_SPEC
282 #define SUBTARGET_CPP_SPEC ""
283 #endif
284 \f
285 /* Run-time Target Specification. */
286 #ifndef TARGET_VERSION
287 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
288 #endif
289
290 /* Nonzero if the function prologue (and epilogue) should obey
291 the ARM Procedure Call Standard. */
292 #define ARM_FLAG_APCS_FRAME (1 << 0)
293
294 /* Nonzero if the function prologue should output the function name to enable
295 the post mortem debugger to print a backtrace (very useful on RISCOS,
296 unused on RISCiX). Specifying this flag also enables
297 -fno-omit-frame-pointer.
298 XXX Must still be implemented in the prologue. */
299 #define ARM_FLAG_POKE (1 << 1)
300
301 /* Nonzero if floating point instructions are emulated by the FPE, in which
302 case instruction scheduling becomes very uninteresting. */
303 #define ARM_FLAG_FPE (1 << 2)
304
305 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
306 that assume restoration of the condition flags when returning from a
307 branch and link (ie a function). */
308 #define ARM_FLAG_APCS_32 (1 << 3)
309
310 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
311
312 /* Nonzero if stack checking should be performed on entry to each function
313 which allocates temporary variables on the stack. */
314 #define ARM_FLAG_APCS_STACK (1 << 4)
315
316 /* Nonzero if floating point parameters should be passed to functions in
317 floating point registers. */
318 #define ARM_FLAG_APCS_FLOAT (1 << 5)
319
320 /* Nonzero if re-entrant, position independent code should be generated.
321 This is equivalent to -fpic. */
322 #define ARM_FLAG_APCS_REENT (1 << 6)
323
324 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
325 be loaded using either LDRH or LDRB instructions. */
326 #define ARM_FLAG_MMU_TRAPS (1 << 7)
327
328 /* Nonzero if all floating point instructions are missing (and there is no
329 emulator either). Generate function calls for all ops in this case. */
330 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
331
332 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
333 #define ARM_FLAG_BIG_END (1 << 9)
334
335 /* Nonzero if we should compile for Thumb interworking. */
336 #define ARM_FLAG_INTERWORK (1 << 10)
337
338 /* Nonzero if we should have little-endian words even when compiling for
339 big-endian (for backwards compatibility with older versions of GCC). */
340 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
341
342 /* Nonzero if we need to protect the prolog from scheduling */
343 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
344
345 /* Nonzero if a call to abort should be generated if a noreturn
346 function tries to return. */
347 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
348
349 /* Nonzero if function prologues should not load the PIC register. */
350 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
351
352 /* Nonzero if all call instructions should be indirect. */
353 #define ARM_FLAG_LONG_CALLS (1 << 15)
354
355 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
356 #define ARM_FLAG_THUMB (1 << 16)
357
358 /* Set if a TPCS style stack frame should be generated, for non-leaf
359 functions, even if they do not need one. */
360 #define THUMB_FLAG_BACKTRACE (1 << 17)
361
362 /* Set if a TPCS style stack frame should be generated, for leaf
363 functions, even if they do not need one. */
364 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
365
366 /* Set if externally visible functions should assume that they
367 might be called in ARM mode, from a non-thumb aware code. */
368 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
369
370 /* Set if calls via function pointers should assume that their
371 destination is non-Thumb aware. */
372 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
373
374 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
375 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
376 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
377 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
378 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
379 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
380 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
381 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
382 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
383 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
384 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
385 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
386 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
387 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
388 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
389 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
390 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
391 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
392 #define TARGET_ARM (! TARGET_THUMB)
393 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
394 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
395 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
396 #define TARGET_BACKTRACE (leaf_function_p () \
397 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
398 : (target_flags & THUMB_FLAG_BACKTRACE))
399
400 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
401 Bit 31 is reserved. See riscix.h. */
402 #ifndef SUBTARGET_SWITCHES
403 #define SUBTARGET_SWITCHES
404 #endif
405
406 #define TARGET_SWITCHES \
407 { \
408 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
409 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
410 N_("Generate APCS conformant stack frames") }, \
411 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
412 {"poke-function-name", ARM_FLAG_POKE, \
413 N_("Store function names in object code") }, \
414 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
415 {"fpe", ARM_FLAG_FPE, "" }, \
416 {"apcs-32", ARM_FLAG_APCS_32, \
417 N_("Use the 32bit version of the APCS") }, \
418 {"apcs-26", -ARM_FLAG_APCS_32, \
419 N_("Use the 26bit version of the APCS") }, \
420 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
421 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
422 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
423 N_("Pass FP arguments in FP registers") }, \
424 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
425 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
426 N_("Generate re-entrant, PIC code") }, \
427 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
428 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
429 N_("The MMU will trap on unaligned accesses") }, \
430 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
431 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
432 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
433 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
434 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
435 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
436 N_("Use library calls to perform FP operations") }, \
437 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
438 N_("Use hardware floating point instructions") }, \
439 {"big-endian", ARM_FLAG_BIG_END, \
440 N_("Assume target CPU is configured as big endian") }, \
441 {"little-endian", -ARM_FLAG_BIG_END, \
442 N_("Assume target CPU is configured as little endian") }, \
443 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
444 N_("Assume big endian bytes, little endian words") }, \
445 {"thumb-interwork", ARM_FLAG_INTERWORK, \
446 N_("Support calls between THUMB and ARM instructions sets") }, \
447 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
448 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
449 N_("Generate a call to abort if a noreturn function returns")}, \
450 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
451 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
452 N_("Do not move instructions into a function's prologue") }, \
453 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
454 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
455 N_("Do not load the PIC register in function prologues") }, \
456 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
457 {"long-calls", ARM_FLAG_LONG_CALLS, \
458 N_("Generate call insns as indirect calls, if necessary") }, \
459 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
460 {"thumb", ARM_FLAG_THUMB, \
461 N_("Compile for the Thumb not the ARM") }, \
462 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
463 {"arm", -ARM_FLAG_THUMB, "" }, \
464 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
465 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
466 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
467 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
468 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
469 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
470 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
471 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
472 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
473 "" }, \
474 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
475 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
476 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
477 "" }, \
478 SUBTARGET_SWITCHES \
479 {"", TARGET_DEFAULT, "" } \
480 }
481
482 #define TARGET_OPTIONS \
483 { \
484 {"cpu=", & arm_select[0].string, \
485 N_("Specify the name of the target CPU") }, \
486 {"arch=", & arm_select[1].string, \
487 N_("Specify the name of the target architecture") }, \
488 {"tune=", & arm_select[2].string, "" }, \
489 {"fpe=", & target_fp_name, "" }, \
490 {"fp=", & target_fp_name, \
491 N_("Specify the version of the floating point emulator") }, \
492 {"structure-size-boundary=", & structure_size_string, \
493 N_("Specify the minimum bit alignment of structures") }, \
494 {"pic-register=", & arm_pic_register_string, \
495 N_("Specify the register to be used for PIC addressing") } \
496 }
497
498 struct arm_cpu_select
499 {
500 const char * string;
501 const char * name;
502 const struct processors * processors;
503 };
504
505 /* This is a magic array. If the user specifies a command line switch
506 which matches one of the entries in TARGET_OPTIONS then the corresponding
507 string pointer will be set to the value specified by the user. */
508 extern struct arm_cpu_select arm_select[];
509
510 enum prog_mode_type
511 {
512 prog_mode26,
513 prog_mode32
514 };
515
516 /* Recast the program mode class to be the prog_mode attribute */
517 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
518
519 extern enum prog_mode_type arm_prgmode;
520
521 /* What sort of floating point unit do we have? Hardware or software.
522 If software, is it issue 2 or issue 3? */
523 enum floating_point_type
524 {
525 FP_HARD,
526 FP_SOFT2,
527 FP_SOFT3
528 };
529
530 /* Recast the floating point class to be the floating point attribute. */
531 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
532
533 /* What type of floating point to tune for */
534 extern enum floating_point_type arm_fpu;
535
536 /* What type of floating point instructions are available */
537 extern enum floating_point_type arm_fpu_arch;
538
539 /* Default floating point architecture. Override in sub-target if
540 necessary. */
541 #define FP_DEFAULT FP_SOFT2
542
543 /* Nonzero if the processor has a fast multiply insn, and one that does
544 a 64-bit multiply of two 32-bit values. */
545 extern int arm_fast_multiply;
546
547 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
548 extern int arm_arch4;
549
550 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
551 extern int arm_arch5;
552
553 /* Nonzero if this chip can benefit from load scheduling. */
554 extern int arm_ld_sched;
555
556 /* Nonzero if generating thumb code. */
557 extern int thumb_code;
558
559 /* Nonzero if this chip is a StrongARM. */
560 extern int arm_is_strong;
561
562 /* Nonzero if this chip is a an ARM6 or an ARM7. */
563 extern int arm_is_6_or_7;
564
565 #ifndef TARGET_DEFAULT
566 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
567 #endif
568
569 /* The frame pointer register used in gcc has nothing to do with debugging;
570 that is controlled by the APCS-FRAME option. */
571 #define CAN_DEBUG_WITHOUT_FP
572
573 #define TARGET_MEM_FUNCTIONS 1
574
575 #define OVERRIDE_OPTIONS arm_override_options ()
576
577 /* Nonzero if PIC code requires explicit qualifiers to generate
578 PLT and GOT relocs rather than the assembler doing so implicitly.
579 Subtargets can override these if required. */
580 #ifndef NEED_GOT_RELOC
581 #define NEED_GOT_RELOC 0
582 #endif
583 #ifndef NEED_PLT_RELOC
584 #define NEED_PLT_RELOC 0
585 #endif
586
587 /* Nonzero if we need to refer to the GOT with a PC-relative
588 offset. In other words, generate
589
590 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
591
592 rather than
593
594 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
595
596 The default is true, which matches NetBSD. Subtargets can
597 override this if required. */
598 #ifndef GOT_PCREL
599 #define GOT_PCREL 1
600 #endif
601 \f
602 /* Target machine storage Layout. */
603
604
605 /* Define this macro if it is advisable to hold scalars in registers
606 in a wider mode than that declared by the program. In such cases,
607 the value is constrained to be within the bounds of the declared
608 type, but kept valid in the wider mode. The signedness of the
609 extension may differ from that of the type. */
610
611 /* It is far faster to zero extend chars than to sign extend them */
612
613 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
614 if (GET_MODE_CLASS (MODE) == MODE_INT \
615 && GET_MODE_SIZE (MODE) < 4) \
616 { \
617 if (MODE == QImode) \
618 UNSIGNEDP = 1; \
619 else if (MODE == HImode) \
620 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
621 (MODE) = SImode; \
622 }
623
624 /* Define this macro if the promotion described by `PROMOTE_MODE'
625 should also be done for outgoing function arguments. */
626 /* This is required to ensure that push insns always push a word. */
627 #define PROMOTE_FUNCTION_ARGS
628
629 /* Define for XFmode extended real floating point support.
630 This will automatically cause REAL_ARITHMETIC to be defined. */
631 /* For the ARM:
632 I think I have added all the code to make this work. Unfortunately,
633 early releases of the floating point emulation code on RISCiX used a
634 different format for extended precision numbers. On my RISCiX box there
635 is a bug somewhere which causes the machine to lock up when running enquire
636 with long doubles. There is the additional aspect that Norcroft C
637 treats long doubles as doubles and we ought to remain compatible.
638 Perhaps someone with an FPA coprocessor and not running RISCiX would like
639 to try this someday. */
640 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
641
642 /* Disable XFmode patterns in md file */
643 #define ENABLE_XF_PATTERNS 0
644
645 /* Define if you don't want extended real, but do want to use the
646 software floating point emulator for REAL_ARITHMETIC and
647 decimal <-> binary conversion. */
648 /* See comment above */
649 #define REAL_ARITHMETIC
650
651 /* Define this if most significant bit is lowest numbered
652 in instructions that operate on numbered bit-fields. */
653 #define BITS_BIG_ENDIAN 0
654
655 /* Define this if most significant byte of a word is the lowest numbered.
656 Most ARM processors are run in little endian mode, so that is the default.
657 If you want to have it run-time selectable, change the definition in a
658 cover file to be TARGET_BIG_ENDIAN. */
659 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
660
661 /* Define this if most significant word of a multiword number is the lowest
662 numbered.
663 This is always false, even when in big-endian mode. */
664 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
665
666 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
667 on processor pre-defineds when compiling libgcc2.c. */
668 #if defined(__ARMEB__) && !defined(__ARMWEL__)
669 #define LIBGCC2_WORDS_BIG_ENDIAN 1
670 #else
671 #define LIBGCC2_WORDS_BIG_ENDIAN 0
672 #endif
673
674 /* Define this if most significant word of doubles is the lowest numbered.
675 This is always true, even when in little-endian mode. */
676 #define FLOAT_WORDS_BIG_ENDIAN 1
677
678 /* Number of bits in an addressable storage unit */
679 #define BITS_PER_UNIT 8
680
681 #define BITS_PER_WORD 32
682
683 #define UNITS_PER_WORD 4
684
685 #define POINTER_SIZE 32
686
687 #define PARM_BOUNDARY 32
688
689 #define STACK_BOUNDARY 32
690
691 #define FUNCTION_BOUNDARY 32
692
693 #define EMPTY_FIELD_BOUNDARY 32
694
695 #define BIGGEST_ALIGNMENT 32
696
697 /* Make strings word-aligned so strcpy from constants will be faster. */
698 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
699 (TREE_CODE (EXP) == STRING_CST \
700 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
701
702 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
703 value set in previous versions of this toolchain was 8, which produces more
704 compact structures. The command line option -mstructure_size_boundary=<n>
705 can be used to change this value. For compatability with the ARM SDK
706 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
707 0020D) page 2-20 says "Structures are aligned on word boundaries". */
708 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
709 extern int arm_structure_size_boundary;
710
711 /* This is the value used to initialise arm_structure_size_boundary. If a
712 particular arm target wants to change the default value it should change
713 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
714 for an example of this. */
715 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
716 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
717 #endif
718
719 /* Used when parsing command line option -mstructure_size_boundary. */
720 extern const char * structure_size_string;
721
722 /* Non-zero if move instructions will actually fail to work
723 when given unaligned data. */
724 #define STRICT_ALIGNMENT 1
725
726 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
727
728 \f
729 /* Standard register usage. */
730
731 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
732 (S - saved over call).
733
734 r0 * argument word/integer result
735 r1-r3 argument word
736
737 r4-r8 S register variable
738 r9 S (rfp) register variable (real frame pointer)
739
740 r10 F S (sl) stack limit (used by -mapcs-stack-check)
741 r11 F S (fp) argument pointer
742 r12 (ip) temp workspace
743 r13 F S (sp) lower end of current stack frame
744 r14 (lr) link address/workspace
745 r15 F (pc) program counter
746
747 f0 floating point result
748 f1-f3 floating point scratch
749
750 f4-f7 S floating point variable
751
752 cc This is NOT a real register, but is used internally
753 to represent things that use or set the condition
754 codes.
755 sfp This isn't either. It is used during rtl generation
756 since the offset between the frame pointer and the
757 auto's isn't known until after register allocation.
758 afp Nor this, we only need this because of non-local
759 goto. Without it fp appears to be used and the
760 elimination code won't get rid of sfp. It tracks
761 fp exactly at all times.
762
763 *: See CONDITIONAL_REGISTER_USAGE */
764
765 /* The stack backtrace structure is as follows:
766 fp points to here: | save code pointer | [fp]
767 | return link value | [fp, #-4]
768 | return sp value | [fp, #-8]
769 | return fp value | [fp, #-12]
770 [| saved r10 value |]
771 [| saved r9 value |]
772 [| saved r8 value |]
773 [| saved r7 value |]
774 [| saved r6 value |]
775 [| saved r5 value |]
776 [| saved r4 value |]
777 [| saved r3 value |]
778 [| saved r2 value |]
779 [| saved r1 value |]
780 [| saved r0 value |]
781 [| saved f7 value |] three words
782 [| saved f6 value |] three words
783 [| saved f5 value |] three words
784 [| saved f4 value |] three words
785 r0-r3 are not normally saved in a C function. */
786
787 /* 1 for registers that have pervasive standard uses
788 and are not available for the register allocator. */
789 #define FIXED_REGISTERS \
790 { \
791 0,0,0,0,0,0,0,0, \
792 0,0,0,0,0,1,0,1, \
793 0,0,0,0,0,0,0,0, \
794 1,1,1 \
795 }
796
797 /* 1 for registers not available across function calls.
798 These must include the FIXED_REGISTERS and also any
799 registers that can be used without being saved.
800 The latter must include the registers where values are returned
801 and the register where structure-value addresses are passed.
802 Aside from that, you can include as many other registers as you like.
803 The CC is not preserved over function calls on the ARM 6, so it is
804 easier to assume this for all. SFP is preserved, since FP is. */
805 #define CALL_USED_REGISTERS \
806 { \
807 1,1,1,1,0,0,0,0, \
808 0,0,0,0,1,1,1,1, \
809 1,1,1,1,0,0,0,0, \
810 1,1,1 \
811 }
812
813 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
814 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
815 #endif
816
817 #define CONDITIONAL_REGISTER_USAGE \
818 { \
819 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
820 { \
821 int regno; \
822 for (regno = FIRST_ARM_FP_REGNUM; \
823 regno <= LAST_ARM_FP_REGNUM; ++regno) \
824 fixed_regs[regno] = call_used_regs[regno] = 1; \
825 } \
826 if (flag_pic) \
827 { \
828 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
829 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
830 } \
831 else if (TARGET_APCS_STACK) \
832 { \
833 fixed_regs[10] = 1; \
834 call_used_regs[10] = 1; \
835 } \
836 if (TARGET_APCS_FRAME) \
837 { \
838 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
839 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
840 } \
841 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
842 }
843
844 /* These are a couple of extensions to the formats accecpted
845 by asm_fprintf:
846 %@ prints out ASM_COMMENT_START
847 %r prints out REGISTER_PREFIX reg_names[arg] */
848 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
849 case '@': \
850 fputs (ASM_COMMENT_START, FILE); \
851 break; \
852 \
853 case 'r': \
854 fputs (REGISTER_PREFIX, FILE); \
855 fputs (reg_names [va_arg (ARGS, int)], FILE); \
856 break;
857
858 /* Round X up to the nearest word. */
859 #define ROUND_UP(X) (((X) + 3) & ~3)
860
861 /* Convert fron bytes to ints. */
862 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
863
864 /* The number of (integer) registers required to hold a quantity of type MODE. */
865 #define NUM_REGS(MODE) \
866 NUM_INTS (GET_MODE_SIZE (MODE))
867
868 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
869 #define NUM_REGS2(MODE, TYPE) \
870 NUM_INTS ((MODE) == BLKmode ? \
871 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
872
873 /* The number of (integer) argument register available. */
874 #define NUM_ARG_REGS 4
875
876 /* Return the regiser number of the N'th (integer) argument. */
877 #define ARG_REGISTER(N) (N - 1)
878
879 /* RTX for structure returns. NULL means use a hidden first argument. */
880 #define STRUCT_VALUE 0
881
882 /* Specify the registers used for certain standard purposes.
883 The values of these macros are register numbers. */
884
885 /* The number of the last argument register. */
886 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
887
888 /* The number of the last "lo" register (thumb). */
889 #define LAST_LO_REGNUM 7
890
891 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
892 as an invisible last argument (possible since varargs don't exist in
893 Pascal), so the following is not true. */
894 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 8 : 9)
895
896 /* Define this to be where the real frame pointer is if it is not possible to
897 work out the offset between the frame pointer and the automatic variables
898 until after register allocation has taken place. FRAME_POINTER_REGNUM
899 should point to a special register that we will make sure is eliminated.
900
901 For the Thumb we have another problem. The TPCS defines the frame pointer
902 as r11, and GCC belives that it is always possible to use the frame pointer
903 as base register for addressing purposes. (See comments in
904 find_reloads_address()). But - the Thumb does not allow high registers,
905 including r11, to be used as base address registers. Hence our problem.
906
907 The solution used here, and in the old thumb port is to use r7 instead of
908 r11 as the hard frame pointer and to have special code to generate
909 backtrace structures on the stack (if required to do so via a command line
910 option) using r11. This is the only 'user visable' use of r11 as a frame
911 pointer. */
912 #define ARM_HARD_FRAME_POINTER_REGNUM 11
913 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
914 #define HARD_FRAME_POINTER_REGNUM (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM)
915 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
916
917 /* Scratch register - used in all kinds of places, eg trampolines. */
918 #define IP_REGNUM 12
919
920 /* Register to use for pushing function arguments. */
921 #define STACK_POINTER_REGNUM 13
922 #define SP_REGNUM STACK_POINTER_REGNUM
923
924 /* Register which holds return address from a subroutine call. */
925 #define LR_REGNUM 14
926
927 /* Define this if the program counter is overloaded on a register. */
928 #define PC_REGNUM 15
929
930 /* The number of the last ARM (integer) register. */
931 #define LAST_ARM_REGNUM 15
932
933 /* ARM floating pointer registers. */
934 #define FIRST_ARM_FP_REGNUM 16
935 #define LAST_ARM_FP_REGNUM 23
936
937 /* Internal, so that we don't need to refer to a raw number */
938 #define CC_REGNUM 24
939
940 /* Base register for access to local variables of the function. */
941 #define FRAME_POINTER_REGNUM 25
942
943 /* Base register for access to arguments of the function. */
944 #define ARG_POINTER_REGNUM 26
945
946 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
947 #define FIRST_PSEUDO_REGISTER 27
948
949 /* Value should be nonzero if functions must have frame pointers.
950 Zero means the frame pointer need not be set up (and parms may be accessed
951 via the stack pointer) in functions that seem suitable.
952 If we have to have a frame pointer we might as well make use of it.
953 APCS says that the frame pointer does not need to be pushed in leaf
954 functions, or simple tail call functions. */
955 #define FRAME_POINTER_REQUIRED \
956 (current_function_has_nonlocal_label \
957 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
958
959 /* Return number of consecutive hard regs needed starting at reg REGNO
960 to hold something of mode MODE.
961 This is ordinarily the length in words of a value of mode MODE
962 but can be less for certain modes in special long registers.
963
964 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
965 mode. */
966 #define HARD_REGNO_NREGS(REGNO, MODE) \
967 ((TARGET_ARM \
968 && REGNO >= FIRST_ARM_FP_REGNUM \
969 && REGNO != FRAME_POINTER_REGNUM \
970 && REGNO != ARG_POINTER_REGNUM) \
971 ? 1 : NUM_REGS (MODE))
972
973 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
974 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
975 regs holding FP.
976 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
977 so that there is always a second lo register available to hold the upper
978 part of the value. Probably we ought to ensure that the register is the
979 start of an even numbered register pair. */
980 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
981 (TARGET_ARM ? \
982 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
983 ( REGNO <= LAST_ARM_REGNUM \
984 || REGNO == FRAME_POINTER_REGNUM \
985 || REGNO == ARG_POINTER_REGNUM \
986 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
987 : \
988 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
989 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
990
991 /* Value is 1 if it is a good idea to tie two pseudo registers
992 when one has mode MODE1 and one has mode MODE2.
993 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
994 for any hard reg, then this must be 0 for correct output. */
995 #define MODES_TIEABLE_P(MODE1, MODE2) \
996 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
997
998 /* The order in which register should be allocated. It is good to use ip
999 since no saving is required (though calls clobber it) and it never contains
1000 function parameters. It is quite good to use lr since other calls may
1001 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1002 least likely to contain a function parameter; in addition results are
1003 returned in r0. */
1004 #define REG_ALLOC_ORDER \
1005 { \
1006 3, 2, 1, 0, 12, 14, 4, 5, \
1007 6, 7, 8, 10, 9, 11, 13, 15, \
1008 16, 17, 18, 19, 20, 21, 22, 23, \
1009 24, 25, 26 \
1010 }
1011 \f
1012 /* Register and constant classes. */
1013
1014 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1015 Now that the Thumb is involved it has become more compilcated. */
1016 enum reg_class
1017 {
1018 NO_REGS,
1019 FPU_REGS,
1020 LO_REGS,
1021 STACK_REG,
1022 BASE_REGS,
1023 HI_REGS,
1024 CC_REG,
1025 GENERAL_REGS,
1026 ALL_REGS,
1027 LIM_REG_CLASSES
1028 };
1029
1030 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1031
1032 /* Give names of register classes as strings for dump file. */
1033 #define REG_CLASS_NAMES \
1034 { \
1035 "NO_REGS", \
1036 "FPU_REGS", \
1037 "LO_REGS", \
1038 "STACK_REG", \
1039 "BASE_REGS", \
1040 "HI_REGS", \
1041 "CC_REG", \
1042 "GENERAL_REGS", \
1043 "ALL_REGS", \
1044 }
1045
1046 /* Define which registers fit in which classes.
1047 This is an initializer for a vector of HARD_REG_SET
1048 of length N_REG_CLASSES. */
1049 #define REG_CLASS_CONTENTS \
1050 { \
1051 { 0x0000000 }, /* NO_REGS */ \
1052 { 0x0FF0000 }, /* FPU_REGS */ \
1053 { 0x00000FF }, /* LO_REGS */ \
1054 { 0x0002000 }, /* STACK_REG */ \
1055 { 0x00020FF }, /* BASE_REGS */ \
1056 { 0x000FF00 }, /* HI_REGS */ \
1057 { 0x1000000 }, /* CC_REG */ \
1058 { 0x200FFFF }, /* GENERAL_REGS */ \
1059 { 0x2FFFFFF } /* ALL_REGS */ \
1060 }
1061
1062 /* The same information, inverted:
1063 Return the class number of the smallest class containing
1064 reg number REGNO. This could be a conditional expression
1065 or could index an array. */
1066 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1067
1068 /* The class value for index registers, and the one for base regs. */
1069 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1070 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1071
1072 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1073 registers explicitly used in the rtl to be used as spill registers
1074 but prevents the compiler from extending the lifetime of these
1075 registers. */
1076 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1077
1078 /* Get reg_class from a letter such as appears in the machine description.
1079 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1080 ARM, but several more letters for the Thumb. */
1081 #define REG_CLASS_FROM_LETTER(C) \
1082 ( (C) == 'f' ? FPU_REGS \
1083 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1084 : TARGET_ARM ? NO_REGS \
1085 : (C) == 'h' ? HI_REGS \
1086 : (C) == 'b' ? BASE_REGS \
1087 : (C) == 'k' ? STACK_REG \
1088 : (C) == 'c' ? CC_REG \
1089 : NO_REGS)
1090
1091 /* The letters I, J, K, L and M in a register constraint string
1092 can be used to stand for particular ranges of immediate operands.
1093 This macro defines what the ranges are.
1094 C is the letter, and VALUE is a constant value.
1095 Return 1 if VALUE is in the range specified by C.
1096 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1097 J: valid indexing constants.
1098 K: ~value ok in rhs argument of data operand.
1099 L: -value ok in rhs argument of data operand.
1100 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1101 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1102 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1103 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1104 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1105 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1106 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1107 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1108 : 0)
1109
1110 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1111 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1112 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1113 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1114 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1115 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1116 && ((VAL) & 3) == 0) : \
1117 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1118 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1119 : 0)
1120
1121 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1122 (TARGET_ARM ? \
1123 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1124
1125 /* Constant letter 'G' for the FPU immediate constants.
1126 'H' means the same constant negated. */
1127 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1128 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1129 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1130
1131 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1132 (TARGET_ARM ? \
1133 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1134
1135 /* For the ARM, `Q' means that this is a memory operand that is just
1136 an offset from a register.
1137 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1138 address. This means that the symbol is in the text segment and can be
1139 accessed without using a load. */
1140
1141 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1142 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1143 (C) == 'R' ? (GET_CODE (OP) == MEM \
1144 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1145 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1146 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1147 : 0)
1148
1149 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1150 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1151 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1152
1153 #define EXTRA_CONSTRAINT(X, C) \
1154 (TARGET_ARM ? \
1155 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1156
1157 /* Given an rtx X being reloaded into a reg required to be
1158 in class CLASS, return the class of reg to actually use.
1159 In general this is just CLASS, but for the Thumb we prefer
1160 a LO_REGS class or a subset. */
1161 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1162 (TARGET_ARM ? (CLASS) : \
1163 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1164
1165 /* Must leave BASE_REGS reloads alone */
1166 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1167 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1168 ? ((true_regnum (X) == -1 ? LO_REGS \
1169 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1170 : NO_REGS)) \
1171 : NO_REGS)
1172
1173 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1174 ((CLASS) != LO_REGS \
1175 ? ((true_regnum (X) == -1 ? LO_REGS \
1176 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1177 : NO_REGS)) \
1178 : NO_REGS)
1179
1180 /* Return the register class of a scratch register needed to copy IN into
1181 or out of a register in CLASS in MODE. If it can be done directly,
1182 NO_REGS is returned. */
1183 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1184 (TARGET_ARM ? \
1185 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1186 ? GENERAL_REGS : NO_REGS) \
1187 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1188
1189 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1190 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1191 (TARGET_ARM ? \
1192 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1193 && (GET_CODE (X) == MEM \
1194 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1195 && true_regnum (X) == -1))) \
1196 ? GENERAL_REGS : NO_REGS) \
1197 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1198
1199 /* Try a machine-dependent way of reloading an illegitimate address
1200 operand. If we find one, push the reload and jump to WIN. This
1201 macro is used in only one place: `find_reloads_address' in reload.c.
1202
1203 For the ARM, we wish to handle large displacements off a base
1204 register by splitting the addend across a MOV and the mem insn.
1205 This can cut the number of reloads needed. */
1206 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1207 do \
1208 { \
1209 if (GET_CODE (X) == PLUS \
1210 && GET_CODE (XEXP (X, 0)) == REG \
1211 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1212 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1213 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1214 { \
1215 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1216 HOST_WIDE_INT low, high; \
1217 \
1218 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1219 low = ((val & 0xf) ^ 0x8) - 0x8; \
1220 else if (MODE == SImode \
1221 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1222 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1223 /* Need to be careful, -4096 is not a valid offset. */ \
1224 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1225 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1226 /* Need to be careful, -256 is not a valid offset. */ \
1227 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1228 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1229 && TARGET_HARD_FLOAT) \
1230 /* Need to be careful, -1024 is not a valid offset. */ \
1231 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1232 else \
1233 break; \
1234 \
1235 high = ((((val - low) & HOST_UINT (0xffffffff)) \
1236 ^ HOST_UINT (0x80000000)) \
1237 - HOST_UINT (0x80000000)); \
1238 /* Check for overflow or zero */ \
1239 if (low == 0 || high == 0 || (high + low != val)) \
1240 break; \
1241 \
1242 /* Reload the high part into a base reg; leave the low part \
1243 in the mem. */ \
1244 X = gen_rtx_PLUS (GET_MODE (X), \
1245 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1246 GEN_INT (high)), \
1247 GEN_INT (low)); \
1248 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1249 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1250 OPNUM, TYPE); \
1251 goto WIN; \
1252 } \
1253 } \
1254 while (0)
1255
1256 /* ??? If an HImode FP+large_offset address is converted to an HImode
1257 SP+large_offset address, then reload won't know how to fix it. It sees
1258 only that SP isn't valid for HImode, and so reloads the SP into an index
1259 register, but the resulting address is still invalid because the offset
1260 is too big. We fix it here instead by reloading the entire address. */
1261 /* We could probably achieve better results by defining PROMOTE_MODE to help
1262 cope with the variances between the Thumb's signed and unsigned byte and
1263 halfword load instructions. */
1264 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1265 { \
1266 if (GET_CODE (X) == PLUS \
1267 && GET_MODE_SIZE (MODE) < 4 \
1268 && GET_CODE (XEXP (X, 0)) == REG \
1269 && XEXP (X, 0) == stack_pointer_rtx \
1270 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1271 && ! LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1272 { \
1273 rtx orig_X = X; \
1274 X = copy_rtx (X); \
1275 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
1276 BASE_REG_CLASS, \
1277 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1278 goto WIN; \
1279 } \
1280 }
1281
1282 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1283 if (TARGET_ARM) \
1284 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1285 else \
1286 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1287
1288 /* Return the maximum number of consecutive registers
1289 needed to represent mode MODE in a register of class CLASS.
1290 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1291 #define CLASS_MAX_NREGS(CLASS, MODE) \
1292 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1293
1294 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1295 #define REGISTER_MOVE_COST(FROM, TO) \
1296 (TARGET_ARM ? \
1297 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1298 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1299 : \
1300 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1301 \f
1302 /* Stack layout; function entry, exit and calling. */
1303
1304 /* Define this if pushing a word on the stack
1305 makes the stack pointer a smaller address. */
1306 #define STACK_GROWS_DOWNWARD 1
1307
1308 /* Define this if the nominal address of the stack frame
1309 is at the high-address end of the local variables;
1310 that is, each additional local variable allocated
1311 goes at a more negative offset in the frame. */
1312 #define FRAME_GROWS_DOWNWARD 1
1313
1314 /* Offset within stack frame to start allocating local variables at.
1315 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1316 first local allocated. Otherwise, it is the offset to the BEGINNING
1317 of the first local allocated. */
1318 #define STARTING_FRAME_OFFSET 0
1319
1320 /* If we generate an insn to push BYTES bytes,
1321 this says how many the stack pointer really advances by. */
1322 /* The push insns do not do this rounding implicitly.
1323 So don't define this. */
1324 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1325
1326 /* Define this if the maximum size of all the outgoing args is to be
1327 accumulated and pushed during the prologue. The amount can be
1328 found in the variable current_function_outgoing_args_size. */
1329 #define ACCUMULATE_OUTGOING_ARGS 1
1330
1331 /* Offset of first parameter from the argument pointer register value. */
1332 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1333
1334 /* Value is the number of byte of arguments automatically
1335 popped when returning from a subroutine call.
1336 FUNDECL is the declaration node of the function (as a tree),
1337 FUNTYPE is the data type of the function (as a tree),
1338 or for a library call it is an identifier node for the subroutine name.
1339 SIZE is the number of bytes of arguments passed on the stack.
1340
1341 On the ARM, the caller does not pop any of its arguments that were passed
1342 on the stack. */
1343 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1344
1345 /* Define how to find the value returned by a library function
1346 assuming the value has mode MODE. */
1347 #define LIBCALL_VALUE(MODE) \
1348 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1349 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1350 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1351
1352 /* Define how to find the value returned by a function.
1353 VALTYPE is the data type of the value (as a tree).
1354 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1355 otherwise, FUNC is 0. */
1356 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1357 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1358
1359 /* 1 if N is a possible register number for a function value.
1360 On the ARM, only r0 and f0 can return results. */
1361 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1362 ((REGNO) == ARG_REGISTER (1) \
1363 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1364
1365 /* How large values are returned */
1366 /* A C expression which can inhibit the returning of certain function values
1367 in registers, based on the type of value. */
1368 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1369
1370 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1371 values must be in memory. On the ARM, they need only do so if larger
1372 than a word, or if they contain elements offset from zero in the struct. */
1373 #define DEFAULT_PCC_STRUCT_RETURN 0
1374
1375 /* Flags for the call/call_value rtl operations set up by function_arg. */
1376 #define CALL_NORMAL 0x00000000 /* No special processing. */
1377 #define CALL_LONG 0x00000001 /* Always call indirect. */
1378 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1379
1380 /* A C structure for machine-specific, per-function data. This is added
1381 to the cfun structure. */
1382 struct machine_function
1383 {
1384 /* Records __builtin_return address. */
1385 struct rtx_def *ra_rtx;
1386 /* Additionsl stack adjustment in __builtin_eh_throw. */
1387 struct rtx_def *eh_epilogue_sp_ofs;
1388 /* Records if LR has to be saved for far jumps. */
1389 int far_jump_used;
1390 /* Records if ARG_POINTER was ever live. */
1391 int arg_pointer_live;
1392 };
1393
1394 /* A C type for declaring a variable that is used as the first argument of
1395 `FUNCTION_ARG' and other related values. For some target machines, the
1396 type `int' suffices and can hold the number of bytes of argument so far. */
1397 typedef struct
1398 {
1399 /* This is the number of registers of arguments scanned so far. */
1400 int nregs;
1401 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1402 int call_cookie;
1403 } CUMULATIVE_ARGS;
1404
1405 /* Define where to put the arguments to a function.
1406 Value is zero to push the argument on the stack,
1407 or a hard register in which to store the argument.
1408
1409 MODE is the argument's machine mode.
1410 TYPE is the data type of the argument (as a tree).
1411 This is null for libcalls where that information may
1412 not be available.
1413 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1414 the preceding args and about the function being called.
1415 NAMED is nonzero if this argument is a named parameter
1416 (otherwise it is an extra parameter matching an ellipsis).
1417
1418 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1419 other arguments are passed on the stack. If (NAMED == 0) (which happens
1420 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1421 passed in the stack (function_prologue will indeed make it pass in the
1422 stack if necessary). */
1423 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1424 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1425
1426 /* For an arg passed partly in registers and partly in memory,
1427 this is the number of registers used.
1428 For args passed entirely in registers or entirely in memory, zero. */
1429 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1430 ( NUM_ARG_REGS > (CUM).nregs \
1431 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1432 ? NUM_ARG_REGS - (CUM).nregs : 0)
1433
1434 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1435 for a call to a function whose data type is FNTYPE.
1436 For a library call, FNTYPE is 0.
1437 On the ARM, the offset starts at 0. */
1438 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1439 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1440
1441 /* Update the data in CUM to advance over an argument
1442 of mode MODE and data type TYPE.
1443 (TYPE is null for libcalls where that information may not be available.) */
1444 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1445 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1446
1447 /* 1 if N is a possible register number for function argument passing.
1448 On the ARM, r0-r3 are used to pass args. */
1449 #define FUNCTION_ARG_REGNO_P(REGNO) \
1450 ((REGNO) >= 0 && (REGNO) <= 3)
1451
1452 \f
1453 /* Tail calling. */
1454
1455 /* A C expression that evaluates to true if it is ok to perform a sibling
1456 call to DECL. */
1457 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1458
1459 /* Perform any actions needed for a function that is receiving a variable
1460 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1461 of the current parameter. PRETEND_SIZE is a variable that should be set to
1462 the amount of stack that must be pushed by the prolog to pretend that our
1463 caller pushed it.
1464
1465 Normally, this macro will push all remaining incoming registers on the
1466 stack and set PRETEND_SIZE to the length of the registers pushed.
1467
1468 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1469 named arg and all anonymous args onto the stack.
1470 XXX I know the prologue shouldn't be pushing registers, but it is faster
1471 that way. */
1472 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1473 { \
1474 extern int current_function_anonymous_args; \
1475 current_function_anonymous_args = 1; \
1476 if ((CUM).nregs < NUM_ARG_REGS) \
1477 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1478 }
1479
1480 /* Generate assembly output for the start of a function. */
1481 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1482 do \
1483 { \
1484 if (TARGET_ARM) \
1485 output_arm_prologue (STREAM, SIZE); \
1486 else \
1487 output_thumb_prologue (STREAM); \
1488 } \
1489 while (0)
1490
1491 /* If your target environment doesn't prefix user functions with an
1492 underscore, you may wish to re-define this to prevent any conflicts.
1493 e.g. AOF may prefix mcount with an underscore. */
1494 #ifndef ARM_MCOUNT_NAME
1495 #define ARM_MCOUNT_NAME "*mcount"
1496 #endif
1497
1498 /* Call the function profiler with a given profile label. The Acorn
1499 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1500 On the ARM the full profile code will look like:
1501 .data
1502 LP1
1503 .word 0
1504 .text
1505 mov ip, lr
1506 bl mcount
1507 .word LP1
1508
1509 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1510 will output the .text section.
1511
1512 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1513 ``prof'' doesn't seem to mind about this! */
1514 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1515 { \
1516 char temp[20]; \
1517 rtx sym; \
1518 \
1519 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1520 IP_REGNUM, LR_REGNUM); \
1521 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1522 fputc ('\n', STREAM); \
1523 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1524 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1525 ASM_OUTPUT_INT (STREAM, sym); \
1526 }
1527
1528 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1529 { \
1530 fprintf (STREAM, "\tmov\\tip, lr\n"); \
1531 fprintf (STREAM, "\tbl\tmcount\n"); \
1532 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1533 }
1534
1535 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1536 if (TARGET_ARM) \
1537 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1538 else \
1539 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1540
1541 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1542 the stack pointer does not matter. The value is tested only in
1543 functions that have frame pointers.
1544 No definition is equivalent to always zero.
1545
1546 On the ARM, the function epilogue recovers the stack pointer from the
1547 frame. */
1548 #define EXIT_IGNORE_STACK 1
1549
1550 /* Generate the assembly code for function exit. */
1551 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1552 output_func_epilogue (SIZE)
1553
1554 /* Determine if the epilogue should be output as RTL.
1555 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1556 #define USE_RETURN_INSN(ISCOND) \
1557 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1558
1559 /* Definitions for register eliminations.
1560
1561 This is an array of structures. Each structure initializes one pair
1562 of eliminable registers. The "from" register number is given first,
1563 followed by "to". Eliminations of the same "from" register are listed
1564 in order of preference.
1565
1566 We have two registers that can be eliminated on the ARM. First, the
1567 arg pointer register can often be eliminated in favor of the stack
1568 pointer register. Secondly, the pseudo frame pointer register can always
1569 be eliminated; it is replaced with either the stack or the real frame
1570 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1571 because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */
1572
1573 #define ELIMINABLE_REGS \
1574 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1575 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1576 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1577 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1578 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1579 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1580 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1581
1582 /* Given FROM and TO register numbers, say whether this elimination is
1583 allowed. Frame pointer elimination is automatically handled.
1584
1585 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1586 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1587 pointer, we must eliminate FRAME_POINTER_REGNUM into
1588 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1589 ARG_POINTER_REGNUM. */
1590 #define CAN_ELIMINATE(FROM, TO) \
1591 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1592 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1593 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1594 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1595 1)
1596
1597 /* Define the offset between two registers, one to be eliminated, and the
1598 other its replacement, at the start of a routine. */
1599 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1600 { \
1601 int volatile_func = arm_volatile_func (); \
1602 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1603 (OFFSET) = 0; \
1604 else if ((FROM) == FRAME_POINTER_REGNUM \
1605 && (TO) == STACK_POINTER_REGNUM) \
1606 (OFFSET) = current_function_outgoing_args_size \
1607 + ROUND_UP (get_frame_size ()); \
1608 else \
1609 { \
1610 int regno; \
1611 int offset = 12; \
1612 int saved_hard_reg = 0; \
1613 \
1614 if (! volatile_func) \
1615 { \
1616 for (regno = 0; regno <= 10; regno++) \
1617 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1618 saved_hard_reg = 1, offset += 4; \
1619 if (! TARGET_APCS_FRAME \
1620 && ! frame_pointer_needed \
1621 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \
1622 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \
1623 saved_hard_reg = 1, offset += 4; \
1624 /* PIC register is a fixed reg, so call_used_regs set. */ \
1625 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1626 saved_hard_reg = 1, offset += 4; \
1627 for (regno = FIRST_ARM_FP_REGNUM; \
1628 regno <= LAST_ARM_FP_REGNUM; regno++) \
1629 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1630 offset += 12; \
1631 } \
1632 if ((FROM) == FRAME_POINTER_REGNUM) \
1633 (OFFSET) = - offset; \
1634 else \
1635 { \
1636 if (! frame_pointer_needed) \
1637 offset -= 16; \
1638 if (! volatile_func \
1639 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1640 offset += 4; \
1641 offset += current_function_outgoing_args_size; \
1642 (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \
1643 } \
1644 } \
1645 }
1646
1647 /* Note: This macro must match the code in thumb_function_prologue(). */
1648 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1649 { \
1650 (OFFSET) = 0; \
1651 if ((FROM) == ARG_POINTER_REGNUM) \
1652 { \
1653 int count_regs = 0; \
1654 int regno; \
1655 for (regno = 8; regno < 13; regno ++) \
1656 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1657 count_regs ++; \
1658 if (count_regs) \
1659 (OFFSET) += 4 * count_regs; \
1660 count_regs = 0; \
1661 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1662 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1663 count_regs ++; \
1664 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1665 (OFFSET) += 4 * (count_regs + 1); \
1666 if (TARGET_BACKTRACE) \
1667 { \
1668 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1669 (OFFSET) += 20; \
1670 else \
1671 (OFFSET) += 16; \
1672 } \
1673 } \
1674 if ((TO) == STACK_POINTER_REGNUM) \
1675 { \
1676 (OFFSET) += current_function_outgoing_args_size; \
1677 (OFFSET) += ROUND_UP (get_frame_size ()); \
1678 } \
1679 }
1680
1681 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1682 if (TARGET_ARM) \
1683 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \
1684 else \
1685 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1686
1687 /* Special case handling of the location of arguments passed on the stack. */
1688 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1689
1690 /* Initialize data used by insn expanders. This is called from insn_emit,
1691 once for every function before code is generated. */
1692 #define INIT_EXPANDERS arm_init_expanders ()
1693
1694 /* Output assembler code for a block containing the constant parts
1695 of a trampoline, leaving space for the variable parts.
1696
1697 On the ARM, (if r8 is the static chain regnum, and remembering that
1698 referencing pc adds an offset of 8) the trampoline looks like:
1699 ldr r8, [pc, #0]
1700 ldr pc, [pc]
1701 .word static chain value
1702 .word function's address
1703 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1704 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1705 { \
1706 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1707 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1708 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1709 PC_REGNUM, PC_REGNUM); \
1710 ASM_OUTPUT_INT (FILE, const0_rtx); \
1711 ASM_OUTPUT_INT (FILE, const0_rtx); \
1712 }
1713
1714 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1715 Why - because it is easier. This code will always be branched to via
1716 a BX instruction and since the compiler magically generates the address
1717 of the function the linker has no opportunity to ensure that the
1718 bottom bit is set. Thus the processor will be in ARM mode when it
1719 reaches this code. So we duplicate the ARM trampoline code and add
1720 a switch into Thumb mode as well. */
1721 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1722 { \
1723 fprintf (FILE, "\t.code 32\n"); \
1724 fprintf (FILE, ".Ltrampoline_start:\n"); \
1725 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1726 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1727 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1728 IP_REGNUM, PC_REGNUM); \
1729 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1730 IP_REGNUM, IP_REGNUM); \
1731 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1732 fprintf (FILE, "\t.word\t0\n"); \
1733 fprintf (FILE, "\t.word\t0\n"); \
1734 fprintf (FILE, "\t.code 16\n"); \
1735 }
1736
1737 #define TRAMPOLINE_TEMPLATE(FILE) \
1738 if (TARGET_ARM) \
1739 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1740 else \
1741 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1742
1743 /* Length in units of the trampoline for entering a nested function. */
1744 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1745
1746 /* Alignment required for a trampoline in units. */
1747 #define TRAMPOLINE_ALIGN 4
1748
1749 /* Emit RTL insns to initialize the variable parts of a trampoline.
1750 FNADDR is an RTX for the address of the function's pure code.
1751 CXT is an RTX for the static chain value for the function. */
1752 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1753 { \
1754 emit_move_insn \
1755 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1756 emit_move_insn \
1757 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1758 }
1759
1760 \f
1761 /* Addressing modes, and classification of registers for them. */
1762 #define HAVE_POST_INCREMENT 1
1763 #define HAVE_PRE_INCREMENT TARGET_ARM
1764 #define HAVE_POST_DECREMENT TARGET_ARM
1765 #define HAVE_PRE_DECREMENT TARGET_ARM
1766
1767 /* Macros to check register numbers against specific register classes. */
1768
1769 /* These assume that REGNO is a hard or pseudo reg number.
1770 They give nonzero only if REGNO is a hard reg of the suitable class
1771 or a pseudo reg currently allocated to a suitable hard reg.
1772 Since they use reg_renumber, they are safe only once reg_renumber
1773 has been allocated, which happens in local-alloc.c. */
1774 #define TEST_REGNO(R, TEST, VALUE) \
1775 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1776
1777 /* On the ARM, don't allow the pc to be used. */
1778 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1779 (TARGET_THUMB ? \
1780 ( TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1781 || (GET_MODE_SIZE (MODE) >= 4 \
1782 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) \
1783 :( \
1784 TEST_REGNO (REGNO, <, PC_REGNUM) \
1785 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1786 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)))
1787
1788 /* This is like REGNO_MODE_OF_FOR_BASE_P, except that in Thumb mode
1789 the stack pointer is always acceptable, hence the passing of SImode */
1790 #define REGNO_OK_FOR_BASE_P(REGNO) \
1791 REGNO_MODE_OK_FOR_BASE_P (REGNO, SImode)
1792
1793 /* We play tricks with REGNO_MODE_OK... here, so that for ARM the macros
1794 are the same, but for Thumb only registers 0 - 7 are OK. */
1795 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1796 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1797
1798 /* Maximum number of registers that can appear in a valid memory address.
1799 Shifts in addresses can't be by a register. */
1800 #define MAX_REGS_PER_ADDRESS 2
1801
1802 /* Recognize any constant value that is a valid address. */
1803 /* XXX We can address any constant, eventually... */
1804
1805 #ifdef AOF_ASSEMBLER
1806
1807 #define CONSTANT_ADDRESS_P(X) \
1808 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1809
1810 #else
1811
1812 #define CONSTANT_ADDRESS_P(X) \
1813 (GET_CODE (X) == SYMBOL_REF \
1814 && (CONSTANT_POOL_ADDRESS_P (X) \
1815 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1816
1817 #endif /* AOF_ASSEMBLER */
1818
1819 /* Nonzero if the constant value X is a legitimate general operand.
1820 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1821
1822 On the ARM, allow any integer (invalid ones are removed later by insn
1823 patterns), nice doubles and symbol_refs which refer to the function's
1824 constant pool XXX.
1825
1826 When generating pic allow anything. */
1827 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1828
1829 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1830 ( GET_CODE (X) == CONST_INT \
1831 || GET_CODE (X) == CONST_DOUBLE \
1832 || CONSTANT_ADDRESS_P (X))
1833
1834 #define LEGITIMATE_CONSTANT_P(X) \
1835 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1836
1837 /* Special characters prefixed to function names
1838 in order to encode attribute like information.
1839 Note, '@' and '*' have already been taken. */
1840 #define SHORT_CALL_FLAG_CHAR '^'
1841 #define LONG_CALL_FLAG_CHAR '#'
1842
1843 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1844 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1845
1846 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1847 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1848
1849 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1850 #define SUBTARGET_NAME_ENCODING_LENGTHS
1851 #endif
1852
1853 /* This is a C fragement for the inside of a switch statement.
1854 Each case label should return the number of characters to
1855 be stripped from the start of a function's name, if that
1856 name starts with the indicated character. */
1857 #define ARM_NAME_ENCODING_LENGTHS \
1858 case SHORT_CALL_FLAG_CHAR: return 1; \
1859 case LONG_CALL_FLAG_CHAR: return 1; \
1860 case '*': return 1; \
1861 SUBTARGET_NAME_ENCODING_LENGTHS
1862
1863 /* This has to be handled by a function because more than part of the
1864 ARM backend uses function name prefixes to encode attributes. */
1865 #undef STRIP_NAME_ENCODING
1866 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1867 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1868
1869 /* This is how to output a reference to a user-level label named NAME.
1870 `assemble_name' uses this. */
1871 #undef ASM_OUTPUT_LABELREF
1872 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1873 fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME))
1874
1875 /* If we are referencing a function that is weak then encode a long call
1876 flag in the function name, otherwise if the function is static or
1877 or known to be defined in this file then encode a short call flag.
1878 This macro is used inside the ENCODE_SECTION macro. */
1879 #define ARM_ENCODE_CALL_TYPE(decl) \
1880 if (TREE_CODE (decl) == FUNCTION_DECL) \
1881 { \
1882 if (DECL_WEAK (decl)) \
1883 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1884 else if (! TREE_PUBLIC (decl)) \
1885 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1886 } \
1887
1888 /* Symbols in the text segment can be accessed without indirecting via the
1889 constant pool; it may take an extra binary operation, but this is still
1890 faster than indirecting via memory. Don't do this when not optimizing,
1891 since we won't be calculating al of the offsets necessary to do this
1892 simplification. */
1893 /* This doesn't work with AOF syntax, since the string table may be in
1894 a different AREA. */
1895 #ifndef AOF_ASSEMBLER
1896 #define ENCODE_SECTION_INFO(decl) \
1897 { \
1898 if (optimize > 0 && TREE_CONSTANT (decl) \
1899 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1900 { \
1901 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1902 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1903 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1904 } \
1905 ARM_ENCODE_CALL_TYPE (decl) \
1906 }
1907 #else
1908 #define ENCODE_SECTION_INFO(decl) \
1909 { \
1910 ARM_ENCODE_CALL_TYPE (decl) \
1911 }
1912 #endif
1913
1914 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1915 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1916
1917 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1918 and check its validity for a certain class.
1919 We have two alternate definitions for each of them.
1920 The usual definition accepts all pseudo regs; the other rejects
1921 them unless they have been allocated suitable hard regs.
1922 The symbol REG_OK_STRICT causes the latter definition to be used. */
1923 #ifndef REG_OK_STRICT
1924
1925 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1926 (TARGET_THUMB ? \
1927 ( REGNO (X) <= LAST_LO_REGNUM \
1928 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1929 || (GET_MODE_SIZE (MODE) >= 4 \
1930 && (REGNO (X) == STACK_POINTER_REGNUM \
1931 || (X) == hard_frame_pointer_rtx \
1932 || (X) == arg_pointer_rtx))) \
1933 :( \
1934 REGNO (X) <= LAST_ARM_REGNUM \
1935 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1936 || REGNO (X) == FRAME_POINTER_REGNUM \
1937 || REGNO (X) == ARG_POINTER_REGNUM))
1938
1939 /* Nonzero if X is a hard reg that can be used as a base reg
1940 or if it is a pseudo reg. */
1941 #define REG_OK_FOR_BASE_P(X) \
1942 REG_MODE_OK_FOR_BASE_P (X, SImode)
1943
1944 /* Nonzero if X is a hard reg that can be used as an index
1945 or if it is a pseudo reg. On the Thumb, the stack pointer
1946 is not suitable. */
1947 #define REG_OK_FOR_INDEX_P(X) \
1948 REG_MODE_OK_FOR_BASE_P (X, QImode)
1949
1950 /* Just like REG_OK_FOR_BASE_P except that we also allow the PC. */
1951 #define REG_OK_FOR_PRE_POST_P(X) \
1952 (REG_OK_FOR_BASE_P (X) || REGNO(X) == PC_REGNUM)
1953
1954 #else /* REG_OK_STRICT */
1955
1956 /* Nonzero if X is a hard reg that can be used as a base reg. */
1957 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1958
1959 /* Nonzero if X is a hard reg that can be used as an index. */
1960 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1961
1962 /* Just like REG_OK_FOR_BASE_P except that we also allow the PC. */
1963 #define REG_OK_FOR_PRE_POST_P(X) \
1964 (REG_OK_FOR_BASE_P (X) || TEST_REGNO (REGNO (X), ==, PC_REGNUM))
1965
1966 #endif /* REG_OK_STRICT */
1967 \f
1968 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1969 that is a valid memory address for an instruction.
1970 The MODE argument is the machine mode for the MEM expression
1971 that wants to use this address.
1972
1973 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1974
1975 /* --------------------------------arm version----------------------------- */
1976 #define BASE_REGISTER_RTX_P(X) \
1977 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1978
1979 #define INDEX_REGISTER_RTX_P(X) \
1980 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1981
1982 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1983 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1984 only be small constants. */
1985 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1986 do \
1987 { \
1988 HOST_WIDE_INT range; \
1989 enum rtx_code code = GET_CODE (INDEX); \
1990 \
1991 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1992 { \
1993 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1994 && INTVAL (INDEX) > -1024 \
1995 && (INTVAL (INDEX) & 3) == 0) \
1996 goto LABEL; \
1997 } \
1998 else \
1999 { \
2000 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
2001 goto LABEL; \
2002 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2003 && (! arm_arch4 || (MODE) != HImode)) \
2004 { \
2005 rtx xiop0 = XEXP (INDEX, 0); \
2006 rtx xiop1 = XEXP (INDEX, 1); \
2007 if (INDEX_REGISTER_RTX_P (xiop0) \
2008 && power_of_two_operand (xiop1, SImode)) \
2009 goto LABEL; \
2010 if (INDEX_REGISTER_RTX_P (xiop1) \
2011 && power_of_two_operand (xiop0, SImode)) \
2012 goto LABEL; \
2013 } \
2014 if (GET_MODE_SIZE (MODE) <= 4 \
2015 && (code == LSHIFTRT || code == ASHIFTRT \
2016 || code == ASHIFT || code == ROTATERT) \
2017 && (! arm_arch4 || (MODE) != HImode)) \
2018 { \
2019 rtx op = XEXP (INDEX, 1); \
2020 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2021 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2022 && INTVAL (op) <= 31) \
2023 goto LABEL; \
2024 } \
2025 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
2026 range = ((MODE) == HImode || (MODE) == QImode) \
2027 ? (arm_arch4 ? 256 : 4095) : 4096; \
2028 if (code == CONST_INT && INTVAL (INDEX) < range \
2029 && INTVAL (INDEX) > -range) \
2030 goto LABEL; \
2031 } \
2032 } \
2033 while (0)
2034
2035 /* Jump to LABEL if X is a valid address RTX. This must also take
2036 REG_OK_STRICT into account when deciding about valid registers, but it uses
2037 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
2038 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
2039 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
2040 refs must be forced though a static cell to ensure addressability. */
2041 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2042 { \
2043 if (BASE_REGISTER_RTX_P (X)) \
2044 goto LABEL; \
2045 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2046 && GET_CODE (XEXP (X, 0)) == REG \
2047 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
2048 goto LABEL; \
2049 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2050 && (GET_CODE (X) == LABEL_REF \
2051 || (GET_CODE (X) == CONST \
2052 && GET_CODE (XEXP ((X), 0)) == PLUS \
2053 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2054 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2055 goto LABEL; \
2056 else if ((MODE) == TImode) \
2057 ; \
2058 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2059 { \
2060 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2061 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2062 { \
2063 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2064 if (val == 4 || val == -4 || val == -8) \
2065 goto LABEL; \
2066 } \
2067 } \
2068 else if (GET_CODE (X) == PLUS) \
2069 { \
2070 rtx xop0 = XEXP (X, 0); \
2071 rtx xop1 = XEXP (X, 1); \
2072 \
2073 if (BASE_REGISTER_RTX_P (xop0)) \
2074 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2075 else if (BASE_REGISTER_RTX_P (xop1)) \
2076 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2077 } \
2078 /* Reload currently can't handle MINUS, so disable this for now */ \
2079 /* else if (GET_CODE (X) == MINUS) \
2080 { \
2081 rtx xop0 = XEXP (X,0); \
2082 rtx xop1 = XEXP (X,1); \
2083 \
2084 if (BASE_REGISTER_RTX_P (xop0)) \
2085 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2086 } */ \
2087 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2088 && GET_CODE (X) == SYMBOL_REF \
2089 && CONSTANT_POOL_ADDRESS_P (X) \
2090 && ! (flag_pic \
2091 && symbol_mentioned_p (get_pool_constant (X)))) \
2092 goto LABEL; \
2093 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2094 && (GET_MODE_SIZE (MODE) <= 4) \
2095 && GET_CODE (XEXP (X, 0)) == REG \
2096 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
2097 goto LABEL; \
2098 }
2099
2100 /* ---------------------thumb version----------------------------------*/
2101 #define LEGITIMATE_OFFSET(MODE, VAL) \
2102 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2103 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2104 && ((VAL) & 1) == 0) \
2105 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2106 && ((VAL) & 3) == 0))
2107
2108 /* The AP may be eliminated to either the SP or the FP, so we use the
2109 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2110
2111 /* ??? Verify whether the above is the right approach. */
2112
2113 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2114 needs special handling also. */
2115
2116 /* ??? Look at how the mips16 port solves this problem. It probably uses
2117 better ways to solve some of these problems. */
2118
2119 /* Although it is not incorrect, we don't accept QImode and HImode
2120 addresses based on the frame pointer or arg pointer until the reload pass starts.
2121 This is so that eliminating such addresses into stack based ones
2122 won't produce impossible code. */
2123 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2124 { \
2125 /* ??? Not clear if this is right. Experiment. */ \
2126 if (GET_MODE_SIZE (MODE) < 4 \
2127 && ! (reload_in_progress || reload_completed) \
2128 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2129 || reg_mentioned_p (arg_pointer_rtx, X) \
2130 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2131 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2132 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2133 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2134 ; \
2135 /* Accept any base register. SP only in SImode or larger. */ \
2136 else if (GET_CODE (X) == REG && REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2137 goto WIN; \
2138 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2139 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2140 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2141 goto WIN; \
2142 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2143 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2144 && (GET_CODE (X) == LABEL_REF \
2145 || (GET_CODE (X) == CONST \
2146 && GET_CODE (XEXP (X, 0)) == PLUS \
2147 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2148 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2149 goto WIN; \
2150 /* Post-inc indexing only supported for SImode and larger. */ \
2151 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2152 && GET_CODE (XEXP (X, 0)) == REG \
2153 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2154 goto WIN; \
2155 else if (GET_CODE (X) == PLUS) \
2156 { \
2157 /* REG+REG address can be any two index registers. */ \
2158 /* We disallow FRAME+REG addressing since we know that FRAME \
2159 will be replaced with STACK, and SP relative addressing only \
2160 permits SP+OFFSET. */ \
2161 if (GET_MODE_SIZE (MODE) <= 4 \
2162 && GET_CODE (XEXP (X, 0)) == REG \
2163 && GET_CODE (XEXP (X, 1)) == REG \
2164 && XEXP (X, 0) != frame_pointer_rtx \
2165 && XEXP (X, 1) != frame_pointer_rtx \
2166 && XEXP (X, 0) != virtual_stack_vars_rtx \
2167 && XEXP (X, 1) != virtual_stack_vars_rtx \
2168 && REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2169 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2170 goto WIN; \
2171 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2172 else if (GET_CODE (XEXP (X, 0)) == REG \
2173 && (REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2174 || XEXP (X, 0) == arg_pointer_rtx) \
2175 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2176 && LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2177 goto WIN; \
2178 /* REG+const has 10 bit offset for SP, but only SImode and \
2179 larger is supported. */ \
2180 /* ??? Should probably check for DI/DFmode overflow here \
2181 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2182 else if (GET_CODE (XEXP (X, 0)) == REG \
2183 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2184 && GET_MODE_SIZE (MODE) >= 4 \
2185 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2186 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2187 + GET_MODE_SIZE (MODE)) <= 1024 \
2188 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2189 goto WIN; \
2190 else if (GET_CODE (XEXP (X, 0)) == REG \
2191 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2192 && GET_MODE_SIZE (MODE) >= 4 \
2193 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2194 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2195 goto WIN; \
2196 } \
2197 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2198 && GET_CODE (X) == SYMBOL_REF \
2199 && CONSTANT_POOL_ADDRESS_P (X) \
2200 && ! (flag_pic \
2201 && symbol_mentioned_p (get_pool_constant (X)))) \
2202 goto WIN; \
2203 }
2204
2205 /* ------------------------------------------------------------------- */
2206 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2207 if (TARGET_ARM) \
2208 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2209 else /* if (TARGET_THUMB) */ \
2210 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2211 /* ------------------------------------------------------------------- */
2212 \f
2213 /* Try machine-dependent ways of modifying an illegitimate address
2214 to be legitimate. If we find one, return the new, valid address.
2215 This macro is used in only one place: `memory_address' in explow.c.
2216
2217 OLDX is the address as it was before break_out_memory_refs was called.
2218 In some cases it is useful to look at this to decide what needs to be done.
2219
2220 MODE and WIN are passed so that this macro can use
2221 GO_IF_LEGITIMATE_ADDRESS.
2222
2223 It is always safe for this macro to do nothing. It exists to recognize
2224 opportunities to optimize the output.
2225
2226 On the ARM, try to convert [REG, #BIGCONST]
2227 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2228 where VALIDCONST == 0 in case of TImode. */
2229 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2230 { \
2231 if (GET_CODE (X) == PLUS) \
2232 { \
2233 rtx xop0 = XEXP (X, 0); \
2234 rtx xop1 = XEXP (X, 1); \
2235 \
2236 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2237 xop0 = force_reg (SImode, xop0); \
2238 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2239 xop1 = force_reg (SImode, xop1); \
2240 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
2241 { \
2242 HOST_WIDE_INT n, low_n; \
2243 rtx base_reg, val; \
2244 n = INTVAL (xop1); \
2245 \
2246 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2247 { \
2248 low_n = n & 0x0f; \
2249 n &= ~0x0f; \
2250 if (low_n > 4) \
2251 { \
2252 n += 16; \
2253 low_n -= 16; \
2254 } \
2255 } \
2256 else \
2257 { \
2258 low_n = ((MODE) == TImode ? 0 \
2259 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2260 n -= low_n; \
2261 } \
2262 base_reg = gen_reg_rtx (SImode); \
2263 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2264 GEN_INT (n)), NULL_RTX); \
2265 emit_move_insn (base_reg, val); \
2266 (X) = (low_n == 0 ? base_reg \
2267 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2268 } \
2269 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2270 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2271 } \
2272 else if (GET_CODE (X) == MINUS) \
2273 { \
2274 rtx xop0 = XEXP (X, 0); \
2275 rtx xop1 = XEXP (X, 1); \
2276 \
2277 if (CONSTANT_P (xop0)) \
2278 xop0 = force_reg (SImode, xop0); \
2279 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2280 xop1 = force_reg (SImode, xop1); \
2281 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2282 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2283 } \
2284 if (flag_pic) \
2285 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2286 if (memory_address_p (MODE, X)) \
2287 goto WIN; \
2288 }
2289
2290 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2291 if (flag_pic) \
2292 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2293
2294 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2295 if (TARGET_ARM) \
2296 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2297 else \
2298 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2299
2300 /* Go to LABEL if ADDR (a legitimate address expression)
2301 has an effect that depends on the machine mode it is used for. */
2302 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2303 { \
2304 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2305 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2306 goto LABEL; \
2307 }
2308
2309 /* Nothing helpful to do for the Thumb */
2310 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2311 if (TARGET_ARM) \
2312 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2313 \f
2314
2315 /* Specify the machine mode that this machine uses
2316 for the index in the tablejump instruction. */
2317 #define CASE_VECTOR_MODE Pmode
2318
2319 /* Define as C expression which evaluates to nonzero if the tablejump
2320 instruction expects the table to contain offsets from the address of the
2321 table.
2322 Do not define this if the table should contain absolute addresses. */
2323 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2324
2325 /* Specify the tree operation to be used to convert reals to integers. */
2326 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2327
2328 /* This is the kind of divide that is easiest to do in the general case. */
2329 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2330
2331 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2332 unsigned is probably best, but may break some code. */
2333 #ifndef DEFAULT_SIGNED_CHAR
2334 #define DEFAULT_SIGNED_CHAR 0
2335 #endif
2336
2337 /* Don't cse the address of the function being compiled. */
2338 #define NO_RECURSIVE_FUNCTION_CSE 1
2339
2340 /* Max number of bytes we can move from memory to memory
2341 in one reasonably fast instruction. */
2342 #define MOVE_MAX 4
2343
2344 /* Define if operations between registers always perform the operation
2345 on the full register even if a narrower mode is specified. */
2346 #define WORD_REGISTER_OPERATIONS
2347
2348 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2349 will either zero-extend or sign-extend. The value of this macro should
2350 be the code that says which one of the two operations is implicitly
2351 done, NIL if none. */
2352 #define LOAD_EXTEND_OP(MODE) \
2353 (TARGET_THUMB ? ZERO_EXTEND : \
2354 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2355 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2356
2357 /* Define this if zero-extension is slow (more than one real instruction).
2358 On the ARM, it is more than one instruction only if not fetching from
2359 memory. */
2360 /* #define SLOW_ZERO_EXTEND */
2361
2362 /* Nonzero if access to memory by bytes is slow and undesirable. */
2363 #define SLOW_BYTE_ACCESS 0
2364
2365 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2366
2367 /* Immediate shift counts are truncated by the output routines (or was it
2368 the assembler?). Shift counts in a register are truncated by ARM. Note
2369 that the native compiler puts too large (> 32) immediate shift counts
2370 into a register and shifts by the register, letting the ARM decide what
2371 to do instead of doing that itself. */
2372 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2373 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2374 On the arm, Y in a register is used modulo 256 for the shift. Only for
2375 rotates is modulo 32 used. */
2376 /* #define SHIFT_COUNT_TRUNCATED 1 */
2377
2378 /* All integers have the same format so truncation is easy. */
2379 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2380
2381 /* Calling from registers is a massive pain. */
2382 #define NO_FUNCTION_CSE 1
2383
2384 /* Chars and shorts should be passed as ints. */
2385 #define PROMOTE_PROTOTYPES 1
2386
2387 /* The machine modes of pointers and functions */
2388 #define Pmode SImode
2389 #define FUNCTION_MODE Pmode
2390
2391 #define ARM_FRAME_RTX(X) \
2392 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2393 || (X) == arg_pointer_rtx)
2394
2395 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2396 return arm_rtx_costs (X, CODE, OUTER_CODE);
2397
2398 /* Moves to and from memory are quite expensive */
2399 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2400 (TARGET_ARM ? 10 : \
2401 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2402 * (CLASS == LO_REGS ? 1 : 2)))
2403
2404 /* All address computations that can be done are free, but rtx cost returns
2405 the same for practically all of them. So we weight the different types
2406 of address here in the order (most pref first):
2407 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2408 #define ARM_ADDRESS_COST(X) \
2409 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2410 || GET_CODE (X) == SYMBOL_REF) \
2411 ? 0 \
2412 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2413 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2414 ? 10 \
2415 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2416 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2417 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2418 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2419 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2420 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2421 ? 1 : 0)) \
2422 : 4)))))
2423
2424 #define THUMB_ADDRESS_COST(X) \
2425 ((GET_CODE (X) == REG \
2426 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2427 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2428 ? 1 : 2)
2429
2430 #define ADDRESS_COST(X) \
2431 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2432
2433 /* Try to generate sequences that don't involve branches, we can then use
2434 conditional instructions */
2435 #define BRANCH_COST \
2436 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2437
2438 /* A C statement to update the variable COST based on the relationship
2439 between INSN that is dependent on DEP through dependence LINK. */
2440 #define ADJUST_COST(INSN, LINK, DEP, COST) \
2441 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
2442 \f
2443 /* Position Independent Code. */
2444 /* We decide which register to use based on the compilation options and
2445 the assembler in use; this is more general than the APCS restriction of
2446 using sb (r9) all the time. */
2447 extern int arm_pic_register;
2448
2449 /* Used when parsing command line option -mpic-register=. */
2450 extern const char * arm_pic_register_string;
2451
2452 /* The register number of the register used to address a table of static
2453 data addresses in memory. */
2454 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2455
2456 #define FINALIZE_PIC arm_finalize_pic ()
2457
2458 /* We can't directly access anything that contains a symbol,
2459 nor can we indirect via the constant pool. */
2460 #define LEGITIMATE_PIC_OPERAND_P(X) \
2461 ( ! symbol_mentioned_p (X) \
2462 && ! label_mentioned_p (X) \
2463 && (! CONSTANT_POOL_ADDRESS_P (X) \
2464 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2465 && ! label_mentioned_p (get_pool_constant (X)))))
2466
2467 /* We need to know when we are making a constant pool; this determines
2468 whether data needs to be in the GOT or can be referenced via a GOT
2469 offset. */
2470 extern int making_const_table;
2471 \f
2472 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2473 with arguments ARGS is a valid machine specific attribute for TYPE.
2474 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2475 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2476 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2477
2478 /* If defined, a C expression whose value is zero if the attributes on
2479 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2480 two if they are nearly compatible (which causes a warning to be
2481 generated). */
2482 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2483 (arm_comp_type_attributes (TYPE1, TYPE2))
2484
2485 /* If defined, a C statement that assigns default attributes to newly
2486 defined TYPE. */
2487 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
2488 arm_set_default_type_attributes (TYPE)
2489
2490 /* Handle pragmas for compatibility with Intel's compilers. */
2491 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2492 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2493 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2494 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2495 } while (0)
2496
2497 /* Condition code information. */
2498 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2499 return the mode to be used for the comparison.
2500 CCFPEmode should be used with floating inequalities,
2501 CCFPmode should be used with floating equalities.
2502 CC_NOOVmode should be used with SImode integer equalities.
2503 CC_Zmode should be used if only the Z flag is set correctly
2504 CCmode should be used otherwise. */
2505
2506 #define EXTRA_CC_MODES \
2507 CC(CC_NOOVmode, "CC_NOOV") \
2508 CC(CC_Zmode, "CC_Z") \
2509 CC(CC_SWPmode, "CC_SWP") \
2510 CC(CCFPmode, "CCFP") \
2511 CC(CCFPEmode, "CCFPE") \
2512 CC(CC_DNEmode, "CC_DNE") \
2513 CC(CC_DEQmode, "CC_DEQ") \
2514 CC(CC_DLEmode, "CC_DLE") \
2515 CC(CC_DLTmode, "CC_DLT") \
2516 CC(CC_DGEmode, "CC_DGE") \
2517 CC(CC_DGTmode, "CC_DGT") \
2518 CC(CC_DLEUmode, "CC_DLEU") \
2519 CC(CC_DLTUmode, "CC_DLTU") \
2520 CC(CC_DGEUmode, "CC_DGEU") \
2521 CC(CC_DGTUmode, "CC_DGTU") \
2522 CC(CC_Cmode, "CC_C")
2523
2524 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2525
2526 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2527
2528 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2529 do \
2530 { \
2531 if (GET_CODE (OP1) == CONST_INT \
2532 && ! (const_ok_for_arm (INTVAL (OP1)) \
2533 || (const_ok_for_arm (- INTVAL (OP1))))) \
2534 { \
2535 rtx const_op = OP1; \
2536 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2537 OP1 = const_op; \
2538 } \
2539 } \
2540 while (0)
2541
2542 #define STORE_FLAG_VALUE 1
2543
2544 \f
2545
2546 /* Gcc puts the pool in the wrong place for ARM, since we can only
2547 load addresses a limited distance around the pc. We do some
2548 special munging to move the constant pool values to the correct
2549 point in the code. */
2550 #define MACHINE_DEPENDENT_REORG(INSN) \
2551 arm_reorg (INSN); \
2552
2553 #undef ASM_APP_OFF
2554 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2555
2556 /* Output an internal label definition. */
2557 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2558 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2559 do \
2560 { \
2561 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2562 \
2563 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2564 && !strcmp (PREFIX, "L")) \
2565 { \
2566 arm_ccfsm_state = 0; \
2567 arm_target_insn = NULL; \
2568 } \
2569 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2570 ASM_OUTPUT_LABEL (STREAM, s); \
2571 } \
2572 while (0)
2573 #endif
2574
2575 /* Output a push or a pop instruction (only used when profiling). */
2576 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2577 if (TARGET_ARM) \
2578 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2579 STACK_POINTER_REGNUM, REGNO); \
2580 else \
2581 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2582
2583
2584 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2585 if (TARGET_ARM) \
2586 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2587 STACK_POINTER_REGNUM, REGNO); \
2588 else \
2589 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2590
2591 /* This is how to output a label which precedes a jumptable. Since
2592 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2593 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2594 do \
2595 { \
2596 if (TARGET_THUMB) \
2597 ASM_OUTPUT_ALIGN (FILE, 2); \
2598 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2599 } \
2600 while (0)
2601
2602 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2603 do \
2604 { \
2605 if (TARGET_THUMB) \
2606 { \
2607 if (is_called_in_ARM_mode (DECL)) \
2608 fprintf (STREAM, "\t.code 32\n") ; \
2609 else \
2610 fprintf (STREAM, "\t.thumb_func\n") ; \
2611 } \
2612 if (TARGET_POKE_FUNCTION_NAME) \
2613 arm_poke_function_name (STREAM, (char *) NAME); \
2614 } \
2615 while (0)
2616
2617 /* For aliases of functions we use .thumb_set instead. */
2618 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2619 do \
2620 { \
2621 char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2622 char * LABEL2 = IDENTIFIER_POINTER (DECL2); \
2623 \
2624 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2625 { \
2626 fprintf (FILE, "\t.thumb_set "); \
2627 assemble_name (FILE, LABEL1); \
2628 fprintf (FILE, ","); \
2629 assemble_name (FILE, LABEL2); \
2630 fprintf (FILE, "\n"); \
2631 } \
2632 else \
2633 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2634 } \
2635 while (0)
2636
2637 /* Target characters. */
2638 #define TARGET_BELL 007
2639 #define TARGET_BS 010
2640 #define TARGET_TAB 011
2641 #define TARGET_NEWLINE 012
2642 #define TARGET_VT 013
2643 #define TARGET_FF 014
2644 #define TARGET_CR 015
2645 \f
2646 /* Only perform branch elimination (by making instructions conditional) if
2647 we're optimising. Otherwise it's of no use anyway. */
2648 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2649 if (TARGET_ARM && optimize) \
2650 arm_final_prescan_insn (INSN); \
2651 else if (TARGET_THUMB) \
2652 thumb_final_prescan_insn (INSN)
2653
2654 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2655 (CODE == '@' || CODE == '|' \
2656 || (TARGET_ARM && (CODE == '?')) \
2657 || (TARGET_THUMB && (CODE == '_')))
2658
2659 /* Output an operand of an instruction. */
2660 #define PRINT_OPERAND(STREAM, X, CODE) \
2661 arm_print_operand (STREAM, X, CODE)
2662
2663 /* Create an [unsigned] host sized integer declaration that
2664 avoids compiler warnings. */
2665 #ifdef __STDC__
2666 #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL)
2667 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL)
2668 #else
2669 #define HOST_INT(x) ((HOST_WIDE_INT) x)
2670 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x)
2671 #endif
2672
2673 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2674 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2675 : (((x) & HOST_UINT (0xffffffff)) | \
2676 (((x) & HOST_UINT (0x80000000)) \
2677 ? ((~ HOST_INT (0)) \
2678 & ~ HOST_UINT(0xffffffff)) \
2679 : 0))))
2680
2681 /* Output the address of an operand. */
2682 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2683 { \
2684 int is_minus = GET_CODE (X) == MINUS; \
2685 \
2686 if (GET_CODE (X) == REG) \
2687 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2688 else if (GET_CODE (X) == PLUS || is_minus) \
2689 { \
2690 rtx base = XEXP (X, 0); \
2691 rtx index = XEXP (X, 1); \
2692 HOST_WIDE_INT offset = 0; \
2693 if (GET_CODE (base) != REG) \
2694 { \
2695 /* Ensure that BASE is a register */ \
2696 /* (one of them must be). */ \
2697 rtx temp = base; \
2698 base = index; \
2699 index = temp; \
2700 } \
2701 switch (GET_CODE (index)) \
2702 { \
2703 case CONST_INT: \
2704 offset = INTVAL (index); \
2705 if (is_minus) \
2706 offset = -offset; \
2707 asm_fprintf (STREAM, "[%r, #%d]", \
2708 REGNO (base), offset); \
2709 break; \
2710 \
2711 case REG: \
2712 asm_fprintf (STREAM, "[%r, %s%r]", \
2713 REGNO (base), is_minus ? "-" : "", \
2714 REGNO (index)); \
2715 break; \
2716 \
2717 case MULT: \
2718 case ASHIFTRT: \
2719 case LSHIFTRT: \
2720 case ASHIFT: \
2721 case ROTATERT: \
2722 { \
2723 asm_fprintf (STREAM, "[%r, %s%r", \
2724 REGNO (base), is_minus ? "-" : "", \
2725 REGNO (XEXP (index, 0))); \
2726 arm_print_operand (STREAM, index, 'S'); \
2727 fputs ("]", STREAM); \
2728 break; \
2729 } \
2730 \
2731 default: \
2732 abort(); \
2733 } \
2734 } \
2735 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2736 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2737 { \
2738 extern int output_memory_reference_mode; \
2739 \
2740 if (GET_CODE (XEXP (X, 0)) != REG) \
2741 abort (); \
2742 \
2743 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2744 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2745 REGNO (XEXP (X, 0)), \
2746 GET_CODE (X) == PRE_DEC ? "-" : "", \
2747 GET_MODE_SIZE (output_memory_reference_mode));\
2748 else \
2749 asm_fprintf (STREAM, "[%r], #%s%d", \
2750 REGNO (XEXP (X, 0)), \
2751 GET_CODE (X) == POST_DEC ? "-" : "", \
2752 GET_MODE_SIZE (output_memory_reference_mode));\
2753 } \
2754 else output_addr_const (STREAM, X); \
2755 }
2756
2757 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2758 { \
2759 if (GET_CODE (X) == REG) \
2760 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2761 else if (GET_CODE (X) == POST_INC) \
2762 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2763 else if (GET_CODE (X) == PLUS) \
2764 { \
2765 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2766 asm_fprintf (STREAM, "[%r, #%d]", \
2767 REGNO (XEXP (X, 0)), \
2768 (int) INTVAL (XEXP (X, 1))); \
2769 else \
2770 asm_fprintf (STREAM, "[%r, %r]", \
2771 REGNO (XEXP (X, 0)), \
2772 REGNO (XEXP (X, 1))); \
2773 } \
2774 else \
2775 output_addr_const (STREAM, X); \
2776 }
2777
2778 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2779 if (TARGET_ARM) \
2780 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2781 else \
2782 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2783
2784 /* Handles PIC addr specially */
2785 #define OUTPUT_INT_ADDR_CONST(STREAM, X) \
2786 { \
2787 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2788 { \
2789 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2790 fputs (" - (", STREAM); \
2791 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2792 fputs (")", STREAM); \
2793 } \
2794 else \
2795 output_addr_const (STREAM, X); \
2796 \
2797 /* Mark symbols as position independent. We only do this in the \
2798 .text segment, not in the .data segment. */ \
2799 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2800 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2801 { \
2802 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2803 fprintf (STREAM, "(GOTOFF)"); \
2804 else if (GET_CODE (X) == LABEL_REF) \
2805 fprintf (STREAM, "(GOTOFF)"); \
2806 else \
2807 fprintf (STREAM, "(GOT)"); \
2808 } \
2809 }
2810
2811 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2812 Used for C++ multiple inheritance. */
2813 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2814 do \
2815 { \
2816 int mi_delta = (DELTA); \
2817 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2818 int shift = 0; \
2819 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2820 ? 1 : 0); \
2821 if (mi_delta < 0) \
2822 mi_delta = - mi_delta; \
2823 while (mi_delta != 0) \
2824 { \
2825 if ((mi_delta & (3 << shift)) == 0) \
2826 shift += 2; \
2827 else \
2828 { \
2829 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2830 mi_op, this_regno, this_regno, \
2831 mi_delta & (0xff << shift)); \
2832 mi_delta &= ~(0xff << shift); \
2833 shift += 8; \
2834 } \
2835 } \
2836 fputs ("\tb\t", FILE); \
2837 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2838 if (NEED_PLT_RELOC) \
2839 fputs ("(PLT)", FILE); \
2840 fputc ('\n', FILE); \
2841 } \
2842 while (0)
2843
2844 /* A C expression whose value is RTL representing the value of the return
2845 address for the frame COUNT steps up from the current frame. */
2846
2847 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2848 arm_return_addr (COUNT, FRAME)
2849
2850 /* Mask of the bits in the PC that contain the real return address
2851 when running in 26-bit mode. */
2852 #define RETURN_ADDR_MASK26 (0x03fffffc)
2853
2854 /* Pick up the return address upon entry to a procedure. Used for
2855 dwarf2 unwind information. This also enables the table driven
2856 mechanism. */
2857 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2858 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2859
2860 /* Used to mask out junk bits from the return address, such as
2861 processor state, interrupt status, condition codes and the like. */
2862 #define MASK_RETURN_ADDR \
2863 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2864 in 26 bit mode, the condition codes must be masked out of the \
2865 return address. This does not apply to ARM6 and later processors \
2866 when running in 32 bit mode. */ \
2867 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2868 : (GEN_INT ((unsigned long)0xffffffff)))
2869
2870 \f
2871 /* Define the codes that are matched by predicates in arm.c */
2872 #define PREDICATE_CODES \
2873 {"s_register_operand", {SUBREG, REG}}, \
2874 {"f_register_operand", {SUBREG, REG}}, \
2875 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2876 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2877 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2878 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2879 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2880 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2881 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2882 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2883 {"offsettable_memory_operand", {MEM}}, \
2884 {"bad_signed_byte_operand", {MEM}}, \
2885 {"alignable_memory_operand", {MEM}}, \
2886 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2887 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2888 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2889 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2890 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2891 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2892 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2893 {"load_multiple_operation", {PARALLEL}}, \
2894 {"store_multiple_operation", {PARALLEL}}, \
2895 {"equality_operator", {EQ, NE}}, \
2896 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2897 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2898 UNGE, UNGT}}, \
2899 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2900 {"const_shift_operand", {CONST_INT}}, \
2901 {"multi_register_push", {PARALLEL}}, \
2902 {"cc_register", {REG}}, \
2903 {"logical_binary_operator", {AND, IOR, XOR}}, \
2904 {"dominant_cc_register", {REG}},
2905
2906 /* Define this if you have special predicates that know special things
2907 about modes. Genrecog will warn about certain forms of
2908 match_operand without a mode; if the operand predicate is listed in
2909 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2910 #define SPECIAL_MODE_PREDICATES \
2911 "cc_register", "dominant_cc_register",
2912
2913 #endif /* __ARM_H__ */
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