1 /* { dg-do compile } */
2 /* { dg-require-effective-target vect_int } */
6 const unsigned int in
[N
] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
9 __attribute__ ((noinline
)) int
12 const unsigned int *pin
= &in
[1];
13 unsigned int *pout
= &out
[0];
15 /* Misaligned load. */
24 /* Verify that the assembly contains vector instructions alone
25 with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
26 or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
28 /* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
29 /* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* } } } } */
30 /* { dg-final { scan-assembler-not "\tstwu?x? " } } */