1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calulates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
195 order. The major one is to form *threads* from colorable
196 allocnos and push them on the stack by threads. Thread is a
197 set of non-conflicting colorable allocnos connected by
198 copies. The thread contains allocnos from the colorable
199 bucket or colorable allocnos already pushed onto the coloring
200 stack. Pushing thread allocnos one after another onto the
201 stack increases chances of removing copies when the allocnos
202 get the same hard reg.
204 We also use a modification of Chaitin-Briggs algorithm which
205 works for intersected register classes of allocnos. To
206 figure out trivial colorability of allocnos, the mentioned
207 above tree of hard register sets is used. To get an idea how
208 the algorithm works in i386 example, let us consider an
209 allocno to which any general hard register can be assigned.
210 If the allocno conflicts with eight allocnos to which only
211 EAX register can be assigned, given allocno is still
212 trivially colorable because all conflicting allocnos might be
213 assigned only to EAX and all other general hard registers are
216 To get an idea of the used trivial colorability criterion, it
217 is also useful to read article "Graph-Coloring Register
218 Allocation for Irregular Architectures" by Michael D. Smith
219 and Glen Holloway. Major difference between the article
220 approach and approach used in IRA is that Smith's approach
221 takes register classes only from machine description and IRA
222 calculate register classes from intermediate code too
223 (e.g. an explicit usage of hard registers in RTL code for
224 parameter passing can result in creation of additional
225 register classes which contain or exclude the hard
226 registers). That makes IRA approach useful for improving
227 coloring even for architectures with regular register files
228 and in fact some benchmarking shows the improvement for
229 regular class architectures is even bigger than for irregular
230 ones. Another difference is that Smith's approach chooses
231 intersection of classes of all insn operands in which a given
232 pseudo occurs. IRA can use bigger classes if it is still
233 more profitable than memory usage.
235 * Popping the allocnos from the stack and assigning them hard
236 registers. If IRA can not assign a hard register to an
237 allocno and the allocno is coalesced, IRA undoes the
238 coalescing and puts the uncoalesced allocnos onto the stack in
239 the hope that some such allocnos will get a hard register
240 separately. If IRA fails to assign hard register or memory
241 is more profitable for it, IRA spills the allocno. IRA
242 assigns the allocno the hard-register with minimal full
243 allocation cost which reflects the cost of usage of the
244 hard-register for the allocno and cost of usage of the
245 hard-register for allocnos conflicting with given allocno.
247 * Chaitin-Briggs coloring assigns as many pseudos as possible
248 to hard registers. After coloringh we try to improve
249 allocation with cost point of view. We improve the
250 allocation by spilling some allocnos and assigning the freed
251 hard registers to other allocnos if it decreases the overall
254 * After allocno assigning in the region, IRA modifies the hard
255 register and memory costs for the corresponding allocnos in
256 the subregions to reflect the cost of possible loads, stores,
257 or moves on the border of the region and its subregions.
258 When default regional allocation algorithm is used
259 (-fira-algorithm=mixed), IRA just propagates the assignment
260 for allocnos if the register pressure in the region for the
261 corresponding pressure class is less than number of available
262 hard registers for given pressure class.
264 o Spill/restore code moving. When IRA performs an allocation
265 by traversing regions in top-down order, it does not know what
266 happens below in the region tree. Therefore, sometimes IRA
267 misses opportunities to perform a better allocation. A simple
268 optimization tries to improve allocation in a region having
269 subregions and containing in another region. If the
270 corresponding allocnos in the subregion are spilled, it spills
271 the region allocno if it is profitable. The optimization
272 implements a simple iterative algorithm performing profitable
273 transformations while they are still possible. It is fast in
274 practice, so there is no real need for a better time complexity
277 o Code change. After coloring, two allocnos representing the
278 same pseudo-register outside and inside a region respectively
279 may be assigned to different locations (hard-registers or
280 memory). In this case IRA creates and uses a new
281 pseudo-register inside the region and adds code to move allocno
282 values on the region's borders. This is done during top-down
283 traversal of the regions (file ira-emit.c). In some
284 complicated cases IRA can create a new allocno to move allocno
285 values (e.g. when a swap of values stored in two hard-registers
286 is needed). At this stage, the new allocno is marked as
287 spilled. IRA still creates the pseudo-register and the moves
288 on the region borders even when both allocnos were assigned to
289 the same hard-register. If the reload pass spills a
290 pseudo-register for some reason, the effect will be smaller
291 because another allocno will still be in the hard-register. In
292 most cases, this is better then spilling both allocnos. If
293 reload does not change the allocation for the two
294 pseudo-registers, the trivial move will be removed by
295 post-reload optimizations. IRA does not generate moves for
296 allocnos assigned to the same hard register when the default
297 regional allocation algorithm is used and the register pressure
298 in the region for the corresponding pressure class is less than
299 number of available hard registers for given pressure class.
300 IRA also does some optimizations to remove redundant stores and
301 to reduce code duplication on the region borders.
303 o Flattening internal representation. After changing code, IRA
304 transforms its internal representation for several regions into
305 one region representation (file ira-build.c). This process is
306 called IR flattening. Such process is more complicated than IR
307 rebuilding would be, but is much faster.
309 o After IR flattening, IRA tries to assign hard registers to all
310 spilled allocnos. This is impelemented by a simple and fast
311 priority coloring algorithm (see function
312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
313 created during the code change pass can be assigned to hard
316 o At the end IRA calls the reload pass. The reload pass
317 communicates with IRA through several functions in file
318 ira-color.c to improve its decisions in
320 * sharing stack slots for the spilled pseudos based on IRA info
321 about pseudo-register conflicts.
323 * reassigning hard-registers to all spilled pseudos at the end
324 of each reload iteration.
326 * choosing a better hard-register to spill based on IRA info
327 about pseudo-register live ranges and the register pressure
328 in places where the pseudo-register lives.
330 IRA uses a lot of data representing the target processors. These
331 data are initilized in file ira.c.
333 If function has no loops (or the loops are ignored when
334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
335 coloring (only instead of separate pass of coalescing, we use hard
336 register preferencing). In such case, IRA works much faster
337 because many things are not made (like IR flattening, the
338 spill/restore optimization, and the code change).
340 Literature is worth to read for better understanding the code:
342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
343 Graph Coloring Register Allocation.
345 o David Callahan, Brian Koblenz. Register allocation via
346 hierarchical graph coloring.
348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
349 Coloring Register Allocation: A Study of the Chaitin-Briggs and
350 Callahan-Koblenz Algorithms.
352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
353 Register Allocation Based on Graph Fusion.
355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
356 Allocation for Irregular Architectures
358 o Vladimir Makarov. The Integrated Register Allocator for GCC.
360 o Vladimir Makarov. The top-down register allocator for irregular
361 register file architectures.
368 #include "coretypes.h"
378 #include "hard-reg-set.h"
379 #include "basic-block.h"
384 #include "tree-pass.h"
388 #include "diagnostic-core.h"
389 #include "function.h"
395 #include "rtl-iter.h"
396 #include "shrink-wrap.h"
398 struct target_ira default_target_ira
;
399 struct target_ira_int default_target_ira_int
;
400 #if SWITCHABLE_TARGET
401 struct target_ira
*this_target_ira
= &default_target_ira
;
402 struct target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
405 /* A modified value of flag `-fira-verbose' used internally. */
406 int internal_flag_ira_verbose
;
408 /* Dump file of the allocator if it is not NULL. */
411 /* The number of elements in the following array. */
412 int ira_spilled_reg_stack_slots_num
;
414 /* The following array contains info about spilled pseudo-registers
415 stack slots used in current function so far. */
416 struct ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
418 /* Correspondingly overall cost of the allocation, overall cost before
419 reload, cost of the allocnos assigned to hard-registers, cost of
420 the allocnos assigned to memory, cost of loads, stores and register
421 move insns generated for pseudo-register live range splitting (see
423 int ira_overall_cost
, overall_cost_before
;
424 int ira_reg_cost
, ira_mem_cost
;
425 int ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
426 int ira_move_loops_num
, ira_additional_jumps_num
;
428 /* All registers that can be eliminated. */
430 HARD_REG_SET eliminable_regset
;
432 /* Value of max_reg_num () before IRA work start. This value helps
433 us to recognize a situation when new pseudos were created during
435 static int max_regno_before_ira
;
437 /* Temporary hard reg set used for a different calculation. */
438 static HARD_REG_SET temp_hard_regset
;
440 #define last_mode_for_init_move_cost \
441 (this_target_ira_int->x_last_mode_for_init_move_cost)
444 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
446 setup_reg_mode_hard_regset (void)
448 int i
, m
, hard_regno
;
450 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
451 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
453 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
454 for (i
= hard_regno_nregs
[hard_regno
][m
] - 1; i
>= 0; i
--)
455 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
456 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
462 #define no_unit_alloc_regs \
463 (this_target_ira_int->x_no_unit_alloc_regs)
465 /* The function sets up the three arrays declared above. */
467 setup_class_hard_regs (void)
469 int cl
, i
, hard_regno
, n
;
470 HARD_REG_SET processed_hard_reg_set
;
472 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
473 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
475 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
476 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
477 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
478 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
480 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
481 ira_class_hard_reg_index
[cl
][i
] = -1;
483 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
485 #ifdef REG_ALLOC_ORDER
486 hard_regno
= reg_alloc_order
[i
];
490 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
492 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
493 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
494 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
497 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
498 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
501 ira_class_hard_regs_num
[cl
] = n
;
502 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
503 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
504 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
505 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
509 /* Set up global variables defining info about hard registers for the
510 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
511 that we can use the hard frame pointer for the allocation. */
513 setup_alloc_regs (bool use_hard_frame_p
)
515 #ifdef ADJUST_REG_ALLOC_ORDER
516 ADJUST_REG_ALLOC_ORDER
;
518 COPY_HARD_REG_SET (no_unit_alloc_regs
, fixed_reg_set
);
519 if (! use_hard_frame_p
)
520 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
521 setup_class_hard_regs ();
526 #define alloc_reg_class_subclasses \
527 (this_target_ira_int->x_alloc_reg_class_subclasses)
529 /* Initialize the table of subclasses of each reg class. */
531 setup_reg_subclasses (void)
534 HARD_REG_SET temp_hard_regset2
;
536 for (i
= 0; i
< N_REG_CLASSES
; i
++)
537 for (j
= 0; j
< N_REG_CLASSES
; j
++)
538 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
540 for (i
= 0; i
< N_REG_CLASSES
; i
++)
542 if (i
== (int) NO_REGS
)
545 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
546 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
547 if (hard_reg_set_empty_p (temp_hard_regset
))
549 for (j
= 0; j
< N_REG_CLASSES
; j
++)
554 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[j
]);
555 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
556 if (! hard_reg_set_subset_p (temp_hard_regset
,
559 p
= &alloc_reg_class_subclasses
[j
][0];
560 while (*p
!= LIM_REG_CLASSES
) p
++;
561 *p
= (enum reg_class
) i
;
568 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
570 setup_class_subset_and_memory_move_costs (void)
572 int cl
, cl2
, mode
, cost
;
573 HARD_REG_SET temp_hard_regset2
;
575 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
576 ira_memory_move_cost
[mode
][NO_REGS
][0]
577 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
578 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
580 if (cl
!= (int) NO_REGS
)
581 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
583 ira_max_memory_move_cost
[mode
][cl
][0]
584 = ira_memory_move_cost
[mode
][cl
][0]
585 = memory_move_cost ((enum machine_mode
) mode
,
586 (reg_class_t
) cl
, false);
587 ira_max_memory_move_cost
[mode
][cl
][1]
588 = ira_memory_move_cost
[mode
][cl
][1]
589 = memory_move_cost ((enum machine_mode
) mode
,
590 (reg_class_t
) cl
, true);
591 /* Costs for NO_REGS are used in cost calculation on the
592 1st pass when the preferred register classes are not
593 known yet. In this case we take the best scenario. */
594 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
595 > ira_memory_move_cost
[mode
][cl
][0])
596 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
597 = ira_memory_move_cost
[mode
][NO_REGS
][0]
598 = ira_memory_move_cost
[mode
][cl
][0];
599 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
600 > ira_memory_move_cost
[mode
][cl
][1])
601 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
602 = ira_memory_move_cost
[mode
][NO_REGS
][1]
603 = ira_memory_move_cost
[mode
][cl
][1];
606 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
607 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
609 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
610 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
611 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
612 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
613 ira_class_subset_p
[cl
][cl2
]
614 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
615 if (! hard_reg_set_empty_p (temp_hard_regset2
)
616 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
617 reg_class_contents
[cl
]))
618 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
620 cost
= ira_memory_move_cost
[mode
][cl2
][0];
621 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
622 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
623 cost
= ira_memory_move_cost
[mode
][cl2
][1];
624 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
625 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
628 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
629 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
631 ira_memory_move_cost
[mode
][cl
][0]
632 = ira_max_memory_move_cost
[mode
][cl
][0];
633 ira_memory_move_cost
[mode
][cl
][1]
634 = ira_max_memory_move_cost
[mode
][cl
][1];
636 setup_reg_subclasses ();
641 /* Define the following macro if allocation through malloc if
643 #define IRA_NO_OBSTACK
645 #ifndef IRA_NO_OBSTACK
646 /* Obstack used for storing all dynamic data (except bitmaps) of the
648 static struct obstack ira_obstack
;
651 /* Obstack used for storing all bitmaps of the IRA. */
652 static struct bitmap_obstack ira_bitmap_obstack
;
654 /* Allocate memory of size LEN for IRA data. */
656 ira_allocate (size_t len
)
660 #ifndef IRA_NO_OBSTACK
661 res
= obstack_alloc (&ira_obstack
, len
);
668 /* Free memory ADDR allocated for IRA data. */
670 ira_free (void *addr ATTRIBUTE_UNUSED
)
672 #ifndef IRA_NO_OBSTACK
680 /* Allocate and returns bitmap for IRA. */
682 ira_allocate_bitmap (void)
684 return BITMAP_ALLOC (&ira_bitmap_obstack
);
687 /* Free bitmap B allocated for IRA. */
689 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
696 /* Output information about allocation of all allocnos (except for
697 caps) into file F. */
699 ira_print_disposition (FILE *f
)
705 fprintf (f
, "Disposition:");
706 max_regno
= max_reg_num ();
707 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
708 for (a
= ira_regno_allocno_map
[i
];
710 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
715 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
716 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
717 fprintf (f
, "b%-3d", bb
->index
);
719 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
720 if (ALLOCNO_HARD_REGNO (a
) >= 0)
721 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
728 /* Outputs information about allocation of all allocnos into
731 ira_debug_disposition (void)
733 ira_print_disposition (stderr
);
738 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
739 register class containing stack registers or NO_REGS if there are
740 no stack registers. To find this class, we iterate through all
741 register pressure classes and choose the first register pressure
742 class containing all the stack registers and having the biggest
745 setup_stack_reg_pressure_class (void)
747 ira_stack_reg_pressure_class
= NO_REGS
;
752 HARD_REG_SET temp_hard_regset2
;
754 CLEAR_HARD_REG_SET (temp_hard_regset
);
755 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
756 SET_HARD_REG_BIT (temp_hard_regset
, i
);
758 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
760 cl
= ira_pressure_classes
[i
];
761 COPY_HARD_REG_SET (temp_hard_regset2
, temp_hard_regset
);
762 AND_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
763 size
= hard_reg_set_size (temp_hard_regset2
);
767 ira_stack_reg_pressure_class
= cl
;
774 /* Find pressure classes which are register classes for which we
775 calculate register pressure in IRA, register pressure sensitive
776 insn scheduling, and register pressure sensitive loop invariant
779 To make register pressure calculation easy, we always use
780 non-intersected register pressure classes. A move of hard
781 registers from one register pressure class is not more expensive
782 than load and store of the hard registers. Most likely an allocno
783 class will be a subset of a register pressure class and in many
784 cases a register pressure class. That makes usage of register
785 pressure classes a good approximation to find a high register
788 setup_pressure_classes (void)
790 int cost
, i
, n
, curr
;
792 enum reg_class pressure_classes
[N_REG_CLASSES
];
794 HARD_REG_SET temp_hard_regset2
;
798 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
800 if (ira_class_hard_regs_num
[cl
] == 0)
802 if (ira_class_hard_regs_num
[cl
] != 1
803 /* A register class without subclasses may contain a few
804 hard registers and movement between them is costly
805 (e.g. SPARC FPCC registers). We still should consider it
806 as a candidate for a pressure class. */
807 && alloc_reg_class_subclasses
[cl
][0] < cl
)
809 /* Check that the moves between any hard registers of the
810 current class are not more expensive for a legal mode
811 than load/store of the hard registers of the current
812 class. Such class is a potential candidate to be a
813 register pressure class. */
814 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
816 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
817 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
818 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
819 ira_prohibited_class_mode_regs
[cl
][m
]);
820 if (hard_reg_set_empty_p (temp_hard_regset
))
822 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
823 cost
= ira_register_move_cost
[m
][cl
][cl
];
824 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
825 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
828 if (m
>= NUM_MACHINE_MODES
)
833 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
834 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
835 /* Remove so far added pressure classes which are subset of the
836 current candidate class. Prefer GENERAL_REGS as a pressure
837 register class to another class containing the same
838 allocatable hard registers. We do this because machine
839 dependent cost hooks might give wrong costs for the latter
840 class but always give the right cost for the former class
842 for (i
= 0; i
< n
; i
++)
844 cl2
= pressure_classes
[i
];
845 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
846 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
847 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
848 && (! hard_reg_set_equal_p (temp_hard_regset
, temp_hard_regset2
)
849 || cl2
== (int) GENERAL_REGS
))
851 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
855 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
856 && (! hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
)
857 || cl
== (int) GENERAL_REGS
))
859 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
861 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
863 /* If the current candidate is a subset of a so far added
864 pressure class, don't add it to the list of the pressure
867 pressure_classes
[curr
++] = (enum reg_class
) cl
;
870 #ifdef ENABLE_IRA_CHECKING
872 HARD_REG_SET ignore_hard_regs
;
874 /* Check pressure classes correctness: here we check that hard
875 registers from all register pressure classes contains all hard
876 registers available for the allocation. */
877 CLEAR_HARD_REG_SET (temp_hard_regset
);
878 CLEAR_HARD_REG_SET (temp_hard_regset2
);
879 COPY_HARD_REG_SET (ignore_hard_regs
, no_unit_alloc_regs
);
880 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
882 /* For some targets (like MIPS with MD_REGS), there are some
883 classes with hard registers available for allocation but
884 not able to hold value of any mode. */
885 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
886 if (contains_reg_of_mode
[cl
][m
])
888 if (m
>= NUM_MACHINE_MODES
)
890 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
893 for (i
= 0; i
< n
; i
++)
894 if ((int) pressure_classes
[i
] == cl
)
896 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
898 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
900 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
901 /* Some targets (like SPARC with ICC reg) have alocatable regs
902 for which no reg class is defined. */
903 if (REGNO_REG_CLASS (i
) == NO_REGS
)
904 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
905 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
906 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
907 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
910 ira_pressure_classes_num
= 0;
911 for (i
= 0; i
< n
; i
++)
913 cl
= (int) pressure_classes
[i
];
914 ira_reg_pressure_class_p
[cl
] = true;
915 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
917 setup_stack_reg_pressure_class ();
920 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
921 whose register move cost between any registers of the class is the
922 same as for all its subclasses. We use the data to speed up the
923 2nd pass of calculations of allocno costs. */
925 setup_uniform_class_p (void)
929 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
931 ira_uniform_class_p
[cl
] = false;
932 if (ira_class_hard_regs_num
[cl
] == 0)
934 /* We can not use alloc_reg_class_subclasses here because move
935 cost hooks does not take into account that some registers are
936 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
937 is element of alloc_reg_class_subclasses for GENERAL_REGS
938 because SSE regs are unavailable. */
939 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
941 if (ira_class_hard_regs_num
[cl2
] == 0)
943 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
944 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
946 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
947 if (ira_register_move_cost
[m
][cl
][cl
]
948 != ira_register_move_cost
[m
][cl2
][cl2
])
951 if (m
< NUM_MACHINE_MODES
)
954 if (cl2
== LIM_REG_CLASSES
)
955 ira_uniform_class_p
[cl
] = true;
959 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
960 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
962 Target may have many subtargets and not all target hard regiters can
963 be used for allocation, e.g. x86 port in 32-bit mode can not use
964 hard registers introduced in x86-64 like r8-r15). Some classes
965 might have the same allocatable hard registers, e.g. INDEX_REGS
966 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
967 calculations efforts we introduce allocno classes which contain
968 unique non-empty sets of allocatable hard-registers.
970 Pseudo class cost calculation in ira-costs.c is very expensive.
971 Therefore we are trying to decrease number of classes involved in
972 such calculation. Register classes used in the cost calculation
973 are called important classes. They are allocno classes and other
974 non-empty classes whose allocatable hard register sets are inside
975 of an allocno class hard register set. From the first sight, it
976 looks like that they are just allocno classes. It is not true. In
977 example of x86-port in 32-bit mode, allocno classes will contain
978 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
979 registers are the same for the both classes). The important
980 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
981 because a machine description insn constraint may refers for
982 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
983 of the insn constraints. */
985 setup_allocno_and_important_classes (void)
989 HARD_REG_SET temp_hard_regset2
;
990 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
993 /* Collect classes which contain unique sets of allocatable hard
994 registers. Prefer GENERAL_REGS to other classes containing the
995 same set of hard registers. */
996 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
998 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
999 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1000 for (j
= 0; j
< n
; j
++)
1003 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
1004 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
1005 no_unit_alloc_regs
);
1006 if (hard_reg_set_equal_p (temp_hard_regset
,
1011 classes
[n
++] = (enum reg_class
) i
;
1012 else if (i
== GENERAL_REGS
)
1013 /* Prefer general regs. For i386 example, it means that
1014 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1015 (all of them consists of the same available hard
1017 classes
[j
] = (enum reg_class
) i
;
1019 classes
[n
] = LIM_REG_CLASSES
;
1021 /* Set up classes which can be used for allocnos as classes
1022 conatining non-empty unique sets of allocatable hard
1024 ira_allocno_classes_num
= 0;
1025 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1026 if (ira_class_hard_regs_num
[cl
] > 0)
1027 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1028 ira_important_classes_num
= 0;
1029 /* Add non-allocno classes containing to non-empty set of
1030 allocatable hard regs. */
1031 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1032 if (ira_class_hard_regs_num
[cl
] > 0)
1034 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1035 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1037 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1039 COPY_HARD_REG_SET (temp_hard_regset2
,
1040 reg_class_contents
[ira_allocno_classes
[j
]]);
1041 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1042 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1044 else if (hard_reg_set_subset_p (temp_hard_regset
,
1048 if (set_p
&& j
>= ira_allocno_classes_num
)
1049 ira_important_classes
[ira_important_classes_num
++]
1050 = (enum reg_class
) cl
;
1052 /* Now add allocno classes to the important classes. */
1053 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1054 ira_important_classes
[ira_important_classes_num
++]
1055 = ira_allocno_classes
[j
];
1056 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1058 ira_reg_allocno_class_p
[cl
] = false;
1059 ira_reg_pressure_class_p
[cl
] = false;
1061 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1062 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1063 setup_pressure_classes ();
1064 setup_uniform_class_p ();
1067 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1068 given by array CLASSES of length CLASSES_NUM. The function is used
1069 make translation any reg class to an allocno class or to an
1070 pressure class. This translation is necessary for some
1071 calculations when we can use only allocno or pressure classes and
1072 such translation represents an approximate representation of all
1075 The translation in case when allocatable hard register set of a
1076 given class is subset of allocatable hard register set of a class
1077 in CLASSES is pretty simple. We use smallest classes from CLASSES
1078 containing a given class. If allocatable hard register set of a
1079 given class is not a subset of any corresponding set of a class
1080 from CLASSES, we use the cheapest (with load/store point of view)
1081 class from CLASSES whose set intersects with given class set */
1083 setup_class_translate_array (enum reg_class
*class_translate
,
1084 int classes_num
, enum reg_class
*classes
)
1087 enum reg_class aclass
, best_class
, *cl_ptr
;
1088 int i
, cost
, min_cost
, best_cost
;
1090 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1091 class_translate
[cl
] = NO_REGS
;
1093 for (i
= 0; i
< classes_num
; i
++)
1095 aclass
= classes
[i
];
1096 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1097 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1099 if (class_translate
[cl
] == NO_REGS
)
1100 class_translate
[cl
] = aclass
;
1101 class_translate
[aclass
] = aclass
;
1103 /* For classes which are not fully covered by one of given classes
1104 (in other words covered by more one given class), use the
1106 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1108 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1110 best_class
= NO_REGS
;
1111 best_cost
= INT_MAX
;
1112 for (i
= 0; i
< classes_num
; i
++)
1114 aclass
= classes
[i
];
1115 COPY_HARD_REG_SET (temp_hard_regset
,
1116 reg_class_contents
[aclass
]);
1117 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1118 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1119 if (! hard_reg_set_empty_p (temp_hard_regset
))
1122 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1124 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1125 + ira_memory_move_cost
[mode
][aclass
][1]);
1126 if (min_cost
> cost
)
1129 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1131 best_class
= aclass
;
1132 best_cost
= min_cost
;
1136 class_translate
[cl
] = best_class
;
1140 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1141 IRA_PRESSURE_CLASS_TRANSLATE. */
1143 setup_class_translate (void)
1145 setup_class_translate_array (ira_allocno_class_translate
,
1146 ira_allocno_classes_num
, ira_allocno_classes
);
1147 setup_class_translate_array (ira_pressure_class_translate
,
1148 ira_pressure_classes_num
, ira_pressure_classes
);
1151 /* Order numbers of allocno classes in original target allocno class
1152 array, -1 for non-allocno classes. */
1153 static int allocno_class_order
[N_REG_CLASSES
];
1155 /* The function used to sort the important classes. */
1157 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1159 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1160 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1161 enum reg_class tcl1
, tcl2
;
1164 tcl1
= ira_allocno_class_translate
[cl1
];
1165 tcl2
= ira_allocno_class_translate
[cl2
];
1166 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1167 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1169 return (int) cl1
- (int) cl2
;
1172 /* For correct work of function setup_reg_class_relation we need to
1173 reorder important classes according to the order of their allocno
1174 classes. It places important classes containing the same
1175 allocatable hard register set adjacent to each other and allocno
1176 class with the allocatable hard register set right after the other
1177 important classes with the same set.
1179 In example from comments of function
1180 setup_allocno_and_important_classes, it places LEGACY_REGS and
1181 GENERAL_REGS close to each other and GENERAL_REGS is after
1184 reorder_important_classes (void)
1188 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1189 allocno_class_order
[i
] = -1;
1190 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1191 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1192 qsort (ira_important_classes
, ira_important_classes_num
,
1193 sizeof (enum reg_class
), comp_reg_classes_func
);
1194 for (i
= 0; i
< ira_important_classes_num
; i
++)
1195 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1198 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1199 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1200 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1201 please see corresponding comments in ira-int.h. */
1203 setup_reg_class_relations (void)
1205 int i
, cl1
, cl2
, cl3
;
1206 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1207 bool important_class_p
[N_REG_CLASSES
];
1209 memset (important_class_p
, 0, sizeof (important_class_p
));
1210 for (i
= 0; i
< ira_important_classes_num
; i
++)
1211 important_class_p
[ira_important_classes
[i
]] = true;
1212 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1214 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1215 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1217 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1218 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1219 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1220 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl1
]);
1221 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1222 COPY_HARD_REG_SET (temp_set2
, reg_class_contents
[cl2
]);
1223 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1224 if (hard_reg_set_empty_p (temp_hard_regset
)
1225 && hard_reg_set_empty_p (temp_set2
))
1227 /* The both classes have no allocatable hard registers
1228 -- take all class hard registers into account and use
1229 reg_class_subunion and reg_class_superunion. */
1232 cl3
= reg_class_subclasses
[cl1
][i
];
1233 if (cl3
== LIM_REG_CLASSES
)
1235 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1236 (enum reg_class
) cl3
))
1237 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1239 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1240 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1243 ira_reg_classes_intersect_p
[cl1
][cl2
]
1244 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1245 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1246 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1248 /* CL1 and CL2 are important classes and CL1 allocatable
1249 hard register set is inside of CL2 allocatable hard
1250 registers -- make CL1 a superset of CL2. */
1253 p
= &ira_reg_class_super_classes
[cl1
][0];
1254 while (*p
!= LIM_REG_CLASSES
)
1256 *p
++ = (enum reg_class
) cl2
;
1257 *p
= LIM_REG_CLASSES
;
1259 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1260 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1261 COPY_HARD_REG_SET (intersection_set
, reg_class_contents
[cl1
]);
1262 AND_HARD_REG_SET (intersection_set
, reg_class_contents
[cl2
]);
1263 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1264 COPY_HARD_REG_SET (union_set
, reg_class_contents
[cl1
]);
1265 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1266 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1267 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1269 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl3
]);
1270 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1271 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1273 /* CL3 allocatable hard register set is inside of
1274 intersection of allocatable hard register sets
1276 if (important_class_p
[cl3
])
1281 [(int) ira_reg_class_intersect
[cl1
][cl2
]]);
1282 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1283 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1284 /* If the allocatable hard register sets are
1285 the same, prefer GENERAL_REGS or the
1286 smallest class for debugging
1288 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1289 && (cl3
== GENERAL_REGS
1290 || ((ira_reg_class_intersect
[cl1
][cl2
]
1292 && hard_reg_set_subset_p
1293 (reg_class_contents
[cl3
],
1296 ira_reg_class_intersect
[cl1
][cl2
]])))))
1297 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1301 reg_class_contents
[(int) ira_reg_class_subset
[cl1
][cl2
]]);
1302 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1303 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1304 /* Ignore unavailable hard registers and prefer
1305 smallest class for debugging purposes. */
1306 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1307 && hard_reg_set_subset_p
1308 (reg_class_contents
[cl3
],
1310 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1311 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1313 if (important_class_p
[cl3
]
1314 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1316 /* CL3 allocatbale hard register set is inside of
1317 union of allocatable hard register sets of CL1
1321 reg_class_contents
[(int) ira_reg_class_subunion
[cl1
][cl2
]]);
1322 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1323 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1324 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1326 && (! hard_reg_set_equal_p (temp_set2
,
1328 || cl3
== GENERAL_REGS
1329 /* If the allocatable hard register sets are the
1330 same, prefer GENERAL_REGS or the smallest
1331 class for debugging purposes. */
1332 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1333 && hard_reg_set_subset_p
1334 (reg_class_contents
[cl3
],
1336 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1337 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1339 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1341 /* CL3 allocatable hard register set contains union
1342 of allocatable hard register sets of CL1 and
1346 reg_class_contents
[(int) ira_reg_class_superunion
[cl1
][cl2
]]);
1347 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1348 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1349 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1351 && (! hard_reg_set_equal_p (temp_set2
,
1353 || cl3
== GENERAL_REGS
1354 /* If the allocatable hard register sets are the
1355 same, prefer GENERAL_REGS or the smallest
1356 class for debugging purposes. */
1357 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1358 && hard_reg_set_subset_p
1359 (reg_class_contents
[cl3
],
1361 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1362 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1369 /* Output all unifrom and important classes into file F. */
1371 print_unform_and_important_classes (FILE *f
)
1373 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1376 fprintf (f
, "Uniform classes:\n");
1377 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1378 if (ira_uniform_class_p
[cl
])
1379 fprintf (f
, " %s", reg_class_names
[cl
]);
1380 fprintf (f
, "\nImportant classes:\n");
1381 for (i
= 0; i
< ira_important_classes_num
; i
++)
1382 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1386 /* Output all possible allocno or pressure classes and their
1387 translation map into file F. */
1389 print_translated_classes (FILE *f
, bool pressure_p
)
1391 int classes_num
= (pressure_p
1392 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1393 enum reg_class
*classes
= (pressure_p
1394 ? ira_pressure_classes
: ira_allocno_classes
);
1395 enum reg_class
*class_translate
= (pressure_p
1396 ? ira_pressure_class_translate
1397 : ira_allocno_class_translate
);
1398 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1401 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1402 for (i
= 0; i
< classes_num
; i
++)
1403 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1404 fprintf (f
, "\nClass translation:\n");
1405 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1406 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1407 reg_class_names
[class_translate
[i
]]);
1410 /* Output all possible allocno and translation classes and the
1411 translation maps into stderr. */
1413 ira_debug_allocno_classes (void)
1415 print_unform_and_important_classes (stderr
);
1416 print_translated_classes (stderr
, false);
1417 print_translated_classes (stderr
, true);
1420 /* Set up different arrays concerning class subsets, allocno and
1421 important classes. */
1423 find_reg_classes (void)
1425 setup_allocno_and_important_classes ();
1426 setup_class_translate ();
1427 reorder_important_classes ();
1428 setup_reg_class_relations ();
1433 /* Set up the array above. */
1435 setup_hard_regno_aclass (void)
1439 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1442 ira_hard_regno_allocno_class
[i
]
1443 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1445 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1449 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1450 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1452 cl
= ira_allocno_classes
[j
];
1453 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1455 ira_hard_regno_allocno_class
[i
] = cl
;
1465 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1467 setup_reg_class_nregs (void)
1471 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1473 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1474 ira_reg_class_max_nregs
[cl
][m
]
1475 = ira_reg_class_min_nregs
[cl
][m
]
1476 = targetm
.class_max_nregs ((reg_class_t
) cl
, (enum machine_mode
) m
);
1477 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1479 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1481 if (ira_reg_class_min_nregs
[cl2
][m
]
1482 < ira_reg_class_min_nregs
[cl
][m
])
1483 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1489 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1490 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1492 setup_prohibited_class_mode_regs (void)
1494 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1496 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1498 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1499 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1500 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1503 last_hard_regno
= -1;
1504 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1505 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1507 hard_regno
= ira_class_hard_regs
[cl
][k
];
1508 if (! HARD_REGNO_MODE_OK (hard_regno
, (enum machine_mode
) j
))
1509 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1511 else if (in_hard_reg_set_p (temp_hard_regset
,
1512 (enum machine_mode
) j
, hard_regno
))
1514 last_hard_regno
= hard_regno
;
1518 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1523 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1524 spanning from one register pressure class to another one. It is
1525 called after defining the pressure classes. */
1527 clarify_prohibited_class_mode_regs (void)
1529 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1531 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1532 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1534 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1535 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1537 hard_regno
= ira_class_hard_regs
[cl
][k
];
1538 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1540 nregs
= hard_regno_nregs
[hard_regno
][j
];
1541 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1543 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1547 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1548 for (nregs
-- ;nregs
>= 0; nregs
--)
1549 if (((enum reg_class
) pclass
1550 != ira_pressure_class_translate
[REGNO_REG_CLASS
1551 (hard_regno
+ nregs
)]))
1553 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1557 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1559 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1560 (enum machine_mode
) j
, hard_regno
);
1565 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1566 and IRA_MAY_MOVE_OUT_COST for MODE. */
1568 ira_init_register_move_cost (enum machine_mode mode
)
1570 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1571 bool all_match
= true;
1572 unsigned int cl1
, cl2
;
1574 ira_assert (ira_register_move_cost
[mode
] == NULL
1575 && ira_may_move_in_cost
[mode
] == NULL
1576 && ira_may_move_out_cost
[mode
] == NULL
);
1577 ira_assert (have_regs_of_mode
[mode
]);
1578 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1579 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1582 if (!contains_reg_of_mode
[cl1
][mode
]
1583 || !contains_reg_of_mode
[cl2
][mode
])
1585 if ((ira_reg_class_max_nregs
[cl1
][mode
]
1586 > ira_class_hard_regs_num
[cl1
])
1587 || (ira_reg_class_max_nregs
[cl2
][mode
]
1588 > ira_class_hard_regs_num
[cl2
]))
1591 cost
= (ira_memory_move_cost
[mode
][cl1
][0]
1592 + ira_memory_move_cost
[mode
][cl2
][1]) * 2;
1596 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1597 (enum reg_class
) cl2
);
1598 ira_assert (cost
< 65535);
1600 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1601 last_move_cost
[cl1
][cl2
] = cost
;
1603 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1605 ira_register_move_cost
[mode
]
1606 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1607 ira_may_move_in_cost
[mode
]
1608 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1609 ira_may_move_out_cost
[mode
]
1610 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1613 last_mode_for_init_move_cost
= mode
;
1614 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1615 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1616 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1617 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1618 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1621 enum reg_class
*p1
, *p2
;
1623 if (last_move_cost
[cl1
][cl2
] == 65535)
1625 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1626 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1627 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1631 cost
= last_move_cost
[cl1
][cl2
];
1633 for (p2
= ®_class_subclasses
[cl2
][0];
1634 *p2
!= LIM_REG_CLASSES
; p2
++)
1635 if (ira_class_hard_regs_num
[*p2
] > 0
1636 && (ira_reg_class_max_nregs
[*p2
][mode
]
1637 <= ira_class_hard_regs_num
[*p2
]))
1638 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1640 for (p1
= ®_class_subclasses
[cl1
][0];
1641 *p1
!= LIM_REG_CLASSES
; p1
++)
1642 if (ira_class_hard_regs_num
[*p1
] > 0
1643 && (ira_reg_class_max_nregs
[*p1
][mode
]
1644 <= ira_class_hard_regs_num
[*p1
]))
1645 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1647 ira_assert (cost
<= 65535);
1648 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1650 if (ira_class_subset_p
[cl1
][cl2
])
1651 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1653 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1655 if (ira_class_subset_p
[cl2
][cl1
])
1656 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1658 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1665 /* This is called once during compiler work. It sets up
1666 different arrays whose values don't depend on the compiled
1669 ira_init_once (void)
1671 ira_init_costs_once ();
1675 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1676 ira_may_move_out_cost for each mode. */
1678 free_register_move_costs (void)
1682 /* Reset move_cost and friends, making sure we only free shared
1683 table entries once. */
1684 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1685 if (ira_register_move_cost
[mode
])
1688 i
< mode
&& (ira_register_move_cost
[i
]
1689 != ira_register_move_cost
[mode
]);
1694 free (ira_register_move_cost
[mode
]);
1695 free (ira_may_move_in_cost
[mode
]);
1696 free (ira_may_move_out_cost
[mode
]);
1699 memset (ira_register_move_cost
, 0, sizeof ira_register_move_cost
);
1700 memset (ira_may_move_in_cost
, 0, sizeof ira_may_move_in_cost
);
1701 memset (ira_may_move_out_cost
, 0, sizeof ira_may_move_out_cost
);
1702 last_mode_for_init_move_cost
= -1;
1705 /* This is called every time when register related information is
1710 free_register_move_costs ();
1711 setup_reg_mode_hard_regset ();
1712 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1713 setup_class_subset_and_memory_move_costs ();
1714 setup_reg_class_nregs ();
1715 setup_prohibited_class_mode_regs ();
1716 find_reg_classes ();
1717 clarify_prohibited_class_mode_regs ();
1718 setup_hard_regno_aclass ();
1722 /* Function called once at the end of compiler work. */
1724 ira_finish_once (void)
1726 ira_finish_costs_once ();
1727 free_register_move_costs ();
1732 #define ira_prohibited_mode_move_regs_initialized_p \
1733 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1735 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1737 setup_prohibited_mode_move_regs (void)
1740 rtx test_reg1
, test_reg2
, move_pat
;
1741 rtx_insn
*move_insn
;
1743 if (ira_prohibited_mode_move_regs_initialized_p
)
1745 ira_prohibited_mode_move_regs_initialized_p
= true;
1746 test_reg1
= gen_rtx_REG (VOIDmode
, 0);
1747 test_reg2
= gen_rtx_REG (VOIDmode
, 0);
1748 move_pat
= gen_rtx_SET (VOIDmode
, test_reg1
, test_reg2
);
1749 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, move_pat
, 0, -1, 0);
1750 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1752 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1753 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1755 if (! HARD_REGNO_MODE_OK (j
, (enum machine_mode
) i
))
1757 SET_REGNO_RAW (test_reg1
, j
);
1758 PUT_MODE (test_reg1
, (enum machine_mode
) i
);
1759 SET_REGNO_RAW (test_reg2
, j
);
1760 PUT_MODE (test_reg2
, (enum machine_mode
) i
);
1761 INSN_CODE (move_insn
) = -1;
1762 recog_memoized (move_insn
);
1763 if (INSN_CODE (move_insn
) < 0)
1765 extract_insn (move_insn
);
1766 if (! constrain_operands (1))
1768 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1775 /* Setup possible alternatives in ALTS for INSN. */
1777 ira_setup_alts (rtx_insn
*insn
, HARD_REG_SET
&alts
)
1779 /* MAP nalt * nop -> start of constraints for given operand and
1781 static vec
<const char *> insn_constraints
;
1786 int commutative
= -1;
1788 extract_insn (insn
);
1789 CLEAR_HARD_REG_SET (alts
);
1790 insn_constraints
.release ();
1791 insn_constraints
.safe_grow_cleared (recog_data
.n_operands
1792 * recog_data
.n_alternatives
+ 1);
1793 /* Check that the hard reg set is enough for holding all
1794 alternatives. It is hard to imagine the situation when the
1795 assertion is wrong. */
1796 ira_assert (recog_data
.n_alternatives
1797 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE
) * CHAR_BIT
,
1798 FIRST_PSEUDO_REGISTER
));
1799 for (curr_swapped
= false;; curr_swapped
= true)
1801 /* Calculate some data common for all alternatives to speed up the
1803 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1805 for (nalt
= 0, p
= recog_data
.constraints
[nop
];
1806 nalt
< recog_data
.n_alternatives
;
1809 insn_constraints
[nop
* recog_data
.n_alternatives
+ nalt
] = p
;
1810 while (*p
&& *p
!= ',')
1816 for (nalt
= 0; nalt
< recog_data
.n_alternatives
; nalt
++)
1818 if (!TEST_BIT (recog_data
.enabled_alternatives
, nalt
)
1819 || TEST_HARD_REG_BIT (alts
, nalt
))
1822 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1826 op
= recog_data
.operand
[nop
];
1827 p
= insn_constraints
[nop
* recog_data
.n_alternatives
+ nalt
];
1828 if (*p
== 0 || *p
== ',')
1832 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
1842 /* We only support one commutative marker, the
1843 first one. We already set commutative
1845 if (commutative
< 0)
1849 case '0': case '1': case '2': case '3': case '4':
1850 case '5': case '6': case '7': case '8': case '9':
1860 enum constraint_num cn
= lookup_constraint (p
);
1861 switch (get_constraint_type (cn
))
1864 if (reg_class_for_constraint (cn
) != NO_REGS
)
1869 if (CONST_INT_P (op
)
1870 && (insn_const_int_ok_for_constraint
1880 if (constraint_satisfied_p (op
, cn
))
1887 while (p
+= len
, c
);
1892 if (nop
>= recog_data
.n_operands
)
1893 SET_HARD_REG_BIT (alts
, nalt
);
1895 if (commutative
< 0)
1899 op
= recog_data
.operand
[commutative
];
1900 recog_data
.operand
[commutative
] = recog_data
.operand
[commutative
+ 1];
1901 recog_data
.operand
[commutative
+ 1] = op
;
1906 /* Return the number of the output non-early clobber operand which
1907 should be the same in any case as operand with number OP_NUM (or
1908 negative value if there is no such operand). The function takes
1909 only really possible alternatives into consideration. */
1911 ira_get_dup_out_num (int op_num
, HARD_REG_SET
&alts
)
1913 int curr_alt
, c
, original
, dup
;
1914 bool ignore_p
, use_commut_op_p
;
1917 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
1919 /* We should find duplications only for input operands. */
1920 if (recog_data
.operand_type
[op_num
] != OP_IN
)
1922 str
= recog_data
.constraints
[op_num
];
1923 use_commut_op_p
= false;
1926 rtx op
= recog_data
.operand
[op_num
];
1928 for (curr_alt
= 0, ignore_p
= !TEST_HARD_REG_BIT (alts
, curr_alt
),
1939 ignore_p
= !TEST_HARD_REG_BIT (alts
, curr_alt
);
1941 else if (! ignore_p
)
1948 enum constraint_num cn
= lookup_constraint (str
);
1949 enum reg_class cl
= reg_class_for_constraint (cn
);
1951 && !targetm
.class_likely_spilled_p (cl
))
1953 if (constraint_satisfied_p (op
, cn
))
1958 case '0': case '1': case '2': case '3': case '4':
1959 case '5': case '6': case '7': case '8': case '9':
1960 if (original
!= -1 && original
!= c
)
1965 str
+= CONSTRAINT_LEN (c
, str
);
1970 for (ignore_p
= false, str
= recog_data
.constraints
[original
- '0'];
1978 else if (*str
== '#')
1980 else if (! ignore_p
)
1983 dup
= original
- '0';
1984 /* It is better ignore an alternative with early clobber. */
1985 else if (*str
== '&')
1991 if (use_commut_op_p
)
1993 use_commut_op_p
= true;
1994 if (recog_data
.constraints
[op_num
][0] == '%')
1995 str
= recog_data
.constraints
[op_num
+ 1];
1996 else if (op_num
> 0 && recog_data
.constraints
[op_num
- 1][0] == '%')
1997 str
= recog_data
.constraints
[op_num
- 1];
2006 /* Search forward to see if the source register of a copy insn dies
2007 before either it or the destination register is modified, but don't
2008 scan past the end of the basic block. If so, we can replace the
2009 source with the destination and let the source die in the copy
2012 This will reduce the number of registers live in that range and may
2013 enable the destination and the source coalescing, thus often saving
2014 one register in addition to a register-register copy. */
2017 decrease_live_ranges_number (void)
2021 rtx set
, src
, dest
, dest_death
, q
, note
;
2025 if (! flag_expensive_optimizations
)
2029 fprintf (ira_dump_file
, "Starting decreasing number of live ranges...\n");
2031 FOR_EACH_BB_FN (bb
, cfun
)
2032 FOR_BB_INSNS (bb
, insn
)
2034 set
= single_set (insn
);
2037 src
= SET_SRC (set
);
2038 dest
= SET_DEST (set
);
2039 if (! REG_P (src
) || ! REG_P (dest
)
2040 || find_reg_note (insn
, REG_DEAD
, src
))
2042 sregno
= REGNO (src
);
2043 dregno
= REGNO (dest
);
2045 /* We don't want to mess with hard regs if register classes
2047 if (sregno
== dregno
2048 || (targetm
.small_register_classes_for_mode_p (GET_MODE (src
))
2049 && (sregno
< FIRST_PSEUDO_REGISTER
2050 || dregno
< FIRST_PSEUDO_REGISTER
))
2051 /* We don't see all updates to SP if they are in an
2052 auto-inc memory reference, so we must disallow this
2053 optimization on them. */
2054 || sregno
== STACK_POINTER_REGNUM
2055 || dregno
== STACK_POINTER_REGNUM
)
2058 dest_death
= NULL_RTX
;
2060 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
2064 if (BLOCK_FOR_INSN (p
) != bb
)
2067 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
2068 /* If SRC is an asm-declared register, it must not be
2069 replaced in any asm. Unfortunately, the REG_EXPR
2070 tree for the asm variable may be absent in the SRC
2071 rtx, so we can't check the actual register
2072 declaration easily (the asm operand will have it,
2073 though). To avoid complicating the test for a rare
2074 case, we just don't perform register replacement
2075 for a hard reg mentioned in an asm. */
2076 || (sregno
< FIRST_PSEUDO_REGISTER
2077 && asm_noperands (PATTERN (p
)) >= 0
2078 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
2079 /* Don't change hard registers used by a call. */
2080 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
2081 && find_reg_fusage (p
, USE
, src
))
2082 /* Don't change a USE of a register. */
2083 || (GET_CODE (PATTERN (p
)) == USE
2084 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
2087 /* See if all of SRC dies in P. This test is slightly
2088 more conservative than it needs to be. */
2089 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
))
2090 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
2094 /* We can do the optimization. Scan forward from INSN
2095 again, replacing regs as we go. Set FAILED if a
2096 replacement can't be done. In that case, we can't
2097 move the death note for SRC. This should be
2100 /* Set to stop at next insn. */
2101 for (q
= next_real_insn (insn
);
2102 q
!= next_real_insn (p
);
2103 q
= next_real_insn (q
))
2105 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
2107 /* If SRC is a hard register, we might miss
2108 some overlapping registers with
2109 validate_replace_rtx, so we would have to
2110 undo it. We can't if DEST is present in
2111 the insn, so fail in that combination of
2113 if (sregno
< FIRST_PSEUDO_REGISTER
2114 && reg_mentioned_p (dest
, PATTERN (q
)))
2117 /* Attempt to replace all uses. */
2118 else if (!validate_replace_rtx (src
, dest
, q
))
2121 /* If this succeeded, but some part of the
2122 register is still present, undo the
2124 else if (sregno
< FIRST_PSEUDO_REGISTER
2125 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
2127 validate_replace_rtx (dest
, src
, q
);
2132 /* If DEST dies here, remove the death note and
2133 save it for later. Make sure ALL of DEST dies
2134 here; again, this is overly conservative. */
2136 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)))
2138 if (GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
2139 remove_note (q
, dest_death
);
2150 /* Move death note of SRC from P to INSN. */
2151 remove_note (p
, note
);
2152 XEXP (note
, 1) = REG_NOTES (insn
);
2153 REG_NOTES (insn
) = note
;
2156 /* DEST is also dead if INSN has a REG_UNUSED note for
2160 = find_regno_note (insn
, REG_UNUSED
, dregno
)))
2162 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
2163 remove_note (insn
, dest_death
);
2166 /* Put death note of DEST on P if we saw it die. */
2169 XEXP (dest_death
, 1) = REG_NOTES (p
);
2170 REG_NOTES (p
) = dest_death
;
2175 /* If SRC is a hard register which is set or killed in
2176 some other way, we can't do this optimization. */
2177 else if (sregno
< FIRST_PSEUDO_REGISTER
&& dead_or_set_p (p
, src
))
2185 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
2187 ira_bad_reload_regno_1 (int regno
, rtx x
)
2191 enum reg_class pref
;
2193 /* We only deal with pseudo regs. */
2194 if (! x
|| GET_CODE (x
) != REG
)
2197 x_regno
= REGNO (x
);
2198 if (x_regno
< FIRST_PSEUDO_REGISTER
)
2201 /* If the pseudo prefers REGNO explicitly, then do not consider
2202 REGNO a bad spill choice. */
2203 pref
= reg_preferred_class (x_regno
);
2204 if (reg_class_size
[pref
] == 1)
2205 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
2207 /* If the pseudo conflicts with REGNO, then we consider REGNO a
2208 poor choice for a reload regno. */
2209 a
= ira_regno_allocno_map
[x_regno
];
2210 n
= ALLOCNO_NUM_OBJECTS (a
);
2211 for (i
= 0; i
< n
; i
++)
2213 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2214 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
2220 /* Return nonzero if REGNO is a particularly bad choice for reloading
2223 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
2225 return (ira_bad_reload_regno_1 (regno
, in
)
2226 || ira_bad_reload_regno_1 (regno
, out
));
2229 /* Add register clobbers from asm statements. */
2231 compute_regs_asm_clobbered (void)
2235 FOR_EACH_BB_FN (bb
, cfun
)
2238 FOR_BB_INSNS_REVERSE (bb
, insn
)
2242 if (NONDEBUG_INSN_P (insn
) && extract_asm_operands (PATTERN (insn
)))
2243 FOR_EACH_INSN_DEF (def
, insn
)
2245 unsigned int dregno
= DF_REF_REGNO (def
);
2246 if (HARD_REGISTER_NUM_P (dregno
))
2247 add_to_hard_reg_set (&crtl
->asm_clobbers
,
2248 GET_MODE (DF_REF_REAL_REG (def
)),
2256 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and
2259 ira_setup_eliminable_regset (void)
2261 #ifdef ELIMINABLE_REGS
2263 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2265 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
2266 sp for alloca. So we can't eliminate the frame pointer in that
2267 case. At some point, we should improve this by emitting the
2268 sp-adjusting insns for this case. */
2269 frame_pointer_needed
2270 = (! flag_omit_frame_pointer
2271 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
2272 /* We need the frame pointer to catch stack overflow exceptions
2273 if the stack pointer is moving. */
2274 || (flag_stack_check
&& STACK_CHECK_MOVING_SP
)
2275 || crtl
->accesses_prior_frames
2276 || (SUPPORTS_STACK_ALIGNMENT
&& crtl
->stack_realign_needed
)
2277 /* We need a frame pointer for all Cilk Plus functions that use
2279 || (flag_cilkplus
&& cfun
->is_cilk_function
)
2280 || targetm
.frame_pointer_required ());
2282 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting
2283 RTL is very small. So if we use frame pointer for RA and RTL
2284 actually prevents this, we will spill pseudos assigned to the
2285 frame pointer in LRA. */
2287 if (frame_pointer_needed
)
2288 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2290 COPY_HARD_REG_SET (ira_no_alloc_regs
, no_unit_alloc_regs
);
2291 CLEAR_HARD_REG_SET (eliminable_regset
);
2293 compute_regs_asm_clobbered ();
2295 /* Build the regset of all eliminable registers and show we can't
2296 use those that we already know won't be eliminated. */
2297 #ifdef ELIMINABLE_REGS
2298 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2301 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
2302 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
2304 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
2306 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
2309 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
2311 else if (cannot_elim
)
2312 error ("%s cannot be used in asm here",
2313 reg_names
[eliminables
[i
].from
]);
2315 df_set_regs_ever_live (eliminables
[i
].from
, true);
2317 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2318 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2320 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
2321 if (frame_pointer_needed
)
2322 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
2324 else if (frame_pointer_needed
)
2325 error ("%s cannot be used in asm here",
2326 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
2328 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2332 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2334 SET_HARD_REG_BIT (eliminable_regset
, FRAME_POINTER_REGNUM
);
2335 if (frame_pointer_needed
)
2336 SET_HARD_REG_BIT (ira_no_alloc_regs
, FRAME_POINTER_REGNUM
);
2338 else if (frame_pointer_needed
)
2339 error ("%s cannot be used in asm here", reg_names
[FRAME_POINTER_REGNUM
]);
2341 df_set_regs_ever_live (FRAME_POINTER_REGNUM
, true);
2347 /* Vector of substitutions of register numbers,
2348 used to map pseudo regs into hardware regs.
2349 This is set up as a result of register allocation.
2350 Element N is the hard reg assigned to pseudo reg N,
2351 or is -1 if no hard reg was assigned.
2352 If N is a hard reg number, element N is N. */
2353 short *reg_renumber
;
2355 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
2356 the allocation found by IRA. */
2358 setup_reg_renumber (void)
2360 int regno
, hard_regno
;
2362 ira_allocno_iterator ai
;
2364 caller_save_needed
= 0;
2365 FOR_EACH_ALLOCNO (a
, ai
)
2367 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
2369 /* There are no caps at this point. */
2370 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
2371 if (! ALLOCNO_ASSIGNED_P (a
))
2372 /* It can happen if A is not referenced but partially anticipated
2373 somewhere in a region. */
2374 ALLOCNO_ASSIGNED_P (a
) = true;
2375 ira_free_allocno_updated_costs (a
);
2376 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2377 regno
= ALLOCNO_REGNO (a
);
2378 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
2379 if (hard_regno
>= 0)
2382 enum reg_class pclass
;
2385 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
2386 nwords
= ALLOCNO_NUM_OBJECTS (a
);
2387 for (i
= 0; i
< nwords
; i
++)
2389 obj
= ALLOCNO_OBJECT (a
, i
);
2390 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
2391 reg_class_contents
[pclass
]);
2393 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
2394 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
2397 ira_assert (!optimize
|| flag_caller_saves
2398 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
2399 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2400 || regno
>= ira_reg_equiv_len
2401 || ira_equiv_no_lvalue_p (regno
));
2402 caller_save_needed
= 1;
2408 /* Set up allocno assignment flags for further allocation
2411 setup_allocno_assignment_flags (void)
2415 ira_allocno_iterator ai
;
2417 FOR_EACH_ALLOCNO (a
, ai
)
2419 if (! ALLOCNO_ASSIGNED_P (a
))
2420 /* It can happen if A is not referenced but partially anticipated
2421 somewhere in a region. */
2422 ira_free_allocno_updated_costs (a
);
2423 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2424 /* Don't assign hard registers to allocnos which are destination
2425 of removed store at the end of loop. It has no sense to keep
2426 the same value in different hard registers. It is also
2427 impossible to assign hard registers correctly to such
2428 allocnos because the cost info and info about intersected
2429 calls are incorrect for them. */
2430 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2431 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2432 || (ALLOCNO_MEMORY_COST (a
)
2433 - ALLOCNO_CLASS_COST (a
)) < 0);
2436 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2437 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2441 /* Evaluate overall allocation cost and the costs for using hard
2442 registers and memory for allocnos. */
2444 calculate_allocation_cost (void)
2446 int hard_regno
, cost
;
2448 ira_allocno_iterator ai
;
2450 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2451 FOR_EACH_ALLOCNO (a
, ai
)
2453 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2454 ira_assert (hard_regno
< 0
2455 || (ira_hard_reg_in_set_p
2456 (hard_regno
, ALLOCNO_MODE (a
),
2457 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2460 cost
= ALLOCNO_MEMORY_COST (a
);
2461 ira_mem_cost
+= cost
;
2463 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2465 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2466 [ira_class_hard_reg_index
2467 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2468 ira_reg_cost
+= cost
;
2472 cost
= ALLOCNO_CLASS_COST (a
);
2473 ira_reg_cost
+= cost
;
2475 ira_overall_cost
+= cost
;
2478 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2480 fprintf (ira_dump_file
,
2481 "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n",
2482 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2483 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2484 fprintf (ira_dump_file
, "+++ move loops %d, new jumps %d\n",
2485 ira_move_loops_num
, ira_additional_jumps_num
);
2490 #ifdef ENABLE_IRA_CHECKING
2491 /* Check the correctness of the allocation. We do need this because
2492 of complicated code to transform more one region internal
2493 representation into one region representation. */
2495 check_allocation (void)
2498 int hard_regno
, nregs
, conflict_nregs
;
2499 ira_allocno_iterator ai
;
2501 FOR_EACH_ALLOCNO (a
, ai
)
2503 int n
= ALLOCNO_NUM_OBJECTS (a
);
2506 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2507 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2509 nregs
= hard_regno_nregs
[hard_regno
][ALLOCNO_MODE (a
)];
2511 /* We allocated a single hard register. */
2514 /* We allocated multiple hard registers, and we will test
2515 conflicts in a granularity of single hard regs. */
2518 for (i
= 0; i
< n
; i
++)
2520 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2521 ira_object_t conflict_obj
;
2522 ira_object_conflict_iterator oci
;
2523 int this_regno
= hard_regno
;
2526 if (REG_WORDS_BIG_ENDIAN
)
2527 this_regno
+= n
- i
- 1;
2531 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2533 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2534 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2535 if (conflict_hard_regno
< 0)
2540 [conflict_hard_regno
][ALLOCNO_MODE (conflict_a
)]);
2542 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2543 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2545 if (REG_WORDS_BIG_ENDIAN
)
2546 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2547 - OBJECT_SUBWORD (conflict_obj
) - 1);
2549 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2553 if ((conflict_hard_regno
<= this_regno
2554 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2555 || (this_regno
<= conflict_hard_regno
2556 && conflict_hard_regno
< this_regno
+ nregs
))
2558 fprintf (stderr
, "bad allocation for %d and %d\n",
2559 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2568 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2569 be already calculated. */
2571 setup_reg_equiv_init (void)
2574 int max_regno
= max_reg_num ();
2576 for (i
= 0; i
< max_regno
; i
++)
2577 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2580 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2581 are insns which were generated for such movement. It is assumed
2582 that FROM_REGNO and TO_REGNO always have the same value at the
2583 point of any move containing such registers. This function is used
2584 to update equiv info for register shuffles on the region borders
2585 and for caller save/restore insns. */
2587 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx_insn
*insns
)
2592 if (! ira_reg_equiv
[from_regno
].defined_p
2593 && (! ira_reg_equiv
[to_regno
].defined_p
2594 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2595 && ! MEM_READONLY_P (x
))))
2598 if (NEXT_INSN (insn
) != NULL_RTX
)
2600 if (! ira_reg_equiv
[to_regno
].defined_p
)
2602 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2605 ira_reg_equiv
[to_regno
].defined_p
= false;
2606 ira_reg_equiv
[to_regno
].memory
2607 = ira_reg_equiv
[to_regno
].constant
2608 = ira_reg_equiv
[to_regno
].invariant
2609 = ira_reg_equiv
[to_regno
].init_insns
= NULL
;
2610 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2611 fprintf (ira_dump_file
,
2612 " Invalidating equiv info for reg %d\n", to_regno
);
2615 /* It is possible that FROM_REGNO still has no equivalence because
2616 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2617 insn was not processed yet. */
2618 if (ira_reg_equiv
[from_regno
].defined_p
)
2620 ira_reg_equiv
[to_regno
].defined_p
= true;
2621 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2623 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2624 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2625 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2626 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2627 ira_reg_equiv
[to_regno
].memory
= x
;
2628 if (! MEM_READONLY_P (x
))
2629 /* We don't add the insn to insn init list because memory
2630 equivalence is just to say what memory is better to use
2631 when the pseudo is spilled. */
2634 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2636 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2637 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2638 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2639 ira_reg_equiv
[to_regno
].constant
= x
;
2643 x
= ira_reg_equiv
[from_regno
].invariant
;
2644 ira_assert (x
!= NULL_RTX
);
2645 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2646 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2647 ira_reg_equiv
[to_regno
].invariant
= x
;
2649 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2651 note
= set_unique_reg_note (insn
, REG_EQUIV
, x
);
2652 gcc_assert (note
!= NULL_RTX
);
2653 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2655 fprintf (ira_dump_file
,
2656 " Adding equiv note to insn %u for reg %d ",
2657 INSN_UID (insn
), to_regno
);
2658 dump_value_slim (ira_dump_file
, x
, 1);
2659 fprintf (ira_dump_file
, "\n");
2663 ira_reg_equiv
[to_regno
].init_insns
2664 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2665 ira_reg_equiv
[to_regno
].init_insns
);
2666 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2667 fprintf (ira_dump_file
,
2668 " Adding equiv init move insn %u to reg %d\n",
2669 INSN_UID (insn
), to_regno
);
2672 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2675 fix_reg_equiv_init (void)
2677 int max_regno
= max_reg_num ();
2678 int i
, new_regno
, max
;
2679 rtx x
, prev
, next
, insn
, set
;
2681 if (max_regno_before_ira
< max_regno
)
2683 max
= vec_safe_length (reg_equivs
);
2685 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2686 for (prev
= NULL_RTX
, x
= reg_equiv_init (i
);
2692 set
= single_set (as_a
<rtx_insn
*> (insn
));
2693 ira_assert (set
!= NULL_RTX
2694 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2695 if (REG_P (SET_DEST (set
))
2696 && ((int) REGNO (SET_DEST (set
)) == i
2697 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2698 new_regno
= REGNO (SET_DEST (set
));
2699 else if (REG_P (SET_SRC (set
))
2700 && ((int) REGNO (SET_SRC (set
)) == i
2701 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2702 new_regno
= REGNO (SET_SRC (set
));
2709 /* Remove the wrong list element. */
2710 if (prev
== NULL_RTX
)
2711 reg_equiv_init (i
) = next
;
2713 XEXP (prev
, 1) = next
;
2714 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2715 reg_equiv_init (new_regno
) = x
;
2721 #ifdef ENABLE_IRA_CHECKING
2722 /* Print redundant memory-memory copies. */
2724 print_redundant_copies (void)
2728 ira_copy_t cp
, next_cp
;
2729 ira_allocno_iterator ai
;
2731 FOR_EACH_ALLOCNO (a
, ai
)
2733 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2736 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2737 if (hard_regno
>= 0)
2739 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2741 next_cp
= cp
->next_first_allocno_copy
;
2744 next_cp
= cp
->next_second_allocno_copy
;
2745 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2746 && cp
->insn
!= NULL_RTX
2747 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2748 fprintf (ira_dump_file
,
2749 " Redundant move from %d(freq %d):%d\n",
2750 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2756 /* Setup preferred and alternative classes for new pseudo-registers
2757 created by IRA starting with START. */
2759 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2762 int max_regno
= max_reg_num ();
2764 for (i
= start
; i
< max_regno
; i
++)
2766 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2767 ira_assert (i
!= old_regno
);
2768 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2769 reg_alternate_class (old_regno
),
2770 reg_allocno_class (old_regno
));
2771 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2772 fprintf (ira_dump_file
,
2773 " New r%d: setting preferred %s, alternative %s\n",
2774 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2775 reg_class_names
[reg_alternate_class (old_regno
)]);
2780 /* The number of entries allocated in teg_info. */
2781 static int allocated_reg_info_size
;
2783 /* Regional allocation can create new pseudo-registers. This function
2784 expands some arrays for pseudo-registers. */
2786 expand_reg_info (void)
2789 int size
= max_reg_num ();
2792 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2793 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2794 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2795 allocated_reg_info_size
= size
;
2798 /* Return TRUE if there is too high register pressure in the function.
2799 It is used to decide when stack slot sharing is worth to do. */
2801 too_high_register_pressure_p (void)
2804 enum reg_class pclass
;
2806 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2808 pclass
= ira_pressure_classes
[i
];
2809 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2817 /* Indicate that hard register number FROM was eliminated and replaced with
2818 an offset from hard register number TO. The status of hard registers live
2819 at the start of a basic block is updated by replacing a use of FROM with
2823 mark_elimination (int from
, int to
)
2828 FOR_EACH_BB_FN (bb
, cfun
)
2831 if (bitmap_bit_p (r
, from
))
2833 bitmap_clear_bit (r
, from
);
2834 bitmap_set_bit (r
, to
);
2838 r
= DF_LIVE_IN (bb
);
2839 if (bitmap_bit_p (r
, from
))
2841 bitmap_clear_bit (r
, from
);
2842 bitmap_set_bit (r
, to
);
2849 /* The length of the following array. */
2850 int ira_reg_equiv_len
;
2852 /* Info about equiv. info for each register. */
2853 struct ira_reg_equiv_s
*ira_reg_equiv
;
2855 /* Expand ira_reg_equiv if necessary. */
2857 ira_expand_reg_equiv (void)
2859 int old
= ira_reg_equiv_len
;
2861 if (ira_reg_equiv_len
> max_reg_num ())
2863 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2865 = (struct ira_reg_equiv_s
*) xrealloc (ira_reg_equiv
,
2867 * sizeof (struct ira_reg_equiv_s
));
2868 gcc_assert (old
< ira_reg_equiv_len
);
2869 memset (ira_reg_equiv
+ old
, 0,
2870 sizeof (struct ira_reg_equiv_s
) * (ira_reg_equiv_len
- old
));
2874 init_reg_equiv (void)
2876 ira_reg_equiv_len
= 0;
2877 ira_reg_equiv
= NULL
;
2878 ira_expand_reg_equiv ();
2882 finish_reg_equiv (void)
2884 free (ira_reg_equiv
);
2891 /* Set when a REG_EQUIV note is found or created. Use to
2892 keep track of what memory accesses might be created later,
2896 /* The list of each instruction which initializes this register. */
2898 /* Loop depth is used to recognize equivalences which appear
2899 to be present within the same loop (or in an inner loop). */
2901 /* Nonzero if this had a preexisting REG_EQUIV note. */
2902 int is_arg_equivalence
;
2903 /* Set when an attempt should be made to replace a register
2904 with the associated src_p entry. */
2908 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2909 structure for that register. */
2910 static struct equivalence
*reg_equiv
;
2912 /* Used for communication between the following two functions: contains
2913 a MEM that we wish to ensure remains unchanged. */
2914 static rtx equiv_mem
;
2916 /* Set nonzero if EQUIV_MEM is modified. */
2917 static int equiv_mem_modified
;
2919 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2920 Called via note_stores. */
2922 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2923 void *data ATTRIBUTE_UNUSED
)
2926 && reg_overlap_mentioned_p (dest
, equiv_mem
))
2928 && anti_dependence (equiv_mem
, dest
)))
2929 equiv_mem_modified
= 1;
2932 /* Verify that no store between START and the death of REG invalidates
2933 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2934 by storing into an overlapping memory location, or with a non-const
2937 Return 1 if MEMREF remains valid. */
2939 validate_equiv_mem (rtx_insn
*start
, rtx reg
, rtx memref
)
2945 equiv_mem_modified
= 0;
2947 /* If the memory reference has side effects or is volatile, it isn't a
2948 valid equivalence. */
2949 if (side_effects_p (memref
))
2952 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
2954 if (! INSN_P (insn
))
2957 if (find_reg_note (insn
, REG_DEAD
, reg
))
2960 /* This used to ignore readonly memory and const/pure calls. The problem
2961 is the equivalent form may reference a pseudo which gets assigned a
2962 call clobbered hard reg. When we later replace REG with its
2963 equivalent form, the value in the call-clobbered reg has been
2964 changed and all hell breaks loose. */
2968 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
2970 /* If a register mentioned in MEMREF is modified via an
2971 auto-increment, we lose the equivalence. Do the same if one
2972 dies; although we could extend the life, it doesn't seem worth
2975 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2976 if ((REG_NOTE_KIND (note
) == REG_INC
2977 || REG_NOTE_KIND (note
) == REG_DEAD
)
2978 && REG_P (XEXP (note
, 0))
2979 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
2986 /* Returns zero if X is known to be invariant. */
2988 equiv_init_varies_p (rtx x
)
2990 RTX_CODE code
= GET_CODE (x
);
2997 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
3006 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
3009 if (MEM_VOLATILE_P (x
))
3018 fmt
= GET_RTX_FORMAT (code
);
3019 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3022 if (equiv_init_varies_p (XEXP (x
, i
)))
3025 else if (fmt
[i
] == 'E')
3028 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3029 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
3036 /* Returns nonzero if X (used to initialize register REGNO) is movable.
3037 X is only movable if the registers it uses have equivalent initializations
3038 which appear to be within the same loop (or in an inner loop) and movable
3039 or if they are not candidates for local_alloc and don't vary. */
3041 equiv_init_movable_p (rtx x
, int regno
)
3045 enum rtx_code code
= GET_CODE (x
);
3050 return equiv_init_movable_p (SET_SRC (x
), regno
);
3065 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
3066 && reg_equiv
[REGNO (x
)].replace
)
3067 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
3068 && ! rtx_varies_p (x
, 0)));
3070 case UNSPEC_VOLATILE
:
3074 if (MEM_VOLATILE_P (x
))
3083 fmt
= GET_RTX_FORMAT (code
);
3084 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3088 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
3092 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3093 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
3101 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
3104 contains_replace_regs (rtx x
)
3108 enum rtx_code code
= GET_CODE (x
);
3122 return reg_equiv
[REGNO (x
)].replace
;
3128 fmt
= GET_RTX_FORMAT (code
);
3129 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3133 if (contains_replace_regs (XEXP (x
, i
)))
3137 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3138 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
3146 /* TRUE if X references a memory location that would be affected by a store
3149 memref_referenced_p (rtx memref
, rtx x
)
3153 enum rtx_code code
= GET_CODE (x
);
3168 return (reg_equiv
[REGNO (x
)].replacement
3169 && memref_referenced_p (memref
,
3170 reg_equiv
[REGNO (x
)].replacement
));
3173 if (true_dependence (memref
, VOIDmode
, x
))
3178 /* If we are setting a MEM, it doesn't count (its address does), but any
3179 other SET_DEST that has a MEM in it is referencing the MEM. */
3180 if (MEM_P (SET_DEST (x
)))
3182 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
3185 else if (memref_referenced_p (memref
, SET_DEST (x
)))
3188 return memref_referenced_p (memref
, SET_SRC (x
));
3194 fmt
= GET_RTX_FORMAT (code
);
3195 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3199 if (memref_referenced_p (memref
, XEXP (x
, i
)))
3203 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3204 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
3212 /* TRUE if some insn in the range (START, END] references a memory location
3213 that would be affected by a store to MEMREF. */
3215 memref_used_between_p (rtx memref
, rtx_insn
*start
, rtx_insn
*end
)
3219 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
3220 insn
= NEXT_INSN (insn
))
3222 if (!NONDEBUG_INSN_P (insn
))
3225 if (memref_referenced_p (memref
, PATTERN (insn
)))
3228 /* Nonconst functions may access memory. */
3229 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
3236 /* Mark REG as having no known equivalence.
3237 Some instructions might have been processed before and furnished
3238 with REG_EQUIV notes for this register; these notes will have to be
3240 STORE is the piece of RTL that does the non-constant / conflicting
3241 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
3242 but needs to be there because this function is called from note_stores. */
3244 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
3245 void *data ATTRIBUTE_UNUSED
)
3252 regno
= REGNO (reg
);
3253 list
= reg_equiv
[regno
].init_insns
;
3254 if (list
== const0_rtx
)
3256 reg_equiv
[regno
].init_insns
= const0_rtx
;
3257 reg_equiv
[regno
].replacement
= NULL_RTX
;
3258 /* This doesn't matter for equivalences made for argument registers, we
3259 should keep their initialization insns. */
3260 if (reg_equiv
[regno
].is_arg_equivalence
)
3262 ira_reg_equiv
[regno
].defined_p
= false;
3263 ira_reg_equiv
[regno
].init_insns
= NULL
;
3264 for (; list
; list
= XEXP (list
, 1))
3266 rtx insn
= XEXP (list
, 0);
3267 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
3271 /* Check whether the SUBREG is a paradoxical subreg and set the result
3275 set_paradoxical_subreg (rtx_insn
*insn
, bool *pdx_subregs
)
3277 subrtx_iterator::array_type array
;
3278 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
3280 const_rtx subreg
= *iter
;
3281 if (GET_CODE (subreg
) == SUBREG
)
3283 const_rtx reg
= SUBREG_REG (subreg
);
3284 if (REG_P (reg
) && paradoxical_subreg_p (subreg
))
3285 pdx_subregs
[REGNO (reg
)] = true;
3290 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
3291 equivalent replacement. */
3294 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
3298 bitmap cleared_regs
= (bitmap
) data
;
3299 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
3300 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv
[REGNO (loc
)].src_p
),
3301 NULL_RTX
, adjust_cleared_regs
, data
);
3306 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
3307 static int recorded_label_ref
;
3309 /* Find registers that are equivalent to a single value throughout the
3310 compilation (either because they can be referenced in memory or are
3311 set once from a single constant). Lower their priority for a
3314 If such a register is only referenced once, try substituting its
3315 value into the using insn. If it succeeds, we can eliminate the
3316 register completely.
3318 Initialize init_insns in ira_reg_equiv array.
3320 Return non-zero if jump label rebuilding should be done. */
3322 update_equiv_regs (void)
3327 bitmap cleared_regs
;
3330 /* We need to keep track of whether or not we recorded a LABEL_REF so
3331 that we know if the jump optimizer needs to be rerun. */
3332 recorded_label_ref
= 0;
3334 /* Use pdx_subregs to show whether a reg is used in a paradoxical
3336 pdx_subregs
= XCNEWVEC (bool, max_regno
);
3338 reg_equiv
= XCNEWVEC (struct equivalence
, max_regno
);
3341 init_alias_analysis ();
3343 /* Scan insns and set pdx_subregs[regno] if the reg is used in a
3344 paradoxical subreg. Don't set such reg sequivalent to a mem,
3345 because lra will not substitute such equiv memory in order to
3346 prevent access beyond allocated memory for paradoxical memory subreg. */
3347 FOR_EACH_BB_FN (bb
, cfun
)
3348 FOR_BB_INSNS (bb
, insn
)
3349 if (NONDEBUG_INSN_P (insn
))
3350 set_paradoxical_subreg (insn
, pdx_subregs
);
3352 /* Scan the insns and find which registers have equivalences. Do this
3353 in a separate scan of the insns because (due to -fcse-follow-jumps)
3354 a register can be set below its use. */
3355 FOR_EACH_BB_FN (bb
, cfun
)
3357 loop_depth
= bb_loop_depth (bb
);
3359 for (insn
= BB_HEAD (bb
);
3360 insn
!= NEXT_INSN (BB_END (bb
));
3361 insn
= NEXT_INSN (insn
))
3368 if (! INSN_P (insn
))
3371 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3372 if (REG_NOTE_KIND (note
) == REG_INC
)
3373 no_equiv (XEXP (note
, 0), note
, NULL
);
3375 set
= single_set (insn
);
3377 /* If this insn contains more (or less) than a single SET,
3378 only mark all destinations as having no known equivalence. */
3381 note_stores (PATTERN (insn
), no_equiv
, NULL
);
3384 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3388 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
3390 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
3392 note_stores (part
, no_equiv
, NULL
);
3396 dest
= SET_DEST (set
);
3397 src
= SET_SRC (set
);
3399 /* See if this is setting up the equivalence between an argument
3400 register and its stack slot. */
3401 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3404 gcc_assert (REG_P (dest
));
3405 regno
= REGNO (dest
);
3407 /* Note that we don't want to clear init_insns in
3408 ira_reg_equiv even if there are multiple sets of this
3410 reg_equiv
[regno
].is_arg_equivalence
= 1;
3412 /* The insn result can have equivalence memory although
3413 the equivalence is not set up by the insn. We add
3414 this insn to init insns as it is a flag for now that
3415 regno has an equivalence. We will remove the insn
3416 from init insn list later. */
3417 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3418 ira_reg_equiv
[regno
].init_insns
3419 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3420 ira_reg_equiv
[regno
].init_insns
);
3422 /* Continue normally in case this is a candidate for
3429 /* We only handle the case of a pseudo register being set
3430 once, or always to the same value. */
3431 /* ??? The mn10200 port breaks if we add equivalences for
3432 values that need an ADDRESS_REGS register and set them equivalent
3433 to a MEM of a pseudo. The actual problem is in the over-conservative
3434 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3435 calculate_needs, but we traditionally work around this problem
3436 here by rejecting equivalences when the destination is in a register
3437 that's likely spilled. This is fragile, of course, since the
3438 preferred class of a pseudo depends on all instructions that set
3442 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3443 || reg_equiv
[regno
].init_insns
== const0_rtx
3444 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3445 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3447 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3448 also set somewhere else to a constant. */
3449 note_stores (set
, no_equiv
, NULL
);
3453 /* Don't set reg (if pdx_subregs[regno] == true) equivalent to a mem. */
3454 if (MEM_P (src
) && pdx_subregs
[regno
])
3456 note_stores (set
, no_equiv
, NULL
);
3460 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3462 /* cse sometimes generates function invariants, but doesn't put a
3463 REG_EQUAL note on the insn. Since this note would be redundant,
3464 there's no point creating it earlier than here. */
3465 if (! note
&& ! rtx_varies_p (src
, 0))
3466 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3468 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3469 since it represents a function call */
3470 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3473 if (DF_REG_DEF_COUNT (regno
) != 1
3475 || rtx_varies_p (XEXP (note
, 0), 0)
3476 || (reg_equiv
[regno
].replacement
3477 && ! rtx_equal_p (XEXP (note
, 0),
3478 reg_equiv
[regno
].replacement
))))
3480 no_equiv (dest
, set
, NULL
);
3483 /* Record this insn as initializing this register. */
3484 reg_equiv
[regno
].init_insns
3485 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3487 /* If this register is known to be equal to a constant, record that
3488 it is always equivalent to the constant. */
3489 if (DF_REG_DEF_COUNT (regno
) == 1
3490 && note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
3492 rtx note_value
= XEXP (note
, 0);
3493 remove_note (insn
, note
);
3494 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3497 /* If this insn introduces a "constant" register, decrease the priority
3498 of that register. Record this insn if the register is only used once
3499 more and the equivalence value is the same as our source.
3501 The latter condition is checked for two reasons: First, it is an
3502 indication that it may be more efficient to actually emit the insn
3503 as written (if no registers are available, reload will substitute
3504 the equivalence). Secondly, it avoids problems with any registers
3505 dying in this insn whose death notes would be missed.
3507 If we don't have a REG_EQUIV note, see if this insn is loading
3508 a register used only in one basic block from a MEM. If so, and the
3509 MEM remains unchanged for the life of the register, add a REG_EQUIV
3512 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3514 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3515 && MEM_P (SET_SRC (set
))
3516 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
3517 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (SET_SRC (set
)));
3521 int regno
= REGNO (dest
);
3522 rtx x
= XEXP (note
, 0);
3524 /* If we haven't done so, record for reload that this is an
3525 equivalencing insn. */
3526 if (!reg_equiv
[regno
].is_arg_equivalence
)
3527 ira_reg_equiv
[regno
].init_insns
3528 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3529 ira_reg_equiv
[regno
].init_insns
);
3531 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
3532 We might end up substituting the LABEL_REF for uses of the
3533 pseudo here or later. That kind of transformation may turn an
3534 indirect jump into a direct jump, in which case we must rerun the
3535 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
3536 if (GET_CODE (x
) == LABEL_REF
3537 || (GET_CODE (x
) == CONST
3538 && GET_CODE (XEXP (x
, 0)) == PLUS
3539 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)))
3540 recorded_label_ref
= 1;
3542 reg_equiv
[regno
].replacement
= x
;
3543 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3544 reg_equiv
[regno
].loop_depth
= loop_depth
;
3546 /* Don't mess with things live during setjmp. */
3547 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
3549 /* Note that the statement below does not affect the priority
3551 REG_LIVE_LENGTH (regno
) *= 2;
3553 /* If the register is referenced exactly twice, meaning it is
3554 set once and used once, indicate that the reference may be
3555 replaced by the equivalence we computed above. Do this
3556 even if the register is only used in one block so that
3557 dependencies can be handled where the last register is
3558 used in a different block (i.e. HIGH / LO_SUM sequences)
3559 and to reduce the number of registers alive across
3562 if (REG_N_REFS (regno
) == 2
3563 && (rtx_equal_p (x
, src
)
3564 || ! equiv_init_varies_p (src
))
3565 && NONJUMP_INSN_P (insn
)
3566 && equiv_init_movable_p (PATTERN (insn
), regno
))
3567 reg_equiv
[regno
].replace
= 1;
3576 /* A second pass, to gather additional equivalences with memory. This needs
3577 to be done after we know which registers we are going to replace. */
3579 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3584 if (! INSN_P (insn
))
3587 set
= single_set (insn
);
3591 dest
= SET_DEST (set
);
3592 src
= SET_SRC (set
);
3594 /* If this sets a MEM to the contents of a REG that is only used
3595 in a single basic block, see if the register is always equivalent
3596 to that memory location and if moving the store from INSN to the
3597 insn that set REG is safe. If so, put a REG_EQUIV note on the
3600 Don't add a REG_EQUIV note if the insn already has one. The existing
3601 REG_EQUIV is likely more useful than the one we are adding.
3603 If one of the regs in the address has reg_equiv[REGNO].replace set,
3604 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
3605 optimization may move the set of this register immediately before
3606 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
3607 the mention in the REG_EQUIV note would be to an uninitialized
3610 if (MEM_P (dest
) && REG_P (src
)
3611 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3612 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3613 && DF_REG_DEF_COUNT (regno
) == 1
3614 && reg_equiv
[regno
].init_insns
!= 0
3615 && reg_equiv
[regno
].init_insns
!= const0_rtx
3616 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
3617 REG_EQUIV
, NULL_RTX
)
3618 && ! contains_replace_regs (XEXP (dest
, 0))
3619 && ! pdx_subregs
[regno
])
3621 rtx_insn
*init_insn
=
3622 as_a
<rtx_insn
*> (XEXP (reg_equiv
[regno
].init_insns
, 0));
3623 if (validate_equiv_mem (init_insn
, src
, dest
)
3624 && ! memref_used_between_p (dest
, init_insn
, insn
)
3625 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3627 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3629 /* This insn makes the equivalence, not the one initializing
3631 ira_reg_equiv
[regno
].init_insns
3632 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3633 df_notes_rescan (init_insn
);
3638 cleared_regs
= BITMAP_ALLOC (NULL
);
3639 /* Now scan all regs killed in an insn to see if any of them are
3640 registers only used that once. If so, see if we can replace the
3641 reference with the equivalent form. If we can, delete the
3642 initializing reference and this register will go away. If we
3643 can't replace the reference, and the initializing reference is
3644 within the same loop (or in an inner loop), then move the register
3645 initialization just before the use, so that they are in the same
3647 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3649 loop_depth
= bb_loop_depth (bb
);
3650 for (insn
= BB_END (bb
);
3651 insn
!= PREV_INSN (BB_HEAD (bb
));
3652 insn
= PREV_INSN (insn
))
3656 if (! INSN_P (insn
))
3659 /* Don't substitute into a non-local goto, this confuses CFG. */
3661 && find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3664 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
3666 if (REG_NOTE_KIND (link
) == REG_DEAD
3667 /* Make sure this insn still refers to the register. */
3668 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
3670 int regno
= REGNO (XEXP (link
, 0));
3673 if (! reg_equiv
[regno
].replace
3674 || reg_equiv
[regno
].loop_depth
< loop_depth
3675 /* There is no sense to move insns if live range
3676 shrinkage or register pressure-sensitive
3677 scheduling were done because it will not
3678 improve allocation but worsen insn schedule
3679 with a big probability. */
3680 || flag_live_range_shrinkage
3681 || (flag_sched_pressure
&& flag_schedule_insns
))
3684 /* reg_equiv[REGNO].replace gets set only when
3685 REG_N_REFS[REGNO] is 2, i.e. the register is set
3686 once and used once. (If it were only set, but
3687 not used, flow would have deleted the setting
3688 insns.) Hence there can only be one insn in
3689 reg_equiv[REGNO].init_insns. */
3690 gcc_assert (reg_equiv
[regno
].init_insns
3691 && !XEXP (reg_equiv
[regno
].init_insns
, 1));
3692 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
3694 /* We may not move instructions that can throw, since
3695 that changes basic block boundaries and we are not
3696 prepared to adjust the CFG to match. */
3697 if (can_throw_internal (equiv_insn
))
3700 if (asm_noperands (PATTERN (equiv_insn
)) < 0
3701 && validate_replace_rtx (regno_reg_rtx
[regno
],
3702 *(reg_equiv
[regno
].src_p
), insn
))
3708 /* Find the last note. */
3709 for (last_link
= link
; XEXP (last_link
, 1);
3710 last_link
= XEXP (last_link
, 1))
3713 /* Append the REG_DEAD notes from equiv_insn. */
3714 equiv_link
= REG_NOTES (equiv_insn
);
3718 equiv_link
= XEXP (equiv_link
, 1);
3719 if (REG_NOTE_KIND (note
) == REG_DEAD
)
3721 remove_note (equiv_insn
, note
);
3722 XEXP (last_link
, 1) = note
;
3723 XEXP (note
, 1) = NULL_RTX
;
3728 remove_death (regno
, insn
);
3729 SET_REG_N_REFS (regno
, 0);
3730 REG_FREQ (regno
) = 0;
3731 delete_insn (equiv_insn
);
3733 reg_equiv
[regno
].init_insns
3734 = XEXP (reg_equiv
[regno
].init_insns
, 1);
3736 ira_reg_equiv
[regno
].init_insns
= NULL
;
3737 bitmap_set_bit (cleared_regs
, regno
);
3739 /* Move the initialization of the register to just before
3740 INSN. Update the flow information. */
3741 else if (prev_nondebug_insn (insn
) != equiv_insn
)
3745 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
3746 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
3747 REG_NOTES (equiv_insn
) = 0;
3748 /* Rescan it to process the notes. */
3749 df_insn_rescan (new_insn
);
3751 /* Make sure this insn is recognized before
3752 reload begins, otherwise
3753 eliminate_regs_in_insn will die. */
3754 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
3756 delete_insn (equiv_insn
);
3758 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3760 REG_BASIC_BLOCK (regno
) = bb
->index
;
3761 REG_N_CALLS_CROSSED (regno
) = 0;
3762 REG_FREQ_CALLS_CROSSED (regno
) = 0;
3763 REG_N_THROWING_CALLS_CROSSED (regno
) = 0;
3764 REG_LIVE_LENGTH (regno
) = 2;
3766 if (insn
== BB_HEAD (bb
))
3767 BB_HEAD (bb
) = PREV_INSN (insn
);
3769 ira_reg_equiv
[regno
].init_insns
3770 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3771 bitmap_set_bit (cleared_regs
, regno
);
3778 if (!bitmap_empty_p (cleared_regs
))
3780 FOR_EACH_BB_FN (bb
, cfun
)
3782 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3783 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3786 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3787 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3790 /* Last pass - adjust debug insns referencing cleared regs. */
3791 if (MAY_HAVE_DEBUG_INSNS
)
3792 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3793 if (DEBUG_INSN_P (insn
))
3795 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3796 INSN_VAR_LOCATION_LOC (insn
)
3797 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3798 adjust_cleared_regs
,
3799 (void *) cleared_regs
);
3800 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3801 df_insn_rescan (insn
);
3805 BITMAP_FREE (cleared_regs
);
3810 end_alias_analysis ();
3813 return recorded_label_ref
;
3818 /* Set up fields memory, constant, and invariant from init_insns in
3819 the structures of array ira_reg_equiv. */
3821 setup_reg_equiv (void)
3824 rtx_insn_list
*elem
, *prev_elem
, *next_elem
;
3828 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3829 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3831 prev_elem
= elem
, elem
= next_elem
)
3833 next_elem
= elem
->next ();
3834 insn
= elem
->insn ();
3835 set
= single_set (insn
);
3837 /* Init insns can set up equivalence when the reg is a destination or
3838 a source (in this case the destination is memory). */
3839 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
3841 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
3844 if (REG_P (SET_DEST (set
))
3845 && REGNO (SET_DEST (set
)) == (unsigned int) i
3846 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
3848 /* This insn reporting the equivalence but
3849 actually not setting it. Remove it from the
3851 if (prev_elem
== NULL
)
3852 ira_reg_equiv
[i
].init_insns
= next_elem
;
3854 XEXP (prev_elem
, 1) = next_elem
;
3858 else if (REG_P (SET_DEST (set
))
3859 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
3863 gcc_assert (REG_P (SET_SRC (set
))
3864 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
3867 if (! function_invariant_p (x
)
3869 /* A function invariant is often CONSTANT_P but may
3870 include a register. We promise to only pass
3871 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
3872 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
3874 /* It can happen that a REG_EQUIV note contains a MEM
3875 that is not a legitimate memory operand. As later
3876 stages of reload assume that all addresses found in
3877 the lra_regno_equiv_* arrays were originally
3878 legitimate, we ignore such REG_EQUIV notes. */
3879 if (memory_operand (x
, VOIDmode
))
3881 ira_reg_equiv
[i
].defined_p
= true;
3882 ira_reg_equiv
[i
].memory
= x
;
3885 else if (function_invariant_p (x
))
3887 enum machine_mode mode
;
3889 mode
= GET_MODE (SET_DEST (set
));
3890 if (GET_CODE (x
) == PLUS
3891 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
3892 /* This is PLUS of frame pointer and a constant,
3894 ira_reg_equiv
[i
].invariant
= x
;
3895 else if (targetm
.legitimate_constant_p (mode
, x
))
3896 ira_reg_equiv
[i
].constant
= x
;
3899 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
3900 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
3902 ira_reg_equiv
[i
].defined_p
= false;
3903 ira_reg_equiv
[i
].init_insns
= NULL
;
3907 ira_reg_equiv
[i
].defined_p
= true;
3912 ira_reg_equiv
[i
].defined_p
= false;
3913 ira_reg_equiv
[i
].init_insns
= NULL
;
3920 /* Print chain C to FILE. */
3922 print_insn_chain (FILE *file
, struct insn_chain
*c
)
3924 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
3925 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
3926 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
3930 /* Print all reload_insn_chains to FILE. */
3932 print_insn_chains (FILE *file
)
3934 struct insn_chain
*c
;
3935 for (c
= reload_insn_chain
; c
; c
= c
->next
)
3936 print_insn_chain (file
, c
);
3939 /* Return true if pseudo REGNO should be added to set live_throughout
3940 or dead_or_set of the insn chains for reload consideration. */
3942 pseudo_for_reload_consideration_p (int regno
)
3944 /* Consider spilled pseudos too for IRA because they still have a
3945 chance to get hard-registers in the reload when IRA is used. */
3946 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
3949 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using
3950 REG to the number of nregs, and INIT_VALUE to get the
3951 initialization. ALLOCNUM need not be the regno of REG. */
3953 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
3954 bitmap live_subregs_used
, int allocnum
, rtx reg
)
3956 unsigned int regno
= REGNO (SUBREG_REG (reg
));
3957 int size
= GET_MODE_SIZE (GET_MODE (regno_reg_rtx
[regno
]));
3959 gcc_assert (size
> 0);
3961 /* Been there, done that. */
3962 if (bitmap_bit_p (live_subregs_used
, allocnum
))
3965 /* Create a new one. */
3966 if (live_subregs
[allocnum
] == NULL
)
3967 live_subregs
[allocnum
] = sbitmap_alloc (size
);
3969 /* If the entire reg was live before blasting into subregs, we need
3970 to init all of the subregs to ones else init to 0. */
3972 bitmap_ones (live_subregs
[allocnum
]);
3974 bitmap_clear (live_subregs
[allocnum
]);
3976 bitmap_set_bit (live_subregs_used
, allocnum
);
3979 /* Walk the insns of the current function and build reload_insn_chain,
3980 and record register life information. */
3982 build_insn_chain (void)
3985 struct insn_chain
**p
= &reload_insn_chain
;
3987 struct insn_chain
*c
= NULL
;
3988 struct insn_chain
*next
= NULL
;
3989 bitmap live_relevant_regs
= BITMAP_ALLOC (NULL
);
3990 bitmap elim_regset
= BITMAP_ALLOC (NULL
);
3991 /* live_subregs is a vector used to keep accurate information about
3992 which hardregs are live in multiword pseudos. live_subregs and
3993 live_subregs_used are indexed by pseudo number. The live_subreg
3994 entry for a particular pseudo is only used if the corresponding
3995 element is non zero in live_subregs_used. The sbitmap size of
3996 live_subreg[allocno] is number of bytes that the pseudo can
3998 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
3999 bitmap live_subregs_used
= BITMAP_ALLOC (NULL
);
4001 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4002 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
4003 bitmap_set_bit (elim_regset
, i
);
4004 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
4009 CLEAR_REG_SET (live_relevant_regs
);
4010 bitmap_clear (live_subregs_used
);
4012 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
4014 if (i
>= FIRST_PSEUDO_REGISTER
)
4016 bitmap_set_bit (live_relevant_regs
, i
);
4019 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
4020 FIRST_PSEUDO_REGISTER
, i
, bi
)
4022 if (pseudo_for_reload_consideration_p (i
))
4023 bitmap_set_bit (live_relevant_regs
, i
);
4026 FOR_BB_INSNS_REVERSE (bb
, insn
)
4028 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4030 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4033 c
= new_insn_chain ();
4040 c
->block
= bb
->index
;
4042 if (NONDEBUG_INSN_P (insn
))
4043 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4045 unsigned int regno
= DF_REF_REGNO (def
);
4047 /* Ignore may clobbers because these are generated
4048 from calls. However, every other kind of def is
4049 added to dead_or_set. */
4050 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
4052 if (regno
< FIRST_PSEUDO_REGISTER
)
4054 if (!fixed_regs
[regno
])
4055 bitmap_set_bit (&c
->dead_or_set
, regno
);
4057 else if (pseudo_for_reload_consideration_p (regno
))
4058 bitmap_set_bit (&c
->dead_or_set
, regno
);
4061 if ((regno
< FIRST_PSEUDO_REGISTER
4062 || reg_renumber
[regno
] >= 0
4064 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
4066 rtx reg
= DF_REF_REG (def
);
4068 /* We can model subregs, but not if they are
4069 wrapped in ZERO_EXTRACTS. */
4070 if (GET_CODE (reg
) == SUBREG
4071 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
))
4073 unsigned int start
= SUBREG_BYTE (reg
);
4074 unsigned int last
= start
4075 + GET_MODE_SIZE (GET_MODE (reg
));
4078 (bitmap_bit_p (live_relevant_regs
, regno
),
4079 live_subregs
, live_subregs_used
, regno
, reg
);
4081 if (!DF_REF_FLAGS_IS_SET
4082 (def
, DF_REF_STRICT_LOW_PART
))
4084 /* Expand the range to cover entire words.
4085 Bytes added here are "don't care". */
4087 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
4088 last
= ((last
+ UNITS_PER_WORD
- 1)
4089 / UNITS_PER_WORD
* UNITS_PER_WORD
);
4092 /* Ignore the paradoxical bits. */
4093 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4094 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4096 while (start
< last
)
4098 bitmap_clear_bit (live_subregs
[regno
], start
);
4102 if (bitmap_empty_p (live_subregs
[regno
]))
4104 bitmap_clear_bit (live_subregs_used
, regno
);
4105 bitmap_clear_bit (live_relevant_regs
, regno
);
4108 /* Set live_relevant_regs here because
4109 that bit has to be true to get us to
4110 look at the live_subregs fields. */
4111 bitmap_set_bit (live_relevant_regs
, regno
);
4115 /* DF_REF_PARTIAL is generated for
4116 subregs, STRICT_LOW_PART, and
4117 ZERO_EXTRACT. We handle the subreg
4118 case above so here we have to keep from
4119 modeling the def as a killing def. */
4120 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
4122 bitmap_clear_bit (live_subregs_used
, regno
);
4123 bitmap_clear_bit (live_relevant_regs
, regno
);
4129 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
4130 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4132 if (NONDEBUG_INSN_P (insn
))
4133 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4135 unsigned int regno
= DF_REF_REGNO (use
);
4136 rtx reg
= DF_REF_REG (use
);
4138 /* DF_REF_READ_WRITE on a use means that this use
4139 is fabricated from a def that is a partial set
4140 to a multiword reg. Here, we only model the
4141 subreg case that is not wrapped in ZERO_EXTRACT
4142 precisely so we do not need to look at the
4144 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
4145 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
4146 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
4149 /* Add the last use of each var to dead_or_set. */
4150 if (!bitmap_bit_p (live_relevant_regs
, regno
))
4152 if (regno
< FIRST_PSEUDO_REGISTER
)
4154 if (!fixed_regs
[regno
])
4155 bitmap_set_bit (&c
->dead_or_set
, regno
);
4157 else if (pseudo_for_reload_consideration_p (regno
))
4158 bitmap_set_bit (&c
->dead_or_set
, regno
);
4161 if (regno
< FIRST_PSEUDO_REGISTER
4162 || pseudo_for_reload_consideration_p (regno
))
4164 if (GET_CODE (reg
) == SUBREG
4165 && !DF_REF_FLAGS_IS_SET (use
,
4167 | DF_REF_ZERO_EXTRACT
))
4169 unsigned int start
= SUBREG_BYTE (reg
);
4170 unsigned int last
= start
4171 + GET_MODE_SIZE (GET_MODE (reg
));
4174 (bitmap_bit_p (live_relevant_regs
, regno
),
4175 live_subregs
, live_subregs_used
, regno
, reg
);
4177 /* Ignore the paradoxical bits. */
4178 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4179 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4181 while (start
< last
)
4183 bitmap_set_bit (live_subregs
[regno
], start
);
4188 /* Resetting the live_subregs_used is
4189 effectively saying do not use the subregs
4190 because we are reading the whole
4192 bitmap_clear_bit (live_subregs_used
, regno
);
4193 bitmap_set_bit (live_relevant_regs
, regno
);
4199 /* FIXME!! The following code is a disaster. Reload needs to see the
4200 labels and jump tables that are just hanging out in between
4201 the basic blocks. See pr33676. */
4202 insn
= BB_HEAD (bb
);
4204 /* Skip over the barriers and cruft. */
4205 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
4206 || BLOCK_FOR_INSN (insn
) == bb
))
4207 insn
= PREV_INSN (insn
);
4209 /* While we add anything except barriers and notes, the focus is
4210 to get the labels and jump tables into the
4211 reload_insn_chain. */
4214 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4216 if (BLOCK_FOR_INSN (insn
))
4219 c
= new_insn_chain ();
4225 /* The block makes no sense here, but it is what the old
4227 c
->block
= bb
->index
;
4229 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4231 insn
= PREV_INSN (insn
);
4235 reload_insn_chain
= c
;
4238 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
4239 if (live_subregs
[i
] != NULL
)
4240 sbitmap_free (live_subregs
[i
]);
4241 free (live_subregs
);
4242 BITMAP_FREE (live_subregs_used
);
4243 BITMAP_FREE (live_relevant_regs
);
4244 BITMAP_FREE (elim_regset
);
4247 print_insn_chains (dump_file
);
4250 /* Examine the rtx found in *LOC, which is read or written to as determined
4251 by TYPE. Return false if we find a reason why an insn containing this
4252 rtx should not be moved (such as accesses to non-constant memory), true
4255 rtx_moveable_p (rtx
*loc
, enum op_type type
)
4259 enum rtx_code code
= GET_CODE (x
);
4262 code
= GET_CODE (x
);
4272 return type
== OP_IN
;
4278 if (x
== frame_pointer_rtx
)
4280 if (HARD_REGISTER_P (x
))
4286 if (type
== OP_IN
&& MEM_READONLY_P (x
))
4287 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
4291 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
4292 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
4294 case STRICT_LOW_PART
:
4295 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
4299 return (rtx_moveable_p (&XEXP (x
, 0), type
)
4300 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
4301 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
4304 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
4310 fmt
= GET_RTX_FORMAT (code
);
4311 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4315 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
4318 else if (fmt
[i
] == 'E')
4319 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4321 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
4328 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
4329 to give dominance relationships between two insns I1 and I2. */
4331 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
4333 basic_block bb1
= BLOCK_FOR_INSN (i1
);
4334 basic_block bb2
= BLOCK_FOR_INSN (i2
);
4337 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
4338 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
4341 /* Record the range of register numbers added by find_moveable_pseudos. */
4342 int first_moveable_pseudo
, last_moveable_pseudo
;
4344 /* These two vectors hold data for every register added by
4345 find_movable_pseudos, with index 0 holding data for the
4346 first_moveable_pseudo. */
4347 /* The original home register. */
4348 static vec
<rtx
> pseudo_replaced_reg
;
4350 /* Look for instances where we have an instruction that is known to increase
4351 register pressure, and whose result is not used immediately. If it is
4352 possible to move the instruction downwards to just before its first use,
4353 split its lifetime into two ranges. We create a new pseudo to compute the
4354 value, and emit a move instruction just before the first use. If, after
4355 register allocation, the new pseudo remains unallocated, the function
4356 move_unallocated_pseudos then deletes the move instruction and places
4357 the computation just before the first use.
4359 Such a move is safe and profitable if all the input registers remain live
4360 and unchanged between the original computation and its first use. In such
4361 a situation, the computation is known to increase register pressure, and
4362 moving it is known to at least not worsen it.
4364 We restrict moves to only those cases where a register remains unallocated,
4365 in order to avoid interfering too much with the instruction schedule. As
4366 an exception, we may move insns which only modify their input register
4367 (typically induction variables), as this increases the freedom for our
4368 intended transformation, and does not limit the second instruction
4372 find_moveable_pseudos (void)
4375 int max_regs
= max_reg_num ();
4376 int max_uid
= get_max_uid ();
4378 int *uid_luid
= XNEWVEC (int, max_uid
);
4379 rtx_insn
**closest_uses
= XNEWVEC (rtx_insn
*, max_regs
);
4380 /* A set of registers which are live but not modified throughout a block. */
4381 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
,
4382 last_basic_block_for_fn (cfun
));
4383 /* A set of registers which only exist in a given basic block. */
4384 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
,
4385 last_basic_block_for_fn (cfun
));
4386 /* A set of registers which are set once, in an instruction that can be
4387 moved freely downwards, but are otherwise transparent to a block. */
4388 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
,
4389 last_basic_block_for_fn (cfun
));
4390 bitmap_head live
, used
, set
, interesting
, unusable_as_input
;
4392 bitmap_initialize (&interesting
, 0);
4394 first_moveable_pseudo
= max_regs
;
4395 pseudo_replaced_reg
.release ();
4396 pseudo_replaced_reg
.safe_grow_cleared (max_regs
);
4399 calculate_dominance_info (CDI_DOMINATORS
);
4402 bitmap_initialize (&live
, 0);
4403 bitmap_initialize (&used
, 0);
4404 bitmap_initialize (&set
, 0);
4405 bitmap_initialize (&unusable_as_input
, 0);
4406 FOR_EACH_BB_FN (bb
, cfun
)
4409 bitmap transp
= bb_transp_live
+ bb
->index
;
4410 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4411 bitmap local
= bb_local
+ bb
->index
;
4413 bitmap_initialize (local
, 0);
4414 bitmap_initialize (transp
, 0);
4415 bitmap_initialize (moveable
, 0);
4416 bitmap_copy (&live
, df_get_live_out (bb
));
4417 bitmap_and_into (&live
, df_get_live_in (bb
));
4418 bitmap_copy (transp
, &live
);
4419 bitmap_clear (moveable
);
4420 bitmap_clear (&live
);
4421 bitmap_clear (&used
);
4422 bitmap_clear (&set
);
4423 FOR_BB_INSNS (bb
, insn
)
4424 if (NONDEBUG_INSN_P (insn
))
4426 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4429 uid_luid
[INSN_UID (insn
)] = i
++;
4431 def
= df_single_def (insn_info
);
4432 use
= df_single_use (insn_info
);
4435 && DF_REF_REGNO (use
) == DF_REF_REGNO (def
)
4436 && !bitmap_bit_p (&set
, DF_REF_REGNO (use
))
4437 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4439 unsigned regno
= DF_REF_REGNO (use
);
4440 bitmap_set_bit (moveable
, regno
);
4441 bitmap_set_bit (&set
, regno
);
4442 bitmap_set_bit (&used
, regno
);
4443 bitmap_clear_bit (transp
, regno
);
4446 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4448 unsigned regno
= DF_REF_REGNO (use
);
4449 bitmap_set_bit (&used
, regno
);
4450 if (bitmap_clear_bit (moveable
, regno
))
4451 bitmap_clear_bit (transp
, regno
);
4454 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4456 unsigned regno
= DF_REF_REGNO (def
);
4457 bitmap_set_bit (&set
, regno
);
4458 bitmap_clear_bit (transp
, regno
);
4459 bitmap_clear_bit (moveable
, regno
);
4464 bitmap_clear (&live
);
4465 bitmap_clear (&used
);
4466 bitmap_clear (&set
);
4468 FOR_EACH_BB_FN (bb
, cfun
)
4470 bitmap local
= bb_local
+ bb
->index
;
4473 FOR_BB_INSNS (bb
, insn
)
4474 if (NONDEBUG_INSN_P (insn
))
4476 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4478 rtx closest_use
, note
;
4481 bool all_dominated
, all_local
;
4482 enum machine_mode mode
;
4484 def
= df_single_def (insn_info
);
4485 /* There must be exactly one def in this insn. */
4486 if (!def
|| !single_set (insn
))
4488 /* This must be the only definition of the reg. We also limit
4489 which modes we deal with so that we can assume we can generate
4490 move instructions. */
4491 regno
= DF_REF_REGNO (def
);
4492 mode
= GET_MODE (DF_REF_REG (def
));
4493 if (DF_REG_DEF_COUNT (regno
) != 1
4494 || !DF_REF_INSN_INFO (def
)
4495 || HARD_REGISTER_NUM_P (regno
)
4496 || DF_REG_EQ_USE_COUNT (regno
) > 0
4497 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
4499 def_insn
= DF_REF_INSN (def
);
4501 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4502 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4508 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4510 bitmap_set_bit (&unusable_as_input
, regno
);
4514 use
= DF_REG_USE_CHAIN (regno
);
4515 all_dominated
= true;
4517 closest_use
= NULL_RTX
;
4518 for (; use
; use
= DF_REF_NEXT_REG (use
))
4521 if (!DF_REF_INSN_INFO (use
))
4523 all_dominated
= false;
4527 insn
= DF_REF_INSN (use
);
4528 if (DEBUG_INSN_P (insn
))
4530 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4532 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4533 all_dominated
= false;
4534 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4536 if (closest_use
== NULL_RTX
)
4538 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4540 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4541 closest_use
= const0_rtx
;
4547 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4552 bitmap_set_bit (local
, regno
);
4553 if (closest_use
== const0_rtx
|| closest_use
== NULL
4554 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4557 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4558 closest_use
== const0_rtx
|| closest_use
== NULL
4559 ? " (no unique first use)" : "");
4563 if (reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
4566 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
4571 bitmap_set_bit (&interesting
, regno
);
4572 /* If we get here, we know closest_use is a non-NULL insn
4573 (as opposed to const_0_rtx). */
4574 closest_uses
[regno
] = as_a
<rtx_insn
*> (closest_use
);
4576 if (dump_file
&& (all_local
|| all_dominated
))
4578 fprintf (dump_file
, "Reg %u:", regno
);
4580 fprintf (dump_file
, " local to bb %d", bb
->index
);
4582 fprintf (dump_file
, " def dominates all uses");
4583 if (closest_use
!= const0_rtx
)
4584 fprintf (dump_file
, " has unique first use");
4585 fputs ("\n", dump_file
);
4590 EXECUTE_IF_SET_IN_BITMAP (&interesting
, 0, i
, bi
)
4592 df_ref def
= DF_REG_DEF_CHAIN (i
);
4593 rtx_insn
*def_insn
= DF_REF_INSN (def
);
4594 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4595 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4596 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4597 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4598 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4599 rtx_insn
*use_insn
= closest_uses
[i
];
4602 bool all_transp
= true;
4604 if (!REG_P (DF_REF_REG (def
)))
4610 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4614 if (reg_equiv_init (i
) != NULL_RTX
)
4617 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4621 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4624 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4625 INSN_UID (def_insn
), i
);
4629 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4630 INSN_UID (def_insn
), i
);
4631 FOR_EACH_INSN_USE (use
, def_insn
)
4633 unsigned regno
= DF_REF_REGNO (use
);
4634 if (bitmap_bit_p (&unusable_as_input
, regno
))
4638 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4641 if (!bitmap_bit_p (def_bb_transp
, regno
))
4643 if (bitmap_bit_p (def_bb_moveable
, regno
)
4644 && !control_flow_insn_p (use_insn
)
4646 && !sets_cc0_p (use_insn
)
4650 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4652 rtx_insn
*x
= NEXT_INSN (def_insn
);
4653 while (!modified_in_p (DF_REF_REG (use
), x
))
4655 gcc_assert (x
!= use_insn
);
4659 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4660 regno
, INSN_UID (x
));
4661 emit_insn_after (PATTERN (x
), use_insn
);
4662 set_insn_deleted (x
);
4667 fprintf (dump_file
, " input reg %u modified between def and use\n",
4678 if (!dbg_cnt (ira_move
))
4681 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4685 rtx def_reg
= DF_REF_REG (def
);
4686 rtx newreg
= ira_create_new_reg (def_reg
);
4687 if (validate_change (def_insn
, DF_REF_REAL_LOC (def
), newreg
, 0))
4689 unsigned nregno
= REGNO (newreg
);
4690 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4692 pseudo_replaced_reg
[nregno
] = def_reg
;
4697 FOR_EACH_BB_FN (bb
, cfun
)
4699 bitmap_clear (bb_local
+ bb
->index
);
4700 bitmap_clear (bb_transp_live
+ bb
->index
);
4701 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4703 bitmap_clear (&interesting
);
4704 bitmap_clear (&unusable_as_input
);
4706 free (closest_uses
);
4708 free (bb_transp_live
);
4709 free (bb_moveable_reg_sets
);
4711 last_moveable_pseudo
= max_reg_num ();
4713 fix_reg_equiv_init ();
4715 regstat_free_n_sets_and_refs ();
4717 regstat_init_n_sets_and_refs ();
4718 regstat_compute_ri ();
4719 free_dominance_info (CDI_DOMINATORS
);
4722 /* If SET pattern SET is an assignment from a hard register to a pseudo which
4723 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return
4724 the destination. Otherwise return NULL. */
4727 interesting_dest_for_shprep_1 (rtx set
, basic_block call_dom
)
4729 rtx src
= SET_SRC (set
);
4730 rtx dest
= SET_DEST (set
);
4731 if (!REG_P (src
) || !HARD_REGISTER_P (src
)
4732 || !REG_P (dest
) || HARD_REGISTER_P (dest
)
4733 || (call_dom
&& !bitmap_bit_p (df_get_live_in (call_dom
), REGNO (dest
))))
4738 /* If insn is interesting for parameter range-splitting shring-wrapping
4739 preparation, i.e. it is a single set from a hard register to a pseudo, which
4740 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
4741 parallel statement with only one such statement, return the destination.
4742 Otherwise return NULL. */
4745 interesting_dest_for_shprep (rtx_insn
*insn
, basic_block call_dom
)
4749 rtx pat
= PATTERN (insn
);
4750 if (GET_CODE (pat
) == SET
)
4751 return interesting_dest_for_shprep_1 (pat
, call_dom
);
4753 if (GET_CODE (pat
) != PARALLEL
)
4756 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
4758 rtx sub
= XVECEXP (pat
, 0, i
);
4759 if (GET_CODE (sub
) == USE
|| GET_CODE (sub
) == CLOBBER
)
4761 if (GET_CODE (sub
) != SET
4762 || side_effects_p (sub
))
4764 rtx dest
= interesting_dest_for_shprep_1 (sub
, call_dom
);
4773 /* Split live ranges of pseudos that are loaded from hard registers in the
4774 first BB in a BB that dominates all non-sibling call if such a BB can be
4775 found and is not in a loop. Return true if the function has made any
4779 split_live_ranges_for_shrink_wrap (void)
4781 basic_block bb
, call_dom
= NULL
;
4782 basic_block first
= single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
4783 rtx_insn
*insn
, *last_interesting_insn
= NULL
;
4784 bitmap_head need_new
, reachable
;
4785 vec
<basic_block
> queue
;
4787 if (!SHRINK_WRAPPING_ENABLED
)
4790 bitmap_initialize (&need_new
, 0);
4791 bitmap_initialize (&reachable
, 0);
4792 queue
.create (n_basic_blocks_for_fn (cfun
));
4794 FOR_EACH_BB_FN (bb
, cfun
)
4795 FOR_BB_INSNS (bb
, insn
)
4796 if (CALL_P (insn
) && !SIBLING_CALL_P (insn
))
4800 bitmap_clear (&need_new
);
4801 bitmap_clear (&reachable
);
4806 bitmap_set_bit (&need_new
, bb
->index
);
4807 bitmap_set_bit (&reachable
, bb
->index
);
4808 queue
.quick_push (bb
);
4812 if (queue
.is_empty ())
4814 bitmap_clear (&need_new
);
4815 bitmap_clear (&reachable
);
4820 while (!queue
.is_empty ())
4826 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4827 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4828 && bitmap_set_bit (&reachable
, e
->dest
->index
))
4829 queue
.quick_push (e
->dest
);
4833 FOR_BB_INSNS (first
, insn
)
4835 rtx dest
= interesting_dest_for_shprep (insn
, NULL
);
4839 if (DF_REG_DEF_COUNT (REGNO (dest
)) > 1)
4841 bitmap_clear (&need_new
);
4842 bitmap_clear (&reachable
);
4846 for (df_ref use
= DF_REG_USE_CHAIN (REGNO(dest
));
4848 use
= DF_REF_NEXT_REG (use
))
4850 int ubbi
= DF_REF_BB (use
)->index
;
4851 if (bitmap_bit_p (&reachable
, ubbi
))
4852 bitmap_set_bit (&need_new
, ubbi
);
4854 last_interesting_insn
= insn
;
4857 bitmap_clear (&reachable
);
4858 if (!last_interesting_insn
)
4860 bitmap_clear (&need_new
);
4864 call_dom
= nearest_common_dominator_for_set (CDI_DOMINATORS
, &need_new
);
4865 bitmap_clear (&need_new
);
4866 if (call_dom
== first
)
4869 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
4870 while (bb_loop_depth (call_dom
) > 0)
4871 call_dom
= get_immediate_dominator (CDI_DOMINATORS
, call_dom
);
4872 loop_optimizer_finalize ();
4874 if (call_dom
== first
)
4877 calculate_dominance_info (CDI_POST_DOMINATORS
);
4878 if (dominated_by_p (CDI_POST_DOMINATORS
, first
, call_dom
))
4880 free_dominance_info (CDI_POST_DOMINATORS
);
4883 free_dominance_info (CDI_POST_DOMINATORS
);
4886 fprintf (dump_file
, "Will split live ranges of parameters at BB %i\n",
4890 FOR_BB_INSNS (first
, insn
)
4892 rtx dest
= interesting_dest_for_shprep (insn
, call_dom
);
4896 rtx newreg
= NULL_RTX
;
4898 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
4900 rtx_insn
*uin
= DF_REF_INSN (use
);
4901 next
= DF_REF_NEXT_REG (use
);
4903 basic_block ubb
= BLOCK_FOR_INSN (uin
);
4905 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
4908 newreg
= ira_create_new_reg (dest
);
4909 validate_change (uin
, DF_REF_REAL_LOC (use
), newreg
, true);
4915 rtx new_move
= gen_move_insn (newreg
, dest
);
4916 emit_insn_after (new_move
, bb_note (call_dom
));
4919 fprintf (dump_file
, "Split live-range of register ");
4920 print_rtl_single (dump_file
, dest
);
4925 if (insn
== last_interesting_insn
)
4928 apply_change_group ();
4932 /* Perform the second half of the transformation started in
4933 find_moveable_pseudos. We look for instances where the newly introduced
4934 pseudo remains unallocated, and remove it by moving the definition to
4935 just before its use, replacing the move instruction generated by
4936 find_moveable_pseudos. */
4938 move_unallocated_pseudos (void)
4941 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
4942 if (reg_renumber
[i
] < 0)
4944 int idx
= i
- first_moveable_pseudo
;
4945 rtx other_reg
= pseudo_replaced_reg
[idx
];
4946 rtx_insn
*def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
4947 /* The use must follow all definitions of OTHER_REG, so we can
4948 insert the new definition immediately after any of them. */
4949 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
4950 rtx_insn
*move_insn
= DF_REF_INSN (other_def
);
4951 rtx_insn
*newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
4956 fprintf (dump_file
, "moving def of %d (insn %d now) ",
4957 REGNO (other_reg
), INSN_UID (def_insn
));
4959 delete_insn (move_insn
);
4960 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
4961 delete_insn (DF_REF_INSN (other_def
));
4962 delete_insn (def_insn
);
4964 set
= single_set (newinsn
);
4965 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
4966 gcc_assert (success
);
4968 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
4969 INSN_UID (newinsn
), i
);
4970 SET_REG_N_REFS (i
, 0);
4974 /* If the backend knows where to allocate pseudos for hard
4975 register initial values, register these allocations now. */
4977 allocate_initial_values (void)
4979 if (targetm
.allocate_initial_value
)
4984 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
4986 if (! initial_value_entry (i
, &hreg
, &preg
))
4989 x
= targetm
.allocate_initial_value (hreg
);
4990 regno
= REGNO (preg
);
4991 if (x
&& REG_N_SETS (regno
) <= 1)
4994 reg_equiv_memory_loc (regno
) = x
;
5000 gcc_assert (REG_P (x
));
5001 new_regno
= REGNO (x
);
5002 reg_renumber
[regno
] = new_regno
;
5003 /* Poke the regno right into regno_reg_rtx so that even
5004 fixed regs are accepted. */
5005 SET_REGNO (preg
, new_regno
);
5006 /* Update global register liveness information. */
5007 FOR_EACH_BB_FN (bb
, cfun
)
5009 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
5010 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
5011 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
5012 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
5018 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
5024 /* True when we use LRA instead of reload pass for the current
5028 /* True if we have allocno conflicts. It is false for non-optimized
5029 mode or when the conflict table is too big. */
5030 bool ira_conflicts_p
;
5032 /* Saved between IRA and reload. */
5033 static int saved_flag_ira_share_spill_slots
;
5035 /* This is the main entry of IRA. */
5040 int ira_max_point_before_emit
;
5042 bool saved_flag_caller_saves
= flag_caller_saves
;
5043 enum ira_region saved_flag_ira_region
= flag_ira_region
;
5045 ira_conflicts_p
= optimize
> 0;
5047 ira_use_lra_p
= targetm
.lra_p ();
5048 /* If there are too many pseudos and/or basic blocks (e.g. 10K
5049 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
5050 use simplified and faster algorithms in LRA. */
5053 && max_reg_num () >= (1 << 26) / last_basic_block_for_fn (cfun
));
5056 /* It permits to skip live range splitting in LRA. */
5057 flag_caller_saves
= false;
5058 /* There is no sense to do regional allocation when we use
5060 flag_ira_region
= IRA_REGION_ONE
;
5061 ira_conflicts_p
= false;
5064 #ifndef IRA_NO_OBSTACK
5065 gcc_obstack_init (&ira_obstack
);
5067 bitmap_obstack_initialize (&ira_bitmap_obstack
);
5069 /* LRA uses its own infrastructure to handle caller save registers. */
5070 if (flag_caller_saves
&& !ira_use_lra_p
)
5071 init_caller_save ();
5073 if (flag_ira_verbose
< 10)
5075 internal_flag_ira_verbose
= flag_ira_verbose
;
5080 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
5081 ira_dump_file
= stderr
;
5084 setup_prohibited_mode_move_regs ();
5085 decrease_live_ranges_number ();
5086 df_note_add_problem ();
5088 /* DF_LIVE can't be used in the register allocator, too many other
5089 parts of the compiler depend on using the "classic" liveness
5090 interpretation of the DF_LR problem. See PR38711.
5091 Remove the problem, so that we don't spend time updating it in
5092 any of the df_analyze() calls during IRA/LRA. */
5094 df_remove_problem (df_live
);
5095 gcc_checking_assert (df_live
== NULL
);
5097 #ifdef ENABLE_CHECKING
5098 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
5103 if (ira_conflicts_p
)
5105 calculate_dominance_info (CDI_DOMINATORS
);
5107 if (split_live_ranges_for_shrink_wrap ())
5110 free_dominance_info (CDI_DOMINATORS
);
5113 df_clear_flags (DF_NO_INSN_RESCAN
);
5115 regstat_init_n_sets_and_refs ();
5116 regstat_compute_ri ();
5118 /* If we are not optimizing, then this is the only place before
5119 register allocation where dataflow is done. And that is needed
5120 to generate these warnings. */
5122 generate_setjmp_warnings ();
5124 /* Determine if the current function is a leaf before running IRA
5125 since this can impact optimizations done by the prologue and
5126 epilogue thus changing register elimination offsets. */
5127 crtl
->is_leaf
= leaf_function_p ();
5129 if (resize_reg_info () && flag_ira_loop_pressure
)
5130 ira_set_pseudo_classes (true, ira_dump_file
);
5132 rebuild_p
= update_equiv_regs ();
5134 setup_reg_equiv_init ();
5136 if (optimize
&& rebuild_p
)
5138 timevar_push (TV_JUMP
);
5139 rebuild_jump_labels (get_insns ());
5140 if (purge_all_dead_edges ())
5141 delete_unreachable_blocks ();
5142 timevar_pop (TV_JUMP
);
5145 allocated_reg_info_size
= max_reg_num ();
5147 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
5150 /* It is not worth to do such improvement when we use a simple
5151 allocation because of -O0 usage or because the function is too
5153 if (ira_conflicts_p
)
5154 find_moveable_pseudos ();
5156 max_regno_before_ira
= max_reg_num ();
5157 ira_setup_eliminable_regset ();
5159 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
5160 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
5161 ira_move_loops_num
= ira_additional_jumps_num
= 0;
5163 ira_assert (current_loops
== NULL
);
5164 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
5165 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
5167 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5168 fprintf (ira_dump_file
, "Building IRA IR\n");
5169 loops_p
= ira_build ();
5171 ira_assert (ira_conflicts_p
|| !loops_p
);
5173 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
5174 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
5175 /* It is just wasting compiler's time to pack spilled pseudos into
5176 stack slots in this case -- prohibit it. We also do this if
5177 there is setjmp call because a variable not modified between
5178 setjmp and longjmp the compiler is required to preserve its
5179 value and sharing slots does not guarantee it. */
5180 flag_ira_share_spill_slots
= FALSE
;
5184 ira_max_point_before_emit
= ira_max_point
;
5186 ira_initiate_emit_data ();
5190 max_regno
= max_reg_num ();
5191 if (ira_conflicts_p
)
5195 if (! ira_use_lra_p
)
5196 ira_initiate_assign ();
5205 ira_allocno_iterator ai
;
5207 FOR_EACH_ALLOCNO (a
, ai
)
5208 ALLOCNO_REGNO (a
) = REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
5212 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5213 fprintf (ira_dump_file
, "Flattening IR\n");
5214 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
5216 /* New insns were generated: add notes and recalculate live
5220 /* ??? Rebuild the loop tree, but why? Does the loop tree
5221 change if new insns were generated? Can that be handled
5222 by updating the loop tree incrementally? */
5223 loop_optimizer_finalize ();
5224 free_dominance_info (CDI_DOMINATORS
);
5225 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
5226 | LOOPS_HAVE_RECORDED_EXITS
);
5228 if (! ira_use_lra_p
)
5230 setup_allocno_assignment_flags ();
5231 ira_initiate_assign ();
5232 ira_reassign_conflict_allocnos (max_regno
);
5237 ira_finish_emit_data ();
5239 setup_reg_renumber ();
5241 calculate_allocation_cost ();
5243 #ifdef ENABLE_IRA_CHECKING
5244 if (ira_conflicts_p
)
5245 check_allocation ();
5248 if (max_regno
!= max_regno_before_ira
)
5250 regstat_free_n_sets_and_refs ();
5252 regstat_init_n_sets_and_refs ();
5253 regstat_compute_ri ();
5256 overall_cost_before
= ira_overall_cost
;
5257 if (! ira_conflicts_p
)
5261 fix_reg_equiv_init ();
5263 #ifdef ENABLE_IRA_CHECKING
5264 print_redundant_copies ();
5267 ira_spilled_reg_stack_slots_num
= 0;
5268 ira_spilled_reg_stack_slots
5269 = ((struct ira_spilled_reg_stack_slot
*)
5270 ira_allocate (max_regno
5271 * sizeof (struct ira_spilled_reg_stack_slot
)));
5272 memset (ira_spilled_reg_stack_slots
, 0,
5273 max_regno
* sizeof (struct ira_spilled_reg_stack_slot
));
5275 allocate_initial_values ();
5277 /* See comment for find_moveable_pseudos call. */
5278 if (ira_conflicts_p
)
5279 move_unallocated_pseudos ();
5281 /* Restore original values. */
5284 flag_caller_saves
= saved_flag_caller_saves
;
5285 flag_ira_region
= saved_flag_ira_region
;
5295 if (flag_ira_verbose
< 10)
5296 ira_dump_file
= dump_file
;
5298 timevar_push (TV_RELOAD
);
5301 if (current_loops
!= NULL
)
5303 loop_optimizer_finalize ();
5304 free_dominance_info (CDI_DOMINATORS
);
5306 FOR_ALL_BB_FN (bb
, cfun
)
5307 bb
->loop_father
= NULL
;
5308 current_loops
= NULL
;
5310 if (ira_conflicts_p
)
5311 ira_free (ira_spilled_reg_stack_slots
);
5315 lra (ira_dump_file
);
5316 /* ???!!! Move it before lra () when we use ira_reg_equiv in
5318 vec_free (reg_equivs
);
5324 df_set_flags (DF_NO_INSN_RESCAN
);
5325 build_insn_chain ();
5327 need_dce
= reload (get_insns (), ira_conflicts_p
);
5331 timevar_pop (TV_RELOAD
);
5333 timevar_push (TV_IRA
);
5335 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5337 ira_free (ira_spilled_reg_stack_slots
);
5338 ira_finish_assign ();
5341 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
5342 && overall_cost_before
!= ira_overall_cost
)
5343 fprintf (ira_dump_file
, "+++Overall after reload %d\n", ira_overall_cost
);
5345 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
5347 if (! ira_use_lra_p
)
5350 if (current_loops
!= NULL
)
5352 loop_optimizer_finalize ();
5353 free_dominance_info (CDI_DOMINATORS
);
5355 FOR_ALL_BB_FN (bb
, cfun
)
5356 bb
->loop_father
= NULL
;
5357 current_loops
= NULL
;
5360 regstat_free_n_sets_and_refs ();
5364 cleanup_cfg (CLEANUP_EXPENSIVE
);
5366 finish_reg_equiv ();
5368 bitmap_obstack_release (&ira_bitmap_obstack
);
5369 #ifndef IRA_NO_OBSTACK
5370 obstack_free (&ira_obstack
, NULL
);
5373 /* The code after the reload has changed so much that at this point
5374 we might as well just rescan everything. Note that
5375 df_rescan_all_insns is not going to help here because it does not
5376 touch the artificial uses and defs. */
5377 df_finish_pass (true);
5378 df_scan_alloc (NULL
);
5383 df_live_add_problem ();
5384 df_live_set_all_dirty ();
5390 if (need_dce
&& optimize
)
5393 /* Diagnose uses of the hard frame pointer when it is used as a global
5394 register. Often we can get away with letting the user appropriate
5395 the frame pointer, but we should let them know when code generation
5396 makes that impossible. */
5397 if (global_regs
[HARD_FRAME_POINTER_REGNUM
] && frame_pointer_needed
)
5399 tree decl
= global_regs_decl
[HARD_FRAME_POINTER_REGNUM
];
5400 error_at (DECL_SOURCE_LOCATION (current_function_decl
),
5401 "frame pointer required, but reserved");
5402 inform (DECL_SOURCE_LOCATION (decl
), "for %qD", decl
);
5405 timevar_pop (TV_IRA
);
5408 /* Run the integrated register allocator. */
5412 const pass_data pass_data_ira
=
5414 RTL_PASS
, /* type */
5416 OPTGROUP_NONE
, /* optinfo_flags */
5418 0, /* properties_required */
5419 0, /* properties_provided */
5420 0, /* properties_destroyed */
5421 0, /* todo_flags_start */
5422 TODO_do_not_ggc_collect
, /* todo_flags_finish */
5425 class pass_ira
: public rtl_opt_pass
5428 pass_ira (gcc::context
*ctxt
)
5429 : rtl_opt_pass (pass_data_ira
, ctxt
)
5432 /* opt_pass methods: */
5433 virtual unsigned int execute (function
*)
5439 }; // class pass_ira
5444 make_pass_ira (gcc::context
*ctxt
)
5446 return new pass_ira (ctxt
);
5451 const pass_data pass_data_reload
=
5453 RTL_PASS
, /* type */
5454 "reload", /* name */
5455 OPTGROUP_NONE
, /* optinfo_flags */
5456 TV_RELOAD
, /* tv_id */
5457 0, /* properties_required */
5458 0, /* properties_provided */
5459 0, /* properties_destroyed */
5460 0, /* todo_flags_start */
5461 0, /* todo_flags_finish */
5464 class pass_reload
: public rtl_opt_pass
5467 pass_reload (gcc::context
*ctxt
)
5468 : rtl_opt_pass (pass_data_reload
, ctxt
)
5471 /* opt_pass methods: */
5472 virtual unsigned int execute (function
*)
5478 }; // class pass_reload
5483 make_pass_reload (gcc::context
*ctxt
)
5485 return new pass_reload (ctxt
);