1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2018 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have 64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return 1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand 0 "register_operand")
68 if (GET_CODE (op) == SUBREG)
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return 1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand 0 "register_operand")
89 if (GET_CODE (op) == SUBREG)
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand 0 "register_operand")
110 if (GET_CODE (op) == SUBREG)
111 op = SUBREG_REG (op);
116 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return 1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand 0 "register_operand")
127 if (GET_CODE (op) == SUBREG)
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return 1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand 0 "register_operand")
149 if (GET_CODE (op) == SUBREG)
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return 1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand 0 "register_operand")
171 if (GET_CODE (op) == SUBREG)
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return 1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand 0 "register_operand")
193 if (GET_CODE (op) == SUBREG)
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return 1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return 1 if operand is constant -1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return 1 if op is a signed 5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
217 ;; Return 1 if op is a unsigned 3-bit constant integer.
218 (define_predicate "u3bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
222 ;; Return 1 if op is a unsigned 5-bit constant integer.
223 (define_predicate "u5bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
227 ;; Return 1 if op is a unsigned 6-bit constant integer.
228 (define_predicate "u6bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
232 ;; Return 1 if op is an unsigned 7-bit constant integer.
233 (define_predicate "u7bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
237 ;; Return 1 if op is a signed 8-bit constant integer.
238 ;; Integer multiplication complete more quickly
239 (define_predicate "s8bit_cint_operand"
240 (and (match_code "const_int")
241 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
243 ;; Return 1 if op is a unsigned 10-bit constant integer.
244 (define_predicate "u10bit_cint_operand"
245 (and (match_code "const_int")
246 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
248 ;; Return 1 if op is a constant integer that can fit in a D field.
249 (define_predicate "short_cint_operand"
250 (and (match_code "const_int")
251 (match_test "satisfies_constraint_I (op)")))
253 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
254 (define_predicate "u_short_cint_operand"
255 (and (match_code "const_int")
256 (match_test "satisfies_constraint_K (op)")))
258 ;; Return 1 if op is a constant integer that is a signed 16-bit constant
259 ;; shifted left 16 bits
260 (define_predicate "upper16_cint_operand"
261 (and (match_code "const_int")
262 (match_test "satisfies_constraint_L (op)")))
264 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
265 (define_predicate "non_short_cint_operand"
266 (and (match_code "const_int")
267 (match_test "(unsigned HOST_WIDE_INT)
268 (INTVAL (op) + 0x8000) >= 0x10000")))
270 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
271 (define_predicate "exact_log2_cint_operand"
272 (and (match_code "const_int")
273 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
275 ;; Match op = 0 or op = 1.
276 (define_predicate "const_0_to_1_operand"
277 (and (match_code "const_int")
278 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
281 (define_predicate "const_0_to_3_operand"
282 (and (match_code "const_int")
283 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
285 ;; Match op = 2 or op = 3.
286 (define_predicate "const_2_to_3_operand"
287 (and (match_code "const_int")
288 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
291 (define_predicate "const_0_to_7_operand"
292 (and (match_code "const_int")
293 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
296 (define_predicate "const_0_to_12_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op), 0, 12)")))
301 (define_predicate "const_0_to_15_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
305 ;; Return 1 if op is a register that is not special.
306 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
307 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
308 ;; the fact that SFmode is represented as DFmode in the VSX registers.
309 (define_predicate "gpc_reg_operand"
310 (match_operand 0 "register_operand")
312 if (GET_CODE (op) == SUBREG)
314 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
317 op = SUBREG_REG (op);
323 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
326 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
329 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
332 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
335 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
336 ;; allow floating point or vector registers. Since vector registers are not
337 ;; allowed, we don't have to reject SFmode/SImode subregs.
338 (define_predicate "int_reg_operand"
339 (match_operand 0 "register_operand")
341 if (GET_CODE (op) == SUBREG)
343 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
346 op = SUBREG_REG (op);
352 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
355 return INT_REGNO_P (REGNO (op));
358 ;; Like int_reg_operand, but don't return true for pseudo registers
359 ;; We don't have to check for SF SUBREGS because pseudo registers
360 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
361 (define_predicate "int_reg_operand_not_pseudo"
362 (match_operand 0 "register_operand")
364 if (GET_CODE (op) == SUBREG)
365 op = SUBREG_REG (op);
370 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
373 return INT_REGNO_P (REGNO (op));
376 ;; Like int_reg_operand, but only return true for base registers
377 (define_predicate "base_reg_operand"
378 (match_operand 0 "int_reg_operand")
380 if (GET_CODE (op) == SUBREG)
381 op = SUBREG_REG (op);
386 return (REGNO (op) != FIRST_GPR_REGNO);
390 ;; Return true if this is a traditional floating point register
391 (define_predicate "fpr_reg_operand"
392 (match_code "reg,subreg")
396 if (GET_CODE (op) == SUBREG)
397 op = SUBREG_REG (op);
403 if (r >= FIRST_PSEUDO_REGISTER)
406 return FP_REGNO_P (r);
409 ;; Return 1 if op is a HTM specific SPR register.
410 (define_predicate "htm_spr_reg_operand"
411 (match_operand 0 "register_operand")
416 if (GET_CODE (op) == SUBREG)
417 op = SUBREG_REG (op);
436 ;; Return 1 if op is a general purpose register that is an even register
437 ;; which suitable for a load/store quad operation
438 ;; Subregs are not allowed here because when they are combine can
439 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
440 ;; think the innermost reg needs reloading, in TImode instead of
441 ;; PTImode. So reload will choose a reg in TImode which has no
442 ;; requirement that the reg be even.
443 (define_predicate "quad_int_reg_operand"
448 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
452 if (r >= FIRST_PSEUDO_REGISTER)
455 return (INT_REGNO_P (r) && ((r & 1) == 0));
458 ;; Return 1 if op is a register that is a condition register field.
459 (define_predicate "cc_reg_operand"
460 (match_operand 0 "register_operand")
462 if (GET_CODE (op) == SUBREG)
463 op = SUBREG_REG (op);
468 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
471 return CR_REGNO_P (REGNO (op));
474 ;; Return 1 if op is a register that is a condition register field not cr0.
475 (define_predicate "cc_reg_not_cr0_operand"
476 (match_operand 0 "register_operand")
478 if (GET_CODE (op) == SUBREG)
479 op = SUBREG_REG (op);
484 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
487 return CR_REGNO_NOT_CR0_P (REGNO (op));
490 ;; Return 1 if op is a constant integer valid for D field
491 ;; or non-special register register.
492 (define_predicate "reg_or_short_operand"
493 (if_then_else (match_code "const_int")
494 (match_operand 0 "short_cint_operand")
495 (match_operand 0 "gpc_reg_operand")))
497 ;; Return 1 if op is a constant integer valid for DS field
498 ;; or non-special register.
499 (define_predicate "reg_or_aligned_short_operand"
500 (if_then_else (match_code "const_int")
501 (and (match_operand 0 "short_cint_operand")
502 (match_test "!(INTVAL (op) & 3)"))
503 (match_operand 0 "gpc_reg_operand")))
505 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
506 ;; or non-special register.
507 (define_predicate "reg_or_u_short_operand"
508 (if_then_else (match_code "const_int")
509 (match_operand 0 "u_short_cint_operand")
510 (match_operand 0 "gpc_reg_operand")))
512 ;; Return 1 if op is any constant integer or a non-special register.
513 (define_predicate "reg_or_cint_operand"
514 (ior (match_code "const_int")
515 (match_operand 0 "gpc_reg_operand")))
517 ;; Return 1 if op is constant zero or a non-special register.
518 (define_predicate "reg_or_zero_operand"
519 (ior (match_operand 0 "zero_constant")
520 (match_operand 0 "gpc_reg_operand")))
522 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
523 (define_predicate "add_cint_operand"
524 (and (match_code "const_int")
525 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
526 + (mode == SImode ? 0x80000000 : 0x80008000))
527 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
529 ;; Return 1 if op is a constant integer valid for addition
530 ;; or non-special register.
531 (define_predicate "reg_or_add_cint_operand"
532 (if_then_else (match_code "const_int")
533 (match_operand 0 "add_cint_operand")
534 (match_operand 0 "gpc_reg_operand")))
536 ;; Return 1 if op is a constant integer valid for subtraction
537 ;; or non-special register.
538 (define_predicate "reg_or_sub_cint_operand"
539 (if_then_else (match_code "const_int")
540 (match_test "(unsigned HOST_WIDE_INT)
541 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
542 < (unsigned HOST_WIDE_INT) 0x100000000ll")
543 (match_operand 0 "gpc_reg_operand")))
545 ;; Return 1 if op is any 32-bit unsigned constant integer
546 ;; or non-special register.
547 (define_predicate "reg_or_logical_cint_operand"
548 (if_then_else (match_code "const_int")
549 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
551 || ((INTVAL (op) & GET_MODE_MASK (mode)
552 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
553 (match_operand 0 "gpc_reg_operand")))
555 ;; Like reg_or_logical_cint_operand, but allow vsx registers
556 (define_predicate "vsx_reg_or_cint_operand"
557 (ior (match_operand 0 "vsx_register_operand")
558 (match_operand 0 "reg_or_logical_cint_operand")))
560 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
561 ;; with no more than one instruction per word.
562 (define_predicate "easy_fp_constant"
563 (match_code "const_double")
565 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
567 /* Consider all constants with -msoft-float to be easy when regs are
568 32-bit and thus can be loaded with a maximum of 2 insns. For
569 64-bit avoid long dependent insn sequences. */
570 if (TARGET_SOFT_FLOAT)
572 if (!TARGET_POWERPC64)
575 int size = GET_MODE_SIZE (mode);
579 int load_from_mem_insns = 2;
581 load_from_mem_insns++;
582 if (TARGET_CMODEL != CMODEL_SMALL)
583 load_from_mem_insns++;
584 if (num_insns_constant (op, mode) <= load_from_mem_insns)
588 /* 0.0D is not all zero bits. */
589 if (DECIMAL_FLOAT_MODE_P (mode))
592 /* The constant 0.0 is easy under VSX. */
593 if (TARGET_VSX && op == CONST0_RTX (mode))
596 /* Otherwise consider floating point constants hard, so that the
597 constant gets pushed to memory during the early RTL phases. This
598 has the advantage that double precision constants that can be
599 represented in single precision without a loss of precision will
600 use single precision loads. */
604 ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
605 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
607 (define_predicate "xxspltib_constant_split"
608 (match_code "const_vector,vec_duplicate,const_int")
613 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
616 return num_insns > 1;
620 ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB
623 (define_predicate "xxspltib_constant_nosplit"
624 (match_code "const_vector,vec_duplicate,const_int")
629 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
632 return num_insns == 1;
635 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
636 ;; vector register without using memory.
637 (define_predicate "easy_vector_constant"
638 (match_code "const_vector")
640 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
645 if (zero_constant (op, mode) || all_ones_constant (op, mode))
649 && xxspltib_constant_p (op, mode, &num_insns, &value))
652 return easy_altivec_constant (op, mode);
658 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
659 (define_predicate "easy_vector_constant_add_self"
660 (and (match_code "const_vector")
661 (and (match_test "TARGET_ALTIVEC")
662 (match_test "easy_altivec_constant (op, mode)")))
666 if (mode == V2DImode || mode == V2DFmode)
668 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
669 val = const_vector_elt_as_int (op, elt);
670 val = ((val & 0xff) ^ 0x80) - 0x80;
671 return EASY_VECTOR_15_ADD_SELF (val);
674 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
675 (define_predicate "easy_vector_constant_msb"
676 (and (match_code "const_vector")
677 (and (match_test "TARGET_ALTIVEC")
678 (match_test "easy_altivec_constant (op, mode)")))
682 if (mode == V2DImode || mode == V2DFmode)
684 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
685 val = const_vector_elt_as_int (op, elt);
686 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
689 ;; Return true if this is an easy altivec constant that we form
691 (define_predicate "easy_vector_constant_vsldoi"
692 (and (match_code "const_vector")
693 (and (match_test "TARGET_ALTIVEC")
694 (and (match_test "easy_altivec_constant (op, mode)")
695 (match_test "vspltis_shifted (op) != 0")))))
697 ;; Return 1 if operand is a vector int register or is either a vector constant
698 ;; of all 0 bits of a vector constant of all 1 bits.
699 (define_predicate "vector_int_reg_or_same_bit"
700 (match_code "reg,subreg,const_vector")
702 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
705 else if (REG_P (op) || SUBREG_P (op))
706 return vint_operand (op, mode);
709 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
712 ;; Return 1 if operand is 0.0.
713 (define_predicate "zero_fp_constant"
714 (and (match_code "const_double")
715 (match_test "SCALAR_FLOAT_MODE_P (mode)
716 && op == CONST0_RTX (mode)")))
718 ;; Return 1 if the operand is in volatile memory. Note that during the
719 ;; RTL generation phase, memory_operand does not return TRUE for volatile
720 ;; memory references. So this function allows us to recognize volatile
721 ;; references where it's safe.
722 (define_predicate "volatile_mem_operand"
723 (and (and (match_code "mem")
724 (match_test "MEM_VOLATILE_P (op)"))
725 (if_then_else (match_test "reload_completed")
726 (match_operand 0 "memory_operand")
727 (match_test "memory_address_p (mode, XEXP (op, 0))"))))
729 ;; Return 1 if the operand is an offsettable memory operand.
730 (define_predicate "offsettable_mem_operand"
731 (and (match_operand 0 "memory_operand")
732 (match_test "offsettable_nonstrict_memref_p (op)")))
734 ;; Return 1 if the operand is a simple offsettable memory operand
735 ;; that does not include pre-increment, post-increment, etc.
736 (define_predicate "simple_offsettable_mem_operand"
737 (match_operand 0 "offsettable_mem_operand")
739 rtx addr = XEXP (op, 0);
741 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
744 if (!CONSTANT_P (XEXP (addr, 1)))
747 return base_reg_operand (XEXP (addr, 0), Pmode);
750 ;; Return 1 if the operand is suitable for load/store quad memory.
751 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
752 (define_predicate "quad_memory_operand"
755 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
758 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128)
761 return quad_address_p (XEXP (op, 0), mode, false);
764 ;; Return 1 if the operand is suitable for load/store to vector registers with
765 ;; d-form addressing (register+offset), which was added in ISA 3.0.
766 ;; Unlike quad_memory_operand, we do not have to check for alignment.
767 (define_predicate "vsx_quad_dform_memory_operand"
770 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
773 return quad_address_p (XEXP (op, 0), mode, false);
776 ;; Return 1 if the operand is an indexed or indirect memory operand.
777 (define_predicate "indexed_or_indirect_operand"
781 if (VECTOR_MEM_ALTIVEC_P (mode)
782 && GET_CODE (op) == AND
783 && GET_CODE (XEXP (op, 1)) == CONST_INT
784 && INTVAL (XEXP (op, 1)) == -16)
787 return indexed_or_indirect_address (op, mode);
790 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
791 ;; moves are supported.
792 (define_predicate "reg_or_indexed_operand"
793 (match_code "mem,reg,subreg")
796 return indexed_or_indirect_operand (op, mode);
797 else if (TARGET_DIRECT_MOVE)
798 return register_operand (op, mode);
803 ;; Return 1 if the operand is an indexed or indirect memory operand with an
804 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
805 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
806 ;; while VSX uses the full address and traps)
807 (define_predicate "altivec_indexed_or_indirect_operand"
811 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
812 && GET_CODE (op) == AND
813 && GET_CODE (XEXP (op, 1)) == CONST_INT
814 && INTVAL (XEXP (op, 1)) == -16)
815 return indexed_or_indirect_address (XEXP (op, 0), mode);
820 ;; Return 1 if the operand is an indexed or indirect address.
821 (define_special_predicate "indexed_or_indirect_address"
822 (and (match_test "REG_P (op)
823 || (GET_CODE (op) == PLUS
824 /* Omit testing REG_P (XEXP (op, 0)). */
825 && REG_P (XEXP (op, 1)))")
826 (match_operand 0 "address_operand")))
828 ;; Return 1 if the operand is an index-form address.
829 (define_special_predicate "indexed_address"
830 (match_test "(GET_CODE (op) == PLUS
831 && REG_P (XEXP (op, 0))
832 && REG_P (XEXP (op, 1)))"))
834 ;; Return 1 if the operand is a MEM with an update-form address. This may
835 ;; also include update-indexed form.
836 (define_special_predicate "update_address_mem"
837 (match_test "(MEM_P (op)
838 && (GET_CODE (XEXP (op, 0)) == PRE_INC
839 || GET_CODE (XEXP (op, 0)) == PRE_DEC
840 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
842 ;; Return 1 if the operand is a MEM with an indexed-form address.
843 (define_special_predicate "indexed_address_mem"
844 (match_test "(MEM_P (op)
845 && (indexed_address (XEXP (op, 0), mode)
846 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
847 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
849 ;; Return 1 if the operand is either a non-special register or can be used
850 ;; as the operand of a `mode' add insn.
851 (define_predicate "add_operand"
852 (if_then_else (match_code "const_int")
853 (match_test "satisfies_constraint_I (op)
854 || satisfies_constraint_L (op)")
855 (match_operand 0 "gpc_reg_operand")))
857 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
858 (define_predicate "adde_operand"
859 (if_then_else (match_code "const_int")
860 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
861 (match_operand 0 "gpc_reg_operand")))
863 ;; Return 1 if OP is a constant but not a valid add_operand.
864 (define_predicate "non_add_cint_operand"
865 (and (match_code "const_int")
866 (match_test "!satisfies_constraint_I (op)
867 && !satisfies_constraint_L (op)")))
869 ;; Return 1 if the operand is a constant that can be used as the operand
870 ;; of an AND, OR or XOR.
871 (define_predicate "logical_const_operand"
872 (match_code "const_int")
876 opl = INTVAL (op) & GET_MODE_MASK (mode);
878 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
879 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
882 ;; Return 1 if the operand is a non-special register or a constant that
883 ;; can be used as the operand of an AND, OR or XOR.
884 (define_predicate "logical_operand"
885 (ior (match_operand 0 "gpc_reg_operand")
886 (match_operand 0 "logical_const_operand")))
888 ;; Return 1 if op is a constant that is not a logical operand, but could
889 ;; be split into one.
890 (define_predicate "non_logical_cint_operand"
891 (and (match_code "const_int,const_wide_int")
892 (and (not (match_operand 0 "logical_operand"))
893 (match_operand 0 "reg_or_logical_cint_operand"))))
895 ;; Return 1 if the operand is either a non-special register or a
896 ;; constant that can be used as the operand of a logical AND.
897 (define_predicate "and_operand"
898 (ior (and (match_code "const_int")
899 (match_test "rs6000_is_valid_and_mask (op, mode)"))
900 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
901 (match_operand 0 "gpc_reg_operand")
902 (match_operand 0 "logical_operand"))))
904 ;; Return 1 if the operand is either a logical operand or a short cint operand.
905 (define_predicate "scc_eq_operand"
906 (ior (match_operand 0 "logical_operand")
907 (match_operand 0 "short_cint_operand")))
909 ;; Return 1 if the operand is a general non-special register or memory operand.
910 (define_predicate "reg_or_mem_operand"
911 (ior (match_operand 0 "memory_operand")
912 (and (match_code "mem")
913 (match_test "macho_lo_sum_memory_operand (op, mode)"))
914 (match_operand 0 "volatile_mem_operand")
915 (match_operand 0 "gpc_reg_operand")))
917 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
918 (define_predicate "zero_reg_mem_operand"
919 (ior (and (match_test "TARGET_VSX")
920 (match_operand 0 "zero_fp_constant"))
921 (match_operand 0 "reg_or_mem_operand")))
923 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
924 ;; data types inside of a vector that scalar instructions operate on
925 (define_predicate "vsx_scalar_64bit"
926 (match_code "const_int")
928 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
931 ;; Return 1 if the operand is a general register or memory operand without
932 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
934 (define_predicate "lwa_operand"
935 (match_code "reg,subreg,mem")
937 rtx inner, addr, offset;
940 if (reload_completed && GET_CODE (inner) == SUBREG)
941 inner = SUBREG_REG (inner);
943 if (gpc_reg_operand (inner, mode))
945 if (!memory_operand (inner, mode))
948 addr = XEXP (inner, 0);
949 if (GET_CODE (addr) == PRE_INC
950 || GET_CODE (addr) == PRE_DEC
951 || (GET_CODE (addr) == PRE_MODIFY
952 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
954 if (GET_CODE (addr) == LO_SUM
955 && GET_CODE (XEXP (addr, 0)) == REG
956 && GET_CODE (XEXP (addr, 1)) == CONST)
957 addr = XEXP (XEXP (addr, 1), 0);
958 if (GET_CODE (addr) != PLUS)
960 offset = XEXP (addr, 1);
961 if (GET_CODE (offset) != CONST_INT)
963 return INTVAL (offset) % 4 == 0;
966 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
967 (define_predicate "symbol_ref_operand"
968 (and (match_code "symbol_ref")
969 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
970 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
972 ;; Return 1 if op is an operand that can be loaded via the GOT.
973 ;; or non-special register register field no cr0
974 (define_predicate "got_operand"
975 (match_code "symbol_ref,const,label_ref"))
977 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
978 ;; excluding labels involving addition.
979 (define_predicate "got_no_const_operand"
980 (match_code "symbol_ref,label_ref"))
982 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
983 (define_predicate "rs6000_tls_symbol_ref"
984 (and (match_code "symbol_ref")
985 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
987 ;; Return 1 for the UNSPEC used in TLS call operands
988 (define_predicate "unspec_tls"
989 (match_code "unspec")
991 return XINT (op, 1) == UNSPEC_TLSGD || XINT (op, 1) == UNSPEC_TLSLD;
994 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
995 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
996 (define_predicate "call_operand"
997 (if_then_else (match_code "reg")
998 (match_test "REGNO (op) == LR_REGNO
999 || REGNO (op) == CTR_REGNO
1000 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1001 (match_code "symbol_ref")))
1003 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1004 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
1005 (define_predicate "indirect_call_operand"
1006 (match_code "reg,unspec")
1009 return (REGNO (op) == LR_REGNO
1010 || REGNO (op) == CTR_REGNO);
1011 if (GET_CODE (op) == UNSPEC)
1013 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1015 op = XVECEXP (op, 0, 0);
1016 return REG_P (op) && REGNO (op) == CTR_REGNO;
1021 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1023 (define_predicate "current_file_function_operand"
1024 (and (match_code "symbol_ref")
1025 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1026 && (SYMBOL_REF_LOCAL_P (op)
1027 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1028 && !decl_replaceable_p (current_function_decl)))
1029 && !((DEFAULT_ABI == ABI_AIX
1030 || DEFAULT_ABI == ABI_ELFv2)
1031 && (SYMBOL_REF_EXTERNAL_P (op)
1032 || SYMBOL_REF_WEAK (op)))")))
1034 ;; Return 1 if this operand is a valid input for a move insn.
1035 (define_predicate "input_operand"
1036 (match_code "symbol_ref,const,reg,subreg,mem,
1037 const_double,const_wide_int,const_vector,const_int")
1039 /* Memory is always valid. */
1040 if (memory_operand (op, mode))
1043 /* For floating-point, easy constants are valid. */
1044 if (SCALAR_FLOAT_MODE_P (mode)
1045 && easy_fp_constant (op, mode))
1048 /* Allow any integer constant. */
1049 if (GET_MODE_CLASS (mode) == MODE_INT
1050 && CONST_SCALAR_INT_P (op))
1053 /* Allow easy vector constants. */
1054 if (GET_CODE (op) == CONST_VECTOR
1055 && easy_vector_constant (op, mode))
1058 /* For floating-point or multi-word mode, the only remaining valid type
1060 if (SCALAR_FLOAT_MODE_P (mode)
1061 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1062 return register_operand (op, mode);
1064 /* We don't allow moving the carry bit around. */
1065 if (ca_operand (op, mode))
1068 /* The only cases left are integral modes one word or smaller (we
1069 do not get called for MODE_CC values). These can be in any
1071 if (register_operand (op, mode))
1074 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1076 if (DEFAULT_ABI == ABI_V4
1077 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1078 && small_data_operand (op, Pmode))
1084 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1085 (define_predicate "splat_input_operand"
1086 (match_code "reg,subreg,mem")
1092 else if (mode == DImode)
1094 else if (mode == SImode && TARGET_P9_VECTOR)
1096 else if (mode == SFmode && TARGET_P9_VECTOR)
1103 rtx addr = XEXP (op, 0);
1105 if (! volatile_ok && MEM_VOLATILE_P (op))
1108 if (lra_in_progress || reload_completed)
1109 return indexed_or_indirect_address (addr, vmode);
1111 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1113 return gpc_reg_operand (op, mode);
1116 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1117 (define_predicate "rotate_mask_operator"
1118 (match_code "rotate,ashift,lshiftrt"))
1120 ;; Return true if operand is boolean operator.
1121 (define_predicate "boolean_operator"
1122 (match_code "and,ior,xor"))
1124 ;; Return true if operand is OR-form of boolean operator.
1125 (define_predicate "boolean_or_operator"
1126 (match_code "ior,xor"))
1128 ;; Return true if operand is an equality operator.
1129 (define_special_predicate "equality_operator"
1130 (match_code "eq,ne"))
1132 ;; Return 1 if OP is a comparison operation that is valid for a branch
1133 ;; instruction. We check the opcode against the mode of the CC value.
1134 ;; validate_condition_mode is an assertion.
1135 (define_predicate "branch_comparison_operator"
1136 (and (match_operand 0 "comparison_operator")
1137 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1138 (match_test "validate_condition_mode (GET_CODE (op),
1139 GET_MODE (XEXP (op, 0))),
1142 ;; Return 1 if OP is an unsigned comparison operator.
1143 (define_predicate "unsigned_comparison_operator"
1144 (match_code "ltu,gtu,leu,geu"))
1146 ;; Return 1 if OP is a signed comparison operator.
1147 (define_predicate "signed_comparison_operator"
1148 (match_code "lt,gt,le,ge"))
1150 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1151 ;; it must be a positive comparison.
1152 (define_predicate "scc_comparison_operator"
1153 (and (match_operand 0 "branch_comparison_operator")
1154 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1156 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1158 (define_predicate "scc_rev_comparison_operator"
1159 (and (match_operand 0 "branch_comparison_operator")
1160 (match_code "ne,le,ge,leu,geu,ordered")))
1162 ;; Return 1 if OP is a comparison operator suitable for floating point
1163 ;; vector/scalar comparisons that generate a -1/0 mask.
1164 (define_predicate "fpmask_comparison_operator"
1165 (match_code "eq,gt,ge"))
1167 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1168 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1169 ;; fpmask_comparison_operator).
1170 (define_predicate "invert_fpmask_comparison_operator"
1171 (match_code "ne,unlt,unle"))
1173 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1174 ;; comparisons that generate a -1/0 mask.
1175 (define_predicate "vecint_comparison_operator"
1176 (match_code "eq,gt,gtu"))
1178 ;; Return 1 if OP is a comparison operation that is valid for a branch
1179 ;; insn, which is true if the corresponding bit in the CC register is set.
1180 (define_predicate "branch_positive_comparison_operator"
1181 (and (match_operand 0 "branch_comparison_operator")
1182 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1184 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1186 (define_predicate "save_world_operation"
1187 (match_code "parallel")
1192 int count = XVECLEN (op, 0);
1198 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1199 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1202 for (i=1; i <= 18; i++)
1204 elt = XVECEXP (op, 0, index++);
1205 if (GET_CODE (elt) != SET
1206 || GET_CODE (SET_DEST (elt)) != MEM
1207 || ! memory_operand (SET_DEST (elt), DFmode)
1208 || GET_CODE (SET_SRC (elt)) != REG
1209 || GET_MODE (SET_SRC (elt)) != DFmode)
1213 for (i=1; i <= 12; i++)
1215 elt = XVECEXP (op, 0, index++);
1216 if (GET_CODE (elt) != SET
1217 || GET_CODE (SET_DEST (elt)) != MEM
1218 || GET_CODE (SET_SRC (elt)) != REG
1219 || GET_MODE (SET_SRC (elt)) != V4SImode)
1223 for (i=1; i <= 19; i++)
1225 elt = XVECEXP (op, 0, index++);
1226 if (GET_CODE (elt) != SET
1227 || GET_CODE (SET_DEST (elt)) != MEM
1228 || ! memory_operand (SET_DEST (elt), Pmode)
1229 || GET_CODE (SET_SRC (elt)) != REG
1230 || GET_MODE (SET_SRC (elt)) != Pmode)
1234 elt = XVECEXP (op, 0, index++);
1235 if (GET_CODE (elt) != SET
1236 || GET_CODE (SET_DEST (elt)) != MEM
1237 || ! memory_operand (SET_DEST (elt), Pmode)
1238 || GET_CODE (SET_SRC (elt)) != REG
1239 || REGNO (SET_SRC (elt)) != CR2_REGNO
1240 || GET_MODE (SET_SRC (elt)) != Pmode)
1243 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1244 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1249 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1251 (define_predicate "restore_world_operation"
1252 (match_code "parallel")
1257 int count = XVECLEN (op, 0);
1263 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1264 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1265 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1268 elt = XVECEXP (op, 0, index++);
1269 if (GET_CODE (elt) != SET
1270 || GET_CODE (SET_SRC (elt)) != MEM
1271 || ! memory_operand (SET_SRC (elt), Pmode)
1272 || GET_CODE (SET_DEST (elt)) != REG
1273 || REGNO (SET_DEST (elt)) != CR2_REGNO
1274 || GET_MODE (SET_DEST (elt)) != Pmode)
1277 for (i=1; i <= 19; i++)
1279 elt = XVECEXP (op, 0, index++);
1280 if (GET_CODE (elt) != SET
1281 || GET_CODE (SET_SRC (elt)) != MEM
1282 || ! memory_operand (SET_SRC (elt), Pmode)
1283 || GET_CODE (SET_DEST (elt)) != REG
1284 || GET_MODE (SET_DEST (elt)) != Pmode)
1288 for (i=1; i <= 12; i++)
1290 elt = XVECEXP (op, 0, index++);
1291 if (GET_CODE (elt) != SET
1292 || GET_CODE (SET_SRC (elt)) != MEM
1293 || GET_CODE (SET_DEST (elt)) != REG
1294 || GET_MODE (SET_DEST (elt)) != V4SImode)
1298 for (i=1; i <= 18; i++)
1300 elt = XVECEXP (op, 0, index++);
1301 if (GET_CODE (elt) != SET
1302 || GET_CODE (SET_SRC (elt)) != MEM
1303 || ! memory_operand (SET_SRC (elt), DFmode)
1304 || GET_CODE (SET_DEST (elt)) != REG
1305 || GET_MODE (SET_DEST (elt)) != DFmode)
1309 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1310 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1311 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1312 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1313 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1318 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1319 (define_predicate "vrsave_operation"
1320 (match_code "parallel")
1322 int count = XVECLEN (op, 0);
1323 unsigned int dest_regno, src_regno;
1327 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1328 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1329 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1330 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1333 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1334 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1336 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1339 for (i = 1; i < count; i++)
1341 rtx elt = XVECEXP (op, 0, i);
1343 if (GET_CODE (elt) != CLOBBER
1344 && GET_CODE (elt) != SET)
1351 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1352 (define_predicate "mfcr_operation"
1353 (match_code "parallel")
1355 int count = XVECLEN (op, 0);
1358 /* Perform a quick check so we don't blow up below. */
1360 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1361 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1362 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1365 for (i = 0; i < count; i++)
1367 rtx exp = XVECEXP (op, 0, i);
1372 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1374 if (GET_CODE (src_reg) != REG
1375 || GET_MODE (src_reg) != CCmode
1376 || ! CR_REGNO_P (REGNO (src_reg)))
1379 if (GET_CODE (exp) != SET
1380 || GET_CODE (SET_DEST (exp)) != REG
1381 || GET_MODE (SET_DEST (exp)) != SImode
1382 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1384 unspec = SET_SRC (exp);
1385 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1387 if (GET_CODE (unspec) != UNSPEC
1388 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1389 || XVECLEN (unspec, 0) != 2
1390 || XVECEXP (unspec, 0, 0) != src_reg
1391 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1392 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1398 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1399 (define_predicate "mtcrf_operation"
1400 (match_code "parallel")
1402 int count = XVECLEN (op, 0);
1406 /* Perform a quick check so we don't blow up below. */
1408 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1409 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1410 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1412 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1414 if (GET_CODE (src_reg) != REG
1415 || GET_MODE (src_reg) != SImode
1416 || ! INT_REGNO_P (REGNO (src_reg)))
1419 for (i = 0; i < count; i++)
1421 rtx exp = XVECEXP (op, 0, i);
1425 if (GET_CODE (exp) != SET
1426 || GET_CODE (SET_DEST (exp)) != REG
1427 || GET_MODE (SET_DEST (exp)) != CCmode
1428 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1430 unspec = SET_SRC (exp);
1431 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1433 if (GET_CODE (unspec) != UNSPEC
1434 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1435 || XVECLEN (unspec, 0) != 2
1436 || XVECEXP (unspec, 0, 0) != src_reg
1437 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1438 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1444 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1445 (define_predicate "crsave_operation"
1446 (match_code "parallel")
1448 int count = XVECLEN (op, 0);
1451 for (i = 1; i < count; i++)
1453 rtx exp = XVECEXP (op, 0, i);
1455 if (GET_CODE (exp) != USE
1456 || GET_CODE (XEXP (exp, 0)) != REG
1457 || GET_MODE (XEXP (exp, 0)) != CCmode
1458 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1464 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1465 (define_predicate "lmw_operation"
1466 (match_code "parallel")
1468 int count = XVECLEN (op, 0);
1469 unsigned int dest_regno;
1471 unsigned int base_regno;
1472 HOST_WIDE_INT offset;
1475 /* Perform a quick check so we don't blow up below. */
1477 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1478 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1479 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1482 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1483 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1486 || count != 32 - (int) dest_regno)
1489 if (legitimate_indirect_address_p (src_addr, 0))
1492 base_regno = REGNO (src_addr);
1493 if (base_regno == 0)
1496 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1498 offset = INTVAL (XEXP (src_addr, 1));
1499 base_regno = REGNO (XEXP (src_addr, 0));
1504 for (i = 0; i < count; i++)
1506 rtx elt = XVECEXP (op, 0, i);
1509 HOST_WIDE_INT newoffset;
1511 if (GET_CODE (elt) != SET
1512 || GET_CODE (SET_DEST (elt)) != REG
1513 || GET_MODE (SET_DEST (elt)) != SImode
1514 || REGNO (SET_DEST (elt)) != dest_regno + i
1515 || GET_CODE (SET_SRC (elt)) != MEM
1516 || GET_MODE (SET_SRC (elt)) != SImode)
1518 newaddr = XEXP (SET_SRC (elt), 0);
1519 if (legitimate_indirect_address_p (newaddr, 0))
1524 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1526 addr_reg = XEXP (newaddr, 0);
1527 newoffset = INTVAL (XEXP (newaddr, 1));
1531 if (REGNO (addr_reg) != base_regno
1532 || newoffset != offset + 4 * i)
1539 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1540 (define_predicate "stmw_operation"
1541 (match_code "parallel")
1543 int count = XVECLEN (op, 0);
1544 unsigned int src_regno;
1546 unsigned int base_regno;
1547 HOST_WIDE_INT offset;
1550 /* Perform a quick check so we don't blow up below. */
1552 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1553 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1554 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1557 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1558 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1561 || count != 32 - (int) src_regno)
1564 if (legitimate_indirect_address_p (dest_addr, 0))
1567 base_regno = REGNO (dest_addr);
1568 if (base_regno == 0)
1571 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1573 offset = INTVAL (XEXP (dest_addr, 1));
1574 base_regno = REGNO (XEXP (dest_addr, 0));
1579 for (i = 0; i < count; i++)
1581 rtx elt = XVECEXP (op, 0, i);
1584 HOST_WIDE_INT newoffset;
1586 if (GET_CODE (elt) != SET
1587 || GET_CODE (SET_SRC (elt)) != REG
1588 || GET_MODE (SET_SRC (elt)) != SImode
1589 || REGNO (SET_SRC (elt)) != src_regno + i
1590 || GET_CODE (SET_DEST (elt)) != MEM
1591 || GET_MODE (SET_DEST (elt)) != SImode)
1593 newaddr = XEXP (SET_DEST (elt), 0);
1594 if (legitimate_indirect_address_p (newaddr, 0))
1599 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1601 addr_reg = XEXP (newaddr, 0);
1602 newoffset = INTVAL (XEXP (newaddr, 1));
1606 if (REGNO (addr_reg) != base_regno
1607 || newoffset != offset + 4 * i)
1614 ;; Return 1 if OP is a stack tie operand.
1615 (define_predicate "tie_operand"
1616 (match_code "parallel")
1618 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1619 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1620 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1621 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1624 ;; Match a small code model toc reference (or medium and large
1625 ;; model toc references before reload).
1626 (define_predicate "small_toc_ref"
1627 (match_code "unspec,plus")
1629 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1632 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1635 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1636 ;; GPR registers on power8.
1637 (define_predicate "fusion_gpr_addis"
1638 (match_code "const_int,high,plus")
1640 HOST_WIDE_INT value;
1643 if (GET_CODE (op) == HIGH)
1646 if (CONST_INT_P (op))
1649 else if (GET_CODE (op) == PLUS
1650 && base_reg_operand (XEXP (op, 0), Pmode)
1651 && CONST_INT_P (XEXP (op, 1)))
1652 int_const = XEXP (op, 1);
1657 value = INTVAL (int_const);
1658 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1661 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1664 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1666 return (IN_RANGE (value >> 16, -16, 15));
1669 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1670 ;; and loads to GPR registers on power8.
1671 (define_predicate "fusion_gpr_mem_load"
1672 (match_code "mem,sign_extend,zero_extend")
1674 rtx addr, base, offset;
1676 /* Handle sign/zero extend. */
1677 if (GET_CODE (op) == ZERO_EXTEND
1678 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1681 mode = GET_MODE (op);
1695 if (!TARGET_POWERPC64)
1699 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1705 addr = XEXP (op, 0);
1706 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1709 base = XEXP (addr, 0);
1710 if (!base_reg_operand (base, GET_MODE (base)))
1713 offset = XEXP (addr, 1);
1715 if (GET_CODE (addr) == PLUS)
1716 return satisfies_constraint_I (offset);
1718 else if (GET_CODE (addr) == LO_SUM)
1720 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1721 return small_toc_ref (offset, GET_MODE (offset));
1723 else if (TARGET_ELF && !TARGET_POWERPC64)
1724 return CONSTANT_P (offset);
1730 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1731 ;; memory field with both the addis and the memory offset. Sign extension
1732 ;; is not handled here, since lha and lwa are not fused.
1733 (define_predicate "fusion_addis_mem_combo_load"
1734 (match_code "mem,zero_extend")
1736 rtx addr, base, offset;
1738 /* Handle zero extend. */
1739 if (GET_CODE (op) == ZERO_EXTEND)
1742 mode = GET_MODE (op);
1755 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1756 separate instructions. */
1758 if (!TARGET_POWERPC64)
1762 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1768 addr = XEXP (op, 0);
1769 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1772 base = XEXP (addr, 0);
1773 if (!fusion_gpr_addis (base, GET_MODE (base)))
1776 offset = XEXP (addr, 1);
1777 if (GET_CODE (addr) == PLUS)
1778 return satisfies_constraint_I (offset);
1780 else if (GET_CODE (addr) == LO_SUM)
1782 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1783 return small_toc_ref (offset, GET_MODE (offset));
1785 else if (TARGET_ELF && !TARGET_POWERPC64)
1786 return CONSTANT_P (offset);