gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
 143    BITS_PER_WORD would invoke undefined behavior.  Work around it.  */
 144
 145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
 146   (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
 147
 148 /* Maximum register number, which is the size of the tables below.  */
 149
 150 static unsigned int combine_max_regno;
 151
 152 struct reg_stat {
 153   /* Record last point of death of (hard or pseudo) register n.  */
 154   rtx                           last_death;
 155
 156   /* Record last point of modification of (hard or pseudo) register n.  */
 157   rtx                           last_set;
 158
 159   /* The next group of fields allows the recording of the last value assigned
 160      to (hard or pseudo) register n.  We use this information to see if an
 161      operation being processed is redundant given a prior operation performed
 162      on the register.  For example, an `and' with a constant is redundant if
 163      all the zero bits are already known to be turned off.
 164
 165      We use an approach similar to that used by cse, but change it in the
 166      following ways:
 167
 168      (1) We do not want to reinitialize at each label.
 169      (2) It is useful, but not critical, to know the actual value assigned
 170          to a register.  Often just its form is helpful.
 171
 172      Therefore, we maintain the following fields:
 173
 174      last_set_value             the last value assigned
 175      last_set_label             records the value of label_tick when the
 176                                 register was assigned
 177      last_set_table_tick        records the value of label_tick when a
 178                                 value using the register is assigned
 179      last_set_invalid           set to nonzero when it is not valid
 180                                 to use the value of this register in some
 181                                 register's value
 182
 183      To understand the usage of these tables, it is important to understand
 184      the distinction between the value in last_set_value being valid and
 185      the register being validly contained in some other expression in the
 186      table.
 187
 188      (The next two parameters are out of date).
 189
 190      reg_stat[i].last_set_value is valid if it is nonzero, and either
 191      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 192
 193      Register I may validly appear in any expression returned for the value
 194      of another register if reg_n_sets[i] is 1.  It may also appear in the
 195      value for register J if reg_stat[j].last_set_invalid is zero, or
 196      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 197
 198      If an expression is found in the table containing a register which may
 199      not validly appear in an expression, the register is replaced by
 200      something that won't match, (clobber (const_int 0)).  */
 201
 202   /* Record last value assigned to (hard or pseudo) register n.  */
 203
 204   rtx                           last_set_value;
 205
 206   /* Record the value of label_tick when an expression involving register n
 207      is placed in last_set_value.  */
 208
 209   int                           last_set_table_tick;
 210
 211   /* Record the value of label_tick when the value for register n is placed in
 212      last_set_value.  */
 213
 214   int                           last_set_label;
 215
 216   /* These fields are maintained in parallel with last_set_value and are
 217      used to store the mode in which the register was last set, the bits
 218      that were known to be zero when it was last set, and the number of
 219      sign bits copies it was known to have when it was last set.  */
 220
 221   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 222   char                          last_set_sign_bit_copies;
 223   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 224
 225   /* Set nonzero if references to register n in expressions should not be
 226      used.  last_set_invalid is set nonzero when this register is being
 227      assigned to and last_set_table_tick == label_tick.  */
 228
 229   char                          last_set_invalid;
 230
 231   /* Some registers that are set more than once and used in more than one
 232      basic block are nevertheless always set in similar ways.  For example,
 233      a QImode register may be loaded from memory in two places on a machine
 234      where byte loads zero extend.
 235
 236      We record in the following fields if a register has some leading bits
 237      that are always equal to the sign bit, and what we know about the
 238      nonzero bits of a register, specifically which bits are known to be
 239      zero.
 240
 241      If an entry is zero, it means that we don't know anything special.  */
 242
 243   unsigned char                 sign_bit_copies;
 244
 245   unsigned HOST_WIDE_INT        nonzero_bits;
 246 };
 247
 248 static struct reg_stat *reg_stat;
 249
 250 /* Record the cuid of the last insn that invalidated memory
 251    (anything that writes memory, and subroutine calls, but not pushes).  */
 252
 253 static int mem_last_set;
 254
 255 /* Record the cuid of the last CALL_INSN
 256    so we can tell whether a potential combination crosses any calls.  */
 257
 258 static int last_call_cuid;
 259
 260 /* When `subst' is called, this is the insn that is being modified
 261    (by combining in a previous insn).  The PATTERN of this insn
 262    is still the old pattern partially modified and it should not be
 263    looked at, but this may be used to examine the successors of the insn
 264    to judge whether a simplification is valid.  */
 265
 266 static rtx subst_insn;
 267
 268 /* This is the lowest CUID that `subst' is currently dealing with.
 269    get_last_value will not return a value if the register was set at or
 270    after this CUID.  If not for this mechanism, we could get confused if
 271    I2 or I1 in try_combine were an insn that used the old value of a register
 272    to obtain a new value.  In that case, we might erroneously get the
 273    new value of the register when we wanted the old one.  */
 274
 275 static int subst_low_cuid;
 276
 277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 278    must consider all these registers to be always live.  */
 279
 280 static HARD_REG_SET newpat_used_regs;
 281
 282 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 283    insn is the earlier than I2 or I3, combine should rescan starting at
 284    that location.  */
 285
 286 static rtx added_links_insn;
 287
 288 /* Basic block in which we are performing combines.  */
 289 static basic_block this_basic_block;
 290
 291 /* A bitmap indicating which blocks had registers go dead at entry.
 292    After combine, we'll need to re-do global life analysis with
 293    those blocks as starting points.  */
 294 static sbitmap refresh_blocks;
 295 \f
 296 /* The following array records the insn_rtx_cost for every insn
 297    in the instruction stream.  */
 298
 299 static int *uid_insn_cost;
 300
 301 /* Length of the currently allocated uid_insn_cost array.  */
 302
 303 static int last_insn_cost;
 304
 305 /* Incremented for each label.  */
 306
 307 static int label_tick;
 308
 309 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 310    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 311
 312 static enum machine_mode nonzero_bits_mode;
 313
 314 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 315    be safely used.  It is zero while computing them and after combine has
 316    completed.  This former test prevents propagating values based on
 317    previously set values, which can be incorrect if a variable is modified
 318    in a loop.  */
 319
 320 static int nonzero_sign_valid;
 321
 322 \f
 323 /* Record one modification to rtl structure
 324    to be undone by storing old_contents into *where.
 325    is_int is 1 if the contents are an int.  */
 326
 327 struct undo
 328 {
 329   struct undo *next;
 330   int is_int;
 331   union {rtx r; int i;} old_contents;
 332   union {rtx *r; int *i;} where;
 333 };
 334
 335 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 336    num_undo says how many are currently recorded.
 337
 338    other_insn is nonzero if we have modified some other insn in the process
 339    of working on subst_insn.  It must be verified too.  */
 340
 341 struct undobuf
 342 {
 343   struct undo *undos;
 344   struct undo *frees;
 345   rtx other_insn;
 346 };
 347
 348 static struct undobuf undobuf;
 349
 350 /* Number of times the pseudo being substituted for
 351    was found and replaced.  */
 352
 353 static int n_occurrences;
 354
 355 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 356                                          enum machine_mode,
 357                                          unsigned HOST_WIDE_INT,
 358                                          unsigned HOST_WIDE_INT *);
 359 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 360                                                 enum machine_mode,
 361                                                 unsigned int, unsigned int *);
 362 static void do_SUBST (rtx *, rtx);
 363 static void do_SUBST_INT (int *, int);
 364 static void init_reg_last (void);
 365 static void setup_incoming_promotions (void);
 366 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 367 static int cant_combine_insn_p (rtx);
 368 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 369 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 370 static int contains_muldiv (rtx);
 371 static rtx try_combine (rtx, rtx, rtx, int *);
 372 static void undo_all (void);
 373 static void undo_commit (void);
 374 static rtx *find_split_point (rtx *, rtx);
 375 static rtx subst (rtx, rtx, rtx, int, int);
 376 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 377 static rtx simplify_if_then_else (rtx);
 378 static rtx simplify_set (rtx);
 379 static rtx simplify_logical (rtx);
 380 static rtx expand_compound_operation (rtx);
 381 static rtx expand_field_assignment (rtx);
 382 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 383                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 384 static rtx extract_left_shift (rtx, int);
 385 static rtx make_compound_operation (rtx, enum rtx_code);
 386 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 387                               unsigned HOST_WIDE_INT *);
 388 static rtx canon_reg_for_combine (rtx, rtx);
 389 static rtx force_to_mode (rtx, enum machine_mode,
 390                           unsigned HOST_WIDE_INT, int);
 391 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 392 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 393 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 394 static rtx make_field_assignment (rtx);
 395 static rtx apply_distributive_law (rtx);
 396 static rtx distribute_and_simplify_rtx (rtx, int);
 397 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 398                                      unsigned HOST_WIDE_INT);
 399 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 400                                    unsigned HOST_WIDE_INT);
 401 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 402                             HOST_WIDE_INT, enum machine_mode, int *);
 403 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 404 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 405                                  int);
 406 static int recog_for_combine (rtx *, rtx, rtx *);
 407 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 408 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 409 static void update_table_tick (rtx);
 410 static void record_value_for_reg (rtx, rtx, rtx);
 411 static void check_promoted_subreg (rtx, rtx);
 412 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 413 static void record_dead_and_set_regs (rtx);
 414 static int get_last_value_validate (rtx *, rtx, int, int);
 415 static rtx get_last_value (rtx);
 416 static int use_crosses_set_p (rtx, int);
 417 static void reg_dead_at_p_1 (rtx, rtx, void *);
 418 static int reg_dead_at_p (rtx, rtx);
 419 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 420 static int reg_bitfield_target_p (rtx, rtx);
 421 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 422 static void distribute_links (rtx);
 423 static void mark_used_regs_combine (rtx);
 424 static int insn_cuid (rtx);
 425 static void record_promoted_value (rtx, rtx);
 426 static int unmentioned_reg_p_1 (rtx *, void *);
 427 static bool unmentioned_reg_p (rtx, rtx);
 428 \f
 429
 430 /* It is not safe to use ordinary gen_lowpart in combine.
 431    See comments in gen_lowpart_for_combine.  */
 432 #undef RTL_HOOKS_GEN_LOWPART
 433 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 434
 435 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 436 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 437 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 438
 439 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 440 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 441
 442 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 443 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 444
 445 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 446
 447 \f
 448 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 449    insn.  The substitution can be undone by undo_all.  If INTO is already
 450    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 451    also call SUBST, we have to compute it before we put anything into
 452    the undo table.  */
 453
 454 static void
 455 do_SUBST (rtx *into, rtx newval)
 456 {
 457   struct undo *buf;
 458   rtx oldval = *into;
 459
 460   if (oldval == newval)
 461     return;
 462
 463   /* We'd like to catch as many invalid transformations here as
 464      possible.  Unfortunately, there are way too many mode changes
 465      that are perfectly valid, so we'd waste too much effort for
 466      little gain doing the checks here.  Focus on catching invalid
 467      transformations involving integer constants.  */
 468   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 469       && GET_CODE (newval) == CONST_INT)
 470     {
 471       /* Sanity check that we're replacing oldval with a CONST_INT
 472          that is a valid sign-extension for the original mode.  */
 473       gcc_assert (INTVAL (newval)
 474                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 475
 476       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 477          CONST_INT is not valid, because after the replacement, the
 478          original mode would be gone.  Unfortunately, we can't tell
 479          when do_SUBST is called to replace the operand thereof, so we
 480          perform this test on oldval instead, checking whether an
 481          invalid replacement took place before we got here.  */
 482       gcc_assert (!(GET_CODE (oldval) == SUBREG
 483                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 484       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 485                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 486     }
 487
 488   if (undobuf.frees)
 489     buf = undobuf.frees, undobuf.frees = buf->next;
 490   else
 491     buf = xmalloc (sizeof (struct undo));
 492
 493   buf->is_int = 0;
 494   buf->where.r = into;
 495   buf->old_contents.r = oldval;
 496   *into = newval;
 497
 498   buf->next = undobuf.undos, undobuf.undos = buf;
 499 }
 500
 501 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 502
 503 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 504    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 505    not safe.  */
 506
 507 static void
 508 do_SUBST_INT (int *into, int newval)
 509 {
 510   struct undo *buf;
 511   int oldval = *into;
 512
 513   if (oldval == newval)
 514     return;
 515
 516   if (undobuf.frees)
 517     buf = undobuf.frees, undobuf.frees = buf->next;
 518   else
 519     buf = xmalloc (sizeof (struct undo));
 520
 521   buf->is_int = 1;
 522   buf->where.i = into;
 523   buf->old_contents.i = oldval;
 524   *into = newval;
 525
 526   buf->next = undobuf.undos, undobuf.undos = buf;
 527 }
 528
 529 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 530 \f
 531 /* Subroutine of try_combine.  Determine whether the combine replacement
 532    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 533    that the original instruction sequence I1, I2 and I3.  Note that I1
 534    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 535    costs of all instructions can be estimated, and the replacements are
 536    more expensive than the original sequence.  */
 537
 538 static bool
 539 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 540 {
 541   int i1_cost, i2_cost, i3_cost;
 542   int new_i2_cost, new_i3_cost;
 543   int old_cost, new_cost;
 544
 545   /* Lookup the original insn_rtx_costs.  */
 546   i2_cost = INSN_UID (i2) <= last_insn_cost
 547             ? uid_insn_cost[INSN_UID (i2)] : 0;
 548   i3_cost = INSN_UID (i3) <= last_insn_cost
 549             ? uid_insn_cost[INSN_UID (i3)] : 0;
 550
 551   if (i1)
 552     {
 553       i1_cost = INSN_UID (i1) <= last_insn_cost
 554                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 555       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 556                  ? i1_cost + i2_cost + i3_cost : 0;
 557     }
 558   else
 559     {
 560       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 561       i1_cost = 0;
 562     }
 563
 564   /* Calculate the replacement insn_rtx_costs.  */
 565   new_i3_cost = insn_rtx_cost (newpat);
 566   if (newi2pat)
 567     {
 568       new_i2_cost = insn_rtx_cost (newi2pat);
 569       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 570                  ? new_i2_cost + new_i3_cost : 0;
 571     }
 572   else
 573     {
 574       new_cost = new_i3_cost;
 575       new_i2_cost = 0;
 576     }
 577
 578   if (undobuf.other_insn)
 579     {
 580       int old_other_cost, new_other_cost;
 581
 582       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 583                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 584       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 585       if (old_other_cost > 0 && new_other_cost > 0)
 586         {
 587           old_cost += old_other_cost;
 588           new_cost += new_other_cost;
 589         }
 590       else
 591         old_cost = 0;
 592     }
 593
 594   /* Disallow this recombination if both new_cost and old_cost are
 595      greater than zero, and new_cost is greater than old cost.  */
 596   if (old_cost > 0
 597       && new_cost > old_cost)
 598     {
 599       if (dump_file)
 600         {
 601           if (i1)
 602             {
 603               fprintf (dump_file,
 604                        "rejecting combination of insns %d, %d and %d\n",
 605                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 606               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 607                        i1_cost, i2_cost, i3_cost, old_cost);
 608             }
 609           else
 610             {
 611               fprintf (dump_file,
 612                        "rejecting combination of insns %d and %d\n",
 613                        INSN_UID (i2), INSN_UID (i3));
 614               fprintf (dump_file, "original costs %d + %d = %d\n",
 615                        i2_cost, i3_cost, old_cost);
 616             }
 617
 618           if (newi2pat)
 619             {
 620               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 621                        new_i2_cost, new_i3_cost, new_cost);
 622             }
 623           else
 624             fprintf (dump_file, "replacement cost %d\n", new_cost);
 625         }
 626
 627       return false;
 628     }
 629
 630   /* Update the uid_insn_cost array with the replacement costs.  */
 631   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 632   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 633   if (i1)
 634     uid_insn_cost[INSN_UID (i1)] = 0;
 635
 636   return true;
 637 }
 638 \f
 639 /* Main entry point for combiner.  F is the first insn of the function.
 640    NREGS is the first unused pseudo-reg number.
 641
 642    Return nonzero if the combiner has turned an indirect jump
 643    instruction into a direct jump.  */
 644 int
 645 combine_instructions (rtx f, unsigned int nregs)
 646 {
 647   rtx insn, next;
 648 #ifdef HAVE_cc0
 649   rtx prev;
 650 #endif
 651   int i;
 652   unsigned int j = 0;
 653   rtx links, nextlinks;
 654   sbitmap_iterator sbi;
 655
 656   int new_direct_jump_p = 0;
 657
 658   combine_attempts = 0;
 659   combine_merges = 0;
 660   combine_extras = 0;
 661   combine_successes = 0;
 662
 663   combine_max_regno = nregs;
 664
 665   rtl_hooks = combine_rtl_hooks;
 666
 667   reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
 668
 669   init_recog_no_volatile ();
 670
 671   /* Compute maximum uid value so uid_cuid can be allocated.  */
 672
 673   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 674     if (INSN_UID (insn) > i)
 675       i = INSN_UID (insn);
 676
 677   uid_cuid = xmalloc ((i + 1) * sizeof (int));
 678   max_uid_cuid = i;
 679
 680   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 681
 682   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 683      problems when, for example, we have j <<= 1 in a loop.  */
 684
 685   nonzero_sign_valid = 0;
 686
 687   /* Compute the mapping from uids to cuids.
 688      Cuids are numbers assigned to insns, like uids,
 689      except that cuids increase monotonically through the code.
 690
 691      Scan all SETs and see if we can deduce anything about what
 692      bits are known to be zero for some registers and how many copies
 693      of the sign bit are known to exist for those registers.
 694
 695      Also set any known values so that we can use it while searching
 696      for what bits are known to be set.  */
 697
 698   label_tick = 1;
 699
 700   setup_incoming_promotions ();
 701
 702   refresh_blocks = sbitmap_alloc (last_basic_block);
 703   sbitmap_zero (refresh_blocks);
 704
 705   /* Allocate array of current insn_rtx_costs.  */
 706   uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
 707   last_insn_cost = max_uid_cuid;
 708
 709   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 710     {
 711       uid_cuid[INSN_UID (insn)] = ++i;
 712       subst_low_cuid = i;
 713       subst_insn = insn;
 714
 715       if (INSN_P (insn))
 716         {
 717           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 718                        NULL);
 719           record_dead_and_set_regs (insn);
 720
 721 #ifdef AUTO_INC_DEC
 722           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 723             if (REG_NOTE_KIND (links) == REG_INC)
 724               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 725                                                 NULL);
 726 #endif
 727
 728           /* Record the current insn_rtx_cost of this instruction.  */
 729           if (NONJUMP_INSN_P (insn))
 730             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 731           if (dump_file)
 732             fprintf(dump_file, "insn_cost %d: %d\n",
 733                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 734         }
 735
 736       if (LABEL_P (insn))
 737         label_tick++;
 738     }
 739
 740   nonzero_sign_valid = 1;
 741
 742   /* Now scan all the insns in forward order.  */
 743
 744   label_tick = 1;
 745   last_call_cuid = 0;
 746   mem_last_set = 0;
 747   init_reg_last ();
 748   setup_incoming_promotions ();
 749
 750   FOR_EACH_BB (this_basic_block)
 751     {
 752       for (insn = BB_HEAD (this_basic_block);
 753            insn != NEXT_INSN (BB_END (this_basic_block));
 754            insn = next ? next : NEXT_INSN (insn))
 755         {
 756           next = 0;
 757
 758           if (LABEL_P (insn))
 759             label_tick++;
 760
 761           else if (INSN_P (insn))
 762             {
 763               /* See if we know about function return values before this
 764                  insn based upon SUBREG flags.  */
 765               check_promoted_subreg (insn, PATTERN (insn));
 766
 767               /* Try this insn with each insn it links back to.  */
 768
 769               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 770                 if ((next = try_combine (insn, XEXP (links, 0),
 771                                          NULL_RTX, &new_direct_jump_p)) != 0)
 772                   goto retry;
 773
 774               /* Try each sequence of three linked insns ending with this one.  */
 775
 776               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 777                 {
 778                   rtx link = XEXP (links, 0);
 779
 780                   /* If the linked insn has been replaced by a note, then there
 781                      is no point in pursuing this chain any further.  */
 782                   if (NOTE_P (link))
 783                     continue;
 784
 785                   for (nextlinks = LOG_LINKS (link);
 786                        nextlinks;
 787                        nextlinks = XEXP (nextlinks, 1))
 788                     if ((next = try_combine (insn, link,
 789                                              XEXP (nextlinks, 0),
 790                                              &new_direct_jump_p)) != 0)
 791                       goto retry;
 792                 }
 793
 794 #ifdef HAVE_cc0
 795               /* Try to combine a jump insn that uses CC0
 796                  with a preceding insn that sets CC0, and maybe with its
 797                  logical predecessor as well.
 798                  This is how we make decrement-and-branch insns.
 799                  We need this special code because data flow connections
 800                  via CC0 do not get entered in LOG_LINKS.  */
 801
 802               if (JUMP_P (insn)
 803                   && (prev = prev_nonnote_insn (insn)) != 0
 804                   && NONJUMP_INSN_P (prev)
 805                   && sets_cc0_p (PATTERN (prev)))
 806                 {
 807                   if ((next = try_combine (insn, prev,
 808                                            NULL_RTX, &new_direct_jump_p)) != 0)
 809                     goto retry;
 810
 811                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 812                        nextlinks = XEXP (nextlinks, 1))
 813                     if ((next = try_combine (insn, prev,
 814                                              XEXP (nextlinks, 0),
 815                                              &new_direct_jump_p)) != 0)
 816                       goto retry;
 817                 }
 818
 819               /* Do the same for an insn that explicitly references CC0.  */
 820               if (NONJUMP_INSN_P (insn)
 821                   && (prev = prev_nonnote_insn (insn)) != 0
 822                   && NONJUMP_INSN_P (prev)
 823                   && sets_cc0_p (PATTERN (prev))
 824                   && GET_CODE (PATTERN (insn)) == SET
 825                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 826                 {
 827                   if ((next = try_combine (insn, prev,
 828                                            NULL_RTX, &new_direct_jump_p)) != 0)
 829                     goto retry;
 830
 831                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 832                        nextlinks = XEXP (nextlinks, 1))
 833                     if ((next = try_combine (insn, prev,
 834                                              XEXP (nextlinks, 0),
 835                                              &new_direct_jump_p)) != 0)
 836                       goto retry;
 837                 }
 838
 839               /* Finally, see if any of the insns that this insn links to
 840                  explicitly references CC0.  If so, try this insn, that insn,
 841                  and its predecessor if it sets CC0.  */
 842               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 843                 if (NONJUMP_INSN_P (XEXP (links, 0))
 844                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 845                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 846                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 847                     && NONJUMP_INSN_P (prev)
 848                     && sets_cc0_p (PATTERN (prev))
 849                     && (next = try_combine (insn, XEXP (links, 0),
 850                                             prev, &new_direct_jump_p)) != 0)
 851                   goto retry;
 852 #endif
 853
 854               /* Try combining an insn with two different insns whose results it
 855                  uses.  */
 856               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 857                 for (nextlinks = XEXP (links, 1); nextlinks;
 858                      nextlinks = XEXP (nextlinks, 1))
 859                   if ((next = try_combine (insn, XEXP (links, 0),
 860                                            XEXP (nextlinks, 0),
 861                                            &new_direct_jump_p)) != 0)
 862                     goto retry;
 863
 864               /* Try this insn with each REG_EQUAL note it links back to.  */
 865               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 866                 {
 867                   rtx set, note;
 868                   rtx temp = XEXP (links, 0);
 869                   if ((set = single_set (temp)) != 0
 870                       && (note = find_reg_equal_equiv_note (temp)) != 0
 871                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 872                       /* Avoid using a register that may already been marked
 873                          dead by an earlier instruction.  */
 874                       && ! unmentioned_reg_p (note, SET_SRC (set))
 875                       && (GET_MODE (note) == VOIDmode
 876                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 877                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 878                     {
 879                       /* Temporarily replace the set's source with the
 880                          contents of the REG_EQUAL note.  The insn will
 881                          be deleted or recognized by try_combine.  */
 882                       rtx orig = SET_SRC (set);
 883                       SET_SRC (set) = note;
 884                       next = try_combine (insn, temp, NULL_RTX,
 885                                           &new_direct_jump_p);
 886                       if (next)
 887                         goto retry;
 888                       SET_SRC (set) = orig;
 889                     }
 890                 }
 891
 892               if (!NOTE_P (insn))
 893                 record_dead_and_set_regs (insn);
 894
 895             retry:
 896               ;
 897             }
 898         }
 899     }
 900   clear_bb_flags ();
 901
 902   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 903     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 904   new_direct_jump_p |= purge_all_dead_edges ();
 905   delete_noop_moves ();
 906
 907   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 908                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 909                                     | PROP_KILL_DEAD_CODE);
 910
 911   /* Clean up.  */
 912   sbitmap_free (refresh_blocks);
 913   free (uid_insn_cost);
 914   free (reg_stat);
 915   free (uid_cuid);
 916
 917   {
 918     struct undo *undo, *next;
 919     for (undo = undobuf.frees; undo; undo = next)
 920       {
 921         next = undo->next;
 922         free (undo);
 923       }
 924     undobuf.frees = 0;
 925   }
 926
 927   total_attempts += combine_attempts;
 928   total_merges += combine_merges;
 929   total_extras += combine_extras;
 930   total_successes += combine_successes;
 931
 932   nonzero_sign_valid = 0;
 933   rtl_hooks = general_rtl_hooks;
 934
 935   /* Make recognizer allow volatile MEMs again.  */
 936   init_recog ();
 937
 938   return new_direct_jump_p;
 939 }
 940
 941 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 942
 943 static void
 944 init_reg_last (void)
 945 {
 946   unsigned int i;
 947   for (i = 0; i < combine_max_regno; i++)
 948     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 949 }
 950 \f
 951 /* Set up any promoted values for incoming argument registers.  */
 952
 953 static void
 954 setup_incoming_promotions (void)
 955 {
 956   unsigned int regno;
 957   rtx reg;
 958   enum machine_mode mode;
 959   int unsignedp;
 960   rtx first = get_insns ();
 961
 962   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
 963     {
 964       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 965         /* Check whether this register can hold an incoming pointer
 966            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
 967            numbers, so translate if necessary due to register windows.  */
 968         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
 969             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 970           {
 971             record_value_for_reg
 972               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
 973                                            : SIGN_EXTEND),
 974                                           GET_MODE (reg),
 975                                           gen_rtx_CLOBBER (mode, const0_rtx)));
 976           }
 977     }
 978 }
 979 \f
 980 /* Called via note_stores.  If X is a pseudo that is narrower than
 981    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 982
 983    If we are setting only a portion of X and we can't figure out what
 984    portion, assume all bits will be used since we don't know what will
 985    be happening.
 986
 987    Similarly, set how many bits of X are known to be copies of the sign bit
 988    at all locations in the function.  This is the smallest number implied
 989    by any set of X.  */
 990
 991 static void
 992 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
 993                                   void *data ATTRIBUTE_UNUSED)
 994 {
 995   unsigned int num;
 996
 997   if (REG_P (x)
 998       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 999       /* If this register is undefined at the start of the file, we can't
1000          say what its contents were.  */
1001       && ! REGNO_REG_SET_P
1002          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1003       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1004     {
1005       if (set == 0 || GET_CODE (set) == CLOBBER)
1006         {
1007           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1008           reg_stat[REGNO (x)].sign_bit_copies = 1;
1009           return;
1010         }
1011
1012       /* If this is a complex assignment, see if we can convert it into a
1013          simple assignment.  */
1014       set = expand_field_assignment (set);
1015
1016       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1017          set what we know about X.  */
1018
1019       if (SET_DEST (set) == x
1020           || (GET_CODE (SET_DEST (set)) == SUBREG
1021               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1022                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1023               && SUBREG_REG (SET_DEST (set)) == x))
1024         {
1025           rtx src = SET_SRC (set);
1026
1027 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1028           /* If X is narrower than a word and SRC is a non-negative
1029              constant that would appear negative in the mode of X,
1030              sign-extend it for use in reg_stat[].nonzero_bits because some
1031              machines (maybe most) will actually do the sign-extension
1032              and this is the conservative approach.
1033
1034              ??? For 2.5, try to tighten up the MD files in this regard
1035              instead of this kludge.  */
1036
1037           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1038               && GET_CODE (src) == CONST_INT
1039               && INTVAL (src) > 0
1040               && 0 != (INTVAL (src)
1041                        & ((HOST_WIDE_INT) 1
1042                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1043             src = GEN_INT (INTVAL (src)
1044                            | ((HOST_WIDE_INT) (-1)
1045                               << GET_MODE_BITSIZE (GET_MODE (x))));
1046 #endif
1047
1048           /* Don't call nonzero_bits if it cannot change anything.  */
1049           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1050             reg_stat[REGNO (x)].nonzero_bits
1051               |= nonzero_bits (src, nonzero_bits_mode);
1052           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1053           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1054               || reg_stat[REGNO (x)].sign_bit_copies > num)
1055             reg_stat[REGNO (x)].sign_bit_copies = num;
1056         }
1057       else
1058         {
1059           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1060           reg_stat[REGNO (x)].sign_bit_copies = 1;
1061         }
1062     }
1063 }
1064 \f
1065 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1066    insns that were previously combined into I3 or that will be combined
1067    into the merger of INSN and I3.
1068
1069    Return 0 if the combination is not allowed for any reason.
1070
1071    If the combination is allowed, *PDEST will be set to the single
1072    destination of INSN and *PSRC to the single source, and this function
1073    will return 1.  */
1074
1075 static int
1076 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1077                rtx *pdest, rtx *psrc)
1078 {
1079   int i;
1080   rtx set = 0, src, dest;
1081   rtx p;
1082 #ifdef AUTO_INC_DEC
1083   rtx link;
1084 #endif
1085   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1086                               && next_active_insn (succ) == i3)
1087                       : next_active_insn (insn) == i3);
1088
1089   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1090      or a PARALLEL consisting of such a SET and CLOBBERs.
1091
1092      If INSN has CLOBBER parallel parts, ignore them for our processing.
1093      By definition, these happen during the execution of the insn.  When it
1094      is merged with another insn, all bets are off.  If they are, in fact,
1095      needed and aren't also supplied in I3, they may be added by
1096      recog_for_combine.  Otherwise, it won't match.
1097
1098      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1099      note.
1100
1101      Get the source and destination of INSN.  If more than one, can't
1102      combine.  */
1103
1104   if (GET_CODE (PATTERN (insn)) == SET)
1105     set = PATTERN (insn);
1106   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1107            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1108     {
1109       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1110         {
1111           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1112           rtx note;
1113
1114           switch (GET_CODE (elt))
1115             {
1116             /* This is important to combine floating point insns
1117                for the SH4 port.  */
1118             case USE:
1119               /* Combining an isolated USE doesn't make sense.
1120                  We depend here on combinable_i3pat to reject them.  */
1121               /* The code below this loop only verifies that the inputs of
1122                  the SET in INSN do not change.  We call reg_set_between_p
1123                  to verify that the REG in the USE does not change between
1124                  I3 and INSN.
1125                  If the USE in INSN was for a pseudo register, the matching
1126                  insn pattern will likely match any register; combining this
1127                  with any other USE would only be safe if we knew that the
1128                  used registers have identical values, or if there was
1129                  something to tell them apart, e.g. different modes.  For
1130                  now, we forgo such complicated tests and simply disallow
1131                  combining of USES of pseudo registers with any other USE.  */
1132               if (REG_P (XEXP (elt, 0))
1133                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1134                 {
1135                   rtx i3pat = PATTERN (i3);
1136                   int i = XVECLEN (i3pat, 0) - 1;
1137                   unsigned int regno = REGNO (XEXP (elt, 0));
1138
1139                   do
1140                     {
1141                       rtx i3elt = XVECEXP (i3pat, 0, i);
1142
1143                       if (GET_CODE (i3elt) == USE
1144                           && REG_P (XEXP (i3elt, 0))
1145                           && (REGNO (XEXP (i3elt, 0)) == regno
1146                               ? reg_set_between_p (XEXP (elt, 0),
1147                                                    PREV_INSN (insn), i3)
1148                               : regno >= FIRST_PSEUDO_REGISTER))
1149                         return 0;
1150                     }
1151                   while (--i >= 0);
1152                 }
1153               break;
1154
1155               /* We can ignore CLOBBERs.  */
1156             case CLOBBER:
1157               break;
1158
1159             case SET:
1160               /* Ignore SETs whose result isn't used but not those that
1161                  have side-effects.  */
1162               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1163                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1164                       || INTVAL (XEXP (note, 0)) <= 0)
1165                   && ! side_effects_p (elt))
1166                 break;
1167
1168               /* If we have already found a SET, this is a second one and
1169                  so we cannot combine with this insn.  */
1170               if (set)
1171                 return 0;
1172
1173               set = elt;
1174               break;
1175
1176             default:
1177               /* Anything else means we can't combine.  */
1178               return 0;
1179             }
1180         }
1181
1182       if (set == 0
1183           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1184              so don't do anything with it.  */
1185           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1186         return 0;
1187     }
1188   else
1189     return 0;
1190
1191   if (set == 0)
1192     return 0;
1193
1194   set = expand_field_assignment (set);
1195   src = SET_SRC (set), dest = SET_DEST (set);
1196
1197   /* Don't eliminate a store in the stack pointer.  */
1198   if (dest == stack_pointer_rtx
1199       /* Don't combine with an insn that sets a register to itself if it has
1200          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1201       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1202       /* Can't merge an ASM_OPERANDS.  */
1203       || GET_CODE (src) == ASM_OPERANDS
1204       /* Can't merge a function call.  */
1205       || GET_CODE (src) == CALL
1206       /* Don't eliminate a function call argument.  */
1207       || (CALL_P (i3)
1208           && (find_reg_fusage (i3, USE, dest)
1209               || (REG_P (dest)
1210                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1211                   && global_regs[REGNO (dest)])))
1212       /* Don't substitute into an incremented register.  */
1213       || FIND_REG_INC_NOTE (i3, dest)
1214       || (succ && FIND_REG_INC_NOTE (succ, dest))
1215       /* Don't substitute into a non-local goto, this confuses CFG.  */
1216       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1217 #if 0
1218       /* Don't combine the end of a libcall into anything.  */
1219       /* ??? This gives worse code, and appears to be unnecessary, since no
1220          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1221          use REG_RETVAL notes for noconflict blocks, but other code here
1222          makes sure that those insns don't disappear.  */
1223       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1224 #endif
1225       /* Make sure that DEST is not used after SUCC but before I3.  */
1226       || (succ && ! all_adjacent
1227           && reg_used_between_p (dest, succ, i3))
1228       /* Make sure that the value that is to be substituted for the register
1229          does not use any registers whose values alter in between.  However,
1230          If the insns are adjacent, a use can't cross a set even though we
1231          think it might (this can happen for a sequence of insns each setting
1232          the same destination; last_set of that register might point to
1233          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1234          equivalent to the memory so the substitution is valid even if there
1235          are intervening stores.  Also, don't move a volatile asm or
1236          UNSPEC_VOLATILE across any other insns.  */
1237       || (! all_adjacent
1238           && (((!MEM_P (src)
1239                 || ! find_reg_note (insn, REG_EQUIV, src))
1240                && use_crosses_set_p (src, INSN_CUID (insn)))
1241               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1242               || GET_CODE (src) == UNSPEC_VOLATILE))
1243       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1244          better register allocation by not doing the combine.  */
1245       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1246       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1247       /* Don't combine across a CALL_INSN, because that would possibly
1248          change whether the life span of some REGs crosses calls or not,
1249          and it is a pain to update that information.
1250          Exception: if source is a constant, moving it later can't hurt.
1251          Accept that special case, because it helps -fforce-addr a lot.  */
1252       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1253     return 0;
1254
1255   /* DEST must either be a REG or CC0.  */
1256   if (REG_P (dest))
1257     {
1258       /* If register alignment is being enforced for multi-word items in all
1259          cases except for parameters, it is possible to have a register copy
1260          insn referencing a hard register that is not allowed to contain the
1261          mode being copied and which would not be valid as an operand of most
1262          insns.  Eliminate this problem by not combining with such an insn.
1263
1264          Also, on some machines we don't want to extend the life of a hard
1265          register.  */
1266
1267       if (REG_P (src)
1268           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1269                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1270               /* Don't extend the life of a hard register unless it is
1271                  user variable (if we have few registers) or it can't
1272                  fit into the desired register (meaning something special
1273                  is going on).
1274                  Also avoid substituting a return register into I3, because
1275                  reload can't handle a conflict with constraints of other
1276                  inputs.  */
1277               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1278                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1279         return 0;
1280     }
1281   else if (GET_CODE (dest) != CC0)
1282     return 0;
1283
1284
1285   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1286     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1287       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1288         {
1289           /* Don't substitute for a register intended as a clobberable
1290              operand.  */
1291           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1292           if (rtx_equal_p (reg, dest))
1293             return 0;
1294
1295           /* If the clobber represents an earlyclobber operand, we must not
1296              substitute an expression containing the clobbered register.
1297              As we do not analyze the constraint strings here, we have to
1298              make the conservative assumption.  However, if the register is
1299              a fixed hard reg, the clobber cannot represent any operand;
1300              we leave it up to the machine description to either accept or
1301              reject use-and-clobber patterns.  */
1302           if (!REG_P (reg)
1303               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1304               || !fixed_regs[REGNO (reg)])
1305             if (reg_overlap_mentioned_p (reg, src))
1306               return 0;
1307         }
1308
1309   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1310      or not), reject, unless nothing volatile comes between it and I3 */
1311
1312   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1313     {
1314       /* Make sure succ doesn't contain a volatile reference.  */
1315       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1316         return 0;
1317
1318       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1319         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1320           return 0;
1321     }
1322
1323   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1324      to be an explicit register variable, and was chosen for a reason.  */
1325
1326   if (GET_CODE (src) == ASM_OPERANDS
1327       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1328     return 0;
1329
1330   /* If there are any volatile insns between INSN and I3, reject, because
1331      they might affect machine state.  */
1332
1333   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1334     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1335       return 0;
1336
1337   /* If INSN contains an autoincrement or autodecrement, make sure that
1338      register is not used between there and I3, and not already used in
1339      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1340      Also insist that I3 not be a jump; if it were one
1341      and the incremented register were spilled, we would lose.  */
1342
1343 #ifdef AUTO_INC_DEC
1344   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1345     if (REG_NOTE_KIND (link) == REG_INC
1346         && (JUMP_P (i3)
1347             || reg_used_between_p (XEXP (link, 0), insn, i3)
1348             || (pred != NULL_RTX
1349                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1350             || (succ != NULL_RTX
1351                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1352             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1353       return 0;
1354 #endif
1355
1356 #ifdef HAVE_cc0
1357   /* Don't combine an insn that follows a CC0-setting insn.
1358      An insn that uses CC0 must not be separated from the one that sets it.
1359      We do, however, allow I2 to follow a CC0-setting insn if that insn
1360      is passed as I1; in that case it will be deleted also.
1361      We also allow combining in this case if all the insns are adjacent
1362      because that would leave the two CC0 insns adjacent as well.
1363      It would be more logical to test whether CC0 occurs inside I1 or I2,
1364      but that would be much slower, and this ought to be equivalent.  */
1365
1366   p = prev_nonnote_insn (insn);
1367   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1368       && ! all_adjacent)
1369     return 0;
1370 #endif
1371
1372   /* If we get here, we have passed all the tests and the combination is
1373      to be allowed.  */
1374
1375   *pdest = dest;
1376   *psrc = src;
1377
1378   return 1;
1379 }
1380 \f
1381 /* LOC is the location within I3 that contains its pattern or the component
1382    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1383
1384    One problem is if I3 modifies its output, as opposed to replacing it
1385    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1386    so would produce an insn that is not equivalent to the original insns.
1387
1388    Consider:
1389
1390          (set (reg:DI 101) (reg:DI 100))
1391          (set (subreg:SI (reg:DI 101) 0) <foo>)
1392
1393    This is NOT equivalent to:
1394
1395          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1396                     (set (reg:DI 101) (reg:DI 100))])
1397
1398    Not only does this modify 100 (in which case it might still be valid
1399    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1400
1401    We can also run into a problem if I2 sets a register that I1
1402    uses and I1 gets directly substituted into I3 (not via I2).  In that
1403    case, we would be getting the wrong value of I2DEST into I3, so we
1404    must reject the combination.  This case occurs when I2 and I1 both
1405    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1406    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1407    of a SET must prevent combination from occurring.
1408
1409    Before doing the above check, we first try to expand a field assignment
1410    into a set of logical operations.
1411
1412    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1413    we place a register that is both set and used within I3.  If more than one
1414    such register is detected, we fail.
1415
1416    Return 1 if the combination is valid, zero otherwise.  */
1417
1418 static int
1419 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1420                   int i1_not_in_src, rtx *pi3dest_killed)
1421 {
1422   rtx x = *loc;
1423
1424   if (GET_CODE (x) == SET)
1425     {
1426       rtx set = x ;
1427       rtx dest = SET_DEST (set);
1428       rtx src = SET_SRC (set);
1429       rtx inner_dest = dest;
1430       rtx subdest;
1431
1432       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1433              || GET_CODE (inner_dest) == SUBREG
1434              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1435         inner_dest = XEXP (inner_dest, 0);
1436
1437       /* Check for the case where I3 modifies its output, as discussed
1438          above.  We don't want to prevent pseudos from being combined
1439          into the address of a MEM, so only prevent the combination if
1440          i1 or i2 set the same MEM.  */
1441       if ((inner_dest != dest &&
1442            (!MEM_P (inner_dest)
1443             || rtx_equal_p (i2dest, inner_dest)
1444             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1445            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1446                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1447
1448           /* This is the same test done in can_combine_p except we can't test
1449              all_adjacent; we don't have to, since this instruction will stay
1450              in place, thus we are not considering increasing the lifetime of
1451              INNER_DEST.
1452
1453              Also, if this insn sets a function argument, combining it with
1454              something that might need a spill could clobber a previous
1455              function argument; the all_adjacent test in can_combine_p also
1456              checks this; here, we do a more specific test for this case.  */
1457
1458           || (REG_P (inner_dest)
1459               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1460               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1461                                         GET_MODE (inner_dest))))
1462           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1463         return 0;
1464
1465       /* If DEST is used in I3, it is being killed in this insn, so
1466          record that for later.  We have to consider paradoxical
1467          subregs here, since they kill the whole register, but we
1468          ignore partial subregs, STRICT_LOW_PART, etc.
1469          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1470          STACK_POINTER_REGNUM, since these are always considered to be
1471          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1472       subdest = dest;
1473       if (GET_CODE (subdest) == SUBREG
1474           && (GET_MODE_SIZE (GET_MODE (subdest))
1475               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1476         subdest = SUBREG_REG (subdest);
1477       if (pi3dest_killed
1478           && REG_P (subdest)
1479           && reg_referenced_p (subdest, PATTERN (i3))
1480           && REGNO (subdest) != FRAME_POINTER_REGNUM
1481 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1482           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1483 #endif
1484 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1485           && (REGNO (subdest) != ARG_POINTER_REGNUM
1486               || ! fixed_regs [REGNO (subdest)])
1487 #endif
1488           && REGNO (subdest) != STACK_POINTER_REGNUM)
1489         {
1490           if (*pi3dest_killed)
1491             return 0;
1492
1493           *pi3dest_killed = subdest;
1494         }
1495     }
1496
1497   else if (GET_CODE (x) == PARALLEL)
1498     {
1499       int i;
1500
1501       for (i = 0; i < XVECLEN (x, 0); i++)
1502         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1503                                 i1_not_in_src, pi3dest_killed))
1504           return 0;
1505     }
1506
1507   return 1;
1508 }
1509 \f
1510 /* Return 1 if X is an arithmetic expression that contains a multiplication
1511    and division.  We don't count multiplications by powers of two here.  */
1512
1513 static int
1514 contains_muldiv (rtx x)
1515 {
1516   switch (GET_CODE (x))
1517     {
1518     case MOD:  case DIV:  case UMOD:  case UDIV:
1519       return 1;
1520
1521     case MULT:
1522       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1523                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1524     default:
1525       if (BINARY_P (x))
1526         return contains_muldiv (XEXP (x, 0))
1527             || contains_muldiv (XEXP (x, 1));
1528
1529       if (UNARY_P (x))
1530         return contains_muldiv (XEXP (x, 0));
1531
1532       return 0;
1533     }
1534 }
1535 \f
1536 /* Determine whether INSN can be used in a combination.  Return nonzero if
1537    not.  This is used in try_combine to detect early some cases where we
1538    can't perform combinations.  */
1539
1540 static int
1541 cant_combine_insn_p (rtx insn)
1542 {
1543   rtx set;
1544   rtx src, dest;
1545
1546   /* If this isn't really an insn, we can't do anything.
1547      This can occur when flow deletes an insn that it has merged into an
1548      auto-increment address.  */
1549   if (! INSN_P (insn))
1550     return 1;
1551
1552   /* Never combine loads and stores involving hard regs that are likely
1553      to be spilled.  The register allocator can usually handle such
1554      reg-reg moves by tying.  If we allow the combiner to make
1555      substitutions of likely-spilled regs, reload might die.
1556      As an exception, we allow combinations involving fixed regs; these are
1557      not available to the register allocator so there's no risk involved.  */
1558
1559   set = single_set (insn);
1560   if (! set)
1561     return 0;
1562   src = SET_SRC (set);
1563   dest = SET_DEST (set);
1564   if (GET_CODE (src) == SUBREG)
1565     src = SUBREG_REG (src);
1566   if (GET_CODE (dest) == SUBREG)
1567     dest = SUBREG_REG (dest);
1568   if (REG_P (src) && REG_P (dest)
1569       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1570            && ! fixed_regs[REGNO (src)]
1571            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1572           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1573               && ! fixed_regs[REGNO (dest)]
1574               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1575     return 1;
1576
1577   return 0;
1578 }
1579
1580 struct likely_spilled_retval_info
1581 {
1582   unsigned regno, nregs;
1583   unsigned mask;
1584 };
1585
1586 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1587    hard registers that are known to be written to / clobbered in full.  */
1588 static void
1589 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1590 {
1591   struct likely_spilled_retval_info *info = data;
1592   unsigned regno, nregs;
1593   unsigned new_mask;
1594
1595   if (!REG_P (XEXP (set, 0)))
1596     return;
1597   regno = REGNO (x);
1598   if (regno >= info->regno + info->nregs)
1599     return;
1600   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1601   if (regno + nregs <= info->regno)
1602     return;
1603   new_mask = (2U << (nregs - 1)) - 1;
1604   if (regno < info->regno)
1605     new_mask >>= info->regno - regno;
1606   else
1607     new_mask <<= regno - info->regno;
1608   info->mask &= new_mask;
1609 }
1610
1611 /* Return nonzero iff part of the return value is live during INSN, and
1612    it is likely spilled.  This can happen when more than one insn is needed
1613    to copy the return value, e.g. when we consider to combine into the
1614    second copy insn for a complex value.  */
1615
1616 static int
1617 likely_spilled_retval_p (rtx insn)
1618 {
1619   rtx use = BB_END (this_basic_block);
1620   rtx reg, p;
1621   unsigned regno, nregs;
1622   /* We assume here that no machine mode needs more than
1623      32 hard registers when the value overlaps with a register
1624      for which FUNCTION_VALUE_REGNO_P is true.  */
1625   unsigned mask;
1626   struct likely_spilled_retval_info info;
1627
1628   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1629     return 0;
1630   reg = XEXP (PATTERN (use), 0);
1631   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1632     return 0;
1633   regno = REGNO (reg);
1634   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1635   if (nregs == 1)
1636     return 0;
1637   mask = (2U << (nregs - 1)) - 1;
1638
1639   /* Disregard parts of the return value that are set later.  */
1640   info.regno = regno;
1641   info.nregs = nregs;
1642   info.mask = mask;
1643   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1644     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1645   mask = info.mask;
1646
1647   /* Check if any of the (probably) live return value registers is
1648      likely spilled.  */
1649   nregs --;
1650   do
1651     {
1652       if ((mask & 1 << nregs)
1653           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1654         return 1;
1655     } while (nregs--);
1656   return 0;
1657 }
1658
1659 /* Adjust INSN after we made a change to its destination.
1660
1661    Changing the destination can invalidate notes that say something about
1662    the results of the insn and a LOG_LINK pointing to the insn.  */
1663
1664 static void
1665 adjust_for_new_dest (rtx insn)
1666 {
1667   rtx *loc;
1668
1669   /* For notes, be conservative and simply remove them.  */
1670   loc = &REG_NOTES (insn);
1671   while (*loc)
1672     {
1673       enum reg_note kind = REG_NOTE_KIND (*loc);
1674       if (kind == REG_EQUAL || kind == REG_EQUIV)
1675         *loc = XEXP (*loc, 1);
1676       else
1677         loc = &XEXP (*loc, 1);
1678     }
1679
1680   /* The new insn will have a destination that was previously the destination
1681      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1682      the next use of that destination.  */
1683   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1684 }
1685
1686 /* Return TRUE if combine can reuse reg X in mode MODE.
1687    ADDED_SETS is nonzero if the original set is still required.  */
1688 static bool
1689 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1690 {
1691   unsigned int regno;
1692
1693   if (!REG_P(x))
1694     return false;
1695
1696   regno = REGNO (x);
1697   /* Allow hard registers if the new mode is legal, and occupies no more
1698      registers than the old mode.  */
1699   if (regno < FIRST_PSEUDO_REGISTER)
1700     return (HARD_REGNO_MODE_OK (regno, mode)
1701             && (hard_regno_nregs[regno][GET_MODE (x)]
1702                 >= hard_regno_nregs[regno][mode]));
1703
1704   /* Or a pseudo that is only used once.  */
1705   return (REG_N_SETS (regno) == 1 && !added_sets
1706           && !REG_USERVAR_P (x));
1707 }
1708
1709
1710 /* Check whether X, the destination of a set, refers to part of
1711    the register specified by REG.  */
1712
1713 static bool
1714 reg_subword_p (rtx x, rtx reg)
1715 {
1716   /* Check that reg is an integer mode register.  */
1717   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1718     return false;
1719
1720   if (GET_CODE (x) == STRICT_LOW_PART
1721       || GET_CODE (x) == ZERO_EXTRACT)
1722     x = XEXP (x, 0);
1723
1724   return GET_CODE (x) == SUBREG
1725          && SUBREG_REG (x) == reg
1726          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1727 }
1728
1729
1730 /* Try to combine the insns I1 and I2 into I3.
1731    Here I1 and I2 appear earlier than I3.
1732    I1 can be zero; then we combine just I2 into I3.
1733
1734    If we are combining three insns and the resulting insn is not recognized,
1735    try splitting it into two insns.  If that happens, I2 and I3 are retained
1736    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1737    are pseudo-deleted.
1738
1739    Return 0 if the combination does not work.  Then nothing is changed.
1740    If we did the combination, return the insn at which combine should
1741    resume scanning.
1742
1743    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1744    new direct jump instruction.  */
1745
1746 static rtx
1747 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1748 {
1749   /* New patterns for I3 and I2, respectively.  */
1750   rtx newpat, newi2pat = 0;
1751   rtvec newpat_vec_with_clobbers = 0;
1752   int substed_i2 = 0, substed_i1 = 0;
1753   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1754   int added_sets_1, added_sets_2;
1755   /* Total number of SETs to put into I3.  */
1756   int total_sets;
1757   /* Nonzero if I2's body now appears in I3.  */
1758   int i2_is_used;
1759   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1760   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1761   /* Contains I3 if the destination of I3 is used in its source, which means
1762      that the old life of I3 is being killed.  If that usage is placed into
1763      I2 and not in I3, a REG_DEAD note must be made.  */
1764   rtx i3dest_killed = 0;
1765   /* SET_DEST and SET_SRC of I2 and I1.  */
1766   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1767   /* PATTERN (I2), or a copy of it in certain cases.  */
1768   rtx i2pat;
1769   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1770   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1771   int i2dest_killed = 0, i1dest_killed = 0;
1772   int i1_feeds_i3 = 0;
1773   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1774   rtx new_i3_notes, new_i2_notes;
1775   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1776   int i3_subst_into_i2 = 0;
1777   /* Notes that I1, I2 or I3 is a MULT operation.  */
1778   int have_mult = 0;
1779   int swap_i2i3 = 0;
1780
1781   int maxreg;
1782   rtx temp;
1783   rtx link;
1784   int i;
1785
1786   /* Exit early if one of the insns involved can't be used for
1787      combinations.  */
1788   if (cant_combine_insn_p (i3)
1789       || cant_combine_insn_p (i2)
1790       || (i1 && cant_combine_insn_p (i1))
1791       || likely_spilled_retval_p (i3)
1792       /* We also can't do anything if I3 has a
1793          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1794          libcall.  */
1795 #if 0
1796       /* ??? This gives worse code, and appears to be unnecessary, since no
1797          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1798       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1799 #endif
1800       )
1801     return 0;
1802
1803   combine_attempts++;
1804   undobuf.other_insn = 0;
1805
1806   /* Reset the hard register usage information.  */
1807   CLEAR_HARD_REG_SET (newpat_used_regs);
1808
1809   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1810      code below, set I1 to be the earlier of the two insns.  */
1811   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1812     temp = i1, i1 = i2, i2 = temp;
1813
1814   added_links_insn = 0;
1815
1816   /* First check for one important special-case that the code below will
1817      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1818      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1819      we may be able to replace that destination with the destination of I3.
1820      This occurs in the common code where we compute both a quotient and
1821      remainder into a structure, in which case we want to do the computation
1822      directly into the structure to avoid register-register copies.
1823
1824      Note that this case handles both multiple sets in I2 and also
1825      cases where I2 has a number of CLOBBER or PARALLELs.
1826
1827      We make very conservative checks below and only try to handle the
1828      most common cases of this.  For example, we only handle the case
1829      where I2 and I3 are adjacent to avoid making difficult register
1830      usage tests.  */
1831
1832   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1833       && REG_P (SET_SRC (PATTERN (i3)))
1834       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1835       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1836       && GET_CODE (PATTERN (i2)) == PARALLEL
1837       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1838       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1839          below would need to check what is inside (and reg_overlap_mentioned_p
1840          doesn't support those codes anyway).  Don't allow those destinations;
1841          the resulting insn isn't likely to be recognized anyway.  */
1842       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1843       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1844       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1845                                     SET_DEST (PATTERN (i3)))
1846       && next_real_insn (i2) == i3)
1847     {
1848       rtx p2 = PATTERN (i2);
1849
1850       /* Make sure that the destination of I3,
1851          which we are going to substitute into one output of I2,
1852          is not used within another output of I2.  We must avoid making this:
1853          (parallel [(set (mem (reg 69)) ...)
1854                     (set (reg 69) ...)])
1855          which is not well-defined as to order of actions.
1856          (Besides, reload can't handle output reloads for this.)
1857
1858          The problem can also happen if the dest of I3 is a memory ref,
1859          if another dest in I2 is an indirect memory ref.  */
1860       for (i = 0; i < XVECLEN (p2, 0); i++)
1861         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1862              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1863             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1864                                         SET_DEST (XVECEXP (p2, 0, i))))
1865           break;
1866
1867       if (i == XVECLEN (p2, 0))
1868         for (i = 0; i < XVECLEN (p2, 0); i++)
1869           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1870                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1871               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1872             {
1873               combine_merges++;
1874
1875               subst_insn = i3;
1876               subst_low_cuid = INSN_CUID (i2);
1877
1878               added_sets_2 = added_sets_1 = 0;
1879               i2dest = SET_SRC (PATTERN (i3));
1880               i2dest_killed = dead_or_set_p (i2, i2dest);
1881
1882               /* Replace the dest in I2 with our dest and make the resulting
1883                  insn the new pattern for I3.  Then skip to where we
1884                  validate the pattern.  Everything was set up above.  */
1885               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1886                      SET_DEST (PATTERN (i3)));
1887
1888               newpat = p2;
1889               i3_subst_into_i2 = 1;
1890               goto validate_replacement;
1891             }
1892     }
1893
1894   /* If I2 is setting a pseudo to a constant and I3 is setting some
1895      sub-part of it to another constant, merge them by making a new
1896      constant.  */
1897   if (i1 == 0
1898       && (temp = single_set (i2)) != 0
1899       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1900           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1901       && GET_CODE (PATTERN (i3)) == SET
1902       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1903           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1904       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1905     {
1906       rtx dest = SET_DEST (PATTERN (i3));
1907       int offset = -1;
1908       int width = 0;
1909
1910       if (GET_CODE (dest) == STRICT_LOW_PART)
1911         {
1912           width = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)));
1913           offset = 0;
1914         }
1915       else if (GET_CODE (dest) == ZERO_EXTRACT)
1916         {
1917           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1918               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1919             {
1920               width = INTVAL (XEXP (dest, 1));
1921               offset = INTVAL (XEXP (dest, 2));
1922
1923               if (BITS_BIG_ENDIAN)
1924                 offset = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)))
1925                          - width - offset;
1926             }
1927         }
1928       else if (subreg_lowpart_p (dest))
1929         {
1930           width = GET_MODE_BITSIZE (GET_MODE (dest));
1931           offset = 0;
1932         }
1933       /* ??? Preserve the original logic to handle setting the high word
1934          of double-word pseudos, where inner is half the size of outer
1935          but not the lowpart.  This could be generalized by handling
1936          SUBREG_BYTE, WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN ourselves.
1937          Unfortunately this logic is tricky to get right and probably
1938          not worth the effort.  */
1939       else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1940                == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1941         {
1942           width = GET_MODE_BITSIZE (GET_MODE (dest));
1943           offset = width;
1944         }
1945
1946       if (offset >= 0)
1947         {
1948           HOST_WIDE_INT mhi, ohi, ihi;
1949           HOST_WIDE_INT mlo, olo, ilo;
1950           rtx inner = SET_SRC (PATTERN (i3));
1951           rtx outer = SET_SRC (temp);
1952
1953           if (GET_CODE (outer) == CONST_INT)
1954             {
1955               olo = INTVAL (outer);
1956               ohi = olo < 0 ? -1 : 0;
1957             }
1958           else
1959             {
1960               olo = CONST_DOUBLE_LOW (outer);
1961               ohi = CONST_DOUBLE_HIGH (outer);
1962             }
1963
1964           if (GET_CODE (inner) == CONST_INT)
1965             {
1966               ilo = INTVAL (inner);
1967               ihi = ilo < 0 ? -1 : 0;
1968             }
1969           else
1970             {
1971               ilo = CONST_DOUBLE_LOW (inner);
1972               ihi = CONST_DOUBLE_HIGH (inner);
1973             }
1974
1975           if (width < HOST_BITS_PER_WIDE_INT)
1976             {
1977               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
1978               mhi = 0;
1979             }
1980           else if (width < HOST_BITS_PER_WIDE_INT * 2)
1981             {
1982               mhi = ((unsigned HOST_WIDE_INT) 1
1983                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
1984               mlo = -1;
1985             }
1986           else
1987             {
1988               mlo = -1;
1989               mhi = -1;
1990             }
1991
1992           ilo &= mlo;
1993           ihi &= mhi;
1994
1995           if (offset >= HOST_BITS_PER_WIDE_INT)
1996             {
1997               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
1998               mlo = 0;
1999               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2000               ilo = 0;
2001             }
2002           else if (offset > 0)
2003             {
2004               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2005                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2006               mlo = mlo << offset;
2007               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2008                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2009               ilo = ilo << offset;
2010             }
2011
2012           olo = (olo & ~mlo) | ilo;
2013           ohi = (ohi & ~mhi) | ihi;
2014
2015           combine_merges++;
2016           subst_insn = i3;
2017           subst_low_cuid = INSN_CUID (i2);
2018           added_sets_2 = added_sets_1 = 0;
2019           i2dest = SET_DEST (temp);
2020           i2dest_killed = dead_or_set_p (i2, i2dest);
2021
2022           SUBST (SET_SRC (temp),
2023                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2024
2025           newpat = PATTERN (i2);
2026           goto validate_replacement;
2027         }
2028     }
2029
2030 #ifndef HAVE_cc0
2031   /* If we have no I1 and I2 looks like:
2032         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2033                    (set Y OP)])
2034      make up a dummy I1 that is
2035         (set Y OP)
2036      and change I2 to be
2037         (set (reg:CC X) (compare:CC Y (const_int 0)))
2038
2039      (We can ignore any trailing CLOBBERs.)
2040
2041      This undoes a previous combination and allows us to match a branch-and-
2042      decrement insn.  */
2043
2044   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2045       && XVECLEN (PATTERN (i2), 0) >= 2
2046       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2047       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2048           == MODE_CC)
2049       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2050       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2051       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2052       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2053       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2054                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2055     {
2056       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2057         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2058           break;
2059
2060       if (i == 1)
2061         {
2062           /* We make I1 with the same INSN_UID as I2.  This gives it
2063              the same INSN_CUID for value tracking.  Our fake I1 will
2064              never appear in the insn stream so giving it the same INSN_UID
2065              as I2 will not cause a problem.  */
2066
2067           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2068                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2069                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2070                              NULL_RTX);
2071
2072           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2073           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2074                  SET_DEST (PATTERN (i1)));
2075         }
2076     }
2077 #endif
2078
2079   /* Verify that I2 and I1 are valid for combining.  */
2080   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2081       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2082     {
2083       undo_all ();
2084       return 0;
2085     }
2086
2087   /* Record whether I2DEST is used in I2SRC and similarly for the other
2088      cases.  Knowing this will help in register status updating below.  */
2089   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2090   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2091   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2092   i2dest_killed = dead_or_set_p (i2, i2dest);
2093   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2094
2095   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2096      in I2SRC.  */
2097   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2098
2099   /* Ensure that I3's pattern can be the destination of combines.  */
2100   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2101                           i1 && i2dest_in_i1src && i1_feeds_i3,
2102                           &i3dest_killed))
2103     {
2104       undo_all ();
2105       return 0;
2106     }
2107
2108   /* See if any of the insns is a MULT operation.  Unless one is, we will
2109      reject a combination that is, since it must be slower.  Be conservative
2110      here.  */
2111   if (GET_CODE (i2src) == MULT
2112       || (i1 != 0 && GET_CODE (i1src) == MULT)
2113       || (GET_CODE (PATTERN (i3)) == SET
2114           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2115     have_mult = 1;
2116
2117   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2118      We used to do this EXCEPT in one case: I3 has a post-inc in an
2119      output operand.  However, that exception can give rise to insns like
2120         mov r3,(r3)+
2121      which is a famous insn on the PDP-11 where the value of r3 used as the
2122      source was model-dependent.  Avoid this sort of thing.  */
2123
2124 #if 0
2125   if (!(GET_CODE (PATTERN (i3)) == SET
2126         && REG_P (SET_SRC (PATTERN (i3)))
2127         && MEM_P (SET_DEST (PATTERN (i3)))
2128         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2129             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2130     /* It's not the exception.  */
2131 #endif
2132 #ifdef AUTO_INC_DEC
2133     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2134       if (REG_NOTE_KIND (link) == REG_INC
2135           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2136               || (i1 != 0
2137                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2138         {
2139           undo_all ();
2140           return 0;
2141         }
2142 #endif
2143
2144   /* See if the SETs in I1 or I2 need to be kept around in the merged
2145      instruction: whenever the value set there is still needed past I3.
2146      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2147
2148      For the SET in I1, we have two cases:  If I1 and I2 independently
2149      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2150      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2151      in I1 needs to be kept around unless I1DEST dies or is set in either
2152      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2153      I1DEST.  If so, we know I1 feeds into I2.  */
2154
2155   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2156
2157   added_sets_1
2158     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2159                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2160
2161   /* If the set in I2 needs to be kept around, we must make a copy of
2162      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2163      PATTERN (I2), we are only substituting for the original I1DEST, not into
2164      an already-substituted copy.  This also prevents making self-referential
2165      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2166      I2DEST.  */
2167
2168   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2169            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2170            : PATTERN (i2));
2171
2172   if (added_sets_2)
2173     i2pat = copy_rtx (i2pat);
2174
2175   combine_merges++;
2176
2177   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2178
2179   maxreg = max_reg_num ();
2180
2181   subst_insn = i3;
2182
2183 #ifndef HAVE_cc0
2184   /* Many machines that don't use CC0 have insns that can both perform an
2185      arithmetic operation and set the condition code.  These operations will
2186      be represented as a PARALLEL with the first element of the vector
2187      being a COMPARE of an arithmetic operation with the constant zero.
2188      The second element of the vector will set some pseudo to the result
2189      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2190      match such a pattern and so will generate an extra insn.   Here we test
2191      for this case, where both the comparison and the operation result are
2192      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2193      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2194
2195   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2196       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2197       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2198       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2199     {
2200 #ifdef SELECT_CC_MODE
2201       rtx *cc_use;
2202       enum machine_mode compare_mode;
2203 #endif
2204
2205       newpat = PATTERN (i3);
2206       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2207
2208       i2_is_used = 1;
2209
2210 #ifdef SELECT_CC_MODE
2211       /* See if a COMPARE with the operand we substituted in should be done
2212          with the mode that is currently being used.  If not, do the same
2213          processing we do in `subst' for a SET; namely, if the destination
2214          is used only once, try to replace it with a register of the proper
2215          mode and also replace the COMPARE.  */
2216       if (undobuf.other_insn == 0
2217           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2218                                         &undobuf.other_insn))
2219           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2220                                               i2src, const0_rtx))
2221               != GET_MODE (SET_DEST (newpat))))
2222         {
2223           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2224                                    compare_mode))
2225             {
2226               unsigned int regno = REGNO (SET_DEST (newpat));
2227               rtx new_dest = gen_rtx_REG (compare_mode, regno);
2228
2229               if (regno >= FIRST_PSEUDO_REGISTER)
2230                 SUBST (regno_reg_rtx[regno], new_dest);
2231
2232               SUBST (SET_DEST (newpat), new_dest);
2233               SUBST (XEXP (*cc_use, 0), new_dest);
2234               SUBST (SET_SRC (newpat),
2235                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2236             }
2237           else
2238             undobuf.other_insn = 0;
2239         }
2240 #endif
2241     }
2242   else
2243 #endif
2244     {
2245       /* It is possible that the source of I2 or I1 may be performing
2246          an unneeded operation, such as a ZERO_EXTEND of something
2247          that is known to have the high part zero.  Handle that case
2248          by letting subst look at the innermost one of them.
2249
2250          Another way to do this would be to have a function that tries
2251          to simplify a single insn instead of merging two or more
2252          insns.  We don't do this because of the potential of infinite
2253          loops and because of the potential extra memory required.
2254          However, doing it the way we are is a bit of a kludge and
2255          doesn't catch all cases.
2256
2257          But only do this if -fexpensive-optimizations since it slows
2258          things down and doesn't usually win.
2259
2260          This is not done in the COMPARE case above because the
2261          unmodified I2PAT is used in the PARALLEL and so a pattern
2262          with a modified I2SRC would not match.  */
2263
2264       if (flag_expensive_optimizations)
2265         {
2266           /* Pass pc_rtx so no substitutions are done, just
2267              simplifications.  */
2268           if (i1)
2269             {
2270               subst_low_cuid = INSN_CUID (i1);
2271               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2272             }
2273           else
2274             {
2275               subst_low_cuid = INSN_CUID (i2);
2276               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2277             }
2278         }
2279
2280       n_occurrences = 0;                /* `subst' counts here */
2281
2282       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2283          need to make a unique copy of I2SRC each time we substitute it
2284          to avoid self-referential rtl.  */
2285
2286       subst_low_cuid = INSN_CUID (i2);
2287       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2288                       ! i1_feeds_i3 && i1dest_in_i1src);
2289       substed_i2 = 1;
2290
2291       /* Record whether i2's body now appears within i3's body.  */
2292       i2_is_used = n_occurrences;
2293     }
2294
2295   /* If we already got a failure, don't try to do more.  Otherwise,
2296      try to substitute in I1 if we have it.  */
2297
2298   if (i1 && GET_CODE (newpat) != CLOBBER)
2299     {
2300       /* Before we can do this substitution, we must redo the test done
2301          above (see detailed comments there) that ensures  that I1DEST
2302          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2303
2304       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2305                               0, (rtx*) 0))
2306         {
2307           undo_all ();
2308           return 0;
2309         }
2310
2311       n_occurrences = 0;
2312       subst_low_cuid = INSN_CUID (i1);
2313       newpat = subst (newpat, i1dest, i1src, 0, 0);
2314       substed_i1 = 1;
2315     }
2316
2317   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2318      to count all the ways that I2SRC and I1SRC can be used.  */
2319   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2320        && i2_is_used + added_sets_2 > 1)
2321       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2322           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2323               > 1))
2324       /* Fail if we tried to make a new register.  */
2325       || max_reg_num () != maxreg
2326       /* Fail if we couldn't do something and have a CLOBBER.  */
2327       || GET_CODE (newpat) == CLOBBER
2328       /* Fail if this new pattern is a MULT and we didn't have one before
2329          at the outer level.  */
2330       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2331           && ! have_mult))
2332     {
2333       undo_all ();
2334       return 0;
2335     }
2336
2337   /* If the actions of the earlier insns must be kept
2338      in addition to substituting them into the latest one,
2339      we must make a new PARALLEL for the latest insn
2340      to hold additional the SETs.  */
2341
2342   if (added_sets_1 || added_sets_2)
2343     {
2344       combine_extras++;
2345
2346       if (GET_CODE (newpat) == PARALLEL)
2347         {
2348           rtvec old = XVEC (newpat, 0);
2349           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2350           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2351           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2352                   sizeof (old->elem[0]) * old->num_elem);
2353         }
2354       else
2355         {
2356           rtx old = newpat;
2357           total_sets = 1 + added_sets_1 + added_sets_2;
2358           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2359           XVECEXP (newpat, 0, 0) = old;
2360         }
2361
2362       if (added_sets_1)
2363         XVECEXP (newpat, 0, --total_sets)
2364           = (GET_CODE (PATTERN (i1)) == PARALLEL
2365              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2366
2367       if (added_sets_2)
2368         {
2369           /* If there is no I1, use I2's body as is.  We used to also not do
2370              the subst call below if I2 was substituted into I3,
2371              but that could lose a simplification.  */
2372           if (i1 == 0)
2373             XVECEXP (newpat, 0, --total_sets) = i2pat;
2374           else
2375             /* See comment where i2pat is assigned.  */
2376             XVECEXP (newpat, 0, --total_sets)
2377               = subst (i2pat, i1dest, i1src, 0, 0);
2378         }
2379     }
2380
2381   /* We come here when we are replacing a destination in I2 with the
2382      destination of I3.  */
2383  validate_replacement:
2384
2385   /* Note which hard regs this insn has as inputs.  */
2386   mark_used_regs_combine (newpat);
2387
2388   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2389      consider splitting this pattern, we might need these clobbers.  */
2390   if (i1 && GET_CODE (newpat) == PARALLEL
2391       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2392     {
2393       int len = XVECLEN (newpat, 0);
2394
2395       newpat_vec_with_clobbers = rtvec_alloc (len);
2396       for (i = 0; i < len; i++)
2397         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2398     }
2399
2400   /* Is the result of combination a valid instruction?  */
2401   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2402
2403   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2404      the second SET's destination is a register that is unused and isn't
2405      marked as an instruction that might trap in an EH region.  In that case,
2406      we just need the first SET.   This can occur when simplifying a divmod
2407      insn.  We *must* test for this case here because the code below that
2408      splits two independent SETs doesn't handle this case correctly when it
2409      updates the register status.
2410
2411      It's pointless doing this if we originally had two sets, one from
2412      i3, and one from i2.  Combining then splitting the parallel results
2413      in the original i2 again plus an invalid insn (which we delete).
2414      The net effect is only to move instructions around, which makes
2415      debug info less accurate.
2416
2417      Also check the case where the first SET's destination is unused.
2418      That would not cause incorrect code, but does cause an unneeded
2419      insn to remain.  */
2420
2421   if (insn_code_number < 0
2422       && !(added_sets_2 && i1 == 0)
2423       && GET_CODE (newpat) == PARALLEL
2424       && XVECLEN (newpat, 0) == 2
2425       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2426       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2427       && asm_noperands (newpat) < 0)
2428     {
2429       rtx set0 = XVECEXP (newpat, 0, 0);
2430       rtx set1 = XVECEXP (newpat, 0, 1);
2431       rtx note;
2432
2433       if (((REG_P (SET_DEST (set1))
2434             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2435            || (GET_CODE (SET_DEST (set1)) == SUBREG
2436                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2437           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2438               || INTVAL (XEXP (note, 0)) <= 0)
2439           && ! side_effects_p (SET_SRC (set1)))
2440         {
2441           newpat = set0;
2442           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2443         }
2444
2445       else if (((REG_P (SET_DEST (set0))
2446                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2447                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2448                     && find_reg_note (i3, REG_UNUSED,
2449                                       SUBREG_REG (SET_DEST (set0)))))
2450                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2451                    || INTVAL (XEXP (note, 0)) <= 0)
2452                && ! side_effects_p (SET_SRC (set0)))
2453         {
2454           newpat = set1;
2455           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2456
2457           if (insn_code_number >= 0)
2458             {
2459               /* If we will be able to accept this, we have made a
2460                  change to the destination of I3.  This requires us to
2461                  do a few adjustments.  */
2462
2463               PATTERN (i3) = newpat;
2464               adjust_for_new_dest (i3);
2465             }
2466         }
2467     }
2468
2469   /* If we were combining three insns and the result is a simple SET
2470      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2471      insns.  There are two ways to do this.  It can be split using a
2472      machine-specific method (like when you have an addition of a large
2473      constant) or by combine in the function find_split_point.  */
2474
2475   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2476       && asm_noperands (newpat) < 0)
2477     {
2478       rtx m_split, *split;
2479       rtx ni2dest = i2dest;
2480
2481       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2482          use I2DEST as a scratch register will help.  In the latter case,
2483          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2484
2485       m_split = split_insns (newpat, i3);
2486
2487       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2488          inputs of NEWPAT.  */
2489
2490       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2491          possible to try that as a scratch reg.  This would require adding
2492          more code to make it work though.  */
2493
2494       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2495         {
2496           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2497           /* If I2DEST is a hard register or the only use of a pseudo,
2498              we can change its mode.  */
2499           if (new_mode != GET_MODE (i2dest)
2500               && new_mode != VOIDmode
2501               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2502             ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2503                                    REGNO (i2dest));
2504
2505           m_split = split_insns (gen_rtx_PARALLEL
2506                                  (VOIDmode,
2507                                   gen_rtvec (2, newpat,
2508                                              gen_rtx_CLOBBER (VOIDmode,
2509                                                               ni2dest))),
2510                                  i3);
2511           /* If the split with the mode-changed register didn't work, try
2512              the original register.  */
2513           if (! m_split && ni2dest != i2dest)
2514             {
2515               ni2dest = i2dest;
2516               m_split = split_insns (gen_rtx_PARALLEL
2517                                      (VOIDmode,
2518                                       gen_rtvec (2, newpat,
2519                                                  gen_rtx_CLOBBER (VOIDmode,
2520                                                                   i2dest))),
2521                                      i3);
2522             }
2523         }
2524
2525       /* If recog_for_combine has discarded clobbers, try to use them
2526          again for the split.  */
2527       if (m_split == 0 && newpat_vec_with_clobbers)
2528         m_split
2529           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2530                                            newpat_vec_with_clobbers), i3);
2531
2532       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2533         {
2534           m_split = PATTERN (m_split);
2535           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2536           if (insn_code_number >= 0)
2537             newpat = m_split;
2538         }
2539       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2540                && (next_real_insn (i2) == i3
2541                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2542         {
2543           rtx i2set, i3set;
2544           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2545           newi2pat = PATTERN (m_split);
2546
2547           i3set = single_set (NEXT_INSN (m_split));
2548           i2set = single_set (m_split);
2549
2550           /* In case we changed the mode of I2DEST, replace it in the
2551              pseudo-register table here.  We can't do it above in case this
2552              code doesn't get executed and we do a split the other way.  */
2553
2554           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2555             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2556
2557           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2558
2559           /* If I2 or I3 has multiple SETs, we won't know how to track
2560              register status, so don't use these insns.  If I2's destination
2561              is used between I2 and I3, we also can't use these insns.  */
2562
2563           if (i2_code_number >= 0 && i2set && i3set
2564               && (next_real_insn (i2) == i3
2565                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2566             insn_code_number = recog_for_combine (&newi3pat, i3,
2567                                                   &new_i3_notes);
2568           if (insn_code_number >= 0)
2569             newpat = newi3pat;
2570
2571           /* It is possible that both insns now set the destination of I3.
2572              If so, we must show an extra use of it.  */
2573
2574           if (insn_code_number >= 0)
2575             {
2576               rtx new_i3_dest = SET_DEST (i3set);
2577               rtx new_i2_dest = SET_DEST (i2set);
2578
2579               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2580                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2581                      || GET_CODE (new_i3_dest) == SUBREG)
2582                 new_i3_dest = XEXP (new_i3_dest, 0);
2583
2584               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2585                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2586                      || GET_CODE (new_i2_dest) == SUBREG)
2587                 new_i2_dest = XEXP (new_i2_dest, 0);
2588
2589               if (REG_P (new_i3_dest)
2590                   && REG_P (new_i2_dest)
2591                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2592                 REG_N_SETS (REGNO (new_i2_dest))++;
2593             }
2594         }
2595
2596       /* If we can split it and use I2DEST, go ahead and see if that
2597          helps things be recognized.  Verify that none of the registers
2598          are set between I2 and I3.  */
2599       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2600 #ifdef HAVE_cc0
2601           && REG_P (i2dest)
2602 #endif
2603           /* We need I2DEST in the proper mode.  If it is a hard register
2604              or the only use of a pseudo, we can change its mode.
2605              Make sure we don't change a hard register to have a mode that
2606              isn't valid for it, or change the number of registers.  */
2607           && (GET_MODE (*split) == GET_MODE (i2dest)
2608               || GET_MODE (*split) == VOIDmode
2609               || can_change_dest_mode (i2dest, added_sets_2,
2610                                        GET_MODE (*split)))
2611           && (next_real_insn (i2) == i3
2612               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2613           /* We can't overwrite I2DEST if its value is still used by
2614              NEWPAT.  */
2615           && ! reg_referenced_p (i2dest, newpat))
2616         {
2617           rtx newdest = i2dest;
2618           enum rtx_code split_code = GET_CODE (*split);
2619           enum machine_mode split_mode = GET_MODE (*split);
2620           bool subst_done = false;
2621           newi2pat = NULL_RTX;
2622
2623           /* Get NEWDEST as a register in the proper mode.  We have already
2624              validated that we can do this.  */
2625           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2626             {
2627               newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2628
2629               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2630                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2631             }
2632
2633           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2634              an ASHIFT.  This can occur if it was inside a PLUS and hence
2635              appeared to be a memory address.  This is a kludge.  */
2636           if (split_code == MULT
2637               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2638               && INTVAL (XEXP (*split, 1)) > 0
2639               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2640             {
2641               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2642                                              XEXP (*split, 0), GEN_INT (i)));
2643               /* Update split_code because we may not have a multiply
2644                  anymore.  */
2645               split_code = GET_CODE (*split);
2646             }
2647
2648 #ifdef INSN_SCHEDULING
2649           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2650              be written as a ZERO_EXTEND.  */
2651           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2652             {
2653 #ifdef LOAD_EXTEND_OP
2654               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2655                  what it really is.  */
2656               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2657                   == SIGN_EXTEND)
2658                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2659                                                     SUBREG_REG (*split)));
2660               else
2661 #endif
2662                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2663                                                     SUBREG_REG (*split)));
2664             }
2665 #endif
2666
2667           /* Attempt to split binary operators using arithmetic identities.  */
2668           if (BINARY_P (SET_SRC (newpat))
2669               && split_mode == GET_MODE (SET_SRC (newpat))
2670               && ! side_effects_p (SET_SRC (newpat)))
2671             {
2672               rtx setsrc = SET_SRC (newpat);
2673               enum machine_mode mode = GET_MODE (setsrc);
2674               enum rtx_code code = GET_CODE (setsrc);
2675               rtx src_op0 = XEXP (setsrc, 0);
2676               rtx src_op1 = XEXP (setsrc, 1);
2677
2678               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2679               if (rtx_equal_p (src_op0, src_op1))
2680                 {
2681                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2682                   SUBST (XEXP (setsrc, 0), newdest);
2683                   SUBST (XEXP (setsrc, 1), newdest);
2684                   subst_done = true;
2685                 }
2686               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2687               else if ((code == PLUS || code == MULT)
2688                        && GET_CODE (src_op0) == code
2689                        && GET_CODE (XEXP (src_op0, 0)) == code
2690                        && (INTEGRAL_MODE_P (mode)
2691                            || (FLOAT_MODE_P (mode)
2692                                && flag_unsafe_math_optimizations)))
2693                 {
2694                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2695                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2696                   rtx r = XEXP (src_op0, 1);
2697                   rtx s = src_op1;
2698
2699                   /* Split both "((X op Y) op X) op Y" and
2700                      "((X op Y) op Y) op X" as "T op T" where T is
2701                      "X op Y".  */
2702                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2703                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2704                     {
2705                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2706                                               XEXP (src_op0, 0));
2707                       SUBST (XEXP (setsrc, 0), newdest);
2708                       SUBST (XEXP (setsrc, 1), newdest);
2709                       subst_done = true;
2710                     }
2711                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2712                      T is "X op Y".  */
2713                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2714                     {
2715                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2716                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2717                       SUBST (XEXP (setsrc, 0), newdest);
2718                       SUBST (XEXP (setsrc, 1), newdest);
2719                       subst_done = true;
2720                     }
2721                 }
2722             }
2723
2724           if (!subst_done)
2725             {
2726               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2727               SUBST (*split, newdest);
2728             }
2729
2730           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2731
2732           /* recog_for_combine might have added CLOBBERs to newi2pat.
2733              Make sure NEWPAT does not depend on the clobbered regs.  */
2734           if (GET_CODE (newi2pat) == PARALLEL)
2735             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2736               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2737                 {
2738                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2739                   if (reg_overlap_mentioned_p (reg, newpat))
2740                     {
2741                       undo_all ();
2742                       return 0;
2743                     }
2744                 }
2745
2746           /* If the split point was a MULT and we didn't have one before,
2747              don't use one now.  */
2748           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2749             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2750         }
2751     }
2752
2753   /* Check for a case where we loaded from memory in a narrow mode and
2754      then sign extended it, but we need both registers.  In that case,
2755      we have a PARALLEL with both loads from the same memory location.
2756      We can split this into a load from memory followed by a register-register
2757      copy.  This saves at least one insn, more if register allocation can
2758      eliminate the copy.
2759
2760      We cannot do this if the destination of the first assignment is a
2761      condition code register or cc0.  We eliminate this case by making sure
2762      the SET_DEST and SET_SRC have the same mode.
2763
2764      We cannot do this if the destination of the second assignment is
2765      a register that we have already assumed is zero-extended.  Similarly
2766      for a SUBREG of such a register.  */
2767
2768   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2769            && GET_CODE (newpat) == PARALLEL
2770            && XVECLEN (newpat, 0) == 2
2771            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2772            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2773            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2774                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2775            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2776            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2777                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2778            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2779                                    INSN_CUID (i2))
2780            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2781            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2782            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2783                  (REG_P (temp)
2784                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2785                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2786                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2787                   && (reg_stat[REGNO (temp)].nonzero_bits
2788                       != GET_MODE_MASK (word_mode))))
2789            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2790                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2791                      (REG_P (temp)
2792                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2793                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2794                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2795                       && (reg_stat[REGNO (temp)].nonzero_bits
2796                           != GET_MODE_MASK (word_mode)))))
2797            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2798                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2799            && ! find_reg_note (i3, REG_UNUSED,
2800                                SET_DEST (XVECEXP (newpat, 0, 0))))
2801     {
2802       rtx ni2dest;
2803
2804       newi2pat = XVECEXP (newpat, 0, 0);
2805       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2806       newpat = XVECEXP (newpat, 0, 1);
2807       SUBST (SET_SRC (newpat),
2808              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2809       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2810
2811       if (i2_code_number >= 0)
2812         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2813
2814       if (insn_code_number >= 0)
2815         swap_i2i3 = 1;
2816     }
2817
2818   /* Similarly, check for a case where we have a PARALLEL of two independent
2819      SETs but we started with three insns.  In this case, we can do the sets
2820      as two separate insns.  This case occurs when some SET allows two
2821      other insns to combine, but the destination of that SET is still live.  */
2822
2823   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2824            && GET_CODE (newpat) == PARALLEL
2825            && XVECLEN (newpat, 0) == 2
2826            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2827            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2828            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2829            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2830            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2831            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2832            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2833                                    INSN_CUID (i2))
2834            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2835            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2836            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2837            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2838                                   XVECEXP (newpat, 0, 0))
2839            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2840                                   XVECEXP (newpat, 0, 1))
2841            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2842                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2843     {
2844       /* Normally, it doesn't matter which of the two is done first,
2845          but it does if one references cc0.  In that case, it has to
2846          be first.  */
2847 #ifdef HAVE_cc0
2848       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2849         {
2850           newi2pat = XVECEXP (newpat, 0, 0);
2851           newpat = XVECEXP (newpat, 0, 1);
2852         }
2853       else
2854 #endif
2855         {
2856           newi2pat = XVECEXP (newpat, 0, 1);
2857           newpat = XVECEXP (newpat, 0, 0);
2858         }
2859
2860       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2861
2862       if (i2_code_number >= 0)
2863         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2864     }
2865
2866   /* If it still isn't recognized, fail and change things back the way they
2867      were.  */
2868   if ((insn_code_number < 0
2869        /* Is the result a reasonable ASM_OPERANDS?  */
2870        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2871     {
2872       undo_all ();
2873       return 0;
2874     }
2875
2876   /* If we had to change another insn, make sure it is valid also.  */
2877   if (undobuf.other_insn)
2878     {
2879       rtx other_pat = PATTERN (undobuf.other_insn);
2880       rtx new_other_notes;
2881       rtx note, next;
2882
2883       CLEAR_HARD_REG_SET (newpat_used_regs);
2884
2885       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2886                                              &new_other_notes);
2887
2888       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2889         {
2890           undo_all ();
2891           return 0;
2892         }
2893
2894       PATTERN (undobuf.other_insn) = other_pat;
2895
2896       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2897          are still valid.  Then add any non-duplicate notes added by
2898          recog_for_combine.  */
2899       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2900         {
2901           next = XEXP (note, 1);
2902
2903           if (REG_NOTE_KIND (note) == REG_UNUSED
2904               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2905             {
2906               if (REG_P (XEXP (note, 0)))
2907                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2908
2909               remove_note (undobuf.other_insn, note);
2910             }
2911         }
2912
2913       for (note = new_other_notes; note; note = XEXP (note, 1))
2914         if (REG_P (XEXP (note, 0)))
2915           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2916
2917       distribute_notes (new_other_notes, undobuf.other_insn,
2918                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2919     }
2920 #ifdef HAVE_cc0
2921   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2922      they are adjacent to each other or not.  */
2923   {
2924     rtx p = prev_nonnote_insn (i3);
2925     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2926         && sets_cc0_p (newi2pat))
2927       {
2928         undo_all ();
2929         return 0;
2930       }
2931   }
2932 #endif
2933
2934   /* Only allow this combination if insn_rtx_costs reports that the
2935      replacement instructions are cheaper than the originals.  */
2936   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2937     {
2938       undo_all ();
2939       return 0;
2940     }
2941
2942   /* We now know that we can do this combination.  Merge the insns and
2943      update the status of registers and LOG_LINKS.  */
2944
2945   if (swap_i2i3)
2946     {
2947       rtx insn;
2948       rtx link;
2949       rtx ni2dest;
2950
2951       /* I3 now uses what used to be its destination and which is now
2952          I2's destination.  This requires us to do a few adjustments.  */
2953       PATTERN (i3) = newpat;
2954       adjust_for_new_dest (i3);
2955
2956       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
2957          so we still will.
2958
2959          However, some later insn might be using I2's dest and have
2960          a LOG_LINK pointing at I3.  We must remove this link.
2961          The simplest way to remove the link is to point it at I1,
2962          which we know will be a NOTE.  */
2963
2964       /* newi2pat is usually a SET here; however, recog_for_combine might
2965          have added some clobbers.  */
2966       if (GET_CODE (newi2pat) == PARALLEL)
2967         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2968       else
2969         ni2dest = SET_DEST (newi2pat);
2970
2971       for (insn = NEXT_INSN (i3);
2972            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2973                     || insn != BB_HEAD (this_basic_block->next_bb));
2974            insn = NEXT_INSN (insn))
2975         {
2976           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2977             {
2978               for (link = LOG_LINKS (insn); link;
2979                    link = XEXP (link, 1))
2980                 if (XEXP (link, 0) == i3)
2981                   XEXP (link, 0) = i1;
2982
2983               break;
2984             }
2985         }
2986     }
2987
2988   {
2989     rtx i3notes, i2notes, i1notes = 0;
2990     rtx i3links, i2links, i1links = 0;
2991     rtx midnotes = 0;
2992     unsigned int regno;
2993     /* Compute which registers we expect to eliminate.  newi2pat may be setting
2994        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
2995        same as i3dest, in which case newi2pat may be setting i1dest.  */
2996     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2997                    || i2dest_in_i2src || i2dest_in_i1src
2998                    || !i2dest_killed
2999                    ? 0 : i2dest);
3000     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3001                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3002                    || !i1dest_killed
3003                    ? 0 : i1dest);
3004
3005     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3006        clear them.  */
3007     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3008     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3009     if (i1)
3010       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3011
3012     /* Ensure that we do not have something that should not be shared but
3013        occurs multiple times in the new insns.  Check this by first
3014        resetting all the `used' flags and then copying anything is shared.  */
3015
3016     reset_used_flags (i3notes);
3017     reset_used_flags (i2notes);
3018     reset_used_flags (i1notes);
3019     reset_used_flags (newpat);
3020     reset_used_flags (newi2pat);
3021     if (undobuf.other_insn)
3022       reset_used_flags (PATTERN (undobuf.other_insn));
3023
3024     i3notes = copy_rtx_if_shared (i3notes);
3025     i2notes = copy_rtx_if_shared (i2notes);
3026     i1notes = copy_rtx_if_shared (i1notes);
3027     newpat = copy_rtx_if_shared (newpat);
3028     newi2pat = copy_rtx_if_shared (newi2pat);
3029     if (undobuf.other_insn)
3030       reset_used_flags (PATTERN (undobuf.other_insn));
3031
3032     INSN_CODE (i3) = insn_code_number;
3033     PATTERN (i3) = newpat;
3034
3035     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3036       {
3037         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3038
3039         reset_used_flags (call_usage);
3040         call_usage = copy_rtx (call_usage);
3041
3042         if (substed_i2)
3043           replace_rtx (call_usage, i2dest, i2src);
3044
3045         if (substed_i1)
3046           replace_rtx (call_usage, i1dest, i1src);
3047
3048         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3049       }
3050
3051     if (undobuf.other_insn)
3052       INSN_CODE (undobuf.other_insn) = other_code_number;
3053
3054     /* We had one special case above where I2 had more than one set and
3055        we replaced a destination of one of those sets with the destination
3056        of I3.  In that case, we have to update LOG_LINKS of insns later
3057        in this basic block.  Note that this (expensive) case is rare.
3058
3059        Also, in this case, we must pretend that all REG_NOTEs for I2
3060        actually came from I3, so that REG_UNUSED notes from I2 will be
3061        properly handled.  */
3062
3063     if (i3_subst_into_i2)
3064       {
3065         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3066           if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
3067               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3068               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3069               && ! find_reg_note (i2, REG_UNUSED,
3070                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3071             for (temp = NEXT_INSN (i2);
3072                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3073                           || BB_HEAD (this_basic_block) != temp);
3074                  temp = NEXT_INSN (temp))
3075               if (temp != i3 && INSN_P (temp))
3076                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3077                   if (XEXP (link, 0) == i2)
3078                     XEXP (link, 0) = i3;
3079
3080         if (i3notes)
3081           {
3082             rtx link = i3notes;
3083             while (XEXP (link, 1))
3084               link = XEXP (link, 1);
3085             XEXP (link, 1) = i2notes;
3086           }
3087         else
3088           i3notes = i2notes;
3089         i2notes = 0;
3090       }
3091
3092     LOG_LINKS (i3) = 0;
3093     REG_NOTES (i3) = 0;
3094     LOG_LINKS (i2) = 0;
3095     REG_NOTES (i2) = 0;
3096
3097     if (newi2pat)
3098       {
3099         INSN_CODE (i2) = i2_code_number;
3100         PATTERN (i2) = newi2pat;
3101       }
3102     else
3103       SET_INSN_DELETED (i2);
3104
3105     if (i1)
3106       {
3107         LOG_LINKS (i1) = 0;
3108         REG_NOTES (i1) = 0;
3109         SET_INSN_DELETED (i1);
3110       }
3111
3112     /* Get death notes for everything that is now used in either I3 or
3113        I2 and used to die in a previous insn.  If we built two new
3114        patterns, move from I1 to I2 then I2 to I3 so that we get the
3115        proper movement on registers that I2 modifies.  */
3116
3117     if (newi2pat)
3118       {
3119         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3120         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3121       }
3122     else
3123       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3124                    i3, &midnotes);
3125
3126     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3127     if (i3notes)
3128       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3129                         elim_i2, elim_i1);
3130     if (i2notes)
3131       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3132                         elim_i2, elim_i1);
3133     if (i1notes)
3134       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3135                         elim_i2, elim_i1);
3136     if (midnotes)
3137       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3138                         elim_i2, elim_i1);
3139
3140     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3141        know these are REG_UNUSED and want them to go to the desired insn,
3142        so we always pass it as i3.  We have not counted the notes in
3143        reg_n_deaths yet, so we need to do so now.  */
3144
3145     if (newi2pat && new_i2_notes)
3146       {
3147         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3148           if (REG_P (XEXP (temp, 0)))
3149             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3150
3151         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3152       }
3153
3154     if (new_i3_notes)
3155       {
3156         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3157           if (REG_P (XEXP (temp, 0)))
3158             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3159
3160         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3161       }
3162
3163     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3164        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3165        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3166        in that case, it might delete I2.  Similarly for I2 and I1.
3167        Show an additional death due to the REG_DEAD note we make here.  If
3168        we discard it in distribute_notes, we will decrement it again.  */
3169
3170     if (i3dest_killed)
3171       {
3172         if (REG_P (i3dest_killed))
3173           REG_N_DEATHS (REGNO (i3dest_killed))++;
3174
3175         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3176           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3177                                                NULL_RTX),
3178                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3179         else
3180           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3181                                                NULL_RTX),
3182                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3183                             elim_i2, elim_i1);
3184       }
3185
3186     if (i2dest_in_i2src)
3187       {
3188         if (REG_P (i2dest))
3189           REG_N_DEATHS (REGNO (i2dest))++;
3190
3191         if (newi2pat && reg_set_p (i2dest, newi2pat))
3192           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3193                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3194         else
3195           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3196                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3197                             NULL_RTX, NULL_RTX);
3198       }
3199
3200     if (i1dest_in_i1src)
3201       {
3202         if (REG_P (i1dest))
3203           REG_N_DEATHS (REGNO (i1dest))++;
3204
3205         if (newi2pat && reg_set_p (i1dest, newi2pat))
3206           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3207                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3208         else
3209           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3210                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3211                             NULL_RTX, NULL_RTX);
3212       }
3213
3214     distribute_links (i3links);
3215     distribute_links (i2links);
3216     distribute_links (i1links);
3217
3218     if (REG_P (i2dest))
3219       {
3220         rtx link;
3221         rtx i2_insn = 0, i2_val = 0, set;
3222
3223         /* The insn that used to set this register doesn't exist, and
3224            this life of the register may not exist either.  See if one of
3225            I3's links points to an insn that sets I2DEST.  If it does,
3226            that is now the last known value for I2DEST. If we don't update
3227            this and I2 set the register to a value that depended on its old
3228            contents, we will get confused.  If this insn is used, thing
3229            will be set correctly in combine_instructions.  */
3230
3231         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3232           if ((set = single_set (XEXP (link, 0))) != 0
3233               && rtx_equal_p (i2dest, SET_DEST (set)))
3234             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3235
3236         record_value_for_reg (i2dest, i2_insn, i2_val);
3237
3238         /* If the reg formerly set in I2 died only once and that was in I3,
3239            zero its use count so it won't make `reload' do any work.  */
3240         if (! added_sets_2
3241             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3242             && ! i2dest_in_i2src)
3243           {
3244             regno = REGNO (i2dest);
3245             REG_N_SETS (regno)--;
3246           }
3247       }
3248
3249     if (i1 && REG_P (i1dest))
3250       {
3251         rtx link;
3252         rtx i1_insn = 0, i1_val = 0, set;
3253
3254         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3255           if ((set = single_set (XEXP (link, 0))) != 0
3256               && rtx_equal_p (i1dest, SET_DEST (set)))
3257             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3258
3259         record_value_for_reg (i1dest, i1_insn, i1_val);
3260
3261         regno = REGNO (i1dest);
3262         if (! added_sets_1 && ! i1dest_in_i1src)
3263           REG_N_SETS (regno)--;
3264       }
3265
3266     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3267        been made to this insn.  The order of
3268        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3269        can affect nonzero_bits of newpat */
3270     if (newi2pat)
3271       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3272     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3273
3274     /* Set new_direct_jump_p if a new return or simple jump instruction
3275        has been created.
3276
3277        If I3 is now an unconditional jump, ensure that it has a
3278        BARRIER following it since it may have initially been a
3279        conditional jump.  It may also be the last nonnote insn.  */
3280
3281     if (returnjump_p (i3) || any_uncondjump_p (i3))
3282       {
3283         *new_direct_jump_p = 1;
3284         mark_jump_label (PATTERN (i3), i3, 0);
3285
3286         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3287             || !BARRIER_P (temp))
3288           emit_barrier_after (i3);
3289       }
3290
3291     if (undobuf.other_insn != NULL_RTX
3292         && (returnjump_p (undobuf.other_insn)
3293             || any_uncondjump_p (undobuf.other_insn)))
3294       {
3295         *new_direct_jump_p = 1;
3296
3297         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3298             || !BARRIER_P (temp))
3299           emit_barrier_after (undobuf.other_insn);
3300       }
3301
3302     /* An NOOP jump does not need barrier, but it does need cleaning up
3303        of CFG.  */
3304     if (GET_CODE (newpat) == SET
3305         && SET_SRC (newpat) == pc_rtx
3306         && SET_DEST (newpat) == pc_rtx)
3307       *new_direct_jump_p = 1;
3308   }
3309
3310   combine_successes++;
3311   undo_commit ();
3312
3313   if (added_links_insn
3314       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3315       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3316     return added_links_insn;
3317   else
3318     return newi2pat ? i2 : i3;
3319 }
3320 \f
3321 /* Undo all the modifications recorded in undobuf.  */
3322
3323 static void
3324 undo_all (void)
3325 {
3326   struct undo *undo, *next;
3327
3328   for (undo = undobuf.undos; undo; undo = next)
3329     {
3330       next = undo->next;
3331       if (undo->is_int)
3332         *undo->where.i = undo->old_contents.i;
3333       else
3334         *undo->where.r = undo->old_contents.r;
3335
3336       undo->next = undobuf.frees;
3337       undobuf.frees = undo;
3338     }
3339
3340   undobuf.undos = 0;
3341 }
3342
3343 /* We've committed to accepting the changes we made.  Move all
3344    of the undos to the free list.  */
3345
3346 static void
3347 undo_commit (void)
3348 {
3349   struct undo *undo, *next;
3350
3351   for (undo = undobuf.undos; undo; undo = next)
3352     {
3353       next = undo->next;
3354       undo->next = undobuf.frees;
3355       undobuf.frees = undo;
3356     }
3357   undobuf.undos = 0;
3358 }
3359
3360 \f
3361 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3362    where we have an arithmetic expression and return that point.  LOC will
3363    be inside INSN.
3364
3365    try_combine will call this function to see if an insn can be split into
3366    two insns.  */
3367
3368 static rtx *
3369 find_split_point (rtx *loc, rtx insn)
3370 {
3371   rtx x = *loc;
3372   enum rtx_code code = GET_CODE (x);
3373   rtx *split;
3374   unsigned HOST_WIDE_INT len = 0;
3375   HOST_WIDE_INT pos = 0;
3376   int unsignedp = 0;
3377   rtx inner = NULL_RTX;
3378
3379   /* First special-case some codes.  */
3380   switch (code)
3381     {
3382     case SUBREG:
3383 #ifdef INSN_SCHEDULING
3384       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3385          point.  */
3386       if (MEM_P (SUBREG_REG (x)))
3387         return loc;
3388 #endif
3389       return find_split_point (&SUBREG_REG (x), insn);
3390
3391     case MEM:
3392 #ifdef HAVE_lo_sum
3393       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3394          using LO_SUM and HIGH.  */
3395       if (GET_CODE (XEXP (x, 0)) == CONST
3396           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3397         {
3398           SUBST (XEXP (x, 0),
3399                  gen_rtx_LO_SUM (Pmode,
3400                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3401                                  XEXP (x, 0)));
3402           return &XEXP (XEXP (x, 0), 0);
3403         }
3404 #endif
3405
3406       /* If we have a PLUS whose second operand is a constant and the
3407          address is not valid, perhaps will can split it up using
3408          the machine-specific way to split large constants.  We use
3409          the first pseudo-reg (one of the virtual regs) as a placeholder;
3410          it will not remain in the result.  */
3411       if (GET_CODE (XEXP (x, 0)) == PLUS
3412           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3413           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3414         {
3415           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3416           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3417                                  subst_insn);
3418
3419           /* This should have produced two insns, each of which sets our
3420              placeholder.  If the source of the second is a valid address,
3421              we can make put both sources together and make a split point
3422              in the middle.  */
3423
3424           if (seq
3425               && NEXT_INSN (seq) != NULL_RTX
3426               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3427               && NONJUMP_INSN_P (seq)
3428               && GET_CODE (PATTERN (seq)) == SET
3429               && SET_DEST (PATTERN (seq)) == reg
3430               && ! reg_mentioned_p (reg,
3431                                     SET_SRC (PATTERN (seq)))
3432               && NONJUMP_INSN_P (NEXT_INSN (seq))
3433               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3434               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3435               && memory_address_p (GET_MODE (x),
3436                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3437             {
3438               rtx src1 = SET_SRC (PATTERN (seq));
3439               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3440
3441               /* Replace the placeholder in SRC2 with SRC1.  If we can
3442                  find where in SRC2 it was placed, that can become our
3443                  split point and we can replace this address with SRC2.
3444                  Just try two obvious places.  */
3445
3446               src2 = replace_rtx (src2, reg, src1);
3447               split = 0;
3448               if (XEXP (src2, 0) == src1)
3449                 split = &XEXP (src2, 0);
3450               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3451                        && XEXP (XEXP (src2, 0), 0) == src1)
3452                 split = &XEXP (XEXP (src2, 0), 0);
3453
3454               if (split)
3455                 {
3456                   SUBST (XEXP (x, 0), src2);
3457                   return split;
3458                 }
3459             }
3460
3461           /* If that didn't work, perhaps the first operand is complex and
3462              needs to be computed separately, so make a split point there.
3463              This will occur on machines that just support REG + CONST
3464              and have a constant moved through some previous computation.  */
3465
3466           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3467                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3468                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3469             return &XEXP (XEXP (x, 0), 0);
3470         }
3471       break;
3472
3473     case SET:
3474 #ifdef HAVE_cc0
3475       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3476          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3477          we need to put the operand into a register.  So split at that
3478          point.  */
3479
3480       if (SET_DEST (x) == cc0_rtx
3481           && GET_CODE (SET_SRC (x)) != COMPARE
3482           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3483           && !OBJECT_P (SET_SRC (x))
3484           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3485                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3486         return &SET_SRC (x);
3487 #endif
3488
3489       /* See if we can split SET_SRC as it stands.  */
3490       split = find_split_point (&SET_SRC (x), insn);
3491       if (split && split != &SET_SRC (x))
3492         return split;
3493
3494       /* See if we can split SET_DEST as it stands.  */
3495       split = find_split_point (&SET_DEST (x), insn);
3496       if (split && split != &SET_DEST (x))
3497         return split;
3498
3499       /* See if this is a bitfield assignment with everything constant.  If
3500          so, this is an IOR of an AND, so split it into that.  */
3501       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3502           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3503               <= HOST_BITS_PER_WIDE_INT)
3504           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3505           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3506           && GET_CODE (SET_SRC (x)) == CONST_INT
3507           && ((INTVAL (XEXP (SET_DEST (x), 1))
3508                + INTVAL (XEXP (SET_DEST (x), 2)))
3509               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3510           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3511         {
3512           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3513           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3514           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3515           rtx dest = XEXP (SET_DEST (x), 0);
3516           enum machine_mode mode = GET_MODE (dest);
3517           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3518           rtx or_mask;
3519
3520           if (BITS_BIG_ENDIAN)
3521             pos = GET_MODE_BITSIZE (mode) - len - pos;
3522
3523           or_mask = gen_int_mode (src << pos, mode);
3524           if (src == mask)
3525             SUBST (SET_SRC (x),
3526                    simplify_gen_binary (IOR, mode, dest, or_mask));
3527           else
3528             {
3529               rtx negmask = gen_int_mode (~(mask << pos), mode);
3530               SUBST (SET_SRC (x),
3531                      simplify_gen_binary (IOR, mode,
3532                                           simplify_gen_binary (AND, mode,
3533                                                                dest, negmask),
3534                                           or_mask));
3535             }
3536
3537           SUBST (SET_DEST (x), dest);
3538
3539           split = find_split_point (&SET_SRC (x), insn);
3540           if (split && split != &SET_SRC (x))
3541             return split;
3542         }
3543
3544       /* Otherwise, see if this is an operation that we can split into two.
3545          If so, try to split that.  */
3546       code = GET_CODE (SET_SRC (x));
3547
3548       switch (code)
3549         {
3550         case AND:
3551           /* If we are AND'ing with a large constant that is only a single
3552              bit and the result is only being used in a context where we
3553              need to know if it is zero or nonzero, replace it with a bit
3554              extraction.  This will avoid the large constant, which might
3555              have taken more than one insn to make.  If the constant were
3556              not a valid argument to the AND but took only one insn to make,
3557              this is no worse, but if it took more than one insn, it will
3558              be better.  */
3559
3560           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3561               && REG_P (XEXP (SET_SRC (x), 0))
3562               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3563               && REG_P (SET_DEST (x))
3564               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3565               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3566               && XEXP (*split, 0) == SET_DEST (x)
3567               && XEXP (*split, 1) == const0_rtx)
3568             {
3569               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3570                                                 XEXP (SET_SRC (x), 0),
3571                                                 pos, NULL_RTX, 1, 1, 0, 0);
3572               if (extraction != 0)
3573                 {
3574                   SUBST (SET_SRC (x), extraction);
3575                   return find_split_point (loc, insn);
3576                 }
3577             }
3578           break;
3579
3580         case NE:
3581           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3582              is known to be on, this can be converted into a NEG of a shift.  */
3583           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3584               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3585               && 1 <= (pos = exact_log2
3586                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3587                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3588             {
3589               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3590
3591               SUBST (SET_SRC (x),
3592                      gen_rtx_NEG (mode,
3593                                   gen_rtx_LSHIFTRT (mode,
3594                                                     XEXP (SET_SRC (x), 0),
3595                                                     GEN_INT (pos))));
3596
3597               split = find_split_point (&SET_SRC (x), insn);
3598               if (split && split != &SET_SRC (x))
3599                 return split;
3600             }
3601           break;
3602
3603         case SIGN_EXTEND:
3604           inner = XEXP (SET_SRC (x), 0);
3605
3606           /* We can't optimize if either mode is a partial integer
3607              mode as we don't know how many bits are significant
3608              in those modes.  */
3609           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3610               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3611             break;
3612
3613           pos = 0;
3614           len = GET_MODE_BITSIZE (GET_MODE (inner));
3615           unsignedp = 0;
3616           break;
3617
3618         case SIGN_EXTRACT:
3619         case ZERO_EXTRACT:
3620           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3621               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3622             {
3623               inner = XEXP (SET_SRC (x), 0);
3624               len = INTVAL (XEXP (SET_SRC (x), 1));
3625               pos = INTVAL (XEXP (SET_SRC (x), 2));
3626
3627               if (BITS_BIG_ENDIAN)
3628                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3629               unsignedp = (code == ZERO_EXTRACT);
3630             }
3631           break;
3632
3633         default:
3634           break;
3635         }
3636
3637       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3638         {
3639           enum machine_mode mode = GET_MODE (SET_SRC (x));
3640
3641           /* For unsigned, we have a choice of a shift followed by an
3642              AND or two shifts.  Use two shifts for field sizes where the
3643              constant might be too large.  We assume here that we can
3644              always at least get 8-bit constants in an AND insn, which is
3645              true for every current RISC.  */
3646
3647           if (unsignedp && len <= 8)
3648             {
3649               SUBST (SET_SRC (x),
3650                      gen_rtx_AND (mode,
3651                                   gen_rtx_LSHIFTRT
3652                                   (mode, gen_lowpart (mode, inner),
3653                                    GEN_INT (pos)),
3654                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3655
3656               split = find_split_point (&SET_SRC (x), insn);
3657               if (split && split != &SET_SRC (x))
3658                 return split;
3659             }
3660           else
3661             {
3662               SUBST (SET_SRC (x),
3663                      gen_rtx_fmt_ee
3664                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3665                       gen_rtx_ASHIFT (mode,
3666                                       gen_lowpart (mode, inner),
3667                                       GEN_INT (GET_MODE_BITSIZE (mode)
3668                                                - len - pos)),
3669                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3670
3671               split = find_split_point (&SET_SRC (x), insn);
3672               if (split && split != &SET_SRC (x))
3673                 return split;
3674             }
3675         }
3676
3677       /* See if this is a simple operation with a constant as the second
3678          operand.  It might be that this constant is out of range and hence
3679          could be used as a split point.  */
3680       if (BINARY_P (SET_SRC (x))
3681           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3682           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3683               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3684                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3685         return &XEXP (SET_SRC (x), 1);
3686
3687       /* Finally, see if this is a simple operation with its first operand
3688          not in a register.  The operation might require this operand in a
3689          register, so return it as a split point.  We can always do this
3690          because if the first operand were another operation, we would have
3691          already found it as a split point.  */
3692       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3693           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3694         return &XEXP (SET_SRC (x), 0);
3695
3696       return 0;
3697
3698     case AND:
3699     case IOR:
3700       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3701          it is better to write this as (not (ior A B)) so we can split it.
3702          Similarly for IOR.  */
3703       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3704         {
3705           SUBST (*loc,
3706                  gen_rtx_NOT (GET_MODE (x),
3707                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3708                                               GET_MODE (x),
3709                                               XEXP (XEXP (x, 0), 0),
3710                                               XEXP (XEXP (x, 1), 0))));
3711           return find_split_point (loc, insn);
3712         }
3713
3714       /* Many RISC machines have a large set of logical insns.  If the
3715          second operand is a NOT, put it first so we will try to split the
3716          other operand first.  */
3717       if (GET_CODE (XEXP (x, 1)) == NOT)
3718         {
3719           rtx tem = XEXP (x, 0);
3720           SUBST (XEXP (x, 0), XEXP (x, 1));
3721           SUBST (XEXP (x, 1), tem);
3722         }
3723       break;
3724
3725     default:
3726       break;
3727     }
3728
3729   /* Otherwise, select our actions depending on our rtx class.  */
3730   switch (GET_RTX_CLASS (code))
3731     {
3732     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3733     case RTX_TERNARY:
3734       split = find_split_point (&XEXP (x, 2), insn);
3735       if (split)
3736         return split;
3737       /* ... fall through ...  */
3738     case RTX_BIN_ARITH:
3739     case RTX_COMM_ARITH:
3740     case RTX_COMPARE:
3741     case RTX_COMM_COMPARE:
3742       split = find_split_point (&XEXP (x, 1), insn);
3743       if (split)
3744         return split;
3745       /* ... fall through ...  */
3746     case RTX_UNARY:
3747       /* Some machines have (and (shift ...) ...) insns.  If X is not
3748          an AND, but XEXP (X, 0) is, use it as our split point.  */
3749       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3750         return &XEXP (x, 0);
3751
3752       split = find_split_point (&XEXP (x, 0), insn);
3753       if (split)
3754         return split;
3755       return loc;
3756
3757     default:
3758       /* Otherwise, we don't have a split point.  */
3759       return 0;
3760     }
3761 }
3762 \f
3763 /* Throughout X, replace FROM with TO, and return the result.
3764    The result is TO if X is FROM;
3765    otherwise the result is X, but its contents may have been modified.
3766    If they were modified, a record was made in undobuf so that
3767    undo_all will (among other things) return X to its original state.
3768
3769    If the number of changes necessary is too much to record to undo,
3770    the excess changes are not made, so the result is invalid.
3771    The changes already made can still be undone.
3772    undobuf.num_undo is incremented for such changes, so by testing that
3773    the caller can tell whether the result is valid.
3774
3775    `n_occurrences' is incremented each time FROM is replaced.
3776
3777    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3778
3779    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3780    by copying if `n_occurrences' is nonzero.  */
3781
3782 static rtx
3783 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3784 {
3785   enum rtx_code code = GET_CODE (x);
3786   enum machine_mode op0_mode = VOIDmode;
3787   const char *fmt;
3788   int len, i;
3789   rtx new;
3790
3791 /* Two expressions are equal if they are identical copies of a shared
3792    RTX or if they are both registers with the same register number
3793    and mode.  */
3794
3795 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3796   ((X) == (Y)                                           \
3797    || (REG_P (X) && REG_P (Y)   \
3798        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3799
3800   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3801     {
3802       n_occurrences++;
3803       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3804     }
3805
3806   /* If X and FROM are the same register but different modes, they will
3807      not have been seen as equal above.  However, flow.c will make a
3808      LOG_LINKS entry for that case.  If we do nothing, we will try to
3809      rerecognize our original insn and, when it succeeds, we will
3810      delete the feeding insn, which is incorrect.
3811
3812      So force this insn not to match in this (rare) case.  */
3813   if (! in_dest && code == REG && REG_P (from)
3814       && REGNO (x) == REGNO (from))
3815     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3816
3817   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3818      of which may contain things that can be combined.  */
3819   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3820     return x;
3821
3822   /* It is possible to have a subexpression appear twice in the insn.
3823      Suppose that FROM is a register that appears within TO.
3824      Then, after that subexpression has been scanned once by `subst',
3825      the second time it is scanned, TO may be found.  If we were
3826      to scan TO here, we would find FROM within it and create a
3827      self-referent rtl structure which is completely wrong.  */
3828   if (COMBINE_RTX_EQUAL_P (x, to))
3829     return to;
3830
3831   /* Parallel asm_operands need special attention because all of the
3832      inputs are shared across the arms.  Furthermore, unsharing the
3833      rtl results in recognition failures.  Failure to handle this case
3834      specially can result in circular rtl.
3835
3836      Solve this by doing a normal pass across the first entry of the
3837      parallel, and only processing the SET_DESTs of the subsequent
3838      entries.  Ug.  */
3839
3840   if (code == PARALLEL
3841       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3842       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3843     {
3844       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3845
3846       /* If this substitution failed, this whole thing fails.  */
3847       if (GET_CODE (new) == CLOBBER
3848           && XEXP (new, 0) == const0_rtx)
3849         return new;
3850
3851       SUBST (XVECEXP (x, 0, 0), new);
3852
3853       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3854         {
3855           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3856
3857           if (!REG_P (dest)
3858               && GET_CODE (dest) != CC0
3859               && GET_CODE (dest) != PC)
3860             {
3861               new = subst (dest, from, to, 0, unique_copy);
3862
3863               /* If this substitution failed, this whole thing fails.  */
3864               if (GET_CODE (new) == CLOBBER
3865                   && XEXP (new, 0) == const0_rtx)
3866                 return new;
3867
3868               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3869             }
3870         }
3871     }
3872   else
3873     {
3874       len = GET_RTX_LENGTH (code);
3875       fmt = GET_RTX_FORMAT (code);
3876
3877       /* We don't need to process a SET_DEST that is a register, CC0,
3878          or PC, so set up to skip this common case.  All other cases
3879          where we want to suppress replacing something inside a
3880          SET_SRC are handled via the IN_DEST operand.  */
3881       if (code == SET
3882           && (REG_P (SET_DEST (x))
3883               || GET_CODE (SET_DEST (x)) == CC0
3884               || GET_CODE (SET_DEST (x)) == PC))
3885         fmt = "ie";
3886
3887       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3888          constant.  */
3889       if (fmt[0] == 'e')
3890         op0_mode = GET_MODE (XEXP (x, 0));
3891
3892       for (i = 0; i < len; i++)
3893         {
3894           if (fmt[i] == 'E')
3895             {
3896               int j;
3897               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3898                 {
3899                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3900                     {
3901                       new = (unique_copy && n_occurrences
3902                              ? copy_rtx (to) : to);
3903                       n_occurrences++;
3904                     }
3905                   else
3906                     {
3907                       new = subst (XVECEXP (x, i, j), from, to, 0,
3908                                    unique_copy);
3909
3910                       /* If this substitution failed, this whole thing
3911                          fails.  */
3912                       if (GET_CODE (new) == CLOBBER
3913                           && XEXP (new, 0) == const0_rtx)
3914                         return new;
3915                     }
3916
3917                   SUBST (XVECEXP (x, i, j), new);
3918                 }
3919             }
3920           else if (fmt[i] == 'e')
3921             {
3922               /* If this is a register being set, ignore it.  */
3923               new = XEXP (x, i);
3924               if (in_dest
3925                   && i == 0
3926                   && (((code == SUBREG || code == ZERO_EXTRACT)
3927                        && REG_P (new))
3928                       || code == STRICT_LOW_PART))
3929                 ;
3930
3931               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3932                 {
3933                   /* In general, don't install a subreg involving two
3934                      modes not tieable.  It can worsen register
3935                      allocation, and can even make invalid reload
3936                      insns, since the reg inside may need to be copied
3937                      from in the outside mode, and that may be invalid
3938                      if it is an fp reg copied in integer mode.
3939
3940                      We allow two exceptions to this: It is valid if
3941                      it is inside another SUBREG and the mode of that
3942                      SUBREG and the mode of the inside of TO is
3943                      tieable and it is valid if X is a SET that copies
3944                      FROM to CC0.  */
3945
3946                   if (GET_CODE (to) == SUBREG
3947                       && ! MODES_TIEABLE_P (GET_MODE (to),
3948                                             GET_MODE (SUBREG_REG (to)))
3949                       && ! (code == SUBREG
3950                             && MODES_TIEABLE_P (GET_MODE (x),
3951                                                 GET_MODE (SUBREG_REG (to))))
3952 #ifdef HAVE_cc0
3953                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3954 #endif
3955                       )
3956                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3957
3958 #ifdef CANNOT_CHANGE_MODE_CLASS
3959                   if (code == SUBREG
3960                       && REG_P (to)
3961                       && REGNO (to) < FIRST_PSEUDO_REGISTER
3962                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3963                                                    GET_MODE (to),
3964                                                    GET_MODE (x)))
3965                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3966 #endif
3967
3968                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3969                   n_occurrences++;
3970                 }
3971               else
3972                 /* If we are in a SET_DEST, suppress most cases unless we
3973                    have gone inside a MEM, in which case we want to
3974                    simplify the address.  We assume here that things that
3975                    are actually part of the destination have their inner
3976                    parts in the first expression.  This is true for SUBREG,
3977                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3978                    things aside from REG and MEM that should appear in a
3979                    SET_DEST.  */
3980                 new = subst (XEXP (x, i), from, to,
3981                              (((in_dest
3982                                 && (code == SUBREG || code == STRICT_LOW_PART
3983                                     || code == ZERO_EXTRACT))
3984                                || code == SET)
3985                               && i == 0), unique_copy);
3986
3987               /* If we found that we will have to reject this combination,
3988                  indicate that by returning the CLOBBER ourselves, rather than
3989                  an expression containing it.  This will speed things up as
3990                  well as prevent accidents where two CLOBBERs are considered
3991                  to be equal, thus producing an incorrect simplification.  */
3992
3993               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3994                 return new;
3995
3996               if (GET_CODE (x) == SUBREG
3997                   && (GET_CODE (new) == CONST_INT
3998                       || GET_CODE (new) == CONST_DOUBLE))
3999                 {
4000                   enum machine_mode mode = GET_MODE (x);
4001
4002                   x = simplify_subreg (GET_MODE (x), new,
4003                                        GET_MODE (SUBREG_REG (x)),
4004                                        SUBREG_BYTE (x));
4005                   if (! x)
4006                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4007                 }
4008               else if (GET_CODE (new) == CONST_INT
4009                        && GET_CODE (x) == ZERO_EXTEND)
4010                 {
4011                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4012                                                 new, GET_MODE (XEXP (x, 0)));
4013                   gcc_assert (x);
4014                 }
4015               else
4016                 SUBST (XEXP (x, i), new);
4017             }
4018         }
4019     }
4020
4021   /* Try to simplify X.  If the simplification changed the code, it is likely
4022      that further simplification will help, so loop, but limit the number
4023      of repetitions that will be performed.  */
4024
4025   for (i = 0; i < 4; i++)
4026     {
4027       /* If X is sufficiently simple, don't bother trying to do anything
4028          with it.  */
4029       if (code != CONST_INT && code != REG && code != CLOBBER)
4030         x = combine_simplify_rtx (x, op0_mode, in_dest);
4031
4032       if (GET_CODE (x) == code)
4033         break;
4034
4035       code = GET_CODE (x);
4036
4037       /* We no longer know the original mode of operand 0 since we
4038          have changed the form of X)  */
4039       op0_mode = VOIDmode;
4040     }
4041
4042   return x;
4043 }
4044 \f
4045 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4046    outer level; call `subst' to simplify recursively.  Return the new
4047    expression.
4048
4049    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4050    if we are inside a SET_DEST.  */
4051
4052 static rtx
4053 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4054 {
4055   enum rtx_code code = GET_CODE (x);
4056   enum machine_mode mode = GET_MODE (x);
4057   rtx temp;
4058   int i;
4059
4060   /* If this is a commutative operation, put a constant last and a complex
4061      expression first.  We don't need to do this for comparisons here.  */
4062   if (COMMUTATIVE_ARITH_P (x)
4063       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4064     {
4065       temp = XEXP (x, 0);
4066       SUBST (XEXP (x, 0), XEXP (x, 1));
4067       SUBST (XEXP (x, 1), temp);
4068     }
4069
4070   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4071      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4072      things.  Check for cases where both arms are testing the same
4073      condition.
4074
4075      Don't do anything if all operands are very simple.  */
4076
4077   if ((BINARY_P (x)
4078        && ((!OBJECT_P (XEXP (x, 0))
4079             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4080                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4081            || (!OBJECT_P (XEXP (x, 1))
4082                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4083                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4084       || (UNARY_P (x)
4085           && (!OBJECT_P (XEXP (x, 0))
4086                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4087                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4088     {
4089       rtx cond, true_rtx, false_rtx;
4090
4091       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4092       if (cond != 0
4093           /* If everything is a comparison, what we have is highly unlikely
4094              to be simpler, so don't use it.  */
4095           && ! (COMPARISON_P (x)
4096                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4097         {
4098           rtx cop1 = const0_rtx;
4099           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4100
4101           if (cond_code == NE && COMPARISON_P (cond))
4102             return x;
4103
4104           /* Simplify the alternative arms; this may collapse the true and
4105              false arms to store-flag values.  Be careful to use copy_rtx
4106              here since true_rtx or false_rtx might share RTL with x as a
4107              result of the if_then_else_cond call above.  */
4108           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4109           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4110
4111           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4112              is unlikely to be simpler.  */
4113           if (general_operand (true_rtx, VOIDmode)
4114               && general_operand (false_rtx, VOIDmode))
4115             {
4116               enum rtx_code reversed;
4117
4118               /* Restarting if we generate a store-flag expression will cause
4119                  us to loop.  Just drop through in this case.  */
4120
4121               /* If the result values are STORE_FLAG_VALUE and zero, we can
4122                  just make the comparison operation.  */
4123               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4124                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4125                                              cond, cop1);
4126               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4127                        && ((reversed = reversed_comparison_code_parts
4128                                         (cond_code, cond, cop1, NULL))
4129                            != UNKNOWN))
4130                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4131                                              cond, cop1);
4132
4133               /* Likewise, we can make the negate of a comparison operation
4134                  if the result values are - STORE_FLAG_VALUE and zero.  */
4135               else if (GET_CODE (true_rtx) == CONST_INT
4136                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4137                        && false_rtx == const0_rtx)
4138                 x = simplify_gen_unary (NEG, mode,
4139                                         simplify_gen_relational (cond_code,
4140                                                                  mode, VOIDmode,
4141                                                                  cond, cop1),
4142                                         mode);
4143               else if (GET_CODE (false_rtx) == CONST_INT
4144                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4145                        && true_rtx == const0_rtx
4146                        && ((reversed = reversed_comparison_code_parts
4147                                         (cond_code, cond, cop1, NULL))
4148                            != UNKNOWN))
4149                 x = simplify_gen_unary (NEG, mode,
4150                                         simplify_gen_relational (reversed,
4151                                                                  mode, VOIDmode,
4152                                                                  cond, cop1),
4153                                         mode);
4154               else
4155                 return gen_rtx_IF_THEN_ELSE (mode,
4156                                              simplify_gen_relational (cond_code,
4157                                                                       mode,
4158                                                                       VOIDmode,
4159                                                                       cond,
4160                                                                       cop1),
4161                                              true_rtx, false_rtx);
4162
4163               code = GET_CODE (x);
4164               op0_mode = VOIDmode;
4165             }
4166         }
4167     }
4168
4169   /* Try to fold this expression in case we have constants that weren't
4170      present before.  */
4171   temp = 0;
4172   switch (GET_RTX_CLASS (code))
4173     {
4174     case RTX_UNARY:
4175       if (op0_mode == VOIDmode)
4176         op0_mode = GET_MODE (XEXP (x, 0));
4177       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4178       break;
4179     case RTX_COMPARE:
4180     case RTX_COMM_COMPARE:
4181       {
4182         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4183         if (cmp_mode == VOIDmode)
4184           {
4185             cmp_mode = GET_MODE (XEXP (x, 1));
4186             if (cmp_mode == VOIDmode)
4187               cmp_mode = op0_mode;
4188           }
4189         temp = simplify_relational_operation (code, mode, cmp_mode,
4190                                               XEXP (x, 0), XEXP (x, 1));
4191       }
4192       break;
4193     case RTX_COMM_ARITH:
4194     case RTX_BIN_ARITH:
4195       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4196       break;
4197     case RTX_BITFIELD_OPS:
4198     case RTX_TERNARY:
4199       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4200                                          XEXP (x, 1), XEXP (x, 2));
4201       break;
4202     default:
4203       break;
4204     }
4205
4206   if (temp)
4207     {
4208       x = temp;
4209       code = GET_CODE (temp);
4210       op0_mode = VOIDmode;
4211       mode = GET_MODE (temp);
4212     }
4213
4214   /* First see if we can apply the inverse distributive law.  */
4215   if (code == PLUS || code == MINUS
4216       || code == AND || code == IOR || code == XOR)
4217     {
4218       x = apply_distributive_law (x);
4219       code = GET_CODE (x);
4220       op0_mode = VOIDmode;
4221     }
4222
4223   /* If CODE is an associative operation not otherwise handled, see if we
4224      can associate some operands.  This can win if they are constants or
4225      if they are logically related (i.e. (a & b) & a).  */
4226   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4227        || code == AND || code == IOR || code == XOR
4228        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4229       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4230           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4231     {
4232       if (GET_CODE (XEXP (x, 0)) == code)
4233         {
4234           rtx other = XEXP (XEXP (x, 0), 0);
4235           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4236           rtx inner_op1 = XEXP (x, 1);
4237           rtx inner;
4238
4239           /* Make sure we pass the constant operand if any as the second
4240              one if this is a commutative operation.  */
4241           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4242             {
4243               rtx tem = inner_op0;
4244               inner_op0 = inner_op1;
4245               inner_op1 = tem;
4246             }
4247           inner = simplify_binary_operation (code == MINUS ? PLUS
4248                                              : code == DIV ? MULT
4249                                              : code,
4250                                              mode, inner_op0, inner_op1);
4251
4252           /* For commutative operations, try the other pair if that one
4253              didn't simplify.  */
4254           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4255             {
4256               other = XEXP (XEXP (x, 0), 1);
4257               inner = simplify_binary_operation (code, mode,
4258                                                  XEXP (XEXP (x, 0), 0),
4259                                                  XEXP (x, 1));
4260             }
4261
4262           if (inner)
4263             return simplify_gen_binary (code, mode, other, inner);
4264         }
4265     }
4266
4267   /* A little bit of algebraic simplification here.  */
4268   switch (code)
4269     {
4270     case MEM:
4271       /* Ensure that our address has any ASHIFTs converted to MULT in case
4272          address-recognizing predicates are called later.  */
4273       temp = make_compound_operation (XEXP (x, 0), MEM);
4274       SUBST (XEXP (x, 0), temp);
4275       break;
4276
4277     case SUBREG:
4278       if (op0_mode == VOIDmode)
4279         op0_mode = GET_MODE (SUBREG_REG (x));
4280
4281       /* See if this can be moved to simplify_subreg.  */
4282       if (CONSTANT_P (SUBREG_REG (x))
4283           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4284              /* Don't call gen_lowpart if the inner mode
4285                 is VOIDmode and we cannot simplify it, as SUBREG without
4286                 inner mode is invalid.  */
4287           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4288               || gen_lowpart_common (mode, SUBREG_REG (x))))
4289         return gen_lowpart (mode, SUBREG_REG (x));
4290
4291       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4292         break;
4293       {
4294         rtx temp;
4295         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4296                                 SUBREG_BYTE (x));
4297         if (temp)
4298           return temp;
4299       }
4300
4301       /* Don't change the mode of the MEM if that would change the meaning
4302          of the address.  */
4303       if (MEM_P (SUBREG_REG (x))
4304           && (MEM_VOLATILE_P (SUBREG_REG (x))
4305               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4306         return gen_rtx_CLOBBER (mode, const0_rtx);
4307
4308       /* Note that we cannot do any narrowing for non-constants since
4309          we might have been counting on using the fact that some bits were
4310          zero.  We now do this in the SET.  */
4311
4312       break;
4313
4314     case NEG:
4315       temp = expand_compound_operation (XEXP (x, 0));
4316
4317       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4318          replaced by (lshiftrt X C).  This will convert
4319          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4320
4321       if (GET_CODE (temp) == ASHIFTRT
4322           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4323           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4324         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4325                                      INTVAL (XEXP (temp, 1)));
4326
4327       /* If X has only a single bit that might be nonzero, say, bit I, convert
4328          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4329          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4330          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4331          or a SUBREG of one since we'd be making the expression more
4332          complex if it was just a register.  */
4333
4334       if (!REG_P (temp)
4335           && ! (GET_CODE (temp) == SUBREG
4336                 && REG_P (SUBREG_REG (temp)))
4337           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4338         {
4339           rtx temp1 = simplify_shift_const
4340             (NULL_RTX, ASHIFTRT, mode,
4341              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4342                                    GET_MODE_BITSIZE (mode) - 1 - i),
4343              GET_MODE_BITSIZE (mode) - 1 - i);
4344
4345           /* If all we did was surround TEMP with the two shifts, we
4346              haven't improved anything, so don't use it.  Otherwise,
4347              we are better off with TEMP1.  */
4348           if (GET_CODE (temp1) != ASHIFTRT
4349               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4350               || XEXP (XEXP (temp1, 0), 0) != temp)
4351             return temp1;
4352         }
4353       break;
4354
4355     case TRUNCATE:
4356       /* We can't handle truncation to a partial integer mode here
4357          because we don't know the real bitsize of the partial
4358          integer mode.  */
4359       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4360         break;
4361
4362       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4363           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4364                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4365         SUBST (XEXP (x, 0),
4366                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4367                               GET_MODE_MASK (mode), 0));
4368
4369       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4370          whose value is a comparison can be replaced with a subreg if
4371          STORE_FLAG_VALUE permits.  */
4372       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4373           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4374           && (temp = get_last_value (XEXP (x, 0)))
4375           && COMPARISON_P (temp))
4376         return gen_lowpart (mode, XEXP (x, 0));
4377       break;
4378
4379 #ifdef HAVE_cc0
4380     case COMPARE:
4381       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4382          using cc0, in which case we want to leave it as a COMPARE
4383          so we can distinguish it from a register-register-copy.  */
4384       if (XEXP (x, 1) == const0_rtx)
4385         return XEXP (x, 0);
4386
4387       /* x - 0 is the same as x unless x's mode has signed zeros and
4388          allows rounding towards -infinity.  Under those conditions,
4389          0 - 0 is -0.  */
4390       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4391             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4392           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4393         return XEXP (x, 0);
4394       break;
4395 #endif
4396
4397     case CONST:
4398       /* (const (const X)) can become (const X).  Do it this way rather than
4399          returning the inner CONST since CONST can be shared with a
4400          REG_EQUAL note.  */
4401       if (GET_CODE (XEXP (x, 0)) == CONST)
4402         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4403       break;
4404
4405 #ifdef HAVE_lo_sum
4406     case LO_SUM:
4407       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4408          can add in an offset.  find_split_point will split this address up
4409          again if it doesn't match.  */
4410       if (GET_CODE (XEXP (x, 0)) == HIGH
4411           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4412         return XEXP (x, 1);
4413       break;
4414 #endif
4415
4416     case PLUS:
4417       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4418          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4419          bit-field and can be replaced by either a sign_extend or a
4420          sign_extract.  The `and' may be a zero_extend and the two
4421          <c>, -<c> constants may be reversed.  */
4422       if (GET_CODE (XEXP (x, 0)) == XOR
4423           && GET_CODE (XEXP (x, 1)) == CONST_INT
4424           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4425           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4426           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4427               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4428           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4429           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4430                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4431                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4432                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4433               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4434                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4435                       == (unsigned int) i + 1))))
4436         return simplify_shift_const
4437           (NULL_RTX, ASHIFTRT, mode,
4438            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4439                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4440                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4441            GET_MODE_BITSIZE (mode) - (i + 1));
4442
4443       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4444          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4445          the bitsize of the mode - 1.  This allows simplification of
4446          "a = (b & 8) == 0;"  */
4447       if (XEXP (x, 1) == constm1_rtx
4448           && !REG_P (XEXP (x, 0))
4449           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4450                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4451           && nonzero_bits (XEXP (x, 0), mode) == 1)
4452         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4453            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4454                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4455                                  GET_MODE_BITSIZE (mode) - 1),
4456            GET_MODE_BITSIZE (mode) - 1);
4457
4458       /* If we are adding two things that have no bits in common, convert
4459          the addition into an IOR.  This will often be further simplified,
4460          for example in cases like ((a & 1) + (a & 2)), which can
4461          become a & 3.  */
4462
4463       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4464           && (nonzero_bits (XEXP (x, 0), mode)
4465               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4466         {
4467           /* Try to simplify the expression further.  */
4468           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4469           temp = combine_simplify_rtx (tor, mode, in_dest);
4470
4471           /* If we could, great.  If not, do not go ahead with the IOR
4472              replacement, since PLUS appears in many special purpose
4473              address arithmetic instructions.  */
4474           if (GET_CODE (temp) != CLOBBER && temp != tor)
4475             return temp;
4476         }
4477       break;
4478
4479     case MINUS:
4480       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4481          (and <foo> (const_int pow2-1))  */
4482       if (GET_CODE (XEXP (x, 1)) == AND
4483           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4484           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4485           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4486         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4487                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4488       break;
4489
4490     case MULT:
4491       /* If we have (mult (plus A B) C), apply the distributive law and then
4492          the inverse distributive law to see if things simplify.  This
4493          occurs mostly in addresses, often when unrolling loops.  */
4494
4495       if (GET_CODE (XEXP (x, 0)) == PLUS)
4496         {
4497           rtx result = distribute_and_simplify_rtx (x, 0);
4498           if (result)
4499             return result;
4500         }
4501
4502       /* Try simplify a*(b/c) as (a*b)/c.  */
4503       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4504           && GET_CODE (XEXP (x, 0)) == DIV)
4505         {
4506           rtx tem = simplify_binary_operation (MULT, mode,
4507                                                XEXP (XEXP (x, 0), 0),
4508                                                XEXP (x, 1));
4509           if (tem)
4510             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4511         }
4512       break;
4513
4514     case UDIV:
4515       /* If this is a divide by a power of two, treat it as a shift if
4516          its first operand is a shift.  */
4517       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4518           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4519           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4520               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4521               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4522               || GET_CODE (XEXP (x, 0)) == ROTATE
4523               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4524         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4525       break;
4526
4527     case EQ:  case NE:
4528     case GT:  case GTU:  case GE:  case GEU:
4529     case LT:  case LTU:  case LE:  case LEU:
4530     case UNEQ:  case LTGT:
4531     case UNGT:  case UNGE:
4532     case UNLT:  case UNLE:
4533     case UNORDERED: case ORDERED:
4534       /* If the first operand is a condition code, we can't do anything
4535          with it.  */
4536       if (GET_CODE (XEXP (x, 0)) == COMPARE
4537           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4538               && ! CC0_P (XEXP (x, 0))))
4539         {
4540           rtx op0 = XEXP (x, 0);
4541           rtx op1 = XEXP (x, 1);
4542           enum rtx_code new_code;
4543
4544           if (GET_CODE (op0) == COMPARE)
4545             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4546
4547           /* Simplify our comparison, if possible.  */
4548           new_code = simplify_comparison (code, &op0, &op1);
4549
4550           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4551              if only the low-order bit is possibly nonzero in X (such as when
4552              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4553              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4554              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4555              (plus X 1).
4556
4557              Remove any ZERO_EXTRACT we made when thinking this was a
4558              comparison.  It may now be simpler to use, e.g., an AND.  If a
4559              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4560              the call to make_compound_operation in the SET case.  */
4561
4562           if (STORE_FLAG_VALUE == 1
4563               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4564               && op1 == const0_rtx
4565               && mode == GET_MODE (op0)
4566               && nonzero_bits (op0, mode) == 1)
4567             return gen_lowpart (mode,
4568                                 expand_compound_operation (op0));
4569
4570           else if (STORE_FLAG_VALUE == 1
4571                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4572                    && op1 == const0_rtx
4573                    && mode == GET_MODE (op0)
4574                    && (num_sign_bit_copies (op0, mode)
4575                        == GET_MODE_BITSIZE (mode)))
4576             {
4577               op0 = expand_compound_operation (op0);
4578               return simplify_gen_unary (NEG, mode,
4579                                          gen_lowpart (mode, op0),
4580                                          mode);
4581             }
4582
4583           else if (STORE_FLAG_VALUE == 1
4584                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4585                    && op1 == const0_rtx
4586                    && mode == GET_MODE (op0)
4587                    && nonzero_bits (op0, mode) == 1)
4588             {
4589               op0 = expand_compound_operation (op0);
4590               return simplify_gen_binary (XOR, mode,
4591                                           gen_lowpart (mode, op0),
4592                                           const1_rtx);
4593             }
4594
4595           else if (STORE_FLAG_VALUE == 1
4596                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4597                    && op1 == const0_rtx
4598                    && mode == GET_MODE (op0)
4599                    && (num_sign_bit_copies (op0, mode)
4600                        == GET_MODE_BITSIZE (mode)))
4601             {
4602               op0 = expand_compound_operation (op0);
4603               return plus_constant (gen_lowpart (mode, op0), 1);
4604             }
4605
4606           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4607              those above.  */
4608           if (STORE_FLAG_VALUE == -1
4609               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4610               && op1 == const0_rtx
4611               && (num_sign_bit_copies (op0, mode)
4612                   == GET_MODE_BITSIZE (mode)))
4613             return gen_lowpart (mode,
4614                                 expand_compound_operation (op0));
4615
4616           else if (STORE_FLAG_VALUE == -1
4617                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4618                    && op1 == const0_rtx
4619                    && mode == GET_MODE (op0)
4620                    && nonzero_bits (op0, mode) == 1)
4621             {
4622               op0 = expand_compound_operation (op0);
4623               return simplify_gen_unary (NEG, mode,
4624                                          gen_lowpart (mode, op0),
4625                                          mode);
4626             }
4627
4628           else if (STORE_FLAG_VALUE == -1
4629                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4630                    && op1 == const0_rtx
4631                    && mode == GET_MODE (op0)
4632                    && (num_sign_bit_copies (op0, mode)
4633                        == GET_MODE_BITSIZE (mode)))
4634             {
4635               op0 = expand_compound_operation (op0);
4636               return simplify_gen_unary (NOT, mode,
4637                                          gen_lowpart (mode, op0),
4638                                          mode);
4639             }
4640
4641           /* If X is 0/1, (eq X 0) is X-1.  */
4642           else if (STORE_FLAG_VALUE == -1
4643                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4644                    && op1 == const0_rtx
4645                    && mode == GET_MODE (op0)
4646                    && nonzero_bits (op0, mode) == 1)
4647             {
4648               op0 = expand_compound_operation (op0);
4649               return plus_constant (gen_lowpart (mode, op0), -1);
4650             }
4651
4652           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4653              one bit that might be nonzero, we can convert (ne x 0) to
4654              (ashift x c) where C puts the bit in the sign bit.  Remove any
4655              AND with STORE_FLAG_VALUE when we are done, since we are only
4656              going to test the sign bit.  */
4657           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4658               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4659               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4660                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4661               && op1 == const0_rtx
4662               && mode == GET_MODE (op0)
4663               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4664             {
4665               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4666                                         expand_compound_operation (op0),
4667                                         GET_MODE_BITSIZE (mode) - 1 - i);
4668               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4669                 return XEXP (x, 0);
4670               else
4671                 return x;
4672             }
4673
4674           /* If the code changed, return a whole new comparison.  */
4675           if (new_code != code)
4676             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4677
4678           /* Otherwise, keep this operation, but maybe change its operands.
4679              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4680           SUBST (XEXP (x, 0), op0);
4681           SUBST (XEXP (x, 1), op1);
4682         }
4683       break;
4684
4685     case IF_THEN_ELSE:
4686       return simplify_if_then_else (x);
4687
4688     case ZERO_EXTRACT:
4689     case SIGN_EXTRACT:
4690     case ZERO_EXTEND:
4691     case SIGN_EXTEND:
4692       /* If we are processing SET_DEST, we are done.  */
4693       if (in_dest)
4694         return x;
4695
4696       return expand_compound_operation (x);
4697
4698     case SET:
4699       return simplify_set (x);
4700
4701     case AND:
4702     case IOR:
4703       return simplify_logical (x);
4704
4705     case ASHIFT:
4706     case LSHIFTRT:
4707     case ASHIFTRT:
4708     case ROTATE:
4709     case ROTATERT:
4710       /* If this is a shift by a constant amount, simplify it.  */
4711       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4712         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4713                                      INTVAL (XEXP (x, 1)));
4714
4715       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4716         SUBST (XEXP (x, 1),
4717                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4718                               ((HOST_WIDE_INT) 1
4719                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4720                               - 1,
4721                               0));
4722       break;
4723
4724     default:
4725       break;
4726     }
4727
4728   return x;
4729 }
4730 \f
4731 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4732
4733 static rtx
4734 simplify_if_then_else (rtx x)
4735 {
4736   enum machine_mode mode = GET_MODE (x);
4737   rtx cond = XEXP (x, 0);
4738   rtx true_rtx = XEXP (x, 1);
4739   rtx false_rtx = XEXP (x, 2);
4740   enum rtx_code true_code = GET_CODE (cond);
4741   int comparison_p = COMPARISON_P (cond);
4742   rtx temp;
4743   int i;
4744   enum rtx_code false_code;
4745   rtx reversed;
4746
4747   /* Simplify storing of the truth value.  */
4748   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4749     return simplify_gen_relational (true_code, mode, VOIDmode,
4750                                     XEXP (cond, 0), XEXP (cond, 1));
4751
4752   /* Also when the truth value has to be reversed.  */
4753   if (comparison_p
4754       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4755       && (reversed = reversed_comparison (cond, mode)))
4756     return reversed;
4757
4758   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4759      in it is being compared against certain values.  Get the true and false
4760      comparisons and see if that says anything about the value of each arm.  */
4761
4762   if (comparison_p
4763       && ((false_code = reversed_comparison_code (cond, NULL))
4764           != UNKNOWN)
4765       && REG_P (XEXP (cond, 0)))
4766     {
4767       HOST_WIDE_INT nzb;
4768       rtx from = XEXP (cond, 0);
4769       rtx true_val = XEXP (cond, 1);
4770       rtx false_val = true_val;
4771       int swapped = 0;
4772
4773       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4774
4775       if (false_code == EQ)
4776         {
4777           swapped = 1, true_code = EQ, false_code = NE;
4778           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4779         }
4780
4781       /* If we are comparing against zero and the expression being tested has
4782          only a single bit that might be nonzero, that is its value when it is
4783          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4784
4785       if (true_code == EQ && true_val == const0_rtx
4786           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4787         false_code = EQ, false_val = GEN_INT (nzb);
4788       else if (true_code == EQ && true_val == const0_rtx
4789                && (num_sign_bit_copies (from, GET_MODE (from))
4790                    == GET_MODE_BITSIZE (GET_MODE (from))))
4791         false_code = EQ, false_val = constm1_rtx;
4792
4793       /* Now simplify an arm if we know the value of the register in the
4794          branch and it is used in the arm.  Be careful due to the potential
4795          of locally-shared RTL.  */
4796
4797       if (reg_mentioned_p (from, true_rtx))
4798         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4799                                       from, true_val),
4800                       pc_rtx, pc_rtx, 0, 0);
4801       if (reg_mentioned_p (from, false_rtx))
4802         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4803                                    from, false_val),
4804                        pc_rtx, pc_rtx, 0, 0);
4805
4806       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4807       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4808
4809       true_rtx = XEXP (x, 1);
4810       false_rtx = XEXP (x, 2);
4811       true_code = GET_CODE (cond);
4812     }
4813
4814   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4815      reversed, do so to avoid needing two sets of patterns for
4816      subtract-and-branch insns.  Similarly if we have a constant in the true
4817      arm, the false arm is the same as the first operand of the comparison, or
4818      the false arm is more complicated than the true arm.  */
4819
4820   if (comparison_p
4821       && reversed_comparison_code (cond, NULL) != UNKNOWN
4822       && (true_rtx == pc_rtx
4823           || (CONSTANT_P (true_rtx)
4824               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4825           || true_rtx == const0_rtx
4826           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4827           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4828               && !OBJECT_P (false_rtx))
4829           || reg_mentioned_p (true_rtx, false_rtx)
4830           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4831     {
4832       true_code = reversed_comparison_code (cond, NULL);
4833       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4834       SUBST (XEXP (x, 1), false_rtx);
4835       SUBST (XEXP (x, 2), true_rtx);
4836
4837       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4838       cond = XEXP (x, 0);
4839
4840       /* It is possible that the conditional has been simplified out.  */
4841       true_code = GET_CODE (cond);
4842       comparison_p = COMPARISON_P (cond);
4843     }
4844
4845   /* If the two arms are identical, we don't need the comparison.  */
4846
4847   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4848     return true_rtx;
4849
4850   /* Convert a == b ? b : a to "a".  */
4851   if (true_code == EQ && ! side_effects_p (cond)
4852       && !HONOR_NANS (mode)
4853       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4854       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4855     return false_rtx;
4856   else if (true_code == NE && ! side_effects_p (cond)
4857            && !HONOR_NANS (mode)
4858            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4859            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4860     return true_rtx;
4861
4862   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4863
4864   if (GET_MODE_CLASS (mode) == MODE_INT
4865       && GET_CODE (false_rtx) == NEG
4866       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4867       && comparison_p
4868       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4869       && ! side_effects_p (true_rtx))
4870     switch (true_code)
4871       {
4872       case GT:
4873       case GE:
4874         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4875       case LT:
4876       case LE:
4877         return
4878           simplify_gen_unary (NEG, mode,
4879                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4880                               mode);
4881       default:
4882         break;
4883       }
4884
4885   /* Look for MIN or MAX.  */
4886
4887   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4888       && comparison_p
4889       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4890       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4891       && ! side_effects_p (cond))
4892     switch (true_code)
4893       {
4894       case GE:
4895       case GT:
4896         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4897       case LE:
4898       case LT:
4899         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4900       case GEU:
4901       case GTU:
4902         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4903       case LEU:
4904       case LTU:
4905         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4906       default:
4907         break;
4908       }
4909
4910   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4911      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4912      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4913      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4914      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4915      neither 1 or -1, but it isn't worth checking for.  */
4916
4917   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4918       && comparison_p
4919       && GET_MODE_CLASS (mode) == MODE_INT
4920       && ! side_effects_p (x))
4921     {
4922       rtx t = make_compound_operation (true_rtx, SET);
4923       rtx f = make_compound_operation (false_rtx, SET);
4924       rtx cond_op0 = XEXP (cond, 0);
4925       rtx cond_op1 = XEXP (cond, 1);
4926       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4927       enum machine_mode m = mode;
4928       rtx z = 0, c1 = NULL_RTX;
4929
4930       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4931            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4932            || GET_CODE (t) == ASHIFT
4933            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4934           && rtx_equal_p (XEXP (t, 0), f))
4935         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4936
4937       /* If an identity-zero op is commutative, check whether there
4938          would be a match if we swapped the operands.  */
4939       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4940                 || GET_CODE (t) == XOR)
4941                && rtx_equal_p (XEXP (t, 1), f))
4942         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4943       else if (GET_CODE (t) == SIGN_EXTEND
4944                && (GET_CODE (XEXP (t, 0)) == PLUS
4945                    || GET_CODE (XEXP (t, 0)) == MINUS
4946                    || GET_CODE (XEXP (t, 0)) == IOR
4947                    || GET_CODE (XEXP (t, 0)) == XOR
4948                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4949                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4950                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4951                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4952                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4953                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4954                && (num_sign_bit_copies (f, GET_MODE (f))
4955                    > (unsigned int)
4956                      (GET_MODE_BITSIZE (mode)
4957                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4958         {
4959           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4960           extend_op = SIGN_EXTEND;
4961           m = GET_MODE (XEXP (t, 0));
4962         }
4963       else if (GET_CODE (t) == SIGN_EXTEND
4964                && (GET_CODE (XEXP (t, 0)) == PLUS
4965                    || GET_CODE (XEXP (t, 0)) == IOR
4966                    || GET_CODE (XEXP (t, 0)) == XOR)
4967                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4968                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4969                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4970                && (num_sign_bit_copies (f, GET_MODE (f))
4971                    > (unsigned int)
4972                      (GET_MODE_BITSIZE (mode)
4973                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4974         {
4975           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4976           extend_op = SIGN_EXTEND;
4977           m = GET_MODE (XEXP (t, 0));
4978         }
4979       else if (GET_CODE (t) == ZERO_EXTEND
4980                && (GET_CODE (XEXP (t, 0)) == PLUS
4981                    || GET_CODE (XEXP (t, 0)) == MINUS
4982                    || GET_CODE (XEXP (t, 0)) == IOR
4983                    || GET_CODE (XEXP (t, 0)) == XOR
4984                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4985                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4986                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4987                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4988                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4989                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4990                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4991                && ((nonzero_bits (f, GET_MODE (f))
4992                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4993                    == 0))
4994         {
4995           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4996           extend_op = ZERO_EXTEND;
4997           m = GET_MODE (XEXP (t, 0));
4998         }
4999       else if (GET_CODE (t) == ZERO_EXTEND
5000                && (GET_CODE (XEXP (t, 0)) == PLUS
5001                    || GET_CODE (XEXP (t, 0)) == IOR
5002                    || GET_CODE (XEXP (t, 0)) == XOR)
5003                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5004                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5005                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5006                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5007                && ((nonzero_bits (f, GET_MODE (f))
5008                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5009                    == 0))
5010         {
5011           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5012           extend_op = ZERO_EXTEND;
5013           m = GET_MODE (XEXP (t, 0));
5014         }
5015
5016       if (z)
5017         {
5018           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5019                                                  cond_op0, cond_op1),
5020                         pc_rtx, pc_rtx, 0, 0);
5021           temp = simplify_gen_binary (MULT, m, temp,
5022                                       simplify_gen_binary (MULT, m, c1,
5023                                                            const_true_rtx));
5024           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5025           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5026
5027           if (extend_op != UNKNOWN)
5028             temp = simplify_gen_unary (extend_op, mode, temp, m);
5029
5030           return temp;
5031         }
5032     }
5033
5034   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5035      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5036      negation of a single bit, we can convert this operation to a shift.  We
5037      can actually do this more generally, but it doesn't seem worth it.  */
5038
5039   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5040       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5041       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5042            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5043           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5044                == GET_MODE_BITSIZE (mode))
5045               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5046     return
5047       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5048                             gen_lowpart (mode, XEXP (cond, 0)), i);
5049
5050   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5051   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5052       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5053       && GET_MODE (XEXP (cond, 0)) == mode
5054       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5055           == nonzero_bits (XEXP (cond, 0), mode)
5056       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5057     return XEXP (cond, 0);
5058
5059   return x;
5060 }
5061 \f
5062 /* Simplify X, a SET expression.  Return the new expression.  */
5063
5064 static rtx
5065 simplify_set (rtx x)
5066 {
5067   rtx src = SET_SRC (x);
5068   rtx dest = SET_DEST (x);
5069   enum machine_mode mode
5070     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5071   rtx other_insn;
5072   rtx *cc_use;
5073
5074   /* (set (pc) (return)) gets written as (return).  */
5075   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5076     return src;
5077
5078   /* Now that we know for sure which bits of SRC we are using, see if we can
5079      simplify the expression for the object knowing that we only need the
5080      low-order bits.  */
5081
5082   if (GET_MODE_CLASS (mode) == MODE_INT
5083       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5084     {
5085       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5086       SUBST (SET_SRC (x), src);
5087     }
5088
5089   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5090      the comparison result and try to simplify it unless we already have used
5091      undobuf.other_insn.  */
5092   if ((GET_MODE_CLASS (mode) == MODE_CC
5093        || GET_CODE (src) == COMPARE
5094        || CC0_P (dest))
5095       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5096       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5097       && COMPARISON_P (*cc_use)
5098       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5099     {
5100       enum rtx_code old_code = GET_CODE (*cc_use);
5101       enum rtx_code new_code;
5102       rtx op0, op1, tmp;
5103       int other_changed = 0;
5104       enum machine_mode compare_mode = GET_MODE (dest);
5105
5106       if (GET_CODE (src) == COMPARE)
5107         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5108       else
5109         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5110
5111       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5112                                            op0, op1);
5113       if (!tmp)
5114         new_code = old_code;
5115       else if (!CONSTANT_P (tmp))
5116         {
5117           new_code = GET_CODE (tmp);
5118           op0 = XEXP (tmp, 0);
5119           op1 = XEXP (tmp, 1);
5120         }
5121       else
5122         {
5123           rtx pat = PATTERN (other_insn);
5124           undobuf.other_insn = other_insn;
5125           SUBST (*cc_use, tmp);
5126
5127           /* Attempt to simplify CC user.  */
5128           if (GET_CODE (pat) == SET)
5129             {
5130               rtx new = simplify_rtx (SET_SRC (pat));
5131               if (new != NULL_RTX)
5132                 SUBST (SET_SRC (pat), new);
5133             }
5134
5135           /* Convert X into a no-op move.  */
5136           SUBST (SET_DEST (x), pc_rtx);
5137           SUBST (SET_SRC (x), pc_rtx);
5138           return x;
5139         }
5140
5141       /* Simplify our comparison, if possible.  */
5142       new_code = simplify_comparison (new_code, &op0, &op1);
5143
5144 #ifdef SELECT_CC_MODE
5145       /* If this machine has CC modes other than CCmode, check to see if we
5146          need to use a different CC mode here.  */
5147       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5148         compare_mode = GET_MODE (op0);
5149       else
5150         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5151
5152 #ifndef HAVE_cc0
5153       /* If the mode changed, we have to change SET_DEST, the mode in the
5154          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5155          a hard register, just build new versions with the proper mode.  If it
5156          is a pseudo, we lose unless it is only time we set the pseudo, in
5157          which case we can safely change its mode.  */
5158       if (compare_mode != GET_MODE (dest))
5159         {
5160           if (can_change_dest_mode (dest, 0, compare_mode))
5161             {
5162               unsigned int regno = REGNO (dest);
5163               rtx new_dest = gen_rtx_REG (compare_mode, regno);
5164
5165               if (regno >= FIRST_PSEUDO_REGISTER)
5166                 SUBST (regno_reg_rtx[regno], new_dest);
5167
5168               SUBST (SET_DEST (x), new_dest);
5169               SUBST (XEXP (*cc_use, 0), new_dest);
5170               other_changed = 1;
5171
5172               dest = new_dest;
5173             }
5174         }
5175 #endif  /* cc0 */
5176 #endif  /* SELECT_CC_MODE */
5177
5178       /* If the code changed, we have to build a new comparison in
5179          undobuf.other_insn.  */
5180       if (new_code != old_code)
5181         {
5182           int other_changed_previously = other_changed;
5183           unsigned HOST_WIDE_INT mask;
5184
5185           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5186                                           dest, const0_rtx));
5187           other_changed = 1;
5188
5189           /* If the only change we made was to change an EQ into an NE or
5190              vice versa, OP0 has only one bit that might be nonzero, and OP1
5191              is zero, check if changing the user of the condition code will
5192              produce a valid insn.  If it won't, we can keep the original code
5193              in that insn by surrounding our operation with an XOR.  */
5194
5195           if (((old_code == NE && new_code == EQ)
5196                || (old_code == EQ && new_code == NE))
5197               && ! other_changed_previously && op1 == const0_rtx
5198               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5199               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5200             {
5201               rtx pat = PATTERN (other_insn), note = 0;
5202
5203               if ((recog_for_combine (&pat, other_insn, &note) < 0
5204                    && ! check_asm_operands (pat)))
5205                 {
5206                   PUT_CODE (*cc_use, old_code);
5207                   other_changed = 0;
5208
5209                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5210                                              op0, GEN_INT (mask));
5211                 }
5212             }
5213         }
5214
5215       if (other_changed)
5216         undobuf.other_insn = other_insn;
5217
5218 #ifdef HAVE_cc0
5219       /* If we are now comparing against zero, change our source if
5220          needed.  If we do not use cc0, we always have a COMPARE.  */
5221       if (op1 == const0_rtx && dest == cc0_rtx)
5222         {
5223           SUBST (SET_SRC (x), op0);
5224           src = op0;
5225         }
5226       else
5227 #endif
5228
5229       /* Otherwise, if we didn't previously have a COMPARE in the
5230          correct mode, we need one.  */
5231       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5232         {
5233           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5234           src = SET_SRC (x);
5235         }
5236       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5237         {
5238           SUBST(SET_SRC (x), op0);
5239           src = SET_SRC (x);
5240         }
5241       else
5242         {
5243           /* Otherwise, update the COMPARE if needed.  */
5244           SUBST (XEXP (src, 0), op0);
5245           SUBST (XEXP (src, 1), op1);
5246         }
5247     }
5248   else
5249     {
5250       /* Get SET_SRC in a form where we have placed back any
5251          compound expressions.  Then do the checks below.  */
5252       src = make_compound_operation (src, SET);
5253       SUBST (SET_SRC (x), src);
5254     }
5255
5256   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5257      and X being a REG or (subreg (reg)), we may be able to convert this to
5258      (set (subreg:m2 x) (op)).
5259
5260      We can always do this if M1 is narrower than M2 because that means that
5261      we only care about the low bits of the result.
5262
5263      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5264      perform a narrower operation than requested since the high-order bits will
5265      be undefined.  On machine where it is defined, this transformation is safe
5266      as long as M1 and M2 have the same number of words.  */
5267
5268   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5269       && !OBJECT_P (SUBREG_REG (src))
5270       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5271            / UNITS_PER_WORD)
5272           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5273                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5274 #ifndef WORD_REGISTER_OPERATIONS
5275       && (GET_MODE_SIZE (GET_MODE (src))
5276         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5277 #endif
5278 #ifdef CANNOT_CHANGE_MODE_CLASS
5279       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5280             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5281                                          GET_MODE (SUBREG_REG (src)),
5282                                          GET_MODE (src)))
5283 #endif
5284       && (REG_P (dest)
5285           || (GET_CODE (dest) == SUBREG
5286               && REG_P (SUBREG_REG (dest)))))
5287     {
5288       SUBST (SET_DEST (x),
5289              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5290                                       dest));
5291       SUBST (SET_SRC (x), SUBREG_REG (src));
5292
5293       src = SET_SRC (x), dest = SET_DEST (x);
5294     }
5295
5296 #ifdef HAVE_cc0
5297   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5298      in SRC.  */
5299   if (dest == cc0_rtx
5300       && GET_CODE (src) == SUBREG
5301       && subreg_lowpart_p (src)
5302       && (GET_MODE_BITSIZE (GET_MODE (src))
5303           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5304     {
5305       rtx inner = SUBREG_REG (src);
5306       enum machine_mode inner_mode = GET_MODE (inner);
5307
5308       /* Here we make sure that we don't have a sign bit on.  */
5309       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5310           && (nonzero_bits (inner, inner_mode)
5311               < ((unsigned HOST_WIDE_INT) 1
5312                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5313         {
5314           SUBST (SET_SRC (x), inner);
5315           src = SET_SRC (x);
5316         }
5317     }
5318 #endif
5319
5320 #ifdef LOAD_EXTEND_OP
5321   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5322      would require a paradoxical subreg.  Replace the subreg with a
5323      zero_extend to avoid the reload that would otherwise be required.  */
5324
5325   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5326       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5327       && SUBREG_BYTE (src) == 0
5328       && (GET_MODE_SIZE (GET_MODE (src))
5329           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5330       && MEM_P (SUBREG_REG (src)))
5331     {
5332       SUBST (SET_SRC (x),
5333              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5334                             GET_MODE (src), SUBREG_REG (src)));
5335
5336       src = SET_SRC (x);
5337     }
5338 #endif
5339
5340   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5341      are comparing an item known to be 0 or -1 against 0, use a logical
5342      operation instead. Check for one of the arms being an IOR of the other
5343      arm with some value.  We compute three terms to be IOR'ed together.  In
5344      practice, at most two will be nonzero.  Then we do the IOR's.  */
5345
5346   if (GET_CODE (dest) != PC
5347       && GET_CODE (src) == IF_THEN_ELSE
5348       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5349       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5350       && XEXP (XEXP (src, 0), 1) == const0_rtx
5351       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5352 #ifdef HAVE_conditional_move
5353       && ! can_conditionally_move_p (GET_MODE (src))
5354 #endif
5355       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5356                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5357           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5358       && ! side_effects_p (src))
5359     {
5360       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5361                       ? XEXP (src, 1) : XEXP (src, 2));
5362       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5363                    ? XEXP (src, 2) : XEXP (src, 1));
5364       rtx term1 = const0_rtx, term2, term3;
5365
5366       if (GET_CODE (true_rtx) == IOR
5367           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5368         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5369       else if (GET_CODE (true_rtx) == IOR
5370                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5371         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5372       else if (GET_CODE (false_rtx) == IOR
5373                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5374         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5375       else if (GET_CODE (false_rtx) == IOR
5376                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5377         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5378
5379       term2 = simplify_gen_binary (AND, GET_MODE (src),
5380                                    XEXP (XEXP (src, 0), 0), true_rtx);
5381       term3 = simplify_gen_binary (AND, GET_MODE (src),
5382                                    simplify_gen_unary (NOT, GET_MODE (src),
5383                                                        XEXP (XEXP (src, 0), 0),
5384                                                        GET_MODE (src)),
5385                                    false_rtx);
5386
5387       SUBST (SET_SRC (x),
5388              simplify_gen_binary (IOR, GET_MODE (src),
5389                                   simplify_gen_binary (IOR, GET_MODE (src),
5390                                                        term1, term2),
5391                                   term3));
5392
5393       src = SET_SRC (x);
5394     }
5395
5396   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5397      whole thing fail.  */
5398   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5399     return src;
5400   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5401     return dest;
5402   else
5403     /* Convert this into a field assignment operation, if possible.  */
5404     return make_field_assignment (x);
5405 }
5406 \f
5407 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5408    result.  */
5409
5410 static rtx
5411 simplify_logical (rtx x)
5412 {
5413   enum machine_mode mode = GET_MODE (x);
5414   rtx op0 = XEXP (x, 0);
5415   rtx op1 = XEXP (x, 1);
5416
5417   switch (GET_CODE (x))
5418     {
5419     case AND:
5420       /* We can call simplify_and_const_int only if we don't lose
5421          any (sign) bits when converting INTVAL (op1) to
5422          "unsigned HOST_WIDE_INT".  */
5423       if (GET_CODE (op1) == CONST_INT
5424           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5425               || INTVAL (op1) > 0))
5426         {
5427           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5428           if (GET_CODE (x) != AND)
5429             return x;
5430
5431           op0 = XEXP (x, 0);
5432           op1 = XEXP (x, 1);
5433         }
5434
5435       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5436          apply the distributive law and then the inverse distributive
5437          law to see if things simplify.  */
5438       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5439         {
5440           rtx result = distribute_and_simplify_rtx (x, 0);
5441           if (result)
5442             return result;
5443         }
5444       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5445         {
5446           rtx result = distribute_and_simplify_rtx (x, 1);
5447           if (result)
5448             return result;
5449         }
5450       break;
5451
5452     case IOR:
5453       /* If we have (ior (and A B) C), apply the distributive law and then
5454          the inverse distributive law to see if things simplify.  */
5455
5456       if (GET_CODE (op0) == AND)
5457         {
5458           rtx result = distribute_and_simplify_rtx (x, 0);
5459           if (result)
5460             return result;
5461         }
5462
5463       if (GET_CODE (op1) == AND)
5464         {
5465           rtx result = distribute_and_simplify_rtx (x, 1);
5466           if (result)
5467             return result;
5468         }
5469       break;
5470
5471     default:
5472       gcc_unreachable ();
5473     }
5474
5475   return x;
5476 }
5477 \f
5478 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5479    operations" because they can be replaced with two more basic operations.
5480    ZERO_EXTEND is also considered "compound" because it can be replaced with
5481    an AND operation, which is simpler, though only one operation.
5482
5483    The function expand_compound_operation is called with an rtx expression
5484    and will convert it to the appropriate shifts and AND operations,
5485    simplifying at each stage.
5486
5487    The function make_compound_operation is called to convert an expression
5488    consisting of shifts and ANDs into the equivalent compound expression.
5489    It is the inverse of this function, loosely speaking.  */
5490
5491 static rtx
5492 expand_compound_operation (rtx x)
5493 {
5494   unsigned HOST_WIDE_INT pos = 0, len;
5495   int unsignedp = 0;
5496   unsigned int modewidth;
5497   rtx tem;
5498
5499   switch (GET_CODE (x))
5500     {
5501     case ZERO_EXTEND:
5502       unsignedp = 1;
5503     case SIGN_EXTEND:
5504       /* We can't necessarily use a const_int for a multiword mode;
5505          it depends on implicitly extending the value.
5506          Since we don't know the right way to extend it,
5507          we can't tell whether the implicit way is right.
5508
5509          Even for a mode that is no wider than a const_int,
5510          we can't win, because we need to sign extend one of its bits through
5511          the rest of it, and we don't know which bit.  */
5512       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5513         return x;
5514
5515       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5516          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5517          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5518          reloaded. If not for that, MEM's would very rarely be safe.
5519
5520          Reject MODEs bigger than a word, because we might not be able
5521          to reference a two-register group starting with an arbitrary register
5522          (and currently gen_lowpart might crash for a SUBREG).  */
5523
5524       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5525         return x;
5526
5527       /* Reject MODEs that aren't scalar integers because turning vector
5528          or complex modes into shifts causes problems.  */
5529
5530       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5531         return x;
5532
5533       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5534       /* If the inner object has VOIDmode (the only way this can happen
5535          is if it is an ASM_OPERANDS), we can't do anything since we don't
5536          know how much masking to do.  */
5537       if (len == 0)
5538         return x;
5539
5540       break;
5541
5542     case ZERO_EXTRACT:
5543       unsignedp = 1;
5544
5545       /* ... fall through ...  */
5546
5547     case SIGN_EXTRACT:
5548       /* If the operand is a CLOBBER, just return it.  */
5549       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5550         return XEXP (x, 0);
5551
5552       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5553           || GET_CODE (XEXP (x, 2)) != CONST_INT
5554           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5555         return x;
5556
5557       /* Reject MODEs that aren't scalar integers because turning vector
5558          or complex modes into shifts causes problems.  */
5559
5560       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5561         return x;
5562
5563       len = INTVAL (XEXP (x, 1));
5564       pos = INTVAL (XEXP (x, 2));
5565
5566       /* If this goes outside the object being extracted, replace the object
5567          with a (use (mem ...)) construct that only combine understands
5568          and is used only for this purpose.  */
5569       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5570         SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5571
5572       if (BITS_BIG_ENDIAN)
5573         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5574
5575       break;
5576
5577     default:
5578       return x;
5579     }
5580   /* Convert sign extension to zero extension, if we know that the high
5581      bit is not set, as this is easier to optimize.  It will be converted
5582      back to cheaper alternative in make_extraction.  */
5583   if (GET_CODE (x) == SIGN_EXTEND
5584       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5585           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5586                 & ~(((unsigned HOST_WIDE_INT)
5587                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5588                      >> 1))
5589                == 0)))
5590     {
5591       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5592       rtx temp2 = expand_compound_operation (temp);
5593
5594       /* Make sure this is a profitable operation.  */
5595       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5596        return temp2;
5597       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5598        return temp;
5599       else
5600        return x;
5601     }
5602
5603   /* We can optimize some special cases of ZERO_EXTEND.  */
5604   if (GET_CODE (x) == ZERO_EXTEND)
5605     {
5606       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5607          know that the last value didn't have any inappropriate bits
5608          set.  */
5609       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5610           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5611           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5612           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5613               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5614         return XEXP (XEXP (x, 0), 0);
5615
5616       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5617       if (GET_CODE (XEXP (x, 0)) == SUBREG
5618           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5619           && subreg_lowpart_p (XEXP (x, 0))
5620           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5621           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5622               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5623         return SUBREG_REG (XEXP (x, 0));
5624
5625       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5626          is a comparison and STORE_FLAG_VALUE permits.  This is like
5627          the first case, but it works even when GET_MODE (x) is larger
5628          than HOST_WIDE_INT.  */
5629       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5630           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5631           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5632           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5633               <= HOST_BITS_PER_WIDE_INT)
5634           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5635               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5636         return XEXP (XEXP (x, 0), 0);
5637
5638       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5639       if (GET_CODE (XEXP (x, 0)) == SUBREG
5640           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5641           && subreg_lowpart_p (XEXP (x, 0))
5642           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5643           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5644               <= HOST_BITS_PER_WIDE_INT)
5645           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5646               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5647         return SUBREG_REG (XEXP (x, 0));
5648
5649     }
5650
5651   /* If we reach here, we want to return a pair of shifts.  The inner
5652      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5653      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5654      logical depending on the value of UNSIGNEDP.
5655
5656      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5657      converted into an AND of a shift.
5658
5659      We must check for the case where the left shift would have a negative
5660      count.  This can happen in a case like (x >> 31) & 255 on machines
5661      that can't shift by a constant.  On those machines, we would first
5662      combine the shift with the AND to produce a variable-position
5663      extraction.  Then the constant of 31 would be substituted in to produce
5664      a such a position.  */
5665
5666   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5667   if (modewidth + len >= pos)
5668     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5669                                 GET_MODE (x),
5670                                 simplify_shift_const (NULL_RTX, ASHIFT,
5671                                                       GET_MODE (x),
5672                                                       XEXP (x, 0),
5673                                                       modewidth - pos - len),
5674                                 modewidth - len);
5675
5676   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5677     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5678                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5679                                                         GET_MODE (x),
5680                                                         XEXP (x, 0), pos),
5681                                   ((HOST_WIDE_INT) 1 << len) - 1);
5682   else
5683     /* Any other cases we can't handle.  */
5684     return x;
5685
5686   /* If we couldn't do this for some reason, return the original
5687      expression.  */
5688   if (GET_CODE (tem) == CLOBBER)
5689     return x;
5690
5691   return tem;
5692 }
5693 \f
5694 /* X is a SET which contains an assignment of one object into
5695    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5696    or certain SUBREGS). If possible, convert it into a series of
5697    logical operations.
5698
5699    We half-heartedly support variable positions, but do not at all
5700    support variable lengths.  */
5701
5702 static rtx
5703 expand_field_assignment (rtx x)
5704 {
5705   rtx inner;
5706   rtx pos;                      /* Always counts from low bit.  */
5707   int len;
5708   rtx mask, cleared, masked;
5709   enum machine_mode compute_mode;
5710
5711   /* Loop until we find something we can't simplify.  */
5712   while (1)
5713     {
5714       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5715           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5716         {
5717           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5718           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5719           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5720         }
5721       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5722                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5723         {
5724           inner = XEXP (SET_DEST (x), 0);
5725           len = INTVAL (XEXP (SET_DEST (x), 1));
5726           pos = XEXP (SET_DEST (x), 2);
5727
5728           /* If the position is constant and spans the width of INNER,
5729              surround INNER  with a USE to indicate this.  */
5730           if (GET_CODE (pos) == CONST_INT
5731               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5732             inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5733
5734           if (BITS_BIG_ENDIAN)
5735             {
5736               if (GET_CODE (pos) == CONST_INT)
5737                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5738                                - INTVAL (pos));
5739               else if (GET_CODE (pos) == MINUS
5740                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5741                        && (INTVAL (XEXP (pos, 1))
5742                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5743                 /* If position is ADJUST - X, new position is X.  */
5744                 pos = XEXP (pos, 0);
5745               else
5746                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5747                                            GEN_INT (GET_MODE_BITSIZE (
5748                                                     GET_MODE (inner))
5749                                                     - len),
5750                                            pos);
5751             }
5752         }
5753
5754       /* A SUBREG between two modes that occupy the same numbers of words
5755          can be done by moving the SUBREG to the source.  */
5756       else if (GET_CODE (SET_DEST (x)) == SUBREG
5757                /* We need SUBREGs to compute nonzero_bits properly.  */
5758                && nonzero_sign_valid
5759                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5760                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5761                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5762                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5763         {
5764           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5765                            gen_lowpart
5766                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5767                             SET_SRC (x)));
5768           continue;
5769         }
5770       else
5771         break;
5772
5773       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5774         inner = SUBREG_REG (inner);
5775
5776       compute_mode = GET_MODE (inner);
5777
5778       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5779       if (! SCALAR_INT_MODE_P (compute_mode))
5780         {
5781           enum machine_mode imode;
5782
5783           /* Don't do anything for vector or complex integral types.  */
5784           if (! FLOAT_MODE_P (compute_mode))
5785             break;
5786
5787           /* Try to find an integral mode to pun with.  */
5788           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5789           if (imode == BLKmode)
5790             break;
5791
5792           compute_mode = imode;
5793           inner = gen_lowpart (imode, inner);
5794         }
5795
5796       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5797       if (len >= HOST_BITS_PER_WIDE_INT)
5798         break;
5799
5800       /* Now compute the equivalent expression.  Make a copy of INNER
5801          for the SET_DEST in case it is a MEM into which we will substitute;
5802          we don't want shared RTL in that case.  */
5803       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5804       cleared = simplify_gen_binary (AND, compute_mode,
5805                                      simplify_gen_unary (NOT, compute_mode,
5806                                        simplify_gen_binary (ASHIFT,
5807                                                             compute_mode,
5808                                                             mask, pos),
5809                                        compute_mode),
5810                                      inner);
5811       masked = simplify_gen_binary (ASHIFT, compute_mode,
5812                                     simplify_gen_binary (
5813                                       AND, compute_mode,
5814                                       gen_lowpart (compute_mode, SET_SRC (x)),
5815                                       mask),
5816                                     pos);
5817
5818       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5819                        simplify_gen_binary (IOR, compute_mode,
5820                                             cleared, masked));
5821     }
5822
5823   return x;
5824 }
5825 \f
5826 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5827    it is an RTX that represents a variable starting position; otherwise,
5828    POS is the (constant) starting bit position (counted from the LSB).
5829
5830    INNER may be a USE.  This will occur when we started with a bitfield
5831    that went outside the boundary of the object in memory, which is
5832    allowed on most machines.  To isolate this case, we produce a USE
5833    whose mode is wide enough and surround the MEM with it.  The only
5834    code that understands the USE is this routine.  If it is not removed,
5835    it will cause the resulting insn not to match.
5836
5837    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5838    signed reference.
5839
5840    IN_DEST is nonzero if this is a reference in the destination of a
5841    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5842    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5843    be used.
5844
5845    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5846    ZERO_EXTRACT should be built even for bits starting at bit 0.
5847
5848    MODE is the desired mode of the result (if IN_DEST == 0).
5849
5850    The result is an RTX for the extraction or NULL_RTX if the target
5851    can't handle it.  */
5852
5853 static rtx
5854 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5855                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5856                  int in_dest, int in_compare)
5857 {
5858   /* This mode describes the size of the storage area
5859      to fetch the overall value from.  Within that, we
5860      ignore the POS lowest bits, etc.  */
5861   enum machine_mode is_mode = GET_MODE (inner);
5862   enum machine_mode inner_mode;
5863   enum machine_mode wanted_inner_mode = byte_mode;
5864   enum machine_mode wanted_inner_reg_mode = word_mode;
5865   enum machine_mode pos_mode = word_mode;
5866   enum machine_mode extraction_mode = word_mode;
5867   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5868   int spans_byte = 0;
5869   rtx new = 0;
5870   rtx orig_pos_rtx = pos_rtx;
5871   HOST_WIDE_INT orig_pos;
5872
5873   /* Get some information about INNER and get the innermost object.  */
5874   if (GET_CODE (inner) == USE)
5875     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5876     /* We don't need to adjust the position because we set up the USE
5877        to pretend that it was a full-word object.  */
5878     spans_byte = 1, inner = XEXP (inner, 0);
5879   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5880     {
5881       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5882          consider just the QI as the memory to extract from.
5883          The subreg adds or removes high bits; its mode is
5884          irrelevant to the meaning of this extraction,
5885          since POS and LEN count from the lsb.  */
5886       if (MEM_P (SUBREG_REG (inner)))
5887         is_mode = GET_MODE (SUBREG_REG (inner));
5888       inner = SUBREG_REG (inner);
5889     }
5890   else if (GET_CODE (inner) == ASHIFT
5891            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5892            && pos_rtx == 0 && pos == 0
5893            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5894     {
5895       /* We're extracting the least significant bits of an rtx
5896          (ashift X (const_int C)), where LEN > C.  Extract the
5897          least significant (LEN - C) bits of X, giving an rtx
5898          whose mode is MODE, then shift it left C times.  */
5899       new = make_extraction (mode, XEXP (inner, 0),
5900                              0, 0, len - INTVAL (XEXP (inner, 1)),
5901                              unsignedp, in_dest, in_compare);
5902       if (new != 0)
5903         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5904     }
5905
5906   inner_mode = GET_MODE (inner);
5907
5908   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5909     pos = INTVAL (pos_rtx), pos_rtx = 0;
5910
5911   /* See if this can be done without an extraction.  We never can if the
5912      width of the field is not the same as that of some integer mode. For
5913      registers, we can only avoid the extraction if the position is at the
5914      low-order bit and this is either not in the destination or we have the
5915      appropriate STRICT_LOW_PART operation available.
5916
5917      For MEM, we can avoid an extract if the field starts on an appropriate
5918      boundary and we can change the mode of the memory reference.  However,
5919      we cannot directly access the MEM if we have a USE and the underlying
5920      MEM is not TMODE.  This combination means that MEM was being used in a
5921      context where bits outside its mode were being referenced; that is only
5922      valid in bit-field insns.  */
5923
5924   if (tmode != BLKmode
5925       && ! (spans_byte && inner_mode != tmode)
5926       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5927            && !MEM_P (inner)
5928            && (! in_dest
5929                || (REG_P (inner)
5930                    && have_insn_for (STRICT_LOW_PART, tmode))))
5931           || (MEM_P (inner) && pos_rtx == 0
5932               && (pos
5933                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5934                      : BITS_PER_UNIT)) == 0
5935               /* We can't do this if we are widening INNER_MODE (it
5936                  may not be aligned, for one thing).  */
5937               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5938               && (inner_mode == tmode
5939                   || (! mode_dependent_address_p (XEXP (inner, 0))
5940                       && ! MEM_VOLATILE_P (inner))))))
5941     {
5942       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5943          field.  If the original and current mode are the same, we need not
5944          adjust the offset.  Otherwise, we do if bytes big endian.
5945
5946          If INNER is not a MEM, get a piece consisting of just the field
5947          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5948
5949       if (MEM_P (inner))
5950         {
5951           HOST_WIDE_INT offset;
5952
5953           /* POS counts from lsb, but make OFFSET count in memory order.  */
5954           if (BYTES_BIG_ENDIAN)
5955             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5956           else
5957             offset = pos / BITS_PER_UNIT;
5958
5959           new = adjust_address_nv (inner, tmode, offset);
5960         }
5961       else if (REG_P (inner))
5962         {
5963           if (tmode != inner_mode)
5964             {
5965               /* We can't call gen_lowpart in a DEST since we
5966                  always want a SUBREG (see below) and it would sometimes
5967                  return a new hard register.  */
5968               if (pos || in_dest)
5969                 {
5970                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5971
5972                   if (WORDS_BIG_ENDIAN
5973                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5974                     final_word = ((GET_MODE_SIZE (inner_mode)
5975                                    - GET_MODE_SIZE (tmode))
5976                                   / UNITS_PER_WORD) - final_word;
5977
5978                   final_word *= UNITS_PER_WORD;
5979                   if (BYTES_BIG_ENDIAN &&
5980                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5981                     final_word += (GET_MODE_SIZE (inner_mode)
5982                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5983
5984                   /* Avoid creating invalid subregs, for example when
5985                      simplifying (x>>32)&255.  */
5986                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
5987                     return NULL_RTX;
5988
5989                   new = gen_rtx_SUBREG (tmode, inner, final_word);
5990                 }
5991               else
5992                 new = gen_lowpart (tmode, inner);
5993             }
5994           else
5995             new = inner;
5996         }
5997       else
5998         new = force_to_mode (inner, tmode,
5999                              len >= HOST_BITS_PER_WIDE_INT
6000                              ? ~(unsigned HOST_WIDE_INT) 0
6001                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6002                              0);
6003
6004       /* If this extraction is going into the destination of a SET,
6005          make a STRICT_LOW_PART unless we made a MEM.  */
6006
6007       if (in_dest)
6008         return (MEM_P (new) ? new
6009                 : (GET_CODE (new) != SUBREG
6010                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6011                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6012
6013       if (mode == tmode)
6014         return new;
6015
6016       if (GET_CODE (new) == CONST_INT)
6017         return gen_int_mode (INTVAL (new), mode);
6018
6019       /* If we know that no extraneous bits are set, and that the high
6020          bit is not set, convert the extraction to the cheaper of
6021          sign and zero extension, that are equivalent in these cases.  */
6022       if (flag_expensive_optimizations
6023           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6024               && ((nonzero_bits (new, tmode)
6025                    & ~(((unsigned HOST_WIDE_INT)
6026                         GET_MODE_MASK (tmode))
6027                        >> 1))
6028                   == 0)))
6029         {
6030           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6031           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6032
6033           /* Prefer ZERO_EXTENSION, since it gives more information to
6034              backends.  */
6035           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6036             return temp;
6037           return temp1;
6038         }
6039
6040       /* Otherwise, sign- or zero-extend unless we already are in the
6041          proper mode.  */
6042
6043       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6044                              mode, new));
6045     }
6046
6047   /* Unless this is a COMPARE or we have a funny memory reference,
6048      don't do anything with zero-extending field extracts starting at
6049      the low-order bit since they are simple AND operations.  */
6050   if (pos_rtx == 0 && pos == 0 && ! in_dest
6051       && ! in_compare && ! spans_byte && unsignedp)
6052     return 0;
6053
6054   /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6055      we would be spanning bytes or if the position is not a constant and the
6056      length is not 1.  In all other cases, we would only be going outside
6057      our object in cases when an original shift would have been
6058      undefined.  */
6059   if (! spans_byte && MEM_P (inner)
6060       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6061           || (pos_rtx != 0 && len != 1)))
6062     return 0;
6063
6064   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6065      and the mode for the result.  */
6066   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6067     {
6068       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6069       pos_mode = mode_for_extraction (EP_insv, 2);
6070       extraction_mode = mode_for_extraction (EP_insv, 3);
6071     }
6072
6073   if (! in_dest && unsignedp
6074       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6075     {
6076       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6077       pos_mode = mode_for_extraction (EP_extzv, 3);
6078       extraction_mode = mode_for_extraction (EP_extzv, 0);
6079     }
6080
6081   if (! in_dest && ! unsignedp
6082       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6083     {
6084       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6085       pos_mode = mode_for_extraction (EP_extv, 3);
6086       extraction_mode = mode_for_extraction (EP_extv, 0);
6087     }
6088
6089   /* Never narrow an object, since that might not be safe.  */
6090
6091   if (mode != VOIDmode
6092       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6093     extraction_mode = mode;
6094
6095   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6096       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6097     pos_mode = GET_MODE (pos_rtx);
6098
6099   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6100      if we have to change the mode of memory and cannot, the desired mode is
6101      EXTRACTION_MODE.  */
6102   if (!MEM_P (inner))
6103     wanted_inner_mode = wanted_inner_reg_mode;
6104   else if (inner_mode != wanted_inner_mode
6105            && (mode_dependent_address_p (XEXP (inner, 0))
6106                || MEM_VOLATILE_P (inner)))
6107     wanted_inner_mode = extraction_mode;
6108
6109   orig_pos = pos;
6110
6111   if (BITS_BIG_ENDIAN)
6112     {
6113       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6114          BITS_BIG_ENDIAN style.  If position is constant, compute new
6115          position.  Otherwise, build subtraction.
6116          Note that POS is relative to the mode of the original argument.
6117          If it's a MEM we need to recompute POS relative to that.
6118          However, if we're extracting from (or inserting into) a register,
6119          we want to recompute POS relative to wanted_inner_mode.  */
6120       int width = (MEM_P (inner)
6121                    ? GET_MODE_BITSIZE (is_mode)
6122                    : GET_MODE_BITSIZE (wanted_inner_mode));
6123
6124       if (pos_rtx == 0)
6125         pos = width - len - pos;
6126       else
6127         pos_rtx
6128           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6129       /* POS may be less than 0 now, but we check for that below.
6130          Note that it can only be less than 0 if !MEM_P (inner).  */
6131     }
6132
6133   /* If INNER has a wider mode, make it smaller.  If this is a constant
6134      extract, try to adjust the byte to point to the byte containing
6135      the value.  */
6136   if (wanted_inner_mode != VOIDmode
6137       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6138       && ((MEM_P (inner)
6139            && (inner_mode == wanted_inner_mode
6140                || (! mode_dependent_address_p (XEXP (inner, 0))
6141                    && ! MEM_VOLATILE_P (inner))))))
6142     {
6143       int offset = 0;
6144
6145       /* The computations below will be correct if the machine is big
6146          endian in both bits and bytes or little endian in bits and bytes.
6147          If it is mixed, we must adjust.  */
6148
6149       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6150          adjust OFFSET to compensate.  */
6151       if (BYTES_BIG_ENDIAN
6152           && ! spans_byte
6153           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6154         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6155
6156       /* If this is a constant position, we can move to the desired byte.
6157          Be careful not to go beyond the original object and maintain the
6158          natural alignment of the memory.  */
6159       if (pos_rtx == 0)
6160         {
6161           enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6162           offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6163           pos %= GET_MODE_BITSIZE (bfmode);
6164         }
6165
6166       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6167           && ! spans_byte
6168           && is_mode != wanted_inner_mode)
6169         offset = (GET_MODE_SIZE (is_mode)
6170                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6171
6172       if (offset != 0 || inner_mode != wanted_inner_mode)
6173         inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6174     }
6175
6176   /* If INNER is not memory, we can always get it into the proper mode.  If we
6177      are changing its mode, POS must be a constant and smaller than the size
6178      of the new mode.  */
6179   else if (!MEM_P (inner))
6180     {
6181       if (GET_MODE (inner) != wanted_inner_mode
6182           && (pos_rtx != 0
6183               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6184         return 0;
6185
6186       inner = force_to_mode (inner, wanted_inner_mode,
6187                              pos_rtx
6188                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6189                              ? ~(unsigned HOST_WIDE_INT) 0
6190                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6191                                 << orig_pos),
6192                              0);
6193     }
6194
6195   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6196      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6197   if (pos_rtx != 0
6198       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6199     {
6200       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6201
6202       /* If we know that no extraneous bits are set, and that the high
6203          bit is not set, convert extraction to cheaper one - either
6204          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6205          cases.  */
6206       if (flag_expensive_optimizations
6207           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6208               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6209                    & ~(((unsigned HOST_WIDE_INT)
6210                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6211                        >> 1))
6212                   == 0)))
6213         {
6214           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6215
6216           /* Prefer ZERO_EXTENSION, since it gives more information to
6217              backends.  */
6218           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6219             temp = temp1;
6220         }
6221       pos_rtx = temp;
6222     }
6223   else if (pos_rtx != 0
6224            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6225     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6226
6227   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6228      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6229      be a CONST_INT.  */
6230   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6231     pos_rtx = orig_pos_rtx;
6232
6233   else if (pos_rtx == 0)
6234     pos_rtx = GEN_INT (pos);
6235
6236   /* Make the required operation.  See if we can use existing rtx.  */
6237   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6238                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6239   if (! in_dest)
6240     new = gen_lowpart (mode, new);
6241
6242   return new;
6243 }
6244 \f
6245 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6246    with any other operations in X.  Return X without that shift if so.  */
6247
6248 static rtx
6249 extract_left_shift (rtx x, int count)
6250 {
6251   enum rtx_code code = GET_CODE (x);
6252   enum machine_mode mode = GET_MODE (x);
6253   rtx tem;
6254
6255   switch (code)
6256     {
6257     case ASHIFT:
6258       /* This is the shift itself.  If it is wide enough, we will return
6259          either the value being shifted if the shift count is equal to
6260          COUNT or a shift for the difference.  */
6261       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6262           && INTVAL (XEXP (x, 1)) >= count)
6263         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6264                                      INTVAL (XEXP (x, 1)) - count);
6265       break;
6266
6267     case NEG:  case NOT:
6268       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6269         return simplify_gen_unary (code, mode, tem, mode);
6270
6271       break;
6272
6273     case PLUS:  case IOR:  case XOR:  case AND:
6274       /* If we can safely shift this constant and we find the inner shift,
6275          make a new operation.  */
6276       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6277           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6278           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6279         return simplify_gen_binary (code, mode, tem,
6280                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6281
6282       break;
6283
6284     default:
6285       break;
6286     }
6287
6288   return 0;
6289 }
6290 \f
6291 /* Look at the expression rooted at X.  Look for expressions
6292    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6293    Form these expressions.
6294
6295    Return the new rtx, usually just X.
6296
6297    Also, for machines like the VAX that don't have logical shift insns,
6298    try to convert logical to arithmetic shift operations in cases where
6299    they are equivalent.  This undoes the canonicalizations to logical
6300    shifts done elsewhere.
6301
6302    We try, as much as possible, to re-use rtl expressions to save memory.
6303
6304    IN_CODE says what kind of expression we are processing.  Normally, it is
6305    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6306    being kludges), it is MEM.  When processing the arguments of a comparison
6307    or a COMPARE against zero, it is COMPARE.  */
6308
6309 static rtx
6310 make_compound_operation (rtx x, enum rtx_code in_code)
6311 {
6312   enum rtx_code code = GET_CODE (x);
6313   enum machine_mode mode = GET_MODE (x);
6314   int mode_width = GET_MODE_BITSIZE (mode);
6315   rtx rhs, lhs;
6316   enum rtx_code next_code;
6317   int i;
6318   rtx new = 0;
6319   rtx tem;
6320   const char *fmt;
6321
6322   /* Select the code to be used in recursive calls.  Once we are inside an
6323      address, we stay there.  If we have a comparison, set to COMPARE,
6324      but once inside, go back to our default of SET.  */
6325
6326   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6327                : ((code == COMPARE || COMPARISON_P (x))
6328                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6329                : in_code == COMPARE ? SET : in_code);
6330
6331   /* Process depending on the code of this operation.  If NEW is set
6332      nonzero, it will be returned.  */
6333
6334   switch (code)
6335     {
6336     case ASHIFT:
6337       /* Convert shifts by constants into multiplications if inside
6338          an address.  */
6339       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6340           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6341           && INTVAL (XEXP (x, 1)) >= 0)
6342         {
6343           new = make_compound_operation (XEXP (x, 0), next_code);
6344           new = gen_rtx_MULT (mode, new,
6345                               GEN_INT ((HOST_WIDE_INT) 1
6346                                        << INTVAL (XEXP (x, 1))));
6347         }
6348       break;
6349
6350     case AND:
6351       /* If the second operand is not a constant, we can't do anything
6352          with it.  */
6353       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6354         break;
6355
6356       /* If the constant is a power of two minus one and the first operand
6357          is a logical right shift, make an extraction.  */
6358       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6359           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6360         {
6361           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6362           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6363                                  0, in_code == COMPARE);
6364         }
6365
6366       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6367       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6368                && subreg_lowpart_p (XEXP (x, 0))
6369                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6370                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6371         {
6372           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6373                                          next_code);
6374           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6375                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6376                                  0, in_code == COMPARE);
6377         }
6378       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6379       else if ((GET_CODE (XEXP (x, 0)) == XOR
6380                 || GET_CODE (XEXP (x, 0)) == IOR)
6381                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6382                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6383                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6384         {
6385           /* Apply the distributive law, and then try to make extractions.  */
6386           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6387                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6388                                              XEXP (x, 1)),
6389                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6390                                              XEXP (x, 1)));
6391           new = make_compound_operation (new, in_code);
6392         }
6393
6394       /* If we are have (and (rotate X C) M) and C is larger than the number
6395          of bits in M, this is an extraction.  */
6396
6397       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6398                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6399                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6400                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6401         {
6402           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6403           new = make_extraction (mode, new,
6404                                  (GET_MODE_BITSIZE (mode)
6405                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6406                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6407         }
6408
6409       /* On machines without logical shifts, if the operand of the AND is
6410          a logical shift and our mask turns off all the propagated sign
6411          bits, we can replace the logical shift with an arithmetic shift.  */
6412       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6413                && !have_insn_for (LSHIFTRT, mode)
6414                && have_insn_for (ASHIFTRT, mode)
6415                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6416                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6417                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6418                && mode_width <= HOST_BITS_PER_WIDE_INT)
6419         {
6420           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6421
6422           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6423           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6424             SUBST (XEXP (x, 0),
6425                    gen_rtx_ASHIFTRT (mode,
6426                                      make_compound_operation
6427                                      (XEXP (XEXP (x, 0), 0), next_code),
6428                                      XEXP (XEXP (x, 0), 1)));
6429         }
6430
6431       /* If the constant is one less than a power of two, this might be
6432          representable by an extraction even if no shift is present.
6433          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6434          we are in a COMPARE.  */
6435       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6436         new = make_extraction (mode,
6437                                make_compound_operation (XEXP (x, 0),
6438                                                         next_code),
6439                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6440
6441       /* If we are in a comparison and this is an AND with a power of two,
6442          convert this into the appropriate bit extract.  */
6443       else if (in_code == COMPARE
6444                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6445         new = make_extraction (mode,
6446                                make_compound_operation (XEXP (x, 0),
6447                                                         next_code),
6448                                i, NULL_RTX, 1, 1, 0, 1);
6449
6450       break;
6451
6452     case LSHIFTRT:
6453       /* If the sign bit is known to be zero, replace this with an
6454          arithmetic shift.  */
6455       if (have_insn_for (ASHIFTRT, mode)
6456           && ! have_insn_for (LSHIFTRT, mode)
6457           && mode_width <= HOST_BITS_PER_WIDE_INT
6458           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6459         {
6460           new = gen_rtx_ASHIFTRT (mode,
6461                                   make_compound_operation (XEXP (x, 0),
6462                                                            next_code),
6463                                   XEXP (x, 1));
6464           break;
6465         }
6466
6467       /* ... fall through ...  */
6468
6469     case ASHIFTRT:
6470       lhs = XEXP (x, 0);
6471       rhs = XEXP (x, 1);
6472
6473       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6474          this is a SIGN_EXTRACT.  */
6475       if (GET_CODE (rhs) == CONST_INT
6476           && GET_CODE (lhs) == ASHIFT
6477           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6478           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6479         {
6480           new = make_compound_operation (XEXP (lhs, 0), next_code);
6481           new = make_extraction (mode, new,
6482                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6483                                  NULL_RTX, mode_width - INTVAL (rhs),
6484                                  code == LSHIFTRT, 0, in_code == COMPARE);
6485           break;
6486         }
6487
6488       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6489          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6490          also do this for some cases of SIGN_EXTRACT, but it doesn't
6491          seem worth the effort; the case checked for occurs on Alpha.  */
6492
6493       if (!OBJECT_P (lhs)
6494           && ! (GET_CODE (lhs) == SUBREG
6495                 && (OBJECT_P (SUBREG_REG (lhs))))
6496           && GET_CODE (rhs) == CONST_INT
6497           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6498           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6499         new = make_extraction (mode, make_compound_operation (new, next_code),
6500                                0, NULL_RTX, mode_width - INTVAL (rhs),
6501                                code == LSHIFTRT, 0, in_code == COMPARE);
6502
6503       break;
6504
6505     case SUBREG:
6506       /* Call ourselves recursively on the inner expression.  If we are
6507          narrowing the object and it has a different RTL code from
6508          what it originally did, do this SUBREG as a force_to_mode.  */
6509
6510       tem = make_compound_operation (SUBREG_REG (x), in_code);
6511
6512       {
6513         rtx simplified;
6514         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6515                                       SUBREG_BYTE (x));
6516
6517         if (simplified)
6518           tem = simplified;
6519
6520         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6521             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6522             && subreg_lowpart_p (x))
6523           {
6524             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6525                                        0);
6526
6527             /* If we have something other than a SUBREG, we might have
6528                done an expansion, so rerun ourselves.  */
6529             if (GET_CODE (newer) != SUBREG)
6530               newer = make_compound_operation (newer, in_code);
6531
6532             return newer;
6533           }
6534
6535         if (simplified)
6536           return tem;
6537       }
6538       break;
6539
6540     default:
6541       break;
6542     }
6543
6544   if (new)
6545     {
6546       x = gen_lowpart (mode, new);
6547       code = GET_CODE (x);
6548     }
6549
6550   /* Now recursively process each operand of this operation.  */
6551   fmt = GET_RTX_FORMAT (code);
6552   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6553     if (fmt[i] == 'e')
6554       {
6555         new = make_compound_operation (XEXP (x, i), next_code);
6556         SUBST (XEXP (x, i), new);
6557       }
6558
6559   /* If this is a commutative operation, the changes to the operands
6560      may have made it noncanonical.  */
6561   if (COMMUTATIVE_ARITH_P (x)
6562       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6563     {
6564       tem = XEXP (x, 0);
6565       SUBST (XEXP (x, 0), XEXP (x, 1));
6566       SUBST (XEXP (x, 1), tem);
6567     }
6568
6569   return x;
6570 }
6571 \f
6572 /* Given M see if it is a value that would select a field of bits
6573    within an item, but not the entire word.  Return -1 if not.
6574    Otherwise, return the starting position of the field, where 0 is the
6575    low-order bit.
6576
6577    *PLEN is set to the length of the field.  */
6578
6579 static int
6580 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6581 {
6582   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6583   int pos = exact_log2 (m & -m);
6584   int len = 0;
6585
6586   if (pos >= 0)
6587     /* Now shift off the low-order zero bits and see if we have a
6588        power of two minus 1.  */
6589     len = exact_log2 ((m >> pos) + 1);
6590
6591   if (len <= 0)
6592     pos = -1;
6593
6594   *plen = len;
6595   return pos;
6596 }
6597 \f
6598 /* If X refers to a register that equals REG in value, replace these
6599    references with REG.  */
6600 static rtx
6601 canon_reg_for_combine (rtx x, rtx reg)
6602 {
6603   rtx op0, op1, op2;
6604   const char *fmt;
6605   int i;
6606   bool copied;
6607
6608   enum rtx_code code = GET_CODE (x);
6609   switch (GET_RTX_CLASS (code))
6610     {
6611     case RTX_UNARY:
6612       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6613       if (op0 != XEXP (x, 0))
6614         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6615                                    GET_MODE (reg));
6616       break;
6617
6618     case RTX_BIN_ARITH:
6619     case RTX_COMM_ARITH:
6620       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6621       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6622       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6623         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6624       break;
6625
6626     case RTX_COMPARE:
6627     case RTX_COMM_COMPARE:
6628       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6629       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6630       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6631         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6632                                         GET_MODE (op0), op0, op1);
6633       break;
6634
6635     case RTX_TERNARY:
6636     case RTX_BITFIELD_OPS:
6637       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6638       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6639       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6640       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6641         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6642                                      GET_MODE (op0), op0, op1, op2);
6643
6644     case RTX_OBJ:
6645       if (REG_P (x))
6646         {
6647           if (rtx_equal_p (get_last_value (reg), x)
6648               || rtx_equal_p (reg, get_last_value (x)))
6649             return reg;
6650           else
6651             break;
6652         }
6653
6654       /* fall through */
6655
6656     default:
6657       fmt = GET_RTX_FORMAT (code);
6658       copied = false;
6659       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6660         if (fmt[i] == 'e')
6661           {
6662             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6663             if (op != XEXP (x, i))
6664               {
6665                 if (!copied)
6666                   {
6667                     copied = true;
6668                     x = copy_rtx (x);
6669                   }
6670                 XEXP (x, i) = op;
6671               }
6672           }
6673         else if (fmt[i] == 'E')
6674           {
6675             int j;
6676             for (j = 0; j < XVECLEN (x, i); j++)
6677               {
6678                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6679                 if (op != XVECEXP (x, i, j))
6680                   {
6681                     if (!copied)
6682                       {
6683                         copied = true;
6684                         x = copy_rtx (x);
6685                       }
6686                     XVECEXP (x, i, j) = op;
6687                   }
6688               }
6689           }
6690
6691       break;
6692     }
6693
6694   return x;
6695 }
6696
6697 /* See if X can be simplified knowing that we will only refer to it in
6698    MODE and will only refer to those bits that are nonzero in MASK.
6699    If other bits are being computed or if masking operations are done
6700    that select a superset of the bits in MASK, they can sometimes be
6701    ignored.
6702
6703    Return a possibly simplified expression, but always convert X to
6704    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6705
6706    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6707    are all off in X.  This is used when X will be complemented, by either
6708    NOT, NEG, or XOR.  */
6709
6710 static rtx
6711 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6712                int just_select)
6713 {
6714   enum rtx_code code = GET_CODE (x);
6715   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6716   enum machine_mode op_mode;
6717   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6718   rtx op0, op1, temp;
6719
6720   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6721      code below will do the wrong thing since the mode of such an
6722      expression is VOIDmode.
6723
6724      Also do nothing if X is a CLOBBER; this can happen if X was
6725      the return value from a call to gen_lowpart.  */
6726   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6727     return x;
6728
6729   /* We want to perform the operation is its present mode unless we know
6730      that the operation is valid in MODE, in which case we do the operation
6731      in MODE.  */
6732   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6733               && have_insn_for (code, mode))
6734              ? mode : GET_MODE (x));
6735
6736   /* It is not valid to do a right-shift in a narrower mode
6737      than the one it came in with.  */
6738   if ((code == LSHIFTRT || code == ASHIFTRT)
6739       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6740     op_mode = GET_MODE (x);
6741
6742   /* Truncate MASK to fit OP_MODE.  */
6743   if (op_mode)
6744     mask &= GET_MODE_MASK (op_mode);
6745
6746   /* When we have an arithmetic operation, or a shift whose count we
6747      do not know, we need to assume that all bits up to the highest-order
6748      bit in MASK will be needed.  This is how we form such a mask.  */
6749   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6750     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6751   else
6752     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6753                    - 1);
6754
6755   /* Determine what bits of X are guaranteed to be (non)zero.  */
6756   nonzero = nonzero_bits (x, mode);
6757
6758   /* If none of the bits in X are needed, return a zero.  */
6759   if (! just_select && (nonzero & mask) == 0)
6760     x = const0_rtx;
6761
6762   /* If X is a CONST_INT, return a new one.  Do this here since the
6763      test below will fail.  */
6764   if (GET_CODE (x) == CONST_INT)
6765     {
6766       if (SCALAR_INT_MODE_P (mode))
6767         return gen_int_mode (INTVAL (x) & mask, mode);
6768       else
6769         {
6770           x = GEN_INT (INTVAL (x) & mask);
6771           return gen_lowpart_common (mode, x);
6772         }
6773     }
6774
6775   /* If X is narrower than MODE and we want all the bits in X's mode, just
6776      get X in the proper mode.  */
6777   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6778       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6779     return gen_lowpart (mode, x);
6780
6781   switch (code)
6782     {
6783     case CLOBBER:
6784       /* If X is a (clobber (const_int)), return it since we know we are
6785          generating something that won't match.  */
6786       return x;
6787
6788     case USE:
6789       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6790          spanned the boundary of the MEM.  If we are now masking so it is
6791          within that boundary, we don't need the USE any more.  */
6792       if (! BITS_BIG_ENDIAN
6793           && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6794         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6795       break;
6796
6797     case SIGN_EXTEND:
6798     case ZERO_EXTEND:
6799     case ZERO_EXTRACT:
6800     case SIGN_EXTRACT:
6801       x = expand_compound_operation (x);
6802       if (GET_CODE (x) != code)
6803         return force_to_mode (x, mode, mask, next_select);
6804       break;
6805
6806     case SUBREG:
6807       if (subreg_lowpart_p (x)
6808           /* We can ignore the effect of this SUBREG if it narrows the mode or
6809              if the constant masks to zero all the bits the mode doesn't
6810              have.  */
6811           && ((GET_MODE_SIZE (GET_MODE (x))
6812                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6813               || (0 == (mask
6814                         & GET_MODE_MASK (GET_MODE (x))
6815                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6816         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6817       break;
6818
6819     case AND:
6820       /* If this is an AND with a constant, convert it into an AND
6821          whose constant is the AND of that constant with MASK.  If it
6822          remains an AND of MASK, delete it since it is redundant.  */
6823
6824       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6825         {
6826           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6827                                       mask & INTVAL (XEXP (x, 1)));
6828
6829           /* If X is still an AND, see if it is an AND with a mask that
6830              is just some low-order bits.  If so, and it is MASK, we don't
6831              need it.  */
6832
6833           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6834               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6835                   == mask))
6836             x = XEXP (x, 0);
6837
6838           /* If it remains an AND, try making another AND with the bits
6839              in the mode mask that aren't in MASK turned on.  If the
6840              constant in the AND is wide enough, this might make a
6841              cheaper constant.  */
6842
6843           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6844               && GET_MODE_MASK (GET_MODE (x)) != mask
6845               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6846             {
6847               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6848                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6849               int width = GET_MODE_BITSIZE (GET_MODE (x));
6850               rtx y;
6851
6852               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6853                  number, sign extend it.  */
6854               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6855                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6856                 cval |= (HOST_WIDE_INT) -1 << width;
6857
6858               y = simplify_gen_binary (AND, GET_MODE (x),
6859                                        XEXP (x, 0), GEN_INT (cval));
6860               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6861                 x = y;
6862             }
6863
6864           break;
6865         }
6866
6867       goto binop;
6868
6869     case PLUS:
6870       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6871          low-order bits (as in an alignment operation) and FOO is already
6872          aligned to that boundary, mask C1 to that boundary as well.
6873          This may eliminate that PLUS and, later, the AND.  */
6874
6875       {
6876         unsigned int width = GET_MODE_BITSIZE (mode);
6877         unsigned HOST_WIDE_INT smask = mask;
6878
6879         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6880            number, sign extend it.  */
6881
6882         if (width < HOST_BITS_PER_WIDE_INT
6883             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6884           smask |= (HOST_WIDE_INT) -1 << width;
6885
6886         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6887             && exact_log2 (- smask) >= 0
6888             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6889             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6890           return force_to_mode (plus_constant (XEXP (x, 0),
6891                                                (INTVAL (XEXP (x, 1)) & smask)),
6892                                 mode, smask, next_select);
6893       }
6894
6895       /* ... fall through ...  */
6896
6897     case MULT:
6898       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6899          most significant bit in MASK since carries from those bits will
6900          affect the bits we are interested in.  */
6901       mask = fuller_mask;
6902       goto binop;
6903
6904     case MINUS:
6905       /* If X is (minus C Y) where C's least set bit is larger than any bit
6906          in the mask, then we may replace with (neg Y).  */
6907       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6908           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6909                                         & -INTVAL (XEXP (x, 0))))
6910               > mask))
6911         {
6912           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6913                                   GET_MODE (x));
6914           return force_to_mode (x, mode, mask, next_select);
6915         }
6916
6917       /* Similarly, if C contains every bit in the fuller_mask, then we may
6918          replace with (not Y).  */
6919       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6920           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6921               == INTVAL (XEXP (x, 0))))
6922         {
6923           x = simplify_gen_unary (NOT, GET_MODE (x),
6924                                   XEXP (x, 1), GET_MODE (x));
6925           return force_to_mode (x, mode, mask, next_select);
6926         }
6927
6928       mask = fuller_mask;
6929       goto binop;
6930
6931     case IOR:
6932     case XOR:
6933       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6934          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6935          operation which may be a bitfield extraction.  Ensure that the
6936          constant we form is not wider than the mode of X.  */
6937
6938       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6939           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6940           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6941           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6942           && GET_CODE (XEXP (x, 1)) == CONST_INT
6943           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6944                + floor_log2 (INTVAL (XEXP (x, 1))))
6945               < GET_MODE_BITSIZE (GET_MODE (x)))
6946           && (INTVAL (XEXP (x, 1))
6947               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6948         {
6949           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6950                           << INTVAL (XEXP (XEXP (x, 0), 1)));
6951           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
6952                                       XEXP (XEXP (x, 0), 0), temp);
6953           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
6954                                    XEXP (XEXP (x, 0), 1));
6955           return force_to_mode (x, mode, mask, next_select);
6956         }
6957
6958     binop:
6959       /* For most binary operations, just propagate into the operation and
6960          change the mode if we have an operation of that mode.  */
6961
6962       op0 = gen_lowpart (op_mode,
6963                          force_to_mode (XEXP (x, 0), mode, mask,
6964                                         next_select));
6965       op1 = gen_lowpart (op_mode,
6966                          force_to_mode (XEXP (x, 1), mode, mask,
6967                                         next_select));
6968
6969       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6970         x = simplify_gen_binary (code, op_mode, op0, op1);
6971       break;
6972
6973     case ASHIFT:
6974       /* For left shifts, do the same, but just for the first operand.
6975          However, we cannot do anything with shifts where we cannot
6976          guarantee that the counts are smaller than the size of the mode
6977          because such a count will have a different meaning in a
6978          wider mode.  */
6979
6980       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6981              && INTVAL (XEXP (x, 1)) >= 0
6982              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6983           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6984                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6985                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6986         break;
6987
6988       /* If the shift count is a constant and we can do arithmetic in
6989          the mode of the shift, refine which bits we need.  Otherwise, use the
6990          conservative form of the mask.  */
6991       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6992           && INTVAL (XEXP (x, 1)) >= 0
6993           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6994           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6995         mask >>= INTVAL (XEXP (x, 1));
6996       else
6997         mask = fuller_mask;
6998
6999       op0 = gen_lowpart (op_mode,
7000                          force_to_mode (XEXP (x, 0), op_mode,
7001                                         mask, next_select));
7002
7003       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7004         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7005       break;
7006
7007     case LSHIFTRT:
7008       /* Here we can only do something if the shift count is a constant,
7009          this shift constant is valid for the host, and we can do arithmetic
7010          in OP_MODE.  */
7011
7012       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7013           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7014           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7015         {
7016           rtx inner = XEXP (x, 0);
7017           unsigned HOST_WIDE_INT inner_mask;
7018
7019           /* Select the mask of the bits we need for the shift operand.  */
7020           inner_mask = mask << INTVAL (XEXP (x, 1));
7021
7022           /* We can only change the mode of the shift if we can do arithmetic
7023              in the mode of the shift and INNER_MASK is no wider than the
7024              width of X's mode.  */
7025           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7026             op_mode = GET_MODE (x);
7027
7028           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7029
7030           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7031             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7032         }
7033
7034       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7035          shift and AND produces only copies of the sign bit (C2 is one less
7036          than a power of two), we can do this with just a shift.  */
7037
7038       if (GET_CODE (x) == LSHIFTRT
7039           && GET_CODE (XEXP (x, 1)) == CONST_INT
7040           /* The shift puts one of the sign bit copies in the least significant
7041              bit.  */
7042           && ((INTVAL (XEXP (x, 1))
7043                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7044               >= GET_MODE_BITSIZE (GET_MODE (x)))
7045           && exact_log2 (mask + 1) >= 0
7046           /* Number of bits left after the shift must be more than the mask
7047              needs.  */
7048           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7049               <= GET_MODE_BITSIZE (GET_MODE (x)))
7050           /* Must be more sign bit copies than the mask needs.  */
7051           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7052               >= exact_log2 (mask + 1)))
7053         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7054                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7055                                           - exact_log2 (mask + 1)));
7056
7057       goto shiftrt;
7058
7059     case ASHIFTRT:
7060       /* If we are just looking for the sign bit, we don't need this shift at
7061          all, even if it has a variable count.  */
7062       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7063           && (mask == ((unsigned HOST_WIDE_INT) 1
7064                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7065         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7066
7067       /* If this is a shift by a constant, get a mask that contains those bits
7068          that are not copies of the sign bit.  We then have two cases:  If
7069          MASK only includes those bits, this can be a logical shift, which may
7070          allow simplifications.  If MASK is a single-bit field not within
7071          those bits, we are requesting a copy of the sign bit and hence can
7072          shift the sign bit to the appropriate location.  */
7073
7074       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7075           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7076         {
7077           int i;
7078
7079           /* If the considered data is wider than HOST_WIDE_INT, we can't
7080              represent a mask for all its bits in a single scalar.
7081              But we only care about the lower bits, so calculate these.  */
7082
7083           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7084             {
7085               nonzero = ~(HOST_WIDE_INT) 0;
7086
7087               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7088                  is the number of bits a full-width mask would have set.
7089                  We need only shift if these are fewer than nonzero can
7090                  hold.  If not, we must keep all bits set in nonzero.  */
7091
7092               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7093                   < HOST_BITS_PER_WIDE_INT)
7094                 nonzero >>= INTVAL (XEXP (x, 1))
7095                             + HOST_BITS_PER_WIDE_INT
7096                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7097             }
7098           else
7099             {
7100               nonzero = GET_MODE_MASK (GET_MODE (x));
7101               nonzero >>= INTVAL (XEXP (x, 1));
7102             }
7103
7104           if ((mask & ~nonzero) == 0)
7105             {
7106               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7107                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7108               if (GET_CODE (x) != ASHIFTRT)
7109                 return force_to_mode (x, mode, mask, next_select);
7110             }
7111
7112           else if ((i = exact_log2 (mask)) >= 0)
7113             {
7114               x = simplify_shift_const
7115                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7116                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7117
7118               if (GET_CODE (x) != ASHIFTRT)
7119                 return force_to_mode (x, mode, mask, next_select);
7120             }
7121         }
7122
7123       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7124          even if the shift count isn't a constant.  */
7125       if (mask == 1)
7126         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7127                                  XEXP (x, 0), XEXP (x, 1));
7128
7129     shiftrt:
7130
7131       /* If this is a zero- or sign-extension operation that just affects bits
7132          we don't care about, remove it.  Be sure the call above returned
7133          something that is still a shift.  */
7134
7135       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7136           && GET_CODE (XEXP (x, 1)) == CONST_INT
7137           && INTVAL (XEXP (x, 1)) >= 0
7138           && (INTVAL (XEXP (x, 1))
7139               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7140           && GET_CODE (XEXP (x, 0)) == ASHIFT
7141           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7142         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7143                               next_select);
7144
7145       break;
7146
7147     case ROTATE:
7148     case ROTATERT:
7149       /* If the shift count is constant and we can do computations
7150          in the mode of X, compute where the bits we care about are.
7151          Otherwise, we can't do anything.  Don't change the mode of
7152          the shift or propagate MODE into the shift, though.  */
7153       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7154           && INTVAL (XEXP (x, 1)) >= 0)
7155         {
7156           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7157                                             GET_MODE (x), GEN_INT (mask),
7158                                             XEXP (x, 1));
7159           if (temp && GET_CODE (temp) == CONST_INT)
7160             SUBST (XEXP (x, 0),
7161                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7162                                   INTVAL (temp), next_select));
7163         }
7164       break;
7165
7166     case NEG:
7167       /* If we just want the low-order bit, the NEG isn't needed since it
7168          won't change the low-order bit.  */
7169       if (mask == 1)
7170         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7171
7172       /* We need any bits less significant than the most significant bit in
7173          MASK since carries from those bits will affect the bits we are
7174          interested in.  */
7175       mask = fuller_mask;
7176       goto unop;
7177
7178     case NOT:
7179       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7180          same as the XOR case above.  Ensure that the constant we form is not
7181          wider than the mode of X.  */
7182
7183       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7184           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7185           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7186           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7187               < GET_MODE_BITSIZE (GET_MODE (x)))
7188           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7189         {
7190           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7191                                GET_MODE (x));
7192           temp = simplify_gen_binary (XOR, GET_MODE (x),
7193                                       XEXP (XEXP (x, 0), 0), temp);
7194           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7195                                    temp, XEXP (XEXP (x, 0), 1));
7196
7197           return force_to_mode (x, mode, mask, next_select);
7198         }
7199
7200       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7201          use the full mask inside the NOT.  */
7202       mask = fuller_mask;
7203
7204     unop:
7205       op0 = gen_lowpart (op_mode,
7206                          force_to_mode (XEXP (x, 0), mode, mask,
7207                                         next_select));
7208       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7209         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7210       break;
7211
7212     case NE:
7213       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7214          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7215          which is equal to STORE_FLAG_VALUE.  */
7216       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7217           && GET_MODE (XEXP (x, 0)) == mode
7218           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7219           && (nonzero_bits (XEXP (x, 0), mode)
7220               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7221         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7222
7223       break;
7224
7225     case IF_THEN_ELSE:
7226       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7227          written in a narrower mode.  We play it safe and do not do so.  */
7228
7229       SUBST (XEXP (x, 1),
7230              gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 1), mode,
7231                                                        mask, next_select)));
7232       SUBST (XEXP (x, 2),
7233              gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 2), mode,
7234                                                        mask, next_select)));
7235       break;
7236
7237     default:
7238       break;
7239     }
7240
7241   /* Ensure we return a value of the proper mode.  */
7242   return gen_lowpart (mode, x);
7243 }
7244 \f
7245 /* Return nonzero if X is an expression that has one of two values depending on
7246    whether some other value is zero or nonzero.  In that case, we return the
7247    value that is being tested, *PTRUE is set to the value if the rtx being
7248    returned has a nonzero value, and *PFALSE is set to the other alternative.
7249
7250    If we return zero, we set *PTRUE and *PFALSE to X.  */
7251
7252 static rtx
7253 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7254 {
7255   enum machine_mode mode = GET_MODE (x);
7256   enum rtx_code code = GET_CODE (x);
7257   rtx cond0, cond1, true0, true1, false0, false1;
7258   unsigned HOST_WIDE_INT nz;
7259
7260   /* If we are comparing a value against zero, we are done.  */
7261   if ((code == NE || code == EQ)
7262       && XEXP (x, 1) == const0_rtx)
7263     {
7264       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7265       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7266       return XEXP (x, 0);
7267     }
7268
7269   /* If this is a unary operation whose operand has one of two values, apply
7270      our opcode to compute those values.  */
7271   else if (UNARY_P (x)
7272            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7273     {
7274       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7275       *pfalse = simplify_gen_unary (code, mode, false0,
7276                                     GET_MODE (XEXP (x, 0)));
7277       return cond0;
7278     }
7279
7280   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7281      make can't possibly match and would suppress other optimizations.  */
7282   else if (code == COMPARE)
7283     ;
7284
7285   /* If this is a binary operation, see if either side has only one of two
7286      values.  If either one does or if both do and they are conditional on
7287      the same value, compute the new true and false values.  */
7288   else if (BINARY_P (x))
7289     {
7290       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7291       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7292
7293       if ((cond0 != 0 || cond1 != 0)
7294           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7295         {
7296           /* If if_then_else_cond returned zero, then true/false are the
7297              same rtl.  We must copy one of them to prevent invalid rtl
7298              sharing.  */
7299           if (cond0 == 0)
7300             true0 = copy_rtx (true0);
7301           else if (cond1 == 0)
7302             true1 = copy_rtx (true1);
7303
7304           if (COMPARISON_P (x))
7305             {
7306               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7307                                                 true0, true1);
7308               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7309                                                  false0, false1);
7310              }
7311           else
7312             {
7313               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7314               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7315             }
7316
7317           return cond0 ? cond0 : cond1;
7318         }
7319
7320       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7321          operands is zero when the other is nonzero, and vice-versa,
7322          and STORE_FLAG_VALUE is 1 or -1.  */
7323
7324       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7325           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7326               || code == UMAX)
7327           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7328         {
7329           rtx op0 = XEXP (XEXP (x, 0), 1);
7330           rtx op1 = XEXP (XEXP (x, 1), 1);
7331
7332           cond0 = XEXP (XEXP (x, 0), 0);
7333           cond1 = XEXP (XEXP (x, 1), 0);
7334
7335           if (COMPARISON_P (cond0)
7336               && COMPARISON_P (cond1)
7337               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7338                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7339                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7340                   || ((swap_condition (GET_CODE (cond0))
7341                        == reversed_comparison_code (cond1, NULL))
7342                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7343                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7344               && ! side_effects_p (x))
7345             {
7346               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7347               *pfalse = simplify_gen_binary (MULT, mode,
7348                                              (code == MINUS
7349                                               ? simplify_gen_unary (NEG, mode,
7350                                                                     op1, mode)
7351                                               : op1),
7352                                               const_true_rtx);
7353               return cond0;
7354             }
7355         }
7356
7357       /* Similarly for MULT, AND and UMIN, except that for these the result
7358          is always zero.  */
7359       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7360           && (code == MULT || code == AND || code == UMIN)
7361           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7362         {
7363           cond0 = XEXP (XEXP (x, 0), 0);
7364           cond1 = XEXP (XEXP (x, 1), 0);
7365
7366           if (COMPARISON_P (cond0)
7367               && COMPARISON_P (cond1)
7368               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7369                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7370                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7371                   || ((swap_condition (GET_CODE (cond0))
7372                        == reversed_comparison_code (cond1, NULL))
7373                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7374                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7375               && ! side_effects_p (x))
7376             {
7377               *ptrue = *pfalse = const0_rtx;
7378               return cond0;
7379             }
7380         }
7381     }
7382
7383   else if (code == IF_THEN_ELSE)
7384     {
7385       /* If we have IF_THEN_ELSE already, extract the condition and
7386          canonicalize it if it is NE or EQ.  */
7387       cond0 = XEXP (x, 0);
7388       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7389       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7390         return XEXP (cond0, 0);
7391       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7392         {
7393           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7394           return XEXP (cond0, 0);
7395         }
7396       else
7397         return cond0;
7398     }
7399
7400   /* If X is a SUBREG, we can narrow both the true and false values
7401      if the inner expression, if there is a condition.  */
7402   else if (code == SUBREG
7403            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7404                                                &true0, &false0)))
7405     {
7406       true0 = simplify_gen_subreg (mode, true0,
7407                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7408       false0 = simplify_gen_subreg (mode, false0,
7409                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7410       if (true0 && false0)
7411         {
7412           *ptrue = true0;
7413           *pfalse = false0;
7414           return cond0;
7415         }
7416     }
7417
7418   /* If X is a constant, this isn't special and will cause confusions
7419      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7420   else if (CONSTANT_P (x)
7421            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7422     ;
7423
7424   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7425      will be least confusing to the rest of the compiler.  */
7426   else if (mode == BImode)
7427     {
7428       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7429       return x;
7430     }
7431
7432   /* If X is known to be either 0 or -1, those are the true and
7433      false values when testing X.  */
7434   else if (x == constm1_rtx || x == const0_rtx
7435            || (mode != VOIDmode
7436                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7437     {
7438       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7439       return x;
7440     }
7441
7442   /* Likewise for 0 or a single bit.  */
7443   else if (SCALAR_INT_MODE_P (mode)
7444            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7445            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7446     {
7447       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7448       return x;
7449     }
7450
7451   /* Otherwise fail; show no condition with true and false values the same.  */
7452   *ptrue = *pfalse = x;
7453   return 0;
7454 }
7455 \f
7456 /* Return the value of expression X given the fact that condition COND
7457    is known to be true when applied to REG as its first operand and VAL
7458    as its second.  X is known to not be shared and so can be modified in
7459    place.
7460
7461    We only handle the simplest cases, and specifically those cases that
7462    arise with IF_THEN_ELSE expressions.  */
7463
7464 static rtx
7465 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7466 {
7467   enum rtx_code code = GET_CODE (x);
7468   rtx temp;
7469   const char *fmt;
7470   int i, j;
7471
7472   if (side_effects_p (x))
7473     return x;
7474
7475   /* If either operand of the condition is a floating point value,
7476      then we have to avoid collapsing an EQ comparison.  */
7477   if (cond == EQ
7478       && rtx_equal_p (x, reg)
7479       && ! FLOAT_MODE_P (GET_MODE (x))
7480       && ! FLOAT_MODE_P (GET_MODE (val)))
7481     return val;
7482
7483   if (cond == UNEQ && rtx_equal_p (x, reg))
7484     return val;
7485
7486   /* If X is (abs REG) and we know something about REG's relationship
7487      with zero, we may be able to simplify this.  */
7488
7489   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7490     switch (cond)
7491       {
7492       case GE:  case GT:  case EQ:
7493         return XEXP (x, 0);
7494       case LT:  case LE:
7495         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7496                                    XEXP (x, 0),
7497                                    GET_MODE (XEXP (x, 0)));
7498       default:
7499         break;
7500       }
7501
7502   /* The only other cases we handle are MIN, MAX, and comparisons if the
7503      operands are the same as REG and VAL.  */
7504
7505   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7506     {
7507       if (rtx_equal_p (XEXP (x, 0), val))
7508         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7509
7510       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7511         {
7512           if (COMPARISON_P (x))
7513             {
7514               if (comparison_dominates_p (cond, code))
7515                 return const_true_rtx;
7516
7517               code = reversed_comparison_code (x, NULL);
7518               if (code != UNKNOWN
7519                   && comparison_dominates_p (cond, code))
7520                 return const0_rtx;
7521               else
7522                 return x;
7523             }
7524           else if (code == SMAX || code == SMIN
7525                    || code == UMIN || code == UMAX)
7526             {
7527               int unsignedp = (code == UMIN || code == UMAX);
7528
7529               /* Do not reverse the condition when it is NE or EQ.
7530                  This is because we cannot conclude anything about
7531                  the value of 'SMAX (x, y)' when x is not equal to y,
7532                  but we can when x equals y.  */
7533               if ((code == SMAX || code == UMAX)
7534                   && ! (cond == EQ || cond == NE))
7535                 cond = reverse_condition (cond);
7536
7537               switch (cond)
7538                 {
7539                 case GE:   case GT:
7540                   return unsignedp ? x : XEXP (x, 1);
7541                 case LE:   case LT:
7542                   return unsignedp ? x : XEXP (x, 0);
7543                 case GEU:  case GTU:
7544                   return unsignedp ? XEXP (x, 1) : x;
7545                 case LEU:  case LTU:
7546                   return unsignedp ? XEXP (x, 0) : x;
7547                 default:
7548                   break;
7549                 }
7550             }
7551         }
7552     }
7553   else if (code == SUBREG)
7554     {
7555       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7556       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7557
7558       if (SUBREG_REG (x) != r)
7559         {
7560           /* We must simplify subreg here, before we lose track of the
7561              original inner_mode.  */
7562           new = simplify_subreg (GET_MODE (x), r,
7563                                  inner_mode, SUBREG_BYTE (x));
7564           if (new)
7565             return new;
7566           else
7567             SUBST (SUBREG_REG (x), r);
7568         }
7569
7570       return x;
7571     }
7572   /* We don't have to handle SIGN_EXTEND here, because even in the
7573      case of replacing something with a modeless CONST_INT, a
7574      CONST_INT is already (supposed to be) a valid sign extension for
7575      its narrower mode, which implies it's already properly
7576      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7577      story is different.  */
7578   else if (code == ZERO_EXTEND)
7579     {
7580       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7581       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7582
7583       if (XEXP (x, 0) != r)
7584         {
7585           /* We must simplify the zero_extend here, before we lose
7586              track of the original inner_mode.  */
7587           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7588                                           r, inner_mode);
7589           if (new)
7590             return new;
7591           else
7592             SUBST (XEXP (x, 0), r);
7593         }
7594
7595       return x;
7596     }
7597
7598   fmt = GET_RTX_FORMAT (code);
7599   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7600     {
7601       if (fmt[i] == 'e')
7602         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7603       else if (fmt[i] == 'E')
7604         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7605           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7606                                                 cond, reg, val));
7607     }
7608
7609   return x;
7610 }
7611 \f
7612 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7613    assignment as a field assignment.  */
7614
7615 static int
7616 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7617 {
7618   if (x == y || rtx_equal_p (x, y))
7619     return 1;
7620
7621   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7622     return 0;
7623
7624   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7625      Note that all SUBREGs of MEM are paradoxical; otherwise they
7626      would have been rewritten.  */
7627   if (MEM_P (x) && GET_CODE (y) == SUBREG
7628       && MEM_P (SUBREG_REG (y))
7629       && rtx_equal_p (SUBREG_REG (y),
7630                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7631     return 1;
7632
7633   if (MEM_P (y) && GET_CODE (x) == SUBREG
7634       && MEM_P (SUBREG_REG (x))
7635       && rtx_equal_p (SUBREG_REG (x),
7636                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7637     return 1;
7638
7639   /* We used to see if get_last_value of X and Y were the same but that's
7640      not correct.  In one direction, we'll cause the assignment to have
7641      the wrong destination and in the case, we'll import a register into this
7642      insn that might have already have been dead.   So fail if none of the
7643      above cases are true.  */
7644   return 0;
7645 }
7646 \f
7647 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7648    Return that assignment if so.
7649
7650    We only handle the most common cases.  */
7651
7652 static rtx
7653 make_field_assignment (rtx x)
7654 {
7655   rtx dest = SET_DEST (x);
7656   rtx src = SET_SRC (x);
7657   rtx assign;
7658   rtx rhs, lhs;
7659   HOST_WIDE_INT c1;
7660   HOST_WIDE_INT pos;
7661   unsigned HOST_WIDE_INT len;
7662   rtx other;
7663   enum machine_mode mode;
7664
7665   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7666      a clear of a one-bit field.  We will have changed it to
7667      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7668      for a SUBREG.  */
7669
7670   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7671       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7672       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7673       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7674     {
7675       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7676                                 1, 1, 1, 0);
7677       if (assign != 0)
7678         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7679       return x;
7680     }
7681
7682   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7683       && subreg_lowpart_p (XEXP (src, 0))
7684       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7685           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7686       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7687       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7688       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7689       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7690     {
7691       assign = make_extraction (VOIDmode, dest, 0,
7692                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7693                                 1, 1, 1, 0);
7694       if (assign != 0)
7695         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7696       return x;
7697     }
7698
7699   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7700      one-bit field.  */
7701   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7702       && XEXP (XEXP (src, 0), 0) == const1_rtx
7703       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7704     {
7705       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7706                                 1, 1, 1, 0);
7707       if (assign != 0)
7708         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7709       return x;
7710     }
7711
7712   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7713      SRC is an AND with all bits of that field set, then we can discard
7714      the AND.  */
7715   if (GET_CODE (dest) == ZERO_EXTRACT
7716       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7717       && GET_CODE (src) == AND
7718       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7719     {
7720       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7721       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7722       unsigned HOST_WIDE_INT ze_mask;
7723
7724       if (width >= HOST_BITS_PER_WIDE_INT)
7725         ze_mask = -1;
7726       else
7727         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7728
7729       /* Complete overlap.  We can remove the source AND.  */
7730       if ((and_mask & ze_mask) == ze_mask)
7731         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7732
7733       /* Partial overlap.  We can reduce the source AND.  */
7734       if ((and_mask & ze_mask) != and_mask)
7735         {
7736           mode = GET_MODE (src);
7737           src = gen_rtx_AND (mode, XEXP (src, 0),
7738                              gen_int_mode (and_mask & ze_mask, mode));
7739           return gen_rtx_SET (VOIDmode, dest, src);
7740         }
7741     }
7742
7743   /* The other case we handle is assignments into a constant-position
7744      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7745      a mask that has all one bits except for a group of zero bits and
7746      OTHER is known to have zeros where C1 has ones, this is such an
7747      assignment.  Compute the position and length from C1.  Shift OTHER
7748      to the appropriate position, force it to the required mode, and
7749      make the extraction.  Check for the AND in both operands.  */
7750
7751   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7752     return x;
7753
7754   rhs = expand_compound_operation (XEXP (src, 0));
7755   lhs = expand_compound_operation (XEXP (src, 1));
7756
7757   if (GET_CODE (rhs) == AND
7758       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7759       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7760     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7761   else if (GET_CODE (lhs) == AND
7762            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7763            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7764     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7765   else
7766     return x;
7767
7768   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7769   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7770       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7771       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7772     return x;
7773
7774   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7775   if (assign == 0)
7776     return x;
7777
7778   /* The mode to use for the source is the mode of the assignment, or of
7779      what is inside a possible STRICT_LOW_PART.  */
7780   mode = (GET_CODE (assign) == STRICT_LOW_PART
7781           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7782
7783   /* Shift OTHER right POS places and make it the source, restricting it
7784      to the proper length and mode.  */
7785
7786   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7787                                                      GET_MODE (src),
7788                                                      other, pos),
7789                                dest);
7790   src = force_to_mode (src, mode,
7791                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7792                        ? ~(unsigned HOST_WIDE_INT) 0
7793                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7794                        0);
7795
7796   /* If SRC is masked by an AND that does not make a difference in
7797      the value being stored, strip it.  */
7798   if (GET_CODE (assign) == ZERO_EXTRACT
7799       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7800       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7801       && GET_CODE (src) == AND
7802       && GET_CODE (XEXP (src, 1)) == CONST_INT
7803       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7804           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7805     src = XEXP (src, 0);
7806
7807   return gen_rtx_SET (VOIDmode, assign, src);
7808 }
7809 \f
7810 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7811    if so.  */
7812
7813 static rtx
7814 apply_distributive_law (rtx x)
7815 {
7816   enum rtx_code code = GET_CODE (x);
7817   enum rtx_code inner_code;
7818   rtx lhs, rhs, other;
7819   rtx tem;
7820
7821   /* Distributivity is not true for floating point as it can change the
7822      value.  So we don't do it unless -funsafe-math-optimizations.  */
7823   if (FLOAT_MODE_P (GET_MODE (x))
7824       && ! flag_unsafe_math_optimizations)
7825     return x;
7826
7827   /* The outer operation can only be one of the following:  */
7828   if (code != IOR && code != AND && code != XOR
7829       && code != PLUS && code != MINUS)
7830     return x;
7831
7832   lhs = XEXP (x, 0);
7833   rhs = XEXP (x, 1);
7834
7835   /* If either operand is a primitive we can't do anything, so get out
7836      fast.  */
7837   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7838     return x;
7839
7840   lhs = expand_compound_operation (lhs);
7841   rhs = expand_compound_operation (rhs);
7842   inner_code = GET_CODE (lhs);
7843   if (inner_code != GET_CODE (rhs))
7844     return x;
7845
7846   /* See if the inner and outer operations distribute.  */
7847   switch (inner_code)
7848     {
7849     case LSHIFTRT:
7850     case ASHIFTRT:
7851     case AND:
7852     case IOR:
7853       /* These all distribute except over PLUS.  */
7854       if (code == PLUS || code == MINUS)
7855         return x;
7856       break;
7857
7858     case MULT:
7859       if (code != PLUS && code != MINUS)
7860         return x;
7861       break;
7862
7863     case ASHIFT:
7864       /* This is also a multiply, so it distributes over everything.  */
7865       break;
7866
7867     case SUBREG:
7868       /* Non-paradoxical SUBREGs distributes over all operations,
7869          provided the inner modes and byte offsets are the same, this
7870          is an extraction of a low-order part, we don't convert an fp
7871          operation to int or vice versa, this is not a vector mode,
7872          and we would not be converting a single-word operation into a
7873          multi-word operation.  The latter test is not required, but
7874          it prevents generating unneeded multi-word operations.  Some
7875          of the previous tests are redundant given the latter test,
7876          but are retained because they are required for correctness.
7877
7878          We produce the result slightly differently in this case.  */
7879
7880       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7881           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7882           || ! subreg_lowpart_p (lhs)
7883           || (GET_MODE_CLASS (GET_MODE (lhs))
7884               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7885           || (GET_MODE_SIZE (GET_MODE (lhs))
7886               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7887           || VECTOR_MODE_P (GET_MODE (lhs))
7888           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7889           /* Result might need to be truncated.  Don't change mode if
7890              explicit truncation is needed.  */
7891           || !TRULY_NOOP_TRUNCATION
7892                (GET_MODE_BITSIZE (GET_MODE (x)),
7893                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7894         return x;
7895
7896       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7897                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7898       return gen_lowpart (GET_MODE (x), tem);
7899
7900     default:
7901       return x;
7902     }
7903
7904   /* Set LHS and RHS to the inner operands (A and B in the example
7905      above) and set OTHER to the common operand (C in the example).
7906      There is only one way to do this unless the inner operation is
7907      commutative.  */
7908   if (COMMUTATIVE_ARITH_P (lhs)
7909       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7910     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7911   else if (COMMUTATIVE_ARITH_P (lhs)
7912            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7913     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7914   else if (COMMUTATIVE_ARITH_P (lhs)
7915            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7916     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7917   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7918     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7919   else
7920     return x;
7921
7922   /* Form the new inner operation, seeing if it simplifies first.  */
7923   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
7924
7925   /* There is one exception to the general way of distributing:
7926      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
7927   if (code == XOR && inner_code == IOR)
7928     {
7929       inner_code = AND;
7930       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7931     }
7932
7933   /* We may be able to continuing distributing the result, so call
7934      ourselves recursively on the inner operation before forming the
7935      outer operation, which we return.  */
7936   return simplify_gen_binary (inner_code, GET_MODE (x),
7937                               apply_distributive_law (tem), other);
7938 }
7939
7940 /* See if X is of the form (* (+ A B) C), and if so convert to
7941    (+ (* A C) (* B C)) and try to simplify.
7942
7943    Most of the time, this results in no change.  However, if some of
7944    the operands are the same or inverses of each other, simplifications
7945    will result.
7946
7947    For example, (and (ior A B) (not B)) can occur as the result of
7948    expanding a bit field assignment.  When we apply the distributive
7949    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
7950    which then simplifies to (and (A (not B))).
7951
7952    Note that no checks happen on the validity of applying the inverse
7953    distributive law.  This is pointless since we can do it in the
7954    few places where this routine is called.
7955
7956    N is the index of the term that is decomposed (the arithmetic operation,
7957    i.e. (+ A B) in the first example above).  !N is the index of the term that
7958    is distributed, i.e. of C in the first example above.  */
7959 static rtx
7960 distribute_and_simplify_rtx (rtx x, int n)
7961 {
7962   enum machine_mode mode;
7963   enum rtx_code outer_code, inner_code;
7964   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
7965
7966   decomposed = XEXP (x, n);
7967   if (!ARITHMETIC_P (decomposed))
7968     return NULL_RTX;
7969
7970   mode = GET_MODE (x);
7971   outer_code = GET_CODE (x);
7972   distributed = XEXP (x, !n);
7973
7974   inner_code = GET_CODE (decomposed);
7975   inner_op0 = XEXP (decomposed, 0);
7976   inner_op1 = XEXP (decomposed, 1);
7977
7978   /* Special case (and (xor B C) (not A)), which is equivalent to
7979      (xor (ior A B) (ior A C))  */
7980   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
7981     {
7982       distributed = XEXP (distributed, 0);
7983       outer_code = IOR;
7984     }
7985
7986   if (n == 0)
7987     {
7988       /* Distribute the second term.  */
7989       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
7990       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
7991     }
7992   else
7993     {
7994       /* Distribute the first term.  */
7995       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
7996       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
7997     }
7998
7999   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8000                                                      new_op0, new_op1));
8001   if (GET_CODE (tmp) != outer_code
8002       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8003     return tmp;
8004
8005   return NULL_RTX;
8006 }
8007 \f
8008 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8009    in MODE.  Return an equivalent form, if different from (and VAROP
8010    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8011
8012 static rtx
8013 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8014                           unsigned HOST_WIDE_INT constop)
8015 {
8016   unsigned HOST_WIDE_INT nonzero;
8017   unsigned HOST_WIDE_INT orig_constop;
8018   rtx orig_varop;
8019   int i;
8020
8021   orig_varop = varop;
8022   orig_constop = constop;
8023   if (GET_CODE (varop) == CLOBBER)
8024     return NULL_RTX;
8025
8026   /* Simplify VAROP knowing that we will be only looking at some of the
8027      bits in it.
8028
8029      Note by passing in CONSTOP, we guarantee that the bits not set in
8030      CONSTOP are not significant and will never be examined.  We must
8031      ensure that is the case by explicitly masking out those bits
8032      before returning.  */
8033   varop = force_to_mode (varop, mode, constop, 0);
8034
8035   /* If VAROP is a CLOBBER, we will fail so return it.  */
8036   if (GET_CODE (varop) == CLOBBER)
8037     return varop;
8038
8039   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8040      to VAROP and return the new constant.  */
8041   if (GET_CODE (varop) == CONST_INT)
8042     return gen_int_mode (INTVAL (varop) & constop, mode);
8043
8044   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8045      a call to nonzero_bits, here we don't care about bits outside
8046      MODE.  */
8047
8048   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8049
8050   /* Turn off all bits in the constant that are known to already be zero.
8051      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8052      which is tested below.  */
8053
8054   constop &= nonzero;
8055
8056   /* If we don't have any bits left, return zero.  */
8057   if (constop == 0)
8058     return const0_rtx;
8059
8060   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8061      a power of two, we can replace this with an ASHIFT.  */
8062   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8063       && (i = exact_log2 (constop)) >= 0)
8064     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8065
8066   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8067      or XOR, then try to apply the distributive law.  This may eliminate
8068      operations if either branch can be simplified because of the AND.
8069      It may also make some cases more complex, but those cases probably
8070      won't match a pattern either with or without this.  */
8071
8072   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8073     return
8074       gen_lowpart
8075         (mode,
8076          apply_distributive_law
8077          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8078                                simplify_and_const_int (NULL_RTX,
8079                                                        GET_MODE (varop),
8080                                                        XEXP (varop, 0),
8081                                                        constop),
8082                                simplify_and_const_int (NULL_RTX,
8083                                                        GET_MODE (varop),
8084                                                        XEXP (varop, 1),
8085                                                        constop))));
8086
8087   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8088      the AND and see if one of the operands simplifies to zero.  If so, we
8089      may eliminate it.  */
8090
8091   if (GET_CODE (varop) == PLUS
8092       && exact_log2 (constop + 1) >= 0)
8093     {
8094       rtx o0, o1;
8095
8096       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8097       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8098       if (o0 == const0_rtx)
8099         return o1;
8100       if (o1 == const0_rtx)
8101         return o0;
8102     }
8103
8104   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8105   varop = gen_lowpart (mode, varop);
8106   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8107     return NULL_RTX;
8108
8109   /* If we are only masking insignificant bits, return VAROP.  */
8110   if (constop == nonzero)
8111     return varop;
8112
8113   if (varop == orig_varop && constop == orig_constop)
8114     return NULL_RTX;
8115
8116   /* Otherwise, return an AND.  */
8117   constop = trunc_int_for_mode (constop, mode);
8118   return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8119 }
8120
8121
8122 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8123    in MODE.
8124
8125    Return an equivalent form, if different from X.  Otherwise, return X.  If
8126    X is zero, we are to always construct the equivalent form.  */
8127
8128 static rtx
8129 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8130                         unsigned HOST_WIDE_INT constop)
8131 {
8132   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8133   if (tem)
8134     return tem;
8135
8136   if (!x)
8137     x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8138   if (GET_MODE (x) != mode)
8139     x = gen_lowpart (mode, x);
8140   return x;
8141 }
8142 \f
8143 /* Given a REG, X, compute which bits in X can be nonzero.
8144    We don't care about bits outside of those defined in MODE.
8145
8146    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8147    a shift, AND, or zero_extract, we can do better.  */
8148
8149 static rtx
8150 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8151                               rtx known_x ATTRIBUTE_UNUSED,
8152                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8153                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8154                               unsigned HOST_WIDE_INT *nonzero)
8155 {
8156   rtx tem;
8157
8158   /* If X is a register whose nonzero bits value is current, use it.
8159      Otherwise, if X is a register whose value we can find, use that
8160      value.  Otherwise, use the previously-computed global nonzero bits
8161      for this register.  */
8162
8163   if (reg_stat[REGNO (x)].last_set_value != 0
8164       && (reg_stat[REGNO (x)].last_set_mode == mode
8165           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8166               && GET_MODE_CLASS (mode) == MODE_INT))
8167       && (reg_stat[REGNO (x)].last_set_label == label_tick
8168           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8169               && REG_N_SETS (REGNO (x)) == 1
8170               && ! REGNO_REG_SET_P
8171                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8172                   REGNO (x))))
8173       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8174     {
8175       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8176       return NULL;
8177     }
8178
8179   tem = get_last_value (x);
8180
8181   if (tem)
8182     {
8183 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8184       /* If X is narrower than MODE and TEM is a non-negative
8185          constant that would appear negative in the mode of X,
8186          sign-extend it for use in reg_nonzero_bits because some
8187          machines (maybe most) will actually do the sign-extension
8188          and this is the conservative approach.
8189
8190          ??? For 2.5, try to tighten up the MD files in this regard
8191          instead of this kludge.  */
8192
8193       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8194           && GET_CODE (tem) == CONST_INT
8195           && INTVAL (tem) > 0
8196           && 0 != (INTVAL (tem)
8197                    & ((HOST_WIDE_INT) 1
8198                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8199         tem = GEN_INT (INTVAL (tem)
8200                        | ((HOST_WIDE_INT) (-1)
8201                           << GET_MODE_BITSIZE (GET_MODE (x))));
8202 #endif
8203       return tem;
8204     }
8205   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8206     {
8207       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8208
8209       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8210         /* We don't know anything about the upper bits.  */
8211         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8212       *nonzero &= mask;
8213     }
8214
8215   return NULL;
8216 }
8217
8218 /* Return the number of bits at the high-order end of X that are known to
8219    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8220    VOIDmode, X will be used in its own mode.  The returned value  will always
8221    be between 1 and the number of bits in MODE.  */
8222
8223 static rtx
8224 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8225                                      rtx known_x ATTRIBUTE_UNUSED,
8226                                      enum machine_mode known_mode
8227                                      ATTRIBUTE_UNUSED,
8228                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8229                                      unsigned int *result)
8230 {
8231   rtx tem;
8232
8233   if (reg_stat[REGNO (x)].last_set_value != 0
8234       && reg_stat[REGNO (x)].last_set_mode == mode
8235       && (reg_stat[REGNO (x)].last_set_label == label_tick
8236           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8237               && REG_N_SETS (REGNO (x)) == 1
8238               && ! REGNO_REG_SET_P
8239                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8240                   REGNO (x))))
8241       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8242     {
8243       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8244       return NULL;
8245     }
8246
8247   tem = get_last_value (x);
8248   if (tem != 0)
8249     return tem;
8250
8251   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8252       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8253     *result = reg_stat[REGNO (x)].sign_bit_copies;
8254
8255   return NULL;
8256 }
8257 \f
8258 /* Return the number of "extended" bits there are in X, when interpreted
8259    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8260    unsigned quantities, this is the number of high-order zero bits.
8261    For signed quantities, this is the number of copies of the sign bit
8262    minus 1.  In both case, this function returns the number of "spare"
8263    bits.  For example, if two quantities for which this function returns
8264    at least 1 are added, the addition is known not to overflow.
8265
8266    This function will always return 0 unless called during combine, which
8267    implies that it must be called from a define_split.  */
8268
8269 unsigned int
8270 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8271 {
8272   if (nonzero_sign_valid == 0)
8273     return 0;
8274
8275   return (unsignedp
8276           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8277              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8278                                - floor_log2 (nonzero_bits (x, mode)))
8279              : 0)
8280           : num_sign_bit_copies (x, mode) - 1);
8281 }
8282 \f
8283 /* This function is called from `simplify_shift_const' to merge two
8284    outer operations.  Specifically, we have already found that we need
8285    to perform operation *POP0 with constant *PCONST0 at the outermost
8286    position.  We would now like to also perform OP1 with constant CONST1
8287    (with *POP0 being done last).
8288
8289    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8290    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8291    complement the innermost operand, otherwise it is unchanged.
8292
8293    MODE is the mode in which the operation will be done.  No bits outside
8294    the width of this mode matter.  It is assumed that the width of this mode
8295    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8296
8297    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8298    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8299    result is simply *PCONST0.
8300
8301    If the resulting operation cannot be expressed as one operation, we
8302    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8303
8304 static int
8305 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8306 {
8307   enum rtx_code op0 = *pop0;
8308   HOST_WIDE_INT const0 = *pconst0;
8309
8310   const0 &= GET_MODE_MASK (mode);
8311   const1 &= GET_MODE_MASK (mode);
8312
8313   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8314   if (op0 == AND)
8315     const1 &= const0;
8316
8317   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8318      if OP0 is SET.  */
8319
8320   if (op1 == UNKNOWN || op0 == SET)
8321     return 1;
8322
8323   else if (op0 == UNKNOWN)
8324     op0 = op1, const0 = const1;
8325
8326   else if (op0 == op1)
8327     {
8328       switch (op0)
8329         {
8330         case AND:
8331           const0 &= const1;
8332           break;
8333         case IOR:
8334           const0 |= const1;
8335           break;
8336         case XOR:
8337           const0 ^= const1;
8338           break;
8339         case PLUS:
8340           const0 += const1;
8341           break;
8342         case NEG:
8343           op0 = UNKNOWN;
8344           break;
8345         default:
8346           break;
8347         }
8348     }
8349
8350   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8351   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8352     return 0;
8353
8354   /* If the two constants aren't the same, we can't do anything.  The
8355      remaining six cases can all be done.  */
8356   else if (const0 != const1)
8357     return 0;
8358
8359   else
8360     switch (op0)
8361       {
8362       case IOR:
8363         if (op1 == AND)
8364           /* (a & b) | b == b */
8365           op0 = SET;
8366         else /* op1 == XOR */
8367           /* (a ^ b) | b == a | b */
8368           {;}
8369         break;
8370
8371       case XOR:
8372         if (op1 == AND)
8373           /* (a & b) ^ b == (~a) & b */
8374           op0 = AND, *pcomp_p = 1;
8375         else /* op1 == IOR */
8376           /* (a | b) ^ b == a & ~b */
8377           op0 = AND, const0 = ~const0;
8378         break;
8379
8380       case AND:
8381         if (op1 == IOR)
8382           /* (a | b) & b == b */
8383         op0 = SET;
8384         else /* op1 == XOR */
8385           /* (a ^ b) & b) == (~a) & b */
8386           *pcomp_p = 1;
8387         break;
8388       default:
8389         break;
8390       }
8391
8392   /* Check for NO-OP cases.  */
8393   const0 &= GET_MODE_MASK (mode);
8394   if (const0 == 0
8395       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8396     op0 = UNKNOWN;
8397   else if (const0 == 0 && op0 == AND)
8398     op0 = SET;
8399   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8400            && op0 == AND)
8401     op0 = UNKNOWN;
8402
8403   /* ??? Slightly redundant with the above mask, but not entirely.
8404      Moving this above means we'd have to sign-extend the mode mask
8405      for the final test.  */
8406   const0 = trunc_int_for_mode (const0, mode);
8407
8408   *pop0 = op0;
8409   *pconst0 = const0;
8410
8411   return 1;
8412 }
8413 \f
8414 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8415    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8416    simplify it.  Otherwise, return a simplified value.
8417
8418    The shift is normally computed in the widest mode we find in VAROP, as
8419    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8420    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8421
8422 static rtx
8423 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8424                         rtx varop, int orig_count)
8425 {
8426   enum rtx_code orig_code = code;
8427   rtx orig_varop = varop;
8428   int count;
8429   enum machine_mode mode = result_mode;
8430   enum machine_mode shift_mode, tmode;
8431   unsigned int mode_words
8432     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8433   /* We form (outer_op (code varop count) (outer_const)).  */
8434   enum rtx_code outer_op = UNKNOWN;
8435   HOST_WIDE_INT outer_const = 0;
8436   int complement_p = 0;
8437   rtx new, x;
8438
8439   /* Make sure and truncate the "natural" shift on the way in.  We don't
8440      want to do this inside the loop as it makes it more difficult to
8441      combine shifts.  */
8442   if (SHIFT_COUNT_TRUNCATED)
8443     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8444
8445   /* If we were given an invalid count, don't do anything except exactly
8446      what was requested.  */
8447
8448   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8449     return NULL_RTX;
8450
8451   count = orig_count;
8452
8453   /* Unless one of the branches of the `if' in this loop does a `continue',
8454      we will `break' the loop after the `if'.  */
8455
8456   while (count != 0)
8457     {
8458       /* If we have an operand of (clobber (const_int 0)), fail.  */
8459       if (GET_CODE (varop) == CLOBBER)
8460         return NULL_RTX;
8461
8462       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8463          here would cause an infinite loop.  */
8464       if (complement_p)
8465         break;
8466
8467       /* Convert ROTATERT to ROTATE.  */
8468       if (code == ROTATERT)
8469         {
8470           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8471           code = ROTATE;
8472           if (VECTOR_MODE_P (result_mode))
8473             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8474           else
8475             count = bitsize - count;
8476         }
8477
8478       /* We need to determine what mode we will do the shift in.  If the
8479          shift is a right shift or a ROTATE, we must always do it in the mode
8480          it was originally done in.  Otherwise, we can do it in MODE, the
8481          widest mode encountered.  */
8482       shift_mode
8483         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8484            ? result_mode : mode);
8485
8486       /* Handle cases where the count is greater than the size of the mode
8487          minus 1.  For ASHIFT, use the size minus one as the count (this can
8488          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8489          take the count modulo the size.  For other shifts, the result is
8490          zero.
8491
8492          Since these shifts are being produced by the compiler by combining
8493          multiple operations, each of which are defined, we know what the
8494          result is supposed to be.  */
8495
8496       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8497         {
8498           if (code == ASHIFTRT)
8499             count = GET_MODE_BITSIZE (shift_mode) - 1;
8500           else if (code == ROTATE || code == ROTATERT)
8501             count %= GET_MODE_BITSIZE (shift_mode);
8502           else
8503             {
8504               /* We can't simply return zero because there may be an
8505                  outer op.  */
8506               varop = const0_rtx;
8507               count = 0;
8508               break;
8509             }
8510         }
8511
8512       /* An arithmetic right shift of a quantity known to be -1 or 0
8513          is a no-op.  */
8514       if (code == ASHIFTRT
8515           && (num_sign_bit_copies (varop, shift_mode)
8516               == GET_MODE_BITSIZE (shift_mode)))
8517         {
8518           count = 0;
8519           break;
8520         }
8521
8522       /* If we are doing an arithmetic right shift and discarding all but
8523          the sign bit copies, this is equivalent to doing a shift by the
8524          bitsize minus one.  Convert it into that shift because it will often
8525          allow other simplifications.  */
8526
8527       if (code == ASHIFTRT
8528           && (count + num_sign_bit_copies (varop, shift_mode)
8529               >= GET_MODE_BITSIZE (shift_mode)))
8530         count = GET_MODE_BITSIZE (shift_mode) - 1;
8531
8532       /* We simplify the tests below and elsewhere by converting
8533          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8534          `make_compound_operation' will convert it to an ASHIFTRT for
8535          those machines (such as VAX) that don't have an LSHIFTRT.  */
8536       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8537           && code == ASHIFTRT
8538           && ((nonzero_bits (varop, shift_mode)
8539                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8540               == 0))
8541         code = LSHIFTRT;
8542
8543       if (code == LSHIFTRT
8544           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8545           && !(nonzero_bits (varop, shift_mode) >> count))
8546         varop = const0_rtx;
8547       if (code == ASHIFT
8548           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8549           && !((nonzero_bits (varop, shift_mode) << count)
8550                & GET_MODE_MASK (shift_mode)))
8551         varop = const0_rtx;
8552
8553       switch (GET_CODE (varop))
8554         {
8555         case SIGN_EXTEND:
8556         case ZERO_EXTEND:
8557         case SIGN_EXTRACT:
8558         case ZERO_EXTRACT:
8559           new = expand_compound_operation (varop);
8560           if (new != varop)
8561             {
8562               varop = new;
8563               continue;
8564             }
8565           break;
8566
8567         case MEM:
8568           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8569              minus the width of a smaller mode, we can do this with a
8570              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8571           if ((code == ASHIFTRT || code == LSHIFTRT)
8572               && ! mode_dependent_address_p (XEXP (varop, 0))
8573               && ! MEM_VOLATILE_P (varop)
8574               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8575                                          MODE_INT, 1)) != BLKmode)
8576             {
8577               new = adjust_address_nv (varop, tmode,
8578                                        BYTES_BIG_ENDIAN ? 0
8579                                        : count / BITS_PER_UNIT);
8580
8581               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8582                                      : ZERO_EXTEND, mode, new);
8583               count = 0;
8584               continue;
8585             }
8586           break;
8587
8588         case USE:
8589           /* Similar to the case above, except that we can only do this if
8590              the resulting mode is the same as that of the underlying
8591              MEM and adjust the address depending on the *bits* endianness
8592              because of the way that bit-field extract insns are defined.  */
8593           if ((code == ASHIFTRT || code == LSHIFTRT)
8594               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8595                                          MODE_INT, 1)) != BLKmode
8596               && tmode == GET_MODE (XEXP (varop, 0)))
8597             {
8598               if (BITS_BIG_ENDIAN)
8599                 new = XEXP (varop, 0);
8600               else
8601                 {
8602                   new = copy_rtx (XEXP (varop, 0));
8603                   SUBST (XEXP (new, 0),
8604                          plus_constant (XEXP (new, 0),
8605                                         count / BITS_PER_UNIT));
8606                 }
8607
8608               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8609                                      : ZERO_EXTEND, mode, new);
8610               count = 0;
8611               continue;
8612             }
8613           break;
8614
8615         case SUBREG:
8616           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8617              the same number of words as what we've seen so far.  Then store
8618              the widest mode in MODE.  */
8619           if (subreg_lowpart_p (varop)
8620               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8621                   > GET_MODE_SIZE (GET_MODE (varop)))
8622               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8623                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8624                  == mode_words)
8625             {
8626               varop = SUBREG_REG (varop);
8627               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8628                 mode = GET_MODE (varop);
8629               continue;
8630             }
8631           break;
8632
8633         case MULT:
8634           /* Some machines use MULT instead of ASHIFT because MULT
8635              is cheaper.  But it is still better on those machines to
8636              merge two shifts into one.  */
8637           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8638               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8639             {
8640               varop
8641                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8642                                        XEXP (varop, 0),
8643                                        GEN_INT (exact_log2 (
8644                                                 INTVAL (XEXP (varop, 1)))));
8645               continue;
8646             }
8647           break;
8648
8649         case UDIV:
8650           /* Similar, for when divides are cheaper.  */
8651           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8652               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8653             {
8654               varop
8655                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8656                                        XEXP (varop, 0),
8657                                        GEN_INT (exact_log2 (
8658                                                 INTVAL (XEXP (varop, 1)))));
8659               continue;
8660             }
8661           break;
8662
8663         case ASHIFTRT:
8664           /* If we are extracting just the sign bit of an arithmetic
8665              right shift, that shift is not needed.  However, the sign
8666              bit of a wider mode may be different from what would be
8667              interpreted as the sign bit in a narrower mode, so, if
8668              the result is narrower, don't discard the shift.  */
8669           if (code == LSHIFTRT
8670               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8671               && (GET_MODE_BITSIZE (result_mode)
8672                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8673             {
8674               varop = XEXP (varop, 0);
8675               continue;
8676             }
8677
8678           /* ... fall through ...  */
8679
8680         case LSHIFTRT:
8681         case ASHIFT:
8682         case ROTATE:
8683           /* Here we have two nested shifts.  The result is usually the
8684              AND of a new shift with a mask.  We compute the result below.  */
8685           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8686               && INTVAL (XEXP (varop, 1)) >= 0
8687               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8688               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8689               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8690             {
8691               enum rtx_code first_code = GET_CODE (varop);
8692               unsigned int first_count = INTVAL (XEXP (varop, 1));
8693               unsigned HOST_WIDE_INT mask;
8694               rtx mask_rtx;
8695
8696               /* We have one common special case.  We can't do any merging if
8697                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8698                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8699                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8700                  we can convert it to
8701                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8702                  This simplifies certain SIGN_EXTEND operations.  */
8703               if (code == ASHIFT && first_code == ASHIFTRT
8704                   && count == (GET_MODE_BITSIZE (result_mode)
8705                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8706                 {
8707                   /* C3 has the low-order C1 bits zero.  */
8708
8709                   mask = (GET_MODE_MASK (mode)
8710                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8711
8712                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8713                                                   XEXP (varop, 0), mask);
8714                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8715                                                 varop, count);
8716                   count = first_count;
8717                   code = ASHIFTRT;
8718                   continue;
8719                 }
8720
8721               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8722                  than C1 high-order bits equal to the sign bit, we can convert
8723                  this to either an ASHIFT or an ASHIFTRT depending on the
8724                  two counts.
8725
8726                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8727
8728               if (code == ASHIFTRT && first_code == ASHIFT
8729                   && GET_MODE (varop) == shift_mode
8730                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8731                       > first_count))
8732                 {
8733                   varop = XEXP (varop, 0);
8734                   count -= first_count;
8735                   if (count < 0)
8736                     {
8737                       count = -count;
8738                       code = ASHIFT;
8739                     }
8740
8741                   continue;
8742                 }
8743
8744               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8745                  we can only do this if FIRST_CODE is also ASHIFTRT.
8746
8747                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8748                  ASHIFTRT.
8749
8750                  If the mode of this shift is not the mode of the outer shift,
8751                  we can't do this if either shift is a right shift or ROTATE.
8752
8753                  Finally, we can't do any of these if the mode is too wide
8754                  unless the codes are the same.
8755
8756                  Handle the case where the shift codes are the same
8757                  first.  */
8758
8759               if (code == first_code)
8760                 {
8761                   if (GET_MODE (varop) != result_mode
8762                       && (code == ASHIFTRT || code == LSHIFTRT
8763                           || code == ROTATE))
8764                     break;
8765
8766                   count += first_count;
8767                   varop = XEXP (varop, 0);
8768                   continue;
8769                 }
8770
8771               if (code == ASHIFTRT
8772                   || (code == ROTATE && first_code == ASHIFTRT)
8773                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8774                   || (GET_MODE (varop) != result_mode
8775                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8776                           || first_code == ROTATE
8777                           || code == ROTATE)))
8778                 break;
8779
8780               /* To compute the mask to apply after the shift, shift the
8781                  nonzero bits of the inner shift the same way the
8782                  outer shift will.  */
8783
8784               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8785
8786               mask_rtx
8787                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8788                                                    GEN_INT (count));
8789
8790               /* Give up if we can't compute an outer operation to use.  */
8791               if (mask_rtx == 0
8792                   || GET_CODE (mask_rtx) != CONST_INT
8793                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8794                                         INTVAL (mask_rtx),
8795                                         result_mode, &complement_p))
8796                 break;
8797
8798               /* If the shifts are in the same direction, we add the
8799                  counts.  Otherwise, we subtract them.  */
8800               if ((code == ASHIFTRT || code == LSHIFTRT)
8801                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8802                 count += first_count;
8803               else
8804                 count -= first_count;
8805
8806               /* If COUNT is positive, the new shift is usually CODE,
8807                  except for the two exceptions below, in which case it is
8808                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8809                  always be used  */
8810               if (count > 0
8811                   && ((first_code == ROTATE && code == ASHIFT)
8812                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8813                 code = first_code;
8814               else if (count < 0)
8815                 code = first_code, count = -count;
8816
8817               varop = XEXP (varop, 0);
8818               continue;
8819             }
8820
8821           /* If we have (A << B << C) for any shift, we can convert this to
8822              (A << C << B).  This wins if A is a constant.  Only try this if
8823              B is not a constant.  */
8824
8825           else if (GET_CODE (varop) == code
8826                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8827                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8828             {
8829               rtx new = simplify_const_binary_operation (code, mode,
8830                                                          XEXP (varop, 0),
8831                                                          GEN_INT (count));
8832               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8833               count = 0;
8834               continue;
8835             }
8836           break;
8837
8838         case NOT:
8839           /* Make this fit the case below.  */
8840           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8841                                GEN_INT (GET_MODE_MASK (mode)));
8842           continue;
8843
8844         case IOR:
8845         case AND:
8846         case XOR:
8847           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8848              with C the size of VAROP - 1 and the shift is logical if
8849              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8850              we have an (le X 0) operation.   If we have an arithmetic shift
8851              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8852              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8853
8854           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8855               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8856               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8857               && (code == LSHIFTRT || code == ASHIFTRT)
8858               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8859               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8860             {
8861               count = 0;
8862               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8863                                   const0_rtx);
8864
8865               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8866                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8867
8868               continue;
8869             }
8870
8871           /* If we have (shift (logical)), move the logical to the outside
8872              to allow it to possibly combine with another logical and the
8873              shift to combine with another shift.  This also canonicalizes to
8874              what a ZERO_EXTRACT looks like.  Also, some machines have
8875              (and (shift)) insns.  */
8876
8877           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8878               /* We can't do this if we have (ashiftrt (xor))  and the
8879                  constant has its sign bit set in shift_mode.  */
8880               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8881                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8882                                               shift_mode))
8883               && (new = simplify_const_binary_operation (code, result_mode,
8884                                                          XEXP (varop, 1),
8885                                                          GEN_INT (count))) != 0
8886               && GET_CODE (new) == CONST_INT
8887               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8888                                   INTVAL (new), result_mode, &complement_p))
8889             {
8890               varop = XEXP (varop, 0);
8891               continue;
8892             }
8893
8894           /* If we can't do that, try to simplify the shift in each arm of the
8895              logical expression, make a new logical expression, and apply
8896              the inverse distributive law.  This also can't be done
8897              for some (ashiftrt (xor)).  */
8898           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8899              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8900                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8901                                              shift_mode)))
8902             {
8903               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8904                                               XEXP (varop, 0), count);
8905               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8906                                               XEXP (varop, 1), count);
8907
8908               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8909                                            lhs, rhs);
8910               varop = apply_distributive_law (varop);
8911
8912               count = 0;
8913               continue;
8914             }
8915           break;
8916
8917         case EQ:
8918           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8919              says that the sign bit can be tested, FOO has mode MODE, C is
8920              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8921              that may be nonzero.  */
8922           if (code == LSHIFTRT
8923               && XEXP (varop, 1) == const0_rtx
8924               && GET_MODE (XEXP (varop, 0)) == result_mode
8925               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8926               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8927               && STORE_FLAG_VALUE == -1
8928               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8929               && merge_outer_ops (&outer_op, &outer_const, XOR,
8930                                   (HOST_WIDE_INT) 1, result_mode,
8931                                   &complement_p))
8932             {
8933               varop = XEXP (varop, 0);
8934               count = 0;
8935               continue;
8936             }
8937           break;
8938
8939         case NEG:
8940           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8941              than the number of bits in the mode is equivalent to A.  */
8942           if (code == LSHIFTRT
8943               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8944               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8945             {
8946               varop = XEXP (varop, 0);
8947               count = 0;
8948               continue;
8949             }
8950
8951           /* NEG commutes with ASHIFT since it is multiplication.  Move the
8952              NEG outside to allow shifts to combine.  */
8953           if (code == ASHIFT
8954               && merge_outer_ops (&outer_op, &outer_const, NEG,
8955                                   (HOST_WIDE_INT) 0, result_mode,
8956                                   &complement_p))
8957             {
8958               varop = XEXP (varop, 0);
8959               continue;
8960             }
8961           break;
8962
8963         case PLUS:
8964           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8965              is one less than the number of bits in the mode is
8966              equivalent to (xor A 1).  */
8967           if (code == LSHIFTRT
8968               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8969               && XEXP (varop, 1) == constm1_rtx
8970               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8971               && merge_outer_ops (&outer_op, &outer_const, XOR,
8972                                   (HOST_WIDE_INT) 1, result_mode,
8973                                   &complement_p))
8974             {
8975               count = 0;
8976               varop = XEXP (varop, 0);
8977               continue;
8978             }
8979
8980           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8981              that might be nonzero in BAR are those being shifted out and those
8982              bits are known zero in FOO, we can replace the PLUS with FOO.
8983              Similarly in the other operand order.  This code occurs when
8984              we are computing the size of a variable-size array.  */
8985
8986           if ((code == ASHIFTRT || code == LSHIFTRT)
8987               && count < HOST_BITS_PER_WIDE_INT
8988               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8989               && (nonzero_bits (XEXP (varop, 1), result_mode)
8990                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8991             {
8992               varop = XEXP (varop, 0);
8993               continue;
8994             }
8995           else if ((code == ASHIFTRT || code == LSHIFTRT)
8996                    && count < HOST_BITS_PER_WIDE_INT
8997                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8998                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8999                             >> count)
9000                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9001                             & nonzero_bits (XEXP (varop, 1),
9002                                                  result_mode)))
9003             {
9004               varop = XEXP (varop, 1);
9005               continue;
9006             }
9007
9008           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9009           if (code == ASHIFT
9010               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9011               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9012                                                          XEXP (varop, 1),
9013                                                          GEN_INT (count))) != 0
9014               && GET_CODE (new) == CONST_INT
9015               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9016                                   INTVAL (new), result_mode, &complement_p))
9017             {
9018               varop = XEXP (varop, 0);
9019               continue;
9020             }
9021
9022           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9023              signbit', and attempt to change the PLUS to an XOR and move it to
9024              the outer operation as is done above in the AND/IOR/XOR case
9025              leg for shift(logical). See details in logical handling above
9026              for reasoning in doing so.  */
9027           if (code == LSHIFTRT
9028               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9029               && mode_signbit_p (result_mode, XEXP (varop, 1))
9030               && (new = simplify_const_binary_operation (code, result_mode,
9031                                                          XEXP (varop, 1),
9032                                                          GEN_INT (count))) != 0
9033               && GET_CODE (new) == CONST_INT
9034               && merge_outer_ops (&outer_op, &outer_const, XOR,
9035                                   INTVAL (new), result_mode, &complement_p))
9036             {
9037               varop = XEXP (varop, 0);
9038               continue;
9039             }
9040
9041           break;
9042
9043         case MINUS:
9044           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9045              with C the size of VAROP - 1 and the shift is logical if
9046              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9047              we have a (gt X 0) operation.  If the shift is arithmetic with
9048              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9049              we have a (neg (gt X 0)) operation.  */
9050
9051           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9052               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9053               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9054               && (code == LSHIFTRT || code == ASHIFTRT)
9055               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9056               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9057               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9058             {
9059               count = 0;
9060               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9061                                   const0_rtx);
9062
9063               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9064                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9065
9066               continue;
9067             }
9068           break;
9069
9070         case TRUNCATE:
9071           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9072              if the truncate does not affect the value.  */
9073           if (code == LSHIFTRT
9074               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9075               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9076               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9077                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9078                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9079             {
9080               rtx varop_inner = XEXP (varop, 0);
9081
9082               varop_inner
9083                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9084                                     XEXP (varop_inner, 0),
9085                                     GEN_INT
9086                                     (count + INTVAL (XEXP (varop_inner, 1))));
9087               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9088               count = 0;
9089               continue;
9090             }
9091           break;
9092
9093         default:
9094           break;
9095         }
9096
9097       break;
9098     }
9099
9100   /* We need to determine what mode to do the shift in.  If the shift is
9101      a right shift or ROTATE, we must always do it in the mode it was
9102      originally done in.  Otherwise, we can do it in MODE, the widest mode
9103      encountered.  The code we care about is that of the shift that will
9104      actually be done, not the shift that was originally requested.  */
9105   shift_mode
9106     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9107        ? result_mode : mode);
9108
9109   /* We have now finished analyzing the shift.  The result should be
9110      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9111      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9112      to the result of the shift.  OUTER_CONST is the relevant constant,
9113      but we must turn off all bits turned off in the shift.  */
9114
9115   if (outer_op == UNKNOWN
9116       && orig_code == code && orig_count == count
9117       && varop == orig_varop
9118       && shift_mode == GET_MODE (varop))
9119     return NULL_RTX;
9120
9121   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9122   varop = gen_lowpart (shift_mode, varop);
9123   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9124     return NULL_RTX;
9125
9126   /* If we have an outer operation and we just made a shift, it is
9127      possible that we could have simplified the shift were it not
9128      for the outer operation.  So try to do the simplification
9129      recursively.  */
9130
9131   if (outer_op != UNKNOWN)
9132     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9133   else
9134     x = NULL_RTX;
9135
9136   if (x == NULL_RTX)
9137     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9138
9139   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9140      turn off all the bits that the shift would have turned off.  */
9141   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9142     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9143                                 GET_MODE_MASK (result_mode) >> orig_count);
9144
9145   /* Do the remainder of the processing in RESULT_MODE.  */
9146   x = gen_lowpart (result_mode, x);
9147
9148   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9149      operation.  */
9150   if (complement_p)
9151     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9152
9153   if (outer_op != UNKNOWN)
9154     {
9155       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9156         outer_const = trunc_int_for_mode (outer_const, result_mode);
9157
9158       if (outer_op == AND)
9159         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9160       else if (outer_op == SET)
9161         /* This means that we have determined that the result is
9162            equivalent to a constant.  This should be rare.  */
9163         x = GEN_INT (outer_const);
9164       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9165         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9166       else
9167         x = simplify_gen_binary (outer_op, result_mode, x,
9168                                  GEN_INT (outer_const));
9169     }
9170
9171   return x;
9172 }
9173
9174 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9175    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9176    return X or, if it is NULL, synthesize the expression with
9177    simplify_gen_binary.  Otherwise, return a simplified value.
9178
9179    The shift is normally computed in the widest mode we find in VAROP, as
9180    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9181    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9182
9183 static rtx
9184 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9185                       rtx varop, int count)
9186 {
9187   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9188   if (tem)
9189     return tem;
9190
9191   if (!x)
9192     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9193   if (GET_MODE (x) != result_mode)
9194     x = gen_lowpart (result_mode, x);
9195   return x;
9196 }
9197
9198 \f
9199 /* Like recog, but we receive the address of a pointer to a new pattern.
9200    We try to match the rtx that the pointer points to.
9201    If that fails, we may try to modify or replace the pattern,
9202    storing the replacement into the same pointer object.
9203
9204    Modifications include deletion or addition of CLOBBERs.
9205
9206    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9207    the CLOBBERs are placed.
9208
9209    The value is the final insn code from the pattern ultimately matched,
9210    or -1.  */
9211
9212 static int
9213 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9214 {
9215   rtx pat = *pnewpat;
9216   int insn_code_number;
9217   int num_clobbers_to_add = 0;
9218   int i;
9219   rtx notes = 0;
9220   rtx old_notes, old_pat;
9221
9222   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9223      we use to indicate that something didn't match.  If we find such a
9224      thing, force rejection.  */
9225   if (GET_CODE (pat) == PARALLEL)
9226     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9227       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9228           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9229         return -1;
9230
9231   old_pat = PATTERN (insn);
9232   old_notes = REG_NOTES (insn);
9233   PATTERN (insn) = pat;
9234   REG_NOTES (insn) = 0;
9235
9236   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9237
9238   /* If it isn't, there is the possibility that we previously had an insn
9239      that clobbered some register as a side effect, but the combined
9240      insn doesn't need to do that.  So try once more without the clobbers
9241      unless this represents an ASM insn.  */
9242
9243   if (insn_code_number < 0 && ! check_asm_operands (pat)
9244       && GET_CODE (pat) == PARALLEL)
9245     {
9246       int pos;
9247
9248       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9249         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9250           {
9251             if (i != pos)
9252               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9253             pos++;
9254           }
9255
9256       SUBST_INT (XVECLEN (pat, 0), pos);
9257
9258       if (pos == 1)
9259         pat = XVECEXP (pat, 0, 0);
9260
9261       PATTERN (insn) = pat;
9262       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9263     }
9264   PATTERN (insn) = old_pat;
9265   REG_NOTES (insn) = old_notes;
9266
9267   /* Recognize all noop sets, these will be killed by followup pass.  */
9268   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9269     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9270
9271   /* If we had any clobbers to add, make a new pattern than contains
9272      them.  Then check to make sure that all of them are dead.  */
9273   if (num_clobbers_to_add)
9274     {
9275       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9276                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9277                                                   ? (XVECLEN (pat, 0)
9278                                                      + num_clobbers_to_add)
9279                                                   : num_clobbers_to_add + 1));
9280
9281       if (GET_CODE (pat) == PARALLEL)
9282         for (i = 0; i < XVECLEN (pat, 0); i++)
9283           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9284       else
9285         XVECEXP (newpat, 0, 0) = pat;
9286
9287       add_clobbers (newpat, insn_code_number);
9288
9289       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9290            i < XVECLEN (newpat, 0); i++)
9291         {
9292           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9293               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9294             return -1;
9295           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9296                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9297         }
9298       pat = newpat;
9299     }
9300
9301   *pnewpat = pat;
9302   *pnotes = notes;
9303
9304   return insn_code_number;
9305 }
9306 \f
9307 /* Like gen_lowpart_general but for use by combine.  In combine it
9308    is not possible to create any new pseudoregs.  However, it is
9309    safe to create invalid memory addresses, because combine will
9310    try to recognize them and all they will do is make the combine
9311    attempt fail.
9312
9313    If for some reason this cannot do its job, an rtx
9314    (clobber (const_int 0)) is returned.
9315    An insn containing that will not be recognized.  */
9316
9317 static rtx
9318 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9319 {
9320   enum machine_mode imode = GET_MODE (x);
9321   unsigned int osize = GET_MODE_SIZE (omode);
9322   unsigned int isize = GET_MODE_SIZE (imode);
9323   rtx result;
9324
9325   if (omode == imode)
9326     return x;
9327
9328   /* Return identity if this is a CONST or symbolic reference.  */
9329   if (omode == Pmode
9330       && (GET_CODE (x) == CONST
9331           || GET_CODE (x) == SYMBOL_REF
9332           || GET_CODE (x) == LABEL_REF))
9333     return x;
9334
9335   /* We can only support MODE being wider than a word if X is a
9336      constant integer or has a mode the same size.  */
9337   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9338       && ! ((imode == VOIDmode
9339              && (GET_CODE (x) == CONST_INT
9340                  || GET_CODE (x) == CONST_DOUBLE))
9341             || isize == osize))
9342     goto fail;
9343
9344   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9345      won't know what to do.  So we will strip off the SUBREG here and
9346      process normally.  */
9347   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9348     {
9349       x = SUBREG_REG (x);
9350
9351       /* For use in case we fall down into the address adjustments
9352          further below, we need to adjust the known mode and size of
9353          x; imode and isize, since we just adjusted x.  */
9354       imode = GET_MODE (x);
9355
9356       if (imode == omode)
9357         return x;
9358
9359       isize = GET_MODE_SIZE (imode);
9360     }
9361
9362   result = gen_lowpart_common (omode, x);
9363
9364 #ifdef CANNOT_CHANGE_MODE_CLASS
9365   if (result != 0 && GET_CODE (result) == SUBREG)
9366     record_subregs_of_mode (result);
9367 #endif
9368
9369   if (result)
9370     return result;
9371
9372   if (MEM_P (x))
9373     {
9374       int offset = 0;
9375
9376       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9377          address.  */
9378       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9379         goto fail;
9380
9381       /* If we want to refer to something bigger than the original memref,
9382          generate a paradoxical subreg instead.  That will force a reload
9383          of the original memref X.  */
9384       if (isize < osize)
9385         return gen_rtx_SUBREG (omode, x, 0);
9386
9387       if (WORDS_BIG_ENDIAN)
9388         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9389
9390       /* Adjust the address so that the address-after-the-data is
9391          unchanged.  */
9392       if (BYTES_BIG_ENDIAN)
9393         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9394
9395       return adjust_address_nv (x, omode, offset);
9396     }
9397
9398   /* If X is a comparison operator, rewrite it in a new mode.  This
9399      probably won't match, but may allow further simplifications.  */
9400   else if (COMPARISON_P (x))
9401     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9402
9403   /* If we couldn't simplify X any other way, just enclose it in a
9404      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9405      include an explicit SUBREG or we may simplify it further in combine.  */
9406   else
9407     {
9408       int offset = 0;
9409       rtx res;
9410
9411       offset = subreg_lowpart_offset (omode, imode);
9412       if (imode == VOIDmode)
9413         {
9414           imode = int_mode_for_mode (omode);
9415           x = gen_lowpart_common (imode, x);
9416           if (x == NULL)
9417             goto fail;
9418         }
9419       res = simplify_gen_subreg (omode, x, imode, offset);
9420       if (res)
9421         return res;
9422     }
9423
9424  fail:
9425   return gen_rtx_CLOBBER (imode, const0_rtx);
9426 }
9427 \f
9428 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9429    comparison code that will be tested.
9430
9431    The result is a possibly different comparison code to use.  *POP0 and
9432    *POP1 may be updated.
9433
9434    It is possible that we might detect that a comparison is either always
9435    true or always false.  However, we do not perform general constant
9436    folding in combine, so this knowledge isn't useful.  Such tautologies
9437    should have been detected earlier.  Hence we ignore all such cases.  */
9438
9439 static enum rtx_code
9440 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9441 {
9442   rtx op0 = *pop0;
9443   rtx op1 = *pop1;
9444   rtx tem, tem1;
9445   int i;
9446   enum machine_mode mode, tmode;
9447
9448   /* Try a few ways of applying the same transformation to both operands.  */
9449   while (1)
9450     {
9451 #ifndef WORD_REGISTER_OPERATIONS
9452       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9453          so check specially.  */
9454       if (code != GTU && code != GEU && code != LTU && code != LEU
9455           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9456           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9457           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9458           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9459           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9460           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9461               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9462           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9463           && XEXP (op0, 1) == XEXP (op1, 1)
9464           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9465           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9466           && (INTVAL (XEXP (op0, 1))
9467               == (GET_MODE_BITSIZE (GET_MODE (op0))
9468                   - (GET_MODE_BITSIZE
9469                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9470         {
9471           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9472           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9473         }
9474 #endif
9475
9476       /* If both operands are the same constant shift, see if we can ignore the
9477          shift.  We can if the shift is a rotate or if the bits shifted out of
9478          this shift are known to be zero for both inputs and if the type of
9479          comparison is compatible with the shift.  */
9480       if (GET_CODE (op0) == GET_CODE (op1)
9481           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9482           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9483               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9484                   && (code != GT && code != LT && code != GE && code != LE))
9485               || (GET_CODE (op0) == ASHIFTRT
9486                   && (code != GTU && code != LTU
9487                       && code != GEU && code != LEU)))
9488           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9489           && INTVAL (XEXP (op0, 1)) >= 0
9490           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9491           && XEXP (op0, 1) == XEXP (op1, 1))
9492         {
9493           enum machine_mode mode = GET_MODE (op0);
9494           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9495           int shift_count = INTVAL (XEXP (op0, 1));
9496
9497           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9498             mask &= (mask >> shift_count) << shift_count;
9499           else if (GET_CODE (op0) == ASHIFT)
9500             mask = (mask & (mask << shift_count)) >> shift_count;
9501
9502           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9503               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9504             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9505           else
9506             break;
9507         }
9508
9509       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9510          SUBREGs are of the same mode, and, in both cases, the AND would
9511          be redundant if the comparison was done in the narrower mode,
9512          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9513          and the operand's possibly nonzero bits are 0xffffff01; in that case
9514          if we only care about QImode, we don't need the AND).  This case
9515          occurs if the output mode of an scc insn is not SImode and
9516          STORE_FLAG_VALUE == 1 (e.g., the 386).
9517
9518          Similarly, check for a case where the AND's are ZERO_EXTEND
9519          operations from some narrower mode even though a SUBREG is not
9520          present.  */
9521
9522       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9523                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9524                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9525         {
9526           rtx inner_op0 = XEXP (op0, 0);
9527           rtx inner_op1 = XEXP (op1, 0);
9528           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9529           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9530           int changed = 0;
9531
9532           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9533               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9534                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9535               && (GET_MODE (SUBREG_REG (inner_op0))
9536                   == GET_MODE (SUBREG_REG (inner_op1)))
9537               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9538                   <= HOST_BITS_PER_WIDE_INT)
9539               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9540                                              GET_MODE (SUBREG_REG (inner_op0)))))
9541               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9542                                              GET_MODE (SUBREG_REG (inner_op1))))))
9543             {
9544               op0 = SUBREG_REG (inner_op0);
9545               op1 = SUBREG_REG (inner_op1);
9546
9547               /* The resulting comparison is always unsigned since we masked
9548                  off the original sign bit.  */
9549               code = unsigned_condition (code);
9550
9551               changed = 1;
9552             }
9553
9554           else if (c0 == c1)
9555             for (tmode = GET_CLASS_NARROWEST_MODE
9556                  (GET_MODE_CLASS (GET_MODE (op0)));
9557                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9558               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9559                 {
9560                   op0 = gen_lowpart (tmode, inner_op0);
9561                   op1 = gen_lowpart (tmode, inner_op1);
9562                   code = unsigned_condition (code);
9563                   changed = 1;
9564                   break;
9565                 }
9566
9567           if (! changed)
9568             break;
9569         }
9570
9571       /* If both operands are NOT, we can strip off the outer operation
9572          and adjust the comparison code for swapped operands; similarly for
9573          NEG, except that this must be an equality comparison.  */
9574       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9575                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9576                    && (code == EQ || code == NE)))
9577         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9578
9579       else
9580         break;
9581     }
9582
9583   /* If the first operand is a constant, swap the operands and adjust the
9584      comparison code appropriately, but don't do this if the second operand
9585      is already a constant integer.  */
9586   if (swap_commutative_operands_p (op0, op1))
9587     {
9588       tem = op0, op0 = op1, op1 = tem;
9589       code = swap_condition (code);
9590     }
9591
9592   /* We now enter a loop during which we will try to simplify the comparison.
9593      For the most part, we only are concerned with comparisons with zero,
9594      but some things may really be comparisons with zero but not start
9595      out looking that way.  */
9596
9597   while (GET_CODE (op1) == CONST_INT)
9598     {
9599       enum machine_mode mode = GET_MODE (op0);
9600       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9601       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9602       int equality_comparison_p;
9603       int sign_bit_comparison_p;
9604       int unsigned_comparison_p;
9605       HOST_WIDE_INT const_op;
9606
9607       /* We only want to handle integral modes.  This catches VOIDmode,
9608          CCmode, and the floating-point modes.  An exception is that we
9609          can handle VOIDmode if OP0 is a COMPARE or a comparison
9610          operation.  */
9611
9612       if (GET_MODE_CLASS (mode) != MODE_INT
9613           && ! (mode == VOIDmode
9614                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9615         break;
9616
9617       /* Get the constant we are comparing against and turn off all bits
9618          not on in our mode.  */
9619       const_op = INTVAL (op1);
9620       if (mode != VOIDmode)
9621         const_op = trunc_int_for_mode (const_op, mode);
9622       op1 = GEN_INT (const_op);
9623
9624       /* If we are comparing against a constant power of two and the value
9625          being compared can only have that single bit nonzero (e.g., it was
9626          `and'ed with that bit), we can replace this with a comparison
9627          with zero.  */
9628       if (const_op
9629           && (code == EQ || code == NE || code == GE || code == GEU
9630               || code == LT || code == LTU)
9631           && mode_width <= HOST_BITS_PER_WIDE_INT
9632           && exact_log2 (const_op) >= 0
9633           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9634         {
9635           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9636           op1 = const0_rtx, const_op = 0;
9637         }
9638
9639       /* Similarly, if we are comparing a value known to be either -1 or
9640          0 with -1, change it to the opposite comparison against zero.  */
9641
9642       if (const_op == -1
9643           && (code == EQ || code == NE || code == GT || code == LE
9644               || code == GEU || code == LTU)
9645           && num_sign_bit_copies (op0, mode) == mode_width)
9646         {
9647           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9648           op1 = const0_rtx, const_op = 0;
9649         }
9650
9651       /* Do some canonicalizations based on the comparison code.  We prefer
9652          comparisons against zero and then prefer equality comparisons.
9653          If we can reduce the size of a constant, we will do that too.  */
9654
9655       switch (code)
9656         {
9657         case LT:
9658           /* < C is equivalent to <= (C - 1) */
9659           if (const_op > 0)
9660             {
9661               const_op -= 1;
9662               op1 = GEN_INT (const_op);
9663               code = LE;
9664               /* ... fall through to LE case below.  */
9665             }
9666           else
9667             break;
9668
9669         case LE:
9670           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9671           if (const_op < 0)
9672             {
9673               const_op += 1;
9674               op1 = GEN_INT (const_op);
9675               code = LT;
9676             }
9677
9678           /* If we are doing a <= 0 comparison on a value known to have
9679              a zero sign bit, we can replace this with == 0.  */
9680           else if (const_op == 0
9681                    && mode_width <= HOST_BITS_PER_WIDE_INT
9682                    && (nonzero_bits (op0, mode)
9683                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9684             code = EQ;
9685           break;
9686
9687         case GE:
9688           /* >= C is equivalent to > (C - 1).  */
9689           if (const_op > 0)
9690             {
9691               const_op -= 1;
9692               op1 = GEN_INT (const_op);
9693               code = GT;
9694               /* ... fall through to GT below.  */
9695             }
9696           else
9697             break;
9698
9699         case GT:
9700           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9701           if (const_op < 0)
9702             {
9703               const_op += 1;
9704               op1 = GEN_INT (const_op);
9705               code = GE;
9706             }
9707
9708           /* If we are doing a > 0 comparison on a value known to have
9709              a zero sign bit, we can replace this with != 0.  */
9710           else if (const_op == 0
9711                    && mode_width <= HOST_BITS_PER_WIDE_INT
9712                    && (nonzero_bits (op0, mode)
9713                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9714             code = NE;
9715           break;
9716
9717         case LTU:
9718           /* < C is equivalent to <= (C - 1).  */
9719           if (const_op > 0)
9720             {
9721               const_op -= 1;
9722               op1 = GEN_INT (const_op);
9723               code = LEU;
9724               /* ... fall through ...  */
9725             }
9726
9727           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9728           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9729                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9730             {
9731               const_op = 0, op1 = const0_rtx;
9732               code = GE;
9733               break;
9734             }
9735           else
9736             break;
9737
9738         case LEU:
9739           /* unsigned <= 0 is equivalent to == 0 */
9740           if (const_op == 0)
9741             code = EQ;
9742
9743           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9744           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9745                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9746             {
9747               const_op = 0, op1 = const0_rtx;
9748               code = GE;
9749             }
9750           break;
9751
9752         case GEU:
9753           /* >= C is equivalent to > (C - 1).  */
9754           if (const_op > 1)
9755             {
9756               const_op -= 1;
9757               op1 = GEN_INT (const_op);
9758               code = GTU;
9759               /* ... fall through ...  */
9760             }
9761
9762           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9763           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9764                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9765             {
9766               const_op = 0, op1 = const0_rtx;
9767               code = LT;
9768               break;
9769             }
9770           else
9771             break;
9772
9773         case GTU:
9774           /* unsigned > 0 is equivalent to != 0 */
9775           if (const_op == 0)
9776             code = NE;
9777
9778           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9779           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9780                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9781             {
9782               const_op = 0, op1 = const0_rtx;
9783               code = LT;
9784             }
9785           break;
9786
9787         default:
9788           break;
9789         }
9790
9791       /* Compute some predicates to simplify code below.  */
9792
9793       equality_comparison_p = (code == EQ || code == NE);
9794       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9795       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9796                                || code == GEU);
9797
9798       /* If this is a sign bit comparison and we can do arithmetic in
9799          MODE, say that we will only be needing the sign bit of OP0.  */
9800       if (sign_bit_comparison_p
9801           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9802         op0 = force_to_mode (op0, mode,
9803                              ((HOST_WIDE_INT) 1
9804                               << (GET_MODE_BITSIZE (mode) - 1)),
9805                              0);
9806
9807       /* Now try cases based on the opcode of OP0.  If none of the cases
9808          does a "continue", we exit this loop immediately after the
9809          switch.  */
9810
9811       switch (GET_CODE (op0))
9812         {
9813         case ZERO_EXTRACT:
9814           /* If we are extracting a single bit from a variable position in
9815              a constant that has only a single bit set and are comparing it
9816              with zero, we can convert this into an equality comparison
9817              between the position and the location of the single bit.  */
9818           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9819              have already reduced the shift count modulo the word size.  */
9820           if (!SHIFT_COUNT_TRUNCATED
9821               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9822               && XEXP (op0, 1) == const1_rtx
9823               && equality_comparison_p && const_op == 0
9824               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9825             {
9826               if (BITS_BIG_ENDIAN)
9827                 {
9828                   enum machine_mode new_mode
9829                     = mode_for_extraction (EP_extzv, 1);
9830                   if (new_mode == MAX_MACHINE_MODE)
9831                     i = BITS_PER_WORD - 1 - i;
9832                   else
9833                     {
9834                       mode = new_mode;
9835                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9836                     }
9837                 }
9838
9839               op0 = XEXP (op0, 2);
9840               op1 = GEN_INT (i);
9841               const_op = i;
9842
9843               /* Result is nonzero iff shift count is equal to I.  */
9844               code = reverse_condition (code);
9845               continue;
9846             }
9847
9848           /* ... fall through ...  */
9849
9850         case SIGN_EXTRACT:
9851           tem = expand_compound_operation (op0);
9852           if (tem != op0)
9853             {
9854               op0 = tem;
9855               continue;
9856             }
9857           break;
9858
9859         case NOT:
9860           /* If testing for equality, we can take the NOT of the constant.  */
9861           if (equality_comparison_p
9862               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9863             {
9864               op0 = XEXP (op0, 0);
9865               op1 = tem;
9866               continue;
9867             }
9868
9869           /* If just looking at the sign bit, reverse the sense of the
9870              comparison.  */
9871           if (sign_bit_comparison_p)
9872             {
9873               op0 = XEXP (op0, 0);
9874               code = (code == GE ? LT : GE);
9875               continue;
9876             }
9877           break;
9878
9879         case NEG:
9880           /* If testing for equality, we can take the NEG of the constant.  */
9881           if (equality_comparison_p
9882               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9883             {
9884               op0 = XEXP (op0, 0);
9885               op1 = tem;
9886               continue;
9887             }
9888
9889           /* The remaining cases only apply to comparisons with zero.  */
9890           if (const_op != 0)
9891             break;
9892
9893           /* When X is ABS or is known positive,
9894              (neg X) is < 0 if and only if X != 0.  */
9895
9896           if (sign_bit_comparison_p
9897               && (GET_CODE (XEXP (op0, 0)) == ABS
9898                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9899                       && (nonzero_bits (XEXP (op0, 0), mode)
9900                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9901             {
9902               op0 = XEXP (op0, 0);
9903               code = (code == LT ? NE : EQ);
9904               continue;
9905             }
9906
9907           /* If we have NEG of something whose two high-order bits are the
9908              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9909           if (num_sign_bit_copies (op0, mode) >= 2)
9910             {
9911               op0 = XEXP (op0, 0);
9912               code = swap_condition (code);
9913               continue;
9914             }
9915           break;
9916
9917         case ROTATE:
9918           /* If we are testing equality and our count is a constant, we
9919              can perform the inverse operation on our RHS.  */
9920           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9921               && (tem = simplify_binary_operation (ROTATERT, mode,
9922                                                    op1, XEXP (op0, 1))) != 0)
9923             {
9924               op0 = XEXP (op0, 0);
9925               op1 = tem;
9926               continue;
9927             }
9928
9929           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9930              a particular bit.  Convert it to an AND of a constant of that
9931              bit.  This will be converted into a ZERO_EXTRACT.  */
9932           if (const_op == 0 && sign_bit_comparison_p
9933               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9934               && mode_width <= HOST_BITS_PER_WIDE_INT)
9935             {
9936               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9937                                             ((HOST_WIDE_INT) 1
9938                                              << (mode_width - 1
9939                                                  - INTVAL (XEXP (op0, 1)))));
9940               code = (code == LT ? NE : EQ);
9941               continue;
9942             }
9943
9944           /* Fall through.  */
9945
9946         case ABS:
9947           /* ABS is ignorable inside an equality comparison with zero.  */
9948           if (const_op == 0 && equality_comparison_p)
9949             {
9950               op0 = XEXP (op0, 0);
9951               continue;
9952             }
9953           break;
9954
9955         case SIGN_EXTEND:
9956           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
9957              (compare FOO CONST) if CONST fits in FOO's mode and we
9958              are either testing inequality or have an unsigned
9959              comparison with ZERO_EXTEND or a signed comparison with
9960              SIGN_EXTEND.  But don't do it if we don't have a compare
9961              insn of the given mode, since we'd have to revert it
9962              later on, and then we wouldn't know whether to sign- or
9963              zero-extend.  */
9964           mode = GET_MODE (XEXP (op0, 0));
9965           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9966               && ! unsigned_comparison_p
9967               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9968               && ((unsigned HOST_WIDE_INT) const_op
9969                   < (((unsigned HOST_WIDE_INT) 1
9970                       << (GET_MODE_BITSIZE (mode) - 1))))
9971               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9972             {
9973               op0 = XEXP (op0, 0);
9974               continue;
9975             }
9976           break;
9977
9978         case SUBREG:
9979           /* Check for the case where we are comparing A - C1 with C2, that is
9980
9981                (subreg:MODE (plus (A) (-C1))) op (C2)
9982
9983              with C1 a constant, and try to lift the SUBREG, i.e. to do the
9984              comparison in the wider mode.  One of the following two conditions
9985              must be true in order for this to be valid:
9986
9987                1. The mode extension results in the same bit pattern being added
9988                   on both sides and the comparison is equality or unsigned.  As
9989                   C2 has been truncated to fit in MODE, the pattern can only be
9990                   all 0s or all 1s.
9991
9992                2. The mode extension results in the sign bit being copied on
9993                   each side.
9994
9995              The difficulty here is that we have predicates for A but not for
9996              (A - C1) so we need to check that C1 is within proper bounds so
9997              as to perturbate A as little as possible.  */
9998
9999           if (mode_width <= HOST_BITS_PER_WIDE_INT
10000               && subreg_lowpart_p (op0)
10001               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10002               && GET_CODE (SUBREG_REG (op0)) == PLUS
10003               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10004             {
10005               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10006               rtx a = XEXP (SUBREG_REG (op0), 0);
10007               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10008
10009               if ((c1 > 0
10010                    && (unsigned HOST_WIDE_INT) c1
10011                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10012                    && (equality_comparison_p || unsigned_comparison_p)
10013                    /* (A - C1) zero-extends if it is positive and sign-extends
10014                       if it is negative, C2 both zero- and sign-extends.  */
10015                    && ((0 == (nonzero_bits (a, inner_mode)
10016                               & ~GET_MODE_MASK (mode))
10017                         && const_op >= 0)
10018                        /* (A - C1) sign-extends if it is positive and 1-extends
10019                           if it is negative, C2 both sign- and 1-extends.  */
10020                        || (num_sign_bit_copies (a, inner_mode)
10021                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10022                                              - mode_width)
10023                            && const_op < 0)))
10024                   || ((unsigned HOST_WIDE_INT) c1
10025                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10026                       /* (A - C1) always sign-extends, like C2.  */
10027                       && num_sign_bit_copies (a, inner_mode)
10028                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10029                                            - (mode_width - 1))))
10030                 {
10031                   op0 = SUBREG_REG (op0);
10032                   continue;
10033                 }
10034             }
10035
10036           /* If the inner mode is narrower and we are extracting the low part,
10037              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10038           if (subreg_lowpart_p (op0)
10039               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10040             /* Fall through */ ;
10041           else
10042             break;
10043
10044           /* ... fall through ...  */
10045
10046         case ZERO_EXTEND:
10047           mode = GET_MODE (XEXP (op0, 0));
10048           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10049               && (unsigned_comparison_p || equality_comparison_p)
10050               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10051               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10052               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10053             {
10054               op0 = XEXP (op0, 0);
10055               continue;
10056             }
10057           break;
10058
10059         case PLUS:
10060           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10061              this for equality comparisons due to pathological cases involving
10062              overflows.  */
10063           if (equality_comparison_p
10064               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10065                                                         op1, XEXP (op0, 1))))
10066             {
10067               op0 = XEXP (op0, 0);
10068               op1 = tem;
10069               continue;
10070             }
10071
10072           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10073           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10074               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10075             {
10076               op0 = XEXP (XEXP (op0, 0), 0);
10077               code = (code == LT ? EQ : NE);
10078               continue;
10079             }
10080           break;
10081
10082         case MINUS:
10083           /* We used to optimize signed comparisons against zero, but that
10084              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10085              arrive here as equality comparisons, or (GEU, LTU) are
10086              optimized away.  No need to special-case them.  */
10087
10088           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10089              (eq B (minus A C)), whichever simplifies.  We can only do
10090              this for equality comparisons due to pathological cases involving
10091              overflows.  */
10092           if (equality_comparison_p
10093               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10094                                                         XEXP (op0, 1), op1)))
10095             {
10096               op0 = XEXP (op0, 0);
10097               op1 = tem;
10098               continue;
10099             }
10100
10101           if (equality_comparison_p
10102               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10103                                                         XEXP (op0, 0), op1)))
10104             {
10105               op0 = XEXP (op0, 1);
10106               op1 = tem;
10107               continue;
10108             }
10109
10110           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10111              of bits in X minus 1, is one iff X > 0.  */
10112           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10113               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10114               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10115                  == mode_width - 1
10116               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10117             {
10118               op0 = XEXP (op0, 1);
10119               code = (code == GE ? LE : GT);
10120               continue;
10121             }
10122           break;
10123
10124         case XOR:
10125           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10126              if C is zero or B is a constant.  */
10127           if (equality_comparison_p
10128               && 0 != (tem = simplify_binary_operation (XOR, mode,
10129                                                         XEXP (op0, 1), op1)))
10130             {
10131               op0 = XEXP (op0, 0);
10132               op1 = tem;
10133               continue;
10134             }
10135           break;
10136
10137         case EQ:  case NE:
10138         case UNEQ:  case LTGT:
10139         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10140         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10141         case UNORDERED: case ORDERED:
10142           /* We can't do anything if OP0 is a condition code value, rather
10143              than an actual data value.  */
10144           if (const_op != 0
10145               || CC0_P (XEXP (op0, 0))
10146               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10147             break;
10148
10149           /* Get the two operands being compared.  */
10150           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10151             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10152           else
10153             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10154
10155           /* Check for the cases where we simply want the result of the
10156              earlier test or the opposite of that result.  */
10157           if (code == NE || code == EQ
10158               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10159                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10160                   && (STORE_FLAG_VALUE
10161                       & (((HOST_WIDE_INT) 1
10162                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10163                   && (code == LT || code == GE)))
10164             {
10165               enum rtx_code new_code;
10166               if (code == LT || code == NE)
10167                 new_code = GET_CODE (op0);
10168               else
10169                 new_code = reversed_comparison_code (op0, NULL);
10170
10171               if (new_code != UNKNOWN)
10172                 {
10173                   code = new_code;
10174                   op0 = tem;
10175                   op1 = tem1;
10176                   continue;
10177                 }
10178             }
10179           break;
10180
10181         case IOR:
10182           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10183              iff X <= 0.  */
10184           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10185               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10186               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10187             {
10188               op0 = XEXP (op0, 1);
10189               code = (code == GE ? GT : LE);
10190               continue;
10191             }
10192           break;
10193
10194         case AND:
10195           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10196              will be converted to a ZERO_EXTRACT later.  */
10197           if (const_op == 0 && equality_comparison_p
10198               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10199               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10200             {
10201               op0 = simplify_and_const_int
10202                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10203                                                    XEXP (op0, 1),
10204                                                    XEXP (XEXP (op0, 0), 1)),
10205                  (HOST_WIDE_INT) 1);
10206               continue;
10207             }
10208
10209           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10210              zero and X is a comparison and C1 and C2 describe only bits set
10211              in STORE_FLAG_VALUE, we can compare with X.  */
10212           if (const_op == 0 && equality_comparison_p
10213               && mode_width <= HOST_BITS_PER_WIDE_INT
10214               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10215               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10216               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10217               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10218               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10219             {
10220               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10221                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10222               if ((~STORE_FLAG_VALUE & mask) == 0
10223                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10224                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10225                           && COMPARISON_P (tem))))
10226                 {
10227                   op0 = XEXP (XEXP (op0, 0), 0);
10228                   continue;
10229                 }
10230             }
10231
10232           /* If we are doing an equality comparison of an AND of a bit equal
10233              to the sign bit, replace this with a LT or GE comparison of
10234              the underlying value.  */
10235           if (equality_comparison_p
10236               && const_op == 0
10237               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10238               && mode_width <= HOST_BITS_PER_WIDE_INT
10239               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10240                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10241             {
10242               op0 = XEXP (op0, 0);
10243               code = (code == EQ ? GE : LT);
10244               continue;
10245             }
10246
10247           /* If this AND operation is really a ZERO_EXTEND from a narrower
10248              mode, the constant fits within that mode, and this is either an
10249              equality or unsigned comparison, try to do this comparison in
10250              the narrower mode.  */
10251           if ((equality_comparison_p || unsigned_comparison_p)
10252               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10253               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10254                                    & GET_MODE_MASK (mode))
10255                                   + 1)) >= 0
10256               && const_op >> i == 0
10257               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10258             {
10259               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10260               continue;
10261             }
10262
10263           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10264              fits in both M1 and M2 and the SUBREG is either paradoxical
10265              or represents the low part, permute the SUBREG and the AND
10266              and try again.  */
10267           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10268             {
10269               unsigned HOST_WIDE_INT c1;
10270               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10271               /* Require an integral mode, to avoid creating something like
10272                  (AND:SF ...).  */
10273               if (SCALAR_INT_MODE_P (tmode)
10274                   /* It is unsafe to commute the AND into the SUBREG if the
10275                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10276                      not defined.  As originally written the upper bits
10277                      have a defined value due to the AND operation.
10278                      However, if we commute the AND inside the SUBREG then
10279                      they no longer have defined values and the meaning of
10280                      the code has been changed.  */
10281                   && (0
10282 #ifdef WORD_REGISTER_OPERATIONS
10283                       || (mode_width > GET_MODE_BITSIZE (tmode)
10284                           && mode_width <= BITS_PER_WORD)
10285 #endif
10286                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10287                           && subreg_lowpart_p (XEXP (op0, 0))))
10288                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10289                   && mode_width <= HOST_BITS_PER_WIDE_INT
10290                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10291                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10292                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10293                   && c1 != mask
10294                   && c1 != GET_MODE_MASK (tmode))
10295                 {
10296                   op0 = simplify_gen_binary (AND, tmode,
10297                                              SUBREG_REG (XEXP (op0, 0)),
10298                                              gen_int_mode (c1, tmode));
10299                   op0 = gen_lowpart (mode, op0);
10300                   continue;
10301                 }
10302             }
10303
10304           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10305           if (const_op == 0 && equality_comparison_p
10306               && XEXP (op0, 1) == const1_rtx
10307               && GET_CODE (XEXP (op0, 0)) == NOT)
10308             {
10309               op0 = simplify_and_const_int
10310                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10311               code = (code == NE ? EQ : NE);
10312               continue;
10313             }
10314
10315           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10316              (eq (and (lshiftrt X) 1) 0).
10317              Also handle the case where (not X) is expressed using xor.  */
10318           if (const_op == 0 && equality_comparison_p
10319               && XEXP (op0, 1) == const1_rtx
10320               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10321             {
10322               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10323               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10324
10325               if (GET_CODE (shift_op) == NOT
10326                   || (GET_CODE (shift_op) == XOR
10327                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10328                       && GET_CODE (shift_count) == CONST_INT
10329                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10330                       && (INTVAL (XEXP (shift_op, 1))
10331                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10332                 {
10333                   op0 = simplify_and_const_int
10334                     (NULL_RTX, mode,
10335                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10336                      (HOST_WIDE_INT) 1);
10337                   code = (code == NE ? EQ : NE);
10338                   continue;
10339                 }
10340             }
10341           break;
10342
10343         case ASHIFT:
10344           /* If we have (compare (ashift FOO N) (const_int C)) and
10345              the high order N bits of FOO (N+1 if an inequality comparison)
10346              are known to be zero, we can do this by comparing FOO with C
10347              shifted right N bits so long as the low-order N bits of C are
10348              zero.  */
10349           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10350               && INTVAL (XEXP (op0, 1)) >= 0
10351               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10352                   < HOST_BITS_PER_WIDE_INT)
10353               && ((const_op
10354                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10355               && mode_width <= HOST_BITS_PER_WIDE_INT
10356               && (nonzero_bits (XEXP (op0, 0), mode)
10357                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10358                                + ! equality_comparison_p))) == 0)
10359             {
10360               /* We must perform a logical shift, not an arithmetic one,
10361                  as we want the top N bits of C to be zero.  */
10362               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10363
10364               temp >>= INTVAL (XEXP (op0, 1));
10365               op1 = gen_int_mode (temp, mode);
10366               op0 = XEXP (op0, 0);
10367               continue;
10368             }
10369
10370           /* If we are doing a sign bit comparison, it means we are testing
10371              a particular bit.  Convert it to the appropriate AND.  */
10372           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10373               && mode_width <= HOST_BITS_PER_WIDE_INT)
10374             {
10375               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10376                                             ((HOST_WIDE_INT) 1
10377                                              << (mode_width - 1
10378                                                  - INTVAL (XEXP (op0, 1)))));
10379               code = (code == LT ? NE : EQ);
10380               continue;
10381             }
10382
10383           /* If this an equality comparison with zero and we are shifting
10384              the low bit to the sign bit, we can convert this to an AND of the
10385              low-order bit.  */
10386           if (const_op == 0 && equality_comparison_p
10387               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10388               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10389                  == mode_width - 1)
10390             {
10391               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10392                                             (HOST_WIDE_INT) 1);
10393               continue;
10394             }
10395           break;
10396
10397         case ASHIFTRT:
10398           /* If this is an equality comparison with zero, we can do this
10399              as a logical shift, which might be much simpler.  */
10400           if (equality_comparison_p && const_op == 0
10401               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10402             {
10403               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10404                                           XEXP (op0, 0),
10405                                           INTVAL (XEXP (op0, 1)));
10406               continue;
10407             }
10408
10409           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10410              do the comparison in a narrower mode.  */
10411           if (! unsigned_comparison_p
10412               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10413               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10414               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10415               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10416                                          MODE_INT, 1)) != BLKmode
10417               && (((unsigned HOST_WIDE_INT) const_op
10418                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10419                   <= GET_MODE_MASK (tmode)))
10420             {
10421               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10422               continue;
10423             }
10424
10425           /* Likewise if OP0 is a PLUS of a sign extension with a
10426              constant, which is usually represented with the PLUS
10427              between the shifts.  */
10428           if (! unsigned_comparison_p
10429               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10430               && GET_CODE (XEXP (op0, 0)) == PLUS
10431               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10432               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10433               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10434               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10435                                          MODE_INT, 1)) != BLKmode
10436               && (((unsigned HOST_WIDE_INT) const_op
10437                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10438                   <= GET_MODE_MASK (tmode)))
10439             {
10440               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10441               rtx add_const = XEXP (XEXP (op0, 0), 1);
10442               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10443                                                    add_const, XEXP (op0, 1));
10444
10445               op0 = simplify_gen_binary (PLUS, tmode,
10446                                          gen_lowpart (tmode, inner),
10447                                          new_const);
10448               continue;
10449             }
10450
10451           /* ... fall through ...  */
10452         case LSHIFTRT:
10453           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10454              the low order N bits of FOO are known to be zero, we can do this
10455              by comparing FOO with C shifted left N bits so long as no
10456              overflow occurs.  */
10457           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10458               && INTVAL (XEXP (op0, 1)) >= 0
10459               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10460               && mode_width <= HOST_BITS_PER_WIDE_INT
10461               && (nonzero_bits (XEXP (op0, 0), mode)
10462                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10463               && (((unsigned HOST_WIDE_INT) const_op
10464                    + (GET_CODE (op0) != LSHIFTRT
10465                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10466                          + 1)
10467                       : 0))
10468                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10469             {
10470               /* If the shift was logical, then we must make the condition
10471                  unsigned.  */
10472               if (GET_CODE (op0) == LSHIFTRT)
10473                 code = unsigned_condition (code);
10474
10475               const_op <<= INTVAL (XEXP (op0, 1));
10476               op1 = GEN_INT (const_op);
10477               op0 = XEXP (op0, 0);
10478               continue;
10479             }
10480
10481           /* If we are using this shift to extract just the sign bit, we
10482              can replace this with an LT or GE comparison.  */
10483           if (const_op == 0
10484               && (equality_comparison_p || sign_bit_comparison_p)
10485               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10486               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10487                  == mode_width - 1)
10488             {
10489               op0 = XEXP (op0, 0);
10490               code = (code == NE || code == GT ? LT : GE);
10491               continue;
10492             }
10493           break;
10494
10495         default:
10496           break;
10497         }
10498
10499       break;
10500     }
10501
10502   /* Now make any compound operations involved in this comparison.  Then,
10503      check for an outmost SUBREG on OP0 that is not doing anything or is
10504      paradoxical.  The latter transformation must only be performed when
10505      it is known that the "extra" bits will be the same in op0 and op1 or
10506      that they don't matter.  There are three cases to consider:
10507
10508      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10509      care bits and we can assume they have any convenient value.  So
10510      making the transformation is safe.
10511
10512      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10513      In this case the upper bits of op0 are undefined.  We should not make
10514      the simplification in that case as we do not know the contents of
10515      those bits.
10516
10517      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10518      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10519      also be sure that they are the same as the upper bits of op1.
10520
10521      We can never remove a SUBREG for a non-equality comparison because
10522      the sign bit is in a different place in the underlying object.  */
10523
10524   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10525   op1 = make_compound_operation (op1, SET);
10526
10527   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10528       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10529       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10530       && (code == NE || code == EQ))
10531     {
10532       if (GET_MODE_SIZE (GET_MODE (op0))
10533           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10534         {
10535           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10536              implemented.  */
10537           if (REG_P (SUBREG_REG (op0)))
10538             {
10539               op0 = SUBREG_REG (op0);
10540               op1 = gen_lowpart (GET_MODE (op0), op1);
10541             }
10542         }
10543       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10544                 <= HOST_BITS_PER_WIDE_INT)
10545                && (nonzero_bits (SUBREG_REG (op0),
10546                                  GET_MODE (SUBREG_REG (op0)))
10547                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10548         {
10549           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10550
10551           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10552                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10553             op0 = SUBREG_REG (op0), op1 = tem;
10554         }
10555     }
10556
10557   /* We now do the opposite procedure: Some machines don't have compare
10558      insns in all modes.  If OP0's mode is an integer mode smaller than a
10559      word and we can't do a compare in that mode, see if there is a larger
10560      mode for which we can do the compare.  There are a number of cases in
10561      which we can use the wider mode.  */
10562
10563   mode = GET_MODE (op0);
10564   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10565       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10566       && ! have_insn_for (COMPARE, mode))
10567     for (tmode = GET_MODE_WIDER_MODE (mode);
10568          (tmode != VOIDmode
10569           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10570          tmode = GET_MODE_WIDER_MODE (tmode))
10571       if (have_insn_for (COMPARE, tmode))
10572         {
10573           int zero_extended;
10574
10575           /* If the only nonzero bits in OP0 and OP1 are those in the
10576              narrower mode and this is an equality or unsigned comparison,
10577              we can use the wider mode.  Similarly for sign-extended
10578              values, in which case it is true for all comparisons.  */
10579           zero_extended = ((code == EQ || code == NE
10580                             || code == GEU || code == GTU
10581                             || code == LEU || code == LTU)
10582                            && (nonzero_bits (op0, tmode)
10583                                & ~GET_MODE_MASK (mode)) == 0
10584                            && ((GET_CODE (op1) == CONST_INT
10585                                 || (nonzero_bits (op1, tmode)
10586                                     & ~GET_MODE_MASK (mode)) == 0)));
10587
10588           if (zero_extended
10589               || ((num_sign_bit_copies (op0, tmode)
10590                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10591                                      - GET_MODE_BITSIZE (mode)))
10592                   && (num_sign_bit_copies (op1, tmode)
10593                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10594                                         - GET_MODE_BITSIZE (mode)))))
10595             {
10596               /* If OP0 is an AND and we don't have an AND in MODE either,
10597                  make a new AND in the proper mode.  */
10598               if (GET_CODE (op0) == AND
10599                   && !have_insn_for (AND, mode))
10600                 op0 = simplify_gen_binary (AND, tmode,
10601                                            gen_lowpart (tmode,
10602                                                         XEXP (op0, 0)),
10603                                            gen_lowpart (tmode,
10604                                                         XEXP (op0, 1)));
10605
10606               op0 = gen_lowpart (tmode, op0);
10607               if (zero_extended && GET_CODE (op1) == CONST_INT)
10608                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10609               op1 = gen_lowpart (tmode, op1);
10610               break;
10611             }
10612
10613           /* If this is a test for negative, we can make an explicit
10614              test of the sign bit.  */
10615
10616           if (op1 == const0_rtx && (code == LT || code == GE)
10617               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10618             {
10619               op0 = simplify_gen_binary (AND, tmode,
10620                                          gen_lowpart (tmode, op0),
10621                                          GEN_INT ((HOST_WIDE_INT) 1
10622                                                   << (GET_MODE_BITSIZE (mode)
10623                                                       - 1)));
10624               code = (code == LT) ? NE : EQ;
10625               break;
10626             }
10627         }
10628
10629 #ifdef CANONICALIZE_COMPARISON
10630   /* If this machine only supports a subset of valid comparisons, see if we
10631      can convert an unsupported one into a supported one.  */
10632   CANONICALIZE_COMPARISON (code, op0, op1);
10633 #endif
10634
10635   *pop0 = op0;
10636   *pop1 = op1;
10637
10638   return code;
10639 }
10640 \f
10641 /* Utility function for record_value_for_reg.  Count number of
10642    rtxs in X.  */
10643 static int
10644 count_rtxs (rtx x)
10645 {
10646   enum rtx_code code = GET_CODE (x);
10647   const char *fmt;
10648   int i, ret = 1;
10649
10650   if (GET_RTX_CLASS (code) == '2'
10651       || GET_RTX_CLASS (code) == 'c')
10652     {
10653       rtx x0 = XEXP (x, 0);
10654       rtx x1 = XEXP (x, 1);
10655
10656       if (x0 == x1)
10657         return 1 + 2 * count_rtxs (x0);
10658
10659       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10660            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10661           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10662         return 2 + 2 * count_rtxs (x0)
10663                + count_rtxs (x == XEXP (x1, 0)
10664                              ? XEXP (x1, 1) : XEXP (x1, 0));
10665
10666       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10667            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10668           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10669         return 2 + 2 * count_rtxs (x1)
10670                + count_rtxs (x == XEXP (x0, 0)
10671                              ? XEXP (x0, 1) : XEXP (x0, 0));
10672     }
10673
10674   fmt = GET_RTX_FORMAT (code);
10675   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10676     if (fmt[i] == 'e')
10677       ret += count_rtxs (XEXP (x, i));
10678
10679   return ret;
10680 }
10681 \f
10682 /* Utility function for following routine.  Called when X is part of a value
10683    being stored into last_set_value.  Sets last_set_table_tick
10684    for each register mentioned.  Similar to mention_regs in cse.c  */
10685
10686 static void
10687 update_table_tick (rtx x)
10688 {
10689   enum rtx_code code = GET_CODE (x);
10690   const char *fmt = GET_RTX_FORMAT (code);
10691   int i;
10692
10693   if (code == REG)
10694     {
10695       unsigned int regno = REGNO (x);
10696       unsigned int endregno
10697         = regno + (regno < FIRST_PSEUDO_REGISTER
10698                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10699       unsigned int r;
10700
10701       for (r = regno; r < endregno; r++)
10702         reg_stat[r].last_set_table_tick = label_tick;
10703
10704       return;
10705     }
10706
10707   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10708     /* Note that we can't have an "E" in values stored; see
10709        get_last_value_validate.  */
10710     if (fmt[i] == 'e')
10711       {
10712         /* Check for identical subexpressions.  If x contains
10713            identical subexpression we only have to traverse one of
10714            them.  */
10715         if (i == 0 && ARITHMETIC_P (x))
10716           {
10717             /* Note that at this point x1 has already been
10718                processed.  */
10719             rtx x0 = XEXP (x, 0);
10720             rtx x1 = XEXP (x, 1);
10721
10722             /* If x0 and x1 are identical then there is no need to
10723                process x0.  */
10724             if (x0 == x1)
10725               break;
10726
10727             /* If x0 is identical to a subexpression of x1 then while
10728                processing x1, x0 has already been processed.  Thus we
10729                are done with x.  */
10730             if (ARITHMETIC_P (x1)
10731                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10732               break;
10733
10734             /* If x1 is identical to a subexpression of x0 then we
10735                still have to process the rest of x0.  */
10736             if (ARITHMETIC_P (x0)
10737                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10738               {
10739                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10740                 break;
10741               }
10742           }
10743
10744         update_table_tick (XEXP (x, i));
10745       }
10746 }
10747
10748 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10749    are saying that the register is clobbered and we no longer know its
10750    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10751    only permitted with VALUE also zero and is used to invalidate the
10752    register.  */
10753
10754 static void
10755 record_value_for_reg (rtx reg, rtx insn, rtx value)
10756 {
10757   unsigned int regno = REGNO (reg);
10758   unsigned int endregno
10759     = regno + (regno < FIRST_PSEUDO_REGISTER
10760                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10761   unsigned int i;
10762
10763   /* If VALUE contains REG and we have a previous value for REG, substitute
10764      the previous value.  */
10765   if (value && insn && reg_overlap_mentioned_p (reg, value))
10766     {
10767       rtx tem;
10768
10769       /* Set things up so get_last_value is allowed to see anything set up to
10770          our insn.  */
10771       subst_low_cuid = INSN_CUID (insn);
10772       tem = get_last_value (reg);
10773
10774       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10775          it isn't going to be useful and will take a lot of time to process,
10776          so just use the CLOBBER.  */
10777
10778       if (tem)
10779         {
10780           if (ARITHMETIC_P (tem)
10781               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10782               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10783             tem = XEXP (tem, 0);
10784           else if (count_occurrences (value, reg, 1) >= 2)
10785             {
10786               /* If there are two or more occurrences of REG in VALUE,
10787                  prevent the value from growing too much.  */
10788               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10789                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10790             }
10791
10792           value = replace_rtx (copy_rtx (value), reg, tem);
10793         }
10794     }
10795
10796   /* For each register modified, show we don't know its value, that
10797      we don't know about its bitwise content, that its value has been
10798      updated, and that we don't know the location of the death of the
10799      register.  */
10800   for (i = regno; i < endregno; i++)
10801     {
10802       if (insn)
10803         reg_stat[i].last_set = insn;
10804
10805       reg_stat[i].last_set_value = 0;
10806       reg_stat[i].last_set_mode = 0;
10807       reg_stat[i].last_set_nonzero_bits = 0;
10808       reg_stat[i].last_set_sign_bit_copies = 0;
10809       reg_stat[i].last_death = 0;
10810     }
10811
10812   /* Mark registers that are being referenced in this value.  */
10813   if (value)
10814     update_table_tick (value);
10815
10816   /* Now update the status of each register being set.
10817      If someone is using this register in this block, set this register
10818      to invalid since we will get confused between the two lives in this
10819      basic block.  This makes using this register always invalid.  In cse, we
10820      scan the table to invalidate all entries using this register, but this
10821      is too much work for us.  */
10822
10823   for (i = regno; i < endregno; i++)
10824     {
10825       reg_stat[i].last_set_label = label_tick;
10826       if (value && reg_stat[i].last_set_table_tick == label_tick)
10827         reg_stat[i].last_set_invalid = 1;
10828       else
10829         reg_stat[i].last_set_invalid = 0;
10830     }
10831
10832   /* The value being assigned might refer to X (like in "x++;").  In that
10833      case, we must replace it with (clobber (const_int 0)) to prevent
10834      infinite loops.  */
10835   if (value && ! get_last_value_validate (&value, insn,
10836                                           reg_stat[regno].last_set_label, 0))
10837     {
10838       value = copy_rtx (value);
10839       if (! get_last_value_validate (&value, insn,
10840                                      reg_stat[regno].last_set_label, 1))
10841         value = 0;
10842     }
10843
10844   /* For the main register being modified, update the value, the mode, the
10845      nonzero bits, and the number of sign bit copies.  */
10846
10847   reg_stat[regno].last_set_value = value;
10848
10849   if (value)
10850     {
10851       enum machine_mode mode = GET_MODE (reg);
10852       subst_low_cuid = INSN_CUID (insn);
10853       reg_stat[regno].last_set_mode = mode;
10854       if (GET_MODE_CLASS (mode) == MODE_INT
10855           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10856         mode = nonzero_bits_mode;
10857       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10858       reg_stat[regno].last_set_sign_bit_copies
10859         = num_sign_bit_copies (value, GET_MODE (reg));
10860     }
10861 }
10862
10863 /* Called via note_stores from record_dead_and_set_regs to handle one
10864    SET or CLOBBER in an insn.  DATA is the instruction in which the
10865    set is occurring.  */
10866
10867 static void
10868 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10869 {
10870   rtx record_dead_insn = (rtx) data;
10871
10872   if (GET_CODE (dest) == SUBREG)
10873     dest = SUBREG_REG (dest);
10874
10875   if (REG_P (dest))
10876     {
10877       /* If we are setting the whole register, we know its value.  Otherwise
10878          show that we don't know the value.  We can handle SUBREG in
10879          some cases.  */
10880       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10881         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10882       else if (GET_CODE (setter) == SET
10883                && GET_CODE (SET_DEST (setter)) == SUBREG
10884                && SUBREG_REG (SET_DEST (setter)) == dest
10885                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10886                && subreg_lowpart_p (SET_DEST (setter)))
10887         record_value_for_reg (dest, record_dead_insn,
10888                               gen_lowpart (GET_MODE (dest),
10889                                                        SET_SRC (setter)));
10890       else
10891         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10892     }
10893   else if (MEM_P (dest)
10894            /* Ignore pushes, they clobber nothing.  */
10895            && ! push_operand (dest, GET_MODE (dest)))
10896     mem_last_set = INSN_CUID (record_dead_insn);
10897 }
10898
10899 /* Update the records of when each REG was most recently set or killed
10900    for the things done by INSN.  This is the last thing done in processing
10901    INSN in the combiner loop.
10902
10903    We update reg_stat[], in particular fields last_set, last_set_value,
10904    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10905    last_death, and also the similar information mem_last_set (which insn
10906    most recently modified memory) and last_call_cuid (which insn was the
10907    most recent subroutine call).  */
10908
10909 static void
10910 record_dead_and_set_regs (rtx insn)
10911 {
10912   rtx link;
10913   unsigned int i;
10914
10915   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10916     {
10917       if (REG_NOTE_KIND (link) == REG_DEAD
10918           && REG_P (XEXP (link, 0)))
10919         {
10920           unsigned int regno = REGNO (XEXP (link, 0));
10921           unsigned int endregno
10922             = regno + (regno < FIRST_PSEUDO_REGISTER
10923                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10924                        : 1);
10925
10926           for (i = regno; i < endregno; i++)
10927             reg_stat[i].last_death = insn;
10928         }
10929       else if (REG_NOTE_KIND (link) == REG_INC)
10930         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10931     }
10932
10933   if (CALL_P (insn))
10934     {
10935       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10936         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10937           {
10938             reg_stat[i].last_set_value = 0;
10939             reg_stat[i].last_set_mode = 0;
10940             reg_stat[i].last_set_nonzero_bits = 0;
10941             reg_stat[i].last_set_sign_bit_copies = 0;
10942             reg_stat[i].last_death = 0;
10943           }
10944
10945       last_call_cuid = mem_last_set = INSN_CUID (insn);
10946
10947       /* Don't bother recording what this insn does.  It might set the
10948          return value register, but we can't combine into a call
10949          pattern anyway, so there's no point trying (and it may cause
10950          a crash, if e.g. we wind up asking for last_set_value of a
10951          SUBREG of the return value register).  */
10952       return;
10953     }
10954
10955   note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10956 }
10957
10958 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10959    register present in the SUBREG, so for each such SUBREG go back and
10960    adjust nonzero and sign bit information of the registers that are
10961    known to have some zero/sign bits set.
10962
10963    This is needed because when combine blows the SUBREGs away, the
10964    information on zero/sign bits is lost and further combines can be
10965    missed because of that.  */
10966
10967 static void
10968 record_promoted_value (rtx insn, rtx subreg)
10969 {
10970   rtx links, set;
10971   unsigned int regno = REGNO (SUBREG_REG (subreg));
10972   enum machine_mode mode = GET_MODE (subreg);
10973
10974   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10975     return;
10976
10977   for (links = LOG_LINKS (insn); links;)
10978     {
10979       insn = XEXP (links, 0);
10980       set = single_set (insn);
10981
10982       if (! set || !REG_P (SET_DEST (set))
10983           || REGNO (SET_DEST (set)) != regno
10984           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10985         {
10986           links = XEXP (links, 1);
10987           continue;
10988         }
10989
10990       if (reg_stat[regno].last_set == insn)
10991         {
10992           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
10993             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
10994         }
10995
10996       if (REG_P (SET_SRC (set)))
10997         {
10998           regno = REGNO (SET_SRC (set));
10999           links = LOG_LINKS (insn);
11000         }
11001       else
11002         break;
11003     }
11004 }
11005
11006 /* Scan X for promoted SUBREGs.  For each one found,
11007    note what it implies to the registers used in it.  */
11008
11009 static void
11010 check_promoted_subreg (rtx insn, rtx x)
11011 {
11012   if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11013       && REG_P (SUBREG_REG (x)))
11014     record_promoted_value (insn, x);
11015   else
11016     {
11017       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11018       int i, j;
11019
11020       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11021         switch (format[i])
11022           {
11023           case 'e':
11024             check_promoted_subreg (insn, XEXP (x, i));
11025             break;
11026           case 'V':
11027           case 'E':
11028             if (XVEC (x, i) != 0)
11029               for (j = 0; j < XVECLEN (x, i); j++)
11030                 check_promoted_subreg (insn, XVECEXP (x, i, j));
11031             break;
11032           }
11033     }
11034 }
11035 \f
11036 /* Utility routine for the following function.  Verify that all the registers
11037    mentioned in *LOC are valid when *LOC was part of a value set when
11038    label_tick == TICK.  Return 0 if some are not.
11039
11040    If REPLACE is nonzero, replace the invalid reference with
11041    (clobber (const_int 0)) and return 1.  This replacement is useful because
11042    we often can get useful information about the form of a value (e.g., if
11043    it was produced by a shift that always produces -1 or 0) even though
11044    we don't know exactly what registers it was produced from.  */
11045
11046 static int
11047 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11048 {
11049   rtx x = *loc;
11050   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11051   int len = GET_RTX_LENGTH (GET_CODE (x));
11052   int i;
11053
11054   if (REG_P (x))
11055     {
11056       unsigned int regno = REGNO (x);
11057       unsigned int endregno
11058         = regno + (regno < FIRST_PSEUDO_REGISTER
11059                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11060       unsigned int j;
11061
11062       for (j = regno; j < endregno; j++)
11063         if (reg_stat[j].last_set_invalid
11064             /* If this is a pseudo-register that was only set once and not
11065                live at the beginning of the function, it is always valid.  */
11066             || (! (regno >= FIRST_PSEUDO_REGISTER
11067                    && REG_N_SETS (regno) == 1
11068                    && (! REGNO_REG_SET_P
11069                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11070                         regno)))
11071                 && reg_stat[j].last_set_label > tick))
11072           {
11073             if (replace)
11074               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11075             return replace;
11076           }
11077
11078       return 1;
11079     }
11080   /* If this is a memory reference, make sure that there were
11081      no stores after it that might have clobbered the value.  We don't
11082      have alias info, so we assume any store invalidates it.  */
11083   else if (MEM_P (x) && !MEM_READONLY_P (x)
11084            && INSN_CUID (insn) <= mem_last_set)
11085     {
11086       if (replace)
11087         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11088       return replace;
11089     }
11090
11091   for (i = 0; i < len; i++)
11092     {
11093       if (fmt[i] == 'e')
11094         {
11095           /* Check for identical subexpressions.  If x contains
11096              identical subexpression we only have to traverse one of
11097              them.  */
11098           if (i == 1 && ARITHMETIC_P (x))
11099             {
11100               /* Note that at this point x0 has already been checked
11101                  and found valid.  */
11102               rtx x0 = XEXP (x, 0);
11103               rtx x1 = XEXP (x, 1);
11104
11105               /* If x0 and x1 are identical then x is also valid.  */
11106               if (x0 == x1)
11107                 return 1;
11108
11109               /* If x1 is identical to a subexpression of x0 then
11110                  while checking x0, x1 has already been checked.  Thus
11111                  it is valid and so as x.  */
11112               if (ARITHMETIC_P (x0)
11113                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11114                 return 1;
11115
11116               /* If x0 is identical to a subexpression of x1 then x is
11117                  valid iff the rest of x1 is valid.  */
11118               if (ARITHMETIC_P (x1)
11119                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11120                 return
11121                   get_last_value_validate (&XEXP (x1,
11122                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11123                                            insn, tick, replace);
11124             }
11125
11126           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11127                                        replace) == 0)
11128             return 0;
11129         }
11130       /* Don't bother with these.  They shouldn't occur anyway.  */
11131       else if (fmt[i] == 'E')
11132         return 0;
11133     }
11134
11135   /* If we haven't found a reason for it to be invalid, it is valid.  */
11136   return 1;
11137 }
11138
11139 /* Get the last value assigned to X, if known.  Some registers
11140    in the value may be replaced with (clobber (const_int 0)) if their value
11141    is known longer known reliably.  */
11142
11143 static rtx
11144 get_last_value (rtx x)
11145 {
11146   unsigned int regno;
11147   rtx value;
11148
11149   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11150      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11151      we cannot predict what values the "extra" bits might have.  */
11152   if (GET_CODE (x) == SUBREG
11153       && subreg_lowpart_p (x)
11154       && (GET_MODE_SIZE (GET_MODE (x))
11155           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11156       && (value = get_last_value (SUBREG_REG (x))) != 0)
11157     return gen_lowpart (GET_MODE (x), value);
11158
11159   if (!REG_P (x))
11160     return 0;
11161
11162   regno = REGNO (x);
11163   value = reg_stat[regno].last_set_value;
11164
11165   /* If we don't have a value, or if it isn't for this basic block and
11166      it's either a hard register, set more than once, or it's a live
11167      at the beginning of the function, return 0.
11168
11169      Because if it's not live at the beginning of the function then the reg
11170      is always set before being used (is never used without being set).
11171      And, if it's set only once, and it's always set before use, then all
11172      uses must have the same last value, even if it's not from this basic
11173      block.  */
11174
11175   if (value == 0
11176       || (reg_stat[regno].last_set_label != label_tick
11177           && (regno < FIRST_PSEUDO_REGISTER
11178               || REG_N_SETS (regno) != 1
11179               || (REGNO_REG_SET_P
11180                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11181                    regno)))))
11182     return 0;
11183
11184   /* If the value was set in a later insn than the ones we are processing,
11185      we can't use it even if the register was only set once.  */
11186   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11187     return 0;
11188
11189   /* If the value has all its registers valid, return it.  */
11190   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11191                                reg_stat[regno].last_set_label, 0))
11192     return value;
11193
11194   /* Otherwise, make a copy and replace any invalid register with
11195      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11196
11197   value = copy_rtx (value);
11198   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11199                                reg_stat[regno].last_set_label, 1))
11200     return value;
11201
11202   return 0;
11203 }
11204 \f
11205 /* Return nonzero if expression X refers to a REG or to memory
11206    that is set in an instruction more recent than FROM_CUID.  */
11207
11208 static int
11209 use_crosses_set_p (rtx x, int from_cuid)
11210 {
11211   const char *fmt;
11212   int i;
11213   enum rtx_code code = GET_CODE (x);
11214
11215   if (code == REG)
11216     {
11217       unsigned int regno = REGNO (x);
11218       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11219                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11220
11221 #ifdef PUSH_ROUNDING
11222       /* Don't allow uses of the stack pointer to be moved,
11223          because we don't know whether the move crosses a push insn.  */
11224       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11225         return 1;
11226 #endif
11227       for (; regno < endreg; regno++)
11228         if (reg_stat[regno].last_set
11229             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11230           return 1;
11231       return 0;
11232     }
11233
11234   if (code == MEM && mem_last_set > from_cuid)
11235     return 1;
11236
11237   fmt = GET_RTX_FORMAT (code);
11238
11239   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11240     {
11241       if (fmt[i] == 'E')
11242         {
11243           int j;
11244           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11245             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11246               return 1;
11247         }
11248       else if (fmt[i] == 'e'
11249                && use_crosses_set_p (XEXP (x, i), from_cuid))
11250         return 1;
11251     }
11252   return 0;
11253 }
11254 \f
11255 /* Define three variables used for communication between the following
11256    routines.  */
11257
11258 static unsigned int reg_dead_regno, reg_dead_endregno;
11259 static int reg_dead_flag;
11260
11261 /* Function called via note_stores from reg_dead_at_p.
11262
11263    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11264    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11265
11266 static void
11267 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11268 {
11269   unsigned int regno, endregno;
11270
11271   if (!REG_P (dest))
11272     return;
11273
11274   regno = REGNO (dest);
11275   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11276                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11277
11278   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11279     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11280 }
11281
11282 /* Return nonzero if REG is known to be dead at INSN.
11283
11284    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11285    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11286    live.  Otherwise, see if it is live or dead at the start of the basic
11287    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11288    must be assumed to be always live.  */
11289
11290 static int
11291 reg_dead_at_p (rtx reg, rtx insn)
11292 {
11293   basic_block block;
11294   unsigned int i;
11295
11296   /* Set variables for reg_dead_at_p_1.  */
11297   reg_dead_regno = REGNO (reg);
11298   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11299                                         ? hard_regno_nregs[reg_dead_regno]
11300                                                           [GET_MODE (reg)]
11301                                         : 1);
11302
11303   reg_dead_flag = 0;
11304
11305   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11306      we allow the machine description to decide whether use-and-clobber
11307      patterns are OK.  */
11308   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11309     {
11310       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11311         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11312           return 0;
11313     }
11314
11315   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11316      beginning of function.  */
11317   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11318        insn = prev_nonnote_insn (insn))
11319     {
11320       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11321       if (reg_dead_flag)
11322         return reg_dead_flag == 1 ? 1 : 0;
11323
11324       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11325         return 1;
11326     }
11327
11328   /* Get the basic block that we were in.  */
11329   if (insn == 0)
11330     block = ENTRY_BLOCK_PTR->next_bb;
11331   else
11332     {
11333       FOR_EACH_BB (block)
11334         if (insn == BB_HEAD (block))
11335           break;
11336
11337       if (block == EXIT_BLOCK_PTR)
11338         return 0;
11339     }
11340
11341   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11342     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11343       return 0;
11344
11345   return 1;
11346 }
11347 \f
11348 /* Note hard registers in X that are used.  This code is similar to
11349    that in flow.c, but much simpler since we don't care about pseudos.  */
11350
11351 static void
11352 mark_used_regs_combine (rtx x)
11353 {
11354   RTX_CODE code = GET_CODE (x);
11355   unsigned int regno;
11356   int i;
11357
11358   switch (code)
11359     {
11360     case LABEL_REF:
11361     case SYMBOL_REF:
11362     case CONST_INT:
11363     case CONST:
11364     case CONST_DOUBLE:
11365     case CONST_VECTOR:
11366     case PC:
11367     case ADDR_VEC:
11368     case ADDR_DIFF_VEC:
11369     case ASM_INPUT:
11370 #ifdef HAVE_cc0
11371     /* CC0 must die in the insn after it is set, so we don't need to take
11372        special note of it here.  */
11373     case CC0:
11374 #endif
11375       return;
11376
11377     case CLOBBER:
11378       /* If we are clobbering a MEM, mark any hard registers inside the
11379          address as used.  */
11380       if (MEM_P (XEXP (x, 0)))
11381         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11382       return;
11383
11384     case REG:
11385       regno = REGNO (x);
11386       /* A hard reg in a wide mode may really be multiple registers.
11387          If so, mark all of them just like the first.  */
11388       if (regno < FIRST_PSEUDO_REGISTER)
11389         {
11390           unsigned int endregno, r;
11391
11392           /* None of this applies to the stack, frame or arg pointers.  */
11393           if (regno == STACK_POINTER_REGNUM
11394 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11395               || regno == HARD_FRAME_POINTER_REGNUM
11396 #endif
11397 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11398               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11399 #endif
11400               || regno == FRAME_POINTER_REGNUM)
11401             return;
11402
11403           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11404           for (r = regno; r < endregno; r++)
11405             SET_HARD_REG_BIT (newpat_used_regs, r);
11406         }
11407       return;
11408
11409     case SET:
11410       {
11411         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11412            the address.  */
11413         rtx testreg = SET_DEST (x);
11414
11415         while (GET_CODE (testreg) == SUBREG
11416                || GET_CODE (testreg) == ZERO_EXTRACT
11417                || GET_CODE (testreg) == STRICT_LOW_PART)
11418           testreg = XEXP (testreg, 0);
11419
11420         if (MEM_P (testreg))
11421           mark_used_regs_combine (XEXP (testreg, 0));
11422
11423         mark_used_regs_combine (SET_SRC (x));
11424       }
11425       return;
11426
11427     default:
11428       break;
11429     }
11430
11431   /* Recursively scan the operands of this expression.  */
11432
11433   {
11434     const char *fmt = GET_RTX_FORMAT (code);
11435
11436     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11437       {
11438         if (fmt[i] == 'e')
11439           mark_used_regs_combine (XEXP (x, i));
11440         else if (fmt[i] == 'E')
11441           {
11442             int j;
11443
11444             for (j = 0; j < XVECLEN (x, i); j++)
11445               mark_used_regs_combine (XVECEXP (x, i, j));
11446           }
11447       }
11448   }
11449 }
11450 \f
11451 /* Remove register number REGNO from the dead registers list of INSN.
11452
11453    Return the note used to record the death, if there was one.  */
11454
11455 rtx
11456 remove_death (unsigned int regno, rtx insn)
11457 {
11458   rtx note = find_regno_note (insn, REG_DEAD, regno);
11459
11460   if (note)
11461     {
11462       REG_N_DEATHS (regno)--;
11463       remove_note (insn, note);
11464     }
11465
11466   return note;
11467 }
11468
11469 /* For each register (hardware or pseudo) used within expression X, if its
11470    death is in an instruction with cuid between FROM_CUID (inclusive) and
11471    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11472    list headed by PNOTES.
11473
11474    That said, don't move registers killed by maybe_kill_insn.
11475
11476    This is done when X is being merged by combination into TO_INSN.  These
11477    notes will then be distributed as needed.  */
11478
11479 static void
11480 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11481              rtx *pnotes)
11482 {
11483   const char *fmt;
11484   int len, i;
11485   enum rtx_code code = GET_CODE (x);
11486
11487   if (code == REG)
11488     {
11489       unsigned int regno = REGNO (x);
11490       rtx where_dead = reg_stat[regno].last_death;
11491       rtx before_dead, after_dead;
11492
11493       /* Don't move the register if it gets killed in between from and to.  */
11494       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11495           && ! reg_referenced_p (x, maybe_kill_insn))
11496         return;
11497
11498       /* WHERE_DEAD could be a USE insn made by combine, so first we
11499          make sure that we have insns with valid INSN_CUID values.  */
11500       before_dead = where_dead;
11501       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11502         before_dead = PREV_INSN (before_dead);
11503
11504       after_dead = where_dead;
11505       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11506         after_dead = NEXT_INSN (after_dead);
11507
11508       if (before_dead && after_dead
11509           && INSN_CUID (before_dead) >= from_cuid
11510           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11511               || (where_dead != after_dead
11512                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11513         {
11514           rtx note = remove_death (regno, where_dead);
11515
11516           /* It is possible for the call above to return 0.  This can occur
11517              when last_death points to I2 or I1 that we combined with.
11518              In that case make a new note.
11519
11520              We must also check for the case where X is a hard register
11521              and NOTE is a death note for a range of hard registers
11522              including X.  In that case, we must put REG_DEAD notes for
11523              the remaining registers in place of NOTE.  */
11524
11525           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11526               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11527                   > GET_MODE_SIZE (GET_MODE (x))))
11528             {
11529               unsigned int deadregno = REGNO (XEXP (note, 0));
11530               unsigned int deadend
11531                 = (deadregno + hard_regno_nregs[deadregno]
11532                                                [GET_MODE (XEXP (note, 0))]);
11533               unsigned int ourend
11534                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11535               unsigned int i;
11536
11537               for (i = deadregno; i < deadend; i++)
11538                 if (i < regno || i >= ourend)
11539                   REG_NOTES (where_dead)
11540                     = gen_rtx_EXPR_LIST (REG_DEAD,
11541                                          regno_reg_rtx[i],
11542                                          REG_NOTES (where_dead));
11543             }
11544
11545           /* If we didn't find any note, or if we found a REG_DEAD note that
11546              covers only part of the given reg, and we have a multi-reg hard
11547              register, then to be safe we must check for REG_DEAD notes
11548              for each register other than the first.  They could have
11549              their own REG_DEAD notes lying around.  */
11550           else if ((note == 0
11551                     || (note != 0
11552                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11553                             < GET_MODE_SIZE (GET_MODE (x)))))
11554                    && regno < FIRST_PSEUDO_REGISTER
11555                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11556             {
11557               unsigned int ourend
11558                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11559               unsigned int i, offset;
11560               rtx oldnotes = 0;
11561
11562               if (note)
11563                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11564               else
11565                 offset = 1;
11566
11567               for (i = regno + offset; i < ourend; i++)
11568                 move_deaths (regno_reg_rtx[i],
11569                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11570             }
11571
11572           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11573             {
11574               XEXP (note, 1) = *pnotes;
11575               *pnotes = note;
11576             }
11577           else
11578             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11579
11580           REG_N_DEATHS (regno)++;
11581         }
11582
11583       return;
11584     }
11585
11586   else if (GET_CODE (x) == SET)
11587     {
11588       rtx dest = SET_DEST (x);
11589
11590       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11591
11592       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11593          that accesses one word of a multi-word item, some
11594          piece of everything register in the expression is used by
11595          this insn, so remove any old death.  */
11596       /* ??? So why do we test for equality of the sizes?  */
11597
11598       if (GET_CODE (dest) == ZERO_EXTRACT
11599           || GET_CODE (dest) == STRICT_LOW_PART
11600           || (GET_CODE (dest) == SUBREG
11601               && (((GET_MODE_SIZE (GET_MODE (dest))
11602                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11603                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11604                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11605         {
11606           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11607           return;
11608         }
11609
11610       /* If this is some other SUBREG, we know it replaces the entire
11611          value, so use that as the destination.  */
11612       if (GET_CODE (dest) == SUBREG)
11613         dest = SUBREG_REG (dest);
11614
11615       /* If this is a MEM, adjust deaths of anything used in the address.
11616          For a REG (the only other possibility), the entire value is
11617          being replaced so the old value is not used in this insn.  */
11618
11619       if (MEM_P (dest))
11620         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11621                      to_insn, pnotes);
11622       return;
11623     }
11624
11625   else if (GET_CODE (x) == CLOBBER)
11626     return;
11627
11628   len = GET_RTX_LENGTH (code);
11629   fmt = GET_RTX_FORMAT (code);
11630
11631   for (i = 0; i < len; i++)
11632     {
11633       if (fmt[i] == 'E')
11634         {
11635           int j;
11636           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11637             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11638                          to_insn, pnotes);
11639         }
11640       else if (fmt[i] == 'e')
11641         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11642     }
11643 }
11644 \f
11645 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11646    pattern of an insn.  X must be a REG.  */
11647
11648 static int
11649 reg_bitfield_target_p (rtx x, rtx body)
11650 {
11651   int i;
11652
11653   if (GET_CODE (body) == SET)
11654     {
11655       rtx dest = SET_DEST (body);
11656       rtx target;
11657       unsigned int regno, tregno, endregno, endtregno;
11658
11659       if (GET_CODE (dest) == ZERO_EXTRACT)
11660         target = XEXP (dest, 0);
11661       else if (GET_CODE (dest) == STRICT_LOW_PART)
11662         target = SUBREG_REG (XEXP (dest, 0));
11663       else
11664         return 0;
11665
11666       if (GET_CODE (target) == SUBREG)
11667         target = SUBREG_REG (target);
11668
11669       if (!REG_P (target))
11670         return 0;
11671
11672       tregno = REGNO (target), regno = REGNO (x);
11673       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11674         return target == x;
11675
11676       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11677       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11678
11679       return endregno > tregno && regno < endtregno;
11680     }
11681
11682   else if (GET_CODE (body) == PARALLEL)
11683     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11684       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11685         return 1;
11686
11687   return 0;
11688 }
11689 \f
11690 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11691    as appropriate.  I3 and I2 are the insns resulting from the combination
11692    insns including FROM (I2 may be zero).
11693
11694    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11695    not need REG_DEAD notes because they are being substituted for.  This
11696    saves searching in the most common cases.
11697
11698    Each note in the list is either ignored or placed on some insns, depending
11699    on the type of note.  */
11700
11701 static void
11702 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11703                   rtx elim_i1)
11704 {
11705   rtx note, next_note;
11706   rtx tem;
11707
11708   for (note = notes; note; note = next_note)
11709     {
11710       rtx place = 0, place2 = 0;
11711
11712       /* If this NOTE references a pseudo register, ensure it references
11713          the latest copy of that register.  */
11714       if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11715           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11716         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11717
11718       next_note = XEXP (note, 1);
11719       switch (REG_NOTE_KIND (note))
11720         {
11721         case REG_BR_PROB:
11722         case REG_BR_PRED:
11723           /* Doesn't matter much where we put this, as long as it's somewhere.
11724              It is preferable to keep these notes on branches, which is most
11725              likely to be i3.  */
11726           place = i3;
11727           break;
11728
11729         case REG_VALUE_PROFILE:
11730           /* Just get rid of this note, as it is unused later anyway.  */
11731           break;
11732
11733         case REG_NON_LOCAL_GOTO:
11734           if (JUMP_P (i3))
11735             place = i3;
11736           else
11737             {
11738               gcc_assert (i2 && JUMP_P (i2));
11739               place = i2;
11740             }
11741           break;
11742
11743         case REG_EH_REGION:
11744           /* These notes must remain with the call or trapping instruction.  */
11745           if (CALL_P (i3))
11746             place = i3;
11747           else if (i2 && CALL_P (i2))
11748             place = i2;
11749           else
11750             {
11751               gcc_assert (flag_non_call_exceptions);
11752               if (may_trap_p (i3))
11753                 place = i3;
11754               else if (i2 && may_trap_p (i2))
11755                 place = i2;
11756               /* ??? Otherwise assume we've combined things such that we
11757                  can now prove that the instructions can't trap.  Drop the
11758                  note in this case.  */
11759             }
11760           break;
11761
11762         case REG_NORETURN:
11763         case REG_SETJMP:
11764           /* These notes must remain with the call.  It should not be
11765              possible for both I2 and I3 to be a call.  */
11766           if (CALL_P (i3))
11767             place = i3;
11768           else
11769             {
11770               gcc_assert (i2 && CALL_P (i2));
11771               place = i2;
11772             }
11773           break;
11774
11775         case REG_UNUSED:
11776           /* Any clobbers for i3 may still exist, and so we must process
11777              REG_UNUSED notes from that insn.
11778
11779              Any clobbers from i2 or i1 can only exist if they were added by
11780              recog_for_combine.  In that case, recog_for_combine created the
11781              necessary REG_UNUSED notes.  Trying to keep any original
11782              REG_UNUSED notes from these insns can cause incorrect output
11783              if it is for the same register as the original i3 dest.
11784              In that case, we will notice that the register is set in i3,
11785              and then add a REG_UNUSED note for the destination of i3, which
11786              is wrong.  However, it is possible to have REG_UNUSED notes from
11787              i2 or i1 for register which were both used and clobbered, so
11788              we keep notes from i2 or i1 if they will turn into REG_DEAD
11789              notes.  */
11790
11791           /* If this register is set or clobbered in I3, put the note there
11792              unless there is one already.  */
11793           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11794             {
11795               if (from_insn != i3)
11796                 break;
11797
11798               if (! (REG_P (XEXP (note, 0))
11799                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11800                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11801                 place = i3;
11802             }
11803           /* Otherwise, if this register is used by I3, then this register
11804              now dies here, so we must put a REG_DEAD note here unless there
11805              is one already.  */
11806           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11807                    && ! (REG_P (XEXP (note, 0))
11808                          ? find_regno_note (i3, REG_DEAD,
11809                                             REGNO (XEXP (note, 0)))
11810                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11811             {
11812               PUT_REG_NOTE_KIND (note, REG_DEAD);
11813               place = i3;
11814             }
11815           break;
11816
11817         case REG_EQUAL:
11818         case REG_EQUIV:
11819         case REG_NOALIAS:
11820           /* These notes say something about results of an insn.  We can
11821              only support them if they used to be on I3 in which case they
11822              remain on I3.  Otherwise they are ignored.
11823
11824              If the note refers to an expression that is not a constant, we
11825              must also ignore the note since we cannot tell whether the
11826              equivalence is still true.  It might be possible to do
11827              slightly better than this (we only have a problem if I2DEST
11828              or I1DEST is present in the expression), but it doesn't
11829              seem worth the trouble.  */
11830
11831           if (from_insn == i3
11832               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11833             place = i3;
11834           break;
11835
11836         case REG_INC:
11837         case REG_NO_CONFLICT:
11838           /* These notes say something about how a register is used.  They must
11839              be present on any use of the register in I2 or I3.  */
11840           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11841             place = i3;
11842
11843           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11844             {
11845               if (place)
11846                 place2 = i2;
11847               else
11848                 place = i2;
11849             }
11850           break;
11851
11852         case REG_LABEL:
11853           /* This can show up in several ways -- either directly in the
11854              pattern, or hidden off in the constant pool with (or without?)
11855              a REG_EQUAL note.  */
11856           /* ??? Ignore the without-reg_equal-note problem for now.  */
11857           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11858               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11859                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11860                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11861             place = i3;
11862
11863           if (i2
11864               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11865                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11866                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11867                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11868             {
11869               if (place)
11870                 place2 = i2;
11871               else
11872                 place = i2;
11873             }
11874
11875           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
11876              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
11877           if (place && JUMP_P (place))
11878             {
11879               rtx label = JUMP_LABEL (place);
11880
11881               if (!label)
11882                 JUMP_LABEL (place) = XEXP (note, 0);
11883               else
11884                 {
11885                   gcc_assert (label == XEXP (note, 0));
11886                   if (LABEL_P (label))
11887                     LABEL_NUSES (label)--;
11888                 }
11889               place = 0;
11890             }
11891           if (place2 && JUMP_P (place2))
11892             {
11893               rtx label = JUMP_LABEL (place2);
11894
11895               if (!label)
11896                 JUMP_LABEL (place2) = XEXP (note, 0);
11897               else
11898                 {
11899                   gcc_assert (label == XEXP (note, 0));
11900                   if (LABEL_P (label))
11901                     LABEL_NUSES (label)--;
11902                 }
11903               place2 = 0;
11904             }
11905           break;
11906
11907         case REG_NONNEG:
11908           /* This note says something about the value of a register prior
11909              to the execution of an insn.  It is too much trouble to see
11910              if the note is still correct in all situations.  It is better
11911              to simply delete it.  */
11912           break;
11913
11914         case REG_RETVAL:
11915           /* If the insn previously containing this note still exists,
11916              put it back where it was.  Otherwise move it to the previous
11917              insn.  Adjust the corresponding REG_LIBCALL note.  */
11918           if (!NOTE_P (from_insn))
11919             place = from_insn;
11920           else
11921             {
11922               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11923               place = prev_real_insn (from_insn);
11924               if (tem && place)
11925                 XEXP (tem, 0) = place;
11926               /* If we're deleting the last remaining instruction of a
11927                  libcall sequence, don't add the notes.  */
11928               else if (XEXP (note, 0) == from_insn)
11929                 tem = place = 0;
11930               /* Don't add the dangling REG_RETVAL note.  */
11931               else if (! tem)
11932                 place = 0;
11933             }
11934           break;
11935
11936         case REG_LIBCALL:
11937           /* This is handled similarly to REG_RETVAL.  */
11938           if (!NOTE_P (from_insn))
11939             place = from_insn;
11940           else
11941             {
11942               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11943               place = next_real_insn (from_insn);
11944               if (tem && place)
11945                 XEXP (tem, 0) = place;
11946               /* If we're deleting the last remaining instruction of a
11947                  libcall sequence, don't add the notes.  */
11948               else if (XEXP (note, 0) == from_insn)
11949                 tem = place = 0;
11950               /* Don't add the dangling REG_LIBCALL note.  */
11951               else if (! tem)
11952                 place = 0;
11953             }
11954           break;
11955
11956         case REG_DEAD:
11957           /* If the register is used as an input in I3, it dies there.
11958              Similarly for I2, if it is nonzero and adjacent to I3.
11959
11960              If the register is not used as an input in either I3 or I2
11961              and it is not one of the registers we were supposed to eliminate,
11962              there are two possibilities.  We might have a non-adjacent I2
11963              or we might have somehow eliminated an additional register
11964              from a computation.  For example, we might have had A & B where
11965              we discover that B will always be zero.  In this case we will
11966              eliminate the reference to A.
11967
11968              In both cases, we must search to see if we can find a previous
11969              use of A and put the death note there.  */
11970
11971           if (from_insn
11972               && CALL_P (from_insn)
11973               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11974             place = from_insn;
11975           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11976             place = i3;
11977           else if (i2 != 0 && next_nonnote_insn (i2) == i3
11978                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11979             place = i2;
11980
11981           if (place == 0
11982               && (rtx_equal_p (XEXP (note, 0), elim_i2)
11983                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
11984             break;
11985
11986           if (place == 0)
11987             {
11988               basic_block bb = this_basic_block;
11989
11990               /* You might think you could search back from FROM_INSN
11991                  rather than from I3, but combine tries to split invalid
11992                  combined instructions.  This can result in the old I2
11993                  or I1 moving later in the insn sequence.  */
11994               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11995                 {
11996                   if (! INSN_P (tem))
11997                     {
11998                       if (tem == BB_HEAD (bb))
11999                         break;
12000                       continue;
12001                     }
12002
12003                   /* If the register is being set at TEM, see if that is all
12004                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12005                      into a REG_UNUSED note instead. Don't delete sets to
12006                      global register vars.  */
12007                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12008                        || !global_regs[REGNO (XEXP (note, 0))])
12009                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12010                     {
12011                       rtx set = single_set (tem);
12012                       rtx inner_dest = 0;
12013 #ifdef HAVE_cc0
12014                       rtx cc0_setter = NULL_RTX;
12015 #endif
12016
12017                       if (set != 0)
12018                         for (inner_dest = SET_DEST (set);
12019                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12020                               || GET_CODE (inner_dest) == SUBREG
12021                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12022                              inner_dest = XEXP (inner_dest, 0))
12023                           ;
12024
12025                       /* Verify that it was the set, and not a clobber that
12026                          modified the register.
12027
12028                          CC0 targets must be careful to maintain setter/user
12029                          pairs.  If we cannot delete the setter due to side
12030                          effects, mark the user with an UNUSED note instead
12031                          of deleting it.  */
12032
12033                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12034                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12035 #ifdef HAVE_cc0
12036                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12037                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12038                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12039 #endif
12040                           )
12041                         {
12042                           /* Move the notes and links of TEM elsewhere.
12043                              This might delete other dead insns recursively.
12044                              First set the pattern to something that won't use
12045                              any register.  */
12046                           rtx old_notes = REG_NOTES (tem);
12047
12048                           PATTERN (tem) = pc_rtx;
12049                           REG_NOTES (tem) = NULL;
12050
12051                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12052                                             NULL_RTX, NULL_RTX);
12053                           distribute_links (LOG_LINKS (tem));
12054
12055                           SET_INSN_DELETED (tem);
12056
12057 #ifdef HAVE_cc0
12058                           /* Delete the setter too.  */
12059                           if (cc0_setter)
12060                             {
12061                               PATTERN (cc0_setter) = pc_rtx;
12062                               old_notes = REG_NOTES (cc0_setter);
12063                               REG_NOTES (cc0_setter) = NULL;
12064
12065                               distribute_notes (old_notes, cc0_setter,
12066                                                 cc0_setter, NULL_RTX,
12067                                                 NULL_RTX, NULL_RTX);
12068                               distribute_links (LOG_LINKS (cc0_setter));
12069
12070                               SET_INSN_DELETED (cc0_setter);
12071                             }
12072 #endif
12073                         }
12074                       else
12075                         {
12076                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12077
12078                           /*  If there isn't already a REG_UNUSED note, put one
12079                               here.  Do not place a REG_DEAD note, even if
12080                               the register is also used here; that would not
12081                               match the algorithm used in lifetime analysis
12082                               and can cause the consistency check in the
12083                               scheduler to fail.  */
12084                           if (! find_regno_note (tem, REG_UNUSED,
12085                                                  REGNO (XEXP (note, 0))))
12086                             place = tem;
12087                           break;
12088                         }
12089                     }
12090                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12091                            || (CALL_P (tem)
12092                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12093                     {
12094                       /* This may not be the correct place for the death
12095                          note if FROM_INSN is before TEM, and the reg is
12096                          set between FROM_INSN and TEM.  The reg might
12097                          die two or more times.  An existing death note
12098                          means we are looking at the wrong live range.  */
12099                       if (from_insn
12100                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12101                           && find_regno_note (tem, REG_DEAD,
12102                                               REGNO (XEXP (note, 0))))
12103                         {
12104                           tem = from_insn;
12105                           if (tem == BB_HEAD (bb))
12106                             break;
12107                           continue;
12108                         }
12109
12110                       place = tem;
12111
12112                       /* If we are doing a 3->2 combination, and we have a
12113                          register which formerly died in i3 and was not used
12114                          by i2, which now no longer dies in i3 and is used in
12115                          i2 but does not die in i2, and place is between i2
12116                          and i3, then we may need to move a link from place to
12117                          i2.  */
12118                       if (i2 && INSN_UID (place) <= max_uid_cuid
12119                           && INSN_CUID (place) > INSN_CUID (i2)
12120                           && from_insn
12121                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12122                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12123                         {
12124                           rtx links = LOG_LINKS (place);
12125                           LOG_LINKS (place) = 0;
12126                           distribute_links (links);
12127                         }
12128                       break;
12129                     }
12130
12131                   if (tem == BB_HEAD (bb))
12132                     break;
12133                 }
12134
12135               /* We haven't found an insn for the death note and it
12136                  is still a REG_DEAD note, but we have hit the beginning
12137                  of the block.  If the existing life info says the reg
12138                  was dead, there's nothing left to do.  Otherwise, we'll
12139                  need to do a global life update after combine.  */
12140               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12141                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12142                                       REGNO (XEXP (note, 0))))
12143                 SET_BIT (refresh_blocks, this_basic_block->index);
12144             }
12145
12146           /* If the register is set or already dead at PLACE, we needn't do
12147              anything with this note if it is still a REG_DEAD note.
12148              We check here if it is set at all, not if is it totally replaced,
12149              which is what `dead_or_set_p' checks, so also check for it being
12150              set partially.  */
12151
12152           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12153             {
12154               unsigned int regno = REGNO (XEXP (note, 0));
12155
12156               /* Similarly, if the instruction on which we want to place
12157                  the note is a noop, we'll need do a global live update
12158                  after we remove them in delete_noop_moves.  */
12159               if (noop_move_p (place))
12160                 SET_BIT (refresh_blocks, this_basic_block->index);
12161
12162               if (dead_or_set_p (place, XEXP (note, 0))
12163                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12164                 {
12165                   /* Unless the register previously died in PLACE, clear
12166                      last_death.  [I no longer understand why this is
12167                      being done.] */
12168                   if (reg_stat[regno].last_death != place)
12169                     reg_stat[regno].last_death = 0;
12170                   place = 0;
12171                 }
12172               else
12173                 reg_stat[regno].last_death = place;
12174
12175               /* If this is a death note for a hard reg that is occupying
12176                  multiple registers, ensure that we are still using all
12177                  parts of the object.  If we find a piece of the object
12178                  that is unused, we must arrange for an appropriate REG_DEAD
12179                  note to be added for it.  However, we can't just emit a USE
12180                  and tag the note to it, since the register might actually
12181                  be dead; so we recourse, and the recursive call then finds
12182                  the previous insn that used this register.  */
12183
12184               if (place && regno < FIRST_PSEUDO_REGISTER
12185                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12186                 {
12187                   unsigned int endregno
12188                     = regno + hard_regno_nregs[regno]
12189                                               [GET_MODE (XEXP (note, 0))];
12190                   int all_used = 1;
12191                   unsigned int i;
12192
12193                   for (i = regno; i < endregno; i++)
12194                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12195                          && ! find_regno_fusage (place, USE, i))
12196                         || dead_or_set_regno_p (place, i))
12197                       all_used = 0;
12198
12199                   if (! all_used)
12200                     {
12201                       /* Put only REG_DEAD notes for pieces that are
12202                          not already dead or set.  */
12203
12204                       for (i = regno; i < endregno;
12205                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12206                         {
12207                           rtx piece = regno_reg_rtx[i];
12208                           basic_block bb = this_basic_block;
12209
12210                           if (! dead_or_set_p (place, piece)
12211                               && ! reg_bitfield_target_p (piece,
12212                                                           PATTERN (place)))
12213                             {
12214                               rtx new_note
12215                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12216
12217                               distribute_notes (new_note, place, place,
12218                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12219                             }
12220                           else if (! refers_to_regno_p (i, i + 1,
12221                                                         PATTERN (place), 0)
12222                                    && ! find_regno_fusage (place, USE, i))
12223                             for (tem = PREV_INSN (place); ;
12224                                  tem = PREV_INSN (tem))
12225                               {
12226                                 if (! INSN_P (tem))
12227                                   {
12228                                     if (tem == BB_HEAD (bb))
12229                                       {
12230                                         SET_BIT (refresh_blocks,
12231                                                  this_basic_block->index);
12232                                         break;
12233                                       }
12234                                     continue;
12235                                   }
12236                                 if (dead_or_set_p (tem, piece)
12237                                     || reg_bitfield_target_p (piece,
12238                                                               PATTERN (tem)))
12239                                   {
12240                                     REG_NOTES (tem)
12241                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12242                                                            REG_NOTES (tem));
12243                                     break;
12244                                   }
12245                               }
12246
12247                         }
12248
12249                       place = 0;
12250                     }
12251                 }
12252             }
12253           break;
12254
12255         default:
12256           /* Any other notes should not be present at this point in the
12257              compilation.  */
12258           gcc_unreachable ();
12259         }
12260
12261       if (place)
12262         {
12263           XEXP (note, 1) = REG_NOTES (place);
12264           REG_NOTES (place) = note;
12265         }
12266       else if ((REG_NOTE_KIND (note) == REG_DEAD
12267                 || REG_NOTE_KIND (note) == REG_UNUSED)
12268                && REG_P (XEXP (note, 0)))
12269         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12270
12271       if (place2)
12272         {
12273           if ((REG_NOTE_KIND (note) == REG_DEAD
12274                || REG_NOTE_KIND (note) == REG_UNUSED)
12275               && REG_P (XEXP (note, 0)))
12276             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12277
12278           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12279                                                REG_NOTE_KIND (note),
12280                                                XEXP (note, 0),
12281                                                REG_NOTES (place2));
12282         }
12283     }
12284 }
12285 \f
12286 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12287    I3, I2, and I1 to new locations.  This is also called to add a link
12288    pointing at I3 when I3's destination is changed.  */
12289
12290 static void
12291 distribute_links (rtx links)
12292 {
12293   rtx link, next_link;
12294
12295   for (link = links; link; link = next_link)
12296     {
12297       rtx place = 0;
12298       rtx insn;
12299       rtx set, reg;
12300
12301       next_link = XEXP (link, 1);
12302
12303       /* If the insn that this link points to is a NOTE or isn't a single
12304          set, ignore it.  In the latter case, it isn't clear what we
12305          can do other than ignore the link, since we can't tell which
12306          register it was for.  Such links wouldn't be used by combine
12307          anyway.
12308
12309          It is not possible for the destination of the target of the link to
12310          have been changed by combine.  The only potential of this is if we
12311          replace I3, I2, and I1 by I3 and I2.  But in that case the
12312          destination of I2 also remains unchanged.  */
12313
12314       if (NOTE_P (XEXP (link, 0))
12315           || (set = single_set (XEXP (link, 0))) == 0)
12316         continue;
12317
12318       reg = SET_DEST (set);
12319       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12320              || GET_CODE (reg) == STRICT_LOW_PART)
12321         reg = XEXP (reg, 0);
12322
12323       /* A LOG_LINK is defined as being placed on the first insn that uses
12324          a register and points to the insn that sets the register.  Start
12325          searching at the next insn after the target of the link and stop
12326          when we reach a set of the register or the end of the basic block.
12327
12328          Note that this correctly handles the link that used to point from
12329          I3 to I2.  Also note that not much searching is typically done here
12330          since most links don't point very far away.  */
12331
12332       for (insn = NEXT_INSN (XEXP (link, 0));
12333            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12334                      || BB_HEAD (this_basic_block->next_bb) != insn));
12335            insn = NEXT_INSN (insn))
12336         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12337           {
12338             if (reg_referenced_p (reg, PATTERN (insn)))
12339               place = insn;
12340             break;
12341           }
12342         else if (CALL_P (insn)
12343                  && find_reg_fusage (insn, USE, reg))
12344           {
12345             place = insn;
12346             break;
12347           }
12348         else if (INSN_P (insn) && reg_set_p (reg, insn))
12349           break;
12350
12351       /* If we found a place to put the link, place it there unless there
12352          is already a link to the same insn as LINK at that point.  */
12353
12354       if (place)
12355         {
12356           rtx link2;
12357
12358           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12359             if (XEXP (link2, 0) == XEXP (link, 0))
12360               break;
12361
12362           if (link2 == 0)
12363             {
12364               XEXP (link, 1) = LOG_LINKS (place);
12365               LOG_LINKS (place) = link;
12366
12367               /* Set added_links_insn to the earliest insn we added a
12368                  link to.  */
12369               if (added_links_insn == 0
12370                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12371                 added_links_insn = place;
12372             }
12373         }
12374     }
12375 }
12376 \f
12377 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12378    Check whether the expression pointer to by LOC is a register or
12379    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12380    Otherwise return zero.  */
12381
12382 static int
12383 unmentioned_reg_p_1 (rtx *loc, void *expr)
12384 {
12385   rtx x = *loc;
12386
12387   if (x != NULL_RTX
12388       && (REG_P (x) || MEM_P (x))
12389       && ! reg_mentioned_p (x, (rtx) expr))
12390     return 1;
12391   return 0;
12392 }
12393
12394 /* Check for any register or memory mentioned in EQUIV that is not
12395    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12396    of EXPR where some registers may have been replaced by constants.  */
12397
12398 static bool
12399 unmentioned_reg_p (rtx equiv, rtx expr)
12400 {
12401   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12402 }
12403 \f
12404 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12405
12406 static int
12407 insn_cuid (rtx insn)
12408 {
12409   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12410          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12411     insn = NEXT_INSN (insn);
12412
12413   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12414
12415   return INSN_CUID (insn);
12416 }
12417 \f
12418 void
12419 dump_combine_stats (FILE *file)
12420 {
12421   fprintf
12422     (file,
12423      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12424      combine_attempts, combine_merges, combine_extras, combine_successes);
12425 }
12426
12427 void
12428 dump_combine_total_stats (FILE *file)
12429 {
12430   fprintf
12431     (file,
12432      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12433      total_attempts, total_merges, total_extras, total_successes);
12434 }
12435 \f
12436
12437 static bool
12438 gate_handle_combine (void)
12439 {
12440   return (optimize > 0);
12441 }
12442
12443 /* Try combining insns through substitution.  */
12444 static void
12445 rest_of_handle_combine (void)
12446 {
12447   int rebuild_jump_labels_after_combine
12448     = combine_instructions (get_insns (), max_reg_num ());
12449
12450   /* Combining insns may have turned an indirect jump into a
12451      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12452      instructions.  */
12453   if (rebuild_jump_labels_after_combine)
12454     {
12455       timevar_push (TV_JUMP);
12456       rebuild_jump_labels (get_insns ());
12457       timevar_pop (TV_JUMP);
12458
12459       delete_dead_jumptables ();
12460       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12461     }
12462 }
12463
12464 struct tree_opt_pass pass_combine =
12465 {
12466   "combine",                            /* name */
12467   gate_handle_combine,                  /* gate */
12468   rest_of_handle_combine,               /* execute */
12469   NULL,                                 /* sub */
12470   NULL,                                 /* next */
12471   0,                                    /* static_pass_number */
12472   TV_COMBINE,                           /* tv_id */
12473   0,                                    /* properties_required */
12474   0,                                    /* properties_provided */
12475   0,                                    /* properties_destroyed */
12476   0,                                    /* todo_flags_start */
12477   TODO_dump_func |
12478   TODO_ggc_collect,                     /* todo_flags_finish */
12479   'c'                                   /* letter */
12480 };
12481