1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload
;
87 struct target_reload
*this_target_reload
= &default_target_reload
;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx
*reg_last_reload_reg
;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload
;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload
;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width
;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber
;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid
;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead
;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs
;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global
;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET
*pseudo_previous_regs
;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET
*pseudo_forbidden_regs
;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs
;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg
;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos
;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos
;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted
;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid
;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed
;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress
= 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack
;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj
;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj
;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj
;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain
*reload_insn_chain
;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce
;
257 /* List of all insns needing reloads. */
258 static struct insn_chain
*insns_need_reload
;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from
; /* Register number to be eliminated. */
268 int to
; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
270 int can_eliminate
; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
276 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx
; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx
; /* REG rtx for the replacement. */
285 static struct elim_table
*reg_eliminate
= 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1
[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset
;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable
;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants
;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num
;
328 static char *offsets_known_at
;
329 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
331 VEC(reg_equivs_t
,gc
) *reg_equivs
;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p
,heap
);
346 static VEC(rtx_p
,heap
) *substitute_stack
;
348 /* Number of labels in the current function. */
350 static int num_labels
;
352 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain
*);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain
*, int);
357 static void find_reload_regs (struct insn_chain
*);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx
, enum reg_class
);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx
);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx
, rtx
, int);
366 static void check_eliminable_occurrences (rtx
);
367 static void elimination_effects (rtx
, enum machine_mode
);
368 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
369 static int eliminate_regs_in_insn (rtx
, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx
, const_rtx
, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx
);
376 static void init_eliminable_invariants (rtx
, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET
*);
380 static void elimination_costs_in_insn (rtx
);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx
);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain
*);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
388 static void forget_marked_reloads (regset
);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
397 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
399 static int allocate_reload_reg (struct insn_chain
*, int, int);
400 static int conflicts_with_override (rtx
);
401 static void failed_reload (rtx
, int);
402 static int set_reload_reg (int, int);
403 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
404 static void choose_reload_regs (struct insn_chain
*);
405 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
407 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
409 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
410 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
411 static void emit_reload_insns (struct insn_chain
*);
412 static void delete_output_reload (rtx
, int, int, rtx
);
413 static void delete_address_reloads (rtx
, rtx
);
414 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
415 static void inc_for_reload (rtx
, rtx
, rtx
, int);
417 static void add_auto_inc_notes (rtx
, rtx
);
419 static void substitute (rtx
*, const_rtx
, rtx
);
420 static bool gen_reload_chain_without_interm_reg_p (int, int);
421 static int reloads_conflict (int, int);
422 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
423 static rtx
emit_insn_if_valid_for_reload (rtx
);
425 /* Initialize the reload pass. This is called at the beginning of compilation
426 and may be called again if the target is reinitialized. */
433 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
434 Set spill_indirect_levels to the number of levels such addressing is
435 permitted, zero if it is not permitted at all. */
438 = gen_rtx_MEM (Pmode
,
441 LAST_VIRTUAL_REGISTER
+ 1),
443 spill_indirect_levels
= 0;
445 while (memory_address_p (QImode
, tem
))
447 spill_indirect_levels
++;
448 tem
= gen_rtx_MEM (Pmode
, tem
);
451 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
453 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
454 indirect_symref_ok
= memory_address_p (QImode
, tem
);
456 /* See if reg+reg is a valid (and offsettable) address. */
458 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
460 tem
= gen_rtx_PLUS (Pmode
,
461 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
462 gen_rtx_REG (Pmode
, i
));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem
= plus_constant (Pmode
, tem
, 4);
467 if (memory_address_p (QImode
, tem
))
469 double_reg_address_ok
= 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack
);
476 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
478 INIT_REG_SET (&spilled_pseudos
);
479 INIT_REG_SET (&changed_allocation_pseudos
);
480 INIT_REG_SET (&pseudos_counted
);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain
*unused_insn_chains
= 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain
*c
;
492 if (unused_insn_chains
== 0)
494 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
495 INIT_REG_SET (&c
->live_throughout
);
496 INIT_REG_SET (&c
->dead_or_set
);
500 c
= unused_insn_chains
;
501 unused_insn_chains
= c
->next
;
503 c
->is_caller_save_insn
= 0;
504 c
->need_operand_change
= 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
517 reg_set_iterator rsi
;
519 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
521 int r
= reg_renumber
[regno
];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p
|| reload_completed
);
532 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
553 unsigned int regno
= REGNO (x
);
555 if (regno
< FIRST_PSEUDO_REGISTER
)
558 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
562 replace_pseudos_in (loc
, mem_mode
, usage
);
566 if (reg_equiv_constant (regno
))
567 *loc
= reg_equiv_constant (regno
);
568 else if (reg_equiv_invariant (regno
))
569 *loc
= reg_equiv_invariant (regno
);
570 else if (reg_equiv_mem (regno
))
571 *loc
= reg_equiv_mem (regno
);
572 else if (reg_equiv_address (regno
))
573 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
576 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
577 || REGNO (regno_reg_rtx
[regno
]) != regno
);
578 *loc
= regno_reg_rtx
[regno
];
583 else if (code
== MEM
)
585 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
589 /* Process each of our operands recursively. */
590 fmt
= GET_RTX_FORMAT (code
);
591 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
593 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
594 else if (*fmt
== 'E')
595 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
596 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block
*tos
, *worklist
, bb
;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
617 bb
->flags
&= ~BB_REACHABLE
;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
621 *tos
++ = EXIT_BLOCK_PTR
;
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos
!= worklist
)
628 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
629 if (!(e
->flags
& EDGE_ABNORMAL
))
631 basic_block src
= e
->src
;
633 if (!(src
->flags
& BB_REACHABLE
))
635 src
->flags
|= BB_REACHABLE
;
642 /* Now see if there's a reachable block with an exceptional incoming
645 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size
= VEC_length (reg_equivs_t
, reg_equivs
);
660 int max_regno
= max_reg_num ();
663 VEC_reserve (reg_equivs_t
, gc
, reg_equivs
, max_regno
);
664 for (i
= old_size
; i
< max_regno
; i
++)
666 VEC_quick_insert (reg_equivs_t
, reg_equivs
, i
, 0);
667 memset (&VEC_index (reg_equivs_t
, reg_equivs
, i
), 0,
668 sizeof (reg_equivs_t
));
674 /* Global variables used by reload and its subroutines. */
676 /* The current basic block while in calculate_elim_costs_all_insns. */
677 static basic_block elim_bb
;
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination
;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed
;
683 /* Set by alter_regs if we spilled a register to the stack. */
684 static bool something_was_spilled
;
686 /* Nonzero means we couldn't get enough spill regs. */
689 /* Temporary array of pseudo-register number. */
690 static int *temp_pseudo_reg_arr
;
692 /* Main entry point for the reload pass.
694 FIRST is the first insn of the function being compiled.
696 GLOBAL nonzero means we were called from global_alloc
697 and should attempt to reallocate any pseudoregs that we
698 displace from hard regs we will use for reloads.
699 If GLOBAL is zero, we do not have enough information to do that,
700 so any pseudo reg that is spilled must go to the stack.
702 Return value is TRUE if reload likely left dead insns in the
703 stream and a DCE pass should be run to elimiante them. Else the
704 return value is FALSE. */
707 reload (rtx first
, int global
)
711 struct elim_table
*ep
;
715 /* Make sure even insns with volatile mem refs are recognizable. */
720 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
722 /* Make sure that the last insn in the chain
723 is not something that needs reloading. */
724 emit_note (NOTE_INSN_DELETED
);
726 /* Enable find_equiv_reg to distinguish insns made by reload. */
727 reload_first_uid
= get_max_uid ();
729 #ifdef SECONDARY_MEMORY_NEEDED
730 /* Initialize the secondary memory table. */
731 clear_secondary_mem ();
734 /* We don't have a stack slot for any spill reg yet. */
735 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
736 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
738 /* Initialize the save area information for caller-save, in case some
742 /* Compute which hard registers are now in use
743 as homes for pseudo registers.
744 This is done here rather than (eg) in global_alloc
745 because this point is reached even if not optimizing. */
746 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
749 /* A function that has a nonlocal label that can reach the exit
750 block via non-exceptional paths must save all call-saved
752 if (cfun
->has_nonlocal_label
753 && has_nonexceptional_receiver ())
754 crtl
->saves_all_registers
= 1;
756 if (crtl
->saves_all_registers
)
757 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
758 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
759 df_set_regs_ever_live (i
, true);
761 /* Find all the pseudo registers that didn't get hard regs
762 but do have known equivalent constants or memory slots.
763 These include parameters (known equivalent to parameter slots)
764 and cse'd or loop-moved constant memory addresses.
766 Record constant equivalents in reg_equiv_constant
767 so they will be substituted by find_reloads.
768 Record memory equivalents in reg_mem_equiv so they can
769 be substituted eventually by altering the REG-rtx's. */
772 reg_old_renumber
= XCNEWVEC (short, max_regno
);
773 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
774 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
775 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
777 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
779 init_eliminable_invariants (first
, true);
782 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
783 stack slots to the pseudos that lack hard regs or equivalents.
784 Do not touch virtual registers. */
786 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
787 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
788 temp_pseudo_reg_arr
[n
++] = i
;
791 /* Ask IRA to order pseudo-registers for better stack slot
793 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
795 for (i
= 0; i
< n
; i
++)
796 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
798 /* If we have some registers we think can be eliminated, scan all insns to
799 see if there is an insn that sets one of these registers to something
800 other than itself plus a constant. If so, the register cannot be
801 eliminated. Doing this scan here eliminates an extra pass through the
802 main reload loop in the most common case where register elimination
804 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
806 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
808 maybe_fix_stack_asms ();
810 insns_need_reload
= 0;
811 something_needs_elimination
= 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs
);
818 /* There can be multiple ways to eliminate a register;
819 they should be listed adjacently.
820 Elimination for any register fails only if all possible ways fail. */
821 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
824 int can_eliminate
= 0;
827 can_eliminate
|= ep
->can_eliminate
;
830 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
832 spill_hard_reg (from
, 1);
835 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
836 if (frame_pointer_needed
)
837 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
839 finish_spills (global
);
841 /* From now on, we may need to generate moves differently. We may also
842 allow modifications of insns which cause them to not be recognized.
843 Any such modifications will be cleaned up during reload itself. */
844 reload_in_progress
= 1;
846 /* This loop scans the entire function each go-round
847 and repeats until one repetition spills no additional hard regs. */
850 int something_changed
;
852 HOST_WIDE_INT starting_frame_size
;
854 starting_frame_size
= get_frame_size ();
855 something_was_spilled
= false;
857 set_initial_elim_offsets ();
858 set_initial_label_offsets ();
860 /* For each pseudo register that has an equivalent location defined,
861 try to eliminate any eliminable registers (such as the frame pointer)
862 assuming initial offsets for the replacement register, which
865 If the resulting location is directly addressable, substitute
866 the MEM we just got directly for the old REG.
868 If it is not addressable but is a constant or the sum of a hard reg
869 and constant, it is probably not addressable because the constant is
870 out of range, in that case record the address; we will generate
871 hairy code to compute the address in a register each time it is
872 needed. Similarly if it is a hard register, but one that is not
873 valid as an address register.
875 If the location is not addressable, but does not have one of the
876 above forms, assign a stack slot. We have to do this to avoid the
877 potential of producing lots of reloads if, e.g., a location involves
878 a pseudo that didn't get a hard register and has an equivalent memory
879 location that also involves a pseudo that didn't get a hard register.
881 Perhaps at some point we will improve reload_when_needed handling
882 so this problem goes away. But that's very hairy. */
884 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
885 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
887 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
890 if (strict_memory_address_addr_space_p
891 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
893 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
894 else if (CONSTANT_P (XEXP (x
, 0))
895 || (REG_P (XEXP (x
, 0))
896 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
897 || (GET_CODE (XEXP (x
, 0)) == PLUS
898 && REG_P (XEXP (XEXP (x
, 0), 0))
899 && (REGNO (XEXP (XEXP (x
, 0), 0))
900 < FIRST_PSEUDO_REGISTER
)
901 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
902 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
905 /* Make a new stack slot. Then indicate that something
906 changed so we go back and recompute offsets for
907 eliminable registers because the allocation of memory
908 below might change some offset. reg_equiv_{mem,address}
909 will be set up for this pseudo on the next pass around
911 reg_equiv_memory_loc (i
) = 0;
912 reg_equiv_init (i
) = 0;
913 alter_reg (i
, -1, true);
917 if (caller_save_needed
)
920 /* If we allocated another stack slot, redo elimination bookkeeping. */
921 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
923 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
925 /* If we have a stack frame, we must align it now. The
926 stack size may be a part of the offset computation for
927 register elimination. So if this changes the stack size,
928 then repeat the elimination bookkeeping. We don't
929 realign when there is no stack, as that will cause a
930 stack frame when none is needed should
931 STARTING_FRAME_OFFSET not be already aligned to
933 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
934 if (starting_frame_size
!= get_frame_size ())
938 if (caller_save_needed
)
940 save_call_clobbered_regs ();
941 /* That might have allocated new insn_chain structures. */
942 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
945 calculate_needs_all_insns (global
);
947 if (! ira_conflicts_p
)
948 /* Don't do it for IRA. We need this info because we don't
949 change live_throughout and dead_or_set for chains when IRA
951 CLEAR_REG_SET (&spilled_pseudos
);
955 something_changed
= 0;
957 /* If we allocated any new memory locations, make another pass
958 since it might have changed elimination offsets. */
959 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
960 something_changed
= 1;
962 /* Even if the frame size remained the same, we might still have
963 changed elimination offsets, e.g. if find_reloads called
964 force_const_mem requiring the back end to allocate a constant
965 pool base register that needs to be saved on the stack. */
966 else if (!verify_initial_elim_offsets ())
967 something_changed
= 1;
970 HARD_REG_SET to_spill
;
971 CLEAR_HARD_REG_SET (to_spill
);
972 update_eliminables (&to_spill
);
973 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
975 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
976 if (TEST_HARD_REG_BIT (to_spill
, i
))
978 spill_hard_reg (i
, 1);
981 /* Regardless of the state of spills, if we previously had
982 a register that we thought we could eliminate, but now can
983 not eliminate, we must run another pass.
985 Consider pseudos which have an entry in reg_equiv_* which
986 reference an eliminable register. We must make another pass
987 to update reg_equiv_* so that we do not substitute in the
988 old value from when we thought the elimination could be
990 something_changed
= 1;
994 select_reload_regs ();
998 if (insns_need_reload
!= 0 || did_spill
)
999 something_changed
|= finish_spills (global
);
1001 if (! something_changed
)
1004 if (caller_save_needed
)
1005 delete_caller_save_insns ();
1007 obstack_free (&reload_obstack
, reload_firstobj
);
1010 /* If global-alloc was run, notify it of any register eliminations we have
1013 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1014 if (ep
->can_eliminate
)
1015 mark_elimination (ep
->from
, ep
->to
);
1017 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1018 If that insn didn't set the register (i.e., it copied the register to
1019 memory), just delete that insn instead of the equivalencing insn plus
1020 anything now dead. If we call delete_dead_insn on that insn, we may
1021 delete the insn that actually sets the register if the register dies
1022 there and that is incorrect. */
1024 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1026 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
1029 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
1031 rtx equiv_insn
= XEXP (list
, 0);
1033 /* If we already deleted the insn or if it may trap, we can't
1034 delete it. The latter case shouldn't happen, but can
1035 if an insn has a variable address, gets a REG_EH_REGION
1036 note added to it, and then gets converted into a load
1037 from a constant address. */
1038 if (NOTE_P (equiv_insn
)
1039 || can_throw_internal (equiv_insn
))
1041 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1042 delete_dead_insn (equiv_insn
);
1044 SET_INSN_DELETED (equiv_insn
);
1049 /* Use the reload registers where necessary
1050 by generating move instructions to move the must-be-register
1051 values into or out of the reload registers. */
1053 if (insns_need_reload
!= 0 || something_needs_elimination
1054 || something_needs_operands_changed
)
1056 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1058 reload_as_needed (global
);
1060 gcc_assert (old_frame_size
== get_frame_size ());
1062 gcc_assert (verify_initial_elim_offsets ());
1065 /* If we were able to eliminate the frame pointer, show that it is no
1066 longer live at the start of any basic block. If it ls live by
1067 virtue of being in a pseudo, that pseudo will be marked live
1068 and hence the frame pointer will be known to be live via that
1071 if (! frame_pointer_needed
)
1073 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1075 /* Come here (with failure set nonzero) if we can't get enough spill
1079 CLEAR_REG_SET (&changed_allocation_pseudos
);
1080 CLEAR_REG_SET (&spilled_pseudos
);
1081 reload_in_progress
= 0;
1083 /* Now eliminate all pseudo regs by modifying them into
1084 their equivalent memory references.
1085 The REG-rtx's for the pseudos are modified in place,
1086 so all insns that used to refer to them now refer to memory.
1088 For a reg that has a reg_equiv_address, all those insns
1089 were changed by reloading so that no insns refer to it any longer;
1090 but the DECL_RTL of a variable decl may refer to it,
1091 and if so this causes the debugging info to mention the variable. */
1093 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1097 if (reg_equiv_mem (i
))
1098 addr
= XEXP (reg_equiv_mem (i
), 0);
1100 if (reg_equiv_address (i
))
1101 addr
= reg_equiv_address (i
);
1105 if (reg_renumber
[i
] < 0)
1107 rtx reg
= regno_reg_rtx
[i
];
1109 REG_USERVAR_P (reg
) = 0;
1110 PUT_CODE (reg
, MEM
);
1111 XEXP (reg
, 0) = addr
;
1112 if (reg_equiv_memory_loc (i
))
1113 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1115 MEM_ATTRS (reg
) = 0;
1116 MEM_NOTRAP_P (reg
) = 1;
1118 else if (reg_equiv_mem (i
))
1119 XEXP (reg_equiv_mem (i
), 0) = addr
;
1122 /* We don't want complex addressing modes in debug insns
1123 if simpler ones will do, so delegitimize equivalences
1125 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1127 rtx reg
= regno_reg_rtx
[i
];
1131 if (reg_equiv_constant (i
))
1132 equiv
= reg_equiv_constant (i
);
1133 else if (reg_equiv_invariant (i
))
1134 equiv
= reg_equiv_invariant (i
);
1135 else if (reg
&& MEM_P (reg
))
1136 equiv
= targetm
.delegitimize_address (reg
);
1137 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1143 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1145 insn
= DF_REF_INSN (use
);
1147 /* Make sure the next ref is for a different instruction,
1148 so that we're not affected by the rescan. */
1149 next
= DF_REF_NEXT_REG (use
);
1150 while (next
&& DF_REF_INSN (next
) == insn
)
1151 next
= DF_REF_NEXT_REG (next
);
1153 if (DEBUG_INSN_P (insn
))
1157 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1158 df_insn_rescan_debug_internal (insn
);
1161 INSN_VAR_LOCATION_LOC (insn
)
1162 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1169 /* We must set reload_completed now since the cleanup_subreg_operands call
1170 below will re-recognize each insn and reload may have generated insns
1171 which are only valid during and after reload. */
1172 reload_completed
= 1;
1174 /* Make a pass over all the insns and delete all USEs which we inserted
1175 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1176 notes. Delete all CLOBBER insns, except those that refer to the return
1177 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1178 from misarranging variable-array code, and simplify (subreg (reg))
1179 operands. Strip and regenerate REG_INC notes that may have been moved
1182 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1188 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1189 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1191 if ((GET_CODE (PATTERN (insn
)) == USE
1192 /* We mark with QImode USEs introduced by reload itself. */
1193 && (GET_MODE (insn
) == QImode
1194 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1195 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1196 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1197 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1198 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1199 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1200 != stack_pointer_rtx
))
1201 && (!REG_P (XEXP (PATTERN (insn
), 0))
1202 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1208 /* Some CLOBBERs may survive until here and still reference unassigned
1209 pseudos with const equivalent, which may in turn cause ICE in later
1210 passes if the reference remains in place. */
1211 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1212 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1213 VOIDmode
, PATTERN (insn
));
1215 /* Discard obvious no-ops, even without -O. This optimization
1216 is fast and doesn't interfere with debugging. */
1217 if (NONJUMP_INSN_P (insn
)
1218 && GET_CODE (PATTERN (insn
)) == SET
1219 && REG_P (SET_SRC (PATTERN (insn
)))
1220 && REG_P (SET_DEST (PATTERN (insn
)))
1221 && (REGNO (SET_SRC (PATTERN (insn
)))
1222 == REGNO (SET_DEST (PATTERN (insn
)))))
1228 pnote
= ®_NOTES (insn
);
1231 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1232 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1233 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1234 *pnote
= XEXP (*pnote
, 1);
1236 pnote
= &XEXP (*pnote
, 1);
1240 add_auto_inc_notes (insn
, PATTERN (insn
));
1243 /* Simplify (subreg (reg)) if it appears as an operand. */
1244 cleanup_subreg_operands (insn
);
1246 /* Clean up invalid ASMs so that they don't confuse later passes.
1248 if (asm_noperands (PATTERN (insn
)) >= 0)
1250 extract_insn (insn
);
1251 if (!constrain_operands (1))
1253 error_for_asm (insn
,
1254 "%<asm%> operand has impossible constraints");
1261 /* If we are doing generic stack checking, give a warning if this
1262 function's frame size is larger than we expect. */
1263 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1265 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1266 static int verbose_warned
= 0;
1268 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1269 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1270 size
+= UNITS_PER_WORD
;
1272 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1274 warning (0, "frame size too large for reliable stack checking");
1275 if (! verbose_warned
)
1277 warning (0, "try reducing the number of local variables");
1283 free (temp_pseudo_reg_arr
);
1285 /* Indicate that we no longer have known memory locations or constants. */
1288 free (reg_max_ref_width
);
1289 free (reg_old_renumber
);
1290 free (pseudo_previous_regs
);
1291 free (pseudo_forbidden_regs
);
1293 CLEAR_HARD_REG_SET (used_spill_regs
);
1294 for (i
= 0; i
< n_spills
; i
++)
1295 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1297 /* Free all the insn_chain structures at once. */
1298 obstack_free (&reload_obstack
, reload_startobj
);
1299 unused_insn_chains
= 0;
1301 inserted
= fixup_abnormal_edges ();
1303 /* We've possibly turned single trapping insn into multiple ones. */
1304 if (cfun
->can_throw_non_call_exceptions
)
1307 blocks
= sbitmap_alloc (last_basic_block
);
1308 sbitmap_ones (blocks
);
1309 find_many_sub_basic_blocks (blocks
);
1310 sbitmap_free (blocks
);
1314 commit_edge_insertions ();
1316 /* Replacing pseudos with their memory equivalents might have
1317 created shared rtx. Subsequent passes would get confused
1318 by this, so unshare everything here. */
1319 unshare_all_rtl_again (first
);
1321 #ifdef STACK_BOUNDARY
1322 /* init_emit has set the alignment of the hard frame pointer
1323 to STACK_BOUNDARY. It is very likely no longer valid if
1324 the hard frame pointer was used for register allocation. */
1325 if (!frame_pointer_needed
)
1326 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1329 VEC_free (rtx_p
, heap
, substitute_stack
);
1331 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1333 reload_completed
= !failure
;
1338 /* Yet another special case. Unfortunately, reg-stack forces people to
1339 write incorrect clobbers in asm statements. These clobbers must not
1340 cause the register to appear in bad_spill_regs, otherwise we'll call
1341 fatal_insn later. We clear the corresponding regnos in the live
1342 register sets to avoid this.
1343 The whole thing is rather sick, I'm afraid. */
1346 maybe_fix_stack_asms (void)
1349 const char *constraints
[MAX_RECOG_OPERANDS
];
1350 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1351 struct insn_chain
*chain
;
1353 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1356 HARD_REG_SET clobbered
, allowed
;
1359 if (! INSN_P (chain
->insn
)
1360 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1362 pat
= PATTERN (chain
->insn
);
1363 if (GET_CODE (pat
) != PARALLEL
)
1366 CLEAR_HARD_REG_SET (clobbered
);
1367 CLEAR_HARD_REG_SET (allowed
);
1369 /* First, make a mask of all stack regs that are clobbered. */
1370 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1372 rtx t
= XVECEXP (pat
, 0, i
);
1373 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1374 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1377 /* Get the operand values and constraints out of the insn. */
1378 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1379 constraints
, operand_mode
, NULL
);
1381 /* For every operand, see what registers are allowed. */
1382 for (i
= 0; i
< noperands
; i
++)
1384 const char *p
= constraints
[i
];
1385 /* For every alternative, we compute the class of registers allowed
1386 for reloading in CLS, and merge its contents into the reg set
1388 int cls
= (int) NO_REGS
;
1394 if (c
== '\0' || c
== ',' || c
== '#')
1396 /* End of one alternative - mark the regs in the current
1397 class, and reset the class. */
1398 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1404 } while (c
!= '\0' && c
!= ',');
1412 case '=': case '+': case '*': case '%': case '?': case '!':
1413 case '0': case '1': case '2': case '3': case '4': case '<':
1414 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1415 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1416 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1417 case TARGET_MEM_CONSTRAINT
:
1421 cls
= (int) reg_class_subunion
[cls
]
1422 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1428 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1432 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1433 cls
= (int) reg_class_subunion
[cls
]
1434 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1437 cls
= (int) reg_class_subunion
[cls
]
1438 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1440 p
+= CONSTRAINT_LEN (c
, p
);
1443 /* Those of the registers which are clobbered, but allowed by the
1444 constraints, must be usable as reload registers. So clear them
1445 out of the life information. */
1446 AND_HARD_REG_SET (allowed
, clobbered
);
1447 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1448 if (TEST_HARD_REG_BIT (allowed
, i
))
1450 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1451 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1458 /* Copy the global variables n_reloads and rld into the corresponding elts
1461 copy_reloads (struct insn_chain
*chain
)
1463 chain
->n_reloads
= n_reloads
;
1464 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1465 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1466 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1469 /* Walk the chain of insns, and determine for each whether it needs reloads
1470 and/or eliminations. Build the corresponding insns_need_reload list, and
1471 set something_needs_elimination as appropriate. */
1473 calculate_needs_all_insns (int global
)
1475 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1476 struct insn_chain
*chain
, *next
= 0;
1478 something_needs_elimination
= 0;
1480 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1481 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1483 rtx insn
= chain
->insn
;
1487 /* Clear out the shortcuts. */
1488 chain
->n_reloads
= 0;
1489 chain
->need_elim
= 0;
1490 chain
->need_reload
= 0;
1491 chain
->need_operand_change
= 0;
1493 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1494 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1495 what effects this has on the known offsets at labels. */
1497 if (LABEL_P (insn
) || JUMP_P (insn
)
1498 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1499 set_label_offsets (insn
, insn
, 0);
1503 rtx old_body
= PATTERN (insn
);
1504 int old_code
= INSN_CODE (insn
);
1505 rtx old_notes
= REG_NOTES (insn
);
1506 int did_elimination
= 0;
1507 int operands_changed
= 0;
1508 rtx set
= single_set (insn
);
1510 /* Skip insns that only set an equivalence. */
1511 if (set
&& REG_P (SET_DEST (set
))
1512 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1513 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1514 || (reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1515 && reg_equiv_init (REGNO (SET_DEST (set
))))
1518 /* If needed, eliminate any eliminable registers. */
1519 if (num_eliminable
|| num_eliminable_invariants
)
1520 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1522 /* Analyze the instruction. */
1523 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1524 global
, spill_reg_order
);
1526 /* If a no-op set needs more than one reload, this is likely
1527 to be something that needs input address reloads. We
1528 can't get rid of this cleanly later, and it is of no use
1529 anyway, so discard it now.
1530 We only do this when expensive_optimizations is enabled,
1531 since this complements reload inheritance / output
1532 reload deletion, and it can make debugging harder. */
1533 if (flag_expensive_optimizations
&& n_reloads
> 1)
1535 rtx set
= single_set (insn
);
1538 ((SET_SRC (set
) == SET_DEST (set
)
1539 && REG_P (SET_SRC (set
))
1540 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1541 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1542 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1543 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1544 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1545 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1546 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1547 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1549 if (ira_conflicts_p
)
1550 /* Inform IRA about the insn deletion. */
1551 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1552 REGNO (SET_SRC (set
)));
1554 /* Delete it from the reload chain. */
1556 chain
->prev
->next
= next
;
1558 reload_insn_chain
= next
;
1560 next
->prev
= chain
->prev
;
1561 chain
->next
= unused_insn_chains
;
1562 unused_insn_chains
= chain
;
1567 update_eliminable_offsets ();
1569 /* Remember for later shortcuts which insns had any reloads or
1570 register eliminations. */
1571 chain
->need_elim
= did_elimination
;
1572 chain
->need_reload
= n_reloads
> 0;
1573 chain
->need_operand_change
= operands_changed
;
1575 /* Discard any register replacements done. */
1576 if (did_elimination
)
1578 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1579 PATTERN (insn
) = old_body
;
1580 INSN_CODE (insn
) = old_code
;
1581 REG_NOTES (insn
) = old_notes
;
1582 something_needs_elimination
= 1;
1585 something_needs_operands_changed
|= operands_changed
;
1589 copy_reloads (chain
);
1590 *pprev_reload
= chain
;
1591 pprev_reload
= &chain
->next_need_reload
;
1598 /* This function is called from the register allocator to set up estimates
1599 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1600 an invariant. The structure is similar to calculate_needs_all_insns. */
1603 calculate_elim_costs_all_insns (void)
1605 int *reg_equiv_init_cost
;
1609 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1611 init_eliminable_invariants (get_insns (), false);
1613 set_initial_elim_offsets ();
1614 set_initial_label_offsets ();
1621 FOR_BB_INSNS (bb
, insn
)
1623 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1624 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1625 what effects this has on the known offsets at labels. */
1627 if (LABEL_P (insn
) || JUMP_P (insn
)
1628 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1629 set_label_offsets (insn
, insn
, 0);
1633 rtx set
= single_set (insn
);
1635 /* Skip insns that only set an equivalence. */
1636 if (set
&& REG_P (SET_DEST (set
))
1637 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1638 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1639 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1641 unsigned regno
= REGNO (SET_DEST (set
));
1642 rtx init
= reg_equiv_init (regno
);
1645 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1647 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1648 int freq
= REG_FREQ_FROM_BB (bb
);
1650 reg_equiv_init_cost
[regno
] = cost
* freq
;
1654 /* If needed, eliminate any eliminable registers. */
1655 if (num_eliminable
|| num_eliminable_invariants
)
1656 elimination_costs_in_insn (insn
);
1659 update_eliminable_offsets ();
1663 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1665 if (reg_equiv_invariant (i
))
1667 if (reg_equiv_init (i
))
1669 int cost
= reg_equiv_init_cost
[i
];
1672 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1674 ira_adjust_equiv_reg_cost (i
, cost
);
1680 "Reg %d had equivalence, but can't be eliminated\n",
1682 ira_adjust_equiv_reg_cost (i
, 0);
1687 free (reg_equiv_init_cost
);
1688 free (offsets_known_at
);
1691 offsets_known_at
= NULL
;
1694 /* Comparison function for qsort to decide which of two reloads
1695 should be handled first. *P1 and *P2 are the reload numbers. */
1698 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1700 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1703 /* Consider required reloads before optional ones. */
1704 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1708 /* Count all solitary classes before non-solitary ones. */
1709 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1710 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1714 /* Aside from solitaires, consider all multi-reg groups first. */
1715 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1719 /* Consider reloads in order of increasing reg-class number. */
1720 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1724 /* If reloads are equally urgent, sort by reload number,
1725 so that the results of qsort leave nothing to chance. */
1729 /* The cost of spilling each hard reg. */
1730 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1732 /* When spilling multiple hard registers, we use SPILL_COST for the first
1733 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1734 only the first hard reg for a multi-reg pseudo. */
1735 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1737 /* Map of hard regno to pseudo regno currently occupying the hard
1739 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1741 /* Update the spill cost arrays, considering that pseudo REG is live. */
1744 count_pseudo (int reg
)
1746 int freq
= REG_FREQ (reg
);
1747 int r
= reg_renumber
[reg
];
1750 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1751 if (ira_conflicts_p
&& r
< 0)
1754 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1755 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1758 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1760 gcc_assert (r
>= 0);
1762 spill_add_cost
[r
] += freq
;
1763 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1766 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1767 spill_cost
[r
+ nregs
] += freq
;
1771 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1772 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1775 order_regs_for_reload (struct insn_chain
*chain
)
1778 HARD_REG_SET used_by_pseudos
;
1779 HARD_REG_SET used_by_pseudos2
;
1780 reg_set_iterator rsi
;
1782 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1784 memset (spill_cost
, 0, sizeof spill_cost
);
1785 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1786 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1787 hard_regno_to_pseudo_regno
[i
] = -1;
1789 /* Count number of uses of each hard reg by pseudo regs allocated to it
1790 and then order them by decreasing use. First exclude hard registers
1791 that are live in or across this insn. */
1793 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1794 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1795 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1796 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1798 /* Now find out which pseudos are allocated to it, and update
1800 CLEAR_REG_SET (&pseudos_counted
);
1802 EXECUTE_IF_SET_IN_REG_SET
1803 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1807 EXECUTE_IF_SET_IN_REG_SET
1808 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1812 CLEAR_REG_SET (&pseudos_counted
);
1815 /* Vector of reload-numbers showing the order in which the reloads should
1817 static short reload_order
[MAX_RELOADS
];
1819 /* This is used to keep track of the spill regs used in one insn. */
1820 static HARD_REG_SET used_spill_regs_local
;
1822 /* We decided to spill hard register SPILLED, which has a size of
1823 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1824 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1825 update SPILL_COST/SPILL_ADD_COST. */
1828 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1830 int freq
= REG_FREQ (reg
);
1831 int r
= reg_renumber
[reg
];
1834 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1835 if (ira_conflicts_p
&& r
< 0)
1838 gcc_assert (r
>= 0);
1840 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1842 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1843 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1846 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1848 spill_add_cost
[r
] -= freq
;
1851 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1852 spill_cost
[r
+ nregs
] -= freq
;
1856 /* Find reload register to use for reload number ORDER. */
1859 find_reg (struct insn_chain
*chain
, int order
)
1861 int rnum
= reload_order
[order
];
1862 struct reload
*rl
= rld
+ rnum
;
1863 int best_cost
= INT_MAX
;
1865 unsigned int i
, j
, n
;
1867 HARD_REG_SET not_usable
;
1868 HARD_REG_SET used_by_other_reload
;
1869 reg_set_iterator rsi
;
1870 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1871 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1873 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1874 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1875 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1877 CLEAR_HARD_REG_SET (used_by_other_reload
);
1878 for (k
= 0; k
< order
; k
++)
1880 int other
= reload_order
[k
];
1882 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1883 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1884 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1887 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1889 #ifdef REG_ALLOC_ORDER
1890 unsigned int regno
= reg_alloc_order
[i
];
1892 unsigned int regno
= i
;
1895 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1896 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1897 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1899 int this_cost
= spill_cost
[regno
];
1901 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1903 for (j
= 1; j
< this_nregs
; j
++)
1905 this_cost
+= spill_add_cost
[regno
+ j
];
1906 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1907 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1913 if (ira_conflicts_p
)
1915 /* Ask IRA to find a better pseudo-register for
1917 for (n
= j
= 0; j
< this_nregs
; j
++)
1919 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1923 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1924 regno_pseudo_regs
[n
++] = r
;
1926 regno_pseudo_regs
[n
++] = -1;
1928 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1929 best_regno_pseudo_regs
,
1936 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1937 if (regno_pseudo_regs
[j
] < 0)
1944 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1946 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1948 if (this_cost
< best_cost
1949 /* Among registers with equal cost, prefer caller-saved ones, or
1950 use REG_ALLOC_ORDER if it is defined. */
1951 || (this_cost
== best_cost
1952 #ifdef REG_ALLOC_ORDER
1953 && (inv_reg_alloc_order
[regno
]
1954 < inv_reg_alloc_order
[best_reg
])
1956 && call_used_regs
[regno
]
1957 && ! call_used_regs
[best_reg
]
1962 best_cost
= this_cost
;
1970 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1972 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1973 rl
->regno
= best_reg
;
1975 EXECUTE_IF_SET_IN_REG_SET
1976 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1978 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1981 EXECUTE_IF_SET_IN_REG_SET
1982 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1984 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1987 for (i
= 0; i
< rl
->nregs
; i
++)
1989 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1990 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1991 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1992 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1997 /* Find more reload regs to satisfy the remaining need of an insn, which
1999 Do it by ascending class number, since otherwise a reg
2000 might be spilled for a big class and might fail to count
2001 for a smaller class even though it belongs to that class. */
2004 find_reload_regs (struct insn_chain
*chain
)
2008 /* In order to be certain of getting the registers we need,
2009 we must sort the reloads into order of increasing register class.
2010 Then our grabbing of reload registers will parallel the process
2011 that provided the reload registers. */
2012 for (i
= 0; i
< chain
->n_reloads
; i
++)
2014 /* Show whether this reload already has a hard reg. */
2015 if (chain
->rld
[i
].reg_rtx
)
2017 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2018 chain
->rld
[i
].regno
= regno
;
2020 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2023 chain
->rld
[i
].regno
= -1;
2024 reload_order
[i
] = i
;
2027 n_reloads
= chain
->n_reloads
;
2028 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2030 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2033 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2035 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2037 /* Compute the order of preference for hard registers to spill. */
2039 order_regs_for_reload (chain
);
2041 for (i
= 0; i
< n_reloads
; i
++)
2043 int r
= reload_order
[i
];
2045 /* Ignore reloads that got marked inoperative. */
2046 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2047 && ! rld
[r
].optional
2048 && rld
[r
].regno
== -1)
2049 if (! find_reg (chain
, i
))
2052 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2053 spill_failure (chain
->insn
, rld
[r
].rclass
);
2059 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2060 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2062 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2066 select_reload_regs (void)
2068 struct insn_chain
*chain
;
2070 /* Try to satisfy the needs for each insn. */
2071 for (chain
= insns_need_reload
; chain
!= 0;
2072 chain
= chain
->next_need_reload
)
2073 find_reload_regs (chain
);
2076 /* Delete all insns that were inserted by emit_caller_save_insns during
2079 delete_caller_save_insns (void)
2081 struct insn_chain
*c
= reload_insn_chain
;
2085 while (c
!= 0 && c
->is_caller_save_insn
)
2087 struct insn_chain
*next
= c
->next
;
2090 if (c
== reload_insn_chain
)
2091 reload_insn_chain
= next
;
2095 next
->prev
= c
->prev
;
2097 c
->prev
->next
= next
;
2098 c
->next
= unused_insn_chains
;
2099 unused_insn_chains
= c
;
2107 /* Handle the failure to find a register to spill.
2108 INSN should be one of the insns which needed this particular spill reg. */
2111 spill_failure (rtx insn
, enum reg_class rclass
)
2113 if (asm_noperands (PATTERN (insn
)) >= 0)
2114 error_for_asm (insn
, "can%'t find a register in class %qs while "
2115 "reloading %<asm%>",
2116 reg_class_names
[rclass
]);
2119 error ("unable to find a register to spill in class %qs",
2120 reg_class_names
[rclass
]);
2124 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2125 debug_reload_to_stream (dump_file
);
2127 fatal_insn ("this is the insn:", insn
);
2131 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2132 data that is dead in INSN. */
2135 delete_dead_insn (rtx insn
)
2137 rtx prev
= prev_active_insn (insn
);
2140 /* If the previous insn sets a register that dies in our insn make
2141 a note that we want to run DCE immediately after reload.
2143 We used to delete the previous insn & recurse, but that's wrong for
2144 block local equivalences. Instead of trying to figure out the exact
2145 circumstances where we can delete the potentially dead insns, just
2146 let DCE do the job. */
2147 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2148 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2149 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2150 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2151 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2154 SET_INSN_DELETED (insn
);
2157 /* Modify the home of pseudo-reg I.
2158 The new home is present in reg_renumber[I].
2160 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2161 or it may be -1, meaning there is none or it is not relevant.
2162 This is used so that all pseudos spilled from a given hard reg
2163 can share one stack slot. */
2166 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2168 /* When outputting an inline function, this can happen
2169 for a reg that isn't actually used. */
2170 if (regno_reg_rtx
[i
] == 0)
2173 /* If the reg got changed to a MEM at rtl-generation time,
2175 if (!REG_P (regno_reg_rtx
[i
]))
2178 /* Modify the reg-rtx to contain the new hard reg
2179 number or else to contain its pseudo reg number. */
2180 SET_REGNO (regno_reg_rtx
[i
],
2181 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2183 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2184 allocate a stack slot for it. */
2186 if (reg_renumber
[i
] < 0
2187 && REG_N_REFS (i
) > 0
2188 && reg_equiv_constant (i
) == 0
2189 && (reg_equiv_invariant (i
) == 0
2190 || reg_equiv_init (i
) == 0)
2191 && reg_equiv_memory_loc (i
) == 0)
2194 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2195 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2196 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2197 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2198 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2201 something_was_spilled
= true;
2203 if (ira_conflicts_p
)
2205 /* Mark the spill for IRA. */
2206 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2208 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2214 /* Each pseudo reg has an inherent size which comes from its own mode,
2215 and a total size which provides room for paradoxical subregs
2216 which refer to the pseudo reg in wider modes.
2218 We can use a slot already allocated if it provides both
2219 enough inherent space and enough total space.
2220 Otherwise, we allocate a new slot, making sure that it has no less
2221 inherent space, and no less total space, then the previous slot. */
2222 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2226 /* No known place to spill from => no slot to reuse. */
2227 x
= assign_stack_local (mode
, total_size
,
2228 min_align
> inherent_align
2229 || total_size
> inherent_size
? -1 : 0);
2233 /* Cancel the big-endian correction done in assign_stack_local.
2234 Get the address of the beginning of the slot. This is so we
2235 can do a big-endian correction unconditionally below. */
2236 if (BYTES_BIG_ENDIAN
)
2238 adjust
= inherent_size
- total_size
;
2241 = adjust_address_nv (x
, mode_for_size (total_size
2247 if (! dont_share_p
&& ira_conflicts_p
)
2248 /* Inform IRA about allocation a new stack slot. */
2249 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2252 /* Reuse a stack slot if possible. */
2253 else if (spill_stack_slot
[from_reg
] != 0
2254 && spill_stack_slot_width
[from_reg
] >= total_size
2255 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2257 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2258 x
= spill_stack_slot
[from_reg
];
2260 /* Allocate a bigger slot. */
2263 /* Compute maximum size needed, both for inherent size
2264 and for total size. */
2267 if (spill_stack_slot
[from_reg
])
2269 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2271 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2272 if (spill_stack_slot_width
[from_reg
] > total_size
)
2273 total_size
= spill_stack_slot_width
[from_reg
];
2274 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2275 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2278 /* Make a slot with that size. */
2279 x
= assign_stack_local (mode
, total_size
,
2280 min_align
> inherent_align
2281 || total_size
> inherent_size
? -1 : 0);
2284 /* Cancel the big-endian correction done in assign_stack_local.
2285 Get the address of the beginning of the slot. This is so we
2286 can do a big-endian correction unconditionally below. */
2287 if (BYTES_BIG_ENDIAN
)
2289 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2292 = adjust_address_nv (x
, mode_for_size (total_size
2298 spill_stack_slot
[from_reg
] = stack_slot
;
2299 spill_stack_slot_width
[from_reg
] = total_size
;
2302 /* On a big endian machine, the "address" of the slot
2303 is the address of the low part that fits its inherent mode. */
2304 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2305 adjust
+= (total_size
- inherent_size
);
2307 /* If we have any adjustment to make, or if the stack slot is the
2308 wrong mode, make a new stack slot. */
2309 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2311 /* Set all of the memory attributes as appropriate for a spill. */
2312 set_mem_attrs_for_spill (x
);
2314 /* Save the stack slot for later. */
2315 reg_equiv_memory_loc (i
) = x
;
2319 /* Mark the slots in regs_ever_live for the hard regs used by
2320 pseudo-reg number REGNO, accessed in MODE. */
2323 mark_home_live_1 (int regno
, enum machine_mode mode
)
2327 i
= reg_renumber
[regno
];
2330 lim
= end_hard_regno (mode
, i
);
2332 df_set_regs_ever_live(i
++, true);
2335 /* Mark the slots in regs_ever_live for the hard regs
2336 used by pseudo-reg number REGNO. */
2339 mark_home_live (int regno
)
2341 if (reg_renumber
[regno
] >= 0)
2342 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2345 /* This function handles the tracking of elimination offsets around branches.
2347 X is a piece of RTL being scanned.
2349 INSN is the insn that it came from, if any.
2351 INITIAL_P is nonzero if we are to set the offset to be the initial
2352 offset and zero if we are setting the offset of the label to be the
2356 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2358 enum rtx_code code
= GET_CODE (x
);
2361 struct elim_table
*p
;
2366 if (LABEL_REF_NONLOCAL_P (x
))
2371 /* ... fall through ... */
2374 /* If we know nothing about this label, set the desired offsets. Note
2375 that this sets the offset at a label to be the offset before a label
2376 if we don't know anything about the label. This is not correct for
2377 the label after a BARRIER, but is the best guess we can make. If
2378 we guessed wrong, we will suppress an elimination that might have
2379 been possible had we been able to guess correctly. */
2381 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2383 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2384 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2385 = (initial_p
? reg_eliminate
[i
].initial_offset
2386 : reg_eliminate
[i
].offset
);
2387 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2390 /* Otherwise, if this is the definition of a label and it is
2391 preceded by a BARRIER, set our offsets to the known offset of
2395 && (tem
= prev_nonnote_insn (insn
)) != 0
2397 set_offsets_for_label (insn
);
2399 /* If neither of the above cases is true, compare each offset
2400 with those previously recorded and suppress any eliminations
2401 where the offsets disagree. */
2403 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2404 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2405 != (initial_p
? reg_eliminate
[i
].initial_offset
2406 : reg_eliminate
[i
].offset
))
2407 reg_eliminate
[i
].can_eliminate
= 0;
2412 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2414 /* ... fall through ... */
2418 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2419 to indirectly and hence must have all eliminations at their
2421 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2422 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2423 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2429 /* Each of the labels in the parallel or address vector must be
2430 at their initial offsets. We want the first field for PARALLEL
2431 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2433 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2434 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2439 /* We only care about setting PC. If the source is not RETURN,
2440 IF_THEN_ELSE, or a label, disable any eliminations not at
2441 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2442 isn't one of those possibilities. For branches to a label,
2443 call ourselves recursively.
2445 Note that this can disable elimination unnecessarily when we have
2446 a non-local goto since it will look like a non-constant jump to
2447 someplace in the current function. This isn't a significant
2448 problem since such jumps will normally be when all elimination
2449 pairs are back to their initial offsets. */
2451 if (SET_DEST (x
) != pc_rtx
)
2454 switch (GET_CODE (SET_SRC (x
)))
2461 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2465 tem
= XEXP (SET_SRC (x
), 1);
2466 if (GET_CODE (tem
) == LABEL_REF
)
2467 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2468 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2471 tem
= XEXP (SET_SRC (x
), 2);
2472 if (GET_CODE (tem
) == LABEL_REF
)
2473 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2474 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2482 /* If we reach here, all eliminations must be at their initial
2483 offset because we are doing a jump to a variable address. */
2484 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2485 if (p
->offset
!= p
->initial_offset
)
2486 p
->can_eliminate
= 0;
2494 /* Called through for_each_rtx, this function examines every reg that occurs
2495 in PX and adjusts the costs for its elimination which are gathered by IRA.
2496 DATA is the insn in which PX occurs. We do not recurse into MEM
2500 note_reg_elim_costly (rtx
*px
, void *data
)
2502 rtx insn
= (rtx
)data
;
2509 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2510 && reg_equiv_init (REGNO (x
))
2511 && reg_equiv_invariant (REGNO (x
)))
2513 rtx t
= reg_equiv_invariant (REGNO (x
));
2514 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2515 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2516 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2519 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2524 /* Scan X and replace any eliminable registers (such as fp) with a
2525 replacement (such as sp), plus an offset.
2527 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2528 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2529 MEM, we are allowed to replace a sum of a register and the constant zero
2530 with the register, which we cannot do outside a MEM. In addition, we need
2531 to record the fact that a register is referenced outside a MEM.
2533 If INSN is an insn, it is the insn containing X. If we replace a REG
2534 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2535 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2536 the REG is being modified.
2538 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2539 That's used when we eliminate in expressions stored in notes.
2540 This means, do not set ref_outside_mem even if the reference
2543 If FOR_COSTS is true, we are being called before reload in order to
2544 estimate the costs of keeping registers with an equivalence unallocated.
2546 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2547 replacements done assuming all offsets are at their initial values. If
2548 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2549 encounter, return the actual location so that find_reloads will do
2550 the proper thing. */
2553 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2554 bool may_use_invariant
, bool for_costs
)
2556 enum rtx_code code
= GET_CODE (x
);
2557 struct elim_table
*ep
;
2564 if (! current_function_decl
)
2587 /* First handle the case where we encounter a bare register that
2588 is eliminable. Replace it with a PLUS. */
2589 if (regno
< FIRST_PSEUDO_REGISTER
)
2591 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2593 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2594 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2597 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2599 && reg_equiv_invariant (regno
))
2601 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2602 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2603 mem_mode
, insn
, true, for_costs
);
2604 /* There exists at least one use of REGNO that cannot be
2605 eliminated. Prevent the defining insn from being deleted. */
2606 reg_equiv_init (regno
) = NULL_RTX
;
2608 alter_reg (regno
, -1, true);
2612 /* You might think handling MINUS in a manner similar to PLUS is a
2613 good idea. It is not. It has been tried multiple times and every
2614 time the change has had to have been reverted.
2616 Other parts of reload know a PLUS is special (gen_reload for example)
2617 and require special code to handle code a reloaded PLUS operand.
2619 Also consider backends where the flags register is clobbered by a
2620 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2621 lea instruction comes to mind). If we try to reload a MINUS, we
2622 may kill the flags register that was holding a useful value.
2624 So, please before trying to handle MINUS, consider reload as a
2625 whole instead of this little section as well as the backend issues. */
2627 /* If this is the sum of an eliminable register and a constant, rework
2629 if (REG_P (XEXP (x
, 0))
2630 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2631 && CONSTANT_P (XEXP (x
, 1)))
2633 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2635 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2637 /* The only time we want to replace a PLUS with a REG (this
2638 occurs when the constant operand of the PLUS is the negative
2639 of the offset) is when we are inside a MEM. We won't want
2640 to do so at other times because that would change the
2641 structure of the insn in a way that reload can't handle.
2642 We special-case the commonest situation in
2643 eliminate_regs_in_insn, so just replace a PLUS with a
2644 PLUS here, unless inside a MEM. */
2645 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2646 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2649 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2650 plus_constant (Pmode
, XEXP (x
, 1),
2651 ep
->previous_offset
));
2654 /* If the register is not eliminable, we are done since the other
2655 operand is a constant. */
2659 /* If this is part of an address, we want to bring any constant to the
2660 outermost PLUS. We will do this by doing register replacement in
2661 our operands and seeing if a constant shows up in one of them.
2663 Note that there is no risk of modifying the structure of the insn,
2664 since we only get called for its operands, thus we are either
2665 modifying the address inside a MEM, or something like an address
2666 operand of a load-address insn. */
2669 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2671 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2674 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2676 /* If one side is a PLUS and the other side is a pseudo that
2677 didn't get a hard register but has a reg_equiv_constant,
2678 we must replace the constant here since it may no longer
2679 be in the position of any operand. */
2680 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2681 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2682 && reg_renumber
[REGNO (new1
)] < 0
2684 && reg_equiv_constant (REGNO (new1
)) != 0)
2685 new1
= reg_equiv_constant (REGNO (new1
));
2686 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2687 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2688 && reg_renumber
[REGNO (new0
)] < 0
2689 && reg_equiv_constant (REGNO (new0
)) != 0)
2690 new0
= reg_equiv_constant (REGNO (new0
));
2692 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2694 /* As above, if we are not inside a MEM we do not want to
2695 turn a PLUS into something else. We might try to do so here
2696 for an addition of 0 if we aren't optimizing. */
2697 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2698 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2706 /* If this is the product of an eliminable register and a
2707 constant, apply the distribute law and move the constant out
2708 so that we have (plus (mult ..) ..). This is needed in order
2709 to keep load-address insns valid. This case is pathological.
2710 We ignore the possibility of overflow here. */
2711 if (REG_P (XEXP (x
, 0))
2712 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2713 && CONST_INT_P (XEXP (x
, 1)))
2714 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2716 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2719 /* Refs inside notes or in DEBUG_INSNs don't count for
2721 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2722 || GET_CODE (insn
) == INSN_LIST
2723 || DEBUG_INSN_P (insn
))))
2724 ep
->ref_outside_mem
= 1;
2727 plus_constant (Pmode
,
2728 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2729 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2732 /* ... fall through ... */
2736 /* See comments before PLUS about handling MINUS. */
2738 case DIV
: case UDIV
:
2739 case MOD
: case UMOD
:
2740 case AND
: case IOR
: case XOR
:
2741 case ROTATERT
: case ROTATE
:
2742 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2744 case GE
: case GT
: case GEU
: case GTU
:
2745 case LE
: case LT
: case LEU
: case LTU
:
2747 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2749 rtx new1
= XEXP (x
, 1)
2750 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2753 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2754 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2759 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2762 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2764 if (new_rtx
!= XEXP (x
, 0))
2766 /* If this is a REG_DEAD note, it is not valid anymore.
2767 Using the eliminated version could result in creating a
2768 REG_DEAD note for the stack or frame pointer. */
2769 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2771 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2775 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2779 /* ... fall through ... */
2782 /* Now do eliminations in the rest of the chain. If this was
2783 an EXPR_LIST, this might result in allocating more memory than is
2784 strictly needed, but it simplifies the code. */
2787 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2789 if (new_rtx
!= XEXP (x
, 1))
2791 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2799 /* We do not support elimination of a register that is modified.
2800 elimination_effects has already make sure that this does not
2806 /* We do not support elimination of a register that is modified.
2807 elimination_effects has already make sure that this does not
2808 happen. The only remaining case we need to consider here is
2809 that the increment value may be an eliminable register. */
2810 if (GET_CODE (XEXP (x
, 1)) == PLUS
2811 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2813 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2814 insn
, true, for_costs
);
2816 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2817 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2818 gen_rtx_PLUS (GET_MODE (x
),
2819 XEXP (x
, 0), new_rtx
));
2823 case STRICT_LOW_PART
:
2825 case SIGN_EXTEND
: case ZERO_EXTEND
:
2826 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2827 case FLOAT
: case FIX
:
2828 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2837 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2839 if (new_rtx
!= XEXP (x
, 0))
2840 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2844 /* Similar to above processing, but preserve SUBREG_BYTE.
2845 Convert (subreg (mem)) to (mem) if not paradoxical.
2846 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2847 pseudo didn't get a hard reg, we must replace this with the
2848 eliminated version of the memory location because push_reload
2849 may do the replacement in certain circumstances. */
2850 if (REG_P (SUBREG_REG (x
))
2851 && !paradoxical_subreg_p (x
)
2853 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2855 new_rtx
= SUBREG_REG (x
);
2858 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2860 if (new_rtx
!= SUBREG_REG (x
))
2862 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2863 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2866 && ((x_size
< new_size
2867 #ifdef WORD_REGISTER_OPERATIONS
2868 /* On these machines, combine can create rtl of the form
2869 (set (subreg:m1 (reg:m2 R) 0) ...)
2870 where m1 < m2, and expects something interesting to
2871 happen to the entire word. Moreover, it will use the
2872 (reg:m2 R) later, expecting all bits to be preserved.
2873 So if the number of words is the same, preserve the
2874 subreg so that push_reload can see it. */
2875 && ! ((x_size
- 1) / UNITS_PER_WORD
2876 == (new_size
-1 ) / UNITS_PER_WORD
)
2879 || x_size
== new_size
)
2881 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2883 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2889 /* Our only special processing is to pass the mode of the MEM to our
2890 recursive call and copy the flags. While we are here, handle this
2891 case more efficiently. */
2893 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2896 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2897 && !memory_address_p (GET_MODE (x
), new_rtx
))
2898 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2900 return replace_equiv_address_nv (x
, new_rtx
);
2903 /* Handle insn_list USE that a call to a pure function may generate. */
2904 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2906 if (new_rtx
!= XEXP (x
, 0))
2907 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2912 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2922 /* Process each of our operands recursively. If any have changed, make a
2924 fmt
= GET_RTX_FORMAT (code
);
2925 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2929 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2931 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2933 x
= shallow_copy_rtx (x
);
2936 XEXP (x
, i
) = new_rtx
;
2938 else if (*fmt
== 'E')
2941 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2943 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2945 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2947 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2951 x
= shallow_copy_rtx (x
);
2954 XVEC (x
, i
) = new_v
;
2957 XVECEXP (x
, i
, j
) = new_rtx
;
2966 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2968 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2971 /* Scan rtx X for modifications of elimination target registers. Update
2972 the table of eliminables to reflect the changed state. MEM_MODE is
2973 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2976 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2978 enum rtx_code code
= GET_CODE (x
);
2979 struct elim_table
*ep
;
3004 /* First handle the case where we encounter a bare register that
3005 is eliminable. Replace it with a PLUS. */
3006 if (regno
< FIRST_PSEUDO_REGISTER
)
3008 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3010 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3013 ep
->ref_outside_mem
= 1;
3018 else if (reg_renumber
[regno
] < 0
3020 && reg_equiv_constant (regno
)
3021 && ! function_invariant_p (reg_equiv_constant (regno
)))
3022 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3031 /* If we modify the source of an elimination rule, disable it. */
3032 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3033 if (ep
->from_rtx
== XEXP (x
, 0))
3034 ep
->can_eliminate
= 0;
3036 /* If we modify the target of an elimination rule by adding a constant,
3037 update its offset. If we modify the target in any other way, we'll
3038 have to disable the rule as well. */
3039 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3040 if (ep
->to_rtx
== XEXP (x
, 0))
3042 int size
= GET_MODE_SIZE (mem_mode
);
3044 /* If more bytes than MEM_MODE are pushed, account for them. */
3045 #ifdef PUSH_ROUNDING
3046 if (ep
->to_rtx
== stack_pointer_rtx
)
3047 size
= PUSH_ROUNDING (size
);
3049 if (code
== PRE_DEC
|| code
== POST_DEC
)
3051 else if (code
== PRE_INC
|| code
== POST_INC
)
3053 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3055 if (GET_CODE (XEXP (x
, 1)) == PLUS
3056 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3057 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3058 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3060 ep
->can_eliminate
= 0;
3064 /* These two aren't unary operators. */
3065 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3068 /* Fall through to generic unary operation case. */
3069 case STRICT_LOW_PART
:
3071 case SIGN_EXTEND
: case ZERO_EXTEND
:
3072 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3073 case FLOAT
: case FIX
:
3074 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3083 elimination_effects (XEXP (x
, 0), mem_mode
);
3087 if (REG_P (SUBREG_REG (x
))
3088 && (GET_MODE_SIZE (GET_MODE (x
))
3089 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3091 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3094 elimination_effects (SUBREG_REG (x
), mem_mode
);
3098 /* If using a register that is the source of an eliminate we still
3099 think can be performed, note it cannot be performed since we don't
3100 know how this register is used. */
3101 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3102 if (ep
->from_rtx
== XEXP (x
, 0))
3103 ep
->can_eliminate
= 0;
3105 elimination_effects (XEXP (x
, 0), mem_mode
);
3109 /* If clobbering a register that is the replacement register for an
3110 elimination we still think can be performed, note that it cannot
3111 be performed. Otherwise, we need not be concerned about it. */
3112 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3113 if (ep
->to_rtx
== XEXP (x
, 0))
3114 ep
->can_eliminate
= 0;
3116 elimination_effects (XEXP (x
, 0), mem_mode
);
3120 /* Check for setting a register that we know about. */
3121 if (REG_P (SET_DEST (x
)))
3123 /* See if this is setting the replacement register for an
3126 If DEST is the hard frame pointer, we do nothing because we
3127 assume that all assignments to the frame pointer are for
3128 non-local gotos and are being done at a time when they are valid
3129 and do not disturb anything else. Some machines want to
3130 eliminate a fake argument pointer (or even a fake frame pointer)
3131 with either the real frame or the stack pointer. Assignments to
3132 the hard frame pointer must not prevent this elimination. */
3134 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3136 if (ep
->to_rtx
== SET_DEST (x
)
3137 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3139 /* If it is being incremented, adjust the offset. Otherwise,
3140 this elimination can't be done. */
3141 rtx src
= SET_SRC (x
);
3143 if (GET_CODE (src
) == PLUS
3144 && XEXP (src
, 0) == SET_DEST (x
)
3145 && CONST_INT_P (XEXP (src
, 1)))
3146 ep
->offset
-= INTVAL (XEXP (src
, 1));
3148 ep
->can_eliminate
= 0;
3152 elimination_effects (SET_DEST (x
), VOIDmode
);
3153 elimination_effects (SET_SRC (x
), VOIDmode
);
3157 /* Our only special processing is to pass the mode of the MEM to our
3159 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3166 fmt
= GET_RTX_FORMAT (code
);
3167 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3170 elimination_effects (XEXP (x
, i
), mem_mode
);
3171 else if (*fmt
== 'E')
3172 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3173 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3177 /* Descend through rtx X and verify that no references to eliminable registers
3178 remain. If any do remain, mark the involved register as not
3182 check_eliminable_occurrences (rtx x
)
3191 code
= GET_CODE (x
);
3193 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3195 struct elim_table
*ep
;
3197 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3198 if (ep
->from_rtx
== x
)
3199 ep
->can_eliminate
= 0;
3203 fmt
= GET_RTX_FORMAT (code
);
3204 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3207 check_eliminable_occurrences (XEXP (x
, i
));
3208 else if (*fmt
== 'E')
3211 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3212 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3217 /* Scan INSN and eliminate all eliminable registers in it.
3219 If REPLACE is nonzero, do the replacement destructively. Also
3220 delete the insn as dead it if it is setting an eliminable register.
3222 If REPLACE is zero, do all our allocations in reload_obstack.
3224 If no eliminations were done and this insn doesn't require any elimination
3225 processing (these are not identical conditions: it might be updating sp,
3226 but not referencing fp; this needs to be seen during reload_as_needed so
3227 that the offset between fp and sp can be taken into consideration), zero
3228 is returned. Otherwise, 1 is returned. */
3231 eliminate_regs_in_insn (rtx insn
, int replace
)
3233 int icode
= recog_memoized (insn
);
3234 rtx old_body
= PATTERN (insn
);
3235 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3236 rtx old_set
= single_set (insn
);
3240 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3241 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3242 struct elim_table
*ep
;
3243 rtx plus_src
, plus_cst_src
;
3245 if (! insn_is_asm
&& icode
< 0)
3247 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3248 || GET_CODE (PATTERN (insn
)) == CLOBBER
3249 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3250 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3251 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3252 || DEBUG_INSN_P (insn
));
3253 if (DEBUG_INSN_P (insn
))
3254 INSN_VAR_LOCATION_LOC (insn
)
3255 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3259 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3260 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3262 /* Check for setting an eliminable register. */
3263 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3264 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3266 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3267 /* If this is setting the frame pointer register to the
3268 hardware frame pointer register and this is an elimination
3269 that will be done (tested above), this insn is really
3270 adjusting the frame pointer downward to compensate for
3271 the adjustment done before a nonlocal goto. */
3272 if (ep
->from
== FRAME_POINTER_REGNUM
3273 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3275 rtx base
= SET_SRC (old_set
);
3276 rtx base_insn
= insn
;
3277 HOST_WIDE_INT offset
= 0;
3279 while (base
!= ep
->to_rtx
)
3281 rtx prev_insn
, prev_set
;
3283 if (GET_CODE (base
) == PLUS
3284 && CONST_INT_P (XEXP (base
, 1)))
3286 offset
+= INTVAL (XEXP (base
, 1));
3287 base
= XEXP (base
, 0);
3289 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3290 && (prev_set
= single_set (prev_insn
)) != 0
3291 && rtx_equal_p (SET_DEST (prev_set
), base
))
3293 base
= SET_SRC (prev_set
);
3294 base_insn
= prev_insn
;
3300 if (base
== ep
->to_rtx
)
3302 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3303 offset
- ep
->offset
);
3305 new_body
= old_body
;
3308 new_body
= copy_insn (old_body
);
3309 if (REG_NOTES (insn
))
3310 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3312 PATTERN (insn
) = new_body
;
3313 old_set
= single_set (insn
);
3315 /* First see if this insn remains valid when we
3316 make the change. If not, keep the INSN_CODE
3317 the same and let reload fit it up. */
3318 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3319 validate_change (insn
, &SET_DEST (old_set
),
3321 if (! apply_change_group ())
3323 SET_SRC (old_set
) = src
;
3324 SET_DEST (old_set
) = ep
->to_rtx
;
3333 /* In this case this insn isn't serving a useful purpose. We
3334 will delete it in reload_as_needed once we know that this
3335 elimination is, in fact, being done.
3337 If REPLACE isn't set, we can't delete this insn, but needn't
3338 process it since it won't be used unless something changes. */
3341 delete_dead_insn (insn
);
3349 /* We allow one special case which happens to work on all machines we
3350 currently support: a single set with the source or a REG_EQUAL
3351 note being a PLUS of an eliminable register and a constant. */
3352 plus_src
= plus_cst_src
= 0;
3353 if (old_set
&& REG_P (SET_DEST (old_set
)))
3355 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3356 plus_src
= SET_SRC (old_set
);
3357 /* First see if the source is of the form (plus (...) CST). */
3359 && CONST_INT_P (XEXP (plus_src
, 1)))
3360 plus_cst_src
= plus_src
;
3361 else if (REG_P (SET_SRC (old_set
))
3364 /* Otherwise, see if we have a REG_EQUAL note of the form
3365 (plus (...) CST). */
3367 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3369 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3370 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3371 && GET_CODE (XEXP (links
, 0)) == PLUS
3372 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3374 plus_cst_src
= XEXP (links
, 0);
3380 /* Check that the first operand of the PLUS is a hard reg or
3381 the lowpart subreg of one. */
3384 rtx reg
= XEXP (plus_cst_src
, 0);
3385 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3386 reg
= SUBREG_REG (reg
);
3388 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3394 rtx reg
= XEXP (plus_cst_src
, 0);
3395 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3397 if (GET_CODE (reg
) == SUBREG
)
3398 reg
= SUBREG_REG (reg
);
3400 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3401 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3403 rtx to_rtx
= ep
->to_rtx
;
3404 offset
+= ep
->offset
;
3405 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3407 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3408 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3410 /* If we have a nonzero offset, and the source is already
3411 a simple REG, the following transformation would
3412 increase the cost of the insn by replacing a simple REG
3413 with (plus (reg sp) CST). So try only when we already
3414 had a PLUS before. */
3415 if (offset
== 0 || plus_src
)
3417 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3420 new_body
= old_body
;
3423 new_body
= copy_insn (old_body
);
3424 if (REG_NOTES (insn
))
3425 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3427 PATTERN (insn
) = new_body
;
3428 old_set
= single_set (insn
);
3430 /* First see if this insn remains valid when we make the
3431 change. If not, try to replace the whole pattern with
3432 a simple set (this may help if the original insn was a
3433 PARALLEL that was only recognized as single_set due to
3434 REG_UNUSED notes). If this isn't valid either, keep
3435 the INSN_CODE the same and let reload fix it up. */
3436 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3438 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3439 SET_DEST (old_set
), new_src
);
3441 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3442 SET_SRC (old_set
) = new_src
;
3449 /* This can't have an effect on elimination offsets, so skip right
3455 /* Determine the effects of this insn on elimination offsets. */
3456 elimination_effects (old_body
, VOIDmode
);
3458 /* Eliminate all eliminable registers occurring in operands that
3459 can be handled by reload. */
3460 extract_insn (insn
);
3461 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3463 orig_operand
[i
] = recog_data
.operand
[i
];
3464 substed_operand
[i
] = recog_data
.operand
[i
];
3466 /* For an asm statement, every operand is eliminable. */
3467 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3469 bool is_set_src
, in_plus
;
3471 /* Check for setting a register that we know about. */
3472 if (recog_data
.operand_type
[i
] != OP_IN
3473 && REG_P (orig_operand
[i
]))
3475 /* If we are assigning to a register that can be eliminated, it
3476 must be as part of a PARALLEL, since the code above handles
3477 single SETs. We must indicate that we can no longer
3478 eliminate this reg. */
3479 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3481 if (ep
->from_rtx
== orig_operand
[i
])
3482 ep
->can_eliminate
= 0;
3485 /* Companion to the above plus substitution, we can allow
3486 invariants as the source of a plain move. */
3489 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3493 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3494 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3498 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3499 replace
? insn
: NULL_RTX
,
3500 is_set_src
|| in_plus
, false);
3501 if (substed_operand
[i
] != orig_operand
[i
])
3503 /* Terminate the search in check_eliminable_occurrences at
3505 *recog_data
.operand_loc
[i
] = 0;
3507 /* If an output operand changed from a REG to a MEM and INSN is an
3508 insn, write a CLOBBER insn. */
3509 if (recog_data
.operand_type
[i
] != OP_IN
3510 && REG_P (orig_operand
[i
])
3511 && MEM_P (substed_operand
[i
])
3513 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3517 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3518 *recog_data
.dup_loc
[i
]
3519 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3521 /* If any eliminable remain, they aren't eliminable anymore. */
3522 check_eliminable_occurrences (old_body
);
3524 /* Substitute the operands; the new values are in the substed_operand
3526 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3527 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3528 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3529 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3531 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3532 re-recognize the insn. We do this in case we had a simple addition
3533 but now can do this as a load-address. This saves an insn in this
3535 If re-recognition fails, the old insn code number will still be used,
3536 and some register operands may have changed into PLUS expressions.
3537 These will be handled by find_reloads by loading them into a register
3542 /* If we aren't replacing things permanently and we changed something,
3543 make another copy to ensure that all the RTL is new. Otherwise
3544 things can go wrong if find_reload swaps commutative operands
3545 and one is inside RTL that has been copied while the other is not. */
3546 new_body
= old_body
;
3549 new_body
= copy_insn (old_body
);
3550 if (REG_NOTES (insn
))
3551 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3553 PATTERN (insn
) = new_body
;
3555 /* If we had a move insn but now we don't, rerecognize it. This will
3556 cause spurious re-recognition if the old move had a PARALLEL since
3557 the new one still will, but we can't call single_set without
3558 having put NEW_BODY into the insn and the re-recognition won't
3559 hurt in this rare case. */
3560 /* ??? Why this huge if statement - why don't we just rerecognize the
3564 && ((REG_P (SET_SRC (old_set
))
3565 && (GET_CODE (new_body
) != SET
3566 || !REG_P (SET_SRC (new_body
))))
3567 /* If this was a load from or store to memory, compare
3568 the MEM in recog_data.operand to the one in the insn.
3569 If they are not equal, then rerecognize the insn. */
3571 && ((MEM_P (SET_SRC (old_set
))
3572 && SET_SRC (old_set
) != recog_data
.operand
[1])
3573 || (MEM_P (SET_DEST (old_set
))
3574 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3575 /* If this was an add insn before, rerecognize. */
3576 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3578 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3580 INSN_CODE (insn
) = new_icode
;
3584 /* Restore the old body. If there were any changes to it, we made a copy
3585 of it while the changes were still in place, so we'll correctly return
3586 a modified insn below. */
3589 /* Restore the old body. */
3590 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3591 /* Restoring a top-level match_parallel would clobber the new_body
3592 we installed in the insn. */
3593 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3594 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3595 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3596 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3599 /* Update all elimination pairs to reflect the status after the current
3600 insn. The changes we make were determined by the earlier call to
3601 elimination_effects.
3603 We also detect cases where register elimination cannot be done,
3604 namely, if a register would be both changed and referenced outside a MEM
3605 in the resulting insn since such an insn is often undefined and, even if
3606 not, we cannot know what meaning will be given to it. Note that it is
3607 valid to have a register used in an address in an insn that changes it
3608 (presumably with a pre- or post-increment or decrement).
3610 If anything changes, return nonzero. */
3612 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3614 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3615 ep
->can_eliminate
= 0;
3617 ep
->ref_outside_mem
= 0;
3619 if (ep
->previous_offset
!= ep
->offset
)
3624 /* If we changed something, perform elimination in REG_NOTES. This is
3625 needed even when REPLACE is zero because a REG_DEAD note might refer
3626 to a register that we eliminate and could cause a different number
3627 of spill registers to be needed in the final reload pass than in
3629 if (val
&& REG_NOTES (insn
) != 0)
3631 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3637 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3638 register allocator. INSN is the instruction we need to examine, we perform
3639 eliminations in its operands and record cases where eliminating a reg with
3640 an invariant equivalence would add extra cost. */
3643 elimination_costs_in_insn (rtx insn
)
3645 int icode
= recog_memoized (insn
);
3646 rtx old_body
= PATTERN (insn
);
3647 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3648 rtx old_set
= single_set (insn
);
3650 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3651 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3652 struct elim_table
*ep
;
3653 rtx plus_src
, plus_cst_src
;
3656 if (! insn_is_asm
&& icode
< 0)
3658 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3659 || GET_CODE (PATTERN (insn
)) == CLOBBER
3660 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3661 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3662 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
3663 || DEBUG_INSN_P (insn
));
3667 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3668 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3670 /* Check for setting an eliminable register. */
3671 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3672 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3676 /* We allow one special case which happens to work on all machines we
3677 currently support: a single set with the source or a REG_EQUAL
3678 note being a PLUS of an eliminable register and a constant. */
3679 plus_src
= plus_cst_src
= 0;
3681 if (old_set
&& REG_P (SET_DEST (old_set
)))
3684 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3685 plus_src
= SET_SRC (old_set
);
3686 /* First see if the source is of the form (plus (...) CST). */
3688 && CONST_INT_P (XEXP (plus_src
, 1)))
3689 plus_cst_src
= plus_src
;
3690 else if (REG_P (SET_SRC (old_set
))
3693 /* Otherwise, see if we have a REG_EQUAL note of the form
3694 (plus (...) CST). */
3696 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3698 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3699 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3700 && GET_CODE (XEXP (links
, 0)) == PLUS
3701 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3703 plus_cst_src
= XEXP (links
, 0);
3710 /* Determine the effects of this insn on elimination offsets. */
3711 elimination_effects (old_body
, VOIDmode
);
3713 /* Eliminate all eliminable registers occurring in operands that
3714 can be handled by reload. */
3715 extract_insn (insn
);
3716 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3717 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3719 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3721 orig_operand
[i
] = recog_data
.operand
[i
];
3723 /* For an asm statement, every operand is eliminable. */
3724 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3726 bool is_set_src
, in_plus
;
3728 /* Check for setting a register that we know about. */
3729 if (recog_data
.operand_type
[i
] != OP_IN
3730 && REG_P (orig_operand
[i
]))
3732 /* If we are assigning to a register that can be eliminated, it
3733 must be as part of a PARALLEL, since the code above handles
3734 single SETs. We must indicate that we can no longer
3735 eliminate this reg. */
3736 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3738 if (ep
->from_rtx
== orig_operand
[i
])
3739 ep
->can_eliminate
= 0;
3742 /* Companion to the above plus substitution, we can allow
3743 invariants as the source of a plain move. */
3745 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3747 if (is_set_src
&& !sets_reg_p
)
3748 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3750 if (plus_src
&& sets_reg_p
3751 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3752 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3755 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3757 is_set_src
|| in_plus
, true);
3758 /* Terminate the search in check_eliminable_occurrences at
3760 *recog_data
.operand_loc
[i
] = 0;
3764 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3765 *recog_data
.dup_loc
[i
]
3766 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3768 /* If any eliminable remain, they aren't eliminable anymore. */
3769 check_eliminable_occurrences (old_body
);
3771 /* Restore the old body. */
3772 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3773 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3774 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3775 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3777 /* Update all elimination pairs to reflect the status after the current
3778 insn. The changes we make were determined by the earlier call to
3779 elimination_effects. */
3781 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3783 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3784 ep
->can_eliminate
= 0;
3786 ep
->ref_outside_mem
= 0;
3792 /* Loop through all elimination pairs.
3793 Recalculate the number not at initial offset.
3795 Compute the maximum offset (minimum offset if the stack does not
3796 grow downward) for each elimination pair. */
3799 update_eliminable_offsets (void)
3801 struct elim_table
*ep
;
3803 num_not_at_initial_offset
= 0;
3804 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3806 ep
->previous_offset
= ep
->offset
;
3807 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3808 num_not_at_initial_offset
++;
3812 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3813 replacement we currently believe is valid, mark it as not eliminable if X
3814 modifies DEST in any way other than by adding a constant integer to it.
3816 If DEST is the frame pointer, we do nothing because we assume that
3817 all assignments to the hard frame pointer are nonlocal gotos and are being
3818 done at a time when they are valid and do not disturb anything else.
3819 Some machines want to eliminate a fake argument pointer with either the
3820 frame or stack pointer. Assignments to the hard frame pointer must not
3821 prevent this elimination.
3823 Called via note_stores from reload before starting its passes to scan
3824 the insns of the function. */
3827 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3831 /* A SUBREG of a hard register here is just changing its mode. We should
3832 not see a SUBREG of an eliminable hard register, but check just in
3834 if (GET_CODE (dest
) == SUBREG
)
3835 dest
= SUBREG_REG (dest
);
3837 if (dest
== hard_frame_pointer_rtx
)
3840 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3841 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3842 && (GET_CODE (x
) != SET
3843 || GET_CODE (SET_SRC (x
)) != PLUS
3844 || XEXP (SET_SRC (x
), 0) != dest
3845 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3847 reg_eliminate
[i
].can_eliminate_previous
3848 = reg_eliminate
[i
].can_eliminate
= 0;
3853 /* Verify that the initial elimination offsets did not change since the
3854 last call to set_initial_elim_offsets. This is used to catch cases
3855 where something illegal happened during reload_as_needed that could
3856 cause incorrect code to be generated if we did not check for it. */
3859 verify_initial_elim_offsets (void)
3863 if (!num_eliminable
)
3866 #ifdef ELIMINABLE_REGS
3868 struct elim_table
*ep
;
3870 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3872 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3873 if (t
!= ep
->initial_offset
)
3878 INITIAL_FRAME_POINTER_OFFSET (t
);
3879 if (t
!= reg_eliminate
[0].initial_offset
)
3886 /* Reset all offsets on eliminable registers to their initial values. */
3889 set_initial_elim_offsets (void)
3891 struct elim_table
*ep
= reg_eliminate
;
3893 #ifdef ELIMINABLE_REGS
3894 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3896 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3897 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3900 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3901 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3904 num_not_at_initial_offset
= 0;
3907 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3910 set_initial_eh_label_offset (rtx label
)
3912 set_label_offsets (label
, NULL_RTX
, 1);
3915 /* Initialize the known label offsets.
3916 Set a known offset for each forced label to be at the initial offset
3917 of each elimination. We do this because we assume that all
3918 computed jumps occur from a location where each elimination is
3919 at its initial offset.
3920 For all other labels, show that we don't know the offsets. */
3923 set_initial_label_offsets (void)
3926 memset (offsets_known_at
, 0, num_labels
);
3928 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3930 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3932 for (x
= nonlocal_goto_handler_labels
; x
; x
= XEXP (x
, 1))
3934 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3936 for_each_eh_label (set_initial_eh_label_offset
);
3939 /* Set all elimination offsets to the known values for the code label given
3943 set_offsets_for_label (rtx insn
)
3946 int label_nr
= CODE_LABEL_NUMBER (insn
);
3947 struct elim_table
*ep
;
3949 num_not_at_initial_offset
= 0;
3950 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3952 ep
->offset
= ep
->previous_offset
3953 = offsets_at
[label_nr
- first_label_num
][i
];
3954 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3955 num_not_at_initial_offset
++;
3959 /* See if anything that happened changes which eliminations are valid.
3960 For example, on the SPARC, whether or not the frame pointer can
3961 be eliminated can depend on what registers have been used. We need
3962 not check some conditions again (such as flag_omit_frame_pointer)
3963 since they can't have changed. */
3966 update_eliminables (HARD_REG_SET
*pset
)
3968 int previous_frame_pointer_needed
= frame_pointer_needed
;
3969 struct elim_table
*ep
;
3971 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3972 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3973 && targetm
.frame_pointer_required ())
3974 #ifdef ELIMINABLE_REGS
3975 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3978 ep
->can_eliminate
= 0;
3980 /* Look for the case where we have discovered that we can't replace
3981 register A with register B and that means that we will now be
3982 trying to replace register A with register C. This means we can
3983 no longer replace register C with register B and we need to disable
3984 such an elimination, if it exists. This occurs often with A == ap,
3985 B == sp, and C == fp. */
3987 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3989 struct elim_table
*op
;
3992 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3994 /* Find the current elimination for ep->from, if there is a
3996 for (op
= reg_eliminate
;
3997 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3998 if (op
->from
== ep
->from
&& op
->can_eliminate
)
4004 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
4006 for (op
= reg_eliminate
;
4007 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
4008 if (op
->from
== new_to
&& op
->to
== ep
->to
)
4009 op
->can_eliminate
= 0;
4013 /* See if any registers that we thought we could eliminate the previous
4014 time are no longer eliminable. If so, something has changed and we
4015 must spill the register. Also, recompute the number of eliminable
4016 registers and see if the frame pointer is needed; it is if there is
4017 no elimination of the frame pointer that we can perform. */
4019 frame_pointer_needed
= 1;
4020 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4022 if (ep
->can_eliminate
4023 && ep
->from
== FRAME_POINTER_REGNUM
4024 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4025 && (! SUPPORTS_STACK_ALIGNMENT
4026 || ! crtl
->stack_realign_needed
))
4027 frame_pointer_needed
= 0;
4029 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4031 ep
->can_eliminate_previous
= 0;
4032 SET_HARD_REG_BIT (*pset
, ep
->from
);
4037 /* If we didn't need a frame pointer last time, but we do now, spill
4038 the hard frame pointer. */
4039 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4040 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4043 /* Return true if X is used as the target register of an elimination. */
4046 elimination_target_reg_p (rtx x
)
4048 struct elim_table
*ep
;
4050 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4051 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4057 /* Initialize the table of registers to eliminate.
4058 Pre-condition: global flag frame_pointer_needed has been set before
4059 calling this function. */
4062 init_elim_table (void)
4064 struct elim_table
*ep
;
4065 #ifdef ELIMINABLE_REGS
4066 const struct elim_table_1
*ep1
;
4070 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4074 #ifdef ELIMINABLE_REGS
4075 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4076 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4078 ep
->from
= ep1
->from
;
4080 ep
->can_eliminate
= ep
->can_eliminate_previous
4081 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4082 && ! (ep
->to
== STACK_POINTER_REGNUM
4083 && frame_pointer_needed
4084 && (! SUPPORTS_STACK_ALIGNMENT
4085 || ! stack_realign_fp
)));
4088 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4089 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4090 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4091 = ! frame_pointer_needed
;
4094 /* Count the number of eliminable registers and build the FROM and TO
4095 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4096 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4097 We depend on this. */
4098 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4100 num_eliminable
+= ep
->can_eliminate
;
4101 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4102 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4106 /* Find all the pseudo registers that didn't get hard regs
4107 but do have known equivalent constants or memory slots.
4108 These include parameters (known equivalent to parameter slots)
4109 and cse'd or loop-moved constant memory addresses.
4111 Record constant equivalents in reg_equiv_constant
4112 so they will be substituted by find_reloads.
4113 Record memory equivalents in reg_mem_equiv so they can
4114 be substituted eventually by altering the REG-rtx's. */
4117 init_eliminable_invariants (rtx first
, bool do_subregs
)
4124 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4126 reg_max_ref_width
= NULL
;
4128 num_eliminable_invariants
= 0;
4130 first_label_num
= get_first_label_num ();
4131 num_labels
= max_label_num () - first_label_num
;
4133 /* Allocate the tables used to store offset information at labels. */
4134 offsets_known_at
= XNEWVEC (char, num_labels
);
4135 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4137 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4138 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4139 find largest such for each pseudo. FIRST is the head of the insn
4142 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4144 rtx set
= single_set (insn
);
4146 /* We may introduce USEs that we want to remove at the end, so
4147 we'll mark them with QImode. Make sure there are no
4148 previously-marked insns left by say regmove. */
4149 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4150 && GET_MODE (insn
) != VOIDmode
)
4151 PUT_MODE (insn
, VOIDmode
);
4153 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4154 scan_paradoxical_subregs (PATTERN (insn
));
4156 if (set
!= 0 && REG_P (SET_DEST (set
)))
4158 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4164 i
= REGNO (SET_DEST (set
));
4167 if (i
<= LAST_VIRTUAL_REGISTER
)
4170 /* If flag_pic and we have constant, verify it's legitimate. */
4172 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4174 /* It can happen that a REG_EQUIV note contains a MEM
4175 that is not a legitimate memory operand. As later
4176 stages of reload assume that all addresses found
4177 in the reg_equiv_* arrays were originally legitimate,
4178 we ignore such REG_EQUIV notes. */
4179 if (memory_operand (x
, VOIDmode
))
4181 /* Always unshare the equivalence, so we can
4182 substitute into this insn without touching the
4184 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4186 else if (function_invariant_p (x
))
4188 enum machine_mode mode
;
4190 mode
= GET_MODE (SET_DEST (set
));
4191 if (GET_CODE (x
) == PLUS
)
4193 /* This is PLUS of frame pointer and a constant,
4194 and might be shared. Unshare it. */
4195 reg_equiv_invariant (i
) = copy_rtx (x
);
4196 num_eliminable_invariants
++;
4198 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4200 reg_equiv_invariant (i
) = x
;
4201 num_eliminable_invariants
++;
4203 else if (targetm
.legitimate_constant_p (mode
, x
))
4204 reg_equiv_constant (i
) = x
;
4207 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4208 if (! reg_equiv_memory_loc (i
))
4209 reg_equiv_init (i
) = NULL_RTX
;
4214 reg_equiv_init (i
) = NULL_RTX
;
4219 reg_equiv_init (i
) = NULL_RTX
;
4224 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4225 if (reg_equiv_init (i
))
4227 fprintf (dump_file
, "init_insns for %u: ", i
);
4228 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4229 fprintf (dump_file
, "\n");
4233 /* Indicate that we no longer have known memory locations or constants.
4234 Free all data involved in tracking these. */
4237 free_reg_equiv (void)
4242 free (offsets_known_at
);
4245 offsets_known_at
= 0;
4247 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4248 if (reg_equiv_alt_mem_list (i
))
4249 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4250 VEC_free (reg_equivs_t
, gc
, reg_equivs
);
4255 /* Kick all pseudos out of hard register REGNO.
4257 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4258 because we found we can't eliminate some register. In the case, no pseudos
4259 are allowed to be in the register, even if they are only in a block that
4260 doesn't require spill registers, unlike the case when we are spilling this
4261 hard reg to produce another spill register.
4263 Return nonzero if any pseudos needed to be kicked out. */
4266 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4272 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4273 df_set_regs_ever_live (regno
, true);
4276 /* Spill every pseudo reg that was allocated to this reg
4277 or to something that overlaps this reg. */
4279 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4280 if (reg_renumber
[i
] >= 0
4281 && (unsigned int) reg_renumber
[i
] <= regno
4282 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4283 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4286 /* After find_reload_regs has been run for all insn that need reloads,
4287 and/or spill_hard_regs was called, this function is used to actually
4288 spill pseudo registers and try to reallocate them. It also sets up the
4289 spill_regs array for use by choose_reload_regs. */
4292 finish_spills (int global
)
4294 struct insn_chain
*chain
;
4295 int something_changed
= 0;
4297 reg_set_iterator rsi
;
4299 /* Build the spill_regs array for the function. */
4300 /* If there are some registers still to eliminate and one of the spill regs
4301 wasn't ever used before, additional stack space may have to be
4302 allocated to store this register. Thus, we may have changed the offset
4303 between the stack and frame pointers, so mark that something has changed.
4305 One might think that we need only set VAL to 1 if this is a call-used
4306 register. However, the set of registers that must be saved by the
4307 prologue is not identical to the call-used set. For example, the
4308 register used by the call insn for the return PC is a call-used register,
4309 but must be saved by the prologue. */
4312 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4313 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4315 spill_reg_order
[i
] = n_spills
;
4316 spill_regs
[n_spills
++] = i
;
4317 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4318 something_changed
= 1;
4319 df_set_regs_ever_live (i
, true);
4322 spill_reg_order
[i
] = -1;
4324 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4325 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4327 /* Record the current hard register the pseudo is allocated to
4328 in pseudo_previous_regs so we avoid reallocating it to the
4329 same hard reg in a later pass. */
4330 gcc_assert (reg_renumber
[i
] >= 0);
4332 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4333 /* Mark it as no longer having a hard register home. */
4334 reg_renumber
[i
] = -1;
4335 if (ira_conflicts_p
)
4336 /* Inform IRA about the change. */
4337 ira_mark_allocation_change (i
);
4338 /* We will need to scan everything again. */
4339 something_changed
= 1;
4342 /* Retry global register allocation if possible. */
4343 if (global
&& ira_conflicts_p
)
4347 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4348 /* For every insn that needs reloads, set the registers used as spill
4349 regs in pseudo_forbidden_regs for every pseudo live across the
4351 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4353 EXECUTE_IF_SET_IN_REG_SET
4354 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4356 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4357 chain
->used_spill_regs
);
4359 EXECUTE_IF_SET_IN_REG_SET
4360 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4362 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4363 chain
->used_spill_regs
);
4367 /* Retry allocating the pseudos spilled in IRA and the
4368 reload. For each reg, merge the various reg sets that
4369 indicate which hard regs can't be used, and call
4370 ira_reassign_pseudos. */
4371 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4372 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4374 if (reg_renumber
[i
] < 0)
4375 temp_pseudo_reg_arr
[n
++] = i
;
4377 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4379 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4380 bad_spill_regs_global
,
4381 pseudo_forbidden_regs
, pseudo_previous_regs
,
4383 something_changed
= 1;
4385 /* Fix up the register information in the insn chain.
4386 This involves deleting those of the spilled pseudos which did not get
4387 a new hard register home from the live_{before,after} sets. */
4388 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4390 HARD_REG_SET used_by_pseudos
;
4391 HARD_REG_SET used_by_pseudos2
;
4393 if (! ira_conflicts_p
)
4395 /* Don't do it for IRA because IRA and the reload still can
4396 assign hard registers to the spilled pseudos on next
4397 reload iterations. */
4398 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4399 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4401 /* Mark any unallocated hard regs as available for spills. That
4402 makes inheritance work somewhat better. */
4403 if (chain
->need_reload
)
4405 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4406 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4407 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4409 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4410 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4411 /* Value of chain->used_spill_regs from previous iteration
4412 may be not included in the value calculated here because
4413 of possible removing caller-saves insns (see function
4414 delete_caller_save_insns. */
4415 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4416 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4420 CLEAR_REG_SET (&changed_allocation_pseudos
);
4421 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4422 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4424 int regno
= reg_renumber
[i
];
4425 if (reg_old_renumber
[i
] == regno
)
4428 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4430 alter_reg (i
, reg_old_renumber
[i
], false);
4431 reg_old_renumber
[i
] = regno
;
4435 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4437 fprintf (dump_file
, " Register %d now in %d.\n\n",
4438 i
, reg_renumber
[i
]);
4442 return something_changed
;
4445 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4448 scan_paradoxical_subregs (rtx x
)
4452 enum rtx_code code
= GET_CODE (x
);
4463 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
4471 if (REG_P (SUBREG_REG (x
))
4472 && (GET_MODE_SIZE (GET_MODE (x
))
4473 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4475 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4476 = GET_MODE_SIZE (GET_MODE (x
));
4477 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4485 fmt
= GET_RTX_FORMAT (code
);
4486 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4489 scan_paradoxical_subregs (XEXP (x
, i
));
4490 else if (fmt
[i
] == 'E')
4493 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4494 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4499 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4500 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4501 and apply the corresponding narrowing subreg to *OTHER_PTR.
4502 Return true if the operands were changed, false otherwise. */
4505 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4507 rtx op
, inner
, other
, tem
;
4510 if (!paradoxical_subreg_p (op
))
4512 inner
= SUBREG_REG (op
);
4515 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4519 /* If the lowpart operation turned a hard register into a subreg,
4520 rather than simplifying it to another hard register, then the
4521 mode change cannot be properly represented. For example, OTHER
4522 might be valid in its current mode, but not in the new one. */
4523 if (GET_CODE (tem
) == SUBREG
4525 && HARD_REGISTER_P (other
))
4533 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4534 examine all of the reload insns between PREV and NEXT exclusive, and
4535 annotate all that may trap. */
4538 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4540 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4543 if (!insn_could_throw_p (insn
))
4544 remove_note (insn
, note
);
4545 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4548 /* Reload pseudo-registers into hard regs around each insn as needed.
4549 Additional register load insns are output before the insn that needs it
4550 and perhaps store insns after insns that modify the reloaded pseudo reg.
4552 reg_last_reload_reg and reg_reloaded_contents keep track of
4553 which registers are already available in reload registers.
4554 We update these for the reloads that we perform,
4555 as the insns are scanned. */
4558 reload_as_needed (int live_known
)
4560 struct insn_chain
*chain
;
4561 #if defined (AUTO_INC_DEC)
4566 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4567 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4568 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4569 INIT_REG_SET (®_has_output_reload
);
4570 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4571 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4573 set_initial_elim_offsets ();
4575 /* Generate a marker insn that we will move around. */
4576 marker
= emit_note (NOTE_INSN_DELETED
);
4577 unlink_insn_chain (marker
, marker
);
4579 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4582 rtx insn
= chain
->insn
;
4583 rtx old_next
= NEXT_INSN (insn
);
4585 rtx old_prev
= PREV_INSN (insn
);
4588 /* If we pass a label, copy the offsets from the label information
4589 into the current offsets of each elimination. */
4591 set_offsets_for_label (insn
);
4593 else if (INSN_P (insn
))
4595 regset_head regs_to_forget
;
4596 INIT_REG_SET (®s_to_forget
);
4597 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4599 /* If this is a USE and CLOBBER of a MEM, ensure that any
4600 references to eliminable registers have been removed. */
4602 if ((GET_CODE (PATTERN (insn
)) == USE
4603 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4604 && MEM_P (XEXP (PATTERN (insn
), 0)))
4605 XEXP (XEXP (PATTERN (insn
), 0), 0)
4606 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4607 GET_MODE (XEXP (PATTERN (insn
), 0)),
4610 /* If we need to do register elimination processing, do so.
4611 This might delete the insn, in which case we are done. */
4612 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4614 eliminate_regs_in_insn (insn
, 1);
4617 update_eliminable_offsets ();
4618 CLEAR_REG_SET (®s_to_forget
);
4623 /* If need_elim is nonzero but need_reload is zero, one might think
4624 that we could simply set n_reloads to 0. However, find_reloads
4625 could have done some manipulation of the insn (such as swapping
4626 commutative operands), and these manipulations are lost during
4627 the first pass for every insn that needs register elimination.
4628 So the actions of find_reloads must be redone here. */
4630 if (! chain
->need_elim
&& ! chain
->need_reload
4631 && ! chain
->need_operand_change
)
4633 /* First find the pseudo regs that must be reloaded for this insn.
4634 This info is returned in the tables reload_... (see reload.h).
4635 Also modify the body of INSN by substituting RELOAD
4636 rtx's for those pseudo regs. */
4639 CLEAR_REG_SET (®_has_output_reload
);
4640 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4642 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4648 rtx next
= NEXT_INSN (insn
);
4651 /* ??? PREV can get deleted by reload inheritance.
4652 Work around this by emitting a marker note. */
4653 prev
= PREV_INSN (insn
);
4654 reorder_insns_nobb (marker
, marker
, prev
);
4656 /* Now compute which reload regs to reload them into. Perhaps
4657 reusing reload regs from previous insns, or else output
4658 load insns to reload them. Maybe output store insns too.
4659 Record the choices of reload reg in reload_reg_rtx. */
4660 choose_reload_regs (chain
);
4662 /* Generate the insns to reload operands into or out of
4663 their reload regs. */
4664 emit_reload_insns (chain
);
4666 /* Substitute the chosen reload regs from reload_reg_rtx
4667 into the insn's body (or perhaps into the bodies of other
4668 load and store insn that we just made for reloading
4669 and that we moved the structure into). */
4670 subst_reloads (insn
);
4672 prev
= PREV_INSN (marker
);
4673 unlink_insn_chain (marker
, marker
);
4675 /* Adjust the exception region notes for loads and stores. */
4676 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4677 fixup_eh_region_note (insn
, prev
, next
);
4679 /* Adjust the location of REG_ARGS_SIZE. */
4680 p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4683 remove_note (insn
, p
);
4684 fixup_args_size_notes (prev
, PREV_INSN (next
),
4685 INTVAL (XEXP (p
, 0)));
4688 /* If this was an ASM, make sure that all the reload insns
4689 we have generated are valid. If not, give an error
4691 if (asm_noperands (PATTERN (insn
)) >= 0)
4692 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4693 if (p
!= insn
&& INSN_P (p
)
4694 && GET_CODE (PATTERN (p
)) != USE
4695 && (recog_memoized (p
) < 0
4696 || (extract_insn (p
), ! constrain_operands (1))))
4698 error_for_asm (insn
,
4699 "%<asm%> operand requires "
4700 "impossible reload");
4705 if (num_eliminable
&& chain
->need_elim
)
4706 update_eliminable_offsets ();
4708 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4709 is no longer validly lying around to save a future reload.
4710 Note that this does not detect pseudos that were reloaded
4711 for this insn in order to be stored in
4712 (obeying register constraints). That is correct; such reload
4713 registers ARE still valid. */
4714 forget_marked_reloads (®s_to_forget
);
4715 CLEAR_REG_SET (®s_to_forget
);
4717 /* There may have been CLOBBER insns placed after INSN. So scan
4718 between INSN and NEXT and use them to forget old reloads. */
4719 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4720 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4721 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4724 /* Likewise for regs altered by auto-increment in this insn.
4725 REG_INC notes have been changed by reloading:
4726 find_reloads_address_1 records substitutions for them,
4727 which have been performed by subst_reloads above. */
4728 for (i
= n_reloads
- 1; i
>= 0; i
--)
4730 rtx in_reg
= rld
[i
].in_reg
;
4733 enum rtx_code code
= GET_CODE (in_reg
);
4734 /* PRE_INC / PRE_DEC will have the reload register ending up
4735 with the same value as the stack slot, but that doesn't
4736 hold true for POST_INC / POST_DEC. Either we have to
4737 convert the memory access to a true POST_INC / POST_DEC,
4738 or we can't use the reload register for inheritance. */
4739 if ((code
== POST_INC
|| code
== POST_DEC
)
4740 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4741 REGNO (rld
[i
].reg_rtx
))
4742 /* Make sure it is the inc/dec pseudo, and not
4743 some other (e.g. output operand) pseudo. */
4744 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4745 == REGNO (XEXP (in_reg
, 0))))
4748 rtx reload_reg
= rld
[i
].reg_rtx
;
4749 enum machine_mode mode
= GET_MODE (reload_reg
);
4753 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4755 /* We really want to ignore REG_INC notes here, so
4756 use PATTERN (p) as argument to reg_set_p . */
4757 if (reg_set_p (reload_reg
, PATTERN (p
)))
4759 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4765 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4767 validate_replace_rtx_group (reload_reg
,
4769 n
= verify_changes (0);
4771 /* We must also verify that the constraints
4772 are met after the replacement. Make sure
4773 extract_insn is only called for an insn
4774 where the replacements were found to be
4779 n
= constrain_operands (1);
4782 /* If the constraints were not met, then
4783 undo the replacement, else confirm it. */
4787 confirm_change_group ();
4793 add_reg_note (p
, REG_INC
, reload_reg
);
4794 /* Mark this as having an output reload so that the
4795 REG_INC processing code below won't invalidate
4796 the reload for inheritance. */
4797 SET_HARD_REG_BIT (reg_is_output_reload
,
4798 REGNO (reload_reg
));
4799 SET_REGNO_REG_SET (®_has_output_reload
,
4800 REGNO (XEXP (in_reg
, 0)));
4803 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4806 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4807 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4808 REGNO (rld
[i
].reg_rtx
))
4809 /* Make sure it is the inc/dec pseudo, and not
4810 some other (e.g. output operand) pseudo. */
4811 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4812 == REGNO (XEXP (in_reg
, 0))))
4814 SET_HARD_REG_BIT (reg_is_output_reload
,
4815 REGNO (rld
[i
].reg_rtx
));
4816 SET_REGNO_REG_SET (®_has_output_reload
,
4817 REGNO (XEXP (in_reg
, 0)));
4819 else if (code
== PRE_INC
|| code
== PRE_DEC
4820 || code
== POST_INC
|| code
== POST_DEC
)
4822 int in_regno
= REGNO (XEXP (in_reg
, 0));
4824 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4827 bool forget_p
= true;
4829 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4830 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4833 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4836 if (x
== reg_reloaded_insn
[in_hard_regno
])
4842 /* If for some reasons, we didn't set up
4843 reg_last_reload_reg in this insn,
4844 invalidate inheritance from previous
4845 insns for the incremented/decremented
4846 register. Such registers will be not in
4847 reg_has_output_reload. Invalidate it
4848 also if the corresponding element in
4849 reg_reloaded_insn is also
4852 forget_old_reloads_1 (XEXP (in_reg
, 0),
4858 /* If a pseudo that got a hard register is auto-incremented,
4859 we must purge records of copying it into pseudos without
4861 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4862 if (REG_NOTE_KIND (x
) == REG_INC
)
4864 /* See if this pseudo reg was reloaded in this insn.
4865 If so, its last-reload info is still valid
4866 because it is based on this insn's reload. */
4867 for (i
= 0; i
< n_reloads
; i
++)
4868 if (rld
[i
].out
== XEXP (x
, 0))
4872 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4876 /* A reload reg's contents are unknown after a label. */
4878 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4880 /* Don't assume a reload reg is still good after a call insn
4881 if it is a call-used reg, or if it contains a value that will
4882 be partially clobbered by the call. */
4883 else if (CALL_P (insn
))
4885 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4886 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4888 /* If this is a call to a setjmp-type function, we must not
4889 reuse any reload reg contents across the call; that will
4890 just be clobbered by other uses of the register in later
4891 code, before the longjmp. */
4892 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4893 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4898 free (reg_last_reload_reg
);
4899 CLEAR_REG_SET (®_has_output_reload
);
4902 /* Discard all record of any value reloaded from X,
4903 or reloaded in X from someplace else;
4904 unless X is an output reload reg of the current insn.
4906 X may be a hard reg (the reload reg)
4907 or it may be a pseudo reg that was reloaded from.
4909 When DATA is non-NULL just mark the registers in regset
4910 to be forgotten later. */
4913 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4918 regset regs
= (regset
) data
;
4920 /* note_stores does give us subregs of hard regs,
4921 subreg_regno_offset requires a hard reg. */
4922 while (GET_CODE (x
) == SUBREG
)
4924 /* We ignore the subreg offset when calculating the regno,
4925 because we are using the entire underlying hard register
4935 if (regno
>= FIRST_PSEUDO_REGISTER
)
4941 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4942 /* Storing into a spilled-reg invalidates its contents.
4943 This can happen if a block-local pseudo is allocated to that reg
4944 and it wasn't spilled because this block's total need is 0.
4945 Then some insn might have an optional reload and use this reg. */
4947 for (i
= 0; i
< nr
; i
++)
4948 /* But don't do this if the reg actually serves as an output
4949 reload reg in the current instruction. */
4951 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4953 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4954 spill_reg_store
[regno
+ i
] = 0;
4960 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4963 /* Since value of X has changed,
4964 forget any value previously copied from it. */
4967 /* But don't forget a copy if this is the output reload
4968 that establishes the copy's validity. */
4970 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4971 reg_last_reload_reg
[regno
+ nr
] = 0;
4975 /* Forget the reloads marked in regset by previous function. */
4977 forget_marked_reloads (regset regs
)
4980 reg_set_iterator rsi
;
4981 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4983 if (reg
< FIRST_PSEUDO_REGISTER
4984 /* But don't do this if the reg actually serves as an output
4985 reload reg in the current instruction. */
4987 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4989 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4990 spill_reg_store
[reg
] = 0;
4993 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4994 reg_last_reload_reg
[reg
] = 0;
4998 /* The following HARD_REG_SETs indicate when each hard register is
4999 used for a reload of various parts of the current insn. */
5001 /* If reg is unavailable for all reloads. */
5002 static HARD_REG_SET reload_reg_unavailable
;
5003 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5004 static HARD_REG_SET reload_reg_used
;
5005 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5006 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5007 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5008 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5009 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5010 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5011 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5012 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5013 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5014 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5015 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5016 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5017 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5018 static HARD_REG_SET reload_reg_used_in_op_addr
;
5019 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5020 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5021 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5022 static HARD_REG_SET reload_reg_used_in_insn
;
5023 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5024 static HARD_REG_SET reload_reg_used_in_other_addr
;
5026 /* If reg is in use as a reload reg for any sort of reload. */
5027 static HARD_REG_SET reload_reg_used_at_all
;
5029 /* If reg is use as an inherited reload. We just mark the first register
5031 static HARD_REG_SET reload_reg_used_for_inherit
;
5033 /* Records which hard regs are used in any way, either as explicit use or
5034 by being allocated to a pseudo during any point of the current insn. */
5035 static HARD_REG_SET reg_used_in_insn
;
5037 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5038 TYPE. MODE is used to indicate how many consecutive regs are
5042 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5043 enum machine_mode mode
)
5048 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5051 case RELOAD_FOR_INPUT_ADDRESS
:
5052 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5055 case RELOAD_FOR_INPADDR_ADDRESS
:
5056 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5059 case RELOAD_FOR_OUTPUT_ADDRESS
:
5060 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5063 case RELOAD_FOR_OUTADDR_ADDRESS
:
5064 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5067 case RELOAD_FOR_OPERAND_ADDRESS
:
5068 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5071 case RELOAD_FOR_OPADDR_ADDR
:
5072 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5075 case RELOAD_FOR_OTHER_ADDRESS
:
5076 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5079 case RELOAD_FOR_INPUT
:
5080 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5083 case RELOAD_FOR_OUTPUT
:
5084 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5087 case RELOAD_FOR_INSN
:
5088 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5092 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5095 /* Similarly, but show REGNO is no longer in use for a reload. */
5098 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5099 enum reload_type type
, enum machine_mode mode
)
5101 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5102 unsigned int start_regno
, end_regno
, r
;
5104 /* A complication is that for some reload types, inheritance might
5105 allow multiple reloads of the same types to share a reload register.
5106 We set check_opnum if we have to check only reloads with the same
5107 operand number, and check_any if we have to check all reloads. */
5108 int check_opnum
= 0;
5110 HARD_REG_SET
*used_in_set
;
5115 used_in_set
= &reload_reg_used
;
5118 case RELOAD_FOR_INPUT_ADDRESS
:
5119 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5122 case RELOAD_FOR_INPADDR_ADDRESS
:
5124 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5127 case RELOAD_FOR_OUTPUT_ADDRESS
:
5128 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5131 case RELOAD_FOR_OUTADDR_ADDRESS
:
5133 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5136 case RELOAD_FOR_OPERAND_ADDRESS
:
5137 used_in_set
= &reload_reg_used_in_op_addr
;
5140 case RELOAD_FOR_OPADDR_ADDR
:
5142 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5145 case RELOAD_FOR_OTHER_ADDRESS
:
5146 used_in_set
= &reload_reg_used_in_other_addr
;
5150 case RELOAD_FOR_INPUT
:
5151 used_in_set
= &reload_reg_used_in_input
[opnum
];
5154 case RELOAD_FOR_OUTPUT
:
5155 used_in_set
= &reload_reg_used_in_output
[opnum
];
5158 case RELOAD_FOR_INSN
:
5159 used_in_set
= &reload_reg_used_in_insn
;
5164 /* We resolve conflicts with remaining reloads of the same type by
5165 excluding the intervals of reload registers by them from the
5166 interval of freed reload registers. Since we only keep track of
5167 one set of interval bounds, we might have to exclude somewhat
5168 more than what would be necessary if we used a HARD_REG_SET here.
5169 But this should only happen very infrequently, so there should
5170 be no reason to worry about it. */
5172 start_regno
= regno
;
5173 end_regno
= regno
+ nregs
;
5174 if (check_opnum
|| check_any
)
5176 for (i
= n_reloads
- 1; i
>= 0; i
--)
5178 if (rld
[i
].when_needed
== type
5179 && (check_any
|| rld
[i
].opnum
== opnum
)
5182 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5183 unsigned int conflict_end
5184 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5186 /* If there is an overlap with the first to-be-freed register,
5187 adjust the interval start. */
5188 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5189 start_regno
= conflict_end
;
5190 /* Otherwise, if there is a conflict with one of the other
5191 to-be-freed registers, adjust the interval end. */
5192 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5193 end_regno
= conflict_start
;
5198 for (r
= start_regno
; r
< end_regno
; r
++)
5199 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5202 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5203 specified by OPNUM and TYPE. */
5206 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5210 /* In use for a RELOAD_OTHER means it's not available for anything. */
5211 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5212 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5218 /* In use for anything means we can't use it for RELOAD_OTHER. */
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5220 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5221 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5222 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5225 for (i
= 0; i
< reload_n_operands
; i
++)
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5227 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5228 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5229 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5230 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5231 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5236 case RELOAD_FOR_INPUT
:
5237 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5238 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5241 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5244 /* If it is used for some other input, can't use it. */
5245 for (i
= 0; i
< reload_n_operands
; i
++)
5246 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5249 /* If it is used in a later operand's address, can't use it. */
5250 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5251 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5252 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5257 case RELOAD_FOR_INPUT_ADDRESS
:
5258 /* Can't use a register if it is used for an input address for this
5259 operand or used as an input in an earlier one. */
5260 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5261 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5264 for (i
= 0; i
< opnum
; i
++)
5265 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5270 case RELOAD_FOR_INPADDR_ADDRESS
:
5271 /* Can't use a register if it is used for an input address
5272 for this operand or used as an input in an earlier
5274 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5277 for (i
= 0; i
< opnum
; i
++)
5278 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5283 case RELOAD_FOR_OUTPUT_ADDRESS
:
5284 /* Can't use a register if it is used for an output address for this
5285 operand or used as an output in this or a later operand. Note
5286 that multiple output operands are emitted in reverse order, so
5287 the conflicting ones are those with lower indices. */
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5291 for (i
= 0; i
<= opnum
; i
++)
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5297 case RELOAD_FOR_OUTADDR_ADDRESS
:
5298 /* Can't use a register if it is used for an output address
5299 for this operand or used as an output in this or a
5300 later operand. Note that multiple output operands are
5301 emitted in reverse order, so the conflicting ones are
5302 those with lower indices. */
5303 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5306 for (i
= 0; i
<= opnum
; i
++)
5307 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5312 case RELOAD_FOR_OPERAND_ADDRESS
:
5313 for (i
= 0; i
< reload_n_operands
; i
++)
5314 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5317 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5318 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5320 case RELOAD_FOR_OPADDR_ADDR
:
5321 for (i
= 0; i
< reload_n_operands
; i
++)
5322 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5325 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5327 case RELOAD_FOR_OUTPUT
:
5328 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5329 outputs, or an operand address for this or an earlier output.
5330 Note that multiple output operands are emitted in reverse order,
5331 so the conflicting ones are those with higher indices. */
5332 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5335 for (i
= 0; i
< reload_n_operands
; i
++)
5336 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5339 for (i
= opnum
; i
< reload_n_operands
; i
++)
5340 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5341 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5346 case RELOAD_FOR_INSN
:
5347 for (i
= 0; i
< reload_n_operands
; i
++)
5348 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5349 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5352 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5353 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5355 case RELOAD_FOR_OTHER_ADDRESS
:
5356 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5363 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5364 the number RELOADNUM, is still available in REGNO at the end of the insn.
5366 We can assume that the reload reg was already tested for availability
5367 at the time it is needed, and we should not check this again,
5368 in case the reg has already been marked in use. */
5371 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5373 int opnum
= rld
[reloadnum
].opnum
;
5374 enum reload_type type
= rld
[reloadnum
].when_needed
;
5377 /* See if there is a reload with the same type for this operand, using
5378 the same register. This case is not handled by the code below. */
5379 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5384 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5386 reg
= rld
[i
].reg_rtx
;
5387 if (reg
== NULL_RTX
)
5389 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5390 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5397 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5398 its value must reach the end. */
5401 /* If this use is for part of the insn,
5402 its value reaches if no subsequent part uses the same register.
5403 Just like the above function, don't try to do this with lots
5406 case RELOAD_FOR_OTHER_ADDRESS
:
5407 /* Here we check for everything else, since these don't conflict
5408 with anything else and everything comes later. */
5410 for (i
= 0; i
< reload_n_operands
; i
++)
5411 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5412 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5413 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5414 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5419 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5420 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5421 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5422 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5424 case RELOAD_FOR_INPUT_ADDRESS
:
5425 case RELOAD_FOR_INPADDR_ADDRESS
:
5426 /* Similar, except that we check only for this and subsequent inputs
5427 and the address of only subsequent inputs and we do not need
5428 to check for RELOAD_OTHER objects since they are known not to
5431 for (i
= opnum
; i
< reload_n_operands
; i
++)
5432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5435 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5436 could be killed if the register is also used by reload with type
5437 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5438 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5439 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5442 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5443 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5444 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5447 for (i
= 0; i
< reload_n_operands
; i
++)
5448 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5449 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5453 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5456 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5457 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5458 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5460 case RELOAD_FOR_INPUT
:
5461 /* Similar to input address, except we start at the next operand for
5462 both input and input address and we do not check for
5463 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5466 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5467 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5468 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5469 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5472 /* ... fall through ... */
5474 case RELOAD_FOR_OPERAND_ADDRESS
:
5475 /* Check outputs and their addresses. */
5477 for (i
= 0; i
< reload_n_operands
; i
++)
5478 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5479 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5480 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5483 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5485 case RELOAD_FOR_OPADDR_ADDR
:
5486 for (i
= 0; i
< reload_n_operands
; i
++)
5487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5488 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5489 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5492 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5493 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5494 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5496 case RELOAD_FOR_INSN
:
5497 /* These conflict with other outputs with RELOAD_OTHER. So
5498 we need only check for output addresses. */
5500 opnum
= reload_n_operands
;
5502 /* ... fall through ... */
5504 case RELOAD_FOR_OUTPUT
:
5505 case RELOAD_FOR_OUTPUT_ADDRESS
:
5506 case RELOAD_FOR_OUTADDR_ADDRESS
:
5507 /* We already know these can't conflict with a later output. So the
5508 only thing to check are later output addresses.
5509 Note that multiple output operands are emitted in reverse order,
5510 so the conflicting ones are those with lower indices. */
5511 for (i
= 0; i
< opnum
; i
++)
5512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5513 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5516 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5517 could be killed if the register is also used by reload with type
5518 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5519 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5520 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5530 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5531 every register in REG. */
5534 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5538 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5539 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5545 /* Returns whether R1 and R2 are uniquely chained: the value of one
5546 is used by the other, and that value is not used by any other
5547 reload for this insn. This is used to partially undo the decision
5548 made in find_reloads when in the case of multiple
5549 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5550 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5551 reloads. This code tries to avoid the conflict created by that
5552 change. It might be cleaner to explicitly keep track of which
5553 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5554 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5555 this after the fact. */
5557 reloads_unique_chain_p (int r1
, int r2
)
5561 /* We only check input reloads. */
5562 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5565 /* Avoid anything with output reloads. */
5566 if (rld
[r1
].out
|| rld
[r2
].out
)
5569 /* "chained" means one reload is a component of the other reload,
5570 not the same as the other reload. */
5571 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5572 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5573 || rld
[r1
].optional
|| rld
[r2
].optional
5574 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5575 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5578 for (i
= 0; i
< n_reloads
; i
++)
5579 /* Look for input reloads that aren't our two */
5580 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5582 /* If our reload is mentioned at all, it isn't a simple chain. */
5583 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5589 /* The recursive function change all occurrences of WHAT in *WHERE
5592 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5601 if (*where
== what
|| rtx_equal_p (*where
, what
))
5603 /* Record the location of the changed rtx. */
5604 VEC_safe_push (rtx_p
, heap
, substitute_stack
, where
);
5609 code
= GET_CODE (*where
);
5610 fmt
= GET_RTX_FORMAT (code
);
5611 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5617 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5618 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5620 else if (fmt
[i
] == 'e')
5621 substitute (&XEXP (*where
, i
), what
, repl
);
5625 /* The function returns TRUE if chain of reload R1 and R2 (in any
5626 order) can be evaluated without usage of intermediate register for
5627 the reload containing another reload. It is important to see
5628 gen_reload to understand what the function is trying to do. As an
5629 example, let us have reload chain
5632 r1: <something> + const
5634 and reload R2 got reload reg HR. The function returns true if
5635 there is a correct insn HR = HR + <something>. Otherwise,
5636 gen_reload will use intermediate register (and this is the reload
5637 reg for R1) to reload <something>.
5639 We need this function to find a conflict for chain reloads. In our
5640 example, if HR = HR + <something> is incorrect insn, then we cannot
5641 use HR as a reload register for R2. If we do use it then we get a
5650 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5652 /* Assume other cases in gen_reload are not possible for
5653 chain reloads or do need an intermediate hard registers. */
5657 rtx last
= get_last_insn ();
5659 /* Make r2 a component of r1. */
5660 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5666 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5667 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5668 gcc_assert (regno
>= 0);
5669 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5671 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5673 /* If IN is a paradoxical SUBREG, remove it and try to put the
5674 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5675 strip_paradoxical_subreg (&in
, &out
);
5677 if (GET_CODE (in
) == PLUS
5678 && (REG_P (XEXP (in
, 0))
5679 || GET_CODE (XEXP (in
, 0)) == SUBREG
5680 || MEM_P (XEXP (in
, 0)))
5681 && (REG_P (XEXP (in
, 1))
5682 || GET_CODE (XEXP (in
, 1)) == SUBREG
5683 || CONSTANT_P (XEXP (in
, 1))
5684 || MEM_P (XEXP (in
, 1))))
5686 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5687 code
= recog_memoized (insn
);
5692 extract_insn (insn
);
5693 /* We want constrain operands to treat this insn strictly in
5694 its validity determination, i.e., the way it would after
5695 reload has completed. */
5696 result
= constrain_operands (1);
5699 delete_insns_since (last
);
5702 /* Restore the original value at each changed address within R1. */
5703 while (!VEC_empty (rtx_p
, substitute_stack
))
5705 rtx
*where
= VEC_pop (rtx_p
, substitute_stack
);
5706 *where
= rld
[r2
].in
;
5712 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5715 This function uses the same algorithm as reload_reg_free_p above. */
5718 reloads_conflict (int r1
, int r2
)
5720 enum reload_type r1_type
= rld
[r1
].when_needed
;
5721 enum reload_type r2_type
= rld
[r2
].when_needed
;
5722 int r1_opnum
= rld
[r1
].opnum
;
5723 int r2_opnum
= rld
[r2
].opnum
;
5725 /* RELOAD_OTHER conflicts with everything. */
5726 if (r2_type
== RELOAD_OTHER
)
5729 /* Otherwise, check conflicts differently for each type. */
5733 case RELOAD_FOR_INPUT
:
5734 return (r2_type
== RELOAD_FOR_INSN
5735 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5736 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5737 || r2_type
== RELOAD_FOR_INPUT
5738 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5739 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5740 && r2_opnum
> r1_opnum
));
5742 case RELOAD_FOR_INPUT_ADDRESS
:
5743 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5744 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5746 case RELOAD_FOR_INPADDR_ADDRESS
:
5747 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5748 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5750 case RELOAD_FOR_OUTPUT_ADDRESS
:
5751 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5752 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5754 case RELOAD_FOR_OUTADDR_ADDRESS
:
5755 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5756 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5758 case RELOAD_FOR_OPERAND_ADDRESS
:
5759 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5760 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5761 && (!reloads_unique_chain_p (r1
, r2
)
5762 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5764 case RELOAD_FOR_OPADDR_ADDR
:
5765 return (r2_type
== RELOAD_FOR_INPUT
5766 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5768 case RELOAD_FOR_OUTPUT
:
5769 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5770 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5771 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5772 && r2_opnum
>= r1_opnum
));
5774 case RELOAD_FOR_INSN
:
5775 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5776 || r2_type
== RELOAD_FOR_INSN
5777 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5779 case RELOAD_FOR_OTHER_ADDRESS
:
5780 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5790 /* Indexed by reload number, 1 if incoming value
5791 inherited from previous insns. */
5792 static char reload_inherited
[MAX_RELOADS
];
5794 /* For an inherited reload, this is the insn the reload was inherited from,
5795 if we know it. Otherwise, this is 0. */
5796 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5798 /* If nonzero, this is a place to get the value of the reload,
5799 rather than using reload_in. */
5800 static rtx reload_override_in
[MAX_RELOADS
];
5802 /* For each reload, the hard register number of the register used,
5803 or -1 if we did not need a register for this reload. */
5804 static int reload_spill_index
[MAX_RELOADS
];
5806 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5807 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5809 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5810 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5812 /* Subroutine of free_for_value_p, used to check a single register.
5813 START_REGNO is the starting regno of the full reload register
5814 (possibly comprising multiple hard registers) that we are considering. */
5817 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5818 enum reload_type type
, rtx value
, rtx out
,
5819 int reloadnum
, int ignore_address_reloads
)
5822 /* Set if we see an input reload that must not share its reload register
5823 with any new earlyclobber, but might otherwise share the reload
5824 register with an output or input-output reload. */
5825 int check_earlyclobber
= 0;
5829 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5832 if (out
== const0_rtx
)
5838 /* We use some pseudo 'time' value to check if the lifetimes of the
5839 new register use would overlap with the one of a previous reload
5840 that is not read-only or uses a different value.
5841 The 'time' used doesn't have to be linear in any shape or form, just
5843 Some reload types use different 'buckets' for each operand.
5844 So there are MAX_RECOG_OPERANDS different time values for each
5846 We compute TIME1 as the time when the register for the prospective
5847 new reload ceases to be live, and TIME2 for each existing
5848 reload as the time when that the reload register of that reload
5850 Where there is little to be gained by exact lifetime calculations,
5851 we just make conservative assumptions, i.e. a longer lifetime;
5852 this is done in the 'default:' cases. */
5855 case RELOAD_FOR_OTHER_ADDRESS
:
5856 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5857 time1
= copy
? 0 : 1;
5860 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5862 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5863 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5864 respectively, to the time values for these, we get distinct time
5865 values. To get distinct time values for each operand, we have to
5866 multiply opnum by at least three. We round that up to four because
5867 multiply by four is often cheaper. */
5868 case RELOAD_FOR_INPADDR_ADDRESS
:
5869 time1
= opnum
* 4 + 2;
5871 case RELOAD_FOR_INPUT_ADDRESS
:
5872 time1
= opnum
* 4 + 3;
5874 case RELOAD_FOR_INPUT
:
5875 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5876 executes (inclusive). */
5877 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5879 case RELOAD_FOR_OPADDR_ADDR
:
5881 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5882 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5884 case RELOAD_FOR_OPERAND_ADDRESS
:
5885 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5887 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5889 case RELOAD_FOR_OUTADDR_ADDRESS
:
5890 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5892 case RELOAD_FOR_OUTPUT_ADDRESS
:
5893 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5896 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5899 for (i
= 0; i
< n_reloads
; i
++)
5901 rtx reg
= rld
[i
].reg_rtx
;
5902 if (reg
&& REG_P (reg
)
5903 && ((unsigned) regno
- true_regnum (reg
)
5904 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5907 rtx other_input
= rld
[i
].in
;
5909 /* If the other reload loads the same input value, that
5910 will not cause a conflict only if it's loading it into
5911 the same register. */
5912 if (true_regnum (reg
) != start_regno
)
5913 other_input
= NULL_RTX
;
5914 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5915 || rld
[i
].out
|| out
)
5918 switch (rld
[i
].when_needed
)
5920 case RELOAD_FOR_OTHER_ADDRESS
:
5923 case RELOAD_FOR_INPADDR_ADDRESS
:
5924 /* find_reloads makes sure that a
5925 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5926 by at most one - the first -
5927 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5928 address reload is inherited, the address address reload
5929 goes away, so we can ignore this conflict. */
5930 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5931 && ignore_address_reloads
5932 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5933 Then the address address is still needed to store
5934 back the new address. */
5935 && ! rld
[reloadnum
].out
)
5937 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5938 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5940 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5941 && ignore_address_reloads
5942 /* Unless we are reloading an auto_inc expression. */
5943 && ! rld
[reloadnum
].out
)
5945 time2
= rld
[i
].opnum
* 4 + 2;
5947 case RELOAD_FOR_INPUT_ADDRESS
:
5948 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5949 && ignore_address_reloads
5950 && ! rld
[reloadnum
].out
)
5952 time2
= rld
[i
].opnum
* 4 + 3;
5954 case RELOAD_FOR_INPUT
:
5955 time2
= rld
[i
].opnum
* 4 + 4;
5956 check_earlyclobber
= 1;
5958 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5959 == MAX_RECOG_OPERAND * 4 */
5960 case RELOAD_FOR_OPADDR_ADDR
:
5961 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5962 && ignore_address_reloads
5963 && ! rld
[reloadnum
].out
)
5965 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5967 case RELOAD_FOR_OPERAND_ADDRESS
:
5968 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5969 check_earlyclobber
= 1;
5971 case RELOAD_FOR_INSN
:
5972 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5974 case RELOAD_FOR_OUTPUT
:
5975 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5976 instruction is executed. */
5977 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5979 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5980 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5982 case RELOAD_FOR_OUTADDR_ADDRESS
:
5983 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5984 && ignore_address_reloads
5985 && ! rld
[reloadnum
].out
)
5987 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5989 case RELOAD_FOR_OUTPUT_ADDRESS
:
5990 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5993 /* If there is no conflict in the input part, handle this
5994 like an output reload. */
5995 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5997 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5998 /* Earlyclobbered outputs must conflict with inputs. */
5999 if (earlyclobber_operand_p (rld
[i
].out
))
6000 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6005 /* RELOAD_OTHER might be live beyond instruction execution,
6006 but this is not obvious when we set time2 = 1. So check
6007 here if there might be a problem with the new reload
6008 clobbering the register used by the RELOAD_OTHER. */
6016 && (! rld
[i
].in
|| rld
[i
].out
6017 || ! rtx_equal_p (other_input
, value
)))
6018 || (out
&& rld
[reloadnum
].out_reg
6019 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6025 /* Earlyclobbered outputs must conflict with inputs. */
6026 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6032 /* Return 1 if the value in reload reg REGNO, as used by a reload
6033 needed for the part of the insn specified by OPNUM and TYPE,
6034 may be used to load VALUE into it.
6036 MODE is the mode in which the register is used, this is needed to
6037 determine how many hard regs to test.
6039 Other read-only reloads with the same value do not conflict
6040 unless OUT is nonzero and these other reloads have to live while
6041 output reloads live.
6042 If OUT is CONST0_RTX, this is a special case: it means that the
6043 test should not be for using register REGNO as reload register, but
6044 for copying from register REGNO into the reload register.
6046 RELOADNUM is the number of the reload we want to load this value for;
6047 a reload does not conflict with itself.
6049 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6050 reloads that load an address for the very reload we are considering.
6052 The caller has to make sure that there is no conflict with the return
6056 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6057 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6058 int ignore_address_reloads
)
6060 int nregs
= hard_regno_nregs
[regno
][mode
];
6062 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6063 value
, out
, reloadnum
,
6064 ignore_address_reloads
))
6069 /* Return nonzero if the rtx X is invariant over the current function. */
6070 /* ??? Actually, the places where we use this expect exactly what is
6071 tested here, and not everything that is function invariant. In
6072 particular, the frame pointer and arg pointer are special cased;
6073 pic_offset_table_rtx is not, and we must not spill these things to
6077 function_invariant_p (const_rtx x
)
6081 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6083 if (GET_CODE (x
) == PLUS
6084 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6085 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6090 /* Determine whether the reload reg X overlaps any rtx'es used for
6091 overriding inheritance. Return nonzero if so. */
6094 conflicts_with_override (rtx x
)
6097 for (i
= 0; i
< n_reloads
; i
++)
6098 if (reload_override_in
[i
]
6099 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6104 /* Give an error message saying we failed to find a reload for INSN,
6105 and clear out reload R. */
6107 failed_reload (rtx insn
, int r
)
6109 if (asm_noperands (PATTERN (insn
)) < 0)
6110 /* It's the compiler's fault. */
6111 fatal_insn ("could not find a spill register", insn
);
6113 /* It's the user's fault; the operand's mode and constraint
6114 don't match. Disable this reload so we don't crash in final. */
6115 error_for_asm (insn
,
6116 "%<asm%> operand constraint incompatible with operand size");
6120 rld
[r
].optional
= 1;
6121 rld
[r
].secondary_p
= 1;
6124 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6125 for reload R. If it's valid, get an rtx for it. Return nonzero if
6128 set_reload_reg (int i
, int r
)
6130 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6132 int regno ATTRIBUTE_UNUSED
;
6133 rtx reg
= spill_reg_rtx
[i
];
6135 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6136 spill_reg_rtx
[i
] = reg
6137 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6139 regno
= true_regnum (reg
);
6141 /* Detect when the reload reg can't hold the reload mode.
6142 This used to be one `if', but Sequent compiler can't handle that. */
6143 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6145 enum machine_mode test_mode
= VOIDmode
;
6147 test_mode
= GET_MODE (rld
[r
].in
);
6148 /* If rld[r].in has VOIDmode, it means we will load it
6149 in whatever mode the reload reg has: to wit, rld[r].mode.
6150 We have already tested that for validity. */
6151 /* Aside from that, we need to test that the expressions
6152 to reload from or into have modes which are valid for this
6153 reload register. Otherwise the reload insns would be invalid. */
6154 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6155 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6156 if (! (rld
[r
].out
!= 0
6157 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6159 /* The reg is OK. */
6162 /* Mark as in use for this insn the reload regs we use
6164 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6165 rld
[r
].when_needed
, rld
[r
].mode
);
6167 rld
[r
].reg_rtx
= reg
;
6168 reload_spill_index
[r
] = spill_regs
[i
];
6175 /* Find a spill register to use as a reload register for reload R.
6176 LAST_RELOAD is nonzero if this is the last reload for the insn being
6179 Set rld[R].reg_rtx to the register allocated.
6181 We return 1 if successful, or 0 if we couldn't find a spill reg and
6182 we didn't change anything. */
6185 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6190 /* If we put this reload ahead, thinking it is a group,
6191 then insist on finding a group. Otherwise we can grab a
6192 reg that some other reload needs.
6193 (That can happen when we have a 68000 DATA_OR_FP_REG
6194 which is a group of data regs or one fp reg.)
6195 We need not be so restrictive if there are no more reloads
6198 ??? Really it would be nicer to have smarter handling
6199 for that kind of reg class, where a problem like this is normal.
6200 Perhaps those classes should be avoided for reloading
6201 by use of more alternatives. */
6203 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6205 /* If we want a single register and haven't yet found one,
6206 take any reg in the right class and not in use.
6207 If we want a consecutive group, here is where we look for it.
6209 We use three passes so we can first look for reload regs to
6210 reuse, which are already in use for other reloads in this insn,
6211 and only then use additional registers which are not "bad", then
6212 finally any register.
6214 I think that maximizing reuse is needed to make sure we don't
6215 run out of reload regs. Suppose we have three reloads, and
6216 reloads A and B can share regs. These need two regs.
6217 Suppose A and B are given different regs.
6218 That leaves none for C. */
6219 for (pass
= 0; pass
< 3; pass
++)
6221 /* I is the index in spill_regs.
6222 We advance it round-robin between insns to use all spill regs
6223 equally, so that inherited reloads have a chance
6224 of leapfrogging each other. */
6228 for (count
= 0; count
< n_spills
; count
++)
6230 int rclass
= (int) rld
[r
].rclass
;
6236 regnum
= spill_regs
[i
];
6238 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6241 /* We check reload_reg_used to make sure we
6242 don't clobber the return register. */
6243 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6244 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6245 rld
[r
].when_needed
, rld
[r
].in
,
6247 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6248 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6249 /* Look first for regs to share, then for unshared. But
6250 don't share regs used for inherited reloads; they are
6251 the ones we want to preserve. */
6253 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6255 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6258 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6260 /* During the second pass we want to avoid reload registers
6261 which are "bad" for this reload. */
6263 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6266 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6267 (on 68000) got us two FP regs. If NR is 1,
6268 we would reject both of them. */
6271 /* If we need only one reg, we have already won. */
6274 /* But reject a single reg if we demand a group. */
6279 /* Otherwise check that as many consecutive regs as we need
6280 are available here. */
6283 int regno
= regnum
+ nr
- 1;
6284 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6285 && spill_reg_order
[regno
] >= 0
6286 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6287 rld
[r
].when_needed
)))
6296 /* If we found something on the current pass, omit later passes. */
6297 if (count
< n_spills
)
6301 /* We should have found a spill register by now. */
6302 if (count
>= n_spills
)
6305 /* I is the index in SPILL_REG_RTX of the reload register we are to
6306 allocate. Get an rtx for it and find its register number. */
6308 return set_reload_reg (i
, r
);
6311 /* Initialize all the tables needed to allocate reload registers.
6312 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6313 is the array we use to restore the reg_rtx field for every reload. */
6316 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6320 for (i
= 0; i
< n_reloads
; i
++)
6321 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6323 memset (reload_inherited
, 0, MAX_RELOADS
);
6324 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6325 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6327 CLEAR_HARD_REG_SET (reload_reg_used
);
6328 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6329 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6330 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6331 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6334 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6337 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6338 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6339 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6340 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6341 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6342 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6345 for (i
= 0; i
< reload_n_operands
; i
++)
6347 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6348 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6349 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6350 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6351 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6352 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6355 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6357 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6359 for (i
= 0; i
< n_reloads
; i
++)
6360 /* If we have already decided to use a certain register,
6361 don't use it in another way. */
6363 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6364 rld
[i
].when_needed
, rld
[i
].mode
);
6367 /* Assign hard reg targets for the pseudo-registers we must reload
6368 into hard regs for this insn.
6369 Also output the instructions to copy them in and out of the hard regs.
6371 For machines with register classes, we are responsible for
6372 finding a reload reg in the proper class. */
6375 choose_reload_regs (struct insn_chain
*chain
)
6377 rtx insn
= chain
->insn
;
6379 unsigned int max_group_size
= 1;
6380 enum reg_class group_class
= NO_REGS
;
6381 int pass
, win
, inheritance
;
6383 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6385 /* In order to be certain of getting the registers we need,
6386 we must sort the reloads into order of increasing register class.
6387 Then our grabbing of reload registers will parallel the process
6388 that provided the reload registers.
6390 Also note whether any of the reloads wants a consecutive group of regs.
6391 If so, record the maximum size of the group desired and what
6392 register class contains all the groups needed by this insn. */
6394 for (j
= 0; j
< n_reloads
; j
++)
6396 reload_order
[j
] = j
;
6397 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6399 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6400 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6401 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6404 reload_spill_index
[j
] = -1;
6406 if (rld
[j
].nregs
> 1)
6408 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6410 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6413 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6417 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6419 /* If -O, try first with inheritance, then turning it off.
6420 If not -O, don't do inheritance.
6421 Using inheritance when not optimizing leads to paradoxes
6422 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6423 because one side of the comparison might be inherited. */
6425 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6427 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6429 /* Process the reloads in order of preference just found.
6430 Beyond this point, subregs can be found in reload_reg_rtx.
6432 This used to look for an existing reloaded home for all of the
6433 reloads, and only then perform any new reloads. But that could lose
6434 if the reloads were done out of reg-class order because a later
6435 reload with a looser constraint might have an old home in a register
6436 needed by an earlier reload with a tighter constraint.
6438 To solve this, we make two passes over the reloads, in the order
6439 described above. In the first pass we try to inherit a reload
6440 from a previous insn. If there is a later reload that needs a
6441 class that is a proper subset of the class being processed, we must
6442 also allocate a spill register during the first pass.
6444 Then make a second pass over the reloads to allocate any reloads
6445 that haven't been given registers yet. */
6447 for (j
= 0; j
< n_reloads
; j
++)
6449 int r
= reload_order
[j
];
6450 rtx search_equiv
= NULL_RTX
;
6452 /* Ignore reloads that got marked inoperative. */
6453 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6454 && ! rld
[r
].secondary_p
)
6457 /* If find_reloads chose to use reload_in or reload_out as a reload
6458 register, we don't need to chose one. Otherwise, try even if it
6459 found one since we might save an insn if we find the value lying
6461 Try also when reload_in is a pseudo without a hard reg. */
6462 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6463 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6464 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6465 && !MEM_P (rld
[r
].in
)
6466 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6469 #if 0 /* No longer needed for correct operation.
6470 It might give better code, or might not; worth an experiment? */
6471 /* If this is an optional reload, we can't inherit from earlier insns
6472 until we are sure that any non-optional reloads have been allocated.
6473 The following code takes advantage of the fact that optional reloads
6474 are at the end of reload_order. */
6475 if (rld
[r
].optional
!= 0)
6476 for (i
= 0; i
< j
; i
++)
6477 if ((rld
[reload_order
[i
]].out
!= 0
6478 || rld
[reload_order
[i
]].in
!= 0
6479 || rld
[reload_order
[i
]].secondary_p
)
6480 && ! rld
[reload_order
[i
]].optional
6481 && rld
[reload_order
[i
]].reg_rtx
== 0)
6482 allocate_reload_reg (chain
, reload_order
[i
], 0);
6485 /* First see if this pseudo is already available as reloaded
6486 for a previous insn. We cannot try to inherit for reloads
6487 that are smaller than the maximum number of registers needed
6488 for groups unless the register we would allocate cannot be used
6491 We could check here to see if this is a secondary reload for
6492 an object that is already in a register of the desired class.
6493 This would avoid the need for the secondary reload register.
6494 But this is complex because we can't easily determine what
6495 objects might want to be loaded via this reload. So let a
6496 register be allocated here. In `emit_reload_insns' we suppress
6497 one of the loads in the case described above. */
6503 enum machine_mode mode
= VOIDmode
;
6507 else if (REG_P (rld
[r
].in
))
6509 regno
= REGNO (rld
[r
].in
);
6510 mode
= GET_MODE (rld
[r
].in
);
6512 else if (REG_P (rld
[r
].in_reg
))
6514 regno
= REGNO (rld
[r
].in_reg
);
6515 mode
= GET_MODE (rld
[r
].in_reg
);
6517 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6518 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6520 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6521 if (regno
< FIRST_PSEUDO_REGISTER
)
6522 regno
= subreg_regno (rld
[r
].in_reg
);
6524 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6525 mode
= GET_MODE (rld
[r
].in_reg
);
6528 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6529 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6531 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6532 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6533 rld
[r
].out
= rld
[r
].in
;
6537 /* This won't work, since REGNO can be a pseudo reg number.
6538 Also, it takes much more hair to keep track of all the things
6539 that can invalidate an inherited reload of part of a pseudoreg. */
6540 else if (GET_CODE (rld
[r
].in
) == SUBREG
6541 && REG_P (SUBREG_REG (rld
[r
].in
)))
6542 regno
= subreg_regno (rld
[r
].in
);
6546 && reg_last_reload_reg
[regno
] != 0
6547 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6548 >= GET_MODE_SIZE (mode
) + byte
)
6549 #ifdef CANNOT_CHANGE_MODE_CLASS
6550 /* Verify that the register it's in can be used in
6552 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6553 GET_MODE (reg_last_reload_reg
[regno
]),
6558 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6559 rtx last_reg
= reg_last_reload_reg
[regno
];
6561 i
= REGNO (last_reg
);
6562 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6563 last_class
= REGNO_REG_CLASS (i
);
6565 if (reg_reloaded_contents
[i
] == regno
6566 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6567 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6568 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6569 /* Even if we can't use this register as a reload
6570 register, we might use it for reload_override_in,
6571 if copying it to the desired class is cheap
6573 || ((register_move_cost (mode
, last_class
, rclass
)
6574 < memory_move_cost (mode
, rclass
, true))
6575 && (secondary_reload_class (1, rclass
, mode
,
6578 #ifdef SECONDARY_MEMORY_NEEDED
6579 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6584 && (rld
[r
].nregs
== max_group_size
6585 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6587 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6588 rld
[r
].when_needed
, rld
[r
].in
,
6591 /* If a group is needed, verify that all the subsequent
6592 registers still have their values intact. */
6593 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6596 for (k
= 1; k
< nr
; k
++)
6597 if (reg_reloaded_contents
[i
+ k
] != regno
6598 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6606 last_reg
= (GET_MODE (last_reg
) == mode
6607 ? last_reg
: gen_rtx_REG (mode
, i
));
6610 for (k
= 0; k
< nr
; k
++)
6611 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6614 /* We found a register that contains the
6615 value we need. If this register is the
6616 same as an `earlyclobber' operand of the
6617 current insn, just mark it as a place to
6618 reload from since we can't use it as the
6619 reload register itself. */
6621 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6622 if (reg_overlap_mentioned_for_reload_p
6623 (reg_last_reload_reg
[regno
],
6624 reload_earlyclobbers
[i1
]))
6627 if (i1
!= n_earlyclobbers
6628 || ! (free_for_value_p (i
, rld
[r
].mode
,
6630 rld
[r
].when_needed
, rld
[r
].in
,
6632 /* Don't use it if we'd clobber a pseudo reg. */
6633 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6635 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6636 /* Don't clobber the frame pointer. */
6637 || (i
== HARD_FRAME_POINTER_REGNUM
6638 && frame_pointer_needed
6640 /* Don't really use the inherited spill reg
6641 if we need it wider than we've got it. */
6642 || (GET_MODE_SIZE (rld
[r
].mode
)
6643 > GET_MODE_SIZE (mode
))
6646 /* If find_reloads chose reload_out as reload
6647 register, stay with it - that leaves the
6648 inherited register for subsequent reloads. */
6649 || (rld
[r
].out
&& rld
[r
].reg_rtx
6650 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6652 if (! rld
[r
].optional
)
6654 reload_override_in
[r
] = last_reg
;
6655 reload_inheritance_insn
[r
]
6656 = reg_reloaded_insn
[i
];
6662 /* We can use this as a reload reg. */
6663 /* Mark the register as in use for this part of
6665 mark_reload_reg_in_use (i
,
6669 rld
[r
].reg_rtx
= last_reg
;
6670 reload_inherited
[r
] = 1;
6671 reload_inheritance_insn
[r
]
6672 = reg_reloaded_insn
[i
];
6673 reload_spill_index
[r
] = i
;
6674 for (k
= 0; k
< nr
; k
++)
6675 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6683 /* Here's another way to see if the value is already lying around. */
6686 && ! reload_inherited
[r
]
6688 && (CONSTANT_P (rld
[r
].in
)
6689 || GET_CODE (rld
[r
].in
) == PLUS
6690 || REG_P (rld
[r
].in
)
6691 || MEM_P (rld
[r
].in
))
6692 && (rld
[r
].nregs
== max_group_size
6693 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6694 search_equiv
= rld
[r
].in
;
6699 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6700 -1, NULL
, 0, rld
[r
].mode
);
6706 regno
= REGNO (equiv
);
6709 /* This must be a SUBREG of a hard register.
6710 Make a new REG since this might be used in an
6711 address and not all machines support SUBREGs
6713 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6714 regno
= subreg_regno (equiv
);
6715 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6716 /* If we choose EQUIV as the reload register, but the
6717 loop below decides to cancel the inheritance, we'll
6718 end up reloading EQUIV in rld[r].mode, not the mode
6719 it had originally. That isn't safe when EQUIV isn't
6720 available as a spill register since its value might
6721 still be live at this point. */
6722 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6723 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6728 /* If we found a spill reg, reject it unless it is free
6729 and of the desired class. */
6733 int bad_for_class
= 0;
6734 int max_regno
= regno
+ rld
[r
].nregs
;
6736 for (i
= regno
; i
< max_regno
; i
++)
6738 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6740 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6745 && ! free_for_value_p (regno
, rld
[r
].mode
,
6746 rld
[r
].opnum
, rld
[r
].when_needed
,
6747 rld
[r
].in
, rld
[r
].out
, r
, 1))
6752 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6755 /* We found a register that contains the value we need.
6756 If this register is the same as an `earlyclobber' operand
6757 of the current insn, just mark it as a place to reload from
6758 since we can't use it as the reload register itself. */
6761 for (i
= 0; i
< n_earlyclobbers
; i
++)
6762 if (reg_overlap_mentioned_for_reload_p (equiv
,
6763 reload_earlyclobbers
[i
]))
6765 if (! rld
[r
].optional
)
6766 reload_override_in
[r
] = equiv
;
6771 /* If the equiv register we have found is explicitly clobbered
6772 in the current insn, it depends on the reload type if we
6773 can use it, use it for reload_override_in, or not at all.
6774 In particular, we then can't use EQUIV for a
6775 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6779 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6780 switch (rld
[r
].when_needed
)
6782 case RELOAD_FOR_OTHER_ADDRESS
:
6783 case RELOAD_FOR_INPADDR_ADDRESS
:
6784 case RELOAD_FOR_INPUT_ADDRESS
:
6785 case RELOAD_FOR_OPADDR_ADDR
:
6788 case RELOAD_FOR_INPUT
:
6789 case RELOAD_FOR_OPERAND_ADDRESS
:
6790 if (! rld
[r
].optional
)
6791 reload_override_in
[r
] = equiv
;
6797 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6798 switch (rld
[r
].when_needed
)
6800 case RELOAD_FOR_OTHER_ADDRESS
:
6801 case RELOAD_FOR_INPADDR_ADDRESS
:
6802 case RELOAD_FOR_INPUT_ADDRESS
:
6803 case RELOAD_FOR_OPADDR_ADDR
:
6804 case RELOAD_FOR_OPERAND_ADDRESS
:
6805 case RELOAD_FOR_INPUT
:
6808 if (! rld
[r
].optional
)
6809 reload_override_in
[r
] = equiv
;
6817 /* If we found an equivalent reg, say no code need be generated
6818 to load it, and use it as our reload reg. */
6820 && (regno
!= HARD_FRAME_POINTER_REGNUM
6821 || !frame_pointer_needed
))
6823 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6825 rld
[r
].reg_rtx
= equiv
;
6826 reload_spill_index
[r
] = regno
;
6827 reload_inherited
[r
] = 1;
6829 /* If reg_reloaded_valid is not set for this register,
6830 there might be a stale spill_reg_store lying around.
6831 We must clear it, since otherwise emit_reload_insns
6832 might delete the store. */
6833 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6834 spill_reg_store
[regno
] = NULL_RTX
;
6835 /* If any of the hard registers in EQUIV are spill
6836 registers, mark them as in use for this insn. */
6837 for (k
= 0; k
< nr
; k
++)
6839 i
= spill_reg_order
[regno
+ k
];
6842 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6845 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6852 /* If we found a register to use already, or if this is an optional
6853 reload, we are done. */
6854 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6858 /* No longer needed for correct operation. Might or might
6859 not give better code on the average. Want to experiment? */
6861 /* See if there is a later reload that has a class different from our
6862 class that intersects our class or that requires less register
6863 than our reload. If so, we must allocate a register to this
6864 reload now, since that reload might inherit a previous reload
6865 and take the only available register in our class. Don't do this
6866 for optional reloads since they will force all previous reloads
6867 to be allocated. Also don't do this for reloads that have been
6870 for (i
= j
+ 1; i
< n_reloads
; i
++)
6872 int s
= reload_order
[i
];
6874 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6875 && ! rld
[s
].secondary_p
)
6879 if ((rld
[s
].rclass
!= rld
[r
].rclass
6880 && reg_classes_intersect_p (rld
[r
].rclass
,
6882 || rld
[s
].nregs
< rld
[r
].nregs
)
6889 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6893 /* Now allocate reload registers for anything non-optional that
6894 didn't get one yet. */
6895 for (j
= 0; j
< n_reloads
; j
++)
6897 int r
= reload_order
[j
];
6899 /* Ignore reloads that got marked inoperative. */
6900 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6903 /* Skip reloads that already have a register allocated or are
6905 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6908 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6912 /* If that loop got all the way, we have won. */
6919 /* Loop around and try without any inheritance. */
6924 /* First undo everything done by the failed attempt
6925 to allocate with inheritance. */
6926 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6928 /* Some sanity tests to verify that the reloads found in the first
6929 pass are identical to the ones we have now. */
6930 gcc_assert (chain
->n_reloads
== n_reloads
);
6932 for (i
= 0; i
< n_reloads
; i
++)
6934 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6936 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6937 for (j
= 0; j
< n_spills
; j
++)
6938 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6939 if (! set_reload_reg (j
, i
))
6940 failed_reload (chain
->insn
, i
);
6944 /* If we thought we could inherit a reload, because it seemed that
6945 nothing else wanted the same reload register earlier in the insn,
6946 verify that assumption, now that all reloads have been assigned.
6947 Likewise for reloads where reload_override_in has been set. */
6949 /* If doing expensive optimizations, do one preliminary pass that doesn't
6950 cancel any inheritance, but removes reloads that have been needed only
6951 for reloads that we know can be inherited. */
6952 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6954 for (j
= 0; j
< n_reloads
; j
++)
6956 int r
= reload_order
[j
];
6958 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6959 check_reg
= rld
[r
].reg_rtx
;
6960 else if (reload_override_in
[r
]
6961 && (REG_P (reload_override_in
[r
])
6962 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6963 check_reg
= reload_override_in
[r
];
6966 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6967 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6968 (reload_inherited
[r
]
6969 ? rld
[r
].out
: const0_rtx
),
6974 reload_inherited
[r
] = 0;
6975 reload_override_in
[r
] = 0;
6977 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6978 reload_override_in, then we do not need its related
6979 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6980 likewise for other reload types.
6981 We handle this by removing a reload when its only replacement
6982 is mentioned in reload_in of the reload we are going to inherit.
6983 A special case are auto_inc expressions; even if the input is
6984 inherited, we still need the address for the output. We can
6985 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6986 If we succeeded removing some reload and we are doing a preliminary
6987 pass just to remove such reloads, make another pass, since the
6988 removal of one reload might allow us to inherit another one. */
6990 && rld
[r
].out
!= rld
[r
].in
6991 && remove_address_replacements (rld
[r
].in
) && pass
)
6996 /* Now that reload_override_in is known valid,
6997 actually override reload_in. */
6998 for (j
= 0; j
< n_reloads
; j
++)
6999 if (reload_override_in
[j
])
7000 rld
[j
].in
= reload_override_in
[j
];
7002 /* If this reload won't be done because it has been canceled or is
7003 optional and not inherited, clear reload_reg_rtx so other
7004 routines (such as subst_reloads) don't get confused. */
7005 for (j
= 0; j
< n_reloads
; j
++)
7006 if (rld
[j
].reg_rtx
!= 0
7007 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7008 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7009 && ! rld
[j
].secondary_p
)))
7011 int regno
= true_regnum (rld
[j
].reg_rtx
);
7013 if (spill_reg_order
[regno
] >= 0)
7014 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7015 rld
[j
].when_needed
, rld
[j
].mode
);
7017 reload_spill_index
[j
] = -1;
7020 /* Record which pseudos and which spill regs have output reloads. */
7021 for (j
= 0; j
< n_reloads
; j
++)
7023 int r
= reload_order
[j
];
7025 i
= reload_spill_index
[r
];
7027 /* I is nonneg if this reload uses a register.
7028 If rld[r].reg_rtx is 0, this is an optional reload
7029 that we opted to ignore. */
7030 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7031 && rld
[r
].reg_rtx
!= 0)
7033 int nregno
= REGNO (rld
[r
].out_reg
);
7036 if (nregno
< FIRST_PSEUDO_REGISTER
)
7037 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7040 SET_REGNO_REG_SET (®_has_output_reload
,
7044 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7046 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7047 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7048 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7053 /* Deallocate the reload register for reload R. This is called from
7054 remove_address_replacements. */
7057 deallocate_reload_reg (int r
)
7061 if (! rld
[r
].reg_rtx
)
7063 regno
= true_regnum (rld
[r
].reg_rtx
);
7065 if (spill_reg_order
[regno
] >= 0)
7066 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7068 reload_spill_index
[r
] = -1;
7071 /* These arrays are filled by emit_reload_insns and its subroutines. */
7072 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7073 static rtx other_input_address_reload_insns
= 0;
7074 static rtx other_input_reload_insns
= 0;
7075 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7076 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7077 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7078 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7079 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7080 static rtx operand_reload_insns
= 0;
7081 static rtx other_operand_reload_insns
= 0;
7082 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7084 /* Values to be put in spill_reg_store are put here first. Instructions
7085 must only be placed here if the associated reload register reaches
7086 the end of the instruction's reload sequence. */
7087 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7088 static HARD_REG_SET reg_reloaded_died
;
7090 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7091 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7092 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7093 adjusted register, and return true. Otherwise, return false. */
7095 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7096 enum reg_class new_class
,
7097 enum machine_mode new_mode
)
7102 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7104 unsigned regno
= REGNO (reg
);
7106 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7108 if (GET_MODE (reg
) != new_mode
)
7110 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7112 if (hard_regno_nregs
[regno
][new_mode
]
7113 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7115 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7123 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7124 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7125 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7126 adjusted register, and return true. Otherwise, return false. */
7128 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7129 enum insn_code icode
)
7132 enum reg_class new_class
= scratch_reload_class (icode
);
7133 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7135 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7136 new_class
, new_mode
);
7139 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7140 has the number J. OLD contains the value to be used as input. */
7143 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7146 rtx insn
= chain
->insn
;
7148 rtx oldequiv_reg
= 0;
7151 enum machine_mode mode
;
7154 /* delete_output_reload is only invoked properly if old contains
7155 the original pseudo register. Since this is replaced with a
7156 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7157 find the pseudo in RELOAD_IN_REG. */
7158 if (reload_override_in
[j
]
7159 && REG_P (rl
->in_reg
))
7166 else if (REG_P (oldequiv
))
7167 oldequiv_reg
= oldequiv
;
7168 else if (GET_CODE (oldequiv
) == SUBREG
)
7169 oldequiv_reg
= SUBREG_REG (oldequiv
);
7171 reloadreg
= reload_reg_rtx_for_input
[j
];
7172 mode
= GET_MODE (reloadreg
);
7174 /* If we are reloading from a register that was recently stored in
7175 with an output-reload, see if we can prove there was
7176 actually no need to store the old value in it. */
7178 if (optimize
&& REG_P (oldequiv
)
7179 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7180 && spill_reg_store
[REGNO (oldequiv
)]
7182 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7183 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7185 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7187 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7190 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7191 oldequiv
= SUBREG_REG (oldequiv
);
7192 if (GET_MODE (oldequiv
) != VOIDmode
7193 && mode
!= GET_MODE (oldequiv
))
7194 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7196 /* Switch to the right place to emit the reload insns. */
7197 switch (rl
->when_needed
)
7200 where
= &other_input_reload_insns
;
7202 case RELOAD_FOR_INPUT
:
7203 where
= &input_reload_insns
[rl
->opnum
];
7205 case RELOAD_FOR_INPUT_ADDRESS
:
7206 where
= &input_address_reload_insns
[rl
->opnum
];
7208 case RELOAD_FOR_INPADDR_ADDRESS
:
7209 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7211 case RELOAD_FOR_OUTPUT_ADDRESS
:
7212 where
= &output_address_reload_insns
[rl
->opnum
];
7214 case RELOAD_FOR_OUTADDR_ADDRESS
:
7215 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7217 case RELOAD_FOR_OPERAND_ADDRESS
:
7218 where
= &operand_reload_insns
;
7220 case RELOAD_FOR_OPADDR_ADDR
:
7221 where
= &other_operand_reload_insns
;
7223 case RELOAD_FOR_OTHER_ADDRESS
:
7224 where
= &other_input_address_reload_insns
;
7230 push_to_sequence (*where
);
7232 /* Auto-increment addresses must be reloaded in a special way. */
7233 if (rl
->out
&& ! rl
->out_reg
)
7235 /* We are not going to bother supporting the case where a
7236 incremented register can't be copied directly from
7237 OLDEQUIV since this seems highly unlikely. */
7238 gcc_assert (rl
->secondary_in_reload
< 0);
7240 if (reload_inherited
[j
])
7241 oldequiv
= reloadreg
;
7243 old
= XEXP (rl
->in_reg
, 0);
7245 /* Prevent normal processing of this reload. */
7247 /* Output a special code sequence for this case. */
7248 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7251 /* If we are reloading a pseudo-register that was set by the previous
7252 insn, see if we can get rid of that pseudo-register entirely
7253 by redirecting the previous insn into our reload register. */
7255 else if (optimize
&& REG_P (old
)
7256 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7257 && dead_or_set_p (insn
, old
)
7258 /* This is unsafe if some other reload
7259 uses the same reg first. */
7260 && ! conflicts_with_override (reloadreg
)
7261 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7262 rl
->when_needed
, old
, rl
->out
, j
, 0))
7264 rtx temp
= PREV_INSN (insn
);
7265 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7266 temp
= PREV_INSN (temp
);
7268 && NONJUMP_INSN_P (temp
)
7269 && GET_CODE (PATTERN (temp
)) == SET
7270 && SET_DEST (PATTERN (temp
)) == old
7271 /* Make sure we can access insn_operand_constraint. */
7272 && asm_noperands (PATTERN (temp
)) < 0
7273 /* This is unsafe if operand occurs more than once in current
7274 insn. Perhaps some occurrences aren't reloaded. */
7275 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7277 rtx old
= SET_DEST (PATTERN (temp
));
7278 /* Store into the reload register instead of the pseudo. */
7279 SET_DEST (PATTERN (temp
)) = reloadreg
;
7281 /* Verify that resulting insn is valid. */
7282 extract_insn (temp
);
7283 if (constrain_operands (1))
7285 /* If the previous insn is an output reload, the source is
7286 a reload register, and its spill_reg_store entry will
7287 contain the previous destination. This is now
7289 if (REG_P (SET_SRC (PATTERN (temp
)))
7290 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7292 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7293 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7296 /* If these are the only uses of the pseudo reg,
7297 pretend for GDB it lives in the reload reg we used. */
7298 if (REG_N_DEATHS (REGNO (old
)) == 1
7299 && REG_N_SETS (REGNO (old
)) == 1)
7301 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7302 if (ira_conflicts_p
)
7303 /* Inform IRA about the change. */
7304 ira_mark_allocation_change (REGNO (old
));
7305 alter_reg (REGNO (old
), -1, false);
7309 /* Adjust any debug insns between temp and insn. */
7310 while ((temp
= NEXT_INSN (temp
)) != insn
)
7311 if (DEBUG_INSN_P (temp
))
7312 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7314 gcc_assert (NOTE_P (temp
));
7318 SET_DEST (PATTERN (temp
)) = old
;
7323 /* We can't do that, so output an insn to load RELOADREG. */
7325 /* If we have a secondary reload, pick up the secondary register
7326 and icode, if any. If OLDEQUIV and OLD are different or
7327 if this is an in-out reload, recompute whether or not we
7328 still need a secondary register and what the icode should
7329 be. If we still need a secondary register and the class or
7330 icode is different, go back to reloading from OLD if using
7331 OLDEQUIV means that we got the wrong type of register. We
7332 cannot have different class or icode due to an in-out reload
7333 because we don't make such reloads when both the input and
7334 output need secondary reload registers. */
7336 if (! special
&& rl
->secondary_in_reload
>= 0)
7338 rtx second_reload_reg
= 0;
7339 rtx third_reload_reg
= 0;
7340 int secondary_reload
= rl
->secondary_in_reload
;
7341 rtx real_oldequiv
= oldequiv
;
7344 enum insn_code icode
;
7345 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7347 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7348 and similarly for OLD.
7349 See comments in get_secondary_reload in reload.c. */
7350 /* If it is a pseudo that cannot be replaced with its
7351 equivalent MEM, we must fall back to reload_in, which
7352 will have all the necessary substitutions registered.
7353 Likewise for a pseudo that can't be replaced with its
7354 equivalent constant.
7356 Take extra care for subregs of such pseudos. Note that
7357 we cannot use reg_equiv_mem in this case because it is
7358 not in the right mode. */
7361 if (GET_CODE (tmp
) == SUBREG
)
7362 tmp
= SUBREG_REG (tmp
);
7364 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7365 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7366 || reg_equiv_constant (REGNO (tmp
)) != 0))
7368 if (! reg_equiv_mem (REGNO (tmp
))
7369 || num_not_at_initial_offset
7370 || GET_CODE (oldequiv
) == SUBREG
)
7371 real_oldequiv
= rl
->in
;
7373 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7377 if (GET_CODE (tmp
) == SUBREG
)
7378 tmp
= SUBREG_REG (tmp
);
7380 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7381 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7382 || reg_equiv_constant (REGNO (tmp
)) != 0))
7384 if (! reg_equiv_mem (REGNO (tmp
))
7385 || num_not_at_initial_offset
7386 || GET_CODE (old
) == SUBREG
)
7389 real_old
= reg_equiv_mem (REGNO (tmp
));
7392 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7393 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7395 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7397 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7398 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7399 /* We'd have to add more code for quartary reloads. */
7400 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7402 icode
= rl
->secondary_in_icode
;
7404 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7405 || (rl
->in
!= 0 && rl
->out
!= 0))
7407 secondary_reload_info sri
, sri2
;
7408 enum reg_class new_class
, new_t_class
;
7410 sri
.icode
= CODE_FOR_nothing
;
7411 sri
.prev_sri
= NULL
;
7413 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7417 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7418 second_reload_reg
= 0;
7419 else if (new_class
== NO_REGS
)
7421 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7423 (enum insn_code
) sri
.icode
))
7425 icode
= (enum insn_code
) sri
.icode
;
7426 third_reload_reg
= 0;
7431 real_oldequiv
= real_old
;
7434 else if (sri
.icode
!= CODE_FOR_nothing
)
7435 /* We currently lack a way to express this in reloads. */
7439 sri2
.icode
= CODE_FOR_nothing
;
7440 sri2
.prev_sri
= &sri
;
7442 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7445 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7447 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7451 third_reload_reg
= 0;
7452 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7457 real_oldequiv
= real_old
;
7460 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7462 rtx intermediate
= second_reload_reg
;
7464 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7466 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7470 second_reload_reg
= intermediate
;
7471 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7476 real_oldequiv
= real_old
;
7479 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7481 rtx intermediate
= second_reload_reg
;
7483 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7485 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7488 second_reload_reg
= intermediate
;
7489 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7494 real_oldequiv
= real_old
;
7499 /* This could be handled more intelligently too. */
7501 real_oldequiv
= real_old
;
7506 /* If we still need a secondary reload register, check
7507 to see if it is being used as a scratch or intermediate
7508 register and generate code appropriately. If we need
7509 a scratch register, use REAL_OLDEQUIV since the form of
7510 the insn may depend on the actual address if it is
7513 if (second_reload_reg
)
7515 if (icode
!= CODE_FOR_nothing
)
7517 /* We'd have to add extra code to handle this case. */
7518 gcc_assert (!third_reload_reg
);
7520 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7521 second_reload_reg
));
7526 /* See if we need a scratch register to load the
7527 intermediate register (a tertiary reload). */
7528 if (tertiary_icode
!= CODE_FOR_nothing
)
7530 emit_insn ((GEN_FCN (tertiary_icode
)
7531 (second_reload_reg
, real_oldequiv
,
7532 third_reload_reg
)));
7534 else if (third_reload_reg
)
7536 gen_reload (third_reload_reg
, real_oldequiv
,
7539 gen_reload (second_reload_reg
, third_reload_reg
,
7544 gen_reload (second_reload_reg
, real_oldequiv
,
7548 oldequiv
= second_reload_reg
;
7553 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7555 rtx real_oldequiv
= oldequiv
;
7557 if ((REG_P (oldequiv
)
7558 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7559 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7560 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7561 || (GET_CODE (oldequiv
) == SUBREG
7562 && REG_P (SUBREG_REG (oldequiv
))
7563 && (REGNO (SUBREG_REG (oldequiv
))
7564 >= FIRST_PSEUDO_REGISTER
)
7565 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7566 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7567 || (CONSTANT_P (oldequiv
)
7568 && (targetm
.preferred_reload_class (oldequiv
,
7569 REGNO_REG_CLASS (REGNO (reloadreg
)))
7571 real_oldequiv
= rl
->in
;
7572 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7576 if (cfun
->can_throw_non_call_exceptions
)
7577 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7579 /* End this sequence. */
7580 *where
= get_insns ();
7583 /* Update reload_override_in so that delete_address_reloads_1
7584 can see the actual register usage. */
7586 reload_override_in
[j
] = oldequiv
;
7589 /* Generate insns to for the output reload RL, which is for the insn described
7590 by CHAIN and has the number J. */
7592 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7596 rtx insn
= chain
->insn
;
7599 enum machine_mode mode
;
7603 if (rl
->when_needed
== RELOAD_OTHER
)
7606 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7608 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7609 mode
= GET_MODE (rl_reg_rtx
);
7611 reloadreg
= rl_reg_rtx
;
7613 /* If we need two reload regs, set RELOADREG to the intermediate
7614 one, since it will be stored into OLD. We might need a secondary
7615 register only for an input reload, so check again here. */
7617 if (rl
->secondary_out_reload
>= 0)
7620 int secondary_reload
= rl
->secondary_out_reload
;
7621 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7623 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7624 && reg_equiv_mem (REGNO (old
)) != 0)
7625 real_old
= reg_equiv_mem (REGNO (old
));
7627 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7629 rtx second_reloadreg
= reloadreg
;
7630 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7632 /* See if RELOADREG is to be used as a scratch register
7633 or as an intermediate register. */
7634 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7636 /* We'd have to add extra code to handle this case. */
7637 gcc_assert (tertiary_reload
< 0);
7639 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7640 (real_old
, second_reloadreg
, reloadreg
)));
7645 /* See if we need both a scratch and intermediate reload
7648 enum insn_code tertiary_icode
7649 = rld
[secondary_reload
].secondary_out_icode
;
7651 /* We'd have to add more code for quartary reloads. */
7652 gcc_assert (tertiary_reload
< 0
7653 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7655 if (GET_MODE (reloadreg
) != mode
)
7656 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7658 if (tertiary_icode
!= CODE_FOR_nothing
)
7660 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7662 /* Copy primary reload reg to secondary reload reg.
7663 (Note that these have been swapped above, then
7664 secondary reload reg to OLD using our insn.) */
7666 /* If REAL_OLD is a paradoxical SUBREG, remove it
7667 and try to put the opposite SUBREG on
7669 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7671 gen_reload (reloadreg
, second_reloadreg
,
7672 rl
->opnum
, rl
->when_needed
);
7673 emit_insn ((GEN_FCN (tertiary_icode
)
7674 (real_old
, reloadreg
, third_reloadreg
)));
7680 /* Copy between the reload regs here and then to
7683 gen_reload (reloadreg
, second_reloadreg
,
7684 rl
->opnum
, rl
->when_needed
);
7685 if (tertiary_reload
>= 0)
7687 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7689 gen_reload (third_reloadreg
, reloadreg
,
7690 rl
->opnum
, rl
->when_needed
);
7691 reloadreg
= third_reloadreg
;
7698 /* Output the last reload insn. */
7703 /* Don't output the last reload if OLD is not the dest of
7704 INSN and is in the src and is clobbered by INSN. */
7705 if (! flag_expensive_optimizations
7707 || !(set
= single_set (insn
))
7708 || rtx_equal_p (old
, SET_DEST (set
))
7709 || !reg_mentioned_p (old
, SET_SRC (set
))
7710 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7711 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7712 gen_reload (old
, reloadreg
, rl
->opnum
,
7716 /* Look at all insns we emitted, just to be safe. */
7717 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7720 rtx pat
= PATTERN (p
);
7722 /* If this output reload doesn't come from a spill reg,
7723 clear any memory of reloaded copies of the pseudo reg.
7724 If this output reload comes from a spill reg,
7725 reg_has_output_reload will make this do nothing. */
7726 note_stores (pat
, forget_old_reloads_1
, NULL
);
7728 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7730 rtx set
= single_set (insn
);
7731 if (reload_spill_index
[j
] < 0
7733 && SET_SRC (set
) == rl_reg_rtx
)
7735 int src
= REGNO (SET_SRC (set
));
7737 reload_spill_index
[j
] = src
;
7738 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7739 if (find_regno_note (insn
, REG_DEAD
, src
))
7740 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7742 if (HARD_REGISTER_P (rl_reg_rtx
))
7744 int s
= rl
->secondary_out_reload
;
7745 set
= single_set (p
);
7746 /* If this reload copies only to the secondary reload
7747 register, the secondary reload does the actual
7749 if (s
>= 0 && set
== NULL_RTX
)
7750 /* We can't tell what function the secondary reload
7751 has and where the actual store to the pseudo is
7752 made; leave new_spill_reg_store alone. */
7755 && SET_SRC (set
) == rl_reg_rtx
7756 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7758 /* Usually the next instruction will be the
7759 secondary reload insn; if we can confirm
7760 that it is, setting new_spill_reg_store to
7761 that insn will allow an extra optimization. */
7762 rtx s_reg
= rld
[s
].reg_rtx
;
7763 rtx next
= NEXT_INSN (p
);
7764 rld
[s
].out
= rl
->out
;
7765 rld
[s
].out_reg
= rl
->out_reg
;
7766 set
= single_set (next
);
7767 if (set
&& SET_SRC (set
) == s_reg
7768 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7770 SET_HARD_REG_BIT (reg_is_output_reload
,
7772 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7775 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7776 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7781 if (rl
->when_needed
== RELOAD_OTHER
)
7783 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7784 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7787 output_reload_insns
[rl
->opnum
] = get_insns ();
7789 if (cfun
->can_throw_non_call_exceptions
)
7790 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7795 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7796 and has the number J. */
7798 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7800 rtx insn
= chain
->insn
;
7801 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7802 ? rl
->in_reg
: rl
->in
);
7803 rtx reg_rtx
= rl
->reg_rtx
;
7807 enum machine_mode mode
;
7809 /* Determine the mode to reload in.
7810 This is very tricky because we have three to choose from.
7811 There is the mode the insn operand wants (rl->inmode).
7812 There is the mode of the reload register RELOADREG.
7813 There is the intrinsic mode of the operand, which we could find
7814 by stripping some SUBREGs.
7815 It turns out that RELOADREG's mode is irrelevant:
7816 we can change that arbitrarily.
7818 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7819 then the reload reg may not support QImode moves, so use SImode.
7820 If foo is in memory due to spilling a pseudo reg, this is safe,
7821 because the QImode value is in the least significant part of a
7822 slot big enough for a SImode. If foo is some other sort of
7823 memory reference, then it is impossible to reload this case,
7824 so previous passes had better make sure this never happens.
7826 Then consider a one-word union which has SImode and one of its
7827 members is a float, being fetched as (SUBREG:SF union:SI).
7828 We must fetch that as SFmode because we could be loading into
7829 a float-only register. In this case OLD's mode is correct.
7831 Consider an immediate integer: it has VOIDmode. Here we need
7832 to get a mode from something else.
7834 In some cases, there is a fourth mode, the operand's
7835 containing mode. If the insn specifies a containing mode for
7836 this operand, it overrides all others.
7838 I am not sure whether the algorithm here is always right,
7839 but it does the right things in those cases. */
7841 mode
= GET_MODE (old
);
7842 if (mode
== VOIDmode
)
7845 /* We cannot use gen_lowpart_common since it can do the wrong thing
7846 when REG_RTX has a multi-word mode. Note that REG_RTX must
7847 always be a REG here. */
7848 if (GET_MODE (reg_rtx
) != mode
)
7849 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7851 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7854 /* AUTO_INC reloads need to be handled even if inherited. We got an
7855 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7856 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7857 && ! rtx_equal_p (reg_rtx
, old
)
7859 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7861 /* When inheriting a wider reload, we have a MEM in rl->in,
7862 e.g. inheriting a SImode output reload for
7863 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7864 if (optimize
&& reload_inherited
[j
] && rl
->in
7866 && MEM_P (rl
->in_reg
)
7867 && reload_spill_index
[j
] >= 0
7868 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7869 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7871 /* If we are reloading a register that was recently stored in with an
7872 output-reload, see if we can prove there was
7873 actually no need to store the old value in it. */
7876 && (reload_inherited
[j
] || reload_override_in
[j
])
7879 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7881 /* There doesn't seem to be any reason to restrict this to pseudos
7882 and doing so loses in the case where we are copying from a
7883 register of the wrong class. */
7884 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7886 /* The insn might have already some references to stackslots
7887 replaced by MEMs, while reload_out_reg still names the
7889 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7890 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7891 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7894 /* Do output reloading for reload RL, which is for the insn described by
7895 CHAIN and has the number J.
7896 ??? At some point we need to support handling output reloads of
7897 JUMP_INSNs or insns that set cc0. */
7899 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7902 rtx insn
= chain
->insn
;
7903 /* If this is an output reload that stores something that is
7904 not loaded in this same reload, see if we can eliminate a previous
7906 rtx pseudo
= rl
->out_reg
;
7907 rtx reg_rtx
= rl
->reg_rtx
;
7909 if (rl
->out
&& reg_rtx
)
7911 enum machine_mode mode
;
7913 /* Determine the mode to reload in.
7914 See comments above (for input reloading). */
7915 mode
= GET_MODE (rl
->out
);
7916 if (mode
== VOIDmode
)
7918 /* VOIDmode should never happen for an output. */
7919 if (asm_noperands (PATTERN (insn
)) < 0)
7920 /* It's the compiler's fault. */
7921 fatal_insn ("VOIDmode on an output", insn
);
7922 error_for_asm (insn
, "output operand is constant in %<asm%>");
7923 /* Prevent crash--use something we know is valid. */
7925 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7927 if (GET_MODE (reg_rtx
) != mode
)
7928 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7930 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7935 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7936 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7937 && reg_last_reload_reg
[REGNO (pseudo
)])
7939 int pseudo_no
= REGNO (pseudo
);
7940 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7942 /* We don't need to test full validity of last_regno for
7943 inherit here; we only want to know if the store actually
7944 matches the pseudo. */
7945 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7946 && reg_reloaded_contents
[last_regno
] == pseudo_no
7947 && spill_reg_store
[last_regno
]
7948 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7949 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7955 || rtx_equal_p (old
, reg_rtx
))
7958 /* An output operand that dies right away does need a reload,
7959 but need not be copied from it. Show the new location in the
7961 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7962 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7964 XEXP (note
, 0) = reg_rtx
;
7967 /* Likewise for a SUBREG of an operand that dies. */
7968 else if (GET_CODE (old
) == SUBREG
7969 && REG_P (SUBREG_REG (old
))
7970 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7973 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7976 else if (GET_CODE (old
) == SCRATCH
)
7977 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7978 but we don't want to make an output reload. */
7981 /* If is a JUMP_INSN, we can't support output reloads yet. */
7982 gcc_assert (NONJUMP_INSN_P (insn
));
7984 emit_output_reload_insns (chain
, rld
+ j
, j
);
7987 /* A reload copies values of MODE from register SRC to register DEST.
7988 Return true if it can be treated for inheritance purposes like a
7989 group of reloads, each one reloading a single hard register. The
7990 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7991 occupy the same number of hard registers. */
7994 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7995 int src ATTRIBUTE_UNUSED
,
7996 enum machine_mode mode ATTRIBUTE_UNUSED
)
7998 #ifdef CANNOT_CHANGE_MODE_CLASS
7999 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8000 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8006 /* Output insns to reload values in and out of the chosen reload regs. */
8009 emit_reload_insns (struct insn_chain
*chain
)
8011 rtx insn
= chain
->insn
;
8015 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8017 for (j
= 0; j
< reload_n_operands
; j
++)
8018 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8019 = inpaddr_address_reload_insns
[j
]
8020 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8021 = outaddr_address_reload_insns
[j
]
8022 = other_output_reload_insns
[j
] = 0;
8023 other_input_address_reload_insns
= 0;
8024 other_input_reload_insns
= 0;
8025 operand_reload_insns
= 0;
8026 other_operand_reload_insns
= 0;
8028 /* Dump reloads into the dump file. */
8031 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8032 debug_reload_to_stream (dump_file
);
8035 for (j
= 0; j
< n_reloads
; j
++)
8036 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8040 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8041 new_spill_reg_store
[i
] = 0;
8044 /* Now output the instructions to copy the data into and out of the
8045 reload registers. Do these in the order that the reloads were reported,
8046 since reloads of base and index registers precede reloads of operands
8047 and the operands may need the base and index registers reloaded. */
8049 for (j
= 0; j
< n_reloads
; j
++)
8051 do_input_reload (chain
, rld
+ j
, j
);
8052 do_output_reload (chain
, rld
+ j
, j
);
8055 /* Now write all the insns we made for reloads in the order expected by
8056 the allocation functions. Prior to the insn being reloaded, we write
8057 the following reloads:
8059 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8061 RELOAD_OTHER reloads.
8063 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8064 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8065 RELOAD_FOR_INPUT reload for the operand.
8067 RELOAD_FOR_OPADDR_ADDRS reloads.
8069 RELOAD_FOR_OPERAND_ADDRESS reloads.
8071 After the insn being reloaded, we write the following:
8073 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8074 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8075 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8076 reloads for the operand. The RELOAD_OTHER output reloads are
8077 output in descending order by reload number. */
8079 emit_insn_before (other_input_address_reload_insns
, insn
);
8080 emit_insn_before (other_input_reload_insns
, insn
);
8082 for (j
= 0; j
< reload_n_operands
; j
++)
8084 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8085 emit_insn_before (input_address_reload_insns
[j
], insn
);
8086 emit_insn_before (input_reload_insns
[j
], insn
);
8089 emit_insn_before (other_operand_reload_insns
, insn
);
8090 emit_insn_before (operand_reload_insns
, insn
);
8092 for (j
= 0; j
< reload_n_operands
; j
++)
8094 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8095 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8096 x
= emit_insn_after (output_reload_insns
[j
], x
);
8097 emit_insn_after (other_output_reload_insns
[j
], x
);
8100 /* For all the spill regs newly reloaded in this instruction,
8101 record what they were reloaded from, so subsequent instructions
8102 can inherit the reloads.
8104 Update spill_reg_store for the reloads of this insn.
8105 Copy the elements that were updated in the loop above. */
8107 for (j
= 0; j
< n_reloads
; j
++)
8109 int r
= reload_order
[j
];
8110 int i
= reload_spill_index
[r
];
8112 /* If this is a non-inherited input reload from a pseudo, we must
8113 clear any memory of a previous store to the same pseudo. Only do
8114 something if there will not be an output reload for the pseudo
8116 if (rld
[r
].in_reg
!= 0
8117 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8119 rtx reg
= rld
[r
].in_reg
;
8121 if (GET_CODE (reg
) == SUBREG
)
8122 reg
= SUBREG_REG (reg
);
8125 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8126 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8128 int nregno
= REGNO (reg
);
8130 if (reg_last_reload_reg
[nregno
])
8132 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8134 if (reg_reloaded_contents
[last_regno
] == nregno
)
8135 spill_reg_store
[last_regno
] = 0;
8140 /* I is nonneg if this reload used a register.
8141 If rld[r].reg_rtx is 0, this is an optional reload
8142 that we opted to ignore. */
8144 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8146 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8149 /* For a multi register reload, we need to check if all or part
8150 of the value lives to the end. */
8151 for (k
= 0; k
< nr
; k
++)
8152 if (reload_reg_reaches_end_p (i
+ k
, r
))
8153 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8155 /* Maybe the spill reg contains a copy of reload_out. */
8157 && (REG_P (rld
[r
].out
)
8159 ? REG_P (rld
[r
].out_reg
)
8160 /* The reload value is an auto-modification of
8161 some kind. For PRE_INC, POST_INC, PRE_DEC
8162 and POST_DEC, we record an equivalence
8163 between the reload register and the operand
8164 on the optimistic assumption that we can make
8165 the equivalence hold. reload_as_needed must
8166 then either make it hold or invalidate the
8169 PRE_MODIFY and POST_MODIFY addresses are reloaded
8170 somewhat differently, and allowing them here leads
8172 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8173 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8177 reg
= reload_reg_rtx_for_output
[r
];
8178 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8180 enum machine_mode mode
= GET_MODE (reg
);
8181 int regno
= REGNO (reg
);
8182 int nregs
= hard_regno_nregs
[regno
][mode
];
8183 rtx out
= (REG_P (rld
[r
].out
)
8187 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8188 int out_regno
= REGNO (out
);
8189 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8190 : hard_regno_nregs
[out_regno
][mode
]);
8193 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8194 spill_reg_stored_to
[regno
] = out
;
8195 reg_last_reload_reg
[out_regno
] = reg
;
8197 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8198 && nregs
== out_nregs
8199 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8201 /* If OUT_REGNO is a hard register, it may occupy more than
8202 one register. If it does, say what is in the
8203 rest of the registers assuming that both registers
8204 agree on how many words the object takes. If not,
8205 invalidate the subsequent registers. */
8207 if (HARD_REGISTER_NUM_P (out_regno
))
8208 for (k
= 1; k
< out_nregs
; k
++)
8209 reg_last_reload_reg
[out_regno
+ k
]
8210 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8212 /* Now do the inverse operation. */
8213 for (k
= 0; k
< nregs
; k
++)
8215 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8216 reg_reloaded_contents
[regno
+ k
]
8217 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8220 reg_reloaded_insn
[regno
+ k
] = insn
;
8221 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8222 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8223 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8226 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8231 /* Maybe the spill reg contains a copy of reload_in. Only do
8232 something if there will not be an output reload for
8233 the register being reloaded. */
8234 else if (rld
[r
].out_reg
== 0
8236 && ((REG_P (rld
[r
].in
)
8237 && !HARD_REGISTER_P (rld
[r
].in
)
8238 && !REGNO_REG_SET_P (®_has_output_reload
,
8240 || (REG_P (rld
[r
].in_reg
)
8241 && !REGNO_REG_SET_P (®_has_output_reload
,
8242 REGNO (rld
[r
].in_reg
))))
8243 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8247 reg
= reload_reg_rtx_for_input
[r
];
8248 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8250 enum machine_mode mode
;
8258 mode
= GET_MODE (reg
);
8259 regno
= REGNO (reg
);
8260 nregs
= hard_regno_nregs
[regno
][mode
];
8261 if (REG_P (rld
[r
].in
)
8262 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8264 else if (REG_P (rld
[r
].in_reg
))
8267 in
= XEXP (rld
[r
].in_reg
, 0);
8268 in_regno
= REGNO (in
);
8270 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8271 : hard_regno_nregs
[in_regno
][mode
]);
8273 reg_last_reload_reg
[in_regno
] = reg
;
8275 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8276 && nregs
== in_nregs
8277 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8279 if (HARD_REGISTER_NUM_P (in_regno
))
8280 for (k
= 1; k
< in_nregs
; k
++)
8281 reg_last_reload_reg
[in_regno
+ k
]
8282 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8284 /* Unless we inherited this reload, show we haven't
8285 recently done a store.
8286 Previous stores of inherited auto_inc expressions
8287 also have to be discarded. */
8288 if (! reload_inherited
[r
]
8289 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8290 spill_reg_store
[regno
] = 0;
8292 for (k
= 0; k
< nregs
; k
++)
8294 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8295 reg_reloaded_contents
[regno
+ k
]
8296 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8299 reg_reloaded_insn
[regno
+ k
] = insn
;
8300 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8301 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8302 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8305 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8312 /* The following if-statement was #if 0'd in 1.34 (or before...).
8313 It's reenabled in 1.35 because supposedly nothing else
8314 deals with this problem. */
8316 /* If a register gets output-reloaded from a non-spill register,
8317 that invalidates any previous reloaded copy of it.
8318 But forget_old_reloads_1 won't get to see it, because
8319 it thinks only about the original insn. So invalidate it here.
8320 Also do the same thing for RELOAD_OTHER constraints where the
8321 output is discarded. */
8323 && ((rld
[r
].out
!= 0
8324 && (REG_P (rld
[r
].out
)
8325 || (MEM_P (rld
[r
].out
)
8326 && REG_P (rld
[r
].out_reg
))))
8327 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8328 && REG_P (rld
[r
].out_reg
))))
8330 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8331 ? rld
[r
].out
: rld
[r
].out_reg
);
8332 int out_regno
= REGNO (out
);
8333 enum machine_mode mode
= GET_MODE (out
);
8335 /* REG_RTX is now set or clobbered by the main instruction.
8336 As the comment above explains, forget_old_reloads_1 only
8337 sees the original instruction, and there is no guarantee
8338 that the original instruction also clobbered REG_RTX.
8339 For example, if find_reloads sees that the input side of
8340 a matched operand pair dies in this instruction, it may
8341 use the input register as the reload register.
8343 Calling forget_old_reloads_1 is a waste of effort if
8344 REG_RTX is also the output register.
8346 If we know that REG_RTX holds the value of a pseudo
8347 register, the code after the call will record that fact. */
8348 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8349 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8351 if (!HARD_REGISTER_NUM_P (out_regno
))
8353 rtx src_reg
, store_insn
= NULL_RTX
;
8355 reg_last_reload_reg
[out_regno
] = 0;
8357 /* If we can find a hard register that is stored, record
8358 the storing insn so that we may delete this insn with
8359 delete_output_reload. */
8360 src_reg
= reload_reg_rtx_for_output
[r
];
8364 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8365 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8371 /* If this is an optional reload, try to find the
8372 source reg from an input reload. */
8373 rtx set
= single_set (insn
);
8374 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8378 src_reg
= SET_SRC (set
);
8380 for (k
= 0; k
< n_reloads
; k
++)
8382 if (rld
[k
].in
== src_reg
)
8384 src_reg
= reload_reg_rtx_for_input
[k
];
8390 if (src_reg
&& REG_P (src_reg
)
8391 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8393 int src_regno
, src_nregs
, k
;
8396 gcc_assert (GET_MODE (src_reg
) == mode
);
8397 src_regno
= REGNO (src_reg
);
8398 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8399 /* The place where to find a death note varies with
8400 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8401 necessarily checked exactly in the code that moves
8402 notes, so just check both locations. */
8403 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8404 if (! note
&& store_insn
)
8405 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8406 for (k
= 0; k
< src_nregs
; k
++)
8408 spill_reg_store
[src_regno
+ k
] = store_insn
;
8409 spill_reg_stored_to
[src_regno
+ k
] = out
;
8410 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8411 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8412 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8413 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8414 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8416 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8419 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8421 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8423 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8425 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8427 reg_last_reload_reg
[out_regno
] = src_reg
;
8428 /* We have to set reg_has_output_reload here, or else
8429 forget_old_reloads_1 will clear reg_last_reload_reg
8431 SET_REGNO_REG_SET (®_has_output_reload
,
8437 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8439 for (k
= 0; k
< out_nregs
; k
++)
8440 reg_last_reload_reg
[out_regno
+ k
] = 0;
8444 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8447 /* Go through the motions to emit INSN and test if it is strictly valid.
8448 Return the emitted insn if valid, else return NULL. */
8451 emit_insn_if_valid_for_reload (rtx insn
)
8453 rtx last
= get_last_insn ();
8456 insn
= emit_insn (insn
);
8457 code
= recog_memoized (insn
);
8461 extract_insn (insn
);
8462 /* We want constrain operands to treat this insn strictly in its
8463 validity determination, i.e., the way it would after reload has
8465 if (constrain_operands (1))
8469 delete_insns_since (last
);
8473 #ifdef SECONDARY_MEMORY_NEEDED
8474 /* If X is not a subreg, return it unmodified. If it is a subreg,
8475 look up whether we made a replacement for the SUBREG_REG. Return
8476 either the replacement or the SUBREG_REG. */
8479 replaced_subreg (rtx x
)
8481 if (GET_CODE (x
) == SUBREG
)
8482 return find_replacement (&SUBREG_REG (x
));
8487 /* Emit code to perform a reload from IN (which may be a reload register) to
8488 OUT (which may also be a reload register). IN or OUT is from operand
8489 OPNUM with reload type TYPE.
8491 Returns first insn emitted. */
8494 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8496 rtx last
= get_last_insn ();
8498 #ifdef SECONDARY_MEMORY_NEEDED
8502 /* If IN is a paradoxical SUBREG, remove it and try to put the
8503 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8504 if (!strip_paradoxical_subreg (&in
, &out
))
8505 strip_paradoxical_subreg (&out
, &in
);
8507 /* How to do this reload can get quite tricky. Normally, we are being
8508 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8509 register that didn't get a hard register. In that case we can just
8510 call emit_move_insn.
8512 We can also be asked to reload a PLUS that adds a register or a MEM to
8513 another register, constant or MEM. This can occur during frame pointer
8514 elimination and while reloading addresses. This case is handled by
8515 trying to emit a single insn to perform the add. If it is not valid,
8516 we use a two insn sequence.
8518 Or we can be asked to reload an unary operand that was a fragment of
8519 an addressing mode, into a register. If it isn't recognized as-is,
8520 we try making the unop operand and the reload-register the same:
8521 (set reg:X (unop:X expr:Y))
8522 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8524 Finally, we could be called to handle an 'o' constraint by putting
8525 an address into a register. In that case, we first try to do this
8526 with a named pattern of "reload_load_address". If no such pattern
8527 exists, we just emit a SET insn and hope for the best (it will normally
8528 be valid on machines that use 'o').
8530 This entire process is made complex because reload will never
8531 process the insns we generate here and so we must ensure that
8532 they will fit their constraints and also by the fact that parts of
8533 IN might be being reloaded separately and replaced with spill registers.
8534 Because of this, we are, in some sense, just guessing the right approach
8535 here. The one listed above seems to work.
8537 ??? At some point, this whole thing needs to be rethought. */
8539 if (GET_CODE (in
) == PLUS
8540 && (REG_P (XEXP (in
, 0))
8541 || GET_CODE (XEXP (in
, 0)) == SUBREG
8542 || MEM_P (XEXP (in
, 0)))
8543 && (REG_P (XEXP (in
, 1))
8544 || GET_CODE (XEXP (in
, 1)) == SUBREG
8545 || CONSTANT_P (XEXP (in
, 1))
8546 || MEM_P (XEXP (in
, 1))))
8548 /* We need to compute the sum of a register or a MEM and another
8549 register, constant, or MEM, and put it into the reload
8550 register. The best possible way of doing this is if the machine
8551 has a three-operand ADD insn that accepts the required operands.
8553 The simplest approach is to try to generate such an insn and see if it
8554 is recognized and matches its constraints. If so, it can be used.
8556 It might be better not to actually emit the insn unless it is valid,
8557 but we need to pass the insn as an operand to `recog' and
8558 `extract_insn' and it is simpler to emit and then delete the insn if
8559 not valid than to dummy things up. */
8561 rtx op0
, op1
, tem
, insn
;
8562 enum insn_code code
;
8564 op0
= find_replacement (&XEXP (in
, 0));
8565 op1
= find_replacement (&XEXP (in
, 1));
8567 /* Since constraint checking is strict, commutativity won't be
8568 checked, so we need to do that here to avoid spurious failure
8569 if the add instruction is two-address and the second operand
8570 of the add is the same as the reload reg, which is frequently
8571 the case. If the insn would be A = B + A, rearrange it so
8572 it will be A = A + B as constrain_operands expects. */
8574 if (REG_P (XEXP (in
, 1))
8575 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8576 tem
= op0
, op0
= op1
, op1
= tem
;
8578 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8579 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8581 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8585 /* If that failed, we must use a conservative two-insn sequence.
8587 Use a move to copy one operand into the reload register. Prefer
8588 to reload a constant, MEM or pseudo since the move patterns can
8589 handle an arbitrary operand. If OP1 is not a constant, MEM or
8590 pseudo and OP1 is not a valid operand for an add instruction, then
8593 After reloading one of the operands into the reload register, add
8594 the reload register to the output register.
8596 If there is another way to do this for a specific machine, a
8597 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8600 code
= optab_handler (add_optab
, GET_MODE (out
));
8602 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8604 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8605 || (code
!= CODE_FOR_nothing
8606 && !insn_operand_matches (code
, 2, op1
)))
8607 tem
= op0
, op0
= op1
, op1
= tem
;
8609 gen_reload (out
, op0
, opnum
, type
);
8611 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8612 This fixes a problem on the 32K where the stack pointer cannot
8613 be used as an operand of an add insn. */
8615 if (rtx_equal_p (op0
, op1
))
8618 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8621 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8622 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8626 /* If that failed, copy the address register to the reload register.
8627 Then add the constant to the reload register. */
8629 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8630 gen_reload (out
, op1
, opnum
, type
);
8631 insn
= emit_insn (gen_add2_insn (out
, op0
));
8632 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8635 #ifdef SECONDARY_MEMORY_NEEDED
8636 /* If we need a memory location to do the move, do it that way. */
8637 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8638 (REG_P (tem1
) && REG_P (tem2
)))
8639 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8640 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8641 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8642 REGNO_REG_CLASS (REGNO (tem2
)),
8645 /* Get the memory to use and rewrite both registers to its mode. */
8646 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8648 if (GET_MODE (loc
) != GET_MODE (out
))
8649 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8651 if (GET_MODE (loc
) != GET_MODE (in
))
8652 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8654 gen_reload (loc
, in
, opnum
, type
);
8655 gen_reload (out
, loc
, opnum
, type
);
8658 else if (REG_P (out
) && UNARY_P (in
))
8665 op1
= find_replacement (&XEXP (in
, 0));
8666 if (op1
!= XEXP (in
, 0))
8667 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8669 /* First, try a plain SET. */
8670 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8674 /* If that failed, move the inner operand to the reload
8675 register, and try the same unop with the inner expression
8676 replaced with the reload register. */
8678 if (GET_MODE (op1
) != GET_MODE (out
))
8679 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8683 gen_reload (out_moded
, op1
, opnum
, type
);
8686 = gen_rtx_SET (VOIDmode
, out
,
8687 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8689 insn
= emit_insn_if_valid_for_reload (insn
);
8692 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8696 fatal_insn ("failure trying to reload:", set
);
8698 /* If IN is a simple operand, use gen_move_insn. */
8699 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8701 tem
= emit_insn (gen_move_insn (out
, in
));
8702 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8703 mark_jump_label (in
, tem
, 0);
8706 #ifdef HAVE_reload_load_address
8707 else if (HAVE_reload_load_address
)
8708 emit_insn (gen_reload_load_address (out
, in
));
8711 /* Otherwise, just write (set OUT IN) and hope for the best. */
8713 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8715 /* Return the first insn emitted.
8716 We can not just return get_last_insn, because there may have
8717 been multiple instructions emitted. Also note that gen_move_insn may
8718 emit more than one insn itself, so we can not assume that there is one
8719 insn emitted per emit_insn_before call. */
8721 return last
? NEXT_INSN (last
) : get_insns ();
8724 /* Delete a previously made output-reload whose result we now believe
8725 is not needed. First we double-check.
8727 INSN is the insn now being processed.
8728 LAST_RELOAD_REG is the hard register number for which we want to delete
8729 the last output reload.
8730 J is the reload-number that originally used REG. The caller has made
8731 certain that reload J doesn't use REG any longer for input.
8732 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8735 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8737 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8738 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8741 int n_inherited
= 0;
8747 /* It is possible that this reload has been only used to set another reload
8748 we eliminated earlier and thus deleted this instruction too. */
8749 if (INSN_DELETED_P (output_reload_insn
))
8752 /* Get the raw pseudo-register referred to. */
8754 while (GET_CODE (reg
) == SUBREG
)
8755 reg
= SUBREG_REG (reg
);
8756 substed
= reg_equiv_memory_loc (REGNO (reg
));
8758 /* This is unsafe if the operand occurs more often in the current
8759 insn than it is inherited. */
8760 for (k
= n_reloads
- 1; k
>= 0; k
--)
8762 rtx reg2
= rld
[k
].in
;
8765 if (MEM_P (reg2
) || reload_override_in
[k
])
8766 reg2
= rld
[k
].in_reg
;
8768 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8769 reg2
= XEXP (rld
[k
].in_reg
, 0);
8771 while (GET_CODE (reg2
) == SUBREG
)
8772 reg2
= SUBREG_REG (reg2
);
8773 if (rtx_equal_p (reg2
, reg
))
8775 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8781 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8782 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8783 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8786 n_occurrences
+= count_occurrences (PATTERN (insn
),
8787 eliminate_regs (substed
, VOIDmode
,
8789 for (i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8791 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8792 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8794 if (n_occurrences
> n_inherited
)
8797 regno
= REGNO (reg
);
8798 if (regno
>= FIRST_PSEUDO_REGISTER
)
8801 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8803 /* If the pseudo-reg we are reloading is no longer referenced
8804 anywhere between the store into it and here,
8805 and we're within the same basic block, then the value can only
8806 pass through the reload reg and end up here.
8807 Otherwise, give up--return. */
8808 for (i1
= NEXT_INSN (output_reload_insn
);
8809 i1
!= insn
; i1
= NEXT_INSN (i1
))
8811 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8813 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8814 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8816 /* If this is USE in front of INSN, we only have to check that
8817 there are no more references than accounted for by inheritance. */
8818 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8820 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8821 i1
= NEXT_INSN (i1
);
8823 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8829 /* We will be deleting the insn. Remove the spill reg information. */
8830 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8832 spill_reg_store
[last_reload_reg
+ k
] = 0;
8833 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8836 /* The caller has already checked that REG dies or is set in INSN.
8837 It has also checked that we are optimizing, and thus some
8838 inaccuracies in the debugging information are acceptable.
8839 So we could just delete output_reload_insn. But in some cases
8840 we can improve the debugging information without sacrificing
8841 optimization - maybe even improving the code: See if the pseudo
8842 reg has been completely replaced with reload regs. If so, delete
8843 the store insn and forget we had a stack slot for the pseudo. */
8844 if (rld
[j
].out
!= rld
[j
].in
8845 && REG_N_DEATHS (REGNO (reg
)) == 1
8846 && REG_N_SETS (REGNO (reg
)) == 1
8847 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8848 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8852 /* We know that it was used only between here and the beginning of
8853 the current basic block. (We also know that the last use before
8854 INSN was the output reload we are thinking of deleting, but never
8855 mind that.) Search that range; see if any ref remains. */
8856 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8858 rtx set
= single_set (i2
);
8860 /* Uses which just store in the pseudo don't count,
8861 since if they are the only uses, they are dead. */
8862 if (set
!= 0 && SET_DEST (set
) == reg
)
8867 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8868 && reg_mentioned_p (reg
, PATTERN (i2
)))
8870 /* Some other ref remains; just delete the output reload we
8872 delete_address_reloads (output_reload_insn
, insn
);
8873 delete_insn (output_reload_insn
);
8878 /* Delete the now-dead stores into this pseudo. Note that this
8879 loop also takes care of deleting output_reload_insn. */
8880 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8882 rtx set
= single_set (i2
);
8884 if (set
!= 0 && SET_DEST (set
) == reg
)
8886 delete_address_reloads (i2
, insn
);
8894 /* For the debugging info, say the pseudo lives in this reload reg. */
8895 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8896 if (ira_conflicts_p
)
8897 /* Inform IRA about the change. */
8898 ira_mark_allocation_change (REGNO (reg
));
8899 alter_reg (REGNO (reg
), -1, false);
8903 delete_address_reloads (output_reload_insn
, insn
);
8904 delete_insn (output_reload_insn
);
8908 /* We are going to delete DEAD_INSN. Recursively delete loads of
8909 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8910 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8912 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8914 rtx set
= single_set (dead_insn
);
8915 rtx set2
, dst
, prev
, next
;
8918 rtx dst
= SET_DEST (set
);
8920 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8922 /* If we deleted the store from a reloaded post_{in,de}c expression,
8923 we can delete the matching adds. */
8924 prev
= PREV_INSN (dead_insn
);
8925 next
= NEXT_INSN (dead_insn
);
8926 if (! prev
|| ! next
)
8928 set
= single_set (next
);
8929 set2
= single_set (prev
);
8931 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8932 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8933 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8935 dst
= SET_DEST (set
);
8936 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8937 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8938 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8939 || (INTVAL (XEXP (SET_SRC (set
), 1))
8940 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8942 delete_related_insns (prev
);
8943 delete_related_insns (next
);
8946 /* Subfunction of delete_address_reloads: process registers found in X. */
8948 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8950 rtx prev
, set
, dst
, i2
;
8952 enum rtx_code code
= GET_CODE (x
);
8956 const char *fmt
= GET_RTX_FORMAT (code
);
8957 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8960 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8961 else if (fmt
[i
] == 'E')
8963 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8964 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8971 if (spill_reg_order
[REGNO (x
)] < 0)
8974 /* Scan backwards for the insn that sets x. This might be a way back due
8976 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8978 code
= GET_CODE (prev
);
8979 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8983 if (reg_set_p (x
, PATTERN (prev
)))
8985 if (reg_referenced_p (x
, PATTERN (prev
)))
8988 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8990 /* Check that PREV only sets the reload register. */
8991 set
= single_set (prev
);
8994 dst
= SET_DEST (set
);
8996 || ! rtx_equal_p (dst
, x
))
8998 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9000 /* Check if DST was used in a later insn -
9001 it might have been inherited. */
9002 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9008 if (reg_referenced_p (dst
, PATTERN (i2
)))
9010 /* If there is a reference to the register in the current insn,
9011 it might be loaded in a non-inherited reload. If no other
9012 reload uses it, that means the register is set before
9014 if (i2
== current_insn
)
9016 for (j
= n_reloads
- 1; j
>= 0; j
--)
9017 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9018 || reload_override_in
[j
] == dst
)
9020 for (j
= n_reloads
- 1; j
>= 0; j
--)
9021 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9030 /* If DST is still live at CURRENT_INSN, check if it is used for
9031 any reload. Note that even if CURRENT_INSN sets DST, we still
9032 have to check the reloads. */
9033 if (i2
== current_insn
)
9035 for (j
= n_reloads
- 1; j
>= 0; j
--)
9036 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9037 || reload_override_in
[j
] == dst
)
9039 /* ??? We can't finish the loop here, because dst might be
9040 allocated to a pseudo in this block if no reload in this
9041 block needs any of the classes containing DST - see
9042 spill_hard_reg. There is no easy way to tell this, so we
9043 have to scan till the end of the basic block. */
9045 if (reg_set_p (dst
, PATTERN (i2
)))
9049 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9050 reg_reloaded_contents
[REGNO (dst
)] = -1;
9054 /* Output reload-insns to reload VALUE into RELOADREG.
9055 VALUE is an autoincrement or autodecrement RTX whose operand
9056 is a register or memory location;
9057 so reloading involves incrementing that location.
9058 IN is either identical to VALUE, or some cheaper place to reload from.
9060 INC_AMOUNT is the number to increment or decrement by (always positive).
9061 This cannot be deduced from VALUE. */
9064 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9066 /* REG or MEM to be copied and incremented. */
9067 rtx incloc
= find_replacement (&XEXP (value
, 0));
9068 /* Nonzero if increment after copying. */
9069 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9070 || GET_CODE (value
) == POST_MODIFY
);
9075 rtx real_in
= in
== value
? incloc
: in
;
9077 /* No hard register is equivalent to this register after
9078 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9079 we could inc/dec that register as well (maybe even using it for
9080 the source), but I'm not sure it's worth worrying about. */
9082 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9084 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9086 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9087 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9091 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9092 inc_amount
= -inc_amount
;
9094 inc
= GEN_INT (inc_amount
);
9097 /* If this is post-increment, first copy the location to the reload reg. */
9098 if (post
&& real_in
!= reloadreg
)
9099 emit_insn (gen_move_insn (reloadreg
, real_in
));
9103 /* See if we can directly increment INCLOC. Use a method similar to
9104 that in gen_reload. */
9106 last
= get_last_insn ();
9107 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9108 gen_rtx_PLUS (GET_MODE (incloc
),
9111 code
= recog_memoized (add_insn
);
9114 extract_insn (add_insn
);
9115 if (constrain_operands (1))
9117 /* If this is a pre-increment and we have incremented the value
9118 where it lives, copy the incremented value to RELOADREG to
9119 be used as an address. */
9122 emit_insn (gen_move_insn (reloadreg
, incloc
));
9126 delete_insns_since (last
);
9129 /* If couldn't do the increment directly, must increment in RELOADREG.
9130 The way we do this depends on whether this is pre- or post-increment.
9131 For pre-increment, copy INCLOC to the reload register, increment it
9132 there, then save back. */
9136 if (in
!= reloadreg
)
9137 emit_insn (gen_move_insn (reloadreg
, real_in
));
9138 emit_insn (gen_add2_insn (reloadreg
, inc
));
9139 emit_insn (gen_move_insn (incloc
, reloadreg
));
9144 Because this might be a jump insn or a compare, and because RELOADREG
9145 may not be available after the insn in an input reload, we must do
9146 the incrementation before the insn being reloaded for.
9148 We have already copied IN to RELOADREG. Increment the copy in
9149 RELOADREG, save that back, then decrement RELOADREG so it has
9150 the original value. */
9152 emit_insn (gen_add2_insn (reloadreg
, inc
));
9153 emit_insn (gen_move_insn (incloc
, reloadreg
));
9154 if (CONST_INT_P (inc
))
9155 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
9157 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9163 add_auto_inc_notes (rtx insn
, rtx x
)
9165 enum rtx_code code
= GET_CODE (x
);
9169 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9171 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9175 /* Scan all the operand sub-expressions. */
9176 fmt
= GET_RTX_FORMAT (code
);
9177 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9180 add_auto_inc_notes (insn
, XEXP (x
, i
));
9181 else if (fmt
[i
] == 'E')
9182 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9183 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));