gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003-2017 Free Software Foundation, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* Driver configuration.  */
  22
  23 /* A generic LIB_SPEC with -leval and --*group tacked on.  */
  24 #undef  LIB_SPEC
  25 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  26
  27 #undef STARTFILE_SPEC
  28 #undef ENDFILE_SPEC
  29
  30 #undef  LINK_SPEC
  31 #define LINK_SPEC "%{h*} %{v:-V} \
  32                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  33
  34 \f
  35 /* Run-time target specifications.  */
  36
  37 #define TARGET_CPU_CPP_BUILTINS()               \
  38   do                                            \
  39     {                                           \
  40       builtin_define ("__iq2000__");            \
  41       builtin_assert ("cpu=iq2000");            \
  42       builtin_assert ("machine=iq2000");        \
  43     }                                           \
  44   while (0)
  45
  46 /* Macros used in the machine description to test the flags.  */
  47
  48 #define TARGET_STATS            0
  49
  50 #define TARGET_DEBUG_MODE       0
  51 #define TARGET_DEBUG_A_MODE     0
  52 #define TARGET_DEBUG_B_MODE     0
  53 #define TARGET_DEBUG_C_MODE     0
  54 #define TARGET_DEBUG_D_MODE     0
  55
  56 #ifndef IQ2000_ISA_DEFAULT
  57 #define IQ2000_ISA_DEFAULT 1
  58 #endif
  59 \f
  60 /* Storage Layout.  */
  61
  62 #define BITS_BIG_ENDIAN                 0
  63 #define BYTES_BIG_ENDIAN                1
  64 #define WORDS_BIG_ENDIAN                1
  65 #define BITS_PER_WORD                   32
  66 #define MAX_BITS_PER_WORD               64
  67 #define UNITS_PER_WORD                  4
  68 #define MIN_UNITS_PER_WORD              4
  69 #define POINTER_SIZE                    32
  70
  71 /* Define this macro if it is advisable to hold scalars in registers
  72    in a wider mode than that declared by the program.  In such cases,
  73    the value is constrained to be within the bounds of the declared
  74    type, but kept valid in the wider mode.  The signedness of the
  75    extension may differ from that of the type.
  76
  77    We promote any value smaller than SImode up to SImode.  */
  78
  79 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  80   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  81       && GET_MODE_SIZE (MODE) < 4)              \
  82     (MODE) = SImode;
  83
  84 #define PARM_BOUNDARY 32
  85
  86 #define STACK_BOUNDARY 64
  87
  88 #define FUNCTION_BOUNDARY 32
  89
  90 #define BIGGEST_ALIGNMENT 64
  91
  92 #undef  DATA_ALIGNMENT
  93 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
  94   ((((ALIGN) < BITS_PER_WORD)                                           \
  95     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
  96         || TREE_CODE (TYPE) == UNION_TYPE                               \
  97         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
  98
  99 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 100   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 101    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 102
 103 #define EMPTY_FIELD_BOUNDARY 32
 104
 105 #define STRUCTURE_SIZE_BOUNDARY 8
 106
 107 #define STRICT_ALIGNMENT 1
 108
 109 #define PCC_BITFIELD_TYPE_MATTERS 1
 110
 111 \f
 112 /* Layout of Source Language Data Types.  */
 113
 114 #define INT_TYPE_SIZE           32
 115 #define SHORT_TYPE_SIZE         16
 116 #define LONG_TYPE_SIZE          32
 117 #define LONG_LONG_TYPE_SIZE     64
 118 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 119 #define FLOAT_TYPE_SIZE         32
 120 #define DOUBLE_TYPE_SIZE        64
 121 #define LONG_DOUBLE_TYPE_SIZE   64
 122 #define DEFAULT_SIGNED_CHAR     1
 123
 124 #undef  SIZE_TYPE
 125 #define SIZE_TYPE "unsigned int"
 126
 127 #undef  PTRDIFF_TYPE
 128 #define PTRDIFF_TYPE "int"
 129
 130 #undef  WCHAR_TYPE
 131 #define WCHAR_TYPE "long int"
 132
 133 #undef  WCHAR_TYPE_SIZE
 134 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 135
 136 \f
 137 /* Register Basics.  */
 138
 139 /* On the IQ2000, we have 32 integer registers.  */
 140 #define FIRST_PSEUDO_REGISTER 33
 141
 142 #define FIXED_REGISTERS                                                 \
 143 {                                                                       \
 144   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 145   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 146 }
 147
 148 #define CALL_USED_REGISTERS                                             \
 149 {                                                                       \
 150   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 151   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 152 }
 153
 154 \f
 155 /* Order of allocation of registers.  */
 156
 157 #define REG_ALLOC_ORDER                                                 \
 158 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 159   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 160 }
 161
 162 \f
 163 /* How Values Fit in Registers.  */
 164
 165 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 166   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 167
 168 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 169   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 170     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 171    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 172        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 173
 174 #define AVOID_CCMODE_COPIES
 175
 176 \f
 177 /* Register Classes.  */
 178
 179 enum reg_class
 180 {
 181   NO_REGS,                      /* No registers in set.  */
 182   GR_REGS,                      /* Integer registers.  */
 183   ALL_REGS,                     /* All registers.  */
 184   LIM_REG_CLASSES               /* Max value + 1.  */
 185 };
 186
 187 #define GENERAL_REGS GR_REGS
 188
 189 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 190
 191 #define REG_CLASS_NAMES                                         \
 192 {                                                               \
 193   "NO_REGS",                                                    \
 194   "GR_REGS",                                                    \
 195   "ALL_REGS"                                                    \
 196 }
 197
 198 #define REG_CLASS_CONTENTS                                      \
 199 {                                                               \
 200   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 201   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 202   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 203 }
 204
 205 #define REGNO_REG_CLASS(REGNO) \
 206 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 207
 208 #define BASE_REG_CLASS  (GR_REGS)
 209
 210 #define INDEX_REG_CLASS NO_REGS
 211
 212 #define REGNO_OK_FOR_INDEX_P(regno)     0
 213
 214 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 215   ((CLASS) != ALL_REGS                                          \
 216    ? (CLASS)                                                    \
 217    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 218        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 219       ? (GR_REGS)                                               \
 220       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 221           || GET_MODE (X) == VOIDmode)                          \
 222          ? (GR_REGS)                                            \
 223          : (CLASS))))
 224
 225 \f
 226 /* Basic Stack Layout.  */
 227
 228 #define STACK_GROWS_DOWNWARD 1
 229
 230 #define FRAME_GROWS_DOWNWARD 0
 231
 232 #define STARTING_FRAME_OFFSET                                           \
 233   (crtl->outgoing_args_size)
 234
 235 /* Use the default value zero.  */
 236 /* #define STACK_POINTER_OFFSET 0 */
 237
 238 #define FIRST_PARM_OFFSET(FNDECL) 0
 239
 240 /* The return address for the current frame is in r31 if this is a leaf
 241    function.  Otherwise, it is on the stack.  It is at a variable offset
 242    from sp/fp/ap, so we define a fake hard register rap which is a
 243    pointer to the return address on the stack.  This always gets eliminated
 244    during reload to be either the frame pointer or the stack pointer plus
 245    an offset.  */
 246
 247 #define RETURN_ADDR_RTX(count, frame)                                   \
 248   (((count) == 0)                                                       \
 249    ? (leaf_function_p ()                                                \
 250       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 251       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 252                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 253     : (rtx) 0)
 254
 255 /* Before the prologue, RA lives in r31.  */
 256 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, GP_REG_FIRST + 31)
 257
 258 \f
 259 /* Register That Address the Stack Frame.  */
 260
 261 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 262 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 263 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 264 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 265 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 266 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 267
 268 \f
 269 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 270
 271 #define ELIMINABLE_REGS                                                 \
 272 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 273  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 274  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 275  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 276  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 277  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 278  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 279
 280 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 281         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 282 \f
 283 /* Passing Function Arguments on the Stack.  */
 284
 285 /* #define PUSH_ROUNDING(BYTES) 0 */
 286
 287 #define ACCUMULATE_OUTGOING_ARGS 1
 288
 289 #define REG_PARM_STACK_SPACE(FNDECL) 0
 290
 291 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 292
 293 \f
 294 /* Function Arguments in Registers.  */
 295
 296 #define MAX_ARGS_IN_REGISTERS 8
 297
 298 typedef struct iq2000_args
 299 {
 300   int gp_reg_found;             /* Whether a gp register was found yet.  */
 301   unsigned int arg_number;      /* Argument number.  */
 302   unsigned int arg_words;       /* # total words the arguments take.  */
 303   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 304   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 305   int fp_code;                  /* Mode of FP arguments.  */
 306   unsigned int num_adjusts;     /* Number of adjustments made.  */
 307                                 /* Adjustments made to args pass in regs.  */
 308   rtx adjust[MAX_ARGS_IN_REGISTERS * 2];
 309 } CUMULATIVE_ARGS;
 310
 311 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 312    for a call to a function whose data type is FNTYPE.
 313    For a library call, FNTYPE is 0.  */
 314 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 315   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 316
 317 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 318   (! BYTES_BIG_ENDIAN                                                   \
 319    ? upward                                                             \
 320    : (((MODE) == BLKmode                                                \
 321        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 322           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 323        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 324           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 325       ? downward : upward))
 326
 327 #define FUNCTION_ARG_REGNO_P(N)                                         \
 328   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 329
 330 \f
 331 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 332
 333 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N)
 334
 335 \f
 336 /* How Large Values are Returned.  */
 337
 338 #define DEFAULT_PCC_STRUCT_RETURN 0
 339 \f
 340 /* Function Entry and Exit.  */
 341
 342 #define EXIT_IGNORE_STACK 1
 343
 344 \f
 345 /* Generating Code for Profiling.  */
 346
 347 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 348 {                                                                       \
 349   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 350   fprintf (FILE, "\t.set\tnoat\n");                                     \
 351   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 352            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 353   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 354   fprintf (FILE,                                                        \
 355            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 356            "subu",                                                      \
 357            reg_names[STACK_POINTER_REGNUM],                             \
 358            reg_names[STACK_POINTER_REGNUM],                             \
 359            Pmode == DImode ? 16 : 8);                                   \
 360   fprintf (FILE, "\t.set\treorder\n");                                  \
 361   fprintf (FILE, "\t.set\tat\n");                                       \
 362 }
 363
 364 \f
 365 /* Trampolines for Nested Functions.  */
 366
 367 #define TRAMPOLINE_CODE_SIZE  (8*4)
 368 #define TRAMPOLINE_SIZE       (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode))
 369 #define TRAMPOLINE_ALIGNMENT  GET_MODE_ALIGNMENT (Pmode)
 370
 371 \f
 372 /* Addressing Modes.  */
 373
 374 #define CONSTANT_ADDRESS_P(X)                                           \
 375   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 376     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 377     || (GET_CODE (X) == CONST)))
 378
 379 #define MAX_REGS_PER_ADDRESS 1
 380
 381 #define REG_OK_FOR_INDEX_P(X) 0
 382
 383 \f
 384 /* Describing Relative Costs of Operations.  */
 385
 386 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 387
 388 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 389   (TO_P ? 2 : 16)
 390
 391 #define BRANCH_COST(speed_p, predictable_p) 2
 392
 393 #define SLOW_BYTE_ACCESS 1
 394
 395 #define NO_FUNCTION_CSE 1
 396
 397 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 398   if (REG_NOTE_KIND (LINK) != 0)                                        \
 399     (COST) = 0; /* Anti or output dependence.  */
 400
 401 \f
 402 /* Dividing the output into sections.  */
 403
 404 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 405
 406 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 407
 408 \f
 409 /* The Overall Framework of an Assembler File.  */
 410
 411 #define ASM_COMMENT_START " #"
 412
 413 #define ASM_APP_ON "#APP\n"
 414
 415 #define ASM_APP_OFF "#NO_APP\n"
 416
 417 \f
 418 /* Output and Generation of Labels.  */
 419
 420 #undef ASM_GENERATE_INTERNAL_LABEL
 421 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 422   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 423
 424 #define GLOBAL_ASM_OP "\t.globl\t"
 425
 426 \f
 427 /* Output of Assembler Instructions.  */
 428
 429 #define REGISTER_NAMES                                                  \
 430 {                                                                       \
 431  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 432  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 433  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 434  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 435 }
 436
 437 #define ADDITIONAL_REGISTER_NAMES                                       \
 438 {                                                                       \
 439   { "%0",        0 + GP_REG_FIRST },                                    \
 440   { "%1",        1 + GP_REG_FIRST },                                    \
 441   { "%2",        2 + GP_REG_FIRST },                                    \
 442   { "%3",        3 + GP_REG_FIRST },                                    \
 443   { "%4",        4 + GP_REG_FIRST },                                    \
 444   { "%5",        5 + GP_REG_FIRST },                                    \
 445   { "%6",        6 + GP_REG_FIRST },                                    \
 446   { "%7",        7 + GP_REG_FIRST },                                    \
 447   { "%8",        8 + GP_REG_FIRST },                                    \
 448   { "%9",        9 + GP_REG_FIRST },                                    \
 449   { "%10",      10 + GP_REG_FIRST },                                    \
 450   { "%11",      11 + GP_REG_FIRST },                                    \
 451   { "%12",      12 + GP_REG_FIRST },                                    \
 452   { "%13",      13 + GP_REG_FIRST },                                    \
 453   { "%14",      14 + GP_REG_FIRST },                                    \
 454   { "%15",      15 + GP_REG_FIRST },                                    \
 455   { "%16",      16 + GP_REG_FIRST },                                    \
 456   { "%17",      17 + GP_REG_FIRST },                                    \
 457   { "%18",      18 + GP_REG_FIRST },                                    \
 458   { "%19",      19 + GP_REG_FIRST },                                    \
 459   { "%20",      20 + GP_REG_FIRST },                                    \
 460   { "%21",      21 + GP_REG_FIRST },                                    \
 461   { "%22",      22 + GP_REG_FIRST },                                    \
 462   { "%23",      23 + GP_REG_FIRST },                                    \
 463   { "%24",      24 + GP_REG_FIRST },                                    \
 464   { "%25",      25 + GP_REG_FIRST },                                    \
 465   { "%26",      26 + GP_REG_FIRST },                                    \
 466   { "%27",      27 + GP_REG_FIRST },                                    \
 467   { "%28",      28 + GP_REG_FIRST },                                    \
 468   { "%29",      29 + GP_REG_FIRST },                                    \
 469   { "%30",      27 + GP_REG_FIRST },                                    \
 470   { "%31",      31 + GP_REG_FIRST },                                    \
 471   { "%rap",     32 + GP_REG_FIRST },                                    \
 472 }
 473
 474 /* Check if the current insn needs a nop in front of it
 475    because of load delays, and also update the delay slot statistics.  */
 476
 477 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 478   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 479
 480 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 481 do                                                                      \
 482   {                                                                     \
 483     fputs ("\n", STREAM);                                               \
 484   }                                                                     \
 485 while (0)
 486
 487 #define LOCAL_LABEL_PREFIX      "$"
 488
 489 #define USER_LABEL_PREFIX       ""
 490
 491 \f
 492 /* Output of dispatch tables.  */
 493
 494 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 495   do                                                                    \
 496     {                                                                   \
 497       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 498                Pmode == DImode ? ".dword" : ".word",                    \
 499                LOCAL_LABEL_PREFIX, VALUE);                              \
 500     }                                                                   \
 501   while (0)
 502
 503 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 504   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 505            Pmode == DImode ? ".dword" : ".word",                        \
 506            LOCAL_LABEL_PREFIX,                                          \
 507            VALUE)
 508
 509 \f
 510 /* Assembler Commands for Alignment.  */
 511
 512 #undef ASM_OUTPUT_SKIP
 513 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 514   fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",      \
 515            (unsigned HOST_WIDE_INT)(SIZE))
 516
 517 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 518   if ((LOG) != 0)                                                       \
 519     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 520
 521 \f
 522 /* Macros Affecting all Debug Formats.  */
 523
 524 #define DEBUGGER_AUTO_OFFSET(X)  \
 525   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 526
 527 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 528   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 529
 530 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 531
 532 #define DWARF2_DEBUGGING_INFO 1
 533
 534 \f
 535 /* Miscellaneous Parameters.  */
 536
 537 #define CASE_VECTOR_MODE SImode
 538
 539 #define WORD_REGISTER_OPERATIONS 1
 540
 541 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 542
 543 #define MOVE_MAX 4
 544
 545 #define MAX_MOVE_MAX 8
 546
 547 #define SHIFT_COUNT_TRUNCATED 1
 548
 549 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 550
 551 #define STORE_FLAG_VALUE 1
 552
 553 #define Pmode SImode
 554
 555 #define FUNCTION_MODE SImode
 556
 557 /* IQ2000 external variables defined in iq2000.c.  */
 558
 559 /* Comparison type.  */
 560 enum cmp_type
 561 {
 562   CMP_SI,                               /* Compare four byte integers.  */
 563   CMP_DI,                               /* Compare eight byte integers.  */
 564   CMP_SF,                               /* Compare single precision floats.  */
 565   CMP_DF,                               /* Compare double precision floats.  */
 566   CMP_MAX                               /* Max comparison type.  */
 567 };
 568
 569 /* Types of delay slot.  */
 570 enum delay_type
 571 {
 572   DELAY_NONE,                           /* No delay slot.  */
 573   DELAY_LOAD,                           /* Load from memory delay.  */
 574   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 575 };
 576
 577 /* Recast the cpu class to be the cpu attribute.  */
 578 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 579
 580 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 581 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 582
 583 \f
 584 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 585
 586 /* Macros to decide whether certain features are available or not,
 587    depending on the instruction set architecture level.  */
 588
 589 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 590
 591 /* ISA has branch likely instructions.  */
 592 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 593
 594 \f
 595 #undef ASM_SPEC
 596
 597 \f
 598 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 599 #define DWARF_FRAME_REGNUM(REG)        (REG)
 600
 601 /* The DWARF 2 CFA column which tracks the return address.  */
 602 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 603
 604 /* Describe how we implement __builtin_eh_return.  */
 605 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 606
 607 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 608    location used to store the amount to adjust the stack.  This is
 609    usually a register that is available from end of the function's body
 610    to the end of the epilogue. Thus, this cannot be a register used as a
 611    temporary by the epilogue.
 612
 613    This must be an integer register.  */
 614 #define EH_RETURN_STACKADJ_REGNO        3
 615 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 616
 617 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 618    location used to store the address the processor should jump to
 619    catch exception.  This is usually a registers that is available from
 620    end of the function's body to the end of the epilogue. Thus, this
 621    cannot be a register used as a temporary by the epilogue.
 622
 623    This must be an address register.  */
 624 #define EH_RETURN_HANDLER_REGNO         26
 625 #define EH_RETURN_HANDLER_RTX           \
 626         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 627
 628 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 629 #define DWARF_CIE_DATA_ALIGNMENT 4
 630
 631 /* For IQ2000, width of a floating point register.  */
 632 #define UNITS_PER_FPREG 4
 633
 634 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 635
 636 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 637
 638 /* Internal macros to classify a register number as to whether it's a
 639    general purpose register, a floating point register, a
 640    multiply/divide register, or a status register.  */
 641
 642 #define GP_REG_FIRST 0
 643 #define GP_REG_LAST  31
 644 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 645
 646 #define RAP_REG_NUM   32
 647 #define AT_REGNUM       (GP_REG_FIRST + 1)
 648
 649 #define GP_REG_P(REGNO) \
 650   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 651
 652 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 653    is larger than 32K bytes.  These registers must come from the
 654    scratch register set, and not used for passing and returning
 655    arguments and any other information used in the calling sequence.  */
 656
 657 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 658 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 659
 660 /* This macro is used later on in the file.  */
 661 #define GR_REG_CLASS_P(CLASS)                                           \
 662   ((CLASS) == GR_REGS)
 663
 664 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 665 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 666
 667 /* Certain machines have the property that some registers cannot be
 668    copied to some other registers without using memory.  Define this
 669    macro on those machines to be a C expression that is nonzero if
 670    objects of mode MODE in registers of CLASS1 can only be copied to
 671    registers of class CLASS2 by storing a register of CLASS1 into
 672    memory and loading that memory location into a register of CLASS2.
 673
 674    Do not define this macro if its value would always be zero.  */
 675
 676 /* Return the maximum number of consecutive registers
 677    needed to represent mode MODE in a register of class CLASS.  */
 678
 679 #define CLASS_UNITS(mode, size)                                         \
 680   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
 681
 682 /* If defined, gives a class of registers that cannot be used as the
 683    operand of a SUBREG that changes the mode of the object illegally.  */
 684
 685 #define CLASS_CANNOT_CHANGE_MODE 0
 686
 687 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
 688
 689 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
 690   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 691
 692 /* Make sure 4 words are always allocated on the stack.  */
 693
 694 #ifndef STACK_ARGS_ADJUST
 695 #define STACK_ARGS_ADJUST(SIZE)                                         \
 696   {                                                                     \
 697     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
 698       SIZE.constant = 4 * UNITS_PER_WORD;                               \
 699   }
 700 #endif
 701
 702 \f
 703 /* Symbolic macros for the registers used to return integer and floating
 704    point values.  */
 705
 706 #define GP_RETURN (GP_REG_FIRST + 2)
 707
 708 /* Symbolic macros for the first/last argument registers.  */
 709
 710 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
 711 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
 712
 713 #define MAX_ARGS_IN_REGISTERS   8
 714
 715 \f
 716 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
 717
 718 #define MUST_SAVE_REGISTER(regno) \
 719   ((df_regs_ever_live_p (regno) && !call_used_regs[regno])              \
 720   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
 721    || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
 722
 723 /* ALIGN FRAMES on double word boundaries */
 724 #ifndef IQ2000_STACK_ALIGN
 725 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
 726 #endif
 727
 728 \f
 729 /* These assume that REGNO is a hard or pseudo reg number.
 730    They give nonzero only if REGNO is a hard reg of the suitable class
 731    or a pseudo reg currently allocated to a suitable hard reg.
 732    These definitions are NOT overridden anywhere.  */
 733
 734 #define BASE_REG_P(regno, mode)                                 \
 735   (GP_REG_P (regno))
 736
 737 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
 738   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
 739              (mode))
 740
 741 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
 742   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
 743
 744 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
 745   GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode))
 746
 747 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 748    and check its validity for a certain class.
 749    We have two alternate definitions for each of them.
 750    The usual definition accepts all pseudo regs; the other rejects them all.
 751    The symbol REG_OK_STRICT causes the latter definition to be used.
 752
 753    Most source files want to accept pseudo regs in the hope that
 754    they will get allocated to the class that the insn wants them to be in.
 755    Some source files that are used after register allocation
 756    need to be strict.  */
 757
 758 #ifndef REG_OK_STRICT
 759 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 760   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
 761 #else
 762 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 763   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
 764 #endif
 765
 766 #if 1
 767 #define GO_PRINTF(x)    fprintf (stderr, (x))
 768 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
 769 #define GO_DEBUG_RTX(x) debug_rtx (x)
 770
 771 #else
 772 #define GO_PRINTF(x)
 773 #define GO_PRINTF2(x,y)
 774 #define GO_DEBUG_RTX(x)
 775 #endif
 776
 777 /* If defined, modifies the length assigned to instruction INSN as a
 778    function of the context in which it is used.  LENGTH is an lvalue
 779    that contains the initially computed length of the insn and should
 780    be updated with the correct length of the insn.  */
 781 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
 782   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
 783
 784 \f
 785
 786
 787 /* How to tell the debugger about changes of source files.  */
 788
 789 #ifndef SET_FILE_NUMBER
 790 #define SET_FILE_NUMBER() ++ num_source_filenames
 791 #endif
 792
 793 /* This is how to output a note the debugger telling it the line number
 794    to which the following sequence of instructions corresponds.  */
 795
 796 #ifndef LABEL_AFTER_LOC
 797 #define LABEL_AFTER_LOC(STREAM)
 798 #endif
 799
 800 \f
 801 /* Default to -G 8 */
 802 #ifndef IQ2000_DEFAULT_GVALUE
 803 #define IQ2000_DEFAULT_GVALUE 8
 804 #endif
 805
 806 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
 807
 808 \f
 809 /* Which instruction set architecture to use.  */
 810 extern int iq2000_isa;
 811
 812 enum iq2000_builtins
 813 {
 814   IQ2000_BUILTIN_ADO16,
 815   IQ2000_BUILTIN_CFC0,
 816   IQ2000_BUILTIN_CFC1,
 817   IQ2000_BUILTIN_CFC2,
 818   IQ2000_BUILTIN_CFC3,
 819   IQ2000_BUILTIN_CHKHDR,
 820   IQ2000_BUILTIN_CTC0,
 821   IQ2000_BUILTIN_CTC1,
 822   IQ2000_BUILTIN_CTC2,
 823   IQ2000_BUILTIN_CTC3,
 824   IQ2000_BUILTIN_LU,
 825   IQ2000_BUILTIN_LUC32L,
 826   IQ2000_BUILTIN_LUC64,
 827   IQ2000_BUILTIN_LUC64L,
 828   IQ2000_BUILTIN_LUK,
 829   IQ2000_BUILTIN_LULCK,
 830   IQ2000_BUILTIN_LUM32,
 831   IQ2000_BUILTIN_LUM32L,
 832   IQ2000_BUILTIN_LUM64,
 833   IQ2000_BUILTIN_LUM64L,
 834   IQ2000_BUILTIN_LUR,
 835   IQ2000_BUILTIN_LURL,
 836   IQ2000_BUILTIN_MFC0,
 837   IQ2000_BUILTIN_MFC1,
 838   IQ2000_BUILTIN_MFC2,
 839   IQ2000_BUILTIN_MFC3,
 840   IQ2000_BUILTIN_MRGB,
 841   IQ2000_BUILTIN_MTC0,
 842   IQ2000_BUILTIN_MTC1,
 843   IQ2000_BUILTIN_MTC2,
 844   IQ2000_BUILTIN_MTC3,
 845   IQ2000_BUILTIN_PKRL,
 846   IQ2000_BUILTIN_RAM,
 847   IQ2000_BUILTIN_RB,
 848   IQ2000_BUILTIN_RX,
 849   IQ2000_BUILTIN_SRRD,
 850   IQ2000_BUILTIN_SRRDL,
 851   IQ2000_BUILTIN_SRULC,
 852   IQ2000_BUILTIN_SRULCK,
 853   IQ2000_BUILTIN_SRWR,
 854   IQ2000_BUILTIN_SRWRU,
 855   IQ2000_BUILTIN_TRAPQF,
 856   IQ2000_BUILTIN_TRAPQFL,
 857   IQ2000_BUILTIN_TRAPQN,
 858   IQ2000_BUILTIN_TRAPQNE,
 859   IQ2000_BUILTIN_TRAPRE,
 860   IQ2000_BUILTIN_TRAPREL,
 861   IQ2000_BUILTIN_WB,
 862   IQ2000_BUILTIN_WBR,
 863   IQ2000_BUILTIN_WBU,
 864   IQ2000_BUILTIN_WX,
 865   IQ2000_BUILTIN_SYSCALL
 866 };