1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "stringpool.h"
39 #include "diagnostic-core.h"
40 #include "conditions.h"
41 #include "insn-attr.h"
44 #include "stor-layout.h"
50 #include "tm-constrs.h"
53 /* This file should be included last. */
54 #include "target-def.h"
56 /* Usable when we have an amount to add or subtract, and want the
57 optimal size of the insn. */
58 #define ADDITIVE_SIZE_MODIFIER(size) \
59 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
61 #define LOSE_AND_RETURN(msgid, x) \
64 cris_operand_lossage (msgid, x); \
68 enum cris_retinsn_type
69 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
71 /* Per-function machine data. */
72 struct GTY(()) machine_function
74 int needs_return_address_on_stack
;
76 /* This is the number of registers we save in the prologue due to
80 enum cris_retinsn_type return_type
;
83 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
85 static char cris_output_insn_is_bound
= 0;
87 /* In code for output macros, this is how we know whether e.g. constant
88 goes in code or in a static initializer. */
89 static int in_code
= 0;
91 /* Fix for reg_overlap_mentioned_p. */
92 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
94 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
95 int *, const_tree
, int);
97 static unsigned int cris_atomic_align_for_mode (machine_mode
);
99 static void cris_print_base (rtx
, FILE *);
101 static void cris_print_index (rtx
, FILE *);
103 static void cris_output_addr_const (FILE *, rtx
);
105 static struct machine_function
* cris_init_machine_status (void);
107 static rtx
cris_struct_value_rtx (tree
, int);
109 static void cris_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
110 tree type
, int *, int);
112 static int cris_initial_frame_pointer_offset (void);
114 static void cris_operand_lossage (const char *, rtx
);
116 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
118 static void cris_print_operand (FILE *, rtx
, int);
120 static void cris_print_operand_address (FILE *, machine_mode
, rtx
);
122 static bool cris_print_operand_punct_valid_p (unsigned char code
);
124 static bool cris_output_addr_const_extra (FILE *, rtx
);
126 static void cris_conditional_register_usage (void);
128 static void cris_asm_output_mi_thunk
129 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
131 static void cris_file_start (void);
132 static void cris_init_libfuncs (void);
134 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
136 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
137 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
138 static bool cris_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
139 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
140 static bool cris_pass_by_reference (cumulative_args_t
, machine_mode
,
142 static int cris_arg_partial_bytes (cumulative_args_t
, machine_mode
,
144 static rtx
cris_function_arg (cumulative_args_t
, machine_mode
,
146 static rtx
cris_function_incoming_arg (cumulative_args_t
,
147 machine_mode
, const_tree
, bool);
148 static void cris_function_arg_advance (cumulative_args_t
, machine_mode
,
150 static rtx_insn
*cris_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
152 vec
<rtx
> &, HARD_REG_SET
&);
153 static bool cris_cannot_force_const_mem (machine_mode
, rtx
);
155 static void cris_option_override (void);
157 static bool cris_frame_pointer_required (void);
159 static void cris_asm_trampoline_template (FILE *);
160 static void cris_trampoline_init (rtx
, tree
, rtx
);
162 static rtx
cris_function_value(const_tree
, const_tree
, bool);
163 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
164 static bool cris_function_value_regno_p (const unsigned int);
165 static void cris_file_end (void);
166 static bool cris_hard_regno_mode_ok (unsigned int, machine_mode
);
168 /* This is the parsed result of the "-max-stack-stackframe=" option. If
169 it (still) is zero, then there was no such option given. */
170 int cris_max_stackframe
= 0;
172 /* This is the parsed result of the "-march=" option, if given. */
173 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
175 #undef TARGET_ASM_ALIGNED_HI_OP
176 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
177 #undef TARGET_ASM_ALIGNED_SI_OP
178 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
179 #undef TARGET_ASM_ALIGNED_DI_OP
180 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
182 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
183 available in ELF. These "normal" pseudos do not have any alignment
184 constraints or side-effects. */
185 #undef TARGET_ASM_UNALIGNED_HI_OP
186 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_UNALIGNED_DI_OP
192 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
194 #undef TARGET_PRINT_OPERAND
195 #define TARGET_PRINT_OPERAND cris_print_operand
196 #undef TARGET_PRINT_OPERAND_ADDRESS
197 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
198 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
199 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
200 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
201 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
203 #undef TARGET_CONDITIONAL_REGISTER_USAGE
204 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
206 #undef TARGET_ASM_OUTPUT_MI_THUNK
207 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
208 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
209 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
211 #undef TARGET_ASM_FILE_START
212 #define TARGET_ASM_FILE_START cris_file_start
213 #undef TARGET_ASM_FILE_END
214 #define TARGET_ASM_FILE_END cris_file_end
216 #undef TARGET_INIT_LIBFUNCS
217 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
220 #define TARGET_LRA_P hook_bool_void_false
222 #undef TARGET_LEGITIMATE_ADDRESS_P
223 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
225 #undef TARGET_LEGITIMATE_CONSTANT_P
226 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
228 #undef TARGET_PREFERRED_RELOAD_CLASS
229 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
231 #undef TARGET_REGISTER_MOVE_COST
232 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
233 #undef TARGET_MEMORY_MOVE_COST
234 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
235 #undef TARGET_RTX_COSTS
236 #define TARGET_RTX_COSTS cris_rtx_costs
237 #undef TARGET_ADDRESS_COST
238 #define TARGET_ADDRESS_COST cris_address_cost
240 #undef TARGET_PROMOTE_FUNCTION_MODE
241 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
243 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
244 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
246 #undef TARGET_STRUCT_VALUE_RTX
247 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
248 #undef TARGET_SETUP_INCOMING_VARARGS
249 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
250 #undef TARGET_PASS_BY_REFERENCE
251 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
252 #undef TARGET_ARG_PARTIAL_BYTES
253 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
254 #undef TARGET_FUNCTION_ARG
255 #define TARGET_FUNCTION_ARG cris_function_arg
256 #undef TARGET_FUNCTION_INCOMING_ARG
257 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
258 #undef TARGET_FUNCTION_ARG_ADVANCE
259 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
260 #undef TARGET_MD_ASM_ADJUST
261 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
263 #undef TARGET_CANNOT_FORCE_CONST_MEM
264 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
266 #undef TARGET_FRAME_POINTER_REQUIRED
267 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
269 #undef TARGET_OPTION_OVERRIDE
270 #define TARGET_OPTION_OVERRIDE cris_option_override
272 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
273 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
274 #undef TARGET_TRAMPOLINE_INIT
275 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
277 #undef TARGET_FUNCTION_VALUE
278 #define TARGET_FUNCTION_VALUE cris_function_value
279 #undef TARGET_LIBCALL_VALUE
280 #define TARGET_LIBCALL_VALUE cris_libcall_value
281 #undef TARGET_FUNCTION_VALUE_REGNO_P
282 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
284 #undef TARGET_HARD_REGNO_MODE_OK
285 #define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok
287 struct gcc_target targetm
= TARGET_INITIALIZER
;
289 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
292 cris_movem_load_rest_p (rtx op
, int offs
)
294 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
300 unsigned int regno
= 0;
302 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
303 other than (MEM reg). */
305 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
306 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
307 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
310 /* Check a possible post-inc indicator. */
311 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
313 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
314 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
320 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
321 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
322 || !CONST_INT_P (inc
)
323 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
333 regno
= reg_count
- 1;
336 elt
= XVECEXP (op
, 0, offs
);
337 src_addr
= XEXP (SET_SRC (elt
), 0);
339 if (GET_CODE (elt
) != SET
340 || !REG_P (SET_DEST (elt
))
341 || GET_MODE (SET_DEST (elt
)) != SImode
342 || REGNO (SET_DEST (elt
)) != regno
343 || !MEM_P (SET_SRC (elt
))
344 || GET_MODE (SET_SRC (elt
)) != SImode
345 || !memory_address_p (SImode
, src_addr
))
348 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
350 rtx elt
= XVECEXP (op
, 0, i
);
353 if (GET_CODE (elt
) != SET
354 || !REG_P (SET_DEST (elt
))
355 || GET_MODE (SET_DEST (elt
)) != SImode
356 || REGNO (SET_DEST (elt
)) != regno
357 || !MEM_P (SET_SRC (elt
))
358 || GET_MODE (SET_SRC (elt
)) != SImode
359 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
360 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
361 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
362 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
369 /* Worker function for predicate for the parallel contents in a movem
373 cris_store_multiple_op_p (rtx op
)
375 int reg_count
= XVECLEN (op
, 0);
386 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
387 other than (MEM reg) and (MEM (PLUS reg const)). */
391 elt
= XVECEXP (op
, 0, 0);
393 if (GET_CODE (elt
) != SET
)
396 dest
= SET_DEST (elt
);
398 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
401 dest_addr
= XEXP (dest
, 0);
403 /* Check a possible post-inc indicator. */
404 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
406 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
407 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
413 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
414 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
415 || !CONST_INT_P (inc
)
416 /* Support increment by number of registers, and by the offset
417 of the destination, if it has the form (MEM (PLUS reg
419 || !((REG_P (dest_addr
)
420 && REGNO (dest_addr
) == REGNO (reg
)
421 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
422 || (GET_CODE (dest_addr
) == PLUS
423 && REG_P (XEXP (dest_addr
, 0))
424 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
425 && CONST_INT_P (XEXP (dest_addr
, 1))
426 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
437 regno
= reg_count
- 1;
440 if (GET_CODE (elt
) != SET
441 || !REG_P (SET_SRC (elt
))
442 || GET_MODE (SET_SRC (elt
)) != SImode
443 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
444 || !MEM_P (SET_DEST (elt
))
445 || GET_MODE (SET_DEST (elt
)) != SImode
)
448 if (REG_P (dest_addr
))
450 dest_base
= dest_addr
;
453 else if (GET_CODE (dest_addr
) == PLUS
454 && REG_P (XEXP (dest_addr
, 0))
455 && CONST_INT_P (XEXP (dest_addr
, 1)))
457 dest_base
= XEXP (dest_addr
, 0);
458 offset
= INTVAL (XEXP (dest_addr
, 1));
463 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
465 rtx elt
= XVECEXP (op
, 0, i
);
468 if (GET_CODE (elt
) != SET
469 || !REG_P (SET_SRC (elt
))
470 || GET_MODE (SET_SRC (elt
)) != SImode
471 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
472 || !MEM_P (SET_DEST (elt
))
473 || GET_MODE (SET_DEST (elt
)) != SImode
474 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
475 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
476 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
477 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
484 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
487 cris_conditional_register_usage (void)
489 /* FIXME: This isn't nice. We should be able to use that register for
490 something else if the PIC table isn't needed. */
492 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
493 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
495 /* Allow use of ACR (PC in pre-V32) and tweak order. */
498 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
501 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
504 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
506 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
509 if (TARGET_HAS_MUL_INSNS
)
510 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
512 /* On early versions, we must use the 16-bit condition-code register,
513 which has another name. */
514 if (cris_cpu_version
< 8)
515 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
518 /* Return crtl->uses_pic_offset_table. For use in cris.md,
519 since some generated files do not include function.h. */
522 cris_cfun_uses_pic_table (void)
524 return crtl
->uses_pic_offset_table
;
527 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
528 We can't put PIC addresses in the constant pool, not even the ones that
529 can be reached as pc-relative as we can't tell when or how to do that. */
532 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
534 enum cris_symbol_type t
= cris_symbol_type_of (x
);
538 || t
== cris_got_symbol
539 || t
== cris_rel_symbol
;
542 /* Given an rtx, return the text string corresponding to the CODE of X.
543 Intended for use in the assembly language output section of a
549 cris_output_insn_is_bound
= 0;
550 switch (GET_CODE (x
))
559 /* This function is for retrieving a part of an instruction name for
560 an operator, for immediate output. If that ever happens for
561 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
563 internal_error ("MULT case in cris_op_str");
591 /* Used to control the sign/zero-extend character for the 'E' modifier.
593 cris_output_insn_is_bound
= 1;
597 return "Unknown operator";
601 /* Emit an error message when we're in an asm, and a fatal error for
602 "normal" insns. Formatted output isn't easily implemented, since we
603 use output_operand_lossage to output the actual message and handle the
604 categorization of the error. */
607 cris_operand_lossage (const char *msgid
, rtx op
)
610 output_operand_lossage ("%s", msgid
);
613 /* Print an index part of an address to file. */
616 cris_print_index (rtx index
, FILE *file
)
618 /* Make the index "additive" unless we'll output a negative number, in
619 which case the sign character is free (as in free beer). */
620 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
624 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
625 else if (CRIS_CONSTANT_P (index
))
626 cris_output_addr_const (file
, index
);
627 else if (GET_CODE (index
) == MULT
)
629 fprintf (file
, "$%s.",
630 reg_names
[REGNO (XEXP (index
, 0))]);
632 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
634 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
636 rtx inner
= XEXP (index
, 0);
637 rtx inner_inner
= XEXP (inner
, 0);
639 if (GET_CODE (inner_inner
) == POST_INC
)
641 fprintf (file
, "[$%s+].",
642 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
643 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
647 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
649 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
652 else if (MEM_P (index
))
654 rtx inner
= XEXP (index
, 0);
655 if (GET_CODE (inner
) == POST_INC
)
656 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
658 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
661 cris_operand_lossage ("unexpected index-type in cris_print_index",
665 /* Print a base rtx of an address to file. */
668 cris_print_base (rtx base
, FILE *file
)
671 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
672 else if (GET_CODE (base
) == POST_INC
)
674 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
675 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
678 cris_operand_lossage ("unexpected base-type in cris_print_base",
682 /* Usable as a guard in expressions. */
685 cris_fatal (char *arg
)
687 internal_error (arg
);
689 /* We'll never get here; this is just to appease compilers. */
693 /* Return nonzero if REGNO is an ordinary register that *needs* to be
694 saved together with other registers, possibly by a MOVEM instruction,
695 or is saved for target-independent reasons. There may be
696 target-dependent reasons to save the register anyway; this is just a
697 wrapper for a complicated conditional. */
700 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
703 (((df_regs_ever_live_p (regno
)
704 && !call_used_regs
[regno
])
705 || (regno
== PIC_OFFSET_TABLE_REGNUM
707 /* It is saved anyway, if there would be a gap. */
709 && df_regs_ever_live_p (regno
+ 1)
710 && !call_used_regs
[regno
+ 1]))))
711 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
712 && regno
!= CRIS_SRP_REGNUM
)
713 || (crtl
->calls_eh_return
714 && (regno
== EH_RETURN_DATA_REGNO (0)
715 || regno
== EH_RETURN_DATA_REGNO (1)
716 || regno
== EH_RETURN_DATA_REGNO (2)
717 || regno
== EH_RETURN_DATA_REGNO (3)));
720 /* The PRINT_OPERAND worker. */
723 cris_print_operand (FILE *file
, rtx x
, int code
)
727 /* Size-strings corresponding to MULT expressions. */
728 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
730 /* New code entries should just be added to the switch below. If
731 handling is finished, just return. If handling was just a
732 modification of the operand, the modified operand should be put in
733 "operand", and then do a break to let default handling
734 (zero-modifier) output the operand. */
739 /* Print the unsigned supplied integer as if it were signed
740 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
741 if (!satisfies_constraint_O (x
))
742 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
743 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
744 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
748 /* Print assembler code for operator. */
749 fprintf (file
, "%s", cris_op_str (operand
));
754 /* A movem modifier working on a parallel; output the register
758 if (GET_CODE (x
) != PARALLEL
)
759 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
761 /* The second item can be (set reg (plus reg const)) to denote a
764 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
766 : XVECLEN (x
, 0) - 1);
768 fprintf (file
, "$%s", reg_names
[regno
]);
774 /* A similar movem modifier; output the memory operand. */
777 if (GET_CODE (x
) != PARALLEL
)
778 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
780 /* The lowest mem operand is in the first item, but perhaps it
781 needs to be output as postincremented. */
782 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
783 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
784 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
786 /* The second item can be a (set reg (plus reg const)) to denote
788 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
790 /* It's a post-increment, if the address is a naked (reg). */
792 addr
= gen_rtx_POST_INC (SImode
, addr
);
795 /* Otherwise, it's a side-effect; RN=RN+M. */
796 fprintf (file
, "[$%s=$%s%s%d]",
797 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
798 reg_names
[REGNO (XEXP (addr
, 0))],
799 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
800 (int) INTVAL (XEXP (addr
, 1)));
804 output_address (VOIDmode
, addr
);
809 /* Adjust a power of two to its log2. */
810 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
811 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
812 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
816 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
817 respectively. This modifier also terminates the inhibiting
818 effects of the 'x' modifier. */
819 cris_output_insn_is_bound
= 0;
820 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
824 if (INTVAL (x
) <= 255)
826 else if (INTVAL (x
) <= 65535)
836 /* For a non-integer, print the size of the operand. */
837 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
838 ? 'd' : GET_MODE (x
) == HImode
? 'w'
839 : GET_MODE (x
) == QImode
? 'b'
840 /* If none of the above, emit an erroneous size letter. */
846 /* Const_int: print b for -127 <= x <= 255,
847 w for -32768 <= x <= 65535, else die. */
849 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
850 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
851 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
855 /* If this is a GOT-symbol, print the size-letter corresponding to
856 -fpic/-fPIC. For everything else, print "d". */
858 && GET_CODE (x
) == CONST
859 && GET_CODE (XEXP (x
, 0)) == UNSPEC
860 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
865 /* Output a 'nop' if there's nothing for the delay slot.
866 This method stolen from the sparc files. */
867 if (dbr_sequence_length () == 0)
868 fputs ("\n\tnop", file
);
872 /* Output directive for alignment padded with "nop" insns.
873 Optimizing for size, it's plain 4-byte alignment, otherwise we
874 align the section to a cache-line (32 bytes) and skip at max 2
875 bytes, i.e. we skip if it's the last insn on a cache-line. The
876 latter is faster by a small amount (for two test-programs 99.6%
877 and 99.9%) and larger by a small amount (ditto 100.1% and
878 100.2%). This is supposed to be the simplest yet performance-
879 wise least intrusive way to make sure the immediately following
880 (supposed) muls/mulu insn isn't located at the end of a
884 ? ".p2alignw 2,0x050f\n\t"
885 : ".p2alignw 5,0x050f,2\n\t", file
);
889 /* The PIC register. */
891 internal_error ("invalid use of ':' modifier");
892 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
896 /* Print high (most significant) part of something. */
897 switch (GET_CODE (operand
))
900 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
901 value is kept here, and so may be other than 0 or -1. */
902 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
903 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
907 /* High part of a long long constant. */
908 if (GET_MODE (operand
) == VOIDmode
)
910 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
914 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
917 /* Print reg + 1. Check that there's not an attempt to print
918 high-parts of registers like stack-pointer or higher, except
919 for SRP (where the "high part" is MOF). */
920 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
921 && (REGNO (operand
) != CRIS_SRP_REGNUM
922 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
923 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
924 LOSE_AND_RETURN ("bad register", operand
);
925 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
929 /* Adjust memory address to high part. */
931 rtx adj_mem
= operand
;
933 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
935 /* Adjust so we can use two SImode in DImode.
936 Calling adj_offsettable_operand will make sure it is an
937 offsettable address. Don't do this for a postincrement
938 though; it should remain as it was. */
939 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
941 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
943 output_address (VOIDmode
, XEXP (adj_mem
, 0));
948 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
952 /* Strip the MEM expression. */
953 operand
= XEXP (operand
, 0);
957 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
958 iterators and attributes in cris.md to avoid the need for %x
959 and %E (and %e) and state passed between those modifiers. */
960 cris_output_insn_is_bound
= 0;
963 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
964 cris_output_insn_is_bound is nonzero. */
965 if (GET_CODE (operand
) != SIGN_EXTEND
966 && GET_CODE (operand
) != ZERO_EXTEND
967 && !CONST_INT_P (operand
))
968 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
970 if (cris_output_insn_is_bound
)
972 cris_output_insn_is_bound
= 0;
976 putc (GET_CODE (operand
) == SIGN_EXTEND
977 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
982 /* Print the size letter of the inner element. We can do it by
983 calling ourselves with the 's' modifier. */
984 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
985 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
986 cris_print_operand (file
, XEXP (operand
, 0), 's');
990 /* Print the least significant part of operand. */
991 if (GET_CODE (operand
) == CONST_DOUBLE
)
993 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
996 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
998 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
999 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1002 /* Otherwise the least significant part equals the normal part,
1003 so handle it normally. */
1007 /* When emitting an add for the high part of a DImode constant, we
1008 want to use addq for 0 and adds.w for -1. */
1009 if (!CONST_INT_P (operand
))
1010 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1011 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1015 /* For const_int operands, print the additive mnemonic and the
1016 modified operand (byte-sized operands don't save anything):
1017 N=MIN_INT..-65536: add.d N
1018 -65535..-64: subu.w -N
1022 65536..MAX_INT: add.d N.
1023 (Emitted mnemonics are capitalized to simplify testing.)
1024 For anything else (N.B: only register is valid), print "add.d". */
1025 if (REG_P (operand
))
1027 fprintf (file
, "Add.d ");
1029 /* Deal with printing the operand by dropping through to the
1036 gcc_assert (CONST_INT_P (operand
));
1038 val
= INTVAL (operand
);
1039 if (!IN_RANGE (val
, -65535, 65535))
1040 fprintf (file
, "Add.d %d", val
);
1041 else if (val
<= -64)
1042 fprintf (file
, "Subu.w %d", -val
);
1044 fprintf (file
, "Subq %d", -val
);
1046 fprintf (file
, "Addq %d", val
);
1047 else if (val
<= 65535)
1048 fprintf (file
, "Addu.w %d", val
);
1054 /* If the operand is an integer -31..31, print "q" else ".d". */
1055 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1056 fprintf (file
, "q");
1058 fprintf (file
, ".d");
1062 /* If this is a GOT symbol, force it to be emitted as :GOT and
1063 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1064 Avoid making this too much of a special case. */
1065 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1067 int flag_pic_save
= flag_pic
;
1070 cris_output_addr_const (file
, operand
);
1071 flag_pic
= flag_pic_save
;
1077 /* When emitting an sub for the high part of a DImode constant, we
1078 want to use subq for 0 and subs.w for -1. */
1079 if (!CONST_INT_P (operand
))
1080 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1081 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1085 /* Print the operand as the index-part of an address.
1086 Easiest way out is to use cris_print_index. */
1087 cris_print_index (operand
, file
);
1091 /* Print the size letter for an operand to a MULT, which must be a
1092 const_int with a suitable value. */
1093 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1094 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1095 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1099 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1101 && GET_CODE (operand
) == CONST
1102 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1103 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1104 fprintf (file
, "u.w");
1106 fprintf (file
, ".d");
1110 /* No code, print as usual. */
1114 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1117 /* Print an operand as without a modifier letter. */
1118 switch (GET_CODE (operand
))
1121 if (REGNO (operand
) > 15
1122 && REGNO (operand
) != CRIS_MOF_REGNUM
1123 && REGNO (operand
) != CRIS_SRP_REGNUM
1124 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1125 internal_error ("internal error: bad register: %d", REGNO (operand
));
1126 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1130 output_address (GET_MODE (operand
), XEXP (operand
, 0));
1134 if (GET_MODE (operand
) == VOIDmode
)
1135 /* A long long constant. */
1136 output_addr_const (file
, operand
);
1139 /* Only single precision is allowed as plain operands the
1143 /* FIXME: Perhaps check overflow of the "single". */
1144 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand
), l
);
1146 fprintf (file
, "0x%lx", l
);
1153 cris_output_addr_const (file
, operand
);
1159 /* For a (MULT (reg X) const_int) we output "rX.S". */
1160 int i
= CONST_INT_P (XEXP (operand
, 1))
1161 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1162 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1163 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1166 || (!CONST_INT_P (XEXP (operand
, 0))
1167 && !CONST_INT_P (XEXP (operand
, 1))))
1168 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1170 cris_print_base (reg
, file
);
1171 fprintf (file
, ".%c",
1172 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1174 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1180 /* No need to handle all strange variants, let output_addr_const
1182 if (CRIS_CONSTANT_P (operand
))
1184 cris_output_addr_const (file
, operand
);
1188 LOSE_AND_RETURN ("unexpected operand", x
);
1193 cris_print_operand_punct_valid_p (unsigned char code
)
1195 return (code
== '#' || code
== '!' || code
== ':');
1198 /* The PRINT_OPERAND_ADDRESS worker. */
1201 cris_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
1203 /* All these were inside MEM:s so output indirection characters. */
1206 if (CONSTANT_ADDRESS_P (x
))
1207 cris_output_addr_const (file
, x
);
1208 else if (cris_base_or_autoincr_p (x
, true))
1209 cris_print_base (x
, file
);
1210 else if (GET_CODE (x
) == PLUS
)
1216 if (cris_base_p (x1
, true))
1218 cris_print_base (x1
, file
);
1219 cris_print_index (x2
, file
);
1221 else if (cris_base_p (x2
, true))
1223 cris_print_base (x2
, file
);
1224 cris_print_index (x1
, file
);
1227 LOSE_AND_RETURN ("unrecognized address", x
);
1231 /* A DIP. Output more indirection characters. */
1233 cris_print_base (XEXP (x
, 0), file
);
1237 LOSE_AND_RETURN ("unrecognized address", x
);
1242 /* The RETURN_ADDR_RTX worker.
1243 We mark that the return address is used, either by EH or
1244 __builtin_return_address, for use by the function prologue and
1245 epilogue. FIXME: This isn't optimal; we just use the mark in the
1246 prologue and epilogue to say that the return address is to be stored
1247 in the stack frame. We could return SRP for leaf-functions and use the
1248 initial-value machinery. */
1251 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1253 cfun
->machine
->needs_return_address_on_stack
= 1;
1255 /* The return-address is stored just above the saved frame-pointer (if
1256 present). Apparently we can't eliminate from the frame-pointer in
1257 that direction, so use the incoming args (maybe pretended) pointer. */
1259 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1263 /* Accessor used in cris.md:return because cfun->machine isn't available
1267 cris_return_address_on_stack (void)
1269 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1270 || cfun
->machine
->needs_return_address_on_stack
;
1273 /* Accessor used in cris.md:return because cfun->machine isn't available
1277 cris_return_address_on_stack_for_return (void)
1279 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1280 : cris_return_address_on_stack ();
1283 /* This handles FP -> SP elimination offset. */
1286 cris_initial_frame_pointer_offset (void)
1290 /* Initial offset is 0 if we don't have a frame pointer. */
1292 bool got_really_used
= false;
1294 if (crtl
->uses_pic_offset_table
)
1296 push_topmost_sequence ();
1298 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1300 pop_topmost_sequence ();
1303 /* And 4 for each register pushed. */
1304 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1305 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1308 /* And then, last, we add the locals allocated. */
1309 offs
+= get_frame_size ();
1311 /* And more; the accumulated args size. */
1312 offs
+= crtl
->outgoing_args_size
;
1314 /* Then round it off, in case we use aligned stack. */
1315 if (TARGET_STACK_ALIGN
)
1316 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1321 /* The INITIAL_ELIMINATION_OFFSET worker.
1322 Calculate the difference between imaginary registers such as frame
1323 pointer and the stack pointer. Used to eliminate the frame pointer
1324 and imaginary arg pointer. */
1327 cris_initial_elimination_offset (int fromreg
, int toreg
)
1330 = cris_initial_frame_pointer_offset ();
1332 /* We should be able to use regs_ever_live and related prologue
1333 information here, or alpha should not as well. */
1334 bool return_address_on_stack
= cris_return_address_on_stack ();
1336 /* Here we act as if the frame-pointer were needed. */
1337 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1339 if (fromreg
== ARG_POINTER_REGNUM
1340 && toreg
== FRAME_POINTER_REGNUM
)
1341 return ap_fp_offset
;
1343 /* Between the frame pointer and the stack are only "normal" stack
1344 variables and saved registers. */
1345 if (fromreg
== FRAME_POINTER_REGNUM
1346 && toreg
== STACK_POINTER_REGNUM
)
1347 return fp_sp_offset
;
1349 /* We need to balance out the frame pointer here. */
1350 if (fromreg
== ARG_POINTER_REGNUM
1351 && toreg
== STACK_POINTER_REGNUM
)
1352 return ap_fp_offset
+ fp_sp_offset
- 4;
1357 /* Nonzero if X is a hard reg that can be used as an index. */
1359 reg_ok_for_base_p (const_rtx x
, bool strict
)
1361 return ((! strict
&& ! HARD_REGISTER_P (x
))
1362 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1365 /* Nonzero if X is a hard reg that can be used as an index. */
1367 reg_ok_for_index_p (const_rtx x
, bool strict
)
1369 return reg_ok_for_base_p (x
, strict
);
1372 /* No symbol can be used as an index (or more correct, as a base) together
1373 with a register with PIC; the PIC register must be there. */
1376 cris_constant_index_p (const_rtx x
)
1378 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1381 /* True if X is a valid base register. */
1384 cris_base_p (const_rtx x
, bool strict
)
1386 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1389 /* True if X is a valid index register. */
1392 cris_index_p (const_rtx x
, bool strict
)
1394 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1397 /* True if X is a valid base register with or without autoincrement. */
1400 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1402 return (cris_base_p (x
, strict
)
1403 || (GET_CODE (x
) == POST_INC
1404 && cris_base_p (XEXP (x
, 0), strict
)
1405 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1408 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1411 cris_bdap_index_p (const_rtx x
, bool strict
)
1414 && GET_MODE (x
) == SImode
1415 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1416 || (GET_CODE (x
) == SIGN_EXTEND
1417 && MEM_P (XEXP (x
, 0))
1418 && (GET_MODE (XEXP (x
, 0)) == HImode
1419 || GET_MODE (XEXP (x
, 0)) == QImode
)
1420 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1423 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1426 cris_biap_index_p (const_rtx x
, bool strict
)
1428 return (cris_index_p (x
, strict
)
1429 || (GET_CODE (x
) == MULT
1430 && cris_index_p (XEXP (x
, 0), strict
)
1431 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1434 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1436 A PIC operand looks like a normal symbol here. At output we dress it
1437 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1438 symbol) so we exclude all addressing modes where we can't replace a
1439 plain "symbol" with that. A global PIC symbol does not fit anywhere
1440 here (but is thankfully a general_operand in itself). A local PIC
1441 symbol is valid for the plain "symbol + offset" case. */
1444 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1448 if (cris_base_or_autoincr_p (x
, strict
))
1450 else if (TARGET_V32
)
1451 /* Nothing else is valid then. */
1453 else if (cris_constant_index_p (x
))
1456 else if (GET_CODE (x
) == PLUS
)
1461 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1462 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1463 /* BDAP Rs[+], Rd. */
1464 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1465 && ((cris_base_p (x1
, strict
)
1466 && cris_bdap_index_p (x2
, strict
))
1467 || (cris_base_p (x2
, strict
)
1468 && cris_bdap_index_p (x1
, strict
))
1470 || (cris_base_p (x1
, strict
)
1471 && cris_biap_index_p (x2
, strict
))
1472 || (cris_base_p (x2
, strict
)
1473 && cris_biap_index_p (x1
, strict
)))))
1478 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1479 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1480 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1487 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1488 PIC constants that aren't legitimized. FIXME: there used to be a
1489 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1490 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1491 While that may be seen as a bug, that guarantee seems a wart by design,
1492 so don't bother; fix the documentation instead. */
1495 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1497 enum cris_symbol_type t
;
1500 return LEGITIMATE_PIC_OPERAND_P (x
);
1502 t
= cris_symbol_type_of (x
);
1506 || t
== cris_offsettable_symbol
1507 || t
== cris_unspec
;
1510 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1513 cris_reload_address_legitimized (rtx x
,
1514 machine_mode mode ATTRIBUTE_UNUSED
,
1515 int opnum ATTRIBUTE_UNUSED
,
1517 int ind_levels ATTRIBUTE_UNUSED
)
1519 enum reload_type type
= (enum reload_type
) itype
;
1523 if (GET_CODE (x
) != PLUS
)
1531 op1p
= &XEXP (x
, 1);
1536 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1538 rtx op00
= XEXP (op0
, 0);
1539 rtx op000
= XEXP (op00
, 0);
1540 rtx
*op000p
= &XEXP (op00
, 0);
1542 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1544 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1546 bool something_reloaded
= false;
1548 if (GET_CODE (op000
) == POST_INC
1549 && REG_P (XEXP (op000
, 0))
1550 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1551 /* No, this gets too complicated and is too rare to care
1552 about trying to improve on the general code Here.
1553 As the return-value is an all-or-nothing indicator, we
1554 punt on the other register too. */
1558 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1560 /* The address of the inner mem is a pseudo or wrong
1561 reg: reload that. */
1562 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1563 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1564 something_reloaded
= true;
1567 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1569 /* Base register is a pseudo or wrong reg: reload it. */
1570 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1571 GET_MODE (x
), VOIDmode
, 0, 0,
1573 something_reloaded
= true;
1576 gcc_assert (something_reloaded
);
1586 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1588 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1589 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1590 out a constant into the constant pool, we will trap this case and
1591 return something a bit more sane. FIXME: Check if this is a bug.
1592 Beware that we must not "override" classes that can be specified as
1593 constraint letters, or else asm operands using them will fail when
1594 they need to be reloaded. FIXME: Investigate whether that constitutes
1598 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1600 if (rclass
!= ACR_REGS
1601 && rclass
!= MOF_REGS
1602 && rclass
!= MOF_SRP_REGS
1603 && rclass
!= SRP_REGS
1604 && rclass
!= CC0_REGS
1605 && rclass
!= SPECIAL_REGS
)
1606 return GENNONACR_REGS
;
1611 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1614 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1615 reg_class_t from
, reg_class_t to
)
1617 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1618 their move cost within that class is higher. How about 7? That's 3
1619 for a move to a GENERAL_REGS register, 3 for the move from the
1620 GENERAL_REGS register, and 1 for the increased register pressure.
1621 Also, it's higher than the memory move cost, as it should.
1622 We also do this for ALL_REGS, since we don't want that class to be
1623 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1624 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1625 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1626 used when a GENERAL_REGS should be used, even if there are call-saved
1627 GENERAL_REGS left to allocate. This is because the fall-back when
1628 the most preferred register class isn't available, isn't the next
1629 (or next good) wider register class, but the *most widest* register
1630 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1632 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1633 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1634 || from
== ALL_REGS
|| to
== ALL_REGS
)
1637 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1638 generally prefer GENERAL_REGS. */
1639 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1640 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1646 /* Worker function for TARGET_MEMORY_MOVE_COST.
1648 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1652 cris_memory_move_cost (machine_mode mode
,
1653 reg_class_t rclass ATTRIBUTE_UNUSED
,
1654 bool in ATTRIBUTE_UNUSED
)
1663 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1664 FIXME: this code is historical; its functionality should be
1665 refactored to look at insn attributes and moved to
1666 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1669 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1671 /* "Normal" means, for:
1676 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1677 register or (v32 and (...) is -32..-1), then CC does not change.
1678 CC_NO_OVERFLOW unless (...) is reg or mem.
1687 (set (reg1) (mem (bdap/biap)))
1688 (set (reg2) (bdap/biap))):
1689 CC is (reg1) and (mem (reg2))
1692 (set (mem (bdap/biap)) (reg1)) [or 0]
1693 (set (reg2) (bdap/biap))):
1696 (where reg and mem includes strict_low_parts variants thereof)
1698 For all others, assume CC is clobbered.
1699 Note that we do not have to care about setting CC_NO_OVERFLOW,
1700 since the overflow flag is set to 0 (i.e. right) for
1701 instructions where it does not have any sane sense, but where
1702 other flags have meanings. (This includes shifts; the carry is
1705 Note that there are other parallel constructs we could match,
1706 but we don't do that yet. */
1708 if (GET_CODE (exp
) == SET
)
1710 /* FIXME: Check when this happens. It looks like we should
1711 actually do a CC_STATUS_INIT here to be safe. */
1712 if (SET_DEST (exp
) == pc_rtx
)
1715 /* Record CC0 changes, so we do not have to output multiple
1717 if (SET_DEST (exp
) == cc0_rtx
)
1721 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1722 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1723 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1725 cc_status
.value1
= SET_SRC (exp
);
1727 /* Handle flags for the special btstq on one bit. */
1728 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1729 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1731 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1733 cc_status
.flags
= CC_INVERTED
;
1735 /* A one-bit btstq. */
1736 cc_status
.flags
= CC_Z_IN_NOT_N
;
1739 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1741 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1742 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1743 /* For some reason gcc will not canonicalize compare
1744 operations, reversing the sign by itself if
1745 operands are in wrong order. */
1746 /* (But NOT inverted; eq is still eq.) */
1747 cc_status
.flags
= CC_REVERSED
;
1749 /* This seems to be overlooked by gcc. FIXME: Check again.
1750 FIXME: Is it really safe? */
1752 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1753 XEXP (SET_SRC (exp
), 0),
1754 XEXP (SET_SRC (exp
), 1));
1758 else if (REG_P (SET_DEST (exp
))
1759 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1760 && REG_P (XEXP (SET_DEST (exp
), 0))))
1762 /* A register is set; normally CC is set to show that no
1763 test insn is needed. Catch the exceptions. */
1765 /* If not to cc0, then no "set"s in non-natural mode give
1767 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1768 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1770 /* ... except add:s and sub:s in DImode. */
1771 if (GET_MODE (SET_DEST (exp
)) == DImode
1772 && (GET_CODE (SET_SRC (exp
)) == PLUS
1773 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1776 cc_status
.value1
= SET_DEST (exp
);
1777 cc_status
.value2
= SET_SRC (exp
);
1779 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1781 cc_status
.value2
= 0;
1783 /* Add and sub may set V, which gets us
1784 unoptimizable results in "gt" and "le" condition
1786 cc_status
.flags
|= CC_NO_OVERFLOW
;
1791 else if (SET_SRC (exp
) == const0_rtx
1792 || (REG_P (SET_SRC (exp
))
1793 && (REGNO (SET_SRC (exp
))
1794 > CRIS_LAST_GENERAL_REGISTER
))
1796 && REG_P (SET_DEST (exp
))
1797 && satisfies_constraint_I (SET_SRC (exp
))))
1799 /* There's no CC0 change for this case. Just check
1801 if (cc_status
.value1
1802 && modified_in_p (cc_status
.value1
, insn
))
1803 cc_status
.value1
= 0;
1805 if (cc_status
.value2
1806 && modified_in_p (cc_status
.value2
, insn
))
1807 cc_status
.value2
= 0;
1814 cc_status
.value1
= SET_DEST (exp
);
1815 cc_status
.value2
= SET_SRC (exp
);
1817 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1819 cc_status
.value2
= 0;
1821 /* Some operations may set V, which gets us
1822 unoptimizable results in "gt" and "le" condition
1824 if (GET_CODE (SET_SRC (exp
)) == PLUS
1825 || GET_CODE (SET_SRC (exp
)) == MINUS
1826 || GET_CODE (SET_SRC (exp
)) == NEG
)
1827 cc_status
.flags
|= CC_NO_OVERFLOW
;
1829 /* For V32, nothing with a register destination sets
1830 C and V usefully. */
1832 cc_status
.flags
|= CC_NO_OVERFLOW
;
1837 else if (MEM_P (SET_DEST (exp
))
1838 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1839 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1841 /* When SET to MEM, then CC is not changed (except for
1843 if (cc_status
.value1
1844 && modified_in_p (cc_status
.value1
, insn
))
1845 cc_status
.value1
= 0;
1847 if (cc_status
.value2
1848 && modified_in_p (cc_status
.value2
, insn
))
1849 cc_status
.value2
= 0;
1854 else if (GET_CODE (exp
) == PARALLEL
)
1856 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1857 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1858 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1860 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1861 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1865 /* For "move.S [rx=ry+o],rz", say CC reflects
1866 value1=rz and value2=[rx] */
1867 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1869 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1870 XEXP (XVECEXP (exp
, 0, 1), 0));
1872 /* Huh? A side-effect cannot change the destination
1874 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1876 internal_error ("internal error: sideeffect-insn affecting main effect");
1878 /* For V32, moves to registers don't set C and V. */
1880 cc_status
.flags
|= CC_NO_OVERFLOW
;
1883 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1884 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1885 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1887 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1888 say flags are not changed, except for overlap. */
1889 if (cc_status
.value1
1890 && modified_in_p (cc_status
.value1
, insn
))
1891 cc_status
.value1
= 0;
1893 if (cc_status
.value2
1894 && modified_in_p (cc_status
.value2
, insn
))
1895 cc_status
.value2
= 0;
1902 /* If we got here, the case wasn't covered by the code above. */
1906 /* This function looks into the pattern to see how this insn affects
1909 Used when to eliminate test insns before a condition-code user,
1910 such as a "scc" insn or a conditional branch. This includes
1911 checking if the entities that cc was updated by, are changed by the
1914 Currently a jumble of the old peek-inside-the-insn and the newer
1915 check-cc-attribute methods. */
1918 cris_notice_update_cc (rtx exp
, rtx_insn
*insn
)
1920 enum attr_cc attrval
= get_attr_cc (insn
);
1922 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1923 to still set CC_REVERSED as below, since that's required by some
1924 compare insn alternatives. (FIXME: GCC should do this virtual
1925 operand swap by itself.) A test-case that may otherwise fail is
1926 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1931 if (attrval
== CC_REV
)
1932 cc_status
.flags
= CC_REVERSED
;
1936 /* Slowly, we're converting to using attributes to control the setting
1937 of condition-code status. */
1941 /* Even if it is "none", a setting may clobber a previous
1942 cc-value, so check. */
1943 if (GET_CODE (exp
) == SET
)
1945 if (cc_status
.value1
1946 && modified_in_p (cc_status
.value1
, insn
))
1947 cc_status
.value1
= 0;
1949 if (cc_status
.value2
1950 && modified_in_p (cc_status
.value2
, insn
))
1951 cc_status
.value2
= 0;
1962 cris_normal_notice_update_cc (exp
, insn
);
1964 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1965 can change bge => bpl and blt => bmi by passing on to the cc0
1966 user that V should not be considered; bgt and ble are taken
1967 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1968 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1969 cc_status
.flags
|= CC_NO_OVERFLOW
;
1973 internal_error ("unknown cc_attr value");
1979 /* Return != 0 if the return sequence for the current function is short,
1980 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1981 registers must be saved, so return 0 then. */
1984 cris_simple_epilogue (void)
1987 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1988 bool got_really_used
= false;
1990 if (! reload_completed
1991 || frame_pointer_needed
1992 || get_frame_size () != 0
1993 || crtl
->args
.pretend_args_size
1995 || crtl
->outgoing_args_size
1996 || crtl
->calls_eh_return
1998 /* If we're not supposed to emit prologue and epilogue, we must
1999 not emit return-type instructions. */
2000 || !TARGET_PROLOGUE_EPILOGUE
)
2003 /* Can't return from stacked return address with v32. */
2004 if (TARGET_V32
&& cris_return_address_on_stack ())
2007 if (crtl
->uses_pic_offset_table
)
2009 push_topmost_sequence ();
2011 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2012 pop_topmost_sequence ();
2015 /* No simple epilogue if there are saved registers. */
2016 for (regno
= 0; regno
< reglimit
; regno
++)
2017 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2023 /* Emit checking that MEM is aligned for an access in MODE, failing
2024 that, executing a "break 8" (or call to abort, if "break 8" is
2028 cris_emit_trap_for_misalignment (rtx mem
)
2030 rtx addr
, reg
, ok_label
, andop
;
2032 int natural_alignment
;
2033 gcc_assert (MEM_P (mem
));
2035 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2036 addr
= XEXP (mem
, 0);
2037 reg
= force_reg (Pmode
, addr
);
2038 ok_label
= gen_label_rtx ();
2040 /* This will yield a btstq without a separate register used, usually -
2041 with the exception for PRE hoisting the "and" but not the branch
2042 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2043 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2044 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2045 NULL_RTX
, Pmode
, 1, ok_label
);
2046 jmp
= get_last_insn ();
2047 gcc_assert (JUMP_P (jmp
));
2049 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2050 expand_builtin_trap ();
2051 emit_label (ok_label
);
2054 /* Expand a return insn (just one insn) marked as using SRP or stack
2055 slot depending on parameter ON_STACK. */
2058 cris_expand_return (bool on_stack
)
2060 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2061 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2062 GCC expect just (return) to do the right thing when optimizing, so
2063 we do that until they're fixed. Currently, all return insns in a
2064 function must be the same (not really a limiting factor) so we need
2065 to check that it doesn't change half-way through. */
2066 emit_jump_insn (ret_rtx
);
2068 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2069 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2071 cfun
->machine
->return_type
2072 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2075 /* Compute a (partial) cost for rtx X. Return true if the complete
2076 cost has been computed, and false if subexpressions should be
2077 scanned. In either case, *TOTAL contains the cost result. */
2080 cris_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno
,
2081 int *total
, bool speed
)
2083 int code
= GET_CODE (x
);
2089 HOST_WIDE_INT val
= INTVAL (x
);
2092 else if (val
< 32 && val
>= -32)
2094 /* Eight or 16 bits are a word and cycle more expensive. */
2095 else if (val
<= 32767 && val
>= -32768)
2097 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2098 another word. FIXME: This isn't linear to 16 bits. */
2114 if (x
!= CONST0_RTX (mode
== VOIDmode
? DImode
: mode
))
2117 /* Make 0.0 cheap, else test-insns will not be used. */
2122 /* If we have one arm of an ADDI, make sure it gets the cost of
2123 one insn, i.e. zero cost for this operand, and just the cost
2124 of the PLUS, as the insn is created by combine from a PLUS
2125 and an ASHIFT, and the MULT cost below would make the
2126 combined value be larger than the separate insns. The insn
2127 validity is checked elsewhere by combine.
2129 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2130 function should be rewritten. */
2131 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2137 /* Identify values that are no powers of two. Powers of 2 are
2138 taken care of already and those values should not be changed. */
2139 if (!CONST_INT_P (XEXP (x
, 1))
2140 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2142 /* If we have a multiply insn, then the cost is between
2143 1 and 2 "fast" instructions. */
2144 if (TARGET_HAS_MUL_INSNS
)
2146 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2150 /* Estimate as 4 + 4 * #ofbits. */
2151 *total
= COSTS_N_INSNS (132);
2160 if (!CONST_INT_P (XEXP (x
, 1))
2161 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2163 /* Estimate this as 4 + 8 * #of bits. */
2164 *total
= COSTS_N_INSNS (260);
2170 if (CONST_INT_P (XEXP (x
, 1))
2171 /* Two constants may actually happen before optimization. */
2172 && !CONST_INT_P (XEXP (x
, 0))
2173 && !satisfies_constraint_I (XEXP (x
, 1)))
2176 = (rtx_cost (XEXP (x
, 0), mode
, (enum rtx_code
) outer_code
,
2178 + 2 * GET_MODE_NUNITS (mode
));
2184 if (outer_code
!= COMPARE
)
2188 case ZERO_EXTEND
: case SIGN_EXTEND
:
2189 *total
= rtx_cost (XEXP (x
, 0), VOIDmode
, (enum rtx_code
) outer_code
,
2198 /* The ADDRESS_COST worker. */
2201 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2202 addr_space_t as ATTRIBUTE_UNUSED
,
2203 bool speed ATTRIBUTE_UNUSED
)
2205 /* The metric to use for the cost-macros is unclear.
2206 The metric used here is (the number of cycles needed) / 2,
2207 where we consider equal a cycle for a word of code and a cycle to
2208 read memory. FIXME: Adding "+ 1" to all values would avoid
2209 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2210 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2211 Unfortunately(?) such a hack would expose other pessimizations,
2212 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2213 loop there, without apparent reason. */
2215 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2216 if (cris_base_or_autoincr_p (x
, false))
2219 /* An indirect mem must be a DIP. This means two bytes extra for code,
2220 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2224 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2225 an extra DIP prefix and 4 bytes of constant in most cases. */
2229 /* Handle BIAP and BDAP prefixes. */
2230 if (GET_CODE (x
) == PLUS
)
2232 rtx tem1
= XEXP (x
, 0);
2233 rtx tem2
= XEXP (x
, 1);
2235 /* Local extended canonicalization rule: the first operand must
2236 be REG, unless it's an operation (MULT). */
2237 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2238 tem1
= tem2
, tem2
= XEXP (x
, 0);
2240 /* We'll "assume" we have canonical RTX now. */
2241 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2243 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2244 recognize the typical MULT which is always in tem1 because of
2245 insn canonicalization. */
2246 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2250 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2251 PLUS is always found in tem2. */
2252 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2255 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2257 if (satisfies_constraint_L (tem2
))
2260 /* A BDAP with some other constant is 2 bytes extra. */
2261 if (CRIS_CONSTANT_P (tem2
))
2262 return (2 + 2 + 2) / 2;
2264 /* BDAP with something indirect should have a higher cost than
2265 BIAP with register. FIXME: Should it cost like a MEM or more? */
2266 return (2 + 2 + 2) / 2;
2269 /* What else? Return a high cost. It matters only for valid
2270 addressing modes. */
2274 /* Check various objections to the side-effect. Used in the test-part
2275 of an anonymous insn describing an insn with a possible side-effect.
2276 Returns nonzero if the implied side-effect is ok.
2279 ops : An array of rtx:es. lreg, rreg, rval,
2280 The variables multop and other_op are indexes into this,
2281 or -1 if they are not applicable.
2282 lreg : The register that gets assigned in the side-effect.
2283 rreg : One register in the side-effect expression
2284 rval : The other register, or an int.
2285 multop : An integer to multiply rval with.
2286 other_op : One of the entities of the main effect,
2287 whose mode we must consider. */
2290 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2291 int lreg
, int rreg
, int rval
,
2292 int multop
, int other_op
)
2294 /* Find what value to multiply with, for rx =ry + rz * n. */
2295 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2297 rtx reg_rtx
= ops
[rreg
];
2298 rtx val_rtx
= ops
[rval
];
2300 /* The operands may be swapped. Canonicalize them in reg_rtx and
2301 val_rtx, where reg_rtx always is a reg (for this constraint to
2303 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2304 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2306 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2307 we have no business. */
2308 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2311 /* Don't do this when -mno-split. */
2312 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2315 /* The mult expression may be hidden in lreg. FIXME: Add more
2316 commentary about that. */
2317 if (GET_CODE (val_rtx
) == MULT
)
2319 mult
= INTVAL (XEXP (val_rtx
, 1));
2320 val_rtx
= XEXP (val_rtx
, 0);
2324 /* First check the "other operand". */
2327 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2330 /* Check if the lvalue register is the same as the "other
2331 operand". If so, the result is undefined and we shouldn't do
2332 this. FIXME: Check again. */
2333 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2334 && cris_base_p (ops
[other_op
],
2335 reload_in_progress
|| reload_completed
)
2336 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2337 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2341 /* Do not accept frame_pointer_rtx as any operand. */
2342 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2343 || ops
[rval
] == frame_pointer_rtx
2344 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2348 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2351 /* Do not allow rx = rx + n if a normal add or sub with same size
2353 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2354 && CONST_INT_P (val_rtx
)
2355 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2358 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2359 if (CRIS_CONSTANT_P (val_rtx
))
2363 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2364 reload_in_progress
|| reload_completed
))
2367 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2368 && MEM_P (XEXP (val_rtx
, 0))
2369 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2370 reload_in_progress
|| reload_completed
))
2373 /* If we got here, it's not a valid addressing mode. */
2376 else if (code
== MULT
2378 && cris_base_p (val_rtx
,
2379 reload_in_progress
|| reload_completed
)))
2381 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2382 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2383 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2386 /* Do not allow bad multiply-values. */
2387 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2390 /* Only allow r + ... */
2391 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2394 /* If we got here, all seems ok.
2395 (All checks need to be done above). */
2399 /* If we get here, the caller got its initial tests wrong. */
2400 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2403 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2404 insn for other reasons. */
2407 cris_cc0_user_requires_cmp (rtx_insn
*insn
)
2409 rtx_insn
*cc0_user
= NULL
;
2413 gcc_assert (insn
!= NULL
);
2418 cc0_user
= next_cc0_user (insn
);
2419 if (cc0_user
== NULL
)
2422 body
= PATTERN (cc0_user
);
2423 set
= single_set (cc0_user
);
2425 /* Users can be sCC and bCC. */
2426 if (JUMP_P (cc0_user
)
2427 && GET_CODE (body
) == SET
2428 && SET_DEST (body
) == pc_rtx
2429 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2430 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2433 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2434 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2439 GET_CODE (SET_SRC (body
)) == GT
2440 || GET_CODE (SET_SRC (body
)) == LE
;
2446 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2447 does not handle the case where the IN operand is strict_low_part; it
2448 does handle it for X. Test-case in Axis-20010516. This function takes
2449 care of that for THIS port. FIXME: strict_low_part is going away
2453 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2455 /* The function reg_overlap_mentioned now handles when X is
2456 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2457 if (GET_CODE (in
) == STRICT_LOW_PART
)
2460 return reg_overlap_mentioned_p (x
, in
);
2463 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2464 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2468 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2470 gcc_assert (flag_pic
);
2472 switch (GET_CODE (x
))
2481 if (GET_CODE (x
) != CONST
)
2486 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2487 if (GET_CODE (x
) == PLUS
2488 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2489 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2490 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2491 && CONST_INT_P (XEXP (x
, 1)))
2494 if (GET_CODE (x
) == UNSPEC
)
2495 switch (XINT (x
, 1))
2497 /* A PCREL operand is only valid for call and movsi. */
2498 case CRIS_UNSPEC_PLT_PCREL
:
2499 case CRIS_UNSPEC_PCREL
:
2500 return !any_operand
;
2502 case CRIS_UNSPEC_PLT_GOTREL
:
2503 case CRIS_UNSPEC_PLTGOTREAD
:
2504 case CRIS_UNSPEC_GOTREAD
:
2505 case CRIS_UNSPEC_GOTREL
:
2511 return cris_symbol_type_of (x
) == cris_no_symbol
;
2514 /* Helper function to find the right symbol-type to generate,
2515 given the original (non-PIC) representation. */
2517 enum cris_symbol_type
2518 cris_symbol_type_of (const_rtx x
)
2520 switch (GET_CODE (x
))
2524 ? (SYMBOL_REF_LOCAL_P (x
)
2525 ? cris_rel_symbol
: cris_got_symbol
)
2526 : cris_offsettable_symbol
;
2529 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2532 return cris_symbol_type_of (XEXP (x
, 0));
2537 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2538 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2540 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2542 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2543 return cris_got_symbol_needing_fixup
;
2545 return t1
!= cris_no_symbol
? t1
: t2
;
2550 return cris_no_symbol
;
2556 fatal_insn ("unrecognized supposed constant", x
);
2562 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2565 cris_legitimate_pic_operand (rtx x
)
2567 /* Symbols are not valid PIC operands as-is; just constants. */
2568 return cris_valid_pic_const (x
, true);
2571 /* Queue an .ident string in the queue of top-level asm statements.
2572 If the front-end is done, we must be being called from toplev.c.
2573 In that case, do nothing. */
2575 cris_asm_output_ident (const char *string
)
2577 if (symtab
->state
!= PARSING
)
2580 default_asm_output_ident_directive (string
);
2583 /* The ASM_OUTPUT_CASE_END worker. */
2586 cris_asm_output_case_end (FILE *stream
, int num
, rtx_insn
*table
)
2588 /* Step back, over the label for the table, to the actual casejump and
2589 assert that we find only what's expected. */
2590 rtx_insn
*whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2591 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2592 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2593 gcc_assert (whole_jump_insn
!= NULL_RTX
2594 && (JUMP_P (whole_jump_insn
)
2595 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2596 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2597 /* Get the pattern of the casejump, so we can extract the default label. */
2598 rtx whole_jump_pat
= PATTERN (whole_jump_insn
);
2602 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2603 filled. We also output the offset word a little differently. */
2605 = (GET_CODE (whole_jump_pat
) == SEQUENCE
2606 ? PATTERN (XVECEXP (whole_jump_pat
, 0, 0)) : whole_jump_pat
);
2608 asm_fprintf (stream
,
2609 "\t.word %LL%d-.%s\n",
2610 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2611 (parallel_jump
, 0, 0),
2613 (TARGET_PDEBUG
? "; default" : ""));
2617 asm_fprintf (stream
,
2618 "\t.word %LL%d-%LL%d%s\n",
2619 CODE_LABEL_NUMBER (XEXP
2621 (XEXP (XVECEXP (whole_jump_pat
, 0, 0), 1),
2624 (TARGET_PDEBUG
? "; default" : ""));
2627 /* The TARGET_OPTION_OVERRIDE worker.
2628 As is the norm, this also parses -mfoo=bar type parameters. */
2631 cris_option_override (void)
2633 if (cris_max_stackframe_str
)
2635 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2637 /* Do some sanity checking. */
2638 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2639 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2640 cris_max_stackframe
, 0x20000000);
2643 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2644 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2645 cris_cpu_version
= CRIS_CPU_SVINTO
;
2646 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2647 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2649 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2653 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2655 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2656 cris_cpu_version
= 3;
2658 if (strcmp ("svinto", cris_cpu_str
) == 0
2659 || strcmp ("etrax100", cris_cpu_str
) == 0)
2660 cris_cpu_version
= 8;
2662 if (strcmp ("ng", cris_cpu_str
) == 0
2663 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2664 cris_cpu_version
= 10;
2666 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2667 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2670 /* Set the target flags. */
2671 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2672 target_flags
|= MASK_ETRAX4_ADD
;
2674 /* If this is Svinto or higher, align for 32 bit accesses. */
2675 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2677 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2678 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2681 /* Note that we do not add new flags when it can be completely
2682 described with a macro that uses -mcpu=X. So
2683 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2689 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2691 if (strcmp ("etrax4", cris_tune_str
) == 0)
2694 if (strcmp ("svinto", cris_tune_str
) == 0
2695 || strcmp ("etrax100", cris_tune_str
) == 0)
2698 if (strcmp ("ng", cris_tune_str
) == 0
2699 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2702 if (cris_tune
< 0 || cris_tune
> 32)
2703 error ("unknown CRIS cpu version specification in -mtune= : %s",
2706 if (cris_tune
>= CRIS_CPU_SVINTO
)
2707 /* We have currently nothing more to tune than alignment for
2710 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2711 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2714 if (cris_cpu_version
>= CRIS_CPU_V32
)
2715 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2719 /* Use error rather than warning, so invalid use is easily
2720 detectable. Still change to the values we expect, to avoid
2724 error ("-fPIC and -fpic are not supported in this configuration");
2728 /* Turn off function CSE. We need to have the addresses reach the
2729 call expanders to get PLT-marked, as they could otherwise be
2730 compared against zero directly or indirectly. After visiting the
2731 call expanders they will then be cse:ed, as the call expanders
2732 force_reg the addresses, effectively forcing flag_no_function_cse
2734 flag_no_function_cse
= 1;
2737 /* Set the per-function-data initializer. */
2738 init_machine_status
= cris_init_machine_status
;
2741 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2744 cris_asm_output_mi_thunk (FILE *stream
,
2745 tree thunkdecl ATTRIBUTE_UNUSED
,
2746 HOST_WIDE_INT delta
,
2747 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2750 /* Make sure unwind info is emitted for the thunk if needed. */
2751 final_start_function (emit_barrier (), stream
, 1);
2754 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2755 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2756 reg_names
[CRIS_FIRST_ARG_REG
]);
2758 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2759 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2760 reg_names
[CRIS_FIRST_ARG_REG
]);
2764 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2766 name
= (* targetm
.strip_name_encoding
) (name
);
2770 fprintf (stream
, "\tba ");
2771 assemble_name (stream
, name
);
2772 fprintf (stream
, "%s\n\tnop\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2776 fprintf (stream
, "\tadd.d ");
2777 assemble_name (stream
, name
);
2778 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2783 fprintf (stream
, "\tjump ");
2784 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2785 fprintf (stream
, "\n");
2788 fprintf (stream
, "\tnop\n");
2791 final_end_function ();
2794 /* Boilerplate emitted at start of file.
2796 NO_APP *only at file start* means faster assembly. It also means
2797 comments are not allowed. In some cases comments will be output
2798 for debugging purposes. Make sure they are allowed then. */
2800 cris_file_start (void)
2802 /* These expressions can vary at run time, so we cannot put
2803 them into TARGET_INITIALIZER. */
2804 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2806 default_file_start ();
2809 /* Output that goes at the end of the file, similarly. */
2812 cris_file_end (void)
2814 /* For CRIS, the default is to assume *no* executable stack, so output
2815 an executable-stack-note only when needed. */
2816 if (TARGET_LINUX
&& trampolines_created
)
2817 file_end_indicate_exec_stack ();
2820 /* Rename the function calls for integer multiply and divide. */
2822 cris_init_libfuncs (void)
2824 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2825 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2826 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2827 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2828 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2830 /* Atomic data being unaligned is unfortunately a reality.
2832 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2834 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2835 "__cris_atcmpxchgr32");
2836 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2837 "__cris_atcmpxchgr16");
2841 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2845 cris_init_expanders (void)
2847 /* Nothing here at the moment. */
2850 /* Zero initialization is OK for all current fields. */
2852 static struct machine_function
*
2853 cris_init_machine_status (void)
2855 return ggc_cleared_alloc
<machine_function
> ();
2858 /* Split a 2 word move (DI or presumably DF) into component parts.
2859 Originally a copy of gen_split_move_double in m32r.c. */
2862 cris_split_movdx (rtx
*operands
)
2864 machine_mode mode
= GET_MODE (operands
[0]);
2865 rtx dest
= operands
[0];
2866 rtx src
= operands
[1];
2869 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2870 longer happen; after reload there are no SUBREGs any more, and we're
2871 only called after reload. */
2872 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2877 int dregno
= REGNO (dest
);
2879 /* Reg-to-reg copy. */
2882 int sregno
= REGNO (src
);
2884 int reverse
= (dregno
== sregno
+ 1);
2886 /* We normally copy the low-numbered register first. However, if
2887 the first register operand 0 is the same as the second register of
2888 operand 1, we must copy in the opposite order. */
2889 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
2890 operand_subword (src
, reverse
, TRUE
, mode
)));
2892 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
2893 operand_subword (src
, !reverse
, TRUE
, mode
)));
2895 /* Constant-to-reg copy. */
2896 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2899 split_double (src
, &words
[0], &words
[1]);
2900 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
2903 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
2906 /* Mem-to-reg copy. */
2907 else if (MEM_P (src
))
2909 /* If the high-address word is used in the address, we must load it
2910 last. Otherwise, load it first. */
2911 rtx addr
= XEXP (src
, 0);
2912 int reverse
= (refers_to_regno_p (dregno
, addr
) != 0);
2914 /* The original code implies that we can't do
2915 move.x [rN+],rM move.x [rN],rM+1
2916 when rN is dead, because of REG_NOTES damage. That is
2917 consistent with what I've seen, so don't try it.
2919 We have two different cases here; if the addr is POST_INC,
2920 just pass it through, otherwise add constants. */
2922 if (GET_CODE (addr
) == POST_INC
)
2927 /* Whenever we emit insns with post-incremented
2928 addresses ourselves, we must add a post-inc note
2930 mem
= change_address (src
, SImode
, addr
);
2932 = gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
), mem
);
2933 insn
= emit_insn (insn
);
2934 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2936 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2939 mem
= copy_rtx (mem
);
2941 = gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
), mem
);
2942 insn
= emit_insn (insn
);
2943 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2945 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2950 /* Make sure we don't get any other addresses with
2951 embedded postincrements. They should be stopped in
2952 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2954 if (side_effects_p (addr
))
2955 fatal_insn ("unexpected side-effects in address", addr
);
2957 emit_insn (gen_rtx_SET
2958 (operand_subword (dest
, reverse
, TRUE
, mode
),
2961 plus_constant (Pmode
, addr
,
2962 reverse
* UNITS_PER_WORD
))));
2963 emit_insn (gen_rtx_SET
2964 (operand_subword (dest
, ! reverse
, TRUE
, mode
),
2967 plus_constant (Pmode
, addr
,
2973 internal_error ("unknown src");
2975 /* Reg-to-mem copy or clear mem. */
2976 else if (MEM_P (dest
)
2978 || src
== const0_rtx
2979 || src
== CONST0_RTX (DFmode
)))
2981 rtx addr
= XEXP (dest
, 0);
2983 if (GET_CODE (addr
) == POST_INC
)
2988 /* Whenever we emit insns with post-incremented addresses
2989 ourselves, we must add a post-inc note manually. */
2990 mem
= change_address (dest
, SImode
, addr
);
2992 = gen_rtx_SET (mem
, operand_subword (src
, 0, TRUE
, mode
));
2993 insn
= emit_insn (insn
);
2994 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2996 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2999 mem
= copy_rtx (mem
);
3000 insn
= gen_rtx_SET (mem
, operand_subword (src
, 1, TRUE
, mode
));
3001 insn
= emit_insn (insn
);
3002 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3004 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3009 /* Make sure we don't get any other addresses with embedded
3010 postincrements. They should be stopped in
3011 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3012 if (side_effects_p (addr
))
3013 fatal_insn ("unexpected side-effects in address", addr
);
3015 emit_insn (gen_rtx_SET
3016 (change_address (dest
, SImode
, addr
),
3017 operand_subword (src
, 0, TRUE
, mode
)));
3019 emit_insn (gen_rtx_SET
3020 (change_address (dest
, SImode
,
3021 plus_constant (Pmode
, addr
,
3023 operand_subword (src
, 1, TRUE
, mode
)));
3028 internal_error ("unknown dest");
3035 /* The expander for the prologue pattern name. */
3038 cris_expand_prologue (void)
3041 int size
= get_frame_size ();
3042 /* Shorten the used name for readability. */
3043 int cfoa_size
= crtl
->outgoing_args_size
;
3044 int last_movem_reg
= -1;
3047 int return_address_on_stack
= cris_return_address_on_stack ();
3048 int got_really_used
= false;
3049 int n_movem_regs
= 0;
3050 int pretend
= crtl
->args
.pretend_args_size
;
3052 /* Don't do anything if no prologues or epilogues are wanted. */
3053 if (!TARGET_PROLOGUE_EPILOGUE
)
3056 CRIS_ASSERT (size
>= 0);
3058 if (crtl
->uses_pic_offset_table
)
3060 /* A reference may have been optimized out (like the abort () in
3061 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3063 push_topmost_sequence ();
3065 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3066 pop_topmost_sequence ();
3069 /* Align the size to what's best for the CPU model. */
3070 if (TARGET_STACK_ALIGN
)
3071 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3075 /* See also cris_setup_incoming_varargs where
3076 cfun->machine->stdarg_regs is set. There are other setters of
3077 crtl->args.pretend_args_size than stdarg handling, like
3078 for an argument passed with parts in R13 and stack. We must
3079 not store R13 into the pretend-area for that case, as GCC does
3080 that itself. "Our" store would be marked as redundant and GCC
3081 will attempt to remove it, which will then be flagged as an
3082 internal error; trying to remove a frame-related insn. */
3083 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3085 framesize
+= pretend
;
3087 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3089 regno
--, pretend
-= 4, stdarg_regs
--)
3091 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3092 plus_constant (Pmode
,
3095 /* FIXME: When dwarf2 frame output and unless asynchronous
3096 exceptions, make dwarf2 bundle together all stack
3097 adjustments like it does for registers between stack
3099 RTX_FRAME_RELATED_P (insn
) = 1;
3101 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3102 set_mem_alias_set (mem
, get_varargs_alias_set ());
3103 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
3105 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3106 the value isn't restored, so we don't want to tell dwarf2
3107 that it's been stored to stack, else EH handling info would
3111 /* For other setters of crtl->args.pretend_args_size, we
3112 just adjust the stack by leaving the remaining size in
3113 "pretend", handled below. */
3116 /* Save SRP if not a leaf function. */
3117 if (return_address_on_stack
)
3119 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3120 plus_constant (Pmode
, stack_pointer_rtx
,
3123 RTX_FRAME_RELATED_P (insn
) = 1;
3125 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3126 set_mem_alias_set (mem
, get_frame_alias_set ());
3127 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3128 RTX_FRAME_RELATED_P (insn
) = 1;
3132 /* Set up the frame pointer, if needed. */
3133 if (frame_pointer_needed
)
3135 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3136 plus_constant (Pmode
, stack_pointer_rtx
,
3139 RTX_FRAME_RELATED_P (insn
) = 1;
3141 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3142 set_mem_alias_set (mem
, get_frame_alias_set ());
3143 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3144 RTX_FRAME_RELATED_P (insn
) = 1;
3146 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3147 RTX_FRAME_RELATED_P (insn
) = 1;
3152 /* Between frame-pointer and saved registers lie the area for local
3153 variables. If we get here with "pretended" size remaining, count
3154 it into the general stack size. */
3157 /* Get a contiguous sequence of registers, starting with R0, that need
3159 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3161 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3165 /* Check if movem may be used for registers so far. */
3166 if (regno
== last_movem_reg
+ 1)
3167 /* Yes, update next expected register. */
3168 last_movem_reg
= regno
;
3171 /* We cannot use movem for all registers. We have to flush
3172 any movem:ed registers we got so far. */
3173 if (last_movem_reg
!= -1)
3176 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3178 /* It is a win to use a side-effect assignment for
3179 64 <= size <= 128. But side-effect on movem was
3180 not usable for CRIS v0..3. Also only do it if
3181 side-effects insns are allowed. */
3182 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3183 && (last_movem_reg
+ 1) * 4 + size
<= 128
3184 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3185 && TARGET_SIDE_EFFECT_PREFIXES
)
3188 = gen_rtx_MEM (SImode
,
3189 plus_constant (Pmode
, stack_pointer_rtx
,
3190 -(n_saved
* 4 + size
)));
3191 set_mem_alias_set (mem
, get_frame_alias_set ());
3193 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3194 -(n_saved
* 4 + size
),
3200 = gen_rtx_SET (stack_pointer_rtx
,
3201 plus_constant (Pmode
, stack_pointer_rtx
,
3202 -(n_saved
* 4 + size
)));
3203 insn
= emit_insn (insn
);
3204 RTX_FRAME_RELATED_P (insn
) = 1;
3206 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3207 set_mem_alias_set (mem
, get_frame_alias_set ());
3208 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3212 framesize
+= n_saved
* 4 + size
;
3213 last_movem_reg
= -1;
3217 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3218 plus_constant (Pmode
,
3221 RTX_FRAME_RELATED_P (insn
) = 1;
3223 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3224 set_mem_alias_set (mem
, get_frame_alias_set ());
3225 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
3226 RTX_FRAME_RELATED_P (insn
) = 1;
3228 framesize
+= 4 + size
;
3234 /* Check after, if we could movem all registers. This is the normal case. */
3235 if (last_movem_reg
!= -1)
3238 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3240 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3241 do it if side-effects insns are allowed. */
3242 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3243 && (last_movem_reg
+ 1) * 4 + size
<= 128
3244 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3245 && TARGET_SIDE_EFFECT_PREFIXES
)
3248 = gen_rtx_MEM (SImode
,
3249 plus_constant (Pmode
, stack_pointer_rtx
,
3250 -(n_saved
* 4 + size
)));
3251 set_mem_alias_set (mem
, get_frame_alias_set ());
3252 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3253 -(n_saved
* 4 + size
), true);
3258 = gen_rtx_SET (stack_pointer_rtx
,
3259 plus_constant (Pmode
, stack_pointer_rtx
,
3260 -(n_saved
* 4 + size
)));
3261 insn
= emit_insn (insn
);
3262 RTX_FRAME_RELATED_P (insn
) = 1;
3264 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3265 set_mem_alias_set (mem
, get_frame_alias_set ());
3266 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3269 framesize
+= n_saved
* 4 + size
;
3270 /* We have to put outgoing argument space after regs. */
3273 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3274 plus_constant (Pmode
,
3277 RTX_FRAME_RELATED_P (insn
) = 1;
3278 framesize
+= cfoa_size
;
3281 else if ((size
+ cfoa_size
) > 0)
3283 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3284 plus_constant (Pmode
,
3286 -(cfoa_size
+ size
))));
3287 RTX_FRAME_RELATED_P (insn
) = 1;
3288 framesize
+= size
+ cfoa_size
;
3291 /* Set up the PIC register, if it is used. */
3292 if (got_really_used
)
3295 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3296 emit_move_insn (pic_offset_table_rtx
, got
);
3298 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3299 follow exceptional paths and tries to delete the GOT load as
3300 unused, if it isn't used on the non-exceptional paths. Other
3301 ports have similar or other cover-ups, or plain bugs marking
3302 the GOT register load as maybe-dead. To see this, remove the
3303 line below and try libsupc++/vec.cc or a trivial
3304 "static void y (); void x () {try {y ();} catch (...) {}}". */
3305 emit_use (pic_offset_table_rtx
);
3308 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3309 warning (0, "stackframe too big: %d bytes", framesize
);
3312 /* The expander for the epilogue pattern. */
3315 cris_expand_epilogue (void)
3318 int size
= get_frame_size ();
3319 int last_movem_reg
= -1;
3320 int argspace_offset
= crtl
->outgoing_args_size
;
3321 int pretend
= crtl
->args
.pretend_args_size
;
3323 bool return_address_on_stack
= cris_return_address_on_stack ();
3324 /* A reference may have been optimized out
3325 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3326 so check that it's still used. */
3327 int got_really_used
= false;
3328 int n_movem_regs
= 0;
3330 if (!TARGET_PROLOGUE_EPILOGUE
)
3333 if (crtl
->uses_pic_offset_table
)
3335 /* A reference may have been optimized out (like the abort () in
3336 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3338 push_topmost_sequence ();
3340 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3341 pop_topmost_sequence ();
3344 /* Align byte count of stack frame. */
3345 if (TARGET_STACK_ALIGN
)
3346 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3348 /* Check how many saved regs we can movem. They start at r0 and must
3351 regno
< FIRST_PSEUDO_REGISTER
;
3353 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3357 if (regno
== last_movem_reg
+ 1)
3358 last_movem_reg
= regno
;
3363 /* If there was only one register that really needed to be saved
3364 through movem, don't use movem. */
3365 if (n_movem_regs
== 1)
3366 last_movem_reg
= -1;
3368 /* Now emit "normal" move insns for all regs higher than the movem
3370 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3371 regno
> last_movem_reg
;
3373 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3377 if (argspace_offset
)
3379 /* There is an area for outgoing parameters located before
3380 the saved registers. We have to adjust for that. */
3381 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3382 plus_constant (Pmode
, stack_pointer_rtx
,
3384 /* Make sure we only do this once. */
3385 argspace_offset
= 0;
3388 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3389 stack_pointer_rtx
));
3390 set_mem_alias_set (mem
, get_frame_alias_set ());
3391 insn
= emit_move_insn (gen_raw_REG (SImode
, regno
), mem
);
3393 /* Whenever we emit insns with post-incremented addresses
3394 ourselves, we must add a post-inc note manually. */
3396 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3399 /* If we have any movem-restore, do it now. */
3400 if (last_movem_reg
!= -1)
3404 if (argspace_offset
)
3406 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3407 plus_constant (Pmode
, stack_pointer_rtx
,
3409 argspace_offset
= 0;
3412 mem
= gen_rtx_MEM (SImode
,
3413 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3414 set_mem_alias_set (mem
, get_frame_alias_set ());
3416 = emit_insn (cris_gen_movem_load (mem
,
3417 GEN_INT (last_movem_reg
+ 1), 0));
3418 /* Whenever we emit insns with post-incremented addresses
3419 ourselves, we must add a post-inc note manually. */
3420 if (side_effects_p (PATTERN (insn
)))
3422 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3425 /* If we don't clobber all of the allocated stack area (we've already
3426 deallocated saved registers), GCC might want to schedule loads from
3427 the stack to *after* the stack-pointer restore, which introduces an
3428 interrupt race condition. This happened for the initial-value
3429 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3430 other failure for that test). It also happened for the stack slot
3431 for the return value in (one version of)
3432 linux/fs/dcache.c:__d_lookup, at least with "-O2
3433 -fno-omit-frame-pointer". */
3435 /* Restore frame pointer if necessary. */
3436 if (frame_pointer_needed
)
3440 emit_insn (gen_cris_frame_deallocated_barrier ());
3442 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3443 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3444 stack_pointer_rtx
));
3445 set_mem_alias_set (mem
, get_frame_alias_set ());
3446 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3448 /* Whenever we emit insns with post-incremented addresses
3449 ourselves, we must add a post-inc note manually. */
3451 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3453 else if ((size
+ argspace_offset
) != 0)
3455 emit_insn (gen_cris_frame_deallocated_barrier ());
3457 /* If there was no frame-pointer to restore sp from, we must
3458 explicitly deallocate local variables. */
3460 /* Handle space for outgoing parameters that hasn't been handled
3462 size
+= argspace_offset
;
3464 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3465 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3468 /* If this function has no pushed register parameters
3469 (stdargs/varargs), and if it is not a leaf function, then we have
3470 the return address on the stack. */
3471 if (return_address_on_stack
&& pretend
== 0)
3473 if (TARGET_V32
|| crtl
->calls_eh_return
)
3477 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3478 mem
= gen_rtx_MEM (SImode
,
3479 gen_rtx_POST_INC (SImode
,
3480 stack_pointer_rtx
));
3481 set_mem_alias_set (mem
, get_frame_alias_set ());
3482 insn
= emit_move_insn (srpreg
, mem
);
3484 /* Whenever we emit insns with post-incremented addresses
3485 ourselves, we must add a post-inc note manually. */
3487 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3489 if (crtl
->calls_eh_return
)
3490 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3492 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3493 cris_expand_return (false);
3496 cris_expand_return (true);
3501 /* If we pushed some register parameters, then adjust the stack for
3505 /* If SRP is stored on the way, we need to restore it first. */
3506 if (return_address_on_stack
)
3509 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3512 mem
= gen_rtx_MEM (SImode
,
3513 gen_rtx_POST_INC (SImode
,
3514 stack_pointer_rtx
));
3515 set_mem_alias_set (mem
, get_frame_alias_set ());
3516 insn
= emit_move_insn (srpreg
, mem
);
3518 /* Whenever we emit insns with post-incremented addresses
3519 ourselves, we must add a post-inc note manually. */
3521 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3524 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3525 plus_constant (Pmode
, stack_pointer_rtx
,
3529 /* Perform the "physical" unwinding that the EH machinery calculated. */
3530 if (crtl
->calls_eh_return
)
3531 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3533 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3534 cris_expand_return (false);
3537 /* Worker function for generating movem from mem for load_multiple. */
3540 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3542 int nregs
= INTVAL (nregs_rtx
);
3546 rtx srcreg
= XEXP (src
, 0);
3547 unsigned int regno
= nregs
- 1;
3556 if (GET_CODE (srcreg
) == POST_INC
)
3557 srcreg
= XEXP (srcreg
, 0);
3559 CRIS_ASSERT (REG_P (srcreg
));
3561 /* Don't use movem for just one insn. The insns are equivalent except
3562 for the pipeline hazard (on v32); movem does not forward the loaded
3563 registers so there's a three cycles penalty for their use. */
3565 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3567 vec
= rtvec_alloc (nprefix
+ nregs
3568 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3570 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3572 RTVEC_ELT (vec
, nprefix
+ 1)
3573 = gen_rtx_SET (srcreg
, plus_constant (Pmode
, srcreg
, nregs
* 4));
3577 src
= replace_equiv_address (src
, srcreg
);
3578 RTVEC_ELT (vec
, nprefix
)
3579 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
), src
);
3582 for (i
= 1; i
< nregs
; i
++, eltno
++)
3584 RTVEC_ELT (vec
, nprefix
+ eltno
)
3585 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
),
3586 adjust_address_nv (src
, SImode
, i
* 4));
3590 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3593 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3594 are added that the dwarf2 machinery understands. */
3597 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3600 int nregs
= INTVAL (nregs_rtx
);
3605 rtx destreg
= XEXP (dest
, 0);
3606 unsigned int regno
= nregs
- 1;
3615 if (GET_CODE (destreg
) == POST_INC
)
3616 increment
+= nregs
* 4;
3618 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3619 destreg
= XEXP (destreg
, 0);
3621 CRIS_ASSERT (REG_P (destreg
));
3623 /* Don't use movem for just one insn. The insns are equivalent except
3624 for the pipeline hazard (on v32); movem does not forward the loaded
3625 registers so there's a three cycles penalty for use. */
3628 rtx mov
= gen_rtx_SET (dest
, gen_rtx_REG (SImode
, 0));
3632 insn
= emit_insn (mov
);
3634 RTX_FRAME_RELATED_P (insn
) = 1;
3638 /* If there was a request for a side-effect, create the ordinary
3640 vec
= rtvec_alloc (2);
3642 RTVEC_ELT (vec
, 0) = mov
;
3643 RTVEC_ELT (vec
, 1) = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3647 RTX_FRAME_RELATED_P (mov
) = 1;
3648 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3653 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3655 = gen_rtx_SET (replace_equiv_address (dest
,
3656 plus_constant (Pmode
, destreg
,
3658 gen_rtx_REG (SImode
, regno
));
3661 /* The dwarf2 info wants this mark on each component in a parallel
3662 that's part of the prologue (though it's optional on the first
3665 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3670 = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3672 ? increment
: nregs
* 4));
3676 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3678 /* Don't call adjust_address_nv on a post-incremented address if
3680 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3681 dest
= replace_equiv_address (dest
, destreg
);
3684 for (i
= 1; i
< nregs
; i
++, eltno
++)
3686 RTVEC_ELT (vec
, eltno
)
3687 = gen_rtx_SET (adjust_address_nv (dest
, SImode
, i
* 4),
3688 gen_rtx_REG (SImode
, regno
));
3690 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3695 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3697 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3698 we need to keep the stack adjustment separate, after the
3699 MEM-setters. Else the stack-adjustment in the second component of
3700 the parallel would be mishandled; the offsets for the SETs that
3701 follow it would be wrong. We prepare for this by adding a
3702 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3703 followed by the increment. Note that we have FRAME_RELATED_P on
3704 all the SETs, including the original stack adjustment SET in the
3710 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3711 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3712 for (i
= 1; i
< nregs
; i
++)
3714 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3715 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3716 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3719 RTX_FRAME_RELATED_P (insn
) = 1;
3725 /* Worker function for expanding the address for PIC function calls. */
3728 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3732 gcc_assert (flag_pic
&& MEM_P (op
));
3735 /* It might be that code can be generated that jumps to 0 (or to a
3736 specific address). Don't die on that. (There is a
3738 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3740 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3742 CRIS_ASSERT (can_create_pseudo_p ());
3744 /* For local symbols (non-PLT), just get the plain symbol
3745 reference into a register. For symbols that can be PLT, make
3747 if (t
== cris_rel_symbol
)
3749 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3750 into a register caused performance regression for 3.2.1,
3751 observable in __floatdidf and elsewhere in libgcc. */
3754 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3755 HOST_WIDE_INT offs
= get_integer_term (op
);
3757 /* We can't get calls to sym+N, N integer, can we? */
3758 gcc_assert (offs
== 0);
3760 op
= gen_rtx_CONST (Pmode
,
3761 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3762 CRIS_UNSPEC_PCREL
));
3765 op
= force_reg (Pmode
, op
);
3768 *markerp
= const0_rtx
;
3770 else if (t
== cris_got_symbol
)
3772 if (TARGET_AVOID_GOTPLT
)
3774 /* Change a "jsr sym" into (allocate register rM, rO)
3775 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3776 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3777 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3781 crtl
->uses_pic_offset_table
= 1;
3782 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3784 ? CRIS_UNSPEC_PLT_PCREL
3785 : CRIS_UNSPEC_PLT_GOTREL
);
3786 tem
= gen_rtx_CONST (Pmode
, tem
);
3791 rm
= gen_reg_rtx (Pmode
);
3792 emit_move_insn (rm
, tem
);
3793 ro
= gen_reg_rtx (Pmode
);
3794 if (expand_binop (Pmode
, add_optab
, rm
,
3795 pic_offset_table_rtx
,
3796 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3797 internal_error ("expand_binop failed in movsi got");
3803 /* Change a "jsr sym" into (allocate register rM, rO)
3804 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3805 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3806 marked as not trapping and not aliasing. No "move.d
3807 [rO],rP" as that would invite to re-use of a value
3808 that should not be reused. FIXME: Need a peephole2
3809 for cases when this is cse:d from the call, to change
3810 back to just get the PLT entry address, so we don't
3811 resolve the same symbol over and over (the memory
3812 access of the PLTGOT isn't constant). */
3813 rtx tem
, mem
, rm
, ro
;
3815 gcc_assert (can_create_pseudo_p ());
3816 crtl
->uses_pic_offset_table
= 1;
3817 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3818 CRIS_UNSPEC_PLTGOTREAD
);
3819 rm
= gen_reg_rtx (Pmode
);
3820 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3821 ro
= gen_reg_rtx (Pmode
);
3822 if (expand_binop (Pmode
, add_optab
, rm
,
3823 pic_offset_table_rtx
,
3824 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3825 internal_error ("expand_binop failed in movsi got");
3826 mem
= gen_rtx_MEM (Pmode
, ro
);
3828 /* This MEM doesn't alias anything. Whether it aliases
3829 other same symbols is unimportant. */
3830 set_mem_alias_set (mem
, new_alias_set ());
3831 MEM_NOTRAP_P (mem
) = 1;
3835 /* We need to prepare this call to go through the PLT; we
3836 need to make GOT available. */
3837 *markerp
= pic_offset_table_rtx
;
3840 /* Can't possibly get anything else for a function-call, right? */
3841 fatal_insn ("unidentifiable call op", op
);
3843 /* If the validizing variant is called, it will try to validize
3844 the address as a valid any-operand constant, but as it's only
3845 valid for calls and moves, it will fail and always be forced
3847 *opp
= replace_equiv_address_nv (*opp
, op
);
3850 /* Can't tell what locality a call to a non-constant address has;
3851 better make the GOT register alive at it.
3852 FIXME: Can we see whether the register has known constant
3854 *markerp
= pic_offset_table_rtx
;
3857 /* Make sure operands are in the right order for an addsi3 insn as
3858 generated by a define_split. Nothing but REG_P as the first
3859 operand is recognized by addsi3 after reload. OPERANDS contains
3860 the operands, with the first at OPERANDS[N] and the second at
3864 cris_order_for_addsi3 (rtx
*operands
, int n
)
3866 if (!REG_P (operands
[n
]))
3868 rtx tem
= operands
[n
];
3869 operands
[n
] = operands
[n
+ 1];
3870 operands
[n
+ 1] = tem
;
3874 /* Use from within code, from e.g. PRINT_OPERAND and
3875 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3876 different things depending on whether code operand or constant is
3880 cris_output_addr_const (FILE *file
, rtx x
)
3883 output_addr_const (file
, x
);
3887 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3890 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3892 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3894 if (flag_pic
&& in_code
> 0)
3896 const char *origstr
= XSTR (x
, 0);
3898 str
= (* targetm
.strip_name_encoding
) (origstr
);
3899 assemble_name (file
, str
);
3902 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3903 output_operand_lossage ("PIC register isn't set up");
3906 assemble_name (file
, XSTR (x
, 0));
3909 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3912 cris_asm_output_label_ref (FILE *file
, char *buf
)
3914 if (flag_pic
&& in_code
> 0)
3916 assemble_name (file
, buf
);
3919 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3920 internal_error ("emitting PIC operand, but PIC register "
3924 assemble_name (file
, buf
);
3927 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3930 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3932 switch (GET_CODE (xconst
))
3937 x
= XVECEXP (xconst
, 0, 0);
3938 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3939 || GET_CODE (x
) == LABEL_REF
3940 || GET_CODE (x
) == CONST
);
3941 output_addr_const (file
, x
);
3942 switch (XINT (xconst
, 1))
3944 case CRIS_UNSPEC_PCREL
:
3945 /* We only get this with -fpic/PIC to tell it apart from an
3946 invalid symbol. We can't tell here, but it should only
3947 be the operand of a call or movsi. */
3948 gcc_assert (TARGET_V32
&& flag_pic
);
3951 case CRIS_UNSPEC_PLT_PCREL
:
3952 gcc_assert (TARGET_V32
);
3953 fprintf (file
, ":PLT");
3956 case CRIS_UNSPEC_PLT_GOTREL
:
3957 gcc_assert (!TARGET_V32
);
3958 fprintf (file
, ":PLTG");
3961 case CRIS_UNSPEC_GOTREL
:
3962 gcc_assert (!TARGET_V32
);
3963 fprintf (file
, ":GOTOFF");
3966 case CRIS_UNSPEC_GOTREAD
:
3968 fprintf (file
, ":GOT16");
3970 fprintf (file
, ":GOT");
3973 case CRIS_UNSPEC_PLTGOTREAD
:
3975 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3977 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
3990 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3993 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3994 int incoming ATTRIBUTE_UNUSED
)
3996 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3999 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4002 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
4003 machine_mode mode ATTRIBUTE_UNUSED
,
4004 tree type ATTRIBUTE_UNUSED
,
4005 int *pretend_arg_size
,
4008 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4010 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4012 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4013 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4014 *pretend_arg_size
= stdarg_regs
* 4;
4018 fprintf (asm_out_file
,
4019 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4020 ca
->regs
, *pretend_arg_size
, second_time
);
4023 /* Return true if TYPE must be passed by invisible reference.
4024 For cris, we pass <= 8 bytes by value, others by reference. */
4027 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4028 machine_mode mode
, const_tree type
,
4029 bool named ATTRIBUTE_UNUSED
)
4031 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4032 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4035 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4036 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4037 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4040 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4042 int *punsignedp ATTRIBUTE_UNUSED
,
4043 const_tree fntype ATTRIBUTE_UNUSED
,
4046 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4047 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4048 Maybe pointless as of now, but let's keep the old behavior. */
4049 if (for_return
== 1)
4051 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4054 /* Atomic types require alignment to be at least their "natural" size. */
4057 cris_atomic_align_for_mode (machine_mode mode
)
4059 return GET_MODE_BITSIZE (mode
);
4062 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4066 cris_function_value(const_tree type
,
4067 const_tree func ATTRIBUTE_UNUSED
,
4068 bool outgoing ATTRIBUTE_UNUSED
)
4070 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4073 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4077 cris_libcall_value (machine_mode mode
,
4078 const_rtx fun ATTRIBUTE_UNUSED
)
4080 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4083 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4087 cris_function_value_regno_p (const unsigned int regno
)
4089 return (regno
== CRIS_FIRST_ARG_REG
);
4093 cris_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
4094 tree type
, bool named ATTRIBUTE_UNUSED
)
4096 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4097 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4098 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4099 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4100 return UNITS_PER_WORD
;
4106 cris_function_arg_1 (cumulative_args_t ca_v
,
4107 machine_mode mode ATTRIBUTE_UNUSED
,
4108 const_tree type ATTRIBUTE_UNUSED
,
4109 bool named
, bool incoming
)
4111 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4113 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4114 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4119 /* Worker function for TARGET_FUNCTION_ARG.
4120 The void_type_node is sent as a "closing" call. */
4123 cris_function_arg (cumulative_args_t ca
, machine_mode mode
,
4124 const_tree type
, bool named
)
4126 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4129 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4131 The differences between this and the previous, is that this one checks
4132 that an argument is named, since incoming stdarg/varargs arguments are
4133 pushed onto the stack, and we don't have to check against the "closing"
4134 void_type_node TYPE parameter. */
4137 cris_function_incoming_arg (cumulative_args_t ca
, machine_mode mode
,
4138 const_tree type
, bool named
)
4140 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4143 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4146 cris_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
4147 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4149 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4151 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4154 /* Worker function for TARGET_MD_ASM_ADJUST. */
4157 cris_md_asm_adjust (vec
<rtx
> &outputs
, vec
<rtx
> &inputs
,
4158 vec
<const char *> &constraints
,
4159 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
4161 /* For the time being, all asms clobber condition codes.
4162 Revisit when there's a reasonable use for inputs/outputs
4163 that mention condition codes. */
4164 clobbers
.safe_push (gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
4165 SET_HARD_REG_BIT (clobbered_regs
, CRIS_CC0_REGNUM
);
4167 /* Determine if the source using MOF. If it is, automatically
4168 clobbering MOF would cause it to have impossible constraints. */
4170 /* Look for a use of the MOF constraint letter: h. */
4171 for (unsigned i
= 0, n
= constraints
.length(); i
< n
; ++i
)
4172 if (strchr (constraints
[i
], 'h') != NULL
)
4175 /* Look for an output or an input that touches MOF. */
4176 rtx mof_reg
= gen_rtx_REG (SImode
, CRIS_MOF_REGNUM
);
4177 for (unsigned i
= 0, n
= outputs
.length(); i
< n
; ++i
)
4178 if (reg_overlap_mentioned_p (mof_reg
, outputs
[i
]))
4180 for (unsigned i
= 0, n
= inputs
.length(); i
< n
; ++i
)
4181 if (reg_overlap_mentioned_p (mof_reg
, inputs
[i
]))
4184 /* No direct reference to MOF or its constraint.
4185 Clobber it for backward compatibility. */
4186 clobbers
.safe_push (mof_reg
);
4187 SET_HARD_REG_BIT (clobbered_regs
, CRIS_MOF_REGNUM
);
4191 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4193 Really only needed if the stack frame has variable length (alloca
4194 or variable sized local arguments (GNU C extension). See PR39499 and
4195 PR38609 for the reason this isn't just 0. */
4198 cris_frame_pointer_required (void)
4200 return !crtl
->sp_is_unchanging
;
4203 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4205 This looks too complicated, and it is. I assigned r7 to be the
4206 static chain register, but it is call-saved, so we have to save it,
4207 and come back to restore it after the call, so we have to save srp...
4208 Anyway, trampolines are rare enough that we can cope with this
4209 somewhat lack of elegance.
4210 (Do not be tempted to "straighten up" whitespace in the asms; the
4211 assembler #NO_APP state mandates strict spacing). */
4212 /* ??? See the i386 regparm=3 implementation that pushes the static
4213 chain value to the stack in the trampoline, and uses a call-saved
4214 register when called directly. */
4217 cris_asm_trampoline_template (FILE *f
)
4221 /* This normally-unused nop insn acts as an instruction to
4222 the simulator to flush its instruction cache. None of
4223 the other instructions in the trampoline template suits
4224 as a trigger for V32. The pc-relative addressing mode
4225 works nicely as a trigger for V10.
4226 FIXME: Have specific V32 template (possibly avoiding the
4227 use of a special instruction). */
4228 fprintf (f
, "\tclearf x\n");
4229 /* We have to use a register as an intermediate, choosing
4230 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4231 so we can use it for address indirection and jsr target. */
4232 fprintf (f
, "\tmove $r1,$mof\n");
4234 fprintf (f
, "\tmove.d 0,$r1\n");
4235 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4236 fprintf (f
, "\taddq 6,$r1\n");
4237 fprintf (f
, "\tmove $mof,[$r1]\n");
4238 fprintf (f
, "\taddq 6,$r1\n");
4239 fprintf (f
, "\tmove $srp,[$r1]\n");
4241 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4243 fprintf (f
, "\tmove.d 0,$r1\n");
4244 fprintf (f
, "\tjsr $r1\n");
4245 fprintf (f
, "\tsetf\n");
4247 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4249 fprintf (f
, "\tmove.d 0,$r1\n");
4251 fprintf (f
, "\tmove.d 0,$r9\n");
4252 fprintf (f
, "\tjump $r9\n");
4253 fprintf (f
, "\tsetf\n");
4257 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4258 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4259 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4260 fprintf (f
, "\tjsr 0\n");
4261 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4262 fprintf (f
, "\tjump 0\n");
4266 /* Implement TARGET_TRAMPOLINE_INIT. */
4269 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4271 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4272 rtx tramp
= XEXP (m_tramp
, 0);
4275 emit_block_move (m_tramp
, assemble_trampoline_template (),
4276 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4280 mem
= adjust_address (m_tramp
, SImode
, 6);
4281 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4282 mem
= adjust_address (m_tramp
, SImode
, 22);
4283 emit_move_insn (mem
, chain_value
);
4284 mem
= adjust_address (m_tramp
, SImode
, 28);
4285 emit_move_insn (mem
, fnaddr
);
4289 mem
= adjust_address (m_tramp
, SImode
, 10);
4290 emit_move_insn (mem
, chain_value
);
4291 mem
= adjust_address (m_tramp
, SImode
, 16);
4292 emit_move_insn (mem
, fnaddr
);
4295 /* Note that there is no need to do anything with the cache for
4296 sake of a trampoline. */
4299 /* Implement TARGET_HARD_REGNO_MODE_OK.
4301 CRIS permits all registers to hold all modes. Well, except for the
4302 condition-code register. And we can't hold larger-than-register size
4303 modes in the last special register that can hold a full 32 bits. */
4305 cris_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4307 return ((mode
== CCmode
|| regno
!= CRIS_CC0_REGNUM
)
4308 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
4309 || (regno
!= CRIS_MOF_REGNUM
&& regno
!= CRIS_ACR_REGNUM
)));
4313 /* Various small functions to replace macros. Only called from a
4314 debugger. They might collide with gcc functions or system functions,
4315 so only emit them when '#if 1' above. */
4317 enum rtx_code
Get_code (rtx
);
4322 return GET_CODE (x
);
4325 const char *Get_mode (rtx
);
4330 return GET_MODE_NAME (GET_MODE (x
));
4333 rtx
Xexp (rtx
, int);
4341 rtx
Xvecexp (rtx
, int, int);
4344 Xvecexp (rtx x
, int n
, int m
)
4346 return XVECEXP (x
, n
, m
);
4349 int Get_rtx_len (rtx
);
4354 return GET_RTX_LENGTH (GET_CODE (x
));
4357 /* Use upper-case to distinguish from local variables that are sometimes
4358 called next_insn and prev_insn. */
4360 rtx
Next_insn (rtx
);
4363 Next_insn (rtx insn
)
4365 return NEXT_INSN (insn
);
4368 rtx
Prev_insn (rtx
);
4371 Prev_insn (rtx insn
)
4373 return PREV_INSN (insn
);
4377 #include "gt-cris.h"
4381 * eval: (c-set-style "gnu")
4382 * indent-tabs-mode: t