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Turn HARD_REGNO_MODE_OK into a target hook
[official-gcc.git] / gcc / config / bfin / bfin.h
blob232ce23fe0df6ca2e7a0f264ff0d0da9887a991a
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005-2017 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #ifndef _BFIN_CONFIG
22 #define _BFIN_CONFIG
23
24 #ifndef BFIN_OPTS_H
25 #include "config/bfin/bfin-opts.h"
26 #endif
27
28 #define OBJECT_FORMAT_ELF
29
30 #define BRT 1
31 #define BRF 0
32
33 /* Predefinition in the preprocessor for this target machine */
34 #ifndef TARGET_CPU_CPP_BUILTINS
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do \
37 { \
38 builtin_define_std ("bfin"); \
39 builtin_define_std ("BFIN"); \
40 builtin_define ("__ADSPBLACKFIN__"); \
41 builtin_define ("__ADSPLPBLACKFIN__"); \
42 \
43 switch (bfin_cpu_type) \
44 { \
45 case BFIN_CPU_UNKNOWN: \
46 break; \
47 case BFIN_CPU_BF512: \
48 builtin_define ("__ADSPBF512__"); \
49 builtin_define ("__ADSPBF51x__"); \
50 break; \
51 case BFIN_CPU_BF514: \
52 builtin_define ("__ADSPBF514__"); \
53 builtin_define ("__ADSPBF51x__"); \
54 break; \
55 case BFIN_CPU_BF516: \
56 builtin_define ("__ADSPBF516__"); \
57 builtin_define ("__ADSPBF51x__"); \
58 break; \
59 case BFIN_CPU_BF518: \
60 builtin_define ("__ADSPBF518__"); \
61 builtin_define ("__ADSPBF51x__"); \
62 break; \
63 case BFIN_CPU_BF522: \
64 builtin_define ("__ADSPBF522__"); \
65 builtin_define ("__ADSPBF52x__"); \
66 break; \
67 case BFIN_CPU_BF523: \
68 builtin_define ("__ADSPBF523__"); \
69 builtin_define ("__ADSPBF52x__"); \
70 break; \
71 case BFIN_CPU_BF524: \
72 builtin_define ("__ADSPBF524__"); \
73 builtin_define ("__ADSPBF52x__"); \
74 break; \
75 case BFIN_CPU_BF525: \
76 builtin_define ("__ADSPBF525__"); \
77 builtin_define ("__ADSPBF52x__"); \
78 break; \
79 case BFIN_CPU_BF526: \
80 builtin_define ("__ADSPBF526__"); \
81 builtin_define ("__ADSPBF52x__"); \
82 break; \
83 case BFIN_CPU_BF527: \
84 builtin_define ("__ADSPBF527__"); \
85 builtin_define ("__ADSPBF52x__"); \
86 break; \
87 case BFIN_CPU_BF531: \
88 builtin_define ("__ADSPBF531__"); \
89 break; \
90 case BFIN_CPU_BF532: \
91 builtin_define ("__ADSPBF532__"); \
92 break; \
93 case BFIN_CPU_BF533: \
94 builtin_define ("__ADSPBF533__"); \
95 break; \
96 case BFIN_CPU_BF534: \
97 builtin_define ("__ADSPBF534__"); \
98 break; \
99 case BFIN_CPU_BF536: \
100 builtin_define ("__ADSPBF536__"); \
101 break; \
102 case BFIN_CPU_BF537: \
103 builtin_define ("__ADSPBF537__"); \
104 break; \
105 case BFIN_CPU_BF538: \
106 builtin_define ("__ADSPBF538__"); \
107 break; \
108 case BFIN_CPU_BF539: \
109 builtin_define ("__ADSPBF539__"); \
110 break; \
111 case BFIN_CPU_BF542M: \
112 builtin_define ("__ADSPBF542M__"); \
113 /* FALLTHRU */ \
114 case BFIN_CPU_BF542: \
115 builtin_define ("__ADSPBF542__"); \
116 builtin_define ("__ADSPBF54x__"); \
117 break; \
118 case BFIN_CPU_BF544M: \
119 builtin_define ("__ADSPBF544M__"); \
120 /* FALLTHRU */ \
121 case BFIN_CPU_BF544: \
122 builtin_define ("__ADSPBF544__"); \
123 builtin_define ("__ADSPBF54x__"); \
124 break; \
125 case BFIN_CPU_BF547M: \
126 builtin_define ("__ADSPBF547M__"); \
127 /* FALLTHRU */ \
128 case BFIN_CPU_BF547: \
129 builtin_define ("__ADSPBF547__"); \
130 builtin_define ("__ADSPBF54x__"); \
131 break; \
132 case BFIN_CPU_BF548M: \
133 builtin_define ("__ADSPBF548M__"); \
134 /* FALLTHRU */ \
135 case BFIN_CPU_BF548: \
136 builtin_define ("__ADSPBF548__"); \
137 builtin_define ("__ADSPBF54x__"); \
138 break; \
139 case BFIN_CPU_BF549M: \
140 builtin_define ("__ADSPBF549M__"); \
141 /* FALLTHRU */ \
142 case BFIN_CPU_BF549: \
143 builtin_define ("__ADSPBF549__"); \
144 builtin_define ("__ADSPBF54x__"); \
145 break; \
146 case BFIN_CPU_BF561: \
147 builtin_define ("__ADSPBF561__"); \
148 break; \
149 case BFIN_CPU_BF592: \
150 builtin_define ("__ADSPBF592__"); \
151 builtin_define ("__ADSPBF59x__"); \
152 break; \
153 } \
154 \
155 if (bfin_si_revision != -1) \
156 { \
157 /* space of 0xnnnn and a NUL */ \
158 char *buf = XALLOCAVEC (char, 7); \
159 \
160 sprintf (buf, "0x%04x", bfin_si_revision); \
161 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
162 } \
163 \
164 if (bfin_workarounds) \
165 builtin_define ("__WORKAROUNDS_ENABLED"); \
166 if (ENABLE_WA_SPECULATIVE_LOADS) \
167 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
168 if (ENABLE_WA_SPECULATIVE_SYNCS) \
169 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
170 if (ENABLE_WA_INDIRECT_CALLS) \
171 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
172 if (ENABLE_WA_RETS) \
173 builtin_define ("__WORKAROUND_RETS"); \
174 \
175 if (TARGET_FDPIC) \
176 { \
177 builtin_define ("__BFIN_FDPIC__"); \
178 builtin_define ("__FDPIC__"); \
179 } \
180 if (TARGET_ID_SHARED_LIBRARY \
181 && !TARGET_SEP_DATA) \
182 builtin_define ("__ID_SHARED_LIB__"); \
183 if (flag_no_builtin) \
184 builtin_define ("__NO_BUILTIN"); \
185 if (TARGET_MULTICORE) \
186 builtin_define ("__BFIN_MULTICORE"); \
187 if (TARGET_COREA) \
188 builtin_define ("__BFIN_COREA"); \
189 if (TARGET_COREB) \
190 builtin_define ("__BFIN_COREB"); \
191 if (TARGET_SDRAM) \
192 builtin_define ("__BFIN_SDRAM"); \
193 } \
194 while (0)
195 #endif
196
197 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
198 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
199 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
200 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
201 "
202 #ifndef SUBTARGET_DRIVER_SELF_SPECS
203 # define SUBTARGET_DRIVER_SELF_SPECS
204 #endif
205
206 #define LINK_GCC_C_SEQUENCE_SPEC "\
207 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
208 "
209
210 #undef ASM_SPEC
211 #define ASM_SPEC "\
212 %{mno-fdpic:-mnopic} %{mfdpic}"
213
214 #define LINK_SPEC "\
215 %{h*} %{v:-V} \
216 %{mfdpic:-melf32bfinfd -z text} \
217 %{static:-dn -Bstatic} \
218 %{shared:-G -Bdynamic} \
219 %{symbolic:-Bsymbolic} \
220 -init __init -fini __fini "
221
222 /* Generate DSP instructions, like DSP halfword loads */
223 #define TARGET_DSP (1)
224
225 #define TARGET_DEFAULT 0
226
227 /* Maximum number of library ids we permit */
228 #define MAX_LIBRARY_ID 255
229
230 extern const char *bfin_library_id_string;
231
232 #define FUNCTION_MODE SImode
233 #define Pmode SImode
234
235 /* store-condition-codes instructions store 0 for false
236 This is the value stored for true. */
237 #define STORE_FLAG_VALUE 1
238
239 /* Define this if pushing a word on the stack
240 makes the stack pointer a smaller address. */
241 #define STACK_GROWS_DOWNWARD 1
242
243 #define STACK_PUSH_CODE PRE_DEC
244
245 /* Define this to nonzero if the nominal address of the stack frame
246 is at the high-address end of the local variables;
247 that is, each additional local variable allocated
248 goes at a more negative offset in the frame. */
249 #define FRAME_GROWS_DOWNWARD 1
250
251 /* We define a dummy ARGP register; the parameters start at offset 0 from
252 it. */
253 #define FIRST_PARM_OFFSET(DECL) 0
254
255 /* Offset within stack frame to start allocating local variables at.
256 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
257 first local allocated. Otherwise, it is the offset to the BEGINNING
258 of the first local allocated. */
259 #define STARTING_FRAME_OFFSET 0
260
261 /* Register to use for pushing function arguments. */
262 #define STACK_POINTER_REGNUM REG_P6
263
264 /* Base register for access to local variables of the function. */
265 #define FRAME_POINTER_REGNUM REG_P7
266
267 /* A dummy register that will be eliminated to either FP or SP. */
268 #define ARG_POINTER_REGNUM REG_ARGP
269
270 /* `PIC_OFFSET_TABLE_REGNUM'
271 The register number of the register used to address a table of
272 static data addresses in memory. In some cases this register is
273 defined by a processor's "application binary interface" (ABI).
274 When this macro is defined, RTL is generated for this register
275 once, as with the stack pointer and frame pointer registers. If
276 this macro is not defined, it is up to the machine-dependent files
277 to allocate such a register (if necessary). */
278 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
279
280 #define FDPIC_FPTR_REGNO REG_P1
281 #define FDPIC_REGNO REG_P3
282 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
283
284 /* A static chain register for nested functions. We need to use a
285 call-clobbered register for this. */
286 #define STATIC_CHAIN_REGNUM REG_P2
287
288 /* Define this if functions should assume that stack space has been
289 allocated for arguments even when their values are passed in
290 registers.
291
292 The value of this macro is the size, in bytes, of the area reserved for
293 arguments passed in registers.
294
295 This space can either be allocated by the caller or be a part of the
296 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
297 says which. */
298 #define FIXED_STACK_AREA 12
299 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
300
301 /* Define this if the above stack space is to be considered part of the
302 * space allocated by the caller. */
303 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
304
305 /* Define this if the maximum size of all the outgoing args is to be
306 accumulated and pushed during the prologue. The amount can be
307 found in the variable crtl->outgoing_args_size. */
308 #define ACCUMULATE_OUTGOING_ARGS 1
309
310 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
311
312 /* If defined, a C expression to compute the alignment for a local
313 variable. TYPE is the data type, and ALIGN is the alignment that
314 the object would ordinarily have. The value of this macro is used
315 instead of that alignment to align the object.
316
317 If this macro is not defined, then ALIGN is used.
318
319 One use of this macro is to increase alignment of medium-size
320 data to make it all fit in fewer cache lines. */
321
322 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
323
324 /* Make strings word-aligned so strcpy from constants will be faster. */
325 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
326 (TREE_CODE (EXP) == STRING_CST \
327 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
328
329 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
330 \f
331 /* Definitions for register eliminations.
332
333 This is an array of structures. Each structure initializes one pair
334 of eliminable registers. The "from" register number is given first,
335 followed by "to". Eliminations of the same "from" register are listed
336 in order of preference.
337
338 There are two registers that can always be eliminated on the i386.
339 The frame pointer and the arg pointer can be replaced by either the
340 hard frame pointer or to the stack pointer, depending upon the
341 circumstances. The hard frame pointer is not used before reload and
342 so it is not eligible for elimination. */
343
344 #define ELIMINABLE_REGS \
345 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
346 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
347 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
348
349 /* Define the offset between two registers, one to be eliminated, and the other
350 its replacement, at the start of a routine. */
351
352 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
353 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
354 \f
355 /* This processor has
356 8 data register for doing arithmetic
357 8 pointer register for doing addressing, including
358 1 stack pointer P6
359 1 frame pointer P7
360 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
361 1 condition code flag register CC
362 5 return address registers RETS/I/X/N/E
363 1 arithmetic status register (ASTAT). */
364
365 #define FIRST_PSEUDO_REGISTER 50
366
367 #define D_REGNO_P(X) ((X) <= REG_R7)
368 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
369 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
370 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
371 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
372 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
373 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
374 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
375 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
376
377 #define REGISTER_NAMES { \
378 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
379 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
380 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
381 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
382 "A0", "A1", \
383 "CC", \
384 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
385 "ARGP", \
386 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
387 }
388
389 #define SHORT_REGISTER_NAMES { \
390 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
391 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
392 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
393 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
394
395 #define HIGH_REGISTER_NAMES { \
396 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
397 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
398 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
399 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
400
401 #define DREGS_PAIR_NAMES { \
402 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
403
404 #define BYTE_REGISTER_NAMES { \
405 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
406
407
408 /* 1 for registers that have pervasive standard uses
409 and are not available for the register allocator. */
410
411 #define FIXED_REGISTERS \
412 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
413 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
414 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
415 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
416 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
417 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
418 /*lb0/1 */ \
419 1, 1 \
420 }
421
422 /* 1 for registers not available across function calls.
423 These must include the FIXED_REGISTERS and also any
424 registers that can be used without being saved.
425 The latter must include the registers where values are returned
426 and the register where structure-value addresses are passed.
427 Aside from that, you can include as many other registers as you like. */
428
429 #define CALL_USED_REGISTERS \
430 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
431 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
432 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
434 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
436 /*lb0/1 */ \
437 1, 1 \
438 }
439
440 /* Order in which to allocate registers. Each register must be
441 listed once, even those in FIXED_REGISTERS. List frame pointer
442 late and fixed registers last. Note that, in general, we prefer
443 registers listed in CALL_USED_REGISTERS, keeping the others
444 available for storage of persistent values. */
445
446 #define REG_ALLOC_ORDER \
447 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
448 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
449 REG_A0, REG_A1, \
450 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
451 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
452 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
453 REG_ASTAT, REG_SEQSTAT, REG_USP, \
454 REG_CC, REG_ARGP, \
455 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
456 }
457
458 /* Define the classes of registers for register constraints in the
459 machine description. Also define ranges of constants.
460
461 One of the classes must always be named ALL_REGS and include all hard regs.
462 If there is more than one class, another class must be named NO_REGS
463 and contain no registers.
464
465 The name GENERAL_REGS must be the name of a class (or an alias for
466 another name such as ALL_REGS). This is the class of registers
467 that is allowed by "g" or "r" in a register constraint.
468 Also, registers outside this class are allocated only when
469 instructions express preferences for them.
470
471 The classes must be numbered in nondecreasing order; that is,
472 a larger-numbered class must never be contained completely
473 in a smaller-numbered class.
474
475 For any two classes, it is very desirable that there be another
476 class that represents their union. */
477
478
479 enum reg_class
480 {
481 NO_REGS,
482 IREGS,
483 BREGS,
484 LREGS,
485 MREGS,
486 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
487 DAGREGS,
488 EVEN_AREGS,
489 ODD_AREGS,
490 AREGS,
491 CCREGS,
492 EVEN_DREGS,
493 ODD_DREGS,
494 D0REGS,
495 D1REGS,
496 D2REGS,
497 D3REGS,
498 D4REGS,
499 D5REGS,
500 D6REGS,
501 D7REGS,
502 DREGS,
503 P0REGS,
504 FDPIC_REGS,
505 FDPIC_FPTR_REGS,
506 PREGS_CLOBBERED,
507 PREGS,
508 IPREGS,
509 DPREGS,
510 MOST_REGS,
511 LT_REGS,
512 LC_REGS,
513 LB_REGS,
514 PROLOGUE_REGS,
515 NON_A_CC_REGS,
516 ALL_REGS, LIM_REG_CLASSES
517 };
518
519 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
520
521 #define GENERAL_REGS DPREGS
522
523 /* Give names of register classes as strings for dump file. */
524
525 #define REG_CLASS_NAMES \
526 { "NO_REGS", \
527 "IREGS", \
528 "BREGS", \
529 "LREGS", \
530 "MREGS", \
531 "CIRCREGS", \
532 "DAGREGS", \
533 "EVEN_AREGS", \
534 "ODD_AREGS", \
535 "AREGS", \
536 "CCREGS", \
537 "EVEN_DREGS", \
538 "ODD_DREGS", \
539 "D0REGS", \
540 "D1REGS", \
541 "D2REGS", \
542 "D3REGS", \
543 "D4REGS", \
544 "D5REGS", \
545 "D6REGS", \
546 "D7REGS", \
547 "DREGS", \
548 "P0REGS", \
549 "FDPIC_REGS", \
550 "FDPIC_FPTR_REGS", \
551 "PREGS_CLOBBERED", \
552 "PREGS", \
553 "IPREGS", \
554 "DPREGS", \
555 "MOST_REGS", \
556 "LT_REGS", \
557 "LC_REGS", \
558 "LB_REGS", \
559 "PROLOGUE_REGS", \
560 "NON_A_CC_REGS", \
561 "ALL_REGS" }
562
563 /* An initializer containing the contents of the register classes, as integers
564 which are bit masks. The Nth integer specifies the contents of class N.
565 The way the integer MASK is interpreted is that register R is in the class
566 if `MASK & (1 << R)' is 1.
567
568 When the machine has more than 32 registers, an integer does not suffice.
569 Then the integers are replaced by sub-initializers, braced groupings
570 containing several integers. Each sub-initializer must be suitable as an
571 initializer for the type `HARD_REG_SET' which is defined in
572 `hard-reg-set.h'. */
573
574 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
575 MOST_REGS as the union of DPREGS and DAGREGS. */
576
577 #define REG_CLASS_CONTENTS \
578 /* 31 - 0 63-32 */ \
579 { { 0x00000000, 0 }, /* NO_REGS */ \
580 { 0x000f0000, 0 }, /* IREGS */ \
581 { 0x00f00000, 0 }, /* BREGS */ \
582 { 0x0f000000, 0 }, /* LREGS */ \
583 { 0xf0000000, 0 }, /* MREGS */ \
584 { 0x0fff0000, 0 }, /* CIRCREGS */ \
585 { 0xffff0000, 0 }, /* DAGREGS */ \
586 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
587 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
588 { 0x00000000, 0x3 }, /* AREGS */ \
589 { 0x00000000, 0x4 }, /* CCREGS */ \
590 { 0x00000055, 0 }, /* EVEN_DREGS */ \
591 { 0x000000aa, 0 }, /* ODD_DREGS */ \
592 { 0x00000001, 0 }, /* D0REGS */ \
593 { 0x00000002, 0 }, /* D1REGS */ \
594 { 0x00000004, 0 }, /* D2REGS */ \
595 { 0x00000008, 0 }, /* D3REGS */ \
596 { 0x00000010, 0 }, /* D4REGS */ \
597 { 0x00000020, 0 }, /* D5REGS */ \
598 { 0x00000040, 0 }, /* D6REGS */ \
599 { 0x00000080, 0 }, /* D7REGS */ \
600 { 0x000000ff, 0 }, /* DREGS */ \
601 { 0x00000100, 0x000 }, /* P0REGS */ \
602 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
603 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
604 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
605 { 0x0000ff00, 0x800 }, /* PREGS */ \
606 { 0x000fff00, 0x800 }, /* IPREGS */ \
607 { 0x0000ffff, 0x800 }, /* DPREGS */ \
608 { 0xffffffff, 0x800 }, /* MOST_REGS */\
609 { 0x00000000, 0x3000 }, /* LT_REGS */\
610 { 0x00000000, 0xc000 }, /* LC_REGS */\
611 { 0x00000000, 0x30000 }, /* LB_REGS */\
612 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
613 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
614 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
615
616 #define IREG_POSSIBLE_P(OUTER) \
617 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
618 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
619 || (OUTER) == MEM || (OUTER) == ADDRESS)
620
621 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
622 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
623
624 #define INDEX_REG_CLASS PREGS
625
626 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
627 (P_REGNO_P (X) || (X) == REG_ARGP \
628 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
629 && I_REGNO_P (X)))
630
631 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
632 ((X) >= FIRST_PSEUDO_REGISTER \
633 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
634
635 #ifdef REG_OK_STRICT
636 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
637 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
638 #else
639 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
640 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
641 #endif
642
643 #define REGNO_OK_FOR_INDEX_P(X) 0
644
645 /* The same information, inverted:
646 Return the class number of the smallest class containing
647 reg number REGNO. This could be a conditional expression
648 or could index an array. */
649
650 #define REGNO_REG_CLASS(REGNO) \
651 ((REGNO) == REG_R0 ? D0REGS \
652 : (REGNO) == REG_R1 ? D1REGS \
653 : (REGNO) == REG_R2 ? D2REGS \
654 : (REGNO) == REG_R3 ? D3REGS \
655 : (REGNO) == REG_R4 ? D4REGS \
656 : (REGNO) == REG_R5 ? D5REGS \
657 : (REGNO) == REG_R6 ? D6REGS \
658 : (REGNO) == REG_R7 ? D7REGS \
659 : (REGNO) == REG_P0 ? P0REGS \
660 : (REGNO) < REG_I0 ? PREGS \
661 : (REGNO) == REG_ARGP ? PREGS \
662 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
663 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
664 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
665 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
666 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
667 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
668 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
669 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
670 : (REGNO) == REG_CC ? CCREGS \
671 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
672 : NO_REGS)
673
674 /* When this hook returns true for MODE, the compiler allows
675 registers explicitly used in the rtl to be used as spill registers
676 but prevents the compiler from extending the lifetime of these
677 registers. */
678 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
679
680 /* Return the maximum number of consecutive registers
681 needed to represent mode MODE in a register of class CLASS. */
682 #define CLASS_MAX_NREGS(CLASS, MODE) \
683 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
684 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
685
686 #define HARD_REGNO_NREGS(REGNO, MODE) \
687 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
688 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
689 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
690
691 /* A C expression that is nonzero if hard register TO can be
692 considered for use as a rename register for FROM register */
693 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
694
695 /* A C expression that is nonzero if it is desirable to choose
696 register allocation so as to avoid move instructions between a
697 value of mode MODE1 and a value of mode MODE2.
698
699 If `TARGET_HARD_REGNO_MODE_OK (R, MODE1)' and
700 `TARGET_HARD_REGNO_MODE_OK (R, MODE2)' are ever different for any R,
701 then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */
702 #define MODES_TIEABLE_P(MODE1, MODE2) \
703 ((MODE1) == (MODE2) \
704 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
705 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
706 && (GET_MODE_CLASS (MODE2) == MODE_INT \
707 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
708 && (MODE1) != BImode && (MODE2) != BImode \
709 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
710 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
711
712 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
713 A C expression that places additional restrictions on the register
714 class to use when it is necessary to copy value X into a register
715 in class CLASS. The value is a register class; perhaps CLASS, or
716 perhaps another, smaller class. */
717 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
718 (GET_CODE (X) == POST_INC \
719 || GET_CODE (X) == POST_DEC \
720 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
721
722 /* Function Calling Conventions. */
723
724 /* The type of the current function; normal functions are of type
725 SUBROUTINE. */
726 typedef enum {
727 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
728 } e_funkind;
729 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
730
731 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
732
733 /* Flags for the call/call_value rtl operations set up by function_arg */
734 #define CALL_NORMAL 0x00000000 /* no special processing */
735 #define CALL_LONG 0x00000001 /* always call indirect */
736 #define CALL_SHORT 0x00000002 /* always call by symbol */
737
738 typedef struct {
739 int words; /* # words passed so far */
740 int nregs; /* # registers available for passing */
741 int *arg_regs; /* array of register -1 terminated */
742 int call_cookie; /* Do special things for this call */
743 } CUMULATIVE_ARGS;
744
745 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
746
747
748 /* Initialize a variable CUM of type CUMULATIVE_ARGS
749 for a call to a function whose data type is FNTYPE.
750 For a library call, FNTYPE is 0. */
751 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
752 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
753
754 /* Define how to find the value returned by a function.
755 VALTYPE is the data type of the value (as a tree).
756 If the precise function being called is known, FUNC is its FUNCTION_DECL;
757 otherwise, FUNC is 0.
758 */
759
760 #define VALUE_REGNO(MODE) (REG_R0)
761
762 #define FUNCTION_VALUE(VALTYPE, FUNC) \
763 gen_rtx_REG (TYPE_MODE (VALTYPE), \
764 VALUE_REGNO(TYPE_MODE(VALTYPE)))
765
766 /* Define how to find the value returned by a library function
767 assuming the value has mode MODE. */
768
769 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
770
771 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
772
773 #define DEFAULT_PCC_STRUCT_RETURN 0
774
775 /* Before the prologue, the return address is in the RETS register. */
776 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
777
778 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
779
780 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
781
782 /* Call instructions don't modify the stack pointer on the Blackfin. */
783 #define INCOMING_FRAME_SP_OFFSET 0
784
785 /* Describe how we implement __builtin_eh_return. */
786 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
787 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
788 #define EH_RETURN_HANDLER_RTX \
789 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \
790 UNITS_PER_WORD))
791
792 /* Addressing Modes */
793
794 /* A number, the maximum number of registers that can appear in a
795 valid memory address. Note that it is up to you to specify a
796 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
797 would ever accept. */
798 #define MAX_REGS_PER_ADDRESS 1
799
800 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
801 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
802
803 #define HAVE_POST_INCREMENT 1
804 #define HAVE_POST_DECREMENT 1
805 #define HAVE_PRE_DECREMENT 1
806
807 /* `LEGITIMATE_PIC_OPERAND_P (X)'
808 A C expression that is nonzero if X is a legitimate immediate
809 operand on the target machine when generating position independent
810 code. You can assume that X satisfies `CONSTANT_P', so you need
811 not check this. You can also assume FLAG_PIC is true, so you need
812 not check it either. You need not define this macro if all
813 constants (including `SYMBOL_REF') can be immediate operands when
814 generating position independent code. */
815 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
816
817 #define SYMBOLIC_CONST(X) \
818 (GET_CODE (X) == SYMBOL_REF \
819 || GET_CODE (X) == LABEL_REF \
820 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
821
822 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
823
824 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
825 is done just by pretending it is already truncated. */
826 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
827
828 /* Max number of bytes we can move from memory to memory
829 in one reasonably fast instruction. */
830 #define MOVE_MAX UNITS_PER_WORD
831
832 /* If a memory-to-memory move would take MOVE_RATIO or more simple
833 move-instruction pairs, we will do a movmem or libcall instead. */
834
835 #define MOVE_RATIO(speed) 5
836
837 /* STORAGE LAYOUT: target machine storage layout
838 Define this macro as a C expression which is nonzero if accessing
839 less than a word of memory (i.e. a `char' or a `short') is no
840 faster than accessing a word of memory, i.e., if such access
841 require more than one instruction or if there is no difference in
842 cost between byte and (aligned) word loads.
843
844 When this macro is not defined, the compiler will access a field by
845 finding the smallest containing object; when it is defined, a
846 fullword load will be used if alignment permits. Unless bytes
847 accesses are faster than word accesses, using word accesses is
848 preferable since it may eliminate subsequent memory access if
849 subsequent accesses occur to other fields in the same word of the
850 structure, but to different bytes. */
851 #define SLOW_BYTE_ACCESS 0
852 #define SLOW_SHORT_ACCESS 0
853
854 /* Define this if most significant bit is lowest numbered
855 in instructions that operate on numbered bit-fields. */
856 #define BITS_BIG_ENDIAN 0
857
858 /* Define this if most significant byte of a word is the lowest numbered.
859 We can't access bytes but if we could we would in the Big Endian order. */
860 #define BYTES_BIG_ENDIAN 0
861
862 /* Define this if most significant word of a multiword number is numbered. */
863 #define WORDS_BIG_ENDIAN 0
864
865 /* Width in bits of a "word", which is the contents of a machine register.
866 Note that this is not necessarily the width of data type `int';
867 if using 16-bit ints on a 68000, this would still be 32.
868 But on a machine with 16-bit registers, this would be 16. */
869 #define BITS_PER_WORD 32
870
871 /* Width of a word, in units (bytes). */
872 #define UNITS_PER_WORD 4
873
874 /* Width in bits of a pointer.
875 See also the macro `Pmode1' defined below. */
876 #define POINTER_SIZE 32
877
878 /* Allocation boundary (in *bits*) for storing pointers in memory. */
879 #define POINTER_BOUNDARY 32
880
881 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
882 #define PARM_BOUNDARY 32
883
884 /* Boundary (in *bits*) on which stack pointer should be aligned. */
885 #define STACK_BOUNDARY 32
886
887 /* Allocation boundary (in *bits*) for the code of a function. */
888 #define FUNCTION_BOUNDARY 32
889
890 /* Alignment of field after `int : 0' in a structure. */
891 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
892
893 /* No data type wants to be aligned rounder than this. */
894 #define BIGGEST_ALIGNMENT 32
895
896 /* Define this if move instructions will actually fail to work
897 when given unaligned data. */
898 #define STRICT_ALIGNMENT 1
899
900 /* (shell-command "rm c-decl.o stor-layout.o")
901 * never define PCC_BITFIELD_TYPE_MATTERS
902 * really cause some alignment problem
903 */
904
905 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
906 BITS_PER_UNIT)
907
908 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
909 BITS_PER_UNIT)
910
911
912 /* what is the 'type' of size_t */
913 #define SIZE_TYPE "long unsigned int"
914
915 /* Define this as 1 if `char' should by default be signed; else as 0. */
916 #define DEFAULT_SIGNED_CHAR 1
917 #define FLOAT_TYPE_SIZE BITS_PER_WORD
918 #define SHORT_TYPE_SIZE 16
919 #define CHAR_TYPE_SIZE 8
920 #define INT_TYPE_SIZE 32
921 #define LONG_TYPE_SIZE 32
922 #define LONG_LONG_TYPE_SIZE 64
923
924 /* Note: Fix this to depend on target switch. -- lev */
925
926 /* Note: Try to implement double and force long double. -- tonyko
927 * #define __DOUBLES_ARE_FLOATS__
928 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
929 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
930 * #define DOUBLES_ARE_FLOATS 1
931 */
932
933 #define DOUBLE_TYPE_SIZE 64
934 #define LONG_DOUBLE_TYPE_SIZE 64
935
936 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
937 A macro to update M and UNSIGNEDP when an object whose type is
938 TYPE and which has the specified mode and signedness is to be
939 stored in a register. This macro is only called when TYPE is a
940 scalar type.
941
942 On most RISC machines, which only have operations that operate on
943 a full register, define this macro to set M to `word_mode' if M is
944 an integer mode narrower than `BITS_PER_WORD'. In most cases,
945 only integer modes should be widened because wider-precision
946 floating-point operations are usually more expensive than their
947 narrower counterparts.
948
949 For most machines, the macro definition does not change UNSIGNEDP.
950 However, some machines, have instructions that preferentially
951 handle either signed or unsigned quantities of certain modes. For
952 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
953 instructions sign-extend the result to 64 bits. On such machines,
954 set UNSIGNEDP according to which kind of extension is more
955 efficient.
956
957 Do not define this macro if it would never modify M.*/
958
959 #define BFIN_PROMOTE_MODE_P(MODE) \
960 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
961 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
962
963 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
964 if (BFIN_PROMOTE_MODE_P(MODE)) \
965 { \
966 if (MODE == QImode) \
967 UNSIGNEDP = 1; \
968 else if (MODE == HImode) \
969 UNSIGNEDP = 0; \
970 (MODE) = SImode; \
971 }
972
973 /* Describing Relative Costs of Operations */
974
975 /* Do not put function addr into constant pool */
976 #define NO_FUNCTION_CSE 1
977
978 /* Specify the machine mode that this machine uses
979 for the index in the tablejump instruction. */
980 #define CASE_VECTOR_MODE SImode
981
982 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
983
984 /* Define if operations between registers always perform the operation
985 on the full register even if a narrower mode is specified.
986 #define WORD_REGISTER_OPERATIONS 1
987 */
988
989 /* Evaluates to true if A and B are mac flags that can be used
990 together in a single multiply insn. That is the case if they are
991 both the same flag not involving M, or if one is a combination of
992 the other with M. */
993 #define MACFLAGS_MATCH_P(A, B) \
994 ((A) == (B) \
995 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
996 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
997 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
998 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
999
1000 /* Switch into a generic section. */
1001 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1002
1003 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1004 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1005
1006 typedef enum sections {
1007 CODE_DIR,
1008 DATA_DIR,
1009 LAST_SECT_NM
1010 } SECT_ENUM_T;
1011
1012 typedef enum directives {
1013 LONG_CONST_DIR,
1014 SHORT_CONST_DIR,
1015 BYTE_CONST_DIR,
1016 SPACE_DIR,
1017 INIT_DIR,
1018 LAST_DIR_NM
1019 } DIR_ENUM_T;
1020
1021 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1022 ((C) == ';' \
1023 || ((C) == '|' && (STR)[1] == '|'))
1024
1025 #define TEXT_SECTION_ASM_OP ".text;"
1026 #define DATA_SECTION_ASM_OP ".data;"
1027
1028 #define ASM_APP_ON ""
1029 #define ASM_APP_OFF ""
1030
1031 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1032 do { fputs (".global ", FILE); \
1033 assemble_name (FILE, NAME); \
1034 fputc (';',FILE); \
1035 fputc ('\n',FILE); \
1036 } while (0)
1037
1038 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1039 do { \
1040 fputs (".type ", FILE); \
1041 assemble_name (FILE, NAME); \
1042 fputs (", STT_FUNC", FILE); \
1043 fputc (';',FILE); \
1044 fputc ('\n',FILE); \
1045 ASM_OUTPUT_LABEL(FILE, NAME); \
1046 } while (0)
1047
1048 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1049 do { assemble_name (FILE, NAME); \
1050 fputs (":\n",FILE); \
1051 } while (0)
1052
1053 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1054 do { fprintf (FILE, "_%s", NAME); \
1055 } while (0)
1056
1057 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1058 do { char __buf[256]; \
1059 fprintf (FILE, "\t.dd\t"); \
1060 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1061 assemble_name (FILE, __buf); \
1062 fputc (';', FILE); \
1063 fputc ('\n', FILE); \
1064 } while (0)
1065
1066 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1067 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1068
1069 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1070 do { \
1071 char __buf[256]; \
1072 fprintf (FILE, "\t.dd\t"); \
1073 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1074 assemble_name (FILE, __buf); \
1075 fputs (" - ", FILE); \
1076 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1077 assemble_name (FILE, __buf); \
1078 fputc (';', FILE); \
1079 fputc ('\n', FILE); \
1080 } while (0)
1081
1082 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1083 do { \
1084 if ((LOG) != 0) \
1085 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1086 } while (0)
1087
1088 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1089 do { \
1090 asm_output_skip (FILE, SIZE); \
1091 } while (0)
1092
1093 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1094 do { \
1095 switch_to_section (data_section); \
1096 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1097 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1098 ASM_OUTPUT_LABEL (FILE, NAME); \
1099 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1100 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1101 } while (0)
1102
1103 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1104 do { \
1105 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1106 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1107
1108 #define ASM_COMMENT_START "//"
1109
1110 #define PROFILE_BEFORE_PROLOGUE
1111 #define FUNCTION_PROFILER(FILE, LABELNO) \
1112 do { \
1113 fprintf (FILE, "\t[--SP] = RETS;\n"); \
1114 if (TARGET_LONG_CALLS) \
1115 { \
1116 fprintf (FILE, "\tP2.h = __mcount;\n"); \
1117 fprintf (FILE, "\tP2.l = __mcount;\n"); \
1118 fprintf (FILE, "\tCALL (P2);\n"); \
1119 } \
1120 else \
1121 fprintf (FILE, "\tCALL __mcount;\n"); \
1122 fprintf (FILE, "\tRETS = [SP++];\n"); \
1123 } while(0)
1124
1125 #undef NO_PROFILE_COUNTERS
1126 #define NO_PROFILE_COUNTERS 1
1127
1128 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO])
1129 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO])
1130
1131 extern rtx bfin_cc_rtx, bfin_rets_rtx;
1132
1133 /* This works for GAS and some other assemblers. */
1134 #define SET_ASM_OP ".set "
1135
1136 /* DBX register number for a given compiler register number */
1137 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1138
1139 #define SIZE_ASM_OP "\t.size\t"
1140
1141 extern int splitting_for_sched, splitting_loops;
1142
1143 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1144
1145 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1146 #define TARGET_SUPPORTS_SYNC_CALLS 0
1147 #endif
1148
1149 struct bfin_cpu
1150 {
1151 const char *name;
1152 bfin_cpu_t type;
1153 int si_revision;
1154 unsigned int workarounds;
1155 };
1156
1157 extern const struct bfin_cpu bfin_cpus[];
1158
1159 #endif /* _BFIN_CONFIG */
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