Daily bump.
[official-gcc.git] / gcc / postreload.c
blobb12b8fe20733bf5f915c6641da5cb0c4b1159410
1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "target.h"
25 #include "rtl.h"
26 #include "tree.h"
27 #include "predict.h"
28 #include "df.h"
29 #include "memmodel.h"
30 #include "tm_p.h"
31 #include "optabs.h"
32 #include "regs.h"
33 #include "emit-rtl.h"
34 #include "recog.h"
36 #include "cfgrtl.h"
37 #include "cfgbuild.h"
38 #include "cfgcleanup.h"
39 #include "reload.h"
40 #include "cselib.h"
41 #include "tree-pass.h"
42 #include "dbgcnt.h"
43 #include "function-abi.h"
44 #include "rtl-iter.h"
46 static int reload_cse_noop_set_p (rtx);
47 static bool reload_cse_simplify (rtx_insn *, rtx);
48 static void reload_cse_regs_1 (void);
49 static int reload_cse_simplify_set (rtx, rtx_insn *);
50 static int reload_cse_simplify_operands (rtx_insn *, rtx);
52 static void reload_combine (void);
53 static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx);
54 static void reload_combine_note_store (rtx, const_rtx, void *);
56 static bool reload_cse_move2add (rtx_insn *);
57 static void move2add_note_store (rtx, const_rtx, void *);
59 /* Call cse / combine like post-reload optimization phases.
60 FIRST is the first instruction. */
62 static void
63 reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED)
65 bool moves_converted;
66 reload_cse_regs_1 ();
67 reload_combine ();
68 moves_converted = reload_cse_move2add (first);
69 if (flag_expensive_optimizations)
71 if (moves_converted)
72 reload_combine ();
73 reload_cse_regs_1 ();
77 /* See whether a single set SET is a noop. */
78 static int
79 reload_cse_noop_set_p (rtx set)
81 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
82 return 0;
84 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
87 /* Try to simplify INSN. Return true if the CFG may have changed. */
88 static bool
89 reload_cse_simplify (rtx_insn *insn, rtx testreg)
91 rtx body = PATTERN (insn);
92 basic_block insn_bb = BLOCK_FOR_INSN (insn);
93 unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
95 /* If NO_FUNCTION_CSE has been set by the target, then we should not try
96 to cse function calls. */
97 if (NO_FUNCTION_CSE && CALL_P (insn))
98 return false;
100 /* Remember if this insn has been sp += const_int. */
101 rtx sp_set = set_for_reg_notes (insn);
102 rtx sp_addend = NULL_RTX;
103 if (sp_set
104 && SET_DEST (sp_set) == stack_pointer_rtx
105 && GET_CODE (SET_SRC (sp_set)) == PLUS
106 && XEXP (SET_SRC (sp_set), 0) == stack_pointer_rtx
107 && CONST_INT_P (XEXP (SET_SRC (sp_set), 1)))
108 sp_addend = XEXP (SET_SRC (sp_set), 1);
110 if (GET_CODE (body) == SET)
112 int count = 0;
114 /* Simplify even if we may think it is a no-op.
115 We may think a memory load of a value smaller than WORD_SIZE
116 is redundant because we haven't taken into account possible
117 implicit extension. reload_cse_simplify_set() will bring
118 this out, so it's safer to simplify before we delete. */
119 count += reload_cse_simplify_set (body, insn);
121 if (!count && reload_cse_noop_set_p (body))
123 if (check_for_inc_dec (insn))
124 delete_insn_and_edges (insn);
125 /* We're done with this insn. */
126 goto done;
129 if (count > 0)
130 apply_change_group ();
131 else
132 reload_cse_simplify_operands (insn, testreg);
134 else if (GET_CODE (body) == PARALLEL)
136 int i;
137 int count = 0;
138 rtx value = NULL_RTX;
140 /* Registers mentioned in the clobber list for an asm cannot be reused
141 within the body of the asm. Invalidate those registers now so that
142 we don't try to substitute values for them. */
143 if (asm_noperands (body) >= 0)
145 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
147 rtx part = XVECEXP (body, 0, i);
148 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
149 cselib_invalidate_rtx (XEXP (part, 0));
153 /* If every action in a PARALLEL is a noop, we can delete
154 the entire PARALLEL. */
155 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
157 rtx part = XVECEXP (body, 0, i);
158 if (GET_CODE (part) == SET)
160 if (! reload_cse_noop_set_p (part))
161 break;
162 if (REG_P (SET_DEST (part))
163 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
165 if (value)
166 break;
167 value = SET_DEST (part);
170 else if (GET_CODE (part) != CLOBBER && GET_CODE (part) != USE)
171 break;
174 if (i < 0)
176 if (check_for_inc_dec (insn))
177 delete_insn_and_edges (insn);
178 /* We're done with this insn. */
179 goto done;
182 /* It's not a no-op, but we can try to simplify it. */
183 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
184 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
185 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
187 if (count > 0)
188 apply_change_group ();
189 else
190 reload_cse_simplify_operands (insn, testreg);
193 /* If sp += const_int insn is changed into sp = reg;, add REG_EQUAL
194 note so that the stack_adjustments pass can undo it if beneficial. */
195 if (sp_addend
196 && SET_DEST (sp_set) == stack_pointer_rtx
197 && REG_P (SET_SRC (sp_set)))
198 set_dst_reg_note (insn, REG_EQUAL,
199 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
200 sp_addend), stack_pointer_rtx);
202 done:
203 return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs);
206 /* Do a very simple CSE pass over the hard registers.
208 This function detects no-op moves where we happened to assign two
209 different pseudo-registers to the same hard register, and then
210 copied one to the other. Reload will generate a useless
211 instruction copying a register to itself.
213 This function also detects cases where we load a value from memory
214 into two different registers, and (if memory is more expensive than
215 registers) changes it to simply copy the first register into the
216 second register.
218 Another optimization is performed that scans the operands of each
219 instruction to see whether the value is already available in a
220 hard register. It then replaces the operand with the hard register
221 if possible, much like an optional reload would. */
223 static void
224 reload_cse_regs_1 (void)
226 bool cfg_changed = false;
227 basic_block bb;
228 rtx_insn *insn;
229 rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
231 cselib_init (CSELIB_RECORD_MEMORY);
232 init_alias_analysis ();
234 FOR_EACH_BB_FN (bb, cfun)
235 FOR_BB_INSNS (bb, insn)
237 if (INSN_P (insn))
238 cfg_changed |= reload_cse_simplify (insn, testreg);
240 cselib_process_insn (insn);
243 /* Clean up. */
244 end_alias_analysis ();
245 cselib_finish ();
246 if (cfg_changed)
247 cleanup_cfg (0);
250 /* Try to simplify a single SET instruction. SET is the set pattern.
251 INSN is the instruction it came from.
252 This function only handles one case: if we set a register to a value
253 which is not a register, we try to find that value in some other register
254 and change the set into a register copy. */
256 static int
257 reload_cse_simplify_set (rtx set, rtx_insn *insn)
259 int did_change = 0;
260 int dreg;
261 rtx src;
262 reg_class_t dclass;
263 int old_cost;
264 cselib_val *val;
265 struct elt_loc_list *l;
266 enum rtx_code extend_op = UNKNOWN;
267 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
269 dreg = true_regnum (SET_DEST (set));
270 if (dreg < 0)
271 return 0;
273 src = SET_SRC (set);
274 if (side_effects_p (src) || true_regnum (src) >= 0)
275 return 0;
277 dclass = REGNO_REG_CLASS (dreg);
279 /* When replacing a memory with a register, we need to honor assumptions
280 that combine made wrt the contents of sign bits. We'll do this by
281 generating an extend instruction instead of a reg->reg copy. Thus
282 the destination must be a register that we can widen. */
283 if (MEM_P (src)
284 && (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN
285 && !REG_P (SET_DEST (set)))
286 return 0;
288 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
289 if (! val)
290 return 0;
292 /* If memory loads are cheaper than register copies, don't change them. */
293 if (MEM_P (src))
294 old_cost = memory_move_cost (GET_MODE (src), dclass, true);
295 else if (REG_P (src))
296 old_cost = register_move_cost (GET_MODE (src),
297 REGNO_REG_CLASS (REGNO (src)), dclass);
298 else
299 old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed);
301 for (l = val->locs; l; l = l->next)
303 rtx this_rtx = l->loc;
304 int this_cost;
306 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
308 if (extend_op != UNKNOWN)
310 wide_int result;
312 if (!CONST_SCALAR_INT_P (this_rtx))
313 continue;
315 switch (extend_op)
317 case ZERO_EXTEND:
318 result = wide_int::from (rtx_mode_t (this_rtx,
319 GET_MODE (src)),
320 BITS_PER_WORD, UNSIGNED);
321 break;
322 case SIGN_EXTEND:
323 result = wide_int::from (rtx_mode_t (this_rtx,
324 GET_MODE (src)),
325 BITS_PER_WORD, SIGNED);
326 break;
327 default:
328 gcc_unreachable ();
330 this_rtx = immed_wide_int_const (result, word_mode);
333 this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed);
335 else if (REG_P (this_rtx))
337 if (extend_op != UNKNOWN)
339 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
340 this_cost = set_src_cost (this_rtx, word_mode, speed);
342 else
343 this_cost = register_move_cost (GET_MODE (this_rtx),
344 REGNO_REG_CLASS (REGNO (this_rtx)),
345 dclass);
347 else
348 continue;
350 /* If equal costs, prefer registers over anything else. That
351 tends to lead to smaller instructions on some machines. */
352 if (this_cost < old_cost
353 || (this_cost == old_cost
354 && REG_P (this_rtx)
355 && !REG_P (SET_SRC (set))))
357 if (extend_op != UNKNOWN
358 && REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),
359 GET_MODE (SET_DEST (set)), word_mode))
361 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
362 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
363 validate_change (insn, &SET_DEST (set), wide_dest, 1);
366 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
367 old_cost = this_cost, did_change = 1;
371 return did_change;
374 /* Try to replace operands in INSN with equivalent values that are already
375 in registers. This can be viewed as optional reloading.
377 For each non-register operand in the insn, see if any hard regs are
378 known to be equivalent to that operand. Record the alternatives which
379 can accept these hard registers. Among all alternatives, select the
380 ones which are better or equal to the one currently matching, where
381 "better" is in terms of '?' and '!' constraints. Among the remaining
382 alternatives, select the one which replaces most operands with
383 hard registers. */
385 static int
386 reload_cse_simplify_operands (rtx_insn *insn, rtx testreg)
388 int i, j;
390 /* For each operand, all registers that are equivalent to it. */
391 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
393 const char *constraints[MAX_RECOG_OPERANDS];
395 /* Vector recording how bad an alternative is. */
396 int *alternative_reject;
397 /* Vector recording how many registers can be introduced by choosing
398 this alternative. */
399 int *alternative_nregs;
400 /* Array of vectors recording, for each operand and each alternative,
401 which hard register to substitute, or -1 if the operand should be
402 left as it is. */
403 int *op_alt_regno[MAX_RECOG_OPERANDS];
404 /* Array of alternatives, sorted in order of decreasing desirability. */
405 int *alternative_order;
407 extract_constrain_insn (insn);
409 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
410 return 0;
412 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
413 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
414 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
415 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
416 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
418 /* For each operand, find out which regs are equivalent. */
419 for (i = 0; i < recog_data.n_operands; i++)
421 cselib_val *v;
422 struct elt_loc_list *l;
423 rtx op;
425 CLEAR_HARD_REG_SET (equiv_regs[i]);
427 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
428 right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL.
429 Likewise if we have a constant and the insn pattern doesn't tell us
430 the mode we need. */
431 if (LABEL_P (recog_data.operand[i])
432 || (NOTE_P (recog_data.operand[i])
433 && NOTE_KIND (recog_data.operand[i]) == NOTE_INSN_DELETED_LABEL)
434 || (CONSTANT_P (recog_data.operand[i])
435 && recog_data.operand_mode[i] == VOIDmode))
436 continue;
438 op = recog_data.operand[i];
439 if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN)
441 rtx set = single_set (insn);
443 /* We might have multiple sets, some of which do implicit
444 extension. Punt on this for now. */
445 if (! set)
446 continue;
447 /* If the destination is also a MEM or a STRICT_LOW_PART, no
448 extension applies.
449 Also, if there is an explicit extension, we don't have to
450 worry about an implicit one. */
451 else if (MEM_P (SET_DEST (set))
452 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
453 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND
454 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
455 ; /* Continue ordinary processing. */
456 /* If the register cannot change mode to word_mode, it follows that
457 it cannot have been used in word_mode. */
458 else if (REG_P (SET_DEST (set))
459 && !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),
460 GET_MODE (SET_DEST (set)),
461 word_mode))
462 ; /* Continue ordinary processing. */
463 /* If this is a straight load, make the extension explicit. */
464 else if (REG_P (SET_DEST (set))
465 && recog_data.n_operands == 2
466 && SET_SRC (set) == op
467 && SET_DEST (set) == recog_data.operand[1-i])
469 validate_change (insn, recog_data.operand_loc[i],
470 gen_rtx_fmt_e (load_extend_op (GET_MODE (op)),
471 word_mode, op),
473 validate_change (insn, recog_data.operand_loc[1-i],
474 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
476 if (! apply_change_group ())
477 return 0;
478 return reload_cse_simplify_operands (insn, testreg);
480 else
481 /* ??? There might be arithmetic operations with memory that are
482 safe to optimize, but is it worth the trouble? */
483 continue;
486 if (side_effects_p (op))
487 continue;
488 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
489 if (! v)
490 continue;
492 for (l = v->locs; l; l = l->next)
493 if (REG_P (l->loc))
494 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
497 alternative_mask preferred = get_preferred_alternatives (insn);
498 for (i = 0; i < recog_data.n_operands; i++)
500 machine_mode mode;
501 int regno;
502 const char *p;
504 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
505 for (j = 0; j < recog_data.n_alternatives; j++)
506 op_alt_regno[i][j] = -1;
508 p = constraints[i] = recog_data.constraints[i];
509 mode = recog_data.operand_mode[i];
511 /* Add the reject values for each alternative given by the constraints
512 for this operand. */
513 j = 0;
514 while (*p != '\0')
516 char c = *p++;
517 if (c == ',')
518 j++;
519 else if (c == '?')
520 alternative_reject[j] += 3;
521 else if (c == '!')
522 alternative_reject[j] += 300;
525 /* We won't change operands which are already registers. We
526 also don't want to modify output operands. */
527 regno = true_regnum (recog_data.operand[i]);
528 if (regno >= 0
529 || constraints[i][0] == '='
530 || constraints[i][0] == '+')
531 continue;
533 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
535 enum reg_class rclass = NO_REGS;
537 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
538 continue;
540 set_mode_and_regno (testreg, mode, regno);
542 /* We found a register equal to this operand. Now look for all
543 alternatives that can accept this register and have not been
544 assigned a register they can use yet. */
545 j = 0;
546 p = constraints[i];
547 for (;;)
549 char c = *p;
551 switch (c)
553 case 'g':
554 rclass = reg_class_subunion[rclass][GENERAL_REGS];
555 break;
557 default:
558 rclass
559 = (reg_class_subunion
560 [rclass]
561 [reg_class_for_constraint (lookup_constraint (p))]);
562 break;
564 case ',': case '\0':
565 /* See if REGNO fits this alternative, and set it up as the
566 replacement register if we don't have one for this
567 alternative yet and the operand being replaced is not
568 a cheap CONST_INT. */
569 if (op_alt_regno[i][j] == -1
570 && TEST_BIT (preferred, j)
571 && reg_fits_class_p (testreg, rclass, 0, mode)
572 && (!CONST_INT_P (recog_data.operand[i])
573 || (set_src_cost (recog_data.operand[i], mode,
574 optimize_bb_for_speed_p
575 (BLOCK_FOR_INSN (insn)))
576 > set_src_cost (testreg, mode,
577 optimize_bb_for_speed_p
578 (BLOCK_FOR_INSN (insn))))))
580 alternative_nregs[j]++;
581 op_alt_regno[i][j] = regno;
583 j++;
584 rclass = NO_REGS;
585 break;
587 p += CONSTRAINT_LEN (c, p);
589 if (c == '\0')
590 break;
595 /* The loop below sets alternative_order[0] but -Wmaybe-uninitialized
596 can't know that. Clear it here to avoid the warning. */
597 alternative_order[0] = 0;
598 gcc_assert (!recog_data.n_alternatives
599 || (which_alternative >= 0
600 && which_alternative < recog_data.n_alternatives));
602 /* Record all alternatives which are better or equal to the currently
603 matching one in the alternative_order array. */
604 for (i = j = 0; i < recog_data.n_alternatives; i++)
605 if (alternative_reject[i] <= alternative_reject[which_alternative])
606 alternative_order[j++] = i;
607 recog_data.n_alternatives = j;
609 /* Sort it. Given a small number of alternatives, a dumb algorithm
610 won't hurt too much. */
611 for (i = 0; i < recog_data.n_alternatives - 1; i++)
613 int best = i;
614 int best_reject = alternative_reject[alternative_order[i]];
615 int best_nregs = alternative_nregs[alternative_order[i]];
617 for (j = i + 1; j < recog_data.n_alternatives; j++)
619 int this_reject = alternative_reject[alternative_order[j]];
620 int this_nregs = alternative_nregs[alternative_order[j]];
622 if (this_reject < best_reject
623 || (this_reject == best_reject && this_nregs > best_nregs))
625 best = j;
626 best_reject = this_reject;
627 best_nregs = this_nregs;
631 std::swap (alternative_order[best], alternative_order[i]);
634 /* Substitute the operands as determined by op_alt_regno for the best
635 alternative. */
636 j = alternative_order[0];
638 for (i = 0; i < recog_data.n_operands; i++)
640 machine_mode mode = recog_data.operand_mode[i];
641 if (op_alt_regno[i][j] == -1)
642 continue;
644 validate_change (insn, recog_data.operand_loc[i],
645 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
648 for (i = recog_data.n_dups - 1; i >= 0; i--)
650 int op = recog_data.dup_num[i];
651 machine_mode mode = recog_data.operand_mode[op];
653 if (op_alt_regno[op][j] == -1)
654 continue;
656 validate_change (insn, recog_data.dup_loc[i],
657 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
660 return apply_change_group ();
663 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
664 addressing now.
665 This code might also be useful when reload gave up on reg+reg addressing
666 because of clashes between the return register and INDEX_REG_CLASS. */
668 /* The maximum number of uses of a register we can keep track of to
669 replace them with reg+reg addressing. */
670 #define RELOAD_COMBINE_MAX_USES 16
672 /* Describes a recorded use of a register. */
673 struct reg_use
675 /* The insn where a register has been used. */
676 rtx_insn *insn;
677 /* Points to the memory reference enclosing the use, if any, NULL_RTX
678 otherwise. */
679 rtx containing_mem;
680 /* Location of the register within INSN. */
681 rtx *usep;
682 /* The reverse uid of the insn. */
683 int ruid;
686 /* If the register is used in some unknown fashion, USE_INDEX is negative.
687 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
688 indicates where it is first set or clobbered.
689 Otherwise, USE_INDEX is the index of the last encountered use of the
690 register (which is first among these we have seen since we scan backwards).
691 USE_RUID indicates the first encountered, i.e. last, of these uses.
692 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
693 with a constant offset; OFFSET contains this constant in that case.
694 STORE_RUID is always meaningful if we only want to use a value in a
695 register in a different place: it denotes the next insn in the insn
696 stream (i.e. the last encountered) that sets or clobbers the register.
697 REAL_STORE_RUID is similar, but clobbers are ignored when updating it.
698 EXPR is the expression used when storing the register. */
699 static struct
701 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
702 rtx offset;
703 int use_index;
704 int store_ruid;
705 int real_store_ruid;
706 int use_ruid;
707 bool all_offsets_match;
708 rtx expr;
709 } reg_state[FIRST_PSEUDO_REGISTER];
711 /* Reverse linear uid. This is increased in reload_combine while scanning
712 the instructions from last to first. It is used to set last_label_ruid
713 and the store_ruid / use_ruid fields in reg_state. */
714 static int reload_combine_ruid;
716 /* The RUID of the last label we encountered in reload_combine. */
717 static int last_label_ruid;
719 /* The RUID of the last jump we encountered in reload_combine. */
720 static int last_jump_ruid;
722 /* The register numbers of the first and last index register. A value of
723 -1 in LAST_INDEX_REG indicates that we've previously computed these
724 values and found no suitable index registers. */
725 static int first_index_reg = -1;
726 static int last_index_reg;
728 #define LABEL_LIVE(LABEL) \
729 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
731 /* Subroutine of reload_combine_split_ruids, called to fix up a single
732 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
734 static inline void
735 reload_combine_split_one_ruid (int *pruid, int split_ruid)
737 if (*pruid > split_ruid)
738 (*pruid)++;
741 /* Called when we insert a new insn in a position we've already passed in
742 the scan. Examine all our state, increasing all ruids that are higher
743 than SPLIT_RUID by one in order to make room for a new insn. */
745 static void
746 reload_combine_split_ruids (int split_ruid)
748 unsigned i;
750 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
751 reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
752 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
754 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
756 int j, idx = reg_state[i].use_index;
757 reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
758 reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
759 reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
760 split_ruid);
761 if (idx < 0)
762 continue;
763 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
765 reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
766 split_ruid);
771 /* Called when we are about to rescan a previously encountered insn with
772 reload_combine_note_use after modifying some part of it. This clears all
773 information about uses in that particular insn. */
775 static void
776 reload_combine_purge_insn_uses (rtx_insn *insn)
778 unsigned i;
780 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
782 int j, k, idx = reg_state[i].use_index;
783 if (idx < 0)
784 continue;
785 j = k = RELOAD_COMBINE_MAX_USES;
786 while (j-- > idx)
788 if (reg_state[i].reg_use[j].insn != insn)
790 k--;
791 if (k != j)
792 reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
795 reg_state[i].use_index = k;
799 /* Called when we need to forget about all uses of REGNO after an insn
800 which is identified by RUID. */
802 static void
803 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
805 int j, k, idx = reg_state[regno].use_index;
806 if (idx < 0)
807 return;
808 j = k = RELOAD_COMBINE_MAX_USES;
809 while (j-- > idx)
811 if (reg_state[regno].reg_use[j].ruid >= ruid)
813 k--;
814 if (k != j)
815 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
818 reg_state[regno].use_index = k;
821 /* Find the use of REGNO with the ruid that is highest among those
822 lower than RUID_LIMIT, and return it if it is the only use of this
823 reg in the insn. Return NULL otherwise. */
825 static struct reg_use *
826 reload_combine_closest_single_use (unsigned regno, int ruid_limit)
828 int i, best_ruid = 0;
829 int use_idx = reg_state[regno].use_index;
830 struct reg_use *retval;
832 if (use_idx < 0)
833 return NULL;
834 retval = NULL;
835 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
837 struct reg_use *use = reg_state[regno].reg_use + i;
838 int this_ruid = use->ruid;
839 if (this_ruid >= ruid_limit)
840 continue;
841 if (this_ruid > best_ruid)
843 best_ruid = this_ruid;
844 retval = use;
846 else if (this_ruid == best_ruid)
847 retval = NULL;
849 if (last_label_ruid >= best_ruid)
850 return NULL;
851 return retval;
854 /* After we've moved an add insn, fix up any debug insns that occur
855 between the old location of the add and the new location. REG is
856 the destination register of the add insn; REPLACEMENT is the
857 SET_SRC of the add. FROM and TO specify the range in which we
858 should make this change on debug insns. */
860 static void
861 fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to)
863 rtx_insn *insn;
864 for (insn = from; insn != to; insn = NEXT_INSN (insn))
866 rtx t;
868 if (!DEBUG_BIND_INSN_P (insn))
869 continue;
871 t = INSN_VAR_LOCATION_LOC (insn);
872 t = simplify_replace_rtx (t, reg, replacement);
873 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
877 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
878 with SRC in the insn described by USE, taking costs into account. Return
879 true if we made the replacement. */
881 static bool
882 try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
884 rtx_insn *use_insn = use->insn;
885 rtx mem = use->containing_mem;
886 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
888 if (mem != NULL_RTX)
890 addr_space_t as = MEM_ADDR_SPACE (mem);
891 rtx oldaddr = XEXP (mem, 0);
892 rtx newaddr = NULL_RTX;
893 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
894 int new_cost;
896 newaddr = simplify_replace_rtx (oldaddr, reg, src);
897 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
899 XEXP (mem, 0) = newaddr;
900 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
901 XEXP (mem, 0) = oldaddr;
902 if (new_cost <= old_cost
903 && validate_change (use_insn,
904 &XEXP (mem, 0), newaddr, 0))
905 return true;
908 else
910 rtx new_set = single_set (use_insn);
911 if (new_set
912 && REG_P (SET_DEST (new_set))
913 && GET_CODE (SET_SRC (new_set)) == PLUS
914 && REG_P (XEXP (SET_SRC (new_set), 0))
915 && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
917 rtx new_src;
918 machine_mode mode = GET_MODE (SET_DEST (new_set));
919 int old_cost = set_src_cost (SET_SRC (new_set), mode, speed);
921 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
922 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
924 if (set_src_cost (new_src, mode, speed) <= old_cost
925 && validate_change (use_insn, &SET_SRC (new_set),
926 new_src, 0))
927 return true;
930 return false;
933 /* Called by reload_combine when scanning INSN. This function tries to detect
934 patterns where a constant is added to a register, and the result is used
935 in an address.
936 Return true if no further processing is needed on INSN; false if it wasn't
937 recognized and should be handled normally. */
939 static bool
940 reload_combine_recognize_const_pattern (rtx_insn *insn)
942 int from_ruid = reload_combine_ruid;
943 rtx set, pat, reg, src, addreg;
944 unsigned int regno;
945 struct reg_use *use;
946 bool must_move_add;
947 rtx_insn *add_moved_after_insn = NULL;
948 int add_moved_after_ruid = 0;
949 int clobbered_regno = -1;
951 set = single_set (insn);
952 if (set == NULL_RTX)
953 return false;
955 reg = SET_DEST (set);
956 src = SET_SRC (set);
957 if (!REG_P (reg)
958 || REG_NREGS (reg) != 1
959 || GET_MODE (reg) != Pmode
960 || reg == stack_pointer_rtx)
961 return false;
963 regno = REGNO (reg);
965 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
966 uses of REG1 inside an address, or inside another add insn. If
967 possible and profitable, merge the addition into subsequent
968 uses. */
969 if (GET_CODE (src) != PLUS
970 || !REG_P (XEXP (src, 0))
971 || !CONSTANT_P (XEXP (src, 1)))
972 return false;
974 addreg = XEXP (src, 0);
975 must_move_add = rtx_equal_p (reg, addreg);
977 pat = PATTERN (insn);
978 if (must_move_add && set != pat)
980 /* We have to be careful when moving the add; apart from the
981 single_set there may also be clobbers. Recognize one special
982 case, that of one clobber alongside the set (likely a clobber
983 of the CC register). */
984 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
985 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
986 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
987 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
988 return false;
989 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
994 use = reload_combine_closest_single_use (regno, from_ruid);
996 if (use)
997 /* Start the search for the next use from here. */
998 from_ruid = use->ruid;
1000 if (use && GET_MODE (*use->usep) == Pmode)
1002 bool delete_add = false;
1003 rtx_insn *use_insn = use->insn;
1004 int use_ruid = use->ruid;
1006 /* Avoid moving the add insn past a jump. */
1007 if (must_move_add && use_ruid <= last_jump_ruid)
1008 break;
1010 /* If the add clobbers another hard reg in parallel, don't move
1011 it past a real set of this hard reg. */
1012 if (must_move_add && clobbered_regno >= 0
1013 && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
1014 break;
1016 gcc_assert (reg_state[regno].store_ruid <= use_ruid);
1017 /* Avoid moving a use of ADDREG past a point where it is stored. */
1018 if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
1019 break;
1021 /* We also must not move the addition past an insn that sets
1022 the same register, unless we can combine two add insns. */
1023 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
1025 if (use->containing_mem == NULL_RTX)
1026 delete_add = true;
1027 else
1028 break;
1031 if (try_replace_in_use (use, reg, src))
1033 reload_combine_purge_insn_uses (use_insn);
1034 reload_combine_note_use (&PATTERN (use_insn), use_insn,
1035 use_ruid, NULL_RTX);
1037 if (delete_add)
1039 fixup_debug_insns (reg, src, insn, use_insn);
1040 delete_insn (insn);
1041 return true;
1043 if (must_move_add)
1045 add_moved_after_insn = use_insn;
1046 add_moved_after_ruid = use_ruid;
1048 continue;
1051 /* If we get here, we couldn't handle this use. */
1052 if (must_move_add)
1053 break;
1055 while (use);
1057 if (!must_move_add || add_moved_after_insn == NULL_RTX)
1058 /* Process the add normally. */
1059 return false;
1061 fixup_debug_insns (reg, src, insn, add_moved_after_insn);
1063 reorder_insns (insn, insn, add_moved_after_insn);
1064 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
1065 reload_combine_split_ruids (add_moved_after_ruid - 1);
1066 reload_combine_note_use (&PATTERN (insn), insn,
1067 add_moved_after_ruid, NULL_RTX);
1068 reg_state[regno].store_ruid = add_moved_after_ruid;
1070 return true;
1073 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1074 can handle and improve. Return true if no further processing is needed on
1075 INSN; false if it wasn't recognized and should be handled normally. */
1077 static bool
1078 reload_combine_recognize_pattern (rtx_insn *insn)
1080 rtx set, reg, src;
1082 set = single_set (insn);
1083 if (set == NULL_RTX)
1084 return false;
1086 reg = SET_DEST (set);
1087 src = SET_SRC (set);
1088 if (!REG_P (reg) || REG_NREGS (reg) != 1)
1089 return false;
1091 unsigned int regno = REGNO (reg);
1092 machine_mode mode = GET_MODE (reg);
1094 if (reg_state[regno].use_index < 0
1095 || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES)
1096 return false;
1098 for (int i = reg_state[regno].use_index;
1099 i < RELOAD_COMBINE_MAX_USES; i++)
1101 struct reg_use *use = reg_state[regno].reg_use + i;
1102 if (GET_MODE (*use->usep) != mode)
1103 return false;
1104 /* Don't try to adjust (use (REGX)). */
1105 if (GET_CODE (PATTERN (use->insn)) == USE
1106 && &XEXP (PATTERN (use->insn), 0) == use->usep)
1107 return false;
1110 /* Look for (set (REGX) (CONST_INT))
1111 (set (REGX) (PLUS (REGX) (REGY)))
1113 ... (MEM (REGX)) ...
1114 and convert it to
1115 (set (REGZ) (CONST_INT))
1117 ... (MEM (PLUS (REGZ) (REGY)))... .
1119 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1120 and that we know all uses of REGX before it dies.
1121 Also, explicitly check that REGX != REGY; our life information
1122 does not yet show whether REGY changes in this insn. */
1124 if (GET_CODE (src) == PLUS
1125 && reg_state[regno].all_offsets_match
1126 && last_index_reg != -1
1127 && REG_P (XEXP (src, 1))
1128 && rtx_equal_p (XEXP (src, 0), reg)
1129 && !rtx_equal_p (XEXP (src, 1), reg)
1130 && last_label_ruid < reg_state[regno].use_ruid)
1132 rtx base = XEXP (src, 1);
1133 rtx_insn *prev = prev_nonnote_nondebug_insn (insn);
1134 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1135 rtx index_reg = NULL_RTX;
1136 rtx reg_sum = NULL_RTX;
1137 int i;
1139 /* Now we need to set INDEX_REG to an index register (denoted as
1140 REGZ in the illustration above) and REG_SUM to the expression
1141 register+register that we want to use to substitute uses of REG
1142 (typically in MEMs) with. First check REG and BASE for being
1143 index registers; we can use them even if they are not dead. */
1144 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1145 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1146 REGNO (base)))
1148 index_reg = reg;
1149 reg_sum = src;
1151 else
1153 /* Otherwise, look for a free index register. Since we have
1154 checked above that neither REG nor BASE are index registers,
1155 if we find anything at all, it will be different from these
1156 two registers. */
1157 for (i = first_index_reg; i <= last_index_reg; i++)
1159 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
1160 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1161 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1162 && (crtl->abi->clobbers_full_reg_p (i)
1163 || df_regs_ever_live_p (i))
1164 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
1165 && !fixed_regs[i] && !global_regs[i]
1166 && hard_regno_nregs (i, GET_MODE (reg)) == 1
1167 && targetm.hard_regno_scratch_ok (i))
1169 index_reg = gen_rtx_REG (GET_MODE (reg), i);
1170 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1171 break;
1176 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1177 (REGY), i.e. BASE, is not clobbered before the last use we'll
1178 create. */
1179 if (reg_sum
1180 && prev_set
1181 && CONST_INT_P (SET_SRC (prev_set))
1182 && rtx_equal_p (SET_DEST (prev_set), reg)
1183 && (reg_state[REGNO (base)].store_ruid
1184 <= reg_state[regno].use_ruid))
1186 /* Change destination register and, if necessary, the constant
1187 value in PREV, the constant loading instruction. */
1188 validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1189 if (reg_state[regno].offset != const0_rtx)
1191 HOST_WIDE_INT c
1192 = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set))
1193 + UINTVAL (reg_state[regno].offset),
1194 GET_MODE (index_reg));
1195 validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1);
1198 /* Now for every use of REG that we have recorded, replace REG
1199 with REG_SUM. */
1200 for (i = reg_state[regno].use_index;
1201 i < RELOAD_COMBINE_MAX_USES; i++)
1202 validate_unshare_change (reg_state[regno].reg_use[i].insn,
1203 reg_state[regno].reg_use[i].usep,
1204 /* Each change must have its own
1205 replacement. */
1206 reg_sum, 1);
1208 if (apply_change_group ())
1210 struct reg_use *lowest_ruid = NULL;
1212 /* For every new use of REG_SUM, we have to record the use
1213 of BASE therein, i.e. operand 1. */
1214 for (i = reg_state[regno].use_index;
1215 i < RELOAD_COMBINE_MAX_USES; i++)
1217 struct reg_use *use = reg_state[regno].reg_use + i;
1218 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
1219 use->ruid, use->containing_mem);
1220 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
1221 lowest_ruid = use;
1224 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
1226 /* Delete the reg-reg addition. */
1227 delete_insn (insn);
1229 if (reg_state[regno].offset != const0_rtx)
1230 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1231 are now invalid. */
1232 remove_reg_equal_equiv_notes (prev);
1234 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1235 return true;
1239 return false;
1242 static void
1243 reload_combine (void)
1245 rtx_insn *insn, *prev;
1246 basic_block bb;
1247 unsigned int r;
1248 int min_labelno, n_labels;
1249 HARD_REG_SET ever_live_at_start, *label_live;
1251 /* To avoid wasting too much time later searching for an index register,
1252 determine the minimum and maximum index register numbers. */
1253 if (INDEX_REG_CLASS == NO_REGS)
1254 last_index_reg = -1;
1255 else if (first_index_reg == -1 && last_index_reg == 0)
1257 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1258 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1260 if (first_index_reg == -1)
1261 first_index_reg = r;
1263 last_index_reg = r;
1266 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1267 to -1 so we'll know to quit early the next time we get here. */
1268 if (first_index_reg == -1)
1270 last_index_reg = -1;
1271 return;
1275 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1276 information is a bit fuzzy immediately after reload, but it's
1277 still good enough to determine which registers are live at a jump
1278 destination. */
1279 min_labelno = get_first_label_num ();
1280 n_labels = max_label_num () - min_labelno;
1281 label_live = XNEWVEC (HARD_REG_SET, n_labels);
1282 CLEAR_HARD_REG_SET (ever_live_at_start);
1284 FOR_EACH_BB_REVERSE_FN (bb, cfun)
1286 insn = BB_HEAD (bb);
1287 if (LABEL_P (insn))
1289 HARD_REG_SET live;
1290 bitmap live_in = df_get_live_in (bb);
1292 REG_SET_TO_HARD_REG_SET (live, live_in);
1293 compute_use_by_pseudos (&live, live_in);
1294 LABEL_LIVE (insn) = live;
1295 ever_live_at_start |= live;
1299 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1300 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1301 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1303 reg_state[r].store_ruid = 0;
1304 reg_state[r].real_store_ruid = 0;
1305 if (fixed_regs[r])
1306 reg_state[r].use_index = -1;
1307 else
1308 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1311 for (insn = get_last_insn (); insn; insn = prev)
1313 bool control_flow_insn;
1314 rtx note;
1316 prev = PREV_INSN (insn);
1318 /* We cannot do our optimization across labels. Invalidating all the use
1319 information we have would be costly, so we just note where the label
1320 is and then later disable any optimization that would cross it. */
1321 if (LABEL_P (insn))
1322 last_label_ruid = reload_combine_ruid;
1323 else if (BARRIER_P (insn))
1325 /* Crossing a barrier resets all the use information. */
1326 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1327 if (! fixed_regs[r])
1328 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1330 else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn)))
1331 /* Optimizations across insns being marked as volatile must be
1332 prevented. All the usage information is invalidated
1333 here. */
1334 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1335 if (! fixed_regs[r]
1336 && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES)
1337 reg_state[r].use_index = -1;
1339 if (! NONDEBUG_INSN_P (insn))
1340 continue;
1342 reload_combine_ruid++;
1344 control_flow_insn = control_flow_insn_p (insn);
1345 if (control_flow_insn)
1346 last_jump_ruid = reload_combine_ruid;
1348 if (reload_combine_recognize_const_pattern (insn)
1349 || reload_combine_recognize_pattern (insn))
1350 continue;
1352 note_stores (insn, reload_combine_note_store, NULL);
1354 if (CALL_P (insn))
1356 rtx link;
1357 HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers ();
1359 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1360 if (TEST_HARD_REG_BIT (used_regs, r))
1362 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1363 reg_state[r].store_ruid = reload_combine_ruid;
1366 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
1367 link = XEXP (link, 1))
1369 rtx setuse = XEXP (link, 0);
1370 rtx usage_rtx = XEXP (setuse, 0);
1372 if (GET_CODE (setuse) == USE && REG_P (usage_rtx))
1374 unsigned int end_regno = END_REGNO (usage_rtx);
1375 for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i)
1376 reg_state[i].use_index = -1;
1381 if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn)))
1383 /* Non-spill registers might be used at the call destination in
1384 some unknown fashion, so we have to mark the unknown use. */
1385 HARD_REG_SET *live;
1387 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
1388 && JUMP_LABEL (insn))
1390 if (ANY_RETURN_P (JUMP_LABEL (insn)))
1391 live = NULL;
1392 else
1393 live = &LABEL_LIVE (JUMP_LABEL (insn));
1395 else
1396 live = &ever_live_at_start;
1398 if (live)
1399 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1400 if (TEST_HARD_REG_BIT (*live, r))
1401 reg_state[r].use_index = -1;
1404 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
1405 NULL_RTX);
1407 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1409 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0)))
1411 int regno = REGNO (XEXP (note, 0));
1412 reg_state[regno].store_ruid = reload_combine_ruid;
1413 reg_state[regno].real_store_ruid = reload_combine_ruid;
1414 reg_state[regno].use_index = -1;
1419 free (label_live);
1422 /* Check if DST is a register or a subreg of a register; if it is,
1423 update store_ruid, real_store_ruid and use_index in the reg_state
1424 structure accordingly. Called via note_stores from reload_combine. */
1426 static void
1427 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1429 int regno = 0;
1430 int i;
1431 machine_mode mode = GET_MODE (dst);
1433 if (GET_CODE (dst) == SUBREG)
1435 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
1436 GET_MODE (SUBREG_REG (dst)),
1437 SUBREG_BYTE (dst),
1438 GET_MODE (dst));
1439 dst = SUBREG_REG (dst);
1442 /* Some targets do argument pushes without adding REG_INC notes. */
1444 if (MEM_P (dst))
1446 dst = XEXP (dst, 0);
1447 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
1448 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC
1449 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY)
1451 unsigned int end_regno = END_REGNO (XEXP (dst, 0));
1452 for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i)
1454 /* We could probably do better, but for now mark the register
1455 as used in an unknown fashion and set/clobbered at this
1456 insn. */
1457 reg_state[i].use_index = -1;
1458 reg_state[i].store_ruid = reload_combine_ruid;
1459 reg_state[i].real_store_ruid = reload_combine_ruid;
1462 else
1463 return;
1466 if (!REG_P (dst))
1467 return;
1468 regno += REGNO (dst);
1470 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1471 careful with registers / register parts that are not full words.
1472 Similarly for ZERO_EXTRACT. */
1473 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1474 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1476 for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--)
1478 reg_state[i].use_index = -1;
1479 reg_state[i].store_ruid = reload_combine_ruid;
1480 reg_state[i].real_store_ruid = reload_combine_ruid;
1483 else
1485 for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--)
1487 reg_state[i].store_ruid = reload_combine_ruid;
1488 if (GET_CODE (set) == SET)
1489 reg_state[i].real_store_ruid = reload_combine_ruid;
1490 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1495 /* XP points to a piece of rtl that has to be checked for any uses of
1496 registers.
1497 *XP is the pattern of INSN, or a part of it.
1498 Called from reload_combine, and recursively by itself. */
1499 static void
1500 reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem)
1502 rtx x = *xp;
1503 enum rtx_code code = x->code;
1504 const char *fmt;
1505 int i, j;
1506 rtx offset = const0_rtx; /* For the REG case below. */
1508 switch (code)
1510 case SET:
1511 if (REG_P (SET_DEST (x)))
1513 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1514 return;
1516 break;
1518 case USE:
1519 /* If this is the USE of a return value, we can't change it. */
1520 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
1522 /* Mark the return register as used in an unknown fashion. */
1523 rtx reg = XEXP (x, 0);
1524 unsigned int end_regno = END_REGNO (reg);
1525 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
1526 reg_state[regno].use_index = -1;
1527 return;
1529 break;
1531 case CLOBBER:
1532 if (REG_P (SET_DEST (x)))
1534 /* No spurious CLOBBERs of pseudo registers may remain. */
1535 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER);
1536 return;
1538 break;
1540 case PLUS:
1541 /* We are interested in (plus (reg) (const_int)) . */
1542 if (!REG_P (XEXP (x, 0))
1543 || !CONST_INT_P (XEXP (x, 1)))
1544 break;
1545 offset = XEXP (x, 1);
1546 x = XEXP (x, 0);
1547 /* Fall through. */
1548 case REG:
1550 int regno = REGNO (x);
1551 int use_index;
1552 int nregs;
1554 /* No spurious USEs of pseudo registers may remain. */
1555 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
1557 nregs = REG_NREGS (x);
1559 /* We can't substitute into multi-hard-reg uses. */
1560 if (nregs > 1)
1562 while (--nregs >= 0)
1563 reg_state[regno + nregs].use_index = -1;
1564 return;
1567 /* We may be called to update uses in previously seen insns.
1568 Don't add uses beyond the last store we saw. */
1569 if (ruid < reg_state[regno].store_ruid)
1570 return;
1572 /* If this register is already used in some unknown fashion, we
1573 can't do anything.
1574 If we decrement the index from zero to -1, we can't store more
1575 uses, so this register becomes used in an unknown fashion. */
1576 use_index = --reg_state[regno].use_index;
1577 if (use_index < 0)
1578 return;
1580 if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1582 /* This is the first use of this register we have seen since we
1583 marked it as dead. */
1584 reg_state[regno].offset = offset;
1585 reg_state[regno].all_offsets_match = true;
1586 reg_state[regno].use_ruid = ruid;
1588 else
1590 if (reg_state[regno].use_ruid > ruid)
1591 reg_state[regno].use_ruid = ruid;
1593 if (! rtx_equal_p (offset, reg_state[regno].offset))
1594 reg_state[regno].all_offsets_match = false;
1597 reg_state[regno].reg_use[use_index].insn = insn;
1598 reg_state[regno].reg_use[use_index].ruid = ruid;
1599 reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1600 reg_state[regno].reg_use[use_index].usep = xp;
1601 return;
1604 case MEM:
1605 containing_mem = x;
1606 break;
1608 default:
1609 break;
1612 /* Recursively process the components of X. */
1613 fmt = GET_RTX_FORMAT (code);
1614 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1616 if (fmt[i] == 'e')
1617 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1618 else if (fmt[i] == 'E')
1620 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1621 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1622 containing_mem);
1627 /* See if we can reduce the cost of a constant by replacing a move
1628 with an add. We track situations in which a register is set to a
1629 constant or to a register plus a constant. */
1630 /* We cannot do our optimization across labels. Invalidating all the
1631 information about register contents we have would be costly, so we
1632 use move2add_last_label_luid to note where the label is and then
1633 later disable any optimization that would cross it.
1634 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1635 are only valid if reg_set_luid[n] is greater than
1636 move2add_last_label_luid.
1637 For a set that established a new (potential) base register with
1638 non-constant value, we use move2add_luid from the place where the
1639 setting insn is encountered; registers based off that base then
1640 get the same reg_set_luid. Constants all get
1641 move2add_last_label_luid + 1 as their reg_set_luid. */
1642 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
1644 /* If reg_base_reg[n] is negative, register n has been set to
1645 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1646 If reg_base_reg[n] is non-negative, register n has been set to the
1647 sum of reg_offset[n] and the value of register reg_base_reg[n]
1648 before reg_set_luid[n], calculated in mode reg_mode[n] .
1649 For multi-hard-register registers, all but the first one are
1650 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1651 marks it as invalid. */
1652 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
1653 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
1654 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
1655 static machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
1657 /* move2add_luid is linearly increased while scanning the instructions
1658 from first to last. It is used to set reg_set_luid in
1659 reload_cse_move2add and move2add_note_store. */
1660 static int move2add_luid;
1662 /* move2add_last_label_luid is set whenever a label is found. Labels
1663 invalidate all previously collected reg_offset data. */
1664 static int move2add_last_label_luid;
1666 /* ??? We don't know how zero / sign extension is handled, hence we
1667 can't go from a narrower to a wider mode. */
1668 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1669 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1670 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1671 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1673 /* Record that REG is being set to a value with the mode of REG. */
1675 static void
1676 move2add_record_mode (rtx reg)
1678 int regno, nregs;
1679 machine_mode mode = GET_MODE (reg);
1681 if (GET_CODE (reg) == SUBREG)
1683 regno = subreg_regno (reg);
1684 nregs = subreg_nregs (reg);
1686 else if (REG_P (reg))
1688 regno = REGNO (reg);
1689 nregs = REG_NREGS (reg);
1691 else
1692 gcc_unreachable ();
1693 for (int i = nregs - 1; i > 0; i--)
1694 reg_mode[regno + i] = BLKmode;
1695 reg_mode[regno] = mode;
1698 /* Record that REG is being set to the sum of SYM and OFF. */
1700 static void
1701 move2add_record_sym_value (rtx reg, rtx sym, rtx off)
1703 int regno = REGNO (reg);
1705 move2add_record_mode (reg);
1706 reg_set_luid[regno] = move2add_luid;
1707 reg_base_reg[regno] = -1;
1708 reg_symbol_ref[regno] = sym;
1709 reg_offset[regno] = INTVAL (off);
1712 /* Check if REGNO contains a valid value in MODE. */
1714 static bool
1715 move2add_valid_value_p (int regno, scalar_int_mode mode)
1717 if (reg_set_luid[regno] <= move2add_last_label_luid)
1718 return false;
1720 if (mode != reg_mode[regno])
1722 scalar_int_mode old_mode;
1723 if (!is_a <scalar_int_mode> (reg_mode[regno], &old_mode)
1724 || !MODES_OK_FOR_MOVE2ADD (mode, old_mode)
1725 || !REG_CAN_CHANGE_MODE_P (regno, old_mode, mode))
1726 return false;
1727 /* The value loaded into regno in reg_mode[regno] is also valid in
1728 mode after truncation only if (REG:mode regno) is the lowpart of
1729 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1730 regno of the lowpart might be different. */
1731 poly_int64 s_off = subreg_lowpart_offset (mode, old_mode);
1732 s_off = subreg_regno_offset (regno, old_mode, s_off, mode);
1733 if (maybe_ne (s_off, 0))
1734 /* We could in principle adjust regno, check reg_mode[regno] to be
1735 BLKmode, and return s_off to the caller (vs. -1 for failure),
1736 but we currently have no callers that could make use of this
1737 information. */
1738 return false;
1741 for (int i = end_hard_regno (mode, regno) - 1; i > regno; i--)
1742 if (reg_mode[i] != BLKmode)
1743 return false;
1744 return true;
1747 /* This function is called with INSN that sets REG (of mode MODE)
1748 to (SYM + OFF), while REG is known to already have value (SYM + offset).
1749 This function tries to change INSN into an add instruction
1750 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1751 It also updates the information about REG's known value.
1752 Return true if we made a change. */
1754 static bool
1755 move2add_use_add2_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off,
1756 rtx_insn *insn)
1758 rtx pat = PATTERN (insn);
1759 rtx src = SET_SRC (pat);
1760 int regno = REGNO (reg);
1761 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], mode);
1762 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1763 bool changed = false;
1765 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1766 use (set (reg) (reg)) instead.
1767 We don't delete this insn, nor do we convert it into a
1768 note, to avoid losing register notes or the return
1769 value flag. jump2 already knows how to get rid of
1770 no-op moves. */
1771 if (new_src == const0_rtx)
1773 /* If the constants are different, this is a
1774 truncation, that, if turned into (set (reg)
1775 (reg)), would be discarded. Maybe we should
1776 try a truncMN pattern? */
1777 if (INTVAL (off) == reg_offset [regno])
1778 changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1780 else
1782 struct full_rtx_costs oldcst, newcst;
1783 rtx tem = gen_rtx_PLUS (mode, reg, new_src);
1785 get_full_set_rtx_cost (pat, &oldcst);
1786 SET_SRC (pat) = tem;
1787 get_full_set_rtx_cost (pat, &newcst);
1788 SET_SRC (pat) = src;
1790 if (costs_lt_p (&newcst, &oldcst, speed)
1791 && have_add2_insn (reg, new_src))
1792 changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1793 else if (sym == NULL_RTX && mode != BImode)
1795 scalar_int_mode narrow_mode;
1796 FOR_EACH_MODE_UNTIL (narrow_mode, mode)
1798 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
1799 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
1800 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
1802 rtx narrow_reg = gen_lowpart_common (narrow_mode, reg);
1803 rtx narrow_src = gen_int_mode (INTVAL (off),
1804 narrow_mode);
1805 rtx new_set
1806 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode,
1807 narrow_reg),
1808 narrow_src);
1809 get_full_set_rtx_cost (new_set, &newcst);
1810 if (costs_lt_p (&newcst, &oldcst, speed))
1812 changed = validate_change (insn, &PATTERN (insn),
1813 new_set, 0);
1814 if (changed)
1815 break;
1821 move2add_record_sym_value (reg, sym, off);
1822 return changed;
1826 /* This function is called with INSN that sets REG (of mode MODE) to
1827 (SYM + OFF), but REG doesn't have known value (SYM + offset). This
1828 function tries to find another register which is known to already have
1829 value (SYM + offset) and change INSN into an add instruction
1830 (set (REG) (plus (the found register) (OFF - offset))) if such
1831 a register is found. It also updates the information about
1832 REG's known value.
1833 Return true iff we made a change. */
1835 static bool
1836 move2add_use_add3_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off,
1837 rtx_insn *insn)
1839 rtx pat = PATTERN (insn);
1840 rtx src = SET_SRC (pat);
1841 int regno = REGNO (reg);
1842 int min_regno = 0;
1843 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1844 int i;
1845 bool changed = false;
1846 struct full_rtx_costs oldcst, newcst, mincst;
1847 rtx plus_expr;
1849 init_costs_to_max (&mincst);
1850 get_full_set_rtx_cost (pat, &oldcst);
1852 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
1853 SET_SRC (pat) = plus_expr;
1855 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1856 if (move2add_valid_value_p (i, mode)
1857 && reg_base_reg[i] < 0
1858 && reg_symbol_ref[i] != NULL_RTX
1859 && rtx_equal_p (sym, reg_symbol_ref[i]))
1861 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i],
1862 GET_MODE (reg));
1863 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1864 use (set (reg) (reg)) instead.
1865 We don't delete this insn, nor do we convert it into a
1866 note, to avoid losing register notes or the return
1867 value flag. jump2 already knows how to get rid of
1868 no-op moves. */
1869 if (new_src == const0_rtx)
1871 init_costs_to_zero (&mincst);
1872 min_regno = i;
1873 break;
1875 else
1877 XEXP (plus_expr, 1) = new_src;
1878 get_full_set_rtx_cost (pat, &newcst);
1880 if (costs_lt_p (&newcst, &mincst, speed))
1882 mincst = newcst;
1883 min_regno = i;
1887 SET_SRC (pat) = src;
1889 if (costs_lt_p (&mincst, &oldcst, speed))
1891 rtx tem;
1893 tem = gen_rtx_REG (GET_MODE (reg), min_regno);
1894 if (i != min_regno)
1896 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno],
1897 GET_MODE (reg));
1898 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1900 if (validate_change (insn, &SET_SRC (pat), tem, 0))
1901 changed = true;
1903 reg_set_luid[regno] = move2add_luid;
1904 move2add_record_sym_value (reg, sym, off);
1905 return changed;
1908 /* Convert move insns with constant inputs to additions if they are cheaper.
1909 Return true if any changes were made. */
1910 static bool
1911 reload_cse_move2add (rtx_insn *first)
1913 int i;
1914 rtx_insn *insn;
1915 bool changed = false;
1917 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1919 reg_set_luid[i] = 0;
1920 reg_offset[i] = 0;
1921 reg_base_reg[i] = 0;
1922 reg_symbol_ref[i] = NULL_RTX;
1923 reg_mode[i] = VOIDmode;
1926 move2add_last_label_luid = 0;
1927 move2add_luid = 2;
1928 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
1930 rtx pat, note;
1932 if (LABEL_P (insn))
1934 move2add_last_label_luid = move2add_luid;
1935 /* We're going to increment move2add_luid twice after a
1936 label, so that we can use move2add_last_label_luid + 1 as
1937 the luid for constants. */
1938 move2add_luid++;
1939 continue;
1941 if (! INSN_P (insn))
1942 continue;
1943 pat = PATTERN (insn);
1944 /* For simplicity, we only perform this optimization on
1945 straightforward SETs. */
1946 scalar_int_mode mode;
1947 if (GET_CODE (pat) == SET
1948 && REG_P (SET_DEST (pat))
1949 && is_a <scalar_int_mode> (GET_MODE (SET_DEST (pat)), &mode))
1951 rtx reg = SET_DEST (pat);
1952 int regno = REGNO (reg);
1953 rtx src = SET_SRC (pat);
1955 /* Check if we have valid information on the contents of this
1956 register in the mode of REG. */
1957 if (move2add_valid_value_p (regno, mode)
1958 && dbg_cnt (cse2_move2add))
1960 /* Try to transform (set (REGX) (CONST_INT A))
1962 (set (REGX) (CONST_INT B))
1964 (set (REGX) (CONST_INT A))
1966 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1968 (set (REGX) (CONST_INT A))
1970 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1973 if (CONST_INT_P (src)
1974 && reg_base_reg[regno] < 0
1975 && reg_symbol_ref[regno] == NULL_RTX)
1977 changed |= move2add_use_add2_insn (mode, reg, NULL_RTX,
1978 src, insn);
1979 continue;
1982 /* Try to transform (set (REGX) (REGY))
1983 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1985 (set (REGX) (REGY))
1986 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1988 (set (REGX) (REGY))
1989 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1991 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1992 else if (REG_P (src)
1993 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
1994 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
1995 && move2add_valid_value_p (REGNO (src), mode))
1997 rtx_insn *next = next_nonnote_nondebug_insn (insn);
1998 rtx set = NULL_RTX;
1999 if (next)
2000 set = single_set (next);
2001 if (set
2002 && SET_DEST (set) == reg
2003 && GET_CODE (SET_SRC (set)) == PLUS
2004 && XEXP (SET_SRC (set), 0) == reg
2005 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
2007 rtx src3 = XEXP (SET_SRC (set), 1);
2008 unsigned HOST_WIDE_INT added_offset = UINTVAL (src3);
2009 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
2010 HOST_WIDE_INT regno_offset = reg_offset[regno];
2011 rtx new_src =
2012 gen_int_mode (added_offset
2013 + base_offset
2014 - regno_offset,
2015 mode);
2016 bool success = false;
2017 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
2019 if (new_src == const0_rtx)
2020 /* See above why we create (set (reg) (reg)) here. */
2021 success
2022 = validate_change (next, &SET_SRC (set), reg, 0);
2023 else
2025 rtx old_src = SET_SRC (set);
2026 struct full_rtx_costs oldcst, newcst;
2027 rtx tem = gen_rtx_PLUS (mode, reg, new_src);
2029 get_full_set_rtx_cost (set, &oldcst);
2030 SET_SRC (set) = tem;
2031 get_full_set_src_cost (tem, mode, &newcst);
2032 SET_SRC (set) = old_src;
2033 costs_add_n_insns (&oldcst, 1);
2035 if (costs_lt_p (&newcst, &oldcst, speed)
2036 && have_add2_insn (reg, new_src))
2038 rtx newpat = gen_rtx_SET (reg, tem);
2039 success
2040 = validate_change (next, &PATTERN (next),
2041 newpat, 0);
2044 if (success)
2045 delete_insn (insn);
2046 changed |= success;
2047 insn = next;
2048 move2add_record_mode (reg);
2049 reg_offset[regno]
2050 = trunc_int_for_mode (added_offset + base_offset,
2051 mode);
2052 continue;
2057 /* Try to transform
2058 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2060 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2062 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2064 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2065 if ((GET_CODE (src) == SYMBOL_REF
2066 || (GET_CODE (src) == CONST
2067 && GET_CODE (XEXP (src, 0)) == PLUS
2068 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
2069 && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
2070 && dbg_cnt (cse2_move2add))
2072 rtx sym, off;
2074 if (GET_CODE (src) == SYMBOL_REF)
2076 sym = src;
2077 off = const0_rtx;
2079 else
2081 sym = XEXP (XEXP (src, 0), 0);
2082 off = XEXP (XEXP (src, 0), 1);
2085 /* If the reg already contains the value which is sum of
2086 sym and some constant value, we can use an add2 insn. */
2087 if (move2add_valid_value_p (regno, mode)
2088 && reg_base_reg[regno] < 0
2089 && reg_symbol_ref[regno] != NULL_RTX
2090 && rtx_equal_p (sym, reg_symbol_ref[regno]))
2091 changed |= move2add_use_add2_insn (mode, reg, sym, off, insn);
2093 /* Otherwise, we have to find a register whose value is sum
2094 of sym and some constant value. */
2095 else
2096 changed |= move2add_use_add3_insn (mode, reg, sym, off, insn);
2098 continue;
2102 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2104 if (REG_NOTE_KIND (note) == REG_INC
2105 && REG_P (XEXP (note, 0)))
2107 /* Reset the information about this register. */
2108 int regno = REGNO (XEXP (note, 0));
2109 if (regno < FIRST_PSEUDO_REGISTER)
2111 move2add_record_mode (XEXP (note, 0));
2112 reg_mode[regno] = VOIDmode;
2117 /* There are no REG_INC notes for SP autoinc. */
2118 subrtx_var_iterator::array_type array;
2119 FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST)
2121 rtx mem = *iter;
2122 if (mem
2123 && MEM_P (mem)
2124 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0))) == RTX_AUTOINC)
2126 if (XEXP (XEXP (mem, 0), 0) == stack_pointer_rtx)
2127 reg_mode[STACK_POINTER_REGNUM] = VOIDmode;
2131 note_stores (insn, move2add_note_store, insn);
2133 /* If INSN is a conditional branch, we try to extract an
2134 implicit set out of it. */
2135 if (any_condjump_p (insn))
2137 rtx cnd = fis_get_condition (insn);
2139 if (cnd != NULL_RTX
2140 && GET_CODE (cnd) == NE
2141 && REG_P (XEXP (cnd, 0))
2142 && !reg_set_p (XEXP (cnd, 0), insn)
2143 /* The following two checks, which are also in
2144 move2add_note_store, are intended to reduce the
2145 number of calls to gen_rtx_SET to avoid memory
2146 allocation if possible. */
2147 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
2148 && REG_NREGS (XEXP (cnd, 0)) == 1
2149 && CONST_INT_P (XEXP (cnd, 1)))
2151 rtx implicit_set =
2152 gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1));
2153 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
2157 /* If this is a CALL_INSN, all call used registers are stored with
2158 unknown values. */
2159 if (CALL_P (insn))
2161 function_abi callee_abi = insn_callee_abi (insn);
2162 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
2163 if (reg_mode[i] != VOIDmode
2164 && reg_mode[i] != BLKmode
2165 && callee_abi.clobbers_reg_p (reg_mode[i], i))
2166 /* Reset the information about this register. */
2167 reg_mode[i] = VOIDmode;
2170 return changed;
2173 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2174 contains SET.
2175 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2176 Called from reload_cse_move2add via note_stores. */
2178 static void
2179 move2add_note_store (rtx dst, const_rtx set, void *data)
2181 rtx_insn *insn = (rtx_insn *) data;
2182 unsigned int regno = 0;
2183 scalar_int_mode mode;
2185 if (GET_CODE (dst) == SUBREG)
2186 regno = subreg_regno (dst);
2187 else if (REG_P (dst))
2188 regno = REGNO (dst);
2189 else
2190 return;
2192 if (!is_a <scalar_int_mode> (GET_MODE (dst), &mode))
2193 goto invalidate;
2195 if (GET_CODE (set) == SET)
2197 rtx note, sym = NULL_RTX;
2198 rtx off;
2200 note = find_reg_equal_equiv_note (insn);
2201 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
2203 sym = XEXP (note, 0);
2204 off = const0_rtx;
2206 else if (note && GET_CODE (XEXP (note, 0)) == CONST
2207 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
2208 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
2209 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
2211 sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
2212 off = XEXP (XEXP (XEXP (note, 0), 0), 1);
2215 if (sym != NULL_RTX)
2217 move2add_record_sym_value (dst, sym, off);
2218 return;
2222 if (GET_CODE (set) == SET
2223 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2224 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
2226 rtx src = SET_SRC (set);
2227 rtx base_reg;
2228 unsigned HOST_WIDE_INT offset;
2229 int base_regno;
2231 switch (GET_CODE (src))
2233 case PLUS:
2234 if (REG_P (XEXP (src, 0)))
2236 base_reg = XEXP (src, 0);
2238 if (CONST_INT_P (XEXP (src, 1)))
2239 offset = UINTVAL (XEXP (src, 1));
2240 else if (REG_P (XEXP (src, 1))
2241 && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode))
2243 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0
2244 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX)
2245 offset = reg_offset[REGNO (XEXP (src, 1))];
2246 /* Maybe the first register is known to be a
2247 constant. */
2248 else if (move2add_valid_value_p (REGNO (base_reg), mode)
2249 && reg_base_reg[REGNO (base_reg)] < 0
2250 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX)
2252 offset = reg_offset[REGNO (base_reg)];
2253 base_reg = XEXP (src, 1);
2255 else
2256 goto invalidate;
2258 else
2259 goto invalidate;
2261 break;
2264 goto invalidate;
2266 case REG:
2267 base_reg = src;
2268 offset = 0;
2269 break;
2271 case CONST_INT:
2272 /* Start tracking the register as a constant. */
2273 reg_base_reg[regno] = -1;
2274 reg_symbol_ref[regno] = NULL_RTX;
2275 reg_offset[regno] = INTVAL (SET_SRC (set));
2276 /* We assign the same luid to all registers set to constants. */
2277 reg_set_luid[regno] = move2add_last_label_luid + 1;
2278 move2add_record_mode (dst);
2279 return;
2281 default:
2282 goto invalidate;
2285 base_regno = REGNO (base_reg);
2286 /* If information about the base register is not valid, set it
2287 up as a new base register, pretending its value is known
2288 starting from the current insn. */
2289 if (!move2add_valid_value_p (base_regno, mode))
2291 reg_base_reg[base_regno] = base_regno;
2292 reg_symbol_ref[base_regno] = NULL_RTX;
2293 reg_offset[base_regno] = 0;
2294 reg_set_luid[base_regno] = move2add_luid;
2295 gcc_assert (GET_MODE (base_reg) == mode);
2296 move2add_record_mode (base_reg);
2299 /* Copy base information from our base register. */
2300 reg_set_luid[regno] = reg_set_luid[base_regno];
2301 reg_base_reg[regno] = reg_base_reg[base_regno];
2302 reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
2304 /* Compute the sum of the offsets or constants. */
2305 reg_offset[regno]
2306 = trunc_int_for_mode (offset + reg_offset[base_regno], mode);
2308 move2add_record_mode (dst);
2310 else
2312 invalidate:
2313 /* Invalidate the contents of the register. */
2314 move2add_record_mode (dst);
2315 reg_mode[regno] = VOIDmode;
2319 namespace {
2321 const pass_data pass_data_postreload_cse =
2323 RTL_PASS, /* type */
2324 "postreload", /* name */
2325 OPTGROUP_NONE, /* optinfo_flags */
2326 TV_RELOAD_CSE_REGS, /* tv_id */
2327 0, /* properties_required */
2328 0, /* properties_provided */
2329 0, /* properties_destroyed */
2330 0, /* todo_flags_start */
2331 TODO_df_finish, /* todo_flags_finish */
2334 class pass_postreload_cse : public rtl_opt_pass
2336 public:
2337 pass_postreload_cse (gcc::context *ctxt)
2338 : rtl_opt_pass (pass_data_postreload_cse, ctxt)
2341 /* opt_pass methods: */
2342 virtual bool gate (function *) { return (optimize > 0 && reload_completed); }
2344 virtual unsigned int execute (function *);
2346 }; // class pass_postreload_cse
2348 unsigned int
2349 pass_postreload_cse::execute (function *fun)
2351 if (!dbg_cnt (postreload_cse))
2352 return 0;
2354 /* Do a very simple CSE pass over just the hard registers. */
2355 reload_cse_regs (get_insns ());
2356 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2357 Remove any EH edges associated with them. */
2358 if (fun->can_throw_non_call_exceptions
2359 && purge_all_dead_edges ())
2360 cleanup_cfg (0);
2362 return 0;
2365 } // anon namespace
2367 rtl_opt_pass *
2368 make_pass_postreload_cse (gcc::context *ctxt)
2370 return new pass_postreload_cse (ctxt);