1 ;; Predicate definitions for S/390 and zSeries.
2 ;; Copyright (C) 2005-2024 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; OP is the current operation.
23 ;; MODE is the current operation mode.
25 ;; operands --------------------------------------------------------------
27 ;; Return true if OP a const 0 operand (int/float/vector).
28 (define_predicate "const0_operand"
29 (and (match_code "const_int,const_wide_int,const_double,const_vector")
30 (match_test "op == CONST0_RTX (mode)")))
32 ;; Return true if OP an all ones operand (int/vector).
33 (define_predicate "all_ones_operand"
34 (and (match_code "const_int, const_wide_int, const_vector")
35 (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
36 (match_test "op == CONSTM1_RTX (mode)")))
38 ;; Return true if OP is a 4 bit mask operand
39 (define_predicate "const_mask_operand"
40 (and (match_code "const_int")
41 (match_test "UINTVAL (op) < 16")))
43 ;; Return true if OP is constant.
45 (define_special_predicate "consttable_operand"
46 (and (match_code "symbol_ref, label_ref, const, const_int, const_wide_int, const_double, const_vector")
47 (match_test "CONSTANT_P (op)")))
49 ; An operand used as vector permutation pattern
51 ; This in particular accepts constants which would otherwise be
52 ; rejected. These constants require special post reload handling
54 (define_special_predicate "permute_pattern_operand"
55 (and (match_code "const_vector,mem,reg,subreg")
56 (match_test "GET_MODE (op) == V16QImode")
57 (match_test "!MEM_P (op) || s390_mem_constraint (\"R\", op)")))
59 ;; Return true if OP is a valid S-type operand.
61 (define_predicate "s_operand"
62 (and (match_code "subreg, mem")
63 (match_operand 0 "general_operand"))
65 /* Just like memory_operand, allow (subreg (mem ...))
68 && GET_CODE (op) == SUBREG
69 && GET_CODE (SUBREG_REG (op)) == MEM)
72 if (GET_CODE (op) != MEM)
74 if (!s390_legitimate_address_without_index_p (op))
80 ;; Return true of the address of the mem operand plus 16 is still a
81 ;; valid Q constraint address.
83 (define_predicate "plus16_Q_operand"
84 (and (match_code "mem")
85 (match_operand 0 "general_operand"))
87 rtx addr = XEXP (op, 0);
91 if (GET_CODE (addr) != PLUS
92 || !REG_P (XEXP (addr, 0))
93 || !CONST_INT_P (XEXP (addr, 1)))
96 return SHORT_DISP_IN_RANGE (INTVAL (XEXP (addr, 1)) + 16);
99 ;; Return true if OP is a valid operand for the BRAS instruction.
100 ;; Allow SYMBOL_REFs and @PLT stubs.
102 (define_special_predicate "bras_sym_operand"
103 (ior (and (match_code "symbol_ref")
104 (ior (match_test "!flag_pic")
105 (match_test "SYMBOL_REF_LOCAL_P (op)")
106 (and (match_test "TARGET_64BIT")
107 (match_test "SYMBOL_REF_FUNCTION_P (op)"))))
108 (and (match_code "const")
109 (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
110 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT31")))))
112 ;; Return true if OP is a PLUS that is not a legitimate
113 ;; operand for the LA instruction.
115 (define_predicate "s390_plus_operand"
116 (and (match_code "plus")
117 (and (match_test "mode == Pmode")
118 (match_test "!legitimate_la_operand_p (op)"))))
120 ;; Return true if OP is a valid operand as scalar shift count or setmem.
122 (define_predicate "setmem_operand"
123 (match_code "reg, subreg, plus, const_int")
125 HOST_WIDE_INT offset;
128 if (GET_MODE (op) != VOIDmode
129 && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
132 /* Extract base register and offset. */
133 if (!s390_decompose_addrstyle_without_index (op, &base, &offset))
136 /* Don't allow any non-base hard registers. Doing so without
137 confusing reload and/or regrename would be tricky, and doesn't
138 buy us much anyway. */
139 if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
142 /* Unfortunately we have to reject constants that are invalid
143 for an address, or else reload will get confused. */
144 if (!DISP_IN_RANGE (offset))
150 ; An integer operand with the lowest order 6 bits all ones.
151 (define_predicate "const_int_6bitset_operand"
152 (and (match_code "const_int")
153 (match_test "(INTVAL (op) & 63) == 63")))
154 (define_predicate "nonzero_shift_count_operand"
155 (and (match_code "const_int")
156 (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
158 ;; Return true if OP a valid operand for the LARL instruction.
160 (define_predicate "larl_operand"
161 (match_code "label_ref, symbol_ref, const")
163 /* Allow labels and local symbols. */
164 if (GET_CODE (op) == LABEL_REF)
166 if (SYMBOL_REF_P (op))
167 return (!SYMBOL_FLAG_NOTALIGN2_P (op)
168 && SYMBOL_REF_TLS_MODEL (op) == 0
169 && s390_rel_address_ok_p (op));
171 /* Everything else must have a CONST, so strip it. */
172 if (GET_CODE (op) != CONST)
176 /* Allow adding *even* in-range constants. */
177 if (GET_CODE (op) == PLUS)
179 if (GET_CODE (XEXP (op, 1)) != CONST_INT
180 || (INTVAL (XEXP (op, 1)) & 1) != 0)
182 if (INTVAL (XEXP (op, 1)) >= HOST_WIDE_INT_1 << 31
183 || INTVAL (XEXP (op, 1)) < -(HOST_WIDE_INT_1 << 31))
188 /* Labels and local symbols allowed here as well. */
189 if (GET_CODE (op) == LABEL_REF)
191 if (SYMBOL_REF_P (op))
192 return (!SYMBOL_FLAG_NOTALIGN2_P (op)
193 && SYMBOL_REF_TLS_MODEL (op) == 0
194 && s390_rel_address_ok_p (op));
197 /* Now we must have a @GOTENT offset or @PLT stub
198 or an @INDNTPOFF TLS offset. */
199 if (GET_CODE (op) == UNSPEC
200 && XINT (op, 1) == UNSPEC_GOTENT)
202 if (GET_CODE (op) == UNSPEC
203 && XINT (op, 1) == UNSPEC_PLT31)
205 if (GET_CODE (op) == UNSPEC
206 && XINT (op, 1) == UNSPEC_INDNTPOFF)
212 ; Predicate that always allows wraparound of the one-bit range.
213 (define_predicate "contiguous_bitmask_operand"
214 (match_code "const_int")
216 return s390_contiguous_bitmask_p (INTVAL (op), true,
217 GET_MODE_BITSIZE (mode), NULL, NULL);
220 ; Same without wraparound.
221 (define_predicate "contiguous_bitmask_nowrap_operand"
222 (match_code "const_int")
224 return s390_contiguous_bitmask_p
225 (INTVAL (op), false, GET_MODE_BITSIZE (mode), NULL, NULL);
228 ;; Return true if OP is legitimate for any LOC instruction.
230 (define_predicate "loc_operand"
231 (ior (match_operand 0 "nonimmediate_operand")
232 (and (match_code "const_int")
233 (match_test "INTVAL (op) <= 32767 && INTVAL (op) >= -32768"))))
235 (define_predicate "reload_const_wide_int_operand"
236 (and (match_code "const_wide_int")
237 (match_test "legitimate_reload_constant_p (op)")))
240 ;; operators --------------------------------------------------------------
242 ;; Return nonzero if OP is a valid comparison operator
243 ;; for a branch condition.
245 (define_predicate "s390_comparison"
246 (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
247 uneq, unlt, ungt, unle, unge, ltgt,
250 if (GET_CODE (XEXP (op, 0)) != REG
251 || REGNO (XEXP (op, 0)) != CC_REGNUM
252 || (XEXP (op, 1) != const0_rtx
253 && !(CONST_INT_P (XEXP (op, 1))
254 && GET_MODE (XEXP (op, 0)) == CCRAWmode
255 && INTVAL (XEXP (op, 1)) >= 0
256 && INTVAL (XEXP (op, 1)) <= 15)))
259 return (s390_branch_condition_mask (op) >= 0);
262 ;; Return true if op is the cc register.
263 (define_predicate "cc_reg_operand"
264 (and (match_code "reg")
265 (match_test "REGNO (op) == CC_REGNUM")))
267 (define_predicate "s390_signed_integer_comparison"
268 (match_code "eq, ne, lt, gt, le, ge")
270 return (s390_compare_and_branch_condition_mask (op) >= 0);
273 (define_predicate "s390_unsigned_integer_comparison"
274 (match_code "eq, ne, ltu, gtu, leu, geu")
276 return (s390_compare_and_branch_condition_mask (op) >= 0);
279 ;; Return nonzero if OP is a valid comparison operator for the
280 ;; cstore expanders -- respectively cstorecc4 and integer cstore.
281 (define_predicate "s390_eqne_operator"
282 (match_code "eq, ne"))
284 (define_predicate "s390_scond_operator"
285 (match_code "ltu, gtu, leu, geu"))
287 (define_predicate "s390_brx_operator"
288 (match_code "le, gt"))
290 ;; Return nonzero if OP is a valid comparison operator
291 ;; for an ALC condition.
293 (define_predicate "s390_alc_comparison"
294 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
296 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
299 if (!COMPARISON_P (op))
302 if (GET_CODE (XEXP (op, 0)) != REG
303 || REGNO (XEXP (op, 0)) != CC_REGNUM
304 || (XEXP (op, 1) != const0_rtx
305 && !(CONST_INT_P (XEXP (op, 1))
306 && GET_MODE (XEXP (op, 0)) == CCRAWmode
307 && INTVAL (XEXP (op, 1)) >= 0
308 && INTVAL (XEXP (op, 1)) <= 15)))
311 switch (GET_MODE (XEXP (op, 0)))
314 return GET_CODE (op) == LTU;
317 return GET_CODE (op) == LEU;
320 return GET_CODE (op) == GEU;
323 return GET_CODE (op) == GTU;
326 return GET_CODE (op) == LTU;
329 return GET_CODE (op) == UNGT;
332 return GET_CODE (op) == UNLT;
339 ;; Return nonzero if OP is a valid comparison operator
340 ;; for an SLB condition.
342 (define_predicate "s390_slb_comparison"
343 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
345 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
348 if (!COMPARISON_P (op))
351 if (GET_CODE (XEXP (op, 0)) != REG
352 || REGNO (XEXP (op, 0)) != CC_REGNUM
353 || XEXP (op, 1) != const0_rtx)
356 switch (GET_MODE (XEXP (op, 0)))
359 return GET_CODE (op) == GEU;
362 return GET_CODE (op) == GTU;
365 return GET_CODE (op) == LTU;
368 return GET_CODE (op) == LEU;
371 return GET_CODE (op) == GEU;
374 return GET_CODE (op) == LE;
377 return GET_CODE (op) == GE;
384 ;; Return true if OP is a load multiple operation. It is known to be a
385 ;; PARALLEL and the first section will be tested.
387 (define_special_predicate "load_multiple_operation"
388 (match_code "parallel")
390 machine_mode elt_mode;
391 int count = XVECLEN (op, 0);
392 unsigned int dest_regno;
396 /* Perform a quick check so we don't blow up below. */
398 || GET_CODE (XVECEXP (op, 0, 0)) != SET
399 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
400 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
403 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
404 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
405 elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
407 /* Check, is base, or base + displacement. */
409 if (GET_CODE (src_addr) == REG)
411 else if (GET_CODE (src_addr) == PLUS
412 && GET_CODE (XEXP (src_addr, 0)) == REG
413 && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
415 off = INTVAL (XEXP (src_addr, 1));
416 src_addr = XEXP (src_addr, 0);
421 for (i = 1; i < count; i++)
423 rtx elt = XVECEXP (op, 0, i);
425 if (GET_CODE (elt) != SET
426 || GET_CODE (SET_DEST (elt)) != REG
427 || GET_MODE (SET_DEST (elt)) != elt_mode
428 || REGNO (SET_DEST (elt)) != dest_regno + i
429 || GET_CODE (SET_SRC (elt)) != MEM
430 || GET_MODE (SET_SRC (elt)) != elt_mode
431 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
432 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
433 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
434 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
435 != off + i * GET_MODE_SIZE (elt_mode))
442 ;; For an execute pattern the target instruction is embedded into the
443 ;; RTX but will not get checked for validity by recog automatically.
444 ;; The execute_operation predicate extracts the target RTX and invokes
446 (define_special_predicate "execute_operation"
447 (match_code "parallel")
453 /* This is redundant but since this predicate is evaluated
454 first when recognizing the insn we can prevent the more
455 expensive code below from being executed for many cases. */
456 if (GET_CODE (XVECEXP (pattern, 0, 0)) != UNSPEC
457 || XINT (XVECEXP (pattern, 0, 0), 1) != UNSPEC_EXECUTE)
460 /* Keep in sync with s390_execute_target. */
461 if (XVECLEN (pattern, 0) == 2)
463 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
467 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
470 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
471 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
473 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
476 /* Since we do not have the wrapping insn here we have to build one. */
477 insn = make_insn_raw (pattern);
478 icode = recog_memoized (insn);
484 return constrain_operands (reload_completed, get_enabled_alternatives (insn)) == 1;
487 ;; Return true if OP is a store multiple operation. It is known to be a
488 ;; PARALLEL and the first section will be tested.
490 (define_special_predicate "store_multiple_operation"
491 (match_code "parallel")
493 machine_mode elt_mode;
494 int count = XVECLEN (op, 0);
495 unsigned int src_regno;
499 /* Perform a quick check so we don't blow up below. */
501 || GET_CODE (XVECEXP (op, 0, 0)) != SET
502 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
503 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
506 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
507 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
508 elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
510 /* Check, is base, or base + displacement. */
512 if (GET_CODE (dest_addr) == REG)
514 else if (GET_CODE (dest_addr) == PLUS
515 && GET_CODE (XEXP (dest_addr, 0)) == REG
516 && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
518 off = INTVAL (XEXP (dest_addr, 1));
519 dest_addr = XEXP (dest_addr, 0);
524 for (i = 1; i < count; i++)
526 rtx elt = XVECEXP (op, 0, i);
528 if (GET_CODE (elt) != SET
529 || GET_CODE (SET_SRC (elt)) != REG
530 || GET_MODE (SET_SRC (elt)) != elt_mode
531 || REGNO (SET_SRC (elt)) != src_regno + i
532 || GET_CODE (SET_DEST (elt)) != MEM
533 || GET_MODE (SET_DEST (elt)) != elt_mode
534 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
535 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
536 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
537 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
538 != off + i * GET_MODE_SIZE (elt_mode))
544 (define_predicate "const_shift_by_byte_operand"
545 (match_code "const_int")
547 unsigned HOST_WIDE_INT val = INTVAL (op);
548 return val <= 128 && val % 8 == 0;
551 ;; Certain operations (e.g. CS) cannot access SYMBOL_REF directly, it needs to
552 ;; be loaded into some register first. In theory, if we put a SYMBOL_REF into
553 ;; a corresponding insn anyway, reload will generate a load for it, but, when
554 ;; coupled with constant propagation, this will lead to an inefficient code
557 (define_predicate "nonsym_memory_operand"
560 return memory_operand (op, mode) && !contains_symbol_ref_p (op);
563 ;; Check for a valid shift count operand with an implicit
564 ;; shift truncation mask of 63.
566 (define_predicate "shift_count_operand"
567 (and (match_code "reg, subreg, and, plus, const_int")
568 (match_test "CONST_INT_P (op) || GET_MODE (op) == E_QImode"))
570 return s390_valid_shift_count (op, 63);
574 ;; This is used as operand predicate. As we do not know
575 ;; the mode of the first operand here and the shift truncation
576 ;; mask depends on the mode, we cannot check the mask.
577 ;; This is supposed to happen in the insn condition which
578 ;; calls s390_valid_shift_count with the proper mode size.
579 ;; We need two separate predicates for non-vector and vector
580 ;; shifts since the (less restrictive) insn condition is checked
581 ;; after the more restrictive operand predicate which will
582 ;; disallow the operand before we can check the condition.
584 (define_predicate "shift_count_operand_vec"
585 (and (match_code "reg, subreg, and, plus, const_int")
586 (match_test "CONST_INT_P (op) || GET_MODE (op) == E_QImode"))
588 return s390_valid_shift_count (op, 0);
592 ; An integer constant which can be used in a signed add with overflow
593 ; pattern without being reloaded.
594 (define_predicate "addv_const_operand"
595 (and (match_code "const_int")
596 (match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767")))
598 ; Match (subreg (reg ...)) operands.
599 ; Used for movstrict destination operands
600 ; When replacing pseudos with hard regs reload strips away the
601 ; subregs. Accept also plain registers then to prevent the insn from
602 ; becoming unrecognizable.
603 (define_predicate "subreg_register_operand"
604 (ior (and (match_code "subreg")
605 (match_test "register_operand (SUBREG_REG (op), GET_MODE (SUBREG_REG (op)))"))
606 (and (match_code "reg")
607 (match_test "reload_completed || reload_in_progress")
608 (match_test "register_operand (op, GET_MODE (op))"))))
610 ; Bias value for LEN_LOAD and LEN_STORE. The bias will be added to the
611 ; length (in bytes for s390) to be loaded. vll/vstl expect the lowest byte
612 ; to load while LEN_LOAD/LEN_STORE use the actual length in bytes. This implies
613 ; that we cannot load a length of 0.
614 (define_predicate "vll_bias_operand"
615 (and (match_code "const_int")
616 (match_test "op == CONSTM1_RTX (QImode)")))