1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2024 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
30 #include "stringpool.h"
41 #include "diagnostic-core.h"
42 #include "conditions.h"
43 #include "insn-attr.h"
46 #include "stor-layout.h"
52 #include "tm-constrs.h"
55 #include "tree-pass.h"
57 /* This file should be included last. */
58 #include "target-def.h"
60 /* Usable when we have an amount to add or subtract, and want the
61 optimal size of the insn. */
62 #define ADDITIVE_SIZE_MODIFIER(size) \
63 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
65 #define LOSE_AND_RETURN(msgid, x) \
68 cris_operand_lossage (msgid, x); \
72 enum cris_retinsn_type
73 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
75 /* Per-function machine data. */
76 struct GTY(()) machine_function
78 int needs_return_address_on_stack
;
80 /* This is the number of registers we save in the prologue due to
84 enum cris_retinsn_type return_type
;
87 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
89 static char cris_output_insn_is_bound
= 0;
91 /* In code for output macros, this is how we know whether e.g. constant
92 goes in code or in a static initializer. */
93 static int in_code
= 0;
95 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
96 int *, const_tree
, int);
98 static unsigned int cris_atomic_align_for_mode (machine_mode
);
100 static void cris_print_base (rtx
, FILE *);
102 static void cris_print_index (rtx
, FILE *);
104 static void cris_output_addr_const (FILE *, rtx
);
106 static struct machine_function
* cris_init_machine_status (void);
108 static rtx
cris_struct_value_rtx (tree
, int);
110 static void cris_setup_incoming_varargs (cumulative_args_t
,
111 const function_arg_info
&,
114 static int cris_initial_frame_pointer_offset (void);
116 static void cris_operand_lossage (const char *, rtx
);
118 static int cris_reg_saved_in_regsave_area (unsigned int);
120 static void cris_print_operand (FILE *, rtx
, int);
122 static void cris_print_operand_address (FILE *, machine_mode
, rtx
);
124 static bool cris_print_operand_punct_valid_p (unsigned char code
);
126 static void cris_conditional_register_usage (void);
128 static void cris_asm_output_mi_thunk
129 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
131 static void cris_file_start (void);
132 static void cris_init_libfuncs (void);
134 static unsigned int cris_postdbr_cmpelim (void);
136 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
137 static reg_class_t
cris_spill_class (reg_class_t
, machine_mode
);
139 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
140 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
141 static machine_mode
cris_cc_modes_compatible (machine_mode
, machine_mode
);
142 static bool cris_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
143 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
144 static bool cris_pass_by_reference (cumulative_args_t
,
145 const function_arg_info
&);
146 static int cris_arg_partial_bytes (cumulative_args_t
,
147 const function_arg_info
&);
148 static rtx
cris_function_arg (cumulative_args_t
, const function_arg_info
&);
149 static rtx
cris_function_incoming_arg (cumulative_args_t
,
150 const function_arg_info
&);
151 static void cris_function_arg_advance (cumulative_args_t
,
152 const function_arg_info
&);
153 static rtx_insn
*cris_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
154 vec
<machine_mode
> &, vec
<const char *> &,
155 vec
<rtx
> &, vec
<rtx
> &,
156 HARD_REG_SET
&, location_t
);
158 static void cris_option_override (void);
160 static bool cris_frame_pointer_required (void);
162 static void cris_asm_trampoline_template (FILE *);
163 static void cris_trampoline_init (rtx
, tree
, rtx
);
165 static rtx
cris_function_value(const_tree
, const_tree
, bool);
166 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
167 static bool cris_function_value_regno_p (const unsigned int);
168 static unsigned int cris_hard_regno_nregs (unsigned int, machine_mode
);
169 static bool cris_hard_regno_mode_ok (unsigned int, machine_mode
);
170 static HOST_WIDE_INT
cris_static_rtx_alignment (machine_mode
);
171 static HOST_WIDE_INT
cris_constant_alignment (const_tree
, HOST_WIDE_INT
);
172 static bool cris_legitimate_address_p_hook (machine_mode
, rtx
, bool,
175 /* This is the parsed result of the "-max-stack-stackframe=" option. If
176 it (still) is zero, then there was no such option given. */
177 int cris_max_stackframe
= 0;
179 /* This is the parsed result of the "-march=" option, if given. */
180 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
182 #undef TARGET_ASM_ALIGNED_HI_OP
183 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
184 #undef TARGET_ASM_ALIGNED_SI_OP
185 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
186 #undef TARGET_ASM_ALIGNED_DI_OP
187 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
189 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
190 available in ELF. These "normal" pseudos do not have any alignment
191 constraints or side-effects. */
192 #undef TARGET_ASM_UNALIGNED_HI_OP
193 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
195 #undef TARGET_ASM_UNALIGNED_SI_OP
196 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
198 #undef TARGET_ASM_UNALIGNED_DI_OP
199 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
201 #undef TARGET_PRINT_OPERAND
202 #define TARGET_PRINT_OPERAND cris_print_operand
203 #undef TARGET_PRINT_OPERAND_ADDRESS
204 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
205 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
206 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
208 #undef TARGET_CONDITIONAL_REGISTER_USAGE
209 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
211 #undef TARGET_ASM_OUTPUT_MI_THUNK
212 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
213 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
214 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
216 #undef TARGET_ASM_FILE_START
217 #define TARGET_ASM_FILE_START cris_file_start
219 #undef TARGET_INIT_LIBFUNCS
220 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
222 #undef TARGET_LEGITIMATE_ADDRESS_P
223 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p_hook
225 #undef TARGET_PREFERRED_RELOAD_CLASS
226 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
228 #undef TARGET_SPILL_CLASS
229 #define TARGET_SPILL_CLASS cris_spill_class
231 /* We don't define TARGET_FIXED_CONDITION_CODE_REGS, as at the time of
232 this writing, it has an effect only on pre-reload CSE and when
233 scheduling (and for "macro fusion" at that). Neither applies for
234 CRIS so don't waste compilation cycles on enabling a pass that does
235 nothing. Beware of changes to its usage; it may make sense to enable
238 #undef TARGET_CC_MODES_COMPATIBLE
239 #define TARGET_CC_MODES_COMPATIBLE cris_cc_modes_compatible
241 #undef TARGET_FLAGS_REGNUM
242 #define TARGET_FLAGS_REGNUM CRIS_CC0_REGNUM
244 #undef TARGET_REGISTER_MOVE_COST
245 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
246 #undef TARGET_MEMORY_MOVE_COST
247 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
248 #undef TARGET_RTX_COSTS
249 #define TARGET_RTX_COSTS cris_rtx_costs
250 #undef TARGET_ADDRESS_COST
251 #define TARGET_ADDRESS_COST cris_address_cost
253 #undef TARGET_PROMOTE_FUNCTION_MODE
254 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
256 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
257 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
259 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
260 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
262 #undef TARGET_STRUCT_VALUE_RTX
263 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
264 #undef TARGET_SETUP_INCOMING_VARARGS
265 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
266 #undef TARGET_PASS_BY_REFERENCE
267 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
268 #undef TARGET_ARG_PARTIAL_BYTES
269 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
270 #undef TARGET_FUNCTION_ARG
271 #define TARGET_FUNCTION_ARG cris_function_arg
272 #undef TARGET_FUNCTION_INCOMING_ARG
273 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
274 #undef TARGET_FUNCTION_ARG_ADVANCE
275 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
276 #undef TARGET_MD_ASM_ADJUST
277 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
279 #undef TARGET_FRAME_POINTER_REQUIRED
280 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
282 #undef TARGET_OPTION_OVERRIDE
283 #define TARGET_OPTION_OVERRIDE cris_option_override
285 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
286 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
287 #undef TARGET_TRAMPOLINE_INIT
288 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
290 #undef TARGET_FUNCTION_VALUE
291 #define TARGET_FUNCTION_VALUE cris_function_value
292 #undef TARGET_LIBCALL_VALUE
293 #define TARGET_LIBCALL_VALUE cris_libcall_value
294 #undef TARGET_FUNCTION_VALUE_REGNO_P
295 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
297 #undef TARGET_HARD_REGNO_NREGS
298 #define TARGET_HARD_REGNO_NREGS cris_hard_regno_nregs
299 #undef TARGET_HARD_REGNO_MODE_OK
300 #define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok
302 #undef TARGET_STATIC_RTX_ALIGNMENT
303 #define TARGET_STATIC_RTX_ALIGNMENT cris_static_rtx_alignment
304 #undef TARGET_CONSTANT_ALIGNMENT
305 #define TARGET_CONSTANT_ALIGNMENT cris_constant_alignment
307 struct gcc_target targetm
= TARGET_INITIALIZER
;
311 const pass_data pass_data_cris_postdbr_cmpelim
=
315 OPTGROUP_NONE
, /* optinfo_flags */
316 TV_MACH_DEP
, /* tv_id */
317 0, /* properties_required */
318 0, /* properties_provided */
319 0, /* properties_destroyed */
320 0, /* todo_flags_start */
321 0, /* todo_flags_finish */
324 class pass_cris_postdbr_cmpelim
: public rtl_opt_pass
327 pass_cris_postdbr_cmpelim (gcc::context
*ctxt
)
328 : rtl_opt_pass (pass_data_cris_postdbr_cmpelim
, ctxt
)
331 /* opt_pass methods: */
332 virtual unsigned int execute (function
*)
334 return cris_postdbr_cmpelim ();
337 /* No use running this if reorg and cmpelim aren't both run. */
338 virtual bool gate (function
*)
342 && flag_delayed_branch
343 && flag_compare_elim_after_reload
;
350 make_pass_cris_postdbr_cmpelim (gcc::context
*ctxt
)
352 return new pass_cris_postdbr_cmpelim (ctxt
);
355 /* "Cheap version" of cmpelim, making use of the opportunities opened up
358 Go through the insns of a function and look at each actual compare
359 insn; considering only those that compare a register to 0. If the
360 previous CC-affecting insn sets the compared register or if a move
361 reads from it, try to change that into a CC-setting move and try to
362 have it recognized. Bail at labels or non-matching insns that
363 clobber the compared register. If successful, delete the compare.
365 Also, reorg isn't up to date regarding data-flow handling, so we
366 can't go beyond classic RTL scanning. */
369 cris_postdbr_cmpelim ()
373 rtx_insn
*prev_cc_setter
= 0;
374 rtx_insn
*prev_cc_outer
= 0;
375 rtx dccr
= gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
);
377 /* Now look for compares in the insn stream. */
378 for (insn
= get_insns (); insn
; insn
= next
)
380 rtx_insn
*outer_insn
= insn
;
382 next
= NEXT_INSN (outer_insn
);
384 /* Forget previous state when we see a label; we can't track or
392 if (!NONDEBUG_INSN_P (insn
))
394 rtx pat
= PATTERN (insn
);
396 /* Consider filled delay slots; there might be a comparison there.
397 It's only the second insn in a sequence that is interesting. */
398 if (GET_CODE (pat
) == SEQUENCE
)
399 insn
= as_a
<rtx_insn
*> (XVECEXP (pat
, 0, 1));
400 /* The "else" eliminates temptations to consider an insn in a
401 delay slot for elimination; it can only be a prev_cc_setter. */
402 else if (prev_cc_setter
!= 0 && GET_CODE (pat
) == SET
)
404 rtx dest
= SET_DEST (pat
);
405 rtx src
= SET_SRC (pat
);
409 && REGNO (dest
) == CRIS_CC0_REGNUM
410 && GET_CODE (src
) == COMPARE
411 && REG_P (XEXP (src
, 0))
412 && XEXP (src
, 1) == const0_rtx
413 && (prev_set
= single_set (prev_cc_setter
)) != 0)
415 /* We have a candidate, and a prev_cc_setter to inspect. */
416 rtx reg
= XEXP (src
, 0);
417 rtx prev_dest
= SET_DEST (prev_set
);
418 rtx prev_src
= SET_SRC (prev_set
);
419 bool src_same
= rtx_equal_p (prev_src
, reg
);
421 /* If the prev_cc_setter isn't a simple SET, or if the
422 compared register is modified in prev_cc_setter without
423 being the destination, or if it's modified between
424 prev_cc_setter (equal to or contained in prev_cc_outer)
425 and this insn, then we can't use the flags result. And
426 of course, the SET_DEST of prev_cc_setter (the main
427 interest, not dccr) has to be the same register and
428 mode we're interested in - or the SET_SRC. We've
429 already checked that the compared register isn't
430 changed in-between. */
431 if (REG_P (prev_dest
)
432 && ! reg_set_p (reg
, prev_src
)
433 && ! reg_set_between_p (reg
, prev_cc_outer
, outer_insn
)
434 && (src_same
|| rtx_equal_p (prev_dest
, reg
)))
436 machine_mode ccmode
= GET_MODE (src
);
437 rtx modeadjusted_dccr
438 = (ccmode
== CCmode
? dccr
439 : gen_rtx_REG (ccmode
, CRIS_CC0_REGNUM
));
441 /* We don't need to copy_rtx pat: we're going to
444 : gen_rtx_SET (modeadjusted_dccr
,
445 gen_rtx_COMPARE (ccmode
,
449 /* Replace tentatively, the prev_set combo that is
450 ((set d s) (clobber dccr)) with
451 ((cmp s 0) (set d s)) where (cmp s 0) is the
452 compare we're looking at, and validate it or fail
453 the whole thing. First replace the ((set d s) ...)
454 with ((cmp s 0) ...)). */
455 validate_change (prev_cc_setter
,
456 &XVECEXP (PATTERN (prev_cc_setter
),
457 0, 0), compare
, true);
459 /* Then the clobber with the (set d s). */
460 validate_change (prev_cc_setter
,
461 &XVECEXP (PATTERN (prev_cc_setter
),
462 0, 1), prev_set
, true);
464 if (apply_change_group ())
468 /* We eliminated the compare. Then we must go to
469 the next insn: we can't consider the eliminated
470 insn for the next prev_cc_setter.
472 FIXME: if later insns still match, we could do
473 the delete_insn part only, for them. But, it
474 seems rare that reorg would manage to move a
475 second CC-clobber to another delay-slot,
476 leaving two identical compares (and presumably
485 if (reg_set_p (dccr
, insn
))
487 rtx pat
= PATTERN (insn
);
491 /* Make sure we can use it later on, otherwise forget it.
492 Don't look too close, we're going to pass a lot of these.
493 Just make sure the structure is that we can work with. */
494 if (GET_CODE (pat
) == PARALLEL
495 && XVECLEN (pat
, 0) == 2
496 && GET_CODE (XVECEXP (pat
, 0, 1)) == CLOBBER
)
498 prev_cc_setter
= insn
;
499 prev_cc_outer
= outer_insn
;
507 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
510 cris_movem_load_rest_p (rtx op
)
512 unsigned int reg_count
= XVECLEN (op
, 0);
518 unsigned int regno
= 0;
520 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
521 other than (MEM reg). */
523 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
524 || !REG_P (SET_DEST (XVECEXP (op
, 0, 0)))
525 || !MEM_P (SET_SRC (XVECEXP (op
, 0, 0))))
528 /* Check a possible post-inc indicator. */
529 if (GET_CODE (XVECEXP (op
, 0, 1)) == SET
530 && GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
532 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
533 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
539 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
540 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
541 || !CONST_INT_P (inc
)
542 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
550 regno
= reg_count
- 1;
552 elt
= XVECEXP (op
, 0, 0);
553 src_addr
= XEXP (SET_SRC (elt
), 0);
555 if (GET_CODE (elt
) != SET
556 || !REG_P (SET_DEST (elt
))
557 || GET_MODE (SET_DEST (elt
)) != SImode
558 || REGNO (SET_DEST (elt
)) != regno
559 || !MEM_P (SET_SRC (elt
))
560 || GET_MODE (SET_SRC (elt
)) != SImode
561 || !memory_address_p (SImode
, src_addr
))
564 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
566 rtx elt
= XVECEXP (op
, 0, i
);
569 if (GET_CODE (elt
) != SET
570 || !REG_P (SET_DEST (elt
))
571 || GET_MODE (SET_DEST (elt
)) != SImode
572 || REGNO (SET_DEST (elt
)) != regno
573 || !MEM_P (SET_SRC (elt
))
574 || GET_MODE (SET_SRC (elt
)) != SImode
575 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
576 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
577 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
578 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
585 /* Worker function for predicate for the parallel contents in a movem
589 cris_store_multiple_op_p (rtx op
)
591 int reg_count
= XVECLEN (op
, 0);
602 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
603 other than (MEM reg) and (MEM (PLUS reg const)). */
607 elt
= XVECEXP (op
, 0, 0);
609 if (GET_CODE (elt
) != SET
)
612 dest
= SET_DEST (elt
);
614 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
617 dest_addr
= XEXP (dest
, 0);
619 /* Check a possible post-inc indicator. */
620 if (GET_CODE (XVECEXP (op
, 0, 1)) == SET
621 && GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
623 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
624 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
629 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
630 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
631 || !CONST_INT_P (inc
)
632 /* Support increment by number of registers, and by the offset
633 of the destination, if it has the form (MEM (PLUS reg
635 || !((REG_P (dest_addr
)
636 && REGNO (dest_addr
) == REGNO (reg
)
637 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
638 || (GET_CODE (dest_addr
) == PLUS
639 && REG_P (XEXP (dest_addr
, 0))
640 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
641 && CONST_INT_P (XEXP (dest_addr
, 1))
642 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
651 regno
= reg_count
- 1;
653 if (GET_CODE (elt
) != SET
654 || !REG_P (SET_SRC (elt
))
655 || GET_MODE (SET_SRC (elt
)) != SImode
656 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
657 || !MEM_P (SET_DEST (elt
))
658 || GET_MODE (SET_DEST (elt
)) != SImode
)
661 if (REG_P (dest_addr
))
663 dest_base
= dest_addr
;
666 else if (GET_CODE (dest_addr
) == PLUS
667 && REG_P (XEXP (dest_addr
, 0))
668 && CONST_INT_P (XEXP (dest_addr
, 1)))
670 dest_base
= XEXP (dest_addr
, 0);
671 offset
= INTVAL (XEXP (dest_addr
, 1));
676 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
678 rtx elt
= XVECEXP (op
, 0, i
);
681 if (GET_CODE (elt
) != SET
682 || !REG_P (SET_SRC (elt
))
683 || GET_MODE (SET_SRC (elt
)) != SImode
684 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
685 || !MEM_P (SET_DEST (elt
))
686 || GET_MODE (SET_DEST (elt
)) != SImode
687 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
688 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
689 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
690 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
697 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
700 cris_conditional_register_usage (void)
702 if (TARGET_HAS_MUL_INSNS
)
703 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
705 /* On early versions, we must use the 16-bit condition-code register,
706 which has another name. */
707 if (cris_cpu_version
< 8)
708 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
711 /* Given an rtx, return the text string corresponding to the CODE of X.
712 Intended for use in the assembly language output section of a
718 cris_output_insn_is_bound
= 0;
719 switch (GET_CODE (x
))
728 /* This function is for retrieving a part of an instruction name for
729 an operator, for immediate output. If that ever happens for
730 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
732 internal_error ("MULT case in %<cris_op_str%>");
760 /* Used to control the sign/zero-extend character for the 'E' modifier.
762 cris_output_insn_is_bound
= 1;
766 return "Unknown operator";
770 /* Emit an error message when we're in an asm, and a fatal error for
771 "normal" insns. Formatted output isn't easily implemented, since we
772 use output_operand_lossage to output the actual message and handle the
773 categorization of the error. */
776 cris_operand_lossage (const char *msgid
, rtx op
)
779 output_operand_lossage ("%s", msgid
);
782 /* Print an index part of an address to file. */
785 cris_print_index (rtx index
, FILE *file
)
787 /* Make the index "additive" unless we'll output a negative number, in
788 which case the sign character is free (as in free beer). */
789 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
793 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
794 else if (CONSTANT_P (index
))
795 cris_output_addr_const (file
, index
);
796 else if (GET_CODE (index
) == MULT
)
798 fprintf (file
, "$%s.",
799 reg_names
[REGNO (XEXP (index
, 0))]);
801 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
803 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
805 rtx inner
= XEXP (index
, 0);
806 rtx inner_inner
= XEXP (inner
, 0);
808 if (GET_CODE (inner_inner
) == POST_INC
)
810 fprintf (file
, "[$%s+].",
811 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
812 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
816 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
818 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
821 else if (MEM_P (index
))
823 rtx inner
= XEXP (index
, 0);
824 if (GET_CODE (inner
) == POST_INC
)
825 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
827 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
830 cris_operand_lossage ("unexpected index-type in cris_print_index",
834 /* Print a base rtx of an address to file. */
837 cris_print_base (rtx base
, FILE *file
)
840 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
841 else if (GET_CODE (base
) == POST_INC
)
842 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
844 cris_operand_lossage ("unexpected base-type in cris_print_base",
848 /* Usable as a guard in expressions. */
851 cris_fatal (char *arg
)
853 internal_error (arg
);
855 /* We'll never get here; this is just to appease compilers. */
859 /* Return nonzero if REGNO is an ordinary register that *needs* to be
860 saved together with other registers, possibly by a MOVEM instruction,
861 or is saved for target-independent reasons. There may be
862 target-dependent reasons to save the register anyway; this is just a
863 wrapper for a complicated conditional. */
866 cris_reg_saved_in_regsave_area (unsigned int regno
)
869 (((df_regs_ever_live_p (regno
)
870 && !call_used_or_fixed_reg_p (regno
)))
871 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
872 && regno
!= CRIS_SRP_REGNUM
)
873 || (crtl
->calls_eh_return
874 && (regno
== EH_RETURN_DATA_REGNO (0)
875 || regno
== EH_RETURN_DATA_REGNO (1)
876 || regno
== EH_RETURN_DATA_REGNO (2)
877 || regno
== EH_RETURN_DATA_REGNO (3)));
880 /* The PRINT_OPERAND worker. */
883 cris_print_operand (FILE *file
, rtx x
, int code
)
887 /* New code entries should just be added to the switch below. If
888 handling is finished, just return. If handling was just a
889 modification of the operand, the modified operand should be put in
890 "operand", and then do a break to let default handling
891 (zero-modifier) output the operand. */
896 /* Print the unsigned supplied integer as if it were signed
897 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
898 if (!satisfies_constraint_O (x
))
899 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
900 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
901 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
905 /* Print assembler code for operator. */
906 fprintf (file
, "%s", cris_op_str (operand
));
911 /* A movem modifier working on a parallel; output the register
915 if (GET_CODE (x
) != PARALLEL
)
916 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
918 /* The second item can be (set reg (plus reg const)) to denote a
921 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
923 : XVECLEN (x
, 0) - 1);
925 fprintf (file
, "$%s", reg_names
[regno
]);
931 /* A similar movem modifier; output the memory operand. */
934 if (GET_CODE (x
) != PARALLEL
)
935 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
937 /* The lowest mem operand is in the first item, but perhaps it
938 needs to be output as postincremented. */
939 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
940 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
941 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
943 /* The second item can be a (set reg (plus reg const)) to denote
945 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
947 /* It's a post-increment, if the address is a naked (reg). */
949 addr
= gen_rtx_POST_INC (SImode
, addr
);
952 /* Otherwise, it's a side-effect; RN=RN+M. */
953 fprintf (file
, "[$%s=$%s%s%d]",
954 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
955 reg_names
[REGNO (XEXP (addr
, 0))],
956 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
957 (int) INTVAL (XEXP (addr
, 1)));
961 output_address (VOIDmode
, addr
);
966 /* Adjust a power of two to its log2. */
967 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
968 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
969 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
973 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
974 respectively. This modifier also terminates the inhibiting
975 effects of the 'x' modifier. */
976 cris_output_insn_is_bound
= 0;
977 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
981 if (INTVAL (x
) <= 255)
983 else if (INTVAL (x
) <= 65535)
993 /* For a non-integer, print the size of the operand. */
994 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
995 ? 'd' : GET_MODE (x
) == HImode
? 'w'
996 : GET_MODE (x
) == QImode
? 'b'
997 /* If none of the above, emit an erroneous size letter. */
1003 /* Const_int: print b for -127 <= x <= 255,
1004 w for -32768 <= x <= 65535, else die. */
1005 if (!CONST_INT_P (x
)
1006 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
1007 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
1008 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
1012 /* Output a 'nop' if there's nothing for the delay slot.
1013 This method stolen from the sparc files. */
1014 if (dbr_sequence_length () == 0)
1015 fputs ("\n\tnop", file
);
1019 /* Output directive for alignment padded with "nop" insns.
1020 Optimizing for size, it's plain 4-byte alignment, otherwise we
1021 align the section to a cache-line (32 bytes) and skip at max 2
1022 bytes, i.e. we skip if it's the last insn on a cache-line. The
1023 latter is faster by a small amount (for two test-programs 99.6%
1024 and 99.9%) and larger by a small amount (ditto 100.1% and
1025 100.2%). This is supposed to be the simplest yet performance-
1026 wise least intrusive way to make sure the immediately following
1027 (supposed) muls/mulu insn isn't located at the end of a
1030 fputs (optimize_size
1031 ? ".p2alignw 2,0x050f\n\t"
1032 : ".p2alignw 5,0x050f,2\n\t", file
);
1036 /* Print high (most significant) part of something. */
1037 switch (GET_CODE (operand
))
1040 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
1041 value is kept here, and so may be other than 0 or -1. */
1042 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
1043 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
1047 /* High part of a long long constant. */
1048 if (GET_MODE (operand
) == VOIDmode
)
1050 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
1054 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
1057 /* Print reg + 1. Check that there's not an attempt to print
1058 high-parts of registers like stack-pointer or higher, except
1059 for SRP (where the "high part" is MOF). */
1060 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
1061 && (REGNO (operand
) != CRIS_SRP_REGNUM
1062 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
1063 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
1064 LOSE_AND_RETURN ("bad register", operand
);
1065 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
1069 /* Adjust memory address to high part. */
1071 rtx adj_mem
= operand
;
1073 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
1075 /* Adjust so we can use two SImode in DImode.
1076 Calling adj_offsettable_operand will make sure it is an
1077 offsettable address. Don't do this for a postincrement
1078 though; it should remain as it was. */
1079 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
1081 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
1083 output_address (VOIDmode
, XEXP (adj_mem
, 0));
1088 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
1092 /* Strip the MEM expression. */
1093 operand
= XEXP (operand
, 0);
1097 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
1098 iterators and attributes in cris.md to avoid the need for %x
1099 and %E (and %e) and state passed between those modifiers. */
1100 cris_output_insn_is_bound
= 0;
1103 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
1104 cris_output_insn_is_bound is nonzero. */
1105 if (GET_CODE (operand
) != SIGN_EXTEND
1106 && GET_CODE (operand
) != ZERO_EXTEND
1107 && !CONST_INT_P (operand
))
1108 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
1110 if (cris_output_insn_is_bound
)
1112 cris_output_insn_is_bound
= 0;
1116 putc (GET_CODE (operand
) == SIGN_EXTEND
1117 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
1122 /* Print the size letter of the inner element. We can do it by
1123 calling ourselves with the 's' modifier. */
1124 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
1125 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
1126 cris_print_operand (file
, XEXP (operand
, 0), 's');
1130 /* Print the least significant part of operand. */
1131 if (GET_CODE (operand
) == CONST_DOUBLE
)
1133 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
1136 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1138 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1139 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1142 /* Otherwise the least significant part equals the normal part,
1143 so handle it normally. */
1147 /* When emitting an add for the high part of a DImode constant, we
1148 want to use addq for 0 and adds.w for -1. */
1149 if (!CONST_INT_P (operand
))
1150 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1151 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1155 /* For const_int operands, print the additive mnemonic and the
1156 modified operand (byte-sized operands don't save anything):
1157 N=MIN_INT..-65536: add.d N
1158 -65535..-64: subu.w -N
1162 65536..MAX_INT: add.d N.
1163 (Emitted mnemonics are capitalized to simplify testing.)
1164 For anything else (N.B: only register is valid), print "add.d". */
1165 if (REG_P (operand
))
1167 fprintf (file
, "Add.d ");
1169 /* Deal with printing the operand by dropping through to the
1176 gcc_assert (CONST_INT_P (operand
));
1178 val
= INTVAL (operand
);
1179 if (!IN_RANGE (val
, -65535, 65535))
1180 fprintf (file
, "Add.d %d", val
);
1181 else if (val
<= -64)
1182 fprintf (file
, "Subu.w %d", -val
);
1184 fprintf (file
, "Subq %d", -val
);
1186 fprintf (file
, "Addq %d", val
);
1187 else if (val
<= 65535)
1188 fprintf (file
, "Addu.w %d", val
);
1194 /* If the operand is an integer -31..31, print "q" else ".d". */
1195 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1196 fprintf (file
, "q");
1198 fprintf (file
, ".d");
1202 /* When emitting an sub for the high part of a DImode constant, we
1203 want to use subq for 0 and subs.w for -1. */
1204 if (!CONST_INT_P (operand
))
1205 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1206 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1210 /* Print the operand as the index-part of an address.
1211 Easiest way out is to use cris_print_index. */
1212 cris_print_index (operand
, file
);
1217 /* Print the size letter for an operand to a ASHIFT, which must be a
1218 const_int with a suitable value. */
1221 if (!CONST_INT_P (operand
))
1222 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1224 shiftval
= INTVAL (operand
);
1226 if (!(shiftval
== 1 || shiftval
== 2))
1227 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1229 fprintf (file
, "%s", shiftval
== 1 ? ".w" : ".d");
1234 /* No code, print as usual. */
1238 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1241 /* Print an operand as without a modifier letter. */
1242 switch (GET_CODE (operand
))
1245 if (REGNO (operand
) > 15
1246 && REGNO (operand
) != CRIS_MOF_REGNUM
1247 && REGNO (operand
) != CRIS_SRP_REGNUM
1248 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1249 internal_error ("internal error: bad register: %d", REGNO (operand
));
1250 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1254 output_address (GET_MODE (operand
), XEXP (operand
, 0));
1258 if (GET_MODE (operand
) == VOIDmode
)
1259 /* A long long constant. */
1260 output_addr_const (file
, operand
);
1263 /* Only single precision is allowed as plain operands the
1267 /* FIXME: Perhaps check overflow of the "single". */
1268 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand
), l
);
1270 fprintf (file
, "0x%lx", l
);
1275 cris_output_addr_const (file
, operand
);
1281 /* For a (MULT (reg X) const_int) we output "rX.S". */
1282 int i
= CONST_INT_P (XEXP (operand
, 1))
1283 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1284 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1285 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1288 || (!CONST_INT_P (XEXP (operand
, 0))
1289 && !CONST_INT_P (XEXP (operand
, 1))))
1290 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1292 cris_print_base (reg
, file
);
1293 fprintf (file
, ".%c",
1294 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1296 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1302 /* No need to handle all strange variants, let output_addr_const
1304 if (CONSTANT_P (operand
))
1306 cris_output_addr_const (file
, operand
);
1310 LOSE_AND_RETURN ("unexpected operand", x
);
1315 cris_print_operand_punct_valid_p (unsigned char code
)
1317 return (code
== '#' || code
== '!');
1320 /* The PRINT_OPERAND_ADDRESS worker. */
1323 cris_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
1325 /* All these were inside MEM:s so output indirection characters. */
1328 if (CONSTANT_ADDRESS_P (x
))
1329 cris_output_addr_const (file
, x
);
1330 else if (cris_base_or_autoincr_p (x
, true))
1331 cris_print_base (x
, file
);
1332 else if (GET_CODE (x
) == PLUS
)
1338 if (cris_base_p (x1
, true))
1340 cris_print_base (x1
, file
);
1341 cris_print_index (x2
, file
);
1343 else if (cris_base_p (x2
, true))
1345 cris_print_base (x2
, file
);
1346 cris_print_index (x1
, file
);
1349 LOSE_AND_RETURN ("unrecognized address", x
);
1353 /* A DIP. Output more indirection characters. */
1355 cris_print_base (XEXP (x
, 0), file
);
1359 LOSE_AND_RETURN ("unrecognized address", x
);
1364 /* The RETURN_ADDR_RTX worker.
1365 We mark that the return address is used, either by EH or
1366 __builtin_return_address, for use by the function prologue and
1367 epilogue. FIXME: This isn't optimal; we just use the mark in the
1368 prologue and epilogue to say that the return address is to be stored
1369 in the stack frame. We could return SRP for leaf-functions and use the
1370 initial-value machinery. */
1373 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1375 cfun
->machine
->needs_return_address_on_stack
= 1;
1377 /* The return-address is stored just above the saved frame-pointer (if
1378 present). Apparently we can't eliminate from the frame-pointer in
1379 that direction, so use the incoming args (maybe pretended) pointer. */
1381 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1385 /* Setting the EH return return address is done by a *store* to a memory
1386 address expressed as relative to "*incoming* args". That store will
1387 be optimized away, unless the MEM is marked as volatile. N.B.: no
1388 optimization opportunities are expected to be lost due to this hack;
1389 __builtin_eh_return isn't called from elsewhere than the EH machinery
1393 cris_eh_return_handler_rtx ()
1395 rtx ret
= cris_return_addr_rtx (0, NULL_RTX
);
1396 gcc_assert (MEM_P (ret
));
1397 MEM_VOLATILE_P (ret
) = true;
1401 /* Accessor used in cris.md:return because cfun->machine isn't available
1405 cris_return_address_on_stack (void)
1407 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1408 || cfun
->machine
->needs_return_address_on_stack
;
1411 /* Accessor used in cris.md:return because cfun->machine isn't available
1415 cris_return_address_on_stack_for_return (void)
1417 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1418 : cris_return_address_on_stack ();
1421 /* This handles FP -> SP elimination offset. */
1424 cris_initial_frame_pointer_offset (void)
1428 /* Initial offset is 0 if we don't have a frame pointer. */
1431 /* And 4 for each register pushed. */
1432 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1433 if (cris_reg_saved_in_regsave_area (regno
))
1436 /* And then, last, we add the locals allocated. */
1437 offs
+= get_frame_size ();
1439 /* And more; the accumulated args size. */
1440 offs
+= crtl
->outgoing_args_size
;
1442 /* Then round it off, in case we use aligned stack. */
1443 if (TARGET_STACK_ALIGN
)
1444 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1449 /* The INITIAL_ELIMINATION_OFFSET worker.
1450 Calculate the difference between imaginary registers such as frame
1451 pointer and the stack pointer. Used to eliminate the frame pointer
1452 and imaginary arg pointer. */
1455 cris_initial_elimination_offset (int fromreg
, int toreg
)
1458 = cris_initial_frame_pointer_offset ();
1460 /* We should be able to use regs_ever_live and related prologue
1461 information here, or alpha should not as well. */
1462 bool return_address_on_stack
= cris_return_address_on_stack ();
1464 /* Here we act as if the frame-pointer were needed. */
1465 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1467 if (fromreg
== ARG_POINTER_REGNUM
1468 && toreg
== HARD_FRAME_POINTER_REGNUM
)
1469 return ap_fp_offset
;
1471 /* Between the frame pointer and the stack are only "normal" stack
1472 variables and saved registers. */
1473 if (fromreg
== FRAME_POINTER_REGNUM
1474 && toreg
== STACK_POINTER_REGNUM
)
1475 return fp_sp_offset
;
1477 /* We need to balance out the frame pointer here. */
1478 if (fromreg
== ARG_POINTER_REGNUM
1479 && toreg
== STACK_POINTER_REGNUM
)
1480 return ap_fp_offset
+ fp_sp_offset
- 4;
1482 if (fromreg
== FRAME_POINTER_REGNUM
1483 && toreg
== HARD_FRAME_POINTER_REGNUM
)
1489 /* Nonzero if X is a hard reg that can be used as an index. */
1491 reg_ok_for_base_p (const_rtx x
, bool strict
)
1493 return ((! strict
&& ! HARD_REGISTER_P (x
))
1494 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1497 /* Nonzero if X is a hard reg that can be used as an index. */
1499 reg_ok_for_index_p (const_rtx x
, bool strict
)
1501 return reg_ok_for_base_p (x
, strict
);
1504 /* True if X is a valid base register. */
1507 cris_base_p (const_rtx x
, bool strict
)
1509 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1512 /* True if X is a valid index register. */
1515 cris_index_p (const_rtx x
, bool strict
)
1517 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1520 /* True if X is a valid base register with or without autoincrement. */
1523 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1525 return (cris_base_p (x
, strict
)
1526 || (GET_CODE (x
) == POST_INC
1527 && cris_base_p (XEXP (x
, 0), strict
)));
1530 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1533 cris_bdap_index_p (const_rtx x
, bool strict
)
1536 && GET_MODE (x
) == SImode
1537 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1538 || (GET_CODE (x
) == SIGN_EXTEND
1539 && MEM_P (XEXP (x
, 0))
1540 && (GET_MODE (XEXP (x
, 0)) == HImode
1541 || GET_MODE (XEXP (x
, 0)) == QImode
)
1542 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1545 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1548 cris_biap_index_p (const_rtx x
, bool strict
)
1550 return (cris_index_p (x
, strict
)
1551 || (GET_CODE (x
) == MULT
1552 && cris_index_p (XEXP (x
, 0), strict
)
1553 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1556 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P. */
1559 cris_legitimate_address_p_hook (machine_mode mode
, rtx x
, bool strict
,
1562 return cris_legitimate_address_p (mode
, x
, strict
);
1566 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1570 if (cris_base_or_autoincr_p (x
, strict
))
1572 else if (CONSTANT_P (x
))
1575 else if (GET_CODE (x
) == PLUS
)
1580 if ((cris_base_p (x1
, strict
) && CONSTANT_P (x2
))
1581 || (cris_base_p (x2
, strict
) && CONSTANT_P (x1
))
1582 /* BDAP Rs[+], Rd. */
1583 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1584 && ((cris_base_p (x1
, strict
)
1585 && cris_bdap_index_p (x2
, strict
))
1586 || (cris_base_p (x2
, strict
)
1587 && cris_bdap_index_p (x1
, strict
))
1589 || (cris_base_p (x1
, strict
)
1590 && cris_biap_index_p (x2
, strict
))
1591 || (cris_base_p (x2
, strict
)
1592 && cris_biap_index_p (x1
, strict
)))))
1597 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1598 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1599 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1606 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1609 cris_reload_address_legitimized (rtx x
,
1610 machine_mode mode ATTRIBUTE_UNUSED
,
1611 int opnum ATTRIBUTE_UNUSED
,
1613 int ind_levels ATTRIBUTE_UNUSED
)
1615 enum reload_type type
= (enum reload_type
) itype
;
1619 if (GET_CODE (x
) != PLUS
)
1624 op1p
= &XEXP (x
, 1);
1629 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1631 rtx op00
= XEXP (op0
, 0);
1632 rtx op000
= XEXP (op00
, 0);
1633 rtx
*op000p
= &XEXP (op00
, 0);
1635 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1637 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1639 bool something_reloaded
= false;
1641 if (GET_CODE (op000
) == POST_INC
1642 && REG_P (XEXP (op000
, 0))
1643 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1644 /* No, this gets too complicated and is too rare to care
1645 about trying to improve on the general code Here.
1646 As the return-value is an all-or-nothing indicator, we
1647 punt on the other register too. */
1651 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1653 /* The address of the inner mem is a pseudo or wrong
1654 reg: reload that. */
1655 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1656 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1657 something_reloaded
= true;
1660 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1662 /* Base register is a pseudo or wrong reg: reload it. */
1663 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1664 GET_MODE (x
), VOIDmode
, 0, 0,
1666 something_reloaded
= true;
1669 gcc_assert (something_reloaded
);
1679 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1681 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1682 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1683 out a constant into the constant pool, we will trap this case and
1684 return something a bit more sane. FIXME: Check if this is a bug.
1685 Beware that we must not "override" classes that can be specified as
1686 constraint letters, or else asm operands using them will fail when
1687 they need to be reloaded. FIXME: Investigate whether that constitutes
1691 cris_preferred_reload_class (rtx x
, reg_class_t rclass
)
1693 if (rclass
!= MOF_REGS
1694 && rclass
!= MOF_SRP_REGS
1695 && rclass
!= SRP_REGS
1696 && rclass
!= CC0_REGS
1697 && rclass
!= SPECIAL_REGS
)
1698 return GENERAL_REGS
;
1700 /* We can't make use of something that's not a general register when
1701 reloading an "eliminated" register (i.e. something that has turned into
1702 e.g. sp + const_int). */
1703 if (GET_CODE (x
) == PLUS
&& !reg_class_subset_p (rclass
, GENERAL_REGS
))
1706 /* Avoid putting constants into a special register, where the instruction is
1707 shorter if loaded into a general register. */
1708 if (satisfies_constraint_P (x
) && !reg_class_subset_p (rclass
, GENERAL_REGS
))
1714 /* Worker function for TARGET_SPILL_CLASS. */
1717 cris_spill_class (reg_class_t
/* orig_class */, machine_mode
)
1722 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1725 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1726 reg_class_t from
, reg_class_t to
)
1728 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1729 their move cost within that class is higher. How about 7? That's 3
1730 for a move to a GENERAL_REGS register, 3 for the move from the
1731 GENERAL_REGS register, and 1 for the increased register pressure.
1732 Also, it's higher than the memory move cost, as it should be. */
1734 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1735 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1738 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1739 generally prefer GENERAL_REGS. */
1740 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1741 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1747 /* Worker function for TARGET_MEMORY_MOVE_COST.
1749 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1753 cris_memory_move_cost (machine_mode mode
,
1754 reg_class_t rclass ATTRIBUTE_UNUSED
,
1755 bool in ATTRIBUTE_UNUSED
)
1764 /* Worker function for SELECT_CC_MODE. */
1767 cris_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
1769 /* We have different sets of patterns before and after
1770 reload_completed, and everything before reload_completed is CCmode.
1771 At the time of this writing, this function isn't called before that
1772 time, so let's just gcc_assert on that assumption rather than doing
1773 "if (!reload_completed) return CCmode;". */
1774 gcc_assert (reload_completed
);
1776 /* For float mode or comparisons with something other than 0, we
1777 always go with CCmode. */
1778 if (GET_MODE_CLASS (GET_MODE (x
)) != MODE_INT
|| y
!= const0_rtx
)
1781 /* If we have a comparison that doesn't have to look at V or C, return
1783 if (op
== EQ
|| op
== NE
|| op
== GTU
|| op
== LEU
1784 || op
== LT
|| op
== GE
)
1787 /* We should only get here for comparison operators. */
1788 gcc_assert (op
== GEU
|| op
== LTU
|| op
== GT
|| op
== LE
);
1793 /* Worker function for TARGET_CC_MODES_COMPATIBLE.
1794 We start with CCmode for most comparisons, which merges and yields to
1795 CC_NZmode or CC_NZVCmode. The exceptions have CC_NZVCmode and can't do with
1799 cris_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
1801 if (m1
== CC_NZVCmode
)
1803 if (m2
== CC_NZVCmode
|| m2
== CCmode
)
1808 if (m2
== CC_NZVCmode
)
1810 if (m1
== CC_NZVCmode
|| m1
== CCmode
)
1821 /* Return != 0 if the return sequence for the current function is short,
1822 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1823 registers must be saved, so return 0 then. */
1826 cris_simple_epilogue (void)
1829 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1831 if (! reload_completed
1832 || frame_pointer_needed
1833 || get_frame_size () != 0
1834 || crtl
->args
.pretend_args_size
1836 || crtl
->outgoing_args_size
1837 || crtl
->calls_eh_return
1839 /* If we're not supposed to emit prologue and epilogue, we must
1840 not emit return-type instructions. */
1841 || !TARGET_PROLOGUE_EPILOGUE
)
1844 /* No simple epilogue if there are saved registers. */
1845 for (regno
= 0; regno
< reglimit
; regno
++)
1846 if (cris_reg_saved_in_regsave_area (regno
))
1852 /* Emit checking that MEM is aligned for an access in MODE, failing
1853 that, executing a "break 8" (or call to abort, if "break 8" is
1857 cris_emit_trap_for_misalignment (rtx mem
)
1859 rtx addr
, reg
, ok_label
, andop
;
1861 int natural_alignment
;
1862 gcc_assert (MEM_P (mem
));
1864 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
1865 addr
= XEXP (mem
, 0);
1866 reg
= force_reg (Pmode
, addr
);
1867 ok_label
= gen_label_rtx ();
1869 /* This will yield a btstq without a separate register used, usually -
1870 with the exception for PRE hoisting the "and" but not the branch
1871 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
1872 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
1873 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
1874 NULL_RTX
, Pmode
, 1, ok_label
);
1875 jmp
= get_last_insn ();
1876 gcc_assert (JUMP_P (jmp
));
1878 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
1879 expand_builtin_trap ();
1880 emit_label (ok_label
);
1883 /* Expand a return insn (just one insn) marked as using SRP or stack
1884 slot depending on parameter ON_STACK. */
1887 cris_expand_return (bool on_stack
)
1889 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1890 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1891 GCC expect just (return) to do the right thing when optimizing, so
1892 we do that until they're fixed. Currently, all return insns in a
1893 function must be the same (not really a limiting factor) so we need
1894 to check that it doesn't change half-way through. */
1895 emit_jump_insn (ret_rtx
);
1897 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
1898 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
1900 cfun
->machine
->return_type
1901 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
1904 /* Compute a (partial) cost for rtx X. Return true if the complete
1905 cost has been computed, and false if subexpressions should be
1906 scanned. In either case, *TOTAL contains the cost result. */
1909 cris_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno
,
1910 int *total
, bool speed
)
1912 int code
= GET_CODE (x
);
1918 HOST_WIDE_INT val
= INTVAL (x
);
1921 else if (val
< 32 && val
>= -32)
1924 /* For modes that fit in one register we tell they cost
1925 the same as with register operands. DImode operations
1926 needs careful consideration for more basic reasons:
1927 shifting by a non-word-size amount needs more
1928 operations than an addition by a register pair.
1929 Deliberately excluding SET, PLUS and comparisons and
1930 also not including the full -64..63 range for (PLUS
1932 case MINUS
: case ASHIFT
: case LSHIFTRT
:
1933 case ASHIFTRT
: case AND
: case IOR
:
1934 if (GET_MODE_SIZE(mode
) <= UNITS_PER_WORD
)
1944 /* Eight or 16 bits are a word and cycle more expensive. */
1945 else if (val
<= 32767 && val
>= -32768)
1947 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1948 another word. FIXME: This isn't linear to 16 bits. */
1964 if (x
!= CONST0_RTX (mode
== VOIDmode
? DImode
: mode
))
1967 /* Make 0.0 cheap, else test-insns will not be used. */
1972 /* If we have one arm of an ADDI, make sure it gets the cost of
1973 one insn, i.e. zero cost for this operand, and just the cost
1974 of the PLUS, as the insn is created by combine from a PLUS
1975 and an ASHIFT, and the MULT cost below would make the
1976 combined value be larger than the separate insns. The insn
1977 validity is checked elsewhere by combine.
1979 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
1980 function should be rewritten. */
1981 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
1987 /* Identify values that are no powers of two. Powers of 2 are
1988 taken care of already and those values should not be changed. */
1989 if (!CONST_INT_P (XEXP (x
, 1))
1990 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1992 /* If we have a multiply insn, then the cost is between
1993 1 and 2 "fast" instructions. */
1994 if (TARGET_HAS_MUL_INSNS
)
1996 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2000 /* Estimate as 4 + 4 * #ofbits. */
2001 *total
= COSTS_N_INSNS (132);
2010 if (!CONST_INT_P (XEXP (x
, 1))
2011 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2013 /* Estimate this as 4 + 8 * #of bits. */
2014 *total
= COSTS_N_INSNS (260);
2020 if (CONST_INT_P (XEXP (x
, 1))
2021 /* Two constants may actually happen before optimization. */
2022 && !CONST_INT_P (XEXP (x
, 0))
2023 && !satisfies_constraint_I (XEXP (x
, 1)))
2026 = (rtx_cost (XEXP (x
, 0), mode
, (enum rtx_code
) outer_code
,
2028 + 2 * GET_MODE_NUNITS (mode
));
2034 /* Conditionals are split after reload, giving a different look. */
2035 if (reload_completed
)
2037 if (outer_code
!= COMPARE
)
2060 case ZERO_EXTEND
: case SIGN_EXTEND
:
2061 *total
= rtx_cost (XEXP (x
, 0), VOIDmode
, (enum rtx_code
) outer_code
,
2070 /* The ADDRESS_COST worker. */
2073 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2074 addr_space_t as ATTRIBUTE_UNUSED
,
2075 bool speed ATTRIBUTE_UNUSED
)
2077 /* The metric to use for the cost-macros is unclear.
2078 The metric used here is (the number of cycles needed) / 2,
2079 where we consider equal a cycle for a word of code and a cycle to
2080 read memory. FIXME: Adding "+ 1" to all values would avoid
2081 returning 0, as tree-ssa-loop-ivopts.cc as of r128272 "normalizes"
2082 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2083 Unfortunately(?) such a hack would expose other pessimizations,
2084 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2085 loop there, without apparent reason. */
2087 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2088 if (cris_base_or_autoincr_p (x
, false))
2091 /* An indirect mem must be a DIP. This means two bytes extra for code,
2092 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2096 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2097 an extra DIP prefix and 4 bytes of constant in most cases. */
2101 /* Handle BIAP and BDAP prefixes. */
2102 if (GET_CODE (x
) == PLUS
)
2104 rtx tem1
= XEXP (x
, 0);
2105 rtx tem2
= XEXP (x
, 1);
2107 /* Local extended canonicalization rule: the first operand must
2108 be REG, unless it's an operation (MULT). */
2109 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2110 tem1
= tem2
, tem2
= XEXP (x
, 0);
2112 /* We'll "assume" we have canonical RTX now. */
2113 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2115 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2116 recognize the typical MULT which is always in tem1 because of
2117 insn canonicalization. */
2118 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2122 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2123 PLUS is always found in tem2. */
2124 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2127 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2129 if (satisfies_constraint_L (tem2
))
2132 /* A BDAP with some other constant is 2 bytes extra. */
2133 if (CONSTANT_P (tem2
))
2134 return (2 + 2 + 2) / 2;
2136 /* BDAP with something indirect should have a higher cost than
2137 BIAP with register. FIXME: Should it cost like a MEM or more? */
2138 return (2 + 2 + 2) / 2;
2141 /* What else? Return a high cost. It matters only for valid
2142 addressing modes. */
2146 /* Check various objections to the side-effect. Used in the test-part
2147 of an anonymous insn describing an insn with a possible side-effect.
2148 Returns nonzero if the implied side-effect is ok.
2151 ops : An array of rtx:es. lreg, rreg, rval,
2152 The variables multop and other_op are indexes into this,
2153 or -1 if they are not applicable.
2154 lreg : The register that gets assigned in the side-effect.
2155 rreg : One register in the side-effect expression
2156 rval : The other register, or an int.
2157 multop : An integer to multiply rval with.
2158 other_op : One of the entities of the main effect,
2159 whose mode we must consider. */
2162 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2163 int lreg
, int rreg
, int rval
,
2164 int multop
, int other_op
)
2166 /* Find what value to multiply with, for rx =ry + rz * n. */
2167 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2169 rtx reg_rtx
= ops
[rreg
];
2170 rtx val_rtx
= ops
[rval
];
2172 /* The operands may be swapped. Canonicalize them in reg_rtx and
2173 val_rtx, where reg_rtx always is a reg (for this constraint to
2175 if (! cris_base_p (reg_rtx
, lra_in_progress
|| reload_completed
))
2176 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2178 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2179 we have no business. */
2180 if (! cris_base_p (reg_rtx
, lra_in_progress
|| reload_completed
))
2183 /* Don't do this when -mno-split. */
2184 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2187 /* The mult expression may be hidden in lreg. FIXME: Add more
2188 commentary about that. */
2189 if (GET_CODE (val_rtx
) == MULT
)
2191 mult
= INTVAL (XEXP (val_rtx
, 1));
2192 val_rtx
= XEXP (val_rtx
, 0);
2196 /* First check the "other operand". */
2199 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2202 /* Check if the lvalue register is the same as the "other
2203 operand". If so, the result is undefined and we shouldn't do
2204 this. FIXME: Check again. */
2205 if ((cris_base_p (ops
[lreg
], lra_in_progress
|| reload_completed
)
2206 && cris_base_p (ops
[other_op
],
2207 lra_in_progress
|| reload_completed
)
2208 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2209 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2213 /* Do not accept frame_pointer_rtx as any operand. */
2214 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2215 || ops
[rval
] == frame_pointer_rtx
2216 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2220 && ! cris_base_p (val_rtx
, lra_in_progress
|| reload_completed
))
2223 /* Do not allow rx = rx + n if a normal add or sub with same size
2225 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2226 && CONST_INT_P (val_rtx
)
2227 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2230 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2231 if (CONSTANT_P (val_rtx
))
2235 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2236 lra_in_progress
|| reload_completed
))
2239 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2240 && MEM_P (XEXP (val_rtx
, 0))
2241 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2242 lra_in_progress
|| reload_completed
))
2245 /* If we got here, it's not a valid addressing mode. */
2248 else if (code
== MULT
2250 && cris_base_p (val_rtx
,
2251 lra_in_progress
|| reload_completed
)))
2253 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2254 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2255 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2258 /* Do not allow bad multiply-values. */
2259 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2262 /* Only allow r + ... */
2263 if (! cris_base_p (reg_rtx
, lra_in_progress
|| reload_completed
))
2266 /* If we got here, all seems ok.
2267 (All checks need to be done above). */
2271 /* If we get here, the caller got its initial tests wrong. */
2272 internal_error ("internal error: %<cris_side_effect_mode_ok%> with bad operands");
2275 /* Queue an .ident string in the queue of top-level asm statements.
2276 If the front-end is done, we must be being called from toplev.cc.
2277 In that case, do nothing. */
2279 cris_asm_output_ident (const char *string
)
2281 if (symtab
->state
!= PARSING
)
2284 default_asm_output_ident_directive (string
);
2287 /* The ASM_OUTPUT_CASE_END worker. */
2290 cris_asm_output_case_end (FILE *stream
, int num
, rtx_insn
*table
)
2292 /* Step back, over the label for the table, to the actual casejump and
2293 assert that we find only what's expected. */
2294 rtx_insn
*whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2295 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2297 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2298 gcc_assert (whole_jump_insn
!= NULL_RTX
&& JUMP_P (whole_jump_insn
));
2300 /* Get the pattern of the casejump, so we can extract the default label. */
2301 rtx whole_jump_pat
= PATTERN (whole_jump_insn
);
2303 asm_fprintf (stream
,
2304 "\t.word %LL%d-%LL%d%s\n",
2305 CODE_LABEL_NUMBER (XEXP
2307 (XEXP (XVECEXP (whole_jump_pat
, 0, 0), 1),
2310 (TARGET_PDEBUG
? "; default" : ""));
2313 /* The TARGET_OPTION_OVERRIDE worker.
2314 As is the norm, this also parses -mfoo=bar type parameters. */
2317 cris_option_override (void)
2319 if (cris_max_stackframe_str
)
2321 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2323 /* Do some sanity checking. */
2324 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2325 internal_error ("%<-max-stackframe=%d%> is not usable, "
2326 "not between 0 and %d",
2327 cris_max_stackframe
, 0x20000000);
2330 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2331 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2332 cris_cpu_version
= CRIS_CPU_SVINTO
;
2333 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2334 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2336 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2340 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2342 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2343 cris_cpu_version
= 3;
2345 if (strcmp ("svinto", cris_cpu_str
) == 0
2346 || strcmp ("etrax100", cris_cpu_str
) == 0)
2347 cris_cpu_version
= 8;
2349 if (strcmp ("ng", cris_cpu_str
) == 0
2350 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2351 cris_cpu_version
= 10;
2353 if (cris_cpu_version
< 0 || cris_cpu_version
> 10)
2354 error ("unknown CRIS version specification in %<-march=%> or "
2355 "%<-mcpu=%>: %s", cris_cpu_str
);
2357 /* Set the target flags. */
2358 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2359 target_flags
|= MASK_ETRAX4_ADD
;
2361 /* If this is Svinto or higher, align for 32 bit accesses. */
2362 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2364 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2365 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2368 /* Note that we do not add new flags when it can be completely
2369 described with a macro that uses -mcpu=X. So
2370 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2376 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2378 if (strcmp ("etrax4", cris_tune_str
) == 0)
2381 if (strcmp ("svinto", cris_tune_str
) == 0
2382 || strcmp ("etrax100", cris_tune_str
) == 0)
2385 if (strcmp ("ng", cris_tune_str
) == 0
2386 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2389 if (cris_tune
< 0 || cris_tune
> 32)
2390 error ("unknown CRIS cpu version specification in %<-mtune=%>: %s",
2393 if (cris_tune
>= CRIS_CPU_SVINTO
)
2394 /* We have currently nothing more to tune than alignment for
2397 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2398 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2403 /* Use error rather than warning, so invalid use is easily
2404 detectable. Still change to the values we expect, to avoid
2406 error ("%<-fPIC%> and %<-fpic%> are not supported on this target");
2410 /* Set the per-function-data initializer. */
2411 init_machine_status
= cris_init_machine_status
;
2414 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2417 cris_asm_output_mi_thunk (FILE *stream
,
2418 tree thunkdecl ATTRIBUTE_UNUSED
,
2419 HOST_WIDE_INT delta
,
2420 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2423 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunkdecl
));
2425 assemble_start_function (thunkdecl
, fnname
);
2426 /* Make sure unwind info is emitted for the thunk if needed. */
2427 final_start_function (emit_barrier (), stream
, 1);
2430 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2431 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2432 reg_names
[CRIS_FIRST_ARG_REG
]);
2434 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2435 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2436 reg_names
[CRIS_FIRST_ARG_REG
]);
2438 fprintf (stream
, "\tjump ");
2439 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2440 fprintf (stream
, "\n");
2442 final_end_function ();
2443 assemble_end_function (thunkdecl
, fnname
);
2446 /* Boilerplate emitted at start of file.
2448 NO_APP *only at file start* means faster assembly. It also means
2449 comments are not allowed. In some cases comments will be output
2450 for debugging purposes. Make sure they are allowed then. */
2452 cris_file_start (void)
2454 /* These expressions can vary at run time, so we cannot put
2455 them into TARGET_INITIALIZER. */
2456 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2458 default_file_start ();
2461 /* Rename the function calls for integer multiply and divide. */
2463 cris_init_libfuncs (void)
2465 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2466 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2467 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2468 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2469 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2471 /* Atomic data being unaligned is unfortunately a reality.
2473 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2475 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2476 "__cris_atcmpxchgr32");
2477 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2478 "__cris_atcmpxchgr16");
2482 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2486 cris_init_expanders (void)
2488 /* Nothing here at the moment. */
2491 /* Zero initialization is OK for all current fields. */
2493 static struct machine_function
*
2494 cris_init_machine_status (void)
2496 return ggc_cleared_alloc
<machine_function
> ();
2499 /* Split a 2 word move (DI or presumably DF) into component parts.
2500 Originally a copy of gen_split_move_double in m32r.cc. */
2503 cris_split_movdx (rtx
*operands
)
2505 machine_mode mode
= GET_MODE (operands
[0]);
2506 rtx dest
= operands
[0];
2507 rtx src
= operands
[1];
2510 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2511 longer happen; after reload there are no SUBREGs any more, and we're
2512 only called after reload. */
2513 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2518 int dregno
= REGNO (dest
);
2520 /* Reg-to-reg copy. */
2523 int sregno
= REGNO (src
);
2525 int reverse
= (dregno
== sregno
+ 1);
2527 /* We normally copy the low-numbered register first. However, if
2528 the first register operand 0 is the same as the second register of
2529 operand 1, we must copy in the opposite order. */
2530 emit_move_insn (operand_subword (dest
, reverse
, TRUE
, mode
),
2531 operand_subword (src
, reverse
, TRUE
, mode
));
2533 emit_move_insn (operand_subword (dest
, !reverse
, TRUE
, mode
),
2534 operand_subword (src
, !reverse
, TRUE
, mode
));
2536 /* Constant-to-reg copy. */
2537 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2540 split_double (src
, &words
[0], &words
[1]);
2541 emit_move_insn (operand_subword (dest
, 0, TRUE
, mode
), words
[0]);
2543 emit_move_insn (operand_subword (dest
, 1, TRUE
, mode
), words
[1]);
2545 /* Mem-to-reg copy. */
2546 else if (MEM_P (src
))
2548 /* If the high-address word is used in the address, we must load it
2549 last. Otherwise, load it first. */
2550 rtx addr
= XEXP (src
, 0);
2551 int reverse
= (refers_to_regno_p (dregno
, addr
) != 0);
2553 /* The original code implies that we can't do
2554 move.x [rN+],rM move.x [rN],rM+1
2555 when rN is dead, because of REG_NOTES damage. That is
2556 consistent with what I've seen, so don't try it.
2558 We have two different cases here; if the addr is POST_INC,
2559 just pass it through, otherwise add constants. */
2561 if (GET_CODE (addr
) == POST_INC
)
2566 /* Whenever we emit insns with post-incremented
2567 addresses ourselves, we must add a post-inc note
2569 mem
= change_address (src
, SImode
, addr
);
2570 insn
= emit_move_insn (operand_subword (dest
, 0, TRUE
, mode
),
2572 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2574 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2577 mem
= copy_rtx (mem
);
2578 insn
= emit_move_insn (operand_subword (dest
, 1, TRUE
, mode
), mem
);
2579 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2581 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2586 /* Make sure we don't get any other addresses with
2587 embedded postincrements. They should be stopped in
2588 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2590 if (side_effects_p (addr
))
2591 fatal_insn ("unexpected side-effects in address", addr
);
2593 emit_move_insn (operand_subword (dest
, reverse
, TRUE
, mode
),
2596 plus_constant (Pmode
, addr
,
2597 reverse
* UNITS_PER_WORD
)));
2598 emit_move_insn (operand_subword (dest
, ! reverse
, TRUE
, mode
),
2601 plus_constant (Pmode
, addr
,
2607 internal_error ("unknown src");
2609 /* Reg-to-mem copy or clear mem. */
2610 else if (MEM_P (dest
)
2612 || src
== const0_rtx
2613 || src
== CONST0_RTX (DFmode
)))
2615 rtx addr
= XEXP (dest
, 0);
2617 if (GET_CODE (addr
) == POST_INC
)
2622 /* Whenever we emit insns with post-incremented addresses
2623 ourselves, we must add a post-inc note manually. */
2624 mem
= change_address (dest
, SImode
, addr
);
2625 insn
= emit_move_insn (mem
, operand_subword (src
, 0, TRUE
, mode
));
2626 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2628 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2631 mem
= copy_rtx (mem
);
2632 insn
= emit_move_insn (mem
, operand_subword (src
, 1, TRUE
, mode
));
2633 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2635 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2640 /* Make sure we don't get any other addresses with embedded
2641 postincrements. They should be stopped in
2642 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2643 if (side_effects_p (addr
))
2644 fatal_insn ("unexpected side-effects in address", addr
);
2646 emit_move_insn (change_address (dest
, SImode
, addr
),
2647 operand_subword (src
, 0, TRUE
, mode
));
2649 emit_move_insn (change_address (dest
, SImode
,
2650 plus_constant (Pmode
, addr
,
2652 operand_subword (src
, 1, TRUE
, mode
));
2657 internal_error ("unknown dest");
2664 /* Try to split the constant WVAL into a number of separate insns of less cost
2665 for the rtx operation CODE and the metric SPEED than using val as-is.
2666 Generate those insns if GENERATE. DEST holds the destination, and OP holds
2667 the other operand for binary operations; NULL when CODE is SET. Return the
2668 number of insns for the operation or 0 if the constant can't be usefully
2669 split (because it's already minimal or is not within range for the known
2670 methods). Parts stolen from arm.cc. */
2673 cris_split_constant (HOST_WIDE_INT wval
, enum rtx_code code
,
2674 machine_mode mode
, bool speed ATTRIBUTE_UNUSED
,
2675 bool generate
, rtx dest
, rtx op
)
2677 int32_t ival
= (int32_t) wval
;
2678 uint32_t uval
= (uint32_t) wval
;
2680 /* Can we do with two addq or two subq, improving chances of filling a
2681 delay-slot? At worst, we break even, both performance and
2684 && (IN_RANGE (ival
, -63 * 2, -63 - 1)
2685 || IN_RANGE (ival
, 63 + 1, 63 * 2)))
2689 int sign
= ival
< 0 ? -1 : 1;
2690 int aval
= abs (ival
);
2694 dest
= gen_rtx_REG (SImode
, REGNO (dest
));
2695 op
= gen_rtx_REG (SImode
, REGNO (op
));
2697 emit_insn (gen_addsi3 (dest
, op
, GEN_INT (63 * sign
)));
2698 emit_insn (gen_addsi3 (dest
, op
, GEN_INT ((aval
- 63) * sign
)));
2703 if (code
!= AND
|| IN_RANGE (ival
, -32, 31)
2704 /* Implemented using movu.[bw] elsewhere. */
2705 || ival
== 255 || ival
== 65535
2706 /* Implemented using clear.[bw] elsewhere. */
2707 || uval
== 0xffffff00 || uval
== 0xffff0000)
2715 /* Count number of leading zeros. */
2716 for (i
= 31; i
>= 0; i
--)
2718 if ((uval
& (1 << i
)) == 0)
2724 /* Count number of trailing zero's. */
2725 for (i
= 0; i
<= 31; i
++)
2727 if ((uval
& (1 << i
)) == 0)
2733 /* Is there a lowest or highest part that is zero (but not both)
2734 and the non-zero part is just ones? */
2735 if (exact_log2 ((uval
>> lsb_zeros
) + 1) > 0
2736 && (lsb_zeros
!= 0) != (msb_zeros
!= 0))
2738 /* If so, we can shift OP in the zero direction, then back. We don't
2739 nominally win anything for uval < 256, except that the insns are split
2740 into slottable insns so it's always beneficial. */
2745 dest
= gen_rtx_REG (SImode
, REGNO (dest
));
2746 op
= gen_rtx_REG (SImode
, REGNO (op
));
2750 emit_insn (gen_ashlsi3 (dest
, op
, GEN_INT (msb_zeros
)));
2751 emit_insn (gen_lshrsi3 (dest
, op
, GEN_INT (msb_zeros
)));
2755 emit_insn (gen_lshrsi3 (dest
, op
, GEN_INT (lsb_zeros
)));
2756 emit_insn (gen_ashlsi3 (dest
, op
, GEN_INT (lsb_zeros
)));
2765 /* Try to change a comparison against a constant to be against zero, and
2766 an unsigned compare against zero to be an equality test. Beware:
2767 only valid for compares of integer-type operands. Also, note that we
2768 don't use operand 0 at the moment. */
2771 cris_reduce_compare (rtx
*relp
, rtx
*, rtx
*op1p
)
2774 rtx_code code
= GET_CODE (*relp
);
2776 /* Code lifted mostly from emit_store_flag_1. */
2780 if (op1
== const1_rtx
)
2784 if (op1
== constm1_rtx
)
2788 if (op1
== const1_rtx
)
2792 if (op1
== constm1_rtx
)
2796 if (op1
== const1_rtx
)
2800 if (op1
== const1_rtx
)
2804 if (op1
== const0_rtx
)
2808 if (op1
== const0_rtx
)
2815 if (code
!= GET_CODE (*relp
))
2818 PUT_CODE (*relp
, code
);
2822 /* The expander for the prologue pattern name. */
2825 cris_expand_prologue (void)
2828 int size
= get_frame_size ();
2829 /* Shorten the used name for readability. */
2830 int cfoa_size
= crtl
->outgoing_args_size
;
2831 int last_movem_reg
= -1;
2834 int return_address_on_stack
= cris_return_address_on_stack ();
2835 int n_movem_regs
= 0;
2836 int pretend
= crtl
->args
.pretend_args_size
;
2838 /* Don't do anything if no prologues or epilogues are wanted. */
2839 if (!TARGET_PROLOGUE_EPILOGUE
)
2842 CRIS_ASSERT (size
>= 0);
2844 /* Align the size to what's best for the CPU model. */
2845 if (TARGET_STACK_ALIGN
)
2846 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2850 /* See also cris_setup_incoming_varargs where
2851 cfun->machine->stdarg_regs is set. There are other setters of
2852 crtl->args.pretend_args_size than stdarg handling, like
2853 for an argument passed with parts in R13 and stack. We must
2854 not store R13 into the pretend-area for that case, as GCC does
2855 that itself. "Our" store would be marked as redundant and GCC
2856 will attempt to remove it, which will then be flagged as an
2857 internal error; trying to remove a frame-related insn. */
2858 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
2860 framesize
+= pretend
;
2862 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
2864 regno
--, pretend
-= 4, stdarg_regs
--)
2866 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (-4)));
2867 /* FIXME: When dwarf2 frame output and unless asynchronous
2868 exceptions, make dwarf2 bundle together all stack
2869 adjustments like it does for registers between stack
2871 RTX_FRAME_RELATED_P (insn
) = 1;
2873 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2874 set_mem_alias_set (mem
, get_varargs_alias_set ());
2875 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
2877 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2878 the value isn't restored, so we don't want to tell dwarf2
2879 that it's been stored to stack, else EH handling info would
2883 /* For other setters of crtl->args.pretend_args_size, we
2884 just adjust the stack by leaving the remaining size in
2885 "pretend", handled below. */
2888 /* Save SRP if not a leaf function. */
2889 if (return_address_on_stack
)
2891 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2892 GEN_INT (-4 - pretend
)));
2894 RTX_FRAME_RELATED_P (insn
) = 1;
2896 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2897 set_mem_alias_set (mem
, get_frame_alias_set ());
2898 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, CRIS_SRP_REGNUM
));
2899 RTX_FRAME_RELATED_P (insn
) = 1;
2903 /* Set up the frame pointer, if needed. */
2904 if (frame_pointer_needed
)
2906 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2907 GEN_INT (-4 - pretend
)));
2909 RTX_FRAME_RELATED_P (insn
) = 1;
2911 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2912 set_mem_alias_set (mem
, get_frame_alias_set ());
2913 insn
= emit_move_insn (mem
, hard_frame_pointer_rtx
);
2914 RTX_FRAME_RELATED_P (insn
) = 1;
2916 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2917 RTX_FRAME_RELATED_P (insn
) = 1;
2922 /* Between frame-pointer and saved registers lie the area for local
2923 variables. If we get here with "pretended" size remaining, count
2924 it into the general stack size. */
2927 /* Get a contiguous sequence of registers, starting with R0, that need
2929 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2931 if (cris_reg_saved_in_regsave_area (regno
))
2935 /* Check if movem may be used for registers so far. */
2936 if (regno
== last_movem_reg
+ 1)
2937 /* Yes, update next expected register. */
2938 last_movem_reg
= regno
;
2941 /* We cannot use movem for all registers. We have to flush
2942 any movem:ed registers we got so far. */
2943 if (last_movem_reg
!= -1)
2946 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2948 /* It is a win to use a side-effect assignment for
2949 64 <= size <= 128. But side-effect on movem was
2950 not usable for CRIS v0..3. Also only do it if
2951 side-effects insns are allowed. */
2952 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2953 && (last_movem_reg
+ 1) * 4 + size
<= 128
2954 && cris_cpu_version
>= CRIS_CPU_SVINTO
2955 /* Don't use side-effect assignment for a single
2958 && TARGET_SIDE_EFFECT_PREFIXES
)
2961 = gen_rtx_MEM (SImode
,
2962 plus_constant (Pmode
, stack_pointer_rtx
,
2963 -(n_saved
* 4 + size
)));
2964 set_mem_alias_set (mem
, get_frame_alias_set ());
2966 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2967 -(n_saved
* 4 + size
),
2973 = emit_insn (gen_add2_insn (stack_pointer_rtx
,
2974 GEN_INT (-(n_saved
* 4
2976 RTX_FRAME_RELATED_P (insn
) = 1;
2978 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2979 set_mem_alias_set (mem
, get_frame_alias_set ());
2980 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2984 framesize
+= n_saved
* 4 + size
;
2985 last_movem_reg
= -1;
2989 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2990 GEN_INT (-4 - size
)));
2991 RTX_FRAME_RELATED_P (insn
) = 1;
2993 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2994 set_mem_alias_set (mem
, get_frame_alias_set ());
2995 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
2996 RTX_FRAME_RELATED_P (insn
) = 1;
2998 framesize
+= 4 + size
;
3004 /* Check after, if we could movem all registers. This is the normal case. */
3005 if (last_movem_reg
!= -1)
3008 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3010 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3011 do it if side-effects insns are allowed. */
3012 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3013 && (last_movem_reg
+ 1) * 4 + size
<= 128
3014 && cris_cpu_version
>= CRIS_CPU_SVINTO
3015 /* Don't use side-effect assignment for a single move. */
3017 && TARGET_SIDE_EFFECT_PREFIXES
)
3020 = gen_rtx_MEM (SImode
,
3021 plus_constant (Pmode
, stack_pointer_rtx
,
3022 -(n_saved
* 4 + size
)));
3023 set_mem_alias_set (mem
, get_frame_alias_set ());
3024 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3025 -(n_saved
* 4 + size
), true);
3029 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
3030 GEN_INT (-(n_saved
* 4 + size
))));
3031 RTX_FRAME_RELATED_P (insn
) = 1;
3033 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3034 set_mem_alias_set (mem
, get_frame_alias_set ());
3035 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3038 framesize
+= n_saved
* 4 + size
;
3039 /* We have to put outgoing argument space after regs. */
3042 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
3043 GEN_INT (-cfoa_size
)));
3044 RTX_FRAME_RELATED_P (insn
) = 1;
3045 framesize
+= cfoa_size
;
3048 else if ((size
+ cfoa_size
) > 0)
3050 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
3051 GEN_INT (-(cfoa_size
+ size
))));
3052 RTX_FRAME_RELATED_P (insn
) = 1;
3053 framesize
+= size
+ cfoa_size
;
3056 /* FIXME: -mmax-stackframe=SIZE is obsoleted; use -Wstack-usage=SIZE
3057 instead. Make it an alias? */
3058 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3059 warning (0, "stackframe too big: %d bytes", framesize
);
3061 if (flag_stack_usage_info
)
3062 current_function_static_stack_size
= framesize
;
3065 /* The expander for the epilogue pattern. */
3068 cris_expand_epilogue (void)
3071 int size
= get_frame_size ();
3072 int last_movem_reg
= -1;
3073 int argspace_offset
= crtl
->outgoing_args_size
;
3074 int pretend
= crtl
->args
.pretend_args_size
;
3076 bool return_address_on_stack
= cris_return_address_on_stack ();
3077 /* A reference may have been optimized out
3078 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3079 so check that it's still used. */
3080 int n_movem_regs
= 0;
3082 if (!TARGET_PROLOGUE_EPILOGUE
)
3085 /* Align byte count of stack frame. */
3086 if (TARGET_STACK_ALIGN
)
3087 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3089 /* Check how many saved regs we can movem. They start at r0 and must
3092 regno
< FIRST_PSEUDO_REGISTER
;
3094 if (cris_reg_saved_in_regsave_area (regno
))
3098 if (regno
== last_movem_reg
+ 1)
3099 last_movem_reg
= regno
;
3104 /* If there was only one register that really needed to be saved
3105 through movem, don't use movem. */
3106 if (n_movem_regs
== 1)
3107 last_movem_reg
= -1;
3109 /* Now emit "normal" move insns for all regs higher than the movem
3111 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3112 regno
> last_movem_reg
;
3114 if (cris_reg_saved_in_regsave_area (regno
))
3118 if (argspace_offset
)
3120 /* There is an area for outgoing parameters located before
3121 the saved registers. We have to adjust for that. */
3122 emit_insn (gen_add2_insn (stack_pointer_rtx
,
3123 GEN_INT (argspace_offset
)));
3124 /* Make sure we only do this once. */
3125 argspace_offset
= 0;
3128 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3129 stack_pointer_rtx
));
3130 set_mem_alias_set (mem
, get_frame_alias_set ());
3131 insn
= emit_move_insn (gen_raw_REG (SImode
, regno
), mem
);
3133 /* Whenever we emit insns with post-incremented addresses
3134 ourselves, we must add a post-inc note manually. */
3136 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3139 /* If we have any movem-restore, do it now. */
3140 if (last_movem_reg
!= -1)
3144 if (argspace_offset
)
3146 emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (argspace_offset
)));
3147 argspace_offset
= 0;
3150 mem
= gen_rtx_MEM (SImode
,
3151 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3152 set_mem_alias_set (mem
, get_frame_alias_set ());
3154 = emit_insn (cris_gen_movem_load (mem
, GEN_INT (last_movem_reg
+ 1)));
3155 /* Whenever we emit insns with post-incremented addresses
3156 ourselves, we must add a post-inc note manually. */
3157 if (side_effects_p (PATTERN (insn
)))
3159 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3162 /* If we don't clobber all of the allocated stack area (we've already
3163 deallocated saved registers), GCC might want to schedule loads from
3164 the stack to *after* the stack-pointer restore, which introduces an
3165 interrupt race condition. This happened for the initial-value
3166 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3167 other failure for that test). It also happened for the stack slot
3168 for the return value in (one version of)
3169 linux/fs/dcache.c:__d_lookup, at least with "-O2
3170 -fno-omit-frame-pointer". */
3172 /* Restore frame pointer if necessary. */
3173 if (frame_pointer_needed
)
3177 emit_insn (gen_cris_frame_deallocated_barrier ());
3179 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3180 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3181 stack_pointer_rtx
));
3182 set_mem_alias_set (mem
, get_frame_alias_set ());
3183 insn
= emit_move_insn (hard_frame_pointer_rtx
, mem
);
3185 /* Whenever we emit insns with post-incremented addresses
3186 ourselves, we must add a post-inc note manually. */
3188 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3190 else if ((size
+ argspace_offset
) != 0)
3192 emit_insn (gen_cris_frame_deallocated_barrier ());
3194 /* If there was no frame-pointer to restore sp from, we must
3195 explicitly deallocate local variables. */
3197 /* Handle space for outgoing parameters that hasn't been handled
3199 size
+= argspace_offset
;
3201 emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (size
)));
3204 /* If this function has no pushed register parameters
3205 (stdargs/varargs), and if it is not a leaf function, then we have
3206 the return address on the stack. */
3207 if (return_address_on_stack
&& pretend
== 0)
3209 if (crtl
->calls_eh_return
)
3213 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3214 mem
= gen_rtx_MEM (SImode
,
3215 gen_rtx_POST_INC (SImode
,
3216 stack_pointer_rtx
));
3217 set_mem_alias_set (mem
, get_frame_alias_set ());
3218 insn
= emit_move_insn (srpreg
, mem
);
3220 /* Whenever we emit insns with post-incremented addresses
3221 ourselves, we must add a post-inc note manually. */
3223 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3225 if (crtl
->calls_eh_return
)
3226 emit_insn (gen_add2_insn (stack_pointer_rtx
,
3227 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3228 cris_expand_return (false);
3231 cris_expand_return (true);
3236 /* If we pushed some register parameters, then adjust the stack for
3240 /* If SRP is stored on the way, we need to restore it first. */
3241 if (return_address_on_stack
)
3244 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3247 mem
= gen_rtx_MEM (SImode
,
3248 gen_rtx_POST_INC (SImode
,
3249 stack_pointer_rtx
));
3250 set_mem_alias_set (mem
, get_frame_alias_set ());
3251 insn
= emit_move_insn (srpreg
, mem
);
3253 /* Whenever we emit insns with post-incremented addresses
3254 ourselves, we must add a post-inc note manually. */
3256 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3259 emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (pretend
)));
3262 /* Perform the "physical" unwinding that the EH machinery calculated. */
3263 if (crtl
->calls_eh_return
)
3264 emit_insn (gen_add2_insn (stack_pointer_rtx
,
3265 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3266 cris_expand_return (false);
3269 /* Worker function for generating movem from mem for load_multiple. */
3272 cris_gen_movem_load (rtx src
, rtx nregs_rtx
)
3274 int nregs
= INTVAL (nregs_rtx
);
3278 rtx srcreg
= XEXP (src
, 0);
3279 unsigned int regno
= nregs
- 1;
3282 if (GET_CODE (srcreg
) == POST_INC
)
3283 srcreg
= XEXP (srcreg
, 0);
3285 CRIS_ASSERT (REG_P (srcreg
));
3287 /* Don't use movem for just one insn. The insns are equivalent. */
3289 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3291 vec
= rtvec_alloc (nregs
+ (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3293 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3296 = gen_rtx_SET (srcreg
, plus_constant (Pmode
, srcreg
, nregs
* 4));
3300 src
= replace_equiv_address (src
, srcreg
);
3302 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
), src
);
3305 for (i
= 1; i
< nregs
; i
++, eltno
++)
3307 RTVEC_ELT (vec
, eltno
)
3308 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
),
3309 adjust_address_nv (src
, SImode
, i
* 4));
3313 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3316 /* Convenience function for CRIS-local use of emit_insn, wrapping the
3317 argument in a parallel with a clobber of CRIS_CC0_REGNUM before
3318 passing on to emit_insn. */
3321 cris_emit_insn (rtx x
)
3323 rtvec vec
= rtvec_alloc (2);
3325 RTVEC_ELT (vec
, 0) = x
;
3327 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
3329 return emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3332 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3333 are added that the dwarf2 machinery understands. */
3336 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3339 int nregs
= INTVAL (nregs_rtx
);
3344 rtx destreg
= XEXP (dest
, 0);
3345 unsigned int regno
= nregs
- 1;
3348 if (GET_CODE (destreg
) == POST_INC
)
3349 increment
+= nregs
* 4;
3351 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3352 destreg
= XEXP (destreg
, 0);
3354 CRIS_ASSERT (REG_P (destreg
));
3356 /* Don't use movem for just one insn. The insns are equivalent. */
3361 insn
= emit_move_insn (dest
, gen_rtx_REG (SImode
, 0));
3363 RTX_FRAME_RELATED_P (insn
) = 1;
3367 /* If there was a request for a side-effect, create the ordinary
3369 vec
= rtvec_alloc (3);
3371 rtx mov
= gen_rtx_SET (dest
, gen_rtx_REG (SImode
, 0));
3372 RTVEC_ELT (vec
, 0) = mov
;
3373 RTVEC_ELT (vec
, 1) = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3376 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
3380 RTX_FRAME_RELATED_P (mov
) = 1;
3381 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3386 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3388 = gen_rtx_SET (replace_equiv_address (dest
,
3389 plus_constant (Pmode
, destreg
,
3391 gen_rtx_REG (SImode
, regno
));
3394 /* The dwarf2 info wants this mark on each component in a parallel
3395 that's part of the prologue (though it's optional on the first
3398 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3403 = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3405 ? increment
: nregs
* 4));
3409 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3411 /* Don't call adjust_address_nv on a post-incremented address if
3413 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3414 dest
= replace_equiv_address (dest
, destreg
);
3417 for (i
= 1; i
< nregs
; i
++, eltno
++)
3419 RTVEC_ELT (vec
, eltno
)
3420 = gen_rtx_SET (adjust_address_nv (dest
, SImode
, i
* 4),
3421 gen_rtx_REG (SImode
, regno
));
3423 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3428 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3430 /* Because dwarf2out.cc handles the insns in a parallel as a sequence,
3431 we need to keep the stack adjustment separate, after the
3432 MEM-setters. Else the stack-adjustment in the second component of
3433 the parallel would be mishandled; the offsets for the SETs that
3434 follow it would be wrong. We prepare for this by adding a
3435 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3436 followed by the increment. Note that we have FRAME_RELATED_P on
3437 all the SETs, including the original stack adjustment SET in the
3443 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3444 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3445 for (i
= 1; i
< nregs
; i
++)
3447 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3448 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3449 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3452 RTX_FRAME_RELATED_P (insn
) = 1;
3458 /* Make sure operands are in the right order for an addsi3 insn as
3459 generated by a define_split. Nothing but REG_P as the first
3460 operand is recognized by addsi3 after reload. OPERANDS contains
3461 the operands, with the first at OPERANDS[N] and the second at
3465 cris_order_for_addsi3 (rtx
*operands
, int n
)
3467 if (!REG_P (operands
[n
]))
3469 rtx tem
= operands
[n
];
3470 operands
[n
] = operands
[n
+ 1];
3471 operands
[n
+ 1] = tem
;
3475 /* Use from within code, from e.g. PRINT_OPERAND and
3476 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3477 different things depending on whether code operand or constant is
3481 cris_output_addr_const (FILE *file
, rtx x
)
3484 output_addr_const (file
, x
);
3488 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3491 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3493 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3494 assemble_name (file
, XSTR (x
, 0));
3497 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3500 cris_asm_output_label_ref (FILE *file
, char *buf
)
3502 assemble_name (file
, buf
);
3505 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3508 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3509 int incoming ATTRIBUTE_UNUSED
)
3511 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3514 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3517 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
3518 const function_arg_info
&,
3519 int *pretend_arg_size
,
3522 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3524 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3526 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
3527 cfun
->machine
->stdarg_regs
= stdarg_regs
;
3528 *pretend_arg_size
= stdarg_regs
* 4;
3532 fprintf (asm_out_file
,
3533 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3534 ca
->regs
, *pretend_arg_size
, second_time
);
3537 /* Return true if ARG must be passed by invisible reference.
3538 For cris, we pass <= 8 bytes by value, others by reference. */
3541 cris_pass_by_reference (cumulative_args_t
, const function_arg_info
&arg
)
3543 return (targetm
.calls
.must_pass_in_stack (arg
)
3544 || CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
) > 8);
3547 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
3548 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
3549 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
3552 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
3554 int *punsignedp ATTRIBUTE_UNUSED
,
3555 const_tree fntype ATTRIBUTE_UNUSED
,
3558 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
3559 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
3560 Maybe pointless as of now, but let's keep the old behavior. */
3561 if (for_return
== 1)
3563 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
3566 /* Atomic types require alignment to be at least their "natural" size. */
3569 cris_atomic_align_for_mode (machine_mode mode
)
3571 return GET_MODE_BITSIZE (mode
);
3574 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3578 cris_function_value(const_tree type
,
3579 const_tree func ATTRIBUTE_UNUSED
,
3580 bool outgoing ATTRIBUTE_UNUSED
)
3582 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
3585 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3589 cris_libcall_value (machine_mode mode
,
3590 const_rtx fun ATTRIBUTE_UNUSED
)
3592 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
3595 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3599 cris_function_value_regno_p (const unsigned int regno
)
3601 return (regno
== CRIS_FIRST_ARG_REG
);
3605 cris_arg_partial_bytes (cumulative_args_t ca
, const function_arg_info
&arg
)
3607 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
3608 && !targetm
.calls
.must_pass_in_stack (arg
)
3609 && CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
) > 4
3610 && CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
) <= 8)
3611 return UNITS_PER_WORD
;
3617 cris_function_arg_1 (cumulative_args_t ca_v
, const function_arg_info
&arg
,
3620 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3622 if ((!incoming
|| arg
.named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3623 return gen_rtx_REG (arg
.mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
3628 /* Worker function for TARGET_FUNCTION_ARG.
3629 The void_type_node is sent as a "closing" call. */
3632 cris_function_arg (cumulative_args_t ca
, const function_arg_info
&arg
)
3634 return cris_function_arg_1 (ca
, arg
, false);
3637 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
3639 The differences between this and the previous, is that this one checks
3640 that an argument is named, since incoming stdarg/varargs arguments are
3641 pushed onto the stack, and we don't have to check against the "closing"
3642 function_arg_info::end_marker parameter. */
3645 cris_function_incoming_arg (cumulative_args_t ca
, const function_arg_info
&arg
)
3647 return cris_function_arg_1 (ca
, arg
, true);
3650 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
3653 cris_function_arg_advance (cumulative_args_t ca_v
,
3654 const function_arg_info
&arg
)
3656 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3658 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
)) / 4;
3661 /* Worker function for TARGET_MD_ASM_ADJUST. */
3664 cris_md_asm_adjust (vec
<rtx
> &outputs
, vec
<rtx
> &inputs
,
3665 vec
<machine_mode
> & /*input_modes*/,
3666 vec
<const char *> &constraints
,
3667 vec
<rtx
> &/*uses*/, vec
<rtx
> &clobbers
,
3668 HARD_REG_SET
&clobbered_regs
, location_t
/*loc*/)
3670 /* For the time being, all asms clobber condition codes.
3671 Revisit when there's a reasonable use for inputs/outputs
3672 that mention condition codes. */
3673 clobbers
.safe_push (gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
3674 SET_HARD_REG_BIT (clobbered_regs
, CRIS_CC0_REGNUM
);
3676 /* Determine if the source using MOF. If it is, automatically
3677 clobbering MOF would cause it to have impossible constraints. */
3679 /* Look for a use of the MOF constraint letter: h. */
3680 for (unsigned i
= 0, n
= constraints
.length(); i
< n
; ++i
)
3681 if (strchr (constraints
[i
], 'h') != NULL
)
3684 /* Look for an output or an input that touches MOF. */
3685 rtx mof_reg
= gen_rtx_REG (SImode
, CRIS_MOF_REGNUM
);
3686 for (unsigned i
= 0, n
= outputs
.length(); i
< n
; ++i
)
3687 if (reg_overlap_mentioned_p (mof_reg
, outputs
[i
]))
3689 for (unsigned i
= 0, n
= inputs
.length(); i
< n
; ++i
)
3690 if (reg_overlap_mentioned_p (mof_reg
, inputs
[i
]))
3693 /* No direct reference to MOF or its constraint.
3694 Clobber it for backward compatibility. */
3695 clobbers
.safe_push (mof_reg
);
3696 SET_HARD_REG_BIT (clobbered_regs
, CRIS_MOF_REGNUM
);
3700 /* Implement TARGET_FRAME_POINTER_REQUIRED.
3702 Really only needed if the stack frame has variable length (alloca
3703 or variable sized local arguments (GNU C extension). See PR39499 and
3704 PR38609 for the reason this isn't just 0. */
3707 cris_frame_pointer_required (void)
3709 return !crtl
->sp_is_unchanging
;
3712 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
3714 This looks too complicated, and it is. I assigned r7 to be the
3715 static chain register, but it is call-saved, so we have to save it,
3716 and come back to restore it after the call, so we have to save srp...
3717 Anyway, trampolines are rare enough that we can cope with this
3718 somewhat lack of elegance.
3719 (Do not be tempted to "straighten up" whitespace in the asms; the
3720 assembler #NO_APP state mandates strict spacing). */
3721 /* ??? See the i386 regparm=3 implementation that pushes the static
3722 chain value to the stack in the trampoline, and uses a call-saved
3723 register when called directly. */
3726 cris_asm_trampoline_template (FILE *f
)
3728 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3729 fprintf (f
, "\tmove $srp,[$pc+22]\n");
3730 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3731 fprintf (f
, "\tjsr 0\n");
3732 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3733 fprintf (f
, "\tjump 0\n");
3736 /* Implement TARGET_TRAMPOLINE_INIT. */
3739 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3741 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3744 emit_block_move (m_tramp
, assemble_trampoline_template (),
3745 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
3747 mem
= adjust_address (m_tramp
, SImode
, 10);
3748 emit_move_insn (mem
, chain_value
);
3749 mem
= adjust_address (m_tramp
, SImode
, 16);
3750 emit_move_insn (mem
, fnaddr
);
3752 /* Note that there is no need to do anything with the cache for
3753 sake of a trampoline. */
3756 /* Implement TARGET_HARD_REGNO_NREGS.
3758 The VOIDmode test is so we can omit mode on anonymous insns. FIXME:
3759 Still needed in 2.9x, at least for Axis-20000319. */
3762 cris_hard_regno_nregs (unsigned int, machine_mode mode
)
3764 if (mode
== VOIDmode
)
3766 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
3769 /* Implement TARGET_HARD_REGNO_MODE_OK.
3771 CRIS permits all registers to hold all modes. Well, except for the
3772 condition-code register. And we can't hold larger-than-register size
3773 modes in the last special register that can hold a full 32 bits. */
3775 cris_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
3777 return ((mode
== CCmode
|| regno
!= CRIS_CC0_REGNUM
)
3778 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
3779 || regno
!= CRIS_MOF_REGNUM
));
3782 /* Return the preferred minimum alignment for a static object. */
3784 static HOST_WIDE_INT
3785 cris_preferred_minimum_alignment (void)
3787 if (!TARGET_CONST_ALIGN
)
3789 if (TARGET_ALIGN_BY_32
)
3794 /* Implement TARGET_STATIC_RTX_ALIGNMENT. */
3796 static HOST_WIDE_INT
3797 cris_static_rtx_alignment (machine_mode mode
)
3799 return MAX (cris_preferred_minimum_alignment (), GET_MODE_ALIGNMENT (mode
));
3802 /* Implement TARGET_CONSTANT_ALIGNMENT. Note that this hook has the
3803 effect of making gcc believe that ALL references to constant stuff
3804 (in code segment, like strings) have this alignment. That is a rather
3805 rushed assumption. Luckily we do not care about the "alignment"
3806 operand to builtin memcpy (only place where it counts), so it doesn't
3807 affect any bad spots. */
3809 static HOST_WIDE_INT
3810 cris_constant_alignment (const_tree
, HOST_WIDE_INT basic_align
)
3812 return MAX (cris_preferred_minimum_alignment (), basic_align
);
3816 /* Various small functions to replace macros. Only called from a
3817 debugger. They might collide with gcc functions or system functions,
3818 so only emit them when '#if 1' above. */
3820 enum rtx_code
Get_code (rtx
);
3825 return GET_CODE (x
);
3828 const char *Get_mode (rtx
);
3833 return GET_MODE_NAME (GET_MODE (x
));
3836 rtx
Xexp (rtx
, int);
3844 rtx
Xvecexp (rtx
, int, int);
3847 Xvecexp (rtx x
, int n
, int m
)
3849 return XVECEXP (x
, n
, m
);
3852 int Get_rtx_len (rtx
);
3857 return GET_RTX_LENGTH (GET_CODE (x
));
3860 /* Use upper-case to distinguish from local variables that are sometimes
3861 called next_insn and prev_insn. */
3863 rtx
Next_insn (rtx
);
3866 Next_insn (rtx insn
)
3868 return NEXT_INSN (insn
);
3871 rtx
Prev_insn (rtx
);
3874 Prev_insn (rtx insn
)
3876 return PREV_INSN (insn
);
3880 #include "gt-cris.h"
3884 * eval: (c-set-style "gnu")
3885 * indent-tabs-mode: t