| blob | 3b95ef40ca6b457919b1fc55dc9e8b3b83342e92 |
1 ;; Machine Description for MIPS MSA ASE
2 ;; Based on the MIPS MSA spec Revision 1.11 8/4/2014
3 ;;
4 ;; Copyright (C) 2015-2018 Free Software Foundation, Inc.
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21 ;;
23 (define_c_enum "unspec" [
24 UNSPEC_MSA_ASUB_S
25 UNSPEC_MSA_ASUB_U
26 UNSPEC_MSA_AVE_S
27 UNSPEC_MSA_AVE_U
28 UNSPEC_MSA_AVER_S
29 UNSPEC_MSA_AVER_U
30 UNSPEC_MSA_BCLR
31 UNSPEC_MSA_BCLRI
32 UNSPEC_MSA_BINSL
33 UNSPEC_MSA_BINSLI
34 UNSPEC_MSA_BINSR
35 UNSPEC_MSA_BINSRI
36 UNSPEC_MSA_BNEG
37 UNSPEC_MSA_BNEGI
38 UNSPEC_MSA_BSET
39 UNSPEC_MSA_BSETI
40 UNSPEC_MSA_BRANCH_V
41 UNSPEC_MSA_BRANCH
42 UNSPEC_MSA_CFCMSA
43 UNSPEC_MSA_CTCMSA
44 UNSPEC_MSA_FCAF
45 UNSPEC_MSA_FCLASS
46 UNSPEC_MSA_FCUNE
47 UNSPEC_MSA_FEXDO
48 UNSPEC_MSA_FEXP2
49 UNSPEC_MSA_FEXUPL
50 UNSPEC_MSA_FEXUPR
51 UNSPEC_MSA_FFQL
52 UNSPEC_MSA_FFQR
53 UNSPEC_MSA_FLOG2
54 UNSPEC_MSA_FRCP
55 UNSPEC_MSA_FRINT
56 UNSPEC_MSA_FRSQRT
57 UNSPEC_MSA_FSAF
58 UNSPEC_MSA_FSEQ
59 UNSPEC_MSA_FSLE
60 UNSPEC_MSA_FSLT
61 UNSPEC_MSA_FSNE
62 UNSPEC_MSA_FSOR
63 UNSPEC_MSA_FSUEQ
64 UNSPEC_MSA_FSULE
65 UNSPEC_MSA_FSULT
66 UNSPEC_MSA_FSUN
67 UNSPEC_MSA_FSUNE
68 UNSPEC_MSA_FTINT_S
69 UNSPEC_MSA_FTINT_U
70 UNSPEC_MSA_FTQ
71 UNSPEC_MSA_MADD_Q
72 UNSPEC_MSA_MADDR_Q
73 UNSPEC_MSA_MSUB_Q
74 UNSPEC_MSA_MSUBR_Q
75 UNSPEC_MSA_MUL_Q
76 UNSPEC_MSA_MULR_Q
77 UNSPEC_MSA_NLOC
78 UNSPEC_MSA_SAT_S
79 UNSPEC_MSA_SAT_U
80 UNSPEC_MSA_SLD
81 UNSPEC_MSA_SLDI
82 UNSPEC_MSA_SPLAT
83 UNSPEC_MSA_SPLATI
84 UNSPEC_MSA_SRAR
85 UNSPEC_MSA_SRARI
86 UNSPEC_MSA_SRLR
87 UNSPEC_MSA_SRLRI
88 UNSPEC_MSA_SUBS_S
89 UNSPEC_MSA_SUBS_U
90 UNSPEC_MSA_SUBSUU_S
91 UNSPEC_MSA_SUBSUS_U
92 UNSPEC_MSA_VSHF
93 ])
95 ;; All vector modes with 128 bits.
96 (define_mode_iterator MSA [V2DF V4SF V2DI V4SI V8HI V16QI])
98 ;; Same as MSA. Used by vcond to iterate two modes.
99 (define_mode_iterator MSA_2 [V2DF V4SF V2DI V4SI V8HI V16QI])
101 ;; Only used for splitting insert_d and copy_{u,s}.d.
102 (define_mode_iterator MSA_D [V2DI V2DF])
104 ;; Only used for copy_{u,s}.w.
105 (define_mode_iterator MSA_W [V4SI V4SF])
107 ;; Only integer modes.
108 (define_mode_iterator IMSA [V2DI V4SI V8HI V16QI])
110 ;; As IMSA but excludes V16QI.
111 (define_mode_iterator IMSA_DWH [V2DI V4SI V8HI])
113 ;; As IMSA but excludes V2DI.
114 (define_mode_iterator IMSA_WHB [V4SI V8HI V16QI])
116 ;; Only integer modes equal or larger than a word.
117 (define_mode_iterator IMSA_DW [V2DI V4SI])
119 ;; Only integer modes smaller than a word.
120 (define_mode_iterator IMSA_HB [V8HI V16QI])
122 ;; Only integer modes for fixed-point madd_q/maddr_q.
123 (define_mode_iterator IMSA_WH [V4SI V8HI])
125 ;; Only floating-point modes.
126 (define_mode_iterator FMSA [V2DF V4SF])
128 ;; Only used for immediate set shuffle elements instruction.
129 (define_mode_iterator MSA_WHB_W [V4SI V8HI V16QI V4SF])
131 ;; The attribute gives the integer vector mode with same size.
132 (define_mode_attr VIMODE
133 [(V2DF "V2DI")
134 (V4SF "V4SI")
135 (V2DI "V2DI")
136 (V4SI "V4SI")
137 (V8HI "V8HI")
138 (V16QI "V16QI")])
140 ;; The attribute gives half modes for vector modes.
141 (define_mode_attr VHMODE
142 [(V8HI "V16QI")
143 (V4SI "V8HI")
144 (V2DI "V4SI")])
146 ;; The attribute gives double modes for vector modes.
147 (define_mode_attr VDMODE
148 [(V4SI "V2DI")
149 (V8HI "V4SI")
150 (V16QI "V8HI")])
152 ;; The attribute gives half modes with same number of elements for vector modes.
153 (define_mode_attr VTRUNCMODE
154 [(V8HI "V8QI")
155 (V4SI "V4HI")
156 (V2DI "V2SI")])
158 ;; This attribute gives the mode of the result for "copy_s_b, copy_u_b" etc.
159 (define_mode_attr VRES
160 [(V2DF "DF")
161 (V4SF "SF")
162 (V2DI "DI")
163 (V4SI "SI")
164 (V8HI "SI")
165 (V16QI "SI")])
167 ;; Only used with MSA_D iterator.
168 (define_mode_attr msa_d
169 [(V2DI "reg_or_0")
170 (V2DF "register")])
172 ;; This attribute gives the integer vector mode with same size.
173 (define_mode_attr mode_i
174 [(V2DF "v2di")
175 (V4SF "v4si")
176 (V2DI "v2di")
177 (V4SI "v4si")
178 (V8HI "v8hi")
179 (V16QI "v16qi")])
181 ;; This attribute gives suffix for MSA instructions.
182 (define_mode_attr msafmt
183 [(V2DF "d")
184 (V4SF "w")
185 (V2DI "d")
186 (V4SI "w")
187 (V8HI "h")
188 (V16QI "b")])
190 ;; This attribute gives suffix for integers in VHMODE.
191 (define_mode_attr hmsafmt
192 [(V2DI "w")
193 (V4SI "h")
194 (V8HI "b")])
196 ;; This attribute gives define_insn suffix for MSA instructions that need
197 ;; distinction between integer and floating point.
198 (define_mode_attr msafmt_f
199 [(V2DF "d_f")
200 (V4SF "w_f")
201 (V2DI "d")
202 (V4SI "w")
203 (V8HI "h")
204 (V16QI "b")])
206 ;; This is used to form an immediate operand constraint using
207 ;; "const_<indeximm>_operand".
208 (define_mode_attr indeximm
209 [(V2DF "0_or_1")
210 (V4SF "0_to_3")
211 (V2DI "0_or_1")
212 (V4SI "0_to_3")
213 (V8HI "uimm3")
214 (V16QI "uimm4")])
216 ;; This attribute represents bitmask needed for vec_merge using
217 ;; "const_<bitmask>_operand".
218 (define_mode_attr bitmask
219 [(V2DF "exp_2")
220 (V4SF "exp_4")
221 (V2DI "exp_2")
222 (V4SI "exp_4")
223 (V8HI "exp_8")
224 (V16QI "exp_16")])
226 ;; This attribute is used to form an immediate operand constraint using
227 ;; "const_<bitimm>_operand".
228 (define_mode_attr bitimm
229 [(V16QI "uimm3")
230 (V8HI "uimm4")
231 (V4SI "uimm5")
232 (V2DI "uimm6")])
234 (define_expand "vec_init<mode><unitmode>"
235 [(match_operand:MSA 0 "register_operand")
236 (match_operand:MSA 1 "")]
237 "ISA_HAS_MSA"
238 {
239 mips_expand_vector_init (operands[0], operands[1]);
240 DONE;
241 })
243 ;; pckev pattern with implicit type conversion.
244 (define_insn "vec_pack_trunc_<mode>"
245 [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
246 (vec_concat:<VHMODE>
247 (truncate:<VTRUNCMODE>
248 (match_operand:IMSA_DWH 1 "register_operand" "f"))
249 (truncate:<VTRUNCMODE>
250 (match_operand:IMSA_DWH 2 "register_operand" "f"))))]
251 "ISA_HAS_MSA"
252 "pckev.<hmsafmt>\t%w0,%w2,%w1"
253 [(set_attr "type" "simd_permute")
254 (set_attr "mode" "<MODE>")])
256 (define_expand "vec_unpacks_hi_v4sf"
257 [(set (match_operand:V2DF 0 "register_operand" "=f")
258 (float_extend:V2DF
259 (vec_select:V2SF
260 (match_operand:V4SF 1 "register_operand" "f")
261 (match_dup 2))))]
262 "ISA_HAS_MSA"
263 {
264 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, true/*high_p*/);
265 })
267 (define_expand "vec_unpacks_lo_v4sf"
268 [(set (match_operand:V2DF 0 "register_operand" "=f")
269 (float_extend:V2DF
270 (vec_select:V2SF
271 (match_operand:V4SF 1 "register_operand" "f")
272 (match_dup 2))))]
273 "ISA_HAS_MSA"
274 {
275 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, false/*high_p*/);
276 })
278 (define_expand "vec_unpacks_hi_<mode>"
279 [(match_operand:<VDMODE> 0 "register_operand")
280 (match_operand:IMSA_WHB 1 "register_operand")]
281 "ISA_HAS_MSA"
282 {
283 mips_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/);
284 DONE;
285 })
287 (define_expand "vec_unpacks_lo_<mode>"
288 [(match_operand:<VDMODE> 0 "register_operand")
289 (match_operand:IMSA_WHB 1 "register_operand")]
290 "ISA_HAS_MSA"
291 {
292 mips_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/);
293 DONE;
294 })
296 (define_expand "vec_unpacku_hi_<mode>"
297 [(match_operand:<VDMODE> 0 "register_operand")
298 (match_operand:IMSA_WHB 1 "register_operand")]
299 "ISA_HAS_MSA"
300 {
301 mips_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/);
302 DONE;
303 })
305 (define_expand "vec_unpacku_lo_<mode>"
306 [(match_operand:<VDMODE> 0 "register_operand")
307 (match_operand:IMSA_WHB 1 "register_operand")]
308 "ISA_HAS_MSA"
309 {
310 mips_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/);
311 DONE;
312 })
314 (define_expand "vec_extract<mode><unitmode>"
315 [(match_operand:<UNITMODE> 0 "register_operand")
316 (match_operand:IMSA 1 "register_operand")
317 (match_operand 2 "const_<indeximm>_operand")]
318 "ISA_HAS_MSA"
319 {
320 if (<UNITMODE>mode == QImode || <UNITMODE>mode == HImode)
321 {
322 rtx dest1 = gen_reg_rtx (SImode);
323 emit_insn (gen_msa_copy_s_<msafmt> (dest1, operands[1], operands[2]));
324 emit_move_insn (operands[0],
325 gen_lowpart (<UNITMODE>mode, dest1));
326 }
327 else
328 emit_insn (gen_msa_copy_s_<msafmt> (operands[0], operands[1], operands[2]));
329 DONE;
330 })
332 (define_expand "vec_extract<mode><unitmode>"
333 [(match_operand:<UNITMODE> 0 "register_operand")
334 (match_operand:FMSA 1 "register_operand")
335 (match_operand 2 "const_<indeximm>_operand")]
336 "ISA_HAS_MSA"
337 {
338 rtx temp;
339 HOST_WIDE_INT val = INTVAL (operands[2]);
341 if (val == 0)
342 temp = operands[1];
343 else
344 {
345 /* We need to do the SLDI operation in V16QImode and adjust
346 operands[2] accordingly. */
347 rtx wd = gen_reg_rtx (V16QImode);
348 rtx ws = gen_reg_rtx (V16QImode);
349 emit_move_insn (ws, gen_rtx_SUBREG (V16QImode, operands[1], 0));
350 rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode));
351 gcc_assert (INTVAL (n) < GET_MODE_NUNITS (V16QImode));
352 emit_insn (gen_msa_sldi_b (wd, ws, ws, n));
353 temp = gen_reg_rtx (<MODE>mode);
354 emit_move_insn (temp, gen_rtx_SUBREG (<MODE>mode, wd, 0));
355 }
356 emit_insn (gen_msa_vec_extract_<msafmt_f> (operands[0], temp));
357 DONE;
358 })
360 (define_insn_and_split "msa_vec_extract_<msafmt_f>"
361 [(set (match_operand:<UNITMODE> 0 "register_operand" "=f")
362 (vec_select:<UNITMODE>
363 (match_operand:FMSA 1 "register_operand" "f")
364 (parallel [(const_int 0)])))]
365 "ISA_HAS_MSA"
366 "#"
367 "&& reload_completed"
368 [(set (match_dup 0) (match_dup 1))]
369 {
370 /* An MSA register cannot be reinterpreted as a single precision
371 register when using -mno-odd-spreg and the MSA register is
372 an odd number. */
373 if (<UNITMODE>mode == SFmode && !TARGET_ODD_SPREG
374 && (REGNO (operands[1]) & 1))
375 {
376 emit_move_insn (gen_rtx_REG (<MODE>mode, REGNO (operands[0])),
377 operands[1]);
378 operands[1] = operands[0];
379 }
380 else
381 operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
382 }
383 [(set_attr "move_type" "fmove")
384 (set_attr "mode" "<UNITMODE>")])
386 (define_expand "vec_set<mode>"
387 [(match_operand:IMSA 0 "register_operand")
388 (match_operand:<UNITMODE> 1 "reg_or_0_operand")
389 (match_operand 2 "const_<indeximm>_operand")]
390 "ISA_HAS_MSA"
391 {
392 rtx index = GEN_INT (1 << INTVAL (operands[2]));
393 emit_insn (gen_msa_insert_<msafmt> (operands[0], operands[1],
394 operands[0], index));
395 DONE;
396 })
398 (define_expand "vec_set<mode>"
399 [(match_operand:FMSA 0 "register_operand")
400 (match_operand:<UNITMODE> 1 "register_operand")
401 (match_operand 2 "const_<indeximm>_operand")]
402 "ISA_HAS_MSA"
403 {
404 rtx index = GEN_INT (1 << INTVAL (operands[2]));
405 emit_insn (gen_msa_insve_<msafmt_f>_scalar (operands[0], operands[1],
406 operands[0], index));
407 DONE;
408 })
410 (define_expand "vcondu<MSA:mode><IMSA:mode>"
411 [(match_operand:MSA 0 "register_operand")
412 (match_operand:MSA 1 "reg_or_m1_operand")
413 (match_operand:MSA 2 "reg_or_0_operand")
414 (match_operator 3 ""
415 [(match_operand:IMSA 4 "register_operand")
416 (match_operand:IMSA 5 "register_operand")])]
417 "ISA_HAS_MSA
418 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<IMSA:MODE>mode))"
419 {
420 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
421 DONE;
422 })
424 (define_expand "vcond<MSA:mode><MSA_2:mode>"
425 [(match_operand:MSA 0 "register_operand")
426 (match_operand:MSA 1 "reg_or_m1_operand")
427 (match_operand:MSA 2 "reg_or_0_operand")
428 (match_operator 3 ""
429 [(match_operand:MSA_2 4 "register_operand")
430 (match_operand:MSA_2 5 "register_operand")])]
431 "ISA_HAS_MSA
432 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<MSA_2:MODE>mode))"
433 {
434 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
435 DONE;
436 })
438 (define_insn "msa_insert_<msafmt_f>"
439 [(set (match_operand:MSA 0 "register_operand" "=f")
440 (vec_merge:MSA
441 (vec_duplicate:MSA
442 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ"))
443 (match_operand:MSA 2 "register_operand" "0")
444 (match_operand 3 "const_<bitmask>_operand" "")))]
445 "ISA_HAS_MSA"
446 {
447 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
448 return "#";
449 else
450 return "insert.<msafmt>\t%w0[%y3],%z1";
451 }
452 [(set_attr "type" "simd_insert")
453 (set_attr "mode" "<MODE>")])
455 (define_split
456 [(set (match_operand:MSA_D 0 "register_operand")
457 (vec_merge:MSA_D
458 (vec_duplicate:MSA_D
459 (match_operand:<UNITMODE> 1 "<MSA_D:msa_d>_operand"))
460 (match_operand:MSA_D 2 "register_operand")
461 (match_operand 3 "const_<bitmask>_operand")))]
462 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
463 [(const_int 0)]
464 {
465 mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]);
466 DONE;
467 })
469 (define_insn "msa_insve_<msafmt_f>"
470 [(set (match_operand:MSA 0 "register_operand" "=f")
471 (vec_merge:MSA
472 (vec_duplicate:MSA
473 (vec_select:<UNITMODE>
474 (match_operand:MSA 1 "register_operand" "f")
475 (parallel [(const_int 0)])))
476 (match_operand:MSA 2 "register_operand" "0")
477 (match_operand 3 "const_<bitmask>_operand" "")))]
478 "ISA_HAS_MSA"
479 "insve.<msafmt>\t%w0[%y3],%w1[0]"
480 [(set_attr "type" "simd_insert")
481 (set_attr "mode" "<MODE>")])
483 ;; Operand 3 is a scalar.
484 (define_insn "msa_insve_<msafmt_f>_scalar"
485 [(set (match_operand:FMSA 0 "register_operand" "=f")
486 (vec_merge:FMSA
487 (vec_duplicate:FMSA
488 (match_operand:<UNITMODE> 1 "register_operand" "f"))
489 (match_operand:FMSA 2 "register_operand" "0")
490 (match_operand 3 "const_<bitmask>_operand" "")))]
491 "ISA_HAS_MSA"
492 "insve.<msafmt>\t%w0[%y3],%w1[0]"
493 [(set_attr "type" "simd_insert")
494 (set_attr "mode" "<MODE>")])
496 (define_insn "msa_copy_<su>_<msafmt>"
497 [(set (match_operand:<VRES> 0 "register_operand" "=d")
498 (any_extend:<VRES>
499 (vec_select:<UNITMODE>
500 (match_operand:IMSA_HB 1 "register_operand" "f")
501 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
502 "ISA_HAS_MSA"
503 "copy_<su>.<msafmt>\t%0,%w1[%2]"
504 [(set_attr "type" "simd_copy")
505 (set_attr "mode" "<MODE>")])
507 (define_insn "msa_copy_u_w"
508 [(set (match_operand:DI 0 "register_operand" "=d")
509 (zero_extend:DI
510 (vec_select:SI
511 (match_operand:V4SI 1 "register_operand" "f")
512 (parallel [(match_operand 2 "const_0_to_3_operand" "")]))))]
513 "ISA_HAS_MSA && TARGET_64BIT"
514 "copy_u.w\t%0,%w1[%2]"
515 [(set_attr "type" "simd_copy")
516 (set_attr "mode" "V4SI")])
518 (define_insn "msa_copy_s_<msafmt_f>_64bit"
519 [(set (match_operand:DI 0 "register_operand" "=d")
520 (sign_extend:DI
521 (vec_select:<UNITMODE>
522 (match_operand:MSA_W 1 "register_operand" "f")
523 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
524 "ISA_HAS_MSA && TARGET_64BIT"
525 "copy_s.<msafmt>\t%0,%w1[%2]"
526 [(set_attr "type" "simd_copy")
527 (set_attr "mode" "<MODE>")])
529 (define_insn "msa_copy_s_<msafmt_f>"
530 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d")
531 (vec_select:<UNITMODE>
532 (match_operand:MSA_W 1 "register_operand" "f")
533 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
534 "ISA_HAS_MSA"
535 "copy_s.<msafmt>\t%0,%w1[%2]"
536 [(set_attr "type" "simd_copy")
537 (set_attr "mode" "<MODE>")])
539 (define_insn_and_split "msa_copy_s_<msafmt_f>"
540 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d")
541 (vec_select:<UNITMODE>
542 (match_operand:MSA_D 1 "register_operand" "f")
543 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
544 "ISA_HAS_MSA"
545 {
546 if (TARGET_64BIT)
547 return "copy_s.<msafmt>\t%0,%w1[%2]";
548 else
549 return "#";
550 }
551 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
552 [(const_int 0)]
553 {
554 mips_split_msa_copy_d (operands[0], operands[1], operands[2],
555 gen_msa_copy_s_w);
556 DONE;
557 }
558 [(set_attr "type" "simd_copy")
559 (set_attr "mode" "<MODE>")])
561 (define_expand "abs<mode>2"
562 [(match_operand:IMSA 0 "register_operand" "=f")
563 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))]
564 "ISA_HAS_MSA"
565 {
566 rtx reg = gen_reg_rtx (<MODE>mode);
567 emit_move_insn (reg, CONST0_RTX (<MODE>mode));
568 emit_insn (gen_msa_add_a_<msafmt> (operands[0], operands[1], reg));
569 DONE;
570 })
572 (define_expand "neg<mode>2"
573 [(set (match_operand:MSA 0 "register_operand")
574 (minus:MSA (match_dup 2)
575 (match_operand:MSA 1 "register_operand")))]
576 "ISA_HAS_MSA"
577 {
578 rtx reg = gen_reg_rtx (<MODE>mode);
579 emit_move_insn (reg, CONST0_RTX (<MODE>mode));
580 operands[2] = reg;
581 })
583 (define_expand "msa_ldi<mode>"
584 [(match_operand:IMSA 0 "register_operand")
585 (match_operand 1 "const_imm10_operand")]
586 "ISA_HAS_MSA"
587 {
588 if (<MODE>mode == V16QImode)
589 operands[1] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]),
590 <UNITMODE>mode));
591 emit_move_insn (operands[0],
592 mips_gen_const_int_vector (<MODE>mode, INTVAL (operands[1])));
593 DONE;
594 })
596 (define_insn "vec_perm<mode>"
597 [(set (match_operand:MSA 0 "register_operand" "=f")
598 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f")
599 (match_operand:MSA 2 "register_operand" "f")
600 (match_operand:<VIMODE> 3 "register_operand" "0")]
601 UNSPEC_MSA_VSHF))]
602 "ISA_HAS_MSA"
603 "vshf.<msafmt>\t%w0,%w2,%w1"
604 [(set_attr "type" "simd_sld")
605 (set_attr "mode" "<MODE>")])
607 (define_expand "mov<mode>"
608 [(set (match_operand:MSA 0)
609 (match_operand:MSA 1))]
610 "ISA_HAS_MSA"
611 {
612 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
613 DONE;
614 })
616 (define_expand "movmisalign<mode>"
617 [(set (match_operand:MSA 0)
618 (match_operand:MSA 1))]
619 "ISA_HAS_MSA"
620 {
621 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
622 DONE;
623 })
625 ;; 128-bit MSA modes can only exist in MSA registers or memory. An exception
626 ;; is allowing MSA modes for GP registers for arguments and return values.
627 (define_insn "mov<mode>_msa"
628 [(set (match_operand:MSA 0 "nonimmediate_operand" "=f,f,R,*d,*f")
629 (match_operand:MSA 1 "move_operand" "fYGYI,R,f,*f,*d"))]
630 "ISA_HAS_MSA"
631 { return mips_output_move (operands[0], operands[1]); }
632 [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert")
633 (set_attr "mode" "<MODE>")])
635 (define_split
636 [(set (match_operand:MSA 0 "nonimmediate_operand")
637 (match_operand:MSA 1 "move_operand"))]
638 "reload_completed && ISA_HAS_MSA
639 && mips_split_move_insn_p (operands[0], operands[1], insn)"
640 [(const_int 0)]
641 {
642 mips_split_move_insn (operands[0], operands[1], curr_insn);
643 DONE;
644 })
646 ;; Offset load
647 (define_expand "msa_ld_<msafmt_f>"
648 [(match_operand:MSA 0 "register_operand")
649 (match_operand 1 "pmode_register_operand")
650 (match_operand 2 "aq10<msafmt>_operand")]
651 "ISA_HAS_MSA"
652 {
653 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
654 INTVAL (operands[2]));
655 mips_emit_move (operands[0], gen_rtx_MEM (<MODE>mode, addr));
656 DONE;
657 })
659 ;; Offset store
660 (define_expand "msa_st_<msafmt_f>"
661 [(match_operand:MSA 0 "register_operand")
662 (match_operand 1 "pmode_register_operand")
663 (match_operand 2 "aq10<msafmt>_operand")]
664 "ISA_HAS_MSA"
665 {
666 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
667 INTVAL (operands[2]));
668 mips_emit_move (gen_rtx_MEM (<MODE>mode, addr), operands[0]);
669 DONE;
670 })
672 ;; Integer operations
673 (define_insn "add<mode>3"
674 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
675 (plus:IMSA
676 (match_operand:IMSA 1 "register_operand" "f,f,f")
677 (match_operand:IMSA 2 "reg_or_vector_same_ximm5_operand" "f,Unv5,Uuv5")))]
678 "ISA_HAS_MSA"
679 {
680 switch (which_alternative)
681 {
682 case 0:
683 return "addv.<msafmt>\t%w0,%w1,%w2";
684 case 1:
685 {
686 HOST_WIDE_INT val = INTVAL (CONST_VECTOR_ELT (operands[2], 0));
688 operands[2] = GEN_INT (-val);
689 return "subvi.<msafmt>\t%w0,%w1,%d2";
690 }
691 case 2:
692 return "addvi.<msafmt>\t%w0,%w1,%E2";
693 default:
694 gcc_unreachable ();
695 }
696 }
697 [(set_attr "alu_type" "simd_add")
698 (set_attr "type" "simd_int_arith")
699 (set_attr "mode" "<MODE>")])
701 (define_insn "sub<mode>3"
702 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
703 (minus:IMSA
704 (match_operand:IMSA 1 "register_operand" "f,f")
705 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
706 "ISA_HAS_MSA"
707 "@
708 subv.<msafmt>\t%w0,%w1,%w2
709 subvi.<msafmt>\t%w0,%w1,%E2"
710 [(set_attr "alu_type" "simd_add")
711 (set_attr "type" "simd_int_arith")
712 (set_attr "mode" "<MODE>")])
714 (define_insn "mul<mode>3"
715 [(set (match_operand:IMSA 0 "register_operand" "=f")
716 (mult:IMSA (match_operand:IMSA 1 "register_operand" "f")
717 (match_operand:IMSA 2 "register_operand" "f")))]
718 "ISA_HAS_MSA"
719 "mulv.<msafmt>\t%w0,%w1,%w2"
720 [(set_attr "type" "simd_mul")
721 (set_attr "mode" "<MODE>")])
723 (define_insn "msa_maddv_<msafmt>"
724 [(set (match_operand:IMSA 0 "register_operand" "=f")
725 (plus:IMSA (mult:IMSA (match_operand:IMSA 1 "register_operand" "f")
726 (match_operand:IMSA 2 "register_operand" "f"))
727 (match_operand:IMSA 3 "register_operand" "0")))]
728 "ISA_HAS_MSA"
729 "maddv.<msafmt>\t%w0,%w1,%w2"
730 [(set_attr "type" "simd_mul")
731 (set_attr "mode" "<MODE>")])
733 (define_insn "msa_msubv_<msafmt>"
734 [(set (match_operand:IMSA 0 "register_operand" "=f")
735 (minus:IMSA (match_operand:IMSA 1 "register_operand" "0")
736 (mult:IMSA (match_operand:IMSA 2 "register_operand" "f")
737 (match_operand:IMSA 3 "register_operand" "f"))))]
738 "ISA_HAS_MSA"
739 "msubv.<msafmt>\t%w0,%w2,%w3"
740 [(set_attr "type" "simd_mul")
741 (set_attr "mode" "<MODE>")])
743 (define_insn "div<mode>3"
744 [(set (match_operand:IMSA 0 "register_operand" "=f")
745 (div:IMSA (match_operand:IMSA 1 "register_operand" "f")
746 (match_operand:IMSA 2 "register_operand" "f")))]
747 "ISA_HAS_MSA"
748 { return mips_msa_output_division ("div_s.<msafmt>\t%w0,%w1,%w2", operands); }
749 [(set_attr "type" "simd_div")
750 (set_attr "mode" "<MODE>")])
752 (define_insn "udiv<mode>3"
753 [(set (match_operand:IMSA 0 "register_operand" "=f")
754 (udiv:IMSA (match_operand:IMSA 1 "register_operand" "f")
755 (match_operand:IMSA 2 "register_operand" "f")))]
756 "ISA_HAS_MSA"
757 { return mips_msa_output_division ("div_u.<msafmt>\t%w0,%w1,%w2", operands); }
758 [(set_attr "type" "simd_div")
759 (set_attr "mode" "<MODE>")])
761 (define_insn "mod<mode>3"
762 [(set (match_operand:IMSA 0 "register_operand" "=f")
763 (mod:IMSA (match_operand:IMSA 1 "register_operand" "f")
764 (match_operand:IMSA 2 "register_operand" "f")))]
765 "ISA_HAS_MSA"
766 { return mips_msa_output_division ("mod_s.<msafmt>\t%w0,%w1,%w2", operands); }
767 [(set_attr "type" "simd_div")
768 (set_attr "mode" "<MODE>")])
770 (define_insn "umod<mode>3"
771 [(set (match_operand:IMSA 0 "register_operand" "=f")
772 (umod:IMSA (match_operand:IMSA 1 "register_operand" "f")
773 (match_operand:IMSA 2 "register_operand" "f")))]
774 "ISA_HAS_MSA"
775 { return mips_msa_output_division ("mod_u.<msafmt>\t%w0,%w1,%w2", operands); }
776 [(set_attr "type" "simd_div")
777 (set_attr "mode" "<MODE>")])
779 (define_insn "xor<mode>3"
780 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
781 (xor:IMSA
782 (match_operand:IMSA 1 "register_operand" "f,f,f")
783 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
784 "ISA_HAS_MSA"
785 "@
786 xor.v\t%w0,%w1,%w2
787 bnegi.%v0\t%w0,%w1,%V2
788 xori.b\t%w0,%w1,%B2"
789 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
790 (set_attr "mode" "<MODE>")])
792 (define_insn "ior<mode>3"
793 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
794 (ior:IMSA
795 (match_operand:IMSA 1 "register_operand" "f,f,f")
796 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
797 "ISA_HAS_MSA"
798 "@
799 or.v\t%w0,%w1,%w2
800 bseti.%v0\t%w0,%w1,%V2
801 ori.b\t%w0,%w1,%B2"
802 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
803 (set_attr "mode" "<MODE>")])
805 (define_insn "and<mode>3"
806 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
807 (and:IMSA
808 (match_operand:IMSA 1 "register_operand" "f,f,f")
809 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
810 "ISA_HAS_MSA"
811 {
812 switch (which_alternative)
813 {
814 case 0:
815 return "and.v\t%w0,%w1,%w2";
816 case 1:
817 {
818 rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
819 unsigned HOST_WIDE_INT val = ~UINTVAL (elt0);
820 operands[2] = mips_gen_const_int_vector (<MODE>mode, val & (-val));
821 return "bclri.%v0\t%w0,%w1,%V2";
822 }
823 case 2:
824 return "andi.b\t%w0,%w1,%B2";
825 default:
826 gcc_unreachable ();
827 }
828 }
829 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
830 (set_attr "mode" "<MODE>")])
832 (define_insn "one_cmpl<mode>2"
833 [(set (match_operand:IMSA 0 "register_operand" "=f")
834 (not:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
835 "ISA_HAS_MSA"
836 "nor.v\t%w0,%w1,%w1"
837 [(set_attr "type" "simd_logic")
838 (set_attr "mode" "TI")])
840 (define_insn "vlshr<mode>3"
841 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
842 (lshiftrt:IMSA
843 (match_operand:IMSA 1 "register_operand" "f,f")
844 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
845 "ISA_HAS_MSA"
846 "@
847 srl.<msafmt>\t%w0,%w1,%w2
848 srli.<msafmt>\t%w0,%w1,%E2"
849 [(set_attr "type" "simd_shift")
850 (set_attr "mode" "<MODE>")])
852 (define_insn "vashr<mode>3"
853 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
854 (ashiftrt:IMSA
855 (match_operand:IMSA 1 "register_operand" "f,f")
856 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
857 "ISA_HAS_MSA"
858 "@
859 sra.<msafmt>\t%w0,%w1,%w2
860 srai.<msafmt>\t%w0,%w1,%E2"
861 [(set_attr "type" "simd_shift")
862 (set_attr "mode" "<MODE>")])
864 (define_insn "vashl<mode>3"
865 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
866 (ashift:IMSA
867 (match_operand:IMSA 1 "register_operand" "f,f")
868 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
869 "ISA_HAS_MSA"
870 "@
871 sll.<msafmt>\t%w0,%w1,%w2
872 slli.<msafmt>\t%w0,%w1,%E2"
873 [(set_attr "type" "simd_shift")
874 (set_attr "mode" "<MODE>")])
876 ;; Floating-point operations
877 (define_insn "add<mode>3"
878 [(set (match_operand:FMSA 0 "register_operand" "=f")
879 (plus:FMSA (match_operand:FMSA 1 "register_operand" "f")
880 (match_operand:FMSA 2 "register_operand" "f")))]
881 "ISA_HAS_MSA"
882 "fadd.<msafmt>\t%w0,%w1,%w2"
883 [(set_attr "type" "simd_fadd")
884 (set_attr "mode" "<MODE>")])
886 (define_insn "sub<mode>3"
887 [(set (match_operand:FMSA 0 "register_operand" "=f")
888 (minus:FMSA (match_operand:FMSA 1 "register_operand" "f")
889 (match_operand:FMSA 2 "register_operand" "f")))]
890 "ISA_HAS_MSA"
891 "fsub.<msafmt>\t%w0,%w1,%w2"
892 [(set_attr "type" "simd_fadd")
893 (set_attr "mode" "<MODE>")])
895 (define_insn "mul<mode>3"
896 [(set (match_operand:FMSA 0 "register_operand" "=f")
897 (mult:FMSA (match_operand:FMSA 1 "register_operand" "f")
898 (match_operand:FMSA 2 "register_operand" "f")))]
899 "ISA_HAS_MSA"
900 "fmul.<msafmt>\t%w0,%w1,%w2"
901 [(set_attr "type" "simd_fmul")
902 (set_attr "mode" "<MODE>")])
904 (define_insn "div<mode>3"
905 [(set (match_operand:FMSA 0 "register_operand" "=f")
906 (div:FMSA (match_operand:FMSA 1 "register_operand" "f")
907 (match_operand:FMSA 2 "register_operand" "f")))]
908 "ISA_HAS_MSA"
909 "fdiv.<msafmt>\t%w0,%w1,%w2"
910 [(set_attr "type" "simd_fdiv")
911 (set_attr "mode" "<MODE>")])
913 (define_insn "fma<mode>4"
914 [(set (match_operand:FMSA 0 "register_operand" "=f")
915 (fma:FMSA (match_operand:FMSA 1 "register_operand" "f")
916 (match_operand:FMSA 2 "register_operand" "f")
917 (match_operand:FMSA 3 "register_operand" "0")))]
918 "ISA_HAS_MSA"
919 "fmadd.<msafmt>\t%w0,%w1,%w2"
920 [(set_attr "type" "simd_fmadd")
921 (set_attr "mode" "<MODE>")])
923 (define_insn "fnma<mode>4"
924 [(set (match_operand:FMSA 0 "register_operand" "=f")
925 (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "register_operand" "f"))
926 (match_operand:FMSA 2 "register_operand" "f")
927 (match_operand:FMSA 3 "register_operand" "0")))]
928 "ISA_HAS_MSA"
929 "fmsub.<msafmt>\t%w0,%w1,%w2"
930 [(set_attr "type" "simd_fmadd")
931 (set_attr "mode" "<MODE>")])
933 (define_insn "sqrt<mode>2"
934 [(set (match_operand:FMSA 0 "register_operand" "=f")
935 (sqrt:FMSA (match_operand:FMSA 1 "register_operand" "f")))]
936 "ISA_HAS_MSA"
937 "fsqrt.<msafmt>\t%w0,%w1"
938 [(set_attr "type" "simd_fdiv")
939 (set_attr "mode" "<MODE>")])
941 ;; Built-in functions
942 (define_insn "msa_add_a_<msafmt>"
943 [(set (match_operand:IMSA 0 "register_operand" "=f")
944 (plus:IMSA (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
945 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))]
946 "ISA_HAS_MSA"
947 "add_a.<msafmt>\t%w0,%w1,%w2"
948 [(set_attr "type" "simd_int_arith")
949 (set_attr "mode" "<MODE>")])
951 (define_insn "msa_adds_a_<msafmt>"
952 [(set (match_operand:IMSA 0 "register_operand" "=f")
953 (ss_plus:IMSA
954 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
955 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))]
956 "ISA_HAS_MSA"
957 "adds_a.<msafmt>\t%w0,%w1,%w2"
958 [(set_attr "type" "simd_int_arith")
959 (set_attr "mode" "<MODE>")])
961 (define_insn "ssadd<mode>3"
962 [(set (match_operand:IMSA 0 "register_operand" "=f")
963 (ss_plus:IMSA (match_operand:IMSA 1 "register_operand" "f")
964 (match_operand:IMSA 2 "register_operand" "f")))]
965 "ISA_HAS_MSA"
966 "adds_s.<msafmt>\t%w0,%w1,%w2"
967 [(set_attr "type" "simd_int_arith")
968 (set_attr "mode" "<MODE>")])
970 (define_insn "usadd<mode>3"
971 [(set (match_operand:IMSA 0 "register_operand" "=f")
972 (us_plus:IMSA (match_operand:IMSA 1 "register_operand" "f")
973 (match_operand:IMSA 2 "register_operand" "f")))]
974 "ISA_HAS_MSA"
975 "adds_u.<msafmt>\t%w0,%w1,%w2"
976 [(set_attr "type" "simd_int_arith")
977 (set_attr "mode" "<MODE>")])
979 (define_insn "msa_asub_s_<msafmt>"
980 [(set (match_operand:IMSA 0 "register_operand" "=f")
981 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
982 (match_operand:IMSA 2 "register_operand" "f")]
983 UNSPEC_MSA_ASUB_S))]
984 "ISA_HAS_MSA"
985 "asub_s.<msafmt>\t%w0,%w1,%w2"
986 [(set_attr "type" "simd_int_arith")
987 (set_attr "mode" "<MODE>")])
989 (define_insn "msa_asub_u_<msafmt>"
990 [(set (match_operand:IMSA 0 "register_operand" "=f")
991 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
992 (match_operand:IMSA 2 "register_operand" "f")]
993 UNSPEC_MSA_ASUB_U))]
994 "ISA_HAS_MSA"
995 "asub_u.<msafmt>\t%w0,%w1,%w2"
996 [(set_attr "type" "simd_int_arith")
997 (set_attr "mode" "<MODE>")])
999 (define_insn "msa_ave_s_<msafmt>"
1000 [(set (match_operand:IMSA 0 "register_operand" "=f")
1001 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1002 (match_operand:IMSA 2 "register_operand" "f")]
1003 UNSPEC_MSA_AVE_S))]
1004 "ISA_HAS_MSA"
1005 "ave_s.<msafmt>\t%w0,%w1,%w2"
1006 [(set_attr "type" "simd_int_arith")
1007 (set_attr "mode" "<MODE>")])
1009 (define_insn "msa_ave_u_<msafmt>"
1010 [(set (match_operand:IMSA 0 "register_operand" "=f")
1011 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1012 (match_operand:IMSA 2 "register_operand" "f")]
1013 UNSPEC_MSA_AVE_U))]
1014 "ISA_HAS_MSA"
1015 "ave_u.<msafmt>\t%w0,%w1,%w2"
1016 [(set_attr "type" "simd_int_arith")
1017 (set_attr "mode" "<MODE>")])
1019 (define_insn "msa_aver_s_<msafmt>"
1020 [(set (match_operand:IMSA 0 "register_operand" "=f")
1021 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1022 (match_operand:IMSA 2 "register_operand" "f")]
1023 UNSPEC_MSA_AVER_S))]
1024 "ISA_HAS_MSA"
1025 "aver_s.<msafmt>\t%w0,%w1,%w2"
1026 [(set_attr "type" "simd_int_arith")
1027 (set_attr "mode" "<MODE>")])
1029 (define_insn "msa_aver_u_<msafmt>"
1030 [(set (match_operand:IMSA 0 "register_operand" "=f")
1031 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1032 (match_operand:IMSA 2 "register_operand" "f")]
1033 UNSPEC_MSA_AVER_U))]
1034 "ISA_HAS_MSA"
1035 "aver_u.<msafmt>\t%w0,%w1,%w2"
1036 [(set_attr "type" "simd_int_arith")
1037 (set_attr "mode" "<MODE>")])
1039 (define_insn "msa_bclr_<msafmt>"
1040 [(set (match_operand:IMSA 0 "register_operand" "=f")
1041 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1042 (match_operand:IMSA 2 "register_operand" "f")]
1043 UNSPEC_MSA_BCLR))]
1044 "ISA_HAS_MSA"
1045 "bclr.<msafmt>\t%w0,%w1,%w2"
1046 [(set_attr "type" "simd_bit")
1047 (set_attr "mode" "<MODE>")])
1049 (define_insn "msa_bclri_<msafmt>"
1050 [(set (match_operand:IMSA 0 "register_operand" "=f")
1051 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1052 (match_operand 2 "const_<bitimm>_operand" "")]
1053 UNSPEC_MSA_BCLRI))]
1054 "ISA_HAS_MSA"
1055 "bclri.<msafmt>\t%w0,%w1,%2"
1056 [(set_attr "type" "simd_bit")
1057 (set_attr "mode" "<MODE>")])
1059 (define_insn "msa_binsl_<msafmt>"
1060 [(set (match_operand:IMSA 0 "register_operand" "=f")
1061 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1062 (match_operand:IMSA 2 "register_operand" "f")
1063 (match_operand:IMSA 3 "register_operand" "f")]
1064 UNSPEC_MSA_BINSL))]
1065 "ISA_HAS_MSA"
1066 "binsl.<msafmt>\t%w0,%w2,%w3"
1067 [(set_attr "type" "simd_bitins")
1068 (set_attr "mode" "<MODE>")])
1070 (define_insn "msa_binsli_<msafmt>"
1071 [(set (match_operand:IMSA 0 "register_operand" "=f")
1072 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1073 (match_operand:IMSA 2 "register_operand" "f")
1074 (match_operand 3 "const_<bitimm>_operand" "")]
1075 UNSPEC_MSA_BINSLI))]
1076 "ISA_HAS_MSA"
1077 "binsli.<msafmt>\t%w0,%w2,%3"
1078 [(set_attr "type" "simd_bitins")
1079 (set_attr "mode" "<MODE>")])
1081 (define_insn "msa_binsr_<msafmt>"
1082 [(set (match_operand:IMSA 0 "register_operand" "=f")
1083 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1084 (match_operand:IMSA 2 "register_operand" "f")
1085 (match_operand:IMSA 3 "register_operand" "f")]
1086 UNSPEC_MSA_BINSR))]
1087 "ISA_HAS_MSA"
1088 "binsr.<msafmt>\t%w0,%w2,%w3"
1089 [(set_attr "type" "simd_bitins")
1090 (set_attr "mode" "<MODE>")])
1092 (define_insn "msa_binsri_<msafmt>"
1093 [(set (match_operand:IMSA 0 "register_operand" "=f")
1094 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1095 (match_operand:IMSA 2 "register_operand" "f")
1096 (match_operand 3 "const_<bitimm>_operand" "")]
1097 UNSPEC_MSA_BINSRI))]
1098 "ISA_HAS_MSA"
1099 "binsri.<msafmt>\t%w0,%w2,%3"
1100 [(set_attr "type" "simd_bitins")
1101 (set_attr "mode" "<MODE>")])
1103 (define_insn "msa_bmnz_<msafmt>"
1104 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1105 (ior:IMSA (and:IMSA (match_operand:IMSA 2 "register_operand" "f,f")
1106 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))
1107 (and:IMSA (not:IMSA (match_dup 3))
1108 (match_operand:IMSA 1 "register_operand" "0,0"))))]
1109 "ISA_HAS_MSA"
1110 "@
1111 bmnz.v\t%w0,%w2,%w3
1112 bmnzi.b\t%w0,%w2,%B3"
1113 [(set_attr "type" "simd_bitmov")
1114 (set_attr "mode" "<MODE>")])
1116 (define_insn "msa_bmz_<msafmt>"
1117 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1118 (ior:IMSA (and:IMSA (not:IMSA
1119 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))
1120 (match_operand:IMSA 2 "register_operand" "f,f"))
1121 (and:IMSA (match_operand:IMSA 1 "register_operand" "0,0")
1122 (match_dup 3))))]
1123 "ISA_HAS_MSA"
1124 "@
1125 bmz.v\t%w0,%w2,%w3
1126 bmzi.b\t%w0,%w2,%B3"
1127 [(set_attr "type" "simd_bitmov")
1128 (set_attr "mode" "<MODE>")])
1130 (define_insn "msa_bneg_<msafmt>"
1131 [(set (match_operand:IMSA 0 "register_operand" "=f")
1132 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1133 (match_operand:IMSA 2 "register_operand" "f")]
1134 UNSPEC_MSA_BNEG))]
1135 "ISA_HAS_MSA"
1136 "bneg.<msafmt>\t%w0,%w1,%w2"
1137 [(set_attr "type" "simd_bit")
1138 (set_attr "mode" "<MODE>")])
1140 (define_insn "msa_bnegi_<msafmt>"
1141 [(set (match_operand:IMSA 0 "register_operand" "=f")
1142 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1143 (match_operand 2 "const_msa_branch_operand" "")]
1144 UNSPEC_MSA_BNEGI))]
1145 "ISA_HAS_MSA"
1146 "bnegi.<msafmt>\t%w0,%w1,%2"
1147 [(set_attr "type" "simd_bit")
1148 (set_attr "mode" "<MODE>")])
1150 (define_insn "msa_bsel_<msafmt>"
1151 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1152 (ior:IMSA (and:IMSA (not:IMSA
1153 (match_operand:IMSA 1 "register_operand" "0,0"))
1154 (match_operand:IMSA 2 "register_operand" "f,f"))
1155 (and:IMSA (match_dup 1)
1156 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))))]
1157 "ISA_HAS_MSA"
1158 "@
1159 bsel.v\t%w0,%w2,%w3
1160 bseli.b\t%w0,%w2,%B3"
1161 [(set_attr "type" "simd_bitmov")
1162 (set_attr "mode" "<MODE>")])
1164 (define_insn "msa_bset_<msafmt>"
1165 [(set (match_operand:IMSA 0 "register_operand" "=f")
1166 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1167 (match_operand:IMSA 2 "register_operand" "f")]
1168 UNSPEC_MSA_BSET))]
1169 "ISA_HAS_MSA"
1170 "bset.<msafmt>\t%w0,%w1,%w2"
1171 [(set_attr "type" "simd_bit")
1172 (set_attr "mode" "<MODE>")])
1174 (define_insn "msa_bseti_<msafmt>"
1175 [(set (match_operand:IMSA 0 "register_operand" "=f")
1176 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1177 (match_operand 2 "const_<bitimm>_operand" "")]
1178 UNSPEC_MSA_BSETI))]
1179 "ISA_HAS_MSA"
1180 "bseti.<msafmt>\t%w0,%w1,%2"
1181 [(set_attr "type" "simd_bit")
1182 (set_attr "mode" "<MODE>")])
1184 (define_code_iterator ICC [eq le leu lt ltu])
1186 (define_code_attr icc
1187 [(eq "eq")
1188 (le "le_s")
1189 (leu "le_u")
1190 (lt "lt_s")
1191 (ltu "lt_u")])
1193 (define_code_attr icci
1194 [(eq "eqi")
1195 (le "lei_s")
1196 (leu "lei_u")
1197 (lt "lti_s")
1198 (ltu "lti_u")])
1200 (define_code_attr cmpi
1201 [(eq "s")
1202 (le "s")
1203 (leu "u")
1204 (lt "s")
1205 (ltu "u")])
1207 (define_insn "msa_c<ICC:icc>_<IMSA:msafmt>"
1208 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1209 (ICC:IMSA
1210 (match_operand:IMSA 1 "register_operand" "f,f")
1211 (match_operand:IMSA 2 "reg_or_vector_same_<ICC:cmpi>imm5_operand" "f,U<ICC:cmpi>v5")))]
1212 "ISA_HAS_MSA"
1213 "@
1214 c<ICC:icc>.<IMSA:msafmt>\t%w0,%w1,%w2
1215 c<ICC:icci>.<IMSA:msafmt>\t%w0,%w1,%E2"
1216 [(set_attr "type" "simd_int_arith")
1217 (set_attr "mode" "<MODE>")])
1219 (define_insn "msa_dotp_<su>_d"
1220 [(set (match_operand:V2DI 0 "register_operand" "=f")
1221 (plus:V2DI
1222 (mult:V2DI
1223 (any_extend:V2DI
1224 (vec_select:V2SI
1225 (match_operand:V4SI 1 "register_operand" "%f")
1226 (parallel [(const_int 0) (const_int 2)])))
1227 (any_extend:V2DI
1228 (vec_select:V2SI
1229 (match_operand:V4SI 2 "register_operand" "f")
1230 (parallel [(const_int 0) (const_int 2)]))))
1231 (mult:V2DI
1232 (any_extend:V2DI
1233 (vec_select:V2SI (match_dup 1)
1234 (parallel [(const_int 1) (const_int 3)])))
1235 (any_extend:V2DI
1236 (vec_select:V2SI (match_dup 2)
1237 (parallel [(const_int 1) (const_int 3)]))))))]
1238 "ISA_HAS_MSA"
1239 "dotp_<su>.d\t%w0,%w1,%w2"
1240 [(set_attr "type" "simd_mul")
1241 (set_attr "mode" "V2DI")])
1243 (define_insn "msa_dotp_<su>_w"
1244 [(set (match_operand:V4SI 0 "register_operand" "=f")
1245 (plus:V4SI
1246 (mult:V4SI
1247 (any_extend:V4SI
1248 (vec_select:V4HI
1249 (match_operand:V8HI 1 "register_operand" "%f")
1250 (parallel [(const_int 0) (const_int 2)
1251 (const_int 4) (const_int 6)])))
1252 (any_extend:V4SI
1253 (vec_select:V4HI
1254 (match_operand:V8HI 2 "register_operand" "f")
1255 (parallel [(const_int 0) (const_int 2)
1256 (const_int 4) (const_int 6)]))))
1257 (mult:V4SI
1258 (any_extend:V4SI
1259 (vec_select:V4HI (match_dup 1)
1260 (parallel [(const_int 1) (const_int 3)
1261 (const_int 5) (const_int 7)])))
1262 (any_extend:V4SI
1263 (vec_select:V4HI (match_dup 2)
1264 (parallel [(const_int 1) (const_int 3)
1265 (const_int 5) (const_int 7)]))))))]
1266 "ISA_HAS_MSA"
1267 "dotp_<su>.w\t%w0,%w1,%w2"
1268 [(set_attr "type" "simd_mul")
1269 (set_attr "mode" "V4SI")])
1271 (define_insn "msa_dotp_<su>_h"
1272 [(set (match_operand:V8HI 0 "register_operand" "=f")
1273 (plus:V8HI
1274 (mult:V8HI
1275 (any_extend:V8HI
1276 (vec_select:V8QI
1277 (match_operand:V16QI 1 "register_operand" "%f")
1278 (parallel [(const_int 0) (const_int 2)
1279 (const_int 4) (const_int 6)
1280 (const_int 8) (const_int 10)
1281 (const_int 12) (const_int 14)])))
1282 (any_extend:V8HI
1283 (vec_select:V8QI
1284 (match_operand:V16QI 2 "register_operand" "f")
1285 (parallel [(const_int 0) (const_int 2)
1286 (const_int 4) (const_int 6)
1287 (const_int 8) (const_int 10)
1288 (const_int 12) (const_int 14)]))))
1289 (mult:V8HI
1290 (any_extend:V8HI
1291 (vec_select:V8QI (match_dup 1)
1292 (parallel [(const_int 1) (const_int 3)
1293 (const_int 5) (const_int 7)
1294 (const_int 9) (const_int 11)
1295 (const_int 13) (const_int 15)])))
1296 (any_extend:V8HI
1297 (vec_select:V8QI (match_dup 2)
1298 (parallel [(const_int 1) (const_int 3)
1299 (const_int 5) (const_int 7)
1300 (const_int 9) (const_int 11)
1301 (const_int 13) (const_int 15)]))))))]
1302 "ISA_HAS_MSA"
1303 "dotp_<su>.h\t%w0,%w1,%w2"
1304 [(set_attr "type" "simd_mul")
1305 (set_attr "mode" "V8HI")])
1307 (define_insn "msa_dpadd_<su>_d"
1308 [(set (match_operand:V2DI 0 "register_operand" "=f")
1309 (plus:V2DI
1310 (plus:V2DI
1311 (mult:V2DI
1312 (any_extend:V2DI
1313 (vec_select:V2SI
1314 (match_operand:V4SI 2 "register_operand" "%f")
1315 (parallel [(const_int 0) (const_int 2)])))
1316 (any_extend:V2DI
1317 (vec_select:V2SI
1318 (match_operand:V4SI 3 "register_operand" "f")
1319 (parallel [(const_int 0) (const_int 2)]))))
1320 (mult:V2DI
1321 (any_extend:V2DI
1322 (vec_select:V2SI (match_dup 2)
1323 (parallel [(const_int 1) (const_int 3)])))
1324 (any_extend:V2DI
1325 (vec_select:V2SI (match_dup 3)
1326 (parallel [(const_int 1) (const_int 3)])))))
1327 (match_operand:V2DI 1 "register_operand" "0")))]
1328 "ISA_HAS_MSA"
1329 "dpadd_<su>.d\t%w0,%w2,%w3"
1330 [(set_attr "type" "simd_mul")
1331 (set_attr "mode" "V2DI")])
1333 (define_insn "msa_dpadd_<su>_w"
1334 [(set (match_operand:V4SI 0 "register_operand" "=f")
1335 (plus:V4SI
1336 (plus:V4SI
1337 (mult:V4SI
1338 (any_extend:V4SI
1339 (vec_select:V4HI
1340 (match_operand:V8HI 2 "register_operand" "%f")
1341 (parallel [(const_int 0) (const_int 2)
1342 (const_int 4) (const_int 6)])))
1343 (any_extend:V4SI
1344 (vec_select:V4HI
1345 (match_operand:V8HI 3 "register_operand" "f")
1346 (parallel [(const_int 0) (const_int 2)
1347 (const_int 4) (const_int 6)]))))
1348 (mult:V4SI
1349 (any_extend:V4SI
1350 (vec_select:V4HI (match_dup 2)
1351 (parallel [(const_int 1) (const_int 3)
1352 (const_int 5) (const_int 7)])))
1353 (any_extend:V4SI
1354 (vec_select:V4HI (match_dup 3)
1355 (parallel [(const_int 1) (const_int 3)
1356 (const_int 5) (const_int 7)])))))
1357 (match_operand:V4SI 1 "register_operand" "0")))]
1358 "ISA_HAS_MSA"
1359 "dpadd_<su>.w\t%w0,%w2,%w3"
1360 [(set_attr "type" "simd_mul")
1361 (set_attr "mode" "V4SI")])
1363 (define_insn "msa_dpadd_<su>_h"
1364 [(set (match_operand:V8HI 0 "register_operand" "=f")
1365 (plus:V8HI
1366 (plus:V8HI
1367 (mult:V8HI
1368 (any_extend:V8HI
1369 (vec_select:V8QI
1370 (match_operand:V16QI 2 "register_operand" "%f")
1371 (parallel [(const_int 0) (const_int 2)
1372 (const_int 4) (const_int 6)
1373 (const_int 8) (const_int 10)
1374 (const_int 12) (const_int 14)])))
1375 (any_extend:V8HI
1376 (vec_select:V8QI
1377 (match_operand:V16QI 3 "register_operand" "f")
1378 (parallel [(const_int 0) (const_int 2)
1379 (const_int 4) (const_int 6)
1380 (const_int 8) (const_int 10)
1381 (const_int 12) (const_int 14)]))))
1382 (mult:V8HI
1383 (any_extend:V8HI
1384 (vec_select:V8QI (match_dup 2)
1385 (parallel [(const_int 1) (const_int 3)
1386 (const_int 5) (const_int 7)
1387 (const_int 9) (const_int 11)
1388 (const_int 13) (const_int 15)])))
1389 (any_extend:V8HI
1390 (vec_select:V8QI (match_dup 3)
1391 (parallel [(const_int 1) (const_int 3)
1392 (const_int 5) (const_int 7)
1393 (const_int 9) (const_int 11)
1394 (const_int 13) (const_int 15)])))))
1395 (match_operand:V8HI 1 "register_operand" "0")))]
1396 "ISA_HAS_MSA"
1397 "dpadd_<su>.h\t%w0,%w2,%w3"
1398 [(set_attr "type" "simd_mul")
1399 (set_attr "mode" "V8HI")])
1401 (define_insn "msa_dpsub_<su>_d"
1402 [(set (match_operand:V2DI 0 "register_operand" "=f")
1403 (minus:V2DI
1404 (match_operand:V2DI 1 "register_operand" "0")
1405 (plus:V2DI
1406 (mult:V2DI
1407 (any_extend:V2DI
1408 (vec_select:V2SI
1409 (match_operand:V4SI 2 "register_operand" "%f")
1410 (parallel [(const_int 0) (const_int 2)])))
1411 (any_extend:V2DI
1412 (vec_select:V2SI
1413 (match_operand:V4SI 3 "register_operand" "f")
1414 (parallel [(const_int 0) (const_int 2)]))))
1415 (mult:V2DI
1416 (any_extend:V2DI
1417 (vec_select:V2SI (match_dup 2)
1418 (parallel [(const_int 1) (const_int 3)])))
1419 (any_extend:V2DI
1420 (vec_select:V2SI (match_dup 3)
1421 (parallel [(const_int 1) (const_int 3)])))))))]
1422 "ISA_HAS_MSA"
1423 "dpsub_<su>.d\t%w0,%w2,%w3"
1424 [(set_attr "type" "simd_mul")
1425 (set_attr "mode" "V2DI")])
1427 (define_insn "msa_dpsub_<su>_w"
1428 [(set (match_operand:V4SI 0 "register_operand" "=f")
1429 (minus:V4SI
1430 (match_operand:V4SI 1 "register_operand" "0")
1431 (plus:V4SI
1432 (mult:V4SI
1433 (any_extend:V4SI
1434 (vec_select:V4HI
1435 (match_operand:V8HI 2 "register_operand" "%f")
1436 (parallel [(const_int 0) (const_int 2)
1437 (const_int 4) (const_int 6)])))
1438 (any_extend:V4SI
1439 (vec_select:V4HI
1440 (match_operand:V8HI 3 "register_operand" "f")
1441 (parallel [(const_int 0) (const_int 2)
1442 (const_int 4) (const_int 6)]))))
1443 (mult:V4SI
1444 (any_extend:V4SI
1445 (vec_select:V4HI (match_dup 2)
1446 (parallel [(const_int 1) (const_int 3)
1447 (const_int 5) (const_int 7)])))
1448 (any_extend:V4SI
1449 (vec_select:V4HI (match_dup 3)
1450 (parallel [(const_int 1) (const_int 3)
1451 (const_int 5) (const_int 7)])))))))]
1452 "ISA_HAS_MSA"
1453 "dpsub_<su>.w\t%w0,%w2,%w3"
1454 [(set_attr "type" "simd_mul")
1455 (set_attr "mode" "V4SI")])
1457 (define_insn "msa_dpsub_<su>_h"
1458 [(set (match_operand:V8HI 0 "register_operand" "=f")
1459 (minus:V8HI
1460 (match_operand:V8HI 1 "register_operand" "0")
1461 (plus:V8HI
1462 (mult:V8HI
1463 (any_extend:V8HI
1464 (vec_select:V8QI
1465 (match_operand:V16QI 2 "register_operand" "%f")
1466 (parallel [(const_int 0) (const_int 2)
1467 (const_int 4) (const_int 6)
1468 (const_int 8) (const_int 10)
1469 (const_int 12) (const_int 14)])))
1470 (any_extend:V8HI
1471 (vec_select:V8QI
1472 (match_operand:V16QI 3 "register_operand" "f")
1473 (parallel [(const_int 0) (const_int 2)
1474 (const_int 4) (const_int 6)
1475 (const_int 8) (const_int 10)
1476 (const_int 12) (const_int 14)]))))
1477 (mult:V8HI
1478 (any_extend:V8HI
1479 (vec_select:V8QI (match_dup 2)
1480 (parallel [(const_int 1) (const_int 3)
1481 (const_int 5) (const_int 7)
1482 (const_int 9) (const_int 11)
1483 (const_int 13) (const_int 15)])))
1484 (any_extend:V8HI
1485 (vec_select:V8QI (match_dup 3)
1486 (parallel [(const_int 1) (const_int 3)
1487 (const_int 5) (const_int 7)
1488 (const_int 9) (const_int 11)
1489 (const_int 13) (const_int 15)])))))))]
1490 "ISA_HAS_MSA"
1491 "dpsub_<su>.h\t%w0,%w2,%w3"
1492 [(set_attr "type" "simd_mul")
1493 (set_attr "mode" "V8HI")])
1495 (define_insn "msa_fclass_<msafmt>"
1496 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1497 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1498 UNSPEC_MSA_FCLASS))]
1499 "ISA_HAS_MSA"
1500 "fclass.<msafmt>\t%w0,%w1"
1501 [(set_attr "type" "simd_fclass")
1502 (set_attr "mode" "<MODE>")])
1504 (define_insn "msa_fcaf_<msafmt>"
1505 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1506 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1507 (match_operand:FMSA 2 "register_operand" "f")]
1508 UNSPEC_MSA_FCAF))]
1509 "ISA_HAS_MSA"
1510 "fcaf.<msafmt>\t%w0,%w1,%w2"
1511 [(set_attr "type" "simd_fcmp")
1512 (set_attr "mode" "<MODE>")])
1514 (define_insn "msa_fcune_<FMSA:msafmt>"
1515 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1516 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1517 (match_operand:FMSA 2 "register_operand" "f")]
1518 UNSPEC_MSA_FCUNE))]
1519 "ISA_HAS_MSA"
1520 "fcune.<FMSA:msafmt>\t%w0,%w1,%w2"
1521 [(set_attr "type" "simd_fcmp")
1522 (set_attr "mode" "<MODE>")])
1524 (define_code_iterator FCC [unordered ordered eq ne le lt uneq unle unlt])
1526 (define_code_attr fcc
1527 [(unordered "fcun")
1528 (ordered "fcor")
1529 (eq "fceq")
1530 (ne "fcne")
1531 (uneq "fcueq")
1532 (unle "fcule")
1533 (unlt "fcult")
1534 (le "fcle")
1535 (lt "fclt")])
1537 (define_int_iterator FSC_UNS [UNSPEC_MSA_FSAF UNSPEC_MSA_FSUN UNSPEC_MSA_FSOR
1538 UNSPEC_MSA_FSEQ UNSPEC_MSA_FSNE UNSPEC_MSA_FSUEQ
1539 UNSPEC_MSA_FSUNE UNSPEC_MSA_FSULE UNSPEC_MSA_FSULT
1540 UNSPEC_MSA_FSLE UNSPEC_MSA_FSLT])
1542 (define_int_attr fsc
1543 [(UNSPEC_MSA_FSAF "fsaf")
1544 (UNSPEC_MSA_FSUN "fsun")
1545 (UNSPEC_MSA_FSOR "fsor")
1546 (UNSPEC_MSA_FSEQ "fseq")
1547 (UNSPEC_MSA_FSNE "fsne")
1548 (UNSPEC_MSA_FSUEQ "fsueq")
1549 (UNSPEC_MSA_FSUNE "fsune")
1550 (UNSPEC_MSA_FSULE "fsule")
1551 (UNSPEC_MSA_FSULT "fsult")
1552 (UNSPEC_MSA_FSLE "fsle")
1553 (UNSPEC_MSA_FSLT "fslt")])
1555 (define_insn "msa_<FCC:fcc>_<FMSA:msafmt>"
1556 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1557 (FCC:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")
1558 (match_operand:FMSA 2 "register_operand" "f")))]
1559 "ISA_HAS_MSA"
1560 "<FCC:fcc>.<FMSA:msafmt>\t%w0,%w1,%w2"
1561 [(set_attr "type" "simd_fcmp")
1562 (set_attr "mode" "<MODE>")])
1564 (define_insn "msa_<fsc>_<FMSA:msafmt>"
1565 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1566 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1567 (match_operand:FMSA 2 "register_operand" "f")]
1568 FSC_UNS))]
1569 "ISA_HAS_MSA"
1570 "<fsc>.<FMSA:msafmt>\t%w0,%w1,%w2"
1571 [(set_attr "type" "simd_fcmp")
1572 (set_attr "mode" "<MODE>")])
1574 (define_insn "msa_fexp2_<msafmt>"
1575 [(set (match_operand:FMSA 0 "register_operand" "=f")
1576 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")
1577 (match_operand:<VIMODE> 2 "register_operand" "f")]
1578 UNSPEC_MSA_FEXP2))]
1579 "ISA_HAS_MSA"
1580 "fexp2.<msafmt>\t%w0,%w1,%w2"
1581 [(set_attr "type" "simd_fexp2")
1582 (set_attr "mode" "<MODE>")])
1584 (define_mode_attr fint
1585 [(V4SF "v4si")
1586 (V2DF "v2di")])
1588 (define_mode_attr FQ
1589 [(V4SF "V8HI")
1590 (V2DF "V4SI")])
1592 (define_mode_attr FINTCNV
1593 [(V4SF "I2S")
1594 (V2DF "I2D")])
1596 (define_mode_attr FINTCNV_2
1597 [(V4SF "S2I")
1598 (V2DF "D2I")])
1600 (define_insn "float<fint><FMSA:mode>2"
1601 [(set (match_operand:FMSA 0 "register_operand" "=f")
1602 (float:FMSA (match_operand:<VIMODE> 1 "register_operand" "f")))]
1603 "ISA_HAS_MSA"
1604 "ffint_s.<msafmt>\t%w0,%w1"
1605 [(set_attr "type" "simd_fcvt")
1606 (set_attr "cnv_mode" "<FINTCNV>")
1607 (set_attr "mode" "<MODE>")])
1609 (define_insn "floatuns<fint><FMSA:mode>2"
1610 [(set (match_operand:FMSA 0 "register_operand" "=f")
1611 (unsigned_float:FMSA
1612 (match_operand:<VIMODE> 1 "register_operand" "f")))]
1613 "ISA_HAS_MSA"
1614 "ffint_u.<msafmt>\t%w0,%w1"
1615 [(set_attr "type" "simd_fcvt")
1616 (set_attr "cnv_mode" "<FINTCNV>")
1617 (set_attr "mode" "<MODE>")])
1619 (define_mode_attr FFQ
1620 [(V4SF "V8HI")
1621 (V2DF "V4SI")])
1623 (define_insn "msa_ffql_<msafmt>"
1624 [(set (match_operand:FMSA 0 "register_operand" "=f")
1625 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")]
1626 UNSPEC_MSA_FFQL))]
1627 "ISA_HAS_MSA"
1628 "ffql.<msafmt>\t%w0,%w1"
1629 [(set_attr "type" "simd_fcvt")
1630 (set_attr "cnv_mode" "<FINTCNV>")
1631 (set_attr "mode" "<MODE>")])
1633 (define_insn "msa_ffqr_<msafmt>"
1634 [(set (match_operand:FMSA 0 "register_operand" "=f")
1635 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")]
1636 UNSPEC_MSA_FFQR))]
1637 "ISA_HAS_MSA"
1638 "ffqr.<msafmt>\t%w0,%w1"
1639 [(set_attr "type" "simd_fcvt")
1640 (set_attr "cnv_mode" "<FINTCNV>")
1641 (set_attr "mode" "<MODE>")])
1643 (define_insn "msa_fill_<msafmt_f>"
1644 [(set (match_operand:MSA 0 "register_operand" "=f,f")
1645 (vec_duplicate:MSA
1646 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "d,J")))]
1647 "ISA_HAS_MSA"
1648 {
1649 if (which_alternative == 1)
1650 return "ldi.<msafmt>\t%w0,0";
1652 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
1653 return "#";
1654 else
1655 return "fill.<msafmt>\t%w0,%z1";
1656 }
1657 [(set_attr "type" "simd_fill")
1658 (set_attr "mode" "<MODE>")])
1660 (define_split
1661 [(set (match_operand:MSA_D 0 "register_operand")
1662 (vec_duplicate:MSA_D
1663 (match_operand:<UNITMODE> 1 "register_operand")))]
1664 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
1665 [(const_int 0)]
1666 {
1667 mips_split_msa_fill_d (operands[0], operands[1]);
1668 DONE;
1669 })
1671 (define_insn "msa_flog2_<msafmt>"
1672 [(set (match_operand:FMSA 0 "register_operand" "=f")
1673 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1674 UNSPEC_MSA_FLOG2))]
1675 "ISA_HAS_MSA"
1676 "flog2.<msafmt>\t%w0,%w1"
1677 [(set_attr "type" "simd_flog2")
1678 (set_attr "mode" "<MODE>")])
1680 (define_insn "smax<mode>3"
1681 [(set (match_operand:FMSA 0 "register_operand" "=f")
1682 (smax:FMSA (match_operand:FMSA 1 "register_operand" "f")
1683 (match_operand:FMSA 2 "register_operand" "f")))]
1684 "ISA_HAS_MSA"
1685 "fmax.<msafmt>\t%w0,%w1,%w2"
1686 [(set_attr "type" "simd_fminmax")
1687 (set_attr "mode" "<MODE>")])
1689 (define_insn "msa_fmax_a_<msafmt>"
1690 [(set (match_operand:FMSA 0 "register_operand" "=f")
1691 (if_then_else:FMSA
1692 (gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
1693 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
1694 (match_dup 1)
1695 (match_dup 2)))]
1696 "ISA_HAS_MSA"
1697 "fmax_a.<msafmt>\t%w0,%w1,%w2"
1698 [(set_attr "type" "simd_fminmax")
1699 (set_attr "mode" "<MODE>")])
1701 (define_insn "smin<mode>3"
1702 [(set (match_operand:FMSA 0 "register_operand" "=f")
1703 (smin:FMSA (match_operand:FMSA 1 "register_operand" "f")
1704 (match_operand:FMSA 2 "register_operand" "f")))]
1705 "ISA_HAS_MSA"
1706 "fmin.<msafmt>\t%w0,%w1,%w2"
1707 [(set_attr "type" "simd_fminmax")
1708 (set_attr "mode" "<MODE>")])
1710 (define_insn "msa_fmin_a_<msafmt>"
1711 [(set (match_operand:FMSA 0 "register_operand" "=f")
1712 (if_then_else:FMSA
1713 (lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
1714 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
1715 (match_dup 1)
1716 (match_dup 2)))]
1717 "ISA_HAS_MSA"
1718 "fmin_a.<msafmt>\t%w0,%w1,%w2"
1719 [(set_attr "type" "simd_fminmax")
1720 (set_attr "mode" "<MODE>")])
1722 (define_insn "msa_frcp_<msafmt>"
1723 [(set (match_operand:FMSA 0 "register_operand" "=f")
1724 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1725 UNSPEC_MSA_FRCP))]
1726 "ISA_HAS_MSA"
1727 "frcp.<msafmt>\t%w0,%w1"
1728 [(set_attr "type" "simd_fdiv")
1729 (set_attr "mode" "<MODE>")])
1731 (define_insn "msa_frint_<msafmt>"
1732 [(set (match_operand:FMSA 0 "register_operand" "=f")
1733 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1734 UNSPEC_MSA_FRINT))]
1735 "ISA_HAS_MSA"
1736 "frint.<msafmt>\t%w0,%w1"
1737 [(set_attr "type" "simd_fcvt")
1738 (set_attr "mode" "<MODE>")])
1740 (define_insn "msa_frsqrt_<msafmt>"
1741 [(set (match_operand:FMSA 0 "register_operand" "=f")
1742 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1743 UNSPEC_MSA_FRSQRT))]
1744 "ISA_HAS_MSA"
1745 "frsqrt.<msafmt>\t%w0,%w1"
1746 [(set_attr "type" "simd_fdiv")
1747 (set_attr "mode" "<MODE>")])
1749 (define_insn "msa_ftint_s_<msafmt>"
1750 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1751 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1752 UNSPEC_MSA_FTINT_S))]
1753 "ISA_HAS_MSA"
1754 "ftint_s.<msafmt>\t%w0,%w1"
1755 [(set_attr "type" "simd_fcvt")
1756 (set_attr "cnv_mode" "<FINTCNV_2>")
1757 (set_attr "mode" "<MODE>")])
1759 (define_insn "msa_ftint_u_<msafmt>"
1760 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1761 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1762 UNSPEC_MSA_FTINT_U))]
1763 "ISA_HAS_MSA"
1764 "ftint_u.<msafmt>\t%w0,%w1"
1765 [(set_attr "type" "simd_fcvt")
1766 (set_attr "cnv_mode" "<FINTCNV_2>")
1767 (set_attr "mode" "<MODE>")])
1769 (define_insn "fix_trunc<FMSA:mode><mode_i>2"
1770 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1771 (fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))]
1772 "ISA_HAS_MSA"
1773 "ftrunc_s.<msafmt>\t%w0,%w1"
1774 [(set_attr "type" "simd_fcvt")
1775 (set_attr "cnv_mode" "<FINTCNV_2>")
1776 (set_attr "mode" "<MODE>")])
1778 (define_insn "fixuns_trunc<FMSA:mode><mode_i>2"
1779 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1780 (unsigned_fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))]
1781 "ISA_HAS_MSA"
1782 "ftrunc_u.<msafmt>\t%w0,%w1"
1783 [(set_attr "type" "simd_fcvt")
1784 (set_attr "cnv_mode" "<FINTCNV_2>")
1785 (set_attr "mode" "<MODE>")])
1787 (define_insn "msa_ftq_h"
1788 [(set (match_operand:V8HI 0 "register_operand" "=f")
1789 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
1790 (match_operand:V4SF 2 "register_operand" "f")]
1791 UNSPEC_MSA_FTQ))]
1792 "ISA_HAS_MSA"
1793 "ftq.h\t%w0,%w1,%w2"
1794 [(set_attr "type" "simd_fcvt")
1795 (set_attr "cnv_mode" "S2I")
1796 (set_attr "mode" "V4SF")])
1798 (define_insn "msa_ftq_w"
1799 [(set (match_operand:V4SI 0 "register_operand" "=f")
1800 (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
1801 (match_operand:V2DF 2 "register_operand" "f")]
1802 UNSPEC_MSA_FTQ))]
1803 "ISA_HAS_MSA"
1804 "ftq.w\t%w0,%w1,%w2"
1805 [(set_attr "type" "simd_fcvt")
1806 (set_attr "cnv_mode" "D2I")
1807 (set_attr "mode" "V2DF")])
1809 (define_insn "msa_h<optab>_<su>_h"
1810 [(set (match_operand:V8HI 0 "register_operand" "=f")
1811 (addsub:V8HI
1812 (any_extend:V8HI
1813 (vec_select:V8QI
1814 (match_operand:V16QI 1 "register_operand" "f")
1815 (parallel [(const_int 1) (const_int 3)
1816 (const_int 5) (const_int 7)
1817 (const_int 9) (const_int 11)
1818 (const_int 13) (const_int 15)])))
1819 (any_extend:V8HI
1820 (vec_select:V8QI
1821 (match_operand:V16QI 2 "register_operand" "f")
1822 (parallel [(const_int 0) (const_int 2)
1823 (const_int 4) (const_int 6)
1824 (const_int 8) (const_int 10)
1825 (const_int 12) (const_int 14)])))))]
1826 "ISA_HAS_MSA"
1827 "h<optab>_<su>.h\t%w0,%w1,%w2"
1828 [(set_attr "type" "simd_int_arith")
1829 (set_attr "mode" "V8HI")])
1831 (define_insn "msa_h<optab>_<su>_w"
1832 [(set (match_operand:V4SI 0 "register_operand" "=f")
1833 (addsub:V4SI
1834 (any_extend:V4SI
1835 (vec_select:V4HI
1836 (match_operand:V8HI 1 "register_operand" "f")
1837 (parallel [(const_int 1) (const_int 3)
1838 (const_int 5) (const_int 7)])))
1839 (any_extend:V4SI
1840 (vec_select:V4HI
1841 (match_operand:V8HI 2 "register_operand" "f")
1842 (parallel [(const_int 0) (const_int 2)
1843 (const_int 4) (const_int 6)])))))]
1844 "ISA_HAS_MSA"
1845 "h<optab>_<su>.w\t%w0,%w1,%w2"
1846 [(set_attr "type" "simd_int_arith")
1847 (set_attr "mode" "V4SI")])
1849 (define_insn "msa_h<optab>_<su>_d"
1850 [(set (match_operand:V2DI 0 "register_operand" "=f")
1851 (addsub:V2DI
1852 (any_extend:V2DI
1853 (vec_select:V2SI
1854 (match_operand:V4SI 1 "register_operand" "f")
1855 (parallel [(const_int 1) (const_int 3)])))
1856 (any_extend:V2DI
1857 (vec_select:V2SI
1858 (match_operand:V4SI 2 "register_operand" "f")
1859 (parallel [(const_int 0) (const_int 2)])))))]
1860 "ISA_HAS_MSA"
1861 "h<optab>_<su>.d\t%w0,%w1,%w2"
1862 [(set_attr "type" "simd_int_arith")
1863 (set_attr "mode" "V2DI")])
1865 (define_insn "msa_ilvev_b"
1866 [(set (match_operand:V16QI 0 "register_operand" "=f")
1867 (vec_select:V16QI
1868 (vec_concat:V32QI
1869 (match_operand:V16QI 1 "register_operand" "f")
1870 (match_operand:V16QI 2 "register_operand" "f"))
1871 (parallel [(const_int 0) (const_int 16)
1872 (const_int 2) (const_int 18)
1873 (const_int 4) (const_int 20)
1874 (const_int 6) (const_int 22)
1875 (const_int 8) (const_int 24)
1876 (const_int 10) (const_int 26)
1877 (const_int 12) (const_int 28)
1878 (const_int 14) (const_int 30)])))]
1879 "ISA_HAS_MSA"
1880 "ilvev.b\t%w0,%w2,%w1"
1881 [(set_attr "type" "simd_permute")
1882 (set_attr "mode" "V16QI")])
1884 (define_insn "msa_ilvev_h"
1885 [(set (match_operand:V8HI 0 "register_operand" "=f")
1886 (vec_select:V8HI
1887 (vec_concat:V16HI
1888 (match_operand:V8HI 1 "register_operand" "f")
1889 (match_operand:V8HI 2 "register_operand" "f"))
1890 (parallel [(const_int 0) (const_int 8)
1891 (const_int 2) (const_int 10)
1892 (const_int 4) (const_int 12)
1893 (const_int 6) (const_int 14)])))]
1894 "ISA_HAS_MSA"
1895 "ilvev.h\t%w0,%w2,%w1"
1896 [(set_attr "type" "simd_permute")
1897 (set_attr "mode" "V8HI")])
1899 (define_insn "msa_ilvev_w"
1900 [(set (match_operand:V4SI 0 "register_operand" "=f")
1901 (vec_select:V4SI
1902 (vec_concat:V8SI
1903 (match_operand:V4SI 1 "register_operand" "f")
1904 (match_operand:V4SI 2 "register_operand" "f"))
1905 (parallel [(const_int 0) (const_int 4)
1906 (const_int 2) (const_int 6)])))]
1907 "ISA_HAS_MSA"
1908 "ilvev.w\t%w0,%w2,%w1"
1909 [(set_attr "type" "simd_permute")
1910 (set_attr "mode" "V4SI")])
1912 (define_insn "msa_ilvev_w_f"
1913 [(set (match_operand:V4SF 0 "register_operand" "=f")
1914 (vec_select:V4SF
1915 (vec_concat:V8SF
1916 (match_operand:V4SF 1 "register_operand" "f")
1917 (match_operand:V4SF 2 "register_operand" "f"))
1918 (parallel [(const_int 0) (const_int 4)
1919 (const_int 2) (const_int 6)])))]
1920 "ISA_HAS_MSA"
1921 "ilvev.w\t%w0,%w2,%w1"
1922 [(set_attr "type" "simd_permute")
1923 (set_attr "mode" "V4SF")])
1925 (define_insn "msa_ilvl_b"
1926 [(set (match_operand:V16QI 0 "register_operand" "=f")
1927 (vec_select:V16QI
1928 (vec_concat:V32QI
1929 (match_operand:V16QI 1 "register_operand" "f")
1930 (match_operand:V16QI 2 "register_operand" "f"))
1931 (parallel [(const_int 8) (const_int 24)
1932 (const_int 9) (const_int 25)
1933 (const_int 10) (const_int 26)
1934 (const_int 11) (const_int 27)
1935 (const_int 12) (const_int 28)
1936 (const_int 13) (const_int 29)
1937 (const_int 14) (const_int 30)
1938 (const_int 15) (const_int 31)])))]
1939 "ISA_HAS_MSA"
1940 "ilvl.b\t%w0,%w2,%w1"
1941 [(set_attr "type" "simd_permute")
1942 (set_attr "mode" "V16QI")])
1944 (define_insn "msa_ilvl_h"
1945 [(set (match_operand:V8HI 0 "register_operand" "=f")
1946 (vec_select:V8HI
1947 (vec_concat:V16HI
1948 (match_operand:V8HI 1 "register_operand" "f")
1949 (match_operand:V8HI 2 "register_operand" "f"))
1950 (parallel [(const_int 4) (const_int 12)
1951 (const_int 5) (const_int 13)
1952 (const_int 6) (const_int 14)
1953 (const_int 7) (const_int 15)])))]
1954 "ISA_HAS_MSA"
1955 "ilvl.h\t%w0,%w2,%w1"
1956 [(set_attr "type" "simd_permute")
1957 (set_attr "mode" "V8HI")])
1959 (define_insn "msa_ilvl_w"
1960 [(set (match_operand:V4SI 0 "register_operand" "=f")
1961 (vec_select:V4SI
1962 (vec_concat:V8SI
1963 (match_operand:V4SI 1 "register_operand" "f")
1964 (match_operand:V4SI 2 "register_operand" "f"))
1965 (parallel [(const_int 2) (const_int 6)
1966 (const_int 3) (const_int 7)])))]
1967 "ISA_HAS_MSA"
1968 "ilvl.w\t%w0,%w2,%w1"
1969 [(set_attr "type" "simd_permute")
1970 (set_attr "mode" "V4SI")])
1972 (define_insn "msa_ilvl_w_f"
1973 [(set (match_operand:V4SF 0 "register_operand" "=f")
1974 (vec_select:V4SF
1975 (vec_concat:V8SF
1976 (match_operand:V4SF 1 "register_operand" "f")
1977 (match_operand:V4SF 2 "register_operand" "f"))
1978 (parallel [(const_int 2) (const_int 6)
1979 (const_int 3) (const_int 7)])))]
1980 "ISA_HAS_MSA"
1981 "ilvl.w\t%w0,%w2,%w1"
1982 [(set_attr "type" "simd_permute")
1983 (set_attr "mode" "V4SF")])
1985 (define_insn "msa_ilvl_d"
1986 [(set (match_operand:V2DI 0 "register_operand" "=f")
1987 (vec_select:V2DI
1988 (vec_concat:V4DI
1989 (match_operand:V2DI 1 "register_operand" "f")
1990 (match_operand:V2DI 2 "register_operand" "f"))
1991 (parallel [(const_int 1) (const_int 3)])))]
1992 "ISA_HAS_MSA"
1993 "ilvl.d\t%w0,%w2,%w1"
1994 [(set_attr "type" "simd_permute")
1995 (set_attr "mode" "V2DI")])
1997 (define_insn "msa_ilvl_d_f"
1998 [(set (match_operand:V2DF 0 "register_operand" "=f")
1999 (vec_select:V2DF
2000 (vec_concat:V4DF
2001 (match_operand:V2DF 1 "register_operand" "f")
2002 (match_operand:V2DF 2 "register_operand" "f"))
2003 (parallel [(const_int 1) (const_int 3)])))]
2004 "ISA_HAS_MSA"
2005 "ilvl.d\t%w0,%w2,%w1"
2006 [(set_attr "type" "simd_permute")
2007 (set_attr "mode" "V2DF")])
2009 (define_insn "msa_ilvod_b"
2010 [(set (match_operand:V16QI 0 "register_operand" "=f")
2011 (vec_select:V16QI
2012 (vec_concat:V32QI
2013 (match_operand:V16QI 1 "register_operand" "f")
2014 (match_operand:V16QI 2 "register_operand" "f"))
2015 (parallel [(const_int 1) (const_int 17)
2016 (const_int 3) (const_int 19)
2017 (const_int 5) (const_int 21)
2018 (const_int 7) (const_int 23)
2019 (const_int 9) (const_int 25)
2020 (const_int 11) (const_int 27)
2021 (const_int 13) (const_int 29)
2022 (const_int 15) (const_int 31)])))]
2023 "ISA_HAS_MSA"
2024 "ilvod.b\t%w0,%w2,%w1"
2025 [(set_attr "type" "simd_permute")
2026 (set_attr "mode" "V16QI")])
2028 (define_insn "msa_ilvod_h"
2029 [(set (match_operand:V8HI 0 "register_operand" "=f")
2030 (vec_select:V8HI
2031 (vec_concat:V16HI
2032 (match_operand:V8HI 1 "register_operand" "f")
2033 (match_operand:V8HI 2 "register_operand" "f"))
2034 (parallel [(const_int 1) (const_int 9)
2035 (const_int 3) (const_int 11)
2036 (const_int 5) (const_int 13)
2037 (const_int 7) (const_int 15)])))]
2038 "ISA_HAS_MSA"
2039 "ilvod.h\t%w0,%w2,%w1"
2040 [(set_attr "type" "simd_permute")
2041 (set_attr "mode" "V8HI")])
2043 (define_insn "msa_ilvod_w"
2044 [(set (match_operand:V4SI 0 "register_operand" "=f")
2045 (vec_select:V4SI
2046 (vec_concat:V8SI
2047 (match_operand:V4SI 1 "register_operand" "f")
2048 (match_operand:V4SI 2 "register_operand" "f"))
2049 (parallel [(const_int 1) (const_int 5)
2050 (const_int 3) (const_int 7)])))]
2051 "ISA_HAS_MSA"
2052 "ilvod.w\t%w0,%w2,%w1"
2053 [(set_attr "type" "simd_permute")
2054 (set_attr "mode" "V4SI")])
2056 (define_insn "msa_ilvod_w_f"
2057 [(set (match_operand:V4SF 0 "register_operand" "=f")
2058 (vec_select:V4SF
2059 (vec_concat:V8SF
2060 (match_operand:V4SF 1 "register_operand" "f")
2061 (match_operand:V4SF 2 "register_operand" "f"))
2062 (parallel [(const_int 1) (const_int 5)
2063 (const_int 3) (const_int 7)])))]
2064 "ISA_HAS_MSA"
2065 "ilvod.w\t%w0,%w2,%w1"
2066 [(set_attr "type" "simd_permute")
2067 (set_attr "mode" "V4SF")])
2069 (define_insn "msa_ilvr_b"
2070 [(set (match_operand:V16QI 0 "register_operand" "=f")
2071 (vec_select:V16QI
2072 (vec_concat:V32QI
2073 (match_operand:V16QI 1 "register_operand" "f")
2074 (match_operand:V16QI 2 "register_operand" "f"))
2075 (parallel [(const_int 0) (const_int 16)
2076 (const_int 1) (const_int 17)
2077 (const_int 2) (const_int 18)
2078 (const_int 3) (const_int 19)
2079 (const_int 4) (const_int 20)
2080 (const_int 5) (const_int 21)
2081 (const_int 6) (const_int 22)
2082 (const_int 7) (const_int 23)])))]
2083 "ISA_HAS_MSA"
2084 "ilvr.b\t%w0,%w2,%w1"
2085 [(set_attr "type" "simd_permute")
2086 (set_attr "mode" "V16QI")])
2088 (define_insn "msa_ilvr_h"
2089 [(set (match_operand:V8HI 0 "register_operand" "=f")
2090 (vec_select:V8HI
2091 (vec_concat:V16HI
2092 (match_operand:V8HI 1 "register_operand" "f")
2093 (match_operand:V8HI 2 "register_operand" "f"))
2094 (parallel [(const_int 0) (const_int 8)
2095 (const_int 1) (const_int 9)
2096 (const_int 2) (const_int 10)
2097 (const_int 3) (const_int 11)])))]
2098 "ISA_HAS_MSA"
2099 "ilvr.h\t%w0,%w2,%w1"
2100 [(set_attr "type" "simd_permute")
2101 (set_attr "mode" "V8HI")])
2103 (define_insn "msa_ilvr_w"
2104 [(set (match_operand:V4SI 0 "register_operand" "=f")
2105 (vec_select:V4SI
2106 (vec_concat:V8SI
2107 (match_operand:V4SI 1 "register_operand" "f")
2108 (match_operand:V4SI 2 "register_operand" "f"))
2109 (parallel [(const_int 0) (const_int 4)
2110 (const_int 1) (const_int 5)])))]
2111 "ISA_HAS_MSA"
2112 "ilvr.w\t%w0,%w2,%w1"
2113 [(set_attr "type" "simd_permute")
2114 (set_attr "mode" "V4SI")])
2116 (define_insn "msa_ilvr_w_f"
2117 [(set (match_operand:V4SF 0 "register_operand" "=f")
2118 (vec_select:V4SF
2119 (vec_concat:V8SF
2120 (match_operand:V4SF 1 "register_operand" "f")
2121 (match_operand:V4SF 2 "register_operand" "f"))
2122 (parallel [(const_int 0) (const_int 4)
2123 (const_int 1) (const_int 5)])))]
2124 "ISA_HAS_MSA"
2125 "ilvr.w\t%w0,%w2,%w1"
2126 [(set_attr "type" "simd_permute")
2127 (set_attr "mode" "V4SF")])
2129 (define_insn "msa_ilvr_d"
2130 [(set (match_operand:V2DI 0 "register_operand" "=f")
2131 (vec_select:V2DI
2132 (vec_concat:V4DI
2133 (match_operand:V2DI 1 "register_operand" "f")
2134 (match_operand:V2DI 2 "register_operand" "f"))
2135 (parallel [(const_int 0) (const_int 2)])))]
2136 "ISA_HAS_MSA"
2137 "ilvr.d\t%w0,%w2,%w1"
2138 [(set_attr "type" "simd_permute")
2139 (set_attr "mode" "V2DI")])
2141 (define_insn "msa_ilvr_d_f"
2142 [(set (match_operand:V2DF 0 "register_operand" "=f")
2143 (vec_select:V2DF
2144 (vec_concat:V4DF
2145 (match_operand:V2DF 1 "register_operand" "f")
2146 (match_operand:V2DF 2 "register_operand" "f"))
2147 (parallel [(const_int 0) (const_int 2)])))]
2148 "ISA_HAS_MSA"
2149 "ilvr.d\t%w0,%w2,%w1"
2150 [(set_attr "type" "simd_permute")
2151 (set_attr "mode" "V2DF")])
2153 (define_insn "msa_madd_q_<msafmt>"
2154 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2155 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2156 (match_operand:IMSA_WH 2 "register_operand" "f")
2157 (match_operand:IMSA_WH 3 "register_operand" "f")]
2158 UNSPEC_MSA_MADD_Q))]
2159 "ISA_HAS_MSA"
2160 "madd_q.<msafmt>\t%w0,%w2,%w3"
2161 [(set_attr "type" "simd_mul")
2162 (set_attr "mode" "<MODE>")])
2164 (define_insn "msa_maddr_q_<msafmt>"
2165 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2166 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2167 (match_operand:IMSA_WH 2 "register_operand" "f")
2168 (match_operand:IMSA_WH 3 "register_operand" "f")]
2169 UNSPEC_MSA_MADDR_Q))]
2170 "ISA_HAS_MSA"
2171 "maddr_q.<msafmt>\t%w0,%w2,%w3"
2172 [(set_attr "type" "simd_mul")
2173 (set_attr "mode" "<MODE>")])
2175 (define_insn "msa_max_a_<msafmt>"
2176 [(set (match_operand:IMSA 0 "register_operand" "=f")
2177 (if_then_else:IMSA
2178 (gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
2179 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
2180 (match_dup 1)
2181 (match_dup 2)))]
2182 "ISA_HAS_MSA"
2183 "max_a.<msafmt>\t%w0,%w1,%w2"
2184 [(set_attr "type" "simd_int_arith")
2185 (set_attr "mode" "<MODE>")])
2187 (define_insn "smax<mode>3"
2188 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2189 (smax:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2190 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
2191 "ISA_HAS_MSA"
2192 "@
2193 max_s.<msafmt>\t%w0,%w1,%w2
2194 maxi_s.<msafmt>\t%w0,%w1,%E2"
2195 [(set_attr "type" "simd_int_arith")
2196 (set_attr "mode" "<MODE>")])
2198 (define_insn "umax<mode>3"
2199 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2200 (umax:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2201 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
2202 "ISA_HAS_MSA"
2203 "@
2204 max_u.<msafmt>\t%w0,%w1,%w2
2205 maxi_u.<msafmt>\t%w0,%w1,%B2"
2206 [(set_attr "type" "simd_int_arith")
2207 (set_attr "mode" "<MODE>")])
2209 (define_insn "msa_min_a_<msafmt>"
2210 [(set (match_operand:IMSA 0 "register_operand" "=f")
2211 (if_then_else:IMSA
2212 (lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
2213 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
2214 (match_dup 1)
2215 (match_dup 2)))]
2216 "ISA_HAS_MSA"
2217 "min_a.<msafmt>\t%w0,%w1,%w2"
2218 [(set_attr "type" "simd_int_arith")
2219 (set_attr "mode" "<MODE>")])
2221 (define_insn "smin<mode>3"
2222 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2223 (smin:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2224 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
2225 "ISA_HAS_MSA"
2226 "@
2227 min_s.<msafmt>\t%w0,%w1,%w2
2228 mini_s.<msafmt>\t%w0,%w1,%E2"
2229 [(set_attr "type" "simd_int_arith")
2230 (set_attr "mode" "<MODE>")])
2232 (define_insn "umin<mode>3"
2233 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2234 (umin:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2235 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
2236 "ISA_HAS_MSA"
2237 "@
2238 min_u.<msafmt>\t%w0,%w1,%w2
2239 mini_u.<msafmt>\t%w0,%w1,%B2"
2240 [(set_attr "type" "simd_int_arith")
2241 (set_attr "mode" "<MODE>")])
2243 (define_insn "msa_msub_q_<msafmt>"
2244 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2245 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2246 (match_operand:IMSA_WH 2 "register_operand" "f")
2247 (match_operand:IMSA_WH 3 "register_operand" "f")]
2248 UNSPEC_MSA_MSUB_Q))]
2249 "ISA_HAS_MSA"
2250 "msub_q.<msafmt>\t%w0,%w2,%w3"
2251 [(set_attr "type" "simd_mul")
2252 (set_attr "mode" "<MODE>")])
2254 (define_insn "msa_msubr_q_<msafmt>"
2255 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2256 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2257 (match_operand:IMSA_WH 2 "register_operand" "f")
2258 (match_operand:IMSA_WH 3 "register_operand" "f")]
2259 UNSPEC_MSA_MSUBR_Q))]
2260 "ISA_HAS_MSA"
2261 "msubr_q.<msafmt>\t%w0,%w2,%w3"
2262 [(set_attr "type" "simd_mul")
2263 (set_attr "mode" "<MODE>")])
2265 (define_insn "msa_mul_q_<msafmt>"
2266 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2267 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f")
2268 (match_operand:IMSA_WH 2 "register_operand" "f")]
2269 UNSPEC_MSA_MUL_Q))]
2270 "ISA_HAS_MSA"
2271 "mul_q.<msafmt>\t%w0,%w1,%w2"
2272 [(set_attr "type" "simd_mul")
2273 (set_attr "mode" "<MODE>")])
2275 (define_insn "msa_mulr_q_<msafmt>"
2276 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2277 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f")
2278 (match_operand:IMSA_WH 2 "register_operand" "f")]
2279 UNSPEC_MSA_MULR_Q))]
2280 "ISA_HAS_MSA"
2281 "mulr_q.<msafmt>\t%w0,%w1,%w2"
2282 [(set_attr "type" "simd_mul")
2283 (set_attr "mode" "<MODE>")])
2285 (define_insn "msa_nloc_<msafmt>"
2286 [(set (match_operand:IMSA 0 "register_operand" "=f")
2287 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")]
2288 UNSPEC_MSA_NLOC))]
2289 "ISA_HAS_MSA"
2290 "nloc.<msafmt>\t%w0,%w1"
2291 [(set_attr "type" "simd_bit")
2292 (set_attr "mode" "<MODE>")])
2294 (define_insn "clz<mode>2"
2295 [(set (match_operand:IMSA 0 "register_operand" "=f")
2296 (clz:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
2297 "ISA_HAS_MSA"
2298 "nlzc.<msafmt>\t%w0,%w1"
2299 [(set_attr "type" "simd_bit")
2300 (set_attr "mode" "<MODE>")])
2302 (define_insn "msa_nor_<msafmt>"
2303 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2304 (and:IMSA (not:IMSA (match_operand:IMSA 1 "register_operand" "f,f"))
2305 (not:IMSA (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,Urv8"))))]
2306 "ISA_HAS_MSA"
2307 "@
2308 nor.v\t%w0,%w1,%w2
2309 nori.b\t%w0,%w1,%B2"
2310 [(set_attr "type" "simd_logic")
2311 (set_attr "mode" "<MODE>")])
2313 (define_insn "msa_pckev_b"
2314 [(set (match_operand:V16QI 0 "register_operand" "=f")
2315 (vec_select:V16QI
2316 (vec_concat:V32QI
2317 (match_operand:V16QI 1 "register_operand" "f")
2318 (match_operand:V16QI 2 "register_operand" "f"))
2319 (parallel [(const_int 0) (const_int 2)
2320 (const_int 4) (const_int 6)
2321 (const_int 8) (const_int 10)
2322 (const_int 12) (const_int 14)
2323 (const_int 16) (const_int 18)
2324 (const_int 20) (const_int 22)
2325 (const_int 24) (const_int 26)
2326 (const_int 28) (const_int 30)])))]
2327 "ISA_HAS_MSA"
2328 "pckev.b\t%w0,%w2,%w1"
2329 [(set_attr "type" "simd_permute")
2330 (set_attr "mode" "V16QI")])
2332 (define_insn "msa_pckev_h"
2333 [(set (match_operand:V8HI 0 "register_operand" "=f")
2334 (vec_select:V8HI
2335 (vec_concat:V16HI
2336 (match_operand:V8HI 1 "register_operand" "f")
2337 (match_operand:V8HI 2 "register_operand" "f"))
2338 (parallel [(const_int 0) (const_int 2)
2339 (const_int 4) (const_int 6)
2340 (const_int 8) (const_int 10)
2341 (const_int 12) (const_int 14)])))]
2342 "ISA_HAS_MSA"
2343 "pckev.h\t%w0,%w2,%w1"
2344 [(set_attr "type" "simd_permute")
2345 (set_attr "mode" "V8HI")])
2347 (define_insn "msa_pckev_w"
2348 [(set (match_operand:V4SI 0 "register_operand" "=f")
2349 (vec_select:V4SI
2350 (vec_concat:V8SI
2351 (match_operand:V4SI 1 "register_operand" "f")
2352 (match_operand:V4SI 2 "register_operand" "f"))
2353 (parallel [(const_int 0) (const_int 2)
2354 (const_int 4) (const_int 6)])))]
2355 "ISA_HAS_MSA"
2356 "pckev.w\t%w0,%w2,%w1"
2357 [(set_attr "type" "simd_permute")
2358 (set_attr "mode" "V4SI")])
2360 (define_insn "msa_pckev_w_f"
2361 [(set (match_operand:V4SF 0 "register_operand" "=f")
2362 (vec_select:V4SF
2363 (vec_concat:V8SF
2364 (match_operand:V4SF 1 "register_operand" "f")
2365 (match_operand:V4SF 2 "register_operand" "f"))
2366 (parallel [(const_int 0) (const_int 2)
2367 (const_int 4) (const_int 6)])))]
2368 "ISA_HAS_MSA"
2369 "pckev.w\t%w0,%w2,%w1"
2370 [(set_attr "type" "simd_permute")
2371 (set_attr "mode" "V4SF")])
2373 (define_insn "msa_pckod_b"
2374 [(set (match_operand:V16QI 0 "register_operand" "=f")
2375 (vec_select:V16QI
2376 (vec_concat:V32QI
2377 (match_operand:V16QI 1 "register_operand" "f")
2378 (match_operand:V16QI 2 "register_operand" "f"))
2379 (parallel [(const_int 1) (const_int 3)
2380 (const_int 5) (const_int 7)
2381 (const_int 9) (const_int 11)
2382 (const_int 13) (const_int 15)
2383 (const_int 17) (const_int 19)
2384 (const_int 21) (const_int 23)
2385 (const_int 25) (const_int 27)
2386 (const_int 29) (const_int 31)])))]
2387 "ISA_HAS_MSA"
2388 "pckod.b\t%w0,%w2,%w1"
2389 [(set_attr "type" "simd_permute")
2390 (set_attr "mode" "V16QI")])
2392 (define_insn "msa_pckod_h"
2393 [(set (match_operand:V8HI 0 "register_operand" "=f")
2394 (vec_select:V8HI
2395 (vec_concat:V16HI
2396 (match_operand:V8HI 1 "register_operand" "f")
2397 (match_operand:V8HI 2 "register_operand" "f"))
2398 (parallel [(const_int 1) (const_int 3)
2399 (const_int 5) (const_int 7)
2400 (const_int 9) (const_int 11)
2401 (const_int 13) (const_int 15)])))]
2402 "ISA_HAS_MSA"
2403 "pckod.h\t%w0,%w2,%w1"
2404 [(set_attr "type" "simd_permute")
2405 (set_attr "mode" "V8HI")])
2407 (define_insn "msa_pckod_w"
2408 [(set (match_operand:V4SI 0 "register_operand" "=f")
2409 (vec_select:V4SI
2410 (vec_concat:V8SI
2411 (match_operand:V4SI 1 "register_operand" "f")
2412 (match_operand:V4SI 2 "register_operand" "f"))
2413 (parallel [(const_int 1) (const_int 3)
2414 (const_int 5) (const_int 7)])))]
2415 "ISA_HAS_MSA"
2416 "pckod.w\t%w0,%w2,%w1"
2417 [(set_attr "type" "simd_permute")
2418 (set_attr "mode" "V4SI")])
2420 (define_insn "msa_pckod_w_f"
2421 [(set (match_operand:V4SF 0 "register_operand" "=f")
2422 (vec_select:V4SF
2423 (vec_concat:V8SF
2424 (match_operand:V4SF 1 "register_operand" "f")
2425 (match_operand:V4SF 2 "register_operand" "f"))
2426 (parallel [(const_int 1) (const_int 3)
2427 (const_int 5) (const_int 7)])))]
2428 "ISA_HAS_MSA"
2429 "pckod.w\t%w0,%w2,%w1"
2430 [(set_attr "type" "simd_permute")
2431 (set_attr "mode" "V4SF")])
2433 (define_insn "popcount<mode>2"
2434 [(set (match_operand:IMSA 0 "register_operand" "=f")
2435 (popcount:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
2436 "ISA_HAS_MSA"
2437 "pcnt.<msafmt>\t%w0,%w1"
2438 [(set_attr "type" "simd_pcnt")
2439 (set_attr "mode" "<MODE>")])
2441 (define_insn "msa_sat_s_<msafmt>"
2442 [(set (match_operand:IMSA 0 "register_operand" "=f")
2443 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2444 (match_operand 2 "const_<bitimm>_operand" "")]
2445 UNSPEC_MSA_SAT_S))]
2446 "ISA_HAS_MSA"
2447 "sat_s.<msafmt>\t%w0,%w1,%2"
2448 [(set_attr "type" "simd_sat")
2449 (set_attr "mode" "<MODE>")])
2451 (define_insn "msa_sat_u_<msafmt>"
2452 [(set (match_operand:IMSA 0 "register_operand" "=f")
2453 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2454 (match_operand 2 "const_<bitimm>_operand" "")]
2455 UNSPEC_MSA_SAT_U))]
2456 "ISA_HAS_MSA"
2457 "sat_u.<msafmt>\t%w0,%w1,%2"
2458 [(set_attr "type" "simd_sat")
2459 (set_attr "mode" "<MODE>")])
2461 (define_insn "msa_shf_<msafmt_f>"
2462 [(set (match_operand:MSA_WHB_W 0 "register_operand" "=f")
2463 (vec_select:MSA_WHB_W
2464 (match_operand:MSA_WHB_W 1 "register_operand" "f")
2465 (match_operand 2 "par_const_vector_shf_set_operand" "")))]
2466 "ISA_HAS_MSA"
2467 {
2468 HOST_WIDE_INT val = 0;
2469 unsigned int i;
2471 /* We convert the selection to an immediate. */
2472 for (i = 0; i < 4; i++)
2473 val |= INTVAL (XVECEXP (operands[2], 0, i)) << (2 * i);
2475 operands[2] = GEN_INT (val);
2476 return "shf.<msafmt>\t%w0,%w1,%X2";
2477 }
2478 [(set_attr "type" "simd_shf")
2479 (set_attr "mode" "<MODE>")])
2481 (define_insn "msa_srar_<msafmt>"
2482 [(set (match_operand:IMSA 0 "register_operand" "=f")
2483 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2484 (match_operand:IMSA 2 "register_operand" "f")]
2485 UNSPEC_MSA_SRAR))]
2486 "ISA_HAS_MSA"
2487 "srar.<msafmt>\t%w0,%w1,%w2"
2488 [(set_attr "type" "simd_shift")
2489 (set_attr "mode" "<MODE>")])
2491 (define_insn "msa_srari_<msafmt>"
2492 [(set (match_operand:IMSA 0 "register_operand" "=f")
2493 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2494 (match_operand 2 "const_<bitimm>_operand" "")]
2495 UNSPEC_MSA_SRARI))]
2496 "ISA_HAS_MSA"
2497 "srari.<msafmt>\t%w0,%w1,%2"
2498 [(set_attr "type" "simd_shift")
2499 (set_attr "mode" "<MODE>")])
2501 (define_insn "msa_srlr_<msafmt>"
2502 [(set (match_operand:IMSA 0 "register_operand" "=f")
2503 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2504 (match_operand:IMSA 2 "register_operand" "f")]
2505 UNSPEC_MSA_SRLR))]
2506 "ISA_HAS_MSA"
2507 "srlr.<msafmt>\t%w0,%w1,%w2"
2508 [(set_attr "type" "simd_shift")
2509 (set_attr "mode" "<MODE>")])
2511 (define_insn "msa_srlri_<msafmt>"
2512 [(set (match_operand:IMSA 0 "register_operand" "=f")
2513 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2514 (match_operand 2 "const_<bitimm>_operand" "")]
2515 UNSPEC_MSA_SRLRI))]
2516 "ISA_HAS_MSA"
2517 "srlri.<msafmt>\t%w0,%w1,%2"
2518 [(set_attr "type" "simd_shift")
2519 (set_attr "mode" "<MODE>")])
2521 (define_insn "msa_subs_s_<msafmt>"
2522 [(set (match_operand:IMSA 0 "register_operand" "=f")
2523 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2524 (match_operand:IMSA 2 "register_operand" "f")]
2525 UNSPEC_MSA_SUBS_S))]
2526 "ISA_HAS_MSA"
2527 "subs_s.<msafmt>\t%w0,%w1,%w2"
2528 [(set_attr "type" "simd_int_arith")
2529 (set_attr "mode" "<MODE>")])
2531 (define_insn "msa_subs_u_<msafmt>"
2532 [(set (match_operand:IMSA 0 "register_operand" "=f")
2533 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2534 (match_operand:IMSA 2 "register_operand" "f")]
2535 UNSPEC_MSA_SUBS_U))]
2536 "ISA_HAS_MSA"
2537 "subs_u.<msafmt>\t%w0,%w1,%w2"
2538 [(set_attr "type" "simd_int_arith")
2539 (set_attr "mode" "<MODE>")])
2541 (define_insn "msa_subsuu_s_<msafmt>"
2542 [(set (match_operand:IMSA 0 "register_operand" "=f")
2543 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2544 (match_operand:IMSA 2 "register_operand" "f")]
2545 UNSPEC_MSA_SUBSUU_S))]
2546 "ISA_HAS_MSA"
2547 "subsuu_s.<msafmt>\t%w0,%w1,%w2"
2548 [(set_attr "type" "simd_int_arith")
2549 (set_attr "mode" "<MODE>")])
2551 (define_insn "msa_subsus_u_<msafmt>"
2552 [(set (match_operand:IMSA 0 "register_operand" "=f")
2553 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2554 (match_operand:IMSA 2 "register_operand" "f")]
2555 UNSPEC_MSA_SUBSUS_U))]
2556 "ISA_HAS_MSA"
2557 "subsus_u.<msafmt>\t%w0,%w1,%w2"
2558 [(set_attr "type" "simd_int_arith")
2559 (set_attr "mode" "<MODE>")])
2561 (define_insn "msa_sld_<msafmt_f>"
2562 [(set (match_operand:MSA 0 "register_operand" "=f")
2563 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0")
2564 (match_operand:MSA 2 "register_operand" "f")
2565 (match_operand:SI 3 "reg_or_0_operand" "dJ")]
2566 UNSPEC_MSA_SLD))]
2567 "ISA_HAS_MSA"
2568 "sld.<msafmt>\t%w0,%w2[%z3]"
2569 [(set_attr "type" "simd_sld")
2570 (set_attr "mode" "<MODE>")])
2572 (define_insn "msa_sldi_<msafmt_f>"
2573 [(set (match_operand:MSA 0 "register_operand" "=f")
2574 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0")
2575 (match_operand:MSA 2 "register_operand" "f")
2576 (match_operand 3 "const_<indeximm>_operand" "")]
2577 UNSPEC_MSA_SLDI))]
2578 "ISA_HAS_MSA"
2579 "sldi.<msafmt>\t%w0,%w2[%3]"
2580 [(set_attr "type" "simd_sld")
2581 (set_attr "mode" "<MODE>")])
2583 (define_insn "msa_splat_<msafmt_f>"
2584 [(set (match_operand:MSA 0 "register_operand" "=f")
2585 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f")
2586 (match_operand:SI 2 "register_operand" "d")]
2587 UNSPEC_MSA_SPLAT))]
2588 "ISA_HAS_MSA"
2589 "splat.<msafmt>\t%w0,%w1[%z2]"
2590 [(set_attr "type" "simd_splat")
2591 (set_attr "mode" "<MODE>")])
2593 (define_insn "msa_splati_<msafmt_f>"
2594 [(set (match_operand:MSA 0 "register_operand" "=f")
2595 (vec_duplicate:MSA
2596 (vec_select:<UNITMODE>
2597 (match_operand:MSA 1 "register_operand" "f")
2598 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
2599 "ISA_HAS_MSA"
2600 "splati.<msafmt>\t%w0,%w1[%2]"
2601 [(set_attr "type" "simd_splat")
2602 (set_attr "mode" "<MODE>")])
2604 (define_insn "msa_splati_<msafmt_f>_scalar"
2605 [(set (match_operand:FMSA 0 "register_operand" "=f")
2606 (unspec:FMSA [(match_operand:<UNITMODE> 1 "register_operand" "f")]
2607 UNSPEC_MSA_SPLATI))]
2608 "ISA_HAS_MSA"
2609 "splati.<msafmt>\t%w0,%w1[0]"
2610 [(set_attr "type" "simd_splat")
2611 (set_attr "mode" "<MODE>")])
2613 (define_insn "msa_cfcmsa"
2614 [(set (match_operand:SI 0 "register_operand" "=d")
2615 (unspec_volatile:SI [(match_operand 1 "const_uimm5_operand" "")]
2616 UNSPEC_MSA_CFCMSA))]
2617 "ISA_HAS_MSA"
2618 "cfcmsa\t%0,$%1"
2619 [(set_attr "type" "simd_cmsa")
2620 (set_attr "mode" "SI")])
2622 (define_insn "msa_ctcmsa"
2623 [(unspec_volatile [(match_operand 0 "const_uimm5_operand" "")
2624 (match_operand:SI 1 "register_operand" "d")]
2625 UNSPEC_MSA_CTCMSA)]
2626 "ISA_HAS_MSA"
2627 "ctcmsa\t$%0,%1"
2628 [(set_attr "type" "simd_cmsa")
2629 (set_attr "mode" "SI")])
2631 (define_insn "msa_fexdo_h"
2632 [(set (match_operand:V8HI 0 "register_operand" "=f")
2633 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
2634 (match_operand:V4SF 2 "register_operand" "f")]
2635 UNSPEC_MSA_FEXDO))]
2636 "ISA_HAS_MSA"
2637 "fexdo.h\t%w0,%w1,%w2"
2638 [(set_attr "type" "simd_fcvt")
2639 (set_attr "mode" "V8HI")])
2641 (define_insn "vec_pack_trunc_v2df"
2642 [(set (match_operand:V4SF 0 "register_operand" "=f")
2643 (vec_concat:V4SF
2644 (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f"))
2645 (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))]
2646 "ISA_HAS_MSA"
2647 "fexdo.w\t%w0,%w2,%w1"
2648 [(set_attr "type" "simd_fcvt")
2649 (set_attr "mode" "V4SF")])
2651 (define_insn "msa_fexupl_w"
2652 [(set (match_operand:V4SF 0 "register_operand" "=f")
2653 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2654 UNSPEC_MSA_FEXUPL))]
2655 "ISA_HAS_MSA"
2656 "fexupl.w\t%w0,%w1"
2657 [(set_attr "type" "simd_fcvt")
2658 (set_attr "mode" "V4SF")])
2660 (define_insn "msa_fexupl_d"
2661 [(set (match_operand:V2DF 0 "register_operand" "=f")
2662 (float_extend:V2DF
2663 (vec_select:V2SF
2664 (match_operand:V4SF 1 "register_operand" "f")
2665 (parallel [(const_int 2) (const_int 3)]))))]
2666 "ISA_HAS_MSA"
2667 "fexupl.d\t%w0,%w1"
2668 [(set_attr "type" "simd_fcvt")
2669 (set_attr "mode" "V2DF")])
2671 (define_insn "msa_fexupr_w"
2672 [(set (match_operand:V4SF 0 "register_operand" "=f")
2673 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2674 UNSPEC_MSA_FEXUPR))]
2675 "ISA_HAS_MSA"
2676 "fexupr.w\t%w0,%w1"
2677 [(set_attr "type" "simd_fcvt")
2678 (set_attr "mode" "V4SF")])
2680 (define_insn "msa_fexupr_d"
2681 [(set (match_operand:V2DF 0 "register_operand" "=f")
2682 (float_extend:V2DF
2683 (vec_select:V2SF
2684 (match_operand:V4SF 1 "register_operand" "f")
2685 (parallel [(const_int 0) (const_int 1)]))))]
2686 "ISA_HAS_MSA"
2687 "fexupr.d\t%w0,%w1"
2688 [(set_attr "type" "simd_fcvt")
2689 (set_attr "mode" "V2DF")])
2691 (define_code_attr msabr
2692 [(eq "bz")
2693 (ne "bnz")])
2695 (define_code_attr msabr_neg
2696 [(eq "bnz")
2697 (ne "bz")])
2699 (define_insn "msa_<msabr>_<msafmt_f>"
2700 [(set (pc) (if_then_else
2701 (equality_op
2702 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2703 UNSPEC_MSA_BRANCH)
2704 (match_operand:SI 2 "const_0_operand"))
2705 (label_ref (match_operand 0))
2706 (pc)))]
2707 "ISA_HAS_MSA"
2708 {
2709 return mips_output_conditional_branch (insn, operands,
2710 MIPS_BRANCH ("<msabr>.<msafmt>",
2711 "%w1,%0"),
2712 MIPS_BRANCH ("<msabr_neg>.<msafmt>",
2713 "%w1,%0"));
2714 }
2715 [(set_attr "type" "simd_branch")
2716 (set_attr "mode" "<MODE>")
2717 (set_attr "compact_form" "never")])
2719 (define_insn "msa_<msabr>_v_<msafmt_f>"
2720 [(set (pc) (if_then_else
2721 (equality_op
2722 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2723 UNSPEC_MSA_BRANCH_V)
2724 (match_operand:SI 2 "const_0_operand"))
2725 (label_ref (match_operand 0))
2726 (pc)))]
2727 "ISA_HAS_MSA"
2728 {
2729 return mips_output_conditional_branch (insn, operands,
2730 MIPS_BRANCH ("<msabr>.v", "%w1,%0"),
2731 MIPS_BRANCH ("<msabr_neg>.v",
2732 "%w1,%0"));
2733 }
2734 [(set_attr "type" "simd_branch")
2735 (set_attr "mode" "TI")
2736 (set_attr "compact_form" "never")])