| blob | 93b0b6c70be010a8d35ab231e15da428345dab0c |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(STACK_POINTER_REGNUM 1)
31 (TOC_REGNUM 2)
32 (STATIC_CHAIN_REGNUM 11)
33 (HARD_FRAME_POINTER_REGNUM 31)
34 (MQ_REGNO 64)
35 (LR_REGNO 65)
36 (CTR_REGNO 66)
37 (ARG_POINTER_REGNUM 67)
38 (CR0_REGNO 68)
39 (CR1_REGNO 69)
40 (CR2_REGNO 70)
41 (CR3_REGNO 71)
42 (CR4_REGNO 72)
43 (CR5_REGNO 73)
44 (CR6_REGNO 74)
45 (CR7_REGNO 75)
46 (MAX_CR_REGNO 75)
47 (CA_REGNO 76)
48 (FIRST_ALTIVEC_REGNO 77)
49 (LAST_ALTIVEC_REGNO 108)
50 (VRSAVE_REGNO 109)
51 (VSCR_REGNO 110)
52 (SPE_ACC_REGNO 111)
53 (SPEFSCR_REGNO 112)
54 (FRAME_POINTER_REGNUM 113)
56 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
57 (TOC_SAVE_OFFSET_32BIT 20)
58 (TOC_SAVE_OFFSET_64BIT 40)
60 ; Function TOC offset in the AIX function descriptor.
61 (AIX_FUNC_DESC_TOC_32BIT 4)
62 (AIX_FUNC_DESC_TOC_64BIT 8)
64 ; Static chain offset in the AIX function descriptor.
65 (AIX_FUNC_DESC_SC_32BIT 8)
66 (AIX_FUNC_DESC_SC_64BIT 16)
67 ])
69 ;;
70 ;; UNSPEC usage
71 ;;
73 (define_c_enum "unspec"
74 [UNSPEC_FRSP ; frsp for POWER machines
75 UNSPEC_PROBE_STACK ; probe stack memory reference
76 UNSPEC_TIE ; tie stack contents and stack pointer
77 UNSPEC_TOCPTR ; address of a word pointing to the TOC
78 UNSPEC_TOC ; address of the TOC (more-or-less)
79 UNSPEC_MOVSI_GOT
80 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
81 UNSPEC_FCTIWZ
82 UNSPEC_FRIM
83 UNSPEC_FRIN
84 UNSPEC_FRIP
85 UNSPEC_FRIZ
86 UNSPEC_LD_MPIC ; load_macho_picbase
87 UNSPEC_MPIC_CORRECT ; macho_correct_pic
88 UNSPEC_TLSGD
89 UNSPEC_TLSLD
90 UNSPEC_MOVESI_FROM_CR
91 UNSPEC_MOVESI_TO_CR
92 UNSPEC_TLSDTPREL
93 UNSPEC_TLSDTPRELHA
94 UNSPEC_TLSDTPRELLO
95 UNSPEC_TLSGOTDTPREL
96 UNSPEC_TLSTPREL
97 UNSPEC_TLSTPRELHA
98 UNSPEC_TLSTPRELLO
99 UNSPEC_TLSGOTTPREL
100 UNSPEC_TLSTLS
101 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
102 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
103 UNSPEC_STFIWX
104 UNSPEC_POPCNTB
105 UNSPEC_FRES
106 UNSPEC_SP_SET
107 UNSPEC_SP_TEST
108 UNSPEC_SYNC
109 UNSPEC_SYNC_OP
110 UNSPEC_ATOMIC
111 UNSPEC_CMPXCHG
112 UNSPEC_XCHG
113 UNSPEC_AND
114 UNSPEC_DLMZB
115 UNSPEC_DLMZB_CR
116 UNSPEC_DLMZB_STRLEN
117 UNSPEC_RSQRT
118 UNSPEC_TOCREL
119 UNSPEC_MACHOPIC_OFFSET
120 UNSPEC_BPERM
121 UNSPEC_COPYSIGN
122 UNSPEC_PARITY
123 UNSPEC_FCTIW
124 UNSPEC_FCTID
125 UNSPEC_LFIWAX
126 UNSPEC_LFIWZX
127 UNSPEC_FCTIWUZ
128 ])
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
134 (define_c_enum "unspecv"
135 [UNSPECV_BLOCK
136 UNSPECV_LL ; load-locked
137 UNSPECV_SC ; store-conditional
138 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
139 UNSPECV_EH_RR ; eh_reg_restore
140 UNSPECV_ISYNC ; isync instruction
141 UNSPECV_LWSYNC ; lwsync
142 ])
144 \f
145 ;; Define an insn type attribute. This is used in function unit delay
146 ;; computations.
147 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
148 (const_string "integer"))
150 ;; Define floating point instruction sub-types for use with Xfpu.md
151 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
153 ;; Length (in bytes).
154 ; '(pc)' in the following doesn't include the instruction itself; it is
155 ; calculated as if the instruction had zero size.
156 (define_attr "length" ""
157 (if_then_else (eq_attr "type" "branch")
158 (if_then_else (and (ge (minus (match_dup 0) (pc))
159 (const_int -32768))
160 (lt (minus (match_dup 0) (pc))
161 (const_int 32764)))
162 (const_int 4)
163 (const_int 8))
164 (const_int 4)))
166 ;; Processor type -- this attribute must exactly match the processor_type
167 ;; enumeration in rs6000.h.
169 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
170 (const (symbol_ref "rs6000_cpu_attr")))
173 ;; If this instruction is microcoded on the CELL processor
174 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
175 (define_attr "cell_micro" "not,conditional,always"
176 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
177 (const_string "always")
178 (const_string "not")))
180 (automata_option "ndfa")
182 (include "rios1.md")
183 (include "rios2.md")
184 (include "rs64.md")
185 (include "mpc.md")
186 (include "40x.md")
187 (include "440.md")
188 (include "476.md")
189 (include "603.md")
190 (include "6xx.md")
191 (include "7xx.md")
192 (include "7450.md")
193 (include "8540.md")
194 (include "e300c2c3.md")
195 (include "e500mc.md")
196 (include "e500mc64.md")
197 (include "power4.md")
198 (include "power5.md")
199 (include "power6.md")
200 (include "power7.md")
201 (include "cell.md")
202 (include "xfpu.md")
203 (include "a2.md")
204 (include "titan.md")
206 (include "predicates.md")
207 (include "constraints.md")
209 (include "darwin.md")
211 \f
212 ;; Mode iterators
214 ; This mode iterator allows :GPR to be used to indicate the allowable size
215 ; of whole values in GPRs.
216 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
218 ; Any supported integer mode.
219 (define_mode_iterator INT [QI HI SI DI TI])
221 ; Any supported integer mode that fits in one register.
222 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
224 ; extend modes for DImode
225 (define_mode_iterator QHSI [QI HI SI])
227 ; SImode or DImode, even if DImode doesn't fit in GPRs.
228 (define_mode_iterator SDI [SI DI])
230 ; The size of a pointer. Also, the size of the value that a record-condition
231 ; (one with a '.') will compare; and the size used for arithmetic carries.
232 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
234 ; Any hardware-supported floating-point mode
235 (define_mode_iterator FP [
236 (SF "TARGET_HARD_FLOAT
237 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
238 (DF "TARGET_HARD_FLOAT
239 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
240 (TF "!TARGET_IEEEQUAD
241 && TARGET_HARD_FLOAT
242 && (TARGET_FPRS || TARGET_E500_DOUBLE)
243 && TARGET_LONG_DOUBLE_128")
244 (DD "TARGET_DFP")
245 (TD "TARGET_DFP")])
247 ; Any fma capable floating-point mode.
248 (define_mode_iterator FMA_F [
249 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
250 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
251 || VECTOR_UNIT_VSX_P (DFmode)")
252 (V2SF "TARGET_PAIRED_FLOAT")
253 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
254 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
255 ])
257 ; These modes do not fit in integer registers in 32-bit mode.
258 ; but on e500v2, the gpr are 64 bit registers
259 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
261 ; Iterator for reciprocal estimate instructions
262 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
264 ; Iterator for just SF/DF
265 (define_mode_iterator SFDF [SF DF])
267 ; Conditional returns.
268 (define_code_iterator any_return [return simple_return])
269 (define_code_attr return_pred [(return "direct_return ()")
270 (simple_return "")])
271 (define_code_attr return_str [(return "") (simple_return "simple_")])
273 ; Various instructions that come in SI and DI forms.
274 ; A generic w/d attribute, for things like cmpw/cmpd.
275 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
277 ; DImode bits
278 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
280 ;; ISEL/ISEL64 target selection
281 (define_mode_attr sel [(SI "") (DI "64")])
283 ;; Suffix for reload patterns
284 (define_mode_attr ptrsize [(SI "32bit")
285 (DI "64bit")])
287 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
288 (DI "TARGET_64BIT")])
290 (define_mode_attr mptrsize [(SI "si")
291 (DI "di")])
293 (define_mode_attr ptrload [(SI "{l|lwz}")
294 (DI "ld")])
296 (define_mode_attr rreg [(SF "f")
297 (DF "ws")
298 (V4SF "wf")
299 (V2DF "wd")])
301 (define_mode_attr rreg2 [(SF "f")
302 (DF "d")])
304 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
305 (DF "TARGET_FCFID")])
307 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
308 (DF "TARGET_E500_DOUBLE")])
310 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
311 (DF "TARGET_DOUBLE_FLOAT")])
312 \f
313 ;; Start with fixed-point load and store insns. Here we put only the more
314 ;; complex forms. Basic data transfer is done later.
316 (define_expand "zero_extend<mode>di2"
317 [(set (match_operand:DI 0 "gpc_reg_operand" "")
318 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
319 "TARGET_POWERPC64"
320 "")
322 (define_insn "*zero_extend<mode>di2_internal1"
323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
324 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
325 "TARGET_POWERPC64"
326 "@
327 l<wd>z%U1%X1 %0,%1
328 rldicl %0,%1,0,<dbits>"
329 [(set_attr "type" "load,*")])
331 (define_insn "*zero_extend<mode>di2_internal2"
332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
333 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
334 (const_int 0)))
335 (clobber (match_scratch:DI 2 "=r,r"))]
336 "TARGET_64BIT"
337 "@
338 rldicl. %2,%1,0,<dbits>
339 #"
340 [(set_attr "type" "compare")
341 (set_attr "length" "4,8")])
343 (define_split
344 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
345 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
346 (const_int 0)))
347 (clobber (match_scratch:DI 2 ""))]
348 "TARGET_POWERPC64 && reload_completed"
349 [(set (match_dup 2)
350 (zero_extend:DI (match_dup 1)))
351 (set (match_dup 0)
352 (compare:CC (match_dup 2)
353 (const_int 0)))]
354 "")
356 (define_insn "*zero_extend<mode>di2_internal3"
357 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
358 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
359 (const_int 0)))
360 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
361 (zero_extend:DI (match_dup 1)))]
362 "TARGET_64BIT"
363 "@
364 rldicl. %0,%1,0,<dbits>
365 #"
366 [(set_attr "type" "compare")
367 (set_attr "length" "4,8")])
369 (define_split
370 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
371 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
372 (const_int 0)))
373 (set (match_operand:DI 0 "gpc_reg_operand" "")
374 (zero_extend:DI (match_dup 1)))]
375 "TARGET_POWERPC64 && reload_completed"
376 [(set (match_dup 0)
377 (zero_extend:DI (match_dup 1)))
378 (set (match_dup 2)
379 (compare:CC (match_dup 0)
380 (const_int 0)))]
381 "")
383 (define_insn "extendqidi2"
384 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
385 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
386 "TARGET_POWERPC64"
387 "extsb %0,%1"
388 [(set_attr "type" "exts")])
390 (define_insn ""
391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
392 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
393 (const_int 0)))
394 (clobber (match_scratch:DI 2 "=r,r"))]
395 "TARGET_64BIT"
396 "@
397 extsb. %2,%1
398 #"
399 [(set_attr "type" "compare")
400 (set_attr "length" "4,8")])
402 (define_split
403 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
404 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
405 (const_int 0)))
406 (clobber (match_scratch:DI 2 ""))]
407 "TARGET_POWERPC64 && reload_completed"
408 [(set (match_dup 2)
409 (sign_extend:DI (match_dup 1)))
410 (set (match_dup 0)
411 (compare:CC (match_dup 2)
412 (const_int 0)))]
413 "")
415 (define_insn ""
416 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
417 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
418 (const_int 0)))
419 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
420 (sign_extend:DI (match_dup 1)))]
421 "TARGET_64BIT"
422 "@
423 extsb. %0,%1
424 #"
425 [(set_attr "type" "compare")
426 (set_attr "length" "4,8")])
428 (define_split
429 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
430 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
431 (const_int 0)))
432 (set (match_operand:DI 0 "gpc_reg_operand" "")
433 (sign_extend:DI (match_dup 1)))]
434 "TARGET_POWERPC64 && reload_completed"
435 [(set (match_dup 0)
436 (sign_extend:DI (match_dup 1)))
437 (set (match_dup 2)
438 (compare:CC (match_dup 0)
439 (const_int 0)))]
440 "")
442 (define_expand "extendhidi2"
443 [(set (match_operand:DI 0 "gpc_reg_operand" "")
444 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
445 "TARGET_POWERPC64"
446 "")
448 (define_insn ""
449 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
450 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
451 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
452 "@
453 lha%U1%X1 %0,%1
454 extsh %0,%1"
455 [(set_attr "type" "load_ext,exts")])
457 (define_insn ""
458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
459 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
460 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
461 "extsh %0,%1"
462 [(set_attr "type" "exts")])
464 (define_insn ""
465 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
466 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
467 (const_int 0)))
468 (clobber (match_scratch:DI 2 "=r,r"))]
469 "TARGET_64BIT"
470 "@
471 extsh. %2,%1
472 #"
473 [(set_attr "type" "compare")
474 (set_attr "length" "4,8")])
476 (define_split
477 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
478 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
479 (const_int 0)))
480 (clobber (match_scratch:DI 2 ""))]
481 "TARGET_POWERPC64 && reload_completed"
482 [(set (match_dup 2)
483 (sign_extend:DI (match_dup 1)))
484 (set (match_dup 0)
485 (compare:CC (match_dup 2)
486 (const_int 0)))]
487 "")
489 (define_insn ""
490 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
491 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
492 (const_int 0)))
493 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
494 (sign_extend:DI (match_dup 1)))]
495 "TARGET_64BIT"
496 "@
497 extsh. %0,%1
498 #"
499 [(set_attr "type" "compare")
500 (set_attr "length" "4,8")])
502 (define_split
503 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
504 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
505 (const_int 0)))
506 (set (match_operand:DI 0 "gpc_reg_operand" "")
507 (sign_extend:DI (match_dup 1)))]
508 "TARGET_POWERPC64 && reload_completed"
509 [(set (match_dup 0)
510 (sign_extend:DI (match_dup 1)))
511 (set (match_dup 2)
512 (compare:CC (match_dup 0)
513 (const_int 0)))]
514 "")
516 (define_expand "extendsidi2"
517 [(set (match_operand:DI 0 "gpc_reg_operand" "")
518 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
519 "TARGET_POWERPC64"
520 "")
522 (define_insn ""
523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
524 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
525 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
526 "@
527 lwa%U1%X1 %0,%1
528 extsw %0,%1"
529 [(set_attr "type" "load_ext,exts")])
531 (define_insn ""
532 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
533 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
534 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
535 "extsw %0,%1"
536 [(set_attr "type" "exts")])
538 (define_insn ""
539 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
540 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
541 (const_int 0)))
542 (clobber (match_scratch:DI 2 "=r,r"))]
543 "TARGET_64BIT"
544 "@
545 extsw. %2,%1
546 #"
547 [(set_attr "type" "compare")
548 (set_attr "length" "4,8")])
550 (define_split
551 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
552 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
553 (const_int 0)))
554 (clobber (match_scratch:DI 2 ""))]
555 "TARGET_POWERPC64 && reload_completed"
556 [(set (match_dup 2)
557 (sign_extend:DI (match_dup 1)))
558 (set (match_dup 0)
559 (compare:CC (match_dup 2)
560 (const_int 0)))]
561 "")
563 (define_insn ""
564 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
565 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
566 (const_int 0)))
567 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
568 (sign_extend:DI (match_dup 1)))]
569 "TARGET_64BIT"
570 "@
571 extsw. %0,%1
572 #"
573 [(set_attr "type" "compare")
574 (set_attr "length" "4,8")])
576 (define_split
577 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
578 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
579 (const_int 0)))
580 (set (match_operand:DI 0 "gpc_reg_operand" "")
581 (sign_extend:DI (match_dup 1)))]
582 "TARGET_POWERPC64 && reload_completed"
583 [(set (match_dup 0)
584 (sign_extend:DI (match_dup 1)))
585 (set (match_dup 2)
586 (compare:CC (match_dup 0)
587 (const_int 0)))]
588 "")
590 (define_expand "zero_extendqisi2"
591 [(set (match_operand:SI 0 "gpc_reg_operand" "")
592 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
593 ""
594 "")
596 (define_insn ""
597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
598 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
599 ""
600 "@
601 lbz%U1%X1 %0,%1
602 {rlinm|rlwinm} %0,%1,0,0xff"
603 [(set_attr "type" "load,*")])
605 (define_insn ""
606 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
607 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
608 (const_int 0)))
609 (clobber (match_scratch:SI 2 "=r,r"))]
610 ""
611 "@
612 {andil.|andi.} %2,%1,0xff
613 #"
614 [(set_attr "type" "fast_compare,compare")
615 (set_attr "length" "4,8")])
617 (define_split
618 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
619 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
620 (const_int 0)))
621 (clobber (match_scratch:SI 2 ""))]
622 "reload_completed"
623 [(set (match_dup 2)
624 (zero_extend:SI (match_dup 1)))
625 (set (match_dup 0)
626 (compare:CC (match_dup 2)
627 (const_int 0)))]
628 "")
630 (define_insn ""
631 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
632 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
633 (const_int 0)))
634 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
635 (zero_extend:SI (match_dup 1)))]
636 ""
637 "@
638 {andil.|andi.} %0,%1,0xff
639 #"
640 [(set_attr "type" "fast_compare,compare")
641 (set_attr "length" "4,8")])
643 (define_split
644 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
645 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
646 (const_int 0)))
647 (set (match_operand:SI 0 "gpc_reg_operand" "")
648 (zero_extend:SI (match_dup 1)))]
649 "reload_completed"
650 [(set (match_dup 0)
651 (zero_extend:SI (match_dup 1)))
652 (set (match_dup 2)
653 (compare:CC (match_dup 0)
654 (const_int 0)))]
655 "")
657 (define_expand "extendqisi2"
658 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
659 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
660 ""
661 "
662 {
663 if (TARGET_POWERPC)
664 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
665 else if (TARGET_POWER)
666 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
667 else
668 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
669 DONE;
670 }")
672 (define_insn "extendqisi2_ppc"
673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
674 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
675 "TARGET_POWERPC"
676 "extsb %0,%1"
677 [(set_attr "type" "exts")])
679 (define_insn ""
680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
681 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
682 (const_int 0)))
683 (clobber (match_scratch:SI 2 "=r,r"))]
684 "TARGET_POWERPC"
685 "@
686 extsb. %2,%1
687 #"
688 [(set_attr "type" "compare")
689 (set_attr "length" "4,8")])
691 (define_split
692 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
693 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
694 (const_int 0)))
695 (clobber (match_scratch:SI 2 ""))]
696 "TARGET_POWERPC && reload_completed"
697 [(set (match_dup 2)
698 (sign_extend:SI (match_dup 1)))
699 (set (match_dup 0)
700 (compare:CC (match_dup 2)
701 (const_int 0)))]
702 "")
704 (define_insn ""
705 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
706 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
707 (const_int 0)))
708 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
709 (sign_extend:SI (match_dup 1)))]
710 "TARGET_POWERPC"
711 "@
712 extsb. %0,%1
713 #"
714 [(set_attr "type" "compare")
715 (set_attr "length" "4,8")])
717 (define_split
718 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
719 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
720 (const_int 0)))
721 (set (match_operand:SI 0 "gpc_reg_operand" "")
722 (sign_extend:SI (match_dup 1)))]
723 "TARGET_POWERPC && reload_completed"
724 [(set (match_dup 0)
725 (sign_extend:SI (match_dup 1)))
726 (set (match_dup 2)
727 (compare:CC (match_dup 0)
728 (const_int 0)))]
729 "")
731 (define_expand "extendqisi2_power"
732 [(parallel [(set (match_dup 2)
733 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
734 (const_int 24)))
735 (clobber (scratch:SI))])
736 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
737 (ashiftrt:SI (match_dup 2)
738 (const_int 24)))
739 (clobber (scratch:SI))])]
740 "TARGET_POWER"
741 "
742 { operands[1] = gen_lowpart (SImode, operands[1]);
743 operands[2] = gen_reg_rtx (SImode); }")
745 (define_expand "extendqisi2_no_power"
746 [(set (match_dup 2)
747 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
748 (const_int 24)))
749 (set (match_operand:SI 0 "gpc_reg_operand" "")
750 (ashiftrt:SI (match_dup 2)
751 (const_int 24)))]
752 "! TARGET_POWER && ! TARGET_POWERPC"
753 "
754 { operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
757 (define_expand "zero_extendqihi2"
758 [(set (match_operand:HI 0 "gpc_reg_operand" "")
759 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
760 ""
761 "")
763 (define_insn ""
764 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
765 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
766 ""
767 "@
768 lbz%U1%X1 %0,%1
769 {rlinm|rlwinm} %0,%1,0,0xff"
770 [(set_attr "type" "load,*")])
772 (define_insn ""
773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
774 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
775 (const_int 0)))
776 (clobber (match_scratch:HI 2 "=r,r"))]
777 ""
778 "@
779 {andil.|andi.} %2,%1,0xff
780 #"
781 [(set_attr "type" "fast_compare,compare")
782 (set_attr "length" "4,8")])
784 (define_split
785 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
786 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
787 (const_int 0)))
788 (clobber (match_scratch:HI 2 ""))]
789 "reload_completed"
790 [(set (match_dup 2)
791 (zero_extend:HI (match_dup 1)))
792 (set (match_dup 0)
793 (compare:CC (match_dup 2)
794 (const_int 0)))]
795 "")
797 (define_insn ""
798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
800 (const_int 0)))
801 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
802 (zero_extend:HI (match_dup 1)))]
803 ""
804 "@
805 {andil.|andi.} %0,%1,0xff
806 #"
807 [(set_attr "type" "fast_compare,compare")
808 (set_attr "length" "4,8")])
810 (define_split
811 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
812 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
813 (const_int 0)))
814 (set (match_operand:HI 0 "gpc_reg_operand" "")
815 (zero_extend:HI (match_dup 1)))]
816 "reload_completed"
817 [(set (match_dup 0)
818 (zero_extend:HI (match_dup 1)))
819 (set (match_dup 2)
820 (compare:CC (match_dup 0)
821 (const_int 0)))]
822 "")
824 (define_expand "extendqihi2"
825 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
826 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
827 ""
828 "
829 {
830 if (TARGET_POWERPC)
831 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
832 else if (TARGET_POWER)
833 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
834 else
835 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
836 DONE;
837 }")
839 (define_insn "extendqihi2_ppc"
840 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
841 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
842 "TARGET_POWERPC"
843 "extsb %0,%1"
844 [(set_attr "type" "exts")])
846 (define_insn ""
847 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
848 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
849 (const_int 0)))
850 (clobber (match_scratch:HI 2 "=r,r"))]
851 "TARGET_POWERPC"
852 "@
853 extsb. %2,%1
854 #"
855 [(set_attr "type" "compare")
856 (set_attr "length" "4,8")])
858 (define_split
859 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
860 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
861 (const_int 0)))
862 (clobber (match_scratch:HI 2 ""))]
863 "TARGET_POWERPC && reload_completed"
864 [(set (match_dup 2)
865 (sign_extend:HI (match_dup 1)))
866 (set (match_dup 0)
867 (compare:CC (match_dup 2)
868 (const_int 0)))]
869 "")
871 (define_insn ""
872 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
873 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
874 (const_int 0)))
875 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
876 (sign_extend:HI (match_dup 1)))]
877 "TARGET_POWERPC"
878 "@
879 extsb. %0,%1
880 #"
881 [(set_attr "type" "compare")
882 (set_attr "length" "4,8")])
884 (define_split
885 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
886 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
887 (const_int 0)))
888 (set (match_operand:HI 0 "gpc_reg_operand" "")
889 (sign_extend:HI (match_dup 1)))]
890 "TARGET_POWERPC && reload_completed"
891 [(set (match_dup 0)
892 (sign_extend:HI (match_dup 1)))
893 (set (match_dup 2)
894 (compare:CC (match_dup 0)
895 (const_int 0)))]
896 "")
898 (define_expand "extendqihi2_power"
899 [(parallel [(set (match_dup 2)
900 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
901 (const_int 24)))
902 (clobber (scratch:SI))])
903 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
904 (ashiftrt:SI (match_dup 2)
905 (const_int 24)))
906 (clobber (scratch:SI))])]
907 "TARGET_POWER"
908 "
909 { operands[0] = gen_lowpart (SImode, operands[0]);
910 operands[1] = gen_lowpart (SImode, operands[1]);
911 operands[2] = gen_reg_rtx (SImode); }")
913 (define_expand "extendqihi2_no_power"
914 [(set (match_dup 2)
915 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
916 (const_int 24)))
917 (set (match_operand:HI 0 "gpc_reg_operand" "")
918 (ashiftrt:SI (match_dup 2)
919 (const_int 24)))]
920 "! TARGET_POWER && ! TARGET_POWERPC"
921 "
922 { operands[0] = gen_lowpart (SImode, operands[0]);
923 operands[1] = gen_lowpart (SImode, operands[1]);
924 operands[2] = gen_reg_rtx (SImode); }")
926 (define_expand "zero_extendhisi2"
927 [(set (match_operand:SI 0 "gpc_reg_operand" "")
928 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
929 ""
930 "")
932 (define_insn ""
933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
934 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
935 ""
936 "@
937 lhz%U1%X1 %0,%1
938 {rlinm|rlwinm} %0,%1,0,0xffff"
939 [(set_attr "type" "load,*")])
941 (define_insn ""
942 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
943 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
944 (const_int 0)))
945 (clobber (match_scratch:SI 2 "=r,r"))]
946 ""
947 "@
948 {andil.|andi.} %2,%1,0xffff
949 #"
950 [(set_attr "type" "fast_compare,compare")
951 (set_attr "length" "4,8")])
953 (define_split
954 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
955 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
956 (const_int 0)))
957 (clobber (match_scratch:SI 2 ""))]
958 "reload_completed"
959 [(set (match_dup 2)
960 (zero_extend:SI (match_dup 1)))
961 (set (match_dup 0)
962 (compare:CC (match_dup 2)
963 (const_int 0)))]
964 "")
966 (define_insn ""
967 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
968 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
969 (const_int 0)))
970 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
971 (zero_extend:SI (match_dup 1)))]
972 ""
973 "@
974 {andil.|andi.} %0,%1,0xffff
975 #"
976 [(set_attr "type" "fast_compare,compare")
977 (set_attr "length" "4,8")])
979 (define_split
980 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
981 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
982 (const_int 0)))
983 (set (match_operand:SI 0 "gpc_reg_operand" "")
984 (zero_extend:SI (match_dup 1)))]
985 "reload_completed"
986 [(set (match_dup 0)
987 (zero_extend:SI (match_dup 1)))
988 (set (match_dup 2)
989 (compare:CC (match_dup 0)
990 (const_int 0)))]
991 "")
993 (define_expand "extendhisi2"
994 [(set (match_operand:SI 0 "gpc_reg_operand" "")
995 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
996 ""
997 "")
999 (define_insn ""
1000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1001 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1002 "rs6000_gen_cell_microcode"
1003 "@
1004 lha%U1%X1 %0,%1
1005 {exts|extsh} %0,%1"
1006 [(set_attr "type" "load_ext,exts")])
1008 (define_insn ""
1009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1010 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1011 "!rs6000_gen_cell_microcode"
1012 "{exts|extsh} %0,%1"
1013 [(set_attr "type" "exts")])
1015 (define_insn ""
1016 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1017 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1018 (const_int 0)))
1019 (clobber (match_scratch:SI 2 "=r,r"))]
1020 ""
1021 "@
1022 {exts.|extsh.} %2,%1
1023 #"
1024 [(set_attr "type" "compare")
1025 (set_attr "length" "4,8")])
1027 (define_split
1028 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1029 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1030 (const_int 0)))
1031 (clobber (match_scratch:SI 2 ""))]
1032 "reload_completed"
1033 [(set (match_dup 2)
1034 (sign_extend:SI (match_dup 1)))
1035 (set (match_dup 0)
1036 (compare:CC (match_dup 2)
1037 (const_int 0)))]
1038 "")
1040 (define_insn ""
1041 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1042 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1043 (const_int 0)))
1044 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1045 (sign_extend:SI (match_dup 1)))]
1046 ""
1047 "@
1048 {exts.|extsh.} %0,%1
1049 #"
1050 [(set_attr "type" "compare")
1051 (set_attr "length" "4,8")])
1052 \f
1053 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1055 (define_insn "*macchwc"
1056 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1057 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1058 (match_operand:SI 2 "gpc_reg_operand" "r")
1059 (const_int 16))
1060 (sign_extend:SI
1061 (match_operand:HI 1 "gpc_reg_operand" "r")))
1062 (match_operand:SI 4 "gpc_reg_operand" "0"))
1063 (const_int 0)))
1064 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1065 (plus:SI (mult:SI (ashiftrt:SI
1066 (match_dup 2)
1067 (const_int 16))
1068 (sign_extend:SI
1069 (match_dup 1)))
1070 (match_dup 4)))]
1071 "TARGET_MULHW"
1072 "macchw. %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1075 (define_insn "*macchw"
1076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1077 (plus:SI (mult:SI (ashiftrt:SI
1078 (match_operand:SI 2 "gpc_reg_operand" "r")
1079 (const_int 16))
1080 (sign_extend:SI
1081 (match_operand:HI 1 "gpc_reg_operand" "r")))
1082 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1083 "TARGET_MULHW"
1084 "macchw %0, %1, %2"
1085 [(set_attr "type" "imul3")])
1087 (define_insn "*macchwuc"
1088 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1089 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1090 (match_operand:SI 2 "gpc_reg_operand" "r")
1091 (const_int 16))
1092 (zero_extend:SI
1093 (match_operand:HI 1 "gpc_reg_operand" "r")))
1094 (match_operand:SI 4 "gpc_reg_operand" "0"))
1095 (const_int 0)))
1096 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1097 (plus:SI (mult:SI (lshiftrt:SI
1098 (match_dup 2)
1099 (const_int 16))
1100 (zero_extend:SI
1101 (match_dup 1)))
1102 (match_dup 4)))]
1103 "TARGET_MULHW"
1104 "macchwu. %0, %1, %2"
1105 [(set_attr "type" "imul3")])
1107 (define_insn "*macchwu"
1108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1109 (plus:SI (mult:SI (lshiftrt:SI
1110 (match_operand:SI 2 "gpc_reg_operand" "r")
1111 (const_int 16))
1112 (zero_extend:SI
1113 (match_operand:HI 1 "gpc_reg_operand" "r")))
1114 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1115 "TARGET_MULHW"
1116 "macchwu %0, %1, %2"
1117 [(set_attr "type" "imul3")])
1119 (define_insn "*machhwc"
1120 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1121 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1122 (match_operand:SI 1 "gpc_reg_operand" "%r")
1123 (const_int 16))
1124 (ashiftrt:SI
1125 (match_operand:SI 2 "gpc_reg_operand" "r")
1126 (const_int 16)))
1127 (match_operand:SI 4 "gpc_reg_operand" "0"))
1128 (const_int 0)))
1129 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1130 (plus:SI (mult:SI (ashiftrt:SI
1131 (match_dup 1)
1132 (const_int 16))
1133 (ashiftrt:SI
1134 (match_dup 2)
1135 (const_int 16)))
1136 (match_dup 4)))]
1137 "TARGET_MULHW"
1138 "machhw. %0, %1, %2"
1139 [(set_attr "type" "imul3")])
1141 (define_insn "*machhw"
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1143 (plus:SI (mult:SI (ashiftrt:SI
1144 (match_operand:SI 1 "gpc_reg_operand" "%r")
1145 (const_int 16))
1146 (ashiftrt:SI
1147 (match_operand:SI 2 "gpc_reg_operand" "r")
1148 (const_int 16)))
1149 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1150 "TARGET_MULHW"
1151 "machhw %0, %1, %2"
1152 [(set_attr "type" "imul3")])
1154 (define_insn "*machhwuc"
1155 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1156 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1157 (match_operand:SI 1 "gpc_reg_operand" "%r")
1158 (const_int 16))
1159 (lshiftrt:SI
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1161 (const_int 16)))
1162 (match_operand:SI 4 "gpc_reg_operand" "0"))
1163 (const_int 0)))
1164 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1165 (plus:SI (mult:SI (lshiftrt:SI
1166 (match_dup 1)
1167 (const_int 16))
1168 (lshiftrt:SI
1169 (match_dup 2)
1170 (const_int 16)))
1171 (match_dup 4)))]
1172 "TARGET_MULHW"
1173 "machhwu. %0, %1, %2"
1174 [(set_attr "type" "imul3")])
1176 (define_insn "*machhwu"
1177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (plus:SI (mult:SI (lshiftrt:SI
1179 (match_operand:SI 1 "gpc_reg_operand" "%r")
1180 (const_int 16))
1181 (lshiftrt:SI
1182 (match_operand:SI 2 "gpc_reg_operand" "r")
1183 (const_int 16)))
1184 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1185 "TARGET_MULHW"
1186 "machhwu %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1189 (define_insn "*maclhwc"
1190 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1191 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1192 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1193 (sign_extend:SI
1194 (match_operand:HI 2 "gpc_reg_operand" "r")))
1195 (match_operand:SI 4 "gpc_reg_operand" "0"))
1196 (const_int 0)))
1197 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1198 (plus:SI (mult:SI (sign_extend:SI
1199 (match_dup 1))
1200 (sign_extend:SI
1201 (match_dup 2)))
1202 (match_dup 4)))]
1203 "TARGET_MULHW"
1204 "maclhw. %0, %1, %2"
1205 [(set_attr "type" "imul3")])
1207 (define_insn "*maclhw"
1208 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (plus:SI (mult:SI (sign_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1211 (sign_extend:SI
1212 (match_operand:HI 2 "gpc_reg_operand" "r")))
1213 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1214 "TARGET_MULHW"
1215 "maclhw %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1218 (define_insn "*maclhwuc"
1219 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1220 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1221 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1222 (zero_extend:SI
1223 (match_operand:HI 2 "gpc_reg_operand" "r")))
1224 (match_operand:SI 4 "gpc_reg_operand" "0"))
1225 (const_int 0)))
1226 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1227 (plus:SI (mult:SI (zero_extend:SI
1228 (match_dup 1))
1229 (zero_extend:SI
1230 (match_dup 2)))
1231 (match_dup 4)))]
1232 "TARGET_MULHW"
1233 "maclhwu. %0, %1, %2"
1234 [(set_attr "type" "imul3")])
1236 (define_insn "*maclhwu"
1237 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1238 (plus:SI (mult:SI (zero_extend:SI
1239 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1240 (zero_extend:SI
1241 (match_operand:HI 2 "gpc_reg_operand" "r")))
1242 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1243 "TARGET_MULHW"
1244 "maclhwu %0, %1, %2"
1245 [(set_attr "type" "imul3")])
1247 (define_insn "*nmacchwc"
1248 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1249 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1250 (mult:SI (ashiftrt:SI
1251 (match_operand:SI 2 "gpc_reg_operand" "r")
1252 (const_int 16))
1253 (sign_extend:SI
1254 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1255 (const_int 0)))
1256 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1257 (minus:SI (match_dup 4)
1258 (mult:SI (ashiftrt:SI
1259 (match_dup 2)
1260 (const_int 16))
1261 (sign_extend:SI
1262 (match_dup 1)))))]
1263 "TARGET_MULHW"
1264 "nmacchw. %0, %1, %2"
1265 [(set_attr "type" "imul3")])
1267 (define_insn "*nmacchw"
1268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1269 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1270 (mult:SI (ashiftrt:SI
1271 (match_operand:SI 2 "gpc_reg_operand" "r")
1272 (const_int 16))
1273 (sign_extend:SI
1274 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1275 "TARGET_MULHW"
1276 "nmacchw %0, %1, %2"
1277 [(set_attr "type" "imul3")])
1279 (define_insn "*nmachhwc"
1280 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1281 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1282 (mult:SI (ashiftrt:SI
1283 (match_operand:SI 1 "gpc_reg_operand" "%r")
1284 (const_int 16))
1285 (ashiftrt:SI
1286 (match_operand:SI 2 "gpc_reg_operand" "r")
1287 (const_int 16))))
1288 (const_int 0)))
1289 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1290 (minus:SI (match_dup 4)
1291 (mult:SI (ashiftrt:SI
1292 (match_dup 1)
1293 (const_int 16))
1294 (ashiftrt:SI
1295 (match_dup 2)
1296 (const_int 16)))))]
1297 "TARGET_MULHW"
1298 "nmachhw. %0, %1, %2"
1299 [(set_attr "type" "imul3")])
1301 (define_insn "*nmachhw"
1302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1303 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1304 (mult:SI (ashiftrt:SI
1305 (match_operand:SI 1 "gpc_reg_operand" "%r")
1306 (const_int 16))
1307 (ashiftrt:SI
1308 (match_operand:SI 2 "gpc_reg_operand" "r")
1309 (const_int 16)))))]
1310 "TARGET_MULHW"
1311 "nmachhw %0, %1, %2"
1312 [(set_attr "type" "imul3")])
1314 (define_insn "*nmaclhwc"
1315 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1316 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1317 (mult:SI (sign_extend:SI
1318 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1319 (sign_extend:SI
1320 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1321 (const_int 0)))
1322 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1323 (minus:SI (match_dup 4)
1324 (mult:SI (sign_extend:SI
1325 (match_dup 1))
1326 (sign_extend:SI
1327 (match_dup 2)))))]
1328 "TARGET_MULHW"
1329 "nmaclhw. %0, %1, %2"
1330 [(set_attr "type" "imul3")])
1332 (define_insn "*nmaclhw"
1333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1335 (mult:SI (sign_extend:SI
1336 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1337 (sign_extend:SI
1338 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1339 "TARGET_MULHW"
1340 "nmaclhw %0, %1, %2"
1341 [(set_attr "type" "imul3")])
1343 (define_insn "*mulchwc"
1344 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1345 (compare:CC (mult:SI (ashiftrt:SI
1346 (match_operand:SI 2 "gpc_reg_operand" "r")
1347 (const_int 16))
1348 (sign_extend:SI
1349 (match_operand:HI 1 "gpc_reg_operand" "r")))
1350 (const_int 0)))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1352 (mult:SI (ashiftrt:SI
1353 (match_dup 2)
1354 (const_int 16))
1355 (sign_extend:SI
1356 (match_dup 1))))]
1357 "TARGET_MULHW"
1358 "mulchw. %0, %1, %2"
1359 [(set_attr "type" "imul3")])
1361 (define_insn "*mulchw"
1362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1363 (mult:SI (ashiftrt:SI
1364 (match_operand:SI 2 "gpc_reg_operand" "r")
1365 (const_int 16))
1366 (sign_extend:SI
1367 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1368 "TARGET_MULHW"
1369 "mulchw %0, %1, %2"
1370 [(set_attr "type" "imul3")])
1372 (define_insn "*mulchwuc"
1373 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1374 (compare:CC (mult:SI (lshiftrt:SI
1375 (match_operand:SI 2 "gpc_reg_operand" "r")
1376 (const_int 16))
1377 (zero_extend:SI
1378 (match_operand:HI 1 "gpc_reg_operand" "r")))
1379 (const_int 0)))
1380 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1381 (mult:SI (lshiftrt:SI
1382 (match_dup 2)
1383 (const_int 16))
1384 (zero_extend:SI
1385 (match_dup 1))))]
1386 "TARGET_MULHW"
1387 "mulchwu. %0, %1, %2"
1388 [(set_attr "type" "imul3")])
1390 (define_insn "*mulchwu"
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (mult:SI (lshiftrt:SI
1393 (match_operand:SI 2 "gpc_reg_operand" "r")
1394 (const_int 16))
1395 (zero_extend:SI
1396 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1397 "TARGET_MULHW"
1398 "mulchwu %0, %1, %2"
1399 [(set_attr "type" "imul3")])
1401 (define_insn "*mulhhwc"
1402 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1403 (compare:CC (mult:SI (ashiftrt:SI
1404 (match_operand:SI 1 "gpc_reg_operand" "%r")
1405 (const_int 16))
1406 (ashiftrt:SI
1407 (match_operand:SI 2 "gpc_reg_operand" "r")
1408 (const_int 16)))
1409 (const_int 0)))
1410 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1411 (mult:SI (ashiftrt:SI
1412 (match_dup 1)
1413 (const_int 16))
1414 (ashiftrt:SI
1415 (match_dup 2)
1416 (const_int 16))))]
1417 "TARGET_MULHW"
1418 "mulhhw. %0, %1, %2"
1419 [(set_attr "type" "imul3")])
1421 (define_insn "*mulhhw"
1422 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1423 (mult:SI (ashiftrt:SI
1424 (match_operand:SI 1 "gpc_reg_operand" "%r")
1425 (const_int 16))
1426 (ashiftrt:SI
1427 (match_operand:SI 2 "gpc_reg_operand" "r")
1428 (const_int 16))))]
1429 "TARGET_MULHW"
1430 "mulhhw %0, %1, %2"
1431 [(set_attr "type" "imul3")])
1433 (define_insn "*mulhhwuc"
1434 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1435 (compare:CC (mult:SI (lshiftrt:SI
1436 (match_operand:SI 1 "gpc_reg_operand" "%r")
1437 (const_int 16))
1438 (lshiftrt:SI
1439 (match_operand:SI 2 "gpc_reg_operand" "r")
1440 (const_int 16)))
1441 (const_int 0)))
1442 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1443 (mult:SI (lshiftrt:SI
1444 (match_dup 1)
1445 (const_int 16))
1446 (lshiftrt:SI
1447 (match_dup 2)
1448 (const_int 16))))]
1449 "TARGET_MULHW"
1450 "mulhhwu. %0, %1, %2"
1451 [(set_attr "type" "imul3")])
1453 (define_insn "*mulhhwu"
1454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1455 (mult:SI (lshiftrt:SI
1456 (match_operand:SI 1 "gpc_reg_operand" "%r")
1457 (const_int 16))
1458 (lshiftrt:SI
1459 (match_operand:SI 2 "gpc_reg_operand" "r")
1460 (const_int 16))))]
1461 "TARGET_MULHW"
1462 "mulhhwu %0, %1, %2"
1463 [(set_attr "type" "imul3")])
1465 (define_insn "*mullhwc"
1466 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1467 (compare:CC (mult:SI (sign_extend:SI
1468 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1469 (sign_extend:SI
1470 (match_operand:HI 2 "gpc_reg_operand" "r")))
1471 (const_int 0)))
1472 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1473 (mult:SI (sign_extend:SI
1474 (match_dup 1))
1475 (sign_extend:SI
1476 (match_dup 2))))]
1477 "TARGET_MULHW"
1478 "mullhw. %0, %1, %2"
1479 [(set_attr "type" "imul3")])
1481 (define_insn "*mullhw"
1482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1483 (mult:SI (sign_extend:SI
1484 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1485 (sign_extend:SI
1486 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1487 "TARGET_MULHW"
1488 "mullhw %0, %1, %2"
1489 [(set_attr "type" "imul3")])
1491 (define_insn "*mullhwuc"
1492 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1493 (compare:CC (mult:SI (zero_extend:SI
1494 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1495 (zero_extend:SI
1496 (match_operand:HI 2 "gpc_reg_operand" "r")))
1497 (const_int 0)))
1498 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1499 (mult:SI (zero_extend:SI
1500 (match_dup 1))
1501 (zero_extend:SI
1502 (match_dup 2))))]
1503 "TARGET_MULHW"
1504 "mullhwu. %0, %1, %2"
1505 [(set_attr "type" "imul3")])
1507 (define_insn "*mullhwu"
1508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1509 (mult:SI (zero_extend:SI
1510 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1511 (zero_extend:SI
1512 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1513 "TARGET_MULHW"
1514 "mullhwu %0, %1, %2"
1515 [(set_attr "type" "imul3")])
1516 \f
1517 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1518 (define_insn "dlmzb"
1519 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1520 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1521 (match_operand:SI 2 "gpc_reg_operand" "r")]
1522 UNSPEC_DLMZB_CR))
1523 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1524 (unspec:SI [(match_dup 1)
1525 (match_dup 2)]
1526 UNSPEC_DLMZB))]
1527 "TARGET_DLMZB"
1528 "dlmzb. %0, %1, %2")
1530 (define_expand "strlensi"
1531 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1532 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1533 (match_operand:QI 2 "const_int_operand" "")
1534 (match_operand 3 "const_int_operand" "")]
1535 UNSPEC_DLMZB_STRLEN))
1536 (clobber (match_scratch:CC 4 "=x"))]
1537 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1538 {
1539 rtx result = operands[0];
1540 rtx src = operands[1];
1541 rtx search_char = operands[2];
1542 rtx align = operands[3];
1543 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1544 rtx loop_label, end_label, mem, cr0, cond;
1545 if (search_char != const0_rtx
1546 || GET_CODE (align) != CONST_INT
1547 || INTVAL (align) < 8)
1548 FAIL;
1549 word1 = gen_reg_rtx (SImode);
1550 word2 = gen_reg_rtx (SImode);
1551 scratch_dlmzb = gen_reg_rtx (SImode);
1552 scratch_string = gen_reg_rtx (Pmode);
1553 loop_label = gen_label_rtx ();
1554 end_label = gen_label_rtx ();
1555 addr = force_reg (Pmode, XEXP (src, 0));
1556 emit_move_insn (scratch_string, addr);
1557 emit_label (loop_label);
1558 mem = change_address (src, SImode, scratch_string);
1559 emit_move_insn (word1, mem);
1560 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1561 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1562 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1563 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1564 emit_jump_insn (gen_rtx_SET (VOIDmode,
1565 pc_rtx,
1566 gen_rtx_IF_THEN_ELSE (VOIDmode,
1567 cond,
1568 gen_rtx_LABEL_REF
1569 (VOIDmode,
1570 end_label),
1571 pc_rtx)));
1572 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1573 emit_jump_insn (gen_rtx_SET (VOIDmode,
1574 pc_rtx,
1575 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1576 emit_barrier ();
1577 emit_label (end_label);
1578 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1579 emit_insn (gen_subsi3 (result, scratch_string, addr));
1580 emit_insn (gen_subsi3 (result, result, const1_rtx));
1581 DONE;
1582 })
1583 \f
1584 (define_split
1585 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1586 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1587 (const_int 0)))
1588 (set (match_operand:SI 0 "gpc_reg_operand" "")
1589 (sign_extend:SI (match_dup 1)))]
1590 "reload_completed"
1591 [(set (match_dup 0)
1592 (sign_extend:SI (match_dup 1)))
1593 (set (match_dup 2)
1594 (compare:CC (match_dup 0)
1595 (const_int 0)))]
1596 "")
1598 ;; Fixed-point arithmetic insns.
1600 (define_expand "add<mode>3"
1601 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1602 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1603 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1604 ""
1605 {
1606 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1607 {
1608 if (non_short_cint_operand (operands[2], DImode))
1609 FAIL;
1610 }
1611 else if (GET_CODE (operands[2]) == CONST_INT
1612 && ! add_operand (operands[2], <MODE>mode))
1613 {
1614 rtx tmp = ((!can_create_pseudo_p ()
1615 || rtx_equal_p (operands[0], operands[1]))
1616 ? operands[0] : gen_reg_rtx (<MODE>mode));
1618 HOST_WIDE_INT val = INTVAL (operands[2]);
1619 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1620 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1622 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1623 FAIL;
1625 /* The ordering here is important for the prolog expander.
1626 When space is allocated from the stack, adding 'low' first may
1627 produce a temporary deallocation (which would be bad). */
1628 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1629 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1630 DONE;
1631 }
1632 })
1634 ;; Discourage ai/addic because of carry but provide it in an alternative
1635 ;; allowing register zero as source.
1636 (define_insn "*add<mode>3_internal1"
1637 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1638 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1639 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1640 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1641 "@
1642 {cax|add} %0,%1,%2
1643 {cal %0,%2(%1)|addi %0,%1,%2}
1644 {ai|addic} %0,%1,%2
1645 {cau|addis} %0,%1,%v2"
1646 [(set_attr "length" "4,4,4,4")])
1648 (define_insn "addsi3_high"
1649 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1650 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1651 (high:SI (match_operand 2 "" ""))))]
1652 "TARGET_MACHO && !TARGET_64BIT"
1653 "{cau|addis} %0,%1,ha16(%2)"
1654 [(set_attr "length" "4")])
1656 (define_insn "*add<mode>3_internal2"
1657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1658 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1659 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1660 (const_int 0)))
1661 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1662 ""
1663 "@
1664 {cax.|add.} %3,%1,%2
1665 {ai.|addic.} %3,%1,%2
1666 #
1667 #"
1668 [(set_attr "type" "fast_compare,compare,compare,compare")
1669 (set_attr "length" "4,4,8,8")])
1671 (define_split
1672 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1673 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1674 (match_operand:GPR 2 "reg_or_short_operand" ""))
1675 (const_int 0)))
1676 (clobber (match_scratch:GPR 3 ""))]
1677 "reload_completed"
1678 [(set (match_dup 3)
1679 (plus:GPR (match_dup 1)
1680 (match_dup 2)))
1681 (set (match_dup 0)
1682 (compare:CC (match_dup 3)
1683 (const_int 0)))]
1684 "")
1686 (define_insn "*add<mode>3_internal3"
1687 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1688 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1689 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1690 (const_int 0)))
1691 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1692 (plus:P (match_dup 1)
1693 (match_dup 2)))]
1694 ""
1695 "@
1696 {cax.|add.} %0,%1,%2
1697 {ai.|addic.} %0,%1,%2
1698 #
1699 #"
1700 [(set_attr "type" "fast_compare,compare,compare,compare")
1701 (set_attr "length" "4,4,8,8")])
1703 (define_split
1704 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1705 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1706 (match_operand:P 2 "reg_or_short_operand" ""))
1707 (const_int 0)))
1708 (set (match_operand:P 0 "gpc_reg_operand" "")
1709 (plus:P (match_dup 1) (match_dup 2)))]
1710 "reload_completed"
1711 [(set (match_dup 0)
1712 (plus:P (match_dup 1)
1713 (match_dup 2)))
1714 (set (match_dup 3)
1715 (compare:CC (match_dup 0)
1716 (const_int 0)))]
1717 "")
1719 ;; Split an add that we can't do in one insn into two insns, each of which
1720 ;; does one 16-bit part. This is used by combine. Note that the low-order
1721 ;; add should be last in case the result gets used in an address.
1723 (define_split
1724 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1725 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1726 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1727 ""
1728 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1729 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1730 {
1731 HOST_WIDE_INT val = INTVAL (operands[2]);
1732 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1733 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1735 operands[4] = GEN_INT (low);
1736 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1737 operands[3] = GEN_INT (rest);
1738 else if (can_create_pseudo_p ())
1739 {
1740 operands[3] = gen_reg_rtx (DImode);
1741 emit_move_insn (operands[3], operands[2]);
1742 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1743 DONE;
1744 }
1745 else
1746 FAIL;
1747 })
1749 (define_insn "one_cmpl<mode>2"
1750 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1751 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1752 ""
1753 "nor %0,%1,%1")
1755 (define_insn ""
1756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1757 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1758 (const_int 0)))
1759 (clobber (match_scratch:P 2 "=r,r"))]
1760 ""
1761 "@
1762 nor. %2,%1,%1
1763 #"
1764 [(set_attr "type" "fast_compare,compare")
1765 (set_attr "length" "4,8")])
1767 (define_split
1768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1769 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1770 (const_int 0)))
1771 (clobber (match_scratch:P 2 ""))]
1772 "reload_completed"
1773 [(set (match_dup 2)
1774 (not:P (match_dup 1)))
1775 (set (match_dup 0)
1776 (compare:CC (match_dup 2)
1777 (const_int 0)))]
1778 "")
1780 (define_insn ""
1781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1782 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1783 (const_int 0)))
1784 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1785 (not:P (match_dup 1)))]
1786 ""
1787 "@
1788 nor. %0,%1,%1
1789 #"
1790 [(set_attr "type" "fast_compare,compare")
1791 (set_attr "length" "4,8")])
1793 (define_split
1794 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1795 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1796 (const_int 0)))
1797 (set (match_operand:P 0 "gpc_reg_operand" "")
1798 (not:P (match_dup 1)))]
1799 "reload_completed"
1800 [(set (match_dup 0)
1801 (not:P (match_dup 1)))
1802 (set (match_dup 2)
1803 (compare:CC (match_dup 0)
1804 (const_int 0)))]
1805 "")
1807 (define_insn ""
1808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1809 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1810 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1811 "! TARGET_POWERPC"
1812 "{sf%I1|subf%I1c} %0,%2,%1")
1814 (define_insn ""
1815 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1816 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1817 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1818 "TARGET_POWERPC"
1819 "@
1820 subf %0,%2,%1
1821 subfic %0,%2,%1")
1823 (define_insn ""
1824 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1825 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1826 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1827 (const_int 0)))
1828 (clobber (match_scratch:SI 3 "=r,r"))]
1829 "! TARGET_POWERPC"
1830 "@
1831 {sf.|subfc.} %3,%2,%1
1832 #"
1833 [(set_attr "type" "compare")
1834 (set_attr "length" "4,8")])
1836 (define_insn ""
1837 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1838 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1839 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1840 (const_int 0)))
1841 (clobber (match_scratch:P 3 "=r,r"))]
1842 "TARGET_POWERPC"
1843 "@
1844 subf. %3,%2,%1
1845 #"
1846 [(set_attr "type" "fast_compare")
1847 (set_attr "length" "4,8")])
1849 (define_split
1850 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1851 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1852 (match_operand:P 2 "gpc_reg_operand" ""))
1853 (const_int 0)))
1854 (clobber (match_scratch:P 3 ""))]
1855 "reload_completed"
1856 [(set (match_dup 3)
1857 (minus:P (match_dup 1)
1858 (match_dup 2)))
1859 (set (match_dup 0)
1860 (compare:CC (match_dup 3)
1861 (const_int 0)))]
1862 "")
1864 (define_insn ""
1865 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1866 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1867 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1868 (const_int 0)))
1869 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1870 (minus:SI (match_dup 1) (match_dup 2)))]
1871 "! TARGET_POWERPC"
1872 "@
1873 {sf.|subfc.} %0,%2,%1
1874 #"
1875 [(set_attr "type" "compare")
1876 (set_attr "length" "4,8")])
1878 (define_insn ""
1879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1880 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1881 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1882 (const_int 0)))
1883 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1884 (minus:P (match_dup 1)
1885 (match_dup 2)))]
1886 "TARGET_POWERPC"
1887 "@
1888 subf. %0,%2,%1
1889 #"
1890 [(set_attr "type" "fast_compare")
1891 (set_attr "length" "4,8")])
1893 (define_split
1894 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1895 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1896 (match_operand:P 2 "gpc_reg_operand" ""))
1897 (const_int 0)))
1898 (set (match_operand:P 0 "gpc_reg_operand" "")
1899 (minus:P (match_dup 1)
1900 (match_dup 2)))]
1901 "reload_completed"
1902 [(set (match_dup 0)
1903 (minus:P (match_dup 1)
1904 (match_dup 2)))
1905 (set (match_dup 3)
1906 (compare:CC (match_dup 0)
1907 (const_int 0)))]
1908 "")
1910 (define_expand "sub<mode>3"
1911 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1912 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1913 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1914 ""
1915 "
1916 {
1917 if (GET_CODE (operands[2]) == CONST_INT)
1918 {
1919 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1920 negate_rtx (<MODE>mode, operands[2])));
1921 DONE;
1922 }
1923 }")
1925 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1926 ;; instruction and some auxiliary computations. Then we just have a single
1927 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1928 ;; combine.
1930 (define_expand "sminsi3"
1931 [(set (match_dup 3)
1932 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1933 (match_operand:SI 2 "reg_or_short_operand" ""))
1934 (const_int 0)
1935 (minus:SI (match_dup 2) (match_dup 1))))
1936 (set (match_operand:SI 0 "gpc_reg_operand" "")
1937 (minus:SI (match_dup 2) (match_dup 3)))]
1938 "TARGET_POWER || TARGET_ISEL"
1939 "
1940 {
1941 if (TARGET_ISEL)
1942 {
1943 operands[2] = force_reg (SImode, operands[2]);
1944 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1945 DONE;
1946 }
1948 operands[3] = gen_reg_rtx (SImode);
1949 }")
1951 (define_split
1952 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1953 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1954 (match_operand:SI 2 "reg_or_short_operand" "")))
1955 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1956 "TARGET_POWER"
1957 [(set (match_dup 3)
1958 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1959 (const_int 0)
1960 (minus:SI (match_dup 2) (match_dup 1))))
1961 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1962 "")
1964 (define_expand "smaxsi3"
1965 [(set (match_dup 3)
1966 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1967 (match_operand:SI 2 "reg_or_short_operand" ""))
1968 (const_int 0)
1969 (minus:SI (match_dup 2) (match_dup 1))))
1970 (set (match_operand:SI 0 "gpc_reg_operand" "")
1971 (plus:SI (match_dup 3) (match_dup 1)))]
1972 "TARGET_POWER || TARGET_ISEL"
1973 "
1974 {
1975 if (TARGET_ISEL)
1976 {
1977 operands[2] = force_reg (SImode, operands[2]);
1978 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1979 DONE;
1980 }
1981 operands[3] = gen_reg_rtx (SImode);
1982 }")
1984 (define_split
1985 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1986 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1987 (match_operand:SI 2 "reg_or_short_operand" "")))
1988 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1989 "TARGET_POWER"
1990 [(set (match_dup 3)
1991 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1992 (const_int 0)
1993 (minus:SI (match_dup 2) (match_dup 1))))
1994 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1995 "")
1997 (define_expand "uminsi3"
1998 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1999 (match_dup 5)))
2000 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2001 (match_dup 5)))
2002 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2003 (const_int 0)
2004 (minus:SI (match_dup 4) (match_dup 3))))
2005 (set (match_operand:SI 0 "gpc_reg_operand" "")
2006 (minus:SI (match_dup 2) (match_dup 3)))]
2007 "TARGET_POWER || TARGET_ISEL"
2008 "
2009 {
2010 if (TARGET_ISEL)
2011 {
2012 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
2013 DONE;
2014 }
2015 operands[3] = gen_reg_rtx (SImode);
2016 operands[4] = gen_reg_rtx (SImode);
2017 operands[5] = GEN_INT (-2147483647 - 1);
2018 }")
2020 (define_expand "umaxsi3"
2021 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2022 (match_dup 5)))
2023 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2024 (match_dup 5)))
2025 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2026 (const_int 0)
2027 (minus:SI (match_dup 4) (match_dup 3))))
2028 (set (match_operand:SI 0 "gpc_reg_operand" "")
2029 (plus:SI (match_dup 3) (match_dup 1)))]
2030 "TARGET_POWER || TARGET_ISEL"
2031 "
2032 {
2033 if (TARGET_ISEL)
2034 {
2035 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
2036 DONE;
2037 }
2038 operands[3] = gen_reg_rtx (SImode);
2039 operands[4] = gen_reg_rtx (SImode);
2040 operands[5] = GEN_INT (-2147483647 - 1);
2041 }")
2043 (define_insn ""
2044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2045 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2046 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2047 (const_int 0)
2048 (minus:SI (match_dup 2) (match_dup 1))))]
2049 "TARGET_POWER"
2050 "doz%I2 %0,%1,%2")
2052 (define_insn ""
2053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2054 (compare:CC
2055 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2056 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2057 (const_int 0)
2058 (minus:SI (match_dup 2) (match_dup 1)))
2059 (const_int 0)))
2060 (clobber (match_scratch:SI 3 "=r,r"))]
2061 "TARGET_POWER"
2062 "@
2063 doz%I2. %3,%1,%2
2064 #"
2065 [(set_attr "type" "delayed_compare")
2066 (set_attr "length" "4,8")])
2068 (define_split
2069 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2070 (compare:CC
2071 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2072 (match_operand:SI 2 "reg_or_short_operand" ""))
2073 (const_int 0)
2074 (minus:SI (match_dup 2) (match_dup 1)))
2075 (const_int 0)))
2076 (clobber (match_scratch:SI 3 ""))]
2077 "TARGET_POWER && reload_completed"
2078 [(set (match_dup 3)
2079 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2080 (const_int 0)
2081 (minus:SI (match_dup 2) (match_dup 1))))
2082 (set (match_dup 0)
2083 (compare:CC (match_dup 3)
2084 (const_int 0)))]
2085 "")
2087 (define_insn ""
2088 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2089 (compare:CC
2090 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2091 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2092 (const_int 0)
2093 (minus:SI (match_dup 2) (match_dup 1)))
2094 (const_int 0)))
2095 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2096 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2097 (const_int 0)
2098 (minus:SI (match_dup 2) (match_dup 1))))]
2099 "TARGET_POWER"
2100 "@
2101 doz%I2. %0,%1,%2
2102 #"
2103 [(set_attr "type" "delayed_compare")
2104 (set_attr "length" "4,8")])
2106 (define_split
2107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2108 (compare:CC
2109 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2110 (match_operand:SI 2 "reg_or_short_operand" ""))
2111 (const_int 0)
2112 (minus:SI (match_dup 2) (match_dup 1)))
2113 (const_int 0)))
2114 (set (match_operand:SI 0 "gpc_reg_operand" "")
2115 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2116 (const_int 0)
2117 (minus:SI (match_dup 2) (match_dup 1))))]
2118 "TARGET_POWER && reload_completed"
2119 [(set (match_dup 0)
2120 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2121 (const_int 0)
2122 (minus:SI (match_dup 2) (match_dup 1))))
2123 (set (match_dup 3)
2124 (compare:CC (match_dup 0)
2125 (const_int 0)))]
2126 "")
2128 ;; We don't need abs with condition code because such comparisons should
2129 ;; never be done.
2130 (define_expand "abssi2"
2131 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2132 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2133 ""
2134 "
2135 {
2136 if (TARGET_ISEL)
2137 {
2138 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2139 DONE;
2140 }
2141 else if (! TARGET_POWER)
2142 {
2143 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2144 DONE;
2145 }
2146 }")
2148 (define_insn "*abssi2_power"
2149 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2150 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2151 "TARGET_POWER"
2152 "abs %0,%1")
2154 (define_insn_and_split "abs<mode>2_isel"
2155 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2156 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2157 (clobber (match_scratch:GPR 2 "=&b"))
2158 (clobber (match_scratch:CC 3 "=y"))]
2159 "TARGET_ISEL"
2160 "#"
2161 "&& reload_completed"
2162 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2163 (set (match_dup 3)
2164 (compare:CC (match_dup 1)
2165 (const_int 0)))
2166 (set (match_dup 0)
2167 (if_then_else:GPR (lt (match_dup 3)
2168 (const_int 0))
2169 (match_dup 2)
2170 (match_dup 1)))]
2171 "")
2173 (define_insn_and_split "nabs<mode>2_isel"
2174 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2175 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2176 (clobber (match_scratch:GPR 2 "=&b"))
2177 (clobber (match_scratch:CC 3 "=y"))]
2178 "TARGET_ISEL"
2179 "#"
2180 "&& reload_completed"
2181 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2182 (set (match_dup 3)
2183 (compare:CC (match_dup 1)
2184 (const_int 0)))
2185 (set (match_dup 0)
2186 (if_then_else:GPR (lt (match_dup 3)
2187 (const_int 0))
2188 (match_dup 1)
2189 (match_dup 2)))]
2190 "")
2192 (define_insn_and_split "abssi2_nopower"
2193 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2194 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2195 (clobber (match_scratch:SI 2 "=&r,&r"))]
2196 "! TARGET_POWER && ! TARGET_ISEL"
2197 "#"
2198 "&& reload_completed"
2199 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2200 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2201 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2202 "")
2204 (define_insn "*nabs_power"
2205 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2206 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2207 "TARGET_POWER"
2208 "nabs %0,%1")
2210 (define_insn_and_split "*nabs_nopower"
2211 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2212 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2213 (clobber (match_scratch:SI 2 "=&r,&r"))]
2214 "! TARGET_POWER"
2215 "#"
2216 "&& reload_completed"
2217 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2218 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2219 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2220 "")
2222 (define_expand "neg<mode>2"
2223 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2224 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2225 ""
2226 "")
2228 (define_insn "*neg<mode>2_internal"
2229 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2230 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2231 ""
2232 "neg %0,%1")
2234 (define_insn ""
2235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2236 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2237 (const_int 0)))
2238 (clobber (match_scratch:P 2 "=r,r"))]
2239 ""
2240 "@
2241 neg. %2,%1
2242 #"
2243 [(set_attr "type" "fast_compare")
2244 (set_attr "length" "4,8")])
2246 (define_split
2247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2248 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2249 (const_int 0)))
2250 (clobber (match_scratch:P 2 ""))]
2251 "reload_completed"
2252 [(set (match_dup 2)
2253 (neg:P (match_dup 1)))
2254 (set (match_dup 0)
2255 (compare:CC (match_dup 2)
2256 (const_int 0)))]
2257 "")
2259 (define_insn ""
2260 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2261 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2262 (const_int 0)))
2263 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2264 (neg:P (match_dup 1)))]
2265 ""
2266 "@
2267 neg. %0,%1
2268 #"
2269 [(set_attr "type" "fast_compare")
2270 (set_attr "length" "4,8")])
2272 (define_split
2273 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2274 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2275 (const_int 0)))
2276 (set (match_operand:P 0 "gpc_reg_operand" "")
2277 (neg:P (match_dup 1)))]
2278 "reload_completed"
2279 [(set (match_dup 0)
2280 (neg:P (match_dup 1)))
2281 (set (match_dup 2)
2282 (compare:CC (match_dup 0)
2283 (const_int 0)))]
2284 "")
2286 (define_insn "clz<mode>2"
2287 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2288 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2289 ""
2290 "{cntlz|cntlz<wd>} %0,%1"
2291 [(set_attr "type" "cntlz")])
2293 (define_expand "ctz<mode>2"
2294 [(set (match_dup 2)
2295 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2296 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2297 (match_dup 2)))
2298 (clobber (scratch:CC))])
2299 (set (match_dup 4) (clz:GPR (match_dup 3)))
2300 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2301 (minus:GPR (match_dup 5) (match_dup 4)))]
2302 ""
2303 {
2304 operands[2] = gen_reg_rtx (<MODE>mode);
2305 operands[3] = gen_reg_rtx (<MODE>mode);
2306 operands[4] = gen_reg_rtx (<MODE>mode);
2307 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2308 })
2310 (define_expand "ffs<mode>2"
2311 [(set (match_dup 2)
2312 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2313 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2314 (match_dup 2)))
2315 (clobber (scratch:CC))])
2316 (set (match_dup 4) (clz:GPR (match_dup 3)))
2317 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2318 (minus:GPR (match_dup 5) (match_dup 4)))]
2319 ""
2320 {
2321 operands[2] = gen_reg_rtx (<MODE>mode);
2322 operands[3] = gen_reg_rtx (<MODE>mode);
2323 operands[4] = gen_reg_rtx (<MODE>mode);
2324 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2325 })
2327 (define_insn "popcntb<mode>2"
2328 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2329 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2330 UNSPEC_POPCNTB))]
2331 "TARGET_POPCNTB"
2332 "popcntb %0,%1")
2334 (define_insn "popcntd<mode>2"
2335 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2336 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2337 "TARGET_POPCNTD"
2338 "popcnt<wd> %0,%1")
2340 (define_expand "popcount<mode>2"
2341 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2342 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2343 "TARGET_POPCNTB || TARGET_POPCNTD"
2344 {
2345 rs6000_emit_popcount (operands[0], operands[1]);
2346 DONE;
2347 })
2349 (define_insn "parity<mode>2_cmpb"
2350 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2351 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2352 "TARGET_CMPB && TARGET_POPCNTB"
2353 "prty<wd> %0,%1")
2355 (define_expand "parity<mode>2"
2356 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2357 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2358 "TARGET_POPCNTB"
2359 {
2360 rs6000_emit_parity (operands[0], operands[1]);
2361 DONE;
2362 })
2364 ;; Since the hardware zeros the upper part of the register, save generating the
2365 ;; AND immediate if we are converting to unsigned
2366 (define_insn "*bswaphi2_extenddi"
2367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2368 (zero_extend:DI
2369 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2370 "TARGET_POWERPC64"
2371 "lhbrx %0,%y1"
2372 [(set_attr "length" "4")
2373 (set_attr "type" "load")])
2375 (define_insn "*bswaphi2_extendsi"
2376 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2377 (zero_extend:SI
2378 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2379 "TARGET_POWERPC"
2380 "lhbrx %0,%y1"
2381 [(set_attr "length" "4")
2382 (set_attr "type" "load")])
2384 (define_expand "bswaphi2"
2385 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2386 (bswap:HI
2387 (match_operand:HI 1 "reg_or_mem_operand" "")))
2388 (clobber (match_scratch:SI 2 ""))])]
2389 ""
2390 {
2391 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2392 operands[1] = force_reg (HImode, operands[1]);
2393 })
2395 (define_insn "bswaphi2_internal"
2396 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2397 (bswap:HI
2398 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2399 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2400 "TARGET_POWERPC"
2401 "@
2402 lhbrx %0,%y1
2403 sthbrx %1,%y0
2404 #"
2405 [(set_attr "length" "4,4,12")
2406 (set_attr "type" "load,store,*")])
2408 (define_split
2409 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2410 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2411 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2412 "TARGET_POWERPC && reload_completed"
2413 [(set (match_dup 3)
2414 (zero_extract:SI (match_dup 4)
2415 (const_int 8)
2416 (const_int 16)))
2417 (set (match_dup 2)
2418 (and:SI (ashift:SI (match_dup 4)
2419 (const_int 8))
2420 (const_int 65280))) ;; 0xff00
2421 (set (match_dup 3)
2422 (ior:SI (match_dup 3)
2423 (match_dup 2)))]
2424 "
2425 {
2426 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2427 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2428 }")
2430 (define_insn "*bswapsi2_extenddi"
2431 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2432 (zero_extend:DI
2433 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2434 "TARGET_POWERPC64"
2435 "lwbrx %0,%y1"
2436 [(set_attr "length" "4")
2437 (set_attr "type" "load")])
2439 (define_expand "bswapsi2"
2440 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2441 (bswap:SI
2442 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2443 ""
2444 {
2445 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2446 operands[1] = force_reg (SImode, operands[1]);
2447 })
2449 (define_insn "*bswapsi2_internal"
2450 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2451 (bswap:SI
2452 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2453 ""
2454 "@
2455 {lbrx|lwbrx} %0,%y1
2456 {stbrx|stwbrx} %1,%y0
2457 #"
2458 [(set_attr "length" "4,4,12")
2459 (set_attr "type" "load,store,*")])
2461 (define_split
2462 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2463 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2464 "reload_completed"
2465 [(set (match_dup 0)
2466 (rotate:SI (match_dup 1) (const_int 8)))
2467 (set (zero_extract:SI (match_dup 0)
2468 (const_int 8)
2469 (const_int 0))
2470 (match_dup 1))
2471 (set (zero_extract:SI (match_dup 0)
2472 (const_int 8)
2473 (const_int 16))
2474 (rotate:SI (match_dup 1)
2475 (const_int 16)))]
2476 "")
2478 (define_expand "bswapdi2"
2479 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2480 (bswap:DI
2481 (match_operand:DI 1 "reg_or_mem_operand" "")))
2482 (clobber (match_scratch:DI 2 ""))
2483 (clobber (match_scratch:DI 3 ""))
2484 (clobber (match_scratch:DI 4 ""))])]
2485 ""
2486 {
2487 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2488 operands[1] = force_reg (DImode, operands[1]);
2490 if (!TARGET_POWERPC64)
2491 {
2492 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2493 that uses 64-bit registers needs the same scratch registers as 64-bit
2494 mode. */
2495 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2496 DONE;
2497 }
2498 })
2500 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2501 (define_insn "*bswapdi2_ldbrx"
2502 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2503 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2504 (clobber (match_scratch:DI 2 "=X,X,&r"))
2505 (clobber (match_scratch:DI 3 "=X,X,&r"))
2506 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2507 "TARGET_POWERPC64 && TARGET_LDBRX
2508 && (REG_P (operands[0]) || REG_P (operands[1]))"
2509 "@
2510 ldbrx %0,%y1
2511 stdbrx %1,%y0
2512 #"
2513 [(set_attr "length" "4,4,36")
2514 (set_attr "type" "load,store,*")])
2516 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2517 (define_insn "*bswapdi2_64bit"
2518 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2519 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2520 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2521 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2522 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2523 "TARGET_POWERPC64 && !TARGET_LDBRX
2524 && (REG_P (operands[0]) || REG_P (operands[1]))"
2525 "#"
2526 [(set_attr "length" "16,12,36")])
2528 (define_split
2529 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2530 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2531 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2532 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2533 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2534 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2535 [(const_int 0)]
2536 "
2537 {
2538 rtx dest = operands[0];
2539 rtx src = operands[1];
2540 rtx op2 = operands[2];
2541 rtx op3 = operands[3];
2542 rtx op4 = operands[4];
2543 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2544 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2545 rtx addr1;
2546 rtx addr2;
2547 rtx word_high;
2548 rtx word_low;
2550 addr1 = XEXP (src, 0);
2551 if (GET_CODE (addr1) == PLUS)
2552 {
2553 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2554 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2555 }
2556 else
2557 {
2558 emit_move_insn (op2, GEN_INT (4));
2559 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2560 }
2562 if (BYTES_BIG_ENDIAN)
2563 {
2564 word_high = change_address (src, SImode, addr1);
2565 word_low = change_address (src, SImode, addr2);
2566 }
2567 else
2568 {
2569 word_high = change_address (src, SImode, addr2);
2570 word_low = change_address (src, SImode, addr1);
2571 }
2573 emit_insn (gen_bswapsi2 (op3_32, word_low));
2574 emit_insn (gen_bswapsi2 (op4_32, word_high));
2575 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2576 emit_insn (gen_iordi3 (dest, dest, op4));
2577 }")
2579 (define_split
2580 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2581 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2582 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2583 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2584 (clobber (match_operand:DI 4 "" ""))]
2585 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2586 [(const_int 0)]
2587 "
2588 {
2589 rtx dest = operands[0];
2590 rtx src = operands[1];
2591 rtx op2 = operands[2];
2592 rtx op3 = operands[3];
2593 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2594 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2595 rtx addr1;
2596 rtx addr2;
2597 rtx word_high;
2598 rtx word_low;
2600 addr1 = XEXP (dest, 0);
2601 if (GET_CODE (addr1) == PLUS)
2602 {
2603 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2604 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2605 }
2606 else
2607 {
2608 emit_move_insn (op2, GEN_INT (4));
2609 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2610 }
2612 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2613 if (BYTES_BIG_ENDIAN)
2614 {
2615 word_high = change_address (dest, SImode, addr1);
2616 word_low = change_address (dest, SImode, addr2);
2617 emit_insn (gen_bswapsi2 (word_high, src_si));
2618 emit_insn (gen_bswapsi2 (word_low, op3_si));
2619 }
2620 else
2621 {
2622 word_high = change_address (dest, SImode, addr2);
2623 word_low = change_address (dest, SImode, addr1);
2624 emit_insn (gen_bswapsi2 (word_low, src_si));
2625 emit_insn (gen_bswapsi2 (word_high, op3_si));
2626 }
2627 }")
2629 (define_split
2630 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2631 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2632 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2633 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2634 (clobber (match_operand:DI 4 "" ""))]
2635 "TARGET_POWERPC64 && reload_completed"
2636 [(const_int 0)]
2637 "
2638 {
2639 rtx dest = operands[0];
2640 rtx src = operands[1];
2641 rtx op2 = operands[2];
2642 rtx op3 = operands[3];
2643 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2644 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2645 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2646 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2648 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2649 emit_insn (gen_bswapsi2 (dest_si, src_si));
2650 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2651 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2652 emit_insn (gen_iordi3 (dest, dest, op3));
2653 }")
2655 (define_insn "bswapdi2_32bit"
2656 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2657 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2658 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2659 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2660 "#"
2661 [(set_attr "length" "16,12,36")])
2663 (define_split
2664 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2665 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2666 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2667 "!TARGET_POWERPC64 && reload_completed"
2668 [(const_int 0)]
2669 "
2670 {
2671 rtx dest = operands[0];
2672 rtx src = operands[1];
2673 rtx op2 = operands[2];
2674 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2675 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2676 rtx addr1;
2677 rtx addr2;
2678 rtx word_high;
2679 rtx word_low;
2681 addr1 = XEXP (src, 0);
2682 if (GET_CODE (addr1) == PLUS)
2683 {
2684 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2685 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2686 }
2687 else
2688 {
2689 emit_move_insn (op2, GEN_INT (4));
2690 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2691 }
2693 if (BYTES_BIG_ENDIAN)
2694 {
2695 word_high = change_address (src, SImode, addr1);
2696 word_low = change_address (src, SImode, addr2);
2697 }
2698 else
2699 {
2700 word_high = change_address (src, SImode, addr2);
2701 word_low = change_address (src, SImode, addr1);
2702 }
2704 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2705 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2706 }")
2708 (define_split
2709 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2710 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2711 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2712 "!TARGET_POWERPC64 && reload_completed"
2713 [(const_int 0)]
2714 "
2715 {
2716 rtx dest = operands[0];
2717 rtx src = operands[1];
2718 rtx op2 = operands[2];
2719 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2720 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2721 rtx addr1;
2722 rtx addr2;
2723 rtx word_high;
2724 rtx word_low;
2726 addr1 = XEXP (dest, 0);
2727 if (GET_CODE (addr1) == PLUS)
2728 {
2729 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2730 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2731 }
2732 else
2733 {
2734 emit_move_insn (op2, GEN_INT (4));
2735 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2736 }
2738 if (BYTES_BIG_ENDIAN)
2739 {
2740 word_high = change_address (dest, SImode, addr1);
2741 word_low = change_address (dest, SImode, addr2);
2742 }
2743 else
2744 {
2745 word_high = change_address (dest, SImode, addr2);
2746 word_low = change_address (dest, SImode, addr1);
2747 }
2749 emit_insn (gen_bswapsi2 (word_high, src_low));
2750 emit_insn (gen_bswapsi2 (word_low, src_high));
2751 }")
2753 (define_split
2754 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2755 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2756 (clobber (match_operand:SI 2 "" ""))]
2757 "!TARGET_POWERPC64 && reload_completed"
2758 [(const_int 0)]
2759 "
2760 {
2761 rtx dest = operands[0];
2762 rtx src = operands[1];
2763 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2764 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2765 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2766 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2768 emit_insn (gen_bswapsi2 (dest_high, src_low));
2769 emit_insn (gen_bswapsi2 (dest_low, src_high));
2770 }")
2772 (define_expand "mulsi3"
2773 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2774 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2775 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2776 ""
2777 "
2778 {
2779 if (TARGET_POWER)
2780 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2781 else
2782 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2783 DONE;
2784 }")
2786 (define_insn "mulsi3_mq"
2787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2788 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2789 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2790 (clobber (match_scratch:SI 3 "=q,q"))]
2791 "TARGET_POWER"
2792 "@
2793 {muls|mullw} %0,%1,%2
2794 {muli|mulli} %0,%1,%2"
2795 [(set (attr "type")
2796 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2797 (const_string "imul3")
2798 (match_operand:SI 2 "short_cint_operand" "")
2799 (const_string "imul2")]
2800 (const_string "imul")))])
2802 (define_insn "mulsi3_no_mq"
2803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2804 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2805 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2806 "! TARGET_POWER"
2807 "@
2808 {muls|mullw} %0,%1,%2
2809 {muli|mulli} %0,%1,%2"
2810 [(set (attr "type")
2811 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2812 (const_string "imul3")
2813 (match_operand:SI 2 "short_cint_operand" "")
2814 (const_string "imul2")]
2815 (const_string "imul")))])
2817 (define_insn "*mulsi3_mq_internal1"
2818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2819 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2820 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2821 (const_int 0)))
2822 (clobber (match_scratch:SI 3 "=r,r"))
2823 (clobber (match_scratch:SI 4 "=q,q"))]
2824 "TARGET_POWER"
2825 "@
2826 {muls.|mullw.} %3,%1,%2
2827 #"
2828 [(set_attr "type" "imul_compare")
2829 (set_attr "length" "4,8")])
2831 (define_split
2832 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2833 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2834 (match_operand:SI 2 "gpc_reg_operand" ""))
2835 (const_int 0)))
2836 (clobber (match_scratch:SI 3 ""))
2837 (clobber (match_scratch:SI 4 ""))]
2838 "TARGET_POWER && reload_completed"
2839 [(parallel [(set (match_dup 3)
2840 (mult:SI (match_dup 1) (match_dup 2)))
2841 (clobber (match_dup 4))])
2842 (set (match_dup 0)
2843 (compare:CC (match_dup 3)
2844 (const_int 0)))]
2845 "")
2847 (define_insn "*mulsi3_no_mq_internal1"
2848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2849 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2850 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2851 (const_int 0)))
2852 (clobber (match_scratch:SI 3 "=r,r"))]
2853 "! TARGET_POWER"
2854 "@
2855 {muls.|mullw.} %3,%1,%2
2856 #"
2857 [(set_attr "type" "imul_compare")
2858 (set_attr "length" "4,8")])
2860 (define_split
2861 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2862 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2863 (match_operand:SI 2 "gpc_reg_operand" ""))
2864 (const_int 0)))
2865 (clobber (match_scratch:SI 3 ""))]
2866 "! TARGET_POWER && reload_completed"
2867 [(set (match_dup 3)
2868 (mult:SI (match_dup 1) (match_dup 2)))
2869 (set (match_dup 0)
2870 (compare:CC (match_dup 3)
2871 (const_int 0)))]
2872 "")
2874 (define_insn "*mulsi3_mq_internal2"
2875 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2876 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2877 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2878 (const_int 0)))
2879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2880 (mult:SI (match_dup 1) (match_dup 2)))
2881 (clobber (match_scratch:SI 4 "=q,q"))]
2882 "TARGET_POWER"
2883 "@
2884 {muls.|mullw.} %0,%1,%2
2885 #"
2886 [(set_attr "type" "imul_compare")
2887 (set_attr "length" "4,8")])
2889 (define_split
2890 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2891 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2892 (match_operand:SI 2 "gpc_reg_operand" ""))
2893 (const_int 0)))
2894 (set (match_operand:SI 0 "gpc_reg_operand" "")
2895 (mult:SI (match_dup 1) (match_dup 2)))
2896 (clobber (match_scratch:SI 4 ""))]
2897 "TARGET_POWER && reload_completed"
2898 [(parallel [(set (match_dup 0)
2899 (mult:SI (match_dup 1) (match_dup 2)))
2900 (clobber (match_dup 4))])
2901 (set (match_dup 3)
2902 (compare:CC (match_dup 0)
2903 (const_int 0)))]
2904 "")
2906 (define_insn "*mulsi3_no_mq_internal2"
2907 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2908 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2909 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2910 (const_int 0)))
2911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2912 (mult:SI (match_dup 1) (match_dup 2)))]
2913 "! TARGET_POWER"
2914 "@
2915 {muls.|mullw.} %0,%1,%2
2916 #"
2917 [(set_attr "type" "imul_compare")
2918 (set_attr "length" "4,8")])
2920 (define_split
2921 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2922 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2923 (match_operand:SI 2 "gpc_reg_operand" ""))
2924 (const_int 0)))
2925 (set (match_operand:SI 0 "gpc_reg_operand" "")
2926 (mult:SI (match_dup 1) (match_dup 2)))]
2927 "! TARGET_POWER && reload_completed"
2928 [(set (match_dup 0)
2929 (mult:SI (match_dup 1) (match_dup 2)))
2930 (set (match_dup 3)
2931 (compare:CC (match_dup 0)
2932 (const_int 0)))]
2933 "")
2935 ;; Operand 1 is divided by operand 2; quotient goes to operand
2936 ;; 0 and remainder to operand 3.
2937 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2939 (define_expand "divmodsi4"
2940 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2941 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2942 (match_operand:SI 2 "gpc_reg_operand" "")))
2943 (set (match_operand:SI 3 "register_operand" "")
2944 (mod:SI (match_dup 1) (match_dup 2)))])]
2945 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2946 "
2947 {
2948 if (! TARGET_POWER && ! TARGET_POWERPC)
2949 {
2950 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2951 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2952 emit_insn (gen_divss_call ());
2953 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2954 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2955 DONE;
2956 }
2957 }")
2959 (define_insn "*divmodsi4_internal"
2960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2961 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2962 (match_operand:SI 2 "gpc_reg_operand" "r")))
2963 (set (match_operand:SI 3 "register_operand" "=q")
2964 (mod:SI (match_dup 1) (match_dup 2)))]
2965 "TARGET_POWER"
2966 "divs %0,%1,%2"
2967 [(set_attr "type" "idiv")])
2969 (define_expand "udiv<mode>3"
2970 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2971 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2972 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2973 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2974 "
2975 {
2976 if (! TARGET_POWER && ! TARGET_POWERPC)
2977 {
2978 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2979 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2980 emit_insn (gen_quous_call ());
2981 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2982 DONE;
2983 }
2984 else if (TARGET_POWER)
2985 {
2986 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2987 DONE;
2988 }
2989 }")
2991 (define_insn "udivsi3_mq"
2992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2993 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2994 (match_operand:SI 2 "gpc_reg_operand" "r")))
2995 (clobber (match_scratch:SI 3 "=q"))]
2996 "TARGET_POWERPC && TARGET_POWER"
2997 "divwu %0,%1,%2"
2998 [(set_attr "type" "idiv")])
3000 (define_insn "*udivsi3_no_mq"
3001 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3002 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3003 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3004 "TARGET_POWERPC && ! TARGET_POWER"
3005 "div<wd>u %0,%1,%2"
3006 [(set (attr "type")
3007 (cond [(match_operand:SI 0 "" "")
3008 (const_string "idiv")]
3009 (const_string "ldiv")))])
3012 ;; For powers of two we can do srai/aze for divide and then adjust for
3013 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
3014 ;; used; for PowerPC, force operands into register and do a normal divide;
3015 ;; for AIX common-mode, use quoss call on register operands.
3016 (define_expand "div<mode>3"
3017 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3018 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3019 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
3020 ""
3021 "
3022 {
3023 if (GET_CODE (operands[2]) == CONST_INT
3024 && INTVAL (operands[2]) > 0
3025 && exact_log2 (INTVAL (operands[2])) >= 0)
3026 ;
3027 else if (TARGET_POWERPC)
3028 {
3029 operands[2] = force_reg (<MODE>mode, operands[2]);
3030 if (TARGET_POWER)
3031 {
3032 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
3033 DONE;
3034 }
3035 }
3036 else if (TARGET_POWER)
3037 FAIL;
3038 else
3039 {
3040 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3041 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3042 emit_insn (gen_quoss_call ());
3043 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3044 DONE;
3045 }
3046 }")
3048 (define_insn "divsi3_mq"
3049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3050 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3051 (match_operand:SI 2 "gpc_reg_operand" "r")))
3052 (clobber (match_scratch:SI 3 "=q"))]
3053 "TARGET_POWERPC && TARGET_POWER"
3054 "divw %0,%1,%2"
3055 [(set_attr "type" "idiv")])
3057 (define_insn "*div<mode>3_no_mq"
3058 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3059 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3060 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3061 "TARGET_POWERPC && ! TARGET_POWER"
3062 "div<wd> %0,%1,%2"
3063 [(set (attr "type")
3064 (cond [(match_operand:SI 0 "" "")
3065 (const_string "idiv")]
3066 (const_string "ldiv")))])
3068 (define_expand "mod<mode>3"
3069 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3070 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3071 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3072 ""
3073 "
3074 {
3075 int i;
3076 rtx temp1;
3077 rtx temp2;
3079 if (GET_CODE (operands[2]) != CONST_INT
3080 || INTVAL (operands[2]) <= 0
3081 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3082 FAIL;
3084 temp1 = gen_reg_rtx (<MODE>mode);
3085 temp2 = gen_reg_rtx (<MODE>mode);
3087 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3088 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3089 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3090 DONE;
3091 }")
3093 (define_insn ""
3094 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3095 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3096 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3097 ""
3098 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3099 [(set_attr "type" "two")
3100 (set_attr "length" "8")])
3102 (define_insn ""
3103 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3104 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3105 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3106 (const_int 0)))
3107 (clobber (match_scratch:P 3 "=r,r"))]
3108 ""
3109 "@
3110 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3111 #"
3112 [(set_attr "type" "compare")
3113 (set_attr "length" "8,12")
3114 (set_attr "cell_micro" "not")])
3116 (define_split
3117 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3118 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3119 (match_operand:GPR 2 "exact_log2_cint_operand"
3120 ""))
3121 (const_int 0)))
3122 (clobber (match_scratch:GPR 3 ""))]
3123 "reload_completed"
3124 [(set (match_dup 3)
3125 (div:<MODE> (match_dup 1) (match_dup 2)))
3126 (set (match_dup 0)
3127 (compare:CC (match_dup 3)
3128 (const_int 0)))]
3129 "")
3131 (define_insn ""
3132 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3133 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3134 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3135 (const_int 0)))
3136 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3137 (div:P (match_dup 1) (match_dup 2)))]
3138 ""
3139 "@
3140 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3141 #"
3142 [(set_attr "type" "compare")
3143 (set_attr "length" "8,12")
3144 (set_attr "cell_micro" "not")])
3146 (define_split
3147 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3148 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3149 (match_operand:GPR 2 "exact_log2_cint_operand"
3150 ""))
3151 (const_int 0)))
3152 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3153 (div:GPR (match_dup 1) (match_dup 2)))]
3154 "reload_completed"
3155 [(set (match_dup 0)
3156 (div:<MODE> (match_dup 1) (match_dup 2)))
3157 (set (match_dup 3)
3158 (compare:CC (match_dup 0)
3159 (const_int 0)))]
3160 "")
3162 (define_insn ""
3163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3164 (udiv:SI
3165 (plus:DI (ashift:DI
3166 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3167 (const_int 32))
3168 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3169 (match_operand:SI 3 "gpc_reg_operand" "r")))
3170 (set (match_operand:SI 2 "register_operand" "=*q")
3171 (umod:SI
3172 (plus:DI (ashift:DI
3173 (zero_extend:DI (match_dup 1)) (const_int 32))
3174 (zero_extend:DI (match_dup 4)))
3175 (match_dup 3)))]
3176 "TARGET_POWER"
3177 "div %0,%1,%3"
3178 [(set_attr "type" "idiv")])
3180 ;; To do unsigned divide we handle the cases of the divisor looking like a
3181 ;; negative number. If it is a constant that is less than 2**31, we don't
3182 ;; have to worry about the branches. So make a few subroutines here.
3183 ;;
3184 ;; First comes the normal case.
3185 (define_expand "udivmodsi4_normal"
3186 [(set (match_dup 4) (const_int 0))
3187 (parallel [(set (match_operand:SI 0 "" "")
3188 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3189 (const_int 32))
3190 (zero_extend:DI (match_operand:SI 1 "" "")))
3191 (match_operand:SI 2 "" "")))
3192 (set (match_operand:SI 3 "" "")
3193 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3194 (const_int 32))
3195 (zero_extend:DI (match_dup 1)))
3196 (match_dup 2)))])]
3197 "TARGET_POWER"
3198 "
3199 { operands[4] = gen_reg_rtx (SImode); }")
3201 ;; This handles the branches.
3202 (define_expand "udivmodsi4_tests"
3203 [(set (match_operand:SI 0 "" "") (const_int 0))
3204 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3205 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3206 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3207 (label_ref (match_operand:SI 4 "" "")) (pc)))
3208 (set (match_dup 0) (const_int 1))
3209 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3210 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3211 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3212 (label_ref (match_dup 4)) (pc)))]
3213 "TARGET_POWER"
3214 "
3215 { operands[5] = gen_reg_rtx (CCUNSmode);
3216 operands[6] = gen_reg_rtx (CCmode);
3217 }")
3219 (define_expand "udivmodsi4"
3220 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3221 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3222 (match_operand:SI 2 "reg_or_cint_operand" "")))
3223 (set (match_operand:SI 3 "gpc_reg_operand" "")
3224 (umod:SI (match_dup 1) (match_dup 2)))])]
3225 ""
3226 "
3227 {
3228 rtx label = 0;
3230 if (! TARGET_POWER)
3231 {
3232 if (! TARGET_POWERPC)
3233 {
3234 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3235 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3236 emit_insn (gen_divus_call ());
3237 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3238 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3239 DONE;
3240 }
3241 else
3242 FAIL;
3243 }
3245 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3246 {
3247 operands[2] = force_reg (SImode, operands[2]);
3248 label = gen_label_rtx ();
3249 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3250 operands[3], label));
3251 }
3252 else
3253 operands[2] = force_reg (SImode, operands[2]);
3255 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3256 operands[3]));
3257 if (label)
3258 emit_label (label);
3260 DONE;
3261 }")
3263 ;; AIX architecture-independent common-mode multiply (DImode),
3264 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3265 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3266 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3267 ;; assumed unused if generating common-mode, so ignore.
3268 (define_insn "mulh_call"
3269 [(set (reg:SI 3)
3270 (truncate:SI
3271 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3272 (sign_extend:DI (reg:SI 4)))
3273 (const_int 32))))
3274 (clobber (reg:SI LR_REGNO))]
3275 "! TARGET_POWER && ! TARGET_POWERPC"
3276 "bla __mulh"
3277 [(set_attr "type" "imul")])
3279 (define_insn "mull_call"
3280 [(set (reg:DI 3)
3281 (mult:DI (sign_extend:DI (reg:SI 3))
3282 (sign_extend:DI (reg:SI 4))))
3283 (clobber (reg:SI LR_REGNO))
3284 (clobber (reg:SI 0))]
3285 "! TARGET_POWER && ! TARGET_POWERPC"
3286 "bla __mull"
3287 [(set_attr "type" "imul")])
3289 (define_insn "divss_call"
3290 [(set (reg:SI 3)
3291 (div:SI (reg:SI 3) (reg:SI 4)))
3292 (set (reg:SI 4)
3293 (mod:SI (reg:SI 3) (reg:SI 4)))
3294 (clobber (reg:SI LR_REGNO))
3295 (clobber (reg:SI 0))]
3296 "! TARGET_POWER && ! TARGET_POWERPC"
3297 "bla __divss"
3298 [(set_attr "type" "idiv")])
3300 (define_insn "divus_call"
3301 [(set (reg:SI 3)
3302 (udiv:SI (reg:SI 3) (reg:SI 4)))
3303 (set (reg:SI 4)
3304 (umod:SI (reg:SI 3) (reg:SI 4)))
3305 (clobber (reg:SI LR_REGNO))
3306 (clobber (reg:SI 0))
3307 (clobber (match_scratch:CC 0 "=x"))
3308 (clobber (reg:CC CR1_REGNO))]
3309 "! TARGET_POWER && ! TARGET_POWERPC"
3310 "bla __divus"
3311 [(set_attr "type" "idiv")])
3313 (define_insn "quoss_call"
3314 [(set (reg:SI 3)
3315 (div:SI (reg:SI 3) (reg:SI 4)))
3316 (clobber (reg:SI LR_REGNO))]
3317 "! TARGET_POWER && ! TARGET_POWERPC"
3318 "bla __quoss"
3319 [(set_attr "type" "idiv")])
3321 (define_insn "quous_call"
3322 [(set (reg:SI 3)
3323 (udiv:SI (reg:SI 3) (reg:SI 4)))
3324 (clobber (reg:SI LR_REGNO))
3325 (clobber (reg:SI 0))
3326 (clobber (match_scratch:CC 0 "=x"))
3327 (clobber (reg:CC CR1_REGNO))]
3328 "! TARGET_POWER && ! TARGET_POWERPC"
3329 "bla __quous"
3330 [(set_attr "type" "idiv")])
3331 \f
3332 ;; Logical instructions
3333 ;; The logical instructions are mostly combined by using match_operator,
3334 ;; but the plain AND insns are somewhat different because there is no
3335 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3336 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3338 (define_expand "andsi3"
3339 [(parallel
3340 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3341 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3342 (match_operand:SI 2 "and_operand" "")))
3343 (clobber (match_scratch:CC 3 ""))])]
3344 ""
3345 "")
3347 (define_insn "andsi3_mc"
3348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3349 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3350 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3351 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3352 "rs6000_gen_cell_microcode"
3353 "@
3354 and %0,%1,%2
3355 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3356 {andil.|andi.} %0,%1,%b2
3357 {andiu.|andis.} %0,%1,%u2"
3358 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3360 (define_insn "andsi3_nomc"
3361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3362 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3363 (match_operand:SI 2 "and_operand" "?r,T")))
3364 (clobber (match_scratch:CC 3 "=X,X"))]
3365 "!rs6000_gen_cell_microcode"
3366 "@
3367 and %0,%1,%2
3368 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3370 (define_insn "andsi3_internal0_nomc"
3371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3372 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3373 (match_operand:SI 2 "and_operand" "?r,T")))]
3374 "!rs6000_gen_cell_microcode"
3375 "@
3376 and %0,%1,%2
3377 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3380 ;; Note to set cr's other than cr0 we do the and immediate and then
3381 ;; the test again -- this avoids a mfcr which on the higher end
3382 ;; machines causes an execution serialization
3384 (define_insn "*andsi3_internal2_mc"
3385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3386 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3387 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3388 (const_int 0)))
3389 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3390 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3391 "TARGET_32BIT && rs6000_gen_cell_microcode"
3392 "@
3393 and. %3,%1,%2
3394 {andil.|andi.} %3,%1,%b2
3395 {andiu.|andis.} %3,%1,%u2
3396 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3397 #
3398 #
3399 #
3400 #"
3401 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3402 compare,compare,compare,compare")
3403 (set_attr "length" "4,4,4,4,8,8,8,8")])
3405 (define_insn "*andsi3_internal3_mc"
3406 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3407 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3408 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3409 (const_int 0)))
3410 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3411 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3412 "TARGET_64BIT && rs6000_gen_cell_microcode"
3413 "@
3414 #
3415 {andil.|andi.} %3,%1,%b2
3416 {andiu.|andis.} %3,%1,%u2
3417 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3418 #
3419 #
3420 #
3421 #"
3422 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3423 compare,compare,compare")
3424 (set_attr "length" "8,4,4,4,8,8,8,8")])
3426 (define_split
3427 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3428 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3429 (match_operand:GPR 2 "and_operand" ""))
3430 (const_int 0)))
3431 (clobber (match_scratch:GPR 3 ""))
3432 (clobber (match_scratch:CC 4 ""))]
3433 "reload_completed"
3434 [(parallel [(set (match_dup 3)
3435 (and:<MODE> (match_dup 1)
3436 (match_dup 2)))
3437 (clobber (match_dup 4))])
3438 (set (match_dup 0)
3439 (compare:CC (match_dup 3)
3440 (const_int 0)))]
3441 "")
3443 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3444 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3446 (define_split
3447 [(set (match_operand:CC 0 "cc_reg_operand" "")
3448 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3449 (match_operand:SI 2 "gpc_reg_operand" ""))
3450 (const_int 0)))
3451 (clobber (match_scratch:SI 3 ""))
3452 (clobber (match_scratch:CC 4 ""))]
3453 "TARGET_POWERPC64 && reload_completed"
3454 [(parallel [(set (match_dup 3)
3455 (and:SI (match_dup 1)
3456 (match_dup 2)))
3457 (clobber (match_dup 4))])
3458 (set (match_dup 0)
3459 (compare:CC (match_dup 3)
3460 (const_int 0)))]
3461 "")
3463 (define_insn "*andsi3_internal4"
3464 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3465 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3466 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3467 (const_int 0)))
3468 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3469 (and:SI (match_dup 1)
3470 (match_dup 2)))
3471 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3472 "TARGET_32BIT && rs6000_gen_cell_microcode"
3473 "@
3474 and. %0,%1,%2
3475 {andil.|andi.} %0,%1,%b2
3476 {andiu.|andis.} %0,%1,%u2
3477 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3478 #
3479 #
3480 #
3481 #"
3482 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3483 compare,compare,compare,compare")
3484 (set_attr "length" "4,4,4,4,8,8,8,8")])
3486 (define_insn "*andsi3_internal5_mc"
3487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3488 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3489 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3490 (const_int 0)))
3491 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3492 (and:SI (match_dup 1)
3493 (match_dup 2)))
3494 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3495 "TARGET_64BIT && rs6000_gen_cell_microcode"
3496 "@
3497 #
3498 {andil.|andi.} %0,%1,%b2
3499 {andiu.|andis.} %0,%1,%u2
3500 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3501 #
3502 #
3503 #
3504 #"
3505 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3506 compare,compare,compare")
3507 (set_attr "length" "8,4,4,4,8,8,8,8")])
3509 (define_split
3510 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3511 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3512 (match_operand:SI 2 "and_operand" ""))
3513 (const_int 0)))
3514 (set (match_operand:SI 0 "gpc_reg_operand" "")
3515 (and:SI (match_dup 1)
3516 (match_dup 2)))
3517 (clobber (match_scratch:CC 4 ""))]
3518 "reload_completed"
3519 [(parallel [(set (match_dup 0)
3520 (and:SI (match_dup 1)
3521 (match_dup 2)))
3522 (clobber (match_dup 4))])
3523 (set (match_dup 3)
3524 (compare:CC (match_dup 0)
3525 (const_int 0)))]
3526 "")
3528 (define_split
3529 [(set (match_operand:CC 3 "cc_reg_operand" "")
3530 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3531 (match_operand:SI 2 "gpc_reg_operand" ""))
3532 (const_int 0)))
3533 (set (match_operand:SI 0 "gpc_reg_operand" "")
3534 (and:SI (match_dup 1)
3535 (match_dup 2)))
3536 (clobber (match_scratch:CC 4 ""))]
3537 "TARGET_POWERPC64 && reload_completed"
3538 [(parallel [(set (match_dup 0)
3539 (and:SI (match_dup 1)
3540 (match_dup 2)))
3541 (clobber (match_dup 4))])
3542 (set (match_dup 3)
3543 (compare:CC (match_dup 0)
3544 (const_int 0)))]
3545 "")
3547 ;; Handle the PowerPC64 rlwinm corner case
3549 (define_insn_and_split "*andsi3_internal6"
3550 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3551 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3552 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3553 "TARGET_POWERPC64"
3554 "#"
3555 "TARGET_POWERPC64"
3556 [(set (match_dup 0)
3557 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3558 (match_dup 4)))
3559 (set (match_dup 0)
3560 (rotate:SI (match_dup 0) (match_dup 5)))]
3561 "
3562 {
3563 int mb = extract_MB (operands[2]);
3564 int me = extract_ME (operands[2]);
3565 operands[3] = GEN_INT (me + 1);
3566 operands[5] = GEN_INT (32 - (me + 1));
3567 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3568 }"
3569 [(set_attr "length" "8")])
3571 (define_expand "iorsi3"
3572 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3573 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3574 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3575 ""
3576 "
3577 {
3578 if (GET_CODE (operands[2]) == CONST_INT
3579 && ! logical_operand (operands[2], SImode))
3580 {
3581 HOST_WIDE_INT value = INTVAL (operands[2]);
3582 rtx tmp = ((!can_create_pseudo_p ()
3583 || rtx_equal_p (operands[0], operands[1]))
3584 ? operands[0] : gen_reg_rtx (SImode));
3586 emit_insn (gen_iorsi3 (tmp, operands[1],
3587 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3588 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3589 DONE;
3590 }
3591 }")
3593 (define_expand "xorsi3"
3594 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3595 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3596 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3597 ""
3598 "
3599 {
3600 if (GET_CODE (operands[2]) == CONST_INT
3601 && ! logical_operand (operands[2], SImode))
3602 {
3603 HOST_WIDE_INT value = INTVAL (operands[2]);
3604 rtx tmp = ((!can_create_pseudo_p ()
3605 || rtx_equal_p (operands[0], operands[1]))
3606 ? operands[0] : gen_reg_rtx (SImode));
3608 emit_insn (gen_xorsi3 (tmp, operands[1],
3609 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3610 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3611 DONE;
3612 }
3613 }")
3615 (define_insn "*boolsi3_internal1"
3616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3617 (match_operator:SI 3 "boolean_or_operator"
3618 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3619 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3620 ""
3621 "@
3622 %q3 %0,%1,%2
3623 {%q3il|%q3i} %0,%1,%b2
3624 {%q3iu|%q3is} %0,%1,%u2")
3626 (define_insn "*boolsi3_internal2"
3627 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3628 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3629 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3630 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3631 (const_int 0)))
3632 (clobber (match_scratch:SI 3 "=r,r"))]
3633 "TARGET_32BIT"
3634 "@
3635 %q4. %3,%1,%2
3636 #"
3637 [(set_attr "type" "fast_compare,compare")
3638 (set_attr "length" "4,8")])
3640 (define_split
3641 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3642 (compare:CC (match_operator:SI 4 "boolean_operator"
3643 [(match_operand:SI 1 "gpc_reg_operand" "")
3644 (match_operand:SI 2 "gpc_reg_operand" "")])
3645 (const_int 0)))
3646 (clobber (match_scratch:SI 3 ""))]
3647 "TARGET_32BIT && reload_completed"
3648 [(set (match_dup 3) (match_dup 4))
3649 (set (match_dup 0)
3650 (compare:CC (match_dup 3)
3651 (const_int 0)))]
3652 "")
3654 (define_insn "*boolsi3_internal3"
3655 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3656 (compare:CC (match_operator:SI 4 "boolean_operator"
3657 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3658 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3659 (const_int 0)))
3660 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3661 (match_dup 4))]
3662 "TARGET_32BIT"
3663 "@
3664 %q4. %0,%1,%2
3665 #"
3666 [(set_attr "type" "fast_compare,compare")
3667 (set_attr "length" "4,8")])
3669 (define_split
3670 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3671 (compare:CC (match_operator:SI 4 "boolean_operator"
3672 [(match_operand:SI 1 "gpc_reg_operand" "")
3673 (match_operand:SI 2 "gpc_reg_operand" "")])
3674 (const_int 0)))
3675 (set (match_operand:SI 0 "gpc_reg_operand" "")
3676 (match_dup 4))]
3677 "TARGET_32BIT && reload_completed"
3678 [(set (match_dup 0) (match_dup 4))
3679 (set (match_dup 3)
3680 (compare:CC (match_dup 0)
3681 (const_int 0)))]
3682 "")
3684 ;; Split a logical operation that we can't do in one insn into two insns,
3685 ;; each of which does one 16-bit part. This is used by combine.
3687 (define_split
3688 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3689 (match_operator:SI 3 "boolean_or_operator"
3690 [(match_operand:SI 1 "gpc_reg_operand" "")
3691 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3692 ""
3693 [(set (match_dup 0) (match_dup 4))
3694 (set (match_dup 0) (match_dup 5))]
3695 "
3696 {
3697 rtx i;
3698 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3699 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3700 operands[1], i);
3701 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3702 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3703 operands[0], i);
3704 }")
3706 (define_insn "*boolcsi3_internal1"
3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (match_operator:SI 3 "boolean_operator"
3709 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3710 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3711 ""
3712 "%q3 %0,%2,%1")
3714 (define_insn "*boolcsi3_internal2"
3715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3716 (compare:CC (match_operator:SI 4 "boolean_operator"
3717 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3718 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3719 (const_int 0)))
3720 (clobber (match_scratch:SI 3 "=r,r"))]
3721 "TARGET_32BIT"
3722 "@
3723 %q4. %3,%2,%1
3724 #"
3725 [(set_attr "type" "compare")
3726 (set_attr "length" "4,8")])
3728 (define_split
3729 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3730 (compare:CC (match_operator:SI 4 "boolean_operator"
3731 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3732 (match_operand:SI 2 "gpc_reg_operand" "")])
3733 (const_int 0)))
3734 (clobber (match_scratch:SI 3 ""))]
3735 "TARGET_32BIT && reload_completed"
3736 [(set (match_dup 3) (match_dup 4))
3737 (set (match_dup 0)
3738 (compare:CC (match_dup 3)
3739 (const_int 0)))]
3740 "")
3742 (define_insn "*boolcsi3_internal3"
3743 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3744 (compare:CC (match_operator:SI 4 "boolean_operator"
3745 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3746 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3747 (const_int 0)))
3748 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3749 (match_dup 4))]
3750 "TARGET_32BIT"
3751 "@
3752 %q4. %0,%2,%1
3753 #"
3754 [(set_attr "type" "compare")
3755 (set_attr "length" "4,8")])
3757 (define_split
3758 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3759 (compare:CC (match_operator:SI 4 "boolean_operator"
3760 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3761 (match_operand:SI 2 "gpc_reg_operand" "")])
3762 (const_int 0)))
3763 (set (match_operand:SI 0 "gpc_reg_operand" "")
3764 (match_dup 4))]
3765 "TARGET_32BIT && reload_completed"
3766 [(set (match_dup 0) (match_dup 4))
3767 (set (match_dup 3)
3768 (compare:CC (match_dup 0)
3769 (const_int 0)))]
3770 "")
3772 (define_insn "*boolccsi3_internal1"
3773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3774 (match_operator:SI 3 "boolean_operator"
3775 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3776 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3777 ""
3778 "%q3 %0,%1,%2")
3780 (define_insn "*boolccsi3_internal2"
3781 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3782 (compare:CC (match_operator:SI 4 "boolean_operator"
3783 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3784 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3785 (const_int 0)))
3786 (clobber (match_scratch:SI 3 "=r,r"))]
3787 "TARGET_32BIT"
3788 "@
3789 %q4. %3,%1,%2
3790 #"
3791 [(set_attr "type" "fast_compare,compare")
3792 (set_attr "length" "4,8")])
3794 (define_split
3795 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3796 (compare:CC (match_operator:SI 4 "boolean_operator"
3797 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3798 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3799 (const_int 0)))
3800 (clobber (match_scratch:SI 3 ""))]
3801 "TARGET_32BIT && reload_completed"
3802 [(set (match_dup 3) (match_dup 4))
3803 (set (match_dup 0)
3804 (compare:CC (match_dup 3)
3805 (const_int 0)))]
3806 "")
3808 (define_insn "*boolccsi3_internal3"
3809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3810 (compare:CC (match_operator:SI 4 "boolean_operator"
3811 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3812 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3813 (const_int 0)))
3814 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3815 (match_dup 4))]
3816 "TARGET_32BIT"
3817 "@
3818 %q4. %0,%1,%2
3819 #"
3820 [(set_attr "type" "fast_compare,compare")
3821 (set_attr "length" "4,8")])
3823 (define_split
3824 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3825 (compare:CC (match_operator:SI 4 "boolean_operator"
3826 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3827 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3828 (const_int 0)))
3829 (set (match_operand:SI 0 "gpc_reg_operand" "")
3830 (match_dup 4))]
3831 "TARGET_32BIT && reload_completed"
3832 [(set (match_dup 0) (match_dup 4))
3833 (set (match_dup 3)
3834 (compare:CC (match_dup 0)
3835 (const_int 0)))]
3836 "")
3838 ;; maskir insn. We need four forms because things might be in arbitrary
3839 ;; orders. Don't define forms that only set CR fields because these
3840 ;; would modify an input register.
3842 (define_insn "*maskir_internal1"
3843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3844 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3845 (match_operand:SI 1 "gpc_reg_operand" "0"))
3846 (and:SI (match_dup 2)
3847 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3848 "TARGET_POWER"
3849 "maskir %0,%3,%2")
3851 (define_insn "*maskir_internal2"
3852 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3853 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3854 (match_operand:SI 1 "gpc_reg_operand" "0"))
3855 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3856 (match_dup 2))))]
3857 "TARGET_POWER"
3858 "maskir %0,%3,%2")
3860 (define_insn "*maskir_internal3"
3861 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3862 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3863 (match_operand:SI 3 "gpc_reg_operand" "r"))
3864 (and:SI (not:SI (match_dup 2))
3865 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3866 "TARGET_POWER"
3867 "maskir %0,%3,%2")
3869 (define_insn "*maskir_internal4"
3870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3871 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3872 (match_operand:SI 2 "gpc_reg_operand" "r"))
3873 (and:SI (not:SI (match_dup 2))
3874 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3875 "TARGET_POWER"
3876 "maskir %0,%3,%2")
3878 (define_insn "*maskir_internal5"
3879 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3880 (compare:CC
3881 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3882 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3883 (and:SI (match_dup 2)
3884 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3885 (const_int 0)))
3886 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3887 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3888 (and:SI (match_dup 2) (match_dup 3))))]
3889 "TARGET_POWER"
3890 "@
3891 maskir. %0,%3,%2
3892 #"
3893 [(set_attr "type" "compare")
3894 (set_attr "length" "4,8")])
3896 (define_split
3897 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3898 (compare:CC
3899 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3900 (match_operand:SI 1 "gpc_reg_operand" ""))
3901 (and:SI (match_dup 2)
3902 (match_operand:SI 3 "gpc_reg_operand" "")))
3903 (const_int 0)))
3904 (set (match_operand:SI 0 "gpc_reg_operand" "")
3905 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3906 (and:SI (match_dup 2) (match_dup 3))))]
3907 "TARGET_POWER && reload_completed"
3908 [(set (match_dup 0)
3909 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3910 (and:SI (match_dup 2) (match_dup 3))))
3911 (set (match_dup 4)
3912 (compare:CC (match_dup 0)
3913 (const_int 0)))]
3914 "")
3916 (define_insn "*maskir_internal6"
3917 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3918 (compare:CC
3919 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3920 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3921 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3922 (match_dup 2)))
3923 (const_int 0)))
3924 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3925 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3926 (and:SI (match_dup 3) (match_dup 2))))]
3927 "TARGET_POWER"
3928 "@
3929 maskir. %0,%3,%2
3930 #"
3931 [(set_attr "type" "compare")
3932 (set_attr "length" "4,8")])
3934 (define_split
3935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3936 (compare:CC
3937 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3938 (match_operand:SI 1 "gpc_reg_operand" ""))
3939 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3940 (match_dup 2)))
3941 (const_int 0)))
3942 (set (match_operand:SI 0 "gpc_reg_operand" "")
3943 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3944 (and:SI (match_dup 3) (match_dup 2))))]
3945 "TARGET_POWER && reload_completed"
3946 [(set (match_dup 0)
3947 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3948 (and:SI (match_dup 3) (match_dup 2))))
3949 (set (match_dup 4)
3950 (compare:CC (match_dup 0)
3951 (const_int 0)))]
3952 "")
3954 (define_insn "*maskir_internal7"
3955 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3956 (compare:CC
3957 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3959 (and:SI (not:SI (match_dup 2))
3960 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3961 (const_int 0)))
3962 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3963 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3964 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3965 "TARGET_POWER"
3966 "@
3967 maskir. %0,%3,%2
3968 #"
3969 [(set_attr "type" "compare")
3970 (set_attr "length" "4,8")])
3972 (define_split
3973 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3974 (compare:CC
3975 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3976 (match_operand:SI 3 "gpc_reg_operand" ""))
3977 (and:SI (not:SI (match_dup 2))
3978 (match_operand:SI 1 "gpc_reg_operand" "")))
3979 (const_int 0)))
3980 (set (match_operand:SI 0 "gpc_reg_operand" "")
3981 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3982 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3983 "TARGET_POWER && reload_completed"
3984 [(set (match_dup 0)
3985 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3986 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3987 (set (match_dup 4)
3988 (compare:CC (match_dup 0)
3989 (const_int 0)))]
3990 "")
3992 (define_insn "*maskir_internal8"
3993 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3994 (compare:CC
3995 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3996 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3997 (and:SI (not:SI (match_dup 2))
3998 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3999 (const_int 0)))
4000 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4001 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4002 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4003 "TARGET_POWER"
4004 "@
4005 maskir. %0,%3,%2
4006 #"
4007 [(set_attr "type" "compare")
4008 (set_attr "length" "4,8")])
4010 (define_split
4011 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4012 (compare:CC
4013 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
4014 (match_operand:SI 2 "gpc_reg_operand" ""))
4015 (and:SI (not:SI (match_dup 2))
4016 (match_operand:SI 1 "gpc_reg_operand" "")))
4017 (const_int 0)))
4018 (set (match_operand:SI 0 "gpc_reg_operand" "")
4019 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4020 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4021 "TARGET_POWER && reload_completed"
4022 [(set (match_dup 0)
4023 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4024 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
4025 (set (match_dup 4)
4026 (compare:CC (match_dup 0)
4027 (const_int 0)))]
4028 "")
4029 \f
4030 ;; Rotate and shift insns, in all their variants. These support shifts,
4031 ;; field inserts and extracts, and various combinations thereof.
4032 (define_expand "insv"
4033 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
4034 (match_operand:SI 1 "const_int_operand" "")
4035 (match_operand:SI 2 "const_int_operand" ""))
4036 (match_operand 3 "gpc_reg_operand" ""))]
4037 ""
4038 "
4039 {
4040 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4041 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4042 compiler if the address of the structure is taken later. Likewise, do
4043 not handle invalid E500 subregs. */
4044 if (GET_CODE (operands[0]) == SUBREG
4045 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
4046 || ((TARGET_E500_DOUBLE || TARGET_SPE)
4047 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
4048 FAIL;
4050 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
4051 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
4052 else
4053 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
4054 DONE;
4055 }")
4057 (define_insn "insvsi"
4058 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4059 (match_operand:SI 1 "const_int_operand" "i")
4060 (match_operand:SI 2 "const_int_operand" "i"))
4061 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4062 ""
4063 "*
4064 {
4065 int start = INTVAL (operands[2]) & 31;
4066 int size = INTVAL (operands[1]) & 31;
4068 operands[4] = GEN_INT (32 - start - size);
4069 operands[1] = GEN_INT (start + size - 1);
4070 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4071 }"
4072 [(set_attr "type" "insert_word")])
4074 (define_insn "*insvsi_internal1"
4075 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4076 (match_operand:SI 1 "const_int_operand" "i")
4077 (match_operand:SI 2 "const_int_operand" "i"))
4078 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4079 (match_operand:SI 4 "const_int_operand" "i")))]
4080 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4081 "*
4082 {
4083 int shift = INTVAL (operands[4]) & 31;
4084 int start = INTVAL (operands[2]) & 31;
4085 int size = INTVAL (operands[1]) & 31;
4087 operands[4] = GEN_INT (shift - start - size);
4088 operands[1] = GEN_INT (start + size - 1);
4089 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4090 }"
4091 [(set_attr "type" "insert_word")])
4093 (define_insn "*insvsi_internal2"
4094 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4095 (match_operand:SI 1 "const_int_operand" "i")
4096 (match_operand:SI 2 "const_int_operand" "i"))
4097 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4098 (match_operand:SI 4 "const_int_operand" "i")))]
4099 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4100 "*
4101 {
4102 int shift = INTVAL (operands[4]) & 31;
4103 int start = INTVAL (operands[2]) & 31;
4104 int size = INTVAL (operands[1]) & 31;
4106 operands[4] = GEN_INT (32 - shift - start - size);
4107 operands[1] = GEN_INT (start + size - 1);
4108 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4109 }"
4110 [(set_attr "type" "insert_word")])
4112 (define_insn "*insvsi_internal3"
4113 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4114 (match_operand:SI 1 "const_int_operand" "i")
4115 (match_operand:SI 2 "const_int_operand" "i"))
4116 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4117 (match_operand:SI 4 "const_int_operand" "i")))]
4118 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4119 "*
4120 {
4121 int shift = INTVAL (operands[4]) & 31;
4122 int start = INTVAL (operands[2]) & 31;
4123 int size = INTVAL (operands[1]) & 31;
4125 operands[4] = GEN_INT (32 - shift - start - size);
4126 operands[1] = GEN_INT (start + size - 1);
4127 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4128 }"
4129 [(set_attr "type" "insert_word")])
4131 (define_insn "*insvsi_internal4"
4132 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4133 (match_operand:SI 1 "const_int_operand" "i")
4134 (match_operand:SI 2 "const_int_operand" "i"))
4135 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4136 (match_operand:SI 4 "const_int_operand" "i")
4137 (match_operand:SI 5 "const_int_operand" "i")))]
4138 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4139 "*
4140 {
4141 int extract_start = INTVAL (operands[5]) & 31;
4142 int extract_size = INTVAL (operands[4]) & 31;
4143 int insert_start = INTVAL (operands[2]) & 31;
4144 int insert_size = INTVAL (operands[1]) & 31;
4146 /* Align extract field with insert field */
4147 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4148 operands[1] = GEN_INT (insert_start + insert_size - 1);
4149 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4150 }"
4151 [(set_attr "type" "insert_word")])
4153 ;; combine patterns for rlwimi
4154 (define_insn "*insvsi_internal5"
4155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4156 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4157 (match_operand:SI 1 "mask_operand" "i"))
4158 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4159 (match_operand:SI 2 "const_int_operand" "i"))
4160 (match_operand:SI 5 "mask_operand" "i"))))]
4161 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4162 "*
4163 {
4164 int me = extract_ME(operands[5]);
4165 int mb = extract_MB(operands[5]);
4166 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4167 operands[2] = GEN_INT(mb);
4168 operands[1] = GEN_INT(me);
4169 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4170 }"
4171 [(set_attr "type" "insert_word")])
4173 (define_insn "*insvsi_internal6"
4174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4175 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4176 (match_operand:SI 2 "const_int_operand" "i"))
4177 (match_operand:SI 5 "mask_operand" "i"))
4178 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4179 (match_operand:SI 1 "mask_operand" "i"))))]
4180 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4181 "*
4182 {
4183 int me = extract_ME(operands[5]);
4184 int mb = extract_MB(operands[5]);
4185 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4186 operands[2] = GEN_INT(mb);
4187 operands[1] = GEN_INT(me);
4188 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4189 }"
4190 [(set_attr "type" "insert_word")])
4192 (define_insn "insvdi"
4193 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4194 (match_operand:SI 1 "const_int_operand" "i")
4195 (match_operand:SI 2 "const_int_operand" "i"))
4196 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4197 "TARGET_POWERPC64"
4198 "*
4199 {
4200 int start = INTVAL (operands[2]) & 63;
4201 int size = INTVAL (operands[1]) & 63;
4203 operands[1] = GEN_INT (64 - start - size);
4204 return \"rldimi %0,%3,%H1,%H2\";
4205 }"
4206 [(set_attr "type" "insert_dword")])
4208 (define_insn "*insvdi_internal2"
4209 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4210 (match_operand:SI 1 "const_int_operand" "i")
4211 (match_operand:SI 2 "const_int_operand" "i"))
4212 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4213 (match_operand:SI 4 "const_int_operand" "i")))]
4214 "TARGET_POWERPC64
4215 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4216 "*
4217 {
4218 int shift = INTVAL (operands[4]) & 63;
4219 int start = (INTVAL (operands[2]) & 63) - 32;
4220 int size = INTVAL (operands[1]) & 63;
4222 operands[4] = GEN_INT (64 - shift - start - size);
4223 operands[2] = GEN_INT (start);
4224 operands[1] = GEN_INT (start + size - 1);
4225 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4226 }")
4228 (define_insn "*insvdi_internal3"
4229 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4230 (match_operand:SI 1 "const_int_operand" "i")
4231 (match_operand:SI 2 "const_int_operand" "i"))
4232 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4233 (match_operand:SI 4 "const_int_operand" "i")))]
4234 "TARGET_POWERPC64
4235 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4236 "*
4237 {
4238 int shift = INTVAL (operands[4]) & 63;
4239 int start = (INTVAL (operands[2]) & 63) - 32;
4240 int size = INTVAL (operands[1]) & 63;
4242 operands[4] = GEN_INT (64 - shift - start - size);
4243 operands[2] = GEN_INT (start);
4244 operands[1] = GEN_INT (start + size - 1);
4245 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4246 }")
4248 (define_expand "extzv"
4249 [(set (match_operand 0 "gpc_reg_operand" "")
4250 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4251 (match_operand:SI 2 "const_int_operand" "")
4252 (match_operand:SI 3 "const_int_operand" "")))]
4253 ""
4254 "
4255 {
4256 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4257 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4258 compiler if the address of the structure is taken later. */
4259 if (GET_CODE (operands[0]) == SUBREG
4260 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4261 FAIL;
4263 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4264 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4265 else
4266 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4267 DONE;
4268 }")
4270 (define_insn "extzvsi"
4271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4272 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4273 (match_operand:SI 2 "const_int_operand" "i")
4274 (match_operand:SI 3 "const_int_operand" "i")))]
4275 ""
4276 "*
4277 {
4278 int start = INTVAL (operands[3]) & 31;
4279 int size = INTVAL (operands[2]) & 31;
4281 if (start + size >= 32)
4282 operands[3] = const0_rtx;
4283 else
4284 operands[3] = GEN_INT (start + size);
4285 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4286 }")
4288 (define_insn "*extzvsi_internal1"
4289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4290 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4291 (match_operand:SI 2 "const_int_operand" "i,i")
4292 (match_operand:SI 3 "const_int_operand" "i,i"))
4293 (const_int 0)))
4294 (clobber (match_scratch:SI 4 "=r,r"))]
4295 ""
4296 "*
4297 {
4298 int start = INTVAL (operands[3]) & 31;
4299 int size = INTVAL (operands[2]) & 31;
4301 /* Force split for non-cc0 compare. */
4302 if (which_alternative == 1)
4303 return \"#\";
4305 /* If the bit-field being tested fits in the upper or lower half of a
4306 word, it is possible to use andiu. or andil. to test it. This is
4307 useful because the condition register set-use delay is smaller for
4308 andi[ul]. than for rlinm. This doesn't work when the starting bit
4309 position is 0 because the LT and GT bits may be set wrong. */
4311 if ((start > 0 && start + size <= 16) || start >= 16)
4312 {
4313 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4314 - (1 << (16 - (start & 15) - size))));
4315 if (start < 16)
4316 return \"{andiu.|andis.} %4,%1,%3\";
4317 else
4318 return \"{andil.|andi.} %4,%1,%3\";
4319 }
4321 if (start + size >= 32)
4322 operands[3] = const0_rtx;
4323 else
4324 operands[3] = GEN_INT (start + size);
4325 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4326 }"
4327 [(set_attr "type" "delayed_compare")
4328 (set_attr "length" "4,8")])
4330 (define_split
4331 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4332 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4333 (match_operand:SI 2 "const_int_operand" "")
4334 (match_operand:SI 3 "const_int_operand" ""))
4335 (const_int 0)))
4336 (clobber (match_scratch:SI 4 ""))]
4337 "reload_completed"
4338 [(set (match_dup 4)
4339 (zero_extract:SI (match_dup 1) (match_dup 2)
4340 (match_dup 3)))
4341 (set (match_dup 0)
4342 (compare:CC (match_dup 4)
4343 (const_int 0)))]
4344 "")
4346 (define_insn "*extzvsi_internal2"
4347 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4348 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4349 (match_operand:SI 2 "const_int_operand" "i,i")
4350 (match_operand:SI 3 "const_int_operand" "i,i"))
4351 (const_int 0)))
4352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4353 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4354 ""
4355 "*
4356 {
4357 int start = INTVAL (operands[3]) & 31;
4358 int size = INTVAL (operands[2]) & 31;
4360 /* Force split for non-cc0 compare. */
4361 if (which_alternative == 1)
4362 return \"#\";
4364 /* Since we are using the output value, we can't ignore any need for
4365 a shift. The bit-field must end at the LSB. */
4366 if (start >= 16 && start + size == 32)
4367 {
4368 operands[3] = GEN_INT ((1 << size) - 1);
4369 return \"{andil.|andi.} %0,%1,%3\";
4370 }
4372 if (start + size >= 32)
4373 operands[3] = const0_rtx;
4374 else
4375 operands[3] = GEN_INT (start + size);
4376 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4377 }"
4378 [(set_attr "type" "delayed_compare")
4379 (set_attr "length" "4,8")])
4381 (define_split
4382 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4383 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4384 (match_operand:SI 2 "const_int_operand" "")
4385 (match_operand:SI 3 "const_int_operand" ""))
4386 (const_int 0)))
4387 (set (match_operand:SI 0 "gpc_reg_operand" "")
4388 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4389 "reload_completed"
4390 [(set (match_dup 0)
4391 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4392 (set (match_dup 4)
4393 (compare:CC (match_dup 0)
4394 (const_int 0)))]
4395 "")
4397 (define_insn "extzvdi"
4398 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4399 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4400 (match_operand:SI 2 "const_int_operand" "i")
4401 (match_operand:SI 3 "const_int_operand" "i")))]
4402 "TARGET_POWERPC64"
4403 "*
4404 {
4405 int start = INTVAL (operands[3]) & 63;
4406 int size = INTVAL (operands[2]) & 63;
4408 if (start + size >= 64)
4409 operands[3] = const0_rtx;
4410 else
4411 operands[3] = GEN_INT (start + size);
4412 operands[2] = GEN_INT (64 - size);
4413 return \"rldicl %0,%1,%3,%2\";
4414 }")
4416 (define_insn "*extzvdi_internal1"
4417 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4418 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4419 (match_operand:SI 2 "const_int_operand" "i")
4420 (match_operand:SI 3 "const_int_operand" "i"))
4421 (const_int 0)))
4422 (clobber (match_scratch:DI 4 "=r"))]
4423 "TARGET_64BIT && rs6000_gen_cell_microcode"
4424 "*
4425 {
4426 int start = INTVAL (operands[3]) & 63;
4427 int size = INTVAL (operands[2]) & 63;
4429 if (start + size >= 64)
4430 operands[3] = const0_rtx;
4431 else
4432 operands[3] = GEN_INT (start + size);
4433 operands[2] = GEN_INT (64 - size);
4434 return \"rldicl. %4,%1,%3,%2\";
4435 }"
4436 [(set_attr "type" "compare")])
4438 (define_insn "*extzvdi_internal2"
4439 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4440 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4441 (match_operand:SI 2 "const_int_operand" "i")
4442 (match_operand:SI 3 "const_int_operand" "i"))
4443 (const_int 0)))
4444 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4445 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4446 "TARGET_64BIT && rs6000_gen_cell_microcode"
4447 "*
4448 {
4449 int start = INTVAL (operands[3]) & 63;
4450 int size = INTVAL (operands[2]) & 63;
4452 if (start + size >= 64)
4453 operands[3] = const0_rtx;
4454 else
4455 operands[3] = GEN_INT (start + size);
4456 operands[2] = GEN_INT (64 - size);
4457 return \"rldicl. %0,%1,%3,%2\";
4458 }"
4459 [(set_attr "type" "compare")])
4461 (define_insn "rotlsi3"
4462 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4463 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4464 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4465 ""
4466 "@
4467 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4468 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4469 [(set_attr "type" "var_shift_rotate,integer")])
4471 (define_insn "*rotlsi3_64"
4472 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4473 (zero_extend:DI
4474 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4475 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4476 "TARGET_64BIT"
4477 "@
4478 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4479 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4480 [(set_attr "type" "var_shift_rotate,integer")])
4482 (define_insn "*rotlsi3_internal2"
4483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4484 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4485 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4486 (const_int 0)))
4487 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4488 ""
4489 "@
4490 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4491 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4492 #
4493 #"
4494 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4495 (set_attr "length" "4,4,8,8")])
4497 (define_split
4498 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4499 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4500 (match_operand:SI 2 "reg_or_cint_operand" ""))
4501 (const_int 0)))
4502 (clobber (match_scratch:SI 3 ""))]
4503 "reload_completed"
4504 [(set (match_dup 3)
4505 (rotate:SI (match_dup 1) (match_dup 2)))
4506 (set (match_dup 0)
4507 (compare:CC (match_dup 3)
4508 (const_int 0)))]
4509 "")
4511 (define_insn "*rotlsi3_internal3"
4512 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4513 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4514 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4515 (const_int 0)))
4516 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4517 (rotate:SI (match_dup 1) (match_dup 2)))]
4518 ""
4519 "@
4520 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4521 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4522 #
4523 #"
4524 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4525 (set_attr "length" "4,4,8,8")])
4527 (define_split
4528 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4529 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4530 (match_operand:SI 2 "reg_or_cint_operand" ""))
4531 (const_int 0)))
4532 (set (match_operand:SI 0 "gpc_reg_operand" "")
4533 (rotate:SI (match_dup 1) (match_dup 2)))]
4534 "reload_completed"
4535 [(set (match_dup 0)
4536 (rotate:SI (match_dup 1) (match_dup 2)))
4537 (set (match_dup 3)
4538 (compare:CC (match_dup 0)
4539 (const_int 0)))]
4540 "")
4542 (define_insn "*rotlsi3_internal4"
4543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4544 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4545 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4546 (match_operand:SI 3 "mask_operand" "n,n")))]
4547 ""
4548 "@
4549 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4550 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4551 [(set_attr "type" "var_shift_rotate,integer")])
4553 (define_insn "*rotlsi3_internal5"
4554 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4555 (compare:CC (and:SI
4556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4557 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4558 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4559 (const_int 0)))
4560 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4561 ""
4562 "@
4563 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4564 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4565 #
4566 #"
4567 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4568 (set_attr "length" "4,4,8,8")])
4570 (define_split
4571 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4572 (compare:CC (and:SI
4573 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4574 (match_operand:SI 2 "reg_or_cint_operand" ""))
4575 (match_operand:SI 3 "mask_operand" ""))
4576 (const_int 0)))
4577 (clobber (match_scratch:SI 4 ""))]
4578 "reload_completed"
4579 [(set (match_dup 4)
4580 (and:SI (rotate:SI (match_dup 1)
4581 (match_dup 2))
4582 (match_dup 3)))
4583 (set (match_dup 0)
4584 (compare:CC (match_dup 4)
4585 (const_int 0)))]
4586 "")
4588 (define_insn "*rotlsi3_internal6"
4589 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4590 (compare:CC (and:SI
4591 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4592 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4593 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4594 (const_int 0)))
4595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4596 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4597 ""
4598 "@
4599 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4600 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4601 #
4602 #"
4603 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4604 (set_attr "length" "4,4,8,8")])
4606 (define_split
4607 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4608 (compare:CC (and:SI
4609 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4610 (match_operand:SI 2 "reg_or_cint_operand" ""))
4611 (match_operand:SI 3 "mask_operand" ""))
4612 (const_int 0)))
4613 (set (match_operand:SI 0 "gpc_reg_operand" "")
4614 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4615 "reload_completed"
4616 [(set (match_dup 0)
4617 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4618 (set (match_dup 4)
4619 (compare:CC (match_dup 0)
4620 (const_int 0)))]
4621 "")
4623 (define_insn "*rotlsi3_internal7"
4624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4625 (zero_extend:SI
4626 (subreg:QI
4627 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4628 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4629 ""
4630 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4631 [(set (attr "cell_micro")
4632 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4633 (const_string "not")
4634 (const_string "always")))])
4636 (define_insn "*rotlsi3_internal8"
4637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4638 (compare:CC (zero_extend:SI
4639 (subreg:QI
4640 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4641 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4642 (const_int 0)))
4643 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4644 ""
4645 "@
4646 {rlnm.|rlwnm.} %3,%1,%2,0xff
4647 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4648 #
4649 #"
4650 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4651 (set_attr "length" "4,4,8,8")])
4653 (define_split
4654 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4655 (compare:CC (zero_extend:SI
4656 (subreg:QI
4657 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4658 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4659 (const_int 0)))
4660 (clobber (match_scratch:SI 3 ""))]
4661 "reload_completed"
4662 [(set (match_dup 3)
4663 (zero_extend:SI (subreg:QI
4664 (rotate:SI (match_dup 1)
4665 (match_dup 2)) 0)))
4666 (set (match_dup 0)
4667 (compare:CC (match_dup 3)
4668 (const_int 0)))]
4669 "")
4671 (define_insn "*rotlsi3_internal9"
4672 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4673 (compare:CC (zero_extend:SI
4674 (subreg:QI
4675 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4676 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4677 (const_int 0)))
4678 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4679 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4680 ""
4681 "@
4682 {rlnm.|rlwnm.} %0,%1,%2,0xff
4683 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4684 #
4685 #"
4686 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4687 (set_attr "length" "4,4,8,8")])
4689 (define_split
4690 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4691 (compare:CC (zero_extend:SI
4692 (subreg:QI
4693 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4694 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4695 (const_int 0)))
4696 (set (match_operand:SI 0 "gpc_reg_operand" "")
4697 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4698 "reload_completed"
4699 [(set (match_dup 0)
4700 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4701 (set (match_dup 3)
4702 (compare:CC (match_dup 0)
4703 (const_int 0)))]
4704 "")
4706 (define_insn "*rotlsi3_internal10"
4707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4708 (zero_extend:SI
4709 (subreg:HI
4710 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4711 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4712 ""
4713 "@
4714 {rlnm|rlwnm} %0,%1,%2,0xffff
4715 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4716 [(set_attr "type" "var_shift_rotate,integer")])
4719 (define_insn "*rotlsi3_internal11"
4720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4721 (compare:CC (zero_extend:SI
4722 (subreg:HI
4723 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4724 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4725 (const_int 0)))
4726 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4727 ""
4728 "@
4729 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4730 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4731 #
4732 #"
4733 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4734 (set_attr "length" "4,4,8,8")])
4736 (define_split
4737 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4738 (compare:CC (zero_extend:SI
4739 (subreg:HI
4740 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4741 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4742 (const_int 0)))
4743 (clobber (match_scratch:SI 3 ""))]
4744 "reload_completed"
4745 [(set (match_dup 3)
4746 (zero_extend:SI (subreg:HI
4747 (rotate:SI (match_dup 1)
4748 (match_dup 2)) 0)))
4749 (set (match_dup 0)
4750 (compare:CC (match_dup 3)
4751 (const_int 0)))]
4752 "")
4754 (define_insn "*rotlsi3_internal12"
4755 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4756 (compare:CC (zero_extend:SI
4757 (subreg:HI
4758 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4759 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4760 (const_int 0)))
4761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4762 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4763 ""
4764 "@
4765 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4766 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4767 #
4768 #"
4769 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4770 (set_attr "length" "4,4,8,8")])
4772 (define_split
4773 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4774 (compare:CC (zero_extend:SI
4775 (subreg:HI
4776 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4777 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4778 (const_int 0)))
4779 (set (match_operand:SI 0 "gpc_reg_operand" "")
4780 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4781 "reload_completed"
4782 [(set (match_dup 0)
4783 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4784 (set (match_dup 3)
4785 (compare:CC (match_dup 0)
4786 (const_int 0)))]
4787 "")
4789 ;; Note that we use "sle." instead of "sl." so that we can set
4790 ;; SHIFT_COUNT_TRUNCATED.
4792 (define_expand "ashlsi3"
4793 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4794 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4795 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4796 ""
4797 "
4798 {
4799 if (TARGET_POWER)
4800 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4801 else
4802 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4803 DONE;
4804 }")
4806 (define_insn "ashlsi3_power"
4807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4808 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4809 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4810 (clobber (match_scratch:SI 3 "=q,X"))]
4811 "TARGET_POWER"
4812 "@
4813 sle %0,%1,%2
4814 {sli|slwi} %0,%1,%h2")
4816 (define_insn "ashlsi3_no_power"
4817 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4818 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4819 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4820 "! TARGET_POWER"
4821 "@
4822 {sl|slw} %0,%1,%2
4823 {sli|slwi} %0,%1,%h2"
4824 [(set_attr "type" "var_shift_rotate,shift")])
4826 (define_insn "*ashlsi3_64"
4827 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4828 (zero_extend:DI
4829 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4830 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4831 "TARGET_POWERPC64"
4832 "@
4833 {sl|slw} %0,%1,%2
4834 {sli|slwi} %0,%1,%h2"
4835 [(set_attr "type" "var_shift_rotate,shift")])
4837 (define_insn ""
4838 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4839 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4840 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4841 (const_int 0)))
4842 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4843 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4844 "TARGET_POWER"
4845 "@
4846 sle. %3,%1,%2
4847 {sli.|slwi.} %3,%1,%h2
4848 #
4849 #"
4850 [(set_attr "type" "delayed_compare")
4851 (set_attr "length" "4,4,8,8")])
4853 (define_split
4854 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4855 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4856 (match_operand:SI 2 "reg_or_cint_operand" ""))
4857 (const_int 0)))
4858 (clobber (match_scratch:SI 3 ""))
4859 (clobber (match_scratch:SI 4 ""))]
4860 "TARGET_POWER && reload_completed"
4861 [(parallel [(set (match_dup 3)
4862 (ashift:SI (match_dup 1) (match_dup 2)))
4863 (clobber (match_dup 4))])
4864 (set (match_dup 0)
4865 (compare:CC (match_dup 3)
4866 (const_int 0)))]
4867 "")
4869 (define_insn ""
4870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4871 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4872 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4873 (const_int 0)))
4874 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4875 "! TARGET_POWER && TARGET_32BIT"
4876 "@
4877 {sl.|slw.} %3,%1,%2
4878 {sli.|slwi.} %3,%1,%h2
4879 #
4880 #"
4881 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4882 (set_attr "length" "4,4,8,8")])
4884 (define_split
4885 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4886 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4887 (match_operand:SI 2 "reg_or_cint_operand" ""))
4888 (const_int 0)))
4889 (clobber (match_scratch:SI 3 ""))]
4890 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4891 [(set (match_dup 3)
4892 (ashift:SI (match_dup 1) (match_dup 2)))
4893 (set (match_dup 0)
4894 (compare:CC (match_dup 3)
4895 (const_int 0)))]
4896 "")
4898 (define_insn ""
4899 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4900 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4901 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4902 (const_int 0)))
4903 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4904 (ashift:SI (match_dup 1) (match_dup 2)))
4905 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4906 "TARGET_POWER"
4907 "@
4908 sle. %0,%1,%2
4909 {sli.|slwi.} %0,%1,%h2
4910 #
4911 #"
4912 [(set_attr "type" "delayed_compare")
4913 (set_attr "length" "4,4,8,8")])
4915 (define_split
4916 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4917 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4918 (match_operand:SI 2 "reg_or_cint_operand" ""))
4919 (const_int 0)))
4920 (set (match_operand:SI 0 "gpc_reg_operand" "")
4921 (ashift:SI (match_dup 1) (match_dup 2)))
4922 (clobber (match_scratch:SI 4 ""))]
4923 "TARGET_POWER && reload_completed"
4924 [(parallel [(set (match_dup 0)
4925 (ashift:SI (match_dup 1) (match_dup 2)))
4926 (clobber (match_dup 4))])
4927 (set (match_dup 3)
4928 (compare:CC (match_dup 0)
4929 (const_int 0)))]
4930 "")
4932 (define_insn ""
4933 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4934 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4935 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4936 (const_int 0)))
4937 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4938 (ashift:SI (match_dup 1) (match_dup 2)))]
4939 "! TARGET_POWER && TARGET_32BIT"
4940 "@
4941 {sl.|slw.} %0,%1,%2
4942 {sli.|slwi.} %0,%1,%h2
4943 #
4944 #"
4945 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4946 (set_attr "length" "4,4,8,8")])
4948 (define_split
4949 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4950 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4951 (match_operand:SI 2 "reg_or_cint_operand" ""))
4952 (const_int 0)))
4953 (set (match_operand:SI 0 "gpc_reg_operand" "")
4954 (ashift:SI (match_dup 1) (match_dup 2)))]
4955 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4956 [(set (match_dup 0)
4957 (ashift:SI (match_dup 1) (match_dup 2)))
4958 (set (match_dup 3)
4959 (compare:CC (match_dup 0)
4960 (const_int 0)))]
4961 "")
4963 (define_insn "rlwinm"
4964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4965 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4966 (match_operand:SI 2 "const_int_operand" "i"))
4967 (match_operand:SI 3 "mask_operand" "n")))]
4968 "includes_lshift_p (operands[2], operands[3])"
4969 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4971 (define_insn ""
4972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4973 (compare:CC
4974 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4975 (match_operand:SI 2 "const_int_operand" "i,i"))
4976 (match_operand:SI 3 "mask_operand" "n,n"))
4977 (const_int 0)))
4978 (clobber (match_scratch:SI 4 "=r,r"))]
4979 "includes_lshift_p (operands[2], operands[3])"
4980 "@
4981 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4982 #"
4983 [(set_attr "type" "delayed_compare")
4984 (set_attr "length" "4,8")])
4986 (define_split
4987 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4988 (compare:CC
4989 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4990 (match_operand:SI 2 "const_int_operand" ""))
4991 (match_operand:SI 3 "mask_operand" ""))
4992 (const_int 0)))
4993 (clobber (match_scratch:SI 4 ""))]
4994 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4995 [(set (match_dup 4)
4996 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4997 (match_dup 3)))
4998 (set (match_dup 0)
4999 (compare:CC (match_dup 4)
5000 (const_int 0)))]
5001 "")
5003 (define_insn ""
5004 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5005 (compare:CC
5006 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5007 (match_operand:SI 2 "const_int_operand" "i,i"))
5008 (match_operand:SI 3 "mask_operand" "n,n"))
5009 (const_int 0)))
5010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5011 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5012 "includes_lshift_p (operands[2], operands[3])"
5013 "@
5014 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
5015 #"
5016 [(set_attr "type" "delayed_compare")
5017 (set_attr "length" "4,8")])
5019 (define_split
5020 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5021 (compare:CC
5022 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
5023 (match_operand:SI 2 "const_int_operand" ""))
5024 (match_operand:SI 3 "mask_operand" ""))
5025 (const_int 0)))
5026 (set (match_operand:SI 0 "gpc_reg_operand" "")
5027 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5028 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
5029 [(set (match_dup 0)
5030 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5031 (set (match_dup 4)
5032 (compare:CC (match_dup 0)
5033 (const_int 0)))]
5034 "")
5036 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5037 ;; "sli x,x,0".
5038 (define_expand "lshrsi3"
5039 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
5040 (use (match_operand:SI 1 "gpc_reg_operand" ""))
5041 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
5042 ""
5043 "
5044 {
5045 if (TARGET_POWER)
5046 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
5047 else
5048 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
5049 DONE;
5050 }")
5052 (define_insn "lshrsi3_power"
5053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5054 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5055 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
5056 (clobber (match_scratch:SI 3 "=q,X,X"))]
5057 "TARGET_POWER"
5058 "@
5059 sre %0,%1,%2
5060 mr %0,%1
5061 {s%A2i|s%A2wi} %0,%1,%h2")
5063 (define_insn "lshrsi3_no_power"
5064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5065 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5066 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5067 "! TARGET_POWER"
5068 "@
5069 mr %0,%1
5070 {sr|srw} %0,%1,%2
5071 {sri|srwi} %0,%1,%h2"
5072 [(set_attr "type" "integer,var_shift_rotate,shift")])
5074 (define_insn "*lshrsi3_64"
5075 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5076 (zero_extend:DI
5077 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5078 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5079 "TARGET_POWERPC64"
5080 "@
5081 {sr|srw} %0,%1,%2
5082 {sri|srwi} %0,%1,%h2"
5083 [(set_attr "type" "var_shift_rotate,shift")])
5085 (define_insn ""
5086 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5087 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5088 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5089 (const_int 0)))
5090 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5091 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5092 "TARGET_POWER"
5093 "@
5094 sre. %3,%1,%2
5095 mr. %1,%1
5096 {s%A2i.|s%A2wi.} %3,%1,%h2
5097 #
5098 #
5099 #"
5100 [(set_attr "type" "delayed_compare")
5101 (set_attr "length" "4,4,4,8,8,8")])
5103 (define_split
5104 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5105 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5106 (match_operand:SI 2 "reg_or_cint_operand" ""))
5107 (const_int 0)))
5108 (clobber (match_scratch:SI 3 ""))
5109 (clobber (match_scratch:SI 4 ""))]
5110 "TARGET_POWER && reload_completed"
5111 [(parallel [(set (match_dup 3)
5112 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5113 (clobber (match_dup 4))])
5114 (set (match_dup 0)
5115 (compare:CC (match_dup 3)
5116 (const_int 0)))]
5117 "")
5119 (define_insn ""
5120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5121 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5122 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5123 (const_int 0)))
5124 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5125 "! TARGET_POWER && TARGET_32BIT"
5126 "@
5127 mr. %1,%1
5128 {sr.|srw.} %3,%1,%2
5129 {sri.|srwi.} %3,%1,%h2
5130 #
5131 #
5132 #"
5133 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5134 (set_attr "length" "4,4,4,8,8,8")])
5136 (define_split
5137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5138 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5139 (match_operand:SI 2 "reg_or_cint_operand" ""))
5140 (const_int 0)))
5141 (clobber (match_scratch:SI 3 ""))]
5142 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5143 [(set (match_dup 3)
5144 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5145 (set (match_dup 0)
5146 (compare:CC (match_dup 3)
5147 (const_int 0)))]
5148 "")
5150 (define_insn ""
5151 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5152 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5153 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5154 (const_int 0)))
5155 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5156 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5157 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5158 "TARGET_POWER"
5159 "@
5160 sre. %0,%1,%2
5161 mr. %0,%1
5162 {s%A2i.|s%A2wi.} %0,%1,%h2
5163 #
5164 #
5165 #"
5166 [(set_attr "type" "delayed_compare")
5167 (set_attr "length" "4,4,4,8,8,8")])
5169 (define_split
5170 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5171 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5172 (match_operand:SI 2 "reg_or_cint_operand" ""))
5173 (const_int 0)))
5174 (set (match_operand:SI 0 "gpc_reg_operand" "")
5175 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5176 (clobber (match_scratch:SI 4 ""))]
5177 "TARGET_POWER && reload_completed"
5178 [(parallel [(set (match_dup 0)
5179 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5180 (clobber (match_dup 4))])
5181 (set (match_dup 3)
5182 (compare:CC (match_dup 0)
5183 (const_int 0)))]
5184 "")
5186 (define_insn ""
5187 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5188 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5189 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5190 (const_int 0)))
5191 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5192 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5193 "! TARGET_POWER && TARGET_32BIT"
5194 "@
5195 mr. %0,%1
5196 {sr.|srw.} %0,%1,%2
5197 {sri.|srwi.} %0,%1,%h2
5198 #
5199 #
5200 #"
5201 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5202 (set_attr "length" "4,4,4,8,8,8")])
5204 (define_split
5205 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5206 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5207 (match_operand:SI 2 "reg_or_cint_operand" ""))
5208 (const_int 0)))
5209 (set (match_operand:SI 0 "gpc_reg_operand" "")
5210 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5211 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5212 [(set (match_dup 0)
5213 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5214 (set (match_dup 3)
5215 (compare:CC (match_dup 0)
5216 (const_int 0)))]
5217 "")
5219 (define_insn ""
5220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5221 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5222 (match_operand:SI 2 "const_int_operand" "i"))
5223 (match_operand:SI 3 "mask_operand" "n")))]
5224 "includes_rshift_p (operands[2], operands[3])"
5225 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5227 (define_insn ""
5228 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5229 (compare:CC
5230 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5231 (match_operand:SI 2 "const_int_operand" "i,i"))
5232 (match_operand:SI 3 "mask_operand" "n,n"))
5233 (const_int 0)))
5234 (clobber (match_scratch:SI 4 "=r,r"))]
5235 "includes_rshift_p (operands[2], operands[3])"
5236 "@
5237 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5238 #"
5239 [(set_attr "type" "delayed_compare")
5240 (set_attr "length" "4,8")])
5242 (define_split
5243 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5244 (compare:CC
5245 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5246 (match_operand:SI 2 "const_int_operand" ""))
5247 (match_operand:SI 3 "mask_operand" ""))
5248 (const_int 0)))
5249 (clobber (match_scratch:SI 4 ""))]
5250 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5251 [(set (match_dup 4)
5252 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5253 (match_dup 3)))
5254 (set (match_dup 0)
5255 (compare:CC (match_dup 4)
5256 (const_int 0)))]
5257 "")
5259 (define_insn ""
5260 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5261 (compare:CC
5262 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5263 (match_operand:SI 2 "const_int_operand" "i,i"))
5264 (match_operand:SI 3 "mask_operand" "n,n"))
5265 (const_int 0)))
5266 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5267 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5268 "includes_rshift_p (operands[2], operands[3])"
5269 "@
5270 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5271 #"
5272 [(set_attr "type" "delayed_compare")
5273 (set_attr "length" "4,8")])
5275 (define_split
5276 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5277 (compare:CC
5278 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5279 (match_operand:SI 2 "const_int_operand" ""))
5280 (match_operand:SI 3 "mask_operand" ""))
5281 (const_int 0)))
5282 (set (match_operand:SI 0 "gpc_reg_operand" "")
5283 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5284 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5285 [(set (match_dup 0)
5286 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5287 (set (match_dup 4)
5288 (compare:CC (match_dup 0)
5289 (const_int 0)))]
5290 "")
5292 (define_insn ""
5293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5294 (zero_extend:SI
5295 (subreg:QI
5296 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5297 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5298 "includes_rshift_p (operands[2], GEN_INT (255))"
5299 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5301 (define_insn ""
5302 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5303 (compare:CC
5304 (zero_extend:SI
5305 (subreg:QI
5306 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5307 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5308 (const_int 0)))
5309 (clobber (match_scratch:SI 3 "=r,r"))]
5310 "includes_rshift_p (operands[2], GEN_INT (255))"
5311 "@
5312 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5313 #"
5314 [(set_attr "type" "delayed_compare")
5315 (set_attr "length" "4,8")])
5317 (define_split
5318 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5319 (compare:CC
5320 (zero_extend:SI
5321 (subreg:QI
5322 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5323 (match_operand:SI 2 "const_int_operand" "")) 0))
5324 (const_int 0)))
5325 (clobber (match_scratch:SI 3 ""))]
5326 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5327 [(set (match_dup 3)
5328 (zero_extend:SI (subreg:QI
5329 (lshiftrt:SI (match_dup 1)
5330 (match_dup 2)) 0)))
5331 (set (match_dup 0)
5332 (compare:CC (match_dup 3)
5333 (const_int 0)))]
5334 "")
5336 (define_insn ""
5337 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5338 (compare:CC
5339 (zero_extend:SI
5340 (subreg:QI
5341 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5342 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5343 (const_int 0)))
5344 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5345 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5346 "includes_rshift_p (operands[2], GEN_INT (255))"
5347 "@
5348 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5349 #"
5350 [(set_attr "type" "delayed_compare")
5351 (set_attr "length" "4,8")])
5353 (define_split
5354 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5355 (compare:CC
5356 (zero_extend:SI
5357 (subreg:QI
5358 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5359 (match_operand:SI 2 "const_int_operand" "")) 0))
5360 (const_int 0)))
5361 (set (match_operand:SI 0 "gpc_reg_operand" "")
5362 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5363 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5364 [(set (match_dup 0)
5365 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5366 (set (match_dup 3)
5367 (compare:CC (match_dup 0)
5368 (const_int 0)))]
5369 "")
5371 (define_insn ""
5372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5373 (zero_extend:SI
5374 (subreg:HI
5375 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5376 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5377 "includes_rshift_p (operands[2], GEN_INT (65535))"
5378 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5380 (define_insn ""
5381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5382 (compare:CC
5383 (zero_extend:SI
5384 (subreg:HI
5385 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5386 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5387 (const_int 0)))
5388 (clobber (match_scratch:SI 3 "=r,r"))]
5389 "includes_rshift_p (operands[2], GEN_INT (65535))"
5390 "@
5391 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5392 #"
5393 [(set_attr "type" "delayed_compare")
5394 (set_attr "length" "4,8")])
5396 (define_split
5397 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5398 (compare:CC
5399 (zero_extend:SI
5400 (subreg:HI
5401 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5402 (match_operand:SI 2 "const_int_operand" "")) 0))
5403 (const_int 0)))
5404 (clobber (match_scratch:SI 3 ""))]
5405 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5406 [(set (match_dup 3)
5407 (zero_extend:SI (subreg:HI
5408 (lshiftrt:SI (match_dup 1)
5409 (match_dup 2)) 0)))
5410 (set (match_dup 0)
5411 (compare:CC (match_dup 3)
5412 (const_int 0)))]
5413 "")
5415 (define_insn ""
5416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5417 (compare:CC
5418 (zero_extend:SI
5419 (subreg:HI
5420 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5421 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5422 (const_int 0)))
5423 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5424 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5425 "includes_rshift_p (operands[2], GEN_INT (65535))"
5426 "@
5427 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5428 #"
5429 [(set_attr "type" "delayed_compare")
5430 (set_attr "length" "4,8")])
5432 (define_split
5433 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5434 (compare:CC
5435 (zero_extend:SI
5436 (subreg:HI
5437 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5438 (match_operand:SI 2 "const_int_operand" "")) 0))
5439 (const_int 0)))
5440 (set (match_operand:SI 0 "gpc_reg_operand" "")
5441 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5442 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5443 [(set (match_dup 0)
5444 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5445 (set (match_dup 3)
5446 (compare:CC (match_dup 0)
5447 (const_int 0)))]
5448 "")
5450 (define_insn ""
5451 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5452 (const_int 1)
5453 (match_operand:SI 1 "gpc_reg_operand" "r"))
5454 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5455 (const_int 31)))]
5456 "TARGET_POWER"
5457 "rrib %0,%1,%2")
5459 (define_insn ""
5460 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5461 (const_int 1)
5462 (match_operand:SI 1 "gpc_reg_operand" "r"))
5463 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5464 (const_int 31)))]
5465 "TARGET_POWER"
5466 "rrib %0,%1,%2")
5468 (define_insn ""
5469 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5470 (const_int 1)
5471 (match_operand:SI 1 "gpc_reg_operand" "r"))
5472 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5473 (const_int 1)
5474 (const_int 0)))]
5475 "TARGET_POWER"
5476 "rrib %0,%1,%2")
5478 (define_expand "ashrsi3"
5479 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5480 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5481 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5482 ""
5483 "
5484 {
5485 if (TARGET_POWER)
5486 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5487 else
5488 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5489 DONE;
5490 }")
5492 (define_insn "ashrsi3_power"
5493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5494 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5495 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5496 (clobber (match_scratch:SI 3 "=q,X"))]
5497 "TARGET_POWER"
5498 "@
5499 srea %0,%1,%2
5500 {srai|srawi} %0,%1,%h2"
5501 [(set_attr "type" "shift")])
5503 (define_insn "ashrsi3_no_power"
5504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5505 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5506 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5507 "! TARGET_POWER"
5508 "@
5509 {sra|sraw} %0,%1,%2
5510 {srai|srawi} %0,%1,%h2"
5511 [(set_attr "type" "var_shift_rotate,shift")])
5513 (define_insn "*ashrsi3_64"
5514 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5515 (sign_extend:DI
5516 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5517 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5518 "TARGET_POWERPC64"
5519 "@
5520 {sra|sraw} %0,%1,%2
5521 {srai|srawi} %0,%1,%h2"
5522 [(set_attr "type" "var_shift_rotate,shift")])
5524 (define_insn ""
5525 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5526 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5527 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5528 (const_int 0)))
5529 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5530 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5531 "TARGET_POWER"
5532 "@
5533 srea. %3,%1,%2
5534 {srai.|srawi.} %3,%1,%h2
5535 #
5536 #"
5537 [(set_attr "type" "delayed_compare")
5538 (set_attr "length" "4,4,8,8")])
5540 (define_split
5541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5542 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5543 (match_operand:SI 2 "reg_or_cint_operand" ""))
5544 (const_int 0)))
5545 (clobber (match_scratch:SI 3 ""))
5546 (clobber (match_scratch:SI 4 ""))]
5547 "TARGET_POWER && reload_completed"
5548 [(parallel [(set (match_dup 3)
5549 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5550 (clobber (match_dup 4))])
5551 (set (match_dup 0)
5552 (compare:CC (match_dup 3)
5553 (const_int 0)))]
5554 "")
5556 (define_insn ""
5557 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5558 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5559 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5560 (const_int 0)))
5561 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5562 "! TARGET_POWER"
5563 "@
5564 {sra.|sraw.} %3,%1,%2
5565 {srai.|srawi.} %3,%1,%h2
5566 #
5567 #"
5568 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5569 (set_attr "length" "4,4,8,8")])
5571 (define_split
5572 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5573 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5574 (match_operand:SI 2 "reg_or_cint_operand" ""))
5575 (const_int 0)))
5576 (clobber (match_scratch:SI 3 ""))]
5577 "! TARGET_POWER && reload_completed"
5578 [(set (match_dup 3)
5579 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5580 (set (match_dup 0)
5581 (compare:CC (match_dup 3)
5582 (const_int 0)))]
5583 "")
5585 (define_insn ""
5586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5587 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5588 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5589 (const_int 0)))
5590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5591 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5592 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5593 "TARGET_POWER"
5594 "@
5595 srea. %0,%1,%2
5596 {srai.|srawi.} %0,%1,%h2
5597 #
5598 #"
5599 [(set_attr "type" "delayed_compare")
5600 (set_attr "length" "4,4,8,8")])
5602 (define_split
5603 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5604 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5605 (match_operand:SI 2 "reg_or_cint_operand" ""))
5606 (const_int 0)))
5607 (set (match_operand:SI 0 "gpc_reg_operand" "")
5608 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5609 (clobber (match_scratch:SI 4 ""))]
5610 "TARGET_POWER && reload_completed"
5611 [(parallel [(set (match_dup 0)
5612 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5613 (clobber (match_dup 4))])
5614 (set (match_dup 3)
5615 (compare:CC (match_dup 0)
5616 (const_int 0)))]
5617 "")
5619 (define_insn ""
5620 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5621 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5622 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5623 (const_int 0)))
5624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5625 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5626 "! TARGET_POWER"
5627 "@
5628 {sra.|sraw.} %0,%1,%2
5629 {srai.|srawi.} %0,%1,%h2
5630 #
5631 #"
5632 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5633 (set_attr "length" "4,4,8,8")])
5634 \f
5635 ;; Builtins to replace a division to generate FRE reciprocal estimate
5636 ;; instructions and the necessary fixup instructions
5637 (define_expand "recip<mode>3"
5638 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5639 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5640 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5641 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5642 {
5643 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5644 DONE;
5645 })
5647 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5648 ;; hardware division. This is only done before register allocation and with
5649 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5650 (define_split
5651 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5652 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5653 (match_operand 2 "gpc_reg_operand" "")))]
5654 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5655 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5656 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5657 [(const_int 0)]
5658 {
5659 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5660 DONE;
5661 })
5663 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5664 ;; appropriate fixup.
5665 (define_expand "rsqrt<mode>2"
5666 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5667 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5668 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5669 {
5670 rs6000_emit_swrsqrt (operands[0], operands[1]);
5671 DONE;
5672 })
5673 \f
5674 (define_split
5675 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5676 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5677 (match_operand:SI 2 "reg_or_cint_operand" ""))
5678 (const_int 0)))
5679 (set (match_operand:SI 0 "gpc_reg_operand" "")
5680 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5681 "! TARGET_POWER && reload_completed"
5682 [(set (match_dup 0)
5683 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5684 (set (match_dup 3)
5685 (compare:CC (match_dup 0)
5686 (const_int 0)))]
5687 "")
5689 ;; Floating-point insns, excluding normal data motion.
5690 ;;
5691 ;; PowerPC has a full set of single-precision floating point instructions.
5692 ;;
5693 ;; For the POWER architecture, we pretend that we have both SFmode and
5694 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5695 ;; The only conversions we will do will be when storing to memory. In that
5696 ;; case, we will use the "frsp" instruction before storing.
5697 ;;
5698 ;; Note that when we store into a single-precision memory location, we need to
5699 ;; use the frsp insn first. If the register being stored isn't dead, we
5700 ;; need a scratch register for the frsp. But this is difficult when the store
5701 ;; is done by reload. It is not incorrect to do the frsp on the register in
5702 ;; this case, we just lose precision that we would have otherwise gotten but
5703 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5705 (define_expand "extendsfdf2"
5706 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5707 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5708 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5709 "")
5711 (define_insn_and_split "*extendsfdf2_fpr"
5712 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5713 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5715 "@
5716 #
5717 fmr %0,%1
5718 lfs%U1%X1 %0,%1"
5719 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5720 [(const_int 0)]
5721 {
5722 emit_note (NOTE_INSN_DELETED);
5723 DONE;
5724 }
5725 [(set_attr "type" "fp,fp,fpload")])
5727 (define_expand "truncdfsf2"
5728 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5729 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5730 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5731 "")
5733 (define_insn "*truncdfsf2_fpr"
5734 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5735 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5736 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5737 "frsp %0,%1"
5738 [(set_attr "type" "fp")])
5740 (define_insn "aux_truncdfsf2"
5741 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5742 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5743 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5744 "frsp %0,%1"
5745 [(set_attr "type" "fp")])
5747 (define_expand "negsf2"
5748 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5749 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5750 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5751 "")
5753 (define_insn "*negsf2"
5754 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5755 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5756 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5757 "fneg %0,%1"
5758 [(set_attr "type" "fp")])
5760 (define_expand "abssf2"
5761 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5762 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5763 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5764 "")
5766 (define_insn "*abssf2"
5767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5768 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5769 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5770 "fabs %0,%1"
5771 [(set_attr "type" "fp")])
5773 (define_insn ""
5774 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5775 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5776 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5777 "fnabs %0,%1"
5778 [(set_attr "type" "fp")])
5780 (define_expand "addsf3"
5781 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5782 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5783 (match_operand:SF 2 "gpc_reg_operand" "")))]
5784 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5785 "")
5787 (define_insn ""
5788 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5789 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5790 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5791 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5792 "fadds %0,%1,%2"
5793 [(set_attr "type" "fp")
5794 (set_attr "fp_type" "fp_addsub_s")])
5796 (define_insn ""
5797 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5798 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5799 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5800 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5801 "{fa|fadd} %0,%1,%2"
5802 [(set_attr "type" "fp")])
5804 (define_expand "subsf3"
5805 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5806 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5807 (match_operand:SF 2 "gpc_reg_operand" "")))]
5808 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5809 "")
5811 (define_insn ""
5812 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5813 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5814 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5815 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5816 "fsubs %0,%1,%2"
5817 [(set_attr "type" "fp")
5818 (set_attr "fp_type" "fp_addsub_s")])
5820 (define_insn ""
5821 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5822 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5823 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5824 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5825 "{fs|fsub} %0,%1,%2"
5826 [(set_attr "type" "fp")])
5828 (define_expand "mulsf3"
5829 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5830 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5831 (match_operand:SF 2 "gpc_reg_operand" "")))]
5832 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5833 "")
5835 (define_insn ""
5836 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5837 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5838 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5839 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5840 "fmuls %0,%1,%2"
5841 [(set_attr "type" "fp")
5842 (set_attr "fp_type" "fp_mul_s")])
5844 (define_insn ""
5845 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5846 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5847 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5848 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5849 "{fm|fmul} %0,%1,%2"
5850 [(set_attr "type" "dmul")])
5852 (define_expand "divsf3"
5853 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5854 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5855 (match_operand:SF 2 "gpc_reg_operand" "")))]
5856 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5857 "")
5859 (define_insn ""
5860 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5861 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5862 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5863 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5864 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5865 "fdivs %0,%1,%2"
5866 [(set_attr "type" "sdiv")])
5868 (define_insn ""
5869 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5870 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5871 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5872 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5873 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5874 "{fd|fdiv} %0,%1,%2"
5875 [(set_attr "type" "ddiv")])
5877 (define_insn "fres"
5878 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5879 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5880 "TARGET_FRES"
5881 "fres %0,%1"
5882 [(set_attr "type" "fp")])
5884 ; builtin fmaf support
5885 (define_insn "*fmasf4_fpr"
5886 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5887 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5888 (match_operand:SF 2 "gpc_reg_operand" "f")
5889 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5890 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5891 {
5892 return (TARGET_POWERPC
5893 ? "fmadds %0,%1,%2,%3"
5894 : "{fma|fmadd} %0,%1,%2,%3");
5895 }
5896 [(set_attr "type" "fp")
5897 (set_attr "fp_type" "fp_maddsub_s")])
5899 (define_insn "*fmssf4_fpr"
5900 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5901 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5902 (match_operand:SF 2 "gpc_reg_operand" "f")
5903 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5904 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5905 {
5906 return (TARGET_POWERPC
5907 ? "fmsubs %0,%1,%2,%3"
5908 : "{fms|fmsub} %0,%1,%2,%3");
5909 }
5910 [(set_attr "type" "fp")
5911 (set_attr "fp_type" "fp_maddsub_s")])
5913 (define_insn "*nfmasf4_fpr"
5914 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5915 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5916 (match_operand:SF 2 "gpc_reg_operand" "f")
5917 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5918 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5919 {
5920 return (TARGET_POWERPC
5921 ? "fnmadds %0,%1,%2,%3"
5922 : "{fnma|fnmadd} %0,%1,%2,%3");
5923 }
5924 [(set_attr "type" "fp")
5925 (set_attr "fp_type" "fp_maddsub_s")])
5927 (define_insn "*nfmssf4_fpr"
5928 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5929 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5930 (match_operand:SF 2 "gpc_reg_operand" "f")
5931 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5932 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5933 {
5934 return (TARGET_POWERPC
5935 ? "fnmsubs %0,%1,%2,%3"
5936 : "{fnms|fnmsub} %0,%1,%2,%3");
5937 }
5938 [(set_attr "type" "fp")
5939 (set_attr "fp_type" "fp_maddsub_s")])
5941 (define_expand "sqrtsf2"
5942 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5943 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5944 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5945 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5946 && !TARGET_SIMPLE_FPU"
5947 "")
5949 (define_insn ""
5950 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5951 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5952 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5953 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5954 "fsqrts %0,%1"
5955 [(set_attr "type" "ssqrt")])
5957 (define_insn ""
5958 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5959 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5960 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5961 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5962 "fsqrt %0,%1"
5963 [(set_attr "type" "dsqrt")])
5965 (define_insn "*rsqrtsf_internal1"
5966 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5967 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5968 UNSPEC_RSQRT))]
5969 "TARGET_FRSQRTES"
5970 "frsqrtes %0,%1"
5971 [(set_attr "type" "fp")])
5973 (define_expand "copysign<mode>3"
5974 [(set (match_dup 3)
5975 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5976 (set (match_dup 4)
5977 (neg:SFDF (abs:SFDF (match_dup 1))))
5978 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5979 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5980 (match_dup 5))
5981 (match_dup 3)
5982 (match_dup 4)))]
5983 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5984 && ((TARGET_PPC_GFXOPT
5985 && !HONOR_NANS (<MODE>mode)
5986 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5987 || TARGET_CMPB
5988 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5989 {
5990 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5991 {
5992 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5993 operands[2]));
5994 DONE;
5995 }
5997 operands[3] = gen_reg_rtx (<MODE>mode);
5998 operands[4] = gen_reg_rtx (<MODE>mode);
5999 operands[5] = CONST0_RTX (<MODE>mode);
6000 })
6002 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
6003 ;; compiler from optimizing -0.0
6004 (define_insn "copysign<mode>3_fcpsgn"
6005 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6006 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
6007 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
6008 UNSPEC_COPYSIGN))]
6009 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6010 "fcpsgn %0,%2,%1"
6011 [(set_attr "type" "fp")])
6013 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6014 ;; fsel instruction and some auxiliary computations. Then we just have a
6015 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6016 ;; combine.
6017 (define_expand "smaxsf3"
6018 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6019 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6020 (match_operand:SF 2 "gpc_reg_operand" ""))
6021 (match_dup 1)
6022 (match_dup 2)))]
6023 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6024 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6025 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6027 (define_expand "sminsf3"
6028 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6029 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6030 (match_operand:SF 2 "gpc_reg_operand" ""))
6031 (match_dup 2)
6032 (match_dup 1)))]
6033 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6034 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6035 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6037 (define_split
6038 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6039 (match_operator:SF 3 "min_max_operator"
6040 [(match_operand:SF 1 "gpc_reg_operand" "")
6041 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6042 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6043 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6044 [(const_int 0)]
6045 "
6046 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6047 operands[1], operands[2]);
6048 DONE;
6049 }")
6051 (define_expand "mov<mode>cc"
6052 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6053 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6054 (match_operand:GPR 2 "gpc_reg_operand" "")
6055 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6056 "TARGET_ISEL<sel>"
6057 "
6058 {
6059 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6060 DONE;
6061 else
6062 FAIL;
6063 }")
6065 ;; We use the BASE_REGS for the isel input operands because, if rA is
6066 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6067 ;; because we may switch the operands and rB may end up being rA.
6068 ;;
6069 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6070 ;; leave out the mode in operand 4 and use one pattern, but reload can
6071 ;; change the mode underneath our feet and then gets confused trying
6072 ;; to reload the value.
6073 (define_insn "isel_signed_<mode>"
6074 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6075 (if_then_else:GPR
6076 (match_operator 1 "scc_comparison_operator"
6077 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6078 (const_int 0)])
6079 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6080 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6081 "TARGET_ISEL<sel>"
6082 "*
6083 { return output_isel (operands); }"
6084 [(set_attr "type" "isel")
6085 (set_attr "length" "4")])
6087 (define_insn "isel_unsigned_<mode>"
6088 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6089 (if_then_else:GPR
6090 (match_operator 1 "scc_comparison_operator"
6091 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6092 (const_int 0)])
6093 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6094 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6095 "TARGET_ISEL<sel>"
6096 "*
6097 { return output_isel (operands); }"
6098 [(set_attr "type" "isel")
6099 (set_attr "length" "4")])
6101 ;; These patterns can be useful for combine; they let combine know that
6102 ;; isel can handle reversed comparisons so long as the operands are
6103 ;; registers.
6105 (define_insn "*isel_reversed_signed_<mode>"
6106 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6107 (if_then_else:GPR
6108 (match_operator 1 "scc_rev_comparison_operator"
6109 [(match_operand:CC 4 "cc_reg_operand" "y")
6110 (const_int 0)])
6111 (match_operand:GPR 2 "gpc_reg_operand" "b")
6112 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6113 "TARGET_ISEL<sel>"
6114 "*
6115 { return output_isel (operands); }"
6116 [(set_attr "type" "isel")
6117 (set_attr "length" "4")])
6119 (define_insn "*isel_reversed_unsigned_<mode>"
6120 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6121 (if_then_else:GPR
6122 (match_operator 1 "scc_rev_comparison_operator"
6123 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6124 (const_int 0)])
6125 (match_operand:GPR 2 "gpc_reg_operand" "b")
6126 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6127 "TARGET_ISEL<sel>"
6128 "*
6129 { return output_isel (operands); }"
6130 [(set_attr "type" "isel")
6131 (set_attr "length" "4")])
6133 (define_expand "movsfcc"
6134 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6135 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6136 (match_operand:SF 2 "gpc_reg_operand" "")
6137 (match_operand:SF 3 "gpc_reg_operand" "")))]
6138 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6139 "
6140 {
6141 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6142 DONE;
6143 else
6144 FAIL;
6145 }")
6147 (define_insn "*fselsfsf4"
6148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6149 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6150 (match_operand:SF 4 "zero_fp_constant" "F"))
6151 (match_operand:SF 2 "gpc_reg_operand" "f")
6152 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6153 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6154 "fsel %0,%1,%2,%3"
6155 [(set_attr "type" "fp")])
6157 (define_insn "*fseldfsf4"
6158 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6159 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6160 (match_operand:DF 4 "zero_fp_constant" "F"))
6161 (match_operand:SF 2 "gpc_reg_operand" "f")
6162 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6163 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6164 "fsel %0,%1,%2,%3"
6165 [(set_attr "type" "fp")])
6167 (define_expand "negdf2"
6168 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6169 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6170 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6171 "")
6173 (define_insn "*negdf2_fpr"
6174 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6175 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6176 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6177 && !VECTOR_UNIT_VSX_P (DFmode)"
6178 "fneg %0,%1"
6179 [(set_attr "type" "fp")])
6181 (define_expand "absdf2"
6182 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6183 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6184 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6185 "")
6187 (define_insn "*absdf2_fpr"
6188 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6189 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6190 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6191 && !VECTOR_UNIT_VSX_P (DFmode)"
6192 "fabs %0,%1"
6193 [(set_attr "type" "fp")])
6195 (define_insn "*nabsdf2_fpr"
6196 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6197 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6198 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6199 && !VECTOR_UNIT_VSX_P (DFmode)"
6200 "fnabs %0,%1"
6201 [(set_attr "type" "fp")])
6203 (define_expand "adddf3"
6204 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6205 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6206 (match_operand:DF 2 "gpc_reg_operand" "")))]
6207 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6208 "")
6210 (define_insn "*adddf3_fpr"
6211 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6212 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6213 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6214 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6215 && !VECTOR_UNIT_VSX_P (DFmode)"
6216 "{fa|fadd} %0,%1,%2"
6217 [(set_attr "type" "fp")
6218 (set_attr "fp_type" "fp_addsub_d")])
6220 (define_expand "subdf3"
6221 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6222 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6223 (match_operand:DF 2 "gpc_reg_operand" "")))]
6224 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6225 "")
6227 (define_insn "*subdf3_fpr"
6228 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6229 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6230 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6231 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6232 && !VECTOR_UNIT_VSX_P (DFmode)"
6233 "{fs|fsub} %0,%1,%2"
6234 [(set_attr "type" "fp")
6235 (set_attr "fp_type" "fp_addsub_d")])
6237 (define_expand "muldf3"
6238 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6239 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6240 (match_operand:DF 2 "gpc_reg_operand" "")))]
6241 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6242 "")
6244 (define_insn "*muldf3_fpr"
6245 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6246 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6247 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6248 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6249 && !VECTOR_UNIT_VSX_P (DFmode)"
6250 "{fm|fmul} %0,%1,%2"
6251 [(set_attr "type" "dmul")
6252 (set_attr "fp_type" "fp_mul_d")])
6254 (define_expand "divdf3"
6255 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6256 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6257 (match_operand:DF 2 "gpc_reg_operand" "")))]
6258 "TARGET_HARD_FLOAT
6259 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6260 && !TARGET_SIMPLE_FPU"
6261 "")
6263 (define_insn "*divdf3_fpr"
6264 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6265 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6266 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6267 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6268 && !VECTOR_UNIT_VSX_P (DFmode)"
6269 "{fd|fdiv} %0,%1,%2"
6270 [(set_attr "type" "ddiv")])
6272 (define_insn "*fred_fpr"
6273 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6274 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6275 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6276 "fre %0,%1"
6277 [(set_attr "type" "fp")])
6279 (define_insn "*rsqrtdf_internal1"
6280 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6281 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6282 UNSPEC_RSQRT))]
6283 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6284 "frsqrte %0,%1"
6285 [(set_attr "type" "fp")])
6287 ; builtin fma support
6288 (define_insn "*fmadf4_fpr"
6289 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6290 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6291 (match_operand:DF 2 "gpc_reg_operand" "f")
6292 (match_operand:DF 3 "gpc_reg_operand" "f")))]
6293 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6294 && VECTOR_UNIT_NONE_P (DFmode)"
6295 "{fma|fmadd} %0,%1,%2,%3"
6296 [(set_attr "type" "fp")
6297 (set_attr "fp_type" "fp_maddsub_d")])
6299 (define_insn "*fmsdf4_fpr"
6300 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6301 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6302 (match_operand:DF 2 "gpc_reg_operand" "f")
6303 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6304 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6305 && VECTOR_UNIT_NONE_P (DFmode)"
6306 "{fms|fmsub} %0,%1,%2,%3"
6307 [(set_attr "type" "fp")
6308 (set_attr "fp_type" "fp_maddsub_d")])
6310 (define_insn "*nfmadf4_fpr"
6311 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6312 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6313 (match_operand:DF 2 "gpc_reg_operand" "f")
6314 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6315 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6316 && VECTOR_UNIT_NONE_P (DFmode)"
6317 "{fnma|fnmadd} %0,%1,%2,%3"
6318 [(set_attr "type" "fp")
6319 (set_attr "fp_type" "fp_maddsub_d")])
6321 (define_insn "*nfmsdf4_fpr"
6322 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6323 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6324 (match_operand:DF 2 "gpc_reg_operand" "f")
6325 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
6326 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6327 && VECTOR_UNIT_NONE_P (DFmode)"
6328 "{fnms|fnmsub} %0,%1,%2,%3"
6329 [(set_attr "type" "fp")
6330 (set_attr "fp_type" "fp_maddsub_d")])
6332 (define_expand "sqrtdf2"
6333 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6334 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6335 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6336 && TARGET_DOUBLE_FLOAT"
6337 "")
6339 (define_insn "*sqrtdf2_fpr"
6340 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6341 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6342 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6343 && TARGET_DOUBLE_FLOAT
6344 && !VECTOR_UNIT_VSX_P (DFmode)"
6345 "fsqrt %0,%1"
6346 [(set_attr "type" "dsqrt")])
6348 ;; The conditional move instructions allow us to perform max and min
6349 ;; operations even when
6351 (define_expand "smaxdf3"
6352 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6353 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6354 (match_operand:DF 2 "gpc_reg_operand" ""))
6355 (match_dup 1)
6356 (match_dup 2)))]
6357 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6358 && !flag_trapping_math"
6359 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6361 (define_expand "smindf3"
6362 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6363 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6364 (match_operand:DF 2 "gpc_reg_operand" ""))
6365 (match_dup 2)
6366 (match_dup 1)))]
6367 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6368 && !flag_trapping_math"
6369 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6371 (define_split
6372 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6373 (match_operator:DF 3 "min_max_operator"
6374 [(match_operand:DF 1 "gpc_reg_operand" "")
6375 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6376 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6377 && !flag_trapping_math"
6378 [(const_int 0)]
6379 "
6380 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6381 operands[1], operands[2]);
6382 DONE;
6383 }")
6385 (define_expand "movdfcc"
6386 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6387 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6388 (match_operand:DF 2 "gpc_reg_operand" "")
6389 (match_operand:DF 3 "gpc_reg_operand" "")))]
6390 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6391 "
6392 {
6393 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6394 DONE;
6395 else
6396 FAIL;
6397 }")
6399 (define_insn "*fseldfdf4"
6400 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6401 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6402 (match_operand:DF 4 "zero_fp_constant" "F"))
6403 (match_operand:DF 2 "gpc_reg_operand" "d")
6404 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6405 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6406 "fsel %0,%1,%2,%3"
6407 [(set_attr "type" "fp")])
6409 (define_insn "*fselsfdf4"
6410 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6411 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6412 (match_operand:SF 4 "zero_fp_constant" "F"))
6413 (match_operand:DF 2 "gpc_reg_operand" "d")
6414 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6415 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6416 "fsel %0,%1,%2,%3"
6417 [(set_attr "type" "fp")])
6418 \f
6419 ;; Conversions to and from floating-point.
6421 ; We don't define lfiwax/lfiwzx with the normal definition, because we
6422 ; don't want to support putting SImode in FPR registers.
6423 (define_insn "lfiwax"
6424 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6425 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6426 UNSPEC_LFIWAX))]
6427 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
6428 "lfiwax %0,%y1"
6429 [(set_attr "type" "fpload")])
6431 ; This split must be run before register allocation because it allocates the
6432 ; memory slot that is needed to move values to/from the FPR. We don't allocate
6433 ; it earlier to allow for the combiner to merge insns together where it might
6434 ; not be needed and also in case the insns are deleted as dead code.
6436 (define_insn_and_split "floatsi<mode>2_lfiwax"
6437 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6438 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6439 (clobber (match_scratch:DI 2 "=d"))]
6440 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6441 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
6442 "#"
6443 ""
6444 [(pc)]
6445 "
6446 {
6447 rtx dest = operands[0];
6448 rtx src = operands[1];
6449 rtx tmp;
6451 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6452 tmp = convert_to_mode (DImode, src, false);
6453 else
6454 {
6455 tmp = operands[2];
6456 if (GET_CODE (tmp) == SCRATCH)
6457 tmp = gen_reg_rtx (DImode);
6458 if (MEM_P (src))
6459 {
6460 src = rs6000_address_for_fpconvert (src);
6461 emit_insn (gen_lfiwax (tmp, src));
6462 }
6463 else
6464 {
6465 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6466 emit_move_insn (stack, src);
6467 emit_insn (gen_lfiwax (tmp, stack));
6468 }
6469 }
6470 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6471 DONE;
6472 }"
6473 [(set_attr "length" "12")
6474 (set_attr "type" "fpload")])
6476 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
6477 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6478 (float:SFDF
6479 (sign_extend:DI
6480 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6481 (clobber (match_scratch:DI 2 "=0,d"))]
6482 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6483 && <SI_CONVERT_FP>"
6484 "#"
6485 ""
6486 [(pc)]
6487 "
6488 {
6489 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6490 if (GET_CODE (operands[2]) == SCRATCH)
6491 operands[2] = gen_reg_rtx (DImode);
6492 emit_insn (gen_lfiwax (operands[2], operands[1]));
6493 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6494 DONE;
6495 }"
6496 [(set_attr "length" "8")
6497 (set_attr "type" "fpload")])
6499 (define_insn "lfiwzx"
6500 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6501 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6502 UNSPEC_LFIWZX))]
6503 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
6504 "lfiwzx %0,%y1"
6505 [(set_attr "type" "fpload")])
6507 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
6508 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6509 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6510 (clobber (match_scratch:DI 2 "=d"))]
6511 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6512 && <SI_CONVERT_FP>"
6513 "#"
6514 ""
6515 [(pc)]
6516 "
6517 {
6518 rtx dest = operands[0];
6519 rtx src = operands[1];
6520 rtx tmp;
6522 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6523 tmp = convert_to_mode (DImode, src, true);
6524 else
6525 {
6526 tmp = operands[2];
6527 if (GET_CODE (tmp) == SCRATCH)
6528 tmp = gen_reg_rtx (DImode);
6529 if (MEM_P (src))
6530 {
6531 src = rs6000_address_for_fpconvert (src);
6532 emit_insn (gen_lfiwzx (tmp, src));
6533 }
6534 else
6535 {
6536 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6537 emit_move_insn (stack, src);
6538 emit_insn (gen_lfiwzx (tmp, stack));
6539 }
6540 }
6541 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6542 DONE;
6543 }"
6544 [(set_attr "length" "12")
6545 (set_attr "type" "fpload")])
6547 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
6548 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6549 (unsigned_float:SFDF
6550 (zero_extend:DI
6551 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6552 (clobber (match_scratch:DI 2 "=0,d"))]
6553 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6554 && <SI_CONVERT_FP>"
6555 "#"
6556 ""
6557 [(pc)]
6558 "
6559 {
6560 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6561 if (GET_CODE (operands[2]) == SCRATCH)
6562 operands[2] = gen_reg_rtx (DImode);
6563 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6564 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6565 DONE;
6566 }"
6567 [(set_attr "length" "8")
6568 (set_attr "type" "fpload")])
6570 ; For each of these conversions, there is a define_expand, a define_insn
6571 ; with a '#' template, and a define_split (with C code). The idea is
6572 ; to allow constant folding with the template of the define_insn,
6573 ; then to have the insns split later (between sched1 and final).
6575 (define_expand "floatsidf2"
6576 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6577 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6578 (use (match_dup 2))
6579 (use (match_dup 3))
6580 (clobber (match_dup 4))
6581 (clobber (match_dup 5))
6582 (clobber (match_dup 6))])]
6583 "TARGET_HARD_FLOAT
6584 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6585 "
6586 {
6587 if (TARGET_E500_DOUBLE)
6588 {
6589 if (!REG_P (operands[1]))
6590 operands[1] = force_reg (SImode, operands[1]);
6591 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6592 DONE;
6593 }
6594 else if (TARGET_LFIWAX && TARGET_FCFID)
6595 {
6596 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
6597 DONE;
6598 }
6599 else if (TARGET_FCFID)
6600 {
6601 rtx dreg = operands[1];
6602 if (!REG_P (dreg))
6603 dreg = force_reg (SImode, dreg);
6604 dreg = convert_to_mode (DImode, dreg, false);
6605 emit_insn (gen_floatdidf2 (operands[0], dreg));
6606 DONE;
6607 }
6609 if (!REG_P (operands[1]))
6610 operands[1] = force_reg (SImode, operands[1]);
6611 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6612 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6613 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6614 operands[5] = gen_reg_rtx (DFmode);
6615 operands[6] = gen_reg_rtx (SImode);
6616 }")
6618 (define_insn_and_split "*floatsidf2_internal"
6619 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6620 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6621 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6622 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6623 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6624 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6625 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6626 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6627 "#"
6628 ""
6629 [(pc)]
6630 "
6631 {
6632 rtx lowword, highword;
6633 gcc_assert (MEM_P (operands[4]));
6634 highword = adjust_address (operands[4], SImode, 0);
6635 lowword = adjust_address (operands[4], SImode, 4);
6636 if (! WORDS_BIG_ENDIAN)
6637 {
6638 rtx tmp;
6639 tmp = highword; highword = lowword; lowword = tmp;
6640 }
6642 emit_insn (gen_xorsi3 (operands[6], operands[1],
6643 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6644 emit_move_insn (lowword, operands[6]);
6645 emit_move_insn (highword, operands[2]);
6646 emit_move_insn (operands[5], operands[4]);
6647 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6648 DONE;
6649 }"
6650 [(set_attr "length" "24")
6651 (set_attr "type" "fp")])
6653 ;; If we don't have a direct conversion to single precision, don't enable this
6654 ;; conversion for 32-bit without fast math, because we don't have the insn to
6655 ;; generate the fixup swizzle to avoid double rounding problems.
6656 (define_expand "floatunssisf2"
6657 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6658 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6659 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6660 && (!TARGET_FPRS
6661 || (TARGET_FPRS
6662 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6663 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6664 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6665 "
6666 {
6667 if (!TARGET_FPRS)
6668 {
6669 if (!REG_P (operands[1]))
6670 operands[1] = force_reg (SImode, operands[1]);
6671 }
6672 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6673 {
6674 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
6675 DONE;
6676 }
6677 else
6678 {
6679 rtx dreg = operands[1];
6680 if (!REG_P (dreg))
6681 dreg = force_reg (SImode, dreg);
6682 dreg = convert_to_mode (DImode, dreg, true);
6683 emit_insn (gen_floatdisf2 (operands[0], dreg));
6684 DONE;
6685 }
6686 }")
6688 (define_expand "floatunssidf2"
6689 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6690 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6691 (use (match_dup 2))
6692 (use (match_dup 3))
6693 (clobber (match_dup 4))
6694 (clobber (match_dup 5))])]
6695 "TARGET_HARD_FLOAT
6696 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6697 "
6698 {
6699 if (TARGET_E500_DOUBLE)
6700 {
6701 if (!REG_P (operands[1]))
6702 operands[1] = force_reg (SImode, operands[1]);
6703 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6704 DONE;
6705 }
6706 else if (TARGET_LFIWZX && TARGET_FCFID)
6707 {
6708 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
6709 DONE;
6710 }
6711 else if (TARGET_FCFID)
6712 {
6713 rtx dreg = operands[1];
6714 if (!REG_P (dreg))
6715 dreg = force_reg (SImode, dreg);
6716 dreg = convert_to_mode (DImode, dreg, true);
6717 emit_insn (gen_floatdidf2 (operands[0], dreg));
6718 DONE;
6719 }
6721 if (!REG_P (operands[1]))
6722 operands[1] = force_reg (SImode, operands[1]);
6723 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6724 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6725 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6726 operands[5] = gen_reg_rtx (DFmode);
6727 }")
6729 (define_insn_and_split "*floatunssidf2_internal"
6730 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6731 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6732 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6733 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6734 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6735 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6736 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6737 && !(TARGET_FCFID && TARGET_POWERPC64)"
6738 "#"
6739 ""
6740 [(pc)]
6741 "
6742 {
6743 rtx lowword, highword;
6744 gcc_assert (MEM_P (operands[4]));
6745 highword = adjust_address (operands[4], SImode, 0);
6746 lowword = adjust_address (operands[4], SImode, 4);
6747 if (! WORDS_BIG_ENDIAN)
6748 {
6749 rtx tmp;
6750 tmp = highword; highword = lowword; lowword = tmp;
6751 }
6753 emit_move_insn (lowword, operands[1]);
6754 emit_move_insn (highword, operands[2]);
6755 emit_move_insn (operands[5], operands[4]);
6756 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6757 DONE;
6758 }"
6759 [(set_attr "length" "20")
6760 (set_attr "type" "fp")])
6762 (define_expand "fix_trunc<mode>si2"
6763 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6764 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6765 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
6766 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6767 "
6768 {
6769 if (!<E500_CONVERT>)
6770 {
6771 rtx tmp, stack;
6773 if (TARGET_STFIWX)
6774 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6775 else
6776 {
6777 tmp = gen_reg_rtx (DImode);
6778 stack = rs6000_allocate_stack_temp (DImode, true, false);
6779 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6780 tmp, stack));
6781 }
6782 DONE;
6783 }
6784 }")
6786 ; Like the convert to float patterns, this insn must be split before
6787 ; register allocation so that it can allocate the memory slot if it
6788 ; needed
6789 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6790 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6791 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6792 (clobber (match_scratch:DI 2 "=d"))]
6793 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6794 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6795 && TARGET_STFIWX && can_create_pseudo_p ()"
6796 "#"
6797 ""
6798 [(pc)]
6799 {
6800 rtx dest = operands[0];
6801 rtx src = operands[1];
6802 rtx tmp = operands[2];
6804 if (GET_CODE (tmp) == SCRATCH)
6805 tmp = gen_reg_rtx (DImode);
6807 emit_insn (gen_fctiwz_<mode> (tmp, src));
6808 if (MEM_P (dest))
6809 {
6810 dest = rs6000_address_for_fpconvert (dest);
6811 emit_insn (gen_stfiwx (dest, tmp));
6812 DONE;
6813 }
6814 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6815 {
6816 dest = gen_lowpart (DImode, dest);
6817 emit_move_insn (dest, tmp);
6818 DONE;
6819 }
6820 else
6821 {
6822 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6823 emit_insn (gen_stfiwx (stack, tmp));
6824 emit_move_insn (dest, stack);
6825 DONE;
6826 }
6827 }
6828 [(set_attr "length" "12")
6829 (set_attr "type" "fp")])
6831 (define_insn_and_split "fix_trunc<mode>si2_internal"
6832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6833 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6834 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6835 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6836 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6837 && TARGET_DOUBLE_FLOAT"
6838 "#"
6839 ""
6840 [(pc)]
6841 "
6842 {
6843 rtx lowword;
6844 gcc_assert (MEM_P (operands[3]));
6845 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6847 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6848 emit_move_insn (operands[3], operands[2]);
6849 emit_move_insn (operands[0], lowword);
6850 DONE;
6851 }"
6852 [(set_attr "length" "16")
6853 (set_attr "type" "fp")])
6855 (define_expand "fix_trunc<mode>di2"
6856 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6857 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6858 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6859 && TARGET_FCFID"
6860 "")
6862 (define_insn "*fix_trunc<mode>di2_fctidz"
6863 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6864 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6865 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6866 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6867 "fctidz %0,%1"
6868 [(set_attr "type" "fp")])
6870 (define_expand "fixuns_trunc<mode>si2"
6871 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6872 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6873 "TARGET_HARD_FLOAT
6874 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6875 || <E500_CONVERT>)"
6876 "
6877 {
6878 if (!<E500_CONVERT>)
6879 {
6880 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6881 DONE;
6882 }
6883 }")
6885 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6886 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6887 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6888 (clobber (match_scratch:DI 2 "=d"))]
6889 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6890 && TARGET_STFIWX && can_create_pseudo_p ()"
6891 "#"
6892 ""
6893 [(pc)]
6894 {
6895 rtx dest = operands[0];
6896 rtx src = operands[1];
6897 rtx tmp = operands[2];
6899 if (GET_CODE (tmp) == SCRATCH)
6900 tmp = gen_reg_rtx (DImode);
6902 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6903 if (MEM_P (dest))
6904 {
6905 dest = rs6000_address_for_fpconvert (dest);
6906 emit_insn (gen_stfiwx (dest, tmp));
6907 DONE;
6908 }
6909 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6910 {
6911 dest = gen_lowpart (DImode, dest);
6912 emit_move_insn (dest, tmp);
6913 DONE;
6914 }
6915 else
6916 {
6917 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6918 emit_insn (gen_stfiwx (stack, tmp));
6919 emit_move_insn (dest, stack);
6920 DONE;
6921 }
6922 }
6923 [(set_attr "length" "12")
6924 (set_attr "type" "fp")])
6926 (define_expand "fixuns_trunc<mode>di2"
6927 [(set (match_operand:DI 0 "register_operand" "")
6928 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6929 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6930 "")
6932 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6933 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6934 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6935 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6936 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6937 "fctiduz %0,%1"
6938 [(set_attr "type" "fp")])
6940 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6941 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6942 ; because the first makes it clear that operand 0 is not live
6943 ; before the instruction.
6944 (define_insn "fctiwz_<mode>"
6945 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6946 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6947 UNSPEC_FCTIWZ))]
6948 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6949 && TARGET_DOUBLE_FLOAT"
6950 "{fcirz|fctiwz} %0,%1"
6951 [(set_attr "type" "fp")])
6953 (define_insn "fctiwuz_<mode>"
6954 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6955 (unspec:DI [(unsigned_fix:SI
6956 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6957 UNSPEC_FCTIWUZ))]
6958 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6959 "fctiwuz %0,%1"
6960 [(set_attr "type" "fp")])
6962 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6963 ;; since the friz instruction does not truncate the value if the floating
6964 ;; point value is < LONG_MIN or > LONG_MAX.
6965 (define_insn "*friz"
6966 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6967 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6968 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6969 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6970 && !flag_trapping_math && TARGET_FRIZ"
6971 "friz %0,%1"
6972 [(set_attr "type" "fp")])
6974 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6975 ;; load to properly sign extend the value, but at least doing a store, load
6976 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6977 ;; if we have 32-bit memory ops
6978 (define_insn_and_split "*round32<mode>2_fprs"
6979 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6980 (float:SFDF
6981 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6982 (clobber (match_scratch:DI 2 "=d"))
6983 (clobber (match_scratch:DI 3 "=d"))]
6984 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6985 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6986 && can_create_pseudo_p ()"
6987 "#"
6988 ""
6989 [(pc)]
6990 {
6991 rtx dest = operands[0];
6992 rtx src = operands[1];
6993 rtx tmp1 = operands[2];
6994 rtx tmp2 = operands[3];
6995 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6997 if (GET_CODE (tmp1) == SCRATCH)
6998 tmp1 = gen_reg_rtx (DImode);
6999 if (GET_CODE (tmp2) == SCRATCH)
7000 tmp2 = gen_reg_rtx (DImode);
7002 emit_insn (gen_fctiwz_<mode> (tmp1, src));
7003 emit_insn (gen_stfiwx (stack, tmp1));
7004 emit_insn (gen_lfiwax (tmp2, stack));
7005 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7006 DONE;
7007 }
7008 [(set_attr "type" "fpload")
7009 (set_attr "length" "16")])
7011 (define_insn_and_split "*roundu32<mode>2_fprs"
7012 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
7013 (unsigned_float:SFDF
7014 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
7015 (clobber (match_scratch:DI 2 "=d"))
7016 (clobber (match_scratch:DI 3 "=d"))]
7017 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7018 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
7019 && can_create_pseudo_p ()"
7020 "#"
7021 ""
7022 [(pc)]
7023 {
7024 rtx dest = operands[0];
7025 rtx src = operands[1];
7026 rtx tmp1 = operands[2];
7027 rtx tmp2 = operands[3];
7028 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
7030 if (GET_CODE (tmp1) == SCRATCH)
7031 tmp1 = gen_reg_rtx (DImode);
7032 if (GET_CODE (tmp2) == SCRATCH)
7033 tmp2 = gen_reg_rtx (DImode);
7035 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
7036 emit_insn (gen_stfiwx (stack, tmp1));
7037 emit_insn (gen_lfiwzx (tmp2, stack));
7038 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7039 DONE;
7040 }
7041 [(set_attr "type" "fpload")
7042 (set_attr "length" "16")])
7044 ;; No VSX equivalent to fctid
7045 (define_insn "lrint<mode>di2"
7046 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7047 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7048 UNSPEC_FCTID))]
7049 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7050 "fctid %0,%1"
7051 [(set_attr "type" "fp")])
7053 (define_expand "btrunc<mode>2"
7054 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7055 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7056 UNSPEC_FRIZ))]
7057 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7058 "")
7060 (define_insn "*btrunc<mode>2_fpr"
7061 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7062 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7063 UNSPEC_FRIZ))]
7064 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7065 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7066 "friz %0,%1"
7067 [(set_attr "type" "fp")])
7069 (define_expand "ceil<mode>2"
7070 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7071 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7072 UNSPEC_FRIP))]
7073 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7074 "")
7076 (define_insn "*ceil<mode>2_fpr"
7077 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7078 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7079 UNSPEC_FRIP))]
7080 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7081 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7082 "frip %0,%1"
7083 [(set_attr "type" "fp")])
7085 (define_expand "floor<mode>2"
7086 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7087 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7088 UNSPEC_FRIM))]
7089 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7090 "")
7092 (define_insn "*floor<mode>2_fpr"
7093 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7094 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7095 UNSPEC_FRIM))]
7096 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7097 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7098 "frim %0,%1"
7099 [(set_attr "type" "fp")])
7101 ;; No VSX equivalent to frin
7102 (define_insn "round<mode>2"
7103 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7104 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7105 UNSPEC_FRIN))]
7106 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7107 "frin %0,%1"
7108 [(set_attr "type" "fp")])
7110 ; An UNSPEC is used so we don't have to support SImode in FP registers.
7111 (define_insn "stfiwx"
7112 [(set (match_operand:SI 0 "memory_operand" "=Z")
7113 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
7114 UNSPEC_STFIWX))]
7115 "TARGET_PPC_GFXOPT"
7116 "stfiwx %1,%y0"
7117 [(set_attr "type" "fpstore")])
7119 ;; If we don't have a direct conversion to single precision, don't enable this
7120 ;; conversion for 32-bit without fast math, because we don't have the insn to
7121 ;; generate the fixup swizzle to avoid double rounding problems.
7122 (define_expand "floatsisf2"
7123 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7124 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
7125 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
7126 && (!TARGET_FPRS
7127 || (TARGET_FPRS
7128 && ((TARGET_FCFIDS && TARGET_LFIWAX)
7129 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
7130 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
7131 "
7132 {
7133 if (!TARGET_FPRS)
7134 {
7135 if (!REG_P (operands[1]))
7136 operands[1] = force_reg (SImode, operands[1]);
7137 }
7138 else if (TARGET_FCFIDS && TARGET_LFIWAX)
7139 {
7140 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
7141 DONE;
7142 }
7143 else if (TARGET_FCFID && TARGET_LFIWAX)
7144 {
7145 rtx dfreg = gen_reg_rtx (DFmode);
7146 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
7147 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
7148 DONE;
7149 }
7150 else
7151 {
7152 rtx dreg = operands[1];
7153 if (!REG_P (dreg))
7154 dreg = force_reg (SImode, dreg);
7155 dreg = convert_to_mode (DImode, dreg, false);
7156 emit_insn (gen_floatdisf2 (operands[0], dreg));
7157 DONE;
7158 }
7159 }")
7161 (define_expand "floatdidf2"
7162 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7163 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
7164 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
7165 "")
7167 (define_insn "*floatdidf2_fpr"
7168 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7169 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7170 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
7171 && !VECTOR_UNIT_VSX_P (DFmode)"
7172 "fcfid %0,%1"
7173 [(set_attr "type" "fp")])
7175 ; Allow the combiner to merge source memory operands to the conversion so that
7176 ; the optimizer/register allocator doesn't try to load the value too early in a
7177 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
7178 ; hit. We will split after reload to avoid the trip through the GPRs
7180 (define_insn_and_split "*floatdidf2_mem"
7181 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7182 (float:DF (match_operand:DI 1 "memory_operand" "m")))
7183 (clobber (match_scratch:DI 2 "=d"))]
7184 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
7185 "#"
7186 "&& reload_completed"
7187 [(set (match_dup 2) (match_dup 1))
7188 (set (match_dup 0) (float:DF (match_dup 2)))]
7189 ""
7190 [(set_attr "length" "8")
7191 (set_attr "type" "fpload")])
7193 (define_expand "floatunsdidf2"
7194 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7195 (unsigned_float:DF
7196 (match_operand:DI 1 "gpc_reg_operand" "")))]
7197 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7198 "")
7200 (define_insn "*floatunsdidf2_fcfidu"
7201 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7202 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7203 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
7204 "fcfidu %0,%1"
7205 [(set_attr "type" "fp")
7206 (set_attr "length" "4")])
7208 (define_insn_and_split "*floatunsdidf2_mem"
7209 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7210 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
7211 (clobber (match_scratch:DI 2 "=d"))]
7212 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7213 "#"
7214 "&& reload_completed"
7215 [(set (match_dup 2) (match_dup 1))
7216 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
7217 ""
7218 [(set_attr "length" "8")
7219 (set_attr "type" "fpload")])
7221 (define_expand "floatdisf2"
7222 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7223 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7224 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7225 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
7226 "
7227 {
7228 if (!TARGET_FCFIDS)
7229 {
7230 rtx val = operands[1];
7231 if (!flag_unsafe_math_optimizations)
7232 {
7233 rtx label = gen_label_rtx ();
7234 val = gen_reg_rtx (DImode);
7235 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
7236 emit_label (label);
7237 }
7238 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
7239 DONE;
7240 }
7241 }")
7243 (define_insn "floatdisf2_fcfids"
7244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7245 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7246 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7247 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7248 "fcfids %0,%1"
7249 [(set_attr "type" "fp")])
7251 (define_insn_and_split "*floatdisf2_mem"
7252 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7253 (float:SF (match_operand:DI 1 "memory_operand" "m")))
7254 (clobber (match_scratch:DI 2 "=f"))]
7255 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7256 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7257 "#"
7258 "&& reload_completed"
7259 [(pc)]
7260 "
7261 {
7262 emit_move_insn (operands[2], operands[1]);
7263 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
7264 DONE;
7265 }"
7266 [(set_attr "length" "8")])
7268 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7269 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7270 ;; from double rounding.
7271 ;; Instead of creating a new cpu type for two FP operations, just use fp
7272 (define_insn_and_split "floatdisf2_internal1"
7273 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7274 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
7275 (clobber (match_scratch:DF 2 "=d"))]
7276 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7277 "#"
7278 "&& reload_completed"
7279 [(set (match_dup 2)
7280 (float:DF (match_dup 1)))
7281 (set (match_dup 0)
7282 (float_truncate:SF (match_dup 2)))]
7283 ""
7284 [(set_attr "length" "8")
7285 (set_attr "type" "fp")])
7287 ;; Twiddles bits to avoid double rounding.
7288 ;; Bits that might be truncated when converting to DFmode are replaced
7289 ;; by a bit that won't be lost at that stage, but is below the SFmode
7290 ;; rounding position.
7291 (define_expand "floatdisf2_internal2"
7292 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
7293 (const_int 53)))
7294 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
7295 (const_int 2047)))
7296 (clobber (scratch:CC))])
7297 (set (match_dup 3) (plus:DI (match_dup 3)
7298 (const_int 1)))
7299 (set (match_dup 0) (plus:DI (match_dup 0)
7300 (const_int 2047)))
7301 (set (match_dup 4) (compare:CCUNS (match_dup 3)
7302 (const_int 2)))
7303 (set (match_dup 0) (ior:DI (match_dup 0)
7304 (match_dup 1)))
7305 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
7306 (const_int -2048)))
7307 (clobber (scratch:CC))])
7308 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
7309 (label_ref (match_operand:DI 2 "" ""))
7310 (pc)))
7311 (set (match_dup 0) (match_dup 1))]
7312 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7313 "
7314 {
7315 operands[3] = gen_reg_rtx (DImode);
7316 operands[4] = gen_reg_rtx (CCUNSmode);
7317 }")
7319 (define_expand "floatunsdisf2"
7320 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7321 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7322 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7323 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7324 "")
7326 (define_insn "floatunsdisf2_fcfidus"
7327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7328 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7329 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7330 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7331 "fcfidus %0,%1"
7332 [(set_attr "type" "fp")])
7334 (define_insn_and_split "*floatunsdisf2_mem"
7335 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7336 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
7337 (clobber (match_scratch:DI 2 "=f"))]
7338 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7339 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7340 "#"
7341 "&& reload_completed"
7342 [(pc)]
7343 "
7344 {
7345 emit_move_insn (operands[2], operands[1]);
7346 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
7347 DONE;
7348 }"
7349 [(set_attr "length" "8")
7350 (set_attr "type" "fpload")])
7351 \f
7352 ;; Define the DImode operations that can be done in a small number
7353 ;; of instructions. The & constraints are to prevent the register
7354 ;; allocator from allocating registers that overlap with the inputs
7355 ;; (for example, having an input in 7,8 and an output in 6,7). We
7356 ;; also allow for the output being the same as one of the inputs.
7358 (define_insn "*adddi3_noppc64"
7359 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
7360 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
7361 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
7362 "! TARGET_POWERPC64"
7363 "*
7364 {
7365 if (WORDS_BIG_ENDIAN)
7366 return (GET_CODE (operands[2])) != CONST_INT
7367 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
7368 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
7369 else
7370 return (GET_CODE (operands[2])) != CONST_INT
7371 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
7372 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
7373 }"
7374 [(set_attr "type" "two")
7375 (set_attr "length" "8")])
7377 (define_insn "*subdi3_noppc64"
7378 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
7379 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
7380 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
7381 "! TARGET_POWERPC64"
7382 "*
7383 {
7384 if (WORDS_BIG_ENDIAN)
7385 return (GET_CODE (operands[1]) != CONST_INT)
7386 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
7387 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
7388 else
7389 return (GET_CODE (operands[1]) != CONST_INT)
7390 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
7391 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
7392 }"
7393 [(set_attr "type" "two")
7394 (set_attr "length" "8")])
7396 (define_insn "*negdi2_noppc64"
7397 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7398 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
7399 "! TARGET_POWERPC64"
7400 "*
7401 {
7402 return (WORDS_BIG_ENDIAN)
7403 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
7404 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
7405 }"
7406 [(set_attr "type" "two")
7407 (set_attr "length" "8")])
7409 (define_expand "mulsidi3"
7410 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7411 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7412 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7413 "! TARGET_POWERPC64"
7414 "
7415 {
7416 if (! TARGET_POWER && ! TARGET_POWERPC)
7417 {
7418 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7419 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7420 emit_insn (gen_mull_call ());
7421 if (WORDS_BIG_ENDIAN)
7422 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
7423 else
7424 {
7425 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
7426 gen_rtx_REG (SImode, 3));
7427 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
7428 gen_rtx_REG (SImode, 4));
7429 }
7430 DONE;
7431 }
7432 else if (TARGET_POWER)
7433 {
7434 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
7435 DONE;
7436 }
7437 }")
7439 (define_insn "mulsidi3_mq"
7440 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7441 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7442 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7443 (clobber (match_scratch:SI 3 "=q"))]
7444 "TARGET_POWER"
7445 "mul %0,%1,%2\;mfmq %L0"
7446 [(set_attr "type" "imul")
7447 (set_attr "length" "8")])
7449 (define_insn "*mulsidi3_no_mq"
7450 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7451 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7452 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7453 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7454 "*
7455 {
7456 return (WORDS_BIG_ENDIAN)
7457 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7458 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7459 }"
7460 [(set_attr "type" "imul")
7461 (set_attr "length" "8")])
7463 (define_split
7464 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7465 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7466 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7467 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7468 [(set (match_dup 3)
7469 (truncate:SI
7470 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7471 (sign_extend:DI (match_dup 2)))
7472 (const_int 32))))
7473 (set (match_dup 4)
7474 (mult:SI (match_dup 1)
7475 (match_dup 2)))]
7476 "
7477 {
7478 int endian = (WORDS_BIG_ENDIAN == 0);
7479 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7480 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7481 }")
7483 (define_expand "umulsidi3"
7484 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7485 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7486 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7487 "TARGET_POWERPC && ! TARGET_POWERPC64"
7488 "
7489 {
7490 if (TARGET_POWER)
7491 {
7492 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7493 DONE;
7494 }
7495 }")
7497 (define_insn "umulsidi3_mq"
7498 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7499 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7500 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7501 (clobber (match_scratch:SI 3 "=q"))]
7502 "TARGET_POWERPC && TARGET_POWER"
7503 "*
7504 {
7505 return (WORDS_BIG_ENDIAN)
7506 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7507 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7508 }"
7509 [(set_attr "type" "imul")
7510 (set_attr "length" "8")])
7512 (define_insn "*umulsidi3_no_mq"
7513 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7514 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7515 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7516 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7517 "*
7518 {
7519 return (WORDS_BIG_ENDIAN)
7520 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7521 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7522 }"
7523 [(set_attr "type" "imul")
7524 (set_attr "length" "8")])
7526 (define_split
7527 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7528 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7529 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7530 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7531 [(set (match_dup 3)
7532 (truncate:SI
7533 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7534 (zero_extend:DI (match_dup 2)))
7535 (const_int 32))))
7536 (set (match_dup 4)
7537 (mult:SI (match_dup 1)
7538 (match_dup 2)))]
7539 "
7540 {
7541 int endian = (WORDS_BIG_ENDIAN == 0);
7542 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7543 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7544 }")
7546 (define_expand "smulsi3_highpart"
7547 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7548 (truncate:SI
7549 (lshiftrt:DI (mult:DI (sign_extend:DI
7550 (match_operand:SI 1 "gpc_reg_operand" ""))
7551 (sign_extend:DI
7552 (match_operand:SI 2 "gpc_reg_operand" "")))
7553 (const_int 32))))]
7554 ""
7555 "
7556 {
7557 if (! TARGET_POWER && ! TARGET_POWERPC)
7558 {
7559 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7560 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7561 emit_insn (gen_mulh_call ());
7562 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7563 DONE;
7564 }
7565 else if (TARGET_POWER)
7566 {
7567 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7568 DONE;
7569 }
7570 }")
7572 (define_insn "smulsi3_highpart_mq"
7573 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7574 (truncate:SI
7575 (lshiftrt:DI (mult:DI (sign_extend:DI
7576 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7577 (sign_extend:DI
7578 (match_operand:SI 2 "gpc_reg_operand" "r")))
7579 (const_int 32))))
7580 (clobber (match_scratch:SI 3 "=q"))]
7581 "TARGET_POWER"
7582 "mul %0,%1,%2"
7583 [(set_attr "type" "imul")])
7585 (define_insn "*smulsi3_highpart_no_mq"
7586 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7587 (truncate:SI
7588 (lshiftrt:DI (mult:DI (sign_extend:DI
7589 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7590 (sign_extend:DI
7591 (match_operand:SI 2 "gpc_reg_operand" "r")))
7592 (const_int 32))))]
7593 "TARGET_POWERPC && ! TARGET_POWER"
7594 "mulhw %0,%1,%2"
7595 [(set_attr "type" "imul")])
7597 (define_expand "umulsi3_highpart"
7598 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7599 (truncate:SI
7600 (lshiftrt:DI (mult:DI (zero_extend:DI
7601 (match_operand:SI 1 "gpc_reg_operand" ""))
7602 (zero_extend:DI
7603 (match_operand:SI 2 "gpc_reg_operand" "")))
7604 (const_int 32))))]
7605 "TARGET_POWERPC"
7606 "
7607 {
7608 if (TARGET_POWER)
7609 {
7610 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7611 DONE;
7612 }
7613 }")
7615 (define_insn "umulsi3_highpart_mq"
7616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7617 (truncate:SI
7618 (lshiftrt:DI (mult:DI (zero_extend:DI
7619 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7620 (zero_extend:DI
7621 (match_operand:SI 2 "gpc_reg_operand" "r")))
7622 (const_int 32))))
7623 (clobber (match_scratch:SI 3 "=q"))]
7624 "TARGET_POWERPC && TARGET_POWER"
7625 "mulhwu %0,%1,%2"
7626 [(set_attr "type" "imul")])
7628 (define_insn "*umulsi3_highpart_no_mq"
7629 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7630 (truncate:SI
7631 (lshiftrt:DI (mult:DI (zero_extend:DI
7632 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7633 (zero_extend:DI
7634 (match_operand:SI 2 "gpc_reg_operand" "r")))
7635 (const_int 32))))]
7636 "TARGET_POWERPC && ! TARGET_POWER"
7637 "mulhwu %0,%1,%2"
7638 [(set_attr "type" "imul")])
7640 ;; If operands 0 and 2 are in the same register, we have a problem. But
7641 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7642 ;; why we have the strange constraints below.
7643 (define_insn "ashldi3_power"
7644 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7645 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7646 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7647 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7648 "TARGET_POWER"
7649 "@
7650 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7651 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7652 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7653 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7654 [(set_attr "length" "8")])
7656 (define_insn "lshrdi3_power"
7657 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7658 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7659 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7660 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7661 "TARGET_POWER"
7662 "@
7663 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7664 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7665 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7666 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7667 [(set_attr "length" "8")])
7669 ;; Shift by a variable amount is too complex to be worth open-coding. We
7670 ;; just handle shifts by constants.
7671 (define_insn "ashrdi3_power"
7672 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7673 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7674 (match_operand:SI 2 "const_int_operand" "M,i")))
7675 (clobber (match_scratch:SI 3 "=X,q"))]
7676 "TARGET_POWER"
7677 "@
7678 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7679 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7680 [(set_attr "type" "shift")
7681 (set_attr "length" "8")])
7683 (define_insn "ashrdi3_no_power"
7684 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7685 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7686 (match_operand:SI 2 "const_int_operand" "M,i")))]
7687 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7688 "@
7689 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7690 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7691 [(set_attr "type" "two,three")
7692 (set_attr "length" "8,12")])
7694 (define_insn "*ashrdisi3_noppc64"
7695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7696 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7697 (const_int 32)) 4))]
7698 "TARGET_32BIT && !TARGET_POWERPC64"
7699 "*
7700 {
7701 if (REGNO (operands[0]) == REGNO (operands[1]))
7702 return \"\";
7703 else
7704 return \"mr %0,%1\";
7705 }"
7706 [(set_attr "length" "4")])
7708 \f
7709 ;; PowerPC64 DImode operations.
7711 (define_expand "absdi2"
7712 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7713 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7714 "TARGET_POWERPC64"
7715 "
7716 {
7717 if (TARGET_ISEL)
7718 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7719 else
7720 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7721 DONE;
7722 }")
7724 (define_insn_and_split "absdi2_internal"
7725 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7726 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7727 (clobber (match_scratch:DI 2 "=&r,&r"))]
7728 "TARGET_POWERPC64 && !TARGET_ISEL"
7729 "#"
7730 "&& reload_completed"
7731 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7732 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7733 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7734 "")
7736 (define_insn_and_split "*nabsdi2"
7737 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7738 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7739 (clobber (match_scratch:DI 2 "=&r,&r"))]
7740 "TARGET_POWERPC64 && !TARGET_ISEL"
7741 "#"
7742 "&& reload_completed"
7743 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7744 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7745 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7746 "")
7748 (define_insn "muldi3"
7749 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7750 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7751 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7752 "TARGET_POWERPC64"
7753 "@
7754 mulld %0,%1,%2
7755 mulli %0,%1,%2"
7756 [(set (attr "type")
7757 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7758 (const_string "imul3")
7759 (match_operand:SI 2 "short_cint_operand" "")
7760 (const_string "imul2")]
7761 (const_string "lmul")))])
7763 (define_insn "*muldi3_internal1"
7764 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7765 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7766 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7767 (const_int 0)))
7768 (clobber (match_scratch:DI 3 "=r,r"))]
7769 "TARGET_POWERPC64"
7770 "@
7771 mulld. %3,%1,%2
7772 #"
7773 [(set_attr "type" "lmul_compare")
7774 (set_attr "length" "4,8")])
7776 (define_split
7777 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7778 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7779 (match_operand:DI 2 "gpc_reg_operand" ""))
7780 (const_int 0)))
7781 (clobber (match_scratch:DI 3 ""))]
7782 "TARGET_POWERPC64 && reload_completed"
7783 [(set (match_dup 3)
7784 (mult:DI (match_dup 1) (match_dup 2)))
7785 (set (match_dup 0)
7786 (compare:CC (match_dup 3)
7787 (const_int 0)))]
7788 "")
7790 (define_insn "*muldi3_internal2"
7791 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7792 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7793 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7794 (const_int 0)))
7795 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7796 (mult:DI (match_dup 1) (match_dup 2)))]
7797 "TARGET_POWERPC64"
7798 "@
7799 mulld. %0,%1,%2
7800 #"
7801 [(set_attr "type" "lmul_compare")
7802 (set_attr "length" "4,8")])
7804 (define_split
7805 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7806 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7807 (match_operand:DI 2 "gpc_reg_operand" ""))
7808 (const_int 0)))
7809 (set (match_operand:DI 0 "gpc_reg_operand" "")
7810 (mult:DI (match_dup 1) (match_dup 2)))]
7811 "TARGET_POWERPC64 && reload_completed"
7812 [(set (match_dup 0)
7813 (mult:DI (match_dup 1) (match_dup 2)))
7814 (set (match_dup 3)
7815 (compare:CC (match_dup 0)
7816 (const_int 0)))]
7817 "")
7819 (define_insn "smuldi3_highpart"
7820 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7821 (truncate:DI
7822 (lshiftrt:TI (mult:TI (sign_extend:TI
7823 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7824 (sign_extend:TI
7825 (match_operand:DI 2 "gpc_reg_operand" "r")))
7826 (const_int 64))))]
7827 "TARGET_POWERPC64"
7828 "mulhd %0,%1,%2"
7829 [(set_attr "type" "lmul")])
7831 (define_insn "umuldi3_highpart"
7832 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7833 (truncate:DI
7834 (lshiftrt:TI (mult:TI (zero_extend:TI
7835 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7836 (zero_extend:TI
7837 (match_operand:DI 2 "gpc_reg_operand" "r")))
7838 (const_int 64))))]
7839 "TARGET_POWERPC64"
7840 "mulhdu %0,%1,%2"
7841 [(set_attr "type" "lmul")])
7843 (define_insn "rotldi3"
7844 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7845 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7846 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7847 "TARGET_POWERPC64"
7848 "@
7849 rldcl %0,%1,%2,0
7850 rldicl %0,%1,%H2,0"
7851 [(set_attr "type" "var_shift_rotate,integer")])
7853 (define_insn "*rotldi3_internal2"
7854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7855 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7856 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7857 (const_int 0)))
7858 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7859 "TARGET_64BIT"
7860 "@
7861 rldcl. %3,%1,%2,0
7862 rldicl. %3,%1,%H2,0
7863 #
7864 #"
7865 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7866 (set_attr "length" "4,4,8,8")])
7868 (define_split
7869 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7870 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7871 (match_operand:DI 2 "reg_or_cint_operand" ""))
7872 (const_int 0)))
7873 (clobber (match_scratch:DI 3 ""))]
7874 "TARGET_POWERPC64 && reload_completed"
7875 [(set (match_dup 3)
7876 (rotate:DI (match_dup 1) (match_dup 2)))
7877 (set (match_dup 0)
7878 (compare:CC (match_dup 3)
7879 (const_int 0)))]
7880 "")
7882 (define_insn "*rotldi3_internal3"
7883 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7884 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7885 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7886 (const_int 0)))
7887 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7888 (rotate:DI (match_dup 1) (match_dup 2)))]
7889 "TARGET_64BIT"
7890 "@
7891 rldcl. %0,%1,%2,0
7892 rldicl. %0,%1,%H2,0
7893 #
7894 #"
7895 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7896 (set_attr "length" "4,4,8,8")])
7898 (define_split
7899 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7900 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7901 (match_operand:DI 2 "reg_or_cint_operand" ""))
7902 (const_int 0)))
7903 (set (match_operand:DI 0 "gpc_reg_operand" "")
7904 (rotate:DI (match_dup 1) (match_dup 2)))]
7905 "TARGET_POWERPC64 && reload_completed"
7906 [(set (match_dup 0)
7907 (rotate:DI (match_dup 1) (match_dup 2)))
7908 (set (match_dup 3)
7909 (compare:CC (match_dup 0)
7910 (const_int 0)))]
7911 "")
7913 (define_insn "*rotldi3_internal4"
7914 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7915 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7916 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7917 (match_operand:DI 3 "mask64_operand" "n,n")))]
7918 "TARGET_POWERPC64"
7919 "@
7920 rldc%B3 %0,%1,%2,%S3
7921 rldic%B3 %0,%1,%H2,%S3"
7922 [(set_attr "type" "var_shift_rotate,integer")])
7924 (define_insn "*rotldi3_internal5"
7925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7926 (compare:CC (and:DI
7927 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7928 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7929 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7930 (const_int 0)))
7931 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7932 "TARGET_64BIT"
7933 "@
7934 rldc%B3. %4,%1,%2,%S3
7935 rldic%B3. %4,%1,%H2,%S3
7936 #
7937 #"
7938 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7939 (set_attr "length" "4,4,8,8")])
7941 (define_split
7942 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7943 (compare:CC (and:DI
7944 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7945 (match_operand:DI 2 "reg_or_cint_operand" ""))
7946 (match_operand:DI 3 "mask64_operand" ""))
7947 (const_int 0)))
7948 (clobber (match_scratch:DI 4 ""))]
7949 "TARGET_POWERPC64 && reload_completed"
7950 [(set (match_dup 4)
7951 (and:DI (rotate:DI (match_dup 1)
7952 (match_dup 2))
7953 (match_dup 3)))
7954 (set (match_dup 0)
7955 (compare:CC (match_dup 4)
7956 (const_int 0)))]
7957 "")
7959 (define_insn "*rotldi3_internal6"
7960 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7961 (compare:CC (and:DI
7962 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7963 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7964 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7965 (const_int 0)))
7966 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7967 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7968 "TARGET_64BIT"
7969 "@
7970 rldc%B3. %0,%1,%2,%S3
7971 rldic%B3. %0,%1,%H2,%S3
7972 #
7973 #"
7974 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7975 (set_attr "length" "4,4,8,8")])
7977 (define_split
7978 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7979 (compare:CC (and:DI
7980 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7981 (match_operand:DI 2 "reg_or_cint_operand" ""))
7982 (match_operand:DI 3 "mask64_operand" ""))
7983 (const_int 0)))
7984 (set (match_operand:DI 0 "gpc_reg_operand" "")
7985 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7986 "TARGET_POWERPC64 && reload_completed"
7987 [(set (match_dup 0)
7988 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7989 (set (match_dup 4)
7990 (compare:CC (match_dup 0)
7991 (const_int 0)))]
7992 "")
7994 (define_insn "*rotldi3_internal7"
7995 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7996 (zero_extend:DI
7997 (subreg:QI
7998 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7999 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8000 "TARGET_POWERPC64"
8001 "@
8002 rldcl %0,%1,%2,56
8003 rldicl %0,%1,%H2,56"
8004 [(set_attr "type" "var_shift_rotate,integer")])
8006 (define_insn "*rotldi3_internal8"
8007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8008 (compare:CC (zero_extend:DI
8009 (subreg:QI
8010 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8011 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8012 (const_int 0)))
8013 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8014 "TARGET_64BIT"
8015 "@
8016 rldcl. %3,%1,%2,56
8017 rldicl. %3,%1,%H2,56
8018 #
8019 #"
8020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8021 (set_attr "length" "4,4,8,8")])
8023 (define_split
8024 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8025 (compare:CC (zero_extend:DI
8026 (subreg:QI
8027 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8028 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8029 (const_int 0)))
8030 (clobber (match_scratch:DI 3 ""))]
8031 "TARGET_POWERPC64 && reload_completed"
8032 [(set (match_dup 3)
8033 (zero_extend:DI (subreg:QI
8034 (rotate:DI (match_dup 1)
8035 (match_dup 2)) 0)))
8036 (set (match_dup 0)
8037 (compare:CC (match_dup 3)
8038 (const_int 0)))]
8039 "")
8041 (define_insn "*rotldi3_internal9"
8042 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8043 (compare:CC (zero_extend:DI
8044 (subreg:QI
8045 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8046 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8047 (const_int 0)))
8048 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8049 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8050 "TARGET_64BIT"
8051 "@
8052 rldcl. %0,%1,%2,56
8053 rldicl. %0,%1,%H2,56
8054 #
8055 #"
8056 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8057 (set_attr "length" "4,4,8,8")])
8059 (define_split
8060 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8061 (compare:CC (zero_extend:DI
8062 (subreg:QI
8063 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8064 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8065 (const_int 0)))
8066 (set (match_operand:DI 0 "gpc_reg_operand" "")
8067 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8068 "TARGET_POWERPC64 && reload_completed"
8069 [(set (match_dup 0)
8070 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8071 (set (match_dup 3)
8072 (compare:CC (match_dup 0)
8073 (const_int 0)))]
8074 "")
8076 (define_insn "*rotldi3_internal10"
8077 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8078 (zero_extend:DI
8079 (subreg:HI
8080 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8081 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8082 "TARGET_POWERPC64"
8083 "@
8084 rldcl %0,%1,%2,48
8085 rldicl %0,%1,%H2,48"
8086 [(set_attr "type" "var_shift_rotate,integer")])
8088 (define_insn "*rotldi3_internal11"
8089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8090 (compare:CC (zero_extend:DI
8091 (subreg:HI
8092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8093 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8094 (const_int 0)))
8095 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8096 "TARGET_64BIT"
8097 "@
8098 rldcl. %3,%1,%2,48
8099 rldicl. %3,%1,%H2,48
8100 #
8101 #"
8102 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8103 (set_attr "length" "4,4,8,8")])
8105 (define_split
8106 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8107 (compare:CC (zero_extend:DI
8108 (subreg:HI
8109 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8110 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8111 (const_int 0)))
8112 (clobber (match_scratch:DI 3 ""))]
8113 "TARGET_POWERPC64 && reload_completed"
8114 [(set (match_dup 3)
8115 (zero_extend:DI (subreg:HI
8116 (rotate:DI (match_dup 1)
8117 (match_dup 2)) 0)))
8118 (set (match_dup 0)
8119 (compare:CC (match_dup 3)
8120 (const_int 0)))]
8121 "")
8123 (define_insn "*rotldi3_internal12"
8124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8125 (compare:CC (zero_extend:DI
8126 (subreg:HI
8127 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8128 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8129 (const_int 0)))
8130 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8131 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8132 "TARGET_64BIT"
8133 "@
8134 rldcl. %0,%1,%2,48
8135 rldicl. %0,%1,%H2,48
8136 #
8137 #"
8138 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8139 (set_attr "length" "4,4,8,8")])
8141 (define_split
8142 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8143 (compare:CC (zero_extend:DI
8144 (subreg:HI
8145 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8146 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8147 (const_int 0)))
8148 (set (match_operand:DI 0 "gpc_reg_operand" "")
8149 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8150 "TARGET_POWERPC64 && reload_completed"
8151 [(set (match_dup 0)
8152 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8153 (set (match_dup 3)
8154 (compare:CC (match_dup 0)
8155 (const_int 0)))]
8156 "")
8158 (define_insn "*rotldi3_internal13"
8159 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8160 (zero_extend:DI
8161 (subreg:SI
8162 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8163 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8164 "TARGET_POWERPC64"
8165 "@
8166 rldcl %0,%1,%2,32
8167 rldicl %0,%1,%H2,32"
8168 [(set_attr "type" "var_shift_rotate,integer")])
8170 (define_insn "*rotldi3_internal14"
8171 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8172 (compare:CC (zero_extend:DI
8173 (subreg:SI
8174 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8175 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8176 (const_int 0)))
8177 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8178 "TARGET_64BIT"
8179 "@
8180 rldcl. %3,%1,%2,32
8181 rldicl. %3,%1,%H2,32
8182 #
8183 #"
8184 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8185 (set_attr "length" "4,4,8,8")])
8187 (define_split
8188 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8189 (compare:CC (zero_extend:DI
8190 (subreg:SI
8191 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8192 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8193 (const_int 0)))
8194 (clobber (match_scratch:DI 3 ""))]
8195 "TARGET_POWERPC64 && reload_completed"
8196 [(set (match_dup 3)
8197 (zero_extend:DI (subreg:SI
8198 (rotate:DI (match_dup 1)
8199 (match_dup 2)) 0)))
8200 (set (match_dup 0)
8201 (compare:CC (match_dup 3)
8202 (const_int 0)))]
8203 "")
8205 (define_insn "*rotldi3_internal15"
8206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8207 (compare:CC (zero_extend:DI
8208 (subreg:SI
8209 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8210 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8211 (const_int 0)))
8212 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8213 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8214 "TARGET_64BIT"
8215 "@
8216 rldcl. %0,%1,%2,32
8217 rldicl. %0,%1,%H2,32
8218 #
8219 #"
8220 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8221 (set_attr "length" "4,4,8,8")])
8223 (define_split
8224 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8225 (compare:CC (zero_extend:DI
8226 (subreg:SI
8227 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8228 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8229 (const_int 0)))
8230 (set (match_operand:DI 0 "gpc_reg_operand" "")
8231 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8232 "TARGET_POWERPC64 && reload_completed"
8233 [(set (match_dup 0)
8234 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8235 (set (match_dup 3)
8236 (compare:CC (match_dup 0)
8237 (const_int 0)))]
8238 "")
8240 (define_expand "ashldi3"
8241 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8242 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8243 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8244 "TARGET_POWERPC64 || TARGET_POWER"
8245 "
8246 {
8247 if (TARGET_POWERPC64)
8248 ;
8249 else if (TARGET_POWER)
8250 {
8251 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
8252 DONE;
8253 }
8254 else
8255 FAIL;
8256 }")
8258 (define_insn "*ashldi3_internal1"
8259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8260 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8261 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8262 "TARGET_POWERPC64"
8263 "@
8264 sld %0,%1,%2
8265 sldi %0,%1,%H2"
8266 [(set_attr "type" "var_shift_rotate,shift")])
8268 (define_insn "*ashldi3_internal2"
8269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8270 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8271 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8272 (const_int 0)))
8273 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8274 "TARGET_64BIT"
8275 "@
8276 sld. %3,%1,%2
8277 sldi. %3,%1,%H2
8278 #
8279 #"
8280 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8281 (set_attr "length" "4,4,8,8")])
8283 (define_split
8284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8285 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8286 (match_operand:SI 2 "reg_or_cint_operand" ""))
8287 (const_int 0)))
8288 (clobber (match_scratch:DI 3 ""))]
8289 "TARGET_POWERPC64 && reload_completed"
8290 [(set (match_dup 3)
8291 (ashift:DI (match_dup 1) (match_dup 2)))
8292 (set (match_dup 0)
8293 (compare:CC (match_dup 3)
8294 (const_int 0)))]
8295 "")
8297 (define_insn "*ashldi3_internal3"
8298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8299 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8300 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8301 (const_int 0)))
8302 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8303 (ashift:DI (match_dup 1) (match_dup 2)))]
8304 "TARGET_64BIT"
8305 "@
8306 sld. %0,%1,%2
8307 sldi. %0,%1,%H2
8308 #
8309 #"
8310 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8311 (set_attr "length" "4,4,8,8")])
8313 (define_split
8314 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8315 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8316 (match_operand:SI 2 "reg_or_cint_operand" ""))
8317 (const_int 0)))
8318 (set (match_operand:DI 0 "gpc_reg_operand" "")
8319 (ashift:DI (match_dup 1) (match_dup 2)))]
8320 "TARGET_POWERPC64 && reload_completed"
8321 [(set (match_dup 0)
8322 (ashift:DI (match_dup 1) (match_dup 2)))
8323 (set (match_dup 3)
8324 (compare:CC (match_dup 0)
8325 (const_int 0)))]
8326 "")
8328 (define_insn "*ashldi3_internal4"
8329 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8330 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8331 (match_operand:SI 2 "const_int_operand" "i"))
8332 (match_operand:DI 3 "const_int_operand" "n")))]
8333 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
8334 "rldic %0,%1,%H2,%W3")
8336 (define_insn "ashldi3_internal5"
8337 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8338 (compare:CC
8339 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8340 (match_operand:SI 2 "const_int_operand" "i,i"))
8341 (match_operand:DI 3 "const_int_operand" "n,n"))
8342 (const_int 0)))
8343 (clobber (match_scratch:DI 4 "=r,r"))]
8344 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8345 "@
8346 rldic. %4,%1,%H2,%W3
8347 #"
8348 [(set_attr "type" "compare")
8349 (set_attr "length" "4,8")])
8351 (define_split
8352 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8353 (compare:CC
8354 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8355 (match_operand:SI 2 "const_int_operand" ""))
8356 (match_operand:DI 3 "const_int_operand" ""))
8357 (const_int 0)))
8358 (clobber (match_scratch:DI 4 ""))]
8359 "TARGET_POWERPC64 && reload_completed
8360 && includes_rldic_lshift_p (operands[2], operands[3])"
8361 [(set (match_dup 4)
8362 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8363 (match_dup 3)))
8364 (set (match_dup 0)
8365 (compare:CC (match_dup 4)
8366 (const_int 0)))]
8367 "")
8369 (define_insn "*ashldi3_internal6"
8370 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8371 (compare:CC
8372 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8373 (match_operand:SI 2 "const_int_operand" "i,i"))
8374 (match_operand:DI 3 "const_int_operand" "n,n"))
8375 (const_int 0)))
8376 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8377 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8378 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8379 "@
8380 rldic. %0,%1,%H2,%W3
8381 #"
8382 [(set_attr "type" "compare")
8383 (set_attr "length" "4,8")])
8385 (define_split
8386 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8387 (compare:CC
8388 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8389 (match_operand:SI 2 "const_int_operand" ""))
8390 (match_operand:DI 3 "const_int_operand" ""))
8391 (const_int 0)))
8392 (set (match_operand:DI 0 "gpc_reg_operand" "")
8393 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8394 "TARGET_POWERPC64 && reload_completed
8395 && includes_rldic_lshift_p (operands[2], operands[3])"
8396 [(set (match_dup 0)
8397 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8398 (match_dup 3)))
8399 (set (match_dup 4)
8400 (compare:CC (match_dup 0)
8401 (const_int 0)))]
8402 "")
8404 (define_insn "*ashldi3_internal7"
8405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8406 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8407 (match_operand:SI 2 "const_int_operand" "i"))
8408 (match_operand:DI 3 "mask64_operand" "n")))]
8409 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
8410 "rldicr %0,%1,%H2,%S3")
8412 (define_insn "ashldi3_internal8"
8413 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8414 (compare:CC
8415 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8416 (match_operand:SI 2 "const_int_operand" "i,i"))
8417 (match_operand:DI 3 "mask64_operand" "n,n"))
8418 (const_int 0)))
8419 (clobber (match_scratch:DI 4 "=r,r"))]
8420 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8421 "@
8422 rldicr. %4,%1,%H2,%S3
8423 #"
8424 [(set_attr "type" "compare")
8425 (set_attr "length" "4,8")])
8427 (define_split
8428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8429 (compare:CC
8430 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8431 (match_operand:SI 2 "const_int_operand" ""))
8432 (match_operand:DI 3 "mask64_operand" ""))
8433 (const_int 0)))
8434 (clobber (match_scratch:DI 4 ""))]
8435 "TARGET_POWERPC64 && reload_completed
8436 && includes_rldicr_lshift_p (operands[2], operands[3])"
8437 [(set (match_dup 4)
8438 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8439 (match_dup 3)))
8440 (set (match_dup 0)
8441 (compare:CC (match_dup 4)
8442 (const_int 0)))]
8443 "")
8445 (define_insn "*ashldi3_internal9"
8446 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8447 (compare:CC
8448 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8449 (match_operand:SI 2 "const_int_operand" "i,i"))
8450 (match_operand:DI 3 "mask64_operand" "n,n"))
8451 (const_int 0)))
8452 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8453 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8454 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8455 "@
8456 rldicr. %0,%1,%H2,%S3
8457 #"
8458 [(set_attr "type" "compare")
8459 (set_attr "length" "4,8")])
8461 (define_split
8462 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8463 (compare:CC
8464 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8465 (match_operand:SI 2 "const_int_operand" ""))
8466 (match_operand:DI 3 "mask64_operand" ""))
8467 (const_int 0)))
8468 (set (match_operand:DI 0 "gpc_reg_operand" "")
8469 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8470 "TARGET_POWERPC64 && reload_completed
8471 && includes_rldicr_lshift_p (operands[2], operands[3])"
8472 [(set (match_dup 0)
8473 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8474 (match_dup 3)))
8475 (set (match_dup 4)
8476 (compare:CC (match_dup 0)
8477 (const_int 0)))]
8478 "")
8480 (define_expand "lshrdi3"
8481 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8482 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8483 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8484 "TARGET_POWERPC64 || TARGET_POWER"
8485 "
8486 {
8487 if (TARGET_POWERPC64)
8488 ;
8489 else if (TARGET_POWER)
8490 {
8491 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8492 DONE;
8493 }
8494 else
8495 FAIL;
8496 }")
8498 (define_insn "*lshrdi3_internal1"
8499 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8500 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8501 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8502 "TARGET_POWERPC64"
8503 "@
8504 srd %0,%1,%2
8505 srdi %0,%1,%H2"
8506 [(set_attr "type" "var_shift_rotate,shift")])
8508 (define_insn "*lshrdi3_internal2"
8509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8510 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8511 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8512 (const_int 0)))
8513 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8514 "TARGET_64BIT "
8515 "@
8516 srd. %3,%1,%2
8517 srdi. %3,%1,%H2
8518 #
8519 #"
8520 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8521 (set_attr "length" "4,4,8,8")])
8523 (define_split
8524 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8525 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8526 (match_operand:SI 2 "reg_or_cint_operand" ""))
8527 (const_int 0)))
8528 (clobber (match_scratch:DI 3 ""))]
8529 "TARGET_POWERPC64 && reload_completed"
8530 [(set (match_dup 3)
8531 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8532 (set (match_dup 0)
8533 (compare:CC (match_dup 3)
8534 (const_int 0)))]
8535 "")
8537 (define_insn "*lshrdi3_internal3"
8538 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8539 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8540 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8541 (const_int 0)))
8542 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8543 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8544 "TARGET_64BIT"
8545 "@
8546 srd. %0,%1,%2
8547 srdi. %0,%1,%H2
8548 #
8549 #"
8550 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8551 (set_attr "length" "4,4,8,8")])
8553 (define_split
8554 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8555 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8556 (match_operand:SI 2 "reg_or_cint_operand" ""))
8557 (const_int 0)))
8558 (set (match_operand:DI 0 "gpc_reg_operand" "")
8559 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8560 "TARGET_POWERPC64 && reload_completed"
8561 [(set (match_dup 0)
8562 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8563 (set (match_dup 3)
8564 (compare:CC (match_dup 0)
8565 (const_int 0)))]
8566 "")
8568 (define_expand "ashrdi3"
8569 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8570 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8571 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8572 "WORDS_BIG_ENDIAN"
8573 "
8574 {
8575 if (TARGET_POWERPC64)
8576 ;
8577 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8578 {
8579 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8580 DONE;
8581 }
8582 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8583 && WORDS_BIG_ENDIAN)
8584 {
8585 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8586 DONE;
8587 }
8588 else
8589 FAIL;
8590 }")
8592 (define_insn "*ashrdi3_internal1"
8593 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8594 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8595 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8596 "TARGET_POWERPC64"
8597 "@
8598 srad %0,%1,%2
8599 sradi %0,%1,%H2"
8600 [(set_attr "type" "var_shift_rotate,shift")])
8602 (define_insn "*ashrdi3_internal2"
8603 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8604 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8605 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8606 (const_int 0)))
8607 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8608 "TARGET_64BIT"
8609 "@
8610 srad. %3,%1,%2
8611 sradi. %3,%1,%H2
8612 #
8613 #"
8614 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8615 (set_attr "length" "4,4,8,8")])
8617 (define_split
8618 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8619 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8620 (match_operand:SI 2 "reg_or_cint_operand" ""))
8621 (const_int 0)))
8622 (clobber (match_scratch:DI 3 ""))]
8623 "TARGET_POWERPC64 && reload_completed"
8624 [(set (match_dup 3)
8625 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8626 (set (match_dup 0)
8627 (compare:CC (match_dup 3)
8628 (const_int 0)))]
8629 "")
8631 (define_insn "*ashrdi3_internal3"
8632 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8633 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8634 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8635 (const_int 0)))
8636 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8637 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8638 "TARGET_64BIT"
8639 "@
8640 srad. %0,%1,%2
8641 sradi. %0,%1,%H2
8642 #
8643 #"
8644 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8645 (set_attr "length" "4,4,8,8")])
8647 (define_split
8648 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8649 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8650 (match_operand:SI 2 "reg_or_cint_operand" ""))
8651 (const_int 0)))
8652 (set (match_operand:DI 0 "gpc_reg_operand" "")
8653 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8654 "TARGET_POWERPC64 && reload_completed"
8655 [(set (match_dup 0)
8656 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8657 (set (match_dup 3)
8658 (compare:CC (match_dup 0)
8659 (const_int 0)))]
8660 "")
8662 (define_expand "anddi3"
8663 [(parallel
8664 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8665 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8666 (match_operand:DI 2 "and64_2_operand" "")))
8667 (clobber (match_scratch:CC 3 ""))])]
8668 "TARGET_POWERPC64"
8669 "")
8671 (define_insn "anddi3_mc"
8672 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8673 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8674 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8675 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8676 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8677 "@
8678 and %0,%1,%2
8679 rldic%B2 %0,%1,0,%S2
8680 rlwinm %0,%1,0,%m2,%M2
8681 andi. %0,%1,%b2
8682 andis. %0,%1,%u2
8683 #"
8684 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8685 (set_attr "length" "4,4,4,4,4,8")])
8687 (define_insn "anddi3_nomc"
8688 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8689 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8690 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8691 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8692 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8693 "@
8694 and %0,%1,%2
8695 rldic%B2 %0,%1,0,%S2
8696 rlwinm %0,%1,0,%m2,%M2
8697 #"
8698 [(set_attr "length" "4,4,4,8")])
8700 (define_split
8701 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8702 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8703 (match_operand:DI 2 "mask64_2_operand" "")))
8704 (clobber (match_scratch:CC 3 ""))]
8705 "TARGET_POWERPC64
8706 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8707 && !mask_operand (operands[2], DImode)
8708 && !mask64_operand (operands[2], DImode)"
8709 [(set (match_dup 0)
8710 (and:DI (rotate:DI (match_dup 1)
8711 (match_dup 4))
8712 (match_dup 5)))
8713 (set (match_dup 0)
8714 (and:DI (rotate:DI (match_dup 0)
8715 (match_dup 6))
8716 (match_dup 7)))]
8717 {
8718 build_mask64_2_operands (operands[2], &operands[4]);
8719 })
8721 (define_insn "*anddi3_internal2_mc"
8722 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8723 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8724 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8725 (const_int 0)))
8726 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8727 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8728 "TARGET_64BIT && rs6000_gen_cell_microcode"
8729 "@
8730 and. %3,%1,%2
8731 rldic%B2. %3,%1,0,%S2
8732 rlwinm. %3,%1,0,%m2,%M2
8733 andi. %3,%1,%b2
8734 andis. %3,%1,%u2
8735 #
8736 #
8737 #
8738 #
8739 #
8740 #
8741 #"
8742 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8743 fast_compare,compare,compare,compare,compare,compare,\
8744 compare,compare")
8745 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8747 (define_split
8748 [(set (match_operand:CC 0 "cc_reg_operand" "")
8749 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8750 (match_operand:DI 2 "mask64_2_operand" ""))
8751 (const_int 0)))
8752 (clobber (match_scratch:DI 3 ""))
8753 (clobber (match_scratch:CC 4 ""))]
8754 "TARGET_64BIT && reload_completed
8755 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8756 && !mask_operand (operands[2], DImode)
8757 && !mask64_operand (operands[2], DImode)"
8758 [(set (match_dup 3)
8759 (and:DI (rotate:DI (match_dup 1)
8760 (match_dup 5))
8761 (match_dup 6)))
8762 (parallel [(set (match_dup 0)
8763 (compare:CC (and:DI (rotate:DI (match_dup 3)
8764 (match_dup 7))
8765 (match_dup 8))
8766 (const_int 0)))
8767 (clobber (match_dup 3))])]
8768 "
8769 {
8770 build_mask64_2_operands (operands[2], &operands[5]);
8771 }")
8773 (define_insn "*anddi3_internal3_mc"
8774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8775 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8776 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8777 (const_int 0)))
8778 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8779 (and:DI (match_dup 1) (match_dup 2)))
8780 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8781 "TARGET_64BIT && rs6000_gen_cell_microcode"
8782 "@
8783 and. %0,%1,%2
8784 rldic%B2. %0,%1,0,%S2
8785 rlwinm. %0,%1,0,%m2,%M2
8786 andi. %0,%1,%b2
8787 andis. %0,%1,%u2
8788 #
8789 #
8790 #
8791 #
8792 #
8793 #
8794 #"
8795 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8796 fast_compare,compare,compare,compare,compare,compare,\
8797 compare,compare")
8798 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8800 (define_split
8801 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8802 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8803 (match_operand:DI 2 "and64_2_operand" ""))
8804 (const_int 0)))
8805 (set (match_operand:DI 0 "gpc_reg_operand" "")
8806 (and:DI (match_dup 1) (match_dup 2)))
8807 (clobber (match_scratch:CC 4 ""))]
8808 "TARGET_64BIT && reload_completed"
8809 [(parallel [(set (match_dup 0)
8810 (and:DI (match_dup 1) (match_dup 2)))
8811 (clobber (match_dup 4))])
8812 (set (match_dup 3)
8813 (compare:CC (match_dup 0)
8814 (const_int 0)))]
8815 "")
8817 (define_split
8818 [(set (match_operand:CC 3 "cc_reg_operand" "")
8819 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8820 (match_operand:DI 2 "mask64_2_operand" ""))
8821 (const_int 0)))
8822 (set (match_operand:DI 0 "gpc_reg_operand" "")
8823 (and:DI (match_dup 1) (match_dup 2)))
8824 (clobber (match_scratch:CC 4 ""))]
8825 "TARGET_64BIT && reload_completed
8826 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8827 && !mask_operand (operands[2], DImode)
8828 && !mask64_operand (operands[2], DImode)"
8829 [(set (match_dup 0)
8830 (and:DI (rotate:DI (match_dup 1)
8831 (match_dup 5))
8832 (match_dup 6)))
8833 (parallel [(set (match_dup 3)
8834 (compare:CC (and:DI (rotate:DI (match_dup 0)
8835 (match_dup 7))
8836 (match_dup 8))
8837 (const_int 0)))
8838 (set (match_dup 0)
8839 (and:DI (rotate:DI (match_dup 0)
8840 (match_dup 7))
8841 (match_dup 8)))])]
8842 "
8843 {
8844 build_mask64_2_operands (operands[2], &operands[5]);
8845 }")
8847 (define_expand "iordi3"
8848 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8849 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8850 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8851 "TARGET_POWERPC64"
8852 "
8853 {
8854 if (non_logical_cint_operand (operands[2], DImode))
8855 {
8856 HOST_WIDE_INT value;
8857 rtx tmp = ((!can_create_pseudo_p ()
8858 || rtx_equal_p (operands[0], operands[1]))
8859 ? operands[0] : gen_reg_rtx (DImode));
8861 if (GET_CODE (operands[2]) == CONST_INT)
8862 {
8863 value = INTVAL (operands[2]);
8864 emit_insn (gen_iordi3 (tmp, operands[1],
8865 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8866 }
8867 else
8868 {
8869 value = CONST_DOUBLE_LOW (operands[2]);
8870 emit_insn (gen_iordi3 (tmp, operands[1],
8871 immed_double_const (value
8872 & (~ (HOST_WIDE_INT) 0xffff),
8873 0, DImode)));
8874 }
8876 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8877 DONE;
8878 }
8879 }")
8881 (define_expand "xordi3"
8882 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8883 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8884 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8885 "TARGET_POWERPC64"
8886 "
8887 {
8888 if (non_logical_cint_operand (operands[2], DImode))
8889 {
8890 HOST_WIDE_INT value;
8891 rtx tmp = ((!can_create_pseudo_p ()
8892 || rtx_equal_p (operands[0], operands[1]))
8893 ? operands[0] : gen_reg_rtx (DImode));
8895 if (GET_CODE (operands[2]) == CONST_INT)
8896 {
8897 value = INTVAL (operands[2]);
8898 emit_insn (gen_xordi3 (tmp, operands[1],
8899 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8900 }
8901 else
8902 {
8903 value = CONST_DOUBLE_LOW (operands[2]);
8904 emit_insn (gen_xordi3 (tmp, operands[1],
8905 immed_double_const (value
8906 & (~ (HOST_WIDE_INT) 0xffff),
8907 0, DImode)));
8908 }
8910 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8911 DONE;
8912 }
8913 }")
8915 (define_insn "*booldi3_internal1"
8916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8917 (match_operator:DI 3 "boolean_or_operator"
8918 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8919 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8920 "TARGET_POWERPC64"
8921 "@
8922 %q3 %0,%1,%2
8923 %q3i %0,%1,%b2
8924 %q3is %0,%1,%u2")
8926 (define_insn "*booldi3_internal2"
8927 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8928 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8929 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8930 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8931 (const_int 0)))
8932 (clobber (match_scratch:DI 3 "=r,r"))]
8933 "TARGET_64BIT"
8934 "@
8935 %q4. %3,%1,%2
8936 #"
8937 [(set_attr "type" "fast_compare,compare")
8938 (set_attr "length" "4,8")])
8940 (define_split
8941 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8942 (compare:CC (match_operator:DI 4 "boolean_operator"
8943 [(match_operand:DI 1 "gpc_reg_operand" "")
8944 (match_operand:DI 2 "gpc_reg_operand" "")])
8945 (const_int 0)))
8946 (clobber (match_scratch:DI 3 ""))]
8947 "TARGET_POWERPC64 && reload_completed"
8948 [(set (match_dup 3) (match_dup 4))
8949 (set (match_dup 0)
8950 (compare:CC (match_dup 3)
8951 (const_int 0)))]
8952 "")
8954 (define_insn "*booldi3_internal3"
8955 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8956 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8957 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8958 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8959 (const_int 0)))
8960 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8961 (match_dup 4))]
8962 "TARGET_64BIT"
8963 "@
8964 %q4. %0,%1,%2
8965 #"
8966 [(set_attr "type" "fast_compare,compare")
8967 (set_attr "length" "4,8")])
8969 (define_split
8970 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8971 (compare:CC (match_operator:DI 4 "boolean_operator"
8972 [(match_operand:DI 1 "gpc_reg_operand" "")
8973 (match_operand:DI 2 "gpc_reg_operand" "")])
8974 (const_int 0)))
8975 (set (match_operand:DI 0 "gpc_reg_operand" "")
8976 (match_dup 4))]
8977 "TARGET_POWERPC64 && reload_completed"
8978 [(set (match_dup 0) (match_dup 4))
8979 (set (match_dup 3)
8980 (compare:CC (match_dup 0)
8981 (const_int 0)))]
8982 "")
8984 ;; Split a logical operation that we can't do in one insn into two insns,
8985 ;; each of which does one 16-bit part. This is used by combine.
8987 (define_split
8988 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8989 (match_operator:DI 3 "boolean_or_operator"
8990 [(match_operand:DI 1 "gpc_reg_operand" "")
8991 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8992 "TARGET_POWERPC64"
8993 [(set (match_dup 0) (match_dup 4))
8994 (set (match_dup 0) (match_dup 5))]
8995 "
8996 {
8997 rtx i3,i4;
8999 if (GET_CODE (operands[2]) == CONST_DOUBLE)
9000 {
9001 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
9002 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9003 0, DImode);
9004 i4 = GEN_INT (value & 0xffff);
9005 }
9006 else
9007 {
9008 i3 = GEN_INT (INTVAL (operands[2])
9009 & (~ (HOST_WIDE_INT) 0xffff));
9010 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9011 }
9012 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
9013 operands[1], i3);
9014 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
9015 operands[0], i4);
9016 }")
9018 (define_insn "*boolcdi3_internal1"
9019 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9020 (match_operator:DI 3 "boolean_operator"
9021 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9022 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
9023 "TARGET_POWERPC64"
9024 "%q3 %0,%2,%1")
9026 (define_insn "*boolcdi3_internal2"
9027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9028 (compare:CC (match_operator:DI 4 "boolean_operator"
9029 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9030 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9031 (const_int 0)))
9032 (clobber (match_scratch:DI 3 "=r,r"))]
9033 "TARGET_64BIT"
9034 "@
9035 %q4. %3,%2,%1
9036 #"
9037 [(set_attr "type" "fast_compare,compare")
9038 (set_attr "length" "4,8")])
9040 (define_split
9041 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9042 (compare:CC (match_operator:DI 4 "boolean_operator"
9043 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9044 (match_operand:DI 2 "gpc_reg_operand" "")])
9045 (const_int 0)))
9046 (clobber (match_scratch:DI 3 ""))]
9047 "TARGET_POWERPC64 && reload_completed"
9048 [(set (match_dup 3) (match_dup 4))
9049 (set (match_dup 0)
9050 (compare:CC (match_dup 3)
9051 (const_int 0)))]
9052 "")
9054 (define_insn "*boolcdi3_internal3"
9055 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9056 (compare:CC (match_operator:DI 4 "boolean_operator"
9057 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9058 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9059 (const_int 0)))
9060 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9061 (match_dup 4))]
9062 "TARGET_64BIT"
9063 "@
9064 %q4. %0,%2,%1
9065 #"
9066 [(set_attr "type" "fast_compare,compare")
9067 (set_attr "length" "4,8")])
9069 (define_split
9070 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9071 (compare:CC (match_operator:DI 4 "boolean_operator"
9072 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9073 (match_operand:DI 2 "gpc_reg_operand" "")])
9074 (const_int 0)))
9075 (set (match_operand:DI 0 "gpc_reg_operand" "")
9076 (match_dup 4))]
9077 "TARGET_POWERPC64 && reload_completed"
9078 [(set (match_dup 0) (match_dup 4))
9079 (set (match_dup 3)
9080 (compare:CC (match_dup 0)
9081 (const_int 0)))]
9082 "")
9084 (define_insn "*boolccdi3_internal1"
9085 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9086 (match_operator:DI 3 "boolean_operator"
9087 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9088 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
9089 "TARGET_POWERPC64"
9090 "%q3 %0,%1,%2")
9092 (define_insn "*boolccdi3_internal2"
9093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9094 (compare:CC (match_operator:DI 4 "boolean_operator"
9095 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9096 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9097 (const_int 0)))
9098 (clobber (match_scratch:DI 3 "=r,r"))]
9099 "TARGET_64BIT"
9100 "@
9101 %q4. %3,%1,%2
9102 #"
9103 [(set_attr "type" "fast_compare,compare")
9104 (set_attr "length" "4,8")])
9106 (define_split
9107 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9108 (compare:CC (match_operator:DI 4 "boolean_operator"
9109 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9110 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9111 (const_int 0)))
9112 (clobber (match_scratch:DI 3 ""))]
9113 "TARGET_POWERPC64 && reload_completed"
9114 [(set (match_dup 3) (match_dup 4))
9115 (set (match_dup 0)
9116 (compare:CC (match_dup 3)
9117 (const_int 0)))]
9118 "")
9120 (define_insn "*boolccdi3_internal3"
9121 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9122 (compare:CC (match_operator:DI 4 "boolean_operator"
9123 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9124 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9125 (const_int 0)))
9126 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9127 (match_dup 4))]
9128 "TARGET_64BIT"
9129 "@
9130 %q4. %0,%1,%2
9131 #"
9132 [(set_attr "type" "fast_compare,compare")
9133 (set_attr "length" "4,8")])
9135 (define_split
9136 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9137 (compare:CC (match_operator:DI 4 "boolean_operator"
9138 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9139 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9140 (const_int 0)))
9141 (set (match_operand:DI 0 "gpc_reg_operand" "")
9142 (match_dup 4))]
9143 "TARGET_POWERPC64 && reload_completed"
9144 [(set (match_dup 0) (match_dup 4))
9145 (set (match_dup 3)
9146 (compare:CC (match_dup 0)
9147 (const_int 0)))]
9148 "")
9150 (define_expand "smindi3"
9151 [(match_operand:DI 0 "gpc_reg_operand" "")
9152 (match_operand:DI 1 "gpc_reg_operand" "")
9153 (match_operand:DI 2 "gpc_reg_operand" "")]
9154 "TARGET_ISEL64"
9155 "
9156 {
9157 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
9158 DONE;
9159 }")
9161 (define_expand "smaxdi3"
9162 [(match_operand:DI 0 "gpc_reg_operand" "")
9163 (match_operand:DI 1 "gpc_reg_operand" "")
9164 (match_operand:DI 2 "gpc_reg_operand" "")]
9165 "TARGET_ISEL64"
9166 "
9167 {
9168 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
9169 DONE;
9170 }")
9172 (define_expand "umindi3"
9173 [(match_operand:DI 0 "gpc_reg_operand" "")
9174 (match_operand:DI 1 "gpc_reg_operand" "")
9175 (match_operand:DI 2 "gpc_reg_operand" "")]
9176 "TARGET_ISEL64"
9177 "
9178 {
9179 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
9180 DONE;
9181 }")
9183 (define_expand "umaxdi3"
9184 [(match_operand:DI 0 "gpc_reg_operand" "")
9185 (match_operand:DI 1 "gpc_reg_operand" "")
9186 (match_operand:DI 2 "gpc_reg_operand" "")]
9187 "TARGET_ISEL64"
9188 "
9189 {
9190 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
9191 DONE;
9192 }")
9194 \f
9195 ;; Now define ways of moving data around.
9197 ;; Set up a register with a value from the GOT table
9199 (define_expand "movsi_got"
9200 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9201 (unspec:SI [(match_operand:SI 1 "got_operand" "")
9202 (match_dup 2)] UNSPEC_MOVSI_GOT))]
9203 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9204 "
9205 {
9206 if (GET_CODE (operands[1]) == CONST)
9207 {
9208 rtx offset = const0_rtx;
9209 HOST_WIDE_INT value;
9211 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
9212 value = INTVAL (offset);
9213 if (value != 0)
9214 {
9215 rtx tmp = (!can_create_pseudo_p ()
9216 ? operands[0]
9217 : gen_reg_rtx (Pmode));
9218 emit_insn (gen_movsi_got (tmp, operands[1]));
9219 emit_insn (gen_addsi3 (operands[0], tmp, offset));
9220 DONE;
9221 }
9222 }
9224 operands[2] = rs6000_got_register (operands[1]);
9225 }")
9227 (define_insn "*movsi_got_internal"
9228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9229 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9230 (match_operand:SI 2 "gpc_reg_operand" "b")]
9231 UNSPEC_MOVSI_GOT))]
9232 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9233 "{l|lwz} %0,%a1@got(%2)"
9234 [(set_attr "type" "load")])
9236 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
9237 ;; didn't get allocated to a hard register.
9238 (define_split
9239 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9240 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9241 (match_operand:SI 2 "memory_operand" "")]
9242 UNSPEC_MOVSI_GOT))]
9243 "DEFAULT_ABI == ABI_V4
9244 && flag_pic == 1
9245 && (reload_in_progress || reload_completed)"
9246 [(set (match_dup 0) (match_dup 2))
9247 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
9248 UNSPEC_MOVSI_GOT))]
9249 "")
9251 ;; For SI, we special-case integers that can't be loaded in one insn. We
9252 ;; do the load 16-bits at a time. We could do this by loading from memory,
9253 ;; and this is even supposed to be faster, but it is simpler not to get
9254 ;; integers in the TOC.
9255 (define_insn "movsi_low"
9256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9257 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9258 (match_operand 2 "" ""))))]
9259 "TARGET_MACHO && ! TARGET_64BIT"
9260 "{l|lwz} %0,lo16(%2)(%1)"
9261 [(set_attr "type" "load")
9262 (set_attr "length" "4")])
9264 (define_insn "*movsi_internal1"
9265 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
9266 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
9267 "!TARGET_SINGLE_FPU &&
9268 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9269 "@
9270 mr %0,%1
9271 {cal|la} %0,%a1
9272 {l%U1%X1|lwz%U1%X1} %0,%1
9273 {st%U0%X0|stw%U0%X0} %1,%0
9274 {lil|li} %0,%1
9275 {liu|lis} %0,%v1
9276 #
9277 {cal|la} %0,%a1
9278 mf%1 %0
9279 mt%0 %1
9280 mt%0 %1
9281 mt%0 %1
9282 {cror 0,0,0|nop}"
9283 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
9284 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
9286 (define_insn "*movsi_internal1_single"
9287 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
9288 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
9289 "TARGET_SINGLE_FPU &&
9290 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9291 "@
9292 mr %0,%1
9293 {cal|la} %0,%a1
9294 {l%U1%X1|lwz%U1%X1} %0,%1
9295 {st%U0%X0|stw%U0%X0} %1,%0
9296 {lil|li} %0,%1
9297 {liu|lis} %0,%v1
9298 #
9299 {cal|la} %0,%a1
9300 mf%1 %0
9301 mt%0 %1
9302 mt%0 %1
9303 mt%0 %1
9304 {cror 0,0,0|nop}
9305 stfs%U0%X0 %1, %0
9306 lfs%U1%X1 %0, %1"
9307 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
9308 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
9310 ;; Split a load of a large constant into the appropriate two-insn
9311 ;; sequence.
9313 (define_split
9314 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9315 (match_operand:SI 1 "const_int_operand" ""))]
9316 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9317 && (INTVAL (operands[1]) & 0xffff) != 0"
9318 [(set (match_dup 0)
9319 (match_dup 2))
9320 (set (match_dup 0)
9321 (ior:SI (match_dup 0)
9322 (match_dup 3)))]
9323 "
9324 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9326 if (tem == operands[0])
9327 DONE;
9328 else
9329 FAIL;
9330 }")
9332 (define_insn "*mov<mode>_internal2"
9333 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9334 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9335 (const_int 0)))
9336 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9337 ""
9338 "@
9339 {cmpi|cmp<wd>i} %2,%0,0
9340 mr. %0,%1
9341 #"
9342 [(set_attr "type" "cmp,compare,cmp")
9343 (set_attr "length" "4,4,8")])
9345 (define_split
9346 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9347 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9348 (const_int 0)))
9349 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9350 "reload_completed"
9351 [(set (match_dup 0) (match_dup 1))
9352 (set (match_dup 2)
9353 (compare:CC (match_dup 0)
9354 (const_int 0)))]
9355 "")
9356 \f
9357 (define_insn "*movhi_internal"
9358 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9359 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9360 "gpc_reg_operand (operands[0], HImode)
9361 || gpc_reg_operand (operands[1], HImode)"
9362 "@
9363 mr %0,%1
9364 lhz%U1%X1 %0,%1
9365 sth%U0%X0 %1,%0
9366 {lil|li} %0,%w1
9367 mf%1 %0
9368 mt%0 %1
9369 mt%0 %1
9370 {cror 0,0,0|nop}"
9371 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9373 (define_expand "mov<mode>"
9374 [(set (match_operand:INT 0 "general_operand" "")
9375 (match_operand:INT 1 "any_operand" ""))]
9376 ""
9377 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9379 (define_insn "*movqi_internal"
9380 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9381 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9382 "gpc_reg_operand (operands[0], QImode)
9383 || gpc_reg_operand (operands[1], QImode)"
9384 "@
9385 mr %0,%1
9386 lbz%U1%X1 %0,%1
9387 stb%U0%X0 %1,%0
9388 {lil|li} %0,%1
9389 mf%1 %0
9390 mt%0 %1
9391 mt%0 %1
9392 {cror 0,0,0|nop}"
9393 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9394 \f
9395 ;; Here is how to move condition codes around. When we store CC data in
9396 ;; an integer register or memory, we store just the high-order 4 bits.
9397 ;; This lets us not shift in the most common case of CR0.
9398 (define_expand "movcc"
9399 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9400 (match_operand:CC 1 "nonimmediate_operand" ""))]
9401 ""
9402 "")
9404 (define_insn "*movcc_internal1"
9405 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
9406 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
9407 "register_operand (operands[0], CCmode)
9408 || register_operand (operands[1], CCmode)"
9409 "@
9410 mcrf %0,%1
9411 mtcrf 128,%1
9412 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
9413 crxor %0,%0,%0
9414 mfcr %0%Q1
9415 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
9416 mr %0,%1
9417 {lil|li} %0,%1
9418 mf%1 %0
9419 mt%0 %1
9420 mt%0 %1
9421 {l%U1%X1|lwz%U1%X1} %0,%1
9422 {st%U0%U1|stw%U0%U1} %1,%0"
9423 [(set (attr "type")
9424 (cond [(eq_attr "alternative" "0,3")
9425 (const_string "cr_logical")
9426 (eq_attr "alternative" "1,2")
9427 (const_string "mtcr")
9428 (eq_attr "alternative" "6,7,9")
9429 (const_string "integer")
9430 (eq_attr "alternative" "8")
9431 (const_string "mfjmpr")
9432 (eq_attr "alternative" "10")
9433 (const_string "mtjmpr")
9434 (eq_attr "alternative" "11")
9435 (const_string "load")
9436 (eq_attr "alternative" "12")
9437 (const_string "store")
9438 (match_test "TARGET_MFCRF")
9439 (const_string "mfcrf")
9440 ]
9441 (const_string "mfcr")))
9442 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
9443 \f
9444 ;; For floating-point, we normally deal with the floating-point registers
9445 ;; unless -msoft-float is used. The sole exception is that parameter passing
9446 ;; can produce floating-point values in fixed-point registers. Unless the
9447 ;; value is a simple constant or already in memory, we deal with this by
9448 ;; allocating memory and copying the value explicitly via that memory location.
9449 (define_expand "movsf"
9450 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9451 (match_operand:SF 1 "any_operand" ""))]
9452 ""
9453 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9455 (define_split
9456 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9457 (match_operand:SF 1 "const_double_operand" ""))]
9458 "reload_completed
9459 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9460 || (GET_CODE (operands[0]) == SUBREG
9461 && GET_CODE (SUBREG_REG (operands[0])) == REG
9462 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9463 [(set (match_dup 2) (match_dup 3))]
9464 "
9465 {
9466 long l;
9467 REAL_VALUE_TYPE rv;
9469 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9470 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9472 if (! TARGET_POWERPC64)
9473 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9474 else
9475 operands[2] = gen_lowpart (SImode, operands[0]);
9477 operands[3] = gen_int_mode (l, SImode);
9478 }")
9480 (define_insn "*movsf_hardfloat"
9481 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9482 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9483 "(gpc_reg_operand (operands[0], SFmode)
9484 || gpc_reg_operand (operands[1], SFmode))
9485 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9486 "@
9487 mr %0,%1
9488 {l%U1%X1|lwz%U1%X1} %0,%1
9489 {st%U0%X0|stw%U0%X0} %1,%0
9490 fmr %0,%1
9491 lfs%U1%X1 %0,%1
9492 stfs%U0%X0 %1,%0
9493 mt%0 %1
9494 mt%0 %1
9495 mf%1 %0
9496 {cror 0,0,0|nop}
9497 #
9498 #"
9499 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9500 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9502 (define_insn "*movsf_softfloat"
9503 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9504 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9505 "(gpc_reg_operand (operands[0], SFmode)
9506 || gpc_reg_operand (operands[1], SFmode))
9507 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9508 "@
9509 mr %0,%1
9510 mt%0 %1
9511 mt%0 %1
9512 mf%1 %0
9513 {l%U1%X1|lwz%U1%X1} %0,%1
9514 {st%U0%X0|stw%U0%X0} %1,%0
9515 {lil|li} %0,%1
9516 {liu|lis} %0,%v1
9517 {cal|la} %0,%a1
9518 #
9519 #
9520 {cror 0,0,0|nop}"
9521 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9522 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9524 \f
9525 (define_expand "movdf"
9526 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9527 (match_operand:DF 1 "any_operand" ""))]
9528 ""
9529 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9531 (define_split
9532 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9533 (match_operand:DF 1 "const_int_operand" ""))]
9534 "! TARGET_POWERPC64 && reload_completed
9535 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9536 || (GET_CODE (operands[0]) == SUBREG
9537 && GET_CODE (SUBREG_REG (operands[0])) == REG
9538 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9539 [(set (match_dup 2) (match_dup 4))
9540 (set (match_dup 3) (match_dup 1))]
9541 "
9542 {
9543 int endian = (WORDS_BIG_ENDIAN == 0);
9544 HOST_WIDE_INT value = INTVAL (operands[1]);
9546 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9547 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9548 #if HOST_BITS_PER_WIDE_INT == 32
9549 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9550 #else
9551 operands[4] = GEN_INT (value >> 32);
9552 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9553 #endif
9554 }")
9556 (define_split
9557 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9558 (match_operand:DF 1 "const_double_operand" ""))]
9559 "! TARGET_POWERPC64 && reload_completed
9560 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9561 || (GET_CODE (operands[0]) == SUBREG
9562 && GET_CODE (SUBREG_REG (operands[0])) == REG
9563 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9564 [(set (match_dup 2) (match_dup 4))
9565 (set (match_dup 3) (match_dup 5))]
9566 "
9567 {
9568 int endian = (WORDS_BIG_ENDIAN == 0);
9569 long l[2];
9570 REAL_VALUE_TYPE rv;
9572 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9573 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9575 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9576 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9577 operands[4] = gen_int_mode (l[endian], SImode);
9578 operands[5] = gen_int_mode (l[1 - endian], SImode);
9579 }")
9581 (define_split
9582 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9583 (match_operand:DF 1 "const_double_operand" ""))]
9584 "TARGET_POWERPC64 && reload_completed
9585 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9586 || (GET_CODE (operands[0]) == SUBREG
9587 && GET_CODE (SUBREG_REG (operands[0])) == REG
9588 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9589 [(set (match_dup 2) (match_dup 3))]
9590 "
9591 {
9592 int endian = (WORDS_BIG_ENDIAN == 0);
9593 long l[2];
9594 REAL_VALUE_TYPE rv;
9595 #if HOST_BITS_PER_WIDE_INT >= 64
9596 HOST_WIDE_INT val;
9597 #endif
9599 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9600 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9602 operands[2] = gen_lowpart (DImode, operands[0]);
9603 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9604 #if HOST_BITS_PER_WIDE_INT >= 64
9605 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9606 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9608 operands[3] = gen_int_mode (val, DImode);
9609 #else
9610 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9611 #endif
9612 }")
9614 ;; Don't have reload use general registers to load a constant. First,
9615 ;; it might not work if the output operand is the equivalent of
9616 ;; a non-offsettable memref, but also it is less efficient than loading
9617 ;; the constant into an FP register, since it will probably be used there.
9618 ;; The "??" is a kludge until we can figure out a more reasonable way
9619 ;; of handling these non-offsettable values.
9620 (define_insn "*movdf_hardfloat32"
9621 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9622 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9623 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9624 && (gpc_reg_operand (operands[0], DFmode)
9625 || gpc_reg_operand (operands[1], DFmode))"
9626 "*
9627 {
9628 switch (which_alternative)
9629 {
9630 default:
9631 gcc_unreachable ();
9632 case 0:
9633 case 1:
9634 case 2:
9635 return \"#\";
9636 case 3:
9637 case 4:
9638 return \"xxlor %x0,%x1,%x1\";
9639 case 5:
9640 case 6:
9641 return \"lxsd%U1x %x0,%y1\";
9642 case 7:
9643 case 8:
9644 return \"stxsd%U0x %x1,%y0\";
9645 case 9:
9646 return \"fmr %0,%1\";
9647 case 10:
9648 return \"lfd%U1%X1 %0,%1\";
9649 case 11:
9650 return \"stfd%U0%X0 %1,%0\";
9651 case 12:
9652 return \"xxlxor %x0,%x0,%x0\";
9653 case 13:
9654 case 14:
9655 case 15:
9656 return \"#\";
9657 }
9658 }"
9659 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9660 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9662 (define_insn "*movdf_softfloat32"
9663 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9664 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9665 "! TARGET_POWERPC64
9666 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9667 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9668 && (gpc_reg_operand (operands[0], DFmode)
9669 || gpc_reg_operand (operands[1], DFmode))"
9670 "#"
9671 [(set_attr "type" "two,load,store,*,*,*")
9672 (set_attr "length" "8,8,8,8,12,16")])
9674 ;; Reload patterns to support gpr load/store with misaligned mem.
9675 (define_expand "reload_di_store"
9676 [(parallel [(match_operand 0 "memory_operand" "=m")
9677 (match_operand 1 "gpc_reg_operand" "r")
9678 (match_operand:DI 2 "register_operand" "=&b")])]
9679 "TARGET_POWERPC64"
9680 {
9681 rs6000_secondary_reload_ppc64 (operands[1], operands[0], operands[2], true);
9682 DONE;
9683 })
9685 (define_expand "reload_di_load"
9686 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9687 (match_operand 1 "memory_operand" "m")
9688 (match_operand:DI 2 "register_operand" "=b")])]
9689 "TARGET_POWERPC64"
9690 {
9691 rs6000_secondary_reload_ppc64 (operands[0], operands[1], operands[2], false);
9692 DONE;
9693 })
9695 ; ld/std require word-aligned displacements -> 'Y' constraint.
9696 ; List Y->r and r->Y before r->r for reload.
9697 (define_insn "*movdf_hardfloat64_mfpgpr"
9698 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9699 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9700 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9701 && TARGET_DOUBLE_FLOAT
9702 && (gpc_reg_operand (operands[0], DFmode)
9703 || gpc_reg_operand (operands[1], DFmode))"
9704 "@
9705 std%U0%X0 %1,%0
9706 ld%U1%X1 %0,%1
9707 mr %0,%1
9708 xxlor %x0,%x1,%x1
9709 xxlor %x0,%x1,%x1
9710 lxsd%U1x %x0,%y1
9711 lxsd%U1x %x0,%y1
9712 stxsd%U0x %x1,%y0
9713 stxsd%U0x %x1,%y0
9714 fmr %0,%1
9715 lfd%U1%X1 %0,%1
9716 stfd%U0%X0 %1,%0
9717 xxlxor %x0,%x0,%x0
9718 mt%0 %1
9719 mf%1 %0
9720 {cror 0,0,0|nop}
9721 #
9722 #
9723 #
9724 mftgpr %0,%1
9725 mffgpr %0,%1"
9726 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9727 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9729 ; ld/std require word-aligned displacements -> 'Y' constraint.
9730 ; List Y->r and r->Y before r->r for reload.
9731 (define_insn "*movdf_hardfloat64"
9732 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9733 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9734 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9735 && TARGET_DOUBLE_FLOAT
9736 && (gpc_reg_operand (operands[0], DFmode)
9737 || gpc_reg_operand (operands[1], DFmode))"
9738 "@
9739 std%U0%X0 %1,%0
9740 ld%U1%X1 %0,%1
9741 mr %0,%1
9742 xxlor %x0,%x1,%x1
9743 xxlor %x0,%x1,%x1
9744 lxsd%U1x %x0,%y1
9745 lxsd%U1x %x0,%y1
9746 stxsd%U0x %x1,%y0
9747 stxsd%U0x %x1,%y0
9748 fmr %0,%1
9749 lfd%U1%X1 %0,%1
9750 stfd%U0%X0 %1,%0
9751 xxlxor %x0,%x0,%x0
9752 mt%0 %1
9753 mf%1 %0
9754 {cror 0,0,0|nop}
9755 #
9756 #
9757 #"
9758 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9759 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9761 (define_insn "*movdf_softfloat64"
9762 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9763 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9764 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9765 && (gpc_reg_operand (operands[0], DFmode)
9766 || gpc_reg_operand (operands[1], DFmode))"
9767 "@
9768 ld%U1%X1 %0,%1
9769 std%U0%X0 %1,%0
9770 mr %0,%1
9771 mt%0 %1
9772 mf%1 %0
9773 #
9774 #
9775 #
9776 {cror 0,0,0|nop}"
9777 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9778 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9779 \f
9780 (define_expand "movtf"
9781 [(set (match_operand:TF 0 "general_operand" "")
9782 (match_operand:TF 1 "any_operand" ""))]
9783 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9784 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9786 ; It's important to list the o->f and f->o moves before f->f because
9787 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9788 ; which doesn't make progress. Likewise r->Y must be before r->r.
9789 (define_insn_and_split "*movtf_internal"
9790 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9791 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9792 "!TARGET_IEEEQUAD
9793 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9794 && (gpc_reg_operand (operands[0], TFmode)
9795 || gpc_reg_operand (operands[1], TFmode))"
9796 "#"
9797 "&& reload_completed"
9798 [(pc)]
9799 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9800 [(set_attr "length" "8,8,8,20,20,16")])
9802 (define_insn_and_split "*movtf_softfloat"
9803 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9804 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9805 "!TARGET_IEEEQUAD
9806 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9807 && (gpc_reg_operand (operands[0], TFmode)
9808 || gpc_reg_operand (operands[1], TFmode))"
9809 "#"
9810 "&& reload_completed"
9811 [(pc)]
9812 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9813 [(set_attr "length" "20,20,16")])
9815 (define_expand "extenddftf2"
9816 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9817 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9818 "!TARGET_IEEEQUAD
9819 && TARGET_HARD_FLOAT
9820 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9821 && TARGET_LONG_DOUBLE_128"
9822 {
9823 if (TARGET_E500_DOUBLE)
9824 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9825 else
9826 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9827 DONE;
9828 })
9830 (define_expand "extenddftf2_fprs"
9831 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9832 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9833 (use (match_dup 2))])]
9834 "!TARGET_IEEEQUAD
9835 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9836 && TARGET_LONG_DOUBLE_128"
9837 {
9838 operands[2] = CONST0_RTX (DFmode);
9839 /* Generate GOT reference early for SVR4 PIC. */
9840 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9841 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9842 })
9844 (define_insn_and_split "*extenddftf2_internal"
9845 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9846 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9847 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9848 "!TARGET_IEEEQUAD
9849 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9850 && TARGET_LONG_DOUBLE_128"
9851 "#"
9852 "&& reload_completed"
9853 [(pc)]
9854 {
9855 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9856 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9857 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9858 operands[1]);
9859 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9860 operands[2]);
9861 DONE;
9862 })
9864 (define_expand "extendsftf2"
9865 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9866 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9867 "!TARGET_IEEEQUAD
9868 && TARGET_HARD_FLOAT
9869 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9870 && TARGET_LONG_DOUBLE_128"
9871 {
9872 rtx tmp = gen_reg_rtx (DFmode);
9873 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9874 emit_insn (gen_extenddftf2 (operands[0], tmp));
9875 DONE;
9876 })
9878 (define_expand "trunctfdf2"
9879 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9880 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9881 "!TARGET_IEEEQUAD
9882 && TARGET_HARD_FLOAT
9883 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9884 && TARGET_LONG_DOUBLE_128"
9885 "")
9887 (define_insn_and_split "trunctfdf2_internal1"
9888 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9889 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9890 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9891 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9892 "@
9893 #
9894 fmr %0,%1"
9895 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9896 [(const_int 0)]
9897 {
9898 emit_note (NOTE_INSN_DELETED);
9899 DONE;
9900 }
9901 [(set_attr "type" "fp")])
9903 (define_insn "trunctfdf2_internal2"
9904 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9905 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9906 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9907 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9908 && TARGET_LONG_DOUBLE_128"
9909 "fadd %0,%1,%L1"
9910 [(set_attr "type" "fp")
9911 (set_attr "fp_type" "fp_addsub_d")])
9913 (define_expand "trunctfsf2"
9914 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9915 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9916 "!TARGET_IEEEQUAD
9917 && TARGET_HARD_FLOAT
9918 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9919 && TARGET_LONG_DOUBLE_128"
9920 {
9921 if (TARGET_E500_DOUBLE)
9922 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9923 else
9924 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9925 DONE;
9926 })
9928 (define_insn_and_split "trunctfsf2_fprs"
9929 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9930 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9931 (clobber (match_scratch:DF 2 "=d"))]
9932 "!TARGET_IEEEQUAD
9933 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9934 && TARGET_LONG_DOUBLE_128"
9935 "#"
9936 "&& reload_completed"
9937 [(set (match_dup 2)
9938 (float_truncate:DF (match_dup 1)))
9939 (set (match_dup 0)
9940 (float_truncate:SF (match_dup 2)))]
9941 "")
9943 (define_expand "floatsitf2"
9944 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9945 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9946 "!TARGET_IEEEQUAD
9947 && TARGET_HARD_FLOAT
9948 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9949 && TARGET_LONG_DOUBLE_128"
9950 {
9951 rtx tmp = gen_reg_rtx (DFmode);
9952 expand_float (tmp, operands[1], false);
9953 emit_insn (gen_extenddftf2 (operands[0], tmp));
9954 DONE;
9955 })
9957 ; fadd, but rounding towards zero.
9958 ; This is probably not the optimal code sequence.
9959 (define_insn "fix_trunc_helper"
9960 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9961 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9962 UNSPEC_FIX_TRUNC_TF))
9963 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9964 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9965 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9966 [(set_attr "type" "fp")
9967 (set_attr "length" "20")])
9969 (define_expand "fix_trunctfsi2"
9970 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9971 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9972 "!TARGET_IEEEQUAD
9973 && (TARGET_POWER2 || TARGET_POWERPC)
9974 && TARGET_HARD_FLOAT
9975 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9976 && TARGET_LONG_DOUBLE_128"
9977 {
9978 if (TARGET_E500_DOUBLE)
9979 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9980 else
9981 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9982 DONE;
9983 })
9985 (define_expand "fix_trunctfsi2_fprs"
9986 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9987 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9988 (clobber (match_dup 2))
9989 (clobber (match_dup 3))
9990 (clobber (match_dup 4))
9991 (clobber (match_dup 5))])]
9992 "!TARGET_IEEEQUAD
9993 && (TARGET_POWER2 || TARGET_POWERPC)
9994 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9995 {
9996 operands[2] = gen_reg_rtx (DFmode);
9997 operands[3] = gen_reg_rtx (DFmode);
9998 operands[4] = gen_reg_rtx (DImode);
9999 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
10000 })
10002 (define_insn_and_split "*fix_trunctfsi2_internal"
10003 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10004 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
10005 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
10006 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
10007 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
10008 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
10009 "!TARGET_IEEEQUAD
10010 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10011 "#"
10012 ""
10013 [(pc)]
10014 {
10015 rtx lowword;
10016 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
10018 gcc_assert (MEM_P (operands[5]));
10019 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
10021 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
10022 emit_move_insn (operands[5], operands[4]);
10023 emit_move_insn (operands[0], lowword);
10024 DONE;
10025 })
10027 (define_expand "negtf2"
10028 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10029 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10030 "!TARGET_IEEEQUAD
10031 && TARGET_HARD_FLOAT
10032 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10033 && TARGET_LONG_DOUBLE_128"
10034 "")
10036 (define_insn "negtf2_internal"
10037 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
10038 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
10039 "!TARGET_IEEEQUAD
10040 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10041 "*
10042 {
10043 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
10044 return \"fneg %L0,%L1\;fneg %0,%1\";
10045 else
10046 return \"fneg %0,%1\;fneg %L0,%L1\";
10047 }"
10048 [(set_attr "type" "fp")
10049 (set_attr "length" "8")])
10051 (define_expand "abstf2"
10052 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10053 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10054 "!TARGET_IEEEQUAD
10055 && TARGET_HARD_FLOAT
10056 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10057 && TARGET_LONG_DOUBLE_128"
10058 "
10059 {
10060 rtx label = gen_label_rtx ();
10061 if (TARGET_E500_DOUBLE)
10062 {
10063 if (flag_finite_math_only && !flag_trapping_math)
10064 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
10065 else
10066 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
10067 }
10068 else
10069 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
10070 emit_label (label);
10071 DONE;
10072 }")
10074 (define_expand "abstf2_internal"
10075 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10076 (match_operand:TF 1 "gpc_reg_operand" ""))
10077 (set (match_dup 3) (match_dup 5))
10078 (set (match_dup 5) (abs:DF (match_dup 5)))
10079 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
10080 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
10081 (label_ref (match_operand 2 "" ""))
10082 (pc)))
10083 (set (match_dup 6) (neg:DF (match_dup 6)))]
10084 "!TARGET_IEEEQUAD
10085 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10086 && TARGET_LONG_DOUBLE_128"
10087 "
10088 {
10089 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10090 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10091 operands[3] = gen_reg_rtx (DFmode);
10092 operands[4] = gen_reg_rtx (CCFPmode);
10093 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10094 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10095 }")
10096 \f
10097 ;; Next come the multi-word integer load and store and the load and store
10098 ;; multiple insns.
10100 ; List r->r after r->"o<>", otherwise reload will try to reload a
10101 ; non-offsettable address by using r->r which won't make progress.
10102 (define_insn "*movdi_internal32"
10103 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r,?wa")
10104 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF,O"))]
10105 "! TARGET_POWERPC64
10106 && (gpc_reg_operand (operands[0], DImode)
10107 || gpc_reg_operand (operands[1], DImode))"
10108 "@
10109 #
10110 #
10111 #
10112 fmr %0,%1
10113 lfd%U1%X1 %0,%1
10114 stfd%U0%X0 %1,%0
10115 #
10116 xxlxor %x0,%x0,%x0"
10117 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*,vecsimple")])
10119 (define_split
10120 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10121 (match_operand:DI 1 "const_int_operand" ""))]
10122 "! TARGET_POWERPC64 && reload_completed
10123 && gpr_or_gpr_p (operands[0], operands[1])"
10124 [(set (match_dup 2) (match_dup 4))
10125 (set (match_dup 3) (match_dup 1))]
10126 "
10127 {
10128 HOST_WIDE_INT value = INTVAL (operands[1]);
10129 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10130 DImode);
10131 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10132 DImode);
10133 #if HOST_BITS_PER_WIDE_INT == 32
10134 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
10135 #else
10136 operands[4] = GEN_INT (value >> 32);
10137 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10138 #endif
10139 }")
10141 (define_split
10142 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10143 (match_operand:DIFD 1 "input_operand" ""))]
10144 "reload_completed && !TARGET_POWERPC64
10145 && gpr_or_gpr_p (operands[0], operands[1])"
10146 [(pc)]
10147 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10149 (define_insn "*movdi_mfpgpr"
10150 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
10151 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
10152 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
10153 && (gpc_reg_operand (operands[0], DImode)
10154 || gpc_reg_operand (operands[1], DImode))"
10155 "@
10156 mr %0,%1
10157 ld%U1%X1 %0,%1
10158 std%U0%X0 %1,%0
10159 li %0,%1
10160 lis %0,%v1
10161 #
10162 la %0,%a1
10163 fmr %0,%1
10164 lfd%U1%X1 %0,%1
10165 stfd%U0%X0 %1,%0
10166 mf%1 %0
10167 mt%0 %1
10168 {cror 0,0,0|nop}
10169 mftgpr %0,%1
10170 mffgpr %0,%1"
10171 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
10172 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
10174 (define_insn "*movdi_internal64"
10175 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,?wa")
10176 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,O"))]
10177 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
10178 && (gpc_reg_operand (operands[0], DImode)
10179 || gpc_reg_operand (operands[1], DImode))"
10180 "@
10181 mr %0,%1
10182 ld%U1%X1 %0,%1
10183 std%U0%X0 %1,%0
10184 li %0,%1
10185 lis %0,%v1
10186 #
10187 la %0,%a1
10188 fmr %0,%1
10189 lfd%U1%X1 %0,%1
10190 stfd%U0%X0 %1,%0
10191 mf%1 %0
10192 mt%0 %1
10193 {cror 0,0,0|nop}
10194 xxlxor %x0,%x0,%x0"
10195 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,vecsimple")
10196 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
10198 ;; immediate value valid for a single instruction hiding in a const_double
10199 (define_insn ""
10200 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10201 (match_operand:DI 1 "const_double_operand" "F"))]
10202 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
10203 && GET_CODE (operands[1]) == CONST_DOUBLE
10204 && num_insns_constant (operands[1], DImode) == 1"
10205 "*
10206 {
10207 return ((unsigned HOST_WIDE_INT)
10208 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
10209 ? \"li %0,%1\" : \"lis %0,%v1\";
10210 }")
10212 ;; Generate all one-bits and clear left or right.
10213 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10214 (define_split
10215 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10216 (match_operand:DI 1 "mask64_operand" ""))]
10217 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10218 [(set (match_dup 0) (const_int -1))
10219 (set (match_dup 0)
10220 (and:DI (rotate:DI (match_dup 0)
10221 (const_int 0))
10222 (match_dup 1)))]
10223 "")
10225 ;; Split a load of a large constant into the appropriate five-instruction
10226 ;; sequence. Handle anything in a constant number of insns.
10227 ;; When non-easy constants can go in the TOC, this should use
10228 ;; easy_fp_constant predicate.
10229 (define_split
10230 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10231 (match_operand:DI 1 "const_int_operand" ""))]
10232 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10233 [(set (match_dup 0) (match_dup 2))
10234 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10235 "
10236 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10238 if (tem == operands[0])
10239 DONE;
10240 else
10241 FAIL;
10242 }")
10244 (define_split
10245 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10246 (match_operand:DI 1 "const_double_operand" ""))]
10247 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10248 [(set (match_dup 0) (match_dup 2))
10249 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10250 "
10251 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10253 if (tem == operands[0])
10254 DONE;
10255 else
10256 FAIL;
10257 }")
10258 \f
10259 ;; TImode is similar, except that we usually want to compute the address into
10260 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
10261 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
10263 ;; We say that MQ is clobbered in the last alternative because the first
10264 ;; alternative would never get used otherwise since it would need a reload
10265 ;; while the 2nd alternative would not. We put memory cases first so they
10266 ;; are preferred. Otherwise, we'd try to reload the output instead of
10267 ;; giving the SCRATCH mq.
10269 (define_insn "*movti_power"
10270 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
10271 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
10272 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
10273 "TARGET_POWER && ! TARGET_POWERPC64
10274 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10275 "*
10276 {
10277 switch (which_alternative)
10278 {
10279 default:
10280 gcc_unreachable ();
10282 case 0:
10283 if (TARGET_STRING)
10284 return \"{stsi|stswi} %1,%P0,16\";
10285 case 1:
10286 case 2:
10287 return \"#\";
10288 case 3:
10289 /* If the address is not used in the output, we can use lsi. Otherwise,
10290 fall through to generating four loads. */
10291 if (TARGET_STRING
10292 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10293 return \"{lsi|lswi} %0,%P1,16\";
10294 /* ... fall through ... */
10295 case 4:
10296 case 5:
10297 return \"#\";
10298 }
10299 }"
10300 [(set_attr "type" "store,store,*,load,load,*")])
10302 (define_insn "*movti_string"
10303 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
10304 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
10305 "! TARGET_POWER && ! TARGET_POWERPC64
10306 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10307 "*
10308 {
10309 switch (which_alternative)
10310 {
10311 default:
10312 gcc_unreachable ();
10313 case 0:
10314 if (TARGET_STRING)
10315 return \"{stsi|stswi} %1,%P0,16\";
10316 case 1:
10317 case 2:
10318 return \"#\";
10319 case 3:
10320 /* If the address is not used in the output, we can use lsi. Otherwise,
10321 fall through to generating four loads. */
10322 if (TARGET_STRING
10323 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10324 return \"{lsi|lswi} %0,%P1,16\";
10325 /* ... fall through ... */
10326 case 4:
10327 case 5:
10328 return \"#\";
10329 }
10330 }"
10331 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
10332 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
10333 (const_string "always")
10334 (const_string "conditional")))])
10336 (define_insn "*movti_ppc64"
10337 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
10338 (match_operand:TI 1 "input_operand" "r,r,m"))]
10339 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
10340 || gpc_reg_operand (operands[1], TImode)))
10341 && VECTOR_MEM_NONE_P (TImode)"
10342 "#"
10343 [(set_attr "type" "*,store,load")])
10345 (define_split
10346 [(set (match_operand:TI 0 "gpc_reg_operand" "")
10347 (match_operand:TI 1 "const_double_operand" ""))]
10348 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
10349 [(set (match_dup 2) (match_dup 4))
10350 (set (match_dup 3) (match_dup 5))]
10351 "
10352 {
10353 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10354 TImode);
10355 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10356 TImode);
10357 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10358 {
10359 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10360 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10361 }
10362 else if (GET_CODE (operands[1]) == CONST_INT)
10363 {
10364 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10365 operands[5] = operands[1];
10366 }
10367 else
10368 FAIL;
10369 }")
10371 (define_split
10372 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10373 (match_operand:TI 1 "input_operand" ""))]
10374 "reload_completed && VECTOR_MEM_NONE_P (TImode)
10375 && gpr_or_gpr_p (operands[0], operands[1])"
10376 [(pc)]
10377 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10378 \f
10379 (define_expand "load_multiple"
10380 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10381 (match_operand:SI 1 "" ""))
10382 (use (match_operand:SI 2 "" ""))])]
10383 "TARGET_STRING && !TARGET_POWERPC64"
10384 "
10385 {
10386 int regno;
10387 int count;
10388 rtx op1;
10389 int i;
10391 /* Support only loading a constant number of fixed-point registers from
10392 memory and only bother with this if more than two; the machine
10393 doesn't support more than eight. */
10394 if (GET_CODE (operands[2]) != CONST_INT
10395 || INTVAL (operands[2]) <= 2
10396 || INTVAL (operands[2]) > 8
10397 || GET_CODE (operands[1]) != MEM
10398 || GET_CODE (operands[0]) != REG
10399 || REGNO (operands[0]) >= 32)
10400 FAIL;
10402 count = INTVAL (operands[2]);
10403 regno = REGNO (operands[0]);
10405 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10406 op1 = replace_equiv_address (operands[1],
10407 force_reg (SImode, XEXP (operands[1], 0)));
10409 for (i = 0; i < count; i++)
10410 XVECEXP (operands[3], 0, i)
10411 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10412 adjust_address_nv (op1, SImode, i * 4));
10413 }")
10415 (define_insn "*ldmsi8"
10416 [(match_parallel 0 "load_multiple_operation"
10417 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10418 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10419 (set (match_operand:SI 3 "gpc_reg_operand" "")
10420 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10421 (set (match_operand:SI 4 "gpc_reg_operand" "")
10422 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10423 (set (match_operand:SI 5 "gpc_reg_operand" "")
10424 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10425 (set (match_operand:SI 6 "gpc_reg_operand" "")
10426 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10427 (set (match_operand:SI 7 "gpc_reg_operand" "")
10428 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10429 (set (match_operand:SI 8 "gpc_reg_operand" "")
10430 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10431 (set (match_operand:SI 9 "gpc_reg_operand" "")
10432 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10433 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10434 "*
10435 { return rs6000_output_load_multiple (operands); }"
10436 [(set_attr "type" "load_ux")
10437 (set_attr "length" "32")])
10439 (define_insn "*ldmsi7"
10440 [(match_parallel 0 "load_multiple_operation"
10441 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10442 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10443 (set (match_operand:SI 3 "gpc_reg_operand" "")
10444 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10445 (set (match_operand:SI 4 "gpc_reg_operand" "")
10446 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10447 (set (match_operand:SI 5 "gpc_reg_operand" "")
10448 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10449 (set (match_operand:SI 6 "gpc_reg_operand" "")
10450 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10451 (set (match_operand:SI 7 "gpc_reg_operand" "")
10452 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10453 (set (match_operand:SI 8 "gpc_reg_operand" "")
10454 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10455 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10456 "*
10457 { return rs6000_output_load_multiple (operands); }"
10458 [(set_attr "type" "load_ux")
10459 (set_attr "length" "32")])
10461 (define_insn "*ldmsi6"
10462 [(match_parallel 0 "load_multiple_operation"
10463 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10464 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10465 (set (match_operand:SI 3 "gpc_reg_operand" "")
10466 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10467 (set (match_operand:SI 4 "gpc_reg_operand" "")
10468 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10469 (set (match_operand:SI 5 "gpc_reg_operand" "")
10470 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10471 (set (match_operand:SI 6 "gpc_reg_operand" "")
10472 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10473 (set (match_operand:SI 7 "gpc_reg_operand" "")
10474 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10475 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10476 "*
10477 { return rs6000_output_load_multiple (operands); }"
10478 [(set_attr "type" "load_ux")
10479 (set_attr "length" "32")])
10481 (define_insn "*ldmsi5"
10482 [(match_parallel 0 "load_multiple_operation"
10483 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10484 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10485 (set (match_operand:SI 3 "gpc_reg_operand" "")
10486 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10487 (set (match_operand:SI 4 "gpc_reg_operand" "")
10488 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10489 (set (match_operand:SI 5 "gpc_reg_operand" "")
10490 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10491 (set (match_operand:SI 6 "gpc_reg_operand" "")
10492 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10493 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10494 "*
10495 { return rs6000_output_load_multiple (operands); }"
10496 [(set_attr "type" "load_ux")
10497 (set_attr "length" "32")])
10499 (define_insn "*ldmsi4"
10500 [(match_parallel 0 "load_multiple_operation"
10501 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10502 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10503 (set (match_operand:SI 3 "gpc_reg_operand" "")
10504 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10505 (set (match_operand:SI 4 "gpc_reg_operand" "")
10506 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10507 (set (match_operand:SI 5 "gpc_reg_operand" "")
10508 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10509 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10510 "*
10511 { return rs6000_output_load_multiple (operands); }"
10512 [(set_attr "type" "load_ux")
10513 (set_attr "length" "32")])
10515 (define_insn "*ldmsi3"
10516 [(match_parallel 0 "load_multiple_operation"
10517 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10518 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10519 (set (match_operand:SI 3 "gpc_reg_operand" "")
10520 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10521 (set (match_operand:SI 4 "gpc_reg_operand" "")
10522 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10523 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10524 "*
10525 { return rs6000_output_load_multiple (operands); }"
10526 [(set_attr "type" "load_ux")
10527 (set_attr "length" "32")])
10529 (define_expand "store_multiple"
10530 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10531 (match_operand:SI 1 "" ""))
10532 (clobber (scratch:SI))
10533 (use (match_operand:SI 2 "" ""))])]
10534 "TARGET_STRING && !TARGET_POWERPC64"
10535 "
10536 {
10537 int regno;
10538 int count;
10539 rtx to;
10540 rtx op0;
10541 int i;
10543 /* Support only storing a constant number of fixed-point registers to
10544 memory and only bother with this if more than two; the machine
10545 doesn't support more than eight. */
10546 if (GET_CODE (operands[2]) != CONST_INT
10547 || INTVAL (operands[2]) <= 2
10548 || INTVAL (operands[2]) > 8
10549 || GET_CODE (operands[0]) != MEM
10550 || GET_CODE (operands[1]) != REG
10551 || REGNO (operands[1]) >= 32)
10552 FAIL;
10554 count = INTVAL (operands[2]);
10555 regno = REGNO (operands[1]);
10557 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10558 to = force_reg (SImode, XEXP (operands[0], 0));
10559 op0 = replace_equiv_address (operands[0], to);
10561 XVECEXP (operands[3], 0, 0)
10562 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10563 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10564 gen_rtx_SCRATCH (SImode));
10566 for (i = 1; i < count; i++)
10567 XVECEXP (operands[3], 0, i + 1)
10568 = gen_rtx_SET (VOIDmode,
10569 adjust_address_nv (op0, SImode, i * 4),
10570 gen_rtx_REG (SImode, regno + i));
10571 }")
10573 (define_insn "*stmsi8"
10574 [(match_parallel 0 "store_multiple_operation"
10575 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10576 (match_operand:SI 2 "gpc_reg_operand" "r"))
10577 (clobber (match_scratch:SI 3 "=X"))
10578 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10579 (match_operand:SI 4 "gpc_reg_operand" "r"))
10580 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10581 (match_operand:SI 5 "gpc_reg_operand" "r"))
10582 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10583 (match_operand:SI 6 "gpc_reg_operand" "r"))
10584 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10585 (match_operand:SI 7 "gpc_reg_operand" "r"))
10586 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10587 (match_operand:SI 8 "gpc_reg_operand" "r"))
10588 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10589 (match_operand:SI 9 "gpc_reg_operand" "r"))
10590 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10591 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10592 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10593 "{stsi|stswi} %2,%1,%O0"
10594 [(set_attr "type" "store_ux")
10595 (set_attr "cell_micro" "always")])
10597 (define_insn "*stmsi7"
10598 [(match_parallel 0 "store_multiple_operation"
10599 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10600 (match_operand:SI 2 "gpc_reg_operand" "r"))
10601 (clobber (match_scratch:SI 3 "=X"))
10602 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10603 (match_operand:SI 4 "gpc_reg_operand" "r"))
10604 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10605 (match_operand:SI 5 "gpc_reg_operand" "r"))
10606 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10607 (match_operand:SI 6 "gpc_reg_operand" "r"))
10608 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10609 (match_operand:SI 7 "gpc_reg_operand" "r"))
10610 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10611 (match_operand:SI 8 "gpc_reg_operand" "r"))
10612 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10613 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10614 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10615 "{stsi|stswi} %2,%1,%O0"
10616 [(set_attr "type" "store_ux")
10617 (set_attr "cell_micro" "always")])
10619 (define_insn "*stmsi6"
10620 [(match_parallel 0 "store_multiple_operation"
10621 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10622 (match_operand:SI 2 "gpc_reg_operand" "r"))
10623 (clobber (match_scratch:SI 3 "=X"))
10624 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10625 (match_operand:SI 4 "gpc_reg_operand" "r"))
10626 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10627 (match_operand:SI 5 "gpc_reg_operand" "r"))
10628 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10629 (match_operand:SI 6 "gpc_reg_operand" "r"))
10630 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10631 (match_operand:SI 7 "gpc_reg_operand" "r"))
10632 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10633 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10634 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10635 "{stsi|stswi} %2,%1,%O0"
10636 [(set_attr "type" "store_ux")
10637 (set_attr "cell_micro" "always")])
10639 (define_insn "*stmsi5"
10640 [(match_parallel 0 "store_multiple_operation"
10641 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10642 (match_operand:SI 2 "gpc_reg_operand" "r"))
10643 (clobber (match_scratch:SI 3 "=X"))
10644 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10645 (match_operand:SI 4 "gpc_reg_operand" "r"))
10646 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10647 (match_operand:SI 5 "gpc_reg_operand" "r"))
10648 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10649 (match_operand:SI 6 "gpc_reg_operand" "r"))
10650 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10651 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10652 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10653 "{stsi|stswi} %2,%1,%O0"
10654 [(set_attr "type" "store_ux")
10655 (set_attr "cell_micro" "always")])
10657 (define_insn "*stmsi4"
10658 [(match_parallel 0 "store_multiple_operation"
10659 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10660 (match_operand:SI 2 "gpc_reg_operand" "r"))
10661 (clobber (match_scratch:SI 3 "=X"))
10662 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10663 (match_operand:SI 4 "gpc_reg_operand" "r"))
10664 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10665 (match_operand:SI 5 "gpc_reg_operand" "r"))
10666 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10667 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10668 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10669 "{stsi|stswi} %2,%1,%O0"
10670 [(set_attr "type" "store_ux")
10671 (set_attr "cell_micro" "always")])
10673 (define_insn "*stmsi3"
10674 [(match_parallel 0 "store_multiple_operation"
10675 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10676 (match_operand:SI 2 "gpc_reg_operand" "r"))
10677 (clobber (match_scratch:SI 3 "=X"))
10678 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10679 (match_operand:SI 4 "gpc_reg_operand" "r"))
10680 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10681 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10682 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10683 "{stsi|stswi} %2,%1,%O0"
10684 [(set_attr "type" "store_ux")
10685 (set_attr "cell_micro" "always")])
10687 (define_insn "*stmsi8_power"
10688 [(match_parallel 0 "store_multiple_operation"
10689 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10690 (match_operand:SI 2 "gpc_reg_operand" "r"))
10691 (clobber (match_scratch:SI 3 "=q"))
10692 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10693 (match_operand:SI 4 "gpc_reg_operand" "r"))
10694 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10695 (match_operand:SI 5 "gpc_reg_operand" "r"))
10696 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10697 (match_operand:SI 6 "gpc_reg_operand" "r"))
10698 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10699 (match_operand:SI 7 "gpc_reg_operand" "r"))
10700 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10701 (match_operand:SI 8 "gpc_reg_operand" "r"))
10702 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10703 (match_operand:SI 9 "gpc_reg_operand" "r"))
10704 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10705 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10706 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10707 "{stsi|stswi} %2,%1,%O0"
10708 [(set_attr "type" "store_ux")
10709 (set_attr "cell_micro" "always")])
10711 (define_insn "*stmsi7_power"
10712 [(match_parallel 0 "store_multiple_operation"
10713 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10714 (match_operand:SI 2 "gpc_reg_operand" "r"))
10715 (clobber (match_scratch:SI 3 "=q"))
10716 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10717 (match_operand:SI 4 "gpc_reg_operand" "r"))
10718 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10719 (match_operand:SI 5 "gpc_reg_operand" "r"))
10720 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10721 (match_operand:SI 6 "gpc_reg_operand" "r"))
10722 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10723 (match_operand:SI 7 "gpc_reg_operand" "r"))
10724 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10725 (match_operand:SI 8 "gpc_reg_operand" "r"))
10726 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10727 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10728 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10729 "{stsi|stswi} %2,%1,%O0"
10730 [(set_attr "type" "store_ux")
10731 (set_attr "cell_micro" "always")])
10733 (define_insn "*stmsi6_power"
10734 [(match_parallel 0 "store_multiple_operation"
10735 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10736 (match_operand:SI 2 "gpc_reg_operand" "r"))
10737 (clobber (match_scratch:SI 3 "=q"))
10738 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10739 (match_operand:SI 4 "gpc_reg_operand" "r"))
10740 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10741 (match_operand:SI 5 "gpc_reg_operand" "r"))
10742 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10743 (match_operand:SI 6 "gpc_reg_operand" "r"))
10744 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10745 (match_operand:SI 7 "gpc_reg_operand" "r"))
10746 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10747 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10748 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10749 "{stsi|stswi} %2,%1,%O0"
10750 [(set_attr "type" "store_ux")
10751 (set_attr "cell_micro" "always")])
10753 (define_insn "*stmsi5_power"
10754 [(match_parallel 0 "store_multiple_operation"
10755 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10756 (match_operand:SI 2 "gpc_reg_operand" "r"))
10757 (clobber (match_scratch:SI 3 "=q"))
10758 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10759 (match_operand:SI 4 "gpc_reg_operand" "r"))
10760 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10761 (match_operand:SI 5 "gpc_reg_operand" "r"))
10762 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10763 (match_operand:SI 6 "gpc_reg_operand" "r"))
10764 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10765 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10766 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10767 "{stsi|stswi} %2,%1,%O0"
10768 [(set_attr "type" "store_ux")
10769 (set_attr "cell_micro" "always")])
10771 (define_insn "*stmsi4_power"
10772 [(match_parallel 0 "store_multiple_operation"
10773 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10774 (match_operand:SI 2 "gpc_reg_operand" "r"))
10775 (clobber (match_scratch:SI 3 "=q"))
10776 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10777 (match_operand:SI 4 "gpc_reg_operand" "r"))
10778 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10779 (match_operand:SI 5 "gpc_reg_operand" "r"))
10780 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10781 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10782 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10783 "{stsi|stswi} %2,%1,%O0"
10784 [(set_attr "type" "store_ux")
10785 (set_attr "cell_micro" "always")])
10787 (define_insn "*stmsi3_power"
10788 [(match_parallel 0 "store_multiple_operation"
10789 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10790 (match_operand:SI 2 "gpc_reg_operand" "r"))
10791 (clobber (match_scratch:SI 3 "=q"))
10792 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10793 (match_operand:SI 4 "gpc_reg_operand" "r"))
10794 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10795 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10796 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10797 "{stsi|stswi} %2,%1,%O0"
10798 [(set_attr "type" "store_ux")
10799 (set_attr "cell_micro" "always")])
10800 \f
10801 (define_expand "setmemsi"
10802 [(parallel [(set (match_operand:BLK 0 "" "")
10803 (match_operand 2 "const_int_operand" ""))
10804 (use (match_operand:SI 1 "" ""))
10805 (use (match_operand:SI 3 "" ""))])]
10806 ""
10807 "
10808 {
10809 /* If value to set is not zero, use the library routine. */
10810 if (operands[2] != const0_rtx)
10811 FAIL;
10813 if (expand_block_clear (operands))
10814 DONE;
10815 else
10816 FAIL;
10817 }")
10819 ;; String/block move insn.
10820 ;; Argument 0 is the destination
10821 ;; Argument 1 is the source
10822 ;; Argument 2 is the length
10823 ;; Argument 3 is the alignment
10825 (define_expand "movmemsi"
10826 [(parallel [(set (match_operand:BLK 0 "" "")
10827 (match_operand:BLK 1 "" ""))
10828 (use (match_operand:SI 2 "" ""))
10829 (use (match_operand:SI 3 "" ""))])]
10830 ""
10831 "
10832 {
10833 if (expand_block_move (operands))
10834 DONE;
10835 else
10836 FAIL;
10837 }")
10839 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10840 ;; register allocator doesn't have a clue about allocating 8 word registers.
10841 ;; rD/rS = r5 is preferred, efficient form.
10842 (define_expand "movmemsi_8reg"
10843 [(parallel [(set (match_operand 0 "" "")
10844 (match_operand 1 "" ""))
10845 (use (match_operand 2 "" ""))
10846 (use (match_operand 3 "" ""))
10847 (clobber (reg:SI 5))
10848 (clobber (reg:SI 6))
10849 (clobber (reg:SI 7))
10850 (clobber (reg:SI 8))
10851 (clobber (reg:SI 9))
10852 (clobber (reg:SI 10))
10853 (clobber (reg:SI 11))
10854 (clobber (reg:SI 12))
10855 (clobber (match_scratch:SI 4 ""))])]
10856 "TARGET_STRING"
10857 "")
10859 (define_insn ""
10860 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10861 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10862 (use (match_operand:SI 2 "immediate_operand" "i"))
10863 (use (match_operand:SI 3 "immediate_operand" "i"))
10864 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10865 (clobber (reg:SI 6))
10866 (clobber (reg:SI 7))
10867 (clobber (reg:SI 8))
10868 (clobber (reg:SI 9))
10869 (clobber (reg:SI 10))
10870 (clobber (reg:SI 11))
10871 (clobber (reg:SI 12))
10872 (clobber (match_scratch:SI 5 "=q"))]
10873 "TARGET_STRING && TARGET_POWER
10874 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10875 || INTVAL (operands[2]) == 0)
10876 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10877 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10878 && REGNO (operands[4]) == 5"
10879 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10880 [(set_attr "type" "store_ux")
10881 (set_attr "cell_micro" "always")
10882 (set_attr "length" "8")])
10884 (define_insn ""
10885 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10886 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10887 (use (match_operand:SI 2 "immediate_operand" "i"))
10888 (use (match_operand:SI 3 "immediate_operand" "i"))
10889 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10890 (clobber (reg:SI 6))
10891 (clobber (reg:SI 7))
10892 (clobber (reg:SI 8))
10893 (clobber (reg:SI 9))
10894 (clobber (reg:SI 10))
10895 (clobber (reg:SI 11))
10896 (clobber (reg:SI 12))
10897 (clobber (match_scratch:SI 5 "=X"))]
10898 "TARGET_STRING && ! TARGET_POWER
10899 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10900 || INTVAL (operands[2]) == 0)
10901 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10902 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10903 && REGNO (operands[4]) == 5"
10904 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10905 [(set_attr "type" "store_ux")
10906 (set_attr "cell_micro" "always")
10907 (set_attr "length" "8")])
10909 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10910 ;; register allocator doesn't have a clue about allocating 6 word registers.
10911 ;; rD/rS = r5 is preferred, efficient form.
10912 (define_expand "movmemsi_6reg"
10913 [(parallel [(set (match_operand 0 "" "")
10914 (match_operand 1 "" ""))
10915 (use (match_operand 2 "" ""))
10916 (use (match_operand 3 "" ""))
10917 (clobber (reg:SI 5))
10918 (clobber (reg:SI 6))
10919 (clobber (reg:SI 7))
10920 (clobber (reg:SI 8))
10921 (clobber (reg:SI 9))
10922 (clobber (reg:SI 10))
10923 (clobber (match_scratch:SI 4 ""))])]
10924 "TARGET_STRING"
10925 "")
10927 (define_insn ""
10928 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10929 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10930 (use (match_operand:SI 2 "immediate_operand" "i"))
10931 (use (match_operand:SI 3 "immediate_operand" "i"))
10932 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10933 (clobber (reg:SI 6))
10934 (clobber (reg:SI 7))
10935 (clobber (reg:SI 8))
10936 (clobber (reg:SI 9))
10937 (clobber (reg:SI 10))
10938 (clobber (match_scratch:SI 5 "=q"))]
10939 "TARGET_STRING && TARGET_POWER
10940 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10941 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10942 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10943 && REGNO (operands[4]) == 5"
10944 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10945 [(set_attr "type" "store_ux")
10946 (set_attr "cell_micro" "always")
10947 (set_attr "length" "8")])
10949 (define_insn ""
10950 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10951 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10952 (use (match_operand:SI 2 "immediate_operand" "i"))
10953 (use (match_operand:SI 3 "immediate_operand" "i"))
10954 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10955 (clobber (reg:SI 6))
10956 (clobber (reg:SI 7))
10957 (clobber (reg:SI 8))
10958 (clobber (reg:SI 9))
10959 (clobber (reg:SI 10))
10960 (clobber (match_scratch:SI 5 "=X"))]
10961 "TARGET_STRING && ! TARGET_POWER
10962 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10963 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10964 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10965 && REGNO (operands[4]) == 5"
10966 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10967 [(set_attr "type" "store_ux")
10968 (set_attr "cell_micro" "always")
10969 (set_attr "length" "8")])
10971 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10972 ;; problems with TImode.
10973 ;; rD/rS = r5 is preferred, efficient form.
10974 (define_expand "movmemsi_4reg"
10975 [(parallel [(set (match_operand 0 "" "")
10976 (match_operand 1 "" ""))
10977 (use (match_operand 2 "" ""))
10978 (use (match_operand 3 "" ""))
10979 (clobber (reg:SI 5))
10980 (clobber (reg:SI 6))
10981 (clobber (reg:SI 7))
10982 (clobber (reg:SI 8))
10983 (clobber (match_scratch:SI 4 ""))])]
10984 "TARGET_STRING"
10985 "")
10987 (define_insn ""
10988 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10989 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10990 (use (match_operand:SI 2 "immediate_operand" "i"))
10991 (use (match_operand:SI 3 "immediate_operand" "i"))
10992 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10993 (clobber (reg:SI 6))
10994 (clobber (reg:SI 7))
10995 (clobber (reg:SI 8))
10996 (clobber (match_scratch:SI 5 "=q"))]
10997 "TARGET_STRING && TARGET_POWER
10998 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10999 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
11000 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
11001 && REGNO (operands[4]) == 5"
11002 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11003 [(set_attr "type" "store_ux")
11004 (set_attr "cell_micro" "always")
11005 (set_attr "length" "8")])
11007 (define_insn ""
11008 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11009 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11010 (use (match_operand:SI 2 "immediate_operand" "i"))
11011 (use (match_operand:SI 3 "immediate_operand" "i"))
11012 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
11013 (clobber (reg:SI 6))
11014 (clobber (reg:SI 7))
11015 (clobber (reg:SI 8))
11016 (clobber (match_scratch:SI 5 "=X"))]
11017 "TARGET_STRING && ! TARGET_POWER
11018 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
11019 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
11020 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
11021 && REGNO (operands[4]) == 5"
11022 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11023 [(set_attr "type" "store_ux")
11024 (set_attr "cell_micro" "always")
11025 (set_attr "length" "8")])
11027 ;; Move up to 8 bytes at a time.
11028 (define_expand "movmemsi_2reg"
11029 [(parallel [(set (match_operand 0 "" "")
11030 (match_operand 1 "" ""))
11031 (use (match_operand 2 "" ""))
11032 (use (match_operand 3 "" ""))
11033 (clobber (match_scratch:DI 4 ""))
11034 (clobber (match_scratch:SI 5 ""))])]
11035 "TARGET_STRING && ! TARGET_POWERPC64"
11036 "")
11038 (define_insn ""
11039 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11040 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11041 (use (match_operand:SI 2 "immediate_operand" "i"))
11042 (use (match_operand:SI 3 "immediate_operand" "i"))
11043 (clobber (match_scratch:DI 4 "=&r"))
11044 (clobber (match_scratch:SI 5 "=q"))]
11045 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
11046 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11047 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11048 [(set_attr "type" "store_ux")
11049 (set_attr "cell_micro" "always")
11050 (set_attr "length" "8")])
11052 (define_insn ""
11053 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11054 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11055 (use (match_operand:SI 2 "immediate_operand" "i"))
11056 (use (match_operand:SI 3 "immediate_operand" "i"))
11057 (clobber (match_scratch:DI 4 "=&r"))
11058 (clobber (match_scratch:SI 5 "=X"))]
11059 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
11060 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11061 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11062 [(set_attr "type" "store_ux")
11063 (set_attr "cell_micro" "always")
11064 (set_attr "length" "8")])
11066 ;; Move up to 4 bytes at a time.
11067 (define_expand "movmemsi_1reg"
11068 [(parallel [(set (match_operand 0 "" "")
11069 (match_operand 1 "" ""))
11070 (use (match_operand 2 "" ""))
11071 (use (match_operand 3 "" ""))
11072 (clobber (match_scratch:SI 4 ""))
11073 (clobber (match_scratch:SI 5 ""))])]
11074 "TARGET_STRING"
11075 "")
11077 (define_insn ""
11078 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11079 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11080 (use (match_operand:SI 2 "immediate_operand" "i"))
11081 (use (match_operand:SI 3 "immediate_operand" "i"))
11082 (clobber (match_scratch:SI 4 "=&r"))
11083 (clobber (match_scratch:SI 5 "=q"))]
11084 "TARGET_STRING && TARGET_POWER
11085 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11086 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11087 [(set_attr "type" "store_ux")
11088 (set_attr "cell_micro" "always")
11089 (set_attr "length" "8")])
11091 (define_insn ""
11092 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11093 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11094 (use (match_operand:SI 2 "immediate_operand" "i"))
11095 (use (match_operand:SI 3 "immediate_operand" "i"))
11096 (clobber (match_scratch:SI 4 "=&r"))
11097 (clobber (match_scratch:SI 5 "=X"))]
11098 "TARGET_STRING && ! TARGET_POWER
11099 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11100 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11101 [(set_attr "type" "store_ux")
11102 (set_attr "cell_micro" "always")
11103 (set_attr "length" "8")])
11104 \f
11105 ;; Define insns that do load or store with update. Some of these we can
11106 ;; get by using pre-decrement or pre-increment, but the hardware can also
11107 ;; do cases where the increment is not the size of the object.
11108 ;;
11109 ;; In all these cases, we use operands 0 and 1 for the register being
11110 ;; incremented because those are the operands that local-alloc will
11111 ;; tie and these are the pair most likely to be tieable (and the ones
11112 ;; that will benefit the most).
11114 (define_insn "*movdi_update1"
11115 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11116 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11117 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11118 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11119 (plus:DI (match_dup 1) (match_dup 2)))]
11120 "TARGET_POWERPC64 && TARGET_UPDATE
11121 && (!avoiding_indexed_address_p (DImode)
11122 || !gpc_reg_operand (operands[2], DImode))"
11123 "@
11124 ldux %3,%0,%2
11125 ldu %3,%2(%0)"
11126 [(set_attr "type" "load_ux,load_u")])
11128 (define_insn "movdi_<mode>_update"
11129 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11130 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11131 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11132 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11133 (plus:P (match_dup 1) (match_dup 2)))]
11134 "TARGET_POWERPC64 && TARGET_UPDATE
11135 && (!avoiding_indexed_address_p (Pmode)
11136 || !gpc_reg_operand (operands[2], Pmode)
11137 || (REG_P (operands[0])
11138 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11139 "@
11140 stdux %3,%0,%2
11141 stdu %3,%2(%0)"
11142 [(set_attr "type" "store_ux,store_u")])
11144 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11145 ;; needed for stack allocation, even if the user passes -mno-update.
11146 (define_insn "movdi_<mode>_update_stack"
11147 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11148 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11149 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11150 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11151 (plus:P (match_dup 1) (match_dup 2)))]
11152 "TARGET_POWERPC64"
11153 "@
11154 stdux %3,%0,%2
11155 stdu %3,%2(%0)"
11156 [(set_attr "type" "store_ux,store_u")])
11158 (define_insn "*movsi_update1"
11159 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11160 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11161 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11162 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11163 (plus:SI (match_dup 1) (match_dup 2)))]
11164 "TARGET_UPDATE
11165 && (!avoiding_indexed_address_p (SImode)
11166 || !gpc_reg_operand (operands[2], SImode))"
11167 "@
11168 {lux|lwzux} %3,%0,%2
11169 {lu|lwzu} %3,%2(%0)"
11170 [(set_attr "type" "load_ux,load_u")])
11172 (define_insn "*movsi_update2"
11173 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11174 (sign_extend:DI
11175 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11176 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11177 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11178 (plus:DI (match_dup 1) (match_dup 2)))]
11179 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11180 && !avoiding_indexed_address_p (DImode)"
11181 "lwaux %3,%0,%2"
11182 [(set_attr "type" "load_ext_ux")])
11184 (define_insn "movsi_update"
11185 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11186 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11187 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11188 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11189 (plus:SI (match_dup 1) (match_dup 2)))]
11190 "TARGET_UPDATE
11191 && (!avoiding_indexed_address_p (SImode)
11192 || !gpc_reg_operand (operands[2], SImode)
11193 || (REG_P (operands[0])
11194 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11195 "@
11196 {stux|stwux} %3,%0,%2
11197 {stu|stwu} %3,%2(%0)"
11198 [(set_attr "type" "store_ux,store_u")])
11200 ;; This is an unconditional pattern; needed for stack allocation, even
11201 ;; if the user passes -mno-update.
11202 (define_insn "movsi_update_stack"
11203 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11204 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11205 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11206 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11207 (plus:SI (match_dup 1) (match_dup 2)))]
11208 ""
11209 "@
11210 {stux|stwux} %3,%0,%2
11211 {stu|stwu} %3,%2(%0)"
11212 [(set_attr "type" "store_ux,store_u")])
11214 (define_insn "*movhi_update1"
11215 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11216 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11217 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11218 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11219 (plus:SI (match_dup 1) (match_dup 2)))]
11220 "TARGET_UPDATE
11221 && (!avoiding_indexed_address_p (SImode)
11222 || !gpc_reg_operand (operands[2], SImode))"
11223 "@
11224 lhzux %3,%0,%2
11225 lhzu %3,%2(%0)"
11226 [(set_attr "type" "load_ux,load_u")])
11228 (define_insn "*movhi_update2"
11229 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11230 (zero_extend:SI
11231 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11232 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11233 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11234 (plus:SI (match_dup 1) (match_dup 2)))]
11235 "TARGET_UPDATE
11236 && (!avoiding_indexed_address_p (SImode)
11237 || !gpc_reg_operand (operands[2], SImode))"
11238 "@
11239 lhzux %3,%0,%2
11240 lhzu %3,%2(%0)"
11241 [(set_attr "type" "load_ux,load_u")])
11243 (define_insn "*movhi_update3"
11244 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11245 (sign_extend:SI
11246 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11247 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11248 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11249 (plus:SI (match_dup 1) (match_dup 2)))]
11250 "TARGET_UPDATE && rs6000_gen_cell_microcode
11251 && (!avoiding_indexed_address_p (SImode)
11252 || !gpc_reg_operand (operands[2], SImode))"
11253 "@
11254 lhaux %3,%0,%2
11255 lhau %3,%2(%0)"
11256 [(set_attr "type" "load_ext_ux,load_ext_u")])
11258 (define_insn "*movhi_update4"
11259 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11260 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11261 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11262 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11263 (plus:SI (match_dup 1) (match_dup 2)))]
11264 "TARGET_UPDATE
11265 && (!avoiding_indexed_address_p (SImode)
11266 || !gpc_reg_operand (operands[2], SImode))"
11267 "@
11268 sthux %3,%0,%2
11269 sthu %3,%2(%0)"
11270 [(set_attr "type" "store_ux,store_u")])
11272 (define_insn "*movqi_update1"
11273 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11274 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11275 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11276 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11277 (plus:SI (match_dup 1) (match_dup 2)))]
11278 "TARGET_UPDATE
11279 && (!avoiding_indexed_address_p (SImode)
11280 || !gpc_reg_operand (operands[2], SImode))"
11281 "@
11282 lbzux %3,%0,%2
11283 lbzu %3,%2(%0)"
11284 [(set_attr "type" "load_ux,load_u")])
11286 (define_insn "*movqi_update2"
11287 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11288 (zero_extend:SI
11289 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11290 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11291 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11292 (plus:SI (match_dup 1) (match_dup 2)))]
11293 "TARGET_UPDATE
11294 && (!avoiding_indexed_address_p (SImode)
11295 || !gpc_reg_operand (operands[2], SImode))"
11296 "@
11297 lbzux %3,%0,%2
11298 lbzu %3,%2(%0)"
11299 [(set_attr "type" "load_ux,load_u")])
11301 (define_insn "*movqi_update3"
11302 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11303 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11304 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11305 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11306 (plus:SI (match_dup 1) (match_dup 2)))]
11307 "TARGET_UPDATE
11308 && (!avoiding_indexed_address_p (SImode)
11309 || !gpc_reg_operand (operands[2], SImode))"
11310 "@
11311 stbux %3,%0,%2
11312 stbu %3,%2(%0)"
11313 [(set_attr "type" "store_ux,store_u")])
11315 (define_insn "*movsf_update1"
11316 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11317 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11318 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11319 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11320 (plus:SI (match_dup 1) (match_dup 2)))]
11321 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11322 && (!avoiding_indexed_address_p (SImode)
11323 || !gpc_reg_operand (operands[2], SImode))"
11324 "@
11325 lfsux %3,%0,%2
11326 lfsu %3,%2(%0)"
11327 [(set_attr "type" "fpload_ux,fpload_u")])
11329 (define_insn "*movsf_update2"
11330 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11331 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11332 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11333 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11334 (plus:SI (match_dup 1) (match_dup 2)))]
11335 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11336 && (!avoiding_indexed_address_p (SImode)
11337 || !gpc_reg_operand (operands[2], SImode))"
11338 "@
11339 stfsux %3,%0,%2
11340 stfsu %3,%2(%0)"
11341 [(set_attr "type" "fpstore_ux,fpstore_u")])
11343 (define_insn "*movsf_update3"
11344 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11345 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11346 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11347 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11348 (plus:SI (match_dup 1) (match_dup 2)))]
11349 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11350 && (!avoiding_indexed_address_p (SImode)
11351 || !gpc_reg_operand (operands[2], SImode))"
11352 "@
11353 {lux|lwzux} %3,%0,%2
11354 {lu|lwzu} %3,%2(%0)"
11355 [(set_attr "type" "load_ux,load_u")])
11357 (define_insn "*movsf_update4"
11358 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11359 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11360 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11361 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11362 (plus:SI (match_dup 1) (match_dup 2)))]
11363 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11364 && (!avoiding_indexed_address_p (SImode)
11365 || !gpc_reg_operand (operands[2], SImode))"
11366 "@
11367 {stux|stwux} %3,%0,%2
11368 {stu|stwu} %3,%2(%0)"
11369 [(set_attr "type" "store_ux,store_u")])
11371 (define_insn "*movdf_update1"
11372 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11373 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11374 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11375 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11376 (plus:SI (match_dup 1) (match_dup 2)))]
11377 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11378 && (!avoiding_indexed_address_p (SImode)
11379 || !gpc_reg_operand (operands[2], SImode))"
11380 "@
11381 lfdux %3,%0,%2
11382 lfdu %3,%2(%0)"
11383 [(set_attr "type" "fpload_ux,fpload_u")])
11385 (define_insn "*movdf_update2"
11386 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11387 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11388 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11389 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11390 (plus:SI (match_dup 1) (match_dup 2)))]
11391 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11392 && (!avoiding_indexed_address_p (SImode)
11393 || !gpc_reg_operand (operands[2], SImode))"
11394 "@
11395 stfdux %3,%0,%2
11396 stfdu %3,%2(%0)"
11397 [(set_attr "type" "fpstore_ux,fpstore_u")])
11399 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
11401 (define_insn "*lfq_power2"
11402 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
11403 (match_operand:V2DF 1 "memory_operand" ""))]
11404 "TARGET_POWER2
11405 && TARGET_HARD_FLOAT && TARGET_FPRS"
11406 "lfq%U1%X1 %0,%1")
11408 (define_peephole2
11409 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11410 (match_operand:DF 1 "memory_operand" ""))
11411 (set (match_operand:DF 2 "gpc_reg_operand" "")
11412 (match_operand:DF 3 "memory_operand" ""))]
11413 "TARGET_POWER2
11414 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11415 && registers_ok_for_quad_peep (operands[0], operands[2])
11416 && mems_ok_for_quad_peep (operands[1], operands[3])"
11417 [(set (match_dup 0)
11418 (match_dup 1))]
11419 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11420 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11422 (define_insn "*stfq_power2"
11423 [(set (match_operand:V2DF 0 "memory_operand" "")
11424 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11425 "TARGET_POWER2
11426 && TARGET_HARD_FLOAT && TARGET_FPRS"
11427 "stfq%U0%X0 %1,%0")
11430 (define_peephole2
11431 [(set (match_operand:DF 0 "memory_operand" "")
11432 (match_operand:DF 1 "gpc_reg_operand" ""))
11433 (set (match_operand:DF 2 "memory_operand" "")
11434 (match_operand:DF 3 "gpc_reg_operand" ""))]
11435 "TARGET_POWER2
11436 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11437 && registers_ok_for_quad_peep (operands[1], operands[3])
11438 && mems_ok_for_quad_peep (operands[0], operands[2])"
11439 [(set (match_dup 0)
11440 (match_dup 1))]
11441 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11442 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11444 ;; After inserting conditional returns we can sometimes have
11445 ;; unnecessary register moves. Unfortunately we cannot have a
11446 ;; modeless peephole here, because some single SImode sets have early
11447 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11448 ;; sequences, using get_attr_length here will smash the operands
11449 ;; array. Neither is there an early_cobbler_p predicate.
11450 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11451 (define_peephole2
11452 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11453 (match_operand:DF 1 "any_operand" ""))
11454 (set (match_operand:DF 2 "gpc_reg_operand" "")
11455 (match_dup 0))]
11456 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11457 && peep2_reg_dead_p (2, operands[0])"
11458 [(set (match_dup 2) (match_dup 1))])
11460 (define_peephole2
11461 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11462 (match_operand:SF 1 "any_operand" ""))
11463 (set (match_operand:SF 2 "gpc_reg_operand" "")
11464 (match_dup 0))]
11465 "peep2_reg_dead_p (2, operands[0])"
11466 [(set (match_dup 2) (match_dup 1))])
11468 \f
11469 ;; TLS support.
11471 ;; Mode attributes for different ABIs.
11472 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11473 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11474 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11475 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11477 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11478 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11479 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11480 (match_operand 4 "" "g")))
11481 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11482 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11483 UNSPEC_TLSGD)
11484 (clobber (reg:SI LR_REGNO))]
11485 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11486 {
11487 if (TARGET_CMODEL != CMODEL_SMALL)
11488 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11489 else
11490 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11491 }
11492 "&& TARGET_TLS_MARKERS"
11493 [(set (match_dup 0)
11494 (unspec:TLSmode [(match_dup 1)
11495 (match_dup 2)]
11496 UNSPEC_TLSGD))
11497 (parallel [(set (match_dup 0)
11498 (call (mem:TLSmode (match_dup 3))
11499 (match_dup 4)))
11500 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11501 (clobber (reg:SI LR_REGNO))])]
11502 ""
11503 [(set_attr "type" "two")
11504 (set (attr "length")
11505 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11506 (const_int 16)
11507 (const_int 12)))])
11509 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11510 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11511 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11512 (match_operand 4 "" "g")))
11513 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11514 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11515 UNSPEC_TLSGD)
11516 (clobber (reg:SI LR_REGNO))]
11517 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11518 {
11519 if (flag_pic)
11520 {
11521 if (TARGET_SECURE_PLT && flag_pic == 2)
11522 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11523 else
11524 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11525 }
11526 else
11527 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11528 }
11529 "&& TARGET_TLS_MARKERS"
11530 [(set (match_dup 0)
11531 (unspec:TLSmode [(match_dup 1)
11532 (match_dup 2)]
11533 UNSPEC_TLSGD))
11534 (parallel [(set (match_dup 0)
11535 (call (mem:TLSmode (match_dup 3))
11536 (match_dup 4)))
11537 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11538 (clobber (reg:SI LR_REGNO))])]
11539 ""
11540 [(set_attr "type" "two")
11541 (set_attr "length" "8")])
11543 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11544 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11545 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11546 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11547 UNSPEC_TLSGD))]
11548 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11549 "addi %0,%1,%2@got@tlsgd"
11550 "&& TARGET_CMODEL != CMODEL_SMALL"
11551 [(set (match_dup 3)
11552 (const:TLSmode
11553 (plus:TLSmode (match_dup 1)
11554 (high:TLSmode
11555 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))))
11556 (set (match_dup 0)
11557 (lo_sum:TLSmode (match_dup 3)
11558 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11559 "
11560 {
11561 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11562 }"
11563 [(set (attr "length")
11564 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11565 (const_int 8)
11566 (const_int 4)))])
11568 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11569 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11570 (const:TLSmode
11571 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11572 (high:TLSmode
11573 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11574 UNSPEC_TLSGD)))))]
11575 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11576 "addis %0,%1,%2@got@tlsgd@ha"
11577 [(set_attr "length" "4")])
11579 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11580 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11581 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11582 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11583 UNSPEC_TLSGD)))]
11584 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11585 "addi %0,%1,%2@got@tlsgd@l"
11586 [(set_attr "length" "4")])
11588 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11589 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11590 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11591 (match_operand 2 "" "g")))
11592 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11593 UNSPEC_TLSGD)
11594 (clobber (reg:SI LR_REGNO))]
11595 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11596 "bl %z1(%3@tlsgd)\;%."
11597 [(set_attr "type" "branch")
11598 (set_attr "length" "8")])
11600 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11601 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11602 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11603 (match_operand 2 "" "g")))
11604 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11605 UNSPEC_TLSGD)
11606 (clobber (reg:SI LR_REGNO))]
11607 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11608 {
11609 if (flag_pic)
11610 {
11611 if (TARGET_SECURE_PLT && flag_pic == 2)
11612 return "bl %z1+32768(%3@tlsgd)@plt";
11613 return "bl %z1(%3@tlsgd)@plt";
11614 }
11615 return "bl %z1(%3@tlsgd)";
11616 }
11617 [(set_attr "type" "branch")
11618 (set_attr "length" "4")])
11620 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11621 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11622 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11623 (match_operand 3 "" "g")))
11624 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11625 UNSPEC_TLSLD)
11626 (clobber (reg:SI LR_REGNO))]
11627 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11628 {
11629 if (TARGET_CMODEL != CMODEL_SMALL)
11630 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11631 else
11632 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11633 }
11634 "&& TARGET_TLS_MARKERS"
11635 [(set (match_dup 0)
11636 (unspec:TLSmode [(match_dup 1)]
11637 UNSPEC_TLSLD))
11638 (parallel [(set (match_dup 0)
11639 (call (mem:TLSmode (match_dup 2))
11640 (match_dup 3)))
11641 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11642 (clobber (reg:SI LR_REGNO))])]
11643 ""
11644 [(set_attr "type" "two")
11645 (set (attr "length")
11646 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11647 (const_int 16)
11648 (const_int 12)))])
11650 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11651 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11652 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11653 (match_operand 3 "" "g")))
11654 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11655 UNSPEC_TLSLD)
11656 (clobber (reg:SI LR_REGNO))]
11657 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11658 {
11659 if (flag_pic)
11660 {
11661 if (TARGET_SECURE_PLT && flag_pic == 2)
11662 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11663 else
11664 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11665 }
11666 else
11667 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11668 }
11669 "&& TARGET_TLS_MARKERS"
11670 [(set (match_dup 0)
11671 (unspec:TLSmode [(match_dup 1)]
11672 UNSPEC_TLSLD))
11673 (parallel [(set (match_dup 0)
11674 (call (mem:TLSmode (match_dup 2))
11675 (match_dup 3)))
11676 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11677 (clobber (reg:SI LR_REGNO))])]
11678 ""
11679 [(set_attr "length" "8")])
11681 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11682 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11683 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11684 UNSPEC_TLSLD))]
11685 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11686 "addi %0,%1,%&@got@tlsld"
11687 "&& TARGET_CMODEL != CMODEL_SMALL"
11688 [(set (match_dup 2)
11689 (const:TLSmode
11690 (plus:TLSmode (match_dup 1)
11691 (high:TLSmode
11692 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))))
11693 (set (match_dup 0)
11694 (lo_sum:TLSmode (match_dup 2)
11695 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11696 "
11697 {
11698 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11699 }"
11700 [(set (attr "length")
11701 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11702 (const_int 8)
11703 (const_int 4)))])
11705 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11706 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11707 (const:TLSmode
11708 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11709 (high:TLSmode
11710 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))))]
11711 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11712 "addis %0,%1,%&@got@tlsld@ha"
11713 [(set_attr "length" "4")])
11715 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11716 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11717 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11718 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11719 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11720 "addi %0,%1,%&@got@tlsld@l"
11721 [(set_attr "length" "4")])
11723 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11724 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11725 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11726 (match_operand 2 "" "g")))
11727 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11728 (clobber (reg:SI LR_REGNO))]
11729 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11730 "bl %z1(%&@tlsld)\;%."
11731 [(set_attr "type" "branch")
11732 (set_attr "length" "8")])
11734 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11735 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11736 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11737 (match_operand 2 "" "g")))
11738 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11739 (clobber (reg:SI LR_REGNO))]
11740 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11741 {
11742 if (flag_pic)
11743 {
11744 if (TARGET_SECURE_PLT && flag_pic == 2)
11745 return "bl %z1+32768(%&@tlsld)@plt";
11746 return "bl %z1(%&@tlsld)@plt";
11747 }
11748 return "bl %z1(%&@tlsld)";
11749 }
11750 [(set_attr "type" "branch")
11751 (set_attr "length" "4")])
11753 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11754 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11755 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11756 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11757 UNSPEC_TLSDTPREL))]
11758 "HAVE_AS_TLS"
11759 "addi %0,%1,%2@dtprel")
11761 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11762 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11763 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11764 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11765 UNSPEC_TLSDTPRELHA))]
11766 "HAVE_AS_TLS"
11767 "addis %0,%1,%2@dtprel@ha")
11769 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11770 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11771 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11772 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11773 UNSPEC_TLSDTPRELLO))]
11774 "HAVE_AS_TLS"
11775 "addi %0,%1,%2@dtprel@l")
11777 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11778 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11779 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11780 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11781 UNSPEC_TLSGOTDTPREL))]
11782 "HAVE_AS_TLS"
11783 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11784 "&& TARGET_CMODEL != CMODEL_SMALL"
11785 [(set (match_dup 3)
11786 (const:TLSmode
11787 (plus:TLSmode (match_dup 1)
11788 (high:TLSmode
11789 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))))
11790 (set (match_dup 0)
11791 (lo_sum:TLSmode (match_dup 3)
11792 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11793 "
11794 {
11795 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11796 }"
11797 [(set (attr "length")
11798 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11799 (const_int 8)
11800 (const_int 4)))])
11802 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11803 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11804 (const:TLSmode
11805 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11806 (high:TLSmode
11807 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11808 UNSPEC_TLSGOTDTPREL)))))]
11809 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11810 "addis %0,%1,%2@got@dtprel@ha"
11811 [(set_attr "length" "4")])
11813 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11814 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11815 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11816 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11817 UNSPEC_TLSGOTDTPREL)))]
11818 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11819 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11820 [(set_attr "length" "4")])
11822 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11823 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11824 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11825 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11826 UNSPEC_TLSTPREL))]
11827 "HAVE_AS_TLS"
11828 "addi %0,%1,%2@tprel")
11830 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11831 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11832 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11833 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11834 UNSPEC_TLSTPRELHA))]
11835 "HAVE_AS_TLS"
11836 "addis %0,%1,%2@tprel@ha")
11838 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11839 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11840 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11841 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11842 UNSPEC_TLSTPRELLO))]
11843 "HAVE_AS_TLS"
11844 "addi %0,%1,%2@tprel@l")
11846 ;; "b" output constraint here and on tls_tls input to support linker tls
11847 ;; optimization. The linker may edit the instructions emitted by a
11848 ;; tls_got_tprel/tls_tls pair to addis,addi.
11849 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11850 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11851 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11852 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11853 UNSPEC_TLSGOTTPREL))]
11854 "HAVE_AS_TLS"
11855 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11856 "&& TARGET_CMODEL != CMODEL_SMALL"
11857 [(set (match_dup 3)
11858 (const:TLSmode
11859 (plus:TLSmode (match_dup 1)
11860 (high:TLSmode
11861 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))))
11862 (set (match_dup 0)
11863 (lo_sum:TLSmode (match_dup 3)
11864 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11865 "
11866 {
11867 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11868 }"
11869 [(set (attr "length")
11870 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11871 (const_int 8)
11872 (const_int 4)))])
11874 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11875 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11876 (const:TLSmode
11877 (plus:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11878 (high:TLSmode
11879 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11880 UNSPEC_TLSGOTTPREL)))))]
11881 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11882 "addis %0,%1,%2@got@tprel@ha"
11883 [(set_attr "length" "4")])
11885 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11886 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11887 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11888 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11889 UNSPEC_TLSGOTTPREL)))]
11890 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11891 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11892 [(set_attr "length" "4")])
11894 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11895 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11896 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11897 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11898 UNSPEC_TLSTLS))]
11899 "HAVE_AS_TLS"
11900 "add %0,%1,%2@tls")
11901 \f
11902 ;; Next come insns related to the calling sequence.
11903 ;;
11904 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11905 ;; We move the back-chain and decrement the stack pointer.
11907 (define_expand "allocate_stack"
11908 [(set (match_operand 0 "gpc_reg_operand" "")
11909 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11910 (set (reg 1)
11911 (minus (reg 1) (match_dup 1)))]
11912 ""
11913 "
11914 { rtx chain = gen_reg_rtx (Pmode);
11915 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11916 rtx neg_op0;
11917 rtx insn, par, set, mem;
11919 emit_move_insn (chain, stack_bot);
11921 /* Check stack bounds if necessary. */
11922 if (crtl->limit_stack)
11923 {
11924 rtx available;
11925 available = expand_binop (Pmode, sub_optab,
11926 stack_pointer_rtx, stack_limit_rtx,
11927 NULL_RTX, 1, OPTAB_WIDEN);
11928 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11929 }
11931 if (GET_CODE (operands[1]) != CONST_INT
11932 || INTVAL (operands[1]) < -32767
11933 || INTVAL (operands[1]) > 32768)
11934 {
11935 neg_op0 = gen_reg_rtx (Pmode);
11936 if (TARGET_32BIT)
11937 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11938 else
11939 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11940 }
11941 else
11942 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11944 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11945 : gen_movdi_di_update_stack))
11946 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11947 chain));
11948 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11949 it now and set the alias set/attributes. The above gen_*_update
11950 calls will generate a PARALLEL with the MEM set being the first
11951 operation. */
11952 par = PATTERN (insn);
11953 gcc_assert (GET_CODE (par) == PARALLEL);
11954 set = XVECEXP (par, 0, 0);
11955 gcc_assert (GET_CODE (set) == SET);
11956 mem = SET_DEST (set);
11957 gcc_assert (MEM_P (mem));
11958 MEM_NOTRAP_P (mem) = 1;
11959 set_mem_alias_set (mem, get_frame_alias_set ());
11961 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11962 DONE;
11963 }")
11965 ;; These patterns say how to save and restore the stack pointer. We need not
11966 ;; save the stack pointer at function level since we are careful to
11967 ;; preserve the backchain. At block level, we have to restore the backchain
11968 ;; when we restore the stack pointer.
11969 ;;
11970 ;; For nonlocal gotos, we must save both the stack pointer and its
11971 ;; backchain and restore both. Note that in the nonlocal case, the
11972 ;; save area is a memory location.
11974 (define_expand "save_stack_function"
11975 [(match_operand 0 "any_operand" "")
11976 (match_operand 1 "any_operand" "")]
11977 ""
11978 "DONE;")
11980 (define_expand "restore_stack_function"
11981 [(match_operand 0 "any_operand" "")
11982 (match_operand 1 "any_operand" "")]
11983 ""
11984 "DONE;")
11986 ;; Adjust stack pointer (op0) to a new value (op1).
11987 ;; First copy old stack backchain to new location, and ensure that the
11988 ;; scheduler won't reorder the sp assignment before the backchain write.
11989 (define_expand "restore_stack_block"
11990 [(set (match_dup 2) (match_dup 3))
11991 (set (match_dup 4) (match_dup 2))
11992 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11993 (set (match_operand 0 "register_operand" "")
11994 (match_operand 1 "register_operand" ""))]
11995 ""
11996 "
11997 {
11998 operands[1] = force_reg (Pmode, operands[1]);
11999 operands[2] = gen_reg_rtx (Pmode);
12000 operands[3] = gen_frame_mem (Pmode, operands[0]);
12001 operands[4] = gen_frame_mem (Pmode, operands[1]);
12002 operands[5] = gen_frame_mem (BLKmode, operands[0]);
12003 }")
12005 (define_expand "save_stack_nonlocal"
12006 [(set (match_dup 3) (match_dup 4))
12007 (set (match_operand 0 "memory_operand" "") (match_dup 3))
12008 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
12009 ""
12010 "
12011 {
12012 int units_per_word = (TARGET_32BIT) ? 4 : 8;
12014 /* Copy the backchain to the first word, sp to the second. */
12015 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
12016 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
12017 operands[3] = gen_reg_rtx (Pmode);
12018 operands[4] = gen_frame_mem (Pmode, operands[1]);
12019 }")
12021 (define_expand "restore_stack_nonlocal"
12022 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
12023 (set (match_dup 3) (match_dup 4))
12024 (set (match_dup 5) (match_dup 2))
12025 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
12026 (set (match_operand 0 "register_operand" "") (match_dup 3))]
12027 ""
12028 "
12029 {
12030 int units_per_word = (TARGET_32BIT) ? 4 : 8;
12032 /* Restore the backchain from the first word, sp from the second. */
12033 operands[2] = gen_reg_rtx (Pmode);
12034 operands[3] = gen_reg_rtx (Pmode);
12035 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
12036 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
12037 operands[5] = gen_frame_mem (Pmode, operands[3]);
12038 operands[6] = gen_frame_mem (BLKmode, operands[0]);
12039 }")
12040 \f
12041 ;; TOC register handling.
12043 ;; Code to initialize the TOC register...
12045 (define_insn "load_toc_aix_si"
12046 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12047 (unspec:SI [(const_int 0)] UNSPEC_TOC))
12048 (use (reg:SI 2))])]
12049 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
12050 "*
12051 {
12052 char buf[30];
12053 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12054 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12055 operands[2] = gen_rtx_REG (Pmode, 2);
12056 return \"{l|lwz} %0,%1(%2)\";
12057 }"
12058 [(set_attr "type" "load")])
12060 (define_insn "load_toc_aix_di"
12061 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12062 (unspec:DI [(const_int 0)] UNSPEC_TOC))
12063 (use (reg:DI 2))])]
12064 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
12065 "*
12066 {
12067 char buf[30];
12068 #ifdef TARGET_RELOCATABLE
12069 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
12070 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
12071 #else
12072 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12073 #endif
12074 if (TARGET_ELF)
12075 strcat (buf, \"@toc\");
12076 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12077 operands[2] = gen_rtx_REG (Pmode, 2);
12078 return \"ld %0,%1(%2)\";
12079 }"
12080 [(set_attr "type" "load")])
12082 (define_insn "load_toc_v4_pic_si"
12083 [(set (reg:SI LR_REGNO)
12084 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
12085 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
12086 "bl _GLOBAL_OFFSET_TABLE_@local-4"
12087 [(set_attr "type" "branch")
12088 (set_attr "length" "4")])
12090 (define_expand "load_toc_v4_PIC_1"
12091 [(parallel [(set (reg:SI LR_REGNO)
12092 (match_operand:SI 0 "immediate_operand" "s"))
12093 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
12094 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12095 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12096 "")
12098 (define_insn "load_toc_v4_PIC_1_normal"
12099 [(set (reg:SI LR_REGNO)
12100 (match_operand:SI 0 "immediate_operand" "s"))
12101 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12102 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
12103 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12104 "bcl 20,31,%0\\n%0:"
12105 [(set_attr "type" "branch")
12106 (set_attr "length" "4")])
12108 (define_insn "load_toc_v4_PIC_1_476"
12109 [(set (reg:SI LR_REGNO)
12110 (match_operand:SI 0 "immediate_operand" "s"))
12111 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12112 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
12113 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12114 "*
12115 {
12116 char name[32];
12117 static char templ[32];
12119 get_ppc476_thunk_name (name);
12120 sprintf (templ, \"bl %s\\n%%0:\", name);
12121 return templ;
12122 }"
12123 [(set_attr "type" "branch")
12124 (set_attr "length" "4")])
12126 (define_expand "load_toc_v4_PIC_1b"
12127 [(parallel [(set (reg:SI LR_REGNO)
12128 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12129 (label_ref (match_operand 1 "" ""))]
12130 UNSPEC_TOCPTR))
12131 (match_dup 1)])]
12132 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12133 "")
12135 (define_insn "load_toc_v4_PIC_1b_normal"
12136 [(set (reg:SI LR_REGNO)
12137 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12138 (label_ref (match_operand 1 "" ""))]
12139 UNSPEC_TOCPTR))
12140 (match_dup 1)]
12141 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12142 "bcl 20,31,$+8\;.long %0-$"
12143 [(set_attr "type" "branch")
12144 (set_attr "length" "8")])
12146 (define_insn "load_toc_v4_PIC_1b_476"
12147 [(set (reg:SI LR_REGNO)
12148 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12149 (label_ref (match_operand 1 "" ""))]
12150 UNSPEC_TOCPTR))
12151 (match_dup 1)]
12152 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12153 "*
12154 {
12155 char name[32];
12156 static char templ[32];
12158 get_ppc476_thunk_name (name);
12159 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
12160 return templ;
12161 }"
12162 [(set_attr "type" "branch")
12163 (set_attr "length" "16")])
12165 (define_insn "load_toc_v4_PIC_2"
12166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12167 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12168 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12169 (match_operand:SI 3 "immediate_operand" "s")))))]
12170 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12171 "{l|lwz} %0,%2-%3(%1)"
12172 [(set_attr "type" "load")])
12174 (define_insn "load_toc_v4_PIC_3b"
12175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12176 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12177 (high:SI
12178 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12179 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12180 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12181 "{cau|addis} %0,%1,%2-%3@ha")
12183 (define_insn "load_toc_v4_PIC_3c"
12184 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12185 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12186 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12187 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12188 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12189 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
12191 ;; If the TOC is shared over a translation unit, as happens with all
12192 ;; the kinds of PIC that we support, we need to restore the TOC
12193 ;; pointer only when jumping over units of translation.
12194 ;; On Darwin, we need to reload the picbase.
12196 (define_expand "builtin_setjmp_receiver"
12197 [(use (label_ref (match_operand 0 "" "")))]
12198 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12199 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12200 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12201 "
12202 {
12203 #if TARGET_MACHO
12204 if (DEFAULT_ABI == ABI_DARWIN)
12205 {
12206 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12207 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12208 rtx tmplabrtx;
12209 char tmplab[20];
12211 crtl->uses_pic_offset_table = 1;
12212 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12213 CODE_LABEL_NUMBER (operands[0]));
12214 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12216 emit_insn (gen_load_macho_picbase (tmplabrtx));
12217 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12218 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12219 }
12220 else
12221 #endif
12222 rs6000_emit_load_toc_table (FALSE);
12223 DONE;
12224 }")
12226 ;; Elf specific ways of loading addresses for non-PIC code.
12227 ;; The output of this could be r0, but we make a very strong
12228 ;; preference for a base register because it will usually
12229 ;; be needed there.
12230 (define_insn "elf_high"
12231 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12232 (high:SI (match_operand 1 "" "")))]
12233 "TARGET_ELF && ! TARGET_64BIT"
12234 "{liu|lis} %0,%1@ha")
12236 (define_insn "elf_low"
12237 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12238 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12239 (match_operand 2 "" "")))]
12240 "TARGET_ELF && ! TARGET_64BIT"
12241 "@
12242 {cal|la} %0,%2@l(%1)
12243 {ai|addic} %0,%1,%K2")
12245 ;; Largetoc support
12246 (define_insn "largetoc_high"
12247 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
12248 (const:DI
12249 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12250 (high:DI (match_operand:DI 2 "" "")))))]
12251 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12252 "{cau|addis} %0,%1,%2@ha")
12254 (define_insn "largetoc_low"
12255 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12256 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
12257 (match_operand:DI 2 "" "")))]
12258 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12259 "{cal %0,%2@l(%1)|addi %0,%1,%2@l}")
12260 \f
12261 ;; Call and call_value insns
12262 (define_expand "call"
12263 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12264 (match_operand 1 "" ""))
12265 (use (match_operand 2 "" ""))
12266 (clobber (reg:SI LR_REGNO))])]
12267 ""
12268 "
12269 {
12270 #if TARGET_MACHO
12271 if (MACHOPIC_INDIRECT)
12272 operands[0] = machopic_indirect_call_target (operands[0]);
12273 #endif
12275 gcc_assert (GET_CODE (operands[0]) == MEM);
12276 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12278 operands[0] = XEXP (operands[0], 0);
12280 if (GET_CODE (operands[0]) != SYMBOL_REF
12281 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12282 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12283 {
12284 if (INTVAL (operands[2]) & CALL_LONG)
12285 operands[0] = rs6000_longcall_ref (operands[0]);
12287 switch (DEFAULT_ABI)
12288 {
12289 case ABI_V4:
12290 case ABI_DARWIN:
12291 operands[0] = force_reg (Pmode, operands[0]);
12292 break;
12294 case ABI_AIX:
12295 /* AIX function pointers are really pointers to a three word
12296 area. */
12297 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
12298 DONE;
12300 default:
12301 gcc_unreachable ();
12302 }
12303 }
12304 }")
12306 (define_expand "call_value"
12307 [(parallel [(set (match_operand 0 "" "")
12308 (call (mem:SI (match_operand 1 "address_operand" ""))
12309 (match_operand 2 "" "")))
12310 (use (match_operand 3 "" ""))
12311 (clobber (reg:SI LR_REGNO))])]
12312 ""
12313 "
12314 {
12315 #if TARGET_MACHO
12316 if (MACHOPIC_INDIRECT)
12317 operands[1] = machopic_indirect_call_target (operands[1]);
12318 #endif
12320 gcc_assert (GET_CODE (operands[1]) == MEM);
12321 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12323 operands[1] = XEXP (operands[1], 0);
12325 if (GET_CODE (operands[1]) != SYMBOL_REF
12326 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12327 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12328 {
12329 if (INTVAL (operands[3]) & CALL_LONG)
12330 operands[1] = rs6000_longcall_ref (operands[1]);
12332 switch (DEFAULT_ABI)
12333 {
12334 case ABI_V4:
12335 case ABI_DARWIN:
12336 operands[1] = force_reg (Pmode, operands[1]);
12337 break;
12339 case ABI_AIX:
12340 /* AIX function pointers are really pointers to a three word
12341 area. */
12342 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
12343 DONE;
12345 default:
12346 gcc_unreachable ();
12347 }
12348 }
12349 }")
12351 ;; Call to function in current module. No TOC pointer reload needed.
12352 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12353 ;; either the function was not prototyped, or it was prototyped as a
12354 ;; variable argument function. It is > 0 if FP registers were passed
12355 ;; and < 0 if they were not.
12357 (define_insn "*call_local32"
12358 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12359 (match_operand 1 "" "g,g"))
12360 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12361 (clobber (reg:SI LR_REGNO))]
12362 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12363 "*
12364 {
12365 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12366 output_asm_insn (\"crxor 6,6,6\", operands);
12368 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12369 output_asm_insn (\"creqv 6,6,6\", operands);
12371 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12372 }"
12373 [(set_attr "type" "branch")
12374 (set_attr "length" "4,8")])
12376 (define_insn "*call_local64"
12377 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12378 (match_operand 1 "" "g,g"))
12379 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12380 (clobber (reg:SI LR_REGNO))]
12381 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12382 "*
12383 {
12384 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12385 output_asm_insn (\"crxor 6,6,6\", operands);
12387 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12388 output_asm_insn (\"creqv 6,6,6\", operands);
12390 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12391 }"
12392 [(set_attr "type" "branch")
12393 (set_attr "length" "4,8")])
12395 (define_insn "*call_value_local32"
12396 [(set (match_operand 0 "" "")
12397 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12398 (match_operand 2 "" "g,g")))
12399 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12400 (clobber (reg:SI LR_REGNO))]
12401 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12402 "*
12403 {
12404 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12405 output_asm_insn (\"crxor 6,6,6\", operands);
12407 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12408 output_asm_insn (\"creqv 6,6,6\", operands);
12410 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12411 }"
12412 [(set_attr "type" "branch")
12413 (set_attr "length" "4,8")])
12416 (define_insn "*call_value_local64"
12417 [(set (match_operand 0 "" "")
12418 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12419 (match_operand 2 "" "g,g")))
12420 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12421 (clobber (reg:SI LR_REGNO))]
12422 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12423 "*
12424 {
12425 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12426 output_asm_insn (\"crxor 6,6,6\", operands);
12428 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12429 output_asm_insn (\"creqv 6,6,6\", operands);
12431 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12432 }"
12433 [(set_attr "type" "branch")
12434 (set_attr "length" "4,8")])
12436 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12437 ;; Operand0 is the addresss of the function to call
12438 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12439 ;; Operand2 is the location in the function descriptor to load r2 from
12440 ;; Operand3 is the stack location to hold the current TOC pointer
12442 (define_insn "call_indirect_aix<ptrsize>"
12443 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12444 (match_operand 1 "" "g,g"))
12445 (use (match_operand:P 2 "memory_operand" "m,m"))
12446 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
12447 (use (reg:P STATIC_CHAIN_REGNUM))
12448 (clobber (reg:P LR_REGNO))]
12449 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12450 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12451 [(set_attr "type" "jmpreg")
12452 (set_attr "length" "12")])
12454 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
12455 ;; Operand0 is the addresss of the function to call
12456 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12457 ;; Operand2 is the location in the function descriptor to load r2 from
12458 ;; Operand3 is the stack location to hold the current TOC pointer
12460 (define_insn "call_indirect_aix<ptrsize>_nor11"
12461 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12462 (match_operand 1 "" "g,g"))
12463 (use (match_operand:P 2 "memory_operand" "m,m"))
12464 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
12465 (clobber (reg:P LR_REGNO))]
12466 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12467 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12468 [(set_attr "type" "jmpreg")
12469 (set_attr "length" "12")])
12471 ;; Operand0 is the return result of the function
12472 ;; Operand1 is the addresss of the function to call
12473 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12474 ;; Operand3 is the location in the function descriptor to load r2 from
12475 ;; Operand4 is the stack location to hold the current TOC pointer
12477 (define_insn "call_value_indirect_aix<ptrsize>"
12478 [(set (match_operand 0 "" "")
12479 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12480 (match_operand 2 "" "g,g")))
12481 (use (match_operand:P 3 "memory_operand" "m,m"))
12482 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
12483 (use (reg:P STATIC_CHAIN_REGNUM))
12484 (clobber (reg:P LR_REGNO))]
12485 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12486 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12487 [(set_attr "type" "jmpreg")
12488 (set_attr "length" "12")])
12490 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
12491 ;; Operand0 is the return result of the function
12492 ;; Operand1 is the addresss of the function to call
12493 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12494 ;; Operand3 is the location in the function descriptor to load r2 from
12495 ;; Operand4 is the stack location to hold the current TOC pointer
12497 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
12498 [(set (match_operand 0 "" "")
12499 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12500 (match_operand 2 "" "g,g")))
12501 (use (match_operand:P 3 "memory_operand" "m,m"))
12502 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
12503 (clobber (reg:P LR_REGNO))]
12504 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12505 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12506 [(set_attr "type" "jmpreg")
12507 (set_attr "length" "12")])
12509 ;; Call to function which may be in another module. Restore the TOC
12510 ;; pointer (r2) after the call unless this is System V.
12511 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12512 ;; either the function was not prototyped, or it was prototyped as a
12513 ;; variable argument function. It is > 0 if FP registers were passed
12514 ;; and < 0 if they were not.
12516 (define_insn "*call_nonlocal_aix32"
12517 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12518 (match_operand 1 "" "g"))
12519 (use (match_operand:SI 2 "immediate_operand" "O"))
12520 (clobber (reg:SI LR_REGNO))]
12521 "TARGET_32BIT
12522 && DEFAULT_ABI == ABI_AIX
12523 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12524 "bl %z0\;%."
12525 [(set_attr "type" "branch")
12526 (set_attr "length" "8")])
12528 (define_insn "*call_nonlocal_aix64"
12529 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12530 (match_operand 1 "" "g"))
12531 (use (match_operand:SI 2 "immediate_operand" "O"))
12532 (clobber (reg:SI LR_REGNO))]
12533 "TARGET_64BIT
12534 && DEFAULT_ABI == ABI_AIX
12535 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12536 "bl %z0\;%."
12537 [(set_attr "type" "branch")
12538 (set_attr "length" "8")])
12540 (define_insn "*call_value_nonlocal_aix32"
12541 [(set (match_operand 0 "" "")
12542 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12543 (match_operand 2 "" "g")))
12544 (use (match_operand:SI 3 "immediate_operand" "O"))
12545 (clobber (reg:SI LR_REGNO))]
12546 "TARGET_32BIT
12547 && DEFAULT_ABI == ABI_AIX
12548 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12549 "bl %z1\;%."
12550 [(set_attr "type" "branch")
12551 (set_attr "length" "8")])
12553 (define_insn "*call_value_nonlocal_aix64"
12554 [(set (match_operand 0 "" "")
12555 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12556 (match_operand 2 "" "g")))
12557 (use (match_operand:SI 3 "immediate_operand" "O"))
12558 (clobber (reg:SI LR_REGNO))]
12559 "TARGET_64BIT
12560 && DEFAULT_ABI == ABI_AIX
12561 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12562 "bl %z1\;%."
12563 [(set_attr "type" "branch")
12564 (set_attr "length" "8")])
12566 ;; A function pointer under System V is just a normal pointer
12567 ;; operands[0] is the function pointer
12568 ;; operands[1] is the stack size to clean up
12569 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12570 ;; which indicates how to set cr1
12572 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12573 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12574 (match_operand 1 "" "g,g,g,g"))
12575 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12576 (clobber (reg:SI LR_REGNO))]
12577 "DEFAULT_ABI == ABI_V4
12578 || DEFAULT_ABI == ABI_DARWIN"
12579 {
12580 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12581 output_asm_insn ("crxor 6,6,6", operands);
12583 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12584 output_asm_insn ("creqv 6,6,6", operands);
12586 return "b%T0l";
12587 }
12588 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12589 (set_attr "length" "4,4,8,8")])
12591 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12592 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12593 (match_operand 1 "" "g,g"))
12594 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12595 (clobber (reg:SI LR_REGNO))]
12596 "(DEFAULT_ABI == ABI_DARWIN
12597 || (DEFAULT_ABI == ABI_V4
12598 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12599 {
12600 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12601 output_asm_insn ("crxor 6,6,6", operands);
12603 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12604 output_asm_insn ("creqv 6,6,6", operands);
12606 #if TARGET_MACHO
12607 return output_call(insn, operands, 0, 2);
12608 #else
12609 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12610 {
12611 gcc_assert (!TARGET_SECURE_PLT);
12612 return "bl %z0@plt";
12613 }
12614 else
12615 return "bl %z0";
12616 #endif
12617 }
12618 "DEFAULT_ABI == ABI_V4
12619 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12620 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12621 [(parallel [(call (mem:SI (match_dup 0))
12622 (match_dup 1))
12623 (use (match_dup 2))
12624 (use (match_dup 3))
12625 (clobber (reg:SI LR_REGNO))])]
12626 {
12627 operands[3] = pic_offset_table_rtx;
12628 }
12629 [(set_attr "type" "branch,branch")
12630 (set_attr "length" "4,8")])
12632 (define_insn "*call_nonlocal_sysv_secure<mode>"
12633 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12634 (match_operand 1 "" "g,g"))
12635 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12636 (use (match_operand:SI 3 "register_operand" "r,r"))
12637 (clobber (reg:SI LR_REGNO))]
12638 "(DEFAULT_ABI == ABI_V4
12639 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12640 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12641 {
12642 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12643 output_asm_insn ("crxor 6,6,6", operands);
12645 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12646 output_asm_insn ("creqv 6,6,6", operands);
12648 if (flag_pic == 2)
12649 /* The magic 32768 offset here and in the other sysv call insns
12650 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12651 See sysv4.h:toc_section. */
12652 return "bl %z0+32768@plt";
12653 else
12654 return "bl %z0@plt";
12655 }
12656 [(set_attr "type" "branch,branch")
12657 (set_attr "length" "4,8")])
12659 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12660 [(set (match_operand 0 "" "")
12661 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12662 (match_operand 2 "" "g,g,g,g")))
12663 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12664 (clobber (reg:SI LR_REGNO))]
12665 "DEFAULT_ABI == ABI_V4
12666 || DEFAULT_ABI == ABI_DARWIN"
12667 {
12668 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12669 output_asm_insn ("crxor 6,6,6", operands);
12671 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12672 output_asm_insn ("creqv 6,6,6", operands);
12674 return "b%T1l";
12675 }
12676 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12677 (set_attr "length" "4,4,8,8")])
12679 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12680 [(set (match_operand 0 "" "")
12681 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12682 (match_operand 2 "" "g,g")))
12683 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12684 (clobber (reg:SI LR_REGNO))]
12685 "(DEFAULT_ABI == ABI_DARWIN
12686 || (DEFAULT_ABI == ABI_V4
12687 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12688 {
12689 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12690 output_asm_insn ("crxor 6,6,6", operands);
12692 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12693 output_asm_insn ("creqv 6,6,6", operands);
12695 #if TARGET_MACHO
12696 return output_call(insn, operands, 1, 3);
12697 #else
12698 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12699 {
12700 gcc_assert (!TARGET_SECURE_PLT);
12701 return "bl %z1@plt";
12702 }
12703 else
12704 return "bl %z1";
12705 #endif
12706 }
12707 "DEFAULT_ABI == ABI_V4
12708 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12709 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12710 [(parallel [(set (match_dup 0)
12711 (call (mem:SI (match_dup 1))
12712 (match_dup 2)))
12713 (use (match_dup 3))
12714 (use (match_dup 4))
12715 (clobber (reg:SI LR_REGNO))])]
12716 {
12717 operands[4] = pic_offset_table_rtx;
12718 }
12719 [(set_attr "type" "branch,branch")
12720 (set_attr "length" "4,8")])
12722 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12723 [(set (match_operand 0 "" "")
12724 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12725 (match_operand 2 "" "g,g")))
12726 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12727 (use (match_operand:SI 4 "register_operand" "r,r"))
12728 (clobber (reg:SI LR_REGNO))]
12729 "(DEFAULT_ABI == ABI_V4
12730 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12731 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12732 {
12733 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12734 output_asm_insn ("crxor 6,6,6", operands);
12736 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12737 output_asm_insn ("creqv 6,6,6", operands);
12739 if (flag_pic == 2)
12740 return "bl %z1+32768@plt";
12741 else
12742 return "bl %z1@plt";
12743 }
12744 [(set_attr "type" "branch,branch")
12745 (set_attr "length" "4,8")])
12747 ;; Call subroutine returning any type.
12748 (define_expand "untyped_call"
12749 [(parallel [(call (match_operand 0 "" "")
12750 (const_int 0))
12751 (match_operand 1 "" "")
12752 (match_operand 2 "" "")])]
12753 ""
12754 "
12755 {
12756 int i;
12758 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12760 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12761 {
12762 rtx set = XVECEXP (operands[2], 0, i);
12763 emit_move_insn (SET_DEST (set), SET_SRC (set));
12764 }
12766 /* The optimizer does not know that the call sets the function value
12767 registers we stored in the result block. We avoid problems by
12768 claiming that all hard registers are used and clobbered at this
12769 point. */
12770 emit_insn (gen_blockage ());
12772 DONE;
12773 }")
12775 ;; sibling call patterns
12776 (define_expand "sibcall"
12777 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12778 (match_operand 1 "" ""))
12779 (use (match_operand 2 "" ""))
12780 (use (reg:SI LR_REGNO))
12781 (simple_return)])]
12782 ""
12783 "
12784 {
12785 #if TARGET_MACHO
12786 if (MACHOPIC_INDIRECT)
12787 operands[0] = machopic_indirect_call_target (operands[0]);
12788 #endif
12790 gcc_assert (GET_CODE (operands[0]) == MEM);
12791 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12793 operands[0] = XEXP (operands[0], 0);
12794 }")
12796 ;; this and similar patterns must be marked as using LR, otherwise
12797 ;; dataflow will try to delete the store into it. This is true
12798 ;; even when the actual reg to jump to is in CTR, when LR was
12799 ;; saved and restored around the PIC-setting BCL.
12800 (define_insn "*sibcall_local32"
12801 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12802 (match_operand 1 "" "g,g"))
12803 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12804 (use (reg:SI LR_REGNO))
12805 (simple_return)]
12806 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12807 "*
12808 {
12809 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12810 output_asm_insn (\"crxor 6,6,6\", operands);
12812 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12813 output_asm_insn (\"creqv 6,6,6\", operands);
12815 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12816 }"
12817 [(set_attr "type" "branch")
12818 (set_attr "length" "4,8")])
12820 (define_insn "*sibcall_local64"
12821 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12822 (match_operand 1 "" "g,g"))
12823 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12824 (use (reg:SI LR_REGNO))
12825 (simple_return)]
12826 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12827 "*
12828 {
12829 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12830 output_asm_insn (\"crxor 6,6,6\", operands);
12832 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12833 output_asm_insn (\"creqv 6,6,6\", operands);
12835 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12836 }"
12837 [(set_attr "type" "branch")
12838 (set_attr "length" "4,8")])
12840 (define_insn "*sibcall_value_local32"
12841 [(set (match_operand 0 "" "")
12842 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12843 (match_operand 2 "" "g,g")))
12844 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12845 (use (reg:SI LR_REGNO))
12846 (simple_return)]
12847 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12848 "*
12849 {
12850 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12851 output_asm_insn (\"crxor 6,6,6\", operands);
12853 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12854 output_asm_insn (\"creqv 6,6,6\", operands);
12856 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12857 }"
12858 [(set_attr "type" "branch")
12859 (set_attr "length" "4,8")])
12862 (define_insn "*sibcall_value_local64"
12863 [(set (match_operand 0 "" "")
12864 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12865 (match_operand 2 "" "g,g")))
12866 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12867 (use (reg:SI LR_REGNO))
12868 (simple_return)]
12869 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12870 "*
12871 {
12872 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12873 output_asm_insn (\"crxor 6,6,6\", operands);
12875 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12876 output_asm_insn (\"creqv 6,6,6\", operands);
12878 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12879 }"
12880 [(set_attr "type" "branch")
12881 (set_attr "length" "4,8")])
12883 (define_insn "*sibcall_nonlocal_aix<mode>"
12884 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12885 (match_operand 1 "" "g,g"))
12886 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12887 (use (reg:SI LR_REGNO))
12888 (simple_return)]
12889 "DEFAULT_ABI == ABI_AIX
12890 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12891 "@
12892 b %z0
12893 b%T0"
12894 [(set_attr "type" "branch")
12895 (set_attr "length" "4")])
12897 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12898 [(set (match_operand 0 "" "")
12899 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12900 (match_operand 2 "" "g,g")))
12901 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12902 (use (reg:SI LR_REGNO))
12903 (simple_return)]
12904 "DEFAULT_ABI == ABI_AIX
12905 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12906 "@
12907 b %z1
12908 b%T1"
12909 [(set_attr "type" "branch")
12910 (set_attr "length" "4")])
12912 (define_insn "*sibcall_nonlocal_sysv<mode>"
12913 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12914 (match_operand 1 "" ""))
12915 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12916 (use (reg:SI LR_REGNO))
12917 (simple_return)]
12918 "(DEFAULT_ABI == ABI_DARWIN
12919 || DEFAULT_ABI == ABI_V4)
12920 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12921 "*
12922 {
12923 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12924 output_asm_insn (\"crxor 6,6,6\", operands);
12926 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12927 output_asm_insn (\"creqv 6,6,6\", operands);
12929 if (which_alternative >= 2)
12930 return \"b%T0\";
12931 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12932 {
12933 gcc_assert (!TARGET_SECURE_PLT);
12934 return \"b %z0@plt\";
12935 }
12936 else
12937 return \"b %z0\";
12938 }"
12939 [(set_attr "type" "branch")
12940 (set_attr "length" "4,8,4,8")])
12942 (define_expand "sibcall_value"
12943 [(parallel [(set (match_operand 0 "register_operand" "")
12944 (call (mem:SI (match_operand 1 "address_operand" ""))
12945 (match_operand 2 "" "")))
12946 (use (match_operand 3 "" ""))
12947 (use (reg:SI LR_REGNO))
12948 (simple_return)])]
12949 ""
12950 "
12951 {
12952 #if TARGET_MACHO
12953 if (MACHOPIC_INDIRECT)
12954 operands[1] = machopic_indirect_call_target (operands[1]);
12955 #endif
12957 gcc_assert (GET_CODE (operands[1]) == MEM);
12958 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12960 operands[1] = XEXP (operands[1], 0);
12961 }")
12963 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12964 [(set (match_operand 0 "" "")
12965 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12966 (match_operand 2 "" "")))
12967 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12968 (use (reg:SI LR_REGNO))
12969 (simple_return)]
12970 "(DEFAULT_ABI == ABI_DARWIN
12971 || DEFAULT_ABI == ABI_V4)
12972 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12973 "*
12974 {
12975 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12976 output_asm_insn (\"crxor 6,6,6\", operands);
12978 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12979 output_asm_insn (\"creqv 6,6,6\", operands);
12981 if (which_alternative >= 2)
12982 return \"b%T1\";
12983 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12984 {
12985 gcc_assert (!TARGET_SECURE_PLT);
12986 return \"b %z1@plt\";
12987 }
12988 else
12989 return \"b %z1\";
12990 }"
12991 [(set_attr "type" "branch")
12992 (set_attr "length" "4,8,4,8")])
12994 (define_expand "sibcall_epilogue"
12995 [(use (const_int 0))]
12996 ""
12997 {
12998 if (!TARGET_SCHED_PROLOG)
12999 emit_insn (gen_blockage ());
13000 rs6000_emit_epilogue (TRUE);
13001 DONE;
13002 })
13004 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13005 ;; all of memory. This blocks insns from being moved across this point.
13007 (define_insn "blockage"
13008 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13009 ""
13010 "")
13012 (define_insn "probe_stack"
13013 [(set (match_operand 0 "memory_operand" "=m")
13014 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13015 ""
13016 "*
13017 {
13018 operands[1] = gen_rtx_REG (Pmode, 0);
13019 return \"{st%U0%X0|stw%U0%X0} %1,%0\";
13020 }"
13021 [(set_attr "type" "store")
13022 (set_attr "length" "4")])
13024 (define_insn "probe_stack_range<P:mode>"
13025 [(set (match_operand:P 0 "register_operand" "=r")
13026 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13027 (match_operand:P 2 "register_operand" "r")]
13028 UNSPECV_PROBE_STACK_RANGE))]
13029 ""
13030 "* return output_probe_stack_range (operands[0], operands[2]);"
13031 [(set_attr "type" "three")])
13032 \f
13033 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13034 ;; signed & unsigned, and one type of branch.
13035 ;;
13036 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13037 ;; insns, and branches.
13039 (define_expand "cbranch<mode>4"
13040 [(use (match_operator 0 "rs6000_cbranch_operator"
13041 [(match_operand:GPR 1 "gpc_reg_operand" "")
13042 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13043 (use (match_operand 3 ""))]
13044 ""
13045 "
13046 {
13047 /* Take care of the possibility that operands[2] might be negative but
13048 this might be a logical operation. That insn doesn't exist. */
13049 if (GET_CODE (operands[2]) == CONST_INT
13050 && INTVAL (operands[2]) < 0)
13051 {
13052 operands[2] = force_reg (<MODE>mode, operands[2]);
13053 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13054 GET_MODE (operands[0]),
13055 operands[1], operands[2]);
13056 }
13058 rs6000_emit_cbranch (<MODE>mode, operands);
13059 DONE;
13060 }")
13062 (define_expand "cbranch<mode>4"
13063 [(use (match_operator 0 "rs6000_cbranch_operator"
13064 [(match_operand:FP 1 "gpc_reg_operand" "")
13065 (match_operand:FP 2 "gpc_reg_operand" "")]))
13066 (use (match_operand 3 ""))]
13067 ""
13068 "
13069 {
13070 rs6000_emit_cbranch (<MODE>mode, operands);
13071 DONE;
13072 }")
13074 (define_expand "cstore<mode>4"
13075 [(use (match_operator 1 "rs6000_cbranch_operator"
13076 [(match_operand:GPR 2 "gpc_reg_operand" "")
13077 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13078 (clobber (match_operand:SI 0 "register_operand"))]
13079 ""
13080 "
13081 {
13082 /* Take care of the possibility that operands[3] might be negative but
13083 this might be a logical operation. That insn doesn't exist. */
13084 if (GET_CODE (operands[3]) == CONST_INT
13085 && INTVAL (operands[3]) < 0)
13086 {
13087 operands[3] = force_reg (<MODE>mode, operands[3]);
13088 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13089 GET_MODE (operands[1]),
13090 operands[2], operands[3]);
13091 }
13093 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13094 For SEQ, likewise, except that comparisons with zero should be done
13095 with an scc insns. However, due to the order that combine see the
13096 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13097 the cases we don't want to handle or are best handled by portable
13098 code. */
13099 if (GET_CODE (operands[1]) == NE)
13100 FAIL;
13101 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13102 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13103 && operands[3] == const0_rtx)
13104 FAIL;
13105 rs6000_emit_sCOND (<MODE>mode, operands);
13106 DONE;
13107 }")
13109 (define_expand "cstore<mode>4"
13110 [(use (match_operator 1 "rs6000_cbranch_operator"
13111 [(match_operand:FP 2 "gpc_reg_operand" "")
13112 (match_operand:FP 3 "gpc_reg_operand" "")]))
13113 (clobber (match_operand:SI 0 "register_operand"))]
13114 ""
13115 "
13116 {
13117 rs6000_emit_sCOND (<MODE>mode, operands);
13118 DONE;
13119 }")
13122 (define_expand "stack_protect_set"
13123 [(match_operand 0 "memory_operand" "")
13124 (match_operand 1 "memory_operand" "")]
13125 ""
13126 {
13127 #ifdef TARGET_THREAD_SSP_OFFSET
13128 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13129 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13130 operands[1] = gen_rtx_MEM (Pmode, addr);
13131 #endif
13132 if (TARGET_64BIT)
13133 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13134 else
13135 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13136 DONE;
13137 })
13139 (define_insn "stack_protect_setsi"
13140 [(set (match_operand:SI 0 "memory_operand" "=m")
13141 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13142 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13143 "TARGET_32BIT"
13144 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
13145 [(set_attr "type" "three")
13146 (set_attr "length" "12")])
13148 (define_insn "stack_protect_setdi"
13149 [(set (match_operand:DI 0 "memory_operand" "=m")
13150 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13151 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13152 "TARGET_64BIT"
13153 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
13154 [(set_attr "type" "three")
13155 (set_attr "length" "12")])
13157 (define_expand "stack_protect_test"
13158 [(match_operand 0 "memory_operand" "")
13159 (match_operand 1 "memory_operand" "")
13160 (match_operand 2 "" "")]
13161 ""
13162 {
13163 rtx test, op0, op1;
13164 #ifdef TARGET_THREAD_SSP_OFFSET
13165 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13166 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13167 operands[1] = gen_rtx_MEM (Pmode, addr);
13168 #endif
13169 op0 = operands[0];
13170 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13171 test = gen_rtx_EQ (VOIDmode, op0, op1);
13172 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13173 DONE;
13174 })
13176 (define_insn "stack_protect_testsi"
13177 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13178 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13179 (match_operand:SI 2 "memory_operand" "m,m")]
13180 UNSPEC_SP_TEST))
13181 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13182 (clobber (match_scratch:SI 3 "=&r,&r"))]
13183 "TARGET_32BIT"
13184 "@
13185 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13186 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13187 [(set_attr "length" "16,20")])
13189 (define_insn "stack_protect_testdi"
13190 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13191 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
13192 (match_operand:DI 2 "memory_operand" "m,m")]
13193 UNSPEC_SP_TEST))
13194 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13195 (clobber (match_scratch:DI 3 "=&r,&r"))]
13196 "TARGET_64BIT"
13197 "@
13198 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13199 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13200 [(set_attr "length" "16,20")])
13202 \f
13203 ;; Here are the actual compare insns.
13204 (define_insn "*cmp<mode>_internal1"
13205 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13206 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13207 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13208 ""
13209 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
13210 [(set_attr "type" "cmp")])
13212 ;; If we are comparing a register for equality with a large constant,
13213 ;; we can do this with an XOR followed by a compare. But this is profitable
13214 ;; only if the large constant is only used for the comparison (and in this
13215 ;; case we already have a register to reuse as scratch).
13216 ;;
13217 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13218 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13220 (define_peephole2
13221 [(set (match_operand:SI 0 "register_operand")
13222 (match_operand:SI 1 "logical_const_operand" ""))
13223 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13224 [(match_dup 0)
13225 (match_operand:SI 2 "logical_const_operand" "")]))
13226 (set (match_operand:CC 4 "cc_reg_operand" "")
13227 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13228 (match_dup 0)))
13229 (set (pc)
13230 (if_then_else (match_operator 6 "equality_operator"
13231 [(match_dup 4) (const_int 0)])
13232 (match_operand 7 "" "")
13233 (match_operand 8 "" "")))]
13234 "peep2_reg_dead_p (3, operands[0])
13235 && peep2_reg_dead_p (4, operands[4])"
13236 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13237 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13238 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13240 {
13241 /* Get the constant we are comparing against, and see what it looks like
13242 when sign-extended from 16 to 32 bits. Then see what constant we could
13243 XOR with SEXTC to get the sign-extended value. */
13244 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13245 SImode,
13246 operands[1], operands[2]);
13247 HOST_WIDE_INT c = INTVAL (cnst);
13248 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13249 HOST_WIDE_INT xorv = c ^ sextc;
13251 operands[9] = GEN_INT (xorv);
13252 operands[10] = GEN_INT (sextc);
13253 })
13255 (define_insn "*cmpsi_internal2"
13256 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13257 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13258 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13259 ""
13260 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
13261 [(set_attr "type" "cmp")])
13263 (define_insn "*cmpdi_internal2"
13264 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13265 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13266 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13267 ""
13268 "cmpld%I2 %0,%1,%b2"
13269 [(set_attr "type" "cmp")])
13271 ;; The following two insns don't exist as single insns, but if we provide
13272 ;; them, we can swap an add and compare, which will enable us to overlap more
13273 ;; of the required delay between a compare and branch. We generate code for
13274 ;; them by splitting.
13276 (define_insn ""
13277 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13278 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13279 (match_operand:SI 2 "short_cint_operand" "i")))
13280 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13281 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13282 ""
13283 "#"
13284 [(set_attr "length" "8")])
13286 (define_insn ""
13287 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13288 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13289 (match_operand:SI 2 "u_short_cint_operand" "i")))
13290 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13291 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13292 ""
13293 "#"
13294 [(set_attr "length" "8")])
13296 (define_split
13297 [(set (match_operand:CC 3 "cc_reg_operand" "")
13298 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13299 (match_operand:SI 2 "short_cint_operand" "")))
13300 (set (match_operand:SI 0 "gpc_reg_operand" "")
13301 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13302 ""
13303 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13304 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13306 (define_split
13307 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13308 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13309 (match_operand:SI 2 "u_short_cint_operand" "")))
13310 (set (match_operand:SI 0 "gpc_reg_operand" "")
13311 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13312 ""
13313 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13314 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13316 (define_insn "*cmpsf_internal1"
13317 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13318 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13319 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13320 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13321 "fcmpu %0,%1,%2"
13322 [(set_attr "type" "fpcompare")])
13324 (define_insn "*cmpdf_internal1"
13325 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13326 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13327 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13328 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13329 && !VECTOR_UNIT_VSX_P (DFmode)"
13330 "fcmpu %0,%1,%2"
13331 [(set_attr "type" "fpcompare")])
13333 ;; Only need to compare second words if first words equal
13334 (define_insn "*cmptf_internal1"
13335 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13336 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13337 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13338 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13339 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13340 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13341 [(set_attr "type" "fpcompare")
13342 (set_attr "length" "12")])
13344 (define_insn_and_split "*cmptf_internal2"
13345 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13346 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13347 (match_operand:TF 2 "gpc_reg_operand" "d")))
13348 (clobber (match_scratch:DF 3 "=d"))
13349 (clobber (match_scratch:DF 4 "=d"))
13350 (clobber (match_scratch:DF 5 "=d"))
13351 (clobber (match_scratch:DF 6 "=d"))
13352 (clobber (match_scratch:DF 7 "=d"))
13353 (clobber (match_scratch:DF 8 "=d"))
13354 (clobber (match_scratch:DF 9 "=d"))
13355 (clobber (match_scratch:DF 10 "=d"))
13356 (clobber (match_scratch:GPR 11 "=b"))]
13357 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13358 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13359 "#"
13360 "&& reload_completed"
13361 [(set (match_dup 3) (match_dup 14))
13362 (set (match_dup 4) (match_dup 15))
13363 (set (match_dup 9) (abs:DF (match_dup 5)))
13364 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13365 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13366 (label_ref (match_dup 12))
13367 (pc)))
13368 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13369 (set (pc) (label_ref (match_dup 13)))
13370 (match_dup 12)
13371 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13372 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13373 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13374 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13375 (match_dup 13)]
13376 {
13377 REAL_VALUE_TYPE rv;
13378 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13379 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13381 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13382 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13383 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13384 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13385 operands[12] = gen_label_rtx ();
13386 operands[13] = gen_label_rtx ();
13387 real_inf (&rv);
13388 operands[14] = force_const_mem (DFmode,
13389 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13390 operands[15] = force_const_mem (DFmode,
13391 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13392 DFmode));
13393 if (TARGET_TOC)
13394 {
13395 rtx tocref;
13396 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13397 operands[14] = gen_const_mem (DFmode, tocref);
13398 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13399 operands[15] = gen_const_mem (DFmode, tocref);
13400 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13401 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13402 }
13403 })
13404 \f
13405 ;; Now we have the scc insns. We can do some combinations because of the
13406 ;; way the machine works.
13407 ;;
13408 ;; Note that this is probably faster if we can put an insn between the
13409 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13410 ;; cases the insns below which don't use an intermediate CR field will
13411 ;; be used instead.
13412 (define_insn ""
13413 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13414 (match_operator:SI 1 "scc_comparison_operator"
13415 [(match_operand 2 "cc_reg_operand" "y")
13416 (const_int 0)]))]
13417 ""
13418 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13419 [(set (attr "type")
13420 (cond [(match_test "TARGET_MFCRF")
13421 (const_string "mfcrf")
13422 ]
13423 (const_string "mfcr")))
13424 (set_attr "length" "8")])
13426 ;; Same as above, but get the GT bit.
13427 (define_insn "move_from_CR_gt_bit"
13428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13429 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13430 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13431 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13432 [(set_attr "type" "mfcr")
13433 (set_attr "length" "8")])
13435 ;; Same as above, but get the OV/ORDERED bit.
13436 (define_insn "move_from_CR_ov_bit"
13437 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13438 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13439 "TARGET_ISEL"
13440 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13441 [(set_attr "type" "mfcr")
13442 (set_attr "length" "8")])
13444 (define_insn ""
13445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13446 (match_operator:DI 1 "scc_comparison_operator"
13447 [(match_operand 2 "cc_reg_operand" "y")
13448 (const_int 0)]))]
13449 "TARGET_POWERPC64"
13450 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13451 [(set (attr "type")
13452 (cond [(match_test "TARGET_MFCRF")
13453 (const_string "mfcrf")
13454 ]
13455 (const_string "mfcr")))
13456 (set_attr "length" "8")])
13458 (define_insn ""
13459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13460 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13461 [(match_operand 2 "cc_reg_operand" "y,y")
13462 (const_int 0)])
13463 (const_int 0)))
13464 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13465 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13466 "TARGET_32BIT"
13467 "@
13468 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13469 #"
13470 [(set_attr "type" "delayed_compare")
13471 (set_attr "length" "8,16")])
13473 (define_split
13474 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13475 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13476 [(match_operand 2 "cc_reg_operand" "")
13477 (const_int 0)])
13478 (const_int 0)))
13479 (set (match_operand:SI 3 "gpc_reg_operand" "")
13480 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13481 "TARGET_32BIT && reload_completed"
13482 [(set (match_dup 3)
13483 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13484 (set (match_dup 0)
13485 (compare:CC (match_dup 3)
13486 (const_int 0)))]
13487 "")
13489 (define_insn ""
13490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13491 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13492 [(match_operand 2 "cc_reg_operand" "y")
13493 (const_int 0)])
13494 (match_operand:SI 3 "const_int_operand" "n")))]
13495 ""
13496 "*
13497 {
13498 int is_bit = ccr_bit (operands[1], 1);
13499 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13500 int count;
13502 if (is_bit >= put_bit)
13503 count = is_bit - put_bit;
13504 else
13505 count = 32 - (put_bit - is_bit);
13507 operands[4] = GEN_INT (count);
13508 operands[5] = GEN_INT (put_bit);
13510 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13511 }"
13512 [(set (attr "type")
13513 (cond [(match_test "TARGET_MFCRF")
13514 (const_string "mfcrf")
13515 ]
13516 (const_string "mfcr")))
13517 (set_attr "length" "8")])
13519 (define_insn ""
13520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13521 (compare:CC
13522 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13523 [(match_operand 2 "cc_reg_operand" "y,y")
13524 (const_int 0)])
13525 (match_operand:SI 3 "const_int_operand" "n,n"))
13526 (const_int 0)))
13527 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13528 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13529 (match_dup 3)))]
13530 ""
13531 "*
13532 {
13533 int is_bit = ccr_bit (operands[1], 1);
13534 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13535 int count;
13537 /* Force split for non-cc0 compare. */
13538 if (which_alternative == 1)
13539 return \"#\";
13541 if (is_bit >= put_bit)
13542 count = is_bit - put_bit;
13543 else
13544 count = 32 - (put_bit - is_bit);
13546 operands[5] = GEN_INT (count);
13547 operands[6] = GEN_INT (put_bit);
13549 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13550 }"
13551 [(set_attr "type" "delayed_compare")
13552 (set_attr "length" "8,16")])
13554 (define_split
13555 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13556 (compare:CC
13557 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13558 [(match_operand 2 "cc_reg_operand" "")
13559 (const_int 0)])
13560 (match_operand:SI 3 "const_int_operand" ""))
13561 (const_int 0)))
13562 (set (match_operand:SI 4 "gpc_reg_operand" "")
13563 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13564 (match_dup 3)))]
13565 "reload_completed"
13566 [(set (match_dup 4)
13567 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13568 (match_dup 3)))
13569 (set (match_dup 0)
13570 (compare:CC (match_dup 4)
13571 (const_int 0)))]
13572 "")
13574 ;; There is a 3 cycle delay between consecutive mfcr instructions
13575 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13577 (define_peephole
13578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13579 (match_operator:SI 1 "scc_comparison_operator"
13580 [(match_operand 2 "cc_reg_operand" "y")
13581 (const_int 0)]))
13582 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13583 (match_operator:SI 4 "scc_comparison_operator"
13584 [(match_operand 5 "cc_reg_operand" "y")
13585 (const_int 0)]))]
13586 "REGNO (operands[2]) != REGNO (operands[5])"
13587 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13588 [(set_attr "type" "mfcr")
13589 (set_attr "length" "12")])
13591 (define_peephole
13592 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13593 (match_operator:DI 1 "scc_comparison_operator"
13594 [(match_operand 2 "cc_reg_operand" "y")
13595 (const_int 0)]))
13596 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13597 (match_operator:DI 4 "scc_comparison_operator"
13598 [(match_operand 5 "cc_reg_operand" "y")
13599 (const_int 0)]))]
13600 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13601 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13602 [(set_attr "type" "mfcr")
13603 (set_attr "length" "12")])
13605 ;; There are some scc insns that can be done directly, without a compare.
13606 ;; These are faster because they don't involve the communications between
13607 ;; the FXU and branch units. In fact, we will be replacing all of the
13608 ;; integer scc insns here or in the portable methods in emit_store_flag.
13609 ;;
13610 ;; Also support (neg (scc ..)) since that construct is used to replace
13611 ;; branches, (plus (scc ..) ..) since that construct is common and
13612 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13613 ;; cases where it is no more expensive than (neg (scc ..)).
13615 ;; Have reload force a constant into a register for the simple insns that
13616 ;; otherwise won't accept constants. We do this because it is faster than
13617 ;; the cmp/mfcr sequence we would otherwise generate.
13619 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13620 (DI "rKJI")])
13622 (define_insn_and_split "*eq<mode>"
13623 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13624 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13625 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13626 "!TARGET_POWER"
13627 "#"
13628 "!TARGET_POWER"
13629 [(set (match_dup 0)
13630 (clz:GPR (match_dup 3)))
13631 (set (match_dup 0)
13632 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13633 {
13634 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13635 {
13636 /* Use output operand as intermediate. */
13637 operands[3] = operands[0];
13639 if (logical_operand (operands[2], <MODE>mode))
13640 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13641 gen_rtx_XOR (<MODE>mode,
13642 operands[1], operands[2])));
13643 else
13644 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13645 gen_rtx_PLUS (<MODE>mode, operands[1],
13646 negate_rtx (<MODE>mode,
13647 operands[2]))));
13648 }
13649 else
13650 operands[3] = operands[1];
13652 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13653 })
13655 (define_insn_and_split "*eq<mode>_compare"
13656 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13657 (compare:CC
13658 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13659 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13660 (const_int 0)))
13661 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13662 (eq:P (match_dup 1) (match_dup 2)))]
13663 "!TARGET_POWER && optimize_size"
13664 "#"
13665 "!TARGET_POWER && optimize_size"
13666 [(set (match_dup 0)
13667 (clz:P (match_dup 4)))
13668 (parallel [(set (match_dup 3)
13669 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13670 (const_int 0)))
13671 (set (match_dup 0)
13672 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13673 {
13674 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13675 {
13676 /* Use output operand as intermediate. */
13677 operands[4] = operands[0];
13679 if (logical_operand (operands[2], <MODE>mode))
13680 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13681 gen_rtx_XOR (<MODE>mode,
13682 operands[1], operands[2])));
13683 else
13684 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13685 gen_rtx_PLUS (<MODE>mode, operands[1],
13686 negate_rtx (<MODE>mode,
13687 operands[2]))));
13688 }
13689 else
13690 operands[4] = operands[1];
13692 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13693 })
13695 (define_insn "*eqsi_power"
13696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13697 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13698 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13699 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13700 "TARGET_POWER"
13701 "@
13702 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13703 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13704 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13705 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13706 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13707 [(set_attr "type" "three,two,three,three,three")
13708 (set_attr "length" "12,8,12,12,12")])
13710 ;; We have insns of the form shown by the first define_insn below. If
13711 ;; there is something inside the comparison operation, we must split it.
13712 (define_split
13713 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13714 (plus:SI (match_operator 1 "comparison_operator"
13715 [(match_operand:SI 2 "" "")
13716 (match_operand:SI 3
13717 "reg_or_cint_operand" "")])
13718 (match_operand:SI 4 "gpc_reg_operand" "")))
13719 (clobber (match_operand:SI 5 "register_operand" ""))]
13720 "! gpc_reg_operand (operands[2], SImode)"
13721 [(set (match_dup 5) (match_dup 2))
13722 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13723 (match_dup 4)))])
13725 (define_insn "*plus_eqsi"
13726 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13727 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13728 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13729 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13730 "TARGET_32BIT"
13731 "@
13732 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13733 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13734 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13735 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13736 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13737 [(set_attr "type" "three,two,three,three,three")
13738 (set_attr "length" "12,8,12,12,12")])
13740 (define_insn "*compare_plus_eqsi"
13741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13742 (compare:CC
13743 (plus:SI
13744 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13745 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13746 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13747 (const_int 0)))
13748 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13749 "TARGET_32BIT && optimize_size"
13750 "@
13751 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13752 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13753 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13754 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13755 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13756 #
13757 #
13758 #
13759 #
13760 #"
13761 [(set_attr "type" "compare")
13762 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13764 (define_split
13765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13766 (compare:CC
13767 (plus:SI
13768 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13769 (match_operand:SI 2 "scc_eq_operand" ""))
13770 (match_operand:SI 3 "gpc_reg_operand" ""))
13771 (const_int 0)))
13772 (clobber (match_scratch:SI 4 ""))]
13773 "TARGET_32BIT && optimize_size && reload_completed"
13774 [(set (match_dup 4)
13775 (plus:SI (eq:SI (match_dup 1)
13776 (match_dup 2))
13777 (match_dup 3)))
13778 (set (match_dup 0)
13779 (compare:CC (match_dup 4)
13780 (const_int 0)))]
13781 "")
13783 (define_insn "*plus_eqsi_compare"
13784 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13785 (compare:CC
13786 (plus:SI
13787 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13788 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13789 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13790 (const_int 0)))
13791 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13792 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13793 "TARGET_32BIT && optimize_size"
13794 "@
13795 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13796 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13797 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13798 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13799 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13800 #
13801 #
13802 #
13803 #
13804 #"
13805 [(set_attr "type" "compare")
13806 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13808 (define_split
13809 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13810 (compare:CC
13811 (plus:SI
13812 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13813 (match_operand:SI 2 "scc_eq_operand" ""))
13814 (match_operand:SI 3 "gpc_reg_operand" ""))
13815 (const_int 0)))
13816 (set (match_operand:SI 0 "gpc_reg_operand" "")
13817 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13818 "TARGET_32BIT && optimize_size && reload_completed"
13819 [(set (match_dup 0)
13820 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13821 (set (match_dup 4)
13822 (compare:CC (match_dup 0)
13823 (const_int 0)))]
13824 "")
13826 (define_insn "*neg_eq0<mode>"
13827 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13828 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13829 (const_int 0))))]
13830 ""
13831 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13832 [(set_attr "type" "two")
13833 (set_attr "length" "8")])
13835 (define_insn_and_split "*neg_eq<mode>"
13836 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13837 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13838 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13839 ""
13840 "#"
13841 ""
13842 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13843 {
13844 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13845 {
13846 /* Use output operand as intermediate. */
13847 operands[3] = operands[0];
13849 if (logical_operand (operands[2], <MODE>mode))
13850 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13851 gen_rtx_XOR (<MODE>mode,
13852 operands[1], operands[2])));
13853 else
13854 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13855 gen_rtx_PLUS (<MODE>mode, operands[1],
13856 negate_rtx (<MODE>mode,
13857 operands[2]))));
13858 }
13859 else
13860 operands[3] = operands[1];
13861 })
13863 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13864 ;; since it nabs/sr is just as fast.
13865 (define_insn "*ne0si"
13866 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13867 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13868 (const_int 31)))
13869 (clobber (match_scratch:SI 2 "=&r"))]
13870 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13871 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13872 [(set_attr "type" "two")
13873 (set_attr "length" "8")])
13875 (define_insn "*ne0di"
13876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13877 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13878 (const_int 63)))
13879 (clobber (match_scratch:DI 2 "=&r"))]
13880 "TARGET_64BIT"
13881 "addic %2,%1,-1\;subfe %0,%2,%1"
13882 [(set_attr "type" "two")
13883 (set_attr "length" "8")])
13885 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13886 (define_insn "*plus_ne0si"
13887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13888 (plus:SI (lshiftrt:SI
13889 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13890 (const_int 31))
13891 (match_operand:SI 2 "gpc_reg_operand" "r")))
13892 (clobber (match_scratch:SI 3 "=&r"))]
13893 "TARGET_32BIT"
13894 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13895 [(set_attr "type" "two")
13896 (set_attr "length" "8")])
13898 (define_insn "*plus_ne0di"
13899 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13900 (plus:DI (lshiftrt:DI
13901 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13902 (const_int 63))
13903 (match_operand:DI 2 "gpc_reg_operand" "r")))
13904 (clobber (match_scratch:DI 3 "=&r"))]
13905 "TARGET_64BIT"
13906 "addic %3,%1,-1\;addze %0,%2"
13907 [(set_attr "type" "two")
13908 (set_attr "length" "8")])
13910 (define_insn "*compare_plus_ne0si"
13911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13912 (compare:CC
13913 (plus:SI (lshiftrt:SI
13914 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13915 (const_int 31))
13916 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13917 (const_int 0)))
13918 (clobber (match_scratch:SI 3 "=&r,&r"))
13919 (clobber (match_scratch:SI 4 "=X,&r"))]
13920 "TARGET_32BIT"
13921 "@
13922 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13923 #"
13924 [(set_attr "type" "compare")
13925 (set_attr "length" "8,12")])
13927 (define_split
13928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13929 (compare:CC
13930 (plus:SI (lshiftrt:SI
13931 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13932 (const_int 31))
13933 (match_operand:SI 2 "gpc_reg_operand" ""))
13934 (const_int 0)))
13935 (clobber (match_scratch:SI 3 ""))
13936 (clobber (match_scratch:SI 4 ""))]
13937 "TARGET_32BIT && reload_completed"
13938 [(parallel [(set (match_dup 3)
13939 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13940 (const_int 31))
13941 (match_dup 2)))
13942 (clobber (match_dup 4))])
13943 (set (match_dup 0)
13944 (compare:CC (match_dup 3)
13945 (const_int 0)))]
13946 "")
13948 (define_insn "*compare_plus_ne0di"
13949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13950 (compare:CC
13951 (plus:DI (lshiftrt:DI
13952 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13953 (const_int 63))
13954 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13955 (const_int 0)))
13956 (clobber (match_scratch:DI 3 "=&r,&r"))]
13957 "TARGET_64BIT"
13958 "@
13959 addic %3,%1,-1\;addze. %3,%2
13960 #"
13961 [(set_attr "type" "compare")
13962 (set_attr "length" "8,12")])
13964 (define_split
13965 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13966 (compare:CC
13967 (plus:DI (lshiftrt:DI
13968 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13969 (const_int 63))
13970 (match_operand:DI 2 "gpc_reg_operand" ""))
13971 (const_int 0)))
13972 (clobber (match_scratch:DI 3 ""))]
13973 "TARGET_64BIT && reload_completed"
13974 [(set (match_dup 3)
13975 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13976 (const_int 63))
13977 (match_dup 2)))
13978 (set (match_dup 0)
13979 (compare:CC (match_dup 3)
13980 (const_int 0)))]
13981 "")
13983 (define_insn "*plus_ne0si_compare"
13984 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13985 (compare:CC
13986 (plus:SI (lshiftrt:SI
13987 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13988 (const_int 31))
13989 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13990 (const_int 0)))
13991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13992 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13993 (match_dup 2)))
13994 (clobber (match_scratch:SI 3 "=&r,&r"))]
13995 "TARGET_32BIT"
13996 "@
13997 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13998 #"
13999 [(set_attr "type" "compare")
14000 (set_attr "length" "8,12")])
14002 (define_split
14003 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14004 (compare:CC
14005 (plus:SI (lshiftrt:SI
14006 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14007 (const_int 31))
14008 (match_operand:SI 2 "gpc_reg_operand" ""))
14009 (const_int 0)))
14010 (set (match_operand:SI 0 "gpc_reg_operand" "")
14011 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14012 (match_dup 2)))
14013 (clobber (match_scratch:SI 3 ""))]
14014 "TARGET_32BIT && reload_completed"
14015 [(parallel [(set (match_dup 0)
14016 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14017 (match_dup 2)))
14018 (clobber (match_dup 3))])
14019 (set (match_dup 4)
14020 (compare:CC (match_dup 0)
14021 (const_int 0)))]
14022 "")
14024 (define_insn "*plus_ne0di_compare"
14025 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14026 (compare:CC
14027 (plus:DI (lshiftrt:DI
14028 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14029 (const_int 63))
14030 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14031 (const_int 0)))
14032 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
14033 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14034 (match_dup 2)))
14035 (clobber (match_scratch:DI 3 "=&r,&r"))]
14036 "TARGET_64BIT"
14037 "@
14038 addic %3,%1,-1\;addze. %0,%2
14039 #"
14040 [(set_attr "type" "compare")
14041 (set_attr "length" "8,12")])
14043 (define_split
14044 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
14045 (compare:CC
14046 (plus:DI (lshiftrt:DI
14047 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14048 (const_int 63))
14049 (match_operand:DI 2 "gpc_reg_operand" ""))
14050 (const_int 0)))
14051 (set (match_operand:DI 0 "gpc_reg_operand" "")
14052 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14053 (match_dup 2)))
14054 (clobber (match_scratch:DI 3 ""))]
14055 "TARGET_64BIT && reload_completed"
14056 [(parallel [(set (match_dup 0)
14057 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14058 (match_dup 2)))
14059 (clobber (match_dup 3))])
14060 (set (match_dup 4)
14061 (compare:CC (match_dup 0)
14062 (const_int 0)))]
14063 "")
14065 (define_insn ""
14066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14067 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14068 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
14069 (clobber (match_scratch:SI 3 "=r,X"))]
14070 "TARGET_POWER"
14071 "@
14072 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
14073 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
14074 [(set_attr "length" "12")])
14076 (define_insn ""
14077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14078 (compare:CC
14079 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14080 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14081 (const_int 0)))
14082 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
14083 (le:SI (match_dup 1) (match_dup 2)))
14084 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
14085 "TARGET_POWER"
14086 "@
14087 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14088 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
14089 #
14090 #"
14091 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
14092 (set_attr "length" "12,12,16,16")])
14094 (define_split
14095 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14096 (compare:CC
14097 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14098 (match_operand:SI 2 "reg_or_short_operand" ""))
14099 (const_int 0)))
14100 (set (match_operand:SI 0 "gpc_reg_operand" "")
14101 (le:SI (match_dup 1) (match_dup 2)))
14102 (clobber (match_scratch:SI 3 ""))]
14103 "TARGET_POWER && reload_completed"
14104 [(parallel [(set (match_dup 0)
14105 (le:SI (match_dup 1) (match_dup 2)))
14106 (clobber (match_dup 3))])
14107 (set (match_dup 4)
14108 (compare:CC (match_dup 0)
14109 (const_int 0)))]
14110 "")
14112 (define_insn ""
14113 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14114 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14115 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
14116 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
14117 "TARGET_POWER"
14118 "@
14119 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
14120 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
14121 [(set_attr "length" "12")])
14123 (define_insn ""
14124 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14125 (compare:CC
14126 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14127 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14128 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14129 (const_int 0)))
14130 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14131 "TARGET_POWER"
14132 "@
14133 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14134 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
14135 #
14136 #"
14137 [(set_attr "type" "compare")
14138 (set_attr "length" "12,12,16,16")])
14140 (define_split
14141 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14142 (compare:CC
14143 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14144 (match_operand:SI 2 "reg_or_short_operand" ""))
14145 (match_operand:SI 3 "gpc_reg_operand" ""))
14146 (const_int 0)))
14147 (clobber (match_scratch:SI 4 ""))]
14148 "TARGET_POWER && reload_completed"
14149 [(set (match_dup 4)
14150 (plus:SI (le:SI (match_dup 1) (match_dup 2))
14151 (match_dup 3)))
14152 (set (match_dup 0)
14153 (compare:CC (match_dup 4)
14154 (const_int 0)))]
14155 "")
14157 (define_insn ""
14158 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14159 (compare:CC
14160 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14161 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14162 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14163 (const_int 0)))
14164 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14165 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14166 "TARGET_POWER"
14167 "@
14168 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14169 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
14170 #
14171 #"
14172 [(set_attr "type" "compare")
14173 (set_attr "length" "12,12,16,16")])
14175 (define_split
14176 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14177 (compare:CC
14178 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14179 (match_operand:SI 2 "reg_or_short_operand" ""))
14180 (match_operand:SI 3 "gpc_reg_operand" ""))
14181 (const_int 0)))
14182 (set (match_operand:SI 0 "gpc_reg_operand" "")
14183 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14184 "TARGET_POWER && reload_completed"
14185 [(set (match_dup 0)
14186 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14187 (set (match_dup 4)
14188 (compare:CC (match_dup 0)
14189 (const_int 0)))]
14190 "")
14192 (define_insn ""
14193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14194 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14195 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
14196 "TARGET_POWER"
14197 "@
14198 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
14199 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
14200 [(set_attr "length" "12")])
14202 (define_insn "*leu<mode>"
14203 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14204 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14205 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14206 ""
14207 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14208 [(set_attr "type" "three")
14209 (set_attr "length" "12")])
14211 (define_insn "*leu<mode>_compare"
14212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14213 (compare:CC
14214 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14215 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14216 (const_int 0)))
14217 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14218 (leu:P (match_dup 1) (match_dup 2)))]
14219 ""
14220 "@
14221 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14222 #"
14223 [(set_attr "type" "compare")
14224 (set_attr "length" "12,16")])
14226 (define_split
14227 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14228 (compare:CC
14229 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14230 (match_operand:P 2 "reg_or_short_operand" ""))
14231 (const_int 0)))
14232 (set (match_operand:P 0 "gpc_reg_operand" "")
14233 (leu:P (match_dup 1) (match_dup 2)))]
14234 "reload_completed"
14235 [(set (match_dup 0)
14236 (leu:P (match_dup 1) (match_dup 2)))
14237 (set (match_dup 3)
14238 (compare:CC (match_dup 0)
14239 (const_int 0)))]
14240 "")
14242 (define_insn "*plus_leu<mode>"
14243 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14244 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14245 (match_operand:P 2 "reg_or_short_operand" "rI"))
14246 (match_operand:P 3 "gpc_reg_operand" "r")))]
14247 ""
14248 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
14249 [(set_attr "type" "two")
14250 (set_attr "length" "8")])
14252 (define_insn ""
14253 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14254 (compare:CC
14255 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14256 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14257 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14258 (const_int 0)))
14259 (clobber (match_scratch:SI 4 "=&r,&r"))]
14260 "TARGET_32BIT"
14261 "@
14262 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
14263 #"
14264 [(set_attr "type" "compare")
14265 (set_attr "length" "8,12")])
14267 (define_split
14268 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14269 (compare:CC
14270 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14271 (match_operand:SI 2 "reg_or_short_operand" ""))
14272 (match_operand:SI 3 "gpc_reg_operand" ""))
14273 (const_int 0)))
14274 (clobber (match_scratch:SI 4 ""))]
14275 "TARGET_32BIT && reload_completed"
14276 [(set (match_dup 4)
14277 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14278 (match_dup 3)))
14279 (set (match_dup 0)
14280 (compare:CC (match_dup 4)
14281 (const_int 0)))]
14282 "")
14284 (define_insn ""
14285 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14286 (compare:CC
14287 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14288 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14289 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14290 (const_int 0)))
14291 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14292 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14293 "TARGET_32BIT"
14294 "@
14295 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
14296 #"
14297 [(set_attr "type" "compare")
14298 (set_attr "length" "8,12")])
14300 (define_split
14301 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14302 (compare:CC
14303 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14304 (match_operand:SI 2 "reg_or_short_operand" ""))
14305 (match_operand:SI 3 "gpc_reg_operand" ""))
14306 (const_int 0)))
14307 (set (match_operand:SI 0 "gpc_reg_operand" "")
14308 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14309 "TARGET_32BIT && reload_completed"
14310 [(set (match_dup 0)
14311 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14312 (set (match_dup 4)
14313 (compare:CC (match_dup 0)
14314 (const_int 0)))]
14315 "")
14317 (define_insn "*neg_leu<mode>"
14318 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14319 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14320 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14321 ""
14322 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
14323 [(set_attr "type" "three")
14324 (set_attr "length" "12")])
14326 (define_insn "*and_neg_leu<mode>"
14327 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14328 (and:P (neg:P
14329 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14330 (match_operand:P 2 "reg_or_short_operand" "rI")))
14331 (match_operand:P 3 "gpc_reg_operand" "r")))]
14332 ""
14333 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14334 [(set_attr "type" "three")
14335 (set_attr "length" "12")])
14337 (define_insn ""
14338 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14339 (compare:CC
14340 (and:SI (neg:SI
14341 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14342 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14343 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14344 (const_int 0)))
14345 (clobber (match_scratch:SI 4 "=&r,&r"))]
14346 "TARGET_32BIT"
14347 "@
14348 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14349 #"
14350 [(set_attr "type" "compare")
14351 (set_attr "length" "12,16")])
14353 (define_split
14354 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14355 (compare:CC
14356 (and:SI (neg:SI
14357 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14358 (match_operand:SI 2 "reg_or_short_operand" "")))
14359 (match_operand:SI 3 "gpc_reg_operand" ""))
14360 (const_int 0)))
14361 (clobber (match_scratch:SI 4 ""))]
14362 "TARGET_32BIT && reload_completed"
14363 [(set (match_dup 4)
14364 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14365 (match_dup 3)))
14366 (set (match_dup 0)
14367 (compare:CC (match_dup 4)
14368 (const_int 0)))]
14369 "")
14371 (define_insn ""
14372 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14373 (compare:CC
14374 (and:SI (neg:SI
14375 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14376 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14377 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14378 (const_int 0)))
14379 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14380 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14381 "TARGET_32BIT"
14382 "@
14383 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14384 #"
14385 [(set_attr "type" "compare")
14386 (set_attr "length" "12,16")])
14388 (define_split
14389 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14390 (compare:CC
14391 (and:SI (neg:SI
14392 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14393 (match_operand:SI 2 "reg_or_short_operand" "")))
14394 (match_operand:SI 3 "gpc_reg_operand" ""))
14395 (const_int 0)))
14396 (set (match_operand:SI 0 "gpc_reg_operand" "")
14397 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14398 "TARGET_32BIT && reload_completed"
14399 [(set (match_dup 0)
14400 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14401 (match_dup 3)))
14402 (set (match_dup 4)
14403 (compare:CC (match_dup 0)
14404 (const_int 0)))]
14405 "")
14407 (define_insn ""
14408 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14409 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14410 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14411 "TARGET_POWER"
14412 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14413 [(set_attr "length" "12")])
14415 (define_insn ""
14416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14417 (compare:CC
14418 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14419 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14420 (const_int 0)))
14421 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14422 (lt:SI (match_dup 1) (match_dup 2)))]
14423 "TARGET_POWER"
14424 "@
14425 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14426 #"
14427 [(set_attr "type" "delayed_compare")
14428 (set_attr "length" "12,16")])
14430 (define_split
14431 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14432 (compare:CC
14433 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14434 (match_operand:SI 2 "reg_or_short_operand" ""))
14435 (const_int 0)))
14436 (set (match_operand:SI 0 "gpc_reg_operand" "")
14437 (lt:SI (match_dup 1) (match_dup 2)))]
14438 "TARGET_POWER && reload_completed"
14439 [(set (match_dup 0)
14440 (lt:SI (match_dup 1) (match_dup 2)))
14441 (set (match_dup 3)
14442 (compare:CC (match_dup 0)
14443 (const_int 0)))]
14444 "")
14446 (define_insn ""
14447 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14448 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14449 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14450 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14451 "TARGET_POWER"
14452 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14453 [(set_attr "length" "12")])
14455 (define_insn ""
14456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14457 (compare:CC
14458 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14459 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14460 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14461 (const_int 0)))
14462 (clobber (match_scratch:SI 4 "=&r,&r"))]
14463 "TARGET_POWER"
14464 "@
14465 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14466 #"
14467 [(set_attr "type" "compare")
14468 (set_attr "length" "12,16")])
14470 (define_split
14471 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14472 (compare:CC
14473 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14474 (match_operand:SI 2 "reg_or_short_operand" ""))
14475 (match_operand:SI 3 "gpc_reg_operand" ""))
14476 (const_int 0)))
14477 (clobber (match_scratch:SI 4 ""))]
14478 "TARGET_POWER && reload_completed"
14479 [(set (match_dup 4)
14480 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14481 (match_dup 3)))
14482 (set (match_dup 0)
14483 (compare:CC (match_dup 4)
14484 (const_int 0)))]
14485 "")
14487 (define_insn ""
14488 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14489 (compare:CC
14490 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14491 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14492 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14493 (const_int 0)))
14494 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14495 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14496 "TARGET_POWER"
14497 "@
14498 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14499 #"
14500 [(set_attr "type" "compare")
14501 (set_attr "length" "12,16")])
14503 (define_split
14504 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14505 (compare:CC
14506 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14507 (match_operand:SI 2 "reg_or_short_operand" ""))
14508 (match_operand:SI 3 "gpc_reg_operand" ""))
14509 (const_int 0)))
14510 (set (match_operand:SI 0 "gpc_reg_operand" "")
14511 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14512 "TARGET_POWER && reload_completed"
14513 [(set (match_dup 0)
14514 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14515 (set (match_dup 4)
14516 (compare:CC (match_dup 0)
14517 (const_int 0)))]
14518 "")
14520 (define_insn ""
14521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14522 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14523 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14524 "TARGET_POWER"
14525 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14526 [(set_attr "length" "12")])
14528 (define_insn_and_split "*ltu<mode>"
14529 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14530 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14531 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14532 ""
14533 "#"
14534 ""
14535 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14536 (set (match_dup 0) (neg:P (match_dup 0)))]
14537 "")
14539 (define_insn_and_split "*ltu<mode>_compare"
14540 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14541 (compare:CC
14542 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14543 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14544 (const_int 0)))
14545 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14546 (ltu:P (match_dup 1) (match_dup 2)))]
14547 ""
14548 "#"
14549 ""
14550 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14551 (parallel [(set (match_dup 3)
14552 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14553 (set (match_dup 0) (neg:P (match_dup 0)))])]
14554 "")
14556 (define_insn_and_split "*plus_ltu<mode>"
14557 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14558 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14559 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14560 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14561 ""
14562 "#"
14563 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14564 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14565 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14566 "")
14568 (define_insn_and_split "*plus_ltu<mode>_compare"
14569 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14570 (compare:CC
14571 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14572 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14573 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14574 (const_int 0)))
14575 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14576 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14577 ""
14578 "#"
14579 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14580 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14581 (parallel [(set (match_dup 4)
14582 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14583 (const_int 0)))
14584 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14585 "")
14587 (define_insn "*neg_ltu<mode>"
14588 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14589 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14590 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14591 ""
14592 "@
14593 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14594 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14595 [(set_attr "type" "two")
14596 (set_attr "length" "8")])
14598 (define_insn ""
14599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14600 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14601 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14602 (clobber (match_scratch:SI 3 "=r"))]
14603 "TARGET_POWER"
14604 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14605 [(set_attr "length" "12")])
14607 (define_insn ""
14608 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14609 (compare:CC
14610 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14611 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14612 (const_int 0)))
14613 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14614 (ge:SI (match_dup 1) (match_dup 2)))
14615 (clobber (match_scratch:SI 3 "=r,r"))]
14616 "TARGET_POWER"
14617 "@
14618 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14619 #"
14620 [(set_attr "type" "compare")
14621 (set_attr "length" "12,16")])
14623 (define_split
14624 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14625 (compare:CC
14626 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14627 (match_operand:SI 2 "reg_or_short_operand" ""))
14628 (const_int 0)))
14629 (set (match_operand:SI 0 "gpc_reg_operand" "")
14630 (ge:SI (match_dup 1) (match_dup 2)))
14631 (clobber (match_scratch:SI 3 ""))]
14632 "TARGET_POWER && reload_completed"
14633 [(parallel [(set (match_dup 0)
14634 (ge:SI (match_dup 1) (match_dup 2)))
14635 (clobber (match_dup 3))])
14636 (set (match_dup 4)
14637 (compare:CC (match_dup 0)
14638 (const_int 0)))]
14639 "")
14641 (define_insn ""
14642 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14643 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14644 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14645 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14646 "TARGET_POWER"
14647 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14648 [(set_attr "length" "12")])
14650 (define_insn ""
14651 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14652 (compare:CC
14653 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14654 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14655 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14656 (const_int 0)))
14657 (clobber (match_scratch:SI 4 "=&r,&r"))]
14658 "TARGET_POWER"
14659 "@
14660 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14661 #"
14662 [(set_attr "type" "compare")
14663 (set_attr "length" "12,16")])
14665 (define_split
14666 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14667 (compare:CC
14668 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14669 (match_operand:SI 2 "reg_or_short_operand" ""))
14670 (match_operand:SI 3 "gpc_reg_operand" ""))
14671 (const_int 0)))
14672 (clobber (match_scratch:SI 4 ""))]
14673 "TARGET_POWER && reload_completed"
14674 [(set (match_dup 4)
14675 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14676 (match_dup 3)))
14677 (set (match_dup 0)
14678 (compare:CC (match_dup 4)
14679 (const_int 0)))]
14680 "")
14682 (define_insn ""
14683 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14684 (compare:CC
14685 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14686 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14687 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14688 (const_int 0)))
14689 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14690 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14691 "TARGET_POWER"
14692 "@
14693 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14694 #"
14695 [(set_attr "type" "compare")
14696 (set_attr "length" "12,16")])
14698 (define_split
14699 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14700 (compare:CC
14701 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14702 (match_operand:SI 2 "reg_or_short_operand" ""))
14703 (match_operand:SI 3 "gpc_reg_operand" ""))
14704 (const_int 0)))
14705 (set (match_operand:SI 0 "gpc_reg_operand" "")
14706 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14707 "TARGET_POWER && reload_completed"
14708 [(set (match_dup 0)
14709 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14710 (set (match_dup 4)
14711 (compare:CC (match_dup 0)
14712 (const_int 0)))]
14713 "")
14715 (define_insn ""
14716 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14717 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14718 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14719 "TARGET_POWER"
14720 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14721 [(set_attr "length" "12")])
14723 (define_insn "*geu<mode>"
14724 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14725 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14726 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14727 ""
14728 "@
14729 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14730 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14731 [(set_attr "type" "three")
14732 (set_attr "length" "12")])
14734 (define_insn "*geu<mode>_compare"
14735 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14736 (compare:CC
14737 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14738 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14739 (const_int 0)))
14740 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14741 (geu:P (match_dup 1) (match_dup 2)))]
14742 ""
14743 "@
14744 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14745 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14746 #
14747 #"
14748 [(set_attr "type" "compare")
14749 (set_attr "length" "12,12,16,16")])
14751 (define_split
14752 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14753 (compare:CC
14754 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14755 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14756 (const_int 0)))
14757 (set (match_operand:P 0 "gpc_reg_operand" "")
14758 (geu:P (match_dup 1) (match_dup 2)))]
14759 "reload_completed"
14760 [(set (match_dup 0)
14761 (geu:P (match_dup 1) (match_dup 2)))
14762 (set (match_dup 3)
14763 (compare:CC (match_dup 0)
14764 (const_int 0)))]
14765 "")
14767 (define_insn "*plus_geu<mode>"
14768 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14769 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14770 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14771 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14772 ""
14773 "@
14774 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14775 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14776 [(set_attr "type" "two")
14777 (set_attr "length" "8")])
14779 (define_insn ""
14780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14781 (compare:CC
14782 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14783 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14784 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14785 (const_int 0)))
14786 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14787 "TARGET_32BIT"
14788 "@
14789 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14790 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14791 #
14792 #"
14793 [(set_attr "type" "compare")
14794 (set_attr "length" "8,8,12,12")])
14796 (define_split
14797 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14798 (compare:CC
14799 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14800 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14801 (match_operand:SI 3 "gpc_reg_operand" ""))
14802 (const_int 0)))
14803 (clobber (match_scratch:SI 4 ""))]
14804 "TARGET_32BIT && reload_completed"
14805 [(set (match_dup 4)
14806 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14807 (match_dup 3)))
14808 (set (match_dup 0)
14809 (compare:CC (match_dup 4)
14810 (const_int 0)))]
14811 "")
14813 (define_insn ""
14814 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14815 (compare:CC
14816 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14817 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14818 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14819 (const_int 0)))
14820 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14821 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14822 "TARGET_32BIT"
14823 "@
14824 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14825 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14826 #
14827 #"
14828 [(set_attr "type" "compare")
14829 (set_attr "length" "8,8,12,12")])
14831 (define_split
14832 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14833 (compare:CC
14834 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14835 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14836 (match_operand:SI 3 "gpc_reg_operand" ""))
14837 (const_int 0)))
14838 (set (match_operand:SI 0 "gpc_reg_operand" "")
14839 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14840 "TARGET_32BIT && reload_completed"
14841 [(set (match_dup 0)
14842 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14843 (set (match_dup 4)
14844 (compare:CC (match_dup 0)
14845 (const_int 0)))]
14846 "")
14848 (define_insn "*neg_geu<mode>"
14849 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14850 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14851 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14852 ""
14853 "@
14854 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14855 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14856 [(set_attr "type" "three")
14857 (set_attr "length" "12")])
14859 (define_insn "*and_neg_geu<mode>"
14860 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14861 (and:P (neg:P
14862 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14863 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14864 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14865 ""
14866 "@
14867 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14868 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14869 [(set_attr "type" "three")
14870 (set_attr "length" "12")])
14872 (define_insn ""
14873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14874 (compare:CC
14875 (and:SI (neg:SI
14876 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14877 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14878 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14879 (const_int 0)))
14880 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14881 "TARGET_32BIT"
14882 "@
14883 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14884 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14885 #
14886 #"
14887 [(set_attr "type" "compare")
14888 (set_attr "length" "12,12,16,16")])
14890 (define_split
14891 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14892 (compare:CC
14893 (and:SI (neg:SI
14894 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14895 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14896 (match_operand:SI 3 "gpc_reg_operand" ""))
14897 (const_int 0)))
14898 (clobber (match_scratch:SI 4 ""))]
14899 "TARGET_32BIT && reload_completed"
14900 [(set (match_dup 4)
14901 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14902 (match_dup 3)))
14903 (set (match_dup 0)
14904 (compare:CC (match_dup 4)
14905 (const_int 0)))]
14906 "")
14908 (define_insn ""
14909 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14910 (compare:CC
14911 (and:SI (neg:SI
14912 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14913 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14914 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14915 (const_int 0)))
14916 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14917 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14918 "TARGET_32BIT"
14919 "@
14920 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14921 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14922 #
14923 #"
14924 [(set_attr "type" "compare")
14925 (set_attr "length" "12,12,16,16")])
14927 (define_split
14928 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14929 (compare:CC
14930 (and:SI (neg:SI
14931 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14932 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14933 (match_operand:SI 3 "gpc_reg_operand" ""))
14934 (const_int 0)))
14935 (set (match_operand:SI 0 "gpc_reg_operand" "")
14936 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14937 "TARGET_32BIT && reload_completed"
14938 [(set (match_dup 0)
14939 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14940 (set (match_dup 4)
14941 (compare:CC (match_dup 0)
14942 (const_int 0)))]
14943 "")
14945 (define_insn ""
14946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14947 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14948 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14949 "TARGET_POWER"
14950 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14951 [(set_attr "length" "12")])
14953 (define_insn ""
14954 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14955 (compare:CC
14956 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14957 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14958 (const_int 0)))
14959 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14960 (gt:SI (match_dup 1) (match_dup 2)))]
14961 "TARGET_POWER"
14962 "@
14963 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14964 #"
14965 [(set_attr "type" "delayed_compare")
14966 (set_attr "length" "12,16")])
14968 (define_split
14969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14970 (compare:CC
14971 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14972 (match_operand:SI 2 "reg_or_short_operand" ""))
14973 (const_int 0)))
14974 (set (match_operand:SI 0 "gpc_reg_operand" "")
14975 (gt:SI (match_dup 1) (match_dup 2)))]
14976 "TARGET_POWER && reload_completed"
14977 [(set (match_dup 0)
14978 (gt:SI (match_dup 1) (match_dup 2)))
14979 (set (match_dup 3)
14980 (compare:CC (match_dup 0)
14981 (const_int 0)))]
14982 "")
14984 (define_insn "*plus_gt0<mode>"
14985 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14986 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14987 (const_int 0))
14988 (match_operand:P 2 "gpc_reg_operand" "r")))]
14989 ""
14990 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14991 [(set_attr "type" "three")
14992 (set_attr "length" "12")])
14994 (define_insn ""
14995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14996 (compare:CC
14997 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14998 (const_int 0))
14999 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15000 (const_int 0)))
15001 (clobber (match_scratch:SI 3 "=&r,&r"))]
15002 "TARGET_32BIT"
15003 "@
15004 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
15005 #"
15006 [(set_attr "type" "compare")
15007 (set_attr "length" "12,16")])
15009 (define_split
15010 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15011 (compare:CC
15012 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15013 (const_int 0))
15014 (match_operand:SI 2 "gpc_reg_operand" ""))
15015 (const_int 0)))
15016 (clobber (match_scratch:SI 3 ""))]
15017 "TARGET_32BIT && reload_completed"
15018 [(set (match_dup 3)
15019 (plus:SI (gt:SI (match_dup 1) (const_int 0))
15020 (match_dup 2)))
15021 (set (match_dup 0)
15022 (compare:CC (match_dup 3)
15023 (const_int 0)))]
15024 "")
15026 (define_insn ""
15027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15028 (compare:CC
15029 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15030 (const_int 0))
15031 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15032 (const_int 0)))
15033 (clobber (match_scratch:DI 3 "=&r,&r"))]
15034 "TARGET_64BIT"
15035 "@
15036 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
15037 #"
15038 [(set_attr "type" "compare")
15039 (set_attr "length" "12,16")])
15041 (define_split
15042 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
15043 (compare:CC
15044 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15045 (const_int 0))
15046 (match_operand:DI 2 "gpc_reg_operand" ""))
15047 (const_int 0)))
15048 (clobber (match_scratch:DI 3 ""))]
15049 "TARGET_64BIT && reload_completed"
15050 [(set (match_dup 3)
15051 (plus:DI (gt:DI (match_dup 1) (const_int 0))
15052 (match_dup 2)))
15053 (set (match_dup 0)
15054 (compare:CC (match_dup 3)
15055 (const_int 0)))]
15056 "")
15058 (define_insn ""
15059 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15060 (compare:CC
15061 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15062 (const_int 0))
15063 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15064 (const_int 0)))
15065 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15066 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15067 "TARGET_32BIT"
15068 "@
15069 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
15070 #"
15071 [(set_attr "type" "compare")
15072 (set_attr "length" "12,16")])
15074 (define_split
15075 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15076 (compare:CC
15077 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15078 (const_int 0))
15079 (match_operand:SI 2 "gpc_reg_operand" ""))
15080 (const_int 0)))
15081 (set (match_operand:SI 0 "gpc_reg_operand" "")
15082 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15083 "TARGET_32BIT && reload_completed"
15084 [(set (match_dup 0)
15085 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
15086 (set (match_dup 3)
15087 (compare:CC (match_dup 0)
15088 (const_int 0)))]
15089 "")
15091 (define_insn ""
15092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15093 (compare:CC
15094 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15095 (const_int 0))
15096 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15097 (const_int 0)))
15098 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
15099 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15100 "TARGET_64BIT"
15101 "@
15102 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
15103 #"
15104 [(set_attr "type" "compare")
15105 (set_attr "length" "12,16")])
15107 (define_split
15108 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
15109 (compare:CC
15110 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15111 (const_int 0))
15112 (match_operand:DI 2 "gpc_reg_operand" ""))
15113 (const_int 0)))
15114 (set (match_operand:DI 0 "gpc_reg_operand" "")
15115 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15116 "TARGET_64BIT && reload_completed"
15117 [(set (match_dup 0)
15118 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
15119 (set (match_dup 3)
15120 (compare:CC (match_dup 0)
15121 (const_int 0)))]
15122 "")
15124 (define_insn ""
15125 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
15126 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15127 (match_operand:SI 2 "reg_or_short_operand" "r"))
15128 (match_operand:SI 3 "gpc_reg_operand" "r")))]
15129 "TARGET_POWER"
15130 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
15131 [(set_attr "length" "12")])
15133 (define_insn ""
15134 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15135 (compare:CC
15136 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15137 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15138 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15139 (const_int 0)))
15140 (clobber (match_scratch:SI 4 "=&r,&r"))]
15141 "TARGET_POWER"
15142 "@
15143 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
15144 #"
15145 [(set_attr "type" "compare")
15146 (set_attr "length" "12,16")])
15148 (define_split
15149 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15150 (compare:CC
15151 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15152 (match_operand:SI 2 "reg_or_short_operand" ""))
15153 (match_operand:SI 3 "gpc_reg_operand" ""))
15154 (const_int 0)))
15155 (clobber (match_scratch:SI 4 ""))]
15156 "TARGET_POWER && reload_completed"
15157 [(set (match_dup 4)
15158 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15159 (set (match_dup 0)
15160 (compare:CC (match_dup 4)
15161 (const_int 0)))]
15162 "")
15164 (define_insn ""
15165 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
15166 (compare:CC
15167 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15168 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15169 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15170 (const_int 0)))
15171 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15172 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15173 "TARGET_POWER"
15174 "@
15175 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
15176 #"
15177 [(set_attr "type" "compare")
15178 (set_attr "length" "12,16")])
15180 (define_split
15181 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15182 (compare:CC
15183 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15184 (match_operand:SI 2 "reg_or_short_operand" ""))
15185 (match_operand:SI 3 "gpc_reg_operand" ""))
15186 (const_int 0)))
15187 (set (match_operand:SI 0 "gpc_reg_operand" "")
15188 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15189 "TARGET_POWER && reload_completed"
15190 [(set (match_dup 0)
15191 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15192 (set (match_dup 4)
15193 (compare:CC (match_dup 0)
15194 (const_int 0)))]
15195 "")
15197 (define_insn ""
15198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15199 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15200 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
15201 "TARGET_POWER"
15202 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
15203 [(set_attr "length" "12")])
15205 (define_insn_and_split "*gtu<mode>"
15206 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15207 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15208 (match_operand:P 2 "reg_or_short_operand" "rI")))]
15209 ""
15210 "#"
15211 ""
15212 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15213 (set (match_dup 0) (neg:P (match_dup 0)))]
15214 "")
15216 (define_insn_and_split "*gtu<mode>_compare"
15217 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15218 (compare:CC
15219 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
15220 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
15221 (const_int 0)))
15222 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
15223 (gtu:P (match_dup 1) (match_dup 2)))]
15224 ""
15225 "#"
15226 ""
15227 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15228 (parallel [(set (match_dup 3)
15229 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
15230 (set (match_dup 0) (neg:P (match_dup 0)))])]
15231 "")
15233 (define_insn_and_split "*plus_gtu<mode>"
15234 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15235 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15236 (match_operand:P 2 "reg_or_short_operand" "rI"))
15237 (match_operand:P 3 "reg_or_short_operand" "rI")))]
15238 ""
15239 "#"
15240 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15241 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15242 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
15243 "")
15245 (define_insn_and_split "*plus_gtu<mode>_compare"
15246 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
15247 (compare:CC
15248 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
15249 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
15250 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
15251 (const_int 0)))
15252 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
15253 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
15254 ""
15255 "#"
15256 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15257 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15258 (parallel [(set (match_dup 4)
15259 (compare:CC (minus:P (match_dup 3) (match_dup 0))
15260 (const_int 0)))
15261 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
15262 "")
15264 (define_insn "*neg_gtu<mode>"
15265 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15266 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15267 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
15268 ""
15269 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
15270 [(set_attr "type" "two")
15271 (set_attr "length" "8")])
15273 \f
15274 ;; Define both directions of branch and return. If we need a reload
15275 ;; register, we'd rather use CR0 since it is much easier to copy a
15276 ;; register CC value to there.
15278 (define_insn ""
15279 [(set (pc)
15280 (if_then_else (match_operator 1 "branch_comparison_operator"
15281 [(match_operand 2
15282 "cc_reg_operand" "y")
15283 (const_int 0)])
15284 (label_ref (match_operand 0 "" ""))
15285 (pc)))]
15286 ""
15287 "*
15288 {
15289 return output_cbranch (operands[1], \"%l0\", 0, insn);
15290 }"
15291 [(set_attr "type" "branch")])
15293 (define_insn ""
15294 [(set (pc)
15295 (if_then_else (match_operator 0 "branch_comparison_operator"
15296 [(match_operand 1
15297 "cc_reg_operand" "y")
15298 (const_int 0)])
15299 (any_return)
15300 (pc)))]
15301 "<return_pred>"
15302 "*
15303 {
15304 return output_cbranch (operands[0], NULL, 0, insn);
15305 }"
15306 [(set_attr "type" "jmpreg")
15307 (set_attr "length" "4")])
15309 (define_insn ""
15310 [(set (pc)
15311 (if_then_else (match_operator 1 "branch_comparison_operator"
15312 [(match_operand 2
15313 "cc_reg_operand" "y")
15314 (const_int 0)])
15315 (pc)
15316 (label_ref (match_operand 0 "" ""))))]
15317 ""
15318 "*
15319 {
15320 return output_cbranch (operands[1], \"%l0\", 1, insn);
15321 }"
15322 [(set_attr "type" "branch")])
15324 (define_insn ""
15325 [(set (pc)
15326 (if_then_else (match_operator 0 "branch_comparison_operator"
15327 [(match_operand 1
15328 "cc_reg_operand" "y")
15329 (const_int 0)])
15330 (pc)
15331 (any_return)))]
15332 "<return_pred>"
15333 "*
15334 {
15335 return output_cbranch (operands[0], NULL, 1, insn);
15336 }"
15337 [(set_attr "type" "jmpreg")
15338 (set_attr "length" "4")])
15340 ;; Logic on condition register values.
15342 ; This pattern matches things like
15343 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
15344 ; (eq:SI (reg:CCFP 68) (const_int 0)))
15345 ; (const_int 1)))
15346 ; which are generated by the branch logic.
15347 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
15349 (define_insn "*cceq_ior_compare"
15350 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15351 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
15352 [(match_operator:SI 2
15353 "branch_positive_comparison_operator"
15354 [(match_operand 3
15355 "cc_reg_operand" "y,y")
15356 (const_int 0)])
15357 (match_operator:SI 4
15358 "branch_positive_comparison_operator"
15359 [(match_operand 5
15360 "cc_reg_operand" "0,y")
15361 (const_int 0)])])
15362 (const_int 1)))]
15363 ""
15364 "cr%q1 %E0,%j2,%j4"
15365 [(set_attr "type" "cr_logical,delayed_cr")])
15367 ; Why is the constant -1 here, but 1 in the previous pattern?
15368 ; Because ~1 has all but the low bit set.
15369 (define_insn ""
15370 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15371 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15372 [(not:SI (match_operator:SI 2
15373 "branch_positive_comparison_operator"
15374 [(match_operand 3
15375 "cc_reg_operand" "y,y")
15376 (const_int 0)]))
15377 (match_operator:SI 4
15378 "branch_positive_comparison_operator"
15379 [(match_operand 5
15380 "cc_reg_operand" "0,y")
15381 (const_int 0)])])
15382 (const_int -1)))]
15383 ""
15384 "cr%q1 %E0,%j2,%j4"
15385 [(set_attr "type" "cr_logical,delayed_cr")])
15387 (define_insn "*cceq_rev_compare"
15388 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15389 (compare:CCEQ (match_operator:SI 1
15390 "branch_positive_comparison_operator"
15391 [(match_operand 2
15392 "cc_reg_operand" "0,y")
15393 (const_int 0)])
15394 (const_int 0)))]
15395 ""
15396 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15397 [(set_attr "type" "cr_logical,delayed_cr")])
15399 ;; If we are comparing the result of two comparisons, this can be done
15400 ;; using creqv or crxor.
15402 (define_insn_and_split ""
15403 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15404 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15405 [(match_operand 2 "cc_reg_operand" "y")
15406 (const_int 0)])
15407 (match_operator 3 "branch_comparison_operator"
15408 [(match_operand 4 "cc_reg_operand" "y")
15409 (const_int 0)])))]
15410 ""
15411 "#"
15412 ""
15413 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15414 (match_dup 5)))]
15415 "
15416 {
15417 int positive_1, positive_2;
15419 positive_1 = branch_positive_comparison_operator (operands[1],
15420 GET_MODE (operands[1]));
15421 positive_2 = branch_positive_comparison_operator (operands[3],
15422 GET_MODE (operands[3]));
15424 if (! positive_1)
15425 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15426 GET_CODE (operands[1])),
15427 SImode,
15428 operands[2], const0_rtx);
15429 else if (GET_MODE (operands[1]) != SImode)
15430 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15431 operands[2], const0_rtx);
15433 if (! positive_2)
15434 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15435 GET_CODE (operands[3])),
15436 SImode,
15437 operands[4], const0_rtx);
15438 else if (GET_MODE (operands[3]) != SImode)
15439 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15440 operands[4], const0_rtx);
15442 if (positive_1 == positive_2)
15443 {
15444 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15445 operands[5] = constm1_rtx;
15446 }
15447 else
15448 {
15449 operands[5] = const1_rtx;
15450 }
15451 }")
15453 ;; Unconditional branch and return.
15455 (define_insn "jump"
15456 [(set (pc)
15457 (label_ref (match_operand 0 "" "")))]
15458 ""
15459 "b %l0"
15460 [(set_attr "type" "branch")])
15462 (define_insn "<return_str>return"
15463 [(any_return)]
15464 "<return_pred>"
15465 "{br|blr}"
15466 [(set_attr "type" "jmpreg")])
15468 (define_expand "indirect_jump"
15469 [(set (pc) (match_operand 0 "register_operand" ""))])
15471 (define_insn "*indirect_jump<mode>"
15472 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15473 ""
15474 "@
15475 bctr
15476 {br|blr}"
15477 [(set_attr "type" "jmpreg")])
15479 ;; Table jump for switch statements:
15480 (define_expand "tablejump"
15481 [(use (match_operand 0 "" ""))
15482 (use (label_ref (match_operand 1 "" "")))]
15483 ""
15484 "
15485 {
15486 if (TARGET_32BIT)
15487 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15488 else
15489 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15490 DONE;
15491 }")
15493 (define_expand "tablejumpsi"
15494 [(set (match_dup 3)
15495 (plus:SI (match_operand:SI 0 "" "")
15496 (match_dup 2)))
15497 (parallel [(set (pc) (match_dup 3))
15498 (use (label_ref (match_operand 1 "" "")))])]
15499 "TARGET_32BIT"
15500 "
15501 { operands[0] = force_reg (SImode, operands[0]);
15502 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15503 operands[3] = gen_reg_rtx (SImode);
15504 }")
15506 (define_expand "tablejumpdi"
15507 [(set (match_dup 4)
15508 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15509 (set (match_dup 3)
15510 (plus:DI (match_dup 4)
15511 (match_dup 2)))
15512 (parallel [(set (pc) (match_dup 3))
15513 (use (label_ref (match_operand 1 "" "")))])]
15514 "TARGET_64BIT"
15515 "
15516 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15517 operands[3] = gen_reg_rtx (DImode);
15518 operands[4] = gen_reg_rtx (DImode);
15519 }")
15521 (define_insn "*tablejump<mode>_internal1"
15522 [(set (pc)
15523 (match_operand:P 0 "register_operand" "c,*l"))
15524 (use (label_ref (match_operand 1 "" "")))]
15525 ""
15526 "@
15527 bctr
15528 {br|blr}"
15529 [(set_attr "type" "jmpreg")])
15531 (define_insn "nop"
15532 [(const_int 0)]
15533 ""
15534 "{cror 0,0,0|nop}")
15535 \f
15536 ;; Define the subtract-one-and-jump insns, starting with the template
15537 ;; so loop.c knows what to generate.
15539 (define_expand "doloop_end"
15540 [(use (match_operand 0 "" "")) ; loop pseudo
15541 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15542 (use (match_operand 2 "" "")) ; max iterations
15543 (use (match_operand 3 "" "")) ; loop level
15544 (use (match_operand 4 "" ""))] ; label
15545 ""
15546 "
15547 {
15548 /* Only use this on innermost loops. */
15549 if (INTVAL (operands[3]) > 1)
15550 FAIL;
15551 if (TARGET_64BIT)
15552 {
15553 if (GET_MODE (operands[0]) != DImode)
15554 FAIL;
15555 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15556 }
15557 else
15558 {
15559 if (GET_MODE (operands[0]) != SImode)
15560 FAIL;
15561 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15562 }
15563 DONE;
15564 }")
15566 (define_expand "ctr<mode>"
15567 [(parallel [(set (pc)
15568 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15569 (const_int 1))
15570 (label_ref (match_operand 1 "" ""))
15571 (pc)))
15572 (set (match_dup 0)
15573 (plus:P (match_dup 0)
15574 (const_int -1)))
15575 (clobber (match_scratch:CC 2 ""))
15576 (clobber (match_scratch:P 3 ""))])]
15577 ""
15578 "")
15580 ;; We need to be able to do this for any operand, including MEM, or we
15581 ;; will cause reload to blow up since we don't allow output reloads on
15582 ;; JUMP_INSNs.
15583 ;; For the length attribute to be calculated correctly, the
15584 ;; label MUST be operand 0.
15586 (define_insn "*ctr<mode>_internal1"
15587 [(set (pc)
15588 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15589 (const_int 1))
15590 (label_ref (match_operand 0 "" ""))
15591 (pc)))
15592 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15593 (plus:P (match_dup 1)
15594 (const_int -1)))
15595 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15596 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15597 ""
15598 "*
15599 {
15600 if (which_alternative != 0)
15601 return \"#\";
15602 else if (get_attr_length (insn) == 4)
15603 return \"{bdn|bdnz} %l0\";
15604 else
15605 return \"bdz $+8\;b %l0\";
15606 }"
15607 [(set_attr "type" "branch")
15608 (set_attr "length" "*,12,16,16")])
15610 (define_insn "*ctr<mode>_internal2"
15611 [(set (pc)
15612 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15613 (const_int 1))
15614 (pc)
15615 (label_ref (match_operand 0 "" ""))))
15616 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15617 (plus:P (match_dup 1)
15618 (const_int -1)))
15619 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15620 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15621 ""
15622 "*
15623 {
15624 if (which_alternative != 0)
15625 return \"#\";
15626 else if (get_attr_length (insn) == 4)
15627 return \"bdz %l0\";
15628 else
15629 return \"{bdn|bdnz} $+8\;b %l0\";
15630 }"
15631 [(set_attr "type" "branch")
15632 (set_attr "length" "*,12,16,16")])
15634 ;; Similar but use EQ
15636 (define_insn "*ctr<mode>_internal5"
15637 [(set (pc)
15638 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15639 (const_int 1))
15640 (label_ref (match_operand 0 "" ""))
15641 (pc)))
15642 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15643 (plus:P (match_dup 1)
15644 (const_int -1)))
15645 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15646 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15647 ""
15648 "*
15649 {
15650 if (which_alternative != 0)
15651 return \"#\";
15652 else if (get_attr_length (insn) == 4)
15653 return \"bdz %l0\";
15654 else
15655 return \"{bdn|bdnz} $+8\;b %l0\";
15656 }"
15657 [(set_attr "type" "branch")
15658 (set_attr "length" "*,12,16,16")])
15660 (define_insn "*ctr<mode>_internal6"
15661 [(set (pc)
15662 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15663 (const_int 1))
15664 (pc)
15665 (label_ref (match_operand 0 "" ""))))
15666 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15667 (plus:P (match_dup 1)
15668 (const_int -1)))
15669 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15670 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15671 ""
15672 "*
15673 {
15674 if (which_alternative != 0)
15675 return \"#\";
15676 else if (get_attr_length (insn) == 4)
15677 return \"{bdn|bdnz} %l0\";
15678 else
15679 return \"bdz $+8\;b %l0\";
15680 }"
15681 [(set_attr "type" "branch")
15682 (set_attr "length" "*,12,16,16")])
15684 ;; Now the splitters if we could not allocate the CTR register
15686 (define_split
15687 [(set (pc)
15688 (if_then_else (match_operator 2 "comparison_operator"
15689 [(match_operand:P 1 "gpc_reg_operand" "")
15690 (const_int 1)])
15691 (match_operand 5 "" "")
15692 (match_operand 6 "" "")))
15693 (set (match_operand:P 0 "gpc_reg_operand" "")
15694 (plus:P (match_dup 1) (const_int -1)))
15695 (clobber (match_scratch:CC 3 ""))
15696 (clobber (match_scratch:P 4 ""))]
15697 "reload_completed"
15698 [(parallel [(set (match_dup 3)
15699 (compare:CC (plus:P (match_dup 1)
15700 (const_int -1))
15701 (const_int 0)))
15702 (set (match_dup 0)
15703 (plus:P (match_dup 1)
15704 (const_int -1)))])
15705 (set (pc) (if_then_else (match_dup 7)
15706 (match_dup 5)
15707 (match_dup 6)))]
15708 "
15709 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15710 operands[3], const0_rtx); }")
15712 (define_split
15713 [(set (pc)
15714 (if_then_else (match_operator 2 "comparison_operator"
15715 [(match_operand:P 1 "gpc_reg_operand" "")
15716 (const_int 1)])
15717 (match_operand 5 "" "")
15718 (match_operand 6 "" "")))
15719 (set (match_operand:P 0 "nonimmediate_operand" "")
15720 (plus:P (match_dup 1) (const_int -1)))
15721 (clobber (match_scratch:CC 3 ""))
15722 (clobber (match_scratch:P 4 ""))]
15723 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15724 [(parallel [(set (match_dup 3)
15725 (compare:CC (plus:P (match_dup 1)
15726 (const_int -1))
15727 (const_int 0)))
15728 (set (match_dup 4)
15729 (plus:P (match_dup 1)
15730 (const_int -1)))])
15731 (set (match_dup 0)
15732 (match_dup 4))
15733 (set (pc) (if_then_else (match_dup 7)
15734 (match_dup 5)
15735 (match_dup 6)))]
15736 "
15737 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15738 operands[3], const0_rtx); }")
15739 \f
15740 (define_insn "trap"
15741 [(trap_if (const_int 1) (const_int 0))]
15742 ""
15743 "{t 31,0,0|trap}"
15744 [(set_attr "type" "trap")])
15746 (define_expand "ctrap<mode>4"
15747 [(trap_if (match_operator 0 "ordered_comparison_operator"
15748 [(match_operand:GPR 1 "register_operand")
15749 (match_operand:GPR 2 "reg_or_short_operand")])
15750 (match_operand 3 "zero_constant" ""))]
15751 ""
15752 "")
15754 (define_insn ""
15755 [(trap_if (match_operator 0 "ordered_comparison_operator"
15756 [(match_operand:GPR 1 "register_operand" "r")
15757 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15758 (const_int 0))]
15759 ""
15760 "{t|t<wd>}%V0%I2 %1,%2"
15761 [(set_attr "type" "trap")])
15762 \f
15763 ;; Insns related to generating the function prologue and epilogue.
15765 (define_expand "prologue"
15766 [(use (const_int 0))]
15767 ""
15768 {
15769 rs6000_emit_prologue ();
15770 if (!TARGET_SCHED_PROLOG)
15771 emit_insn (gen_blockage ());
15772 DONE;
15773 })
15775 (define_insn "*movesi_from_cr_one"
15776 [(match_parallel 0 "mfcr_operation"
15777 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15778 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15779 (match_operand 3 "immediate_operand" "n")]
15780 UNSPEC_MOVESI_FROM_CR))])]
15781 "TARGET_MFCRF"
15782 "*
15783 {
15784 int mask = 0;
15785 int i;
15786 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15787 {
15788 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15789 operands[4] = GEN_INT (mask);
15790 output_asm_insn (\"mfcr %1,%4\", operands);
15791 }
15792 return \"\";
15793 }"
15794 [(set_attr "type" "mfcrf")])
15796 (define_insn "movesi_from_cr"
15797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15798 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15799 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15800 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15801 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15802 UNSPEC_MOVESI_FROM_CR))]
15803 ""
15804 "mfcr %0"
15805 [(set_attr "type" "mfcr")])
15807 (define_insn "*stmw"
15808 [(match_parallel 0 "stmw_operation"
15809 [(set (match_operand:SI 1 "memory_operand" "=m")
15810 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15811 "TARGET_MULTIPLE"
15812 "{stm|stmw} %2,%1"
15813 [(set_attr "type" "store_ux")])
15815 ; The following comment applies to:
15816 ; save_gpregs_*
15817 ; save_fpregs_*
15818 ; restore_gpregs*
15819 ; return_and_restore_gpregs*
15820 ; return_and_restore_fpregs*
15821 ; return_and_restore_fpregs_aix*
15822 ;
15823 ; The out-of-line save / restore functions expects one input argument.
15824 ; Since those are not standard call_insn's, we must avoid using
15825 ; MATCH_OPERAND for that argument. That way the register rename
15826 ; optimization will not try to rename this register.
15827 ; Each pattern is repeated for each possible register number used in
15828 ; various ABIs (r11, r1, and for some functions r12)
15830 (define_insn "*save_gpregs_<mode>_r11"
15831 [(match_parallel 0 "any_parallel_operand"
15832 [(clobber (reg:P 65))
15833 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15834 (use (reg:P 11))
15835 (set (match_operand:P 2 "memory_operand" "=m")
15836 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15837 ""
15838 "bl %1"
15839 [(set_attr "type" "branch")
15840 (set_attr "length" "4")])
15842 (define_insn "*save_gpregs_<mode>_r12"
15843 [(match_parallel 0 "any_parallel_operand"
15844 [(clobber (reg:P 65))
15845 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15846 (use (reg:P 12))
15847 (set (match_operand:P 2 "memory_operand" "=m")
15848 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15849 ""
15850 "bl %1"
15851 [(set_attr "type" "branch")
15852 (set_attr "length" "4")])
15854 (define_insn "*save_gpregs_<mode>_r1"
15855 [(match_parallel 0 "any_parallel_operand"
15856 [(clobber (reg:P 65))
15857 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15858 (use (reg:P 1))
15859 (set (match_operand:P 2 "memory_operand" "=m")
15860 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15861 ""
15862 "bl %1"
15863 [(set_attr "type" "branch")
15864 (set_attr "length" "4")])
15866 (define_insn "*save_fpregs_<mode>_r11"
15867 [(match_parallel 0 "any_parallel_operand"
15868 [(clobber (reg:P 65))
15869 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15870 (use (reg:P 11))
15871 (set (match_operand:DF 2 "memory_operand" "=m")
15872 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15873 ""
15874 "bl %1"
15875 [(set_attr "type" "branch")
15876 (set_attr "length" "4")])
15878 (define_insn "*save_fpregs_<mode>_r12"
15879 [(match_parallel 0 "any_parallel_operand"
15880 [(clobber (reg:P 65))
15881 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15882 (use (reg:P 12))
15883 (set (match_operand:DF 2 "memory_operand" "=m")
15884 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15885 ""
15886 "bl %1"
15887 [(set_attr "type" "branch")
15888 (set_attr "length" "4")])
15890 (define_insn "*save_fpregs_<mode>_r1"
15891 [(match_parallel 0 "any_parallel_operand"
15892 [(clobber (reg:P 65))
15893 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15894 (use (reg:P 1))
15895 (set (match_operand:DF 2 "memory_operand" "=m")
15896 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15897 ""
15898 "bl %1"
15899 [(set_attr "type" "branch")
15900 (set_attr "length" "4")])
15902 ; These are to explain that changes to the stack pointer should
15903 ; not be moved over stores to stack memory.
15904 (define_insn "stack_tie"
15905 [(set (match_operand:BLK 0 "memory_operand" "+m")
15906 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15907 ""
15908 ""
15909 [(set_attr "length" "0")])
15911 ; Like stack_tie, but depend on both fp and sp based memory.
15912 (define_insn "frame_tie"
15913 [(set (match_operand:BLK 0 "memory_operand" "+m")
15914 (unspec:BLK [(match_dup 0)
15915 (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15916 ""
15917 ""
15918 [(set_attr "length" "0")])
15921 (define_expand "epilogue"
15922 [(use (const_int 0))]
15923 ""
15924 {
15925 if (!TARGET_SCHED_PROLOG)
15926 emit_insn (gen_blockage ());
15927 rs6000_emit_epilogue (FALSE);
15928 DONE;
15929 })
15931 ; On some processors, doing the mtcrf one CC register at a time is
15932 ; faster (like on the 604e). On others, doing them all at once is
15933 ; faster; for instance, on the 601 and 750.
15935 (define_expand "movsi_to_cr_one"
15936 [(set (match_operand:CC 0 "cc_reg_operand" "")
15937 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15938 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15939 ""
15940 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15942 (define_insn "*movsi_to_cr"
15943 [(match_parallel 0 "mtcrf_operation"
15944 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15945 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15946 (match_operand 3 "immediate_operand" "n")]
15947 UNSPEC_MOVESI_TO_CR))])]
15948 ""
15949 "*
15950 {
15951 int mask = 0;
15952 int i;
15953 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15954 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15955 operands[4] = GEN_INT (mask);
15956 return \"mtcrf %4,%2\";
15957 }"
15958 [(set_attr "type" "mtcr")])
15960 (define_insn "*mtcrfsi"
15961 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15962 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15963 (match_operand 2 "immediate_operand" "n")]
15964 UNSPEC_MOVESI_TO_CR))]
15965 "GET_CODE (operands[0]) == REG
15966 && CR_REGNO_P (REGNO (operands[0]))
15967 && GET_CODE (operands[2]) == CONST_INT
15968 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15969 "mtcrf %R0,%1"
15970 [(set_attr "type" "mtcr")])
15972 ; The load-multiple instructions have similar properties.
15973 ; Note that "load_multiple" is a name known to the machine-independent
15974 ; code that actually corresponds to the PowerPC load-string.
15976 (define_insn "*lmw"
15977 [(match_parallel 0 "lmw_operation"
15978 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15979 (match_operand:SI 2 "memory_operand" "m"))])]
15980 "TARGET_MULTIPLE"
15981 "{lm|lmw} %1,%2"
15982 [(set_attr "type" "load_ux")
15983 (set_attr "cell_micro" "always")])
15985 (define_insn "*return_internal_<mode>"
15986 [(simple_return)
15987 (use (match_operand:P 0 "register_operand" "lc"))]
15988 ""
15989 "b%T0"
15990 [(set_attr "type" "jmpreg")])
15992 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15993 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15995 ; The following comment applies to:
15996 ; save_gpregs_*
15997 ; save_fpregs_*
15998 ; restore_gpregs*
15999 ; return_and_restore_gpregs*
16000 ; return_and_restore_fpregs*
16001 ; return_and_restore_fpregs_aix*
16002 ;
16003 ; The out-of-line save / restore functions expects one input argument.
16004 ; Since those are not standard call_insn's, we must avoid using
16005 ; MATCH_OPERAND for that argument. That way the register rename
16006 ; optimization will not try to rename this register.
16007 ; Each pattern is repeated for each possible register number used in
16008 ; various ABIs (r11, r1, and for some functions r12)
16010 (define_insn "*restore_gpregs_<mode>_r11"
16011 [(match_parallel 0 "any_parallel_operand"
16012 [(clobber (match_operand:P 1 "register_operand" "=l"))
16013 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16014 (use (reg:P 11))
16015 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16016 (match_operand:P 4 "memory_operand" "m"))])]
16017 ""
16018 "bl %2"
16019 [(set_attr "type" "branch")
16020 (set_attr "length" "4")])
16022 (define_insn "*restore_gpregs_<mode>_r12"
16023 [(match_parallel 0 "any_parallel_operand"
16024 [(clobber (match_operand:P 1 "register_operand" "=l"))
16025 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16026 (use (reg:P 12))
16027 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16028 (match_operand:P 4 "memory_operand" "m"))])]
16029 ""
16030 "bl %2"
16031 [(set_attr "type" "branch")
16032 (set_attr "length" "4")])
16034 (define_insn "*restore_gpregs_<mode>_r1"
16035 [(match_parallel 0 "any_parallel_operand"
16036 [(clobber (match_operand:P 1 "register_operand" "=l"))
16037 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16038 (use (reg:P 1))
16039 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16040 (match_operand:P 4 "memory_operand" "m"))])]
16041 ""
16042 "bl %2"
16043 [(set_attr "type" "branch")
16044 (set_attr "length" "4")])
16046 (define_insn "*return_and_restore_gpregs_<mode>_r11"
16047 [(match_parallel 0 "any_parallel_operand"
16048 [(return)
16049 (clobber (match_operand:P 1 "register_operand" "=l"))
16050 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16051 (use (reg:P 11))
16052 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16053 (match_operand:P 4 "memory_operand" "m"))])]
16054 ""
16055 "b %2"
16056 [(set_attr "type" "branch")
16057 (set_attr "length" "4")])
16059 (define_insn "*return_and_restore_gpregs_<mode>_r12"
16060 [(match_parallel 0 "any_parallel_operand"
16061 [(return)
16062 (clobber (match_operand:P 1 "register_operand" "=l"))
16063 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16064 (use (reg:P 12))
16065 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16066 (match_operand:P 4 "memory_operand" "m"))])]
16067 ""
16068 "b %2"
16069 [(set_attr "type" "branch")
16070 (set_attr "length" "4")])
16072 (define_insn "*return_and_restore_gpregs_<mode>_r1"
16073 [(match_parallel 0 "any_parallel_operand"
16074 [(return)
16075 (clobber (match_operand:P 1 "register_operand" "=l"))
16076 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16077 (use (reg:P 1))
16078 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16079 (match_operand:P 4 "memory_operand" "m"))])]
16080 ""
16081 "b %2"
16082 [(set_attr "type" "branch")
16083 (set_attr "length" "4")])
16085 (define_insn "*return_and_restore_fpregs_<mode>_r11"
16086 [(match_parallel 0 "any_parallel_operand"
16087 [(return)
16088 (clobber (match_operand:P 1 "register_operand" "=l"))
16089 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16090 (use (reg:P 11))
16091 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16092 (match_operand:DF 4 "memory_operand" "m"))])]
16093 ""
16094 "b %2"
16095 [(set_attr "type" "branch")
16096 (set_attr "length" "4")])
16098 (define_insn "*return_and_restore_fpregs_<mode>_r12"
16099 [(match_parallel 0 "any_parallel_operand"
16100 [(return)
16101 (clobber (match_operand:P 1 "register_operand" "=l"))
16102 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16103 (use (reg:P 12))
16104 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16105 (match_operand:DF 4 "memory_operand" "m"))])]
16106 ""
16107 "b %2"
16108 [(set_attr "type" "branch")
16109 (set_attr "length" "4")])
16111 (define_insn "*return_and_restore_fpregs_<mode>_r1"
16112 [(match_parallel 0 "any_parallel_operand"
16113 [(return)
16114 (clobber (match_operand:P 1 "register_operand" "=l"))
16115 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16116 (use (reg:P 1))
16117 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16118 (match_operand:DF 4 "memory_operand" "m"))])]
16119 ""
16120 "b %2"
16121 [(set_attr "type" "branch")
16122 (set_attr "length" "4")])
16124 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
16125 [(match_parallel 0 "any_parallel_operand"
16126 [(return)
16127 (use (match_operand:P 1 "register_operand" "l"))
16128 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16129 (use (reg:P 11))
16130 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16131 (match_operand:DF 4 "memory_operand" "m"))])]
16132 ""
16133 "b %2"
16134 [(set_attr "type" "branch")
16135 (set_attr "length" "4")])
16137 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
16138 [(match_parallel 0 "any_parallel_operand"
16139 [(return)
16140 (use (match_operand:P 1 "register_operand" "l"))
16141 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16142 (use (reg:P 1))
16143 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16144 (match_operand:DF 4 "memory_operand" "m"))])]
16145 ""
16146 "b %2"
16147 [(set_attr "type" "branch")
16148 (set_attr "length" "4")])
16150 ; This is used in compiling the unwind routines.
16151 (define_expand "eh_return"
16152 [(use (match_operand 0 "general_operand" ""))]
16153 ""
16154 "
16155 {
16156 if (TARGET_32BIT)
16157 emit_insn (gen_eh_set_lr_si (operands[0]));
16158 else
16159 emit_insn (gen_eh_set_lr_di (operands[0]));
16160 DONE;
16161 }")
16163 ; We can't expand this before we know where the link register is stored.
16164 (define_insn "eh_set_lr_<mode>"
16165 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
16166 UNSPECV_EH_RR)
16167 (clobber (match_scratch:P 1 "=&b"))]
16168 ""
16169 "#")
16171 (define_split
16172 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
16173 (clobber (match_scratch 1 ""))]
16174 "reload_completed"
16175 [(const_int 0)]
16176 "
16177 {
16178 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
16179 DONE;
16180 }")
16182 (define_insn "prefetch"
16183 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
16184 (match_operand:SI 1 "const_int_operand" "n")
16185 (match_operand:SI 2 "const_int_operand" "n"))]
16186 "TARGET_POWERPC"
16187 "*
16188 {
16189 if (GET_CODE (operands[0]) == REG)
16190 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
16191 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
16192 }"
16193 [(set_attr "type" "load")])
16194 \f
16195 (define_insn "bpermd_<mode>"
16196 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
16197 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
16198 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
16199 "TARGET_POPCNTD"
16200 "bpermd %0,%1,%2"
16201 [(set_attr "type" "integer")])
16203 \f
16204 ;; Builtin fma support. Handle
16205 ;; Note that the conditions for expansion are in the FMA_F iterator.
16207 (define_expand "fma<mode>4"
16208 [(set (match_operand:FMA_F 0 "register_operand" "")
16209 (fma:FMA_F
16210 (match_operand:FMA_F 1 "register_operand" "")
16211 (match_operand:FMA_F 2 "register_operand" "")
16212 (match_operand:FMA_F 3 "register_operand" "")))]
16213 ""
16214 "")
16216 ; Altivec only has fma and nfms.
16217 (define_expand "fms<mode>4"
16218 [(set (match_operand:FMA_F 0 "register_operand" "")
16219 (fma:FMA_F
16220 (match_operand:FMA_F 1 "register_operand" "")
16221 (match_operand:FMA_F 2 "register_operand" "")
16222 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
16223 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16224 "")
16226 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
16227 (define_expand "fnma<mode>4"
16228 [(set (match_operand:FMA_F 0 "register_operand" "")
16229 (neg:FMA_F
16230 (fma:FMA_F
16231 (match_operand:FMA_F 1 "register_operand" "")
16232 (match_operand:FMA_F 2 "register_operand" "")
16233 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16234 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
16235 "")
16237 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
16238 (define_expand "fnms<mode>4"
16239 [(set (match_operand:FMA_F 0 "register_operand" "")
16240 (neg:FMA_F
16241 (fma:FMA_F
16242 (match_operand:FMA_F 1 "register_operand" "")
16243 (match_operand:FMA_F 2 "register_operand" "")
16244 (match_operand:FMA_F 3 "register_operand" ""))))]
16245 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16246 "")
16248 ; Not an official optab name, but used from builtins.
16249 (define_expand "nfma<mode>4"
16250 [(set (match_operand:FMA_F 0 "register_operand" "")
16251 (neg:FMA_F
16252 (fma:FMA_F
16253 (match_operand:FMA_F 1 "register_operand" "")
16254 (match_operand:FMA_F 2 "register_operand" "")
16255 (match_operand:FMA_F 3 "register_operand" ""))))]
16256 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16257 "")
16259 ; Not an official optab name, but used from builtins.
16260 (define_expand "nfms<mode>4"
16261 [(set (match_operand:FMA_F 0 "register_operand" "")
16262 (neg:FMA_F
16263 (fma:FMA_F
16264 (match_operand:FMA_F 1 "register_operand" "")
16265 (match_operand:FMA_F 2 "register_operand" "")
16266 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16267 ""
16268 "")
16270 \f
16272 (include "sync.md")
16273 (include "vector.md")
16274 (include "vsx.md")
16275 (include "altivec.md")
16276 (include "spe.md")
16277 (include "dfp.md")
16278 (include "paired.md")