1 ;; Constraint definitions for RS6000
2 ;; Copyright (C) 2006-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Available constraint letters: "e", "k", "q", "u", "A", "B", "C", "D"
22 ;; Register constraints
24 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
27 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
30 (define_register_constraint "b" "BASE_REGS"
33 (define_register_constraint "h" "SPECIAL_REGS"
36 (define_register_constraint "c" "CTR_REGS"
39 (define_register_constraint "l" "LINK_REGS"
42 (define_register_constraint "v" "ALTIVEC_REGS"
45 (define_register_constraint "x" "CR0_REGS"
48 (define_register_constraint "y" "CR_REGS"
51 (define_register_constraint "z" "CA_REGS"
54 ;; Use w as a prefix to add VSX modes
56 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
57 "Any VSX register if the -mvsx option was used or NO_REGS.")
59 ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
60 ;; It is currently used for that purpose in LLVM.
62 (define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
63 "VSX vector register to hold vector double data or NO_REGS.")
65 (define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
66 "VSX vector register to hold vector float data or NO_REGS.")
68 (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
69 "If -mmfpgpr was used, a floating point register or NO_REGS.")
71 (define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
72 "Floating point register if direct moves are available, or NO_REGS.")
74 ;; At present, DImode is not allowed in the Altivec registers. If in the
75 ;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
76 (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
77 "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
79 (define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
80 "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
82 (define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
83 "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
85 (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
86 "Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
88 (define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]"
89 "VSX register if direct move instructions are enabled, or NO_REGS.")
91 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
92 ;; direct move directly, and movsf can't to move between the register sets.
93 ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
94 (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
96 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
97 "General purpose register if 64-bit instructions are enabled or NO_REGS.")
99 (define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
100 "VSX vector register to hold scalar double values or NO_REGS.")
102 (define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
103 "VSX vector register to hold 128 bit integer or NO_REGS.")
105 (define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]"
106 "Altivec register to use for float/32-bit int loads/stores or NO_REGS.")
108 (define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
109 "Altivec register to use for double loads/stores or NO_REGS.")
111 (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
112 "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
114 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
115 "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
117 (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
118 "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
120 (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
121 "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
123 (define_constraint "wD"
124 "Int constant that is the element number of the 64-bit scalar in a vector."
125 (and (match_code "const_int")
126 (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)")))
128 ;; Lq/stq validates the address for load/store quad
129 (define_memory_constraint "wQ"
130 "Memory operand suitable for the load/store quad instructions"
131 (match_operand 0 "quad_memory_operand"))
133 ;; Altivec style load/store that ignores the bottom bits of the address
134 (define_memory_constraint "wZ"
135 "Indexed or indirect memory operand, ignoring the bottom 4 bits"
136 (match_operand 0 "altivec_indexed_or_indirect_operand"))
138 ;; Integer constraints
140 (define_constraint "I"
141 "A signed 16-bit constant"
142 (and (match_code "const_int")
143 (match_test "(unsigned HOST_WIDE_INT) (ival + 0x8000) < 0x10000")))
145 (define_constraint "J"
146 "high-order 16 bits nonzero"
147 (and (match_code "const_int")
148 (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
150 (define_constraint "K"
151 "low-order 16 bits nonzero"
152 (and (match_code "const_int")
153 (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
155 (define_constraint "L"
156 "signed 16-bit constant shifted left 16 bits"
157 (and (match_code "const_int")
158 (match_test "((ival & 0xffff) == 0
159 && (ival >> 31 == -1 || ival >> 31 == 0))")))
161 (define_constraint "M"
162 "constant greater than 31"
163 (and (match_code "const_int")
164 (match_test "ival > 31")))
166 (define_constraint "N"
167 "positive constant that is an exact power of two"
168 (and (match_code "const_int")
169 (match_test "ival > 0 && exact_log2 (ival) >= 0")))
171 (define_constraint "O"
173 (and (match_code "const_int")
174 (match_test "ival == 0")))
176 (define_constraint "P"
177 "constant whose negation is signed 16-bit constant"
178 (and (match_code "const_int")
179 (match_test "(unsigned HOST_WIDE_INT) ((- ival) + 0x8000) < 0x10000")))
181 ;; Floating-point constraints
183 (define_constraint "G"
184 "Constant that can be copied into GPR with two insns for DF/DI
186 (and (match_code "const_double")
187 (match_test "num_insns_constant (op, mode)
188 == (mode == SFmode ? 1 : 2)")))
190 (define_constraint "H"
191 "DF/DI constant that takes three insns."
192 (and (match_code "const_double")
193 (match_test "num_insns_constant (op, mode) == 3")))
195 ;; Memory constraints
197 (define_memory_constraint "es"
198 "A ``stable'' memory operand; that is, one which does not include any
199 automodification of the base register. Unlike @samp{m}, this constraint
200 can be used in @code{asm} statements that might access the operand
201 several times, or that might not access it at all."
202 (and (match_code "mem")
203 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
205 (define_memory_constraint "Q"
206 "Memory operand that is an offset from a register (it is usually better
207 to use @samp{m} or @samp{es} in @code{asm} statements)"
208 (and (match_code "mem")
209 (match_test "GET_CODE (XEXP (op, 0)) == REG")))
211 (define_memory_constraint "Y"
212 "memory operand for 8 byte and 16 byte gpr load/store"
213 (and (match_code "mem")
214 (match_operand 0 "mem_operand_gpr")))
216 (define_memory_constraint "Z"
217 "Memory operand that is an indexed or indirect from a register (it is
218 usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
219 (match_operand 0 "indexed_or_indirect_operand"))
221 ;; Address constraints
223 (define_address_constraint "a"
224 "Indexed or indirect address operand"
225 (match_operand 0 "indexed_or_indirect_address"))
227 (define_constraint "R"
229 (match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
231 ;; General constraints
233 (define_constraint "S"
234 "Constant that can be placed into a 64-bit mask operand"
235 (and (match_test "TARGET_POWERPC64")
236 (match_operand 0 "mask64_operand")))
238 (define_constraint "T"
239 "Constant that can be placed into a 32-bit mask operand"
240 (match_operand 0 "mask_operand"))
242 (define_constraint "U"
243 "V.4 small data reference"
244 (and (match_test "DEFAULT_ABI == ABI_V4")
245 (match_operand 0 "small_data_operand")))
247 (define_constraint "t"
248 "AND masks that can be performed by two rldic{l,r} insns
249 (but excluding those that could match other constraints of anddi3)"
250 (and (and (and (match_operand 0 "mask64_2_operand")
251 (match_test "(fixed_regs[CR0_REGNO]
252 || !logical_operand (op, DImode))"))
253 (not (match_operand 0 "mask_operand")))
254 (not (match_operand 0 "mask64_operand"))))
256 (define_constraint "W"
257 "vector constant that does not require memory"
258 (match_operand 0 "easy_vector_constant"))
260 (define_constraint "j"
261 "Zero vector constant"
262 (match_test "op == const0_rtx || op == CONST0_RTX (GET_MODE (op))"))