1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts
;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges
;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras
;
112 /* Number of instructions combined in this function. */
114 static int combine_successes
;
116 /* Totals over entire compilation. */
118 static int total_attempts
, total_merges
, total_extras
, total_successes
;
120 /* Define a default value for REVERSIBLE_CC_MODE.
121 We can never assume that a condition code mode is safe to reverse unless
122 the md tells us so. */
123 #ifndef REVERSIBLE_CC_MODE
124 #define REVERSIBLE_CC_MODE(MODE) 0
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid
;
135 static int max_uid_cuid
;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static int combine_max_regno
;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx
*reg_last_death
;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx
*reg_last_set
;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set
;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid
;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn
;
172 /* This is an insn that belongs before subst_insn, but is not currently
173 on the insn chain. */
175 static rtx subst_prev_insn
;
177 /* This is the lowest CUID that `subst' is currently dealing with.
178 get_last_value will not return a value if the register was set at or
179 after this CUID. If not for this mechanism, we could get confused if
180 I2 or I1 in try_combine were an insn that used the old value of a register
181 to obtain a new value. In that case, we might erroneously get the
182 new value of the register when we wanted the old one. */
184 static int subst_low_cuid
;
186 /* This contains any hard registers that are used in newpat; reg_dead_at_p
187 must consider all these registers to be always live. */
189 static HARD_REG_SET newpat_used_regs
;
191 /* This is an insn to which a LOG_LINKS entry has been added. If this
192 insn is the earlier than I2 or I3, combine should rescan starting at
195 static rtx added_links_insn
;
197 /* Basic block number of the block in which we are performing combines. */
198 static int this_basic_block
;
200 /* A bitmap indicating which blocks had registers go dead at entry.
201 After combine, we'll need to re-do global life analysis with
202 those blocks as starting points. */
203 static sbitmap refresh_blocks
;
204 static int need_refresh
;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx
*reg_last_set_value
;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label
;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick
;
264 /* Set non-zero if references to register n in expressions should not be
267 static char *reg_last_set_invalid
;
269 /* Incremented for each label. */
271 static int label_tick
;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode
;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static char *reg_sign_bit_copies
;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid
;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode
*reg_last_set_mode
;
308 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
309 static char *reg_last_set_sign_bit_copies
;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r
; int i
;} old_contents
;
320 union {rtx
*r
; int *i
;} where
;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too.
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
342 struct undo
*previous_undos
;
346 static struct undobuf undobuf
;
348 /* Number of times the pseudo being substituted for
349 was found and replaced. */
351 static int n_occurrences
;
353 static void do_SUBST
PROTO((rtx
*, rtx
));
354 static void do_SUBST_INT
PROTO((int *, int));
355 static void init_reg_last_arrays
PROTO((void));
356 static void setup_incoming_promotions
PROTO((void));
357 static void set_nonzero_bits_and_sign_copies
PROTO((rtx
, rtx
, void *));
358 static int can_combine_p
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
359 static int sets_function_arg_p
PROTO((rtx
));
360 static int combinable_i3pat
PROTO((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
361 static int contains_muldiv
PROTO((rtx
));
362 static rtx try_combine
PROTO((rtx
, rtx
, rtx
));
363 static void undo_all
PROTO((void));
364 static void undo_commit
PROTO((void));
365 static rtx
*find_split_point
PROTO((rtx
*, rtx
));
366 static rtx subst
PROTO((rtx
, rtx
, rtx
, int, int));
367 static rtx combine_simplify_rtx
PROTO((rtx
, enum machine_mode
, int, int));
368 static rtx simplify_if_then_else
PROTO((rtx
));
369 static rtx simplify_set
PROTO((rtx
));
370 static rtx simplify_logical
PROTO((rtx
, int));
371 static rtx expand_compound_operation
PROTO((rtx
));
372 static rtx expand_field_assignment
PROTO((rtx
));
373 static rtx make_extraction
PROTO((enum machine_mode
, rtx
, int, rtx
, int,
375 static rtx extract_left_shift
PROTO((rtx
, int));
376 static rtx make_compound_operation
PROTO((rtx
, enum rtx_code
));
377 static int get_pos_from_mask
PROTO((unsigned HOST_WIDE_INT
, int *));
378 static rtx force_to_mode
PROTO((rtx
, enum machine_mode
,
379 unsigned HOST_WIDE_INT
, rtx
, int));
380 static rtx if_then_else_cond
PROTO((rtx
, rtx
*, rtx
*));
381 static rtx known_cond
PROTO((rtx
, enum rtx_code
, rtx
, rtx
));
382 static int rtx_equal_for_field_assignment_p
PROTO((rtx
, rtx
));
383 static rtx make_field_assignment
PROTO((rtx
));
384 static rtx apply_distributive_law
PROTO((rtx
));
385 static rtx simplify_and_const_int
PROTO((rtx
, enum machine_mode
, rtx
,
386 unsigned HOST_WIDE_INT
));
387 static unsigned HOST_WIDE_INT nonzero_bits
PROTO((rtx
, enum machine_mode
));
388 static int num_sign_bit_copies
PROTO((rtx
, enum machine_mode
));
389 static int merge_outer_ops
PROTO((enum rtx_code
*, HOST_WIDE_INT
*,
390 enum rtx_code
, HOST_WIDE_INT
,
391 enum machine_mode
, int *));
392 static rtx simplify_shift_const
PROTO((rtx
, enum rtx_code
, enum machine_mode
,
394 static int recog_for_combine
PROTO((rtx
*, rtx
, rtx
*));
395 static rtx gen_lowpart_for_combine
PROTO((enum machine_mode
, rtx
));
396 static rtx gen_rtx_combine
PVPROTO((enum rtx_code code
, enum machine_mode mode
,
398 static rtx gen_binary
PROTO((enum rtx_code
, enum machine_mode
,
400 static rtx gen_unary
PROTO((enum rtx_code
, enum machine_mode
,
401 enum machine_mode
, rtx
));
402 static enum rtx_code simplify_comparison
PROTO((enum rtx_code
, rtx
*, rtx
*));
403 static int reversible_comparison_p
PROTO((rtx
));
404 static void update_table_tick
PROTO((rtx
));
405 static void record_value_for_reg
PROTO((rtx
, rtx
, rtx
));
406 static void record_dead_and_set_regs_1
PROTO((rtx
, rtx
, void *));
407 static void record_dead_and_set_regs
PROTO((rtx
));
408 static int get_last_value_validate
PROTO((rtx
*, rtx
, int, int));
409 static rtx get_last_value
PROTO((rtx
));
410 static int use_crosses_set_p
PROTO((rtx
, int));
411 static void reg_dead_at_p_1
PROTO((rtx
, rtx
, void *));
412 static int reg_dead_at_p
PROTO((rtx
, rtx
));
413 static void move_deaths
PROTO((rtx
, rtx
, int, rtx
, rtx
*));
414 static int reg_bitfield_target_p
PROTO((rtx
, rtx
));
415 static void distribute_notes
PROTO((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
416 static void distribute_links
PROTO((rtx
));
417 static void mark_used_regs_combine
PROTO((rtx
));
418 static int insn_cuid
PROTO((rtx
));
420 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
421 insn. The substitution can be undone by undo_all. If INTO is already
422 set to NEWVAL, do not record this change. Because computing NEWVAL might
423 also call SUBST, we have to compute it before we put anything into
427 do_SUBST(into
, newval
)
433 if (oldval
== newval
)
437 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
439 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
443 buf
->old_contents
.r
= oldval
;
446 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
449 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
451 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
452 for the value of a HOST_WIDE_INT value (including CONST_INT) is
456 do_SUBST_INT(into
, newval
)
462 if (oldval
== newval
)
466 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
468 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
472 buf
->old_contents
.i
= oldval
;
475 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
478 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
480 /* Main entry point for combiner. F is the first insn of the function.
481 NREGS is the first unused pseudo-reg number. */
484 combine_instructions (f
, nregs
)
488 register rtx insn
, next
;
493 register rtx links
, nextlinks
;
495 combine_attempts
= 0;
498 combine_successes
= 0;
500 combine_max_regno
= nregs
;
502 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
503 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
504 reg_sign_bit_copies
= (char *) xcalloc (nregs
, sizeof (char));
506 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
507 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
508 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
509 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
510 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
511 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
513 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
514 reg_last_set_nonzero_bits
515 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
516 reg_last_set_sign_bit_copies
517 = (char *) xmalloc (nregs
* sizeof (char));
519 init_reg_last_arrays ();
521 init_recog_no_volatile ();
523 /* Compute maximum uid value so uid_cuid can be allocated. */
525 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
526 if (INSN_UID (insn
) > i
)
529 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
532 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
534 /* Don't use reg_nonzero_bits when computing it. This can cause problems
535 when, for example, we have j <<= 1 in a loop. */
537 nonzero_sign_valid
= 0;
539 /* Compute the mapping from uids to cuids.
540 Cuids are numbers assigned to insns, like uids,
541 except that cuids increase monotonically through the code.
543 Scan all SETs and see if we can deduce anything about what
544 bits are known to be zero for some registers and how many copies
545 of the sign bit are known to exist for those registers.
547 Also set any known values so that we can use it while searching
548 for what bits are known to be set. */
552 /* We need to initialize it here, because record_dead_and_set_regs may call
554 subst_prev_insn
= NULL_RTX
;
556 setup_incoming_promotions ();
558 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
559 sbitmap_zero (refresh_blocks
);
562 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
564 uid_cuid
[INSN_UID (insn
)] = ++i
;
568 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
570 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
572 record_dead_and_set_regs (insn
);
575 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
576 if (REG_NOTE_KIND (links
) == REG_INC
)
577 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
582 if (GET_CODE (insn
) == CODE_LABEL
)
586 nonzero_sign_valid
= 1;
588 /* Now scan all the insns in forward order. */
590 this_basic_block
= -1;
594 init_reg_last_arrays ();
595 setup_incoming_promotions ();
597 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
601 /* If INSN starts a new basic block, update our basic block number. */
602 if (this_basic_block
+ 1 < n_basic_blocks
603 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
606 if (GET_CODE (insn
) == CODE_LABEL
)
609 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
)) != 0)
617 /* Try each sequence of three linked insns ending with this one. */
619 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
620 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
621 nextlinks
= XEXP (nextlinks
, 1))
622 if ((next
= try_combine (insn
, XEXP (links
, 0),
623 XEXP (nextlinks
, 0))) != 0)
627 /* Try to combine a jump insn that uses CC0
628 with a preceding insn that sets CC0, and maybe with its
629 logical predecessor as well.
630 This is how we make decrement-and-branch insns.
631 We need this special code because data flow connections
632 via CC0 do not get entered in LOG_LINKS. */
634 if (GET_CODE (insn
) == JUMP_INSN
635 && (prev
= prev_nonnote_insn (insn
)) != 0
636 && GET_CODE (prev
) == INSN
637 && sets_cc0_p (PATTERN (prev
)))
639 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
642 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
643 nextlinks
= XEXP (nextlinks
, 1))
644 if ((next
= try_combine (insn
, prev
,
645 XEXP (nextlinks
, 0))) != 0)
649 /* Do the same for an insn that explicitly references CC0. */
650 if (GET_CODE (insn
) == INSN
651 && (prev
= prev_nonnote_insn (insn
)) != 0
652 && GET_CODE (prev
) == INSN
653 && sets_cc0_p (PATTERN (prev
))
654 && GET_CODE (PATTERN (insn
)) == SET
655 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
657 if ((next
= try_combine (insn
, prev
, NULL_RTX
)) != 0)
660 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
661 nextlinks
= XEXP (nextlinks
, 1))
662 if ((next
= try_combine (insn
, prev
,
663 XEXP (nextlinks
, 0))) != 0)
667 /* Finally, see if any of the insns that this insn links to
668 explicitly references CC0. If so, try this insn, that insn,
669 and its predecessor if it sets CC0. */
670 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
671 if (GET_CODE (XEXP (links
, 0)) == INSN
672 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
673 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
674 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
675 && GET_CODE (prev
) == INSN
676 && sets_cc0_p (PATTERN (prev
))
677 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
681 /* Try combining an insn with two different insns whose results it
683 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
684 for (nextlinks
= XEXP (links
, 1); nextlinks
;
685 nextlinks
= XEXP (nextlinks
, 1))
686 if ((next
= try_combine (insn
, XEXP (links
, 0),
687 XEXP (nextlinks
, 0))) != 0)
690 if (GET_CODE (insn
) != NOTE
)
691 record_dead_and_set_regs (insn
);
700 compute_bb_for_insn (get_max_uid ());
701 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
706 sbitmap_free (refresh_blocks
);
707 free (reg_nonzero_bits
);
708 free (reg_sign_bit_copies
);
709 free (reg_last_death
);
711 free (reg_last_set_value
);
712 free (reg_last_set_table_tick
);
713 free (reg_last_set_label
);
714 free (reg_last_set_invalid
);
715 free (reg_last_set_mode
);
716 free (reg_last_set_nonzero_bits
);
717 free (reg_last_set_sign_bit_copies
);
721 struct undo
*undo
, *next
;
722 for (undo
= undobuf
.frees
; undo
; undo
= next
)
730 total_attempts
+= combine_attempts
;
731 total_merges
+= combine_merges
;
732 total_extras
+= combine_extras
;
733 total_successes
+= combine_successes
;
735 nonzero_sign_valid
= 0;
737 /* Make recognizer allow volatile MEMs again. */
741 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
744 init_reg_last_arrays ()
746 int nregs
= combine_max_regno
;
748 bzero ((char *) reg_last_death
, nregs
* sizeof (rtx
));
749 bzero ((char *) reg_last_set
, nregs
* sizeof (rtx
));
750 bzero ((char *) reg_last_set_value
, nregs
* sizeof (rtx
));
751 bzero ((char *) reg_last_set_table_tick
, nregs
* sizeof (int));
752 bzero ((char *) reg_last_set_label
, nregs
* sizeof (int));
753 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
754 bzero ((char *) reg_last_set_mode
, nregs
* sizeof (enum machine_mode
));
755 bzero ((char *) reg_last_set_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
756 bzero (reg_last_set_sign_bit_copies
, nregs
* sizeof (char));
759 /* Set up any promoted values for incoming argument registers. */
762 setup_incoming_promotions ()
764 #ifdef PROMOTE_FUNCTION_ARGS
767 enum machine_mode mode
;
769 rtx first
= get_insns ();
771 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
772 if (FUNCTION_ARG_REGNO_P (regno
)
773 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
776 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
779 gen_rtx_CLOBBER (mode
, const0_rtx
)));
784 /* Called via note_stores. If X is a pseudo that is narrower than
785 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
787 If we are setting only a portion of X and we can't figure out what
788 portion, assume all bits will be used since we don't know what will
791 Similarly, set how many bits of X are known to be copies of the sign bit
792 at all locations in the function. This is the smallest number implied
796 set_nonzero_bits_and_sign_copies (x
, set
, data
)
799 void *data ATTRIBUTE_UNUSED
;
803 if (GET_CODE (x
) == REG
804 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
805 /* If this register is undefined at the start of the file, we can't
806 say what its contents were. */
807 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
808 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
810 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
812 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
813 reg_sign_bit_copies
[REGNO (x
)] = 1;
817 /* If this is a complex assignment, see if we can convert it into a
818 simple assignment. */
819 set
= expand_field_assignment (set
);
821 /* If this is a simple assignment, or we have a paradoxical SUBREG,
822 set what we know about X. */
824 if (SET_DEST (set
) == x
825 || (GET_CODE (SET_DEST (set
)) == SUBREG
826 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
827 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
828 && SUBREG_REG (SET_DEST (set
)) == x
))
830 rtx src
= SET_SRC (set
);
832 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
833 /* If X is narrower than a word and SRC is a non-negative
834 constant that would appear negative in the mode of X,
835 sign-extend it for use in reg_nonzero_bits because some
836 machines (maybe most) will actually do the sign-extension
837 and this is the conservative approach.
839 ??? For 2.5, try to tighten up the MD files in this regard
840 instead of this kludge. */
842 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
843 && GET_CODE (src
) == CONST_INT
845 && 0 != (INTVAL (src
)
847 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
848 src
= GEN_INT (INTVAL (src
)
849 | ((HOST_WIDE_INT
) (-1)
850 << GET_MODE_BITSIZE (GET_MODE (x
))));
853 reg_nonzero_bits
[REGNO (x
)]
854 |= nonzero_bits (src
, nonzero_bits_mode
);
855 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
856 if (reg_sign_bit_copies
[REGNO (x
)] == 0
857 || reg_sign_bit_copies
[REGNO (x
)] > num
)
858 reg_sign_bit_copies
[REGNO (x
)] = num
;
862 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
863 reg_sign_bit_copies
[REGNO (x
)] = 1;
868 /* See if INSN can be combined into I3. PRED and SUCC are optionally
869 insns that were previously combined into I3 or that will be combined
870 into the merger of INSN and I3.
872 Return 0 if the combination is not allowed for any reason.
874 If the combination is allowed, *PDEST will be set to the single
875 destination of INSN and *PSRC to the single source, and this function
879 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
882 rtx pred ATTRIBUTE_UNUSED
;
887 rtx set
= 0, src
, dest
;
892 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
893 && next_active_insn (succ
) == i3
)
894 : next_active_insn (insn
) == i3
);
896 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
897 or a PARALLEL consisting of such a SET and CLOBBERs.
899 If INSN has CLOBBER parallel parts, ignore them for our processing.
900 By definition, these happen during the execution of the insn. When it
901 is merged with another insn, all bets are off. If they are, in fact,
902 needed and aren't also supplied in I3, they may be added by
903 recog_for_combine. Otherwise, it won't match.
905 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
908 Get the source and destination of INSN. If more than one, can't
911 if (GET_CODE (PATTERN (insn
)) == SET
)
912 set
= PATTERN (insn
);
913 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
914 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
916 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
918 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
920 switch (GET_CODE (elt
))
922 /* This is important to combine floating point insns
925 /* Combining an isolated USE doesn't make sense.
926 We depend here on combinable_i3_pat to reject them. */
927 /* The code below this loop only verifies that the inputs of
928 the SET in INSN do not change. We call reg_set_between_p
929 to verify that the REG in the USE does not change betweeen
931 If the USE in INSN was for a pseudo register, the matching
932 insn pattern will likely match any register; combining this
933 with any other USE would only be safe if we knew that the
934 used registers have identical values, or if there was
935 something to tell them apart, e.g. different modes. For
936 now, we forgo such compilcated tests and simply disallow
937 combining of USES of pseudo registers with any other USE. */
938 if (GET_CODE (XEXP (elt
, 0)) == REG
939 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
941 rtx i3pat
= PATTERN (i3
);
942 int i
= XVECLEN (i3pat
, 0) - 1;
943 int regno
= REGNO (XEXP (elt
, 0));
946 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
947 if (GET_CODE (i3elt
) == USE
948 && GET_CODE (XEXP (i3elt
, 0)) == REG
949 && (REGNO (XEXP (i3elt
, 0)) == regno
950 ? reg_set_between_p (XEXP (elt
, 0),
951 PREV_INSN (insn
), i3
)
952 : regno
>= FIRST_PSEUDO_REGISTER
))
959 /* We can ignore CLOBBERs. */
964 /* Ignore SETs whose result isn't used but not those that
965 have side-effects. */
966 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
967 && ! side_effects_p (elt
))
970 /* If we have already found a SET, this is a second one and
971 so we cannot combine with this insn. */
979 /* Anything else means we can't combine. */
985 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
986 so don't do anything with it. */
987 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
996 set
= expand_field_assignment (set
);
997 src
= SET_SRC (set
), dest
= SET_DEST (set
);
999 /* Don't eliminate a store in the stack pointer. */
1000 if (dest
== stack_pointer_rtx
1001 /* If we couldn't eliminate a field assignment, we can't combine. */
1002 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1003 /* Don't combine with an insn that sets a register to itself if it has
1004 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1005 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1006 /* Can't merge a function call. */
1007 || GET_CODE (src
) == CALL
1008 /* Don't eliminate a function call argument. */
1009 || (GET_CODE (i3
) == CALL_INSN
1010 && (find_reg_fusage (i3
, USE
, dest
)
1011 || (GET_CODE (dest
) == REG
1012 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1013 && global_regs
[REGNO (dest
)])))
1014 /* Don't substitute into an incremented register. */
1015 || FIND_REG_INC_NOTE (i3
, dest
)
1016 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1018 /* Don't combine the end of a libcall into anything. */
1019 /* ??? This gives worse code, and appears to be unnecessary, since no
1020 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1021 use REG_RETVAL notes for noconflict blocks, but other code here
1022 makes sure that those insns don't disappear. */
1023 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1025 /* Make sure that DEST is not used after SUCC but before I3. */
1026 || (succ
&& ! all_adjacent
1027 && reg_used_between_p (dest
, succ
, i3
))
1028 /* Make sure that the value that is to be substituted for the register
1029 does not use any registers whose values alter in between. However,
1030 If the insns are adjacent, a use can't cross a set even though we
1031 think it might (this can happen for a sequence of insns each setting
1032 the same destination; reg_last_set of that register might point to
1033 a NOTE). If INSN has a REG_EQUIV note, the register is always
1034 equivalent to the memory so the substitution is valid even if there
1035 are intervening stores. Also, don't move a volatile asm or
1036 UNSPEC_VOLATILE across any other insns. */
1038 && (((GET_CODE (src
) != MEM
1039 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1040 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1041 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1042 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1043 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1044 better register allocation by not doing the combine. */
1045 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1046 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1047 /* Don't combine across a CALL_INSN, because that would possibly
1048 change whether the life span of some REGs crosses calls or not,
1049 and it is a pain to update that information.
1050 Exception: if source is a constant, moving it later can't hurt.
1051 Accept that special case, because it helps -fforce-addr a lot. */
1052 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1055 /* DEST must either be a REG or CC0. */
1056 if (GET_CODE (dest
) == REG
)
1058 /* If register alignment is being enforced for multi-word items in all
1059 cases except for parameters, it is possible to have a register copy
1060 insn referencing a hard register that is not allowed to contain the
1061 mode being copied and which would not be valid as an operand of most
1062 insns. Eliminate this problem by not combining with such an insn.
1064 Also, on some machines we don't want to extend the life of a hard
1067 This is the same test done in can_combine except that we don't test
1068 if SRC is a CALL operation to permit a hard register with
1069 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1072 if (GET_CODE (src
) == REG
1073 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1074 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1075 /* Don't extend the life of a hard register unless it is
1076 user variable (if we have few registers) or it can't
1077 fit into the desired register (meaning something special
1079 Also avoid substituting a return register into I3, because
1080 reload can't handle a conflict with constraints of other
1082 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1083 && (! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
))
1084 || (SMALL_REGISTER_CLASSES
1085 && ((! all_adjacent
&& ! REG_USERVAR_P (src
))
1086 || (FUNCTION_VALUE_REGNO_P (REGNO (src
))
1087 && ! REG_USERVAR_P (src
))))))))
1090 else if (GET_CODE (dest
) != CC0
)
1093 /* Don't substitute for a register intended as a clobberable operand.
1094 Similarly, don't substitute an expression containing a register that
1095 will be clobbered in I3. */
1096 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1097 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1098 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1099 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1101 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1104 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1105 or not), reject, unless nothing volatile comes between it and I3 */
1107 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1109 /* Make sure succ doesn't contain a volatile reference. */
1110 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1113 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1114 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1115 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1119 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1120 to be an explicit register variable, and was chosen for a reason. */
1122 if (GET_CODE (src
) == ASM_OPERANDS
1123 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1126 /* If there are any volatile insns between INSN and I3, reject, because
1127 they might affect machine state. */
1129 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1130 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1131 && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1134 /* If INSN or I2 contains an autoincrement or autodecrement,
1135 make sure that register is not used between there and I3,
1136 and not already used in I3 either.
1137 Also insist that I3 not be a jump; if it were one
1138 and the incremented register were spilled, we would lose. */
1141 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1142 if (REG_NOTE_KIND (link
) == REG_INC
1143 && (GET_CODE (i3
) == JUMP_INSN
1144 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1145 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1150 /* Don't combine an insn that follows a CC0-setting insn.
1151 An insn that uses CC0 must not be separated from the one that sets it.
1152 We do, however, allow I2 to follow a CC0-setting insn if that insn
1153 is passed as I1; in that case it will be deleted also.
1154 We also allow combining in this case if all the insns are adjacent
1155 because that would leave the two CC0 insns adjacent as well.
1156 It would be more logical to test whether CC0 occurs inside I1 or I2,
1157 but that would be much slower, and this ought to be equivalent. */
1159 p
= prev_nonnote_insn (insn
);
1160 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1165 /* If we get here, we have passed all the tests and the combination is
1174 /* Check if PAT is an insn - or a part of it - used to set up an
1175 argument for a function in a hard register. */
1178 sets_function_arg_p (pat
)
1184 switch (GET_CODE (pat
))
1187 return sets_function_arg_p (PATTERN (pat
));
1190 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1191 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1197 inner_dest
= SET_DEST (pat
);
1198 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1199 || GET_CODE (inner_dest
) == SUBREG
1200 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1201 inner_dest
= XEXP (inner_dest
, 0);
1203 return (GET_CODE (inner_dest
) == REG
1204 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1205 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1214 /* LOC is the location within I3 that contains its pattern or the component
1215 of a PARALLEL of the pattern. We validate that it is valid for combining.
1217 One problem is if I3 modifies its output, as opposed to replacing it
1218 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1219 so would produce an insn that is not equivalent to the original insns.
1223 (set (reg:DI 101) (reg:DI 100))
1224 (set (subreg:SI (reg:DI 101) 0) <foo>)
1226 This is NOT equivalent to:
1228 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1229 (set (reg:DI 101) (reg:DI 100))])
1231 Not only does this modify 100 (in which case it might still be valid
1232 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1234 We can also run into a problem if I2 sets a register that I1
1235 uses and I1 gets directly substituted into I3 (not via I2). In that
1236 case, we would be getting the wrong value of I2DEST into I3, so we
1237 must reject the combination. This case occurs when I2 and I1 both
1238 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1239 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1240 of a SET must prevent combination from occurring.
1242 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1243 if the destination of a SET is a hard register that isn't a user
1246 Before doing the above check, we first try to expand a field assignment
1247 into a set of logical operations.
1249 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1250 we place a register that is both set and used within I3. If more than one
1251 such register is detected, we fail.
1253 Return 1 if the combination is valid, zero otherwise. */
1256 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1262 rtx
*pi3dest_killed
;
1266 if (GET_CODE (x
) == SET
)
1268 rtx set
= expand_field_assignment (x
);
1269 rtx dest
= SET_DEST (set
);
1270 rtx src
= SET_SRC (set
);
1271 rtx inner_dest
= dest
;
1274 rtx inner_src
= src
;
1279 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1280 || GET_CODE (inner_dest
) == SUBREG
1281 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1282 inner_dest
= XEXP (inner_dest
, 0);
1284 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1287 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1288 || GET_CODE (inner_src
) == SUBREG
1289 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1290 inner_src
= XEXP (inner_src
, 0);
1292 /* If it is better that two different modes keep two different pseudos,
1293 avoid combining them. This avoids producing the following pattern
1295 (set (subreg:SI (reg/v:QI 21) 0)
1296 (lshiftrt:SI (reg/v:SI 20)
1298 If that were made, reload could not handle the pair of
1299 reg 20/21, since it would try to get any GENERAL_REGS
1300 but some of them don't handle QImode. */
1302 if (rtx_equal_p (inner_src
, i2dest
)
1303 && GET_CODE (inner_dest
) == REG
1304 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1308 /* Check for the case where I3 modifies its output, as
1310 if ((inner_dest
!= dest
1311 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1312 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1314 /* This is the same test done in can_combine_p except that we
1315 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1316 CALL operation. Moreover, we can't test all_adjacent; we don't
1317 have to, since this instruction will stay in place, thus we are
1318 not considering increasing the lifetime of INNER_DEST.
1320 Also, if this insn sets a function argument, combining it with
1321 something that might need a spill could clobber a previous
1322 function argument; the all_adjacent test in can_combine_p also
1323 checks this; here, we do a more specific test for this case. */
1325 || (GET_CODE (inner_dest
) == REG
1326 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1327 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1328 GET_MODE (inner_dest
))
1329 || (SMALL_REGISTER_CLASSES
&& GET_CODE (src
) != CALL
1330 && ! REG_USERVAR_P (inner_dest
)
1331 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest
))
1332 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest
))
1334 && sets_function_arg_p (prev_nonnote_insn (i3
)))))))
1335 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1338 /* If DEST is used in I3, it is being killed in this insn,
1339 so record that for later.
1340 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1341 STACK_POINTER_REGNUM, since these are always considered to be
1342 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1343 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1344 && reg_referenced_p (dest
, PATTERN (i3
))
1345 && REGNO (dest
) != FRAME_POINTER_REGNUM
1346 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1347 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1349 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1350 && (REGNO (dest
) != ARG_POINTER_REGNUM
1351 || ! fixed_regs
[REGNO (dest
)])
1353 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1355 if (*pi3dest_killed
)
1358 *pi3dest_killed
= dest
;
1362 else if (GET_CODE (x
) == PARALLEL
)
1366 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1367 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1368 i1_not_in_src
, pi3dest_killed
))
1375 /* Return 1 if X is an arithmetic expression that contains a multiplication
1376 and division. We don't count multiplications by powers of two here. */
1382 switch (GET_CODE (x
))
1384 case MOD
: case DIV
: case UMOD
: case UDIV
:
1388 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1389 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1391 switch (GET_RTX_CLASS (GET_CODE (x
)))
1393 case 'c': case '<': case '2':
1394 return contains_muldiv (XEXP (x
, 0))
1395 || contains_muldiv (XEXP (x
, 1));
1398 return contains_muldiv (XEXP (x
, 0));
1406 /* Try to combine the insns I1 and I2 into I3.
1407 Here I1 and I2 appear earlier than I3.
1408 I1 can be zero; then we combine just I2 into I3.
1410 It we are combining three insns and the resulting insn is not recognized,
1411 try splitting it into two insns. If that happens, I2 and I3 are retained
1412 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1415 Return 0 if the combination does not work. Then nothing is changed.
1416 If we did the combination, return the insn at which combine should
1420 try_combine (i3
, i2
, i1
)
1421 register rtx i3
, i2
, i1
;
1423 /* New patterns for I3 and I3, respectively. */
1424 rtx newpat
, newi2pat
= 0;
1425 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1426 int added_sets_1
, added_sets_2
;
1427 /* Total number of SETs to put into I3. */
1429 /* Nonzero is I2's body now appears in I3. */
1431 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1432 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1433 /* Contains I3 if the destination of I3 is used in its source, which means
1434 that the old life of I3 is being killed. If that usage is placed into
1435 I2 and not in I3, a REG_DEAD note must be made. */
1436 rtx i3dest_killed
= 0;
1437 /* SET_DEST and SET_SRC of I2 and I1. */
1438 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1439 /* PATTERN (I2), or a copy of it in certain cases. */
1441 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1442 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1443 int i1_feeds_i3
= 0;
1444 /* Notes that must be added to REG_NOTES in I3 and I2. */
1445 rtx new_i3_notes
, new_i2_notes
;
1446 /* Notes that we substituted I3 into I2 instead of the normal case. */
1447 int i3_subst_into_i2
= 0;
1448 /* Notes that I1, I2 or I3 is a MULT operation. */
1456 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1457 This can occur when flow deletes an insn that it has merged into an
1458 auto-increment address. We also can't do anything if I3 has a
1459 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1462 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1463 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1464 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1466 /* ??? This gives worse code, and appears to be unnecessary, since no
1467 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1468 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1474 undobuf
.other_insn
= 0;
1476 /* Save the current high-water-mark so we can free storage if we didn't
1477 accept this combination. */
1478 undobuf
.storage
= (char *) oballoc (0);
1480 /* Reset the hard register usage information. */
1481 CLEAR_HARD_REG_SET (newpat_used_regs
);
1483 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1484 code below, set I1 to be the earlier of the two insns. */
1485 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1486 temp
= i1
, i1
= i2
, i2
= temp
;
1488 added_links_insn
= 0;
1490 /* First check for one important special-case that the code below will
1491 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1492 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1493 we may be able to replace that destination with the destination of I3.
1494 This occurs in the common code where we compute both a quotient and
1495 remainder into a structure, in which case we want to do the computation
1496 directly into the structure to avoid register-register copies.
1498 We make very conservative checks below and only try to handle the
1499 most common cases of this. For example, we only handle the case
1500 where I2 and I3 are adjacent to avoid making difficult register
1503 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1504 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1505 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1506 && (! SMALL_REGISTER_CLASSES
1507 || (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1508 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1509 || REG_USERVAR_P (SET_DEST (PATTERN (i3
)))))
1510 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1511 && GET_CODE (PATTERN (i2
)) == PARALLEL
1512 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1513 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1514 below would need to check what is inside (and reg_overlap_mentioned_p
1515 doesn't support those codes anyway). Don't allow those destinations;
1516 the resulting insn isn't likely to be recognized anyway. */
1517 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1518 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1519 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1520 SET_DEST (PATTERN (i3
)))
1521 && next_real_insn (i2
) == i3
)
1523 rtx p2
= PATTERN (i2
);
1525 /* Make sure that the destination of I3,
1526 which we are going to substitute into one output of I2,
1527 is not used within another output of I2. We must avoid making this:
1528 (parallel [(set (mem (reg 69)) ...)
1529 (set (reg 69) ...)])
1530 which is not well-defined as to order of actions.
1531 (Besides, reload can't handle output reloads for this.)
1533 The problem can also happen if the dest of I3 is a memory ref,
1534 if another dest in I2 is an indirect memory ref. */
1535 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1536 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1537 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1538 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1539 SET_DEST (XVECEXP (p2
, 0, i
))))
1542 if (i
== XVECLEN (p2
, 0))
1543 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1544 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1549 subst_low_cuid
= INSN_CUID (i2
);
1551 added_sets_2
= added_sets_1
= 0;
1552 i2dest
= SET_SRC (PATTERN (i3
));
1554 /* Replace the dest in I2 with our dest and make the resulting
1555 insn the new pattern for I3. Then skip to where we
1556 validate the pattern. Everything was set up above. */
1557 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1558 SET_DEST (PATTERN (i3
)));
1561 i3_subst_into_i2
= 1;
1562 goto validate_replacement
;
1567 /* If we have no I1 and I2 looks like:
1568 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1570 make up a dummy I1 that is
1573 (set (reg:CC X) (compare:CC Y (const_int 0)))
1575 (We can ignore any trailing CLOBBERs.)
1577 This undoes a previous combination and allows us to match a branch-and-
1580 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1581 && XVECLEN (PATTERN (i2
), 0) >= 2
1582 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1583 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1585 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1586 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1587 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1588 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1589 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1590 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1592 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1593 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1598 /* We make I1 with the same INSN_UID as I2. This gives it
1599 the same INSN_CUID for value tracking. Our fake I1 will
1600 never appear in the insn stream so giving it the same INSN_UID
1601 as I2 will not cause a problem. */
1603 subst_prev_insn
= i1
1604 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1605 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1608 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1609 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1610 SET_DEST (PATTERN (i1
)));
1615 /* Verify that I2 and I1 are valid for combining. */
1616 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1617 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1623 /* Record whether I2DEST is used in I2SRC and similarly for the other
1624 cases. Knowing this will help in register status updating below. */
1625 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1626 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1627 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1629 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1631 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1633 /* Ensure that I3's pattern can be the destination of combines. */
1634 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1635 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1642 /* See if any of the insns is a MULT operation. Unless one is, we will
1643 reject a combination that is, since it must be slower. Be conservative
1645 if (GET_CODE (i2src
) == MULT
1646 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1647 || (GET_CODE (PATTERN (i3
)) == SET
1648 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1651 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1652 We used to do this EXCEPT in one case: I3 has a post-inc in an
1653 output operand. However, that exception can give rise to insns like
1655 which is a famous insn on the PDP-11 where the value of r3 used as the
1656 source was model-dependent. Avoid this sort of thing. */
1659 if (!(GET_CODE (PATTERN (i3
)) == SET
1660 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1661 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1662 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1663 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1664 /* It's not the exception. */
1667 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1668 if (REG_NOTE_KIND (link
) == REG_INC
1669 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1671 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1678 /* See if the SETs in I1 or I2 need to be kept around in the merged
1679 instruction: whenever the value set there is still needed past I3.
1680 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1682 For the SET in I1, we have two cases: If I1 and I2 independently
1683 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1684 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1685 in I1 needs to be kept around unless I1DEST dies or is set in either
1686 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1687 I1DEST. If so, we know I1 feeds into I2. */
1689 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1692 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1693 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1695 /* If the set in I2 needs to be kept around, we must make a copy of
1696 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1697 PATTERN (I2), we are only substituting for the original I1DEST, not into
1698 an already-substituted copy. This also prevents making self-referential
1699 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1702 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1703 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1707 i2pat
= copy_rtx (i2pat
);
1711 /* Substitute in the latest insn for the regs set by the earlier ones. */
1713 maxreg
= max_reg_num ();
1717 /* It is possible that the source of I2 or I1 may be performing an
1718 unneeded operation, such as a ZERO_EXTEND of something that is known
1719 to have the high part zero. Handle that case by letting subst look at
1720 the innermost one of them.
1722 Another way to do this would be to have a function that tries to
1723 simplify a single insn instead of merging two or more insns. We don't
1724 do this because of the potential of infinite loops and because
1725 of the potential extra memory required. However, doing it the way
1726 we are is a bit of a kludge and doesn't catch all cases.
1728 But only do this if -fexpensive-optimizations since it slows things down
1729 and doesn't usually win. */
1731 if (flag_expensive_optimizations
)
1733 /* Pass pc_rtx so no substitutions are done, just simplifications.
1734 The cases that we are interested in here do not involve the few
1735 cases were is_replaced is checked. */
1738 subst_low_cuid
= INSN_CUID (i1
);
1739 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1743 subst_low_cuid
= INSN_CUID (i2
);
1744 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1747 undobuf
.previous_undos
= undobuf
.undos
;
1751 /* Many machines that don't use CC0 have insns that can both perform an
1752 arithmetic operation and set the condition code. These operations will
1753 be represented as a PARALLEL with the first element of the vector
1754 being a COMPARE of an arithmetic operation with the constant zero.
1755 The second element of the vector will set some pseudo to the result
1756 of the same arithmetic operation. If we simplify the COMPARE, we won't
1757 match such a pattern and so will generate an extra insn. Here we test
1758 for this case, where both the comparison and the operation result are
1759 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1760 I2SRC. Later we will make the PARALLEL that contains I2. */
1762 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1763 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1764 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1765 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1767 #ifdef EXTRA_CC_MODES
1769 enum machine_mode compare_mode
;
1772 newpat
= PATTERN (i3
);
1773 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1777 #ifdef EXTRA_CC_MODES
1778 /* See if a COMPARE with the operand we substituted in should be done
1779 with the mode that is currently being used. If not, do the same
1780 processing we do in `subst' for a SET; namely, if the destination
1781 is used only once, try to replace it with a register of the proper
1782 mode and also replace the COMPARE. */
1783 if (undobuf
.other_insn
== 0
1784 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1785 &undobuf
.other_insn
))
1786 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1788 != GET_MODE (SET_DEST (newpat
))))
1790 int regno
= REGNO (SET_DEST (newpat
));
1791 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1793 if (regno
< FIRST_PSEUDO_REGISTER
1794 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1795 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1797 if (regno
>= FIRST_PSEUDO_REGISTER
)
1798 SUBST (regno_reg_rtx
[regno
], new_dest
);
1800 SUBST (SET_DEST (newpat
), new_dest
);
1801 SUBST (XEXP (*cc_use
, 0), new_dest
);
1802 SUBST (SET_SRC (newpat
),
1803 gen_rtx_combine (COMPARE
, compare_mode
,
1804 i2src
, const0_rtx
));
1807 undobuf
.other_insn
= 0;
1814 n_occurrences
= 0; /* `subst' counts here */
1816 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1817 need to make a unique copy of I2SRC each time we substitute it
1818 to avoid self-referential rtl. */
1820 subst_low_cuid
= INSN_CUID (i2
);
1821 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1822 ! i1_feeds_i3
&& i1dest_in_i1src
);
1823 undobuf
.previous_undos
= undobuf
.undos
;
1825 /* Record whether i2's body now appears within i3's body. */
1826 i2_is_used
= n_occurrences
;
1829 /* If we already got a failure, don't try to do more. Otherwise,
1830 try to substitute in I1 if we have it. */
1832 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1834 /* Before we can do this substitution, we must redo the test done
1835 above (see detailed comments there) that ensures that I1DEST
1836 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1838 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1846 subst_low_cuid
= INSN_CUID (i1
);
1847 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1848 undobuf
.previous_undos
= undobuf
.undos
;
1851 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1852 to count all the ways that I2SRC and I1SRC can be used. */
1853 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1854 && i2_is_used
+ added_sets_2
> 1)
1855 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1856 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1858 /* Fail if we tried to make a new register (we used to abort, but there's
1859 really no reason to). */
1860 || max_reg_num () != maxreg
1861 /* Fail if we couldn't do something and have a CLOBBER. */
1862 || GET_CODE (newpat
) == CLOBBER
1863 /* Fail if this new pattern is a MULT and we didn't have one before
1864 at the outer level. */
1865 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1872 /* If the actions of the earlier insns must be kept
1873 in addition to substituting them into the latest one,
1874 we must make a new PARALLEL for the latest insn
1875 to hold additional the SETs. */
1877 if (added_sets_1
|| added_sets_2
)
1881 if (GET_CODE (newpat
) == PARALLEL
)
1883 rtvec old
= XVEC (newpat
, 0);
1884 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1885 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1886 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
1887 sizeof (old
->elem
[0]) * old
->num_elem
);
1892 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1893 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1894 XVECEXP (newpat
, 0, 0) = old
;
1898 XVECEXP (newpat
, 0, --total_sets
)
1899 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1900 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1904 /* If there is no I1, use I2's body as is. We used to also not do
1905 the subst call below if I2 was substituted into I3,
1906 but that could lose a simplification. */
1908 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1910 /* See comment where i2pat is assigned. */
1911 XVECEXP (newpat
, 0, --total_sets
)
1912 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1916 /* We come here when we are replacing a destination in I2 with the
1917 destination of I3. */
1918 validate_replacement
:
1920 /* Note which hard regs this insn has as inputs. */
1921 mark_used_regs_combine (newpat
);
1923 /* Is the result of combination a valid instruction? */
1924 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1926 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1927 the second SET's destination is a register that is unused. In that case,
1928 we just need the first SET. This can occur when simplifying a divmod
1929 insn. We *must* test for this case here because the code below that
1930 splits two independent SETs doesn't handle this case correctly when it
1931 updates the register status. Also check the case where the first
1932 SET's destination is unused. That would not cause incorrect code, but
1933 does cause an unneeded insn to remain. */
1935 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1936 && XVECLEN (newpat
, 0) == 2
1937 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1938 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1939 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1940 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1941 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1942 && asm_noperands (newpat
) < 0)
1944 newpat
= XVECEXP (newpat
, 0, 0);
1945 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1948 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1949 && XVECLEN (newpat
, 0) == 2
1950 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1951 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1952 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1953 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1954 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1955 && asm_noperands (newpat
) < 0)
1957 newpat
= XVECEXP (newpat
, 0, 1);
1958 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1961 /* If we were combining three insns and the result is a simple SET
1962 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1963 insns. There are two ways to do this. It can be split using a
1964 machine-specific method (like when you have an addition of a large
1965 constant) or by combine in the function find_split_point. */
1967 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1968 && asm_noperands (newpat
) < 0)
1970 rtx m_split
, *split
;
1971 rtx ni2dest
= i2dest
;
1973 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1974 use I2DEST as a scratch register will help. In the latter case,
1975 convert I2DEST to the mode of the source of NEWPAT if we can. */
1977 m_split
= split_insns (newpat
, i3
);
1979 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1980 inputs of NEWPAT. */
1982 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1983 possible to try that as a scratch reg. This would require adding
1984 more code to make it work though. */
1986 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
1988 /* If I2DEST is a hard register or the only use of a pseudo,
1989 we can change its mode. */
1990 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
1991 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
1992 && GET_CODE (i2dest
) == REG
1993 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1994 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
1995 && ! REG_USERVAR_P (i2dest
))))
1996 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
1999 m_split
= split_insns (gen_rtx_PARALLEL
2001 gen_rtvec (2, newpat
,
2002 gen_rtx_CLOBBER (VOIDmode
,
2007 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2008 && XVECLEN (m_split
, 0) == 2
2009 && (next_real_insn (i2
) == i3
2010 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2014 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2015 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2017 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2018 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2020 /* In case we changed the mode of I2DEST, replace it in the
2021 pseudo-register table here. We can't do it above in case this
2022 code doesn't get executed and we do a split the other way. */
2024 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2025 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2027 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2029 /* If I2 or I3 has multiple SETs, we won't know how to track
2030 register status, so don't use these insns. If I2's destination
2031 is used between I2 and I3, we also can't use these insns. */
2033 if (i2_code_number
>= 0 && i2set
&& i3set
2034 && (next_real_insn (i2
) == i3
2035 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2036 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2038 if (insn_code_number
>= 0)
2041 /* It is possible that both insns now set the destination of I3.
2042 If so, we must show an extra use of it. */
2044 if (insn_code_number
>= 0)
2046 rtx new_i3_dest
= SET_DEST (i3set
);
2047 rtx new_i2_dest
= SET_DEST (i2set
);
2049 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2050 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2051 || GET_CODE (new_i3_dest
) == SUBREG
)
2052 new_i3_dest
= XEXP (new_i3_dest
, 0);
2054 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2055 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2056 || GET_CODE (new_i2_dest
) == SUBREG
)
2057 new_i2_dest
= XEXP (new_i2_dest
, 0);
2059 if (GET_CODE (new_i3_dest
) == REG
2060 && GET_CODE (new_i2_dest
) == REG
2061 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2062 REG_N_SETS (REGNO (new_i2_dest
))++;
2066 /* If we can split it and use I2DEST, go ahead and see if that
2067 helps things be recognized. Verify that none of the registers
2068 are set between I2 and I3. */
2069 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2071 && GET_CODE (i2dest
) == REG
2073 /* We need I2DEST in the proper mode. If it is a hard register
2074 or the only use of a pseudo, we can change its mode. */
2075 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2076 || GET_MODE (*split
) == VOIDmode
2077 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2078 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2079 && ! REG_USERVAR_P (i2dest
)))
2080 && (next_real_insn (i2
) == i3
2081 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2082 /* We can't overwrite I2DEST if its value is still used by
2084 && ! reg_referenced_p (i2dest
, newpat
))
2086 rtx newdest
= i2dest
;
2087 enum rtx_code split_code
= GET_CODE (*split
);
2088 enum machine_mode split_mode
= GET_MODE (*split
);
2090 /* Get NEWDEST as a register in the proper mode. We have already
2091 validated that we can do this. */
2092 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2094 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2096 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2097 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2100 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2101 an ASHIFT. This can occur if it was inside a PLUS and hence
2102 appeared to be a memory address. This is a kludge. */
2103 if (split_code
== MULT
2104 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2105 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2107 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2108 XEXP (*split
, 0), GEN_INT (i
)));
2109 /* Update split_code because we may not have a multiply
2111 split_code
= GET_CODE (*split
);
2114 #ifdef INSN_SCHEDULING
2115 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2116 be written as a ZERO_EXTEND. */
2117 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2118 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2122 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2123 SUBST (*split
, newdest
);
2124 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2126 /* If the split point was a MULT and we didn't have one before,
2127 don't use one now. */
2128 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2129 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2133 /* Check for a case where we loaded from memory in a narrow mode and
2134 then sign extended it, but we need both registers. In that case,
2135 we have a PARALLEL with both loads from the same memory location.
2136 We can split this into a load from memory followed by a register-register
2137 copy. This saves at least one insn, more if register allocation can
2140 We cannot do this if the destination of the second assignment is
2141 a register that we have already assumed is zero-extended. Similarly
2142 for a SUBREG of such a register. */
2144 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2145 && GET_CODE (newpat
) == PARALLEL
2146 && XVECLEN (newpat
, 0) == 2
2147 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2148 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2149 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2150 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2151 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2152 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2154 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2155 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2156 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2157 (GET_CODE (temp
) == REG
2158 && reg_nonzero_bits
[REGNO (temp
)] != 0
2159 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2160 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2161 && (reg_nonzero_bits
[REGNO (temp
)]
2162 != GET_MODE_MASK (word_mode
))))
2163 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2164 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2165 (GET_CODE (temp
) == REG
2166 && reg_nonzero_bits
[REGNO (temp
)] != 0
2167 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2168 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2169 && (reg_nonzero_bits
[REGNO (temp
)]
2170 != GET_MODE_MASK (word_mode
)))))
2171 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2172 SET_SRC (XVECEXP (newpat
, 0, 1)))
2173 && ! find_reg_note (i3
, REG_UNUSED
,
2174 SET_DEST (XVECEXP (newpat
, 0, 0))))
2178 newi2pat
= XVECEXP (newpat
, 0, 0);
2179 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2180 newpat
= XVECEXP (newpat
, 0, 1);
2181 SUBST (SET_SRC (newpat
),
2182 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2183 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2185 if (i2_code_number
>= 0)
2186 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2188 if (insn_code_number
>= 0)
2193 /* If we will be able to accept this, we have made a change to the
2194 destination of I3. This can invalidate a LOG_LINKS pointing
2195 to I3. No other part of combine.c makes such a transformation.
2197 The new I3 will have a destination that was previously the
2198 destination of I1 or I2 and which was used in i2 or I3. Call
2199 distribute_links to make a LOG_LINK from the next use of
2200 that destination. */
2202 PATTERN (i3
) = newpat
;
2203 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2205 /* I3 now uses what used to be its destination and which is
2206 now I2's destination. That means we need a LOG_LINK from
2207 I3 to I2. But we used to have one, so we still will.
2209 However, some later insn might be using I2's dest and have
2210 a LOG_LINK pointing at I3. We must remove this link.
2211 The simplest way to remove the link is to point it at I1,
2212 which we know will be a NOTE. */
2214 for (insn
= NEXT_INSN (i3
);
2215 insn
&& (this_basic_block
== n_basic_blocks
- 1
2216 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2217 insn
= NEXT_INSN (insn
))
2219 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
2220 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2222 for (link
= LOG_LINKS (insn
); link
;
2223 link
= XEXP (link
, 1))
2224 if (XEXP (link
, 0) == i3
)
2225 XEXP (link
, 0) = i1
;
2233 /* Similarly, check for a case where we have a PARALLEL of two independent
2234 SETs but we started with three insns. In this case, we can do the sets
2235 as two separate insns. This case occurs when some SET allows two
2236 other insns to combine, but the destination of that SET is still live. */
2238 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2239 && GET_CODE (newpat
) == PARALLEL
2240 && XVECLEN (newpat
, 0) == 2
2241 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2242 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2243 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2244 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2245 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2246 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2247 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2249 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2250 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2251 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2252 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2253 XVECEXP (newpat
, 0, 0))
2254 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2255 XVECEXP (newpat
, 0, 1))
2256 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2257 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2259 /* Normally, it doesn't matter which of the two is done first,
2260 but it does if one references cc0. In that case, it has to
2263 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2265 newi2pat
= XVECEXP (newpat
, 0, 0);
2266 newpat
= XVECEXP (newpat
, 0, 1);
2271 newi2pat
= XVECEXP (newpat
, 0, 1);
2272 newpat
= XVECEXP (newpat
, 0, 0);
2275 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2277 if (i2_code_number
>= 0)
2278 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2281 /* If it still isn't recognized, fail and change things back the way they
2283 if ((insn_code_number
< 0
2284 /* Is the result a reasonable ASM_OPERANDS? */
2285 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2291 /* If we had to change another insn, make sure it is valid also. */
2292 if (undobuf
.other_insn
)
2294 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2295 rtx new_other_notes
;
2298 CLEAR_HARD_REG_SET (newpat_used_regs
);
2300 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2303 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2309 PATTERN (undobuf
.other_insn
) = other_pat
;
2311 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2312 are still valid. Then add any non-duplicate notes added by
2313 recog_for_combine. */
2314 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2316 next
= XEXP (note
, 1);
2318 if (REG_NOTE_KIND (note
) == REG_UNUSED
2319 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2321 if (GET_CODE (XEXP (note
, 0)) == REG
)
2322 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2324 remove_note (undobuf
.other_insn
, note
);
2328 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2329 if (GET_CODE (XEXP (note
, 0)) == REG
)
2330 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2332 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2333 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2336 /* We now know that we can do this combination. Merge the insns and
2337 update the status of registers and LOG_LINKS. */
2340 rtx i3notes
, i2notes
, i1notes
= 0;
2341 rtx i3links
, i2links
, i1links
= 0;
2344 /* Compute which registers we expect to eliminate. newi2pat may be setting
2345 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2346 same as i3dest, in which case newi2pat may be setting i1dest. */
2347 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2348 || i2dest_in_i2src
|| i2dest_in_i1src
2350 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2351 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2354 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2356 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2357 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2359 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2361 /* Ensure that we do not have something that should not be shared but
2362 occurs multiple times in the new insns. Check this by first
2363 resetting all the `used' flags and then copying anything is shared. */
2365 reset_used_flags (i3notes
);
2366 reset_used_flags (i2notes
);
2367 reset_used_flags (i1notes
);
2368 reset_used_flags (newpat
);
2369 reset_used_flags (newi2pat
);
2370 if (undobuf
.other_insn
)
2371 reset_used_flags (PATTERN (undobuf
.other_insn
));
2373 i3notes
= copy_rtx_if_shared (i3notes
);
2374 i2notes
= copy_rtx_if_shared (i2notes
);
2375 i1notes
= copy_rtx_if_shared (i1notes
);
2376 newpat
= copy_rtx_if_shared (newpat
);
2377 newi2pat
= copy_rtx_if_shared (newi2pat
);
2378 if (undobuf
.other_insn
)
2379 reset_used_flags (PATTERN (undobuf
.other_insn
));
2381 INSN_CODE (i3
) = insn_code_number
;
2382 PATTERN (i3
) = newpat
;
2383 if (undobuf
.other_insn
)
2384 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2386 /* We had one special case above where I2 had more than one set and
2387 we replaced a destination of one of those sets with the destination
2388 of I3. In that case, we have to update LOG_LINKS of insns later
2389 in this basic block. Note that this (expensive) case is rare.
2391 Also, in this case, we must pretend that all REG_NOTEs for I2
2392 actually came from I3, so that REG_UNUSED notes from I2 will be
2393 properly handled. */
2395 if (i3_subst_into_i2
)
2397 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2398 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2399 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2400 && ! find_reg_note (i2
, REG_UNUSED
,
2401 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2402 for (temp
= NEXT_INSN (i2
);
2403 temp
&& (this_basic_block
== n_basic_blocks
- 1
2404 || BLOCK_HEAD (this_basic_block
) != temp
);
2405 temp
= NEXT_INSN (temp
))
2406 if (temp
!= i3
&& GET_RTX_CLASS (GET_CODE (temp
)) == 'i')
2407 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2408 if (XEXP (link
, 0) == i2
)
2409 XEXP (link
, 0) = i3
;
2414 while (XEXP (link
, 1))
2415 link
= XEXP (link
, 1);
2416 XEXP (link
, 1) = i2notes
;
2430 INSN_CODE (i2
) = i2_code_number
;
2431 PATTERN (i2
) = newi2pat
;
2435 PUT_CODE (i2
, NOTE
);
2436 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2437 NOTE_SOURCE_FILE (i2
) = 0;
2444 PUT_CODE (i1
, NOTE
);
2445 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2446 NOTE_SOURCE_FILE (i1
) = 0;
2449 /* Get death notes for everything that is now used in either I3 or
2450 I2 and used to die in a previous insn. If we built two new
2451 patterns, move from I1 to I2 then I2 to I3 so that we get the
2452 proper movement on registers that I2 modifies. */
2456 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2457 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2460 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2463 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2465 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2468 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2471 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2474 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2477 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2478 know these are REG_UNUSED and want them to go to the desired insn,
2479 so we always pass it as i3. We have not counted the notes in
2480 reg_n_deaths yet, so we need to do so now. */
2482 if (newi2pat
&& new_i2_notes
)
2484 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2485 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2486 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2488 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2493 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2494 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2495 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2497 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2500 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2501 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2502 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2503 in that case, it might delete I2. Similarly for I2 and I1.
2504 Show an additional death due to the REG_DEAD note we make here. If
2505 we discard it in distribute_notes, we will decrement it again. */
2509 if (GET_CODE (i3dest_killed
) == REG
)
2510 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2512 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2513 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2515 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2517 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2519 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2523 if (i2dest_in_i2src
)
2525 if (GET_CODE (i2dest
) == REG
)
2526 REG_N_DEATHS (REGNO (i2dest
))++;
2528 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2529 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2530 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2532 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2533 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2534 NULL_RTX
, NULL_RTX
);
2537 if (i1dest_in_i1src
)
2539 if (GET_CODE (i1dest
) == REG
)
2540 REG_N_DEATHS (REGNO (i1dest
))++;
2542 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2543 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2544 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2546 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2547 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2548 NULL_RTX
, NULL_RTX
);
2551 distribute_links (i3links
);
2552 distribute_links (i2links
);
2553 distribute_links (i1links
);
2555 if (GET_CODE (i2dest
) == REG
)
2558 rtx i2_insn
= 0, i2_val
= 0, set
;
2560 /* The insn that used to set this register doesn't exist, and
2561 this life of the register may not exist either. See if one of
2562 I3's links points to an insn that sets I2DEST. If it does,
2563 that is now the last known value for I2DEST. If we don't update
2564 this and I2 set the register to a value that depended on its old
2565 contents, we will get confused. If this insn is used, thing
2566 will be set correctly in combine_instructions. */
2568 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2569 if ((set
= single_set (XEXP (link
, 0))) != 0
2570 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2571 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2573 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2575 /* If the reg formerly set in I2 died only once and that was in I3,
2576 zero its use count so it won't make `reload' do any work. */
2578 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2579 && ! i2dest_in_i2src
)
2581 regno
= REGNO (i2dest
);
2582 REG_N_SETS (regno
)--;
2583 if (REG_N_SETS (regno
) == 0
2584 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
2586 REG_N_REFS (regno
) = 0;
2590 if (i1
&& GET_CODE (i1dest
) == REG
)
2593 rtx i1_insn
= 0, i1_val
= 0, set
;
2595 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2596 if ((set
= single_set (XEXP (link
, 0))) != 0
2597 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2598 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2600 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2602 regno
= REGNO (i1dest
);
2603 if (! added_sets_1
&& ! i1dest_in_i1src
)
2605 REG_N_SETS (regno
)--;
2606 if (REG_N_SETS (regno
) == 0
2607 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
2609 REG_N_REFS (regno
) = 0;
2613 /* Update reg_nonzero_bits et al for any changes that may have been made
2616 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2618 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2620 /* If I3 is now an unconditional jump, ensure that it has a
2621 BARRIER following it since it may have initially been a
2622 conditional jump. It may also be the last nonnote insn. */
2624 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
2625 && ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2626 || GET_CODE (temp
) != BARRIER
))
2627 emit_barrier_after (i3
);
2630 combine_successes
++;
2633 /* Clear this here, so that subsequent get_last_value calls are not
2635 subst_prev_insn
= NULL_RTX
;
2637 if (added_links_insn
2638 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2639 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2640 return added_links_insn
;
2642 return newi2pat
? i2
: i3
;
2645 /* Undo all the modifications recorded in undobuf. */
2650 struct undo
*undo
, *next
;
2652 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2656 *undo
->where
.i
= undo
->old_contents
.i
;
2658 *undo
->where
.r
= undo
->old_contents
.r
;
2660 undo
->next
= undobuf
.frees
;
2661 undobuf
.frees
= undo
;
2664 obfree (undobuf
.storage
);
2665 undobuf
.undos
= undobuf
.previous_undos
= 0;
2667 /* Clear this here, so that subsequent get_last_value calls are not
2669 subst_prev_insn
= NULL_RTX
;
2672 /* We've committed to accepting the changes we made. Move all
2673 of the undos to the free list. */
2678 struct undo
*undo
, *next
;
2680 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2683 undo
->next
= undobuf
.frees
;
2684 undobuf
.frees
= undo
;
2686 undobuf
.undos
= undobuf
.previous_undos
= 0;
2690 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2691 where we have an arithmetic expression and return that point. LOC will
2694 try_combine will call this function to see if an insn can be split into
2698 find_split_point (loc
, insn
)
2703 enum rtx_code code
= GET_CODE (x
);
2705 int len
= 0, pos
= 0, unsignedp
= 0;
2706 rtx inner
= NULL_RTX
;
2708 /* First special-case some codes. */
2712 #ifdef INSN_SCHEDULING
2713 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2715 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2718 return find_split_point (&SUBREG_REG (x
), insn
);
2722 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2723 using LO_SUM and HIGH. */
2724 if (GET_CODE (XEXP (x
, 0)) == CONST
2725 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2728 gen_rtx_combine (LO_SUM
, Pmode
,
2729 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2731 return &XEXP (XEXP (x
, 0), 0);
2735 /* If we have a PLUS whose second operand is a constant and the
2736 address is not valid, perhaps will can split it up using
2737 the machine-specific way to split large constants. We use
2738 the first pseudo-reg (one of the virtual regs) as a placeholder;
2739 it will not remain in the result. */
2740 if (GET_CODE (XEXP (x
, 0)) == PLUS
2741 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2742 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2744 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2745 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2748 /* This should have produced two insns, each of which sets our
2749 placeholder. If the source of the second is a valid address,
2750 we can make put both sources together and make a split point
2753 if (seq
&& XVECLEN (seq
, 0) == 2
2754 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2755 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2756 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2757 && ! reg_mentioned_p (reg
,
2758 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2759 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2760 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2761 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2762 && memory_address_p (GET_MODE (x
),
2763 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2765 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2766 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2768 /* Replace the placeholder in SRC2 with SRC1. If we can
2769 find where in SRC2 it was placed, that can become our
2770 split point and we can replace this address with SRC2.
2771 Just try two obvious places. */
2773 src2
= replace_rtx (src2
, reg
, src1
);
2775 if (XEXP (src2
, 0) == src1
)
2776 split
= &XEXP (src2
, 0);
2777 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2778 && XEXP (XEXP (src2
, 0), 0) == src1
)
2779 split
= &XEXP (XEXP (src2
, 0), 0);
2783 SUBST (XEXP (x
, 0), src2
);
2788 /* If that didn't work, perhaps the first operand is complex and
2789 needs to be computed separately, so make a split point there.
2790 This will occur on machines that just support REG + CONST
2791 and have a constant moved through some previous computation. */
2793 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2794 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2795 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2797 return &XEXP (XEXP (x
, 0), 0);
2803 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2804 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2805 we need to put the operand into a register. So split at that
2808 if (SET_DEST (x
) == cc0_rtx
2809 && GET_CODE (SET_SRC (x
)) != COMPARE
2810 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2811 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2812 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2813 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2814 return &SET_SRC (x
);
2817 /* See if we can split SET_SRC as it stands. */
2818 split
= find_split_point (&SET_SRC (x
), insn
);
2819 if (split
&& split
!= &SET_SRC (x
))
2822 /* See if we can split SET_DEST as it stands. */
2823 split
= find_split_point (&SET_DEST (x
), insn
);
2824 if (split
&& split
!= &SET_DEST (x
))
2827 /* See if this is a bitfield assignment with everything constant. If
2828 so, this is an IOR of an AND, so split it into that. */
2829 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2830 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2831 <= HOST_BITS_PER_WIDE_INT
)
2832 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2833 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2834 && GET_CODE (SET_SRC (x
)) == CONST_INT
2835 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2836 + INTVAL (XEXP (SET_DEST (x
), 2)))
2837 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2838 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2840 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2841 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2842 int src
= INTVAL (SET_SRC (x
));
2843 rtx dest
= XEXP (SET_DEST (x
), 0);
2844 enum machine_mode mode
= GET_MODE (dest
);
2845 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2847 if (BITS_BIG_ENDIAN
)
2848 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2850 if ((unsigned HOST_WIDE_INT
) src
== mask
)
2852 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2855 gen_binary (IOR
, mode
,
2856 gen_binary (AND
, mode
, dest
,
2857 GEN_INT (~ (mask
<< pos
)
2858 & GET_MODE_MASK (mode
))),
2859 GEN_INT (src
<< pos
)));
2861 SUBST (SET_DEST (x
), dest
);
2863 split
= find_split_point (&SET_SRC (x
), insn
);
2864 if (split
&& split
!= &SET_SRC (x
))
2868 /* Otherwise, see if this is an operation that we can split into two.
2869 If so, try to split that. */
2870 code
= GET_CODE (SET_SRC (x
));
2875 /* If we are AND'ing with a large constant that is only a single
2876 bit and the result is only being used in a context where we
2877 need to know if it is zero or non-zero, replace it with a bit
2878 extraction. This will avoid the large constant, which might
2879 have taken more than one insn to make. If the constant were
2880 not a valid argument to the AND but took only one insn to make,
2881 this is no worse, but if it took more than one insn, it will
2884 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2885 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2886 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
2887 && GET_CODE (SET_DEST (x
)) == REG
2888 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
2889 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
2890 && XEXP (*split
, 0) == SET_DEST (x
)
2891 && XEXP (*split
, 1) == const0_rtx
)
2893 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
2894 XEXP (SET_SRC (x
), 0),
2895 pos
, NULL_RTX
, 1, 1, 0, 0);
2896 if (extraction
!= 0)
2898 SUBST (SET_SRC (x
), extraction
);
2899 return find_split_point (loc
, insn
);
2905 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2906 is known to be on, this can be converted into a NEG of a shift. */
2907 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
2908 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
2909 && 1 <= (pos
= exact_log2
2910 (nonzero_bits (XEXP (SET_SRC (x
), 0),
2911 GET_MODE (XEXP (SET_SRC (x
), 0))))))
2913 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
2916 gen_rtx_combine (NEG
, mode
,
2917 gen_rtx_combine (LSHIFTRT
, mode
,
2918 XEXP (SET_SRC (x
), 0),
2921 split
= find_split_point (&SET_SRC (x
), insn
);
2922 if (split
&& split
!= &SET_SRC (x
))
2928 inner
= XEXP (SET_SRC (x
), 0);
2930 /* We can't optimize if either mode is a partial integer
2931 mode as we don't know how many bits are significant
2933 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
2934 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
2938 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2944 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2945 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2947 inner
= XEXP (SET_SRC (x
), 0);
2948 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2949 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2951 if (BITS_BIG_ENDIAN
)
2952 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2953 unsignedp
= (code
== ZERO_EXTRACT
);
2961 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2963 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2965 /* For unsigned, we have a choice of a shift followed by an
2966 AND or two shifts. Use two shifts for field sizes where the
2967 constant might be too large. We assume here that we can
2968 always at least get 8-bit constants in an AND insn, which is
2969 true for every current RISC. */
2971 if (unsignedp
&& len
<= 8)
2976 gen_rtx_combine (LSHIFTRT
, mode
,
2977 gen_lowpart_for_combine (mode
, inner
),
2979 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
2981 split
= find_split_point (&SET_SRC (x
), insn
);
2982 if (split
&& split
!= &SET_SRC (x
))
2989 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
2990 gen_rtx_combine (ASHIFT
, mode
,
2991 gen_lowpart_for_combine (mode
, inner
),
2992 GEN_INT (GET_MODE_BITSIZE (mode
)
2994 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
2996 split
= find_split_point (&SET_SRC (x
), insn
);
2997 if (split
&& split
!= &SET_SRC (x
))
3002 /* See if this is a simple operation with a constant as the second
3003 operand. It might be that this constant is out of range and hence
3004 could be used as a split point. */
3005 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3006 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3007 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3008 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3009 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3010 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3011 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3013 return &XEXP (SET_SRC (x
), 1);
3015 /* Finally, see if this is a simple operation with its first operand
3016 not in a register. The operation might require this operand in a
3017 register, so return it as a split point. We can always do this
3018 because if the first operand were another operation, we would have
3019 already found it as a split point. */
3020 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3021 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3022 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3023 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3024 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3025 return &XEXP (SET_SRC (x
), 0);
3031 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3032 it is better to write this as (not (ior A B)) so we can split it.
3033 Similarly for IOR. */
3034 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3037 gen_rtx_combine (NOT
, GET_MODE (x
),
3038 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3040 XEXP (XEXP (x
, 0), 0),
3041 XEXP (XEXP (x
, 1), 0))));
3042 return find_split_point (loc
, insn
);
3045 /* Many RISC machines have a large set of logical insns. If the
3046 second operand is a NOT, put it first so we will try to split the
3047 other operand first. */
3048 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3050 rtx tem
= XEXP (x
, 0);
3051 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3052 SUBST (XEXP (x
, 1), tem
);
3060 /* Otherwise, select our actions depending on our rtx class. */
3061 switch (GET_RTX_CLASS (code
))
3063 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3065 split
= find_split_point (&XEXP (x
, 2), insn
);
3068 /* ... fall through ... */
3072 split
= find_split_point (&XEXP (x
, 1), insn
);
3075 /* ... fall through ... */
3077 /* Some machines have (and (shift ...) ...) insns. If X is not
3078 an AND, but XEXP (X, 0) is, use it as our split point. */
3079 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3080 return &XEXP (x
, 0);
3082 split
= find_split_point (&XEXP (x
, 0), insn
);
3088 /* Otherwise, we don't have a split point. */
3092 /* Throughout X, replace FROM with TO, and return the result.
3093 The result is TO if X is FROM;
3094 otherwise the result is X, but its contents may have been modified.
3095 If they were modified, a record was made in undobuf so that
3096 undo_all will (among other things) return X to its original state.
3098 If the number of changes necessary is too much to record to undo,
3099 the excess changes are not made, so the result is invalid.
3100 The changes already made can still be undone.
3101 undobuf.num_undo is incremented for such changes, so by testing that
3102 the caller can tell whether the result is valid.
3104 `n_occurrences' is incremented each time FROM is replaced.
3106 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3108 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3109 by copying if `n_occurrences' is non-zero. */
3112 subst (x
, from
, to
, in_dest
, unique_copy
)
3113 register rtx x
, from
, to
;
3117 register enum rtx_code code
= GET_CODE (x
);
3118 enum machine_mode op0_mode
= VOIDmode
;
3119 register const char *fmt
;
3120 register int len
, i
;
3123 /* Two expressions are equal if they are identical copies of a shared
3124 RTX or if they are both registers with the same register number
3127 #define COMBINE_RTX_EQUAL_P(X,Y) \
3129 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3130 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3132 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3135 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3138 /* If X and FROM are the same register but different modes, they will
3139 not have been seen as equal above. However, flow.c will make a
3140 LOG_LINKS entry for that case. If we do nothing, we will try to
3141 rerecognize our original insn and, when it succeeds, we will
3142 delete the feeding insn, which is incorrect.
3144 So force this insn not to match in this (rare) case. */
3145 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3146 && REGNO (x
) == REGNO (from
))
3147 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3149 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3150 of which may contain things that can be combined. */
3151 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3154 /* It is possible to have a subexpression appear twice in the insn.
3155 Suppose that FROM is a register that appears within TO.
3156 Then, after that subexpression has been scanned once by `subst',
3157 the second time it is scanned, TO may be found. If we were
3158 to scan TO here, we would find FROM within it and create a
3159 self-referent rtl structure which is completely wrong. */
3160 if (COMBINE_RTX_EQUAL_P (x
, to
))
3163 /* Parallel asm_operands need special attention because all of the
3164 inputs are shared across the arms. Furthermore, unsharing the
3165 rtl results in recognition failures. Failure to handle this case
3166 specially can result in circular rtl.
3168 Solve this by doing a normal pass across the first entry of the
3169 parallel, and only processing the SET_DESTs of the subsequent
3172 if (code
== PARALLEL
3173 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3174 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3176 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3178 /* If this substitution failed, this whole thing fails. */
3179 if (GET_CODE (new) == CLOBBER
3180 && XEXP (new, 0) == const0_rtx
)
3183 SUBST (XVECEXP (x
, 0, 0), new);
3185 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3187 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3189 if (GET_CODE (dest
) != REG
3190 && GET_CODE (dest
) != CC0
3191 && GET_CODE (dest
) != PC
)
3193 new = subst (dest
, from
, to
, 0, unique_copy
);
3195 /* If this substitution failed, this whole thing fails. */
3196 if (GET_CODE (new) == CLOBBER
3197 && XEXP (new, 0) == const0_rtx
)
3200 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3206 len
= GET_RTX_LENGTH (code
);
3207 fmt
= GET_RTX_FORMAT (code
);
3209 /* We don't need to process a SET_DEST that is a register, CC0,
3210 or PC, so set up to skip this common case. All other cases
3211 where we want to suppress replacing something inside a
3212 SET_SRC are handled via the IN_DEST operand. */
3214 && (GET_CODE (SET_DEST (x
)) == REG
3215 || GET_CODE (SET_DEST (x
)) == CC0
3216 || GET_CODE (SET_DEST (x
)) == PC
))
3219 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3222 op0_mode
= GET_MODE (XEXP (x
, 0));
3224 for (i
= 0; i
< len
; i
++)
3229 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3231 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3233 new = (unique_copy
&& n_occurrences
3234 ? copy_rtx (to
) : to
);
3239 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3242 /* If this substitution failed, this whole thing
3244 if (GET_CODE (new) == CLOBBER
3245 && XEXP (new, 0) == const0_rtx
)
3249 SUBST (XVECEXP (x
, i
, j
), new);
3252 else if (fmt
[i
] == 'e')
3254 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3256 /* In general, don't install a subreg involving two
3257 modes not tieable. It can worsen register
3258 allocation, and can even make invalid reload
3259 insns, since the reg inside may need to be copied
3260 from in the outside mode, and that may be invalid
3261 if it is an fp reg copied in integer mode.
3263 We allow two exceptions to this: It is valid if
3264 it is inside another SUBREG and the mode of that
3265 SUBREG and the mode of the inside of TO is
3266 tieable and it is valid if X is a SET that copies
3269 if (GET_CODE (to
) == SUBREG
3270 && ! MODES_TIEABLE_P (GET_MODE (to
),
3271 GET_MODE (SUBREG_REG (to
)))
3272 && ! (code
== SUBREG
3273 && MODES_TIEABLE_P (GET_MODE (x
),
3274 GET_MODE (SUBREG_REG (to
))))
3276 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3279 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3281 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3285 /* If we are in a SET_DEST, suppress most cases unless we
3286 have gone inside a MEM, in which case we want to
3287 simplify the address. We assume here that things that
3288 are actually part of the destination have their inner
3289 parts in the first expression. This is true for SUBREG,
3290 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3291 things aside from REG and MEM that should appear in a
3293 new = subst (XEXP (x
, i
), from
, to
,
3295 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3296 || code
== ZERO_EXTRACT
))
3298 && i
== 0), unique_copy
);
3300 /* If we found that we will have to reject this combination,
3301 indicate that by returning the CLOBBER ourselves, rather than
3302 an expression containing it. This will speed things up as
3303 well as prevent accidents where two CLOBBERs are considered
3304 to be equal, thus producing an incorrect simplification. */
3306 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3309 SUBST (XEXP (x
, i
), new);
3314 /* Try to simplify X. If the simplification changed the code, it is likely
3315 that further simplification will help, so loop, but limit the number
3316 of repetitions that will be performed. */
3318 for (i
= 0; i
< 4; i
++)
3320 /* If X is sufficiently simple, don't bother trying to do anything
3322 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3323 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3325 if (GET_CODE (x
) == code
)
3328 code
= GET_CODE (x
);
3330 /* We no longer know the original mode of operand 0 since we
3331 have changed the form of X) */
3332 op0_mode
= VOIDmode
;
3338 /* Simplify X, a piece of RTL. We just operate on the expression at the
3339 outer level; call `subst' to simplify recursively. Return the new
3342 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3343 will be the iteration even if an expression with a code different from
3344 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3347 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3349 enum machine_mode op0_mode
;
3353 enum rtx_code code
= GET_CODE (x
);
3354 enum machine_mode mode
= GET_MODE (x
);
3358 /* If this is a commutative operation, put a constant last and a complex
3359 expression first. We don't need to do this for comparisons here. */
3360 if (GET_RTX_CLASS (code
) == 'c'
3361 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3362 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3363 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3364 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3365 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3366 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3369 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3370 SUBST (XEXP (x
, 1), temp
);
3373 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3374 sign extension of a PLUS with a constant, reverse the order of the sign
3375 extension and the addition. Note that this not the same as the original
3376 code, but overflow is undefined for signed values. Also note that the
3377 PLUS will have been partially moved "inside" the sign-extension, so that
3378 the first operand of X will really look like:
3379 (ashiftrt (plus (ashift A C4) C5) C4).
3381 (plus (ashiftrt (ashift A C4) C2) C4)
3382 and replace the first operand of X with that expression. Later parts
3383 of this function may simplify the expression further.
3385 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3386 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3387 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3389 We do this to simplify address expressions. */
3391 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3392 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3393 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3394 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3395 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3396 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3397 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3398 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3399 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3400 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3401 XEXP (XEXP (x
, 0), 1))) != 0)
3404 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3405 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3406 INTVAL (XEXP (XEXP (x
, 0), 1)));
3408 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3409 INTVAL (XEXP (XEXP (x
, 0), 1)));
3411 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3414 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3415 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3416 things. Check for cases where both arms are testing the same
3419 Don't do anything if all operands are very simple. */
3421 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3422 || GET_RTX_CLASS (code
) == '<')
3423 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3424 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3425 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3427 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3428 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3429 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3431 || (GET_RTX_CLASS (code
) == '1'
3432 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3433 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3434 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3437 rtx cond
, true, false;
3439 cond
= if_then_else_cond (x
, &true, &false);
3441 /* If everything is a comparison, what we have is highly unlikely
3442 to be simpler, so don't use it. */
3443 && ! (GET_RTX_CLASS (code
) == '<'
3444 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3445 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3447 rtx cop1
= const0_rtx
;
3448 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3450 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3453 /* Simplify the alternative arms; this may collapse the true and
3454 false arms to store-flag values. */
3455 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3456 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3458 /* Restarting if we generate a store-flag expression will cause
3459 us to loop. Just drop through in this case. */
3461 /* If the result values are STORE_FLAG_VALUE and zero, we can
3462 just make the comparison operation. */
3463 if (true == const_true_rtx
&& false == const0_rtx
)
3464 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3465 else if (true == const0_rtx
&& false == const_true_rtx
)
3466 x
= gen_binary (reverse_condition (cond_code
), mode
, cond
, cop1
);
3468 /* Likewise, we can make the negate of a comparison operation
3469 if the result values are - STORE_FLAG_VALUE and zero. */
3470 else if (GET_CODE (true) == CONST_INT
3471 && INTVAL (true) == - STORE_FLAG_VALUE
3472 && false == const0_rtx
)
3473 x
= gen_unary (NEG
, mode
, mode
,
3474 gen_binary (cond_code
, mode
, cond
, cop1
));
3475 else if (GET_CODE (false) == CONST_INT
3476 && INTVAL (false) == - STORE_FLAG_VALUE
3477 && true == const0_rtx
)
3478 x
= gen_unary (NEG
, mode
, mode
,
3479 gen_binary (reverse_condition (cond_code
),
3482 return gen_rtx_IF_THEN_ELSE (mode
,
3483 gen_binary (cond_code
, VOIDmode
,
3487 code
= GET_CODE (x
);
3488 op0_mode
= VOIDmode
;
3492 /* Try to fold this expression in case we have constants that weren't
3495 switch (GET_RTX_CLASS (code
))
3498 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3501 temp
= simplify_relational_operation (code
, op0_mode
,
3502 XEXP (x
, 0), XEXP (x
, 1));
3503 #ifdef FLOAT_STORE_FLAG_VALUE
3504 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3505 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
3506 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
3511 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3515 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3516 XEXP (x
, 1), XEXP (x
, 2));
3521 x
= temp
, code
= GET_CODE (temp
);
3523 /* First see if we can apply the inverse distributive law. */
3524 if (code
== PLUS
|| code
== MINUS
3525 || code
== AND
|| code
== IOR
|| code
== XOR
)
3527 x
= apply_distributive_law (x
);
3528 code
= GET_CODE (x
);
3531 /* If CODE is an associative operation not otherwise handled, see if we
3532 can associate some operands. This can win if they are constants or
3533 if they are logically related (i.e. (a & b) & a. */
3534 if ((code
== PLUS
|| code
== MINUS
3535 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3536 || code
== DIV
|| code
== UDIV
3537 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3538 && INTEGRAL_MODE_P (mode
))
3540 if (GET_CODE (XEXP (x
, 0)) == code
)
3542 rtx other
= XEXP (XEXP (x
, 0), 0);
3543 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3544 rtx inner_op1
= XEXP (x
, 1);
3547 /* Make sure we pass the constant operand if any as the second
3548 one if this is a commutative operation. */
3549 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3551 rtx tem
= inner_op0
;
3552 inner_op0
= inner_op1
;
3555 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3556 : code
== DIV
? MULT
3557 : code
== UDIV
? MULT
3559 mode
, inner_op0
, inner_op1
);
3561 /* For commutative operations, try the other pair if that one
3563 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3565 other
= XEXP (XEXP (x
, 0), 1);
3566 inner
= simplify_binary_operation (code
, mode
,
3567 XEXP (XEXP (x
, 0), 0),
3572 return gen_binary (code
, mode
, other
, inner
);
3576 /* A little bit of algebraic simplification here. */
3580 /* Ensure that our address has any ASHIFTs converted to MULT in case
3581 address-recognizing predicates are called later. */
3582 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3583 SUBST (XEXP (x
, 0), temp
);
3587 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3588 is paradoxical. If we can't do that safely, then it becomes
3589 something nonsensical so that this combination won't take place. */
3591 if (GET_CODE (SUBREG_REG (x
)) == MEM
3592 && (GET_MODE_SIZE (mode
)
3593 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3595 rtx inner
= SUBREG_REG (x
);
3596 int endian_offset
= 0;
3597 /* Don't change the mode of the MEM
3598 if that would change the meaning of the address. */
3599 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3600 || mode_dependent_address_p (XEXP (inner
, 0)))
3601 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3603 if (BYTES_BIG_ENDIAN
)
3605 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3606 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3607 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3608 endian_offset
-= (UNITS_PER_WORD
3609 - GET_MODE_SIZE (GET_MODE (inner
)));
3611 /* Note if the plus_constant doesn't make a valid address
3612 then this combination won't be accepted. */
3613 x
= gen_rtx_MEM (mode
,
3614 plus_constant (XEXP (inner
, 0),
3615 (SUBREG_WORD (x
) * UNITS_PER_WORD
3617 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
3618 MEM_COPY_ATTRIBUTES (x
, inner
);
3622 /* If we are in a SET_DEST, these other cases can't apply. */
3626 /* Changing mode twice with SUBREG => just change it once,
3627 or not at all if changing back to starting mode. */
3628 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3630 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3631 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3632 return SUBREG_REG (SUBREG_REG (x
));
3634 SUBST_INT (SUBREG_WORD (x
),
3635 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3636 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3639 /* SUBREG of a hard register => just change the register number
3640 and/or mode. If the hard register is not valid in that mode,
3641 suppress this combination. If the hard register is the stack,
3642 frame, or argument pointer, leave this as a SUBREG. */
3644 if (GET_CODE (SUBREG_REG (x
)) == REG
3645 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3646 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3647 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3648 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3650 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3651 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3653 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3655 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3657 return gen_rtx_REG (mode
,
3658 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3660 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3663 /* For a constant, try to pick up the part we want. Handle a full
3664 word and low-order part. Only do this if we are narrowing
3665 the constant; if it is being widened, we have no idea what
3666 the extra bits will have been set to. */
3668 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3669 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3670 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3671 && GET_MODE_CLASS (mode
) == MODE_INT
)
3673 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3679 /* If we want a subreg of a constant, at offset 0,
3680 take the low bits. On a little-endian machine, that's
3681 always valid. On a big-endian machine, it's valid
3682 only if the constant's mode fits in one word. Note that we
3683 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3684 if (CONSTANT_P (SUBREG_REG (x
))
3685 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3686 || ! WORDS_BIG_ENDIAN
)
3687 ? SUBREG_WORD (x
) == 0
3689 == ((GET_MODE_SIZE (op0_mode
)
3690 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3692 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3693 && (! WORDS_BIG_ENDIAN
3694 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3695 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3697 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3698 since we are saying that the high bits don't matter. */
3699 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3700 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3702 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3703 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
3704 return operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
), 0, mode
);
3705 return SUBREG_REG (x
);
3708 /* Note that we cannot do any narrowing for non-constants since
3709 we might have been counting on using the fact that some bits were
3710 zero. We now do this in the SET. */
3715 /* (not (plus X -1)) can become (neg X). */
3716 if (GET_CODE (XEXP (x
, 0)) == PLUS
3717 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3718 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3720 /* Similarly, (not (neg X)) is (plus X -1). */
3721 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3722 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3725 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3726 if (GET_CODE (XEXP (x
, 0)) == XOR
3727 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3728 && (temp
= simplify_unary_operation (NOT
, mode
,
3729 XEXP (XEXP (x
, 0), 1),
3731 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3733 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3734 other than 1, but that is not valid. We could do a similar
3735 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3736 but this doesn't seem common enough to bother with. */
3737 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3738 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3739 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3740 XEXP (XEXP (x
, 0), 1));
3742 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3743 && subreg_lowpart_p (XEXP (x
, 0))
3744 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3745 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3746 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3747 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3749 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3751 x
= gen_rtx_ROTATE (inner_mode
,
3752 gen_unary (NOT
, inner_mode
, inner_mode
,
3754 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3755 return gen_lowpart_for_combine (mode
, x
);
3758 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3759 reversing the comparison code if valid. */
3760 if (STORE_FLAG_VALUE
== -1
3761 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3762 && reversible_comparison_p (XEXP (x
, 0)))
3763 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3764 mode
, XEXP (XEXP (x
, 0), 0),
3765 XEXP (XEXP (x
, 0), 1));
3767 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3768 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3769 perform the above simplification. */
3771 if (STORE_FLAG_VALUE
== -1
3772 && XEXP (x
, 1) == const1_rtx
3773 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3774 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3775 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3776 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3778 /* Apply De Morgan's laws to reduce number of patterns for machines
3779 with negating logical insns (and-not, nand, etc.). If result has
3780 only one NOT, put it first, since that is how the patterns are
3783 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3785 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3787 if (GET_CODE (in1
) == NOT
)
3788 in1
= XEXP (in1
, 0);
3790 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
3792 if (GET_CODE (in2
) == NOT
)
3793 in2
= XEXP (in2
, 0);
3794 else if (GET_CODE (in2
) == CONST_INT
3795 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3796 in2
= GEN_INT (GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
3798 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
3800 if (GET_CODE (in2
) == NOT
)
3803 in2
= in1
; in1
= tem
;
3806 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3812 /* (neg (plus X 1)) can become (not X). */
3813 if (GET_CODE (XEXP (x
, 0)) == PLUS
3814 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3815 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3817 /* Similarly, (neg (not X)) is (plus X 1). */
3818 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3819 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3821 /* (neg (minus X Y)) can become (minus Y X). */
3822 if (GET_CODE (XEXP (x
, 0)) == MINUS
3823 && (! FLOAT_MODE_P (mode
)
3824 /* x-y != -(y-x) with IEEE floating point. */
3825 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3827 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3828 XEXP (XEXP (x
, 0), 0));
3830 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3831 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3832 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3833 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3835 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3836 if we can then eliminate the NEG (e.g.,
3837 if the operand is a constant). */
3839 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3841 temp
= simplify_unary_operation (NEG
, mode
,
3842 XEXP (XEXP (x
, 0), 0), mode
);
3845 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3850 temp
= expand_compound_operation (XEXP (x
, 0));
3852 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3853 replaced by (lshiftrt X C). This will convert
3854 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3856 if (GET_CODE (temp
) == ASHIFTRT
3857 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3858 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3859 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3860 INTVAL (XEXP (temp
, 1)));
3862 /* If X has only a single bit that might be nonzero, say, bit I, convert
3863 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3864 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3865 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3866 or a SUBREG of one since we'd be making the expression more
3867 complex if it was just a register. */
3869 if (GET_CODE (temp
) != REG
3870 && ! (GET_CODE (temp
) == SUBREG
3871 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3872 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3874 rtx temp1
= simplify_shift_const
3875 (NULL_RTX
, ASHIFTRT
, mode
,
3876 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3877 GET_MODE_BITSIZE (mode
) - 1 - i
),
3878 GET_MODE_BITSIZE (mode
) - 1 - i
);
3880 /* If all we did was surround TEMP with the two shifts, we
3881 haven't improved anything, so don't use it. Otherwise,
3882 we are better off with TEMP1. */
3883 if (GET_CODE (temp1
) != ASHIFTRT
3884 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3885 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3891 /* We can't handle truncation to a partial integer mode here
3892 because we don't know the real bitsize of the partial
3894 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3897 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3898 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3899 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3901 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3902 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3904 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3905 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3906 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3907 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3908 return XEXP (XEXP (x
, 0), 0);
3910 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3911 (OP:SI foo:SI) if OP is NEG or ABS. */
3912 if ((GET_CODE (XEXP (x
, 0)) == ABS
3913 || GET_CODE (XEXP (x
, 0)) == NEG
)
3914 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3915 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3916 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3917 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3918 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3920 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3922 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3923 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3924 && subreg_lowpart_p (XEXP (x
, 0)))
3925 return SUBREG_REG (XEXP (x
, 0));
3927 /* If we know that the value is already truncated, we can
3928 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3929 is nonzero for the corresponding modes. But don't do this
3930 for an (LSHIFTRT (MULT ...)) since this will cause problems
3931 with the umulXi3_highpart patterns. */
3932 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3933 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3934 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3935 >= GET_MODE_BITSIZE (mode
) + 1
3936 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3937 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3938 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3940 /* A truncate of a comparison can be replaced with a subreg if
3941 STORE_FLAG_VALUE permits. This is like the previous test,
3942 but it works even if the comparison is done in a mode larger
3943 than HOST_BITS_PER_WIDE_INT. */
3944 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3945 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3946 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0)
3947 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3949 /* Similarly, a truncate of a register whose value is a
3950 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3952 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3953 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0
3954 && (temp
= get_last_value (XEXP (x
, 0)))
3955 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
3956 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3960 case FLOAT_TRUNCATE
:
3961 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3962 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
3963 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3964 return XEXP (XEXP (x
, 0), 0);
3966 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3967 (OP:SF foo:SF) if OP is NEG or ABS. */
3968 if ((GET_CODE (XEXP (x
, 0)) == ABS
3969 || GET_CODE (XEXP (x
, 0)) == NEG
)
3970 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
3971 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3972 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
3973 XEXP (XEXP (XEXP (x
, 0), 0), 0));
3975 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3976 is (float_truncate:SF x). */
3977 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3978 && subreg_lowpart_p (XEXP (x
, 0))
3979 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
3980 return SUBREG_REG (XEXP (x
, 0));
3985 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3986 using cc0, in which case we want to leave it as a COMPARE
3987 so we can distinguish it from a register-register-copy. */
3988 if (XEXP (x
, 1) == const0_rtx
)
3991 /* In IEEE floating point, x-0 is not the same as x. */
3992 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3993 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
3995 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4001 /* (const (const X)) can become (const X). Do it this way rather than
4002 returning the inner CONST since CONST can be shared with a
4004 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4005 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4010 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4011 can add in an offset. find_split_point will split this address up
4012 again if it doesn't match. */
4013 if (GET_CODE (XEXP (x
, 0)) == HIGH
4014 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4020 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4021 outermost. That's because that's the way indexed addresses are
4022 supposed to appear. This code used to check many more cases, but
4023 they are now checked elsewhere. */
4024 if (GET_CODE (XEXP (x
, 0)) == PLUS
4025 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4026 return gen_binary (PLUS
, mode
,
4027 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4029 XEXP (XEXP (x
, 0), 1));
4031 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4032 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4033 bit-field and can be replaced by either a sign_extend or a
4034 sign_extract. The `and' may be a zero_extend and the two
4035 <c>, -<c> constants may be reversed. */
4036 if (GET_CODE (XEXP (x
, 0)) == XOR
4037 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4038 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4039 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
4040 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4041 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4042 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4043 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4044 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4045 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4046 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4047 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4048 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4050 return simplify_shift_const
4051 (NULL_RTX
, ASHIFTRT
, mode
,
4052 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4053 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4054 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4055 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4057 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4058 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4059 is 1. This produces better code than the alternative immediately
4061 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4062 && reversible_comparison_p (XEXP (x
, 0))
4063 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4064 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
4066 gen_unary (NEG
, mode
, mode
,
4067 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
4068 mode
, XEXP (XEXP (x
, 0), 0),
4069 XEXP (XEXP (x
, 0), 1)));
4071 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4072 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4073 the bitsize of the mode - 1. This allows simplification of
4074 "a = (b & 8) == 0;" */
4075 if (XEXP (x
, 1) == constm1_rtx
4076 && GET_CODE (XEXP (x
, 0)) != REG
4077 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4078 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4079 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4080 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4081 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4082 gen_rtx_combine (XOR
, mode
,
4083 XEXP (x
, 0), const1_rtx
),
4084 GET_MODE_BITSIZE (mode
) - 1),
4085 GET_MODE_BITSIZE (mode
) - 1);
4087 /* If we are adding two things that have no bits in common, convert
4088 the addition into an IOR. This will often be further simplified,
4089 for example in cases like ((a & 1) + (a & 2)), which can
4092 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4093 && (nonzero_bits (XEXP (x
, 0), mode
)
4094 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4095 return gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4099 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4100 by reversing the comparison code if valid. */
4101 if (STORE_FLAG_VALUE
== 1
4102 && XEXP (x
, 0) == const1_rtx
4103 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4104 && reversible_comparison_p (XEXP (x
, 1)))
4105 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))),
4106 mode
, XEXP (XEXP (x
, 1), 0),
4107 XEXP (XEXP (x
, 1), 1));
4109 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4110 (and <foo> (const_int pow2-1)) */
4111 if (GET_CODE (XEXP (x
, 1)) == AND
4112 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4113 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4114 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4115 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4116 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4118 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4120 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4121 return gen_binary (MINUS
, mode
,
4122 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4123 XEXP (XEXP (x
, 1), 0)),
4124 XEXP (XEXP (x
, 1), 1));
4128 /* If we have (mult (plus A B) C), apply the distributive law and then
4129 the inverse distributive law to see if things simplify. This
4130 occurs mostly in addresses, often when unrolling loops. */
4132 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4134 x
= apply_distributive_law
4135 (gen_binary (PLUS
, mode
,
4136 gen_binary (MULT
, mode
,
4137 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4138 gen_binary (MULT
, mode
,
4139 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
4141 if (GET_CODE (x
) != MULT
)
4147 /* If this is a divide by a power of two, treat it as a shift if
4148 its first operand is a shift. */
4149 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4150 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4151 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4152 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4153 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4154 || GET_CODE (XEXP (x
, 0)) == ROTATE
4155 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4156 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4160 case GT
: case GTU
: case GE
: case GEU
:
4161 case LT
: case LTU
: case LE
: case LEU
:
4162 /* If the first operand is a condition code, we can't do anything
4164 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4165 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4167 && XEXP (x
, 0) != cc0_rtx
4171 rtx op0
= XEXP (x
, 0);
4172 rtx op1
= XEXP (x
, 1);
4173 enum rtx_code new_code
;
4175 if (GET_CODE (op0
) == COMPARE
)
4176 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4178 /* Simplify our comparison, if possible. */
4179 new_code
= simplify_comparison (code
, &op0
, &op1
);
4181 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4182 if only the low-order bit is possibly nonzero in X (such as when
4183 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4184 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4185 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4188 Remove any ZERO_EXTRACT we made when thinking this was a
4189 comparison. It may now be simpler to use, e.g., an AND. If a
4190 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4191 the call to make_compound_operation in the SET case. */
4193 if (STORE_FLAG_VALUE
== 1
4194 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4195 && op1
== const0_rtx
&& nonzero_bits (op0
, mode
) == 1)
4196 return gen_lowpart_for_combine (mode
,
4197 expand_compound_operation (op0
));
4199 else if (STORE_FLAG_VALUE
== 1
4200 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4201 && op1
== const0_rtx
4202 && (num_sign_bit_copies (op0
, mode
)
4203 == GET_MODE_BITSIZE (mode
)))
4205 op0
= expand_compound_operation (op0
);
4206 return gen_unary (NEG
, mode
, mode
,
4207 gen_lowpart_for_combine (mode
, op0
));
4210 else if (STORE_FLAG_VALUE
== 1
4211 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4212 && op1
== const0_rtx
4213 && nonzero_bits (op0
, mode
) == 1)
4215 op0
= expand_compound_operation (op0
);
4216 return gen_binary (XOR
, mode
,
4217 gen_lowpart_for_combine (mode
, op0
),
4221 else if (STORE_FLAG_VALUE
== 1
4222 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4223 && op1
== const0_rtx
4224 && (num_sign_bit_copies (op0
, mode
)
4225 == GET_MODE_BITSIZE (mode
)))
4227 op0
= expand_compound_operation (op0
);
4228 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4231 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4233 if (STORE_FLAG_VALUE
== -1
4234 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4235 && op1
== const0_rtx
4236 && (num_sign_bit_copies (op0
, mode
)
4237 == GET_MODE_BITSIZE (mode
)))
4238 return gen_lowpart_for_combine (mode
,
4239 expand_compound_operation (op0
));
4241 else if (STORE_FLAG_VALUE
== -1
4242 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4243 && op1
== const0_rtx
4244 && nonzero_bits (op0
, mode
) == 1)
4246 op0
= expand_compound_operation (op0
);
4247 return gen_unary (NEG
, mode
, mode
,
4248 gen_lowpart_for_combine (mode
, op0
));
4251 else if (STORE_FLAG_VALUE
== -1
4252 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4253 && op1
== const0_rtx
4254 && (num_sign_bit_copies (op0
, mode
)
4255 == GET_MODE_BITSIZE (mode
)))
4257 op0
= expand_compound_operation (op0
);
4258 return gen_unary (NOT
, mode
, mode
,
4259 gen_lowpart_for_combine (mode
, op0
));
4262 /* If X is 0/1, (eq X 0) is X-1. */
4263 else if (STORE_FLAG_VALUE
== -1
4264 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4265 && op1
== const0_rtx
4266 && nonzero_bits (op0
, mode
) == 1)
4268 op0
= expand_compound_operation (op0
);
4269 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4272 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4273 one bit that might be nonzero, we can convert (ne x 0) to
4274 (ashift x c) where C puts the bit in the sign bit. Remove any
4275 AND with STORE_FLAG_VALUE when we are done, since we are only
4276 going to test the sign bit. */
4277 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4278 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4279 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4280 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4281 && op1
== const0_rtx
4282 && mode
== GET_MODE (op0
)
4283 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4285 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4286 expand_compound_operation (op0
),
4287 GET_MODE_BITSIZE (mode
) - 1 - i
);
4288 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4294 /* If the code changed, return a whole new comparison. */
4295 if (new_code
!= code
)
4296 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4298 /* Otherwise, keep this operation, but maybe change its operands.
4299 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4300 SUBST (XEXP (x
, 0), op0
);
4301 SUBST (XEXP (x
, 1), op1
);
4306 return simplify_if_then_else (x
);
4312 /* If we are processing SET_DEST, we are done. */
4316 return expand_compound_operation (x
);
4319 return simplify_set (x
);
4324 return simplify_logical (x
, last
);
4327 /* (abs (neg <foo>)) -> (abs <foo>) */
4328 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4329 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4331 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4333 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4336 /* If operand is something known to be positive, ignore the ABS. */
4337 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4338 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4339 <= HOST_BITS_PER_WIDE_INT
)
4340 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4341 & ((HOST_WIDE_INT
) 1
4342 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4347 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4348 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4349 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4354 /* (ffs (*_extend <X>)) = (ffs <X>) */
4355 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4356 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4357 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4361 /* (float (sign_extend <X>)) = (float <X>). */
4362 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4363 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4371 /* If this is a shift by a constant amount, simplify it. */
4372 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4373 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4374 INTVAL (XEXP (x
, 1)));
4376 #ifdef SHIFT_COUNT_TRUNCATED
4377 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4379 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4381 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4395 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4398 simplify_if_then_else (x
)
4401 enum machine_mode mode
= GET_MODE (x
);
4402 rtx cond
= XEXP (x
, 0);
4403 rtx
true = XEXP (x
, 1);
4404 rtx
false = XEXP (x
, 2);
4405 enum rtx_code true_code
= GET_CODE (cond
);
4406 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4410 /* Simplify storing of the truth value. */
4411 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
4412 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4414 /* Also when the truth value has to be reversed. */
4415 if (comparison_p
&& reversible_comparison_p (cond
)
4416 && true == const0_rtx
&& false == const_true_rtx
)
4417 return gen_binary (reverse_condition (true_code
),
4418 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4420 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4421 in it is being compared against certain values. Get the true and false
4422 comparisons and see if that says anything about the value of each arm. */
4424 if (comparison_p
&& reversible_comparison_p (cond
)
4425 && GET_CODE (XEXP (cond
, 0)) == REG
)
4428 rtx from
= XEXP (cond
, 0);
4429 enum rtx_code false_code
= reverse_condition (true_code
);
4430 rtx true_val
= XEXP (cond
, 1);
4431 rtx false_val
= true_val
;
4434 /* If FALSE_CODE is EQ, swap the codes and arms. */
4436 if (false_code
== EQ
)
4438 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4439 temp
= true, true = false, false = temp
;
4442 /* If we are comparing against zero and the expression being tested has
4443 only a single bit that might be nonzero, that is its value when it is
4444 not equal to zero. Similarly if it is known to be -1 or 0. */
4446 if (true_code
== EQ
&& true_val
== const0_rtx
4447 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4448 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4449 else if (true_code
== EQ
&& true_val
== const0_rtx
4450 && (num_sign_bit_copies (from
, GET_MODE (from
))
4451 == GET_MODE_BITSIZE (GET_MODE (from
))))
4452 false_code
= EQ
, false_val
= constm1_rtx
;
4454 /* Now simplify an arm if we know the value of the register in the
4455 branch and it is used in the arm. Be careful due to the potential
4456 of locally-shared RTL. */
4458 if (reg_mentioned_p (from
, true))
4459 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4460 pc_rtx
, pc_rtx
, 0, 0);
4461 if (reg_mentioned_p (from
, false))
4462 false = subst (known_cond (copy_rtx (false), false_code
,
4464 pc_rtx
, pc_rtx
, 0, 0);
4466 SUBST (XEXP (x
, 1), swapped
? false : true);
4467 SUBST (XEXP (x
, 2), swapped
? true : false);
4469 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4472 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4473 reversed, do so to avoid needing two sets of patterns for
4474 subtract-and-branch insns. Similarly if we have a constant in the true
4475 arm, the false arm is the same as the first operand of the comparison, or
4476 the false arm is more complicated than the true arm. */
4478 if (comparison_p
&& reversible_comparison_p (cond
)
4480 || (CONSTANT_P (true)
4481 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4482 || true == const0_rtx
4483 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4484 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4485 || (GET_CODE (true) == SUBREG
4486 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4487 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4488 || reg_mentioned_p (true, false)
4489 || rtx_equal_p (false, XEXP (cond
, 0))))
4491 true_code
= reverse_condition (true_code
);
4493 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
4496 SUBST (XEXP (x
, 1), false);
4497 SUBST (XEXP (x
, 2), true);
4499 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4501 /* It is possible that the conditional has been simplified out. */
4502 true_code
= GET_CODE (cond
);
4503 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4506 /* If the two arms are identical, we don't need the comparison. */
4508 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4511 /* Convert a == b ? b : a to "a". */
4512 if (true_code
== EQ
&& ! side_effects_p (cond
)
4513 && rtx_equal_p (XEXP (cond
, 0), false)
4514 && rtx_equal_p (XEXP (cond
, 1), true))
4516 else if (true_code
== NE
&& ! side_effects_p (cond
)
4517 && rtx_equal_p (XEXP (cond
, 0), true)
4518 && rtx_equal_p (XEXP (cond
, 1), false))
4521 /* Look for cases where we have (abs x) or (neg (abs X)). */
4523 if (GET_MODE_CLASS (mode
) == MODE_INT
4524 && GET_CODE (false) == NEG
4525 && rtx_equal_p (true, XEXP (false, 0))
4527 && rtx_equal_p (true, XEXP (cond
, 0))
4528 && ! side_effects_p (true))
4533 return gen_unary (ABS
, mode
, mode
, true);
4536 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4541 /* Look for MIN or MAX. */
4543 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4545 && rtx_equal_p (XEXP (cond
, 0), true)
4546 && rtx_equal_p (XEXP (cond
, 1), false)
4547 && ! side_effects_p (cond
))
4552 return gen_binary (SMAX
, mode
, true, false);
4555 return gen_binary (SMIN
, mode
, true, false);
4558 return gen_binary (UMAX
, mode
, true, false);
4561 return gen_binary (UMIN
, mode
, true, false);
4566 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4567 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4568 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4569 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4570 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4571 neither 1 or -1, but it isn't worth checking for. */
4573 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4574 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4576 rtx t
= make_compound_operation (true, SET
);
4577 rtx f
= make_compound_operation (false, SET
);
4578 rtx cond_op0
= XEXP (cond
, 0);
4579 rtx cond_op1
= XEXP (cond
, 1);
4580 enum rtx_code op
= NIL
, extend_op
= NIL
;
4581 enum machine_mode m
= mode
;
4582 rtx z
= 0, c1
= NULL_RTX
;
4584 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4585 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4586 || GET_CODE (t
) == ASHIFT
4587 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4588 && rtx_equal_p (XEXP (t
, 0), f
))
4589 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4591 /* If an identity-zero op is commutative, check whether there
4592 would be a match if we swapped the operands. */
4593 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4594 || GET_CODE (t
) == XOR
)
4595 && rtx_equal_p (XEXP (t
, 1), f
))
4596 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4597 else if (GET_CODE (t
) == SIGN_EXTEND
4598 && (GET_CODE (XEXP (t
, 0)) == PLUS
4599 || GET_CODE (XEXP (t
, 0)) == MINUS
4600 || GET_CODE (XEXP (t
, 0)) == IOR
4601 || GET_CODE (XEXP (t
, 0)) == XOR
4602 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4603 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4604 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4605 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4606 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4607 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4608 && (num_sign_bit_copies (f
, GET_MODE (f
))
4609 > (GET_MODE_BITSIZE (mode
)
4610 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4612 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4613 extend_op
= SIGN_EXTEND
;
4614 m
= GET_MODE (XEXP (t
, 0));
4616 else if (GET_CODE (t
) == SIGN_EXTEND
4617 && (GET_CODE (XEXP (t
, 0)) == PLUS
4618 || GET_CODE (XEXP (t
, 0)) == IOR
4619 || GET_CODE (XEXP (t
, 0)) == XOR
)
4620 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4621 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4622 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4623 && (num_sign_bit_copies (f
, GET_MODE (f
))
4624 > (GET_MODE_BITSIZE (mode
)
4625 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4627 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4628 extend_op
= SIGN_EXTEND
;
4629 m
= GET_MODE (XEXP (t
, 0));
4631 else if (GET_CODE (t
) == ZERO_EXTEND
4632 && (GET_CODE (XEXP (t
, 0)) == PLUS
4633 || GET_CODE (XEXP (t
, 0)) == MINUS
4634 || GET_CODE (XEXP (t
, 0)) == IOR
4635 || GET_CODE (XEXP (t
, 0)) == XOR
4636 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4637 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4638 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4639 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4640 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4641 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4642 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4643 && ((nonzero_bits (f
, GET_MODE (f
))
4644 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4647 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4648 extend_op
= ZERO_EXTEND
;
4649 m
= GET_MODE (XEXP (t
, 0));
4651 else if (GET_CODE (t
) == ZERO_EXTEND
4652 && (GET_CODE (XEXP (t
, 0)) == PLUS
4653 || GET_CODE (XEXP (t
, 0)) == IOR
4654 || GET_CODE (XEXP (t
, 0)) == XOR
)
4655 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4656 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4657 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4658 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4659 && ((nonzero_bits (f
, GET_MODE (f
))
4660 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4663 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4664 extend_op
= ZERO_EXTEND
;
4665 m
= GET_MODE (XEXP (t
, 0));
4670 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4671 pc_rtx
, pc_rtx
, 0, 0);
4672 temp
= gen_binary (MULT
, m
, temp
,
4673 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4674 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4675 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4677 if (extend_op
!= NIL
)
4678 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4684 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4685 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4686 negation of a single bit, we can convert this operation to a shift. We
4687 can actually do this more generally, but it doesn't seem worth it. */
4689 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4690 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4691 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4692 && (i
= exact_log2 (INTVAL (true))) >= 0)
4693 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4694 == GET_MODE_BITSIZE (mode
))
4695 && (i
= exact_log2 (- INTVAL (true))) >= 0)))
4697 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4698 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4703 /* Simplify X, a SET expression. Return the new expression. */
4709 rtx src
= SET_SRC (x
);
4710 rtx dest
= SET_DEST (x
);
4711 enum machine_mode mode
4712 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4716 /* (set (pc) (return)) gets written as (return). */
4717 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4720 /* Now that we know for sure which bits of SRC we are using, see if we can
4721 simplify the expression for the object knowing that we only need the
4724 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4726 src
= force_to_mode (src
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
4727 SUBST (SET_SRC (x
), src
);
4730 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4731 the comparison result and try to simplify it unless we already have used
4732 undobuf.other_insn. */
4733 if ((GET_CODE (src
) == COMPARE
4738 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4739 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4740 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4741 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4743 enum rtx_code old_code
= GET_CODE (*cc_use
);
4744 enum rtx_code new_code
;
4746 int other_changed
= 0;
4747 enum machine_mode compare_mode
= GET_MODE (dest
);
4749 if (GET_CODE (src
) == COMPARE
)
4750 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4752 op0
= src
, op1
= const0_rtx
;
4754 /* Simplify our comparison, if possible. */
4755 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4757 #ifdef EXTRA_CC_MODES
4758 /* If this machine has CC modes other than CCmode, check to see if we
4759 need to use a different CC mode here. */
4760 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4761 #endif /* EXTRA_CC_MODES */
4763 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4764 /* If the mode changed, we have to change SET_DEST, the mode in the
4765 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4766 a hard register, just build new versions with the proper mode. If it
4767 is a pseudo, we lose unless it is only time we set the pseudo, in
4768 which case we can safely change its mode. */
4769 if (compare_mode
!= GET_MODE (dest
))
4771 int regno
= REGNO (dest
);
4772 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4774 if (regno
< FIRST_PSEUDO_REGISTER
4775 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4777 if (regno
>= FIRST_PSEUDO_REGISTER
)
4778 SUBST (regno_reg_rtx
[regno
], new_dest
);
4780 SUBST (SET_DEST (x
), new_dest
);
4781 SUBST (XEXP (*cc_use
, 0), new_dest
);
4789 /* If the code changed, we have to build a new comparison in
4790 undobuf.other_insn. */
4791 if (new_code
!= old_code
)
4793 unsigned HOST_WIDE_INT mask
;
4795 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
4798 /* If the only change we made was to change an EQ into an NE or
4799 vice versa, OP0 has only one bit that might be nonzero, and OP1
4800 is zero, check if changing the user of the condition code will
4801 produce a valid insn. If it won't, we can keep the original code
4802 in that insn by surrounding our operation with an XOR. */
4804 if (((old_code
== NE
&& new_code
== EQ
)
4805 || (old_code
== EQ
&& new_code
== NE
))
4806 && ! other_changed
&& op1
== const0_rtx
4807 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4808 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4810 rtx pat
= PATTERN (other_insn
), note
= 0;
4812 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4813 && ! check_asm_operands (pat
)))
4815 PUT_CODE (*cc_use
, old_code
);
4818 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4826 undobuf
.other_insn
= other_insn
;
4829 /* If we are now comparing against zero, change our source if
4830 needed. If we do not use cc0, we always have a COMPARE. */
4831 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4833 SUBST (SET_SRC (x
), op0
);
4839 /* Otherwise, if we didn't previously have a COMPARE in the
4840 correct mode, we need one. */
4841 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4844 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
4849 /* Otherwise, update the COMPARE if needed. */
4850 SUBST (XEXP (src
, 0), op0
);
4851 SUBST (XEXP (src
, 1), op1
);
4856 /* Get SET_SRC in a form where we have placed back any
4857 compound expressions. Then do the checks below. */
4858 src
= make_compound_operation (src
, SET
);
4859 SUBST (SET_SRC (x
), src
);
4862 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4863 and X being a REG or (subreg (reg)), we may be able to convert this to
4864 (set (subreg:m2 x) (op)).
4866 We can always do this if M1 is narrower than M2 because that means that
4867 we only care about the low bits of the result.
4869 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4870 perform a narrower operation than requested since the high-order bits will
4871 be undefined. On machine where it is defined, this transformation is safe
4872 as long as M1 and M2 have the same number of words. */
4874 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4875 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
4876 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
4878 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
4879 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
4880 #ifndef WORD_REGISTER_OPERATIONS
4881 && (GET_MODE_SIZE (GET_MODE (src
))
4882 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4884 #ifdef CLASS_CANNOT_CHANGE_SIZE
4885 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
4886 && (TEST_HARD_REG_BIT
4887 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
],
4889 && (GET_MODE_SIZE (GET_MODE (src
))
4890 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
4892 && (GET_CODE (dest
) == REG
4893 || (GET_CODE (dest
) == SUBREG
4894 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
4896 SUBST (SET_DEST (x
),
4897 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
4899 SUBST (SET_SRC (x
), SUBREG_REG (src
));
4901 src
= SET_SRC (x
), dest
= SET_DEST (x
);
4904 #ifdef LOAD_EXTEND_OP
4905 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4906 would require a paradoxical subreg. Replace the subreg with a
4907 zero_extend to avoid the reload that would otherwise be required. */
4909 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4910 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
4911 && SUBREG_WORD (src
) == 0
4912 && (GET_MODE_SIZE (GET_MODE (src
))
4913 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4914 && GET_CODE (SUBREG_REG (src
)) == MEM
)
4917 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
4918 GET_MODE (src
), XEXP (src
, 0)));
4924 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4925 are comparing an item known to be 0 or -1 against 0, use a logical
4926 operation instead. Check for one of the arms being an IOR of the other
4927 arm with some value. We compute three terms to be IOR'ed together. In
4928 practice, at most two will be nonzero. Then we do the IOR's. */
4930 if (GET_CODE (dest
) != PC
4931 && GET_CODE (src
) == IF_THEN_ELSE
4932 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
4933 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
4934 && XEXP (XEXP (src
, 0), 1) == const0_rtx
4935 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
4936 #ifdef HAVE_conditional_move
4937 && ! can_conditionally_move_p (GET_MODE (src
))
4939 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
4940 GET_MODE (XEXP (XEXP (src
, 0), 0)))
4941 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
4942 && ! side_effects_p (src
))
4944 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
4945 ? XEXP (src
, 1) : XEXP (src
, 2));
4946 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
4947 ? XEXP (src
, 2) : XEXP (src
, 1));
4948 rtx term1
= const0_rtx
, term2
, term3
;
4950 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
4951 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
4952 else if (GET_CODE (true) == IOR
4953 && rtx_equal_p (XEXP (true, 1), false))
4954 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
4955 else if (GET_CODE (false) == IOR
4956 && rtx_equal_p (XEXP (false, 0), true))
4957 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
4958 else if (GET_CODE (false) == IOR
4959 && rtx_equal_p (XEXP (false, 1), true))
4960 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
4962 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
4963 term3
= gen_binary (AND
, GET_MODE (src
),
4964 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
4965 XEXP (XEXP (src
, 0), 0)),
4969 gen_binary (IOR
, GET_MODE (src
),
4970 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
4976 #ifdef HAVE_conditional_arithmetic
4977 /* If we have conditional arithmetic and the operand of a SET is
4978 a conditional expression, replace this with an IF_THEN_ELSE.
4979 We can either have a conditional expression or a MULT of that expression
4981 if ((GET_RTX_CLASS (GET_CODE (src
)) == '1'
4982 || GET_RTX_CLASS (GET_CODE (src
)) == '2'
4983 || GET_RTX_CLASS (GET_CODE (src
)) == 'c')
4984 && (GET_RTX_CLASS (GET_CODE (XEXP (src
, 0))) == '<'
4985 || (GET_CODE (XEXP (src
, 0)) == MULT
4986 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src
, 0), 0))) == '<'
4987 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
)))
4989 rtx cond
= XEXP (src
, 0);
4990 rtx true_val
= const1_rtx
;
4991 rtx false_arm
, true_arm
;
4993 if (GET_CODE (cond
) == MULT
)
4995 true_val
= XEXP (cond
, 1);
4996 cond
= XEXP (cond
, 0);
4999 if (GET_RTX_CLASS (GET_CODE (src
)) == '1')
5001 true_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5002 GET_MODE (XEXP (src
, 0)), true_val
);
5003 false_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5004 GET_MODE (XEXP (src
, 0)), const0_rtx
);
5008 true_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5009 true_val
, XEXP (src
, 1));
5010 false_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5011 const0_rtx
, XEXP (src
, 1));
5014 /* Canonicalize if true_arm is the simpler one. */
5015 if (GET_RTX_CLASS (GET_CODE (true_arm
)) == 'o'
5016 && GET_RTX_CLASS (GET_CODE (false_arm
)) != 'o'
5017 && reversible_comparison_p (cond
))
5019 rtx temp
= true_arm
;
5021 true_arm
= false_arm
;
5024 cond
= gen_rtx_combine (reverse_condition (GET_CODE (cond
)),
5025 GET_MODE (cond
), XEXP (cond
, 0),
5029 src
= gen_rtx_combine (IF_THEN_ELSE
, GET_MODE (src
),
5030 gen_rtx_combine (GET_CODE (cond
), VOIDmode
,
5033 true_arm
, false_arm
);
5034 SUBST (SET_SRC (x
), src
);
5038 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5039 whole thing fail. */
5040 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5042 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5045 /* Convert this into a field assignment operation, if possible. */
5046 return make_field_assignment (x
);
5049 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5050 result. LAST is nonzero if this is the last retry. */
5053 simplify_logical (x
, last
)
5057 enum machine_mode mode
= GET_MODE (x
);
5058 rtx op0
= XEXP (x
, 0);
5059 rtx op1
= XEXP (x
, 1);
5061 switch (GET_CODE (x
))
5064 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5065 insn (and may simplify more). */
5066 if (GET_CODE (op0
) == XOR
5067 && rtx_equal_p (XEXP (op0
, 0), op1
)
5068 && ! side_effects_p (op1
))
5069 x
= gen_binary (AND
, mode
,
5070 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5072 if (GET_CODE (op0
) == XOR
5073 && rtx_equal_p (XEXP (op0
, 1), op1
)
5074 && ! side_effects_p (op1
))
5075 x
= gen_binary (AND
, mode
,
5076 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5078 /* Similarly for (~ (A ^ B)) & A. */
5079 if (GET_CODE (op0
) == NOT
5080 && GET_CODE (XEXP (op0
, 0)) == XOR
5081 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5082 && ! side_effects_p (op1
))
5083 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5085 if (GET_CODE (op0
) == NOT
5086 && GET_CODE (XEXP (op0
, 0)) == XOR
5087 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5088 && ! side_effects_p (op1
))
5089 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5091 /* We can call simplify_and_const_int only if we don't lose
5092 any (sign) bits when converting INTVAL (op1) to
5093 "unsigned HOST_WIDE_INT". */
5094 if (GET_CODE (op1
) == CONST_INT
5095 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5096 || INTVAL (op1
) > 0))
5098 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5100 /* If we have (ior (and (X C1) C2)) and the next restart would be
5101 the last, simplify this by making C1 as small as possible
5104 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5105 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5106 && GET_CODE (op1
) == CONST_INT
)
5107 return gen_binary (IOR
, mode
,
5108 gen_binary (AND
, mode
, XEXP (op0
, 0),
5109 GEN_INT (INTVAL (XEXP (op0
, 1))
5110 & ~ INTVAL (op1
))), op1
);
5112 if (GET_CODE (x
) != AND
)
5115 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5116 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5117 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5120 /* Convert (A | B) & A to A. */
5121 if (GET_CODE (op0
) == IOR
5122 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5123 || rtx_equal_p (XEXP (op0
, 1), op1
))
5124 && ! side_effects_p (XEXP (op0
, 0))
5125 && ! side_effects_p (XEXP (op0
, 1)))
5128 /* In the following group of tests (and those in case IOR below),
5129 we start with some combination of logical operations and apply
5130 the distributive law followed by the inverse distributive law.
5131 Most of the time, this results in no change. However, if some of
5132 the operands are the same or inverses of each other, simplifications
5135 For example, (and (ior A B) (not B)) can occur as the result of
5136 expanding a bit field assignment. When we apply the distributive
5137 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5138 which then simplifies to (and (A (not B))).
5140 If we have (and (ior A B) C), apply the distributive law and then
5141 the inverse distributive law to see if things simplify. */
5143 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5145 x
= apply_distributive_law
5146 (gen_binary (GET_CODE (op0
), mode
,
5147 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5148 gen_binary (AND
, mode
, XEXP (op0
, 1), op1
)));
5149 if (GET_CODE (x
) != AND
)
5153 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5154 return apply_distributive_law
5155 (gen_binary (GET_CODE (op1
), mode
,
5156 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5157 gen_binary (AND
, mode
, XEXP (op1
, 1), op0
)));
5159 /* Similarly, taking advantage of the fact that
5160 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5162 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5163 return apply_distributive_law
5164 (gen_binary (XOR
, mode
,
5165 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5166 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 1))));
5168 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5169 return apply_distributive_law
5170 (gen_binary (XOR
, mode
,
5171 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5172 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 1))));
5176 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5177 if (GET_CODE (op1
) == CONST_INT
5178 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5179 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
5182 /* Convert (A & B) | A to A. */
5183 if (GET_CODE (op0
) == AND
5184 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5185 || rtx_equal_p (XEXP (op0
, 1), op1
))
5186 && ! side_effects_p (XEXP (op0
, 0))
5187 && ! side_effects_p (XEXP (op0
, 1)))
5190 /* If we have (ior (and A B) C), apply the distributive law and then
5191 the inverse distributive law to see if things simplify. */
5193 if (GET_CODE (op0
) == AND
)
5195 x
= apply_distributive_law
5196 (gen_binary (AND
, mode
,
5197 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5198 gen_binary (IOR
, mode
, XEXP (op0
, 1), op1
)));
5200 if (GET_CODE (x
) != IOR
)
5204 if (GET_CODE (op1
) == AND
)
5206 x
= apply_distributive_law
5207 (gen_binary (AND
, mode
,
5208 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5209 gen_binary (IOR
, mode
, XEXP (op1
, 1), op0
)));
5211 if (GET_CODE (x
) != IOR
)
5215 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5216 mode size to (rotate A CX). */
5218 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5219 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5220 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5221 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5222 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5223 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5224 == GET_MODE_BITSIZE (mode
)))
5225 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5226 (GET_CODE (op0
) == ASHIFT
5227 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5229 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5230 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5231 does not affect any of the bits in OP1, it can really be done
5232 as a PLUS and we can associate. We do this by seeing if OP1
5233 can be safely shifted left C bits. */
5234 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5235 && GET_CODE (XEXP (op0
, 0)) == PLUS
5236 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5237 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5238 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5240 int count
= INTVAL (XEXP (op0
, 1));
5241 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5243 if (mask
>> count
== INTVAL (op1
)
5244 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5246 SUBST (XEXP (XEXP (op0
, 0), 1),
5247 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5254 /* If we are XORing two things that have no bits in common,
5255 convert them into an IOR. This helps to detect rotation encoded
5256 using those methods and possibly other simplifications. */
5258 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5259 && (nonzero_bits (op0
, mode
)
5260 & nonzero_bits (op1
, mode
)) == 0)
5261 return (gen_binary (IOR
, mode
, op0
, op1
));
5263 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5264 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5267 int num_negated
= 0;
5269 if (GET_CODE (op0
) == NOT
)
5270 num_negated
++, op0
= XEXP (op0
, 0);
5271 if (GET_CODE (op1
) == NOT
)
5272 num_negated
++, op1
= XEXP (op1
, 0);
5274 if (num_negated
== 2)
5276 SUBST (XEXP (x
, 0), op0
);
5277 SUBST (XEXP (x
, 1), op1
);
5279 else if (num_negated
== 1)
5280 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5283 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5284 correspond to a machine insn or result in further simplifications
5285 if B is a constant. */
5287 if (GET_CODE (op0
) == AND
5288 && rtx_equal_p (XEXP (op0
, 1), op1
)
5289 && ! side_effects_p (op1
))
5290 return gen_binary (AND
, mode
,
5291 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5294 else if (GET_CODE (op0
) == AND
5295 && rtx_equal_p (XEXP (op0
, 0), op1
)
5296 && ! side_effects_p (op1
))
5297 return gen_binary (AND
, mode
,
5298 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5301 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5302 comparison if STORE_FLAG_VALUE is 1. */
5303 if (STORE_FLAG_VALUE
== 1
5304 && op1
== const1_rtx
5305 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5306 && reversible_comparison_p (op0
))
5307 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5308 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5310 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5311 is (lt foo (const_int 0)), so we can perform the above
5312 simplification if STORE_FLAG_VALUE is 1. */
5314 if (STORE_FLAG_VALUE
== 1
5315 && op1
== const1_rtx
5316 && GET_CODE (op0
) == LSHIFTRT
5317 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5318 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5319 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5321 /* (xor (comparison foo bar) (const_int sign-bit))
5322 when STORE_FLAG_VALUE is the sign bit. */
5323 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5324 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5325 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5326 && op1
== const_true_rtx
5327 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5328 && reversible_comparison_p (op0
))
5329 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5330 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5341 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5342 operations" because they can be replaced with two more basic operations.
5343 ZERO_EXTEND is also considered "compound" because it can be replaced with
5344 an AND operation, which is simpler, though only one operation.
5346 The function expand_compound_operation is called with an rtx expression
5347 and will convert it to the appropriate shifts and AND operations,
5348 simplifying at each stage.
5350 The function make_compound_operation is called to convert an expression
5351 consisting of shifts and ANDs into the equivalent compound expression.
5352 It is the inverse of this function, loosely speaking. */
5355 expand_compound_operation (x
)
5363 switch (GET_CODE (x
))
5368 /* We can't necessarily use a const_int for a multiword mode;
5369 it depends on implicitly extending the value.
5370 Since we don't know the right way to extend it,
5371 we can't tell whether the implicit way is right.
5373 Even for a mode that is no wider than a const_int,
5374 we can't win, because we need to sign extend one of its bits through
5375 the rest of it, and we don't know which bit. */
5376 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5379 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5380 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5381 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5382 reloaded. If not for that, MEM's would very rarely be safe.
5384 Reject MODEs bigger than a word, because we might not be able
5385 to reference a two-register group starting with an arbitrary register
5386 (and currently gen_lowpart might crash for a SUBREG). */
5388 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5391 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5392 /* If the inner object has VOIDmode (the only way this can happen
5393 is if it is a ASM_OPERANDS), we can't do anything since we don't
5394 know how much masking to do. */
5403 /* If the operand is a CLOBBER, just return it. */
5404 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5407 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5408 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5409 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5412 len
= INTVAL (XEXP (x
, 1));
5413 pos
= INTVAL (XEXP (x
, 2));
5415 /* If this goes outside the object being extracted, replace the object
5416 with a (use (mem ...)) construct that only combine understands
5417 and is used only for this purpose. */
5418 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5419 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5421 if (BITS_BIG_ENDIAN
)
5422 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5430 /* We can optimize some special cases of ZERO_EXTEND. */
5431 if (GET_CODE (x
) == ZERO_EXTEND
)
5433 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5434 know that the last value didn't have any inappropriate bits
5436 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5437 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5438 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5439 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5440 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5441 return XEXP (XEXP (x
, 0), 0);
5443 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5444 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5445 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5446 && subreg_lowpart_p (XEXP (x
, 0))
5447 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5448 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5449 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5450 return SUBREG_REG (XEXP (x
, 0));
5452 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5453 is a comparison and STORE_FLAG_VALUE permits. This is like
5454 the first case, but it works even when GET_MODE (x) is larger
5455 than HOST_WIDE_INT. */
5456 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5457 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5458 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5459 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5460 <= HOST_BITS_PER_WIDE_INT
)
5461 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5462 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5463 return XEXP (XEXP (x
, 0), 0);
5465 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5466 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5467 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5468 && subreg_lowpart_p (XEXP (x
, 0))
5469 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5470 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5471 <= HOST_BITS_PER_WIDE_INT
)
5472 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5473 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5474 return SUBREG_REG (XEXP (x
, 0));
5476 /* If sign extension is cheaper than zero extension, then use it
5477 if we know that no extraneous bits are set, and that the high
5479 if (flag_expensive_optimizations
5480 && ((GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5481 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (x
))
5482 & ~ (((unsigned HOST_WIDE_INT
)
5483 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5486 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5487 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5488 <= HOST_BITS_PER_WIDE_INT
)
5489 && (((HOST_WIDE_INT
) STORE_FLAG_VALUE
5490 & ~ (((unsigned HOST_WIDE_INT
)
5491 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5495 rtx temp
= gen_rtx_SIGN_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5497 if (rtx_cost (temp
, SET
) < rtx_cost (x
, SET
))
5498 return expand_compound_operation (temp
);
5502 /* If we reach here, we want to return a pair of shifts. The inner
5503 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5504 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5505 logical depending on the value of UNSIGNEDP.
5507 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5508 converted into an AND of a shift.
5510 We must check for the case where the left shift would have a negative
5511 count. This can happen in a case like (x >> 31) & 255 on machines
5512 that can't shift by a constant. On those machines, we would first
5513 combine the shift with the AND to produce a variable-position
5514 extraction. Then the constant of 31 would be substituted in to produce
5515 a such a position. */
5517 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5518 if (modewidth
>= pos
- len
)
5519 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5521 simplify_shift_const (NULL_RTX
, ASHIFT
,
5524 modewidth
- pos
- len
),
5527 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5528 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5529 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5532 ((HOST_WIDE_INT
) 1 << len
) - 1);
5534 /* Any other cases we can't handle. */
5538 /* If we couldn't do this for some reason, return the original
5540 if (GET_CODE (tem
) == CLOBBER
)
5546 /* X is a SET which contains an assignment of one object into
5547 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5548 or certain SUBREGS). If possible, convert it into a series of
5551 We half-heartedly support variable positions, but do not at all
5552 support variable lengths. */
5555 expand_field_assignment (x
)
5559 rtx pos
; /* Always counts from low bit. */
5562 enum machine_mode compute_mode
;
5564 /* Loop until we find something we can't simplify. */
5567 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5568 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5570 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5571 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5572 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5574 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5575 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5577 inner
= XEXP (SET_DEST (x
), 0);
5578 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5579 pos
= XEXP (SET_DEST (x
), 2);
5581 /* If the position is constant and spans the width of INNER,
5582 surround INNER with a USE to indicate this. */
5583 if (GET_CODE (pos
) == CONST_INT
5584 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5585 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5587 if (BITS_BIG_ENDIAN
)
5589 if (GET_CODE (pos
) == CONST_INT
)
5590 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5592 else if (GET_CODE (pos
) == MINUS
5593 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5594 && (INTVAL (XEXP (pos
, 1))
5595 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5596 /* If position is ADJUST - X, new position is X. */
5597 pos
= XEXP (pos
, 0);
5599 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5600 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5606 /* A SUBREG between two modes that occupy the same numbers of words
5607 can be done by moving the SUBREG to the source. */
5608 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5609 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5610 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5611 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5612 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5614 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5615 gen_lowpart_for_combine
5616 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5623 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5624 inner
= SUBREG_REG (inner
);
5626 compute_mode
= GET_MODE (inner
);
5628 /* Don't attempt bitwise arithmetic on non-integral modes. */
5629 if (! INTEGRAL_MODE_P (compute_mode
))
5631 enum machine_mode imode
;
5633 /* Something is probably seriously wrong if this matches. */
5634 if (! FLOAT_MODE_P (compute_mode
))
5637 /* Try to find an integral mode to pun with. */
5638 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5639 if (imode
== BLKmode
)
5642 compute_mode
= imode
;
5643 inner
= gen_lowpart_for_combine (imode
, inner
);
5646 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5647 if (len
< HOST_BITS_PER_WIDE_INT
)
5648 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5652 /* Now compute the equivalent expression. Make a copy of INNER
5653 for the SET_DEST in case it is a MEM into which we will substitute;
5654 we don't want shared RTL in that case. */
5656 (VOIDmode
, copy_rtx (inner
),
5657 gen_binary (IOR
, compute_mode
,
5658 gen_binary (AND
, compute_mode
,
5659 gen_unary (NOT
, compute_mode
,
5665 gen_binary (ASHIFT
, compute_mode
,
5666 gen_binary (AND
, compute_mode
,
5667 gen_lowpart_for_combine
5668 (compute_mode
, SET_SRC (x
)),
5676 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5677 it is an RTX that represents a variable starting position; otherwise,
5678 POS is the (constant) starting bit position (counted from the LSB).
5680 INNER may be a USE. This will occur when we started with a bitfield
5681 that went outside the boundary of the object in memory, which is
5682 allowed on most machines. To isolate this case, we produce a USE
5683 whose mode is wide enough and surround the MEM with it. The only
5684 code that understands the USE is this routine. If it is not removed,
5685 it will cause the resulting insn not to match.
5687 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5690 IN_DEST is non-zero if this is a reference in the destination of a
5691 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5692 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5695 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5696 ZERO_EXTRACT should be built even for bits starting at bit 0.
5698 MODE is the desired mode of the result (if IN_DEST == 0).
5700 The result is an RTX for the extraction or NULL_RTX if the target
5704 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5705 unsignedp
, in_dest
, in_compare
)
5706 enum machine_mode mode
;
5712 int in_dest
, in_compare
;
5714 /* This mode describes the size of the storage area
5715 to fetch the overall value from. Within that, we
5716 ignore the POS lowest bits, etc. */
5717 enum machine_mode is_mode
= GET_MODE (inner
);
5718 enum machine_mode inner_mode
;
5719 enum machine_mode wanted_inner_mode
= byte_mode
;
5720 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5721 enum machine_mode pos_mode
= word_mode
;
5722 enum machine_mode extraction_mode
= word_mode
;
5723 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5726 rtx orig_pos_rtx
= pos_rtx
;
5729 /* Get some information about INNER and get the innermost object. */
5730 if (GET_CODE (inner
) == USE
)
5731 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5732 /* We don't need to adjust the position because we set up the USE
5733 to pretend that it was a full-word object. */
5734 spans_byte
= 1, inner
= XEXP (inner
, 0);
5735 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5737 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5738 consider just the QI as the memory to extract from.
5739 The subreg adds or removes high bits; its mode is
5740 irrelevant to the meaning of this extraction,
5741 since POS and LEN count from the lsb. */
5742 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5743 is_mode
= GET_MODE (SUBREG_REG (inner
));
5744 inner
= SUBREG_REG (inner
);
5747 inner_mode
= GET_MODE (inner
);
5749 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5750 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5752 /* See if this can be done without an extraction. We never can if the
5753 width of the field is not the same as that of some integer mode. For
5754 registers, we can only avoid the extraction if the position is at the
5755 low-order bit and this is either not in the destination or we have the
5756 appropriate STRICT_LOW_PART operation available.
5758 For MEM, we can avoid an extract if the field starts on an appropriate
5759 boundary and we can change the mode of the memory reference. However,
5760 we cannot directly access the MEM if we have a USE and the underlying
5761 MEM is not TMODE. This combination means that MEM was being used in a
5762 context where bits outside its mode were being referenced; that is only
5763 valid in bit-field insns. */
5765 if (tmode
!= BLKmode
5766 && ! (spans_byte
&& inner_mode
!= tmode
)
5767 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5768 && GET_CODE (inner
) != MEM
5770 || (GET_CODE (inner
) == REG
5771 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5772 != CODE_FOR_nothing
))))
5773 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5775 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5776 : BITS_PER_UNIT
)) == 0
5777 /* We can't do this if we are widening INNER_MODE (it
5778 may not be aligned, for one thing). */
5779 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5780 && (inner_mode
== tmode
5781 || (! mode_dependent_address_p (XEXP (inner
, 0))
5782 && ! MEM_VOLATILE_P (inner
))))))
5784 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5785 field. If the original and current mode are the same, we need not
5786 adjust the offset. Otherwise, we do if bytes big endian.
5788 If INNER is not a MEM, get a piece consisting of just the field
5789 of interest (in this case POS % BITS_PER_WORD must be 0). */
5791 if (GET_CODE (inner
) == MEM
)
5794 /* POS counts from lsb, but make OFFSET count in memory order. */
5795 if (BYTES_BIG_ENDIAN
)
5796 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5798 offset
= pos
/ BITS_PER_UNIT
;
5800 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
5801 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
5802 MEM_COPY_ATTRIBUTES (new, inner
);
5804 else if (GET_CODE (inner
) == REG
)
5806 /* We can't call gen_lowpart_for_combine here since we always want
5807 a SUBREG and it would sometimes return a new hard register. */
5808 if (tmode
!= inner_mode
)
5809 new = gen_rtx_SUBREG (tmode
, inner
,
5811 && (GET_MODE_SIZE (inner_mode
)
5813 ? (((GET_MODE_SIZE (inner_mode
)
5814 - GET_MODE_SIZE (tmode
))
5816 - pos
/ BITS_PER_WORD
)
5817 : pos
/ BITS_PER_WORD
));
5822 new = force_to_mode (inner
, tmode
,
5823 len
>= HOST_BITS_PER_WIDE_INT
5824 ? GET_MODE_MASK (tmode
)
5825 : ((HOST_WIDE_INT
) 1 << len
) - 1,
5828 /* If this extraction is going into the destination of a SET,
5829 make a STRICT_LOW_PART unless we made a MEM. */
5832 return (GET_CODE (new) == MEM
? new
5833 : (GET_CODE (new) != SUBREG
5834 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5835 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
5837 /* Otherwise, sign- or zero-extend unless we already are in the
5840 return (mode
== tmode
? new
5841 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5845 /* Unless this is a COMPARE or we have a funny memory reference,
5846 don't do anything with zero-extending field extracts starting at
5847 the low-order bit since they are simple AND operations. */
5848 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5849 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5852 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5853 we would be spanning bytes or if the position is not a constant and the
5854 length is not 1. In all other cases, we would only be going outside
5855 our object in cases when an original shift would have been
5857 if (! spans_byte
&& GET_CODE (inner
) == MEM
5858 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5859 || (pos_rtx
!= 0 && len
!= 1)))
5862 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5863 and the mode for the result. */
5867 wanted_inner_reg_mode
5868 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
5869 if (wanted_inner_reg_mode
== VOIDmode
)
5870 wanted_inner_reg_mode
= word_mode
;
5872 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
5873 if (pos_mode
== VOIDmode
)
5874 pos_mode
= word_mode
;
5876 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
5877 if (extraction_mode
== VOIDmode
)
5878 extraction_mode
= word_mode
;
5883 if (! in_dest
&& unsignedp
)
5885 wanted_inner_reg_mode
5886 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
5887 if (wanted_inner_reg_mode
== VOIDmode
)
5888 wanted_inner_reg_mode
= word_mode
;
5890 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
5891 if (pos_mode
== VOIDmode
)
5892 pos_mode
= word_mode
;
5894 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
5895 if (extraction_mode
== VOIDmode
)
5896 extraction_mode
= word_mode
;
5901 if (! in_dest
&& ! unsignedp
)
5903 wanted_inner_reg_mode
5904 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
5905 if (wanted_inner_reg_mode
== VOIDmode
)
5906 wanted_inner_reg_mode
= word_mode
;
5908 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
5909 if (pos_mode
== VOIDmode
)
5910 pos_mode
= word_mode
;
5912 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
5913 if (extraction_mode
== VOIDmode
)
5914 extraction_mode
= word_mode
;
5918 /* Never narrow an object, since that might not be safe. */
5920 if (mode
!= VOIDmode
5921 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
5922 extraction_mode
= mode
;
5924 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
5925 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
5926 pos_mode
= GET_MODE (pos_rtx
);
5928 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5929 if we have to change the mode of memory and cannot, the desired mode is
5931 if (GET_CODE (inner
) != MEM
)
5932 wanted_inner_mode
= wanted_inner_reg_mode
;
5933 else if (inner_mode
!= wanted_inner_mode
5934 && (mode_dependent_address_p (XEXP (inner
, 0))
5935 || MEM_VOLATILE_P (inner
)))
5936 wanted_inner_mode
= extraction_mode
;
5940 if (BITS_BIG_ENDIAN
)
5942 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5943 BITS_BIG_ENDIAN style. If position is constant, compute new
5944 position. Otherwise, build subtraction.
5945 Note that POS is relative to the mode of the original argument.
5946 If it's a MEM we need to recompute POS relative to that.
5947 However, if we're extracting from (or inserting into) a register,
5948 we want to recompute POS relative to wanted_inner_mode. */
5949 int width
= (GET_CODE (inner
) == MEM
5950 ? GET_MODE_BITSIZE (is_mode
)
5951 : GET_MODE_BITSIZE (wanted_inner_mode
));
5954 pos
= width
- len
- pos
;
5957 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
5958 GEN_INT (width
- len
), pos_rtx
);
5959 /* POS may be less than 0 now, but we check for that below.
5960 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5963 /* If INNER has a wider mode, make it smaller. If this is a constant
5964 extract, try to adjust the byte to point to the byte containing
5966 if (wanted_inner_mode
!= VOIDmode
5967 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
5968 && ((GET_CODE (inner
) == MEM
5969 && (inner_mode
== wanted_inner_mode
5970 || (! mode_dependent_address_p (XEXP (inner
, 0))
5971 && ! MEM_VOLATILE_P (inner
))))))
5975 /* The computations below will be correct if the machine is big
5976 endian in both bits and bytes or little endian in bits and bytes.
5977 If it is mixed, we must adjust. */
5979 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5980 adjust OFFSET to compensate. */
5981 if (BYTES_BIG_ENDIAN
5983 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
5984 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
5986 /* If this is a constant position, we can move to the desired byte. */
5989 offset
+= pos
/ BITS_PER_UNIT
;
5990 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
5993 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
5995 && is_mode
!= wanted_inner_mode
)
5996 offset
= (GET_MODE_SIZE (is_mode
)
5997 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
5999 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6001 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6002 plus_constant (XEXP (inner
, 0), offset
));
6003 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
6004 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6009 /* If INNER is not memory, we can always get it into the proper mode. If we
6010 are changing its mode, POS must be a constant and smaller than the size
6012 else if (GET_CODE (inner
) != MEM
)
6014 if (GET_MODE (inner
) != wanted_inner_mode
6016 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6019 inner
= force_to_mode (inner
, wanted_inner_mode
,
6021 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6022 ? GET_MODE_MASK (wanted_inner_mode
)
6023 : (((HOST_WIDE_INT
) 1 << len
) - 1) << orig_pos
,
6027 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6028 have to zero extend. Otherwise, we can just use a SUBREG. */
6030 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6031 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6032 else if (pos_rtx
!= 0
6033 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6034 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6036 /* Make POS_RTX unless we already have it and it is correct. If we don't
6037 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6039 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6040 pos_rtx
= orig_pos_rtx
;
6042 else if (pos_rtx
== 0)
6043 pos_rtx
= GEN_INT (pos
);
6045 /* Make the required operation. See if we can use existing rtx. */
6046 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6047 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6049 new = gen_lowpart_for_combine (mode
, new);
6054 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6055 with any other operations in X. Return X without that shift if so. */
6058 extract_left_shift (x
, count
)
6062 enum rtx_code code
= GET_CODE (x
);
6063 enum machine_mode mode
= GET_MODE (x
);
6069 /* This is the shift itself. If it is wide enough, we will return
6070 either the value being shifted if the shift count is equal to
6071 COUNT or a shift for the difference. */
6072 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6073 && INTVAL (XEXP (x
, 1)) >= count
)
6074 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6075 INTVAL (XEXP (x
, 1)) - count
);
6079 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6080 return gen_unary (code
, mode
, mode
, tem
);
6084 case PLUS
: case IOR
: case XOR
: case AND
:
6085 /* If we can safely shift this constant and we find the inner shift,
6086 make a new operation. */
6087 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6088 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6089 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6090 return gen_binary (code
, mode
, tem
,
6091 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6102 /* Look at the expression rooted at X. Look for expressions
6103 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6104 Form these expressions.
6106 Return the new rtx, usually just X.
6108 Also, for machines like the Vax that don't have logical shift insns,
6109 try to convert logical to arithmetic shift operations in cases where
6110 they are equivalent. This undoes the canonicalizations to logical
6111 shifts done elsewhere.
6113 We try, as much as possible, to re-use rtl expressions to save memory.
6115 IN_CODE says what kind of expression we are processing. Normally, it is
6116 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6117 being kludges), it is MEM. When processing the arguments of a comparison
6118 or a COMPARE against zero, it is COMPARE. */
6121 make_compound_operation (x
, in_code
)
6123 enum rtx_code in_code
;
6125 enum rtx_code code
= GET_CODE (x
);
6126 enum machine_mode mode
= GET_MODE (x
);
6127 int mode_width
= GET_MODE_BITSIZE (mode
);
6129 enum rtx_code next_code
;
6135 /* Select the code to be used in recursive calls. Once we are inside an
6136 address, we stay there. If we have a comparison, set to COMPARE,
6137 but once inside, go back to our default of SET. */
6139 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6140 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6141 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6142 : in_code
== COMPARE
? SET
: in_code
);
6144 /* Process depending on the code of this operation. If NEW is set
6145 non-zero, it will be returned. */
6150 /* Convert shifts by constants into multiplications if inside
6152 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6153 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6154 && INTVAL (XEXP (x
, 1)) >= 0)
6156 new = make_compound_operation (XEXP (x
, 0), next_code
);
6157 new = gen_rtx_combine (MULT
, mode
, new,
6158 GEN_INT ((HOST_WIDE_INT
) 1
6159 << INTVAL (XEXP (x
, 1))));
6164 /* If the second operand is not a constant, we can't do anything
6166 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6169 /* If the constant is a power of two minus one and the first operand
6170 is a logical right shift, make an extraction. */
6171 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6172 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6174 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6175 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6176 0, in_code
== COMPARE
);
6179 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6180 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6181 && subreg_lowpart_p (XEXP (x
, 0))
6182 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6183 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6185 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6187 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6188 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6189 0, in_code
== COMPARE
);
6191 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6192 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6193 || GET_CODE (XEXP (x
, 0)) == IOR
)
6194 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6195 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6196 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6198 /* Apply the distributive law, and then try to make extractions. */
6199 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6200 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6202 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6204 new = make_compound_operation (new, in_code
);
6207 /* If we are have (and (rotate X C) M) and C is larger than the number
6208 of bits in M, this is an extraction. */
6210 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6211 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6212 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6213 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6215 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6216 new = make_extraction (mode
, new,
6217 (GET_MODE_BITSIZE (mode
)
6218 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6219 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6222 /* On machines without logical shifts, if the operand of the AND is
6223 a logical shift and our mask turns off all the propagated sign
6224 bits, we can replace the logical shift with an arithmetic shift. */
6225 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6226 && (lshr_optab
->handlers
[(int) mode
].insn_code
6227 == CODE_FOR_nothing
)
6228 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6229 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6230 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6231 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6232 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6234 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6236 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6237 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6239 gen_rtx_combine (ASHIFTRT
, mode
,
6240 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6242 XEXP (XEXP (x
, 0), 1)));
6245 /* If the constant is one less than a power of two, this might be
6246 representable by an extraction even if no shift is present.
6247 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6248 we are in a COMPARE. */
6249 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6250 new = make_extraction (mode
,
6251 make_compound_operation (XEXP (x
, 0),
6253 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6255 /* If we are in a comparison and this is an AND with a power of two,
6256 convert this into the appropriate bit extract. */
6257 else if (in_code
== COMPARE
6258 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6259 new = make_extraction (mode
,
6260 make_compound_operation (XEXP (x
, 0),
6262 i
, NULL_RTX
, 1, 1, 0, 1);
6267 /* If the sign bit is known to be zero, replace this with an
6268 arithmetic shift. */
6269 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6270 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6271 && mode_width
<= HOST_BITS_PER_WIDE_INT
6272 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6274 new = gen_rtx_combine (ASHIFTRT
, mode
,
6275 make_compound_operation (XEXP (x
, 0),
6281 /* ... fall through ... */
6287 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6288 this is a SIGN_EXTRACT. */
6289 if (GET_CODE (rhs
) == CONST_INT
6290 && GET_CODE (lhs
) == ASHIFT
6291 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6292 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6294 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6295 new = make_extraction (mode
, new,
6296 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6297 NULL_RTX
, mode_width
- INTVAL (rhs
),
6298 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6301 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6302 If so, try to merge the shifts into a SIGN_EXTEND. We could
6303 also do this for some cases of SIGN_EXTRACT, but it doesn't
6304 seem worth the effort; the case checked for occurs on Alpha. */
6306 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6307 && ! (GET_CODE (lhs
) == SUBREG
6308 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6309 && GET_CODE (rhs
) == CONST_INT
6310 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6311 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6312 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6313 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6314 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6319 /* Call ourselves recursively on the inner expression. If we are
6320 narrowing the object and it has a different RTL code from
6321 what it originally did, do this SUBREG as a force_to_mode. */
6323 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6324 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6325 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6326 && subreg_lowpart_p (x
))
6328 rtx newer
= force_to_mode (tem
, mode
,
6329 GET_MODE_MASK (mode
), NULL_RTX
, 0);
6331 /* If we have something other than a SUBREG, we might have
6332 done an expansion, so rerun outselves. */
6333 if (GET_CODE (newer
) != SUBREG
)
6334 newer
= make_compound_operation (newer
, in_code
);
6339 /* If this is a paradoxical subreg, and the new code is a sign or
6340 zero extension, omit the subreg and widen the extension. If it
6341 is a regular subreg, we can still get rid of the subreg by not
6342 widening so much, or in fact removing the extension entirely. */
6343 if ((GET_CODE (tem
) == SIGN_EXTEND
6344 || GET_CODE (tem
) == ZERO_EXTEND
)
6345 && subreg_lowpart_p (x
))
6347 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6348 || (GET_MODE_SIZE (mode
) >
6349 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6350 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6352 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6363 x
= gen_lowpart_for_combine (mode
, new);
6364 code
= GET_CODE (x
);
6367 /* Now recursively process each operand of this operation. */
6368 fmt
= GET_RTX_FORMAT (code
);
6369 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6372 new = make_compound_operation (XEXP (x
, i
), next_code
);
6373 SUBST (XEXP (x
, i
), new);
6379 /* Given M see if it is a value that would select a field of bits
6380 within an item, but not the entire word. Return -1 if not.
6381 Otherwise, return the starting position of the field, where 0 is the
6384 *PLEN is set to the length of the field. */
6387 get_pos_from_mask (m
, plen
)
6388 unsigned HOST_WIDE_INT m
;
6391 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6392 int pos
= exact_log2 (m
& - m
);
6397 /* Now shift off the low-order zero bits and see if we have a power of
6399 *plen
= exact_log2 ((m
>> pos
) + 1);
6407 /* See if X can be simplified knowing that we will only refer to it in
6408 MODE and will only refer to those bits that are nonzero in MASK.
6409 If other bits are being computed or if masking operations are done
6410 that select a superset of the bits in MASK, they can sometimes be
6413 Return a possibly simplified expression, but always convert X to
6414 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6416 Also, if REG is non-zero and X is a register equal in value to REG,
6419 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6420 are all off in X. This is used when X will be complemented, by either
6421 NOT, NEG, or XOR. */
6424 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6426 enum machine_mode mode
;
6427 unsigned HOST_WIDE_INT mask
;
6431 enum rtx_code code
= GET_CODE (x
);
6432 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6433 enum machine_mode op_mode
;
6434 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6437 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6438 code below will do the wrong thing since the mode of such an
6439 expression is VOIDmode.
6441 Also do nothing if X is a CLOBBER; this can happen if X was
6442 the return value from a call to gen_lowpart_for_combine. */
6443 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6446 /* We want to perform the operation is its present mode unless we know
6447 that the operation is valid in MODE, in which case we do the operation
6449 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6450 && code_to_optab
[(int) code
] != 0
6451 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6452 != CODE_FOR_nothing
))
6453 ? mode
: GET_MODE (x
));
6455 /* It is not valid to do a right-shift in a narrower mode
6456 than the one it came in with. */
6457 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6458 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6459 op_mode
= GET_MODE (x
);
6461 /* Truncate MASK to fit OP_MODE. */
6463 mask
&= GET_MODE_MASK (op_mode
);
6465 /* When we have an arithmetic operation, or a shift whose count we
6466 do not know, we need to assume that all bit the up to the highest-order
6467 bit in MASK will be needed. This is how we form such a mask. */
6469 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6470 ? GET_MODE_MASK (op_mode
)
6471 : ((HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1)) - 1);
6473 fuller_mask
= ~ (HOST_WIDE_INT
) 0;
6475 /* Determine what bits of X are guaranteed to be (non)zero. */
6476 nonzero
= nonzero_bits (x
, mode
);
6478 /* If none of the bits in X are needed, return a zero. */
6479 if (! just_select
&& (nonzero
& mask
) == 0)
6482 /* If X is a CONST_INT, return a new one. Do this here since the
6483 test below will fail. */
6484 if (GET_CODE (x
) == CONST_INT
)
6486 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6487 int width
= GET_MODE_BITSIZE (mode
);
6489 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6490 number, sign extend it. */
6491 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6492 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6493 cval
|= (HOST_WIDE_INT
) -1 << width
;
6495 return GEN_INT (cval
);
6498 /* If X is narrower than MODE and we want all the bits in X's mode, just
6499 get X in the proper mode. */
6500 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6501 && (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
) == 0)
6502 return gen_lowpart_for_combine (mode
, x
);
6504 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6505 MASK are already known to be zero in X, we need not do anything. */
6506 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~ mask
& nonzero
) == 0)
6512 /* If X is a (clobber (const_int)), return it since we know we are
6513 generating something that won't match. */
6517 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6518 spanned the boundary of the MEM. If we are now masking so it is
6519 within that boundary, we don't need the USE any more. */
6520 if (! BITS_BIG_ENDIAN
6521 && (mask
& ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6522 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6529 x
= expand_compound_operation (x
);
6530 if (GET_CODE (x
) != code
)
6531 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6535 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6536 || rtx_equal_p (reg
, get_last_value (x
))))
6541 if (subreg_lowpart_p (x
)
6542 /* We can ignore the effect of this SUBREG if it narrows the mode or
6543 if the constant masks to zero all the bits the mode doesn't
6545 && ((GET_MODE_SIZE (GET_MODE (x
))
6546 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6548 & GET_MODE_MASK (GET_MODE (x
))
6549 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6550 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6554 /* If this is an AND with a constant, convert it into an AND
6555 whose constant is the AND of that constant with MASK. If it
6556 remains an AND of MASK, delete it since it is redundant. */
6558 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6560 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6561 mask
& INTVAL (XEXP (x
, 1)));
6563 /* If X is still an AND, see if it is an AND with a mask that
6564 is just some low-order bits. If so, and it is MASK, we don't
6567 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6568 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6571 /* If it remains an AND, try making another AND with the bits
6572 in the mode mask that aren't in MASK turned on. If the
6573 constant in the AND is wide enough, this might make a
6574 cheaper constant. */
6576 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6577 && GET_MODE_MASK (GET_MODE (x
)) != mask
6578 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6580 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6581 | (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
));
6582 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6585 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6586 number, sign extend it. */
6587 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6588 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6589 cval
|= (HOST_WIDE_INT
) -1 << width
;
6591 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6592 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6602 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6603 low-order bits (as in an alignment operation) and FOO is already
6604 aligned to that boundary, mask C1 to that boundary as well.
6605 This may eliminate that PLUS and, later, the AND. */
6608 int width
= GET_MODE_BITSIZE (mode
);
6609 unsigned HOST_WIDE_INT smask
= mask
;
6611 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6612 number, sign extend it. */
6614 if (width
< HOST_BITS_PER_WIDE_INT
6615 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6616 smask
|= (HOST_WIDE_INT
) -1 << width
;
6618 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6619 && exact_log2 (- smask
) >= 0)
6623 && (XEXP (x
, 0) == stack_pointer_rtx
6624 || XEXP (x
, 0) == frame_pointer_rtx
))
6626 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6627 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6629 sp_mask
&= ~ (sp_alignment
- 1);
6630 if ((sp_mask
& ~ smask
) == 0
6631 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~ smask
) != 0)
6632 return force_to_mode (plus_constant (XEXP (x
, 0),
6633 ((INTVAL (XEXP (x
, 1)) -
6634 STACK_BIAS
) & smask
)
6636 mode
, smask
, reg
, next_select
);
6639 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~ smask
) == 0
6640 && (INTVAL (XEXP (x
, 1)) & ~ smask
) != 0)
6641 return force_to_mode (plus_constant (XEXP (x
, 0),
6642 (INTVAL (XEXP (x
, 1))
6644 mode
, smask
, reg
, next_select
);
6648 /* ... fall through ... */
6652 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6653 most significant bit in MASK since carries from those bits will
6654 affect the bits we are interested in. */
6660 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6661 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6662 operation which may be a bitfield extraction. Ensure that the
6663 constant we form is not wider than the mode of X. */
6665 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6666 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6667 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6668 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6669 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6670 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6671 + floor_log2 (INTVAL (XEXP (x
, 1))))
6672 < GET_MODE_BITSIZE (GET_MODE (x
)))
6673 && (INTVAL (XEXP (x
, 1))
6674 & ~ nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6676 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6677 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6678 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6679 XEXP (XEXP (x
, 0), 0), temp
);
6680 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6681 XEXP (XEXP (x
, 0), 1));
6682 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6686 /* For most binary operations, just propagate into the operation and
6687 change the mode if we have an operation of that mode. */
6689 op0
= gen_lowpart_for_combine (op_mode
,
6690 force_to_mode (XEXP (x
, 0), mode
, mask
,
6692 op1
= gen_lowpart_for_combine (op_mode
,
6693 force_to_mode (XEXP (x
, 1), mode
, mask
,
6696 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6697 MASK since OP1 might have been sign-extended but we never want
6698 to turn on extra bits, since combine might have previously relied
6699 on them being off. */
6700 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6701 && (INTVAL (op1
) & mask
) != 0)
6702 op1
= GEN_INT (INTVAL (op1
) & mask
);
6704 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6705 x
= gen_binary (code
, op_mode
, op0
, op1
);
6709 /* For left shifts, do the same, but just for the first operand.
6710 However, we cannot do anything with shifts where we cannot
6711 guarantee that the counts are smaller than the size of the mode
6712 because such a count will have a different meaning in a
6715 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6716 && INTVAL (XEXP (x
, 1)) >= 0
6717 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6718 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6719 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6720 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6723 /* If the shift count is a constant and we can do arithmetic in
6724 the mode of the shift, refine which bits we need. Otherwise, use the
6725 conservative form of the mask. */
6726 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6727 && INTVAL (XEXP (x
, 1)) >= 0
6728 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6729 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6730 mask
>>= INTVAL (XEXP (x
, 1));
6734 op0
= gen_lowpart_for_combine (op_mode
,
6735 force_to_mode (XEXP (x
, 0), op_mode
,
6736 mask
, reg
, next_select
));
6738 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6739 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6743 /* Here we can only do something if the shift count is a constant,
6744 this shift constant is valid for the host, and we can do arithmetic
6747 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6748 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6749 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6751 rtx inner
= XEXP (x
, 0);
6753 /* Select the mask of the bits we need for the shift operand. */
6754 mask
<<= INTVAL (XEXP (x
, 1));
6756 /* We can only change the mode of the shift if we can do arithmetic
6757 in the mode of the shift and MASK is no wider than the width of
6759 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6760 || (mask
& ~ GET_MODE_MASK (op_mode
)) != 0)
6761 op_mode
= GET_MODE (x
);
6763 inner
= force_to_mode (inner
, op_mode
, mask
, reg
, next_select
);
6765 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6766 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6769 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6770 shift and AND produces only copies of the sign bit (C2 is one less
6771 than a power of two), we can do this with just a shift. */
6773 if (GET_CODE (x
) == LSHIFTRT
6774 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6775 && ((INTVAL (XEXP (x
, 1))
6776 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6777 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6778 && exact_log2 (mask
+ 1) >= 0
6779 && (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6780 >= exact_log2 (mask
+ 1)))
6781 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6782 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6783 - exact_log2 (mask
+ 1)));
6788 /* If we are just looking for the sign bit, we don't need this shift at
6789 all, even if it has a variable count. */
6790 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6791 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6792 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6793 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6795 /* If this is a shift by a constant, get a mask that contains those bits
6796 that are not copies of the sign bit. We then have two cases: If
6797 MASK only includes those bits, this can be a logical shift, which may
6798 allow simplifications. If MASK is a single-bit field not within
6799 those bits, we are requesting a copy of the sign bit and hence can
6800 shift the sign bit to the appropriate location. */
6802 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6803 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6807 /* If the considered data is wider then HOST_WIDE_INT, we can't
6808 represent a mask for all its bits in a single scalar.
6809 But we only care about the lower bits, so calculate these. */
6811 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6813 nonzero
= ~ (HOST_WIDE_INT
) 0;
6815 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6816 is the number of bits a full-width mask would have set.
6817 We need only shift if these are fewer than nonzero can
6818 hold. If not, we must keep all bits set in nonzero. */
6820 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6821 < HOST_BITS_PER_WIDE_INT
)
6822 nonzero
>>= INTVAL (XEXP (x
, 1))
6823 + HOST_BITS_PER_WIDE_INT
6824 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6828 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6829 nonzero
>>= INTVAL (XEXP (x
, 1));
6832 if ((mask
& ~ nonzero
) == 0
6833 || (i
= exact_log2 (mask
)) >= 0)
6835 x
= simplify_shift_const
6836 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6837 i
< 0 ? INTVAL (XEXP (x
, 1))
6838 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
6840 if (GET_CODE (x
) != ASHIFTRT
)
6841 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6845 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6846 even if the shift count isn't a constant. */
6848 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
6852 /* If this is a zero- or sign-extension operation that just affects bits
6853 we don't care about, remove it. Be sure the call above returned
6854 something that is still a shift. */
6856 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
6857 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6858 && INTVAL (XEXP (x
, 1)) >= 0
6859 && (INTVAL (XEXP (x
, 1))
6860 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
6861 && GET_CODE (XEXP (x
, 0)) == ASHIFT
6862 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6863 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
6864 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
6871 /* If the shift count is constant and we can do computations
6872 in the mode of X, compute where the bits we care about are.
6873 Otherwise, we can't do anything. Don't change the mode of
6874 the shift or propagate MODE into the shift, though. */
6875 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6876 && INTVAL (XEXP (x
, 1)) >= 0)
6878 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
6879 GET_MODE (x
), GEN_INT (mask
),
6881 if (temp
&& GET_CODE(temp
) == CONST_INT
)
6883 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
6884 INTVAL (temp
), reg
, next_select
));
6889 /* If we just want the low-order bit, the NEG isn't needed since it
6890 won't change the low-order bit. */
6892 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
6894 /* We need any bits less significant than the most significant bit in
6895 MASK since carries from those bits will affect the bits we are
6901 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6902 same as the XOR case above. Ensure that the constant we form is not
6903 wider than the mode of X. */
6905 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6906 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6907 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6908 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
6909 < GET_MODE_BITSIZE (GET_MODE (x
)))
6910 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
6912 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
6913 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
6914 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
6916 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6919 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6920 use the full mask inside the NOT. */
6924 op0
= gen_lowpart_for_combine (op_mode
,
6925 force_to_mode (XEXP (x
, 0), mode
, mask
,
6927 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6928 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
6932 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6933 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6934 which is equal to STORE_FLAG_VALUE. */
6935 if ((mask
& ~ STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
6936 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
6937 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
6938 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6943 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6944 written in a narrower mode. We play it safe and do not do so. */
6947 gen_lowpart_for_combine (GET_MODE (x
),
6948 force_to_mode (XEXP (x
, 1), mode
,
6949 mask
, reg
, next_select
)));
6951 gen_lowpart_for_combine (GET_MODE (x
),
6952 force_to_mode (XEXP (x
, 2), mode
,
6953 mask
, reg
,next_select
)));
6960 /* Ensure we return a value of the proper mode. */
6961 return gen_lowpart_for_combine (mode
, x
);
6964 /* Return nonzero if X is an expression that has one of two values depending on
6965 whether some other value is zero or nonzero. In that case, we return the
6966 value that is being tested, *PTRUE is set to the value if the rtx being
6967 returned has a nonzero value, and *PFALSE is set to the other alternative.
6969 If we return zero, we set *PTRUE and *PFALSE to X. */
6972 if_then_else_cond (x
, ptrue
, pfalse
)
6974 rtx
*ptrue
, *pfalse
;
6976 enum machine_mode mode
= GET_MODE (x
);
6977 enum rtx_code code
= GET_CODE (x
);
6978 int size
= GET_MODE_BITSIZE (mode
);
6979 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
6980 unsigned HOST_WIDE_INT nz
;
6982 /* If we are comparing a value against zero, we are done. */
6983 if ((code
== NE
|| code
== EQ
)
6984 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
6986 *ptrue
= (code
== NE
) ? const1_rtx
: const0_rtx
;
6987 *pfalse
= (code
== NE
) ? const0_rtx
: const1_rtx
;
6991 /* If this is a unary operation whose operand has one of two values, apply
6992 our opcode to compute those values. */
6993 else if (GET_RTX_CLASS (code
) == '1'
6994 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
6996 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
6997 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
7001 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7002 make can't possibly match and would suppress other optimizations. */
7003 else if (code
== COMPARE
)
7006 /* If this is a binary operation, see if either side has only one of two
7007 values. If either one does or if both do and they are conditional on
7008 the same value, compute the new true and false values. */
7009 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7010 || GET_RTX_CLASS (code
) == '<')
7012 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7013 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7015 if ((cond0
!= 0 || cond1
!= 0)
7016 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7018 /* If if_then_else_cond returned zero, then true/false are the
7019 same rtl. We must copy one of them to prevent invalid rtl
7022 true0
= copy_rtx (true0
);
7023 else if (cond1
== 0)
7024 true1
= copy_rtx (true1
);
7026 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7027 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7028 return cond0
? cond0
: cond1
;
7031 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7032 operands is zero when the other is non-zero, and vice-versa,
7033 and STORE_FLAG_VALUE is 1 or -1. */
7035 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7036 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7038 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7040 rtx op0
= XEXP (XEXP (x
, 0), 1);
7041 rtx op1
= XEXP (XEXP (x
, 1), 1);
7043 cond0
= XEXP (XEXP (x
, 0), 0);
7044 cond1
= XEXP (XEXP (x
, 1), 0);
7046 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7047 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7048 && reversible_comparison_p (cond1
)
7049 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7050 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7051 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7052 || ((swap_condition (GET_CODE (cond0
))
7053 == reverse_condition (GET_CODE (cond1
)))
7054 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7055 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7056 && ! side_effects_p (x
))
7058 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7059 *pfalse
= gen_binary (MULT
, mode
,
7061 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7067 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7069 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7070 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7071 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7073 cond0
= XEXP (XEXP (x
, 0), 0);
7074 cond1
= XEXP (XEXP (x
, 1), 0);
7076 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7077 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7078 && reversible_comparison_p (cond1
)
7079 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7080 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7081 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7082 || ((swap_condition (GET_CODE (cond0
))
7083 == reverse_condition (GET_CODE (cond1
)))
7084 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7085 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7086 && ! side_effects_p (x
))
7088 *ptrue
= *pfalse
= const0_rtx
;
7094 else if (code
== IF_THEN_ELSE
)
7096 /* If we have IF_THEN_ELSE already, extract the condition and
7097 canonicalize it if it is NE or EQ. */
7098 cond0
= XEXP (x
, 0);
7099 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7100 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7101 return XEXP (cond0
, 0);
7102 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7104 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7105 return XEXP (cond0
, 0);
7111 /* If X is a normal SUBREG with both inner and outer modes integral,
7112 we can narrow both the true and false values of the inner expression,
7113 if there is a condition. */
7114 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7115 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7116 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7117 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7120 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7121 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
7123 true0
= operand_subword (true0
, SUBREG_WORD (x
), 0, mode
);
7124 false0
= operand_subword (false0
, SUBREG_WORD (x
), 0, mode
);
7126 *ptrue
= force_to_mode (true0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
7128 = force_to_mode (false0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
7133 /* If X is a constant, this isn't special and will cause confusions
7134 if we treat it as such. Likewise if it is equivalent to a constant. */
7135 else if (CONSTANT_P (x
)
7136 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7139 /* If X is known to be either 0 or -1, those are the true and
7140 false values when testing X. */
7141 else if (num_sign_bit_copies (x
, mode
) == size
)
7143 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7147 /* Likewise for 0 or a single bit. */
7148 else if (exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7150 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7154 /* Otherwise fail; show no condition with true and false values the same. */
7155 *ptrue
= *pfalse
= x
;
7159 /* Return the value of expression X given the fact that condition COND
7160 is known to be true when applied to REG as its first operand and VAL
7161 as its second. X is known to not be shared and so can be modified in
7164 We only handle the simplest cases, and specifically those cases that
7165 arise with IF_THEN_ELSE expressions. */
7168 known_cond (x
, cond
, reg
, val
)
7173 enum rtx_code code
= GET_CODE (x
);
7178 if (side_effects_p (x
))
7181 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
7184 /* If X is (abs REG) and we know something about REG's relationship
7185 with zero, we may be able to simplify this. */
7187 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7190 case GE
: case GT
: case EQ
:
7193 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7199 /* The only other cases we handle are MIN, MAX, and comparisons if the
7200 operands are the same as REG and VAL. */
7202 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7204 if (rtx_equal_p (XEXP (x
, 0), val
))
7205 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7207 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7209 if (GET_RTX_CLASS (code
) == '<')
7210 return (comparison_dominates_p (cond
, code
) ? const_true_rtx
7211 : (comparison_dominates_p (cond
,
7212 reverse_condition (code
))
7215 else if (code
== SMAX
|| code
== SMIN
7216 || code
== UMIN
|| code
== UMAX
)
7218 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7220 if (code
== SMAX
|| code
== UMAX
)
7221 cond
= reverse_condition (cond
);
7226 return unsignedp
? x
: XEXP (x
, 1);
7228 return unsignedp
? x
: XEXP (x
, 0);
7230 return unsignedp
? XEXP (x
, 1) : x
;
7232 return unsignedp
? XEXP (x
, 0) : x
;
7240 fmt
= GET_RTX_FORMAT (code
);
7241 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7244 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7245 else if (fmt
[i
] == 'E')
7246 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7247 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7254 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7255 assignment as a field assignment. */
7258 rtx_equal_for_field_assignment_p (x
, y
)
7262 if (x
== y
|| rtx_equal_p (x
, y
))
7265 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7268 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7269 Note that all SUBREGs of MEM are paradoxical; otherwise they
7270 would have been rewritten. */
7271 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7272 && GET_CODE (SUBREG_REG (y
)) == MEM
7273 && rtx_equal_p (SUBREG_REG (y
),
7274 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7277 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7278 && GET_CODE (SUBREG_REG (x
)) == MEM
7279 && rtx_equal_p (SUBREG_REG (x
),
7280 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7283 /* We used to see if get_last_value of X and Y were the same but that's
7284 not correct. In one direction, we'll cause the assignment to have
7285 the wrong destination and in the case, we'll import a register into this
7286 insn that might have already have been dead. So fail if none of the
7287 above cases are true. */
7291 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7292 Return that assignment if so.
7294 We only handle the most common cases. */
7297 make_field_assignment (x
)
7300 rtx dest
= SET_DEST (x
);
7301 rtx src
= SET_SRC (x
);
7307 enum machine_mode mode
;
7309 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7310 a clear of a one-bit field. We will have changed it to
7311 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7314 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7315 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7316 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7317 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7319 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7322 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7326 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7327 && subreg_lowpart_p (XEXP (src
, 0))
7328 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7329 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7330 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7331 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7332 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7334 assign
= make_extraction (VOIDmode
, dest
, 0,
7335 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7338 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7342 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7344 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7345 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7346 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7348 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7351 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7355 /* The other case we handle is assignments into a constant-position
7356 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7357 a mask that has all one bits except for a group of zero bits and
7358 OTHER is known to have zeros where C1 has ones, this is such an
7359 assignment. Compute the position and length from C1. Shift OTHER
7360 to the appropriate position, force it to the required mode, and
7361 make the extraction. Check for the AND in both operands. */
7363 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7366 rhs
= expand_compound_operation (XEXP (src
, 0));
7367 lhs
= expand_compound_operation (XEXP (src
, 1));
7369 if (GET_CODE (rhs
) == AND
7370 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7371 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7372 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7373 else if (GET_CODE (lhs
) == AND
7374 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7375 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7376 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7380 pos
= get_pos_from_mask ((~ c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7381 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7382 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7383 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7386 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7390 /* The mode to use for the source is the mode of the assignment, or of
7391 what is inside a possible STRICT_LOW_PART. */
7392 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7393 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7395 /* Shift OTHER right POS places and make it the source, restricting it
7396 to the proper length and mode. */
7398 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7399 GET_MODE (src
), other
, pos
),
7401 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7402 ? GET_MODE_MASK (mode
)
7403 : ((HOST_WIDE_INT
) 1 << len
) - 1,
7406 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7409 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7413 apply_distributive_law (x
)
7416 enum rtx_code code
= GET_CODE (x
);
7417 rtx lhs
, rhs
, other
;
7419 enum rtx_code inner_code
;
7421 /* Distributivity is not true for floating point.
7422 It can change the value. So don't do it.
7423 -- rms and moshier@world.std.com. */
7424 if (FLOAT_MODE_P (GET_MODE (x
)))
7427 /* The outer operation can only be one of the following: */
7428 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7429 && code
!= PLUS
&& code
!= MINUS
)
7432 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7434 /* If either operand is a primitive we can't do anything, so get out
7436 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7437 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7440 lhs
= expand_compound_operation (lhs
);
7441 rhs
= expand_compound_operation (rhs
);
7442 inner_code
= GET_CODE (lhs
);
7443 if (inner_code
!= GET_CODE (rhs
))
7446 /* See if the inner and outer operations distribute. */
7453 /* These all distribute except over PLUS. */
7454 if (code
== PLUS
|| code
== MINUS
)
7459 if (code
!= PLUS
&& code
!= MINUS
)
7464 /* This is also a multiply, so it distributes over everything. */
7468 /* Non-paradoxical SUBREGs distributes over all operations, provided
7469 the inner modes and word numbers are the same, this is an extraction
7470 of a low-order part, we don't convert an fp operation to int or
7471 vice versa, and we would not be converting a single-word
7472 operation into a multi-word operation. The latter test is not
7473 required, but it prevents generating unneeded multi-word operations.
7474 Some of the previous tests are redundant given the latter test, but
7475 are retained because they are required for correctness.
7477 We produce the result slightly differently in this case. */
7479 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7480 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7481 || ! subreg_lowpart_p (lhs
)
7482 || (GET_MODE_CLASS (GET_MODE (lhs
))
7483 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7484 || (GET_MODE_SIZE (GET_MODE (lhs
))
7485 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7486 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7489 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7490 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7491 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7497 /* Set LHS and RHS to the inner operands (A and B in the example
7498 above) and set OTHER to the common operand (C in the example).
7499 These is only one way to do this unless the inner operation is
7501 if (GET_RTX_CLASS (inner_code
) == 'c'
7502 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7503 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7504 else if (GET_RTX_CLASS (inner_code
) == 'c'
7505 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7506 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7507 else if (GET_RTX_CLASS (inner_code
) == 'c'
7508 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7509 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7510 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7511 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7515 /* Form the new inner operation, seeing if it simplifies first. */
7516 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7518 /* There is one exception to the general way of distributing:
7519 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7520 if (code
== XOR
&& inner_code
== IOR
)
7523 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7526 /* We may be able to continuing distributing the result, so call
7527 ourselves recursively on the inner operation before forming the
7528 outer operation, which we return. */
7529 return gen_binary (inner_code
, GET_MODE (x
),
7530 apply_distributive_law (tem
), other
);
7533 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7536 Return an equivalent form, if different from X. Otherwise, return X. If
7537 X is zero, we are to always construct the equivalent form. */
7540 simplify_and_const_int (x
, mode
, varop
, constop
)
7542 enum machine_mode mode
;
7544 unsigned HOST_WIDE_INT constop
;
7546 unsigned HOST_WIDE_INT nonzero
;
7549 /* Simplify VAROP knowing that we will be only looking at some of the
7551 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7553 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7554 CONST_INT, we are done. */
7555 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7558 /* See what bits may be nonzero in VAROP. Unlike the general case of
7559 a call to nonzero_bits, here we don't care about bits outside
7562 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7563 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7565 /* Turn off all bits in the constant that are known to already be zero.
7566 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7567 which is tested below. */
7571 /* If we don't have any bits left, return zero. */
7575 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7576 a power of two, we can replace this with a ASHIFT. */
7577 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7578 && (i
= exact_log2 (constop
)) >= 0)
7579 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7581 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7582 or XOR, then try to apply the distributive law. This may eliminate
7583 operations if either branch can be simplified because of the AND.
7584 It may also make some cases more complex, but those cases probably
7585 won't match a pattern either with or without this. */
7587 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7589 gen_lowpart_for_combine
7591 apply_distributive_law
7592 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7593 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7594 XEXP (varop
, 0), constop
),
7595 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7596 XEXP (varop
, 1), constop
))));
7598 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7599 if we already had one (just check for the simplest cases). */
7600 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7601 && GET_MODE (XEXP (x
, 0)) == mode
7602 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7603 varop
= XEXP (x
, 0);
7605 varop
= gen_lowpart_for_combine (mode
, varop
);
7607 /* If we can't make the SUBREG, try to return what we were given. */
7608 if (GET_CODE (varop
) == CLOBBER
)
7609 return x
? x
: varop
;
7611 /* If we are only masking insignificant bits, return VAROP. */
7612 if (constop
== nonzero
)
7615 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7616 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7617 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7621 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7622 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7623 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7625 SUBST (XEXP (x
, 0), varop
);
7631 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7632 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7633 is less useful. We can't allow both, because that results in exponential
7634 run time recursion. There is a nullstone testcase that triggered
7635 this. This macro avoids accidental uses of num_sign_bit_copies. */
7636 #define num_sign_bit_copies()
7638 /* Given an expression, X, compute which bits in X can be non-zero.
7639 We don't care about bits outside of those defined in MODE.
7641 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7642 a shift, AND, or zero_extract, we can do better. */
7644 static unsigned HOST_WIDE_INT
7645 nonzero_bits (x
, mode
)
7647 enum machine_mode mode
;
7649 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7650 unsigned HOST_WIDE_INT inner_nz
;
7652 int mode_width
= GET_MODE_BITSIZE (mode
);
7655 /* For floating-point values, assume all bits are needed. */
7656 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7659 /* If X is wider than MODE, use its mode instead. */
7660 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7662 mode
= GET_MODE (x
);
7663 nonzero
= GET_MODE_MASK (mode
);
7664 mode_width
= GET_MODE_BITSIZE (mode
);
7667 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7668 /* Our only callers in this case look for single bit values. So
7669 just return the mode mask. Those tests will then be false. */
7672 #ifndef WORD_REGISTER_OPERATIONS
7673 /* If MODE is wider than X, but both are a single word for both the host
7674 and target machines, we can compute this from which bits of the
7675 object might be nonzero in its own mode, taking into account the fact
7676 that on many CISC machines, accessing an object in a wider mode
7677 causes the high-order bits to become undefined. So they are
7678 not known to be zero. */
7680 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7681 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7682 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7683 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7685 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7686 nonzero
|= GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
));
7691 code
= GET_CODE (x
);
7695 #ifdef POINTERS_EXTEND_UNSIGNED
7696 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7697 all the bits above ptr_mode are known to be zero. */
7698 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7699 && REGNO_POINTER_FLAG (REGNO (x
)))
7700 nonzero
&= GET_MODE_MASK (ptr_mode
);
7703 #ifdef STACK_BOUNDARY
7704 /* If this is the stack pointer, we may know something about its
7705 alignment. If PUSH_ROUNDING is defined, it is possible for the
7706 stack to be momentarily aligned only to that amount, so we pick
7707 the least alignment. */
7709 /* We can't check for arg_pointer_rtx here, because it is not
7710 guaranteed to have as much alignment as the stack pointer.
7711 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7712 alignment but the argument pointer has only 64 bit alignment. */
7714 if ((x
== frame_pointer_rtx
7715 || x
== stack_pointer_rtx
7716 || x
== hard_frame_pointer_rtx
7717 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7718 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7724 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7726 #ifdef PUSH_ROUNDING
7727 if (REGNO (x
) == STACK_POINTER_REGNUM
)
7728 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7731 /* We must return here, otherwise we may get a worse result from
7732 one of the choices below. There is nothing useful below as
7733 far as the stack pointer is concerned. */
7734 return nonzero
&= ~ (sp_alignment
- 1);
7738 /* If X is a register whose nonzero bits value is current, use it.
7739 Otherwise, if X is a register whose value we can find, use that
7740 value. Otherwise, use the previously-computed global nonzero bits
7741 for this register. */
7743 if (reg_last_set_value
[REGNO (x
)] != 0
7744 && reg_last_set_mode
[REGNO (x
)] == mode
7745 && (reg_last_set_label
[REGNO (x
)] == label_tick
7746 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7747 && REG_N_SETS (REGNO (x
)) == 1
7748 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7750 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7751 return reg_last_set_nonzero_bits
[REGNO (x
)];
7753 tem
= get_last_value (x
);
7757 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7758 /* If X is narrower than MODE and TEM is a non-negative
7759 constant that would appear negative in the mode of X,
7760 sign-extend it for use in reg_nonzero_bits because some
7761 machines (maybe most) will actually do the sign-extension
7762 and this is the conservative approach.
7764 ??? For 2.5, try to tighten up the MD files in this regard
7765 instead of this kludge. */
7767 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7768 && GET_CODE (tem
) == CONST_INT
7770 && 0 != (INTVAL (tem
)
7771 & ((HOST_WIDE_INT
) 1
7772 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7773 tem
= GEN_INT (INTVAL (tem
)
7774 | ((HOST_WIDE_INT
) (-1)
7775 << GET_MODE_BITSIZE (GET_MODE (x
))));
7777 return nonzero_bits (tem
, mode
);
7779 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7780 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7785 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7786 /* If X is negative in MODE, sign-extend the value. */
7787 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7788 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7789 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7795 #ifdef LOAD_EXTEND_OP
7796 /* In many, if not most, RISC machines, reading a byte from memory
7797 zeros the rest of the register. Noticing that fact saves a lot
7798 of extra zero-extends. */
7799 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7800 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7810 /* If this produces an integer result, we know which bits are set.
7811 Code here used to clear bits outside the mode of X, but that is
7814 if (GET_MODE_CLASS (mode
) == MODE_INT
7815 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7816 nonzero
= STORE_FLAG_VALUE
;
7821 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7822 and num_sign_bit_copies. */
7823 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7824 == GET_MODE_BITSIZE (GET_MODE (x
)))
7828 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
7829 nonzero
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
7834 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7835 and num_sign_bit_copies. */
7836 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7837 == GET_MODE_BITSIZE (GET_MODE (x
)))
7843 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
7847 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
7848 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7849 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7853 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7854 Otherwise, show all the bits in the outer mode but not the inner
7856 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
7857 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
7859 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
7861 & (((HOST_WIDE_INT
) 1
7862 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
7863 inner_nz
|= (GET_MODE_MASK (mode
)
7864 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
7867 nonzero
&= inner_nz
;
7871 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7872 & nonzero_bits (XEXP (x
, 1), mode
));
7876 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
7877 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
7878 | nonzero_bits (XEXP (x
, 1), mode
));
7881 case PLUS
: case MINUS
:
7883 case DIV
: case UDIV
:
7884 case MOD
: case UMOD
:
7885 /* We can apply the rules of arithmetic to compute the number of
7886 high- and low-order zero bits of these operations. We start by
7887 computing the width (position of the highest-order non-zero bit)
7888 and the number of low-order zero bits for each value. */
7890 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
7891 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
7892 int width0
= floor_log2 (nz0
) + 1;
7893 int width1
= floor_log2 (nz1
) + 1;
7894 int low0
= floor_log2 (nz0
& -nz0
);
7895 int low1
= floor_log2 (nz1
& -nz1
);
7896 HOST_WIDE_INT op0_maybe_minusp
7897 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7898 HOST_WIDE_INT op1_maybe_minusp
7899 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
7900 int result_width
= mode_width
;
7908 && (XEXP (x
, 0) == stack_pointer_rtx
7909 || XEXP (x
, 0) == frame_pointer_rtx
)
7910 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7912 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7914 nz0
= (GET_MODE_MASK (mode
) & ~ (sp_alignment
- 1));
7915 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
7916 width0
= floor_log2 (nz0
) + 1;
7917 width1
= floor_log2 (nz1
) + 1;
7918 low0
= floor_log2 (nz0
& -nz0
);
7919 low1
= floor_log2 (nz1
& -nz1
);
7922 result_width
= MAX (width0
, width1
) + 1;
7923 result_low
= MIN (low0
, low1
);
7926 result_low
= MIN (low0
, low1
);
7929 result_width
= width0
+ width1
;
7930 result_low
= low0
+ low1
;
7933 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7934 result_width
= width0
;
7937 result_width
= width0
;
7940 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
7941 result_width
= MIN (width0
, width1
);
7942 result_low
= MIN (low0
, low1
);
7945 result_width
= MIN (width0
, width1
);
7946 result_low
= MIN (low0
, low1
);
7952 if (result_width
< mode_width
)
7953 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
7956 nonzero
&= ~ (((HOST_WIDE_INT
) 1 << result_low
) - 1);
7961 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7962 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7963 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
7967 /* If this is a SUBREG formed for a promoted variable that has
7968 been zero-extended, we know that at least the high-order bits
7969 are zero, though others might be too. */
7971 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
7972 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
7973 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
7975 /* If the inner mode is a single word for both the host and target
7976 machines, we can compute this from which bits of the inner
7977 object might be nonzero. */
7978 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
7979 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
7980 <= HOST_BITS_PER_WIDE_INT
))
7982 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
7984 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7985 /* If this is a typical RISC machine, we only have to worry
7986 about the way loads are extended. */
7987 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
7989 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1)))
7990 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
7993 /* On many CISC machines, accessing an object in a wider mode
7994 causes the high-order bits to become undefined. So they are
7995 not known to be zero. */
7996 if (GET_MODE_SIZE (GET_MODE (x
))
7997 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7998 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
7999 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8008 /* The nonzero bits are in two classes: any bits within MODE
8009 that aren't in GET_MODE (x) are always significant. The rest of the
8010 nonzero bits are those that are significant in the operand of
8011 the shift when shifted the appropriate number of bits. This
8012 shows that high-order bits are cleared by the right shift and
8013 low-order bits by left shifts. */
8014 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8015 && INTVAL (XEXP (x
, 1)) >= 0
8016 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8018 enum machine_mode inner_mode
= GET_MODE (x
);
8019 int width
= GET_MODE_BITSIZE (inner_mode
);
8020 int count
= INTVAL (XEXP (x
, 1));
8021 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8022 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8023 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8024 unsigned HOST_WIDE_INT outer
= 0;
8026 if (mode_width
> width
)
8027 outer
= (op_nonzero
& nonzero
& ~ mode_mask
);
8029 if (code
== LSHIFTRT
)
8031 else if (code
== ASHIFTRT
)
8035 /* If the sign bit may have been nonzero before the shift, we
8036 need to mark all the places it could have been copied to
8037 by the shift as possibly nonzero. */
8038 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8039 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8041 else if (code
== ASHIFT
)
8044 inner
= ((inner
<< (count
% width
)
8045 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8047 nonzero
&= (outer
| inner
);
8052 /* This is at most the number of bits in the mode. */
8053 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8057 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8058 | nonzero_bits (XEXP (x
, 2), mode
));
8068 /* See the macro definition above. */
8069 #undef num_sign_bit_copies
8071 /* Return the number of bits at the high-order end of X that are known to
8072 be equal to the sign bit. X will be used in mode MODE; if MODE is
8073 VOIDmode, X will be used in its own mode. The returned value will always
8074 be between 1 and the number of bits in MODE. */
8077 num_sign_bit_copies (x
, mode
)
8079 enum machine_mode mode
;
8081 enum rtx_code code
= GET_CODE (x
);
8083 int num0
, num1
, result
;
8084 unsigned HOST_WIDE_INT nonzero
;
8087 /* If we weren't given a mode, use the mode of X. If the mode is still
8088 VOIDmode, we don't know anything. Likewise if one of the modes is
8091 if (mode
== VOIDmode
)
8092 mode
= GET_MODE (x
);
8094 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8097 bitwidth
= GET_MODE_BITSIZE (mode
);
8099 /* For a smaller object, just ignore the high bits. */
8100 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8101 return MAX (1, (num_sign_bit_copies (x
, GET_MODE (x
))
8102 - (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
)));
8104 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8106 #ifndef WORD_REGISTER_OPERATIONS
8107 /* If this machine does not do all register operations on the entire
8108 register and MODE is wider than the mode of X, we can say nothing
8109 at all about the high-order bits. */
8112 /* Likewise on machines that do, if the mode of the object is smaller
8113 than a word and loads of that size don't sign extend, we can say
8114 nothing about the high order bits. */
8115 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8116 #ifdef LOAD_EXTEND_OP
8117 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8128 #ifdef POINTERS_EXTEND_UNSIGNED
8129 /* If pointers extend signed and this is a pointer in Pmode, say that
8130 all the bits above ptr_mode are known to be sign bit copies. */
8131 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8132 && REGNO_POINTER_FLAG (REGNO (x
)))
8133 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8136 if (reg_last_set_value
[REGNO (x
)] != 0
8137 && reg_last_set_mode
[REGNO (x
)] == mode
8138 && (reg_last_set_label
[REGNO (x
)] == label_tick
8139 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8140 && REG_N_SETS (REGNO (x
)) == 1
8141 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8143 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8144 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8146 tem
= get_last_value (x
);
8148 return num_sign_bit_copies (tem
, mode
);
8150 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8151 return reg_sign_bit_copies
[REGNO (x
)];
8155 #ifdef LOAD_EXTEND_OP
8156 /* Some RISC machines sign-extend all loads of smaller than a word. */
8157 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8158 return MAX (1, bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1);
8163 /* If the constant is negative, take its 1's complement and remask.
8164 Then see how many zero bits we have. */
8165 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8166 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8167 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8168 nonzero
= (~ nonzero
) & GET_MODE_MASK (mode
);
8170 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8173 /* If this is a SUBREG for a promoted object that is sign-extended
8174 and we are looking at it in a wider mode, we know that at least the
8175 high-order bits are known to be sign bit copies. */
8177 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8178 return MAX (bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8179 num_sign_bit_copies (SUBREG_REG (x
), mode
));
8181 /* For a smaller object, just ignore the high bits. */
8182 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8184 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8185 return MAX (1, (num0
8186 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8190 #ifdef WORD_REGISTER_OPERATIONS
8191 #ifdef LOAD_EXTEND_OP
8192 /* For paradoxical SUBREGs on machines where all register operations
8193 affect the entire register, just look inside. Note that we are
8194 passing MODE to the recursive call, so the number of sign bit copies
8195 will remain relative to that mode, not the inner mode. */
8197 /* This works only if loads sign extend. Otherwise, if we get a
8198 reload for the inner part, it may be loaded from the stack, and
8199 then we lose all sign bit copies that existed before the store
8202 if ((GET_MODE_SIZE (GET_MODE (x
))
8203 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8204 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8205 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8211 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8212 return MAX (1, bitwidth
- INTVAL (XEXP (x
, 1)));
8216 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8217 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8220 /* For a smaller object, just ignore the high bits. */
8221 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8222 return MAX (1, (num0
- (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8226 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8228 case ROTATE
: case ROTATERT
:
8229 /* If we are rotating left by a number of bits less than the number
8230 of sign bit copies, we can just subtract that amount from the
8232 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8233 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8235 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8236 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8237 : bitwidth
- INTVAL (XEXP (x
, 1))));
8242 /* In general, this subtracts one sign bit copy. But if the value
8243 is known to be positive, the number of sign bit copies is the
8244 same as that of the input. Finally, if the input has just one bit
8245 that might be nonzero, all the bits are copies of the sign bit. */
8246 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8247 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8248 return num0
> 1 ? num0
- 1 : 1;
8250 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8255 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8260 case IOR
: case AND
: case XOR
:
8261 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8262 /* Logical operations will preserve the number of sign-bit copies.
8263 MIN and MAX operations always return one of the operands. */
8264 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8265 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8266 return MIN (num0
, num1
);
8268 case PLUS
: case MINUS
:
8269 /* For addition and subtraction, we can have a 1-bit carry. However,
8270 if we are subtracting 1 from a positive number, there will not
8271 be such a carry. Furthermore, if the positive number is known to
8272 be 0 or 1, we know the result is either -1 or 0. */
8274 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8275 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8277 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8278 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8279 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8280 : bitwidth
- floor_log2 (nonzero
) - 1);
8283 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8284 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8285 return MAX (1, MIN (num0
, num1
) - 1);
8288 /* The number of bits of the product is the sum of the number of
8289 bits of both terms. However, unless one of the terms if known
8290 to be positive, we must allow for an additional bit since negating
8291 a negative number can remove one sign bit copy. */
8293 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8294 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8296 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8298 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8299 || (((nonzero_bits (XEXP (x
, 0), mode
)
8300 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8301 && ((nonzero_bits (XEXP (x
, 1), mode
)
8302 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8305 return MAX (1, result
);
8308 /* The result must be <= the first operand. If the first operand
8309 has the high bit set, we know nothing about the number of sign
8311 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8313 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8314 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8317 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8320 /* The result must be <= the scond operand. */
8321 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8324 /* Similar to unsigned division, except that we have to worry about
8325 the case where the divisor is negative, in which case we have
8327 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8329 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8330 || (nonzero_bits (XEXP (x
, 1), mode
)
8331 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8337 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8339 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8340 || (nonzero_bits (XEXP (x
, 1), mode
)
8341 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8347 /* Shifts by a constant add to the number of bits equal to the
8349 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8350 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8351 && INTVAL (XEXP (x
, 1)) > 0)
8352 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8357 /* Left shifts destroy copies. */
8358 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8359 || INTVAL (XEXP (x
, 1)) < 0
8360 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8363 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8364 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8367 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8368 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8369 return MIN (num0
, num1
);
8371 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8372 case GEU
: case GTU
: case LEU
: case LTU
:
8373 if (STORE_FLAG_VALUE
== -1)
8381 /* If we haven't been able to figure it out by one of the above rules,
8382 see if some of the high-order bits are known to be zero. If so,
8383 count those bits and return one less than that amount. If we can't
8384 safely compute the mask for this mode, always return BITWIDTH. */
8386 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8389 nonzero
= nonzero_bits (x
, mode
);
8390 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8391 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8394 /* Return the number of "extended" bits there are in X, when interpreted
8395 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8396 unsigned quantities, this is the number of high-order zero bits.
8397 For signed quantities, this is the number of copies of the sign bit
8398 minus 1. In both case, this function returns the number of "spare"
8399 bits. For example, if two quantities for which this function returns
8400 at least 1 are added, the addition is known not to overflow.
8402 This function will always return 0 unless called during combine, which
8403 implies that it must be called from a define_split. */
8406 extended_count (x
, mode
, unsignedp
)
8408 enum machine_mode mode
;
8411 if (nonzero_sign_valid
== 0)
8415 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8416 && (GET_MODE_BITSIZE (mode
) - 1
8417 - floor_log2 (nonzero_bits (x
, mode
))))
8418 : num_sign_bit_copies (x
, mode
) - 1);
8421 /* This function is called from `simplify_shift_const' to merge two
8422 outer operations. Specifically, we have already found that we need
8423 to perform operation *POP0 with constant *PCONST0 at the outermost
8424 position. We would now like to also perform OP1 with constant CONST1
8425 (with *POP0 being done last).
8427 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8428 the resulting operation. *PCOMP_P is set to 1 if we would need to
8429 complement the innermost operand, otherwise it is unchanged.
8431 MODE is the mode in which the operation will be done. No bits outside
8432 the width of this mode matter. It is assumed that the width of this mode
8433 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8435 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8436 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8437 result is simply *PCONST0.
8439 If the resulting operation cannot be expressed as one operation, we
8440 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8443 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8444 enum rtx_code
*pop0
;
8445 HOST_WIDE_INT
*pconst0
;
8447 HOST_WIDE_INT const1
;
8448 enum machine_mode mode
;
8451 enum rtx_code op0
= *pop0
;
8452 HOST_WIDE_INT const0
= *pconst0
;
8454 const0
&= GET_MODE_MASK (mode
);
8455 const1
&= GET_MODE_MASK (mode
);
8457 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8461 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8464 if (op1
== NIL
|| op0
== SET
)
8467 else if (op0
== NIL
)
8468 op0
= op1
, const0
= const1
;
8470 else if (op0
== op1
)
8494 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8495 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8498 /* If the two constants aren't the same, we can't do anything. The
8499 remaining six cases can all be done. */
8500 else if (const0
!= const1
)
8508 /* (a & b) | b == b */
8510 else /* op1 == XOR */
8511 /* (a ^ b) | b == a | b */
8517 /* (a & b) ^ b == (~a) & b */
8518 op0
= AND
, *pcomp_p
= 1;
8519 else /* op1 == IOR */
8520 /* (a | b) ^ b == a & ~b */
8521 op0
= AND
, *pconst0
= ~ const0
;
8526 /* (a | b) & b == b */
8528 else /* op1 == XOR */
8529 /* (a ^ b) & b) == (~a) & b */
8536 /* Check for NO-OP cases. */
8537 const0
&= GET_MODE_MASK (mode
);
8539 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8541 else if (const0
== 0 && op0
== AND
)
8543 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8547 /* ??? Slightly redundant with the above mask, but not entirely.
8548 Moving this above means we'd have to sign-extend the mode mask
8549 for the final test. */
8550 const0
= trunc_int_for_mode (const0
, mode
);
8558 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8559 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8560 that we started with.
8562 The shift is normally computed in the widest mode we find in VAROP, as
8563 long as it isn't a different number of words than RESULT_MODE. Exceptions
8564 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8567 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
8570 enum machine_mode result_mode
;
8574 enum rtx_code orig_code
= code
;
8575 int orig_count
= count
;
8576 enum machine_mode mode
= result_mode
;
8577 enum machine_mode shift_mode
, tmode
;
8579 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8580 /* We form (outer_op (code varop count) (outer_const)). */
8581 enum rtx_code outer_op
= NIL
;
8582 HOST_WIDE_INT outer_const
= 0;
8584 int complement_p
= 0;
8587 /* If we were given an invalid count, don't do anything except exactly
8588 what was requested. */
8590 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
8595 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (count
));
8598 /* Unless one of the branches of the `if' in this loop does a `continue',
8599 we will `break' the loop after the `if'. */
8603 /* If we have an operand of (clobber (const_int 0)), just return that
8605 if (GET_CODE (varop
) == CLOBBER
)
8608 /* If we discovered we had to complement VAROP, leave. Making a NOT
8609 here would cause an infinite loop. */
8613 /* Convert ROTATERT to ROTATE. */
8614 if (code
== ROTATERT
)
8615 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8617 /* We need to determine what mode we will do the shift in. If the
8618 shift is a right shift or a ROTATE, we must always do it in the mode
8619 it was originally done in. Otherwise, we can do it in MODE, the
8620 widest mode encountered. */
8622 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8623 ? result_mode
: mode
);
8625 /* Handle cases where the count is greater than the size of the mode
8626 minus 1. For ASHIFT, use the size minus one as the count (this can
8627 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8628 take the count modulo the size. For other shifts, the result is
8631 Since these shifts are being produced by the compiler by combining
8632 multiple operations, each of which are defined, we know what the
8633 result is supposed to be. */
8635 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8637 if (code
== ASHIFTRT
)
8638 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8639 else if (code
== ROTATE
|| code
== ROTATERT
)
8640 count
%= GET_MODE_BITSIZE (shift_mode
);
8643 /* We can't simply return zero because there may be an
8651 /* Negative counts are invalid and should not have been made (a
8652 programmer-specified negative count should have been handled
8657 /* An arithmetic right shift of a quantity known to be -1 or 0
8659 if (code
== ASHIFTRT
8660 && (num_sign_bit_copies (varop
, shift_mode
)
8661 == GET_MODE_BITSIZE (shift_mode
)))
8667 /* If we are doing an arithmetic right shift and discarding all but
8668 the sign bit copies, this is equivalent to doing a shift by the
8669 bitsize minus one. Convert it into that shift because it will often
8670 allow other simplifications. */
8672 if (code
== ASHIFTRT
8673 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8674 >= GET_MODE_BITSIZE (shift_mode
)))
8675 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8677 /* We simplify the tests below and elsewhere by converting
8678 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8679 `make_compound_operation' will convert it to a ASHIFTRT for
8680 those machines (such as Vax) that don't have a LSHIFTRT. */
8681 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8683 && ((nonzero_bits (varop
, shift_mode
)
8684 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8688 switch (GET_CODE (varop
))
8694 new = expand_compound_operation (varop
);
8703 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8704 minus the width of a smaller mode, we can do this with a
8705 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8706 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8707 && ! mode_dependent_address_p (XEXP (varop
, 0))
8708 && ! MEM_VOLATILE_P (varop
)
8709 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8710 MODE_INT
, 1)) != BLKmode
)
8712 if (BYTES_BIG_ENDIAN
)
8713 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
8715 new = gen_rtx_MEM (tmode
,
8716 plus_constant (XEXP (varop
, 0),
8717 count
/ BITS_PER_UNIT
));
8718 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
8719 MEM_COPY_ATTRIBUTES (new, varop
);
8720 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8721 : ZERO_EXTEND
, mode
, new);
8728 /* Similar to the case above, except that we can only do this if
8729 the resulting mode is the same as that of the underlying
8730 MEM and adjust the address depending on the *bits* endianness
8731 because of the way that bit-field extract insns are defined. */
8732 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8733 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8734 MODE_INT
, 1)) != BLKmode
8735 && tmode
== GET_MODE (XEXP (varop
, 0)))
8737 if (BITS_BIG_ENDIAN
)
8738 new = XEXP (varop
, 0);
8741 new = copy_rtx (XEXP (varop
, 0));
8742 SUBST (XEXP (new, 0),
8743 plus_constant (XEXP (new, 0),
8744 count
/ BITS_PER_UNIT
));
8747 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8748 : ZERO_EXTEND
, mode
, new);
8755 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8756 the same number of words as what we've seen so far. Then store
8757 the widest mode in MODE. */
8758 if (subreg_lowpart_p (varop
)
8759 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8760 > GET_MODE_SIZE (GET_MODE (varop
)))
8761 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8762 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8765 varop
= SUBREG_REG (varop
);
8766 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8767 mode
= GET_MODE (varop
);
8773 /* Some machines use MULT instead of ASHIFT because MULT
8774 is cheaper. But it is still better on those machines to
8775 merge two shifts into one. */
8776 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8777 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8779 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8780 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8786 /* Similar, for when divides are cheaper. */
8787 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8788 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8790 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8791 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8797 /* If we are extracting just the sign bit of an arithmetic right
8798 shift, that shift is not needed. */
8799 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
8801 varop
= XEXP (varop
, 0);
8805 /* ... fall through ... */
8810 /* Here we have two nested shifts. The result is usually the
8811 AND of a new shift with a mask. We compute the result below. */
8812 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8813 && INTVAL (XEXP (varop
, 1)) >= 0
8814 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8815 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8816 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8818 enum rtx_code first_code
= GET_CODE (varop
);
8819 int first_count
= INTVAL (XEXP (varop
, 1));
8820 unsigned HOST_WIDE_INT mask
;
8823 /* We have one common special case. We can't do any merging if
8824 the inner code is an ASHIFTRT of a smaller mode. However, if
8825 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8826 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8827 we can convert it to
8828 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8829 This simplifies certain SIGN_EXTEND operations. */
8830 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8831 && (GET_MODE_BITSIZE (result_mode
)
8832 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
8834 /* C3 has the low-order C1 bits zero. */
8836 mask
= (GET_MODE_MASK (mode
)
8837 & ~ (((HOST_WIDE_INT
) 1 << first_count
) - 1));
8839 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8840 XEXP (varop
, 0), mask
);
8841 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8843 count
= first_count
;
8848 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8849 than C1 high-order bits equal to the sign bit, we can convert
8850 this to either an ASHIFT or a ASHIFTRT depending on the
8853 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8855 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8856 && GET_MODE (varop
) == shift_mode
8857 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8860 count
-= first_count
;
8862 count
= - count
, code
= ASHIFT
;
8863 varop
= XEXP (varop
, 0);
8867 /* There are some cases we can't do. If CODE is ASHIFTRT,
8868 we can only do this if FIRST_CODE is also ASHIFTRT.
8870 We can't do the case when CODE is ROTATE and FIRST_CODE is
8873 If the mode of this shift is not the mode of the outer shift,
8874 we can't do this if either shift is a right shift or ROTATE.
8876 Finally, we can't do any of these if the mode is too wide
8877 unless the codes are the same.
8879 Handle the case where the shift codes are the same
8882 if (code
== first_code
)
8884 if (GET_MODE (varop
) != result_mode
8885 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8889 count
+= first_count
;
8890 varop
= XEXP (varop
, 0);
8894 if (code
== ASHIFTRT
8895 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8896 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8897 || (GET_MODE (varop
) != result_mode
8898 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8899 || first_code
== ROTATE
8900 || code
== ROTATE
)))
8903 /* To compute the mask to apply after the shift, shift the
8904 nonzero bits of the inner shift the same way the
8905 outer shift will. */
8907 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8910 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8913 /* Give up if we can't compute an outer operation to use. */
8915 || GET_CODE (mask_rtx
) != CONST_INT
8916 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8918 result_mode
, &complement_p
))
8921 /* If the shifts are in the same direction, we add the
8922 counts. Otherwise, we subtract them. */
8923 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8924 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8925 count
+= first_count
;
8927 count
-= first_count
;
8929 /* If COUNT is positive, the new shift is usually CODE,
8930 except for the two exceptions below, in which case it is
8931 FIRST_CODE. If the count is negative, FIRST_CODE should
8934 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8935 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8938 code
= first_code
, count
= - count
;
8940 varop
= XEXP (varop
, 0);
8944 /* If we have (A << B << C) for any shift, we can convert this to
8945 (A << C << B). This wins if A is a constant. Only try this if
8946 B is not a constant. */
8948 else if (GET_CODE (varop
) == code
8949 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8951 = simplify_binary_operation (code
, mode
,
8955 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
8962 /* Make this fit the case below. */
8963 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
8964 GEN_INT (GET_MODE_MASK (mode
)));
8970 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8971 with C the size of VAROP - 1 and the shift is logical if
8972 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8973 we have an (le X 0) operation. If we have an arithmetic shift
8974 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8975 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8977 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8978 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8979 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8980 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8981 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
8982 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8985 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
8988 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8989 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
8994 /* If we have (shift (logical)), move the logical to the outside
8995 to allow it to possibly combine with another logical and the
8996 shift to combine with another shift. This also canonicalizes to
8997 what a ZERO_EXTRACT looks like. Also, some machines have
8998 (and (shift)) insns. */
9000 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9001 && (new = simplify_binary_operation (code
, result_mode
,
9003 GEN_INT (count
))) != 0
9004 && GET_CODE(new) == CONST_INT
9005 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9006 INTVAL (new), result_mode
, &complement_p
))
9008 varop
= XEXP (varop
, 0);
9012 /* If we can't do that, try to simplify the shift in each arm of the
9013 logical expression, make a new logical expression, and apply
9014 the inverse distributive law. */
9016 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9017 XEXP (varop
, 0), count
);
9018 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9019 XEXP (varop
, 1), count
);
9021 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9022 varop
= apply_distributive_law (varop
);
9029 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9030 says that the sign bit can be tested, FOO has mode MODE, C is
9031 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9032 that may be nonzero. */
9033 if (code
== LSHIFTRT
9034 && XEXP (varop
, 1) == const0_rtx
9035 && GET_MODE (XEXP (varop
, 0)) == result_mode
9036 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9037 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9038 && ((STORE_FLAG_VALUE
9039 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
9040 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9041 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9042 (HOST_WIDE_INT
) 1, result_mode
,
9045 varop
= XEXP (varop
, 0);
9052 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9053 than the number of bits in the mode is equivalent to A. */
9054 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9055 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9057 varop
= XEXP (varop
, 0);
9062 /* NEG commutes with ASHIFT since it is multiplication. Move the
9063 NEG outside to allow shifts to combine. */
9065 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9066 (HOST_WIDE_INT
) 0, result_mode
,
9069 varop
= XEXP (varop
, 0);
9075 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9076 is one less than the number of bits in the mode is
9077 equivalent to (xor A 1). */
9078 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9079 && XEXP (varop
, 1) == constm1_rtx
9080 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9081 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9082 (HOST_WIDE_INT
) 1, result_mode
,
9086 varop
= XEXP (varop
, 0);
9090 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9091 that might be nonzero in BAR are those being shifted out and those
9092 bits are known zero in FOO, we can replace the PLUS with FOO.
9093 Similarly in the other operand order. This code occurs when
9094 we are computing the size of a variable-size array. */
9096 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9097 && count
< HOST_BITS_PER_WIDE_INT
9098 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9099 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9100 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9102 varop
= XEXP (varop
, 0);
9105 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9106 && count
< HOST_BITS_PER_WIDE_INT
9107 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9108 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9110 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9111 & nonzero_bits (XEXP (varop
, 1),
9114 varop
= XEXP (varop
, 1);
9118 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9120 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9121 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9123 GEN_INT (count
))) != 0
9124 && GET_CODE(new) == CONST_INT
9125 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9126 INTVAL (new), result_mode
, &complement_p
))
9128 varop
= XEXP (varop
, 0);
9134 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9135 with C the size of VAROP - 1 and the shift is logical if
9136 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9137 we have a (gt X 0) operation. If the shift is arithmetic with
9138 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9139 we have a (neg (gt X 0)) operation. */
9141 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9142 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9143 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9144 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9145 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9146 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9147 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9150 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9153 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9154 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9161 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9162 if the truncate does not affect the value. */
9163 if (code
== LSHIFTRT
9164 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9165 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9166 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9167 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9168 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9170 rtx varop_inner
= XEXP (varop
, 0);
9172 varop_inner
= gen_rtx_combine (LSHIFTRT
,
9173 GET_MODE (varop_inner
),
9174 XEXP (varop_inner
, 0),
9175 GEN_INT (count
+ INTVAL (XEXP (varop_inner
, 1))));
9176 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9190 /* We need to determine what mode to do the shift in. If the shift is
9191 a right shift or ROTATE, we must always do it in the mode it was
9192 originally done in. Otherwise, we can do it in MODE, the widest mode
9193 encountered. The code we care about is that of the shift that will
9194 actually be done, not the shift that was originally requested. */
9196 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9197 ? result_mode
: mode
);
9199 /* We have now finished analyzing the shift. The result should be
9200 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9201 OUTER_OP is non-NIL, it is an operation that needs to be applied
9202 to the result of the shift. OUTER_CONST is the relevant constant,
9203 but we must turn off all bits turned off in the shift.
9205 If we were passed a value for X, see if we can use any pieces of
9206 it. If not, make new rtx. */
9208 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9209 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9210 && INTVAL (XEXP (x
, 1)) == count
)
9211 const_rtx
= XEXP (x
, 1);
9213 const_rtx
= GEN_INT (count
);
9215 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9216 && GET_MODE (XEXP (x
, 0)) == shift_mode
9217 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9218 varop
= XEXP (x
, 0);
9219 else if (GET_MODE (varop
) != shift_mode
)
9220 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9222 /* If we can't make the SUBREG, try to return what we were given. */
9223 if (GET_CODE (varop
) == CLOBBER
)
9224 return x
? x
: varop
;
9226 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9231 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9232 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9234 SUBST (XEXP (x
, 0), varop
);
9235 SUBST (XEXP (x
, 1), const_rtx
);
9238 /* If we have an outer operation and we just made a shift, it is
9239 possible that we could have simplified the shift were it not
9240 for the outer operation. So try to do the simplification
9243 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9244 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9245 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9246 INTVAL (XEXP (x
, 1)));
9248 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9249 turn off all the bits that the shift would have turned off. */
9250 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9251 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9252 GET_MODE_MASK (result_mode
) >> orig_count
);
9254 /* Do the remainder of the processing in RESULT_MODE. */
9255 x
= gen_lowpart_for_combine (result_mode
, x
);
9257 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9260 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9262 if (outer_op
!= NIL
)
9264 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9265 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9267 if (outer_op
== AND
)
9268 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9269 else if (outer_op
== SET
)
9270 /* This means that we have determined that the result is
9271 equivalent to a constant. This should be rare. */
9272 x
= GEN_INT (outer_const
);
9273 else if (GET_RTX_CLASS (outer_op
) == '1')
9274 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9276 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9282 /* Like recog, but we receive the address of a pointer to a new pattern.
9283 We try to match the rtx that the pointer points to.
9284 If that fails, we may try to modify or replace the pattern,
9285 storing the replacement into the same pointer object.
9287 Modifications include deletion or addition of CLOBBERs.
9289 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9290 the CLOBBERs are placed.
9292 The value is the final insn code from the pattern ultimately matched,
9296 recog_for_combine (pnewpat
, insn
, pnotes
)
9301 register rtx pat
= *pnewpat
;
9302 int insn_code_number
;
9303 int num_clobbers_to_add
= 0;
9307 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9308 we use to indicate that something didn't match. If we find such a
9309 thing, force rejection. */
9310 if (GET_CODE (pat
) == PARALLEL
)
9311 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9312 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9313 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9316 /* Is the result of combination a valid instruction? */
9317 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9319 /* If it isn't, there is the possibility that we previously had an insn
9320 that clobbered some register as a side effect, but the combined
9321 insn doesn't need to do that. So try once more without the clobbers
9322 unless this represents an ASM insn. */
9324 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9325 && GET_CODE (pat
) == PARALLEL
)
9329 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9330 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9333 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9337 SUBST_INT (XVECLEN (pat
, 0), pos
);
9340 pat
= XVECEXP (pat
, 0, 0);
9342 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9345 /* If we had any clobbers to add, make a new pattern than contains
9346 them. Then check to make sure that all of them are dead. */
9347 if (num_clobbers_to_add
)
9349 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9350 gen_rtvec (GET_CODE (pat
) == PARALLEL
9352 + num_clobbers_to_add
)
9353 : num_clobbers_to_add
+ 1));
9355 if (GET_CODE (pat
) == PARALLEL
)
9356 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9357 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9359 XVECEXP (newpat
, 0, 0) = pat
;
9361 add_clobbers (newpat
, insn_code_number
);
9363 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9364 i
< XVECLEN (newpat
, 0); i
++)
9366 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9367 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9369 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9370 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9378 return insn_code_number
;
9381 /* Like gen_lowpart but for use by combine. In combine it is not possible
9382 to create any new pseudoregs. However, it is safe to create
9383 invalid memory addresses, because combine will try to recognize
9384 them and all they will do is make the combine attempt fail.
9386 If for some reason this cannot do its job, an rtx
9387 (clobber (const_int 0)) is returned.
9388 An insn containing that will not be recognized. */
9393 gen_lowpart_for_combine (mode
, x
)
9394 enum machine_mode mode
;
9399 if (GET_MODE (x
) == mode
)
9402 /* We can only support MODE being wider than a word if X is a
9403 constant integer or has a mode the same size. */
9405 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9406 && ! ((GET_MODE (x
) == VOIDmode
9407 && (GET_CODE (x
) == CONST_INT
9408 || GET_CODE (x
) == CONST_DOUBLE
))
9409 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9410 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9412 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9413 won't know what to do. So we will strip off the SUBREG here and
9414 process normally. */
9415 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9418 if (GET_MODE (x
) == mode
)
9422 result
= gen_lowpart_common (mode
, x
);
9424 && GET_CODE (result
) == SUBREG
9425 && GET_CODE (SUBREG_REG (result
)) == REG
9426 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9427 && (GET_MODE_SIZE (GET_MODE (result
))
9428 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result
)))))
9429 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result
))) = 1;
9434 if (GET_CODE (x
) == MEM
)
9436 register int offset
= 0;
9439 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9441 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9442 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9444 /* If we want to refer to something bigger than the original memref,
9445 generate a perverse subreg instead. That will force a reload
9446 of the original memref X. */
9447 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9448 return gen_rtx_SUBREG (mode
, x
, 0);
9450 if (WORDS_BIG_ENDIAN
)
9451 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9452 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9454 if (BYTES_BIG_ENDIAN
)
9456 /* Adjust the address so that the address-after-the-data is
9458 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9459 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9461 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9462 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
9463 MEM_COPY_ATTRIBUTES (new, x
);
9467 /* If X is a comparison operator, rewrite it in a new mode. This
9468 probably won't match, but may allow further simplifications. */
9469 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9470 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9472 /* If we couldn't simplify X any other way, just enclose it in a
9473 SUBREG. Normally, this SUBREG won't match, but some patterns may
9474 include an explicit SUBREG or we may simplify it further in combine. */
9479 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9480 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9481 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9483 return gen_rtx_SUBREG (mode
, x
, word
);
9487 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9488 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9490 If the identical expression was previously in the insn (in the undobuf),
9491 it will be returned. Only if it is not found will a new expression
9496 gen_rtx_combine
VPROTO((enum rtx_code code
, enum machine_mode mode
, ...))
9498 #ifndef ANSI_PROTOTYPES
9500 enum machine_mode mode
;
9512 #ifndef ANSI_PROTOTYPES
9513 code
= va_arg (p
, enum rtx_code
);
9514 mode
= va_arg (p
, enum machine_mode
);
9517 n_args
= GET_RTX_LENGTH (code
);
9518 fmt
= GET_RTX_FORMAT (code
);
9520 if (n_args
== 0 || n_args
> 3)
9523 /* Get each arg and verify that it is supposed to be an expression. */
9524 for (j
= 0; j
< n_args
; j
++)
9529 args
[j
] = va_arg (p
, rtx
);
9534 /* See if this is in undobuf. Be sure we don't use objects that came
9535 from another insn; this could produce circular rtl structures. */
9537 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9539 && GET_CODE (undo
->old_contents
.r
) == code
9540 && GET_MODE (undo
->old_contents
.r
) == mode
)
9542 for (j
= 0; j
< n_args
; j
++)
9543 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9547 return undo
->old_contents
.r
;
9550 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9551 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9552 rt
= rtx_alloc (code
);
9553 PUT_MODE (rt
, mode
);
9554 XEXP (rt
, 0) = args
[0];
9557 XEXP (rt
, 1) = args
[1];
9559 XEXP (rt
, 2) = args
[2];
9564 /* These routines make binary and unary operations by first seeing if they
9565 fold; if not, a new expression is allocated. */
9568 gen_binary (code
, mode
, op0
, op1
)
9570 enum machine_mode mode
;
9576 if (GET_RTX_CLASS (code
) == 'c'
9577 && (GET_CODE (op0
) == CONST_INT
9578 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9579 tem
= op0
, op0
= op1
, op1
= tem
;
9581 if (GET_RTX_CLASS (code
) == '<')
9583 enum machine_mode op_mode
= GET_MODE (op0
);
9585 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9586 just (REL_OP X Y). */
9587 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9589 op1
= XEXP (op0
, 1);
9590 op0
= XEXP (op0
, 0);
9591 op_mode
= GET_MODE (op0
);
9594 if (op_mode
== VOIDmode
)
9595 op_mode
= GET_MODE (op1
);
9596 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9599 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9604 /* Put complex operands first and constants second. */
9605 if (GET_RTX_CLASS (code
) == 'c'
9606 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9607 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9608 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9609 || (GET_CODE (op0
) == SUBREG
9610 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9611 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9612 return gen_rtx_combine (code
, mode
, op1
, op0
);
9614 /* If we are turning off bits already known off in OP0, we need not do
9616 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9617 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9618 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
9621 return gen_rtx_combine (code
, mode
, op0
, op1
);
9625 gen_unary (code
, mode
, op0_mode
, op0
)
9627 enum machine_mode mode
, op0_mode
;
9630 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
9635 return gen_rtx_combine (code
, mode
, op0
);
9638 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9639 comparison code that will be tested.
9641 The result is a possibly different comparison code to use. *POP0 and
9642 *POP1 may be updated.
9644 It is possible that we might detect that a comparison is either always
9645 true or always false. However, we do not perform general constant
9646 folding in combine, so this knowledge isn't useful. Such tautologies
9647 should have been detected earlier. Hence we ignore all such cases. */
9649 static enum rtx_code
9650 simplify_comparison (code
, pop0
, pop1
)
9659 enum machine_mode mode
, tmode
;
9661 /* Try a few ways of applying the same transformation to both operands. */
9664 #ifndef WORD_REGISTER_OPERATIONS
9665 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9666 so check specially. */
9667 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9668 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9669 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9670 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9671 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9672 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9673 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9674 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9675 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9676 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9677 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9678 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9679 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9680 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9681 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9682 && (INTVAL (XEXP (op0
, 1))
9683 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9685 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9687 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9688 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9692 /* If both operands are the same constant shift, see if we can ignore the
9693 shift. We can if the shift is a rotate or if the bits shifted out of
9694 this shift are known to be zero for both inputs and if the type of
9695 comparison is compatible with the shift. */
9696 if (GET_CODE (op0
) == GET_CODE (op1
)
9697 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9698 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9699 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9700 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9701 || (GET_CODE (op0
) == ASHIFTRT
9702 && (code
!= GTU
&& code
!= LTU
9703 && code
!= GEU
&& code
!= GEU
)))
9704 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9705 && INTVAL (XEXP (op0
, 1)) >= 0
9706 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9707 && XEXP (op0
, 1) == XEXP (op1
, 1))
9709 enum machine_mode mode
= GET_MODE (op0
);
9710 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9711 int shift_count
= INTVAL (XEXP (op0
, 1));
9713 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9714 mask
&= (mask
>> shift_count
) << shift_count
;
9715 else if (GET_CODE (op0
) == ASHIFT
)
9716 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9718 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
9719 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
9720 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9725 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9726 SUBREGs are of the same mode, and, in both cases, the AND would
9727 be redundant if the comparison was done in the narrower mode,
9728 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9729 and the operand's possibly nonzero bits are 0xffffff01; in that case
9730 if we only care about QImode, we don't need the AND). This case
9731 occurs if the output mode of an scc insn is not SImode and
9732 STORE_FLAG_VALUE == 1 (e.g., the 386).
9734 Similarly, check for a case where the AND's are ZERO_EXTEND
9735 operations from some narrower mode even though a SUBREG is not
9738 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9739 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9740 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9742 rtx inner_op0
= XEXP (op0
, 0);
9743 rtx inner_op1
= XEXP (op1
, 0);
9744 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9745 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9748 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9749 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9750 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9751 && (GET_MODE (SUBREG_REG (inner_op0
))
9752 == GET_MODE (SUBREG_REG (inner_op1
)))
9753 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9754 <= HOST_BITS_PER_WIDE_INT
)
9755 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9756 GET_MODE (SUBREG_REG (inner_op0
)))))
9757 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9758 GET_MODE (SUBREG_REG (inner_op1
))))))
9760 op0
= SUBREG_REG (inner_op0
);
9761 op1
= SUBREG_REG (inner_op1
);
9763 /* The resulting comparison is always unsigned since we masked
9764 off the original sign bit. */
9765 code
= unsigned_condition (code
);
9771 for (tmode
= GET_CLASS_NARROWEST_MODE
9772 (GET_MODE_CLASS (GET_MODE (op0
)));
9773 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9774 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9776 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9777 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9778 code
= unsigned_condition (code
);
9787 /* If both operands are NOT, we can strip off the outer operation
9788 and adjust the comparison code for swapped operands; similarly for
9789 NEG, except that this must be an equality comparison. */
9790 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9791 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9792 && (code
== EQ
|| code
== NE
)))
9793 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9799 /* If the first operand is a constant, swap the operands and adjust the
9800 comparison code appropriately, but don't do this if the second operand
9801 is already a constant integer. */
9802 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9804 tem
= op0
, op0
= op1
, op1
= tem
;
9805 code
= swap_condition (code
);
9808 /* We now enter a loop during which we will try to simplify the comparison.
9809 For the most part, we only are concerned with comparisons with zero,
9810 but some things may really be comparisons with zero but not start
9811 out looking that way. */
9813 while (GET_CODE (op1
) == CONST_INT
)
9815 enum machine_mode mode
= GET_MODE (op0
);
9816 int mode_width
= GET_MODE_BITSIZE (mode
);
9817 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9818 int equality_comparison_p
;
9819 int sign_bit_comparison_p
;
9820 int unsigned_comparison_p
;
9821 HOST_WIDE_INT const_op
;
9823 /* We only want to handle integral modes. This catches VOIDmode,
9824 CCmode, and the floating-point modes. An exception is that we
9825 can handle VOIDmode if OP0 is a COMPARE or a comparison
9828 if (GET_MODE_CLASS (mode
) != MODE_INT
9829 && ! (mode
== VOIDmode
9830 && (GET_CODE (op0
) == COMPARE
9831 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
9834 /* Get the constant we are comparing against and turn off all bits
9835 not on in our mode. */
9836 const_op
= INTVAL (op1
);
9837 if (mode_width
<= HOST_BITS_PER_WIDE_INT
)
9840 /* If we are comparing against a constant power of two and the value
9841 being compared can only have that single bit nonzero (e.g., it was
9842 `and'ed with that bit), we can replace this with a comparison
9845 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9846 || code
== LT
|| code
== LTU
)
9847 && mode_width
<= HOST_BITS_PER_WIDE_INT
9848 && exact_log2 (const_op
) >= 0
9849 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9851 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9852 op1
= const0_rtx
, const_op
= 0;
9855 /* Similarly, if we are comparing a value known to be either -1 or
9856 0 with -1, change it to the opposite comparison against zero. */
9859 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9860 || code
== GEU
|| code
== LTU
)
9861 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9863 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9864 op1
= const0_rtx
, const_op
= 0;
9867 /* Do some canonicalizations based on the comparison code. We prefer
9868 comparisons against zero and then prefer equality comparisons.
9869 If we can reduce the size of a constant, we will do that too. */
9874 /* < C is equivalent to <= (C - 1) */
9878 op1
= GEN_INT (const_op
);
9880 /* ... fall through to LE case below. */
9886 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9890 op1
= GEN_INT (const_op
);
9894 /* If we are doing a <= 0 comparison on a value known to have
9895 a zero sign bit, we can replace this with == 0. */
9896 else if (const_op
== 0
9897 && mode_width
<= HOST_BITS_PER_WIDE_INT
9898 && (nonzero_bits (op0
, mode
)
9899 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9904 /* >= C is equivalent to > (C - 1). */
9908 op1
= GEN_INT (const_op
);
9910 /* ... fall through to GT below. */
9916 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9920 op1
= GEN_INT (const_op
);
9924 /* If we are doing a > 0 comparison on a value known to have
9925 a zero sign bit, we can replace this with != 0. */
9926 else if (const_op
== 0
9927 && mode_width
<= HOST_BITS_PER_WIDE_INT
9928 && (nonzero_bits (op0
, mode
)
9929 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9934 /* < C is equivalent to <= (C - 1). */
9938 op1
= GEN_INT (const_op
);
9940 /* ... fall through ... */
9943 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9944 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9945 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9947 const_op
= 0, op1
= const0_rtx
;
9955 /* unsigned <= 0 is equivalent to == 0 */
9959 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9960 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9961 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9963 const_op
= 0, op1
= const0_rtx
;
9969 /* >= C is equivalent to < (C - 1). */
9973 op1
= GEN_INT (const_op
);
9975 /* ... fall through ... */
9978 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9979 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9980 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9982 const_op
= 0, op1
= const0_rtx
;
9990 /* unsigned > 0 is equivalent to != 0 */
9994 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9995 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9996 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9998 const_op
= 0, op1
= const0_rtx
;
10007 /* Compute some predicates to simplify code below. */
10009 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10010 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10011 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10014 /* If this is a sign bit comparison and we can do arithmetic in
10015 MODE, say that we will only be needing the sign bit of OP0. */
10016 if (sign_bit_comparison_p
10017 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10018 op0
= force_to_mode (op0
, mode
,
10020 << (GET_MODE_BITSIZE (mode
) - 1)),
10023 /* Now try cases based on the opcode of OP0. If none of the cases
10024 does a "continue", we exit this loop immediately after the
10027 switch (GET_CODE (op0
))
10030 /* If we are extracting a single bit from a variable position in
10031 a constant that has only a single bit set and are comparing it
10032 with zero, we can convert this into an equality comparison
10033 between the position and the location of the single bit. */
10035 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10036 && XEXP (op0
, 1) == const1_rtx
10037 && equality_comparison_p
&& const_op
== 0
10038 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10040 if (BITS_BIG_ENDIAN
)
10043 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10044 if (mode
== VOIDmode
)
10046 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10048 i
= BITS_PER_WORD
- 1 - i
;
10052 op0
= XEXP (op0
, 2);
10056 /* Result is nonzero iff shift count is equal to I. */
10057 code
= reverse_condition (code
);
10061 /* ... fall through ... */
10064 tem
= expand_compound_operation (op0
);
10073 /* If testing for equality, we can take the NOT of the constant. */
10074 if (equality_comparison_p
10075 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10077 op0
= XEXP (op0
, 0);
10082 /* If just looking at the sign bit, reverse the sense of the
10084 if (sign_bit_comparison_p
)
10086 op0
= XEXP (op0
, 0);
10087 code
= (code
== GE
? LT
: GE
);
10093 /* If testing for equality, we can take the NEG of the constant. */
10094 if (equality_comparison_p
10095 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10097 op0
= XEXP (op0
, 0);
10102 /* The remaining cases only apply to comparisons with zero. */
10106 /* When X is ABS or is known positive,
10107 (neg X) is < 0 if and only if X != 0. */
10109 if (sign_bit_comparison_p
10110 && (GET_CODE (XEXP (op0
, 0)) == ABS
10111 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10112 && (nonzero_bits (XEXP (op0
, 0), mode
)
10113 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10115 op0
= XEXP (op0
, 0);
10116 code
= (code
== LT
? NE
: EQ
);
10120 /* If we have NEG of something whose two high-order bits are the
10121 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10122 if (num_sign_bit_copies (op0
, mode
) >= 2)
10124 op0
= XEXP (op0
, 0);
10125 code
= swap_condition (code
);
10131 /* If we are testing equality and our count is a constant, we
10132 can perform the inverse operation on our RHS. */
10133 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10134 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10135 op1
, XEXP (op0
, 1))) != 0)
10137 op0
= XEXP (op0
, 0);
10142 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10143 a particular bit. Convert it to an AND of a constant of that
10144 bit. This will be converted into a ZERO_EXTRACT. */
10145 if (const_op
== 0 && sign_bit_comparison_p
10146 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10147 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10149 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10152 - INTVAL (XEXP (op0
, 1)))));
10153 code
= (code
== LT
? NE
: EQ
);
10157 /* ... fall through ... */
10160 /* ABS is ignorable inside an equality comparison with zero. */
10161 if (const_op
== 0 && equality_comparison_p
)
10163 op0
= XEXP (op0
, 0);
10170 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10171 to (compare FOO CONST) if CONST fits in FOO's mode and we
10172 are either testing inequality or have an unsigned comparison
10173 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10174 if (! unsigned_comparison_p
10175 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10176 <= HOST_BITS_PER_WIDE_INT
)
10177 && ((unsigned HOST_WIDE_INT
) const_op
10178 < (((unsigned HOST_WIDE_INT
) 1
10179 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10181 op0
= XEXP (op0
, 0);
10187 /* Check for the case where we are comparing A - C1 with C2,
10188 both constants are smaller than 1/2 the maximum positive
10189 value in MODE, and the comparison is equality or unsigned.
10190 In that case, if A is either zero-extended to MODE or has
10191 sufficient sign bits so that the high-order bit in MODE
10192 is a copy of the sign in the inner mode, we can prove that it is
10193 safe to do the operation in the wider mode. This simplifies
10194 many range checks. */
10196 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10197 && subreg_lowpart_p (op0
)
10198 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10199 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10200 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10201 && (- INTVAL (XEXP (SUBREG_REG (op0
), 1))
10202 < (HOST_WIDE_INT
)(GET_MODE_MASK (mode
) / 2))
10203 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10204 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10205 GET_MODE (SUBREG_REG (op0
)))
10206 & ~ GET_MODE_MASK (mode
))
10207 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10208 GET_MODE (SUBREG_REG (op0
)))
10209 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10210 - GET_MODE_BITSIZE (mode
)))))
10212 op0
= SUBREG_REG (op0
);
10216 /* If the inner mode is narrower and we are extracting the low part,
10217 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10218 if (subreg_lowpart_p (op0
)
10219 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10220 /* Fall through */ ;
10224 /* ... fall through ... */
10227 if ((unsigned_comparison_p
|| equality_comparison_p
)
10228 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10229 <= HOST_BITS_PER_WIDE_INT
)
10230 && ((unsigned HOST_WIDE_INT
) const_op
10231 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10233 op0
= XEXP (op0
, 0);
10239 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10240 this for equality comparisons due to pathological cases involving
10242 if (equality_comparison_p
10243 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10244 op1
, XEXP (op0
, 1))))
10246 op0
= XEXP (op0
, 0);
10251 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10252 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10253 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10255 op0
= XEXP (XEXP (op0
, 0), 0);
10256 code
= (code
== LT
? EQ
: NE
);
10262 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10263 (eq B (minus A C)), whichever simplifies. We can only do
10264 this for equality comparisons due to pathological cases involving
10266 if (equality_comparison_p
10267 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10268 XEXP (op0
, 1), op1
)))
10270 op0
= XEXP (op0
, 0);
10275 if (equality_comparison_p
10276 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10277 XEXP (op0
, 0), op1
)))
10279 op0
= XEXP (op0
, 1);
10284 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10285 of bits in X minus 1, is one iff X > 0. */
10286 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10287 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10288 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10289 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10291 op0
= XEXP (op0
, 1);
10292 code
= (code
== GE
? LE
: GT
);
10298 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10299 if C is zero or B is a constant. */
10300 if (equality_comparison_p
10301 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10302 XEXP (op0
, 1), op1
)))
10304 op0
= XEXP (op0
, 0);
10311 case LT
: case LTU
: case LE
: case LEU
:
10312 case GT
: case GTU
: case GE
: case GEU
:
10313 /* We can't do anything if OP0 is a condition code value, rather
10314 than an actual data value. */
10317 || XEXP (op0
, 0) == cc0_rtx
10319 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10322 /* Get the two operands being compared. */
10323 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10324 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10326 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10328 /* Check for the cases where we simply want the result of the
10329 earlier test or the opposite of that result. */
10331 || (code
== EQ
&& reversible_comparison_p (op0
))
10332 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10333 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10334 && (STORE_FLAG_VALUE
10335 & (((HOST_WIDE_INT
) 1
10336 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10338 || (code
== GE
&& reversible_comparison_p (op0
)))))
10340 code
= (code
== LT
|| code
== NE
10341 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
10342 op0
= tem
, op1
= tem1
;
10348 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10350 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10351 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10352 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10354 op0
= XEXP (op0
, 1);
10355 code
= (code
== GE
? GT
: LE
);
10361 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10362 will be converted to a ZERO_EXTRACT later. */
10363 if (const_op
== 0 && equality_comparison_p
10364 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10365 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10367 op0
= simplify_and_const_int
10368 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10370 XEXP (XEXP (op0
, 0), 1)),
10371 (HOST_WIDE_INT
) 1);
10375 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10376 zero and X is a comparison and C1 and C2 describe only bits set
10377 in STORE_FLAG_VALUE, we can compare with X. */
10378 if (const_op
== 0 && equality_comparison_p
10379 && mode_width
<= HOST_BITS_PER_WIDE_INT
10380 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10381 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10382 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10383 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10384 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10386 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10387 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10388 if ((~ STORE_FLAG_VALUE
& mask
) == 0
10389 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10390 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10391 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10393 op0
= XEXP (XEXP (op0
, 0), 0);
10398 /* If we are doing an equality comparison of an AND of a bit equal
10399 to the sign bit, replace this with a LT or GE comparison of
10400 the underlying value. */
10401 if (equality_comparison_p
10403 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10404 && mode_width
<= HOST_BITS_PER_WIDE_INT
10405 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10406 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10408 op0
= XEXP (op0
, 0);
10409 code
= (code
== EQ
? GE
: LT
);
10413 /* If this AND operation is really a ZERO_EXTEND from a narrower
10414 mode, the constant fits within that mode, and this is either an
10415 equality or unsigned comparison, try to do this comparison in
10416 the narrower mode. */
10417 if ((equality_comparison_p
|| unsigned_comparison_p
)
10418 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10419 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10420 & GET_MODE_MASK (mode
))
10422 && const_op
>> i
== 0
10423 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10425 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10429 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10430 in both M1 and M2 and the SUBREG is either paradoxical or
10431 represents the low part, permute the SUBREG and the AND and
10433 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10435 #ifdef WORD_REGISTER_OPERATIONS
10437 > (GET_MODE_BITSIZE
10438 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10439 && mode_width
<= BITS_PER_WORD
)
10442 <= (GET_MODE_BITSIZE
10443 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10444 && subreg_lowpart_p (XEXP (op0
, 0))))
10445 #ifndef WORD_REGISTER_OPERATIONS
10446 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10447 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10448 As originally written the upper bits have a defined value
10449 due to the AND operation. However, if we commute the AND
10450 inside the SUBREG then they no longer have defined values
10451 and the meaning of the code has been changed. */
10452 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10453 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10455 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10456 && mode_width
<= HOST_BITS_PER_WIDE_INT
10457 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10458 <= HOST_BITS_PER_WIDE_INT
)
10459 && (INTVAL (XEXP (op0
, 1)) & ~ mask
) == 0
10460 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10461 & INTVAL (XEXP (op0
, 1)))
10462 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10463 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10464 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10468 = gen_lowpart_for_combine
10470 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10471 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10478 /* If we have (compare (ashift FOO N) (const_int C)) and
10479 the high order N bits of FOO (N+1 if an inequality comparison)
10480 are known to be zero, we can do this by comparing FOO with C
10481 shifted right N bits so long as the low-order N bits of C are
10483 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10484 && INTVAL (XEXP (op0
, 1)) >= 0
10485 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10486 < HOST_BITS_PER_WIDE_INT
)
10488 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10489 && mode_width
<= HOST_BITS_PER_WIDE_INT
10490 && (nonzero_bits (XEXP (op0
, 0), mode
)
10491 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
10492 + ! equality_comparison_p
))) == 0)
10494 /* We must perform a logical shift, not an arithmetic one,
10495 as we want the top N bits of C to be zero. */
10496 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10498 temp
>>= INTVAL (XEXP (op0
, 1));
10499 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10500 op0
= XEXP (op0
, 0);
10504 /* If we are doing a sign bit comparison, it means we are testing
10505 a particular bit. Convert it to the appropriate AND. */
10506 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10507 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10509 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10512 - INTVAL (XEXP (op0
, 1)))));
10513 code
= (code
== LT
? NE
: EQ
);
10517 /* If this an equality comparison with zero and we are shifting
10518 the low bit to the sign bit, we can convert this to an AND of the
10520 if (const_op
== 0 && equality_comparison_p
10521 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10522 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10524 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10525 (HOST_WIDE_INT
) 1);
10531 /* If this is an equality comparison with zero, we can do this
10532 as a logical shift, which might be much simpler. */
10533 if (equality_comparison_p
&& const_op
== 0
10534 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10536 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10538 INTVAL (XEXP (op0
, 1)));
10542 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10543 do the comparison in a narrower mode. */
10544 if (! unsigned_comparison_p
10545 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10546 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10547 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10548 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10549 MODE_INT
, 1)) != BLKmode
10550 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10551 || ((unsigned HOST_WIDE_INT
) - const_op
10552 <= GET_MODE_MASK (tmode
))))
10554 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10558 /* Likewise if OP0 is a PLUS of a sign extension with a
10559 constant, which is usually represented with the PLUS
10560 between the shifts. */
10561 if (! unsigned_comparison_p
10562 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10563 && GET_CODE (XEXP (op0
, 0)) == PLUS
10564 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10565 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10566 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10567 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10568 MODE_INT
, 1)) != BLKmode
10569 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10570 || ((unsigned HOST_WIDE_INT
) - const_op
10571 <= GET_MODE_MASK (tmode
))))
10573 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10574 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10575 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10578 op0
= gen_binary (PLUS
, tmode
,
10579 gen_lowpart_for_combine (tmode
, inner
),
10584 /* ... fall through ... */
10586 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10587 the low order N bits of FOO are known to be zero, we can do this
10588 by comparing FOO with C shifted left N bits so long as no
10589 overflow occurs. */
10590 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10591 && INTVAL (XEXP (op0
, 1)) >= 0
10592 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10593 && mode_width
<= HOST_BITS_PER_WIDE_INT
10594 && (nonzero_bits (XEXP (op0
, 0), mode
)
10595 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10597 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10600 const_op
<<= INTVAL (XEXP (op0
, 1));
10601 op1
= GEN_INT (const_op
);
10602 op0
= XEXP (op0
, 0);
10606 /* If we are using this shift to extract just the sign bit, we
10607 can replace this with an LT or GE comparison. */
10609 && (equality_comparison_p
|| sign_bit_comparison_p
)
10610 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10611 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10613 op0
= XEXP (op0
, 0);
10614 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10626 /* Now make any compound operations involved in this comparison. Then,
10627 check for an outmost SUBREG on OP0 that is not doing anything or is
10628 paradoxical. The latter case can only occur when it is known that the
10629 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10630 We can never remove a SUBREG for a non-equality comparison because the
10631 sign bit is in a different place in the underlying object. */
10633 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10634 op1
= make_compound_operation (op1
, SET
);
10636 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10637 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10638 && (code
== NE
|| code
== EQ
)
10639 && ((GET_MODE_SIZE (GET_MODE (op0
))
10640 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10642 op0
= SUBREG_REG (op0
);
10643 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10646 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10647 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10648 && (code
== NE
|| code
== EQ
)
10649 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10650 <= HOST_BITS_PER_WIDE_INT
)
10651 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10652 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
10653 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10655 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10656 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
10657 op0
= SUBREG_REG (op0
), op1
= tem
;
10659 /* We now do the opposite procedure: Some machines don't have compare
10660 insns in all modes. If OP0's mode is an integer mode smaller than a
10661 word and we can't do a compare in that mode, see if there is a larger
10662 mode for which we can do the compare. There are a number of cases in
10663 which we can use the wider mode. */
10665 mode
= GET_MODE (op0
);
10666 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10667 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10668 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
10669 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10671 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10672 tmode
= GET_MODE_WIDER_MODE (tmode
))
10673 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
10675 /* If the only nonzero bits in OP0 and OP1 are those in the
10676 narrower mode and this is an equality or unsigned comparison,
10677 we can use the wider mode. Similarly for sign-extended
10678 values, in which case it is true for all comparisons. */
10679 if (((code
== EQ
|| code
== NE
10680 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10681 && (nonzero_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
10682 && (nonzero_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0)
10683 || ((num_sign_bit_copies (op0
, tmode
)
10684 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10685 && (num_sign_bit_copies (op1
, tmode
)
10686 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10688 /* If OP0 is an AND and we don't have an AND in MODE either,
10689 make a new AND in the proper mode. */
10690 if (GET_CODE (op0
) == AND
10691 && (add_optab
->handlers
[(int) mode
].insn_code
10692 == CODE_FOR_nothing
))
10693 op0
= gen_binary (AND
, tmode
,
10694 gen_lowpart_for_combine (tmode
,
10696 gen_lowpart_for_combine (tmode
,
10699 op0
= gen_lowpart_for_combine (tmode
, op0
);
10700 op1
= gen_lowpart_for_combine (tmode
, op1
);
10704 /* If this is a test for negative, we can make an explicit
10705 test of the sign bit. */
10707 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10708 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10710 op0
= gen_binary (AND
, tmode
,
10711 gen_lowpart_for_combine (tmode
, op0
),
10712 GEN_INT ((HOST_WIDE_INT
) 1
10713 << (GET_MODE_BITSIZE (mode
) - 1)));
10714 code
= (code
== LT
) ? NE
: EQ
;
10719 #ifdef CANONICALIZE_COMPARISON
10720 /* If this machine only supports a subset of valid comparisons, see if we
10721 can convert an unsupported one into a supported one. */
10722 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10731 /* Return 1 if we know that X, a comparison operation, is not operating
10732 on a floating-point value or is EQ or NE, meaning that we can safely
10736 reversible_comparison_p (x
)
10739 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
10741 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
10744 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
10747 case MODE_PARTIAL_INT
:
10748 case MODE_COMPLEX_INT
:
10752 /* If the mode of the condition codes tells us that this is safe,
10753 we need look no further. */
10754 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
10757 /* Otherwise try and find where the condition codes were last set and
10759 x
= get_last_value (XEXP (x
, 0));
10760 return (x
&& GET_CODE (x
) == COMPARE
10761 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
10768 /* Utility function for following routine. Called when X is part of a value
10769 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10770 for each register mentioned. Similar to mention_regs in cse.c */
10773 update_table_tick (x
)
10776 register enum rtx_code code
= GET_CODE (x
);
10777 register const char *fmt
= GET_RTX_FORMAT (code
);
10782 int regno
= REGNO (x
);
10783 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10784 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10786 for (i
= regno
; i
< endregno
; i
++)
10787 reg_last_set_table_tick
[i
] = label_tick
;
10792 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10793 /* Note that we can't have an "E" in values stored; see
10794 get_last_value_validate. */
10796 update_table_tick (XEXP (x
, i
));
10799 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10800 are saying that the register is clobbered and we no longer know its
10801 value. If INSN is zero, don't update reg_last_set; this is only permitted
10802 with VALUE also zero and is used to invalidate the register. */
10805 record_value_for_reg (reg
, insn
, value
)
10810 int regno
= REGNO (reg
);
10811 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10812 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
10815 /* If VALUE contains REG and we have a previous value for REG, substitute
10816 the previous value. */
10817 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10821 /* Set things up so get_last_value is allowed to see anything set up to
10823 subst_low_cuid
= INSN_CUID (insn
);
10824 tem
= get_last_value (reg
);
10826 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10827 it isn't going to be useful and will take a lot of time to process,
10828 so just use the CLOBBER. */
10832 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
10833 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
10834 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10835 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10836 tem
= XEXP (tem
, 0);
10838 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10842 /* For each register modified, show we don't know its value, that
10843 we don't know about its bitwise content, that its value has been
10844 updated, and that we don't know the location of the death of the
10846 for (i
= regno
; i
< endregno
; i
++)
10849 reg_last_set
[i
] = insn
;
10850 reg_last_set_value
[i
] = 0;
10851 reg_last_set_mode
[i
] = 0;
10852 reg_last_set_nonzero_bits
[i
] = 0;
10853 reg_last_set_sign_bit_copies
[i
] = 0;
10854 reg_last_death
[i
] = 0;
10857 /* Mark registers that are being referenced in this value. */
10859 update_table_tick (value
);
10861 /* Now update the status of each register being set.
10862 If someone is using this register in this block, set this register
10863 to invalid since we will get confused between the two lives in this
10864 basic block. This makes using this register always invalid. In cse, we
10865 scan the table to invalidate all entries using this register, but this
10866 is too much work for us. */
10868 for (i
= regno
; i
< endregno
; i
++)
10870 reg_last_set_label
[i
] = label_tick
;
10871 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
10872 reg_last_set_invalid
[i
] = 1;
10874 reg_last_set_invalid
[i
] = 0;
10877 /* The value being assigned might refer to X (like in "x++;"). In that
10878 case, we must replace it with (clobber (const_int 0)) to prevent
10880 if (value
&& ! get_last_value_validate (&value
, insn
,
10881 reg_last_set_label
[regno
], 0))
10883 value
= copy_rtx (value
);
10884 if (! get_last_value_validate (&value
, insn
,
10885 reg_last_set_label
[regno
], 1))
10889 /* For the main register being modified, update the value, the mode, the
10890 nonzero bits, and the number of sign bit copies. */
10892 reg_last_set_value
[regno
] = value
;
10896 subst_low_cuid
= INSN_CUID (insn
);
10897 reg_last_set_mode
[regno
] = GET_MODE (reg
);
10898 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
10899 reg_last_set_sign_bit_copies
[regno
]
10900 = num_sign_bit_copies (value
, GET_MODE (reg
));
10904 /* Called via note_stores from record_dead_and_set_regs to handle one
10905 SET or CLOBBER in an insn. DATA is the instruction in which the
10906 set is occurring. */
10909 record_dead_and_set_regs_1 (dest
, setter
, data
)
10913 rtx record_dead_insn
= (rtx
) data
;
10915 if (GET_CODE (dest
) == SUBREG
)
10916 dest
= SUBREG_REG (dest
);
10918 if (GET_CODE (dest
) == REG
)
10920 /* If we are setting the whole register, we know its value. Otherwise
10921 show that we don't know the value. We can handle SUBREG in
10923 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10924 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10925 else if (GET_CODE (setter
) == SET
10926 && GET_CODE (SET_DEST (setter
)) == SUBREG
10927 && SUBREG_REG (SET_DEST (setter
)) == dest
10928 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10929 && subreg_lowpart_p (SET_DEST (setter
)))
10930 record_value_for_reg (dest
, record_dead_insn
,
10931 gen_lowpart_for_combine (GET_MODE (dest
),
10932 SET_SRC (setter
)));
10934 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10936 else if (GET_CODE (dest
) == MEM
10937 /* Ignore pushes, they clobber nothing. */
10938 && ! push_operand (dest
, GET_MODE (dest
)))
10939 mem_last_set
= INSN_CUID (record_dead_insn
);
10942 /* Update the records of when each REG was most recently set or killed
10943 for the things done by INSN. This is the last thing done in processing
10944 INSN in the combiner loop.
10946 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10947 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10948 and also the similar information mem_last_set (which insn most recently
10949 modified memory) and last_call_cuid (which insn was the most recent
10950 subroutine call). */
10953 record_dead_and_set_regs (insn
)
10959 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10961 if (REG_NOTE_KIND (link
) == REG_DEAD
10962 && GET_CODE (XEXP (link
, 0)) == REG
)
10964 int regno
= REGNO (XEXP (link
, 0));
10966 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10967 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
10970 for (i
= regno
; i
< endregno
; i
++)
10971 reg_last_death
[i
] = insn
;
10973 else if (REG_NOTE_KIND (link
) == REG_INC
)
10974 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10977 if (GET_CODE (insn
) == CALL_INSN
)
10979 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10980 if (call_used_regs
[i
])
10982 reg_last_set_value
[i
] = 0;
10983 reg_last_set_mode
[i
] = 0;
10984 reg_last_set_nonzero_bits
[i
] = 0;
10985 reg_last_set_sign_bit_copies
[i
] = 0;
10986 reg_last_death
[i
] = 0;
10989 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
10992 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
10995 /* Utility routine for the following function. Verify that all the registers
10996 mentioned in *LOC are valid when *LOC was part of a value set when
10997 label_tick == TICK. Return 0 if some are not.
10999 If REPLACE is non-zero, replace the invalid reference with
11000 (clobber (const_int 0)) and return 1. This replacement is useful because
11001 we often can get useful information about the form of a value (e.g., if
11002 it was produced by a shift that always produces -1 or 0) even though
11003 we don't know exactly what registers it was produced from. */
11006 get_last_value_validate (loc
, insn
, tick
, replace
)
11013 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11014 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11017 if (GET_CODE (x
) == REG
)
11019 int regno
= REGNO (x
);
11020 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11021 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11024 for (j
= regno
; j
< endregno
; j
++)
11025 if (reg_last_set_invalid
[j
]
11026 /* If this is a pseudo-register that was only set once and not
11027 live at the beginning of the function, it is always valid. */
11028 || (! (regno
>= FIRST_PSEUDO_REGISTER
11029 && REG_N_SETS (regno
) == 1
11030 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, regno
))
11031 && reg_last_set_label
[j
] > tick
))
11034 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11040 /* If this is a memory reference, make sure that there were
11041 no stores after it that might have clobbered the value. We don't
11042 have alias info, so we assume any store invalidates it. */
11043 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11044 && INSN_CUID (insn
) <= mem_last_set
)
11047 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11051 for (i
= 0; i
< len
; i
++)
11053 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11054 /* Don't bother with these. They shouldn't occur anyway. */
11058 /* If we haven't found a reason for it to be invalid, it is valid. */
11062 /* Get the last value assigned to X, if known. Some registers
11063 in the value may be replaced with (clobber (const_int 0)) if their value
11064 is known longer known reliably. */
11073 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11074 then convert it to the desired mode. If this is a paradoxical SUBREG,
11075 we cannot predict what values the "extra" bits might have. */
11076 if (GET_CODE (x
) == SUBREG
11077 && subreg_lowpart_p (x
)
11078 && (GET_MODE_SIZE (GET_MODE (x
))
11079 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11080 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11081 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11083 if (GET_CODE (x
) != REG
)
11087 value
= reg_last_set_value
[regno
];
11089 /* If we don't have a value, or if it isn't for this basic block and
11090 it's either a hard register, set more than once, or it's a live
11091 at the beginning of the function, return 0.
11093 Because if it's not live at the beginnning of the function then the reg
11094 is always set before being used (is never used without being set).
11095 And, if it's set only once, and it's always set before use, then all
11096 uses must have the same last value, even if it's not from this basic
11100 || (reg_last_set_label
[regno
] != label_tick
11101 && (regno
< FIRST_PSEUDO_REGISTER
11102 || REG_N_SETS (regno
) != 1
11103 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, regno
))))
11106 /* If the value was set in a later insn than the ones we are processing,
11107 we can't use it even if the register was only set once. */
11108 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11111 /* If the value has all its registers valid, return it. */
11112 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11113 reg_last_set_label
[regno
], 0))
11116 /* Otherwise, make a copy and replace any invalid register with
11117 (clobber (const_int 0)). If that fails for some reason, return 0. */
11119 value
= copy_rtx (value
);
11120 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11121 reg_last_set_label
[regno
], 1))
11127 /* Return nonzero if expression X refers to a REG or to memory
11128 that is set in an instruction more recent than FROM_CUID. */
11131 use_crosses_set_p (x
, from_cuid
)
11135 register const char *fmt
;
11137 register enum rtx_code code
= GET_CODE (x
);
11141 register int regno
= REGNO (x
);
11142 int endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11143 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11145 #ifdef PUSH_ROUNDING
11146 /* Don't allow uses of the stack pointer to be moved,
11147 because we don't know whether the move crosses a push insn. */
11148 if (regno
== STACK_POINTER_REGNUM
)
11151 for (;regno
< endreg
; regno
++)
11152 if (reg_last_set
[regno
]
11153 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11158 if (code
== MEM
&& mem_last_set
> from_cuid
)
11161 fmt
= GET_RTX_FORMAT (code
);
11163 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11168 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11169 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11172 else if (fmt
[i
] == 'e'
11173 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11179 /* Define three variables used for communication between the following
11182 static int reg_dead_regno
, reg_dead_endregno
;
11183 static int reg_dead_flag
;
11185 /* Function called via note_stores from reg_dead_at_p.
11187 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11188 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11191 reg_dead_at_p_1 (dest
, x
, data
)
11194 void *data ATTRIBUTE_UNUSED
;
11196 int regno
, endregno
;
11198 if (GET_CODE (dest
) != REG
)
11201 regno
= REGNO (dest
);
11202 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11203 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11205 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11206 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11209 /* Return non-zero if REG is known to be dead at INSN.
11211 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11212 referencing REG, it is dead. If we hit a SET referencing REG, it is
11213 live. Otherwise, see if it is live or dead at the start of the basic
11214 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11215 must be assumed to be always live. */
11218 reg_dead_at_p (reg
, insn
)
11224 /* Set variables for reg_dead_at_p_1. */
11225 reg_dead_regno
= REGNO (reg
);
11226 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11227 ? HARD_REGNO_NREGS (reg_dead_regno
,
11233 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11234 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11236 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11237 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11241 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11242 beginning of function. */
11243 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11244 insn
= prev_nonnote_insn (insn
))
11246 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11248 return reg_dead_flag
== 1 ? 1 : 0;
11250 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11254 /* Get the basic block number that we were in. */
11259 for (block
= 0; block
< n_basic_blocks
; block
++)
11260 if (insn
== BLOCK_HEAD (block
))
11263 if (block
== n_basic_blocks
)
11267 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11268 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11274 /* Note hard registers in X that are used. This code is similar to
11275 that in flow.c, but much simpler since we don't care about pseudos. */
11278 mark_used_regs_combine (x
)
11281 register RTX_CODE code
= GET_CODE (x
);
11282 register int regno
;
11294 case ADDR_DIFF_VEC
:
11297 /* CC0 must die in the insn after it is set, so we don't need to take
11298 special note of it here. */
11304 /* If we are clobbering a MEM, mark any hard registers inside the
11305 address as used. */
11306 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11307 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11312 /* A hard reg in a wide mode may really be multiple registers.
11313 If so, mark all of them just like the first. */
11314 if (regno
< FIRST_PSEUDO_REGISTER
)
11316 /* None of this applies to the stack, frame or arg pointers */
11317 if (regno
== STACK_POINTER_REGNUM
11318 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11319 || regno
== HARD_FRAME_POINTER_REGNUM
11321 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11322 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11324 || regno
== FRAME_POINTER_REGNUM
)
11327 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11329 SET_HARD_REG_BIT (newpat_used_regs
, regno
+ i
);
11335 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11337 register rtx testreg
= SET_DEST (x
);
11339 while (GET_CODE (testreg
) == SUBREG
11340 || GET_CODE (testreg
) == ZERO_EXTRACT
11341 || GET_CODE (testreg
) == SIGN_EXTRACT
11342 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11343 testreg
= XEXP (testreg
, 0);
11345 if (GET_CODE (testreg
) == MEM
)
11346 mark_used_regs_combine (XEXP (testreg
, 0));
11348 mark_used_regs_combine (SET_SRC (x
));
11356 /* Recursively scan the operands of this expression. */
11359 register const char *fmt
= GET_RTX_FORMAT (code
);
11361 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11364 mark_used_regs_combine (XEXP (x
, i
));
11365 else if (fmt
[i
] == 'E')
11369 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11370 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11377 /* Remove register number REGNO from the dead registers list of INSN.
11379 Return the note used to record the death, if there was one. */
11382 remove_death (regno
, insn
)
11386 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11390 REG_N_DEATHS (regno
)--;
11391 remove_note (insn
, note
);
11397 /* For each register (hardware or pseudo) used within expression X, if its
11398 death is in an instruction with cuid between FROM_CUID (inclusive) and
11399 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11400 list headed by PNOTES.
11402 That said, don't move registers killed by maybe_kill_insn.
11404 This is done when X is being merged by combination into TO_INSN. These
11405 notes will then be distributed as needed. */
11408 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11410 rtx maybe_kill_insn
;
11415 register const char *fmt
;
11416 register int len
, i
;
11417 register enum rtx_code code
= GET_CODE (x
);
11421 register int regno
= REGNO (x
);
11422 register rtx where_dead
= reg_last_death
[regno
];
11423 register rtx before_dead
, after_dead
;
11425 /* Don't move the register if it gets killed in between from and to */
11426 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11427 && !reg_referenced_p (x
, maybe_kill_insn
))
11430 /* WHERE_DEAD could be a USE insn made by combine, so first we
11431 make sure that we have insns with valid INSN_CUID values. */
11432 before_dead
= where_dead
;
11433 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11434 before_dead
= PREV_INSN (before_dead
);
11435 after_dead
= where_dead
;
11436 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11437 after_dead
= NEXT_INSN (after_dead
);
11439 if (before_dead
&& after_dead
11440 && INSN_CUID (before_dead
) >= from_cuid
11441 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11442 || (where_dead
!= after_dead
11443 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11445 rtx note
= remove_death (regno
, where_dead
);
11447 /* It is possible for the call above to return 0. This can occur
11448 when reg_last_death points to I2 or I1 that we combined with.
11449 In that case make a new note.
11451 We must also check for the case where X is a hard register
11452 and NOTE is a death note for a range of hard registers
11453 including X. In that case, we must put REG_DEAD notes for
11454 the remaining registers in place of NOTE. */
11456 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11457 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11458 > GET_MODE_SIZE (GET_MODE (x
))))
11460 int deadregno
= REGNO (XEXP (note
, 0));
11462 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11463 GET_MODE (XEXP (note
, 0))));
11464 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11467 for (i
= deadregno
; i
< deadend
; i
++)
11468 if (i
< regno
|| i
>= ourend
)
11469 REG_NOTES (where_dead
)
11470 = gen_rtx_EXPR_LIST (REG_DEAD
,
11471 gen_rtx_REG (reg_raw_mode
[i
], i
),
11472 REG_NOTES (where_dead
));
11474 /* If we didn't find any note, or if we found a REG_DEAD note that
11475 covers only part of the given reg, and we have a multi-reg hard
11476 register, then to be safe we must check for REG_DEAD notes
11477 for each register other than the first. They could have
11478 their own REG_DEAD notes lying around. */
11479 else if ((note
== 0
11481 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11482 < GET_MODE_SIZE (GET_MODE (x
)))))
11483 && regno
< FIRST_PSEUDO_REGISTER
11484 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11486 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11491 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11495 for (i
= regno
+ offset
; i
< ourend
; i
++)
11496 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11497 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11500 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11502 XEXP (note
, 1) = *pnotes
;
11506 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11508 REG_N_DEATHS (regno
)++;
11514 else if (GET_CODE (x
) == SET
)
11516 rtx dest
= SET_DEST (x
);
11518 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11520 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11521 that accesses one word of a multi-word item, some
11522 piece of everything register in the expression is used by
11523 this insn, so remove any old death. */
11525 if (GET_CODE (dest
) == ZERO_EXTRACT
11526 || GET_CODE (dest
) == STRICT_LOW_PART
11527 || (GET_CODE (dest
) == SUBREG
11528 && (((GET_MODE_SIZE (GET_MODE (dest
))
11529 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11530 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11531 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11533 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11537 /* If this is some other SUBREG, we know it replaces the entire
11538 value, so use that as the destination. */
11539 if (GET_CODE (dest
) == SUBREG
)
11540 dest
= SUBREG_REG (dest
);
11542 /* If this is a MEM, adjust deaths of anything used in the address.
11543 For a REG (the only other possibility), the entire value is
11544 being replaced so the old value is not used in this insn. */
11546 if (GET_CODE (dest
) == MEM
)
11547 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11552 else if (GET_CODE (x
) == CLOBBER
)
11555 len
= GET_RTX_LENGTH (code
);
11556 fmt
= GET_RTX_FORMAT (code
);
11558 for (i
= 0; i
< len
; i
++)
11563 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11564 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11567 else if (fmt
[i
] == 'e')
11568 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11572 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11573 pattern of an insn. X must be a REG. */
11576 reg_bitfield_target_p (x
, body
)
11582 if (GET_CODE (body
) == SET
)
11584 rtx dest
= SET_DEST (body
);
11586 int regno
, tregno
, endregno
, endtregno
;
11588 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11589 target
= XEXP (dest
, 0);
11590 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11591 target
= SUBREG_REG (XEXP (dest
, 0));
11595 if (GET_CODE (target
) == SUBREG
)
11596 target
= SUBREG_REG (target
);
11598 if (GET_CODE (target
) != REG
)
11601 tregno
= REGNO (target
), regno
= REGNO (x
);
11602 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11603 return target
== x
;
11605 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11606 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11608 return endregno
> tregno
&& regno
< endtregno
;
11611 else if (GET_CODE (body
) == PARALLEL
)
11612 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11613 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11619 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11620 as appropriate. I3 and I2 are the insns resulting from the combination
11621 insns including FROM (I2 may be zero).
11623 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11624 not need REG_DEAD notes because they are being substituted for. This
11625 saves searching in the most common cases.
11627 Each note in the list is either ignored or placed on some insns, depending
11628 on the type of note. */
11631 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11635 rtx elim_i2
, elim_i1
;
11637 rtx note
, next_note
;
11640 for (note
= notes
; note
; note
= next_note
)
11642 rtx place
= 0, place2
= 0;
11644 /* If this NOTE references a pseudo register, ensure it references
11645 the latest copy of that register. */
11646 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11647 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11648 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11650 next_note
= XEXP (note
, 1);
11651 switch (REG_NOTE_KIND (note
))
11654 case REG_EXEC_COUNT
:
11655 /* Doesn't matter much where we put this, as long as it's somewhere.
11656 It is preferable to keep these notes on branches, which is most
11657 likely to be i3. */
11661 case REG_EH_REGION
:
11662 case REG_EH_RETHROW
:
11663 /* These notes must remain with the call. It should not be
11664 possible for both I2 and I3 to be a call. */
11665 if (GET_CODE (i3
) == CALL_INSN
)
11667 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11674 /* Any clobbers for i3 may still exist, and so we must process
11675 REG_UNUSED notes from that insn.
11677 Any clobbers from i2 or i1 can only exist if they were added by
11678 recog_for_combine. In that case, recog_for_combine created the
11679 necessary REG_UNUSED notes. Trying to keep any original
11680 REG_UNUSED notes from these insns can cause incorrect output
11681 if it is for the same register as the original i3 dest.
11682 In that case, we will notice that the register is set in i3,
11683 and then add a REG_UNUSED note for the destination of i3, which
11684 is wrong. However, it is possible to have REG_UNUSED notes from
11685 i2 or i1 for register which were both used and clobbered, so
11686 we keep notes from i2 or i1 if they will turn into REG_DEAD
11689 /* If this register is set or clobbered in I3, put the note there
11690 unless there is one already. */
11691 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11693 if (from_insn
!= i3
)
11696 if (! (GET_CODE (XEXP (note
, 0)) == REG
11697 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11698 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11701 /* Otherwise, if this register is used by I3, then this register
11702 now dies here, so we must put a REG_DEAD note here unless there
11704 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11705 && ! (GET_CODE (XEXP (note
, 0)) == REG
11706 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
11707 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11709 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11718 /* These notes say something about results of an insn. We can
11719 only support them if they used to be on I3 in which case they
11720 remain on I3. Otherwise they are ignored.
11722 If the note refers to an expression that is not a constant, we
11723 must also ignore the note since we cannot tell whether the
11724 equivalence is still true. It might be possible to do
11725 slightly better than this (we only have a problem if I2DEST
11726 or I1DEST is present in the expression), but it doesn't
11727 seem worth the trouble. */
11729 if (from_insn
== i3
11730 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11735 case REG_NO_CONFLICT
:
11736 /* These notes say something about how a register is used. They must
11737 be present on any use of the register in I2 or I3. */
11738 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11741 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11751 /* This can show up in several ways -- either directly in the
11752 pattern, or hidden off in the constant pool with (or without?)
11753 a REG_EQUAL note. */
11754 /* ??? Ignore the without-reg_equal-note problem for now. */
11755 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11756 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11757 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11758 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11762 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11763 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11764 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11765 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11775 /* It is too much trouble to try to see if this note is still
11776 correct in all situations. It is better to simply delete it. */
11780 /* If the insn previously containing this note still exists,
11781 put it back where it was. Otherwise move it to the previous
11782 insn. Adjust the corresponding REG_LIBCALL note. */
11783 if (GET_CODE (from_insn
) != NOTE
)
11787 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
11788 place
= prev_real_insn (from_insn
);
11790 XEXP (tem
, 0) = place
;
11795 /* This is handled similarly to REG_RETVAL. */
11796 if (GET_CODE (from_insn
) != NOTE
)
11800 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
11801 place
= next_real_insn (from_insn
);
11803 XEXP (tem
, 0) = place
;
11808 /* If the register is used as an input in I3, it dies there.
11809 Similarly for I2, if it is non-zero and adjacent to I3.
11811 If the register is not used as an input in either I3 or I2
11812 and it is not one of the registers we were supposed to eliminate,
11813 there are two possibilities. We might have a non-adjacent I2
11814 or we might have somehow eliminated an additional register
11815 from a computation. For example, we might have had A & B where
11816 we discover that B will always be zero. In this case we will
11817 eliminate the reference to A.
11819 In both cases, we must search to see if we can find a previous
11820 use of A and put the death note there. */
11823 && GET_CODE (from_insn
) == CALL_INSN
11824 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
11826 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
11828 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
11829 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11832 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
11835 /* If the register is used in both I2 and I3 and it dies in I3,
11836 we might have added another reference to it. If reg_n_refs
11837 was 2, bump it to 3. This has to be correct since the
11838 register must have been set somewhere. The reason this is
11839 done is because local-alloc.c treats 2 references as a
11842 if (place
== i3
&& i2
!= 0 && GET_CODE (XEXP (note
, 0)) == REG
11843 && REG_N_REFS (REGNO (XEXP (note
, 0)))== 2
11844 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11845 REG_N_REFS (REGNO (XEXP (note
, 0))) = 3;
11849 basic_block bb
= BASIC_BLOCK (this_basic_block
);
11851 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
11853 if (GET_RTX_CLASS (GET_CODE (tem
)) != 'i')
11855 if (tem
== bb
->head
)
11860 /* If the register is being set at TEM, see if that is all
11861 TEM is doing. If so, delete TEM. Otherwise, make this
11862 into a REG_UNUSED note instead. */
11863 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
11865 rtx set
= single_set (tem
);
11866 rtx inner_dest
= 0;
11868 rtx cc0_setter
= NULL_RTX
;
11872 for (inner_dest
= SET_DEST (set
);
11873 GET_CODE (inner_dest
) == STRICT_LOW_PART
11874 || GET_CODE (inner_dest
) == SUBREG
11875 || GET_CODE (inner_dest
) == ZERO_EXTRACT
;
11876 inner_dest
= XEXP (inner_dest
, 0))
11879 /* Verify that it was the set, and not a clobber that
11880 modified the register.
11882 CC0 targets must be careful to maintain setter/user
11883 pairs. If we cannot delete the setter due to side
11884 effects, mark the user with an UNUSED note instead
11887 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
11888 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
11890 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
11891 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
11892 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
11896 /* Move the notes and links of TEM elsewhere.
11897 This might delete other dead insns recursively.
11898 First set the pattern to something that won't use
11901 PATTERN (tem
) = pc_rtx
;
11903 distribute_notes (REG_NOTES (tem
), tem
, tem
,
11904 NULL_RTX
, NULL_RTX
, NULL_RTX
);
11905 distribute_links (LOG_LINKS (tem
));
11907 PUT_CODE (tem
, NOTE
);
11908 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
11909 NOTE_SOURCE_FILE (tem
) = 0;
11912 /* Delete the setter too. */
11915 PATTERN (cc0_setter
) = pc_rtx
;
11917 distribute_notes (REG_NOTES (cc0_setter
),
11918 cc0_setter
, cc0_setter
,
11919 NULL_RTX
, NULL_RTX
, NULL_RTX
);
11920 distribute_links (LOG_LINKS (cc0_setter
));
11922 PUT_CODE (cc0_setter
, NOTE
);
11923 NOTE_LINE_NUMBER (cc0_setter
)
11924 = NOTE_INSN_DELETED
;
11925 NOTE_SOURCE_FILE (cc0_setter
) = 0;
11929 /* If the register is both set and used here, put the
11930 REG_DEAD note here, but place a REG_UNUSED note
11931 here too unless there already is one. */
11932 else if (reg_referenced_p (XEXP (note
, 0),
11937 if (! find_regno_note (tem
, REG_UNUSED
,
11938 REGNO (XEXP (note
, 0))))
11940 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
11945 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
11947 /* If there isn't already a REG_UNUSED note, put one
11949 if (! find_regno_note (tem
, REG_UNUSED
,
11950 REGNO (XEXP (note
, 0))))
11955 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
11956 || (GET_CODE (tem
) == CALL_INSN
11957 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
11961 /* If we are doing a 3->2 combination, and we have a
11962 register which formerly died in i3 and was not used
11963 by i2, which now no longer dies in i3 and is used in
11964 i2 but does not die in i2, and place is between i2
11965 and i3, then we may need to move a link from place to
11967 if (i2
&& INSN_UID (place
) <= max_uid_cuid
11968 && INSN_CUID (place
) > INSN_CUID (i2
)
11969 && from_insn
&& INSN_CUID (from_insn
) > INSN_CUID (i2
)
11970 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11972 rtx links
= LOG_LINKS (place
);
11973 LOG_LINKS (place
) = 0;
11974 distribute_links (links
);
11979 if (tem
== bb
->head
)
11983 /* We haven't found an insn for the death note and it
11984 is still a REG_DEAD note, but we have hit the beginning
11985 of the block. If the existing life info says the reg
11986 was dead, there's nothing left to do. Otherwise, we'll
11987 need to do a global life update after combine. */
11988 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0)
11990 int regno
= REGNO (XEXP (note
, 0));
11991 if (REGNO_REG_SET_P (bb
->global_live_at_start
, regno
))
11993 SET_BIT (refresh_blocks
, this_basic_block
);
11999 /* If the register is set or already dead at PLACE, we needn't do
12000 anything with this note if it is still a REG_DEAD note.
12001 We can here if it is set at all, not if is it totally replace,
12002 which is what `dead_or_set_p' checks, so also check for it being
12005 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12007 int regno
= REGNO (XEXP (note
, 0));
12009 if (dead_or_set_p (place
, XEXP (note
, 0))
12010 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12012 /* Unless the register previously died in PLACE, clear
12013 reg_last_death. [I no longer understand why this is
12015 if (reg_last_death
[regno
] != place
)
12016 reg_last_death
[regno
] = 0;
12020 reg_last_death
[regno
] = place
;
12022 /* If this is a death note for a hard reg that is occupying
12023 multiple registers, ensure that we are still using all
12024 parts of the object. If we find a piece of the object
12025 that is unused, we must add a USE for that piece before
12026 PLACE and put the appropriate REG_DEAD note on it.
12028 An alternative would be to put a REG_UNUSED for the pieces
12029 on the insn that set the register, but that can't be done if
12030 it is not in the same block. It is simpler, though less
12031 efficient, to add the USE insns. */
12033 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12034 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12037 = regno
+ HARD_REGNO_NREGS (regno
,
12038 GET_MODE (XEXP (note
, 0)));
12042 for (i
= regno
; i
< endregno
; i
++)
12043 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12044 && ! find_regno_fusage (place
, USE
, i
))
12046 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12049 /* See if we already placed a USE note for this
12050 register in front of PLACE. */
12052 GET_CODE (PREV_INSN (p
)) == INSN
12053 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
12055 if (rtx_equal_p (piece
,
12056 XEXP (PATTERN (PREV_INSN (p
)), 0)))
12065 = emit_insn_before (gen_rtx_USE (VOIDmode
,
12068 REG_NOTES (use_insn
)
12069 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
12070 REG_NOTES (use_insn
));
12076 /* Check for the case where the register dying partially
12077 overlaps the register set by this insn. */
12079 for (i
= regno
; i
< endregno
; i
++)
12080 if (dead_or_set_regno_p (place
, i
))
12088 /* Put only REG_DEAD notes for pieces that are
12089 still used and that are not already dead or set. */
12091 for (i
= regno
; i
< endregno
; i
++)
12093 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12095 if ((reg_referenced_p (piece
, PATTERN (place
))
12096 || (GET_CODE (place
) == CALL_INSN
12097 && find_reg_fusage (place
, USE
, piece
)))
12098 && ! dead_or_set_p (place
, piece
)
12099 && ! reg_bitfield_target_p (piece
,
12102 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
12103 REG_NOTES (place
));
12113 /* Any other notes should not be present at this point in the
12120 XEXP (note
, 1) = REG_NOTES (place
);
12121 REG_NOTES (place
) = note
;
12123 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12124 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12125 && GET_CODE (XEXP (note
, 0)) == REG
)
12126 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12130 if ((REG_NOTE_KIND (note
) == REG_DEAD
12131 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12132 && GET_CODE (XEXP (note
, 0)) == REG
)
12133 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12135 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12136 REG_NOTE_KIND (note
),
12138 REG_NOTES (place2
));
12143 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12144 I3, I2, and I1 to new locations. This is also called in one case to
12145 add a link pointing at I3 when I3's destination is changed. */
12148 distribute_links (links
)
12151 rtx link
, next_link
;
12153 for (link
= links
; link
; link
= next_link
)
12159 next_link
= XEXP (link
, 1);
12161 /* If the insn that this link points to is a NOTE or isn't a single
12162 set, ignore it. In the latter case, it isn't clear what we
12163 can do other than ignore the link, since we can't tell which
12164 register it was for. Such links wouldn't be used by combine
12167 It is not possible for the destination of the target of the link to
12168 have been changed by combine. The only potential of this is if we
12169 replace I3, I2, and I1 by I3 and I2. But in that case the
12170 destination of I2 also remains unchanged. */
12172 if (GET_CODE (XEXP (link
, 0)) == NOTE
12173 || (set
= single_set (XEXP (link
, 0))) == 0)
12176 reg
= SET_DEST (set
);
12177 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12178 || GET_CODE (reg
) == SIGN_EXTRACT
12179 || GET_CODE (reg
) == STRICT_LOW_PART
)
12180 reg
= XEXP (reg
, 0);
12182 /* A LOG_LINK is defined as being placed on the first insn that uses
12183 a register and points to the insn that sets the register. Start
12184 searching at the next insn after the target of the link and stop
12185 when we reach a set of the register or the end of the basic block.
12187 Note that this correctly handles the link that used to point from
12188 I3 to I2. Also note that not much searching is typically done here
12189 since most links don't point very far away. */
12191 for (insn
= NEXT_INSN (XEXP (link
, 0));
12192 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12193 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12194 insn
= NEXT_INSN (insn
))
12195 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
12196 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12198 if (reg_referenced_p (reg
, PATTERN (insn
)))
12202 else if (GET_CODE (insn
) == CALL_INSN
12203 && find_reg_fusage (insn
, USE
, reg
))
12209 /* If we found a place to put the link, place it there unless there
12210 is already a link to the same insn as LINK at that point. */
12216 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12217 if (XEXP (link2
, 0) == XEXP (link
, 0))
12222 XEXP (link
, 1) = LOG_LINKS (place
);
12223 LOG_LINKS (place
) = link
;
12225 /* Set added_links_insn to the earliest insn we added a
12227 if (added_links_insn
== 0
12228 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12229 added_links_insn
= place
;
12235 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12241 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12242 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12243 insn
= NEXT_INSN (insn
);
12245 if (INSN_UID (insn
) > max_uid_cuid
)
12248 return INSN_CUID (insn
);
12252 dump_combine_stats (file
)
12257 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12258 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12262 dump_combine_total_stats (file
)
12267 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12268 total_attempts
, total_merges
, total_extras
, total_successes
);