1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ::::::::::::::::::::
29 ;; ::::::::::::::::::::
31 ;; GOT constants must go 12/HI/LO for the splitter to work
37 (UNSPEC_PIC_PROLOGUE 3)
39 (UNSPEC_STACK_ADJUST 5)
40 (UNSPEC_EH_RETURN_EPILOGUE 6)
48 (R_FRV_FUNCDESC_GOT12 15)
49 (R_FRV_FUNCDESC_GOTHI 16)
50 (R_FRV_FUNCDESC_GOTLO 17)
51 (R_FRV_FUNCDESC_VALUE 18)
52 (R_FRV_FUNCDESC_GOTOFF12 19)
53 (R_FRV_FUNCDESC_GOTOFFHI 20)
54 (R_FRV_FUNCDESC_GOTOFFLO 21)
67 ;; ::::::::::::::::::::
71 ;; ::::::::::::::::::::
73 ;; Standard Constraints
75 ;; `m' A memory operand is allowed, with any kind of address that the
76 ;; machine supports in general.
78 ;; `o' A memory operand is allowed, but only if the address is
79 ;; "offsettable". This means that adding a small integer (actually, the
80 ;; width in bytes of the operand, as determined by its machine mode) may be
81 ;; added to the address and the result is also a valid memory address.
83 ;; `V' A memory operand that is not offsettable. In other words,
84 ;; anything that would fit the `m' constraint but not the `o' constraint.
86 ;; `<' A memory operand with autodecrement addressing (either
87 ;; predecrement or postdecrement) is allowed.
89 ;; `>' A memory operand with autoincrement addressing (either
90 ;; preincrement or postincrement) is allowed.
92 ;; `r' A register operand is allowed provided that it is in a general
96 ;; Other letters can be defined in machine-dependent fashion to stand for
97 ;; particular classes of registers. `d', `a' and `f' are defined on the
98 ;; 68000/68020 to stand for data, address and floating point registers.
100 ;; `i' An immediate integer operand (one with constant value) is allowed.
101 ;; This includes symbolic constants whose values will be known only at
104 ;; `n' An immediate integer operand with a known numeric value is allowed.
105 ;; Many systems cannot support assembly-time constants for operands less
106 ;; than a word wide. Constraints for these operands should use `n' rather
109 ;; 'I' First machine-dependent integer constant (6 bit signed ints).
110 ;; 'J' Second machine-dependent integer constant (10 bit signed ints).
111 ;; 'K' Third machine-dependent integer constant (-2048).
112 ;; 'L' Fourth machine-dependent integer constant (16 bit signed ints).
113 ;; 'M' Fifth machine-dependent integer constant (16 bit unsigned ints).
114 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
115 ;; 'O' Seventh machine-dependent integer constant (zero).
116 ;; 'P' Eighth machine-dependent integer constant (1..2047).
118 ;; Other letters in the range `I' through `P' may be defined in a
119 ;; machine-dependent fashion to permit immediate integer operands with
120 ;; explicit integer values in specified ranges. For example, on the 68000,
121 ;; `I' is defined to stand for the range of values 1 to 8. This is the
122 ;; range permitted as a shift count in the shift instructions.
124 ;; `E' An immediate floating operand (expression code `const_double') is
125 ;; allowed, but only if the target floating point format is the same as
126 ;; that of the host machine (on which the compiler is running).
128 ;; `F' An immediate floating operand (expression code `const_double') is
131 ;; 'G' First machine-dependent const_double.
132 ;; 'H' Second machine-dependent const_double.
134 ;; `s' An immediate integer operand whose value is not an explicit
135 ;; integer is allowed.
137 ;; This might appear strange; if an insn allows a constant operand with a
138 ;; value not known at compile time, it certainly must allow any known
139 ;; value. So why use `s' instead of `i'? Sometimes it allows better code
142 ;; For example, on the 68000 in a fullword instruction it is possible to
143 ;; use an immediate operand; but if the immediate value is between -128 and
144 ;; 127, better code results from loading the value into a register and
145 ;; using the register. This is because the load into the register can be
146 ;; done with a `moveq' instruction. We arrange for this to happen by
147 ;; defining the letter `K' to mean "any integer outside the range -128 to
148 ;; 127", and then specifying `Ks' in the operand constraints.
150 ;; `g' Any register, memory or immediate integer operand is allowed,
151 ;; except for registers that are not general registers.
153 ;; `X' Any operand whatsoever is allowed, even if it does not satisfy
154 ;; `general_operand'. This is normally used in the constraint of a
155 ;; `match_scratch' when certain alternatives will not actually require a
158 ;; `0' Match operand 0.
159 ;; `1' Match operand 1.
160 ;; `2' Match operand 2.
161 ;; `3' Match operand 3.
162 ;; `4' Match operand 4.
163 ;; `5' Match operand 5.
164 ;; `6' Match operand 6.
165 ;; `7' Match operand 7.
166 ;; `8' Match operand 8.
167 ;; `9' Match operand 9.
169 ;; An operand that matches the specified operand number is allowed. If a
170 ;; digit is used together with letters within the same alternative, the
171 ;; digit should come last.
173 ;; This is called a "matching constraint" and what it really means is that
174 ;; the assembler has only a single operand that fills two roles considered
175 ;; separate in the RTL insn. For example, an add insn has two input
176 ;; operands and one output operand in the RTL, but on most CISC machines an
177 ;; add instruction really has only two operands, one of them an
178 ;; input-output operand:
182 ;; Matching constraints are used in these circumstances. More precisely,
183 ;; the two operands that match must include one input-only operand and one
184 ;; output-only operand. Moreover, the digit must be a smaller number than
185 ;; the number of the operand that uses it in the constraint.
187 ;; For operands to match in a particular case usually means that they are
188 ;; identical-looking RTL expressions. But in a few special cases specific
189 ;; kinds of dissimilarity are allowed. For example, `*x' as an input
190 ;; operand will match `*x++' as an output operand. For proper results in
191 ;; such cases, the output template should always use the output-operand's
192 ;; number when printing the operand.
194 ;; `p' An operand that is a valid memory address is allowed. This is for
195 ;; "load address" and "push address" instructions.
197 ;; `p' in the constraint must be accompanied by `address_operand' as the
198 ;; predicate in the `match_operand'. This predicate interprets the mode
199 ;; specified in the `match_operand' as the mode of the memory reference for
200 ;; which the address would be valid.
202 ;; `Q` First non constant, non register machine-dependent insns
203 ;; `R` Second non constant, non register machine-dependent insns
204 ;; `S` Third non constant, non register machine-dependent insns
205 ;; `T` Fourth non constant, non register machine-dependent insns
206 ;; `U` Fifth non constant, non register machine-dependent insns
208 ;; Letters in the range `Q' through `U' may be defined in a
209 ;; machine-dependent fashion to stand for arbitrary operand types. The
210 ;; machine description macro `EXTRA_CONSTRAINT' is passed the operand as
211 ;; its first argument and the constraint letter as its second operand.
213 ;; A typical use for this would be to distinguish certain types of memory
214 ;; references that affect other insn operands.
216 ;; Do not define these constraint letters to accept register references
217 ;; (`reg'); the reload pass does not expect this and would not handle it
220 ;; Multiple Alternative Constraints
221 ;; `?' Disparage slightly the alternative that the `?' appears in, as a
222 ;; choice when no alternative applies exactly. The compiler regards this
223 ;; alternative as one unit more costly for each `?' that appears in it.
225 ;; `!' Disparage severely the alternative that the `!' appears in. This
226 ;; alternative can still be used if it fits without reloading, but if
227 ;; reloading is needed, some other alternative will be used.
229 ;; Constraint modifiers
230 ;; `=' Means that this operand is write-only for this instruction: the
231 ;; previous value is discarded and replaced by output data.
233 ;; `+' Means that this operand is both read and written by the
236 ;; When the compiler fixes up the operands to satisfy the constraints, it
237 ;; needs to know which operands are inputs to the instruction and which are
238 ;; outputs from it. `=' identifies an output; `+' identifies an operand
239 ;; that is both input and output; all other operands are assumed to be
242 ;; `&' Means (in a particular alternative) that this operand is written
243 ;; before the instruction is finished using the input operands. Therefore,
244 ;; this operand may not lie in a register that is used as an input operand
245 ;; or as part of any memory address.
247 ;; `&' applies only to the alternative in which it is written. In
248 ;; constraints with multiple alternatives, sometimes one alternative
249 ;; requires `&' while others do not.
251 ;; `&' does not obviate the need to write `='.
253 ;; `%' Declares the instruction to be commutative for this operand and the
254 ;; following operand. This means that the compiler may interchange the two
255 ;; operands if that is the cheapest way to make all operands fit the
256 ;; constraints. This is often used in patterns for addition instructions
257 ;; that really have only two operands: the result must go in one of the
260 ;; `#' Says that all following characters, up to the next comma, are to be
261 ;; ignored as a constraint. They are significant only for choosing
262 ;; register preferences.
264 ;; `*' Says that the following character should be ignored when choosing
265 ;; register preferences. `*' has no effect on the meaning of the
266 ;; constraint as a constraint, and no effect on reloading.
269 ;; ::::::::::::::::::::
273 ;; ::::::::::::::::::::
275 ;; The `define_attr' expression is used to define each attribute required by
276 ;; the target machine. It looks like:
278 ;; (define_attr NAME LIST-OF-VALUES DEFAULT)
280 ;; NAME is a string specifying the name of the attribute being defined.
282 ;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
283 ;; values that can be assigned to the attribute, or a null string to indicate
284 ;; that the attribute takes numeric values.
286 ;; DEFAULT is an attribute expression that gives the value of this attribute
287 ;; for insns that match patterns whose definition does not include an explicit
288 ;; value for this attribute.
290 ;; For each defined attribute, a number of definitions are written to the
291 ;; `insn-attr.h' file. For cases where an explicit set of values is specified
292 ;; for an attribute, the following are defined:
294 ;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
296 ;; * An enumeral class is defined for `attr_NAME' with elements of the
297 ;; form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
298 ;; converted to upper case.
300 ;; * A function `get_attr_NAME' is defined that is passed an insn and
301 ;; returns the attribute value for that insn.
303 ;; For example, if the following is present in the `md' file:
305 ;; (define_attr "type" "branch,fp,load,store,arith" ...)
307 ;; the following lines will be written to the file `insn-attr.h'.
309 ;; #define HAVE_ATTR_type
310 ;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
311 ;; extern enum attr_type get_attr_type ();
313 ;; If the attribute takes numeric values, no `enum' type will be defined and
314 ;; the function to obtain the attribute's value will return `int'.
316 (define_attr "length" "" (const_int 4))
318 ;; Processor type -- this attribute must exactly match the processor_type
319 ;; enumeration in frv-protos.h.
321 (define_attr "cpu" "generic,fr500,fr400,fr300,simple,tomcat"
322 (const (symbol_ref "frv_cpu_type")))
324 ;; Attribute is "yes" for branches and jumps that span too great a distance
325 ;; to be implemented in the most natural way. Such instructions will use
326 ;; a call instruction in some way.
328 (define_attr "far_jump" "yes,no" (const_string "no"))
332 ;; The table below summarizes the types of media instruction and their
333 ;; scheduling classification. Headings are:
335 ;; Type: the name of the define_attr type
336 ;; Conditions: "yes" if conditional variants are available
337 ;; FR500: Fujitsu's categorization for the FR500
338 ;; FR400: Fujitsu's categorization for the FR400 (but see below).
340 ;; On the FR400, media instructions are divided into 2 broad categories.
341 ;; Category 1 instructions can execute in either the M0 or M1 unit and can
342 ;; execute in parallel with other category 1 instructions. Category 2
343 ;; instructions must use the M0 unit, and therefore cannot run in parallel
344 ;; with other media instructions.
346 ;; The FR400 documentation also divides media instructions into one of seven
347 ;; categories (m1 to m7). m1 to m4 contain both Category 1 and Category 2
348 ;; instructions, so we use a combination of the categories here.
350 ;; Type Conditional FR500 FR400
351 ;; ---- ---------- ----- -----
352 ;; mlogic yes m1 m1:1
358 ;; mqaddh yes m1 m1:2
360 ;; munpackh no m2 m3:2
361 ;; mdpackh no m5 m3:2
362 ;; mbhconv yes m2 m3:2
365 ;; mexpdhw yes m2 m3:1
366 ;; mexpdhd yes m2 m3:2
372 ;; mqmulh yes m4 m2:2
373 ;; mqmulxh no m4 m2:2
374 ;; mqmach yes m4 m2:2
378 ;; mclracc no m3 m4:1
379 ;; mclracca no m6 m4:2
380 ;; mdunpackh no m2 n/a
381 ;; mbhconve no m2 n/a
382 ;; maddacc no n/a m2:1
383 ;; mdaddacc no n/a m2:2
388 ;; mqsath no n/a m1:2
392 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,branch,jump,jumpl,call,spr,trap,fsconv,fsadd,fsmul,fmas,fsdiv,sqrt_single,fdconv,fdadd,fdmul,fddiv,sqrt_double,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mset,m7,ccr,multi,unknown"
393 (const_string "unknown"))
397 /* This is description of pipeline hazards based on DFA. The
398 following constructions can be used for this:
400 o define_cpu_unit string [string]) describes a cpu functional unit
401 (separated by comma).
403 1st operand: Names of cpu function units.
404 2nd operand: Name of automaton (see comments for
407 All define_reservations and define_cpu_units should have unique
408 names which cannot be "nothing".
410 o (exclusion_set string string) means that each CPU function unit
411 in the first string cannot be reserved simultaneously with each
412 unit whose name is in the second string and vise versa. CPU
413 units in the string are separated by commas. For example, it is
414 useful for description CPU with fully pipelined floating point
415 functional unit which can execute simultaneously only single
416 floating point insns or only double floating point insns.
418 o (presence_set string string) means that each CPU function unit in
419 the first string cannot be reserved unless at least one of units
420 whose names are in the second string is reserved. This is an
421 asymmetric relation. CPU units in the string are separated by
422 commas. For example, it is useful for description that slot1 is
423 reserved after slot0 reservation for a VLIW processor.
425 o (absence_set string string) means that each CPU function unit in
426 the first string cannot be reserved only if each unit whose name
427 is in the second string is not reserved. This is an asymmetric
428 relation (actually exclusion set is analogous to this one but it
429 is symmetric). CPU units in the string are separated by commas.
430 For example, it is useful for description that slot0 cannot be
431 reserved after slot1 or slot2 reservation for a VLIW processor.
433 o (define_bypass number out_insn_names in_insn_names) names bypass with
434 given latency (the first number) from insns given by the first
435 string (see define_insn_reservation) into insns given by the
436 second string. Insn names in the strings are separated by
439 o (define_automaton string) describes names of an automaton
440 generated and used for pipeline hazards recognition. The names
441 are separated by comma. Actually it is possibly to generate the
442 single automaton but unfortunately it can be very large. If we
443 use more one automata, the summary size of the automata usually
444 is less than the single one. The automaton name is used in
445 define_cpu_unit. All automata should have unique names.
447 o (define_reservation string string) names reservation (the first
448 string) of cpu functional units (the 2nd string). Sometimes unit
449 reservations for different insns contain common parts. In such
450 case, you describe common part and use one its name (the 1st
451 parameter) in regular expression in define_insn_reservation. All
452 define_reservations, define results and define_cpu_units should
453 have unique names which cannot be "nothing".
455 o (define_insn_reservation name default_latency condition regexpr)
456 describes reservation of cpu functional units (the 3nd operand)
457 for instruction which is selected by the condition (the 2nd
458 parameter). The first parameter is used for output of debugging
459 information. The reservations are described by a regular
460 expression according the following syntax:
462 regexp = regexp "," oneof
465 oneof = oneof "|" allof
468 allof = allof "+" repeat
471 repeat = element "*" number
474 element = cpu_function_name
480 1. "," is used for describing start of the next cycle in
483 2. "|" is used for describing the reservation described by the
484 first regular expression *or* the reservation described by
485 the second regular expression *or* etc.
487 3. "+" is used for describing the reservation described by the
488 first regular expression *and* the reservation described by
489 the second regular expression *and* etc.
491 4. "*" is used for convenience and simply means sequence in
492 which the regular expression are repeated NUMBER times with
493 cycle advancing (see ",").
495 5. cpu function unit name which means reservation.
497 6. reservation name -- see define_reservation.
499 7. string "nothing" means no units reservation.
503 (define_automaton "nodiv, idiv, div")
505 ;; An FR500 packet can contain a single control instruction or a sequence
506 ;; of up to four operations matching the regular expression:
508 ;; (I FM? I? FM? | FM? FM?) B? B?
510 ;; where I denotes an integer operation, FM a floating-point or media
511 ;; operation, and B a branch operation. There are two units for each type
512 ;; of instruction: I0 and I1, FM0 and FM1, and B0 and B1. Units are
513 ;; allocated left-to-right: the first integer instruction uses I0, the
514 ;; second uses I1, and so on.
516 ;; The FR400 is similar to the FR500 except that it allows only 2 operations
517 ;; per packet and has only one branch unit. We can use the FR500 conflict
518 ;; description for the FR400, but need to define different cpu_units
521 ;; Slot/unit combinations available on the FR400 and above:
522 (define_cpu_unit "sl0_i0, sl0_fm0, sl0_b0, sl0_c" "nodiv")
523 (define_cpu_unit "sl1_fm0, sl1_i1, sl1_fm1, sl1_b0" "nodiv")
525 ;; These are available on the FR500 and above:
526 (define_cpu_unit "sl1_b1" "nodiv")
527 (define_cpu_unit "sl2_i1, sl2_fm1, sl2_b0, sl2_b1" "nodiv")
528 (define_cpu_unit "sl3_fm1, sl3_b0, sl3_b1" "nodiv")
530 ;; The following describes conflicts by slots
532 (exclusion_set "sl0_i0" "sl0_fm0,sl0_b0,sl0_c")
533 (exclusion_set "sl0_fm0" "sl0_b0,sl0_c")
534 (exclusion_set "sl0_b0" "sl0_c")
537 (exclusion_set "sl1_fm0" "sl1_i1,sl1_fm1,sl1_b0,sl1_b1")
538 (exclusion_set "sl1_i1" "sl1_fm1,sl1_b0,sl1_b1")
539 (exclusion_set "sl1_fm1" "sl1_b0,sl1_b1")
540 (exclusion_set "sl1_b0" "sl1_b1")
543 (exclusion_set "sl2_i1" "sl2_fm1,sl2_b0,sl2_b1")
544 (exclusion_set "sl2_fm1" "sl2_b0,sl2_b1")
545 (exclusion_set "sl2_b0" "sl2_b1")
548 (exclusion_set "sl3_fm1" "sl3_b0,sl3_b1")
549 (exclusion_set "sl3_b0" "sl3_b1")
551 ;; The following describes conflicts by units
553 (exclusion_set "sl0_fm0" "sl1_fm0")
556 (exclusion_set "sl0_b0" "sl1_b0,sl2_b0,sl3_b0")
557 (exclusion_set "sl1_b0" "sl2_b0,sl3_b0")
558 (exclusion_set "sl2_b0" "sl3_b0")
561 (exclusion_set "sl1_i1" "sl2_i1")
564 (exclusion_set "sl1_fm1" "sl2_fm1,sl3_fm1")
565 (exclusion_set "sl2_fm1" "sl3_fm1")
568 (exclusion_set "sl1_b1" "sl2_b1,sl3_b1")
569 (exclusion_set "sl2_b1" "sl3_b1")
571 ;; The following describes remaining combinations of conflicts
573 (exclusion_set "sl0_i0" "sl1_fm1,sl1_b1")
574 (exclusion_set "sl0_fm0" "sl1_i1,sl1_b1,sl2_i1,sl2_fm1,sl3_fm1,sl3_b0")
575 (exclusion_set "sl0_b0" "sl1_fm0,sl1_i1,sl1_fm1,sl2_i1,sl2_fm1,sl2_b1,\
577 (exclusion_set "sl0_c" "sl1_fm0,sl1_i1,sl1_fm1,sl1_b0,sl1_b1,sl2_i1,sl2_fm1,\
578 sl2_b0,sl2_b1,sl3_fm1,sl3_b0,sl3_b1")
582 (exclusion_set "sl1_fm0" "sl2_b1")
583 (exclusion_set "sl1_i1" "sl2_fm1,sl2_b1,sl3_fm1,sl3_b0")
584 (exclusion_set "sl1_fm1" "sl2_i1,sl2_b1,sl3_b0")
585 (exclusion_set "sl1_b0" "sl2_i1,sl2_fm1,sl3_fm1,sl3_b1")
586 (exclusion_set "sl1_b1" "sl2_i1,sl2_fm1,sl2_b0,sl3_fm1,sl3_b0")
589 (exclusion_set "sl2_i1" "sl3_b1")
590 (exclusion_set "sl2_fm1" "sl3_b1")
591 (exclusion_set "sl2_b0" "sl3_fm1")
592 (exclusion_set "sl2_b1" "sl3_fm1,sl3_b0")
595 (exclusion_set "sl1_fm0" "sl2_i1,sl2_fm1,sl2_b0,sl2_b1,sl3_fm1,sl3_b0,sl3_b1")
596 (exclusion_set "sl3_fm1" "sl2_i1,sl2_fm1,sl2_b0,sl2_b1,sl3_b0,sl3_b1")
598 ;; ::::::::::::::::::::
600 ;; :: Generic/FR500 scheduler description
602 ;; ::::::::::::::::::::
604 ;; Define reservation in order to describe only in terms of units.
606 (define_reservation "i0" "sl0_i0")
607 (define_reservation "f0" "sl0_fm0|sl1_fm0")
608 (define_reservation "m0" "f0")
609 (define_reservation "b0" "sl0_b0|sl1_b0|sl2_b0|sl3_b0")
610 (define_reservation "c" "sl0_c")
611 (define_reservation "i1" "sl1_i1|sl2_i1")
612 (define_reservation "f1" "sl1_fm1|sl2_fm1|sl3_fm1")
613 (define_reservation "m1" "f1")
614 (define_reservation "b1" "sl1_b1|sl2_b1|sl3_b1")
617 ;; It is not possibly to issue load & store in one VLIW insn.
618 (define_cpu_unit "idiv1" "idiv")
619 (define_cpu_unit "idiv2" "idiv")
620 (define_cpu_unit "l0" "nodiv")
621 (define_cpu_unit "l1" "nodiv")
622 (define_cpu_unit "s0" "nodiv")
624 (exclusion_set "l1,l0" "s0")
626 ;; We set the default_latency of sethi to be 0 to allow sethi and setlo to be
627 ;; combined in the same VLIW instruction as allowed by the architecture. This
628 ;; assumes the only use of sethi is always followed by a setlo of the same
630 (define_insn_reservation "i1_sethi" 0
631 (and (eq_attr "cpu" "generic,fr500,tomcat")
632 (eq_attr "type" "sethi"))
635 (define_insn_reservation "i1_setlo" 1
636 (and (eq_attr "cpu" "generic,fr500,tomcat")
637 (eq_attr "type" "setlo"))
640 (define_insn_reservation "i1_int" 1
641 (and (eq_attr "cpu" "generic,fr500,tomcat")
642 (eq_attr "type" "int"))
645 (define_insn_reservation "i1_mul" 3
646 (and (eq_attr "cpu" "generic,fr500,tomcat")
647 (eq_attr "type" "mul"))
650 (define_insn_reservation "i1_div" 19
651 (and (eq_attr "cpu" "generic,fr500,tomcat")
652 (eq_attr "type" "div"))
653 "(i0|i1),(idiv1*18|idiv2*18)")
655 (define_insn_reservation "i2_gload" 4
656 (and (eq_attr "cpu" "generic,fr500,tomcat")
657 (eq_attr "type" "gload"))
660 (define_insn_reservation "i2_fload" 4
661 (and (eq_attr "cpu" "generic,fr500,tomcat")
662 (eq_attr "type" "fload"))
665 (define_insn_reservation "i3_gstore" 0
666 (and (eq_attr "cpu" "generic,fr500,tomcat")
667 (eq_attr "type" "gstore"))
670 (define_insn_reservation "i3_fstore" 0
671 (and (eq_attr "cpu" "generic,fr500,tomcat")
672 (eq_attr "type" "fstore"))
675 (define_insn_reservation "i4_move_gf" 3
676 (and (eq_attr "cpu" "generic,fr500,tomcat")
677 (eq_attr "type" "movgf"))
680 (define_insn_reservation "i4_move_fg" 3
681 (and (eq_attr "cpu" "generic,fr500,tomcat")
682 (eq_attr "type" "movfg"))
685 (define_insn_reservation "i5" 0
686 (and (eq_attr "cpu" "generic,fr500,tomcat")
687 (eq_attr "type" "jumpl"))
690 ;; Clear/commit is not generated now:
691 (define_insn_reservation "i6" 0 (const_int 0) "i0|i1")
694 ;; Branch-instructions
696 (define_insn_reservation "b1/b3" 0
697 (and (eq_attr "cpu" "generic,fr500,tomcat")
698 (eq_attr "type" "jump,branch,ccr"))
701 ;; The following insn is not generated now.
703 (define_insn_reservation "b2" 0 (const_int 0) "b0")
705 (define_insn_reservation "b4" 0
706 (and (eq_attr "cpu" "generic,fr500,tomcat")
707 (eq_attr "type" "call"))
710 ;; The following insns are not generated now.
711 (define_insn_reservation "b5" 0 (const_int 0) "b0|b1")
712 (define_insn_reservation "b6" 0 (const_int 0) "b0|b1")
715 (define_insn_reservation "trap" 0
716 (and (eq_attr "cpu" "generic,fr500,tomcat")
717 (eq_attr "type" "trap"))
720 (define_insn_reservation "control" 0
721 (and (eq_attr "cpu" "generic,fr500,tomcat")
722 (eq_attr "type" "spr"))
725 ;; Floating point insns
726 (define_cpu_unit "add0" "nodiv")
727 (define_cpu_unit "add1" "nodiv")
728 (define_cpu_unit "mul0" "nodiv")
729 (define_cpu_unit "mul1" "nodiv")
730 (define_cpu_unit "div1" "div")
731 (define_cpu_unit "div2" "div")
732 (define_cpu_unit "root" "div")
734 (define_bypass 4 "f1" "m1,m2,m3,m4,m5,m6,m7")
735 (define_insn_reservation "f1" 3
736 (and (eq_attr "cpu" "generic,fr500,tomcat")
737 (eq_attr "type" "fsconv,fdconv"))
740 (define_bypass 4 "f2" "m1,m2,m3,m4,m5,m6,m7")
741 (define_insn_reservation "f2" 3
742 (and (eq_attr "cpu" "generic,fr500,tomcat")
743 (eq_attr "type" "fsadd,fdadd"))
744 "(f0|f1)+(add0|add1)")
746 (define_bypass 4 "f3" "m1,m2,m3,m4,m5,m6,m7")
747 (define_insn_reservation "f3" 3
748 (and (eq_attr "cpu" "generic,fr500,tomcat")
749 (eq_attr "type" "fsmul,fdmul"))
750 "(f0|f1)+(mul0|mul1)")
752 (define_bypass 11 "f4_div" "m1,m2,m3,m4,m5,m6,m7")
753 (define_insn_reservation "f4_div" 10
754 (and (eq_attr "cpu" "generic,fr500,tomcat")
755 (eq_attr "type" "fsdiv,fddiv"))
756 "(f0|f1),(div1*9|div2*9)")
758 (define_bypass 16 "f4_root" "m1,m2,m3,m4,m5,m6,m7")
759 (define_insn_reservation "f4_root" 15
760 (and (eq_attr "cpu" "generic,fr500,tomcat")
761 (eq_attr "type" "sqrt_single,sqrt_double"))
764 (define_bypass 4 "f5" "m1,m2,m3,m4,m5,m6,m7")
765 (define_insn_reservation "f5" 3
766 (and (eq_attr "cpu" "generic,fr500,tomcat")
767 (eq_attr "type" "fmas"))
768 "(f0|f1)+(add0|add1)+(mul0|mul1)")
770 ;; The following insns are not generated by gcc now:
771 (define_insn_reservation "f6" 0 (const_int 0) "(f0|f1)+add0+add1")
772 (define_insn_reservation "f7" 0 (const_int 0) "(f0|f1)+mul0+mul1")
774 ;; Media insns. Now they are all not generated now.
775 (define_cpu_unit "m1_0" "nodiv")
776 (define_cpu_unit "m1_1" "nodiv")
777 (define_cpu_unit "m2_0" "nodiv")
778 (define_cpu_unit "m2_1" "nodiv")
779 (define_cpu_unit "m3_0" "nodiv")
780 (define_cpu_unit "m3_1" "nodiv")
781 (define_cpu_unit "m4_0" "nodiv")
782 (define_cpu_unit "m4_1" "nodiv")
783 (define_cpu_unit "m5" "nodiv")
784 (define_cpu_unit "m6" "nodiv")
785 (define_cpu_unit "m7" "nodiv")
787 (exclusion_set "m5,m6,m7" "m2_0,m2_1,m3_0,m3_1")
788 (exclusion_set "m5" "m6,m7")
789 (exclusion_set "m6" "m4_0,m4_1,m7")
790 (exclusion_set "m7" "m1_0,m1_1,add0,add1,mul0,mul1")
792 (define_bypass 2 "m1" "m1,m2,m3,m4,m5,m6,m7")
793 (define_bypass 4 "m1" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
794 (define_insn_reservation "m1" 3
795 (and (eq_attr "cpu" "generic,fr500,tomcat")
796 (eq_attr "type" "mlogic,maveh,msath,maddh,mqaddh"))
797 "(m0|m1)+(m1_0|m1_1)")
799 (define_bypass 2 "m2" "m1,m2,m3,m4,m5,m6,m7")
800 (define_bypass 4 "m2" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
801 (define_insn_reservation "m2" 3
802 (and (eq_attr "cpu" "generic,fr500,tomcat")
803 (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
804 "(m0|m1)+(m2_0|m2_1)")
806 (define_bypass 1 "m3" "m4")
807 (define_insn_reservation "m3" 2
808 (and (eq_attr "cpu" "generic,fr500,tomcat")
809 (eq_attr "type" "mclracc,mwtacc"))
810 "(m0|m1)+(m3_0|m3_1)")
812 (define_bypass 1 "m4" "m4")
813 (define_insn_reservation "m4" 2
814 (and (eq_attr "cpu" "generic,fr500,tomcat")
815 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
816 "(m0|m1)+(m4_0|m4_1)")
818 (define_bypass 2 "m5" "m1,m2,m3,m4,m5,m6,m7")
819 (define_bypass 4 "m5" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
820 (define_insn_reservation "m5" 3
821 (and (eq_attr "cpu" "generic,fr500,tomcat")
822 (eq_attr "type" "mdpackh"))
825 (define_bypass 1 "m6" "m4")
826 (define_insn_reservation "m6" 2
827 (and (eq_attr "cpu" "generic,fr500,tomcat")
828 (eq_attr "type" "mclracca"))
831 (define_bypass 2 "m7" "m1,m2,m3,m4,m5,m6,m7")
832 (define_bypass 4 "m7" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
834 (define_insn_reservation "m7" 3
835 (and (eq_attr "cpu" "generic,fr500,tomcat")
836 (eq_attr "type" "m7"))
839 ;; Unknown & multi insns starts on new cycle and the next insn starts
840 ;; on new cycle. To describe this we consider as a control insn.
841 (define_insn_reservation "unknown" 1
842 (and (eq_attr "cpu" "generic,fr500,tomcat")
843 (eq_attr "type" "unknown,multi"))
846 ;; ::::::::::::::::::::
848 ;; :: FR400 scheduler description
850 ;; ::::::::::::::::::::
852 ;; Category 2 media instructions use both media units, but can be packed
853 ;; with non-media instructions. Use fr400_m1unit to claim the M1 unit
854 ;; without claiming a slot.
856 (define_cpu_unit "fr400_m1unit" "nodiv")
858 (define_reservation "fr400_i0" "sl0_i0")
859 (define_reservation "fr400_i1" "sl1_i1")
860 (define_reservation "fr400_m0" "sl0_fm0|sl1_fm0")
861 (define_reservation "fr400_m1" "sl1_fm1")
862 (define_reservation "fr400_meither" "fr400_m0|(fr400_m1+fr400_m1unit)")
863 (define_reservation "fr400_mboth" "fr400_m0+fr400_m1unit")
864 (define_reservation "fr400_b" "sl0_b0|sl1_b0")
865 (define_reservation "fr400_c" "sl0_c")
867 ;; Name Class Units Latency
868 ;; ==== ===== ===== =======
870 ;; sethi I1 I0/I1 0 -- does not interfere with setlo
875 ;; fload I2 I0 4 -- only 3 if read by a media insn
876 ;; gstore I3 I0 0 -- provides no result
877 ;; fstore I3 I0 0 -- provides no result
880 ;; jumpl I5 I0 0 -- provides no result
882 ;; (*) The results of these instructions can be read one cycle earlier
883 ;; than indicated. The penalty given is for instructions with write-after-
884 ;; write dependencies.
886 ;; The FR400 can only do loads and stores in I0, so we there's no danger
887 ;; of memory unit collision in the same packet. There's only one divide
890 (define_insn_reservation "fr400_i1_int" 1
891 (and (eq_attr "cpu" "fr400")
892 (eq_attr "type" "int"))
895 (define_insn_reservation "fr400_i1_sethi" 0
896 (and (eq_attr "cpu" "fr400")
897 (eq_attr "type" "sethi"))
900 (define_insn_reservation "fr400_i1_setlo" 1
901 (and (eq_attr "cpu" "fr400")
902 (eq_attr "type" "setlo"))
905 (define_insn_reservation "fr400_i1_mul" 3
906 (and (eq_attr "cpu" "fr400")
907 (eq_attr "type" "mul"))
910 (define_insn_reservation "fr400_i1_div" 20
911 (and (eq_attr "cpu" "fr400")
912 (eq_attr "type" "div"))
915 (define_insn_reservation "fr400_i2_gload" 4
916 (and (eq_attr "cpu" "fr400")
917 (eq_attr "type" "gload"))
920 (define_insn_reservation "fr400_i2_fload" 4
921 (and (eq_attr "cpu" "fr400")
922 (eq_attr "type" "fload"))
925 (define_insn_reservation "fr400_i3_gstore" 0
926 (and (eq_attr "cpu" "fr400")
927 (eq_attr "type" "gstore"))
930 (define_insn_reservation "fr400_i3_fstore" 0
931 (and (eq_attr "cpu" "fr400")
932 (eq_attr "type" "fstore"))
935 (define_insn_reservation "fr400_i4_movfg" 3
936 (and (eq_attr "cpu" "fr400")
937 (eq_attr "type" "movfg"))
940 (define_insn_reservation "fr400_i4_movgf" 3
941 (and (eq_attr "cpu" "fr400")
942 (eq_attr "type" "movgf"))
945 (define_insn_reservation "fr400_i5_jumpl" 0
946 (and (eq_attr "cpu" "fr400")
947 (eq_attr "type" "jumpl"))
950 ;; The bypass between FPR loads and media instructions, described above.
954 "fr400_m1_1,fr400_m1_2,\
955 fr400_m2_1,fr400_m2_2,\
956 fr400_m3_1,fr400_m3_2,\
957 fr400_m4_1,fr400_m4_2,\
960 ;; The branch instructions all use the B unit and produce no result.
962 (define_insn_reservation "fr400_b" 0
963 (and (eq_attr "cpu" "fr400")
964 (eq_attr "type" "jump,branch,ccr,call"))
967 ;; Control instructions use the C unit, which excludes all the others.
969 (define_insn_reservation "fr400_c" 0
970 (and (eq_attr "cpu" "fr400")
971 (eq_attr "type" "spr,trap"))
974 ;; Unknown instructions use the C unit, since it requires single-operation
977 (define_insn_reservation "fr400_unknown" 1
978 (and (eq_attr "cpu" "fr400")
979 (eq_attr "type" "unknown,multi"))
982 ;; FP->FP moves are marked as "fsconv" instructions in the define_insns
983 ;; below, but are implemented on the FR400 using "mlogic" instructions.
984 ;; It's easier to class "fsconv" as a "m1:1" instruction than provide
985 ;; separate define_insns for the FR400.
987 ;; M1 instructions store their results in FPRs. Any instruction can read
988 ;; the result in the following cycle, so no penalty occurs.
990 (define_insn_reservation "fr400_m1_1" 1
991 (and (eq_attr "cpu" "fr400")
992 (eq_attr "type" "fsconv,mlogic,maveh,msath,maddh,mabsh,mset"))
995 (define_insn_reservation "fr400_m1_2" 1
996 (and (eq_attr "cpu" "fr400")
997 (eq_attr "type" "mqaddh,mqsath"))
1000 ;; M2 instructions store their results in accumulators, which are read
1001 ;; by M2 or M4 media commands. M2 instructions can read the results in
1002 ;; the following cycle, but M4 instructions must wait a cycle more.
1005 "fr400_m2_1,fr400_m2_2"
1006 "fr400_m2_1,fr400_m2_2")
1008 (define_insn_reservation "fr400_m2_1" 2
1009 (and (eq_attr "cpu" "fr400")
1010 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
1013 (define_insn_reservation "fr400_m2_2" 2
1014 (and (eq_attr "cpu" "fr400")
1015 (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
1018 ;; For our purposes, there seems to be little real difference between
1019 ;; M1 and M3 instructions. Keep them separate anyway in case the distinction
1022 (define_insn_reservation "fr400_m3_1" 1
1023 (and (eq_attr "cpu" "fr400")
1024 (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
1027 (define_insn_reservation "fr400_m3_2" 1
1028 (and (eq_attr "cpu" "fr400")
1029 (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
1032 ;; M4 instructions write to accumulators or FPRs. MOVFG and STF
1033 ;; instructions can read an FPR result in the following cycle, but
1034 ;; M-unit instructions must wait a cycle more for either kind of result.
1037 "fr400_m4_1,fr400_m4_2"
1038 "fr400_i3_fstore,fr400_i4_movfg")
1040 (define_insn_reservation "fr400_m4_1" 2
1041 (and (eq_attr "cpu" "fr400")
1042 (eq_attr "type" "mrdacc,mcut,mclracc"))
1045 (define_insn_reservation "fr400_m4_2" 2
1046 (and (eq_attr "cpu" "fr400")
1047 (eq_attr "type" "mclracca,mdcut"))
1050 ;; M5 instructions always incur a 1-cycle penalty.
1052 (define_insn_reservation "fr400_m5" 2
1053 (and (eq_attr "cpu" "fr400")
1054 (eq_attr "type" "mwtacc"))
1057 ;; ::::::::::::::::::::
1059 ;; :: Simple/FR300 scheduler description
1061 ;; ::::::::::::::::::::
1063 ;; Fr300 or simple processor. To describe it as 1 insn issue
1064 ;; processor, we use control unit.
1066 (define_insn_reservation "fr300_lat1" 1
1067 (and (eq_attr "cpu" "fr300,simple")
1068 (eq_attr "type" "!gload,fload,movfg,movgf"))
1071 (define_insn_reservation "fr300_lat2" 2
1072 (and (eq_attr "cpu" "fr300,simple")
1073 (eq_attr "type" "gload,fload,movfg,movgf"))
1077 ;; ::::::::::::::::::::
1081 ;; ::::::::::::::::::::
1083 ;; The insn attribute mechanism can be used to specify the requirements for
1084 ;; delay slots, if any, on a target machine. An instruction is said to require
1085 ;; a "delay slot" if some instructions that are physically after the
1086 ;; instruction are executed as if they were located before it. Classic
1087 ;; examples are branch and call instructions, which often execute the following
1088 ;; instruction before the branch or call is performed.
1090 ;; On some machines, conditional branch instructions can optionally "annul"
1091 ;; instructions in the delay slot. This means that the instruction will not be
1092 ;; executed for certain branch outcomes. Both instructions that annul if the
1093 ;; branch is true and instructions that annul if the branch is false are
1096 ;; Delay slot scheduling differs from instruction scheduling in that
1097 ;; determining whether an instruction needs a delay slot is dependent only
1098 ;; on the type of instruction being generated, not on data flow between the
1099 ;; instructions. See the next section for a discussion of data-dependent
1100 ;; instruction scheduling.
1102 ;; The requirement of an insn needing one or more delay slots is indicated via
1103 ;; the `define_delay' expression. It has the following form:
1105 ;; (define_delay TEST
1106 ;; [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
1107 ;; DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
1110 ;; TEST is an attribute test that indicates whether this `define_delay' applies
1111 ;; to a particular insn. If so, the number of required delay slots is
1112 ;; determined by the length of the vector specified as the second argument. An
1113 ;; insn placed in delay slot N must satisfy attribute test DELAY-N.
1114 ;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1115 ;; if the branch is true. Similarly, ANNUL-FALSE-N specifies which insns in
1116 ;; the delay slot may be annulled if the branch is false. If annulling is not
1117 ;; supported for that delay slot, `(nil)' should be coded.
1119 ;; For example, in the common case where branch and call insns require a single
1120 ;; delay slot, which may contain any insn other than a branch or call, the
1121 ;; following would be placed in the `md' file:
1123 ;; (define_delay (eq_attr "type" "branch,call")
1124 ;; [(eq_attr "type" "!branch,call") (nil) (nil)])
1126 ;; Multiple `define_delay' expressions may be specified. In this case, each
1127 ;; such expression specifies different delay slot requirements and there must
1128 ;; be no insn for which tests in two `define_delay' expressions are both true.
1130 ;; For example, if we have a machine that requires one delay slot for branches
1131 ;; but two for calls, no delay slot can contain a branch or call insn, and any
1132 ;; valid insn in the delay slot for the branch can be annulled if the branch is
1133 ;; true, we might represent this as follows:
1135 ;; (define_delay (eq_attr "type" "branch")
1136 ;; [(eq_attr "type" "!branch,call")
1137 ;; (eq_attr "type" "!branch,call")
1140 ;; (define_delay (eq_attr "type" "call")
1141 ;; [(eq_attr "type" "!branch,call") (nil) (nil)
1142 ;; (eq_attr "type" "!branch,call") (nil) (nil)])
1144 ;; Note - it is the backend's responsibility to fill any unfilled delay slots
1145 ;; at assembler generation time. This is usually done by adding a special print
1146 ;; operand to the delayed instruction, and then in the PRINT_OPERAND function
1147 ;; calling dbr_sequence_length() to determine how many delay slots were filled.
1150 ;; --------------<machine>.md-----------------
1151 ;; (define_insn "call"
1152 ;; [(call (match_operand 0 "memory_operand" "m")
1153 ;; (match_operand 1 "" ""))]
1155 ;; "call_delayed %0,%1,%2%#"
1156 ;; [(set_attr "length" "4")
1157 ;; (set_attr "type" "call")])
1159 ;; -------------<machine>.h-------------------
1160 ;; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
1162 ;; ------------<machine>.c------------------
1164 ;; machine_print_operand (file, x, code)
1172 ;; if (dbr_sequence_length () == 0)
1173 ;; fputs ("\n\tnop", file);
1176 ;; ::::::::::::::::::::
1178 ;; :: Notes on Patterns
1180 ;; ::::::::::::::::::::
1182 ;; If you need to construct a sequence of assembler instructions in order
1183 ;; to implement a pattern be sure to escape any backslashes and double quotes
1184 ;; that you use, eg:
1186 ;; (define_insn "an example"
1190 ;; { static char buffer [100];
1191 ;; sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
1196 ;; Also if there is more than one instruction, they can be separated by \\;
1197 ;; which is a space saving synonym for \\n\\t:
1199 ;; (define_insn "another example"
1203 ;; { static char buffer [100];
1204 ;; sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
1205 ;; REGNO (operands[1]));
1212 ;; ::::::::::::::::::::
1216 ;; ::::::::::::::::::::
1218 ;; Wrap moves in define_expand to prevent memory->memory moves from being
1219 ;; generated at the RTL level, which generates better code for most machines
1220 ;; which can't do mem->mem moves.
1222 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1223 ;; than M, the effect of this instruction is to store the specified value in
1224 ;; the part of the register that corresponds to mode M. The effect on the rest
1225 ;; of the register is undefined.
1227 ;; This class of patterns is special in several ways. First of all, each of
1228 ;; these names *must* be defined, because there is no other way to copy a datum
1229 ;; from one place to another.
1231 ;; Second, these patterns are not used solely in the RTL generation pass. Even
1232 ;; the reload pass can generate move insns to copy values from stack slots into
1233 ;; temporary registers. When it does so, one of the operands is a hard
1234 ;; register and the other is an operand that can need to be reloaded into a
1237 ;; Therefore, when given such a pair of operands, the pattern must
1238 ;; generate RTL which needs no reloading and needs no temporary
1239 ;; registers--no registers other than the operands. For example, if
1240 ;; you support the pattern with a `define_expand', then in such a
1241 ;; case the `define_expand' mustn't call `force_reg' or any other such
1242 ;; function which might generate new pseudo registers.
1244 ;; This requirement exists even for subword modes on a RISC machine
1245 ;; where fetching those modes from memory normally requires several
1246 ;; insns and some temporary registers. Look in `spur.md' to see how
1247 ;; the requirement can be satisfied.
1249 ;; During reload a memory reference with an invalid address may be passed as an
1250 ;; operand. Such an address will be replaced with a valid address later in the
1251 ;; reload pass. In this case, nothing may be done with the address except to
1252 ;; use it as it stands. If it is copied, it will not be replaced with a valid
1253 ;; address. No attempt should be made to make such an address into a valid
1254 ;; address and no routine (such as `change_address') that will do so may be
1255 ;; called. Note that `general_operand' will fail when applied to such an
1258 ;; The global variable `reload_in_progress' (which must be explicitly declared
1259 ;; if required) can be used to determine whether such special handling is
1262 ;; The variety of operands that have reloads depends on the rest of
1263 ;; the machine description, but typically on a RISC machine these can
1264 ;; only be pseudo registers that did not get hard registers, while on
1265 ;; other machines explicit memory references will get optional
1268 ;; If a scratch register is required to move an object to or from memory, it
1269 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
1270 ;; impossible during and after reload. If there are cases needing scratch
1271 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1272 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1273 ;; patterns `reload_inM' or `reload_outM' to handle them.
1275 ;; The constraints on a `moveM' must permit moving any hard register to any
1276 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
1277 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
1280 ;; It is obligatory to support floating point `moveM' instructions
1281 ;; into and out of any registers that can hold fixed point values,
1282 ;; because unions and structures (which have modes `SImode' or
1283 ;; `DImode') can be in those registers and they may have floating
1286 ;; There may also be a need to support fixed point `moveM' instructions in and
1287 ;; out of floating point registers. Unfortunately, I have forgotten why this
1288 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
1289 ;; rejects fixed point values in floating point registers, then the constraints
1290 ;; of the fixed point `moveM' instructions must be designed to avoid ever
1291 ;; trying to reload into a floating point register.
1293 (define_expand "movqi"
1294 [(set (match_operand:QI 0 "general_operand" "")
1295 (match_operand:QI 1 "general_operand" ""))]
1299 if (!reload_in_progress
1300 && !reload_completed
1301 && !register_operand (operands[0], QImode)
1302 && !reg_or_0_operand (operands[1], QImode))
1303 operands[1] = copy_to_mode_reg (QImode, operands[1]);
1306 (define_insn "*movqi_load"
1307 [(set (match_operand:QI 0 "register_operand" "=d,f")
1308 (match_operand:QI 1 "frv_load_operand" "m,m"))]
1310 "* return output_move_single (operands, insn);"
1311 [(set_attr "length" "4")
1312 (set_attr "type" "gload,fload")])
1314 (define_insn "*movqi_internal"
1315 [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f,d,f")
1316 (match_operand:QI 1 "move_source_operand" "L,d,d,O, d, f, f, f,GO,!m,!m"))]
1317 "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
1318 "* return output_move_single (operands, insn);"
1319 [(set_attr "length" "4")
1320 (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1322 (define_expand "movhi"
1323 [(set (match_operand:HI 0 "general_operand" "")
1324 (match_operand:HI 1 "general_operand" ""))]
1328 if (!reload_in_progress
1329 && !reload_completed
1330 && !register_operand (operands[0], HImode)
1331 && !reg_or_0_operand (operands[1], HImode))
1332 operands[1] = copy_to_mode_reg (HImode, operands[1]);
1335 (define_insn "*movhi_load"
1336 [(set (match_operand:HI 0 "register_operand" "=d,f")
1337 (match_operand:HI 1 "frv_load_operand" "m,m"))]
1339 "* return output_move_single (operands, insn);"
1340 [(set_attr "length" "4")
1341 (set_attr "type" "gload,fload")])
1343 (define_insn "*movhi_internal"
1344 [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f,d,f")
1345 (match_operand:HI 1 "move_source_operand" "L,n,d,d,O, d, f, f, f,GO,!m,!m"))]
1346 "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
1347 "* return output_move_single (operands, insn);"
1348 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4")
1349 (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1351 ;; Split 2 word load of constants into sethi/setlo instructions
1353 [(set (match_operand:HI 0 "integer_register_operand" "")
1354 (match_operand:HI 1 "int_2word_operand" ""))]
1357 (high:HI (match_dup 1)))
1359 (lo_sum:HI (match_dup 0)
1363 (define_insn "movhi_high"
1364 [(set (match_operand:HI 0 "integer_register_operand" "=d")
1365 (high:HI (match_operand:HI 1 "int_2word_operand" "i")))]
1368 [(set_attr "type" "sethi")
1369 (set_attr "length" "4")])
1371 (define_insn "movhi_lo_sum"
1372 [(set (match_operand:HI 0 "integer_register_operand" "+d")
1373 (lo_sum:HI (match_dup 0)
1374 (match_operand:HI 1 "int_2word_operand" "i")))]
1377 [(set_attr "type" "setlo")
1378 (set_attr "length" "4")])
1380 (define_expand "movsi"
1381 [(set (match_operand:SI 0 "move_destination_operand" "")
1382 (match_operand:SI 1 "move_source_operand" ""))]
1386 if (frv_emit_movsi (operands[0], operands[1]))
1390 ;; Note - it is best to only have one movsi pattern and to handle
1391 ;; all the various contingencies by the use of alternatives. This
1392 ;; allows reload the greatest amount of flexibility (since reload will
1393 ;; only choose amoungst alternatives for a selected insn, it will not
1394 ;; replace the insn with another one).
1396 ;; Unfortunately, we do have to separate out load-type moves from the rest,
1397 ;; and only allow memory source operands in the former. If we do memory and
1398 ;; constant loads in a single pattern, reload will be tempted to force
1399 ;; constants into memory when the destination is a floating-point register.
1400 ;; That may make a function use a PIC pointer when it didn't before, and we
1401 ;; cannot change PIC usage (and hence stack layout) so late in the game.
1402 ;; The resulting sequences for loading constants into FPRs are preferable
1403 ;; even when we're not generating PIC code.
1405 ;; However, if we don't accept input from memory at all in the generic
1406 ;; movsi pattern, reloads for asm instructions that reference pseudos
1407 ;; that end up assigned to memory will fail to match, because we
1408 ;; recognize them right after they're emitted, and we don't
1409 ;; re-recognize them again after the substitution for memory. So keep
1410 ;; a memory constraint available, just make sure reload won't be
1411 ;; tempted to use it.
1413 (define_insn "*movsi_load"
1414 [(set (match_operand:SI 0 "register_operand" "=d,f")
1415 (match_operand:SI 1 "frv_load_operand" "m,m"))]
1417 "* return output_move_single (operands, insn);"
1418 [(set_attr "length" "4")
1419 (set_attr "type" "gload,fload")])
1421 (define_insn "*movsi_got"
1422 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1423 (match_operand:SI 1 "got12_operand" ""))]
1426 [(set_attr "type" "int")
1427 (set_attr "length" "4")])
1429 (define_insn "*movsi_high_got"
1430 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1431 (high:SI (match_operand:SI 1 "const_unspec_operand" "")))]
1434 [(set_attr "type" "sethi")
1435 (set_attr "length" "4")])
1437 (define_insn "*movsi_lo_sum_got"
1438 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1439 (lo_sum:SI (match_operand:SI 1 "integer_register_operand" "0")
1440 (match_operand:SI 2 "const_unspec_operand" "")))]
1443 [(set_attr "type" "setlo")
1444 (set_attr "length" "4")])
1446 (define_insn "*movsi_internal"
1447 [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z,d,f")
1448 (match_operand:SI 1 "move_source_operand" "L,n,d,d,O,d,z,f,d,f,f,GO,GO,!m,!m"))]
1449 "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
1450 "* return output_move_single (operands, insn);"
1451 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4,4,4")
1452 (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr,gload,fload")])
1454 ;; Split 2 word load of constants into sethi/setlo instructions
1455 (define_insn_and_split "*movsi_2word"
1456 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1457 (match_operand:SI 1 "int_2word_operand" "i"))]
1462 (high:SI (match_dup 1)))
1464 (lo_sum:SI (match_dup 0)
1467 [(set_attr "length" "8")
1468 (set_attr "type" "multi")])
1470 (define_insn "movsi_high"
1471 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1472 (high:SI (match_operand:SI 1 "int_2word_operand" "i")))]
1475 [(set_attr "type" "sethi")
1476 (set_attr "length" "4")])
1478 (define_insn "movsi_lo_sum"
1479 [(set (match_operand:SI 0 "integer_register_operand" "+d")
1480 (lo_sum:SI (match_dup 0)
1481 (match_operand:SI 1 "int_2word_operand" "i")))]
1484 [(set_attr "type" "setlo")
1485 (set_attr "length" "4")])
1487 (define_expand "movdi"
1488 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1489 (match_operand:DI 1 "general_operand" ""))]
1493 if (!reload_in_progress
1494 && !reload_completed
1495 && !register_operand (operands[0], DImode)
1496 && !reg_or_0_operand (operands[1], DImode))
1497 operands[1] = copy_to_mode_reg (DImode, operands[1]);
1500 (define_insn "*movdi_double"
1501 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1502 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1504 && (register_operand (operands[0], DImode)
1505 || reg_or_0_operand (operands[1], DImode))"
1506 "* return output_move_double (operands, insn);"
1507 [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
1508 (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1510 (define_insn "*movdi_nodouble"
1511 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1512 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1514 && (register_operand (operands[0], DImode)
1515 || reg_or_0_operand (operands[1], DImode))"
1516 "* return output_move_double (operands, insn);"
1517 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1518 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1521 [(set (match_operand:DI 0 "register_operand" "")
1522 (match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
1525 "frv_split_double_load (operands[0], operands[1]);")
1528 [(set (match_operand:DI 0 "odd_reg_operand" "")
1529 (match_operand:DI 1 "memory_operand" ""))]
1532 "frv_split_double_load (operands[0], operands[1]);")
1535 [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
1536 (match_operand:DI 1 "reg_or_0_operand" ""))]
1539 "frv_split_double_store (operands[0], operands[1]);")
1542 [(set (match_operand:DI 0 "memory_operand" "")
1543 (match_operand:DI 1 "odd_reg_operand" ""))]
1546 "frv_split_double_store (operands[0], operands[1]);")
1549 [(set (match_operand:DI 0 "register_operand" "")
1550 (match_operand:DI 1 "register_operand" ""))]
1552 && (odd_reg_operand (operands[0], DImode)
1553 || odd_reg_operand (operands[1], DImode)
1554 || (integer_register_operand (operands[0], DImode)
1555 && integer_register_operand (operands[1], DImode))
1557 && fpr_operand (operands[0], DImode)
1558 && fpr_operand (operands[1], DImode)))"
1559 [(set (match_dup 2) (match_dup 4))
1560 (set (match_dup 3) (match_dup 5))]
1563 rtx op0 = operands[0];
1564 rtx op0_low = gen_lowpart (SImode, op0);
1565 rtx op0_high = gen_highpart (SImode, op0);
1566 rtx op1 = operands[1];
1567 rtx op1_low = gen_lowpart (SImode, op1);
1568 rtx op1_high = gen_highpart (SImode, op1);
1570 /* We normally copy the low-numbered register first. However, if the first
1571 register operand 0 is the same as the second register of operand 1, we
1572 must copy in the opposite order. */
1574 if (REGNO (op0_high) == REGNO (op1_low))
1576 operands[2] = op0_low;
1577 operands[3] = op0_high;
1578 operands[4] = op1_low;
1579 operands[5] = op1_high;
1583 operands[2] = op0_high;
1584 operands[3] = op0_low;
1585 operands[4] = op1_high;
1586 operands[5] = op1_low;
1591 [(set (match_operand:DI 0 "register_operand" "")
1592 (match_operand:DI 1 "const_int_operand" ""))]
1594 [(set (match_dup 2) (match_dup 4))
1595 (set (match_dup 3) (match_dup 1))]
1598 rtx op0 = operands[0];
1599 rtx op1 = operands[1];
1601 operands[2] = gen_highpart (SImode, op0);
1602 operands[3] = gen_lowpart (SImode, op0);
1603 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1607 [(set (match_operand:DI 0 "register_operand" "")
1608 (match_operand:DI 1 "const_double_operand" ""))]
1610 [(set (match_dup 2) (match_dup 4))
1611 (set (match_dup 3) (match_dup 5))]
1614 rtx op0 = operands[0];
1615 rtx op1 = operands[1];
1617 operands[2] = gen_highpart (SImode, op0);
1618 operands[3] = gen_lowpart (SImode, op0);
1619 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
1620 operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
1623 ;; Floating Point Moves
1625 ;; Note - Patterns for SF mode moves are compulsory, but
1626 ;; patterns for DF are optional, as GCC can synthesize them.
1628 (define_expand "movsf"
1629 [(set (match_operand:SF 0 "general_operand" "")
1630 (match_operand:SF 1 "general_operand" ""))]
1634 if (!reload_in_progress
1635 && !reload_completed
1636 && !register_operand (operands[0], SFmode)
1637 && !reg_or_0_operand (operands[1], SFmode))
1638 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
1642 [(set (match_operand:SF 0 "integer_register_operand" "")
1643 (match_operand:SF 1 "int_2word_operand" ""))]
1646 (high:SF (match_dup 1)))
1648 (lo_sum:SF (match_dup 0)
1652 (define_insn "*movsf_load_has_fprs"
1653 [(set (match_operand:SF 0 "register_operand" "=f,d")
1654 (match_operand:SF 1 "frv_load_operand" "m,m"))]
1656 "* return output_move_single (operands, insn);"
1657 [(set_attr "length" "4")
1658 (set_attr "type" "fload,gload")])
1660 (define_insn "*movsf_internal_has_fprs"
1661 [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
1662 (match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
1664 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1665 "* return output_move_single (operands, insn);"
1666 [(set_attr "length" "4,4,4,4,4,4,4,4,8")
1667 (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])
1669 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1670 ;; will all be emulated
1671 (define_insn "*movsf_internal_no_fprs"
1672 [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
1673 (match_operand:SF 1 "move_source_operand" " d,OG,dOG,m,F"))]
1675 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1676 "* return output_move_single (operands, insn);"
1677 [(set_attr "length" "4,4,4,4,8")
1678 (set_attr "type" "int,int,gstore,gload,multi")])
1680 (define_insn "movsf_high"
1681 [(set (match_operand:SF 0 "integer_register_operand" "=d")
1682 (high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
1685 [(set_attr "type" "sethi")
1686 (set_attr "length" "4")])
1688 (define_insn "movsf_lo_sum"
1689 [(set (match_operand:SF 0 "integer_register_operand" "+d")
1690 (lo_sum:SF (match_dup 0)
1691 (match_operand:SF 1 "int_2word_operand" "i")))]
1694 [(set_attr "type" "setlo")
1695 (set_attr "length" "4")])
1697 (define_expand "movdf"
1698 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1699 (match_operand:DF 1 "general_operand" ""))]
1703 if (!reload_in_progress
1704 && !reload_completed
1705 && !register_operand (operands[0], DFmode)
1706 && !reg_or_0_operand (operands[1], DFmode))
1707 operands[1] = copy_to_mode_reg (DFmode, operands[1]);
1710 (define_insn "*movdf_double"
1711 [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d,e,??d")
1712 (match_operand:DF 1 "move_source_operand" " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO,F,F"))]
1714 && (register_operand (operands[0], DFmode)
1715 || reg_or_0_operand (operands[1], DFmode))"
1716 "* return output_move_double (operands, insn);"
1717 [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8,16,16")
1718 (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi,multi,multi")])
1720 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1721 ;; will all be emulated
1722 (define_insn "*movdf_nodouble"
1723 [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1724 (match_operand:DF 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1726 && (register_operand (operands[0], DFmode)
1727 || reg_or_0_operand (operands[1], DFmode))"
1728 "* return output_move_double (operands, insn);"
1729 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1730 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1733 [(set (match_operand:DF 0 "register_operand" "")
1734 (match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
1737 "frv_split_double_load (operands[0], operands[1]);")
1740 [(set (match_operand:DF 0 "odd_reg_operand" "")
1741 (match_operand:DF 1 "memory_operand" ""))]
1744 "frv_split_double_load (operands[0], operands[1]);")
1747 [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
1748 (match_operand:DF 1 "reg_or_0_operand" ""))]
1751 "frv_split_double_store (operands[0], operands[1]);")
1754 [(set (match_operand:DF 0 "memory_operand" "")
1755 (match_operand:DF 1 "odd_reg_operand" ""))]
1758 "frv_split_double_store (operands[0], operands[1]);")
1761 [(set (match_operand:DF 0 "register_operand" "")
1762 (match_operand:DF 1 "register_operand" ""))]
1764 && (odd_reg_operand (operands[0], DFmode)
1765 || odd_reg_operand (operands[1], DFmode)
1766 || (integer_register_operand (operands[0], DFmode)
1767 && integer_register_operand (operands[1], DFmode))
1769 && fpr_operand (operands[0], DFmode)
1770 && fpr_operand (operands[1], DFmode)))"
1771 [(set (match_dup 2) (match_dup 4))
1772 (set (match_dup 3) (match_dup 5))]
1775 rtx op0 = operands[0];
1776 rtx op0_low = gen_lowpart (SImode, op0);
1777 rtx op0_high = gen_highpart (SImode, op0);
1778 rtx op1 = operands[1];
1779 rtx op1_low = gen_lowpart (SImode, op1);
1780 rtx op1_high = gen_highpart (SImode, op1);
1782 /* We normally copy the low-numbered register first. However, if the first
1783 register operand 0 is the same as the second register of operand 1, we
1784 must copy in the opposite order. */
1786 if (REGNO (op0_high) == REGNO (op1_low))
1788 operands[2] = op0_low;
1789 operands[3] = op0_high;
1790 operands[4] = op1_low;
1791 operands[5] = op1_high;
1795 operands[2] = op0_high;
1796 operands[3] = op0_low;
1797 operands[4] = op1_high;
1798 operands[5] = op1_low;
1803 [(set (match_operand:DF 0 "register_operand" "")
1804 (match_operand:DF 1 "const_int_operand" ""))]
1806 [(set (match_dup 2) (match_dup 4))
1807 (set (match_dup 3) (match_dup 1))]
1810 rtx op0 = operands[0];
1811 rtx op1 = operands[1];
1813 operands[2] = gen_highpart (SImode, op0);
1814 operands[3] = gen_lowpart (SImode, op0);
1815 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1819 [(set (match_operand:DF 0 "register_operand" "")
1820 (match_operand:DF 1 "const_double_operand" ""))]
1822 [(set (match_dup 2) (match_dup 4))
1823 (set (match_dup 3) (match_dup 5))]
1826 rtx op0 = operands[0];
1827 rtx op1 = operands[1];
1831 REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
1832 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1834 operands[2] = gen_highpart (SImode, op0);
1835 operands[3] = gen_lowpart (SImode, op0);
1836 operands[4] = GEN_INT (l[0]);
1837 operands[5] = GEN_INT (l[1]);
1840 ;; String/block move insn.
1841 ;; Argument 0 is the destination
1842 ;; Argument 1 is the source
1843 ;; Argument 2 is the length
1844 ;; Argument 3 is the alignment
1846 (define_expand "movmemsi"
1847 [(parallel [(set (match_operand:BLK 0 "" "")
1848 (match_operand:BLK 1 "" ""))
1849 (use (match_operand:SI 2 "" ""))
1850 (use (match_operand:SI 3 "" ""))])]
1854 if (frv_expand_block_move (operands))
1860 ;; String/block clear insn.
1861 ;; Argument 0 is the destination
1862 ;; Argument 1 is the length
1863 ;; Argument 2 is the alignment
1865 (define_expand "clrmemsi"
1866 [(parallel [(set (match_operand:BLK 0 "" "")
1868 (use (match_operand:SI 1 "" ""))
1869 (use (match_operand:SI 2 "" ""))])]
1873 if (frv_expand_block_clear (operands))
1880 ;; ::::::::::::::::::::
1882 ;; :: Reload CC registers
1884 ;; ::::::::::::::::::::
1886 ;; Use as a define_expand so that cse/gcse/combine can't accidentally
1887 ;; create movcc insns.
1889 (define_expand "movcc"
1890 [(parallel [(set (match_operand:CC 0 "move_destination_operand" "")
1891 (match_operand:CC 1 "move_source_operand" ""))
1892 (clobber (match_dup 2))])]
1896 if (! reload_in_progress && ! reload_completed)
1899 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
1902 (define_insn "*internal_movcc"
1903 [(set (match_operand:CC 0 "move_destination_operand" "=t,d,d,m,d")
1904 (match_operand:CC 1 "move_source_operand" "d,d,m,d,t"))
1905 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
1906 "reload_in_progress || reload_completed"
1913 [(set_attr "length" "4,4,4,4,20")
1914 (set_attr "type" "int,int,gload,gstore,multi")])
1916 ;; To move an ICC value to a GPR for a signed comparison, we create a value
1917 ;; that when compared to 0, sets the N and Z flags appropriately (we don't care
1918 ;; about the V and C flags, since these comparisons are signed).
1921 [(set (match_operand:CC 0 "integer_register_operand" "")
1922 (match_operand:CC 1 "icc_operand" ""))
1923 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
1924 "reload_in_progress || reload_completed"
1928 rtx dest = simplify_gen_subreg (SImode, operands[0], CCmode, 0);
1929 rtx icc = operands[1];
1930 rtx icr = operands[2];
1934 emit_insn (gen_rtx_SET (VOIDmode, icr,
1935 gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
1937 emit_insn (gen_movsi (dest, const1_rtx));
1939 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
1940 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
1941 gen_rtx_SET (VOIDmode, dest,
1942 gen_rtx_NEG (SImode, dest))));
1944 emit_insn (gen_rtx_SET (VOIDmode, icr,
1945 gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
1947 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
1948 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
1949 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
1951 operands[3] = get_insns ();
1955 (define_expand "reload_incc"
1956 [(parallel [(set (match_operand:CC 2 "integer_register_operand" "=&d")
1957 (match_operand:CC 1 "memory_operand" "m"))
1958 (clobber (match_scratch:CC_CCR 3 ""))])
1959 (parallel [(set (match_operand:CC 0 "icc_operand" "=t")
1961 (clobber (match_scratch:CC_CCR 4 ""))])]
1965 (define_expand "reload_outcc"
1966 [(parallel [(set (match_operand:CC 2 "integer_register_operand" "=&d")
1967 (match_operand:CC 1 "icc_operand" "t"))
1968 (clobber (match_dup 3))])
1969 (parallel [(set (match_operand:CC 0 "memory_operand" "=m")
1971 (clobber (match_scratch:CC_CCR 4 ""))])]
1973 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
1975 ;; Reload CC_UNSmode for unsigned integer comparisons
1976 ;; Use define_expand so that cse/gcse/combine can't create movcc_uns insns
1978 (define_expand "movcc_uns"
1979 [(parallel [(set (match_operand:CC_UNS 0 "move_destination_operand" "")
1980 (match_operand:CC_UNS 1 "move_source_operand" ""))
1981 (clobber (match_dup 2))])]
1985 if (! reload_in_progress && ! reload_completed)
1987 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
1990 (define_insn "*internal_movcc_uns"
1991 [(set (match_operand:CC_UNS 0 "move_destination_operand" "=t,d,d,m,d")
1992 (match_operand:CC_UNS 1 "move_source_operand" "d,d,m,d,t"))
1993 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
1994 "reload_in_progress || reload_completed"
2001 [(set_attr "length" "4,4,4,4,20")
2002 (set_attr "type" "int,int,gload,gstore,multi")])
2004 ;; To move an ICC value to a GPR for an unsigned comparison, we create a value
2005 ;; that when compared to 1, sets the Z, V, and C flags appropriately (we don't
2006 ;; care about the N flag, since these comparisons are unsigned).
2009 [(set (match_operand:CC_UNS 0 "integer_register_operand" "")
2010 (match_operand:CC_UNS 1 "icc_operand" ""))
2011 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2012 "reload_in_progress || reload_completed"
2016 rtx dest = simplify_gen_subreg (SImode, operands[0], CC_UNSmode, 0);
2017 rtx icc = operands[1];
2018 rtx icr = operands[2];
2022 emit_insn (gen_rtx_SET (VOIDmode, icr,
2023 gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2025 emit_insn (gen_movsi (dest, const1_rtx));
2027 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2028 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2029 gen_addsi3 (dest, dest, dest)));
2031 emit_insn (gen_rtx_SET (VOIDmode, icr,
2032 gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2034 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2035 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2036 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2038 operands[3] = get_insns ();
2042 (define_expand "reload_incc_uns"
2043 [(parallel [(set (match_operand:CC_UNS 2 "integer_register_operand" "=&d")
2044 (match_operand:CC_UNS 1 "memory_operand" "m"))
2045 (clobber (match_scratch:CC_CCR 3 ""))])
2046 (parallel [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
2048 (clobber (match_scratch:CC_CCR 4 ""))])]
2052 (define_expand "reload_outcc_uns"
2053 [(parallel [(set (match_operand:CC_UNS 2 "integer_register_operand" "=&d")
2054 (match_operand:CC_UNS 1 "icc_operand" "t"))
2055 (clobber (match_dup 3))])
2056 (parallel [(set (match_operand:CC_UNS 0 "memory_operand" "=m")
2058 (clobber (match_scratch:CC_CCR 4 ""))])]
2060 "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
2062 ;; Reload CC_FPmode for floating point comparisons
2063 ;; We use a define_expand here so that cse/gcse/combine can't accidentally
2064 ;; create movcc insns. If this was a named define_insn, we would not be able
2065 ;; to make it conditional on reload.
2067 (define_expand "movcc_fp"
2068 [(set (match_operand:CC_FP 0 "move_destination_operand" "")
2069 (match_operand:CC_FP 1 "move_source_operand" ""))]
2073 if (! reload_in_progress && ! reload_completed)
2077 (define_insn "*movcc_fp_internal"
2078 [(set (match_operand:CC_FP 0 "move_destination_operand" "=d,d,d,m")
2079 (match_operand:CC_FP 1 "move_source_operand" "u,d,m,d"))]
2080 "TARGET_HAS_FPRS && (reload_in_progress || reload_completed)"
2086 [(set_attr "length" "12,4,4,4")
2087 (set_attr "type" "multi,int,gload,gstore")])
2090 (define_expand "reload_incc_fp"
2091 [(match_operand:CC_FP 0 "fcc_operand" "=u")
2092 (match_operand:CC_FP 1 "memory_operand" "m")
2093 (match_operand:TI 2 "integer_register_operand" "=&d")]
2097 rtx cc_op2 = simplify_gen_subreg (CC_FPmode, operands[2], TImode, 0);
2098 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], TImode, 0);
2099 rtx temp1 = simplify_gen_subreg (SImode, operands[2], TImode, 4);
2100 rtx temp2 = simplify_gen_subreg (SImode, operands[2], TImode, 8);
2101 int shift = CC_SHIFT_RIGHT (REGNO (operands[0]));
2104 emit_insn (gen_movcc_fp (cc_op2, operands[1]));
2106 emit_insn (gen_ashlsi3 (int_op2, int_op2, GEN_INT (shift)));
2108 mask = ~ ((HOST_WIDE_INT)CC_MASK << shift);
2109 emit_insn (gen_movsi (temp1, GEN_INT (mask)));
2110 emit_insn (gen_update_fcc (operands[0], int_op2, temp1, temp2));
2114 (define_expand "reload_outcc_fp"
2115 [(set (match_operand:CC_FP 2 "integer_register_operand" "=&d")
2116 (match_operand:CC_FP 1 "fcc_operand" "u"))
2117 (set (match_operand:CC_FP 0 "memory_operand" "=m")
2122 ;; Convert a FCC value to gpr
2123 (define_insn "read_fcc"
2124 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2125 (unspec:SI [(match_operand:CC_FP 1 "fcc_operand" "u")]
2129 [(set_attr "type" "spr")
2130 (set_attr "length" "4")])
2133 [(set (match_operand:CC_FP 0 "integer_register_operand" "")
2134 (match_operand:CC_FP 1 "fcc_operand" ""))]
2135 "reload_completed && TARGET_HAS_FPRS"
2139 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_FPmode, 0);
2140 int shift = CC_SHIFT_RIGHT (REGNO (operands[1]));
2144 emit_insn (gen_read_fcc (int_op0, operands[1]));
2146 emit_insn (gen_lshrsi3 (int_op0, int_op0, GEN_INT (shift)));
2148 emit_insn (gen_andsi3 (int_op0, int_op0, GEN_INT (CC_MASK)));
2150 operands[2] = get_insns ();
2154 ;; Move a gpr value to FCC.
2156 ;; Operand1 = reloaded value shifted appropriately
2157 ;; Operand2 = mask to eliminate current register
2158 ;; Operand3 = temporary to load/store ccr
2159 (define_insn "update_fcc"
2160 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
2161 (unspec:CC_FP [(match_operand:SI 1 "integer_register_operand" "d")
2162 (match_operand:SI 2 "integer_register_operand" "d")]
2164 (clobber (match_operand:SI 3 "integer_register_operand" "=&d"))]
2166 "movsg ccr, %3\;and %2, %3, %3\;or %1, %3, %3\;movgs %3, ccr"
2167 [(set_attr "type" "multi")
2168 (set_attr "length" "16")])
2170 ;; Reload CC_CCRmode for conditional execution registers
2171 (define_insn "movcc_ccr"
2172 [(set (match_operand:CC_CCR 0 "move_destination_operand" "=d,d,d,m,v,?w,C,d")
2173 (match_operand:CC_CCR 1 "move_source_operand" "C,d,m,d,n,n,C,L"))]
2184 [(set_attr "length" "8,4,4,4,8,12,4,4")
2185 (set_attr "type" "multi,int,gload,gstore,multi,multi,ccr,int")])
2187 (define_expand "reload_incc_ccr"
2188 [(match_operand:CC_CCR 0 "cr_operand" "=C")
2189 (match_operand:CC_CCR 1 "memory_operand" "m")
2190 (match_operand:CC_CCR 2 "integer_register_operand" "=&d")]
2194 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2195 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], CC_CCRmode, 0);
2196 rtx icr = (ICR_P (REGNO (operands[0]))
2197 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2199 emit_insn (gen_movcc_ccr (operands[2], operands[1]));
2200 emit_insn (gen_cmpsi_cc (icc, int_op2, const0_rtx));
2201 emit_insn (gen_movcc_ccr (icr, gen_rtx_NE (CC_CCRmode, icc, const0_rtx)));
2203 if (! ICR_P (REGNO (operands[0])))
2204 emit_insn (gen_movcc_ccr (operands[0], icr));
2209 (define_expand "reload_outcc_ccr"
2210 [(set (match_operand:CC_CCR 2 "integer_register_operand" "=&d")
2211 (match_operand:CC_CCR 1 "cr_operand" "C"))
2212 (set (match_operand:CC_CCR 0 "memory_operand" "=m")
2218 [(set (match_operand:CC_CCR 0 "integer_register_operand" "")
2219 (match_operand:CC_CCR 1 "cr_operand" ""))]
2224 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_CCRmode, 0);
2227 emit_move_insn (operands[0], const1_rtx);
2228 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2229 gen_rtx_EQ (CC_CCRmode,
2232 gen_rtx_SET (VOIDmode, int_op0,
2235 operands[2] = get_insns ();
2240 [(set (match_operand:CC_CCR 0 "cr_operand" "")
2241 (match_operand:CC_CCR 1 "const_int_operand" ""))]
2246 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2247 rtx r0 = gen_rtx_REG (SImode, GPR_FIRST);
2248 rtx icr = (ICR_P (REGNO (operands[0]))
2249 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2253 emit_insn (gen_cmpsi_cc (icc, r0, const0_rtx));
2255 emit_insn (gen_movcc_ccr (icr,
2256 gen_rtx_fmt_ee (((INTVAL (operands[1]) == 0)
2257 ? EQ : NE), CC_CCRmode,
2260 if (! ICR_P (REGNO (operands[0])))
2261 emit_insn (gen_movcc_ccr (operands[0], icr));
2263 operands[2] = get_insns ();
2268 ;; ::::::::::::::::::::
2272 ;; ::::::::::::::::::::
2274 ;; Signed conversions from a smaller integer to a larger integer
2276 ;; These operations are optional. If they are not
2277 ;; present GCC will synthesize them for itself
2278 ;; Even though frv does not provide these instructions, we define them
2279 ;; to allow load + sign extend to be collapsed together
2280 (define_insn "extendqihi2"
2281 [(set (match_operand:HI 0 "integer_register_operand" "=d,d")
2282 (sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2287 [(set_attr "length" "8,4")
2288 (set_attr "type" "multi,gload")])
2291 [(set (match_operand:HI 0 "integer_register_operand" "")
2292 (sign_extend:HI (match_operand:QI 1 "integer_register_operand" "")))]
2298 rtx op0 = gen_lowpart (SImode, operands[0]);
2299 rtx op1 = gen_lowpart (SImode, operands[1]);
2300 rtx shift = GEN_INT (24);
2302 operands[2] = gen_ashlsi3 (op0, op1, shift);
2303 operands[3] = gen_ashrsi3 (op0, op0, shift);
2306 (define_insn "extendqisi2"
2307 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2308 (sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2313 [(set_attr "length" "8,4")
2314 (set_attr "type" "multi,gload")])
2317 [(set (match_operand:SI 0 "integer_register_operand" "")
2318 (sign_extend:SI (match_operand:QI 1 "integer_register_operand" "")))]
2324 rtx op0 = gen_lowpart (SImode, operands[0]);
2325 rtx op1 = gen_lowpart (SImode, operands[1]);
2326 rtx shift = GEN_INT (24);
2328 operands[2] = gen_ashlsi3 (op0, op1, shift);
2329 operands[3] = gen_ashrsi3 (op0, op0, shift);
2332 ;;(define_insn "extendqidi2"
2333 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2334 ;; (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2336 ;; "extendqihi2 %0,%1"
2337 ;; [(set_attr "length" "4")])
2339 (define_insn "extendhisi2"
2340 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2341 (sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,m")))]
2346 [(set_attr "length" "8,4")
2347 (set_attr "type" "multi,gload")])
2350 [(set (match_operand:SI 0 "integer_register_operand" "")
2351 (sign_extend:SI (match_operand:HI 1 "integer_register_operand" "")))]
2357 rtx op0 = gen_lowpart (SImode, operands[0]);
2358 rtx op1 = gen_lowpart (SImode, operands[1]);
2359 rtx shift = GEN_INT (16);
2361 operands[2] = gen_ashlsi3 (op0, op1, shift);
2362 operands[3] = gen_ashrsi3 (op0, op0, shift);
2365 ;;(define_insn "extendhidi2"
2366 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2367 ;; (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2369 ;; "extendhihi2 %0,%1"
2370 ;; [(set_attr "length" "4")])
2372 ;;(define_insn "extendsidi2"
2373 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2374 ;; (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2376 ;; "extendsidi2 %0,%1"
2377 ;; [(set_attr "length" "4")])
2379 ;; Unsigned conversions from a smaller integer to a larger integer
2380 (define_insn "zero_extendqihi2"
2381 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
2383 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2389 [(set_attr "length" "4")
2390 (set_attr "type" "int,int,gload")])
2392 (define_insn "zero_extendqisi2"
2393 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
2395 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2401 [(set_attr "length" "4")
2402 (set_attr "type" "int,int,gload")])
2404 ;;(define_insn "zero_extendqidi2"
2405 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2406 ;; (zero_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2408 ;; "zero_extendqihi2 %0,%1"
2409 ;; [(set_attr "length" "4")])
2411 ;; Do not set the type for the sethi to "sethi", since the scheduler will think
2412 ;; the sethi takes 0 cycles as part of allowing sethi/setlo to be in the same
2413 ;; VLIW instruction.
2414 (define_insn "zero_extendhisi2"
2415 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2416 (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "0,m")))]
2421 [(set_attr "length" "4")
2422 (set_attr "type" "int,gload")])
2424 ;;(define_insn "zero_extendhidi2"
2425 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2426 ;; (zero_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2428 ;; "zero_extendhihi2 %0,%1"
2429 ;; [(set_attr "length" "4")])
2431 ;;(define_insn "zero_extendsidi2"
2432 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2433 ;; (zero_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2435 ;; "zero_extendsidi2 %0,%1"
2436 ;; [(set_attr "length" "4")])
2438 ;;;; Convert between floating point types of different sizes.
2440 ;;(define_insn "extendsfdf2"
2441 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2442 ;; (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
2444 ;; "extendsfdf2 %0,%1"
2445 ;; [(set_attr "length" "4")])
2447 ;;(define_insn "truncdfsf2"
2448 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2449 ;; (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
2451 ;; "truncdfsf2 %0,%1"
2452 ;; [(set_attr "length" "4")])
2454 ;;;; Convert between signed integer types and floating point.
2455 (define_insn "floatsisf2"
2456 [(set (match_operand:SF 0 "fpr_operand" "=f")
2457 (float:SF (match_operand:SI 1 "fpr_operand" "f")))]
2460 [(set_attr "length" "4")
2461 (set_attr "type" "fsconv")])
2463 (define_insn "floatsidf2"
2464 [(set (match_operand:DF 0 "fpr_operand" "=h")
2465 (float:DF (match_operand:SI 1 "fpr_operand" "f")))]
2466 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2468 [(set_attr "length" "4")
2469 (set_attr "type" "fdconv")])
2471 ;;(define_insn "floatdisf2"
2472 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2473 ;; (float:SF (match_operand:DI 1 "register_operand" "r")))]
2475 ;; "floatdisf2 %0,%1"
2476 ;; [(set_attr "length" "4")])
2478 ;;(define_insn "floatdidf2"
2479 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2480 ;; (float:DF (match_operand:DI 1 "register_operand" "r")))]
2482 ;; "floatdidf2 %0,%1"
2483 ;; [(set_attr "length" "4")])
2485 (define_insn "fix_truncsfsi2"
2486 [(set (match_operand:SI 0 "fpr_operand" "=f")
2487 (fix:SI (match_operand:SF 1 "fpr_operand" "f")))]
2490 [(set_attr "length" "4")
2491 (set_attr "type" "fsconv")])
2493 (define_insn "fix_truncdfsi2"
2494 [(set (match_operand:SI 0 "fpr_operand" "=f")
2495 (fix:SI (match_operand:DF 1 "fpr_operand" "h")))]
2496 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2498 [(set_attr "length" "4")
2499 (set_attr "type" "fdconv")])
2501 ;;(define_insn "fix_truncsfdi2"
2502 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2503 ;; (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2505 ;; "fix_truncsfdi2 %0,%1"
2506 ;; [(set_attr "length" "4")])
2508 ;;(define_insn "fix_truncdfdi2"
2509 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2510 ;; (fix:DI (match_operand:DF 1 "register_operand" "r")))]
2512 ;; "fix_truncdfdi2 %0,%1"
2513 ;; [(set_attr "length" "4")])
2515 ;;;; Convert between unsigned integer types and floating point.
2517 ;;(define_insn "floatunssisf2"
2518 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2519 ;; (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
2521 ;; "floatunssisf2 %0,%1"
2522 ;; [(set_attr "length" "4")])
2524 ;;(define_insn "floatunssidf2"
2525 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2526 ;; (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
2528 ;; "floatunssidf2 %0,%1"
2529 ;; [(set_attr "length" "4")])
2531 ;;(define_insn "floatunsdisf2"
2532 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2533 ;; (unsigned_float:SF (match_operand:DI 1 "register_operand" "r")))]
2535 ;; "floatunsdisf2 %0,%1"
2536 ;; [(set_attr "length" "4")])
2538 ;;(define_insn "floatunsdidf2"
2539 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2540 ;; (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
2542 ;; "floatunsdidf2 %0,%1"
2543 ;; [(set_attr "length" "4")])
2545 ;;(define_insn "fixuns_truncsfsi2"
2546 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2547 ;; (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2549 ;; "fixuns_truncsfsi2 %0,%1"
2550 ;; [(set_attr "length" "4")])
2552 ;;(define_insn "fixuns_truncdfsi2"
2553 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2554 ;; (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
2556 ;; "fixuns_truncdfsi2 %0,%1"
2557 ;; [(set_attr "length" "4")])
2559 ;;(define_insn "fixuns_truncsfdi2"
2560 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2561 ;; (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2563 ;; "fixuns_truncsfdi2 %0,%1"
2564 ;; [(set_attr "length" "4")])
2566 ;;(define_insn "fixuns_truncdfdi2"
2567 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2568 ;; (unsigned_fix:DI (match_operand:DF 1 "register_operand" "r")))]
2570 ;; "fixuns_truncdfdi2 %0,%1"
2571 ;; [(set_attr "length" "4")])
2574 ;; ::::::::::::::::::::
2576 ;; :: 32 bit Integer arithmetic
2578 ;; ::::::::::::::::::::
2581 (define_insn "addsi3"
2582 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2583 (plus:SI (match_operand:SI 1 "integer_register_operand" "%d")
2584 (match_operand:SI 2 "gpr_or_int12_operand" "dNOPQ")))]
2587 [(set_attr "length" "4")
2588 (set_attr "type" "int")])
2590 ;; Subtraction. No need to worry about constants, since the compiler
2591 ;; canonicalizes them into addsi3's. We prevent SUBREG's here to work around a
2592 ;; combine bug, that combines the 32x32->upper 32 bit multiply that uses a
2593 ;; SUBREG with a minus that shows up in modulus by constants.
2594 (define_insn "subsi3"
2595 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2596 (minus:SI (match_operand:SI 1 "gpr_no_subreg_operand" "d")
2597 (match_operand:SI 2 "gpr_no_subreg_operand" "d")))]
2600 [(set_attr "length" "4")
2601 (set_attr "type" "int")])
2603 ;; Signed multiplication producing 64 bit results from 32 bit inputs
2604 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
2605 ;; will do the 32x32->64 bit multiply and use the bottom word.
2606 (define_expand "mulsidi3"
2607 [(set (match_operand:DI 0 "integer_register_operand" "")
2608 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2609 (sign_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2613 if (GET_CODE (operands[2]) == CONST_INT)
2615 emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
2620 (define_insn "*mulsidi3_reg"
2621 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2622 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2623 (sign_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2626 [(set_attr "length" "4")
2627 (set_attr "type" "mul")])
2629 (define_insn "mulsidi3_const"
2630 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2631 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2632 (match_operand:SI 2 "int12_operand" "NOP")))]
2635 [(set_attr "length" "4")
2636 (set_attr "type" "mul")])
2638 ;; Unsigned multiplication producing 64 bit results from 32 bit inputs
2639 (define_expand "umulsidi3"
2640 [(set (match_operand:DI 0 "even_gpr_operand" "")
2641 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2642 (zero_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2646 if (GET_CODE (operands[2]) == CONST_INT)
2648 emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
2653 (define_insn "*mulsidi3_reg"
2654 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2655 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2656 (zero_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2659 [(set_attr "length" "4")
2660 (set_attr "type" "mul")])
2662 (define_insn "umulsidi3_const"
2663 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2664 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2665 (match_operand:SI 2 "int12_operand" "NOP")))]
2668 [(set_attr "length" "4")
2669 (set_attr "type" "mul")])
2672 (define_insn "divsi3"
2673 [(set (match_operand:SI 0 "register_operand" "=d,d")
2674 (div:SI (match_operand:SI 1 "register_operand" "d,d")
2675 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
2678 [(set_attr "length" "4")
2679 (set_attr "type" "div")])
2681 ;; Unsigned Division
2682 (define_insn "udivsi3"
2683 [(set (match_operand:SI 0 "register_operand" "=d,d")
2684 (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
2685 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
2688 [(set_attr "length" "4")
2689 (set_attr "type" "div")])
2692 (define_insn "negsi2"
2693 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2694 (neg:SI (match_operand:SI 1 "integer_register_operand" "d")))]
2697 [(set_attr "length" "4")
2698 (set_attr "type" "int")])
2700 ;; Find first one bit
2701 ;; (define_insn "ffssi2"
2702 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2703 ;; (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
2706 ;; [(set_attr "length" "4")])
2709 ;; ::::::::::::::::::::
2711 ;; :: 64 bit Integer arithmetic
2713 ;; ::::::::::::::::::::
2716 (define_expand "adddi3"
2717 [(parallel [(set (match_operand:DI 0 "integer_register_operand" "")
2718 (plus:DI (match_operand:DI 1 "integer_register_operand" "")
2719 (match_operand:DI 2 "gpr_or_int10_operand" "")))
2720 (clobber (match_scratch:CC 3 ""))])]
2724 if (GET_CODE (operands[2]) == CONST_INT
2725 && INTVAL (operands[2]) == -2048
2727 operands[2] = force_reg (DImode, operands[2]);
2730 (define_insn_and_split "*adddi3_internal"
2731 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e,&e,e,&e,e")
2732 (plus:DI (match_operand:DI 1 "integer_register_operand" "%e,0,e,e,0,e,0")
2733 (match_operand:DI 2 "gpr_or_int10_operand" "e,e,0,N,N,OP,OP")))
2734 (clobber (match_scratch:CC 3 "=t,t,t,t,t,t,t"))]
2735 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -2048"
2742 rtx op0_high = gen_highpart (SImode, operands[0]);
2743 rtx op1_high = gen_highpart (SImode, operands[1]);
2744 rtx op0_low = gen_lowpart (SImode, operands[0]);
2745 rtx op1_low = gen_lowpart (SImode, operands[1]);
2746 rtx op2 = operands[2];
2747 rtx op3 = operands[3];
2749 if (GET_CODE (op2) != CONST_INT)
2751 rtx op2_high = gen_highpart (SImode, operands[2]);
2752 rtx op2_low = gen_lowpart (SImode, operands[2]);
2753 operands[4] = gen_adddi3_lower (op0_low, op1_low, op2_low, op3);
2754 operands[5] = gen_adddi3_upper (op0_high, op1_high, op2_high, op3);
2756 else if (INTVAL (op2) >= 0)
2758 operands[4] = gen_adddi3_lower (op0_low, op1_low, op2, op3);
2759 operands[5] = gen_adddi3_upper (op0_high, op1_high, const0_rtx, op3);
2763 operands[4] = gen_subdi3_lower (op0_low, op1_low,
2764 GEN_INT (- INTVAL (op2)), op3);
2765 operands[5] = gen_subdi3_upper (op0_high, op1_high, const0_rtx, op3);
2768 [(set_attr "length" "8")
2769 (set_attr "type" "multi")])
2771 ;; Subtraction No need to worry about constants, since the compiler
2772 ;; canonicalizes them into adddi3's.
2773 (define_insn_and_split "subdi3"
2774 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e")
2775 (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e")
2776 (match_operand:DI 2 "integer_register_operand" "e,e,0")))
2777 (clobber (match_scratch:CC 3 "=t,t,t"))]
2785 rtx op0_high = gen_highpart (SImode, operands[0]);
2786 rtx op1_high = gen_highpart (SImode, operands[1]);
2787 rtx op2_high = gen_highpart (SImode, operands[2]);
2788 rtx op0_low = gen_lowpart (SImode, operands[0]);
2789 rtx op1_low = gen_lowpart (SImode, operands[1]);
2790 rtx op2_low = gen_lowpart (SImode, operands[2]);
2791 rtx op3 = operands[3];
2793 operands[4] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
2794 operands[5] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
2796 [(set_attr "length" "8")
2797 (set_attr "type" "multi")])
2799 ;; Patterns for addsi3/subdi3 after splitting
2800 (define_insn "adddi3_lower"
2801 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2802 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
2803 (match_operand:SI 2 "gpr_or_int10_operand" "dOP")))
2804 (set (match_operand:CC 3 "icc_operand" "=t")
2805 (compare:CC (plus:SI (match_dup 1)
2808 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 0"
2809 "add%I2cc %1,%2,%0,%3"
2810 [(set_attr "length" "4")
2811 (set_attr "type" "int")])
2813 (define_insn "adddi3_upper"
2814 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2815 (plus:SI (match_operand:SI 1 "integer_register_operand" "d,d")
2816 (plus:SI (match_operand:SI 2 "reg_or_0_operand" "d,O")
2817 (match_operand:CC 3 "icc_operand" "t,t"))))]
2822 [(set_attr "length" "4")
2823 (set_attr "type" "int")])
2825 (define_insn "subdi3_lower"
2826 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2827 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
2828 (match_operand:SI 2 "gpr_or_int10_operand" "dOP")))
2829 (set (match_operand:CC 3 "icc_operand" "=t")
2830 (compare:CC (plus:SI (match_dup 1)
2833 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 0"
2834 "sub%I2cc %1,%2,%0,%3"
2835 [(set_attr "length" "4")
2836 (set_attr "type" "int")])
2838 (define_insn "subdi3_upper"
2839 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2840 (minus:SI (match_operand:SI 1 "integer_register_operand" "d,d")
2841 (minus:SI (match_operand:SI 2 "reg_or_0_operand" "d,O")
2842 (match_operand:CC 3 "icc_operand" "t,t"))))]
2847 [(set_attr "length" "4")
2848 (set_attr "type" "int")])
2850 (define_insn_and_split "negdi2"
2851 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
2852 (neg:DI (match_operand:DI 1 "integer_register_operand" "e,0")))
2853 (clobber (match_scratch:CC 2 "=t,t"))]
2861 rtx op0_high = gen_highpart (SImode, operands[0]);
2862 rtx op1_high = gen_rtx_REG (SImode, GPR_FIRST);
2863 rtx op2_high = gen_highpart (SImode, operands[1]);
2864 rtx op0_low = gen_lowpart (SImode, operands[0]);
2865 rtx op1_low = op1_high;
2866 rtx op2_low = gen_lowpart (SImode, operands[1]);
2867 rtx op3 = operands[2];
2869 operands[3] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
2870 operands[4] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
2872 [(set_attr "length" "8")
2873 (set_attr "type" "multi")])
2875 ;; Multiplication (same size)
2876 ;; (define_insn "muldi3"
2877 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2878 ;; (mult:DI (match_operand:DI 1 "register_operand" "%r")
2879 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
2881 ;; "muldi3 %0,%1,%2"
2882 ;; [(set_attr "length" "4")])
2885 ;; (define_insn "divdi3"
2886 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2887 ;; (div:DI (match_operand:DI 1 "register_operand" "r")
2888 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
2890 ;; "divdi3 %0,%1,%2"
2891 ;; [(set_attr "length" "4")])
2893 ;; Undsgned Division
2894 ;; (define_insn "udivdi3"
2895 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2896 ;; (udiv:DI (match_operand:DI 1 "register_operand" "r")
2897 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
2899 ;; "udivdi3 %0,%1,%2"
2900 ;; [(set_attr "length" "4")])
2903 ;; (define_insn "negdi2"
2904 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2905 ;; (neg:DI (match_operand:DI 1 "register_operand" "r")))]
2908 ;; [(set_attr "length" "4")])
2910 ;; Find first one bit
2911 ;; (define_insn "ffsdi2"
2912 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2913 ;; (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
2916 ;; [(set_attr "length" "4")])
2919 ;; ::::::::::::::::::::
2921 ;; :: 32 bit floating point arithmetic
2923 ;; ::::::::::::::::::::
2926 (define_insn "addsf3"
2927 [(set (match_operand:SF 0 "fpr_operand" "=f")
2928 (plus:SF (match_operand:SF 1 "fpr_operand" "%f")
2929 (match_operand:SF 2 "fpr_operand" "f")))]
2932 [(set_attr "length" "4")
2933 (set_attr "type" "fsadd")])
2936 (define_insn "subsf3"
2937 [(set (match_operand:SF 0 "fpr_operand" "=f")
2938 (minus:SF (match_operand:SF 1 "fpr_operand" "f")
2939 (match_operand:SF 2 "fpr_operand" "f")))]
2942 [(set_attr "length" "4")
2943 (set_attr "type" "fsadd")])
2946 (define_insn "mulsf3"
2947 [(set (match_operand:SF 0 "fpr_operand" "=f")
2948 (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
2949 (match_operand:SF 2 "fpr_operand" "f")))]
2952 [(set_attr "length" "4")
2953 (set_attr "type" "fsmul")])
2955 ;; Multiplication with addition/subtraction
2956 (define_insn "*muladdsf4"
2957 [(set (match_operand:SF 0 "fpr_operand" "=f")
2958 (plus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
2959 (match_operand:SF 2 "fpr_operand" "f"))
2960 (match_operand:SF 3 "fpr_operand" "0")))]
2961 "TARGET_HARD_FLOAT && TARGET_MULADD"
2963 [(set_attr "length" "4")
2964 (set_attr "type" "fmas")])
2966 (define_insn "*mulsubsf4"
2967 [(set (match_operand:SF 0 "fpr_operand" "=f")
2968 (minus:SF (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
2969 (match_operand:SF 2 "fpr_operand" "f"))
2970 (match_operand:SF 3 "fpr_operand" "0")))]
2971 "TARGET_HARD_FLOAT && TARGET_MULADD"
2973 [(set_attr "length" "4")
2974 (set_attr "type" "fmas")])
2977 (define_insn "divsf3"
2978 [(set (match_operand:SF 0 "fpr_operand" "=f")
2979 (div:SF (match_operand:SF 1 "fpr_operand" "f")
2980 (match_operand:SF 2 "fpr_operand" "f")))]
2983 [(set_attr "length" "4")
2984 (set_attr "type" "fsdiv")])
2987 (define_insn "negsf2"
2988 [(set (match_operand:SF 0 "fpr_operand" "=f")
2989 (neg:SF (match_operand:SF 1 "fpr_operand" "f")))]
2992 [(set_attr "length" "4")
2993 (set_attr "type" "fsconv")])
2996 (define_insn "abssf2"
2997 [(set (match_operand:SF 0 "fpr_operand" "=f")
2998 (abs:SF (match_operand:SF 1 "fpr_operand" "f")))]
3001 [(set_attr "length" "4")
3002 (set_attr "type" "fsconv")])
3005 (define_insn "sqrtsf2"
3006 [(set (match_operand:SF 0 "fpr_operand" "=f")
3007 (sqrt:SF (match_operand:SF 1 "fpr_operand" "f")))]
3010 [(set_attr "length" "4")
3011 (set_attr "type" "sqrt_single")])
3014 ;; ::::::::::::::::::::
3016 ;; :: 64 bit floating point arithmetic
3018 ;; ::::::::::::::::::::
3021 (define_insn "adddf3"
3022 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3023 (plus:DF (match_operand:DF 1 "fpr_operand" "%h")
3024 (match_operand:DF 2 "fpr_operand" "h")))]
3025 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3027 [(set_attr "length" "4")
3028 (set_attr "type" "fdadd")])
3031 (define_insn "subdf3"
3032 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3033 (minus:DF (match_operand:DF 1 "fpr_operand" "h")
3034 (match_operand:DF 2 "fpr_operand" "h")))]
3035 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3037 [(set_attr "length" "4")
3038 (set_attr "type" "fdadd")])
3041 (define_insn "muldf3"
3042 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3043 (mult:DF (match_operand:DF 1 "fpr_operand" "%h")
3044 (match_operand:DF 2 "fpr_operand" "h")))]
3045 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3047 [(set_attr "length" "4")
3048 (set_attr "type" "fdmul")])
3050 ;; Multiplication with addition/subtraction
3051 (define_insn "*muladddf4"
3052 [(set (match_operand:DF 0 "fpr_operand" "=f")
3053 (plus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3054 (match_operand:DF 2 "fpr_operand" "f"))
3055 (match_operand:DF 3 "fpr_operand" "0")))]
3056 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3058 [(set_attr "length" "4")
3059 (set_attr "type" "fmas")])
3061 (define_insn "*mulsubdf4"
3062 [(set (match_operand:DF 0 "fpr_operand" "=f")
3063 (minus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3064 (match_operand:DF 2 "fpr_operand" "f"))
3065 (match_operand:DF 3 "fpr_operand" "0")))]
3066 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3068 [(set_attr "length" "4")
3069 (set_attr "type" "fmas")])
3072 (define_insn "divdf3"
3073 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3074 (div:DF (match_operand:DF 1 "fpr_operand" "h")
3075 (match_operand:DF 2 "fpr_operand" "h")))]
3076 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3078 [(set_attr "length" "4")
3079 (set_attr "type" "fddiv")])
3082 (define_insn "negdf2"
3083 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3084 (neg:DF (match_operand:DF 1 "fpr_operand" "h")))]
3085 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3087 [(set_attr "length" "4")
3088 (set_attr "type" "fdconv")])
3091 (define_insn "absdf2"
3092 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3093 (abs:DF (match_operand:DF 1 "fpr_operand" "h")))]
3094 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3096 [(set_attr "length" "4")
3097 (set_attr "type" "fdconv")])
3100 (define_insn "sqrtdf2"
3101 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3102 (sqrt:DF (match_operand:DF 1 "fpr_operand" "h")))]
3103 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3105 [(set_attr "length" "4")
3106 (set_attr "type" "sqrt_double")])
3109 ;; ::::::::::::::::::::
3111 ;; :: 32 bit Integer Shifts and Rotates
3113 ;; ::::::::::::::::::::
3115 ;; Arithmetic Shift Left
3116 (define_insn "ashlsi3"
3117 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3118 (ashift:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3119 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3122 [(set_attr "length" "4")
3123 (set_attr "type" "int")])
3125 ;; Arithmetic Shift Right
3126 (define_insn "ashrsi3"
3127 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3128 (ashiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3129 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3132 [(set_attr "length" "4")
3133 (set_attr "type" "int")])
3135 ;; Logical Shift Right
3136 (define_insn "lshrsi3"
3137 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3138 (lshiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3139 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3142 [(set_attr "length" "4")
3143 (set_attr "type" "int")])
3146 ;; (define_insn "rotlsi3"
3147 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3148 ;; (rotate:SI (match_operand:SI 1 "register_operand" "r")
3149 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3151 ;; "rotlsi3 %0,%1,%2"
3152 ;; [(set_attr "length" "4")])
3155 ;; (define_insn "rotrsi3"
3156 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3157 ;; (rotatert:SI (match_operand:SI 1 "register_operand" "r")
3158 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3160 ;; "rotrsi3 %0,%1,%2"
3161 ;; [(set_attr "length" "4")])
3164 ;; ::::::::::::::::::::
3166 ;; :: 64 bit Integer Shifts and Rotates
3168 ;; ::::::::::::::::::::
3170 ;; Arithmetic Shift Left
3171 ;; (define_insn "ashldi3"
3172 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3173 ;; (ashift:DI (match_operand:DI 1 "register_operand" "r")
3174 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3176 ;; "ashldi3 %0,%1,%2"
3177 ;; [(set_attr "length" "4")])
3179 ;; Arithmetic Shift Right
3180 ;; (define_insn "ashrdi3"
3181 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3182 ;; (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
3183 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3185 ;; "ashrdi3 %0,%1,%2"
3186 ;; [(set_attr "length" "4")])
3188 ;; Logical Shift Right
3189 ;; (define_insn "lshrdi3"
3190 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3191 ;; (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
3192 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3194 ;; "lshrdi3 %0,%1,%2"
3195 ;; [(set_attr "length" "4")])
3198 ;; (define_insn "rotldi3"
3199 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3200 ;; (rotate:DI (match_operand:DI 1 "register_operand" "r")
3201 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3203 ;; "rotldi3 %0,%1,%2"
3204 ;; [(set_attr "length" "4")])
3207 ;; (define_insn "rotrdi3"
3208 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3209 ;; (rotatert:DI (match_operand:DI 1 "register_operand" "r")
3210 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3212 ;; "rotrdi3 %0,%1,%2"
3213 ;; [(set_attr "length" "4")])
3216 ;; ::::::::::::::::::::
3218 ;; :: 32 Bit Integer Logical operations
3220 ;; ::::::::::::::::::::
3222 ;; Logical AND, 32 bit integers
3223 (define_insn "andsi3_media"
3224 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3225 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3226 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3231 [(set_attr "length" "4")
3232 (set_attr "type" "int,mlogic")])
3234 (define_insn "andsi3_nomedia"
3235 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3236 (and:SI (match_operand:SI 1 "integer_register_operand" "%d")
3237 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3240 [(set_attr "length" "4")
3241 (set_attr "type" "int")])
3243 (define_expand "andsi3"
3244 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3245 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3246 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3250 ;; Inclusive OR, 32 bit integers
3251 (define_insn "iorsi3_media"
3252 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3253 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3254 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3259 [(set_attr "length" "4")
3260 (set_attr "type" "int,mlogic")])
3262 (define_insn "iorsi3_nomedia"
3263 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3264 (ior:SI (match_operand:SI 1 "integer_register_operand" "%d")
3265 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3268 [(set_attr "length" "4")
3269 (set_attr "type" "int")])
3271 (define_expand "iorsi3"
3272 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3273 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3274 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3278 ;; Exclusive OR, 32 bit integers
3279 (define_insn "xorsi3_media"
3280 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3281 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3282 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3287 [(set_attr "length" "4")
3288 (set_attr "type" "int,mlogic")])
3290 (define_insn "xorsi3_nomedia"
3291 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3292 (xor:SI (match_operand:SI 1 "integer_register_operand" "%d")
3293 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3296 [(set_attr "length" "4")
3297 (set_attr "type" "int")])
3299 (define_expand "xorsi3"
3300 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3301 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3302 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3306 ;; One's complement, 32 bit integers
3307 (define_insn "one_cmplsi2_media"
3308 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3309 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
3314 [(set_attr "length" "4")
3315 (set_attr "type" "int,mlogic")])
3317 (define_insn "one_cmplsi2_nomedia"
3318 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3319 (not:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3322 [(set_attr "length" "4")
3323 (set_attr "type" "int")])
3325 (define_expand "one_cmplsi2"
3326 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3327 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")))]
3332 ;; ::::::::::::::::::::
3334 ;; :: 64 Bit Integer Logical operations
3336 ;; ::::::::::::::::::::
3338 ;; Logical AND, 64 bit integers
3339 ;; (define_insn "anddi3"
3340 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3341 ;; (and:DI (match_operand:DI 1 "register_operand" "%r")
3342 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3344 ;; "anddi3 %0,%1,%2"
3345 ;; [(set_attr "length" "4")])
3347 ;; Inclusive OR, 64 bit integers
3348 ;; (define_insn "iordi3"
3349 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3350 ;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
3351 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3353 ;; "iordi3 %0,%1,%2"
3354 ;; [(set_attr "length" "4")])
3356 ;; Exclusive OR, 64 bit integers
3357 ;; (define_insn "xordi3"
3358 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3359 ;; (xor:DI (match_operand:DI 1 "register_operand" "%r")
3360 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3362 ;; "xordi3 %0,%1,%2"
3363 ;; [(set_attr "length" "4")])
3365 ;; One's complement, 64 bit integers
3366 ;; (define_insn "one_cmpldi2"
3367 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3368 ;; (not:DI (match_operand:DI 1 "register_operand" "r")))]
3371 ;; [(set_attr "length" "4")])
3374 ;; ::::::::::::::::::::
3376 ;; :: Combination of integer operation with comparison
3378 ;; ::::::::::::::::::::
3380 (define_insn "*combo_intop_compare1"
3381 [(set (match_operand:CC 0 "icc_operand" "=t")
3382 (compare:CC (match_operator:SI 1 "intop_compare_operator"
3383 [(match_operand:SI 2 "integer_register_operand" "d")
3384 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3387 "%O1%I3cc %2, %3, %., %0"
3388 [(set_attr "type" "int")
3389 (set_attr "length" "4")])
3391 (define_insn "*combo_intop_compare2"
3392 [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
3393 (compare:CC_UNS (match_operator:SI 1 "intop_compare_operator"
3394 [(match_operand:SI 2 "integer_register_operand" "d")
3395 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3398 "%O1%I3cc %2, %3, %., %0"
3399 [(set_attr "type" "int")
3400 (set_attr "length" "4")])
3402 (define_insn "*combo_intop_compare3"
3403 [(set (match_operand:CC 0 "icc_operand" "=t")
3404 (compare:CC (match_operator:SI 1 "intop_compare_operator"
3405 [(match_operand:SI 2 "integer_register_operand" "d")
3406 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3408 (set (match_operand:SI 4 "integer_register_operand" "=d")
3409 (match_operator:SI 5 "intop_compare_operator"
3412 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3413 "%O1%I3cc %2, %3, %4, %0"
3414 [(set_attr "type" "int")
3415 (set_attr "length" "4")])
3417 (define_insn "*combo_intop_compare4"
3418 [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
3419 (compare:CC_UNS (match_operator:SI 1 "intop_compare_operator"
3420 [(match_operand:SI 2 "integer_register_operand" "d")
3421 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3423 (set (match_operand:SI 4 "integer_register_operand" "=d")
3424 (match_operator:SI 5 "intop_compare_operator"
3427 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3428 "%O1%I3cc %2, %3, %4, %0"
3429 [(set_attr "type" "int")
3430 (set_attr "length" "4")])
3433 ;; ::::::::::::::::::::
3437 ;; ::::::::::::::::::::
3439 ;; Note, we store the operands in the comparison insns, and use them later
3440 ;; when generating the branch or scc operation.
3442 ;; First the routines called by the machine independent part of the compiler
3443 (define_expand "cmpsi"
3445 (compare (match_operand:SI 0 "integer_register_operand" "")
3446 (match_operand:SI 1 "gpr_or_int10_operand" "")))]
3450 frv_compare_op0 = operands[0];
3451 frv_compare_op1 = operands[1];
3455 ;(define_expand "cmpdi"
3457 ; (compare (match_operand:DI 0 "register_operand" "")
3458 ; (match_operand:DI 1 "nonmemory_operand" "")))]
3462 ; frv_compare_op0 = operands[0];
3463 ; frv_compare_op1 = operands[1];
3467 (define_expand "cmpsf"
3469 (compare (match_operand:SF 0 "fpr_operand" "")
3470 (match_operand:SF 1 "fpr_operand" "")))]
3474 frv_compare_op0 = operands[0];
3475 frv_compare_op1 = operands[1];
3479 (define_expand "cmpdf"
3481 (compare (match_operand:DF 0 "fpr_operand" "")
3482 (match_operand:DF 1 "fpr_operand" "")))]
3483 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3486 frv_compare_op0 = operands[0];
3487 frv_compare_op1 = operands[1];
3491 ;; Now, the actual comparisons, generated by the branch and/or scc operations
3493 (define_insn "cmpsi_cc"
3494 [(set (match_operand:CC 0 "icc_operand" "=t,t")
3495 (compare:CC (match_operand:SI 1 "integer_register_operand" "d,d")
3496 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3499 [(set_attr "length" "4")
3500 (set_attr "type" "int")])
3502 (define_insn "*cmpsi_cc_uns"
3503 [(set (match_operand:CC_UNS 0 "icc_operand" "=t,t")
3504 (compare:CC_UNS (match_operand:SI 1 "integer_register_operand" "d,d")
3505 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3508 [(set_attr "length" "4")
3509 (set_attr "type" "int")])
3511 (define_insn "*cmpsf_cc_fp"
3512 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3513 (compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
3514 (match_operand:SF 2 "fpr_operand" "f")))]
3517 [(set_attr "length" "4")
3518 (set_attr "type" "fsadd")])
3520 (define_insn "*cmpdf_cc_fp"
3521 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3522 (compare:CC_FP (match_operand:DF 1 "even_fpr_operand" "h")
3523 (match_operand:DF 2 "even_fpr_operand" "h")))]
3524 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3526 [(set_attr "length" "4")
3527 (set_attr "type" "fdadd")])
3530 ;; ::::::::::::::::::::
3534 ;; ::::::::::::::::::::
3536 ;; Define_expands called by the machine independent part of the compiler
3537 ;; to allocate a new comparison register. Each of these named patterns
3538 ;; must be present, and they cannot be amalgamated into one pattern.
3540 ;; If a fixed condition code register is being used, (as opposed to, say,
3541 ;; using cc0), then the expands should look like this:
3543 ;; (define_expand "<name_of_test>"
3544 ;; [(set (reg:CC <number_of_CC_register>)
3545 ;; (compare:CC (match_dup 1)
3548 ;; (if_then_else (eq:CC (reg:CC <number_of_CC_register>)
3550 ;; (label_ref (match_operand 0 "" ""))
3554 ;; operands[1] = frv_compare_op0;
3555 ;; operands[2] = frv_compare_op1;
3559 (define_expand "beq"
3560 [(use (match_operand 0 "" ""))]
3564 if (! frv_emit_cond_branch (EQ, operands[0]))
3570 (define_expand "bne"
3571 [(use (match_operand 0 "" ""))]
3575 if (! frv_emit_cond_branch (NE, operands[0]))
3581 (define_expand "blt"
3582 [(use (match_operand 0 "" ""))]
3586 if (! frv_emit_cond_branch (LT, operands[0]))
3592 (define_expand "ble"
3593 [(use (match_operand 0 "" ""))]
3597 if (! frv_emit_cond_branch (LE, operands[0]))
3603 (define_expand "bgt"
3604 [(use (match_operand 0 "" ""))]
3608 if (! frv_emit_cond_branch (GT, operands[0]))
3614 (define_expand "bge"
3615 [(use (match_operand 0 "" ""))]
3619 if (! frv_emit_cond_branch (GE, operands[0]))
3625 (define_expand "bltu"
3626 [(use (match_operand 0 "" ""))]
3630 if (! frv_emit_cond_branch (LTU, operands[0]))
3636 (define_expand "bleu"
3637 [(use (match_operand 0 "" ""))]
3641 if (! frv_emit_cond_branch (LEU, operands[0]))
3647 (define_expand "bgtu"
3648 [(use (match_operand 0 "" ""))]
3652 if (! frv_emit_cond_branch (GTU, operands[0]))
3658 (define_expand "bgeu"
3659 [(use (match_operand 0 "" ""))]
3663 if (! frv_emit_cond_branch (GEU, operands[0]))
3669 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
3670 ;; swapped. If they are swapped, it reverses the sense of the branch.
3672 ;; Note - unlike the define expands above, these patterns can be amalgamated
3673 ;; into one pattern for branch-if-true and one for branch-if-false. This does
3674 ;; require an operand operator to select the correct branch mnemonic.
3676 ;; If a fixed condition code register is being used, (as opposed to, say,
3677 ;; using cc0), then the expands could look like this:
3679 ;; (define_insn "*branch_true"
3681 ;; (if_then_else (match_operator:CC 0 "comparison_operator"
3682 ;; [(reg:CC <number_of_CC_register>)
3684 ;; (label_ref (match_operand 1 "" ""))
3688 ;; [(set_attr "length" "4")]
3691 ;; In the above example the %B is a directive to frv_print_operand()
3692 ;; to decode and print the correct branch mnemonic.
3694 (define_insn "*branch_signed_true"
3696 (if_then_else (match_operator:CC 0 "signed_relational_operator"
3697 [(match_operand 1 "icc_operand" "t")
3699 (label_ref (match_operand 2 "" ""))
3704 if (get_attr_length (insn) == 4)
3705 return \"b%c0 %1,%#,%l2\";
3707 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
3709 [(set (attr "length")
3711 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3712 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3715 (set (attr "far_jump")
3717 (eq_attr "length" "4")
3719 (const_string "yes")))
3722 (eq_attr "length" "4")
3723 (const_string "branch")
3724 (const_string "multi")))])
3726 (define_insn "*branch_signed_false"
3728 (if_then_else (match_operator:CC 0 "signed_relational_operator"
3729 [(match_operand 1 "icc_operand" "t")
3732 (label_ref (match_operand 2 "" ""))))]
3736 if (get_attr_length (insn) == 4)
3737 return \"b%C0 %1,%#,%l2\";
3739 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
3741 [(set (attr "length")
3743 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3744 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3747 (set (attr "far_jump")
3749 (eq_attr "length" "4")
3751 (const_string "yes")))
3754 (eq_attr "length" "4")
3755 (const_string "branch")
3756 (const_string "multi")))])
3758 (define_insn "*branch_unsigned_true"
3760 (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
3761 [(match_operand 1 "icc_operand" "t")
3763 (label_ref (match_operand 2 "" ""))
3768 if (get_attr_length (insn) == 4)
3769 return \"b%c0 %1,%#,%l2\";
3771 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
3773 [(set (attr "length")
3775 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3776 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3779 (set (attr "far_jump")
3781 (eq_attr "length" "4")
3783 (const_string "yes")))
3786 (eq_attr "length" "4")
3787 (const_string "branch")
3788 (const_string "multi")))])
3790 (define_insn "*branch_unsigned_false"
3792 (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
3793 [(match_operand 1 "icc_operand" "t")
3796 (label_ref (match_operand 2 "" ""))))]
3800 if (get_attr_length (insn) == 4)
3801 return \"b%C0 %1,%#,%l2\";
3803 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
3805 [(set (attr "length")
3807 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3808 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3811 (set (attr "far_jump")
3813 (eq_attr "length" "4")
3815 (const_string "yes")))
3818 (eq_attr "length" "4")
3819 (const_string "branch")
3820 (const_string "multi")))])
3822 (define_insn "*branch_fp_true"
3824 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3825 [(match_operand 1 "fcc_operand" "u")
3827 (label_ref (match_operand 2 "" ""))
3832 if (get_attr_length (insn) == 4)
3833 return \"fb%f0 %1,%#,%l2\";
3835 return \"fb%F0 %1,%#,1f\;call %l2\\n1:\";
3837 [(set (attr "length")
3839 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3840 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3843 (set (attr "far_jump")
3845 (eq_attr "length" "4")
3847 (const_string "yes")))
3850 (eq_attr "length" "4")
3851 (const_string "branch")
3852 (const_string "multi")))])
3854 (define_insn "*branch_fp_false"
3856 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3857 [(match_operand 1 "fcc_operand" "u")
3860 (label_ref (match_operand 2 "" ""))))]
3864 if (get_attr_length (insn) == 4)
3865 return \"fb%F0 %1,%#,%l2\";
3867 return \"fb%f0 %1,%#,1f\;call %l2\\n1:\";
3869 [(set (attr "length")
3871 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3872 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3875 (set (attr "far_jump")
3877 (eq_attr "length" "4")
3879 (const_string "yes")))
3882 (eq_attr "length" "4")
3883 (const_string "branch")
3884 (const_string "multi")))])
3887 ;; ::::::::::::::::::::
3889 ;; :: Set flag operations
3891 ;; ::::::::::::::::::::
3893 ;; Define_expands called by the machine independent part of the compiler
3894 ;; to allocate a new comparison register
3896 (define_expand "seq"
3897 [(match_operand:SI 0 "integer_register_operand" "")]
3901 if (! frv_emit_scc (EQ, operands[0]))
3907 (define_expand "sne"
3908 [(match_operand:SI 0 "integer_register_operand" "")]
3912 if (! frv_emit_scc (NE, operands[0]))
3918 (define_expand "slt"
3919 [(match_operand:SI 0 "integer_register_operand" "")]
3923 if (! frv_emit_scc (LT, operands[0]))
3929 (define_expand "sle"
3930 [(match_operand:SI 0 "integer_register_operand" "")]
3934 if (! frv_emit_scc (LE, operands[0]))
3940 (define_expand "sgt"
3941 [(match_operand:SI 0 "integer_register_operand" "")]
3945 if (! frv_emit_scc (GT, operands[0]))
3951 (define_expand "sge"
3952 [(match_operand:SI 0 "integer_register_operand" "")]
3956 if (! frv_emit_scc (GE, operands[0]))
3962 (define_expand "sltu"
3963 [(match_operand:SI 0 "integer_register_operand" "")]
3967 if (! frv_emit_scc (LTU, operands[0]))
3973 (define_expand "sleu"
3974 [(match_operand:SI 0 "integer_register_operand" "")]
3978 if (! frv_emit_scc (LEU, operands[0]))
3984 (define_expand "sgtu"
3985 [(match_operand:SI 0 "integer_register_operand" "")]
3989 if (! frv_emit_scc (GTU, operands[0]))
3995 (define_expand "sgeu"
3996 [(match_operand:SI 0 "integer_register_operand" "")]
4000 if (! frv_emit_scc (GEU, operands[0]))
4006 (define_insn "*scc_signed"
4007 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4008 (match_operator:SI 1 "signed_relational_operator"
4009 [(match_operand:CC 2 "icc_operand" "t")
4011 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4014 [(set_attr "length" "12")
4015 (set_attr "type" "multi")])
4017 (define_insn "*scc_unsigned"
4018 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4019 (match_operator:SI 1 "unsigned_relational_operator"
4020 [(match_operand:CC_UNS 2 "icc_operand" "t")
4022 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4025 [(set_attr "length" "12")
4026 (set_attr "type" "multi")])
4028 (define_insn "*scc_float"
4029 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4030 (match_operator:SI 1 "float_relational_operator"
4031 [(match_operand:CC_FP 2 "fcc_operand" "u")
4033 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4036 [(set_attr "length" "12")
4037 (set_attr "type" "multi")])
4039 ;; XXX -- add reload_completed to the splits, because register allocation
4040 ;; currently isn't ready to see cond_exec packets.
4042 [(set (match_operand:SI 0 "integer_register_operand" "")
4043 (match_operator:SI 1 "relational_operator"
4044 [(match_operand 2 "cc_operand" "")
4046 (clobber (match_operand 3 "cr_operand" ""))]
4049 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4050 operands[3], (HOST_WIDE_INT) 1);")
4052 (define_insn "*scc_neg1_signed"
4053 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4054 (neg:SI (match_operator:SI 1 "signed_relational_operator"
4055 [(match_operand:CC 2 "icc_operand" "t")
4057 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4060 [(set_attr "length" "12")
4061 (set_attr "type" "multi")])
4063 (define_insn "*scc_neg1_unsigned"
4064 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4065 (neg:SI (match_operator:SI 1 "unsigned_relational_operator"
4066 [(match_operand:CC_UNS 2 "icc_operand" "t")
4068 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4071 [(set_attr "length" "12")
4072 (set_attr "type" "multi")])
4074 (define_insn "*scc_neg1_float"
4075 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4076 (neg:SI (match_operator:SI 1 "float_relational_operator"
4077 [(match_operand:CC_FP 2 "fcc_operand" "u")
4079 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4082 [(set_attr "length" "12")
4083 (set_attr "type" "multi")])
4086 [(set (match_operand:SI 0 "integer_register_operand" "")
4087 (neg:SI (match_operator:SI 1 "relational_operator"
4088 [(match_operand 2 "cc_operand" "")
4090 (clobber (match_operand 3 "cr_operand" ""))]
4093 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4094 operands[3], (HOST_WIDE_INT) -1);")
4097 ;; ::::::::::::::::::::
4099 ;; :: Conditionally executed instructions
4101 ;; ::::::::::::::::::::
4103 ;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
4104 (define_insn "*ck_signed"
4105 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4106 (match_operator:CC_CCR 1 "signed_relational_operator"
4107 [(match_operand:CC 2 "icc_operand" "t")
4111 [(set_attr "length" "4")
4112 (set_attr "type" "ccr")])
4114 (define_insn "*ck_unsigned"
4115 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4116 (match_operator:CC_CCR 1 "unsigned_relational_operator"
4117 [(match_operand:CC_UNS 2 "icc_operand" "t")
4121 [(set_attr "length" "4")
4122 (set_attr "type" "ccr")])
4124 (define_insn "*fck_float"
4125 [(set (match_operand:CC_CCR 0 "fcr_operand" "=w")
4126 (match_operator:CC_CCR 1 "float_relational_operator"
4127 [(match_operand:CC_FP 2 "fcc_operand" "u")
4131 [(set_attr "length" "4")
4132 (set_attr "type" "ccr")])
4134 ;; Conditionally convert ICC/FCC comparison into CCR bits to provide && and ||
4135 ;; tests in conditional execution
4136 (define_insn "cond_exec_ck"
4137 [(set (match_operand:CC_CCR 0 "cr_operand" "=v,w")
4138 (if_then_else:CC_CCR (match_operator 1 "ccr_eqne_operator"
4139 [(match_operand 2 "cr_operand" "C,C")
4141 (match_operator 3 "relational_operator"
4142 [(match_operand 4 "cc_operand" "t,u")
4147 cck%c3 %4, %0, %2, %e1
4148 cfck%f3 %4, %0, %2, %e1"
4149 [(set_attr "length" "4")
4150 (set_attr "type" "ccr")])
4152 ;; Conditionally set a register to either 0 or another register
4153 (define_insn "*cond_exec_movqi"
4155 (match_operator 0 "ccr_eqne_operator"
4156 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4158 (set (match_operand:QI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4159 (match_operand:QI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4160 "register_operand(operands[2], QImode) || reg_or_0_operand (operands[3], QImode)"
4161 "* return output_condmove_single (operands, insn);"
4162 [(set_attr "length" "4")
4163 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4165 (define_insn "*cond_exec_movhi"
4167 (match_operator 0 "ccr_eqne_operator"
4168 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4170 (set (match_operand:HI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4171 (match_operand:HI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4172 "register_operand(operands[2], HImode) || reg_or_0_operand (operands[3], HImode)"
4173 "* return output_condmove_single (operands, insn);"
4174 [(set_attr "length" "4")
4175 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4177 (define_insn "*cond_exec_movsi"
4179 (match_operator 0 "ccr_eqne_operator"
4180 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C")
4182 (set (match_operand:SI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d,?f,?m")
4183 (match_operand:SI 3 "condexec_source_operand" "dO,U,dO,f,d,f,m,f")))]
4184 "register_operand(operands[2], SImode) || reg_or_0_operand (operands[3], SImode)"
4185 "* return output_condmove_single (operands, insn);"
4186 [(set_attr "length" "4")
4187 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg,fload,fstore")])
4190 (define_insn "*cond_exec_movsf_has_fprs"
4192 (match_operator 0 "ccr_eqne_operator"
4193 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C,C,C")
4195 (set (match_operand:SF 2 "condexec_dest_operand" "=f,?d,?d,?f,f,f,?d,U,?U,U")
4196 (match_operand:SF 3 "condexec_source_operand" "f,d,f,d,G,U,U,f,d,G")))]
4198 "* return output_condmove_single (operands, insn);"
4199 [(set_attr "length" "4")
4200 (set_attr "type" "fsconv,int,movgf,movfg,movgf,fload,gload,fstore,gstore,gstore")])
4202 (define_insn "*cond_exec_movsf_no_fprs"
4204 (match_operator 0 "ccr_eqne_operator"
4205 [(match_operand 1 "cr_operand" "C,C,C")
4207 (set (match_operand:SF 2 "condexec_dest_operand" "=d,d,U")
4208 (match_operand:SF 3 "condexec_source_operand" "d,U,dG")))]
4210 "* return output_condmove_single (operands, insn);"
4211 [(set_attr "length" "4")
4212 (set_attr "type" "int,gload,gstore")])
4214 (define_insn "*cond_exec_si_binary1"
4216 (match_operator 0 "ccr_eqne_operator"
4217 [(match_operand 1 "cr_operand" "C")
4219 (set (match_operand:SI 2 "integer_register_operand" "=d")
4220 (match_operator:SI 3 "condexec_si_binary_operator"
4221 [(match_operand:SI 4 "integer_register_operand" "d")
4222 (match_operand:SI 5 "integer_register_operand" "d")])))]
4226 switch (GET_CODE (operands[3]))
4228 case PLUS: return \"cadd %4, %z5, %2, %1, %e0\";
4229 case MINUS: return \"csub %4, %z5, %2, %1, %e0\";
4230 case AND: return \"cand %4, %z5, %2, %1, %e0\";
4231 case IOR: return \"cor %4, %z5, %2, %1, %e0\";
4232 case XOR: return \"cxor %4, %z5, %2, %1, %e0\";
4233 case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
4234 case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
4235 case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
4239 [(set_attr "length" "4")
4240 (set_attr "type" "int")])
4242 (define_insn "*cond_exec_si_binary2"
4244 (match_operator 0 "ccr_eqne_operator"
4245 [(match_operand 1 "cr_operand" "C")
4247 (set (match_operand:SI 2 "fpr_operand" "=f")
4248 (match_operator:SI 3 "condexec_si_media_operator"
4249 [(match_operand:SI 4 "fpr_operand" "f")
4250 (match_operand:SI 5 "fpr_operand" "f")])))]
4254 switch (GET_CODE (operands[3]))
4256 case AND: return \"cmand %4, %5, %2, %1, %e0\";
4257 case IOR: return \"cmor %4, %5, %2, %1, %e0\";
4258 case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
4262 [(set_attr "length" "4")
4263 (set_attr "type" "mlogic")])
4265 ;; Note, flow does not (currently) know how to handle an operation that uses
4266 ;; only part of the hard registers allocated for a multiregister value, such as
4267 ;; DImode in this case if the user is only interested in the lower 32-bits. So
4268 ;; we emit a USE of the entire register after the csmul instruction so it won't
4269 ;; get confused. See frv_ifcvt_modify_insn for more details.
4271 (define_insn "*cond_exec_si_smul"
4273 (match_operator 0 "ccr_eqne_operator"
4274 [(match_operand 1 "cr_operand" "C")
4276 (set (match_operand:DI 2 "even_gpr_operand" "=e")
4277 (mult:DI (sign_extend:DI (match_operand:SI 3 "integer_register_operand" "%d"))
4278 (sign_extend:DI (match_operand:SI 4 "integer_register_operand" "d")))))]
4280 "csmul %3, %4, %2, %1, %e0"
4281 [(set_attr "length" "4")
4282 (set_attr "type" "mul")])
4284 (define_insn "*cond_exec_si_divide"
4286 (match_operator 0 "ccr_eqne_operator"
4287 [(match_operand 1 "cr_operand" "C")
4289 (set (match_operand:SI 2 "integer_register_operand" "=d")
4290 (match_operator:SI 3 "condexec_si_divide_operator"
4291 [(match_operand:SI 4 "integer_register_operand" "d")
4292 (match_operand:SI 5 "integer_register_operand" "d")])))]
4296 switch (GET_CODE (operands[3]))
4298 case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
4299 case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
4303 [(set_attr "length" "4")
4304 (set_attr "type" "div")])
4306 (define_insn "*cond_exec_si_unary1"
4308 (match_operator 0 "ccr_eqne_operator"
4309 [(match_operand 1 "cr_operand" "C")
4311 (set (match_operand:SI 2 "integer_register_operand" "=d")
4312 (match_operator:SI 3 "condexec_si_unary_operator"
4313 [(match_operand:SI 4 "integer_register_operand" "d")])))]
4317 switch (GET_CODE (operands[3]))
4319 case NOT: return \"cnot %4, %2, %1, %e0\";
4320 case NEG: return \"csub %., %4, %2, %1, %e0\";
4324 [(set_attr "length" "4")
4325 (set_attr "type" "int")])
4327 (define_insn "*cond_exec_si_unary2"
4329 (match_operator 0 "ccr_eqne_operator"
4330 [(match_operand 1 "cr_operand" "C")
4332 (set (match_operand:SI 2 "fpr_operand" "=f")
4333 (not:SI (match_operand:SI 3 "fpr_operand" "f"))))]
4335 "cmnot %3, %2, %1, %e0"
4336 [(set_attr "length" "4")
4337 (set_attr "type" "mlogic")])
4339 (define_insn "*cond_exec_cmpsi_cc"
4341 (match_operator 0 "ccr_eqne_operator"
4342 [(match_operand 1 "cr_operand" "C")
4344 (set (match_operand:CC 2 "icc_operand" "=t")
4345 (compare:CC (match_operand:SI 3 "integer_register_operand" "d")
4346 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4348 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4349 "ccmp %3, %z4, %1, %e0"
4350 [(set_attr "length" "4")
4351 (set_attr "type" "int")])
4353 (define_insn "*cond_exec_cmpsi_cc_uns"
4355 (match_operator 0 "ccr_eqne_operator"
4356 [(match_operand 1 "cr_operand" "C")
4358 (set (match_operand:CC_UNS 2 "icc_operand" "=t")
4359 (compare:CC_UNS (match_operand:SI 3 "integer_register_operand" "d")
4360 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4362 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4363 "ccmp %3, %z4, %1, %e0"
4364 [(set_attr "length" "4")
4365 (set_attr "type" "int")])
4367 (define_insn "*cond_exec_sf_conv"
4369 (match_operator 0 "ccr_eqne_operator"
4370 [(match_operand 1 "cr_operand" "C")
4372 (set (match_operand:SF 2 "fpr_operand" "=f")
4373 (match_operator:SF 3 "condexec_sf_conv_operator"
4374 [(match_operand:SF 4 "fpr_operand" "f")])))]
4378 switch (GET_CODE (operands[3]))
4380 case ABS: return \"cfabss %4, %2, %1, %e0\";
4381 case NEG: return \"cfnegs %4, %2, %1, %e0\";
4385 [(set_attr "length" "4")
4386 (set_attr "type" "fsconv")])
4388 (define_insn "*cond_exec_sf_add"
4390 (match_operator 0 "ccr_eqne_operator"
4391 [(match_operand 1 "cr_operand" "C")
4393 (set (match_operand:SF 2 "fpr_operand" "=f")
4394 (match_operator:SF 3 "condexec_sf_add_operator"
4395 [(match_operand:SF 4 "fpr_operand" "f")
4396 (match_operand:SF 5 "fpr_operand" "f")])))]
4400 switch (GET_CODE (operands[3]))
4402 case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
4403 case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
4407 [(set_attr "length" "4")
4408 (set_attr "type" "fsadd")])
4410 (define_insn "*cond_exec_sf_mul"
4412 (match_operator 0 "ccr_eqne_operator"
4413 [(match_operand 1 "cr_operand" "C")
4415 (set (match_operand:SF 2 "fpr_operand" "=f")
4416 (mult:SF (match_operand:SF 3 "fpr_operand" "f")
4417 (match_operand:SF 4 "fpr_operand" "f"))))]
4419 "cfmuls %3, %4, %2, %1, %e0"
4420 [(set_attr "length" "4")
4421 (set_attr "type" "fsmul")])
4423 (define_insn "*cond_exec_sf_div"
4425 (match_operator 0 "ccr_eqne_operator"
4426 [(match_operand 1 "cr_operand" "C")
4428 (set (match_operand:SF 2 "fpr_operand" "=f")
4429 (div:SF (match_operand:SF 3 "fpr_operand" "f")
4430 (match_operand:SF 4 "fpr_operand" "f"))))]
4432 "cfdivs %3, %4, %2, %1, %e0"
4433 [(set_attr "length" "4")
4434 (set_attr "type" "fsdiv")])
4436 (define_insn "*cond_exec_sf_sqrt"
4438 (match_operator 0 "ccr_eqne_operator"
4439 [(match_operand 1 "cr_operand" "C")
4441 (set (match_operand:SF 2 "fpr_operand" "=f")
4442 (sqrt:SF (match_operand:SF 3 "fpr_operand" "f"))))]
4444 "cfsqrts %3, %2, %1, %e0"
4445 [(set_attr "length" "4")
4446 (set_attr "type" "fsdiv")])
4448 (define_insn "*cond_exec_cmpsi_cc_fp"
4450 (match_operator 0 "ccr_eqne_operator"
4451 [(match_operand 1 "cr_operand" "C")
4453 (set (match_operand:CC_FP 2 "fcc_operand" "=u")
4454 (compare:CC_FP (match_operand:SF 3 "fpr_operand" "f")
4455 (match_operand:SF 4 "fpr_operand" "f"))))]
4456 "reload_completed && TARGET_HARD_FLOAT
4457 && REGNO (operands[1]) == REGNO (operands[2]) - FCC_FIRST + FCR_FIRST"
4458 "cfcmps %3, %4, %2, %1, %e0"
4459 [(set_attr "length" "4")
4460 (set_attr "type" "fsconv")])
4463 ;; ::::::::::::::::::::
4465 ;; :: Logical operations on CR registers
4467 ;; ::::::::::::::::::::
4469 ;; We use UNSPEC to encode andcr/iorcr/etc. rather than the normal RTL
4470 ;; operations, since the RTL operations only have an idea of TRUE and FALSE,
4471 ;; while the CRs have TRUE, FALSE, and UNDEFINED.
4473 (define_expand "andcr"
4474 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4475 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4476 (match_operand:CC_CCR 2 "cr_operand" "")
4477 (const_int 0)] UNSPEC_CR_LOGIC))]
4481 (define_expand "orcr"
4482 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4483 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4484 (match_operand:CC_CCR 2 "cr_operand" "")
4485 (const_int 1)] UNSPEC_CR_LOGIC))]
4489 (define_expand "xorcr"
4490 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4491 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4492 (match_operand:CC_CCR 2 "cr_operand" "")
4493 (const_int 2)] UNSPEC_CR_LOGIC))]
4497 (define_expand "nandcr"
4498 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4499 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4500 (match_operand:CC_CCR 2 "cr_operand" "")
4501 (const_int 3)] UNSPEC_CR_LOGIC))]
4505 (define_expand "norcr"
4506 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4507 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4508 (match_operand:CC_CCR 2 "cr_operand" "")
4509 (const_int 4)] UNSPEC_CR_LOGIC))]
4513 (define_expand "andncr"
4514 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4515 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4516 (match_operand:CC_CCR 2 "cr_operand" "")
4517 (const_int 5)] UNSPEC_CR_LOGIC))]
4521 (define_expand "orncr"
4522 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4523 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4524 (match_operand:CC_CCR 2 "cr_operand" "")
4525 (const_int 6)] UNSPEC_CR_LOGIC))]
4529 (define_expand "nandncr"
4530 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4531 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4532 (match_operand:CC_CCR 2 "cr_operand" "")
4533 (const_int 7)] UNSPEC_CR_LOGIC))]
4537 (define_expand "norncr"
4538 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4539 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4540 (match_operand:CC_CCR 2 "cr_operand" "")
4541 (const_int 8)] UNSPEC_CR_LOGIC))]
4545 (define_expand "notcr"
4546 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4547 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4549 (const_int 9)] UNSPEC_CR_LOGIC))]
4553 (define_insn "*logical_cr"
4554 [(set (match_operand:CC_CCR 0 "cr_operand" "=C")
4555 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "C")
4556 (match_operand:CC_CCR 2 "cr_operand" "C")
4557 (match_operand:SI 3 "const_int_operand" "n")]
4562 switch (INTVAL (operands[3]))
4565 case 0: return \"andcr %1, %2, %0\";
4566 case 1: return \"orcr %1, %2, %0\";
4567 case 2: return \"xorcr %1, %2, %0\";
4568 case 3: return \"nandcr %1, %2, %0\";
4569 case 4: return \"norcr %1, %2, %0\";
4570 case 5: return \"andncr %1, %2, %0\";
4571 case 6: return \"orncr %1, %2, %0\";
4572 case 7: return \"nandncr %1, %2, %0\";
4573 case 8: return \"norncr %1, %2, %0\";
4574 case 9: return \"notcr %1, %0\";
4577 fatal_insn (\"logical_cr\", insn);
4579 [(set_attr "length" "4")
4580 (set_attr "type" "ccr")])
4583 ;; ::::::::::::::::::::
4585 ;; :: Conditional move instructions
4587 ;; ::::::::::::::::::::
4590 ;; - conditional moves based on floating-point comparisons require
4591 ;; TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4593 ;; - conditional moves between FPRs based on integer comparisons
4594 ;; require TARGET_HAS_FPRS.
4596 (define_expand "movqicc"
4597 [(set (match_operand:QI 0 "integer_register_operand" "")
4598 (if_then_else:QI (match_operand 1 "" "")
4599 (match_operand:QI 2 "gpr_or_int_operand" "")
4600 (match_operand:QI 3 "gpr_or_int_operand" "")))]
4604 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4610 (define_insn "*movqicc_internal1_signed"
4611 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4612 (if_then_else:QI (match_operator:CC 1 "signed_relational_operator"
4613 [(match_operand:CC 2 "icc_operand" "t,t,t")
4615 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4616 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4617 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4620 [(set_attr "length" "8,8,12")
4621 (set_attr "type" "multi")])
4623 (define_insn "*movqicc_internal1_unsigned"
4624 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4625 (if_then_else:QI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4626 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4628 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4629 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4630 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4633 [(set_attr "length" "8,8,12")
4634 (set_attr "type" "multi")])
4636 (define_insn "*movqicc_internal1_float"
4637 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4638 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4639 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4641 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4642 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4643 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4646 [(set_attr "length" "8,8,12")
4647 (set_attr "type" "multi")])
4649 (define_insn "*movqicc_internal2_signed"
4650 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4651 (if_then_else:QI (match_operator:CC 1 "signed_relational_operator"
4652 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
4654 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4655 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4656 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4657 "(INTVAL (operands[3]) == 0
4658 || INTVAL (operands[4]) == 0
4659 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4660 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4662 [(set_attr "length" "8,12,8,12,12")
4663 (set_attr "type" "multi")])
4665 (define_insn "*movqicc_internal2_unsigned"
4666 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4667 (if_then_else:QI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4668 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
4670 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4671 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4672 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4673 "(INTVAL (operands[3]) == 0
4674 || INTVAL (operands[4]) == 0
4675 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4676 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4678 [(set_attr "length" "8,12,8,12,12")
4679 (set_attr "type" "multi")])
4681 (define_insn "*movqicc_internal2_float"
4682 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4683 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4684 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4686 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4687 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4688 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4690 && (INTVAL (operands[3]) == 0
4691 || INTVAL (operands[4]) == 0
4692 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4693 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4695 [(set_attr "length" "8,12,8,12,12")
4696 (set_attr "type" "multi")])
4699 [(set (match_operand:QI 0 "integer_register_operand" "")
4700 (if_then_else:QI (match_operator 1 "relational_operator"
4701 [(match_operand 2 "cc_operand" "")
4703 (match_operand:QI 3 "gpr_or_int_operand" "")
4704 (match_operand:QI 4 "gpr_or_int_operand" "")))
4705 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4708 "operands[6] = frv_split_cond_move (operands);")
4710 (define_expand "movhicc"
4711 [(set (match_operand:HI 0 "integer_register_operand" "")
4712 (if_then_else:HI (match_operand 1 "" "")
4713 (match_operand:HI 2 "gpr_or_int_operand" "")
4714 (match_operand:HI 3 "gpr_or_int_operand" "")))]
4718 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4724 (define_insn "*movhicc_internal1_signed"
4725 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4726 (if_then_else:HI (match_operator:CC 1 "signed_relational_operator"
4727 [(match_operand:CC 2 "icc_operand" "t,t,t")
4729 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4730 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4731 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4734 [(set_attr "length" "8,8,12")
4735 (set_attr "type" "multi")])
4737 (define_insn "*movhicc_internal1_unsigned"
4738 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4739 (if_then_else:HI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4740 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4742 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4743 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4744 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4747 [(set_attr "length" "8,8,12")
4748 (set_attr "type" "multi")])
4750 (define_insn "*movhicc_internal1_float"
4751 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4752 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4753 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4755 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4756 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4757 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4760 [(set_attr "length" "8,8,12")
4761 (set_attr "type" "multi")])
4763 (define_insn "*movhicc_internal2_signed"
4764 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4765 (if_then_else:HI (match_operator:CC 1 "signed_relational_operator"
4766 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
4768 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4769 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4770 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4771 "(INTVAL (operands[3]) == 0
4772 || INTVAL (operands[4]) == 0
4773 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4774 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4776 [(set_attr "length" "8,12,8,12,12")
4777 (set_attr "type" "multi")])
4779 (define_insn "*movhicc_internal2_unsigned"
4780 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4781 (if_then_else:HI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4782 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
4784 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4785 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4786 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4787 "(INTVAL (operands[3]) == 0
4788 || INTVAL (operands[4]) == 0
4789 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4790 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4792 [(set_attr "length" "8,12,8,12,12")
4793 (set_attr "type" "multi")])
4795 (define_insn "*movhicc_internal2_float"
4796 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4797 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4798 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4800 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4801 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4802 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4804 && (INTVAL (operands[3]) == 0
4805 || INTVAL (operands[4]) == 0
4806 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4807 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4809 [(set_attr "length" "8,12,8,12,12")
4810 (set_attr "type" "multi")])
4813 [(set (match_operand:HI 0 "integer_register_operand" "")
4814 (if_then_else:HI (match_operator 1 "relational_operator"
4815 [(match_operand 2 "cc_operand" "")
4817 (match_operand:HI 3 "gpr_or_int_operand" "")
4818 (match_operand:HI 4 "gpr_or_int_operand" "")))
4819 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4822 "operands[6] = frv_split_cond_move (operands);")
4824 (define_expand "movsicc"
4825 [(set (match_operand:SI 0 "integer_register_operand" "")
4826 (if_then_else:SI (match_operand 1 "" "")
4827 (match_operand:SI 2 "gpr_or_int_operand" "")
4828 (match_operand:SI 3 "gpr_or_int_operand" "")))]
4832 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4838 (define_insn "*movsicc_internal1_signed"
4839 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4840 (if_then_else:SI (match_operator:CC 1 "signed_relational_operator"
4841 [(match_operand:CC 2 "icc_operand" "t,t,t")
4843 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4844 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4845 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4848 [(set_attr "length" "8,8,12")
4849 (set_attr "type" "multi")])
4851 (define_insn "*movsicc_internal1_unsigned"
4852 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4853 (if_then_else:SI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4854 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
4856 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4857 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4858 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4861 [(set_attr "length" "8,8,12")
4862 (set_attr "type" "multi")])
4864 (define_insn "*movsicc_internal1_float"
4865 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4866 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4867 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4869 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4870 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4871 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4874 [(set_attr "length" "8,8,12")
4875 (set_attr "type" "multi")])
4877 (define_insn "*movsicc_internal2_signed"
4878 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4879 (if_then_else:SI (match_operator:CC 1 "signed_relational_operator"
4880 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
4882 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4883 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4884 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4885 "(INTVAL (operands[3]) == 0
4886 || INTVAL (operands[4]) == 0
4887 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4888 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4890 [(set_attr "length" "8,12,8,12,12")
4891 (set_attr "type" "multi")])
4893 (define_insn "*movsicc_internal2_unsigned"
4894 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4895 (if_then_else:SI (match_operator:CC_UNS 1 "unsigned_relational_operator"
4896 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
4898 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4899 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4900 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4901 "(INTVAL (operands[3]) == 0
4902 || INTVAL (operands[4]) == 0
4903 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4904 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4906 [(set_attr "length" "8,12,8,12,12")
4907 (set_attr "type" "multi")])
4909 (define_insn "*movsicc_internal2_float"
4910 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4911 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4912 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4914 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4915 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4916 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4918 && (INTVAL (operands[3]) == 0
4919 || INTVAL (operands[4]) == 0
4920 || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
4921 && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4923 [(set_attr "length" "8,12,8,12,12")
4924 (set_attr "type" "multi")])
4927 [(set (match_operand:SI 0 "integer_register_operand" "")
4928 (if_then_else:SI (match_operator 1 "relational_operator"
4929 [(match_operand 2 "cc_operand" "")
4931 (match_operand:SI 3 "gpr_or_int_operand" "")
4932 (match_operand:SI 4 "gpr_or_int_operand" "")))
4933 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4936 "operands[6] = frv_split_cond_move (operands);")
4938 (define_expand "movsfcc"
4939 [(set (match_operand:SF 0 "register_operand" "")
4940 (if_then_else:SF (match_operand 1 "" "")
4941 (match_operand:SF 2 "register_operand" "")
4942 (match_operand:SF 3 "register_operand" "")))]
4946 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4952 (define_insn "*movsfcc_has_fprs_signed"
4953 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4954 (if_then_else:SF (match_operator:CC 1 "signed_relational_operator"
4955 [(match_operand:CC 2 "icc_operand" "t,t,t,t,t,t")
4957 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4958 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4959 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
4962 [(set_attr "length" "8,8,12,12,12,12")
4963 (set_attr "type" "multi")])
4965 (define_insn "*movsfcc_has_fprs_unsigned"
4966 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4967 (if_then_else:SF (match_operator:CC_UNS 1 "unsigned_relational_operator"
4968 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t,t")
4970 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4971 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4972 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
4975 [(set_attr "length" "8,8,12,12,12,12")
4976 (set_attr "type" "multi")])
4978 (define_insn "*movsfcc_hardfloat_float"
4979 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4980 (if_then_else:SF (match_operator:CC_FP 1 "float_relational_operator"
4981 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u,u")
4983 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4984 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4985 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w,w"))]
4988 [(set_attr "length" "8,8,12,12,12,12")
4989 (set_attr "type" "multi")])
4991 (define_insn "*movsfcc_no_fprs_signed"
4992 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
4993 (if_then_else:SF (match_operator:CC 1 "signed_relational_operator"
4994 [(match_operand:CC 2 "icc_operand" "t,t,t")
4996 (match_operand:SF 3 "integer_register_operand" "0,d,d")
4997 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
4998 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5001 [(set_attr "length" "8,8,12")
5002 (set_attr "type" "multi")])
5004 (define_insn "*movsfcc_no_fprs_unsigned"
5005 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
5006 (if_then_else:SF (match_operator:CC_UNS 1 "unsigned_relational_operator"
5007 [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
5009 (match_operand:SF 3 "integer_register_operand" "0,d,d")
5010 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
5011 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5014 [(set_attr "length" "8,8,12")
5015 (set_attr "type" "multi")])
5018 [(set (match_operand:SF 0 "register_operand" "")
5019 (if_then_else:SF (match_operator 1 "relational_operator"
5020 [(match_operand 2 "cc_operand" "")
5022 (match_operand:SF 3 "register_operand" "")
5023 (match_operand:SF 4 "register_operand" "")))
5024 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
5027 "operands[6] = frv_split_cond_move (operands);")
5030 ;; ::::::::::::::::::::
5032 ;; :: Minimum, maximum, and integer absolute value
5034 ;; ::::::::::::::::::::
5036 ;; These 'instructions' are provided to give the compiler a slightly better
5037 ;; nudge at register allocation, then it would if it constructed the
5038 ;; instructions from basic building blocks (since it indicates it prefers one
5039 ;; of the operands to be the same as the destination. It also helps the
5040 ;; earlier passes of the compiler, by not breaking things into small basic
5043 (define_expand "abssi2"
5044 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5045 (abs:SI (match_operand:SI 1 "integer_register_operand" "")))
5046 (clobber (match_dup 2))
5047 (clobber (match_dup 3))])]
5051 operands[2] = gen_reg_rtx (CCmode);
5052 operands[3] = gen_reg_rtx (CC_CCRmode);
5055 (define_insn_and_split "*abssi2_internal"
5056 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
5057 (abs:SI (match_operand:SI 1 "integer_register_operand" "0,d")))
5058 (clobber (match_operand:CC 2 "icc_operand" "=t,t"))
5059 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v,v"))]
5064 "operands[4] = frv_split_abs (operands);"
5065 [(set_attr "length" "12,16")
5066 (set_attr "type" "multi")])
5068 (define_expand "sminsi3"
5069 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5070 (smin:SI (match_operand:SI 1 "integer_register_operand" "")
5071 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5072 (clobber (match_dup 3))
5073 (clobber (match_dup 4))])]
5077 operands[3] = gen_reg_rtx (CCmode);
5078 operands[4] = gen_reg_rtx (CC_CCRmode);
5081 (define_expand "smaxsi3"
5082 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5083 (smax:SI (match_operand:SI 1 "integer_register_operand" "")
5084 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5085 (clobber (match_dup 3))
5086 (clobber (match_dup 4))])]
5090 operands[3] = gen_reg_rtx (CCmode);
5091 operands[4] = gen_reg_rtx (CC_CCRmode);
5094 (define_insn_and_split "*minmax_si_signed"
5095 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5096 (match_operator:SI 1 "minmax_operator"
5097 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5098 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5099 (clobber (match_operand:CC 4 "icc_operand" "=t,t,t"))
5100 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5105 "operands[6] = frv_split_minmax (operands);"
5106 [(set_attr "length" "12,12,16")
5107 (set_attr "type" "multi")])
5109 (define_expand "uminsi3"
5110 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5111 (umin:SI (match_operand:SI 1 "integer_register_operand" "")
5112 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5113 (clobber (match_dup 3))
5114 (clobber (match_dup 4))])]
5118 operands[3] = gen_reg_rtx (CC_UNSmode);
5119 operands[4] = gen_reg_rtx (CC_CCRmode);
5122 (define_expand "umaxsi3"
5123 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
5124 (umax:SI (match_operand:SI 1 "integer_register_operand" "")
5125 (match_operand:SI 2 "gpr_or_int10_operand" "")))
5126 (clobber (match_dup 3))
5127 (clobber (match_dup 4))])]
5131 operands[3] = gen_reg_rtx (CC_UNSmode);
5132 operands[4] = gen_reg_rtx (CC_CCRmode);
5135 (define_insn_and_split "*minmax_si_unsigned"
5136 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5137 (match_operator:SI 1 "minmax_operator"
5138 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5139 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5140 (clobber (match_operand:CC_UNS 4 "icc_operand" "=t,t,t"))
5141 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5146 "operands[6] = frv_split_minmax (operands);"
5147 [(set_attr "length" "12,12,16")
5148 (set_attr "type" "multi")])
5150 (define_expand "sminsf3"
5151 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5152 (smin:SF (match_operand:SF 1 "fpr_operand" "")
5153 (match_operand:SF 2 "fpr_operand" "")))
5154 (clobber (match_dup 3))
5155 (clobber (match_dup 4))])]
5156 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5159 operands[3] = gen_reg_rtx (CC_FPmode);
5160 operands[4] = gen_reg_rtx (CC_CCRmode);
5163 (define_expand "smaxsf3"
5164 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5165 (smax:SF (match_operand:SF 1 "fpr_operand" "")
5166 (match_operand:SF 2 "fpr_operand" "")))
5167 (clobber (match_dup 3))
5168 (clobber (match_dup 4))])]
5169 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5172 operands[3] = gen_reg_rtx (CC_FPmode);
5173 operands[4] = gen_reg_rtx (CC_CCRmode);
5176 (define_insn_and_split "*minmax_sf"
5177 [(set (match_operand:SF 0 "fpr_operand" "=f,f,f")
5178 (match_operator:SF 1 "minmax_operator"
5179 [(match_operand:SF 2 "fpr_operand" "%0,f,f")
5180 (match_operand:SF 3 "fpr_operand" "f,0,f")]))
5181 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5182 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5183 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5187 "operands[6] = frv_split_minmax (operands);"
5188 [(set_attr "length" "12,12,16")
5189 (set_attr "type" "multi")])
5191 (define_expand "smindf3"
5192 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5193 (smin:DF (match_operand:DF 1 "fpr_operand" "")
5194 (match_operand:DF 2 "fpr_operand" "")))
5195 (clobber (match_dup 3))
5196 (clobber (match_dup 4))])]
5197 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5200 operands[3] = gen_reg_rtx (CC_FPmode);
5201 operands[4] = gen_reg_rtx (CC_CCRmode);
5204 (define_expand "smaxdf3"
5205 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5206 (smax:DF (match_operand:DF 1 "fpr_operand" "")
5207 (match_operand:DF 2 "fpr_operand" "")))
5208 (clobber (match_dup 3))
5209 (clobber (match_dup 4))])]
5210 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5213 operands[3] = gen_reg_rtx (CC_FPmode);
5214 operands[4] = gen_reg_rtx (CC_CCRmode);
5217 (define_insn_and_split "*minmax_df"
5218 [(set (match_operand:DF 0 "fpr_operand" "=f,f,f")
5219 (match_operator:DF 1 "minmax_operator"
5220 [(match_operand:DF 2 "fpr_operand" "%0,f,f")
5221 (match_operand:DF 3 "fpr_operand" "f,0,f")]))
5222 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5223 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5224 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5228 "operands[6] = frv_split_minmax (operands);"
5229 [(set_attr "length" "12,12,16")
5230 (set_attr "type" "multi")])
5233 ;; ::::::::::::::::::::
5235 ;; :: Call and branch instructions
5237 ;; ::::::::::::::::::::
5239 ;; Subroutine call instruction returning no value. Operand 0 is the function
5240 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5241 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5242 ;; registers used as operands.
5244 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5245 ;; is supplied for the sake of some RISC machines which need to put this
5246 ;; information into the assembler code; they can put it in the RTL instead of
5249 (define_expand "call"
5250 [(use (match_operand:QI 0 "" ""))
5251 (use (match_operand 1 "" ""))
5252 (use (match_operand 2 "" ""))
5253 (use (match_operand 3 "" ""))]
5257 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5260 if (GET_CODE (operands[0]) != MEM)
5263 addr = XEXP (operands[0], 0);
5264 if (! call_operand (addr, Pmode))
5265 addr = force_reg (Pmode, addr);
5268 operands[2] = const0_rtx;
5271 frv_expand_fdpic_call (operands, false, false);
5273 emit_call_insn (gen_call_internal (addr, operands[1], operands[2], lr));
5278 (define_insn "call_internal"
5279 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5280 (match_operand 1 "" ""))
5281 (use (match_operand 2 "" ""))
5282 (clobber (match_operand:SI 3 "lr_operand" "=l,l"))]
5287 [(set_attr "length" "4")
5288 (set_attr "type" "call,jumpl")])
5290 ;; The odd use of GR0 within the UNSPEC below prevents cseing or
5291 ;; hoisting function descriptor loads out of loops. This is almost
5292 ;; never desirable, since if we preserve the function descriptor in a
5293 ;; pair of registers, it takes two insns to move it to gr14/gr15, and
5294 ;; if it's in the stack, we just waste space with the store, since
5295 ;; we'll have to load back from memory anyway. And, in the worst
5296 ;; case, we may end up reusing a function descriptor still pointing at
5297 ;; a PLT entry, instead of to the resolved function, which means going
5298 ;; through the resolver for every call that uses the outdated value.
5301 ;; The explicit MEM inside the SPEC prevents the compiler from moving
5302 ;; the load before a branch after a NULL test, or before a store that
5303 ;; initializes a function descriptor.
5305 (define_insn "movdi_ldd"
5306 [(set (match_operand:DI 0 "fdpic_fptr_operand" "=e")
5307 (unspec:DI [(mem:DI (match_operand:SI 1 "ldd_address_operand" "p"))
5308 (reg:SI 0)] UNSPEC_LDD))]
5311 [(set_attr "length" "4")
5312 (set_attr "type" "gload")])
5314 (define_insn "call_fdpicdi"
5315 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5316 (match_operand 1 "" ""))
5317 (clobber (match_operand:SI 2 "lr_operand" "=l"))]
5320 [(set_attr "length" "4")
5321 (set_attr "type" "jumpl")])
5323 (define_insn "call_fdpicsi"
5324 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5325 (match_operand 1 "" ""))
5326 (use (match_operand 2 "" ""))
5327 (use (match_operand:SI 3 "fdpic_operand" "Z,Z"))
5328 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5333 [(set_attr "length" "4")
5334 (set_attr "type" "call,jumpl")])
5336 (define_expand "sibcall"
5337 [(use (match_operand:QI 0 "" ""))
5338 (use (match_operand 1 "" ""))
5339 (use (match_operand 2 "" ""))
5340 (use (match_operand 3 "" ""))]
5346 if (GET_CODE (operands[0]) != MEM)
5349 addr = XEXP (operands[0], 0);
5350 if (! sibcall_operand (addr, Pmode))
5351 addr = force_reg (Pmode, addr);
5354 operands[2] = const0_rtx;
5357 frv_expand_fdpic_call (operands, false, true);
5359 emit_call_insn (gen_sibcall_internal (addr, operands[1], operands[2]));
5364 ;; It might seem that these sibcall patterns are missing references to
5365 ;; LR, but they're not necessary because sibcall_epilogue will make
5366 ;; sure LR is restored, and having LR here will set
5367 ;; regs_ever_used[REG_LR], forcing it to be saved on the stack, and
5368 ;; then restored in sibcalls and regular return code paths, even if
5369 ;; the function becomes a leaf function after tail-call elimination.
5371 ;; We must not use a call-saved register here. `W' limits ourselves
5372 ;; to gr14 or gr15, but since we're almost running out of constraint
5373 ;; letters, and most other call-clobbered registers are often used for
5374 ;; argument-passing, this will do.
5375 (define_insn "sibcall_internal"
5376 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "WNOP"))
5377 (match_operand 1 "" ""))
5378 (use (match_operand 2 "" ""))
5382 [(set_attr "length" "4")
5383 (set_attr "type" "jumpl")])
5385 (define_insn "sibcall_fdpicdi"
5386 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5387 (match_operand 1 "" ""))
5391 [(set_attr "length" "4")
5392 (set_attr "type" "jumpl")])
5395 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5396 ;; register in which the value is returned. There are three more operands, the
5397 ;; same as the three operands of the `call' instruction (but with numbers
5398 ;; increased by one).
5400 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5402 (define_expand "call_value"
5403 [(use (match_operand 0 "" ""))
5404 (use (match_operand:QI 1 "" ""))
5405 (use (match_operand 2 "" ""))
5406 (use (match_operand 3 "" ""))
5407 (use (match_operand 4 "" ""))]
5411 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5414 if (GET_CODE (operands[1]) != MEM)
5417 addr = XEXP (operands[1], 0);
5418 if (! call_operand (addr, Pmode))
5419 addr = force_reg (Pmode, addr);
5422 operands[3] = const0_rtx;
5425 frv_expand_fdpic_call (operands, true, false);
5427 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
5433 (define_insn "call_value_internal"
5434 [(set (match_operand 0 "register_operand" "=d,d")
5435 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5436 (match_operand 2 "" "")))
5437 (use (match_operand 3 "" ""))
5438 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5443 [(set_attr "length" "4")
5444 (set_attr "type" "call,jumpl")])
5446 (define_insn "call_value_fdpicdi"
5447 [(set (match_operand 0 "register_operand" "=d")
5448 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5449 (match_operand 2 "" "")))
5450 (clobber (match_operand:SI 3 "lr_operand" "=l"))]
5453 [(set_attr "length" "4")
5454 (set_attr "type" "jumpl")])
5456 (define_insn "call_value_fdpicsi"
5457 [(set (match_operand 0 "register_operand" "=d,d")
5458 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5459 (match_operand 2 "" "")))
5460 (use (match_operand 3 "" ""))
5461 (use (match_operand:SI 4 "fdpic_operand" "Z,Z"))
5462 (clobber (match_operand:SI 5 "lr_operand" "=l,l"))]
5467 [(set_attr "length" "4")
5468 (set_attr "type" "call,jumpl")])
5470 (define_expand "sibcall_value"
5471 [(use (match_operand 0 "" ""))
5472 (use (match_operand:QI 1 "" ""))
5473 (use (match_operand 2 "" ""))
5474 (use (match_operand 3 "" ""))
5475 (use (match_operand 4 "" ""))]
5481 if (GET_CODE (operands[1]) != MEM)
5484 addr = XEXP (operands[1], 0);
5485 if (! sibcall_operand (addr, Pmode))
5486 addr = force_reg (Pmode, addr);
5489 operands[3] = const0_rtx;
5492 frv_expand_fdpic_call (operands, true, true);
5494 emit_call_insn (gen_sibcall_value_internal (operands[0], addr, operands[2],
5499 (define_insn "sibcall_value_internal"
5500 [(set (match_operand 0 "register_operand" "=d")
5501 (call (mem:QI (match_operand:SI 1 "sibcall_operand" "WNOP"))
5502 (match_operand 2 "" "")))
5503 (use (match_operand 3 "" ""))
5507 [(set_attr "length" "4")
5508 (set_attr "type" "jumpl")])
5510 (define_insn "sibcall_value_fdpicdi"
5511 [(set (match_operand 0 "register_operand" "=d")
5512 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5513 (match_operand 2 "" "")))
5517 [(set_attr "length" "4")
5518 (set_attr "type" "jumpl")])
5520 ;; return instruction generated instead of jmp to epilog
5521 (define_expand "return"
5522 [(parallel [(return)
5524 (use (const_int 1))])]
5525 "direct_return_p ()"
5528 operands[0] = gen_rtx_REG (Pmode, LR_REGNO);
5531 ;; return instruction generated by the epilogue
5532 (define_expand "epilogue_return"
5533 [(parallel [(return)
5534 (use (match_operand:SI 0 "register_operand" ""))
5535 (use (const_int 0))])]
5539 (define_insn "*return_internal"
5541 (use (match_operand:SI 0 "register_operand" "l,d"))
5542 (use (match_operand:SI 1 "immediate_operand" "n,n"))]
5547 [(set_attr "length" "4")
5548 (set_attr "type" "jump,jumpl")])
5550 (define_insn "*return_true"
5552 (if_then_else (match_operator:CC 0 "signed_relational_operator"
5553 [(match_operand 1 "icc_operand" "t")
5557 "direct_return_p ()"
5559 [(set_attr "length" "4")
5560 (set_attr "type" "jump")])
5562 (define_insn "*return_false"
5564 (if_then_else (match_operator:CC 0 "signed_relational_operator"
5565 [(match_operand 1 "icc_operand" "t")
5569 "direct_return_p ()"
5571 [(set_attr "length" "4")
5572 (set_attr "type" "jump")])
5574 (define_insn "*return_unsigned_true"
5576 (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
5577 [(match_operand 1 "icc_operand" "t")
5581 "direct_return_p ()"
5583 [(set_attr "length" "4")
5584 (set_attr "type" "jump")])
5586 (define_insn "*return_unsigned_false"
5588 (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
5589 [(match_operand 1 "icc_operand" "t")
5593 "direct_return_p ()"
5595 [(set_attr "length" "4")
5596 (set_attr "type" "jump")])
5598 ;; A version of addsi3 for deallocating stack space at the end of the
5599 ;; epilogue. The addition is done in parallel with an (unspec_volatile),
5600 ;; which represents the clobbering of the deallocated space.
5601 (define_insn "stack_adjust"
5602 [(set (match_operand:SI 0 "register_operand" "=d")
5603 (plus:SI (match_operand:SI 1 "register_operand" "d")
5604 (match_operand:SI 2 "general_operand" "dNOP")))
5605 (unspec_volatile [(const_int 0)] UNSPEC_STACK_ADJUST)]
5608 [(set_attr "length" "4")
5609 (set_attr "type" "int")])
5611 ;; Normal unconditional jump
5613 ;; Use the "call" instruction for long branches, but prefer to use "bra" for
5614 ;; short ones since it does not force us to save the link register.
5616 ;; This define_insn uses the branch-shortening code to decide which
5617 ;; instruction it emits. Since the main branch-shortening interface is
5618 ;; through get_attr_length(), the two alternatives must be given different
5619 ;; lengths. Here we pretend that the far jump is 8 rather than 4 bytes
5620 ;; long, though both alternatives are really the same size.
5622 [(set (pc) (label_ref (match_operand 0 "" "")))]
5626 if (get_attr_length (insn) == 4)
5629 return \"call %l0\";
5631 [(set (attr "length")
5633 (and (ge (minus (match_dup 0) (pc)) (const_int -32768))
5634 (le (minus (match_dup 0) (pc)) (const_int 32764)))
5637 (set (attr "far_jump")
5639 (eq_attr "length" "4")
5641 (const_string "yes")))
5644 (eq_attr "length" "4")
5645 (const_string "jump")
5646 (const_string "call")))])
5648 ;; Indirect jump through a register
5649 (define_insn "indirect_jump"
5650 [(set (pc) (match_operand:SI 0 "register_operand" "d,l"))]
5655 [(set_attr "length" "4")
5656 (set_attr "type" "jumpl,branch")])
5658 ;; Instruction to jump to a variable address. This is a low-level capability
5659 ;; which can be used to implement a dispatch table when there is no `casesi'
5660 ;; pattern. Either the 'casesi' pattern or the 'tablejump' pattern, or both,
5661 ;; MUST be present in this file.
5663 ;; This pattern requires two operands: the address or offset, and a label which
5664 ;; should immediately precede the jump table. If the macro
5665 ;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5666 ;; which counts from the address of the table; otherwise, it is an absolute
5667 ;; address to jump to. In either case, the first operand has mode `Pmode'.
5669 ;; The `tablejump' insn is always the last insn before the jump table it uses.
5670 ;; Its assembler code normally has no need to use the second operand, but you
5671 ;; should incorporate it in the RTL pattern so that the jump optimizer will not
5672 ;; delete the table as unreachable code.
5674 (define_expand "tablejump"
5675 [(parallel [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5676 (use (label_ref (match_operand 1 "" "")))])]
5680 (define_insn "tablejump_insn"
5681 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5682 (use (label_ref (match_operand 1 "" "")))]
5685 [(set_attr "length" "4")
5686 (set_attr "type" "jumpl")])
5688 ;; Implement switch statements when generating PIC code. Switches are
5689 ;; implemented by `tablejump' when not using -fpic.
5691 ;; Emit code here to do the range checking and make the index zero based.
5692 ;; operand 0 is the index
5693 ;; operand 1 is the lower bound
5694 ;; operand 2 is the range of indices (highest - lowest + 1)
5695 ;; operand 3 is the label that precedes the table itself
5696 ;; operand 4 is the fall through label
5698 (define_expand "casesi"
5699 [(use (match_operand:SI 0 "integer_register_operand" ""))
5700 (use (match_operand:SI 1 "const_int_operand" ""))
5701 (use (match_operand:SI 2 "const_int_operand" ""))
5702 (use (match_operand 3 "" ""))
5703 (use (match_operand 4 "" ""))]
5709 rtx low = operands[1];
5710 rtx range = operands[2];
5711 rtx table = operands[3];
5713 rtx fail = operands[4];
5718 if (GET_CODE (operands[1]) != CONST_INT)
5721 if (GET_CODE (operands[2]) != CONST_INT)
5724 /* If we can't generate an immediate instruction, promote to register. */
5725 if (! IN_RANGE_P (INTVAL (range), -2048, 2047))
5726 range = force_reg (SImode, range);
5728 /* If low bound is 0, we don't have to subtract it. */
5729 if (INTVAL (operands[1]) == 0)
5733 indx = gen_reg_rtx (SImode);
5734 if (IN_RANGE_P (INTVAL (low), -2047, 2048))
5735 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5737 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5740 /* Do an unsigned comparison (in the proper mode) between the index
5741 expression and the value which represents the length of the range.
5742 Since we just finished subtracting the lower bound of the range
5743 from the index expression, this comparison allows us to simultaneously
5744 check that the original index expression value is both greater than
5745 or equal to the minimum value of the range and less than or equal to
5746 the maximum value of the range. */
5748 emit_cmp_and_jump_insns (indx, range, GTU, NULL_RTX, SImode, 1, fail);
5750 /* Move the table address to a register. */
5751 treg = gen_reg_rtx (Pmode);
5752 emit_insn (gen_movsi (treg, gen_rtx_LABEL_REF (VOIDmode, table)));
5754 /* Scale index-low by wordsize. */
5755 scale = gen_reg_rtx (SImode);
5756 emit_insn (gen_ashlsi3 (scale, indx, const2_rtx));
5758 /* Load the address, add the start of the table back in,
5760 mem = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, scale, treg));
5761 reg2 = gen_reg_rtx (SImode);
5762 reg3 = gen_reg_rtx (SImode);
5763 emit_insn (gen_movsi (reg2, mem));
5764 emit_insn (gen_addsi3 (reg3, reg2, treg));
5765 emit_jump_insn (gen_tablejump_insn (reg3, table));
5770 ;; ::::::::::::::::::::
5772 ;; :: Prologue and Epilogue instructions
5774 ;; ::::::::::::::::::::
5776 ;; Called after register allocation to add any instructions needed for the
5777 ;; prologue. Using a prologue insn is favored compared to putting all of the
5778 ;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
5779 ;; to intermix instructions with the saves of the caller saved registers. In
5780 ;; some cases, it might be necessary to emit a barrier instruction as the last
5781 ;; insn to prevent such scheduling.
5782 (define_expand "prologue"
5787 frv_expand_prologue ();
5791 ;; Called after register allocation to add any instructions needed for the
5792 ;; epilogue. Using an epilogue insn is favored compared to putting all of the
5793 ;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
5794 ;; to intermix instructions with the restires of the caller saved registers.
5795 ;; In some cases, it might be necessary to emit a barrier instruction as the
5796 ;; first insn to prevent such scheduling.
5797 (define_expand "epilogue"
5802 frv_expand_epilogue (true);
5806 ;; This pattern, if defined, emits RTL for exit from a function without the final
5807 ;; branch back to the calling function. This pattern will be emitted before any
5808 ;; sibling call (aka tail call) sites.
5810 ;; The sibcall_epilogue pattern must not clobber any arguments used for
5811 ;; parameter passing or any stack slots for arguments passed to the current
5813 (define_expand "sibcall_epilogue"
5818 frv_expand_epilogue (false);
5822 ;; Set up the pic register to hold the address of the pic table
5823 (define_insn "pic_prologue"
5824 [(set (match_operand:SI 0 "integer_register_operand" "=d")
5825 (unspec_volatile:SI [(const_int 0)] UNSPEC_PIC_PROLOGUE))
5826 (clobber (match_operand:SI 1 "lr_operand" "=l"))
5827 (clobber (match_operand:SI 2 "integer_register_operand" "=d"))]
5831 static int frv_pic_labelno = 0;
5833 operands[3] = GEN_INT (frv_pic_labelno++);
5834 return \"call %P3\\n%P3:\;movsg %1, %0\;sethi #gprelhi(%P3), %2\;setlo #gprello(%P3), %2\;sub %0,%2,%0\";
5836 [(set_attr "length" "16")
5837 (set_attr "type" "multi")])
5839 ;; ::::::::::::::::::::
5841 ;; :: Miscellaneous instructions
5843 ;; ::::::::::::::::::::
5845 ;; No operation, needed in case the user uses -g but not -O.
5850 [(set_attr "length" "4")
5851 (set_attr "type" "int")])
5853 ;; Pseudo instruction that prevents the scheduler from moving code above this
5854 ;; point. Note, type unknown is used to make sure the VLIW instructions are
5855 ;; not continued past this point.
5856 (define_insn "blockage"
5857 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5860 [(set_attr "length" "0")
5861 (set_attr "type" "unknown")])
5863 ;; ::::::::::::::::::::
5865 ;; :: Media instructions
5867 ;; ::::::::::::::::::::
5869 ;; Unimplemented instructions:
5873 [(UNSPEC_MLOGIC 100)
5880 (UNSPEC_MUNPACKH 107)
5881 (UNSPEC_MDPACKH 108)
5886 (UNSPEC_MEXPDHW 113)
5887 (UNSPEC_MEXPDHD 114)
5894 (UNSPEC_MQMULXH 121)
5900 (UNSPEC_MRDACCG 127)
5902 (UNSPEC_MWTACCG 129)
5904 (UNSPEC_MCLRACC 131)
5905 (UNSPEC_MCLRACCA 132)
5908 (UNSPEC_MDUNPACKH 135)
5909 (UNSPEC_MDUNPACKH_INTERNAL 136)
5911 (UNSPEC_MBTOHE_INTERNAL 138)
5913 (UNSPEC_MBTOHE_INTERNAL 138)
5914 (UNSPEC_MQMACH2 139)
5915 (UNSPEC_MADDACC 140)
5916 (UNSPEC_MDADDACC 141)
5918 (UNSPEC_MDROTLI 143)
5921 (UNSPEC_MDCUTSSI 146)
5922 (UNSPEC_MQSATHS 147)
5923 (UNSPEC_MHSETLOS 148)
5924 (UNSPEC_MHSETLOH 149)
5925 (UNSPEC_MHSETHIS 150)
5926 (UNSPEC_MHSETHIH 151)
5927 (UNSPEC_MHDSETS 152)
5928 (UNSPEC_MHDSETH 153)
5931 ;; Logic operations: type "mlogic"
5933 (define_expand "mand"
5934 [(set (match_operand:SI 0 "fpr_operand" "")
5935 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5936 (match_operand:SI 2 "fpr_operand" "")
5940 "operands[3] = GEN_INT (FRV_BUILTIN_MAND);")
5942 (define_expand "mor"
5943 [(set (match_operand:SI 0 "fpr_operand" "")
5944 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5945 (match_operand:SI 2 "fpr_operand" "")
5949 "operands[3] = GEN_INT (FRV_BUILTIN_MOR);")
5951 (define_expand "mxor"
5952 [(set (match_operand:SI 0 "fpr_operand" "")
5953 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5954 (match_operand:SI 2 "fpr_operand" "")
5958 "operands[3] = GEN_INT (FRV_BUILTIN_MXOR);")
5960 (define_insn "*mlogic"
5961 [(set (match_operand:SI 0 "fpr_operand" "=f")
5962 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5963 (match_operand:SI 2 "fpr_operand" "f")
5964 (match_operand:SI 3 "const_int_operand" "n")]
5969 switch (INTVAL (operands[3]))
5972 case FRV_BUILTIN_MAND: return \"mand %1, %2, %0\";
5973 case FRV_BUILTIN_MOR: return \"mor %1, %2, %0\";
5974 case FRV_BUILTIN_MXOR: return \"mxor %1, %2, %0\";
5977 fatal_insn (\"Bad media insn, mlogic\", insn);
5979 [(set_attr "length" "4")
5980 (set_attr "type" "mlogic")])
5982 (define_insn "*cond_exec_mlogic"
5984 (match_operator 0 "ccr_eqne_operator"
5985 [(match_operand 1 "cr_operand" "C")
5987 (set (match_operand:SI 2 "fpr_operand" "=f")
5988 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
5989 (match_operand:SI 4 "fpr_operand" "f")
5990 (match_operand:SI 5 "const_int_operand" "n")]
5995 switch (INTVAL (operands[5]))
5998 case FRV_BUILTIN_MAND: return \"cmand %3, %4, %2, %1, %e0\";
5999 case FRV_BUILTIN_MOR: return \"cmor %3, %4, %2, %1, %e0\";
6000 case FRV_BUILTIN_MXOR: return \"cmxor %3, %4, %2, %1, %e0\";
6003 fatal_insn (\"Bad media insn, cond_exec_mlogic\", insn);
6005 [(set_attr "length" "4")
6006 (set_attr "type" "mlogic")])
6008 ;; Logical not: type "mlogic"
6011 [(set (match_operand:SI 0 "fpr_operand" "=f")
6012 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MNOT))]
6015 [(set_attr "length" "4")
6016 (set_attr "type" "mlogic")])
6018 (define_insn "*cond_exec_mnot"
6020 (match_operator 0 "ccr_eqne_operator"
6021 [(match_operand 1 "cr_operand" "C")
6023 (set (match_operand:SI 2 "fpr_operand" "=f")
6024 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")] UNSPEC_MNOT)))]
6026 "cmnot %3, %2, %1, %e0"
6027 [(set_attr "length" "4")
6028 (set_attr "type" "mlogic")])
6030 ;; Dual average (halfword): type "maveh"
6032 (define_insn "maveh"
6033 [(set (match_operand:SI 0 "fpr_operand" "=f")
6034 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6035 (match_operand:SI 2 "fpr_operand" "f")]
6039 [(set_attr "length" "4")
6040 (set_attr "type" "maveh")])
6042 ;; Dual saturation (halfword): type "msath"
6044 (define_expand "msaths"
6045 [(set (match_operand:SI 0 "fpr_operand" "=f")
6046 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6047 (match_operand:SI 2 "fpr_operand" "f")
6051 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHS);")
6053 (define_expand "msathu"
6054 [(set (match_operand:SI 0 "fpr_operand" "=f")
6055 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6056 (match_operand:SI 2 "fpr_operand" "f")
6060 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHU);")
6062 (define_insn "*msath"
6063 [(set (match_operand:SI 0 "fpr_operand" "=f")
6064 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6065 (match_operand:SI 2 "fpr_operand" "f")
6066 (match_operand:SI 3 "const_int_operand" "n")]
6071 switch (INTVAL (operands[3]))
6074 case FRV_BUILTIN_MSATHS: return \"msaths %1, %2, %0\";
6075 case FRV_BUILTIN_MSATHU: return \"msathu %1, %2, %0\";
6078 fatal_insn (\"Bad media insn, msath\", insn);
6080 [(set_attr "length" "4")
6081 (set_attr "type" "msath")])
6083 ;; Dual addition/subtraction with saturation (halfword): type "maddh"
6085 (define_expand "maddhss"
6086 [(set (match_operand:SI 0 "fpr_operand" "=f")
6087 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6088 (match_operand:SI 2 "fpr_operand" "f")
6092 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHSS);")
6094 (define_expand "maddhus"
6095 [(set (match_operand:SI 0 "fpr_operand" "=f")
6096 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6097 (match_operand:SI 2 "fpr_operand" "f")
6101 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHUS);")
6103 (define_expand "msubhss"
6104 [(set (match_operand:SI 0 "fpr_operand" "=f")
6105 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6106 (match_operand:SI 2 "fpr_operand" "f")
6110 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHSS);")
6112 (define_expand "msubhus"
6113 [(set (match_operand:SI 0 "fpr_operand" "=f")
6114 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6115 (match_operand:SI 2 "fpr_operand" "f")
6119 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHUS);")
6121 (define_insn "*maddh"
6122 [(set (match_operand:SI 0 "fpr_operand" "=f")
6123 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6124 (match_operand:SI 2 "fpr_operand" "f")
6125 (match_operand:SI 3 "const_int_operand" "n")]
6130 switch (INTVAL (operands[3]))
6133 case FRV_BUILTIN_MADDHSS: return \"maddhss %1, %2, %0\";
6134 case FRV_BUILTIN_MADDHUS: return \"maddhus %1, %2, %0\";
6135 case FRV_BUILTIN_MSUBHSS: return \"msubhss %1, %2, %0\";
6136 case FRV_BUILTIN_MSUBHUS: return \"msubhus %1, %2, %0\";
6139 fatal_insn (\"Bad media insn, maddh\", insn);
6141 [(set_attr "length" "4")
6142 (set_attr "type" "maddh")])
6144 (define_insn "*cond_exec_maddh"
6146 (match_operator 0 "ccr_eqne_operator"
6147 [(match_operand 1 "cr_operand" "C")
6149 (set (match_operand:SI 2 "fpr_operand" "=f")
6150 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6151 (match_operand:SI 4 "fpr_operand" "f")
6152 (match_operand:SI 5 "const_int_operand" "n")]
6157 switch (INTVAL (operands[5]))
6160 case FRV_BUILTIN_MADDHSS: return \"cmaddhss %3, %4, %2, %1, %e0\";
6161 case FRV_BUILTIN_MADDHUS: return \"cmaddhus %3, %4, %2, %1, %e0\";
6162 case FRV_BUILTIN_MSUBHSS: return \"cmsubhss %3, %4, %2, %1, %e0\";
6163 case FRV_BUILTIN_MSUBHUS: return \"cmsubhus %3, %4, %2, %1, %e0\";
6166 fatal_insn (\"Bad media insn, cond_exec_maddh\", insn);
6168 [(set_attr "length" "4")
6169 (set_attr "type" "maddh")])
6171 ;; Quad addition/subtraction with saturation (halfword): type "mqaddh"
6173 (define_expand "mqaddhss"
6174 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6175 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6176 (match_operand:DI 2 "even_fpr_operand" "h")
6180 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHSS);")
6182 (define_expand "mqaddhus"
6183 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6184 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6185 (match_operand:DI 2 "even_fpr_operand" "h")
6189 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHUS);")
6191 (define_expand "mqsubhss"
6192 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6193 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6194 (match_operand:DI 2 "even_fpr_operand" "h")
6198 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHSS);")
6200 (define_expand "mqsubhus"
6201 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6202 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6203 (match_operand:DI 2 "even_fpr_operand" "h")
6207 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHUS);")
6209 (define_insn "*mqaddh"
6210 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6211 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6212 (match_operand:DI 2 "even_fpr_operand" "h")
6213 (match_operand:SI 3 "const_int_operand" "n")]
6218 switch (INTVAL (operands[3]))
6221 case FRV_BUILTIN_MQADDHSS: return \"mqaddhss %1, %2, %0\";
6222 case FRV_BUILTIN_MQADDHUS: return \"mqaddhus %1, %2, %0\";
6223 case FRV_BUILTIN_MQSUBHSS: return \"mqsubhss %1, %2, %0\";
6224 case FRV_BUILTIN_MQSUBHUS: return \"mqsubhus %1, %2, %0\";
6227 fatal_insn (\"Bad media insn, mqaddh\", insn);
6229 [(set_attr "length" "4")
6230 (set_attr "type" "mqaddh")])
6232 (define_insn "*cond_exec_mqaddh"
6234 (match_operator 0 "ccr_eqne_operator"
6235 [(match_operand 1 "cr_operand" "C")
6237 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6238 (unspec:DI [(match_operand:DI 3 "even_fpr_operand" "h")
6239 (match_operand:DI 4 "even_fpr_operand" "h")
6240 (match_operand:SI 5 "const_int_operand" "n")]
6245 switch (INTVAL (operands[5]))
6248 case FRV_BUILTIN_MQADDHSS: return \"cmqaddhss %3, %4, %2, %1, %e0\";
6249 case FRV_BUILTIN_MQADDHUS: return \"cmqaddhus %3, %4, %2, %1, %e0\";
6250 case FRV_BUILTIN_MQSUBHSS: return \"cmqsubhss %3, %4, %2, %1, %e0\";
6251 case FRV_BUILTIN_MQSUBHUS: return \"cmqsubhus %3, %4, %2, %1, %e0\";
6254 fatal_insn (\"Bad media insn, cond_exec_mqaddh\", insn);
6256 [(set_attr "length" "4")
6257 (set_attr "type" "mqaddh")])
6259 ;; Pack halfword: type "mpackh"
6261 (define_insn "mpackh"
6262 [(set (match_operand:SI 0 "fpr_operand" "=f")
6263 (unspec:SI [(match_operand:HI 1 "fpr_operand" "f")
6264 (match_operand:HI 2 "fpr_operand" "f")]
6268 [(set_attr "length" "4")
6269 (set_attr "type" "mpackh")])
6271 ;; Unpack halfword: type "mpackh"
6273 (define_insn "munpackh"
6274 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6275 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6279 [(set_attr "length" "4")
6280 (set_attr "type" "munpackh")])
6282 ;; Dual pack halfword: type "mdpackh"
6284 (define_insn "mdpackh"
6285 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6286 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6287 (match_operand:DI 2 "even_fpr_operand" "h")]
6290 "mdpackh %1, %2, %0"
6291 [(set_attr "length" "4")
6292 (set_attr "type" "mdpackh")])
6294 ;; Byte-halfword conversion: type "mbhconv"
6296 (define_insn "mbtoh"
6297 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6298 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6302 [(set_attr "length" "4")
6303 (set_attr "type" "mbhconv")])
6305 (define_insn "*cond_exec_mbtoh"
6307 (match_operator 0 "ccr_eqne_operator"
6308 [(match_operand 1 "cr_operand" "C")
6310 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6311 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")]
6314 "cmbtoh %3, %2, %1, %e0"
6315 [(set_attr "length" "4")
6316 (set_attr "type" "mbhconv")])
6318 (define_insn "mhtob"
6319 [(set (match_operand:SI 0 "fpr_operand" "=f")
6320 (unspec:SI [(match_operand:DI 1 "even_fpr_operand" "h")]
6324 [(set_attr "length" "4")
6325 (set_attr "type" "mbhconv")])
6327 (define_insn "*cond_exec_mhtob"
6329 (match_operator 0 "ccr_eqne_operator"
6330 [(match_operand 1 "cr_operand" "C")
6332 (set (match_operand:SI 2 "fpr_operand" "=f")
6333 (unspec:SI [(match_operand:DI 3 "even_fpr_operand" "h")]
6336 "cmhtob %3, %2, %1, %e0"
6337 [(set_attr "length" "4")
6338 (set_attr "type" "mbhconv")])
6340 ;; Rotate: type "mrot"
6342 (define_expand "mrotli"
6343 [(set (match_operand:SI 0 "fpr_operand" "")
6344 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6345 (match_operand:SI 2 "uint5_operand" "")
6349 "operands[3] = GEN_INT (FRV_BUILTIN_MROTLI);")
6351 (define_expand "mrotri"
6352 [(set (match_operand:SI 0 "fpr_operand" "")
6353 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6354 (match_operand:SI 2 "uint5_operand" "")
6358 "operands[3] = GEN_INT (FRV_BUILTIN_MROTRI);")
6360 (define_insn "*mrot"
6361 [(set (match_operand:SI 0 "fpr_operand" "=f")
6362 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6363 (match_operand:SI 2 "uint5_operand" "I")
6364 (match_operand:SI 3 "const_int_operand" "n")]
6369 switch (INTVAL (operands[3]))
6372 case FRV_BUILTIN_MROTLI: return \"mrotli %1, %2, %0\";
6373 case FRV_BUILTIN_MROTRI: return \"mrotri %1, %2, %0\";
6376 fatal_insn (\"Bad media insn, mrot\", insn);
6378 [(set_attr "length" "4")
6379 (set_attr "type" "mrot")])
6381 ;; Dual shift halfword: type "msh"
6383 (define_expand "msllhi"
6384 [(set (match_operand:SI 0 "fpr_operand" "")
6385 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6386 (match_operand:SI 2 "uint4_operand" "")
6390 "operands[3] = GEN_INT (FRV_BUILTIN_MSLLHI);")
6392 (define_expand "msrlhi"
6393 [(set (match_operand:SI 0 "fpr_operand" "")
6394 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6395 (match_operand:SI 2 "uint4_operand" "")
6399 "operands[3] = GEN_INT (FRV_BUILTIN_MSRLHI);")
6401 (define_expand "msrahi"
6402 [(set (match_operand:SI 0 "fpr_operand" "")
6403 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6404 (match_operand:SI 2 "uint4_operand" "")
6408 "operands[3] = GEN_INT (FRV_BUILTIN_MSRAHI);")
6410 (define_insn "*mshift"
6411 [(set (match_operand:SI 0 "fpr_operand" "=f")
6412 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6413 (match_operand:SI 2 "uint4_operand" "I")
6414 (match_operand:SI 3 "const_int_operand" "n")]
6419 switch (INTVAL (operands[3]))
6422 case FRV_BUILTIN_MSLLHI: return \"msllhi %1, %2, %0\";
6423 case FRV_BUILTIN_MSRLHI: return \"msrlhi %1, %2, %0\";
6424 case FRV_BUILTIN_MSRAHI: return \"msrahi %1, %2, %0\";
6427 fatal_insn (\"Bad media insn, mshift\", insn);
6429 [(set_attr "length" "4")
6430 (set_attr "type" "mshift")])
6432 ;; Expand halfword to word: type "mexpdhw"
6434 (define_insn "mexpdhw"
6435 [(set (match_operand:SI 0 "even_fpr_operand" "=h")
6436 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6437 (match_operand:SI 2 "uint1_operand" "I")]
6440 "mexpdhw %1, %2, %0"
6441 [(set_attr "length" "4")
6442 (set_attr "type" "mexpdhw")])
6444 (define_insn "*cond_exec_mexpdhw"
6446 (match_operator 0 "ccr_eqne_operator"
6447 [(match_operand 1 "cr_operand" "C")
6449 (set (match_operand:SI 2 "even_fpr_operand" "=h")
6450 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6451 (match_operand:SI 4 "uint1_operand" "I")]
6454 "cmexpdhw %3, %4, %2, %1, %e0"
6455 [(set_attr "length" "4")
6456 (set_attr "type" "mexpdhw")])
6458 ;; Expand halfword to double: type "mexpdhd"
6460 (define_insn "mexpdhd"
6461 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6462 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6463 (match_operand:SI 2 "uint1_operand" "I")]
6466 "mexpdhd %1, %2, %0"
6467 [(set_attr "length" "4")
6468 (set_attr "type" "mexpdhd")])
6470 (define_insn "*cond_exec_mexpdhd"
6472 (match_operator 0 "ccr_eqne_operator"
6473 [(match_operand 1 "cr_operand" "C")
6475 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6476 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6477 (match_operand:SI 4 "uint1_operand" "I")]
6480 "cmexpdhd %3, %4, %2, %1, %e0"
6481 [(set_attr "length" "4")
6482 (set_attr "type" "mexpdhd")])
6484 ;; FR cut: type "mwcut"
6486 (define_insn "mwcut"
6487 [(set (match_operand:SI 0 "fpr_operand" "=f")
6488 (unspec:SI [(match_operand:DI 1 "fpr_operand" "f")
6489 (match_operand:SI 2 "fpr_or_int6_operand" "fI")]
6492 "mwcut%i2 %1, %2, %0"
6493 [(set_attr "length" "4")
6494 (set_attr "type" "mwcut")])
6496 ;; Dual multiplication (halfword): type "mmulh"
6498 (define_expand "mmulhs"
6499 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6500 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6501 (match_operand:SI 2 "fpr_operand" "f")
6504 (set (match_operand:HI 3 "accg_operand" "=B")
6505 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6507 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHS);")
6509 (define_expand "mmulhu"
6510 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6511 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6512 (match_operand:SI 2 "fpr_operand" "f")
6515 (set (match_operand:HI 3 "accg_operand" "=B")
6516 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6518 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHU);")
6520 (define_insn "*mmulh"
6521 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6522 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6523 (match_operand:SI 2 "fpr_operand" "f")
6524 (match_operand:SI 3 "const_int_operand" "n")]
6526 (set (match_operand:HI 4 "accg_operand" "=B")
6527 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]
6531 switch (INTVAL (operands[3]))
6534 case FRV_BUILTIN_MMULHS: return \"mmulhs %1, %2, %0\";
6535 case FRV_BUILTIN_MMULHU: return \"mmulhu %1, %2, %0\";
6538 fatal_insn (\"Bad media insn, mmulh\", insn);
6540 [(set_attr "length" "4")
6541 (set_attr "type" "mmulh")])
6543 (define_insn "*cond_exec_mmulh"
6545 (match_operator 0 "ccr_eqne_operator"
6546 [(match_operand 1 "cr_operand" "C")
6548 (parallel [(set (match_operand:DI 2 "even_acc_operand" "=b")
6549 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6550 (match_operand:SI 4 "fpr_operand" "f")
6551 (match_operand:SI 5 "const_int_operand" "n")]
6553 (set (match_operand:HI 6 "accg_operand" "=B")
6554 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]))]
6558 switch (INTVAL (operands[5]))
6561 case FRV_BUILTIN_MMULHS: return \"cmmulhs %3, %4, %2, %1, %e0\";
6562 case FRV_BUILTIN_MMULHU: return \"cmmulhu %3, %4, %2, %1, %e0\";
6565 fatal_insn (\"Bad media insn, cond_exec_mmulh\", insn);
6567 [(set_attr "length" "4")
6568 (set_attr "type" "mmulh")])
6570 ;; Dual cross multiplication (halfword): type "mmulxh"
6572 (define_expand "mmulxhs"
6573 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6574 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6575 (match_operand:SI 2 "fpr_operand" "f")
6578 (set (match_operand:HI 3 "accg_operand" "=B")
6579 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6581 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHS);")
6583 (define_expand "mmulxhu"
6584 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6585 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6586 (match_operand:SI 2 "fpr_operand" "f")
6589 (set (match_operand:HI 3 "accg_operand" "=B")
6590 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6592 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHU);")
6594 (define_insn "*mmulxh"
6595 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6596 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6597 (match_operand:SI 2 "fpr_operand" "f")
6598 (match_operand:SI 3 "const_int_operand" "n")]
6600 (set (match_operand:HI 4 "accg_operand" "=B")
6601 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))]
6605 switch (INTVAL (operands[3]))
6608 case FRV_BUILTIN_MMULXHS: return \"mmulxhs %1, %2, %0\";
6609 case FRV_BUILTIN_MMULXHU: return \"mmulxhu %1, %2, %0\";
6612 fatal_insn (\"Bad media insn, mmulxh\", insn);
6614 [(set_attr "length" "4")
6615 (set_attr "type" "mmulxh")])
6617 ;; Dual product-sum (halfword): type "mmach"
6619 (define_expand "mmachs"
6620 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6621 (unspec:DI [(match_dup 0)
6622 (match_operand:SI 1 "fpr_operand" "f")
6623 (match_operand:SI 2 "fpr_operand" "f")
6624 (match_operand:HI 3 "accg_operand" "+B")
6628 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6630 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHS);")
6632 (define_expand "mmachu"
6633 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6634 (unspec:DI [(match_dup 0)
6635 (match_operand:SI 1 "fpr_operand" "f")
6636 (match_operand:SI 2 "fpr_operand" "f")
6637 (match_operand:HI 3 "accg_operand" "+B")
6641 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6643 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHU);")
6645 (define_insn "*mmach"
6646 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6647 (unspec:DI [(match_dup 0)
6648 (match_operand:SI 1 "fpr_operand" "f")
6649 (match_operand:SI 2 "fpr_operand" "f")
6650 (match_operand:HI 3 "accg_operand" "+B")
6651 (match_operand:SI 4 "const_int_operand" "n")]
6653 (set (match_dup 3) (unspec:HI [(const_int 0)] UNSPEC_MMACH))]
6657 switch (INTVAL (operands[4]))
6660 case FRV_BUILTIN_MMACHS: return \"mmachs %1, %2, %0\";
6661 case FRV_BUILTIN_MMACHU: return \"mmachu %1, %2, %0\";
6664 fatal_insn (\"Bad media insn, mmach\", insn);
6666 [(set_attr "length" "4")
6667 (set_attr "type" "mmach")])
6669 (define_insn "*cond_exec_mmach"
6671 (match_operator 0 "ccr_eqne_operator"
6672 [(match_operand 1 "cr_operand" "C")
6674 (parallel [(set (match_operand:DI 2 "even_acc_operand" "+b")
6675 (unspec:DI [(match_dup 2)
6676 (match_operand:SI 3 "fpr_operand" "f")
6677 (match_operand:SI 4 "fpr_operand" "f")
6678 (match_operand:HI 5 "accg_operand" "+B")
6679 (match_operand:SI 6 "const_int_operand" "n")]
6682 (unspec:HI [(const_int 0)] UNSPEC_MMACH))]))]
6686 switch (INTVAL (operands[6]))
6689 case FRV_BUILTIN_MMACHS: return \"cmmachs %3, %4, %2, %1, %e0\";
6690 case FRV_BUILTIN_MMACHU: return \"cmmachu %3, %4, %2, %1, %e0\";
6693 fatal_insn (\"Bad media insn, cond_exec_mmach\", insn);
6695 [(set_attr "length" "4")
6696 (set_attr "type" "mmach")])
6698 ;; Dual product-difference: type "mmrdh"
6700 (define_expand "mmrdhs"
6701 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6702 (unspec:DI [(match_dup 0)
6703 (match_operand:SI 1 "fpr_operand" "f")
6704 (match_operand:SI 2 "fpr_operand" "f")
6705 (match_operand:HI 3 "accg_operand" "+B")
6709 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6711 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHS);")
6713 (define_expand "mmrdhu"
6714 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6715 (unspec:DI [(match_dup 0)
6716 (match_operand:SI 1 "fpr_operand" "f")
6717 (match_operand:SI 2 "fpr_operand" "f")
6718 (match_operand:HI 3 "accg_operand" "+B")
6722 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6724 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHU);")
6726 (define_insn "*mmrdh"
6727 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6728 (unspec:DI [(match_dup 0)
6729 (match_operand:SI 1 "fpr_operand" "f")
6730 (match_operand:SI 2 "fpr_operand" "f")
6731 (match_operand:HI 3 "accg_operand" "+B")
6732 (match_operand:SI 4 "const_int_operand" "n")]
6735 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))]
6739 switch (INTVAL (operands[4]))
6742 case FRV_BUILTIN_MMRDHS: return \"mmrdhs %1, %2, %0\";
6743 case FRV_BUILTIN_MMRDHU: return \"mmrdhu %1, %2, %0\";
6746 fatal_insn (\"Bad media insn, mrdh\", insn);
6748 [(set_attr "length" "4")
6749 (set_attr "type" "mmrdh")])
6751 ;; Quad multiply (halfword): type "mqmulh"
6753 (define_expand "mqmulhs"
6754 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6755 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6756 (match_operand:DI 2 "even_fpr_operand" "h")
6759 (set (match_operand:V4QI 3 "accg_operand" "=B")
6760 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6762 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHS);")
6764 (define_expand "mqmulhu"
6765 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6766 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6767 (match_operand:DI 2 "even_fpr_operand" "h")
6770 (set (match_operand:V4QI 3 "accg_operand" "=B")
6771 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6773 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHU);")
6775 (define_insn "*mqmulh"
6776 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6777 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6778 (match_operand:DI 2 "even_fpr_operand" "h")
6779 (match_operand:SI 3 "const_int_operand" "n")]
6781 (set (match_operand:V4QI 4 "accg_operand" "=B")
6782 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]
6786 switch (INTVAL (operands[3]))
6789 case FRV_BUILTIN_MQMULHS: return \"mqmulhs %1, %2, %0\";
6790 case FRV_BUILTIN_MQMULHU: return \"mqmulhu %1, %2, %0\";
6793 fatal_insn (\"Bad media insn, mqmulh\", insn);
6795 [(set_attr "length" "4")
6796 (set_attr "type" "mqmulh")])
6798 (define_insn "*cond_exec_mqmulh"
6800 (match_operator 0 "ccr_eqne_operator"
6801 [(match_operand 1 "cr_operand" "C")
6803 (parallel [(set (match_operand:V4SI 2 "quad_acc_operand" "=A")
6804 (unspec:V4SI [(match_operand:DI 3 "even_fpr_operand" "h")
6805 (match_operand:DI 4 "even_fpr_operand" "h")
6806 (match_operand:SI 5 "const_int_operand" "n")]
6808 (set (match_operand:V4QI 6 "accg_operand" "=B")
6809 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]))]
6813 switch (INTVAL (operands[5]))
6816 case FRV_BUILTIN_MQMULHS: return \"cmqmulhs %3, %4, %2, %1, %e0\";
6817 case FRV_BUILTIN_MQMULHU: return \"cmqmulhu %3, %4, %2, %1, %e0\";
6820 fatal_insn (\"Bad media insn, cond_exec_mqmulh\", insn);
6822 [(set_attr "length" "4")
6823 (set_attr "type" "mqmulh")])
6825 ;; Quad cross multiply (halfword): type "mqmulxh"
6827 (define_expand "mqmulxhs"
6828 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6829 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6830 (match_operand:DI 2 "even_fpr_operand" "h")
6833 (set (match_operand:V4QI 3 "accg_operand" "=B")
6834 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6836 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHS);")
6838 (define_expand "mqmulxhu"
6839 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6840 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6841 (match_operand:DI 2 "even_fpr_operand" "h")
6844 (set (match_operand:V4QI 3 "accg_operand" "=B")
6845 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6847 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHU);")
6849 (define_insn "*mqmulxh"
6850 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6851 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6852 (match_operand:DI 2 "even_fpr_operand" "h")
6853 (match_operand:SI 3 "const_int_operand" "n")]
6855 (set (match_operand:V4QI 4 "accg_operand" "=B")
6856 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))]
6860 switch (INTVAL (operands[3]))
6863 case FRV_BUILTIN_MQMULXHS: return \"mqmulxhs %1, %2, %0\";
6864 case FRV_BUILTIN_MQMULXHU: return \"mqmulxhu %1, %2, %0\";
6867 fatal_insn (\"Bad media insn, mqmulxh\", insn);
6869 [(set_attr "length" "4")
6870 (set_attr "type" "mqmulxh")])
6872 ;; Quad product-sum (halfword): type "mqmach"
6874 (define_expand "mqmachs"
6875 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6876 (unspec:V4SI [(match_dup 0)
6877 (match_operand:DI 1 "even_fpr_operand" "h")
6878 (match_operand:DI 2 "even_fpr_operand" "h")
6879 (match_operand:V4QI 3 "accg_operand" "+B")
6883 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6885 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHS);")
6887 (define_expand "mqmachu"
6888 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6889 (unspec:V4SI [(match_dup 0)
6890 (match_operand:DI 1 "even_fpr_operand" "h")
6891 (match_operand:DI 2 "even_fpr_operand" "h")
6892 (match_operand:V4QI 3 "accg_operand" "+B")
6896 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6898 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHU);")
6900 (define_insn "*mqmach"
6901 [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6902 (unspec:V4SI [(match_dup 0)
6903 (match_operand:DI 1 "even_fpr_operand" "h")
6904 (match_operand:DI 2 "even_fpr_operand" "h")
6905 (match_operand:V4QI 3 "accg_operand" "+B")
6906 (match_operand:SI 4 "const_int_operand" "n")]
6909 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]
6913 switch (INTVAL (operands[4]))
6916 case FRV_BUILTIN_MQMACHS: return \"mqmachs %1, %2, %0\";
6917 case FRV_BUILTIN_MQMACHU: return \"mqmachu %1, %2, %0\";
6920 fatal_insn (\"Bad media insn, mqmach\", insn);
6922 [(set_attr "length" "4")
6923 (set_attr "type" "mqmach")])
6925 (define_insn "*cond_exec_mqmach"
6927 (match_operator 0 "ccr_eqne_operator"
6928 [(match_operand 1 "cr_operand" "C")
6930 (parallel [(set (match_operand:V4SI 2 "even_acc_operand" "+A")
6931 (unspec:V4SI [(match_dup 2)
6932 (match_operand:DI 3 "even_fpr_operand" "h")
6933 (match_operand:DI 4 "even_fpr_operand" "h")
6934 (match_operand:V4QI 5 "accg_operand" "+B")
6935 (match_operand:SI 6 "const_int_operand" "n")]
6938 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]))]
6942 switch (INTVAL (operands[6]))
6945 case FRV_BUILTIN_MQMACHS: return \"cmqmachs %3, %4, %2, %1, %e0\";
6946 case FRV_BUILTIN_MQMACHU: return \"cmqmachu %3, %4, %2, %1, %e0\";
6949 fatal_insn (\"Bad media insn, cond_exec_mqmach\", insn);
6951 [(set_attr "length" "4")
6952 (set_attr "type" "mqmach")])
6954 ;; Dual complex number product-sum (halfword)
6956 (define_expand "mcpxrs"
6957 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6958 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6959 (match_operand:SI 2 "fpr_operand" "f")
6962 (set (match_operand:QI 3 "accg_operand" "=B")
6963 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6965 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRS);")
6967 (define_expand "mcpxru"
6968 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6969 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6970 (match_operand:SI 2 "fpr_operand" "f")
6973 (set (match_operand:QI 3 "accg_operand" "=B")
6974 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6976 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRU);")
6978 (define_expand "mcpxis"
6979 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6980 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6981 (match_operand:SI 2 "fpr_operand" "f")
6984 (set (match_operand:QI 3 "accg_operand" "=B")
6985 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6987 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIS);")
6989 (define_expand "mcpxiu"
6990 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6991 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6992 (match_operand:SI 2 "fpr_operand" "f")
6995 (set (match_operand:QI 3 "accg_operand" "=B")
6996 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6998 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIU);")
7000 (define_insn "*mcpx"
7001 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7002 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7003 (match_operand:SI 2 "fpr_operand" "f")
7004 (match_operand:SI 3 "const_int_operand" "n")]
7006 (set (match_operand:QI 4 "accg_operand" "=B")
7007 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
7011 switch (INTVAL (operands[3]))
7014 case FRV_BUILTIN_MCPXRS: return \"mcpxrs %1, %2, %0\";
7015 case FRV_BUILTIN_MCPXRU: return \"mcpxru %1, %2, %0\";
7016 case FRV_BUILTIN_MCPXIS: return \"mcpxis %1, %2, %0\";
7017 case FRV_BUILTIN_MCPXIU: return \"mcpxiu %1, %2, %0\";
7020 fatal_insn (\"Bad media insn, mcpx\", insn);
7022 [(set_attr "length" "4")
7023 (set_attr "type" "mcpx")])
7025 (define_insn "*cond_exec_mcpx"
7027 (match_operator 0 "ccr_eqne_operator"
7028 [(match_operand 1 "cr_operand" "C")
7030 (parallel [(set (match_operand:SI 2 "acc_operand" "=a")
7031 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
7032 (match_operand:SI 4 "fpr_operand" "f")
7033 (match_operand:SI 5 "const_int_operand" "n")]
7035 (set (match_operand:QI 6 "accg_operand" "=B")
7036 (unspec:QI [(const_int 0)] UNSPEC_MCPX))]))]
7040 switch (INTVAL (operands[5]))
7043 case FRV_BUILTIN_MCPXRS: return \"cmcpxrs %3, %4, %2, %1, %e0\";
7044 case FRV_BUILTIN_MCPXRU: return \"cmcpxru %3, %4, %2, %1, %e0\";
7045 case FRV_BUILTIN_MCPXIS: return \"cmcpxis %3, %4, %2, %1, %e0\";
7046 case FRV_BUILTIN_MCPXIU: return \"cmcpxiu %3, %4, %2, %1, %e0\";
7049 fatal_insn (\"Bad media insn, cond_exec_mcpx\", insn);
7051 [(set_attr "length" "4")
7052 (set_attr "type" "mcpx")])
7054 ;; Quad complex number product-sum (halfword): type "mqcpx"
7056 (define_expand "mqcpxrs"
7057 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7058 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7059 (match_operand:DI 2 "fpr_operand" "f")
7062 (set (match_operand:HI 3 "accg_operand" "=B")
7063 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7065 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRS);")
7067 (define_expand "mqcpxru"
7068 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7069 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7070 (match_operand:DI 2 "fpr_operand" "f")
7073 (set (match_operand:HI 3 "accg_operand" "=B")
7074 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7076 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRU);")
7078 (define_expand "mqcpxis"
7079 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7080 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7081 (match_operand:DI 2 "fpr_operand" "f")
7084 (set (match_operand:HI 3 "accg_operand" "=B")
7085 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7087 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIS);")
7089 (define_expand "mqcpxiu"
7090 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
7091 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7092 (match_operand:DI 2 "fpr_operand" "f")
7095 (set (match_operand:HI 3 "accg_operand" "=B")
7096 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
7098 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIU);")
7100 (define_insn "*mqcpx"
7101 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7102 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
7103 (match_operand:DI 2 "fpr_operand" "f")
7104 (match_operand:SI 3 "const_int_operand" "n")]
7106 (set (match_operand:HI 4 "accg_operand" "=B")
7107 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))]
7111 switch (INTVAL (operands[3]))
7114 case FRV_BUILTIN_MQCPXRS: return \"mqcpxrs %1, %2, %0\";
7115 case FRV_BUILTIN_MQCPXRU: return \"mqcpxru %1, %2, %0\";
7116 case FRV_BUILTIN_MQCPXIS: return \"mqcpxis %1, %2, %0\";
7117 case FRV_BUILTIN_MQCPXIU: return \"mqcpxiu %1, %2, %0\";
7120 fatal_insn (\"Bad media insn, mqcpx\", insn);
7122 [(set_attr "length" "4")
7123 (set_attr "type" "mqcpx")])
7127 (define_expand "mcut"
7128 [(set (match_operand:SI 0 "fpr_operand" "=f")
7129 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7130 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7131 (match_operand:QI 3 "accg_operand" "B")
7135 "operands[4] = GEN_INT (FRV_BUILTIN_MCUT);")
7137 (define_expand "mcutss"
7138 [(set (match_operand:SI 0 "fpr_operand" "=f")
7139 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7140 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7141 (match_operand:QI 3 "accg_operand" "B")
7145 "operands[4] = GEN_INT (FRV_BUILTIN_MCUTSS);")
7147 (define_insn "*mcut"
7148 [(set (match_operand:SI 0 "fpr_operand" "=f")
7149 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7150 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7151 (match_operand:QI 3 "accg_operand" "B")
7152 (match_operand:SI 4 "const_int_operand" "n")]
7157 switch (INTVAL (operands[4]))
7160 case FRV_BUILTIN_MCUT: return \"mcut%i2 %1, %2, %0\";
7161 case FRV_BUILTIN_MCUTSS: return \"mcutss%i2 %1, %2, %0\";
7164 fatal_insn (\"Bad media insn, mcut\", insn);
7166 [(set_attr "length" "4")
7167 (set_attr "type" "mcut")])
7169 ;; Accumulator read: type "mrdacc"
7171 (define_insn "mrdacc"
7172 [(set (match_operand:SI 0 "fpr_operand" "=f")
7173 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")] UNSPEC_MRDACC))]
7176 [(set_attr "length" "4")
7177 (set_attr "type" "mrdacc")])
7179 (define_insn "mrdaccg"
7180 [(set (match_operand:SI 0 "fpr_operand" "=f")
7181 (unspec:SI [(match_operand:QI 1 "accg_operand" "B")] UNSPEC_MRDACCG))]
7184 [(set_attr "length" "4")
7185 (set_attr "type" "mrdacc")])
7187 ;; Accumulator write: type "mwtacc"
7189 (define_insn "mwtacc"
7190 [(set (match_operand:SI 0 "acc_operand" "=a")
7191 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACC))]
7194 [(set_attr "length" "4")
7195 (set_attr "type" "mwtacc")])
7197 (define_insn "mwtaccg"
7198 [(set (match_operand:QI 0 "accg_operand" "=B")
7199 (unspec:QI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACCG))]
7202 [(set_attr "length" "4")
7203 (set_attr "type" "mwtacc")])
7205 ;; Trap: This one executes on the control unit, not the media units.
7207 (define_insn "mtrap"
7208 [(unspec_volatile [(const_int 0)] UNSPEC_MTRAP)]
7211 [(set_attr "length" "4")
7212 (set_attr "type" "trap")])
7214 ;; Clear single accumulator: type "mclracc"
7216 (define_insn "mclracc_internal"
7217 [(set (match_operand:SI 0 "acc_operand" "=a")
7218 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7219 (set (match_operand:QI 1 "accg_operand" "=B")
7220 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))]
7223 [(set_attr "length" "4")
7224 (set_attr "type" "mclracc")])
7226 (define_expand "mclracc"
7227 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7228 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7230 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))])]
7234 if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
7237 operands[1] = frv_matching_accg_for_acc (operands[0]);
7240 ;; Clear all accumulators: type "mclracca"
7242 (define_insn "mclracca8_internal"
7243 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7244 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7245 (set (match_operand:V4SI 1 "quad_acc_operand" "=b")
7246 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7247 (set (match_operand:V4QI 2 "accg_operand" "=B")
7248 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7249 (set (match_operand:V4QI 3 "accg_operand" "=B")
7250 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7251 "TARGET_MEDIA && TARGET_ACC_8"
7253 [(set_attr "length" "4")
7254 (set_attr "type" "mclracca")])
7256 (define_insn "mclracca4_internal"
7257 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7258 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7259 (set (match_operand:V4QI 1 "accg_operand" "=B")
7260 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7261 "TARGET_MEDIA && TARGET_ACC_4"
7263 [(set_attr "length" "4")
7264 (set_attr "type" "mclracca")])
7266 (define_expand "mclracca8"
7267 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7268 (set (match_dup 1) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7269 (set (match_dup 2) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7270 (set (match_dup 3) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7271 "TARGET_MEDIA && TARGET_ACC_8"
7274 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7275 operands[1] = gen_rtx_REG (V4SImode, ACC_FIRST + 4);
7276 operands[2] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7277 operands[3] = gen_rtx_REG (V4QImode, ACCG_FIRST + 4);
7280 (define_expand "mclracca4"
7281 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7282 (set (match_dup 1) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7283 "TARGET_MEDIA && TARGET_ACC_4"
7286 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7287 operands[1] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7290 (define_insn "mcop1"
7291 [(set (match_operand:SI 0 "fpr_operand" "=f")
7292 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7293 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP1))]
7296 [(set_attr "length" "4")
7297 ;; What is the class of the insn ???
7298 (set_attr "type" "multi")])
7300 (define_insn "mcop2"
7301 [(set (match_operand:SI 0 "fpr_operand" "=f")
7302 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7303 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP2))]
7306 [(set_attr "length" "4")
7307 ;; What is the class of the insn ???
7308 (set_attr "type" "multi")])
7310 (define_insn "*mdunpackh_internal"
7311 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7312 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7313 UNSPEC_MDUNPACKH_INTERNAL))]
7316 [(set_attr "length" "4")
7317 (set_attr "type" "mdunpackh")])
7319 (define_insn_and_split "mdunpackh"
7320 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7321 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7323 (clobber (match_scratch:V4SI 2 "=x"))]
7328 (unspec:V4SI [(match_dup 1)] UNSPEC_MDUNPACKH_INTERNAL))
7335 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7336 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7337 operands[5] = frv_index_memory (operands[0], DImode, 1);
7338 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7340 [(set_attr "length" "20")
7341 (set_attr "type" "multi")])
7343 (define_insn "*mbtohe_internal"
7344 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7345 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7346 UNSPEC_MBTOHE_INTERNAL))]
7349 [(set_attr "length" "4")
7350 (set_attr "type" "mbhconve")])
7352 (define_insn_and_split "mbtohe"
7353 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7354 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7356 (clobber (match_scratch:V4SI 2 "=x"))]
7361 (unspec:V4SI [(match_dup 1)] UNSPEC_MBTOHE_INTERNAL))
7368 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7369 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7370 operands[5] = frv_index_memory (operands[0], DImode, 1);
7371 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7373 [(set_attr "length" "20")
7374 (set_attr "type" "multi")])
7376 ;; Quad product-sum (halfword) instructions only found on the FR400.
7379 (define_expand "mqxmachs"
7380 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7381 (unspec:V4SI [(match_dup 0)
7382 (match_operand:DI 1 "even_fpr_operand" "")
7383 (match_operand:DI 2 "even_fpr_operand" "")
7384 (match_operand:V4QI 3 "accg_operand" "")
7388 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7390 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACHS);")
7392 (define_expand "mqxmacxhs"
7393 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7394 (unspec:V4SI [(match_dup 0)
7395 (match_operand:DI 1 "even_fpr_operand" "")
7396 (match_operand:DI 2 "even_fpr_operand" "")
7397 (match_operand:V4QI 3 "accg_operand" "")
7401 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7403 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACXHS);")
7405 (define_expand "mqmacxhs"
7406 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7407 (unspec:V4SI [(match_dup 0)
7408 (match_operand:DI 1 "even_fpr_operand" "")
7409 (match_operand:DI 2 "even_fpr_operand" "")
7410 (match_operand:V4QI 3 "accg_operand" "")
7414 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7416 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACXHS);")
7418 (define_insn "*mqmach2"
7419 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7420 (unspec:V4SI [(match_dup 0)
7421 (match_operand:DI 1 "even_fpr_operand" "h")
7422 (match_operand:DI 2 "even_fpr_operand" "h")
7423 (match_operand:V4QI 3 "accg_operand" "+B")
7424 (match_operand:SI 4 "const_int_operand" "n")]
7427 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))]
7431 switch (INTVAL (operands[4]))
7434 case FRV_BUILTIN_MQXMACHS: return \"mqxmachs %1, %2, %0\";
7435 case FRV_BUILTIN_MQXMACXHS: return \"mqxmacxhs %1, %2, %0\";
7436 case FRV_BUILTIN_MQMACXHS: return \"mqmacxhs %1, %2, %0\";
7439 fatal_insn (\"Bad media insn, mqmach2\", insn);
7441 [(set_attr "length" "4")
7442 (set_attr "type" "mqmach")])
7444 ;; Accumulator addition/subtraction: type "maddacc"
7446 (define_expand "maddaccs"
7447 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7448 (unspec:DI [(match_dup 0)
7449 (match_operand:DI 1 "even_acc_operand" "")]
7451 (set (match_operand:HI 2 "accg_operand" "")
7452 (unspec:HI [(match_dup 2)
7453 (match_operand:HI 3 "accg_operand" "")
7457 "operands[4] = GEN_INT (FRV_BUILTIN_MADDACCS);")
7459 (define_expand "msubaccs"
7460 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7461 (unspec:DI [(match_dup 0)
7462 (match_operand:DI 1 "even_acc_operand" "")]
7464 (set (match_operand:HI 2 "accg_operand" "")
7465 (unspec:HI [(match_dup 2)
7466 (match_operand:HI 3 "accg_operand" "")
7470 "operands[4] = GEN_INT (FRV_BUILTIN_MSUBACCS);")
7472 (define_expand "masaccs"
7473 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7474 (unspec:DI [(match_dup 0)
7475 (match_operand:DI 1 "even_acc_operand" "")]
7477 (set (match_operand:HI 2 "accg_operand" "")
7478 (unspec:HI [(match_dup 2)
7479 (match_operand:HI 3 "accg_operand" "")
7483 "operands[4] = GEN_INT (FRV_BUILTIN_MASACCS);")
7485 (define_insn "*maddacc"
7486 [(set (match_operand:DI 0 "even_acc_operand" "+b")
7487 (unspec:DI [(match_dup 0)
7488 (match_operand:DI 1 "even_acc_operand" "b")]
7490 (set (match_operand:HI 2 "accg_operand" "+B")
7491 (unspec:HI [(match_dup 2)
7492 (match_operand:HI 3 "accg_operand" "B")
7493 (match_operand:SI 4 "const_int_operand" "n")]
7498 switch (INTVAL (operands[4]))
7501 case FRV_BUILTIN_MADDACCS: return \"maddaccs %1, %0\";
7502 case FRV_BUILTIN_MSUBACCS: return \"msubaccs %1, %0\";
7503 case FRV_BUILTIN_MASACCS: return \"masaccs %1, %0\";
7506 fatal_insn (\"Bad media insn, maddacc\", insn);
7508 [(set_attr "length" "4")
7509 (set_attr "type" "maddacc")])
7511 ;; Dual accumulator addition/subtraction: type "mdaddacc"
7513 (define_expand "mdaddaccs"
7514 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7515 (unspec:V4SI [(match_dup 0)
7516 (match_operand:V4SI 1 "quad_acc_operand" "")]
7518 (set (match_operand:V4QI 2 "accg_operand" "")
7519 (unspec:V4QI [(match_dup 2)
7520 (match_operand:V4QI 3 "accg_operand" "")
7522 UNSPEC_MDADDACC))])]
7524 "operands[4] = GEN_INT (FRV_BUILTIN_MDADDACCS);")
7526 (define_expand "mdsubaccs"
7527 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7528 (unspec:V4SI [(match_dup 0)
7529 (match_operand:V4SI 1 "quad_acc_operand" "")]
7531 (set (match_operand:V4QI 2 "accg_operand" "")
7532 (unspec:V4QI [(match_dup 2)
7533 (match_operand:V4QI 3 "accg_operand" "")
7535 UNSPEC_MDADDACC))])]
7537 "operands[4] = GEN_INT (FRV_BUILTIN_MDSUBACCS);")
7539 (define_expand "mdasaccs"
7540 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7541 (unspec:V4SI [(match_dup 0)
7542 (match_operand:V4SI 1 "quad_acc_operand" "")]
7544 (set (match_operand:V4QI 2 "accg_operand" "")
7545 (unspec:V4QI [(match_dup 2)
7546 (match_operand:V4QI 3 "accg_operand" "")
7548 UNSPEC_MDADDACC))])]
7550 "operands[4] = GEN_INT (FRV_BUILTIN_MDASACCS);")
7552 (define_insn "*mdaddacc"
7553 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7554 (unspec:V4SI [(match_dup 0)
7555 (match_operand:V4SI 1 "quad_acc_operand" "A")]
7557 (set (match_operand:V4QI 2 "accg_operand" "+B")
7558 (unspec:V4QI [(match_dup 2)
7559 (match_operand:V4QI 3 "accg_operand" "B")
7560 (match_operand:SI 4 "const_int_operand" "n")]
7565 switch (INTVAL (operands[4]))
7568 case FRV_BUILTIN_MDADDACCS: return \"mdaddaccs %1, %0\";
7569 case FRV_BUILTIN_MDSUBACCS: return \"mdsubaccs %1, %0\";
7570 case FRV_BUILTIN_MDASACCS: return \"mdasaccs %1, %0\";
7573 fatal_insn (\"Bad media insn, mdaddacc\", insn);
7575 [(set_attr "length" "4")
7576 (set_attr "type" "mdaddacc")])
7578 ;; Dual absolute (halfword): type "mabsh"
7580 (define_insn "mabshs"
7581 [(set (match_operand:SI 0 "fpr_operand" "=f")
7582 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MABSHS))]
7585 [(set_attr "length" "4")
7586 (set_attr "type" "mabsh")])
7588 ;; Dual rotate: type "mdrot"
7590 (define_insn "mdrotli"
7591 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7592 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7593 (match_operand:SI 2 "uint5_operand" "I")]
7596 "mdrotli %1, %2, %0"
7597 [(set_attr "length" "4")
7598 (set_attr "type" "mdrot")])
7600 ;; Dual coupling (concatenation): type "mcpl"
7602 (define_insn "mcplhi"
7603 [(set (match_operand:SI 0 "fpr_operand" "=f")
7604 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7605 (match_operand:SI 2 "uint4_operand" "I")]
7609 [(set_attr "length" "4")
7610 (set_attr "type" "mcpl")])
7612 (define_insn "mcpli"
7613 [(set (match_operand:SI 0 "fpr_operand" "=f")
7614 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7615 (match_operand:SI 2 "uint5_operand" "I")]
7619 [(set_attr "length" "4")
7620 (set_attr "type" "mcpl")])
7622 ;; Dual cut: type "mdcut"
7624 (define_insn "mdcutssi"
7625 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7626 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")
7627 (match_operand:SI 2 "int6_operand" "I")
7628 (match_operand:HI 3 "accg_operand" "B")]
7631 "mdcutssi %1, %2, %0"
7632 [(set_attr "length" "4")
7633 (set_attr "type" "mdcut")])
7635 ;; Quad saturate (halfword): type "mqsath"
7637 (define_insn "mqsaths"
7638 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7639 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7640 (match_operand:DI 2 "even_fpr_operand" "h")]
7643 "mqsaths %1, %2, %0"
7644 [(set_attr "length" "4")
7645 (set_attr "type" "mqsath")])
7647 ;; Set hi/lo instructions: type "mset"
7649 (define_insn "mhsetlos"
7650 [(set (match_operand:SI 0 "fpr_operand" "=f")
7651 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7652 (match_operand:SI 2 "int12_operand" "NOP")]
7656 [(set_attr "length" "4")
7657 (set_attr "type" "mset")])
7659 (define_insn "mhsetloh"
7660 [(set (match_operand:SI 0 "fpr_operand" "=f")
7661 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7662 (match_operand:SI 2 "int5_operand" "I")]
7666 [(set_attr "length" "4")
7667 (set_attr "type" "mset")])
7669 (define_insn "mhsethis"
7670 [(set (match_operand:SI 0 "fpr_operand" "=f")
7671 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7672 (match_operand:SI 2 "int12_operand" "NOP")]
7676 [(set_attr "length" "4")
7677 (set_attr "type" "mset")])
7679 (define_insn "mhsethih"
7680 [(set (match_operand:SI 0 "fpr_operand" "=f")
7681 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7682 (match_operand:SI 2 "int5_operand" "I")]
7686 [(set_attr "length" "4")
7687 (set_attr "type" "mset")])
7689 (define_insn "mhdsets"
7690 [(set (match_operand:SI 0 "fpr_operand" "=f")
7691 (unspec:SI [(match_operand:SI 1 "int12_operand" "NOP")]
7695 [(set_attr "length" "4")
7696 (set_attr "type" "mset")])
7698 (define_insn "mhdseth"
7699 [(set (match_operand:SI 0 "fpr_operand" "=f")
7700 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7701 (match_operand:SI 2 "int5_operand" "I")]
7705 [(set_attr "length" "4")
7706 (set_attr "type" "mset")])
7708 ;;-----------------------------------------------------------------------------
7710 (define_expand "symGOT2reg"
7711 [(match_operand:SI 0 "" "")
7712 (match_operand:SI 1 "" "")
7713 (match_operand:SI 2 "" "")
7714 (match_operand:SI 3 "" "")]
7720 insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1], operands[2], operands[3]));
7722 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7724 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
7730 (define_expand "symGOT2reg_i"
7731 [(set (match_operand:SI 0 "" "")
7732 (mem:SI (plus:SI (match_operand:SI 2 "" "")
7733 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7734 (match_operand:SI 3 "" "")]
7739 (define_expand "symGOT2reg_hilo"
7741 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7742 (match_dup 4)] UNSPEC_GOT))))
7744 (lo_sum:SI (match_dup 6)
7745 (const:SI (unspec:SI [(match_dup 1)
7746 (match_operand:SI 3 "" "")]
7748 (set (match_operand:SI 0 "" "")
7749 (mem:SI (plus:SI (match_dup 5)
7750 (match_operand:SI 2 "" ""))))
7756 operands[6] = operands[5] = operands[0];
7759 operands[6] = gen_reg_rtx (SImode);
7760 operands[5] = gen_reg_rtx (SImode);
7763 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7764 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7767 (define_expand "symGOTOFF2reg_hilo"
7769 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7770 (match_dup 4)] UNSPEC_GOT))))
7772 (lo_sum:SI (match_dup 6)
7773 (const:SI (unspec:SI [(match_dup 1)
7774 (match_operand:SI 3 "" "")]
7776 (set (match_operand:SI 0 "" "")
7777 (plus:SI (match_dup 5)
7778 (match_operand:SI 2 "" "")))
7784 operands[6] = operands[5] = operands[0];
7787 operands[6] = gen_reg_rtx (SImode);
7788 operands[5] = gen_reg_rtx (SImode);
7791 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7792 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7795 (define_expand "symGOTOFF2reg"
7796 [(match_operand:SI 0 "" "")
7797 (match_operand:SI 1 "" "")
7798 (match_operand:SI 2 "" "")
7799 (match_operand:SI 3 "" "")]
7803 rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], operands[2], operands[3]));
7805 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
7811 (define_expand "symGOTOFF2reg_i"
7812 [(set (match_operand:SI 0 "" "")
7813 (plus:SI (match_operand:SI 2 "" "")
7815 (unspec:SI [(match_operand:SI 1 "" "")
7816 (match_operand:SI 3 "" "")]
7821 (define_expand "symGPREL2reg"
7822 [(match_operand:SI 0 "" "")
7823 (match_operand:SI 1 "" "")
7824 (match_operand:SI 2 "" "")
7825 (match_operand:SI 3 "" "")
7833 operands[4] = operands[0];
7835 operands[4] = gen_reg_rtx (SImode);
7837 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7839 insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
7840 operands[4], operands[3]));
7842 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
7848 (define_expand "symGPREL2reg_hilo"
7849 [(match_operand:SI 0 "" "")
7850 (match_operand:SI 1 "" "")
7851 (match_operand:SI 2 "" "")
7852 (match_operand:SI 3 "" "")
7861 emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2],
7862 GEN_INT (R_FRV_GOT12)));
7866 operands[4] = gen_reg_rtx (SImode);
7868 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7870 insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1],
7871 operands[4], operands[3]));
7873 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],