1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "stor-layout.h"
91 #include "hard-reg-set.h"
94 #include "dominance.h"
97 #include "cfgcleanup.h"
98 #include "basic-block.h"
99 #include "insn-config.h"
100 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
105 #include "emit-rtl.h"
109 #include "insn-attr.h"
111 #include "diagnostic-core.h"
113 #include "insn-codes.h"
115 #include "rtlhooks-def.h"
117 #include "tree-pass.h"
119 #include "valtrack.h"
121 #include "plugin-api.h"
125 #include "rtl-iter.h"
127 /* Number of attempts to combine instructions in this function. */
129 static int combine_attempts
;
131 /* Number of attempts that got as far as substitution in this function. */
133 static int combine_merges
;
135 /* Number of instructions combined with added SETs in this function. */
137 static int combine_extras
;
139 /* Number of instructions combined in this function. */
141 static int combine_successes
;
143 /* Totals over entire compilation. */
145 static int total_attempts
, total_merges
, total_extras
, total_successes
;
147 /* combine_instructions may try to replace the right hand side of the
148 second instruction with the value of an associated REG_EQUAL note
149 before throwing it at try_combine. That is problematic when there
150 is a REG_DEAD note for a register used in the old right hand side
151 and can cause distribute_notes to do wrong things. This is the
152 second instruction if it has been so modified, null otherwise. */
154 static rtx_insn
*i2mod
;
156 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
158 static rtx i2mod_old_rhs
;
160 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
162 static rtx i2mod_new_rhs
;
164 typedef struct reg_stat_struct
{
165 /* Record last point of death of (hard or pseudo) register n. */
166 rtx_insn
*last_death
;
168 /* Record last point of modification of (hard or pseudo) register n. */
171 /* The next group of fields allows the recording of the last value assigned
172 to (hard or pseudo) register n. We use this information to see if an
173 operation being processed is redundant given a prior operation performed
174 on the register. For example, an `and' with a constant is redundant if
175 all the zero bits are already known to be turned off.
177 We use an approach similar to that used by cse, but change it in the
180 (1) We do not want to reinitialize at each label.
181 (2) It is useful, but not critical, to know the actual value assigned
182 to a register. Often just its form is helpful.
184 Therefore, we maintain the following fields:
186 last_set_value the last value assigned
187 last_set_label records the value of label_tick when the
188 register was assigned
189 last_set_table_tick records the value of label_tick when a
190 value using the register is assigned
191 last_set_invalid set to nonzero when it is not valid
192 to use the value of this register in some
195 To understand the usage of these tables, it is important to understand
196 the distinction between the value in last_set_value being valid and
197 the register being validly contained in some other expression in the
200 (The next two parameters are out of date).
202 reg_stat[i].last_set_value is valid if it is nonzero, and either
203 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
205 Register I may validly appear in any expression returned for the value
206 of another register if reg_n_sets[i] is 1. It may also appear in the
207 value for register J if reg_stat[j].last_set_invalid is zero, or
208 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
210 If an expression is found in the table containing a register which may
211 not validly appear in an expression, the register is replaced by
212 something that won't match, (clobber (const_int 0)). */
214 /* Record last value assigned to (hard or pseudo) register n. */
218 /* Record the value of label_tick when an expression involving register n
219 is placed in last_set_value. */
221 int last_set_table_tick
;
223 /* Record the value of label_tick when the value for register n is placed in
228 /* These fields are maintained in parallel with last_set_value and are
229 used to store the mode in which the register was last set, the bits
230 that were known to be zero when it was last set, and the number of
231 sign bits copies it was known to have when it was last set. */
233 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
234 char last_set_sign_bit_copies
;
235 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
237 /* Set nonzero if references to register n in expressions should not be
238 used. last_set_invalid is set nonzero when this register is being
239 assigned to and last_set_table_tick == label_tick. */
241 char last_set_invalid
;
243 /* Some registers that are set more than once and used in more than one
244 basic block are nevertheless always set in similar ways. For example,
245 a QImode register may be loaded from memory in two places on a machine
246 where byte loads zero extend.
248 We record in the following fields if a register has some leading bits
249 that are always equal to the sign bit, and what we know about the
250 nonzero bits of a register, specifically which bits are known to be
253 If an entry is zero, it means that we don't know anything special. */
255 unsigned char sign_bit_copies
;
257 unsigned HOST_WIDE_INT nonzero_bits
;
259 /* Record the value of the label_tick when the last truncation
260 happened. The field truncated_to_mode is only valid if
261 truncation_label == label_tick. */
263 int truncation_label
;
265 /* Record the last truncation seen for this register. If truncation
266 is not a nop to this mode we might be able to save an explicit
267 truncation if we know that value already contains a truncated
270 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
274 static vec
<reg_stat_type
> reg_stat
;
276 /* One plus the highest pseudo for which we track REG_N_SETS.
277 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
278 but during combine_split_insns new pseudos can be created. As we don't have
279 updated DF information in that case, it is hard to initialize the array
280 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
281 so instead of growing the arrays, just assume all newly created pseudos
282 during combine might be set multiple times. */
284 static unsigned int reg_n_sets_max
;
286 /* Record the luid of the last insn that invalidated memory
287 (anything that writes memory, and subroutine calls, but not pushes). */
289 static int mem_last_set
;
291 /* Record the luid of the last CALL_INSN
292 so we can tell whether a potential combination crosses any calls. */
294 static int last_call_luid
;
296 /* When `subst' is called, this is the insn that is being modified
297 (by combining in a previous insn). The PATTERN of this insn
298 is still the old pattern partially modified and it should not be
299 looked at, but this may be used to examine the successors of the insn
300 to judge whether a simplification is valid. */
302 static rtx_insn
*subst_insn
;
304 /* This is the lowest LUID that `subst' is currently dealing with.
305 get_last_value will not return a value if the register was set at or
306 after this LUID. If not for this mechanism, we could get confused if
307 I2 or I1 in try_combine were an insn that used the old value of a register
308 to obtain a new value. In that case, we might erroneously get the
309 new value of the register when we wanted the old one. */
311 static int subst_low_luid
;
313 /* This contains any hard registers that are used in newpat; reg_dead_at_p
314 must consider all these registers to be always live. */
316 static HARD_REG_SET newpat_used_regs
;
318 /* This is an insn to which a LOG_LINKS entry has been added. If this
319 insn is the earlier than I2 or I3, combine should rescan starting at
322 static rtx_insn
*added_links_insn
;
324 /* Basic block in which we are performing combines. */
325 static basic_block this_basic_block
;
326 static bool optimize_this_for_speed_p
;
329 /* Length of the currently allocated uid_insn_cost array. */
331 static int max_uid_known
;
333 /* The following array records the insn_rtx_cost for every insn
334 in the instruction stream. */
336 static int *uid_insn_cost
;
338 /* The following array records the LOG_LINKS for every insn in the
339 instruction stream as struct insn_link pointers. */
344 struct insn_link
*next
;
347 static struct insn_link
**uid_log_links
;
349 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
350 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
352 #define FOR_EACH_LOG_LINK(L, INSN) \
353 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
355 /* Links for LOG_LINKS are allocated from this obstack. */
357 static struct obstack insn_link_obstack
;
359 /* Allocate a link. */
361 static inline struct insn_link
*
362 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
365 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
366 sizeof (struct insn_link
));
373 /* Incremented for each basic block. */
375 static int label_tick
;
377 /* Reset to label_tick for each extended basic block in scanning order. */
379 static int label_tick_ebb_start
;
381 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
382 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
384 static machine_mode nonzero_bits_mode
;
386 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
387 be safely used. It is zero while computing them and after combine has
388 completed. This former test prevents propagating values based on
389 previously set values, which can be incorrect if a variable is modified
392 static int nonzero_sign_valid
;
395 /* Record one modification to rtl structure
396 to be undone by storing old_contents into *where. */
398 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
404 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
405 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
408 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
409 num_undo says how many are currently recorded.
411 other_insn is nonzero if we have modified some other insn in the process
412 of working on subst_insn. It must be verified too. */
418 rtx_insn
*other_insn
;
421 static struct undobuf undobuf
;
423 /* Number of times the pseudo being substituted for
424 was found and replaced. */
426 static int n_occurrences
;
428 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
430 unsigned HOST_WIDE_INT
,
431 unsigned HOST_WIDE_INT
*);
432 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
434 unsigned int, unsigned int *);
435 static void do_SUBST (rtx
*, rtx
);
436 static void do_SUBST_INT (int *, int);
437 static void init_reg_last (void);
438 static void setup_incoming_promotions (rtx_insn
*);
439 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
440 static int cant_combine_insn_p (rtx_insn
*);
441 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
442 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
443 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
444 static int contains_muldiv (rtx
);
445 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
447 static void undo_all (void);
448 static void undo_commit (void);
449 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
450 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
451 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
452 static rtx
simplify_if_then_else (rtx
);
453 static rtx
simplify_set (rtx
);
454 static rtx
simplify_logical (rtx
);
455 static rtx
expand_compound_operation (rtx
);
456 static const_rtx
expand_field_assignment (const_rtx
);
457 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
458 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
459 static rtx
extract_left_shift (rtx
, int);
460 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
461 unsigned HOST_WIDE_INT
*);
462 static rtx
canon_reg_for_combine (rtx
, rtx
);
463 static rtx
force_to_mode (rtx
, machine_mode
,
464 unsigned HOST_WIDE_INT
, int);
465 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
466 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
467 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
468 static rtx
make_field_assignment (rtx
);
469 static rtx
apply_distributive_law (rtx
);
470 static rtx
distribute_and_simplify_rtx (rtx
, int);
471 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
472 unsigned HOST_WIDE_INT
);
473 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
474 unsigned HOST_WIDE_INT
);
475 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
476 HOST_WIDE_INT
, machine_mode
, int *);
477 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
478 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
480 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
481 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
482 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
484 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
485 static void update_table_tick (rtx
);
486 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
487 static void check_promoted_subreg (rtx_insn
*, rtx
);
488 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
489 static void record_dead_and_set_regs (rtx_insn
*);
490 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
491 static rtx
get_last_value (const_rtx
);
492 static int use_crosses_set_p (const_rtx
, int);
493 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
494 static int reg_dead_at_p (rtx
, rtx_insn
*);
495 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
496 static int reg_bitfield_target_p (rtx
, rtx
);
497 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
498 static void distribute_links (struct insn_link
*);
499 static void mark_used_regs_combine (rtx
);
500 static void record_promoted_value (rtx_insn
*, rtx
);
501 static bool unmentioned_reg_p (rtx
, rtx
);
502 static void record_truncated_values (rtx
*, void *);
503 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
504 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
507 /* It is not safe to use ordinary gen_lowpart in combine.
508 See comments in gen_lowpart_for_combine. */
509 #undef RTL_HOOKS_GEN_LOWPART
510 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
512 /* Our implementation of gen_lowpart never emits a new pseudo. */
513 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
514 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
516 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
517 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
519 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
520 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
522 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
523 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
525 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
528 /* Convenience wrapper for the canonicalize_comparison target hook.
529 Target hooks cannot use enum rtx_code. */
531 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
532 bool op0_preserve_value
)
534 int code_int
= (int)*code
;
535 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
536 *code
= (enum rtx_code
)code_int
;
539 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
540 PATTERN can not be split. Otherwise, it returns an insn sequence.
541 This is a wrapper around split_insns which ensures that the
542 reg_stat vector is made larger if the splitter creates a new
546 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
551 ret
= split_insns (pattern
, insn
);
552 nregs
= max_reg_num ();
553 if (nregs
> reg_stat
.length ())
554 reg_stat
.safe_grow_cleared (nregs
);
558 /* This is used by find_single_use to locate an rtx in LOC that
559 contains exactly one use of DEST, which is typically either a REG
560 or CC0. It returns a pointer to the innermost rtx expression
561 containing DEST. Appearances of DEST that are being used to
562 totally replace it are not counted. */
565 find_single_use_1 (rtx dest
, rtx
*loc
)
568 enum rtx_code code
= GET_CODE (x
);
584 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
585 of a REG that occupies all of the REG, the insn uses DEST if
586 it is mentioned in the destination or the source. Otherwise, we
587 need just check the source. */
588 if (GET_CODE (SET_DEST (x
)) != CC0
589 && GET_CODE (SET_DEST (x
)) != PC
590 && !REG_P (SET_DEST (x
))
591 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
592 && REG_P (SUBREG_REG (SET_DEST (x
)))
593 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
594 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
595 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
596 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
599 return find_single_use_1 (dest
, &SET_SRC (x
));
603 return find_single_use_1 (dest
, &XEXP (x
, 0));
609 /* If it wasn't one of the common cases above, check each expression and
610 vector of this code. Look for a unique usage of DEST. */
612 fmt
= GET_RTX_FORMAT (code
);
613 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
617 if (dest
== XEXP (x
, i
)
618 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
619 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
622 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
625 result
= this_result
;
626 else if (this_result
)
627 /* Duplicate usage. */
630 else if (fmt
[i
] == 'E')
634 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
636 if (XVECEXP (x
, i
, j
) == dest
638 && REG_P (XVECEXP (x
, i
, j
))
639 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
642 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
645 result
= this_result
;
646 else if (this_result
)
656 /* See if DEST, produced in INSN, is used only a single time in the
657 sequel. If so, return a pointer to the innermost rtx expression in which
660 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
662 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
663 care about REG_DEAD notes or LOG_LINKS.
665 Otherwise, we find the single use by finding an insn that has a
666 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
667 only referenced once in that insn, we know that it must be the first
668 and last insn referencing DEST. */
671 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
676 struct insn_link
*link
;
680 next
= NEXT_INSN (insn
);
682 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
685 result
= find_single_use_1 (dest
, &PATTERN (next
));
694 bb
= BLOCK_FOR_INSN (insn
);
695 for (next
= NEXT_INSN (insn
);
696 next
&& BLOCK_FOR_INSN (next
) == bb
;
697 next
= NEXT_INSN (next
))
698 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
700 FOR_EACH_LOG_LINK (link
, next
)
701 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
706 result
= find_single_use_1 (dest
, &PATTERN (next
));
716 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
717 insn. The substitution can be undone by undo_all. If INTO is already
718 set to NEWVAL, do not record this change. Because computing NEWVAL might
719 also call SUBST, we have to compute it before we put anything into
723 do_SUBST (rtx
*into
, rtx newval
)
728 if (oldval
== newval
)
731 /* We'd like to catch as many invalid transformations here as
732 possible. Unfortunately, there are way too many mode changes
733 that are perfectly valid, so we'd waste too much effort for
734 little gain doing the checks here. Focus on catching invalid
735 transformations involving integer constants. */
736 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
737 && CONST_INT_P (newval
))
739 /* Sanity check that we're replacing oldval with a CONST_INT
740 that is a valid sign-extension for the original mode. */
741 gcc_assert (INTVAL (newval
)
742 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
744 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
745 CONST_INT is not valid, because after the replacement, the
746 original mode would be gone. Unfortunately, we can't tell
747 when do_SUBST is called to replace the operand thereof, so we
748 perform this test on oldval instead, checking whether an
749 invalid replacement took place before we got here. */
750 gcc_assert (!(GET_CODE (oldval
) == SUBREG
751 && CONST_INT_P (SUBREG_REG (oldval
))));
752 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
753 && CONST_INT_P (XEXP (oldval
, 0))));
757 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
759 buf
= XNEW (struct undo
);
761 buf
->kind
= UNDO_RTX
;
763 buf
->old_contents
.r
= oldval
;
766 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
769 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
771 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
772 for the value of a HOST_WIDE_INT value (including CONST_INT) is
776 do_SUBST_INT (int *into
, int newval
)
781 if (oldval
== newval
)
785 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
787 buf
= XNEW (struct undo
);
789 buf
->kind
= UNDO_INT
;
791 buf
->old_contents
.i
= oldval
;
794 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
797 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
799 /* Similar to SUBST, but just substitute the mode. This is used when
800 changing the mode of a pseudo-register, so that any other
801 references to the entry in the regno_reg_rtx array will change as
805 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
808 machine_mode oldval
= GET_MODE (*into
);
810 if (oldval
== newval
)
814 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
816 buf
= XNEW (struct undo
);
818 buf
->kind
= UNDO_MODE
;
820 buf
->old_contents
.m
= oldval
;
821 adjust_reg_mode (*into
, newval
);
823 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
826 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
829 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
832 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
835 struct insn_link
* oldval
= *into
;
837 if (oldval
== newval
)
841 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
843 buf
= XNEW (struct undo
);
845 buf
->kind
= UNDO_LINKS
;
847 buf
->old_contents
.l
= oldval
;
850 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
853 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
856 /* Subroutine of try_combine. Determine whether the replacement patterns
857 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
858 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
859 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
860 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
861 of all the instructions can be estimated and the replacements are more
862 expensive than the original sequence. */
865 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
866 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
868 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
869 int new_i2_cost
, new_i3_cost
;
870 int old_cost
, new_cost
;
872 /* Lookup the original insn_rtx_costs. */
873 i2_cost
= INSN_COST (i2
);
874 i3_cost
= INSN_COST (i3
);
878 i1_cost
= INSN_COST (i1
);
881 i0_cost
= INSN_COST (i0
);
882 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
883 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
887 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
888 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
894 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
895 i1_cost
= i0_cost
= 0;
898 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
900 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
904 /* Calculate the replacement insn_rtx_costs. */
905 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
908 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
909 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
910 ? new_i2_cost
+ new_i3_cost
: 0;
914 new_cost
= new_i3_cost
;
918 if (undobuf
.other_insn
)
920 int old_other_cost
, new_other_cost
;
922 old_other_cost
= INSN_COST (undobuf
.other_insn
);
923 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
924 if (old_other_cost
> 0 && new_other_cost
> 0)
926 old_cost
+= old_other_cost
;
927 new_cost
+= new_other_cost
;
933 /* Disallow this combination if both new_cost and old_cost are greater than
934 zero, and new_cost is greater than old cost. */
935 int reject
= old_cost
> 0 && new_cost
> old_cost
;
939 fprintf (dump_file
, "%s combination of insns ",
940 reject
? "rejecting" : "allowing");
942 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
943 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
944 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
945 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
947 fprintf (dump_file
, "original costs ");
949 fprintf (dump_file
, "%d + ", i0_cost
);
950 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
951 fprintf (dump_file
, "%d + ", i1_cost
);
952 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
955 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
956 new_i2_cost
, new_i3_cost
, new_cost
);
958 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
964 /* Update the uid_insn_cost array with the replacement costs. */
965 INSN_COST (i2
) = new_i2_cost
;
966 INSN_COST (i3
) = new_i3_cost
;
978 /* Delete any insns that copy a register to itself. */
981 delete_noop_moves (void)
983 rtx_insn
*insn
, *next
;
986 FOR_EACH_BB_FN (bb
, cfun
)
988 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
990 next
= NEXT_INSN (insn
);
991 if (INSN_P (insn
) && noop_move_p (insn
))
994 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
996 delete_insn_and_edges (insn
);
1003 /* Return false if we do not want to (or cannot) combine DEF. */
1005 can_combine_def_p (df_ref def
)
1007 /* Do not consider if it is pre/post modification in MEM. */
1008 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1011 unsigned int regno
= DF_REF_REGNO (def
);
1013 /* Do not combine frame pointer adjustments. */
1014 if ((regno
== FRAME_POINTER_REGNUM
1015 && (!reload_completed
|| frame_pointer_needed
))
1016 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1017 || (regno
== HARD_FRAME_POINTER_REGNUM
1018 && (!reload_completed
|| frame_pointer_needed
))
1020 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1021 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1027 /* Return false if we do not want to (or cannot) combine USE. */
1029 can_combine_use_p (df_ref use
)
1031 /* Do not consider the usage of the stack pointer by function call. */
1032 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1038 /* Fill in log links field for all insns. */
1041 create_log_links (void)
1044 rtx_insn
**next_use
;
1048 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1050 /* Pass through each block from the end, recording the uses of each
1051 register and establishing log links when def is encountered.
1052 Note that we do not clear next_use array in order to save time,
1053 so we have to test whether the use is in the same basic block as def.
1055 There are a few cases below when we do not consider the definition or
1056 usage -- these are taken from original flow.c did. Don't ask me why it is
1057 done this way; I don't know and if it works, I don't want to know. */
1059 FOR_EACH_BB_FN (bb
, cfun
)
1061 FOR_BB_INSNS_REVERSE (bb
, insn
)
1063 if (!NONDEBUG_INSN_P (insn
))
1066 /* Log links are created only once. */
1067 gcc_assert (!LOG_LINKS (insn
));
1069 FOR_EACH_INSN_DEF (def
, insn
)
1071 unsigned int regno
= DF_REF_REGNO (def
);
1074 if (!next_use
[regno
])
1077 if (!can_combine_def_p (def
))
1080 use_insn
= next_use
[regno
];
1081 next_use
[regno
] = NULL
;
1083 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1088 We don't build a LOG_LINK for hard registers contained
1089 in ASM_OPERANDs. If these registers get replaced,
1090 we might wind up changing the semantics of the insn,
1091 even if reload can make what appear to be valid
1092 assignments later. */
1093 if (regno
< FIRST_PSEUDO_REGISTER
1094 && asm_noperands (PATTERN (use_insn
)) >= 0)
1097 /* Don't add duplicate links between instructions. */
1098 struct insn_link
*links
;
1099 FOR_EACH_LOG_LINK (links
, use_insn
)
1100 if (insn
== links
->insn
&& regno
== links
->regno
)
1104 LOG_LINKS (use_insn
)
1105 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1108 FOR_EACH_INSN_USE (use
, insn
)
1109 if (can_combine_use_p (use
))
1110 next_use
[DF_REF_REGNO (use
)] = insn
;
1117 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1118 true if we found a LOG_LINK that proves that A feeds B. This only works
1119 if there are no instructions between A and B which could have a link
1120 depending on A, since in that case we would not record a link for B.
1121 We also check the implicit dependency created by a cc0 setter/user
1125 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1127 struct insn_link
*links
;
1128 FOR_EACH_LOG_LINK (links
, b
)
1129 if (links
->insn
== a
)
1131 if (HAVE_cc0
&& sets_cc0_p (a
))
1136 /* Main entry point for combiner. F is the first insn of the function.
1137 NREGS is the first unused pseudo-reg number.
1139 Return nonzero if the combiner has turned an indirect jump
1140 instruction into a direct jump. */
1142 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1144 rtx_insn
*insn
, *next
;
1148 struct insn_link
*links
, *nextlinks
;
1150 basic_block last_bb
;
1152 int new_direct_jump_p
= 0;
1154 for (first
= f
; first
&& !INSN_P (first
); )
1155 first
= NEXT_INSN (first
);
1159 combine_attempts
= 0;
1162 combine_successes
= 0;
1164 rtl_hooks
= combine_rtl_hooks
;
1166 reg_stat
.safe_grow_cleared (nregs
);
1168 init_recog_no_volatile ();
1170 /* Allocate array for insn info. */
1171 max_uid_known
= get_max_uid ();
1172 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1173 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1174 gcc_obstack_init (&insn_link_obstack
);
1176 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1178 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1179 problems when, for example, we have j <<= 1 in a loop. */
1181 nonzero_sign_valid
= 0;
1182 label_tick
= label_tick_ebb_start
= 1;
1184 /* Scan all SETs and see if we can deduce anything about what
1185 bits are known to be zero for some registers and how many copies
1186 of the sign bit are known to exist for those registers.
1188 Also set any known values so that we can use it while searching
1189 for what bits are known to be set. */
1191 setup_incoming_promotions (first
);
1192 /* Allow the entry block and the first block to fall into the same EBB.
1193 Conceptually the incoming promotions are assigned to the entry block. */
1194 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1196 create_log_links ();
1197 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1199 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1204 if (!single_pred_p (this_basic_block
)
1205 || single_pred (this_basic_block
) != last_bb
)
1206 label_tick_ebb_start
= label_tick
;
1207 last_bb
= this_basic_block
;
1209 FOR_BB_INSNS (this_basic_block
, insn
)
1210 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1216 subst_low_luid
= DF_INSN_LUID (insn
);
1219 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1221 record_dead_and_set_regs (insn
);
1224 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1225 if (REG_NOTE_KIND (links
) == REG_INC
)
1226 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1230 /* Record the current insn_rtx_cost of this instruction. */
1231 if (NONJUMP_INSN_P (insn
))
1232 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1233 optimize_this_for_speed_p
);
1235 fprintf (dump_file
, "insn_cost %d: %d\n",
1236 INSN_UID (insn
), INSN_COST (insn
));
1240 nonzero_sign_valid
= 1;
1242 /* Now scan all the insns in forward order. */
1243 label_tick
= label_tick_ebb_start
= 1;
1245 setup_incoming_promotions (first
);
1246 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1247 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1249 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1251 rtx_insn
*last_combined_insn
= NULL
;
1252 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1257 if (!single_pred_p (this_basic_block
)
1258 || single_pred (this_basic_block
) != last_bb
)
1259 label_tick_ebb_start
= label_tick
;
1260 last_bb
= this_basic_block
;
1262 rtl_profile_for_bb (this_basic_block
);
1263 for (insn
= BB_HEAD (this_basic_block
);
1264 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1265 insn
= next
? next
: NEXT_INSN (insn
))
1268 if (!NONDEBUG_INSN_P (insn
))
1271 while (last_combined_insn
1272 && last_combined_insn
->deleted ())
1273 last_combined_insn
= PREV_INSN (last_combined_insn
);
1274 if (last_combined_insn
== NULL_RTX
1275 || BARRIER_P (last_combined_insn
)
1276 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1277 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1278 last_combined_insn
= insn
;
1280 /* See if we know about function return values before this
1281 insn based upon SUBREG flags. */
1282 check_promoted_subreg (insn
, PATTERN (insn
));
1284 /* See if we can find hardregs and subreg of pseudos in
1285 narrower modes. This could help turning TRUNCATEs
1287 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1289 /* Try this insn with each insn it links back to. */
1291 FOR_EACH_LOG_LINK (links
, insn
)
1292 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1293 NULL
, &new_direct_jump_p
,
1294 last_combined_insn
)) != 0)
1296 statistics_counter_event (cfun
, "two-insn combine", 1);
1300 /* Try each sequence of three linked insns ending with this one. */
1302 if (max_combine
>= 3)
1303 FOR_EACH_LOG_LINK (links
, insn
)
1305 rtx_insn
*link
= links
->insn
;
1307 /* If the linked insn has been replaced by a note, then there
1308 is no point in pursuing this chain any further. */
1312 FOR_EACH_LOG_LINK (nextlinks
, link
)
1313 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1314 NULL
, &new_direct_jump_p
,
1315 last_combined_insn
)) != 0)
1317 statistics_counter_event (cfun
, "three-insn combine", 1);
1323 /* Try to combine a jump insn that uses CC0
1324 with a preceding insn that sets CC0, and maybe with its
1325 logical predecessor as well.
1326 This is how we make decrement-and-branch insns.
1327 We need this special code because data flow connections
1328 via CC0 do not get entered in LOG_LINKS. */
1331 && (prev
= prev_nonnote_insn (insn
)) != 0
1332 && NONJUMP_INSN_P (prev
)
1333 && sets_cc0_p (PATTERN (prev
)))
1335 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1337 last_combined_insn
)) != 0)
1340 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1341 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1342 NULL
, &new_direct_jump_p
,
1343 last_combined_insn
)) != 0)
1347 /* Do the same for an insn that explicitly references CC0. */
1348 if (NONJUMP_INSN_P (insn
)
1349 && (prev
= prev_nonnote_insn (insn
)) != 0
1350 && NONJUMP_INSN_P (prev
)
1351 && sets_cc0_p (PATTERN (prev
))
1352 && GET_CODE (PATTERN (insn
)) == SET
1353 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1355 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1357 last_combined_insn
)) != 0)
1360 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1361 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1362 NULL
, &new_direct_jump_p
,
1363 last_combined_insn
)) != 0)
1367 /* Finally, see if any of the insns that this insn links to
1368 explicitly references CC0. If so, try this insn, that insn,
1369 and its predecessor if it sets CC0. */
1370 FOR_EACH_LOG_LINK (links
, insn
)
1371 if (NONJUMP_INSN_P (links
->insn
)
1372 && GET_CODE (PATTERN (links
->insn
)) == SET
1373 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1374 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1375 && NONJUMP_INSN_P (prev
)
1376 && sets_cc0_p (PATTERN (prev
))
1377 && (next
= try_combine (insn
, links
->insn
,
1378 prev
, NULL
, &new_direct_jump_p
,
1379 last_combined_insn
)) != 0)
1383 /* Try combining an insn with two different insns whose results it
1385 if (max_combine
>= 3)
1386 FOR_EACH_LOG_LINK (links
, insn
)
1387 for (nextlinks
= links
->next
; nextlinks
;
1388 nextlinks
= nextlinks
->next
)
1389 if ((next
= try_combine (insn
, links
->insn
,
1390 nextlinks
->insn
, NULL
,
1392 last_combined_insn
)) != 0)
1395 statistics_counter_event (cfun
, "three-insn combine", 1);
1399 /* Try four-instruction combinations. */
1400 if (max_combine
>= 4)
1401 FOR_EACH_LOG_LINK (links
, insn
)
1403 struct insn_link
*next1
;
1404 rtx_insn
*link
= links
->insn
;
1406 /* If the linked insn has been replaced by a note, then there
1407 is no point in pursuing this chain any further. */
1411 FOR_EACH_LOG_LINK (next1
, link
)
1413 rtx_insn
*link1
= next1
->insn
;
1416 /* I0 -> I1 -> I2 -> I3. */
1417 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1418 if ((next
= try_combine (insn
, link
, link1
,
1421 last_combined_insn
)) != 0)
1423 statistics_counter_event (cfun
, "four-insn combine", 1);
1426 /* I0, I1 -> I2, I2 -> I3. */
1427 for (nextlinks
= next1
->next
; nextlinks
;
1428 nextlinks
= nextlinks
->next
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1439 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1441 rtx_insn
*link1
= next1
->insn
;
1444 /* I0 -> I2; I1, I2 -> I3. */
1445 FOR_EACH_LOG_LINK (nextlinks
, link
)
1446 if ((next
= try_combine (insn
, link
, link1
,
1449 last_combined_insn
)) != 0)
1451 statistics_counter_event (cfun
, "four-insn combine", 1);
1454 /* I0 -> I1; I1, I2 -> I3. */
1455 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1456 if ((next
= try_combine (insn
, link
, link1
,
1459 last_combined_insn
)) != 0)
1461 statistics_counter_event (cfun
, "four-insn combine", 1);
1467 /* Try this insn with each REG_EQUAL note it links back to. */
1468 FOR_EACH_LOG_LINK (links
, insn
)
1471 rtx_insn
*temp
= links
->insn
;
1472 if ((set
= single_set (temp
)) != 0
1473 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1474 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1475 /* Avoid using a register that may already been marked
1476 dead by an earlier instruction. */
1477 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1478 && (GET_MODE (note
) == VOIDmode
1479 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1480 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1482 /* Temporarily replace the set's source with the
1483 contents of the REG_EQUAL note. The insn will
1484 be deleted or recognized by try_combine. */
1485 rtx orig
= SET_SRC (set
);
1486 SET_SRC (set
) = note
;
1488 i2mod_old_rhs
= copy_rtx (orig
);
1489 i2mod_new_rhs
= copy_rtx (note
);
1490 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1492 last_combined_insn
);
1496 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1499 SET_SRC (set
) = orig
;
1504 record_dead_and_set_regs (insn
);
1511 default_rtl_profile ();
1513 new_direct_jump_p
|= purge_all_dead_edges ();
1514 delete_noop_moves ();
1517 obstack_free (&insn_link_obstack
, NULL
);
1518 free (uid_log_links
);
1519 free (uid_insn_cost
);
1520 reg_stat
.release ();
1523 struct undo
*undo
, *next
;
1524 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1532 total_attempts
+= combine_attempts
;
1533 total_merges
+= combine_merges
;
1534 total_extras
+= combine_extras
;
1535 total_successes
+= combine_successes
;
1537 nonzero_sign_valid
= 0;
1538 rtl_hooks
= general_rtl_hooks
;
1540 /* Make recognizer allow volatile MEMs again. */
1543 return new_direct_jump_p
;
1546 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1549 init_reg_last (void)
1554 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1555 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1558 /* Set up any promoted values for incoming argument registers. */
1561 setup_incoming_promotions (rtx_insn
*first
)
1564 bool strictly_local
= false;
1566 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1567 arg
= DECL_CHAIN (arg
))
1569 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1571 machine_mode mode1
, mode2
, mode3
, mode4
;
1573 /* Only continue if the incoming argument is in a register. */
1577 /* Determine, if possible, whether all call sites of the current
1578 function lie within the current compilation unit. (This does
1579 take into account the exporting of a function via taking its
1580 address, and so forth.) */
1581 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1583 /* The mode and signedness of the argument before any promotions happen
1584 (equal to the mode of the pseudo holding it at that stage). */
1585 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1586 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1588 /* The mode and signedness of the argument after any source language and
1589 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1590 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1591 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1593 /* The mode and signedness of the argument as it is actually passed,
1594 see assign_parm_setup_reg in function.c. */
1595 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1596 TREE_TYPE (cfun
->decl
), 0);
1598 /* The mode of the register in which the argument is being passed. */
1599 mode4
= GET_MODE (reg
);
1601 /* Eliminate sign extensions in the callee when:
1602 (a) A mode promotion has occurred; */
1605 /* (b) The mode of the register is the same as the mode of
1606 the argument as it is passed; */
1609 /* (c) There's no language level extension; */
1612 /* (c.1) All callers are from the current compilation unit. If that's
1613 the case we don't have to rely on an ABI, we only have to know
1614 what we're generating right now, and we know that we will do the
1615 mode1 to mode2 promotion with the given sign. */
1616 else if (!strictly_local
)
1618 /* (c.2) The combination of the two promotions is useful. This is
1619 true when the signs match, or if the first promotion is unsigned.
1620 In the later case, (sign_extend (zero_extend x)) is the same as
1621 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1627 /* Record that the value was promoted from mode1 to mode3,
1628 so that any sign extension at the head of the current
1629 function may be eliminated. */
1630 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1631 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1632 record_value_for_reg (reg
, first
, x
);
1636 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1637 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1638 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1639 because some machines (maybe most) will actually do the sign-extension and
1640 this is the conservative approach.
1642 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1646 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1648 if (GET_MODE_PRECISION (mode
) < prec
1649 && CONST_INT_P (src
)
1651 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1652 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1658 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1662 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1665 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1666 unsigned HOST_WIDE_INT bits
= 0;
1667 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1668 unsigned int num
= 0;
1671 reg_equal
= XEXP (reg_equal_note
, 0);
1673 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1674 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1676 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1679 /* Don't call nonzero_bits if it cannot change anything. */
1680 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1682 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1683 if (reg_equal
&& bits
)
1684 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1685 rsp
->nonzero_bits
|= bits
;
1688 /* Don't call num_sign_bit_copies if it cannot change anything. */
1689 if (rsp
->sign_bit_copies
!= 1)
1691 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1692 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1694 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1695 if (num
== 0 || numeq
> num
)
1698 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1699 rsp
->sign_bit_copies
= num
;
1703 /* Called via note_stores. If X is a pseudo that is narrower than
1704 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1706 If we are setting only a portion of X and we can't figure out what
1707 portion, assume all bits will be used since we don't know what will
1710 Similarly, set how many bits of X are known to be copies of the sign bit
1711 at all locations in the function. This is the smallest number implied
1715 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1717 rtx_insn
*insn
= (rtx_insn
*) data
;
1720 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1721 /* If this register is undefined at the start of the file, we can't
1722 say what its contents were. */
1723 && ! REGNO_REG_SET_P
1724 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1725 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1727 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1729 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1731 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1732 rsp
->sign_bit_copies
= 1;
1736 /* If this register is being initialized using itself, and the
1737 register is uninitialized in this basic block, and there are
1738 no LOG_LINKS which set the register, then part of the
1739 register is uninitialized. In that case we can't assume
1740 anything about the number of nonzero bits.
1742 ??? We could do better if we checked this in
1743 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1744 could avoid making assumptions about the insn which initially
1745 sets the register, while still using the information in other
1746 insns. We would have to be careful to check every insn
1747 involved in the combination. */
1750 && reg_referenced_p (x
, PATTERN (insn
))
1751 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1754 struct insn_link
*link
;
1756 FOR_EACH_LOG_LINK (link
, insn
)
1757 if (dead_or_set_p (link
->insn
, x
))
1761 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1762 rsp
->sign_bit_copies
= 1;
1767 /* If this is a complex assignment, see if we can convert it into a
1768 simple assignment. */
1769 set
= expand_field_assignment (set
);
1771 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1772 set what we know about X. */
1774 if (SET_DEST (set
) == x
1775 || (paradoxical_subreg_p (SET_DEST (set
))
1776 && SUBREG_REG (SET_DEST (set
)) == x
))
1777 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1780 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1781 rsp
->sign_bit_copies
= 1;
1786 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1787 optionally insns that were previously combined into I3 or that will be
1788 combined into the merger of INSN and I3. The order is PRED, PRED2,
1789 INSN, SUCC, SUCC2, I3.
1791 Return 0 if the combination is not allowed for any reason.
1793 If the combination is allowed, *PDEST will be set to the single
1794 destination of INSN and *PSRC to the single source, and this function
1798 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1799 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1800 rtx
*pdest
, rtx
*psrc
)
1809 bool all_adjacent
= true;
1810 int (*is_volatile_p
) (const_rtx
);
1816 if (next_active_insn (succ2
) != i3
)
1817 all_adjacent
= false;
1818 if (next_active_insn (succ
) != succ2
)
1819 all_adjacent
= false;
1821 else if (next_active_insn (succ
) != i3
)
1822 all_adjacent
= false;
1823 if (next_active_insn (insn
) != succ
)
1824 all_adjacent
= false;
1826 else if (next_active_insn (insn
) != i3
)
1827 all_adjacent
= false;
1829 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1830 or a PARALLEL consisting of such a SET and CLOBBERs.
1832 If INSN has CLOBBER parallel parts, ignore them for our processing.
1833 By definition, these happen during the execution of the insn. When it
1834 is merged with another insn, all bets are off. If they are, in fact,
1835 needed and aren't also supplied in I3, they may be added by
1836 recog_for_combine. Otherwise, it won't match.
1838 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1841 Get the source and destination of INSN. If more than one, can't
1844 if (GET_CODE (PATTERN (insn
)) == SET
)
1845 set
= PATTERN (insn
);
1846 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1847 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1849 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1851 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1853 switch (GET_CODE (elt
))
1855 /* This is important to combine floating point insns
1856 for the SH4 port. */
1858 /* Combining an isolated USE doesn't make sense.
1859 We depend here on combinable_i3pat to reject them. */
1860 /* The code below this loop only verifies that the inputs of
1861 the SET in INSN do not change. We call reg_set_between_p
1862 to verify that the REG in the USE does not change between
1864 If the USE in INSN was for a pseudo register, the matching
1865 insn pattern will likely match any register; combining this
1866 with any other USE would only be safe if we knew that the
1867 used registers have identical values, or if there was
1868 something to tell them apart, e.g. different modes. For
1869 now, we forgo such complicated tests and simply disallow
1870 combining of USES of pseudo registers with any other USE. */
1871 if (REG_P (XEXP (elt
, 0))
1872 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1874 rtx i3pat
= PATTERN (i3
);
1875 int i
= XVECLEN (i3pat
, 0) - 1;
1876 unsigned int regno
= REGNO (XEXP (elt
, 0));
1880 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1882 if (GET_CODE (i3elt
) == USE
1883 && REG_P (XEXP (i3elt
, 0))
1884 && (REGNO (XEXP (i3elt
, 0)) == regno
1885 ? reg_set_between_p (XEXP (elt
, 0),
1886 PREV_INSN (insn
), i3
)
1887 : regno
>= FIRST_PSEUDO_REGISTER
))
1894 /* We can ignore CLOBBERs. */
1899 /* Ignore SETs whose result isn't used but not those that
1900 have side-effects. */
1901 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1902 && insn_nothrow_p (insn
)
1903 && !side_effects_p (elt
))
1906 /* If we have already found a SET, this is a second one and
1907 so we cannot combine with this insn. */
1915 /* Anything else means we can't combine. */
1921 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1922 so don't do anything with it. */
1923 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1932 /* The simplification in expand_field_assignment may call back to
1933 get_last_value, so set safe guard here. */
1934 subst_low_luid
= DF_INSN_LUID (insn
);
1936 set
= expand_field_assignment (set
);
1937 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1939 /* Do not eliminate user-specified register if it is in an
1940 asm input because we may break the register asm usage defined
1941 in GCC manual if allow to do so.
1942 Be aware that this may cover more cases than we expect but this
1943 should be harmless. */
1944 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1945 && extract_asm_operands (PATTERN (i3
)))
1948 /* Don't eliminate a store in the stack pointer. */
1949 if (dest
== stack_pointer_rtx
1950 /* Don't combine with an insn that sets a register to itself if it has
1951 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1952 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1953 /* Can't merge an ASM_OPERANDS. */
1954 || GET_CODE (src
) == ASM_OPERANDS
1955 /* Can't merge a function call. */
1956 || GET_CODE (src
) == CALL
1957 /* Don't eliminate a function call argument. */
1959 && (find_reg_fusage (i3
, USE
, dest
)
1961 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1962 && global_regs
[REGNO (dest
)])))
1963 /* Don't substitute into an incremented register. */
1964 || FIND_REG_INC_NOTE (i3
, dest
)
1965 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1966 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1967 /* Don't substitute into a non-local goto, this confuses CFG. */
1968 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1969 /* Make sure that DEST is not used after SUCC but before I3. */
1972 && (reg_used_between_p (dest
, succ2
, i3
)
1973 || reg_used_between_p (dest
, succ
, succ2
)))
1974 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1975 /* Make sure that the value that is to be substituted for the register
1976 does not use any registers whose values alter in between. However,
1977 If the insns are adjacent, a use can't cross a set even though we
1978 think it might (this can happen for a sequence of insns each setting
1979 the same destination; last_set of that register might point to
1980 a NOTE). If INSN has a REG_EQUIV note, the register is always
1981 equivalent to the memory so the substitution is valid even if there
1982 are intervening stores. Also, don't move a volatile asm or
1983 UNSPEC_VOLATILE across any other insns. */
1986 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1987 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1988 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1989 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1990 /* Don't combine across a CALL_INSN, because that would possibly
1991 change whether the life span of some REGs crosses calls or not,
1992 and it is a pain to update that information.
1993 Exception: if source is a constant, moving it later can't hurt.
1994 Accept that as a special case. */
1995 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1998 /* DEST must either be a REG or CC0. */
2001 /* If register alignment is being enforced for multi-word items in all
2002 cases except for parameters, it is possible to have a register copy
2003 insn referencing a hard register that is not allowed to contain the
2004 mode being copied and which would not be valid as an operand of most
2005 insns. Eliminate this problem by not combining with such an insn.
2007 Also, on some machines we don't want to extend the life of a hard
2011 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2012 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2013 /* Don't extend the life of a hard register unless it is
2014 user variable (if we have few registers) or it can't
2015 fit into the desired register (meaning something special
2017 Also avoid substituting a return register into I3, because
2018 reload can't handle a conflict with constraints of other
2020 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2021 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2024 else if (GET_CODE (dest
) != CC0
)
2028 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2029 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2030 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2032 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2034 /* If the clobber represents an earlyclobber operand, we must not
2035 substitute an expression containing the clobbered register.
2036 As we do not analyze the constraint strings here, we have to
2037 make the conservative assumption. However, if the register is
2038 a fixed hard reg, the clobber cannot represent any operand;
2039 we leave it up to the machine description to either accept or
2040 reject use-and-clobber patterns. */
2042 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2043 || !fixed_regs
[REGNO (reg
)])
2044 if (reg_overlap_mentioned_p (reg
, src
))
2048 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2049 or not), reject, unless nothing volatile comes between it and I3 */
2051 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2053 /* Make sure neither succ nor succ2 contains a volatile reference. */
2054 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2056 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2058 /* We'll check insns between INSN and I3 below. */
2061 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2062 to be an explicit register variable, and was chosen for a reason. */
2064 if (GET_CODE (src
) == ASM_OPERANDS
2065 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2068 /* If INSN contains volatile references (specifically volatile MEMs),
2069 we cannot combine across any other volatile references.
2070 Even if INSN doesn't contain volatile references, any intervening
2071 volatile insn might affect machine state. */
2073 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2077 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2078 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2081 /* If INSN contains an autoincrement or autodecrement, make sure that
2082 register is not used between there and I3, and not already used in
2083 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2084 Also insist that I3 not be a jump; if it were one
2085 and the incremented register were spilled, we would lose. */
2088 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2089 if (REG_NOTE_KIND (link
) == REG_INC
2091 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2092 || (pred
!= NULL_RTX
2093 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2094 || (pred2
!= NULL_RTX
2095 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2096 || (succ
!= NULL_RTX
2097 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2098 || (succ2
!= NULL_RTX
2099 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2100 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2104 /* Don't combine an insn that follows a CC0-setting insn.
2105 An insn that uses CC0 must not be separated from the one that sets it.
2106 We do, however, allow I2 to follow a CC0-setting insn if that insn
2107 is passed as I1; in that case it will be deleted also.
2108 We also allow combining in this case if all the insns are adjacent
2109 because that would leave the two CC0 insns adjacent as well.
2110 It would be more logical to test whether CC0 occurs inside I1 or I2,
2111 but that would be much slower, and this ought to be equivalent. */
2115 p
= prev_nonnote_insn (insn
);
2116 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2121 /* If we get here, we have passed all the tests and the combination is
2130 /* LOC is the location within I3 that contains its pattern or the component
2131 of a PARALLEL of the pattern. We validate that it is valid for combining.
2133 One problem is if I3 modifies its output, as opposed to replacing it
2134 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2135 doing so would produce an insn that is not equivalent to the original insns.
2139 (set (reg:DI 101) (reg:DI 100))
2140 (set (subreg:SI (reg:DI 101) 0) <foo>)
2142 This is NOT equivalent to:
2144 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2145 (set (reg:DI 101) (reg:DI 100))])
2147 Not only does this modify 100 (in which case it might still be valid
2148 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2150 We can also run into a problem if I2 sets a register that I1
2151 uses and I1 gets directly substituted into I3 (not via I2). In that
2152 case, we would be getting the wrong value of I2DEST into I3, so we
2153 must reject the combination. This case occurs when I2 and I1 both
2154 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2155 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2156 of a SET must prevent combination from occurring. The same situation
2157 can occur for I0, in which case I0_NOT_IN_SRC is set.
2159 Before doing the above check, we first try to expand a field assignment
2160 into a set of logical operations.
2162 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2163 we place a register that is both set and used within I3. If more than one
2164 such register is detected, we fail.
2166 Return 1 if the combination is valid, zero otherwise. */
2169 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2170 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2174 if (GET_CODE (x
) == SET
)
2177 rtx dest
= SET_DEST (set
);
2178 rtx src
= SET_SRC (set
);
2179 rtx inner_dest
= dest
;
2182 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2183 || GET_CODE (inner_dest
) == SUBREG
2184 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2185 inner_dest
= XEXP (inner_dest
, 0);
2187 /* Check for the case where I3 modifies its output, as discussed
2188 above. We don't want to prevent pseudos from being combined
2189 into the address of a MEM, so only prevent the combination if
2190 i1 or i2 set the same MEM. */
2191 if ((inner_dest
!= dest
&&
2192 (!MEM_P (inner_dest
)
2193 || rtx_equal_p (i2dest
, inner_dest
)
2194 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2195 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2196 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2197 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2198 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2200 /* This is the same test done in can_combine_p except we can't test
2201 all_adjacent; we don't have to, since this instruction will stay
2202 in place, thus we are not considering increasing the lifetime of
2205 Also, if this insn sets a function argument, combining it with
2206 something that might need a spill could clobber a previous
2207 function argument; the all_adjacent test in can_combine_p also
2208 checks this; here, we do a more specific test for this case. */
2210 || (REG_P (inner_dest
)
2211 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2212 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2213 GET_MODE (inner_dest
))))
2214 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2215 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2218 /* If DEST is used in I3, it is being killed in this insn, so
2219 record that for later. We have to consider paradoxical
2220 subregs here, since they kill the whole register, but we
2221 ignore partial subregs, STRICT_LOW_PART, etc.
2222 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2223 STACK_POINTER_REGNUM, since these are always considered to be
2224 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2226 if (GET_CODE (subdest
) == SUBREG
2227 && (GET_MODE_SIZE (GET_MODE (subdest
))
2228 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2229 subdest
= SUBREG_REG (subdest
);
2232 && reg_referenced_p (subdest
, PATTERN (i3
))
2233 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2234 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2235 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2237 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2238 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2239 || ! fixed_regs
[REGNO (subdest
)]))
2240 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2242 if (*pi3dest_killed
)
2245 *pi3dest_killed
= subdest
;
2249 else if (GET_CODE (x
) == PARALLEL
)
2253 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2254 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2255 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2262 /* Return 1 if X is an arithmetic expression that contains a multiplication
2263 and division. We don't count multiplications by powers of two here. */
2266 contains_muldiv (rtx x
)
2268 switch (GET_CODE (x
))
2270 case MOD
: case DIV
: case UMOD
: case UDIV
:
2274 return ! (CONST_INT_P (XEXP (x
, 1))
2275 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2278 return contains_muldiv (XEXP (x
, 0))
2279 || contains_muldiv (XEXP (x
, 1));
2282 return contains_muldiv (XEXP (x
, 0));
2288 /* Determine whether INSN can be used in a combination. Return nonzero if
2289 not. This is used in try_combine to detect early some cases where we
2290 can't perform combinations. */
2293 cant_combine_insn_p (rtx_insn
*insn
)
2298 /* If this isn't really an insn, we can't do anything.
2299 This can occur when flow deletes an insn that it has merged into an
2300 auto-increment address. */
2301 if (! INSN_P (insn
))
2304 /* Never combine loads and stores involving hard regs that are likely
2305 to be spilled. The register allocator can usually handle such
2306 reg-reg moves by tying. If we allow the combiner to make
2307 substitutions of likely-spilled regs, reload might die.
2308 As an exception, we allow combinations involving fixed regs; these are
2309 not available to the register allocator so there's no risk involved. */
2311 set
= single_set (insn
);
2314 src
= SET_SRC (set
);
2315 dest
= SET_DEST (set
);
2316 if (GET_CODE (src
) == SUBREG
)
2317 src
= SUBREG_REG (src
);
2318 if (GET_CODE (dest
) == SUBREG
)
2319 dest
= SUBREG_REG (dest
);
2320 if (REG_P (src
) && REG_P (dest
)
2321 && ((HARD_REGISTER_P (src
)
2322 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2323 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2324 || (HARD_REGISTER_P (dest
)
2325 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2326 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2332 struct likely_spilled_retval_info
2334 unsigned regno
, nregs
;
2338 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2339 hard registers that are known to be written to / clobbered in full. */
2341 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2343 struct likely_spilled_retval_info
*const info
=
2344 (struct likely_spilled_retval_info
*) data
;
2345 unsigned regno
, nregs
;
2348 if (!REG_P (XEXP (set
, 0)))
2351 if (regno
>= info
->regno
+ info
->nregs
)
2353 nregs
= REG_NREGS (x
);
2354 if (regno
+ nregs
<= info
->regno
)
2356 new_mask
= (2U << (nregs
- 1)) - 1;
2357 if (regno
< info
->regno
)
2358 new_mask
>>= info
->regno
- regno
;
2360 new_mask
<<= regno
- info
->regno
;
2361 info
->mask
&= ~new_mask
;
2364 /* Return nonzero iff part of the return value is live during INSN, and
2365 it is likely spilled. This can happen when more than one insn is needed
2366 to copy the return value, e.g. when we consider to combine into the
2367 second copy insn for a complex value. */
2370 likely_spilled_retval_p (rtx_insn
*insn
)
2372 rtx_insn
*use
= BB_END (this_basic_block
);
2375 unsigned regno
, nregs
;
2376 /* We assume here that no machine mode needs more than
2377 32 hard registers when the value overlaps with a register
2378 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2380 struct likely_spilled_retval_info info
;
2382 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2384 reg
= XEXP (PATTERN (use
), 0);
2385 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2387 regno
= REGNO (reg
);
2388 nregs
= REG_NREGS (reg
);
2391 mask
= (2U << (nregs
- 1)) - 1;
2393 /* Disregard parts of the return value that are set later. */
2397 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2399 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2402 /* Check if any of the (probably) live return value registers is
2407 if ((mask
& 1 << nregs
)
2408 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2414 /* Adjust INSN after we made a change to its destination.
2416 Changing the destination can invalidate notes that say something about
2417 the results of the insn and a LOG_LINK pointing to the insn. */
2420 adjust_for_new_dest (rtx_insn
*insn
)
2422 /* For notes, be conservative and simply remove them. */
2423 remove_reg_equal_equiv_notes (insn
);
2425 /* The new insn will have a destination that was previously the destination
2426 of an insn just above it. Call distribute_links to make a LOG_LINK from
2427 the next use of that destination. */
2429 rtx set
= single_set (insn
);
2432 rtx reg
= SET_DEST (set
);
2434 while (GET_CODE (reg
) == ZERO_EXTRACT
2435 || GET_CODE (reg
) == STRICT_LOW_PART
2436 || GET_CODE (reg
) == SUBREG
)
2437 reg
= XEXP (reg
, 0);
2438 gcc_assert (REG_P (reg
));
2440 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2442 df_insn_rescan (insn
);
2445 /* Return TRUE if combine can reuse reg X in mode MODE.
2446 ADDED_SETS is nonzero if the original set is still required. */
2448 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2456 /* Allow hard registers if the new mode is legal, and occupies no more
2457 registers than the old mode. */
2458 if (regno
< FIRST_PSEUDO_REGISTER
)
2459 return (HARD_REGNO_MODE_OK (regno
, mode
)
2460 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2462 /* Or a pseudo that is only used once. */
2463 return (regno
< reg_n_sets_max
2464 && REG_N_SETS (regno
) == 1
2466 && !REG_USERVAR_P (x
));
2470 /* Check whether X, the destination of a set, refers to part of
2471 the register specified by REG. */
2474 reg_subword_p (rtx x
, rtx reg
)
2476 /* Check that reg is an integer mode register. */
2477 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2480 if (GET_CODE (x
) == STRICT_LOW_PART
2481 || GET_CODE (x
) == ZERO_EXTRACT
)
2484 return GET_CODE (x
) == SUBREG
2485 && SUBREG_REG (x
) == reg
2486 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2489 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2490 Note that the INSN should be deleted *after* removing dead edges, so
2491 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2492 but not for a (set (pc) (label_ref FOO)). */
2495 update_cfg_for_uncondjump (rtx_insn
*insn
)
2497 basic_block bb
= BLOCK_FOR_INSN (insn
);
2498 gcc_assert (BB_END (bb
) == insn
);
2500 purge_dead_edges (bb
);
2503 if (EDGE_COUNT (bb
->succs
) == 1)
2507 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2509 /* Remove barriers from the footer if there are any. */
2510 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2511 if (BARRIER_P (insn
))
2513 if (PREV_INSN (insn
))
2514 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2516 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2517 if (NEXT_INSN (insn
))
2518 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2520 else if (LABEL_P (insn
))
2525 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2526 by an arbitrary number of CLOBBERs. */
2528 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2530 if (GET_CODE (pat
) != PARALLEL
)
2533 int len
= XVECLEN (pat
, 0);
2538 for (i
= 0; i
< n
; i
++)
2539 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2540 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2542 for ( ; i
< len
; i
++)
2543 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2550 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2551 CLOBBERs), can be split into individual SETs in that order, without
2552 changing semantics. */
2554 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2556 if (!insn_nothrow_p (insn
))
2559 rtx pat
= PATTERN (insn
);
2562 for (i
= 0; i
< n
; i
++)
2564 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2567 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2569 for (j
= i
+ 1; j
< n
; j
++)
2570 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2578 /* Try to combine the insns I0, I1 and I2 into I3.
2579 Here I0, I1 and I2 appear earlier than I3.
2580 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2583 If we are combining more than two insns and the resulting insn is not
2584 recognized, try splitting it into two insns. If that happens, I2 and I3
2585 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2586 Otherwise, I0, I1 and I2 are pseudo-deleted.
2588 Return 0 if the combination does not work. Then nothing is changed.
2589 If we did the combination, return the insn at which combine should
2592 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2593 new direct jump instruction.
2595 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2596 been I3 passed to an earlier try_combine within the same basic
2600 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2601 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2603 /* New patterns for I3 and I2, respectively. */
2604 rtx newpat
, newi2pat
= 0;
2605 rtvec newpat_vec_with_clobbers
= 0;
2606 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2607 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2609 int added_sets_0
, added_sets_1
, added_sets_2
;
2610 /* Total number of SETs to put into I3. */
2612 /* Nonzero if I2's or I1's body now appears in I3. */
2613 int i2_is_used
= 0, i1_is_used
= 0;
2614 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2615 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2616 /* Contains I3 if the destination of I3 is used in its source, which means
2617 that the old life of I3 is being killed. If that usage is placed into
2618 I2 and not in I3, a REG_DEAD note must be made. */
2619 rtx i3dest_killed
= 0;
2620 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2621 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2622 /* Copy of SET_SRC of I1 and I0, if needed. */
2623 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2624 /* Set if I2DEST was reused as a scratch register. */
2625 bool i2scratch
= false;
2626 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2627 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2628 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2629 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2630 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2631 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2632 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2633 /* Notes that must be added to REG_NOTES in I3 and I2. */
2634 rtx new_i3_notes
, new_i2_notes
;
2635 /* Notes that we substituted I3 into I2 instead of the normal case. */
2636 int i3_subst_into_i2
= 0;
2637 /* Notes that I1, I2 or I3 is a MULT operation. */
2640 int changed_i3_dest
= 0;
2643 rtx_insn
*temp_insn
;
2645 struct insn_link
*link
;
2647 rtx new_other_notes
;
2650 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2652 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2655 /* Only try four-insn combinations when there's high likelihood of
2656 success. Look for simple insns, such as loads of constants or
2657 binary operations involving a constant. */
2665 if (!flag_expensive_optimizations
)
2668 for (i
= 0; i
< 4; i
++)
2670 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2671 rtx set
= single_set (insn
);
2675 src
= SET_SRC (set
);
2676 if (CONSTANT_P (src
))
2681 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2683 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2684 || GET_CODE (src
) == LSHIFTRT
)
2688 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2689 are likely manipulating its value. Ideally we'll be able to combine
2690 all four insns into a bitfield insertion of some kind.
2692 Note the source in I0 might be inside a sign/zero extension and the
2693 memory modes in I0 and I3 might be different. So extract the address
2694 from the destination of I3 and search for it in the source of I0.
2696 In the event that there's a match but the source/dest do not actually
2697 refer to the same memory, the worst that happens is we try some
2698 combinations that we wouldn't have otherwise. */
2699 if ((set0
= single_set (i0
))
2700 /* Ensure the source of SET0 is a MEM, possibly buried inside
2702 && (GET_CODE (SET_SRC (set0
)) == MEM
2703 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2704 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2705 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2706 && (set3
= single_set (i3
))
2707 /* Ensure the destination of SET3 is a MEM. */
2708 && GET_CODE (SET_DEST (set3
)) == MEM
2709 /* Would it be better to extract the base address for the MEM
2710 in SET3 and look for that? I don't have cases where it matters
2711 but I could envision such cases. */
2712 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2715 if (ngood
< 2 && nshift
< 2)
2719 /* Exit early if one of the insns involved can't be used for
2722 || (i1
&& CALL_P (i1
))
2723 || (i0
&& CALL_P (i0
))
2724 || cant_combine_insn_p (i3
)
2725 || cant_combine_insn_p (i2
)
2726 || (i1
&& cant_combine_insn_p (i1
))
2727 || (i0
&& cant_combine_insn_p (i0
))
2728 || likely_spilled_retval_p (i3
))
2732 undobuf
.other_insn
= 0;
2734 /* Reset the hard register usage information. */
2735 CLEAR_HARD_REG_SET (newpat_used_regs
);
2737 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2740 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2741 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2743 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2744 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2746 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2747 INSN_UID (i2
), INSN_UID (i3
));
2750 /* If multiple insns feed into one of I2 or I3, they can be in any
2751 order. To simplify the code below, reorder them in sequence. */
2752 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2753 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2754 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2755 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2756 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2757 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2759 added_links_insn
= 0;
2761 /* First check for one important special case that the code below will
2762 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2763 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2764 we may be able to replace that destination with the destination of I3.
2765 This occurs in the common code where we compute both a quotient and
2766 remainder into a structure, in which case we want to do the computation
2767 directly into the structure to avoid register-register copies.
2769 Note that this case handles both multiple sets in I2 and also cases
2770 where I2 has a number of CLOBBERs inside the PARALLEL.
2772 We make very conservative checks below and only try to handle the
2773 most common cases of this. For example, we only handle the case
2774 where I2 and I3 are adjacent to avoid making difficult register
2777 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2778 && REG_P (SET_SRC (PATTERN (i3
)))
2779 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2780 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2781 && GET_CODE (PATTERN (i2
)) == PARALLEL
2782 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2783 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2784 below would need to check what is inside (and reg_overlap_mentioned_p
2785 doesn't support those codes anyway). Don't allow those destinations;
2786 the resulting insn isn't likely to be recognized anyway. */
2787 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2788 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2789 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2790 SET_DEST (PATTERN (i3
)))
2791 && next_active_insn (i2
) == i3
)
2793 rtx p2
= PATTERN (i2
);
2795 /* Make sure that the destination of I3,
2796 which we are going to substitute into one output of I2,
2797 is not used within another output of I2. We must avoid making this:
2798 (parallel [(set (mem (reg 69)) ...)
2799 (set (reg 69) ...)])
2800 which is not well-defined as to order of actions.
2801 (Besides, reload can't handle output reloads for this.)
2803 The problem can also happen if the dest of I3 is a memory ref,
2804 if another dest in I2 is an indirect memory ref. */
2805 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2806 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2807 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2808 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2809 SET_DEST (XVECEXP (p2
, 0, i
))))
2812 /* Make sure this PARALLEL is not an asm. We do not allow combining
2813 that usually (see can_combine_p), so do not here either. */
2814 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2815 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2816 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2819 if (i
== XVECLEN (p2
, 0))
2820 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2821 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2822 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2827 subst_low_luid
= DF_INSN_LUID (i2
);
2829 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2830 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2831 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2832 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2834 /* Replace the dest in I2 with our dest and make the resulting
2835 insn the new pattern for I3. Then skip to where we validate
2836 the pattern. Everything was set up above. */
2837 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2839 i3_subst_into_i2
= 1;
2840 goto validate_replacement
;
2844 /* If I2 is setting a pseudo to a constant and I3 is setting some
2845 sub-part of it to another constant, merge them by making a new
2848 && (temp_expr
= single_set (i2
)) != 0
2849 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2850 && GET_CODE (PATTERN (i3
)) == SET
2851 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2852 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2854 rtx dest
= SET_DEST (PATTERN (i3
));
2858 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2860 if (CONST_INT_P (XEXP (dest
, 1))
2861 && CONST_INT_P (XEXP (dest
, 2)))
2863 width
= INTVAL (XEXP (dest
, 1));
2864 offset
= INTVAL (XEXP (dest
, 2));
2865 dest
= XEXP (dest
, 0);
2866 if (BITS_BIG_ENDIAN
)
2867 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2872 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2873 dest
= XEXP (dest
, 0);
2874 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2880 /* If this is the low part, we're done. */
2881 if (subreg_lowpart_p (dest
))
2883 /* Handle the case where inner is twice the size of outer. */
2884 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2885 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2886 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2887 /* Otherwise give up for now. */
2894 rtx inner
= SET_SRC (PATTERN (i3
));
2895 rtx outer
= SET_SRC (temp_expr
);
2898 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2899 std::make_pair (inner
, GET_MODE (dest
)),
2904 subst_low_luid
= DF_INSN_LUID (i2
);
2905 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2906 i2dest
= SET_DEST (temp_expr
);
2907 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2909 /* Replace the source in I2 with the new constant and make the
2910 resulting insn the new pattern for I3. Then skip to where we
2911 validate the pattern. Everything was set up above. */
2912 SUBST (SET_SRC (temp_expr
),
2913 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2915 newpat
= PATTERN (i2
);
2917 /* The dest of I3 has been replaced with the dest of I2. */
2918 changed_i3_dest
= 1;
2919 goto validate_replacement
;
2924 /* If we have no I1 and I2 looks like:
2925 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2927 make up a dummy I1 that is
2930 (set (reg:CC X) (compare:CC Y (const_int 0)))
2932 (We can ignore any trailing CLOBBERs.)
2934 This undoes a previous combination and allows us to match a branch-and-
2938 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2939 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2941 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2942 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2943 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2944 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2945 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2946 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2948 /* We make I1 with the same INSN_UID as I2. This gives it
2949 the same DF_INSN_LUID for value tracking. Our fake I1 will
2950 never appear in the insn stream so giving it the same INSN_UID
2951 as I2 will not cause a problem. */
2953 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2954 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2956 INSN_UID (i1
) = INSN_UID (i2
);
2958 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2959 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2960 SET_DEST (PATTERN (i1
)));
2961 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2962 SUBST_LINK (LOG_LINKS (i2
),
2963 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2966 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2967 make those two SETs separate I1 and I2 insns, and make an I0 that is
2970 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2971 && can_split_parallel_of_n_reg_sets (i2
, 2)
2972 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2973 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2975 /* If there is no I1, there is no I0 either. */
2978 /* We make I1 with the same INSN_UID as I2. This gives it
2979 the same DF_INSN_LUID for value tracking. Our fake I1 will
2980 never appear in the insn stream so giving it the same INSN_UID
2981 as I2 will not cause a problem. */
2983 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2984 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2986 INSN_UID (i1
) = INSN_UID (i2
);
2988 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2992 /* Verify that I2 and I1 are valid for combining. */
2993 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2994 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2996 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
3003 /* Record whether I2DEST is used in I2SRC and similarly for the other
3004 cases. Knowing this will help in register status updating below. */
3005 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3006 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3007 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3008 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3009 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3010 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3011 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3012 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3013 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3015 /* For the earlier insns, determine which of the subsequent ones they
3017 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3018 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3019 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3020 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3021 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3023 /* Ensure that I3's pattern can be the destination of combines. */
3024 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3025 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3026 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3027 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3034 /* See if any of the insns is a MULT operation. Unless one is, we will
3035 reject a combination that is, since it must be slower. Be conservative
3037 if (GET_CODE (i2src
) == MULT
3038 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3039 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3040 || (GET_CODE (PATTERN (i3
)) == SET
3041 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3044 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3045 We used to do this EXCEPT in one case: I3 has a post-inc in an
3046 output operand. However, that exception can give rise to insns like
3048 which is a famous insn on the PDP-11 where the value of r3 used as the
3049 source was model-dependent. Avoid this sort of thing. */
3052 if (!(GET_CODE (PATTERN (i3
)) == SET
3053 && REG_P (SET_SRC (PATTERN (i3
)))
3054 && MEM_P (SET_DEST (PATTERN (i3
)))
3055 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3056 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3057 /* It's not the exception. */
3062 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3063 if (REG_NOTE_KIND (link
) == REG_INC
3064 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3066 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3074 /* See if the SETs in I1 or I2 need to be kept around in the merged
3075 instruction: whenever the value set there is still needed past I3.
3076 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3078 For the SET in I1, we have two cases: if I1 and I2 independently feed
3079 into I3, the set in I1 needs to be kept around unless I1DEST dies
3080 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3081 in I1 needs to be kept around unless I1DEST dies or is set in either
3082 I2 or I3. The same considerations apply to I0. */
3084 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3087 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3088 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3093 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3094 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3095 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3096 && dead_or_set_p (i2
, i0dest
)));
3100 /* We are about to copy insns for the case where they need to be kept
3101 around. Check that they can be copied in the merged instruction. */
3103 if (targetm
.cannot_copy_insn_p
3104 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3105 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3106 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3112 /* If the set in I2 needs to be kept around, we must make a copy of
3113 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3114 PATTERN (I2), we are only substituting for the original I1DEST, not into
3115 an already-substituted copy. This also prevents making self-referential
3116 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3121 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3122 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3124 i2pat
= copy_rtx (PATTERN (i2
));
3129 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3130 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3132 i1pat
= copy_rtx (PATTERN (i1
));
3137 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3138 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3140 i0pat
= copy_rtx (PATTERN (i0
));
3145 /* Substitute in the latest insn for the regs set by the earlier ones. */
3147 maxreg
= max_reg_num ();
3151 /* Many machines that don't use CC0 have insns that can both perform an
3152 arithmetic operation and set the condition code. These operations will
3153 be represented as a PARALLEL with the first element of the vector
3154 being a COMPARE of an arithmetic operation with the constant zero.
3155 The second element of the vector will set some pseudo to the result
3156 of the same arithmetic operation. If we simplify the COMPARE, we won't
3157 match such a pattern and so will generate an extra insn. Here we test
3158 for this case, where both the comparison and the operation result are
3159 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3160 I2SRC. Later we will make the PARALLEL that contains I2. */
3162 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3163 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3164 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3165 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3168 rtx
*cc_use_loc
= NULL
;
3169 rtx_insn
*cc_use_insn
= NULL
;
3170 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3171 machine_mode compare_mode
, orig_compare_mode
;
3172 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3174 newpat
= PATTERN (i3
);
3175 newpat_dest
= SET_DEST (newpat
);
3176 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3178 if (undobuf
.other_insn
== 0
3179 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3182 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3183 compare_code
= simplify_compare_const (compare_code
,
3184 GET_MODE (i2dest
), op0
, &op1
);
3185 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3188 /* Do the rest only if op1 is const0_rtx, which may be the
3189 result of simplification. */
3190 if (op1
== const0_rtx
)
3192 /* If a single use of the CC is found, prepare to modify it
3193 when SELECT_CC_MODE returns a new CC-class mode, or when
3194 the above simplify_compare_const() returned a new comparison
3195 operator. undobuf.other_insn is assigned the CC use insn
3196 when modifying it. */
3199 #ifdef SELECT_CC_MODE
3200 machine_mode new_mode
3201 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3202 if (new_mode
!= orig_compare_mode
3203 && can_change_dest_mode (SET_DEST (newpat
),
3204 added_sets_2
, new_mode
))
3206 unsigned int regno
= REGNO (newpat_dest
);
3207 compare_mode
= new_mode
;
3208 if (regno
< FIRST_PSEUDO_REGISTER
)
3209 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3212 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3213 newpat_dest
= regno_reg_rtx
[regno
];
3217 /* Cases for modifying the CC-using comparison. */
3218 if (compare_code
!= orig_compare_code
3219 /* ??? Do we need to verify the zero rtx? */
3220 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3222 /* Replace cc_use_loc with entire new RTX. */
3224 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3225 newpat_dest
, const0_rtx
));
3226 undobuf
.other_insn
= cc_use_insn
;
3228 else if (compare_mode
!= orig_compare_mode
)
3230 /* Just replace the CC reg with a new mode. */
3231 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3232 undobuf
.other_insn
= cc_use_insn
;
3236 /* Now we modify the current newpat:
3237 First, SET_DEST(newpat) is updated if the CC mode has been
3238 altered. For targets without SELECT_CC_MODE, this should be
3240 if (compare_mode
!= orig_compare_mode
)
3241 SUBST (SET_DEST (newpat
), newpat_dest
);
3242 /* This is always done to propagate i2src into newpat. */
3243 SUBST (SET_SRC (newpat
),
3244 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3245 /* Create new version of i2pat if needed; the below PARALLEL
3246 creation needs this to work correctly. */
3247 if (! rtx_equal_p (i2src
, op0
))
3248 i2pat
= gen_rtx_SET (i2dest
, op0
);
3253 if (i2_is_used
== 0)
3255 /* It is possible that the source of I2 or I1 may be performing
3256 an unneeded operation, such as a ZERO_EXTEND of something
3257 that is known to have the high part zero. Handle that case
3258 by letting subst look at the inner insns.
3260 Another way to do this would be to have a function that tries
3261 to simplify a single insn instead of merging two or more
3262 insns. We don't do this because of the potential of infinite
3263 loops and because of the potential extra memory required.
3264 However, doing it the way we are is a bit of a kludge and
3265 doesn't catch all cases.
3267 But only do this if -fexpensive-optimizations since it slows
3268 things down and doesn't usually win.
3270 This is not done in the COMPARE case above because the
3271 unmodified I2PAT is used in the PARALLEL and so a pattern
3272 with a modified I2SRC would not match. */
3274 if (flag_expensive_optimizations
)
3276 /* Pass pc_rtx so no substitutions are done, just
3280 subst_low_luid
= DF_INSN_LUID (i1
);
3281 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3284 subst_low_luid
= DF_INSN_LUID (i2
);
3285 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3288 n_occurrences
= 0; /* `subst' counts here */
3289 subst_low_luid
= DF_INSN_LUID (i2
);
3291 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3292 copy of I2SRC each time we substitute it, in order to avoid creating
3293 self-referential RTL when we will be substituting I1SRC for I1DEST
3294 later. Likewise if I0 feeds into I2, either directly or indirectly
3295 through I1, and I0DEST is in I0SRC. */
3296 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3297 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3298 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3299 && i0dest_in_i0src
));
3302 /* Record whether I2's body now appears within I3's body. */
3303 i2_is_used
= n_occurrences
;
3306 /* If we already got a failure, don't try to do more. Otherwise, try to
3307 substitute I1 if we have it. */
3309 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3311 /* Check that an autoincrement side-effect on I1 has not been lost.
3312 This happens if I1DEST is mentioned in I2 and dies there, and
3313 has disappeared from the new pattern. */
3314 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3316 && dead_or_set_p (i2
, i1dest
)
3317 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3318 /* Before we can do this substitution, we must redo the test done
3319 above (see detailed comments there) that ensures I1DEST isn't
3320 mentioned in any SETs in NEWPAT that are field assignments. */
3321 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3329 subst_low_luid
= DF_INSN_LUID (i1
);
3331 /* If the following substitution will modify I1SRC, make a copy of it
3332 for the case where it is substituted for I1DEST in I2PAT later. */
3333 if (added_sets_2
&& i1_feeds_i2_n
)
3334 i1src_copy
= copy_rtx (i1src
);
3336 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3337 copy of I1SRC each time we substitute it, in order to avoid creating
3338 self-referential RTL when we will be substituting I0SRC for I0DEST
3340 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3341 i0_feeds_i1_n
&& i0dest_in_i0src
);
3344 /* Record whether I1's body now appears within I3's body. */
3345 i1_is_used
= n_occurrences
;
3348 /* Likewise for I0 if we have it. */
3350 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3352 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3353 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3354 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3355 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3356 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3363 /* If the following substitution will modify I0SRC, make a copy of it
3364 for the case where it is substituted for I0DEST in I1PAT later. */
3365 if (added_sets_1
&& i0_feeds_i1_n
)
3366 i0src_copy
= copy_rtx (i0src
);
3367 /* And a copy for I0DEST in I2PAT substitution. */
3368 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3369 || (i0_feeds_i2_n
)))
3370 i0src_copy2
= copy_rtx (i0src
);
3373 subst_low_luid
= DF_INSN_LUID (i0
);
3374 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3378 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3379 to count all the ways that I2SRC and I1SRC can be used. */
3380 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3381 && i2_is_used
+ added_sets_2
> 1)
3382 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3383 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3385 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3386 && (n_occurrences
+ added_sets_0
3387 + (added_sets_1
&& i0_feeds_i1_n
)
3388 + (added_sets_2
&& i0_feeds_i2_n
)
3390 /* Fail if we tried to make a new register. */
3391 || max_reg_num () != maxreg
3392 /* Fail if we couldn't do something and have a CLOBBER. */
3393 || GET_CODE (newpat
) == CLOBBER
3394 /* Fail if this new pattern is a MULT and we didn't have one before
3395 at the outer level. */
3396 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3403 /* If the actions of the earlier insns must be kept
3404 in addition to substituting them into the latest one,
3405 we must make a new PARALLEL for the latest insn
3406 to hold additional the SETs. */
3408 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3410 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3413 if (GET_CODE (newpat
) == PARALLEL
)
3415 rtvec old
= XVEC (newpat
, 0);
3416 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3417 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3418 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3419 sizeof (old
->elem
[0]) * old
->num_elem
);
3424 total_sets
= 1 + extra_sets
;
3425 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3426 XVECEXP (newpat
, 0, 0) = old
;
3430 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3436 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3438 XVECEXP (newpat
, 0, --total_sets
) = t
;
3444 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3445 i0_feeds_i1_n
&& i0dest_in_i0src
);
3446 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3447 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3449 XVECEXP (newpat
, 0, --total_sets
) = t
;
3453 validate_replacement
:
3455 /* Note which hard regs this insn has as inputs. */
3456 mark_used_regs_combine (newpat
);
3458 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3459 consider splitting this pattern, we might need these clobbers. */
3460 if (i1
&& GET_CODE (newpat
) == PARALLEL
3461 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3463 int len
= XVECLEN (newpat
, 0);
3465 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3466 for (i
= 0; i
< len
; i
++)
3467 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3470 /* We have recognized nothing yet. */
3471 insn_code_number
= -1;
3473 /* See if this is a PARALLEL of two SETs where one SET's destination is
3474 a register that is unused and this isn't marked as an instruction that
3475 might trap in an EH region. In that case, we just need the other SET.
3476 We prefer this over the PARALLEL.
3478 This can occur when simplifying a divmod insn. We *must* test for this
3479 case here because the code below that splits two independent SETs doesn't
3480 handle this case correctly when it updates the register status.
3482 It's pointless doing this if we originally had two sets, one from
3483 i3, and one from i2. Combining then splitting the parallel results
3484 in the original i2 again plus an invalid insn (which we delete).
3485 The net effect is only to move instructions around, which makes
3486 debug info less accurate. */
3488 if (!(added_sets_2
&& i1
== 0)
3489 && is_parallel_of_n_reg_sets (newpat
, 2)
3490 && asm_noperands (newpat
) < 0)
3492 rtx set0
= XVECEXP (newpat
, 0, 0);
3493 rtx set1
= XVECEXP (newpat
, 0, 1);
3494 rtx oldpat
= newpat
;
3496 if (((REG_P (SET_DEST (set1
))
3497 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3498 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3499 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3500 && insn_nothrow_p (i3
)
3501 && !side_effects_p (SET_SRC (set1
)))
3504 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3507 else if (((REG_P (SET_DEST (set0
))
3508 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3509 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3510 && find_reg_note (i3
, REG_UNUSED
,
3511 SUBREG_REG (SET_DEST (set0
)))))
3512 && insn_nothrow_p (i3
)
3513 && !side_effects_p (SET_SRC (set0
)))
3516 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3518 if (insn_code_number
>= 0)
3519 changed_i3_dest
= 1;
3522 if (insn_code_number
< 0)
3526 /* Is the result of combination a valid instruction? */
3527 if (insn_code_number
< 0)
3528 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3530 /* If we were combining three insns and the result is a simple SET
3531 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3532 insns. There are two ways to do this. It can be split using a
3533 machine-specific method (like when you have an addition of a large
3534 constant) or by combine in the function find_split_point. */
3536 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3537 && asm_noperands (newpat
) < 0)
3539 rtx parallel
, *split
;
3540 rtx_insn
*m_split_insn
;
3542 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3543 use I2DEST as a scratch register will help. In the latter case,
3544 convert I2DEST to the mode of the source of NEWPAT if we can. */
3546 m_split_insn
= combine_split_insns (newpat
, i3
);
3548 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3549 inputs of NEWPAT. */
3551 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3552 possible to try that as a scratch reg. This would require adding
3553 more code to make it work though. */
3555 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3557 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3559 /* First try to split using the original register as a
3560 scratch register. */
3561 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3562 gen_rtvec (2, newpat
,
3563 gen_rtx_CLOBBER (VOIDmode
,
3565 m_split_insn
= combine_split_insns (parallel
, i3
);
3567 /* If that didn't work, try changing the mode of I2DEST if
3569 if (m_split_insn
== 0
3570 && new_mode
!= GET_MODE (i2dest
)
3571 && new_mode
!= VOIDmode
3572 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3574 machine_mode old_mode
= GET_MODE (i2dest
);
3577 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3578 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3581 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3582 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3585 parallel
= (gen_rtx_PARALLEL
3587 gen_rtvec (2, newpat
,
3588 gen_rtx_CLOBBER (VOIDmode
,
3590 m_split_insn
= combine_split_insns (parallel
, i3
);
3592 if (m_split_insn
== 0
3593 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3597 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3598 buf
= undobuf
.undos
;
3599 undobuf
.undos
= buf
->next
;
3600 buf
->next
= undobuf
.frees
;
3601 undobuf
.frees
= buf
;
3605 i2scratch
= m_split_insn
!= 0;
3608 /* If recog_for_combine has discarded clobbers, try to use them
3609 again for the split. */
3610 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3612 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3613 m_split_insn
= combine_split_insns (parallel
, i3
);
3616 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3618 rtx m_split_pat
= PATTERN (m_split_insn
);
3619 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3620 if (insn_code_number
>= 0)
3621 newpat
= m_split_pat
;
3623 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3624 && (next_nonnote_nondebug_insn (i2
) == i3
3625 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3628 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3629 newi2pat
= PATTERN (m_split_insn
);
3631 i3set
= single_set (NEXT_INSN (m_split_insn
));
3632 i2set
= single_set (m_split_insn
);
3634 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3636 /* If I2 or I3 has multiple SETs, we won't know how to track
3637 register status, so don't use these insns. If I2's destination
3638 is used between I2 and I3, we also can't use these insns. */
3640 if (i2_code_number
>= 0 && i2set
&& i3set
3641 && (next_nonnote_nondebug_insn (i2
) == i3
3642 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3643 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3645 if (insn_code_number
>= 0)
3648 /* It is possible that both insns now set the destination of I3.
3649 If so, we must show an extra use of it. */
3651 if (insn_code_number
>= 0)
3653 rtx new_i3_dest
= SET_DEST (i3set
);
3654 rtx new_i2_dest
= SET_DEST (i2set
);
3656 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3657 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3658 || GET_CODE (new_i3_dest
) == SUBREG
)
3659 new_i3_dest
= XEXP (new_i3_dest
, 0);
3661 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3662 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3663 || GET_CODE (new_i2_dest
) == SUBREG
)
3664 new_i2_dest
= XEXP (new_i2_dest
, 0);
3666 if (REG_P (new_i3_dest
)
3667 && REG_P (new_i2_dest
)
3668 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3669 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3670 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3674 /* If we can split it and use I2DEST, go ahead and see if that
3675 helps things be recognized. Verify that none of the registers
3676 are set between I2 and I3. */
3677 if (insn_code_number
< 0
3678 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3679 && (!HAVE_cc0
|| REG_P (i2dest
))
3680 /* We need I2DEST in the proper mode. If it is a hard register
3681 or the only use of a pseudo, we can change its mode.
3682 Make sure we don't change a hard register to have a mode that
3683 isn't valid for it, or change the number of registers. */
3684 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3685 || GET_MODE (*split
) == VOIDmode
3686 || can_change_dest_mode (i2dest
, added_sets_2
,
3688 && (next_nonnote_nondebug_insn (i2
) == i3
3689 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3690 /* We can't overwrite I2DEST if its value is still used by
3692 && ! reg_referenced_p (i2dest
, newpat
))
3694 rtx newdest
= i2dest
;
3695 enum rtx_code split_code
= GET_CODE (*split
);
3696 machine_mode split_mode
= GET_MODE (*split
);
3697 bool subst_done
= false;
3698 newi2pat
= NULL_RTX
;
3702 /* *SPLIT may be part of I2SRC, so make sure we have the
3703 original expression around for later debug processing.
3704 We should not need I2SRC any more in other cases. */
3705 if (MAY_HAVE_DEBUG_INSNS
)
3706 i2src
= copy_rtx (i2src
);
3710 /* Get NEWDEST as a register in the proper mode. We have already
3711 validated that we can do this. */
3712 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3714 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3715 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3718 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3719 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3723 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3724 an ASHIFT. This can occur if it was inside a PLUS and hence
3725 appeared to be a memory address. This is a kludge. */
3726 if (split_code
== MULT
3727 && CONST_INT_P (XEXP (*split
, 1))
3728 && INTVAL (XEXP (*split
, 1)) > 0
3729 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3731 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3732 XEXP (*split
, 0), GEN_INT (i
)));
3733 /* Update split_code because we may not have a multiply
3735 split_code
= GET_CODE (*split
);
3738 /* Similarly for (plus (mult FOO (const_int pow2))). */
3739 if (split_code
== PLUS
3740 && GET_CODE (XEXP (*split
, 0)) == MULT
3741 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3742 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3743 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3745 rtx nsplit
= XEXP (*split
, 0);
3746 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3747 XEXP (nsplit
, 0), GEN_INT (i
)));
3748 /* Update split_code because we may not have a multiply
3750 split_code
= GET_CODE (*split
);
3753 #ifdef INSN_SCHEDULING
3754 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3755 be written as a ZERO_EXTEND. */
3756 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3758 #ifdef LOAD_EXTEND_OP
3759 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3760 what it really is. */
3761 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3763 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3764 SUBREG_REG (*split
)));
3767 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3768 SUBREG_REG (*split
)));
3772 /* Attempt to split binary operators using arithmetic identities. */
3773 if (BINARY_P (SET_SRC (newpat
))
3774 && split_mode
== GET_MODE (SET_SRC (newpat
))
3775 && ! side_effects_p (SET_SRC (newpat
)))
3777 rtx setsrc
= SET_SRC (newpat
);
3778 machine_mode mode
= GET_MODE (setsrc
);
3779 enum rtx_code code
= GET_CODE (setsrc
);
3780 rtx src_op0
= XEXP (setsrc
, 0);
3781 rtx src_op1
= XEXP (setsrc
, 1);
3783 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3784 if (rtx_equal_p (src_op0
, src_op1
))
3786 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3787 SUBST (XEXP (setsrc
, 0), newdest
);
3788 SUBST (XEXP (setsrc
, 1), newdest
);
3791 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3792 else if ((code
== PLUS
|| code
== MULT
)
3793 && GET_CODE (src_op0
) == code
3794 && GET_CODE (XEXP (src_op0
, 0)) == code
3795 && (INTEGRAL_MODE_P (mode
)
3796 || (FLOAT_MODE_P (mode
)
3797 && flag_unsafe_math_optimizations
)))
3799 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3800 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3801 rtx r
= XEXP (src_op0
, 1);
3804 /* Split both "((X op Y) op X) op Y" and
3805 "((X op Y) op Y) op X" as "T op T" where T is
3807 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3808 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3810 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3811 SUBST (XEXP (setsrc
, 0), newdest
);
3812 SUBST (XEXP (setsrc
, 1), newdest
);
3815 /* Split "((X op X) op Y) op Y)" as "T op T" where
3817 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3819 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3820 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3821 SUBST (XEXP (setsrc
, 0), newdest
);
3822 SUBST (XEXP (setsrc
, 1), newdest
);
3830 newi2pat
= gen_rtx_SET (newdest
, *split
);
3831 SUBST (*split
, newdest
);
3834 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3836 /* recog_for_combine might have added CLOBBERs to newi2pat.
3837 Make sure NEWPAT does not depend on the clobbered regs. */
3838 if (GET_CODE (newi2pat
) == PARALLEL
)
3839 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3840 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3842 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3843 if (reg_overlap_mentioned_p (reg
, newpat
))
3850 /* If the split point was a MULT and we didn't have one before,
3851 don't use one now. */
3852 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3853 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3857 /* Check for a case where we loaded from memory in a narrow mode and
3858 then sign extended it, but we need both registers. In that case,
3859 we have a PARALLEL with both loads from the same memory location.
3860 We can split this into a load from memory followed by a register-register
3861 copy. This saves at least one insn, more if register allocation can
3864 We cannot do this if the destination of the first assignment is a
3865 condition code register or cc0. We eliminate this case by making sure
3866 the SET_DEST and SET_SRC have the same mode.
3868 We cannot do this if the destination of the second assignment is
3869 a register that we have already assumed is zero-extended. Similarly
3870 for a SUBREG of such a register. */
3872 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3873 && GET_CODE (newpat
) == PARALLEL
3874 && XVECLEN (newpat
, 0) == 2
3875 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3876 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3877 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3878 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3879 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3880 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3881 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3882 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3884 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3885 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3886 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3888 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3889 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3890 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3891 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3892 != GET_MODE_MASK (word_mode
))))
3893 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3894 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3896 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3897 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3898 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3899 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3900 != GET_MODE_MASK (word_mode
)))))
3901 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3902 SET_SRC (XVECEXP (newpat
, 0, 1)))
3903 && ! find_reg_note (i3
, REG_UNUSED
,
3904 SET_DEST (XVECEXP (newpat
, 0, 0))))
3908 newi2pat
= XVECEXP (newpat
, 0, 0);
3909 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3910 newpat
= XVECEXP (newpat
, 0, 1);
3911 SUBST (SET_SRC (newpat
),
3912 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3913 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3915 if (i2_code_number
>= 0)
3916 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3918 if (insn_code_number
>= 0)
3922 /* Similarly, check for a case where we have a PARALLEL of two independent
3923 SETs but we started with three insns. In this case, we can do the sets
3924 as two separate insns. This case occurs when some SET allows two
3925 other insns to combine, but the destination of that SET is still live.
3927 Also do this if we started with two insns and (at least) one of the
3928 resulting sets is a noop; this noop will be deleted later. */
3930 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3931 && GET_CODE (newpat
) == PARALLEL
3932 && XVECLEN (newpat
, 0) == 2
3933 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3934 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3935 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3936 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3937 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3938 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3939 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3940 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3941 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3942 XVECEXP (newpat
, 0, 0))
3943 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3944 XVECEXP (newpat
, 0, 1))
3945 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3946 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3948 rtx set0
= XVECEXP (newpat
, 0, 0);
3949 rtx set1
= XVECEXP (newpat
, 0, 1);
3951 /* Normally, it doesn't matter which of the two is done first,
3952 but the one that references cc0 can't be the second, and
3953 one which uses any regs/memory set in between i2 and i3 can't
3954 be first. The PARALLEL might also have been pre-existing in i3,
3955 so we need to make sure that we won't wrongly hoist a SET to i2
3956 that would conflict with a death note present in there. */
3957 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3958 && !(REG_P (SET_DEST (set1
))
3959 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3960 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3961 && find_reg_note (i2
, REG_DEAD
,
3962 SUBREG_REG (SET_DEST (set1
))))
3963 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3964 /* If I3 is a jump, ensure that set0 is a jump so that
3965 we do not create invalid RTL. */
3966 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3972 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3973 && !(REG_P (SET_DEST (set0
))
3974 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3975 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3976 && find_reg_note (i2
, REG_DEAD
,
3977 SUBREG_REG (SET_DEST (set0
))))
3978 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3979 /* If I3 is a jump, ensure that set1 is a jump so that
3980 we do not create invalid RTL. */
3981 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3993 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3995 if (i2_code_number
>= 0)
3997 /* recog_for_combine might have added CLOBBERs to newi2pat.
3998 Make sure NEWPAT does not depend on the clobbered regs. */
3999 if (GET_CODE (newi2pat
) == PARALLEL
)
4001 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4002 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4004 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4005 if (reg_overlap_mentioned_p (reg
, newpat
))
4013 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4017 /* If it still isn't recognized, fail and change things back the way they
4019 if ((insn_code_number
< 0
4020 /* Is the result a reasonable ASM_OPERANDS? */
4021 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4027 /* If we had to change another insn, make sure it is valid also. */
4028 if (undobuf
.other_insn
)
4030 CLEAR_HARD_REG_SET (newpat_used_regs
);
4032 other_pat
= PATTERN (undobuf
.other_insn
);
4033 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4036 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4043 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4044 they are adjacent to each other or not. */
4047 rtx_insn
*p
= prev_nonnote_insn (i3
);
4048 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4049 && sets_cc0_p (newi2pat
))
4056 /* Only allow this combination if insn_rtx_costs reports that the
4057 replacement instructions are cheaper than the originals. */
4058 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4064 if (MAY_HAVE_DEBUG_INSNS
)
4068 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4069 if (undo
->kind
== UNDO_MODE
)
4071 rtx reg
= *undo
->where
.r
;
4072 machine_mode new_mode
= GET_MODE (reg
);
4073 machine_mode old_mode
= undo
->old_contents
.m
;
4075 /* Temporarily revert mode back. */
4076 adjust_reg_mode (reg
, old_mode
);
4078 if (reg
== i2dest
&& i2scratch
)
4080 /* If we used i2dest as a scratch register with a
4081 different mode, substitute it for the original
4082 i2src while its original mode is temporarily
4083 restored, and then clear i2scratch so that we don't
4084 do it again later. */
4085 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4088 /* Put back the new mode. */
4089 adjust_reg_mode (reg
, new_mode
);
4093 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4094 rtx_insn
*first
, *last
;
4099 last
= last_combined_insn
;
4104 last
= undobuf
.other_insn
;
4106 if (DF_INSN_LUID (last
)
4107 < DF_INSN_LUID (last_combined_insn
))
4108 last
= last_combined_insn
;
4111 /* We're dealing with a reg that changed mode but not
4112 meaning, so we want to turn it into a subreg for
4113 the new mode. However, because of REG sharing and
4114 because its mode had already changed, we have to do
4115 it in two steps. First, replace any debug uses of
4116 reg, with its original mode temporarily restored,
4117 with this copy we have created; then, replace the
4118 copy with the SUBREG of the original shared reg,
4119 once again changed to the new mode. */
4120 propagate_for_debug (first
, last
, reg
, tempreg
,
4122 adjust_reg_mode (reg
, new_mode
);
4123 propagate_for_debug (first
, last
, tempreg
,
4124 lowpart_subreg (old_mode
, reg
, new_mode
),
4130 /* If we will be able to accept this, we have made a
4131 change to the destination of I3. This requires us to
4132 do a few adjustments. */
4134 if (changed_i3_dest
)
4136 PATTERN (i3
) = newpat
;
4137 adjust_for_new_dest (i3
);
4140 /* We now know that we can do this combination. Merge the insns and
4141 update the status of registers and LOG_LINKS. */
4143 if (undobuf
.other_insn
)
4147 PATTERN (undobuf
.other_insn
) = other_pat
;
4149 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4150 ensure that they are still valid. Then add any non-duplicate
4151 notes added by recog_for_combine. */
4152 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4154 next
= XEXP (note
, 1);
4156 if ((REG_NOTE_KIND (note
) == REG_DEAD
4157 && !reg_referenced_p (XEXP (note
, 0),
4158 PATTERN (undobuf
.other_insn
)))
4159 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4160 && !reg_set_p (XEXP (note
, 0),
4161 PATTERN (undobuf
.other_insn
))))
4162 remove_note (undobuf
.other_insn
, note
);
4165 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4166 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4173 struct insn_link
*link
;
4176 /* I3 now uses what used to be its destination and which is now
4177 I2's destination. This requires us to do a few adjustments. */
4178 PATTERN (i3
) = newpat
;
4179 adjust_for_new_dest (i3
);
4181 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4184 However, some later insn might be using I2's dest and have
4185 a LOG_LINK pointing at I3. We must remove this link.
4186 The simplest way to remove the link is to point it at I1,
4187 which we know will be a NOTE. */
4189 /* newi2pat is usually a SET here; however, recog_for_combine might
4190 have added some clobbers. */
4191 if (GET_CODE (newi2pat
) == PARALLEL
)
4192 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4194 ni2dest
= SET_DEST (newi2pat
);
4196 for (insn
= NEXT_INSN (i3
);
4197 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4198 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4199 insn
= NEXT_INSN (insn
))
4201 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4203 FOR_EACH_LOG_LINK (link
, insn
)
4204 if (link
->insn
== i3
)
4213 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4214 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4217 /* Compute which registers we expect to eliminate. newi2pat may be setting
4218 either i3dest or i2dest, so we must check it. */
4219 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4220 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4223 /* For i1, we need to compute both local elimination and global
4224 elimination information with respect to newi2pat because i1dest
4225 may be the same as i3dest, in which case newi2pat may be setting
4226 i1dest. Global information is used when distributing REG_DEAD
4227 note for i2 and i3, in which case it does matter if newi2pat sets
4230 Local information is used when distributing REG_DEAD note for i1,
4231 in which case it doesn't matter if newi2pat sets i1dest or not.
4232 See PR62151, if we have four insns combination:
4234 i1: r1 <- i1src (using r0)
4236 i2: r0 <- i2src (using r1)
4237 i3: r3 <- i3src (using r0)
4239 From i1's point of view, r0 is eliminated, no matter if it is set
4240 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4241 should be discarded.
4243 Note local information only affects cases in forms like "I1->I2->I3",
4244 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4245 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4247 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4250 rtx elim_i1
= (local_elim_i1
== 0
4251 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4253 /* Same case as i1. */
4254 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4256 rtx elim_i0
= (local_elim_i0
== 0
4257 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4260 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4262 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4263 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4265 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4267 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4269 /* Ensure that we do not have something that should not be shared but
4270 occurs multiple times in the new insns. Check this by first
4271 resetting all the `used' flags and then copying anything is shared. */
4273 reset_used_flags (i3notes
);
4274 reset_used_flags (i2notes
);
4275 reset_used_flags (i1notes
);
4276 reset_used_flags (i0notes
);
4277 reset_used_flags (newpat
);
4278 reset_used_flags (newi2pat
);
4279 if (undobuf
.other_insn
)
4280 reset_used_flags (PATTERN (undobuf
.other_insn
));
4282 i3notes
= copy_rtx_if_shared (i3notes
);
4283 i2notes
= copy_rtx_if_shared (i2notes
);
4284 i1notes
= copy_rtx_if_shared (i1notes
);
4285 i0notes
= copy_rtx_if_shared (i0notes
);
4286 newpat
= copy_rtx_if_shared (newpat
);
4287 newi2pat
= copy_rtx_if_shared (newi2pat
);
4288 if (undobuf
.other_insn
)
4289 reset_used_flags (PATTERN (undobuf
.other_insn
));
4291 INSN_CODE (i3
) = insn_code_number
;
4292 PATTERN (i3
) = newpat
;
4294 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4296 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4298 reset_used_flags (call_usage
);
4299 call_usage
= copy_rtx (call_usage
);
4303 /* I2SRC must still be meaningful at this point. Some splitting
4304 operations can invalidate I2SRC, but those operations do not
4307 replace_rtx (call_usage
, i2dest
, i2src
);
4311 replace_rtx (call_usage
, i1dest
, i1src
);
4313 replace_rtx (call_usage
, i0dest
, i0src
);
4315 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4318 if (undobuf
.other_insn
)
4319 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4321 /* We had one special case above where I2 had more than one set and
4322 we replaced a destination of one of those sets with the destination
4323 of I3. In that case, we have to update LOG_LINKS of insns later
4324 in this basic block. Note that this (expensive) case is rare.
4326 Also, in this case, we must pretend that all REG_NOTEs for I2
4327 actually came from I3, so that REG_UNUSED notes from I2 will be
4328 properly handled. */
4330 if (i3_subst_into_i2
)
4332 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4333 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4334 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4335 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4336 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4337 && ! find_reg_note (i2
, REG_UNUSED
,
4338 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4339 for (temp_insn
= NEXT_INSN (i2
);
4341 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4342 || BB_HEAD (this_basic_block
) != temp_insn
);
4343 temp_insn
= NEXT_INSN (temp_insn
))
4344 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4345 FOR_EACH_LOG_LINK (link
, temp_insn
)
4346 if (link
->insn
== i2
)
4352 while (XEXP (link
, 1))
4353 link
= XEXP (link
, 1);
4354 XEXP (link
, 1) = i2notes
;
4361 LOG_LINKS (i3
) = NULL
;
4363 LOG_LINKS (i2
) = NULL
;
4368 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4369 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4371 INSN_CODE (i2
) = i2_code_number
;
4372 PATTERN (i2
) = newi2pat
;
4376 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4377 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4379 SET_INSN_DELETED (i2
);
4384 LOG_LINKS (i1
) = NULL
;
4386 if (MAY_HAVE_DEBUG_INSNS
)
4387 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4389 SET_INSN_DELETED (i1
);
4394 LOG_LINKS (i0
) = NULL
;
4396 if (MAY_HAVE_DEBUG_INSNS
)
4397 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4399 SET_INSN_DELETED (i0
);
4402 /* Get death notes for everything that is now used in either I3 or
4403 I2 and used to die in a previous insn. If we built two new
4404 patterns, move from I1 to I2 then I2 to I3 so that we get the
4405 proper movement on registers that I2 modifies. */
4408 from_luid
= DF_INSN_LUID (i0
);
4410 from_luid
= DF_INSN_LUID (i1
);
4412 from_luid
= DF_INSN_LUID (i2
);
4414 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4415 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4417 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4419 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4420 elim_i2
, elim_i1
, elim_i0
);
4422 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4423 elim_i2
, elim_i1
, elim_i0
);
4425 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4426 elim_i2
, local_elim_i1
, local_elim_i0
);
4428 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4429 elim_i2
, elim_i1
, local_elim_i0
);
4431 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4432 elim_i2
, elim_i1
, elim_i0
);
4434 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4435 know these are REG_UNUSED and want them to go to the desired insn,
4436 so we always pass it as i3. */
4438 if (newi2pat
&& new_i2_notes
)
4439 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4443 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4446 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4447 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4448 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4449 in that case, it might delete I2. Similarly for I2 and I1.
4450 Show an additional death due to the REG_DEAD note we make here. If
4451 we discard it in distribute_notes, we will decrement it again. */
4455 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4456 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4457 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4460 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4461 elim_i2
, elim_i1
, elim_i0
);
4464 if (i2dest_in_i2src
)
4466 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4467 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4468 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4469 NULL_RTX
, NULL_RTX
);
4471 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4472 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4475 if (i1dest_in_i1src
)
4477 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4478 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4479 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4480 NULL_RTX
, NULL_RTX
);
4482 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4483 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4486 if (i0dest_in_i0src
)
4488 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4489 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4490 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4491 NULL_RTX
, NULL_RTX
);
4493 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4494 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4497 distribute_links (i3links
);
4498 distribute_links (i2links
);
4499 distribute_links (i1links
);
4500 distribute_links (i0links
);
4504 struct insn_link
*link
;
4505 rtx_insn
*i2_insn
= 0;
4506 rtx i2_val
= 0, set
;
4508 /* The insn that used to set this register doesn't exist, and
4509 this life of the register may not exist either. See if one of
4510 I3's links points to an insn that sets I2DEST. If it does,
4511 that is now the last known value for I2DEST. If we don't update
4512 this and I2 set the register to a value that depended on its old
4513 contents, we will get confused. If this insn is used, thing
4514 will be set correctly in combine_instructions. */
4515 FOR_EACH_LOG_LINK (link
, i3
)
4516 if ((set
= single_set (link
->insn
)) != 0
4517 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4518 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4520 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4522 /* If the reg formerly set in I2 died only once and that was in I3,
4523 zero its use count so it won't make `reload' do any work. */
4525 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4526 && ! i2dest_in_i2src
4527 && REGNO (i2dest
) < reg_n_sets_max
)
4528 INC_REG_N_SETS (REGNO (i2dest
), -1);
4531 if (i1
&& REG_P (i1dest
))
4533 struct insn_link
*link
;
4534 rtx_insn
*i1_insn
= 0;
4535 rtx i1_val
= 0, set
;
4537 FOR_EACH_LOG_LINK (link
, i3
)
4538 if ((set
= single_set (link
->insn
)) != 0
4539 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4540 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4542 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4545 && ! i1dest_in_i1src
4546 && REGNO (i1dest
) < reg_n_sets_max
)
4547 INC_REG_N_SETS (REGNO (i1dest
), -1);
4550 if (i0
&& REG_P (i0dest
))
4552 struct insn_link
*link
;
4553 rtx_insn
*i0_insn
= 0;
4554 rtx i0_val
= 0, set
;
4556 FOR_EACH_LOG_LINK (link
, i3
)
4557 if ((set
= single_set (link
->insn
)) != 0
4558 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4559 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4561 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4564 && ! i0dest_in_i0src
4565 && REGNO (i0dest
) < reg_n_sets_max
)
4566 INC_REG_N_SETS (REGNO (i0dest
), -1);
4569 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4570 been made to this insn. The order is important, because newi2pat
4571 can affect nonzero_bits of newpat. */
4573 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4574 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4577 if (undobuf
.other_insn
!= NULL_RTX
)
4581 fprintf (dump_file
, "modifying other_insn ");
4582 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4584 df_insn_rescan (undobuf
.other_insn
);
4587 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4591 fprintf (dump_file
, "modifying insn i0 ");
4592 dump_insn_slim (dump_file
, i0
);
4594 df_insn_rescan (i0
);
4597 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4601 fprintf (dump_file
, "modifying insn i1 ");
4602 dump_insn_slim (dump_file
, i1
);
4604 df_insn_rescan (i1
);
4607 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4611 fprintf (dump_file
, "modifying insn i2 ");
4612 dump_insn_slim (dump_file
, i2
);
4614 df_insn_rescan (i2
);
4617 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4621 fprintf (dump_file
, "modifying insn i3 ");
4622 dump_insn_slim (dump_file
, i3
);
4624 df_insn_rescan (i3
);
4627 /* Set new_direct_jump_p if a new return or simple jump instruction
4628 has been created. Adjust the CFG accordingly. */
4629 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4631 *new_direct_jump_p
= 1;
4632 mark_jump_label (PATTERN (i3
), i3
, 0);
4633 update_cfg_for_uncondjump (i3
);
4636 if (undobuf
.other_insn
!= NULL_RTX
4637 && (returnjump_p (undobuf
.other_insn
)
4638 || any_uncondjump_p (undobuf
.other_insn
)))
4640 *new_direct_jump_p
= 1;
4641 update_cfg_for_uncondjump (undobuf
.other_insn
);
4644 /* A noop might also need cleaning up of CFG, if it comes from the
4645 simplification of a jump. */
4647 && GET_CODE (newpat
) == SET
4648 && SET_SRC (newpat
) == pc_rtx
4649 && SET_DEST (newpat
) == pc_rtx
)
4651 *new_direct_jump_p
= 1;
4652 update_cfg_for_uncondjump (i3
);
4655 if (undobuf
.other_insn
!= NULL_RTX
4656 && JUMP_P (undobuf
.other_insn
)
4657 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4658 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4659 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4661 *new_direct_jump_p
= 1;
4662 update_cfg_for_uncondjump (undobuf
.other_insn
);
4665 combine_successes
++;
4668 if (added_links_insn
4669 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4670 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4671 return added_links_insn
;
4673 return newi2pat
? i2
: i3
;
4676 /* Get a marker for undoing to the current state. */
4679 get_undo_marker (void)
4681 return undobuf
.undos
;
4684 /* Undo the modifications up to the marker. */
4687 undo_to_marker (void *marker
)
4689 struct undo
*undo
, *next
;
4691 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4699 *undo
->where
.r
= undo
->old_contents
.r
;
4702 *undo
->where
.i
= undo
->old_contents
.i
;
4705 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4708 *undo
->where
.l
= undo
->old_contents
.l
;
4714 undo
->next
= undobuf
.frees
;
4715 undobuf
.frees
= undo
;
4718 undobuf
.undos
= (struct undo
*) marker
;
4721 /* Undo all the modifications recorded in undobuf. */
4729 /* We've committed to accepting the changes we made. Move all
4730 of the undos to the free list. */
4735 struct undo
*undo
, *next
;
4737 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4740 undo
->next
= undobuf
.frees
;
4741 undobuf
.frees
= undo
;
4746 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4747 where we have an arithmetic expression and return that point. LOC will
4750 try_combine will call this function to see if an insn can be split into
4754 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4757 enum rtx_code code
= GET_CODE (x
);
4759 unsigned HOST_WIDE_INT len
= 0;
4760 HOST_WIDE_INT pos
= 0;
4762 rtx inner
= NULL_RTX
;
4764 /* First special-case some codes. */
4768 #ifdef INSN_SCHEDULING
4769 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4771 if (MEM_P (SUBREG_REG (x
)))
4774 return find_split_point (&SUBREG_REG (x
), insn
, false);
4777 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4778 using LO_SUM and HIGH. */
4779 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4780 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4782 machine_mode address_mode
= get_address_mode (x
);
4785 gen_rtx_LO_SUM (address_mode
,
4786 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4788 return &XEXP (XEXP (x
, 0), 0);
4791 /* If we have a PLUS whose second operand is a constant and the
4792 address is not valid, perhaps will can split it up using
4793 the machine-specific way to split large constants. We use
4794 the first pseudo-reg (one of the virtual regs) as a placeholder;
4795 it will not remain in the result. */
4796 if (GET_CODE (XEXP (x
, 0)) == PLUS
4797 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4798 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4799 MEM_ADDR_SPACE (x
)))
4801 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4802 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4805 /* This should have produced two insns, each of which sets our
4806 placeholder. If the source of the second is a valid address,
4807 we can make put both sources together and make a split point
4811 && NEXT_INSN (seq
) != NULL_RTX
4812 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4813 && NONJUMP_INSN_P (seq
)
4814 && GET_CODE (PATTERN (seq
)) == SET
4815 && SET_DEST (PATTERN (seq
)) == reg
4816 && ! reg_mentioned_p (reg
,
4817 SET_SRC (PATTERN (seq
)))
4818 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4819 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4820 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4821 && memory_address_addr_space_p
4822 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4823 MEM_ADDR_SPACE (x
)))
4825 rtx src1
= SET_SRC (PATTERN (seq
));
4826 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4828 /* Replace the placeholder in SRC2 with SRC1. If we can
4829 find where in SRC2 it was placed, that can become our
4830 split point and we can replace this address with SRC2.
4831 Just try two obvious places. */
4833 src2
= replace_rtx (src2
, reg
, src1
);
4835 if (XEXP (src2
, 0) == src1
)
4836 split
= &XEXP (src2
, 0);
4837 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4838 && XEXP (XEXP (src2
, 0), 0) == src1
)
4839 split
= &XEXP (XEXP (src2
, 0), 0);
4843 SUBST (XEXP (x
, 0), src2
);
4848 /* If that didn't work, perhaps the first operand is complex and
4849 needs to be computed separately, so make a split point there.
4850 This will occur on machines that just support REG + CONST
4851 and have a constant moved through some previous computation. */
4853 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4854 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4855 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4856 return &XEXP (XEXP (x
, 0), 0);
4859 /* If we have a PLUS whose first operand is complex, try computing it
4860 separately by making a split there. */
4861 if (GET_CODE (XEXP (x
, 0)) == PLUS
4862 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4864 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4865 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4866 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4867 return &XEXP (XEXP (x
, 0), 0);
4871 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4872 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4873 we need to put the operand into a register. So split at that
4876 if (SET_DEST (x
) == cc0_rtx
4877 && GET_CODE (SET_SRC (x
)) != COMPARE
4878 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4879 && !OBJECT_P (SET_SRC (x
))
4880 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4881 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4882 return &SET_SRC (x
);
4884 /* See if we can split SET_SRC as it stands. */
4885 split
= find_split_point (&SET_SRC (x
), insn
, true);
4886 if (split
&& split
!= &SET_SRC (x
))
4889 /* See if we can split SET_DEST as it stands. */
4890 split
= find_split_point (&SET_DEST (x
), insn
, false);
4891 if (split
&& split
!= &SET_DEST (x
))
4894 /* See if this is a bitfield assignment with everything constant. If
4895 so, this is an IOR of an AND, so split it into that. */
4896 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4897 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4898 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4899 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4900 && CONST_INT_P (SET_SRC (x
))
4901 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4902 + INTVAL (XEXP (SET_DEST (x
), 2)))
4903 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4904 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4906 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4907 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4908 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4909 rtx dest
= XEXP (SET_DEST (x
), 0);
4910 machine_mode mode
= GET_MODE (dest
);
4911 unsigned HOST_WIDE_INT mask
4912 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4915 if (BITS_BIG_ENDIAN
)
4916 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4918 or_mask
= gen_int_mode (src
<< pos
, mode
);
4921 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4924 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4926 simplify_gen_binary (IOR
, mode
,
4927 simplify_gen_binary (AND
, mode
,
4932 SUBST (SET_DEST (x
), dest
);
4934 split
= find_split_point (&SET_SRC (x
), insn
, true);
4935 if (split
&& split
!= &SET_SRC (x
))
4939 /* Otherwise, see if this is an operation that we can split into two.
4940 If so, try to split that. */
4941 code
= GET_CODE (SET_SRC (x
));
4946 /* If we are AND'ing with a large constant that is only a single
4947 bit and the result is only being used in a context where we
4948 need to know if it is zero or nonzero, replace it with a bit
4949 extraction. This will avoid the large constant, which might
4950 have taken more than one insn to make. If the constant were
4951 not a valid argument to the AND but took only one insn to make,
4952 this is no worse, but if it took more than one insn, it will
4955 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4956 && REG_P (XEXP (SET_SRC (x
), 0))
4957 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4958 && REG_P (SET_DEST (x
))
4959 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4960 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4961 && XEXP (*split
, 0) == SET_DEST (x
)
4962 && XEXP (*split
, 1) == const0_rtx
)
4964 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4965 XEXP (SET_SRC (x
), 0),
4966 pos
, NULL_RTX
, 1, 1, 0, 0);
4967 if (extraction
!= 0)
4969 SUBST (SET_SRC (x
), extraction
);
4970 return find_split_point (loc
, insn
, false);
4976 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4977 is known to be on, this can be converted into a NEG of a shift. */
4978 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4979 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4980 && 1 <= (pos
= exact_log2
4981 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4982 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4984 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4988 gen_rtx_LSHIFTRT (mode
,
4989 XEXP (SET_SRC (x
), 0),
4992 split
= find_split_point (&SET_SRC (x
), insn
, true);
4993 if (split
&& split
!= &SET_SRC (x
))
4999 inner
= XEXP (SET_SRC (x
), 0);
5001 /* We can't optimize if either mode is a partial integer
5002 mode as we don't know how many bits are significant
5004 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5005 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5009 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5015 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5016 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5018 inner
= XEXP (SET_SRC (x
), 0);
5019 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5020 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5022 if (BITS_BIG_ENDIAN
)
5023 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5024 unsignedp
= (code
== ZERO_EXTRACT
);
5033 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5035 machine_mode mode
= GET_MODE (SET_SRC (x
));
5037 /* For unsigned, we have a choice of a shift followed by an
5038 AND or two shifts. Use two shifts for field sizes where the
5039 constant might be too large. We assume here that we can
5040 always at least get 8-bit constants in an AND insn, which is
5041 true for every current RISC. */
5043 if (unsignedp
&& len
<= 8)
5045 unsigned HOST_WIDE_INT mask
5046 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
5050 (mode
, gen_lowpart (mode
, inner
),
5052 gen_int_mode (mask
, mode
)));
5054 split
= find_split_point (&SET_SRC (x
), insn
, true);
5055 if (split
&& split
!= &SET_SRC (x
))
5062 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5063 gen_rtx_ASHIFT (mode
,
5064 gen_lowpart (mode
, inner
),
5065 GEN_INT (GET_MODE_PRECISION (mode
)
5067 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5069 split
= find_split_point (&SET_SRC (x
), insn
, true);
5070 if (split
&& split
!= &SET_SRC (x
))
5075 /* See if this is a simple operation with a constant as the second
5076 operand. It might be that this constant is out of range and hence
5077 could be used as a split point. */
5078 if (BINARY_P (SET_SRC (x
))
5079 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5080 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5081 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5082 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5083 return &XEXP (SET_SRC (x
), 1);
5085 /* Finally, see if this is a simple operation with its first operand
5086 not in a register. The operation might require this operand in a
5087 register, so return it as a split point. We can always do this
5088 because if the first operand were another operation, we would have
5089 already found it as a split point. */
5090 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5091 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5092 return &XEXP (SET_SRC (x
), 0);
5098 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5099 it is better to write this as (not (ior A B)) so we can split it.
5100 Similarly for IOR. */
5101 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5104 gen_rtx_NOT (GET_MODE (x
),
5105 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5107 XEXP (XEXP (x
, 0), 0),
5108 XEXP (XEXP (x
, 1), 0))));
5109 return find_split_point (loc
, insn
, set_src
);
5112 /* Many RISC machines have a large set of logical insns. If the
5113 second operand is a NOT, put it first so we will try to split the
5114 other operand first. */
5115 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5117 rtx tem
= XEXP (x
, 0);
5118 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5119 SUBST (XEXP (x
, 1), tem
);
5125 /* Canonicalization can produce (minus A (mult B C)), where C is a
5126 constant. It may be better to try splitting (plus (mult B -C) A)
5127 instead if this isn't a multiply by a power of two. */
5128 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5129 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5130 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
5132 machine_mode mode
= GET_MODE (x
);
5133 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5134 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5135 SUBST (*loc
, gen_rtx_PLUS (mode
,
5137 XEXP (XEXP (x
, 1), 0),
5138 gen_int_mode (other_int
,
5141 return find_split_point (loc
, insn
, set_src
);
5144 /* Split at a multiply-accumulate instruction. However if this is
5145 the SET_SRC, we likely do not have such an instruction and it's
5146 worthless to try this split. */
5148 && (GET_CODE (XEXP (x
, 0)) == MULT
5149 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5150 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5157 /* Otherwise, select our actions depending on our rtx class. */
5158 switch (GET_RTX_CLASS (code
))
5160 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5162 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5165 /* ... fall through ... */
5167 case RTX_COMM_ARITH
:
5169 case RTX_COMM_COMPARE
:
5170 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5173 /* ... fall through ... */
5175 /* Some machines have (and (shift ...) ...) insns. If X is not
5176 an AND, but XEXP (X, 0) is, use it as our split point. */
5177 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5178 return &XEXP (x
, 0);
5180 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5186 /* Otherwise, we don't have a split point. */
5191 /* Throughout X, replace FROM with TO, and return the result.
5192 The result is TO if X is FROM;
5193 otherwise the result is X, but its contents may have been modified.
5194 If they were modified, a record was made in undobuf so that
5195 undo_all will (among other things) return X to its original state.
5197 If the number of changes necessary is too much to record to undo,
5198 the excess changes are not made, so the result is invalid.
5199 The changes already made can still be undone.
5200 undobuf.num_undo is incremented for such changes, so by testing that
5201 the caller can tell whether the result is valid.
5203 `n_occurrences' is incremented each time FROM is replaced.
5205 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5207 IN_COND is nonzero if we are at the top level of a condition.
5209 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5210 by copying if `n_occurrences' is nonzero. */
5213 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5215 enum rtx_code code
= GET_CODE (x
);
5216 machine_mode op0_mode
= VOIDmode
;
5221 /* Two expressions are equal if they are identical copies of a shared
5222 RTX or if they are both registers with the same register number
5225 #define COMBINE_RTX_EQUAL_P(X,Y) \
5227 || (REG_P (X) && REG_P (Y) \
5228 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5230 /* Do not substitute into clobbers of regs -- this will never result in
5232 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5235 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5238 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5241 /* If X and FROM are the same register but different modes, they
5242 will not have been seen as equal above. However, the log links code
5243 will make a LOG_LINKS entry for that case. If we do nothing, we
5244 will try to rerecognize our original insn and, when it succeeds,
5245 we will delete the feeding insn, which is incorrect.
5247 So force this insn not to match in this (rare) case. */
5248 if (! in_dest
&& code
== REG
&& REG_P (from
)
5249 && reg_overlap_mentioned_p (x
, from
))
5250 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5252 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5253 of which may contain things that can be combined. */
5254 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5257 /* It is possible to have a subexpression appear twice in the insn.
5258 Suppose that FROM is a register that appears within TO.
5259 Then, after that subexpression has been scanned once by `subst',
5260 the second time it is scanned, TO may be found. If we were
5261 to scan TO here, we would find FROM within it and create a
5262 self-referent rtl structure which is completely wrong. */
5263 if (COMBINE_RTX_EQUAL_P (x
, to
))
5266 /* Parallel asm_operands need special attention because all of the
5267 inputs are shared across the arms. Furthermore, unsharing the
5268 rtl results in recognition failures. Failure to handle this case
5269 specially can result in circular rtl.
5271 Solve this by doing a normal pass across the first entry of the
5272 parallel, and only processing the SET_DESTs of the subsequent
5275 if (code
== PARALLEL
5276 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5277 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5279 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5281 /* If this substitution failed, this whole thing fails. */
5282 if (GET_CODE (new_rtx
) == CLOBBER
5283 && XEXP (new_rtx
, 0) == const0_rtx
)
5286 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5288 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5290 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5293 && GET_CODE (dest
) != CC0
5294 && GET_CODE (dest
) != PC
)
5296 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5298 /* If this substitution failed, this whole thing fails. */
5299 if (GET_CODE (new_rtx
) == CLOBBER
5300 && XEXP (new_rtx
, 0) == const0_rtx
)
5303 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5309 len
= GET_RTX_LENGTH (code
);
5310 fmt
= GET_RTX_FORMAT (code
);
5312 /* We don't need to process a SET_DEST that is a register, CC0,
5313 or PC, so set up to skip this common case. All other cases
5314 where we want to suppress replacing something inside a
5315 SET_SRC are handled via the IN_DEST operand. */
5317 && (REG_P (SET_DEST (x
))
5318 || GET_CODE (SET_DEST (x
)) == CC0
5319 || GET_CODE (SET_DEST (x
)) == PC
))
5322 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5325 op0_mode
= GET_MODE (XEXP (x
, 0));
5327 for (i
= 0; i
< len
; i
++)
5332 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5334 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5336 new_rtx
= (unique_copy
&& n_occurrences
5337 ? copy_rtx (to
) : to
);
5342 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5345 /* If this substitution failed, this whole thing
5347 if (GET_CODE (new_rtx
) == CLOBBER
5348 && XEXP (new_rtx
, 0) == const0_rtx
)
5352 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5355 else if (fmt
[i
] == 'e')
5357 /* If this is a register being set, ignore it. */
5358 new_rtx
= XEXP (x
, i
);
5361 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5363 || code
== STRICT_LOW_PART
))
5366 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5368 /* In general, don't install a subreg involving two
5369 modes not tieable. It can worsen register
5370 allocation, and can even make invalid reload
5371 insns, since the reg inside may need to be copied
5372 from in the outside mode, and that may be invalid
5373 if it is an fp reg copied in integer mode.
5375 We allow two exceptions to this: It is valid if
5376 it is inside another SUBREG and the mode of that
5377 SUBREG and the mode of the inside of TO is
5378 tieable and it is valid if X is a SET that copies
5381 if (GET_CODE (to
) == SUBREG
5382 && ! MODES_TIEABLE_P (GET_MODE (to
),
5383 GET_MODE (SUBREG_REG (to
)))
5384 && ! (code
== SUBREG
5385 && MODES_TIEABLE_P (GET_MODE (x
),
5386 GET_MODE (SUBREG_REG (to
))))
5388 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5391 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5395 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5396 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5399 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5401 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5405 /* If we are in a SET_DEST, suppress most cases unless we
5406 have gone inside a MEM, in which case we want to
5407 simplify the address. We assume here that things that
5408 are actually part of the destination have their inner
5409 parts in the first expression. This is true for SUBREG,
5410 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5411 things aside from REG and MEM that should appear in a
5413 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5415 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5416 || code
== ZERO_EXTRACT
))
5419 code
== IF_THEN_ELSE
&& i
== 0,
5422 /* If we found that we will have to reject this combination,
5423 indicate that by returning the CLOBBER ourselves, rather than
5424 an expression containing it. This will speed things up as
5425 well as prevent accidents where two CLOBBERs are considered
5426 to be equal, thus producing an incorrect simplification. */
5428 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5431 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5433 machine_mode mode
= GET_MODE (x
);
5435 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5436 GET_MODE (SUBREG_REG (x
)),
5439 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5441 else if (CONST_SCALAR_INT_P (new_rtx
)
5442 && GET_CODE (x
) == ZERO_EXTEND
)
5444 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5445 new_rtx
, GET_MODE (XEXP (x
, 0)));
5449 SUBST (XEXP (x
, i
), new_rtx
);
5454 /* Check if we are loading something from the constant pool via float
5455 extension; in this case we would undo compress_float_constant
5456 optimization and degenerate constant load to an immediate value. */
5457 if (GET_CODE (x
) == FLOAT_EXTEND
5458 && MEM_P (XEXP (x
, 0))
5459 && MEM_READONLY_P (XEXP (x
, 0)))
5461 rtx tmp
= avoid_constant_pool_reference (x
);
5466 /* Try to simplify X. If the simplification changed the code, it is likely
5467 that further simplification will help, so loop, but limit the number
5468 of repetitions that will be performed. */
5470 for (i
= 0; i
< 4; i
++)
5472 /* If X is sufficiently simple, don't bother trying to do anything
5474 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5475 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5477 if (GET_CODE (x
) == code
)
5480 code
= GET_CODE (x
);
5482 /* We no longer know the original mode of operand 0 since we
5483 have changed the form of X) */
5484 op0_mode
= VOIDmode
;
5490 /* Simplify X, a piece of RTL. We just operate on the expression at the
5491 outer level; call `subst' to simplify recursively. Return the new
5494 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5495 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5499 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5502 enum rtx_code code
= GET_CODE (x
);
5503 machine_mode mode
= GET_MODE (x
);
5507 /* If this is a commutative operation, put a constant last and a complex
5508 expression first. We don't need to do this for comparisons here. */
5509 if (COMMUTATIVE_ARITH_P (x
)
5510 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5513 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5514 SUBST (XEXP (x
, 1), temp
);
5517 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5518 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5519 things. Check for cases where both arms are testing the same
5522 Don't do anything if all operands are very simple. */
5525 && ((!OBJECT_P (XEXP (x
, 0))
5526 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5527 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5528 || (!OBJECT_P (XEXP (x
, 1))
5529 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5530 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5532 && (!OBJECT_P (XEXP (x
, 0))
5533 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5534 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5536 rtx cond
, true_rtx
, false_rtx
;
5538 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5540 /* If everything is a comparison, what we have is highly unlikely
5541 to be simpler, so don't use it. */
5542 && ! (COMPARISON_P (x
)
5543 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5545 rtx cop1
= const0_rtx
;
5546 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5548 if (cond_code
== NE
&& COMPARISON_P (cond
))
5551 /* Simplify the alternative arms; this may collapse the true and
5552 false arms to store-flag values. Be careful to use copy_rtx
5553 here since true_rtx or false_rtx might share RTL with x as a
5554 result of the if_then_else_cond call above. */
5555 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5556 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5558 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5559 is unlikely to be simpler. */
5560 if (general_operand (true_rtx
, VOIDmode
)
5561 && general_operand (false_rtx
, VOIDmode
))
5563 enum rtx_code reversed
;
5565 /* Restarting if we generate a store-flag expression will cause
5566 us to loop. Just drop through in this case. */
5568 /* If the result values are STORE_FLAG_VALUE and zero, we can
5569 just make the comparison operation. */
5570 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5571 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5573 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5574 && ((reversed
= reversed_comparison_code_parts
5575 (cond_code
, cond
, cop1
, NULL
))
5577 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5580 /* Likewise, we can make the negate of a comparison operation
5581 if the result values are - STORE_FLAG_VALUE and zero. */
5582 else if (CONST_INT_P (true_rtx
)
5583 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5584 && false_rtx
== const0_rtx
)
5585 x
= simplify_gen_unary (NEG
, mode
,
5586 simplify_gen_relational (cond_code
,
5590 else if (CONST_INT_P (false_rtx
)
5591 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5592 && true_rtx
== const0_rtx
5593 && ((reversed
= reversed_comparison_code_parts
5594 (cond_code
, cond
, cop1
, NULL
))
5596 x
= simplify_gen_unary (NEG
, mode
,
5597 simplify_gen_relational (reversed
,
5602 return gen_rtx_IF_THEN_ELSE (mode
,
5603 simplify_gen_relational (cond_code
,
5608 true_rtx
, false_rtx
);
5610 code
= GET_CODE (x
);
5611 op0_mode
= VOIDmode
;
5616 /* Try to fold this expression in case we have constants that weren't
5619 switch (GET_RTX_CLASS (code
))
5622 if (op0_mode
== VOIDmode
)
5623 op0_mode
= GET_MODE (XEXP (x
, 0));
5624 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5627 case RTX_COMM_COMPARE
:
5629 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5630 if (cmp_mode
== VOIDmode
)
5632 cmp_mode
= GET_MODE (XEXP (x
, 1));
5633 if (cmp_mode
== VOIDmode
)
5634 cmp_mode
= op0_mode
;
5636 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5637 XEXP (x
, 0), XEXP (x
, 1));
5640 case RTX_COMM_ARITH
:
5642 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5644 case RTX_BITFIELD_OPS
:
5646 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5647 XEXP (x
, 1), XEXP (x
, 2));
5656 code
= GET_CODE (temp
);
5657 op0_mode
= VOIDmode
;
5658 mode
= GET_MODE (temp
);
5661 /* First see if we can apply the inverse distributive law. */
5662 if (code
== PLUS
|| code
== MINUS
5663 || code
== AND
|| code
== IOR
|| code
== XOR
)
5665 x
= apply_distributive_law (x
);
5666 code
= GET_CODE (x
);
5667 op0_mode
= VOIDmode
;
5670 /* If CODE is an associative operation not otherwise handled, see if we
5671 can associate some operands. This can win if they are constants or
5672 if they are logically related (i.e. (a & b) & a). */
5673 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5674 || code
== AND
|| code
== IOR
|| code
== XOR
5675 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5676 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5677 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5679 if (GET_CODE (XEXP (x
, 0)) == code
)
5681 rtx other
= XEXP (XEXP (x
, 0), 0);
5682 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5683 rtx inner_op1
= XEXP (x
, 1);
5686 /* Make sure we pass the constant operand if any as the second
5687 one if this is a commutative operation. */
5688 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5690 rtx tem
= inner_op0
;
5691 inner_op0
= inner_op1
;
5694 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5695 : code
== DIV
? MULT
5697 mode
, inner_op0
, inner_op1
);
5699 /* For commutative operations, try the other pair if that one
5701 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5703 other
= XEXP (XEXP (x
, 0), 1);
5704 inner
= simplify_binary_operation (code
, mode
,
5705 XEXP (XEXP (x
, 0), 0),
5710 return simplify_gen_binary (code
, mode
, other
, inner
);
5714 /* A little bit of algebraic simplification here. */
5718 /* Ensure that our address has any ASHIFTs converted to MULT in case
5719 address-recognizing predicates are called later. */
5720 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5721 SUBST (XEXP (x
, 0), temp
);
5725 if (op0_mode
== VOIDmode
)
5726 op0_mode
= GET_MODE (SUBREG_REG (x
));
5728 /* See if this can be moved to simplify_subreg. */
5729 if (CONSTANT_P (SUBREG_REG (x
))
5730 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5731 /* Don't call gen_lowpart if the inner mode
5732 is VOIDmode and we cannot simplify it, as SUBREG without
5733 inner mode is invalid. */
5734 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5735 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5736 return gen_lowpart (mode
, SUBREG_REG (x
));
5738 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5742 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5747 /* If op is known to have all lower bits zero, the result is zero. */
5749 && SCALAR_INT_MODE_P (mode
)
5750 && SCALAR_INT_MODE_P (op0_mode
)
5751 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5752 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5753 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5754 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5755 & GET_MODE_MASK (mode
)) == 0)
5756 return CONST0_RTX (mode
);
5759 /* Don't change the mode of the MEM if that would change the meaning
5761 if (MEM_P (SUBREG_REG (x
))
5762 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5763 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5764 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5765 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5767 /* Note that we cannot do any narrowing for non-constants since
5768 we might have been counting on using the fact that some bits were
5769 zero. We now do this in the SET. */
5774 temp
= expand_compound_operation (XEXP (x
, 0));
5776 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5777 replaced by (lshiftrt X C). This will convert
5778 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5780 if (GET_CODE (temp
) == ASHIFTRT
5781 && CONST_INT_P (XEXP (temp
, 1))
5782 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5783 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5784 INTVAL (XEXP (temp
, 1)));
5786 /* If X has only a single bit that might be nonzero, say, bit I, convert
5787 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5788 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5789 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5790 or a SUBREG of one since we'd be making the expression more
5791 complex if it was just a register. */
5794 && ! (GET_CODE (temp
) == SUBREG
5795 && REG_P (SUBREG_REG (temp
)))
5796 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5798 rtx temp1
= simplify_shift_const
5799 (NULL_RTX
, ASHIFTRT
, mode
,
5800 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5801 GET_MODE_PRECISION (mode
) - 1 - i
),
5802 GET_MODE_PRECISION (mode
) - 1 - i
);
5804 /* If all we did was surround TEMP with the two shifts, we
5805 haven't improved anything, so don't use it. Otherwise,
5806 we are better off with TEMP1. */
5807 if (GET_CODE (temp1
) != ASHIFTRT
5808 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5809 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5815 /* We can't handle truncation to a partial integer mode here
5816 because we don't know the real bitsize of the partial
5818 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5821 if (HWI_COMPUTABLE_MODE_P (mode
))
5823 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5824 GET_MODE_MASK (mode
), 0));
5826 /* We can truncate a constant value and return it. */
5827 if (CONST_INT_P (XEXP (x
, 0)))
5828 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5830 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5831 whose value is a comparison can be replaced with a subreg if
5832 STORE_FLAG_VALUE permits. */
5833 if (HWI_COMPUTABLE_MODE_P (mode
)
5834 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5835 && (temp
= get_last_value (XEXP (x
, 0)))
5836 && COMPARISON_P (temp
))
5837 return gen_lowpart (mode
, XEXP (x
, 0));
5841 /* (const (const X)) can become (const X). Do it this way rather than
5842 returning the inner CONST since CONST can be shared with a
5844 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5845 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5849 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5850 can add in an offset. find_split_point will split this address up
5851 again if it doesn't match. */
5852 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5853 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5858 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5859 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5860 bit-field and can be replaced by either a sign_extend or a
5861 sign_extract. The `and' may be a zero_extend and the two
5862 <c>, -<c> constants may be reversed. */
5863 if (GET_CODE (XEXP (x
, 0)) == XOR
5864 && CONST_INT_P (XEXP (x
, 1))
5865 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5866 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5867 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5868 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5869 && HWI_COMPUTABLE_MODE_P (mode
)
5870 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5871 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5872 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5873 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5874 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5875 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5876 == (unsigned int) i
+ 1))))
5877 return simplify_shift_const
5878 (NULL_RTX
, ASHIFTRT
, mode
,
5879 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5880 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5881 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5882 GET_MODE_PRECISION (mode
) - (i
+ 1));
5884 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5885 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5886 the bitsize of the mode - 1. This allows simplification of
5887 "a = (b & 8) == 0;" */
5888 if (XEXP (x
, 1) == constm1_rtx
5889 && !REG_P (XEXP (x
, 0))
5890 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5891 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5892 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5893 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5894 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5895 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5896 GET_MODE_PRECISION (mode
) - 1),
5897 GET_MODE_PRECISION (mode
) - 1);
5899 /* If we are adding two things that have no bits in common, convert
5900 the addition into an IOR. This will often be further simplified,
5901 for example in cases like ((a & 1) + (a & 2)), which can
5904 if (HWI_COMPUTABLE_MODE_P (mode
)
5905 && (nonzero_bits (XEXP (x
, 0), mode
)
5906 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5908 /* Try to simplify the expression further. */
5909 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5910 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5912 /* If we could, great. If not, do not go ahead with the IOR
5913 replacement, since PLUS appears in many special purpose
5914 address arithmetic instructions. */
5915 if (GET_CODE (temp
) != CLOBBER
5916 && (GET_CODE (temp
) != IOR
5917 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5918 || XEXP (temp
, 1) != XEXP (x
, 1))
5919 && (XEXP (temp
, 0) != XEXP (x
, 1)
5920 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5926 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5927 (and <foo> (const_int pow2-1)) */
5928 if (GET_CODE (XEXP (x
, 1)) == AND
5929 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5930 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5931 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5932 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5933 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5937 /* If we have (mult (plus A B) C), apply the distributive law and then
5938 the inverse distributive law to see if things simplify. This
5939 occurs mostly in addresses, often when unrolling loops. */
5941 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5943 rtx result
= distribute_and_simplify_rtx (x
, 0);
5948 /* Try simplify a*(b/c) as (a*b)/c. */
5949 if (FLOAT_MODE_P (mode
) && flag_associative_math
5950 && GET_CODE (XEXP (x
, 0)) == DIV
)
5952 rtx tem
= simplify_binary_operation (MULT
, mode
,
5953 XEXP (XEXP (x
, 0), 0),
5956 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5961 /* If this is a divide by a power of two, treat it as a shift if
5962 its first operand is a shift. */
5963 if (CONST_INT_P (XEXP (x
, 1))
5964 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5965 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5966 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5967 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5968 || GET_CODE (XEXP (x
, 0)) == ROTATE
5969 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5970 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5974 case GT
: case GTU
: case GE
: case GEU
:
5975 case LT
: case LTU
: case LE
: case LEU
:
5976 case UNEQ
: case LTGT
:
5977 case UNGT
: case UNGE
:
5978 case UNLT
: case UNLE
:
5979 case UNORDERED
: case ORDERED
:
5980 /* If the first operand is a condition code, we can't do anything
5982 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5983 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5984 && ! CC0_P (XEXP (x
, 0))))
5986 rtx op0
= XEXP (x
, 0);
5987 rtx op1
= XEXP (x
, 1);
5988 enum rtx_code new_code
;
5990 if (GET_CODE (op0
) == COMPARE
)
5991 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5993 /* Simplify our comparison, if possible. */
5994 new_code
= simplify_comparison (code
, &op0
, &op1
);
5996 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5997 if only the low-order bit is possibly nonzero in X (such as when
5998 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5999 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6000 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6003 Remove any ZERO_EXTRACT we made when thinking this was a
6004 comparison. It may now be simpler to use, e.g., an AND. If a
6005 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6006 the call to make_compound_operation in the SET case.
6008 Don't apply these optimizations if the caller would
6009 prefer a comparison rather than a value.
6010 E.g., for the condition in an IF_THEN_ELSE most targets need
6011 an explicit comparison. */
6016 else if (STORE_FLAG_VALUE
== 1
6017 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6018 && op1
== const0_rtx
6019 && mode
== GET_MODE (op0
)
6020 && nonzero_bits (op0
, mode
) == 1)
6021 return gen_lowpart (mode
,
6022 expand_compound_operation (op0
));
6024 else if (STORE_FLAG_VALUE
== 1
6025 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6026 && op1
== const0_rtx
6027 && mode
== GET_MODE (op0
)
6028 && (num_sign_bit_copies (op0
, mode
)
6029 == GET_MODE_PRECISION (mode
)))
6031 op0
= expand_compound_operation (op0
);
6032 return simplify_gen_unary (NEG
, mode
,
6033 gen_lowpart (mode
, op0
),
6037 else if (STORE_FLAG_VALUE
== 1
6038 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6039 && op1
== const0_rtx
6040 && mode
== GET_MODE (op0
)
6041 && nonzero_bits (op0
, mode
) == 1)
6043 op0
= expand_compound_operation (op0
);
6044 return simplify_gen_binary (XOR
, mode
,
6045 gen_lowpart (mode
, op0
),
6049 else if (STORE_FLAG_VALUE
== 1
6050 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6051 && op1
== const0_rtx
6052 && mode
== GET_MODE (op0
)
6053 && (num_sign_bit_copies (op0
, mode
)
6054 == GET_MODE_PRECISION (mode
)))
6056 op0
= expand_compound_operation (op0
);
6057 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6060 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6065 else if (STORE_FLAG_VALUE
== -1
6066 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6067 && op1
== const0_rtx
6068 && mode
== GET_MODE (op0
)
6069 && (num_sign_bit_copies (op0
, mode
)
6070 == GET_MODE_PRECISION (mode
)))
6071 return gen_lowpart (mode
,
6072 expand_compound_operation (op0
));
6074 else if (STORE_FLAG_VALUE
== -1
6075 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6076 && op1
== const0_rtx
6077 && mode
== GET_MODE (op0
)
6078 && nonzero_bits (op0
, mode
) == 1)
6080 op0
= expand_compound_operation (op0
);
6081 return simplify_gen_unary (NEG
, mode
,
6082 gen_lowpart (mode
, op0
),
6086 else if (STORE_FLAG_VALUE
== -1
6087 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6088 && op1
== const0_rtx
6089 && mode
== GET_MODE (op0
)
6090 && (num_sign_bit_copies (op0
, mode
)
6091 == GET_MODE_PRECISION (mode
)))
6093 op0
= expand_compound_operation (op0
);
6094 return simplify_gen_unary (NOT
, mode
,
6095 gen_lowpart (mode
, op0
),
6099 /* If X is 0/1, (eq X 0) is X-1. */
6100 else if (STORE_FLAG_VALUE
== -1
6101 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6102 && op1
== const0_rtx
6103 && mode
== GET_MODE (op0
)
6104 && nonzero_bits (op0
, mode
) == 1)
6106 op0
= expand_compound_operation (op0
);
6107 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6110 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6111 one bit that might be nonzero, we can convert (ne x 0) to
6112 (ashift x c) where C puts the bit in the sign bit. Remove any
6113 AND with STORE_FLAG_VALUE when we are done, since we are only
6114 going to test the sign bit. */
6115 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6116 && HWI_COMPUTABLE_MODE_P (mode
)
6117 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6118 && op1
== const0_rtx
6119 && mode
== GET_MODE (op0
)
6120 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6122 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6123 expand_compound_operation (op0
),
6124 GET_MODE_PRECISION (mode
) - 1 - i
);
6125 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6131 /* If the code changed, return a whole new comparison.
6132 We also need to avoid using SUBST in cases where
6133 simplify_comparison has widened a comparison with a CONST_INT,
6134 since in that case the wider CONST_INT may fail the sanity
6135 checks in do_SUBST. */
6136 if (new_code
!= code
6137 || (CONST_INT_P (op1
)
6138 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6139 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6140 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6142 /* Otherwise, keep this operation, but maybe change its operands.
6143 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6144 SUBST (XEXP (x
, 0), op0
);
6145 SUBST (XEXP (x
, 1), op1
);
6150 return simplify_if_then_else (x
);
6156 /* If we are processing SET_DEST, we are done. */
6160 return expand_compound_operation (x
);
6163 return simplify_set (x
);
6167 return simplify_logical (x
);
6174 /* If this is a shift by a constant amount, simplify it. */
6175 if (CONST_INT_P (XEXP (x
, 1)))
6176 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6177 INTVAL (XEXP (x
, 1)));
6179 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6181 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6182 ((unsigned HOST_WIDE_INT
) 1
6183 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6195 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6198 simplify_if_then_else (rtx x
)
6200 machine_mode mode
= GET_MODE (x
);
6201 rtx cond
= XEXP (x
, 0);
6202 rtx true_rtx
= XEXP (x
, 1);
6203 rtx false_rtx
= XEXP (x
, 2);
6204 enum rtx_code true_code
= GET_CODE (cond
);
6205 int comparison_p
= COMPARISON_P (cond
);
6208 enum rtx_code false_code
;
6211 /* Simplify storing of the truth value. */
6212 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6213 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6214 XEXP (cond
, 0), XEXP (cond
, 1));
6216 /* Also when the truth value has to be reversed. */
6218 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6219 && (reversed
= reversed_comparison (cond
, mode
)))
6222 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6223 in it is being compared against certain values. Get the true and false
6224 comparisons and see if that says anything about the value of each arm. */
6227 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6229 && REG_P (XEXP (cond
, 0)))
6232 rtx from
= XEXP (cond
, 0);
6233 rtx true_val
= XEXP (cond
, 1);
6234 rtx false_val
= true_val
;
6237 /* If FALSE_CODE is EQ, swap the codes and arms. */
6239 if (false_code
== EQ
)
6241 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6242 std::swap (true_rtx
, false_rtx
);
6245 /* If we are comparing against zero and the expression being tested has
6246 only a single bit that might be nonzero, that is its value when it is
6247 not equal to zero. Similarly if it is known to be -1 or 0. */
6249 if (true_code
== EQ
&& true_val
== const0_rtx
6250 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6253 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6255 else if (true_code
== EQ
&& true_val
== const0_rtx
6256 && (num_sign_bit_copies (from
, GET_MODE (from
))
6257 == GET_MODE_PRECISION (GET_MODE (from
))))
6260 false_val
= constm1_rtx
;
6263 /* Now simplify an arm if we know the value of the register in the
6264 branch and it is used in the arm. Be careful due to the potential
6265 of locally-shared RTL. */
6267 if (reg_mentioned_p (from
, true_rtx
))
6268 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6270 pc_rtx
, pc_rtx
, 0, 0, 0);
6271 if (reg_mentioned_p (from
, false_rtx
))
6272 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6274 pc_rtx
, pc_rtx
, 0, 0, 0);
6276 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6277 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6279 true_rtx
= XEXP (x
, 1);
6280 false_rtx
= XEXP (x
, 2);
6281 true_code
= GET_CODE (cond
);
6284 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6285 reversed, do so to avoid needing two sets of patterns for
6286 subtract-and-branch insns. Similarly if we have a constant in the true
6287 arm, the false arm is the same as the first operand of the comparison, or
6288 the false arm is more complicated than the true arm. */
6291 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6292 && (true_rtx
== pc_rtx
6293 || (CONSTANT_P (true_rtx
)
6294 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6295 || true_rtx
== const0_rtx
6296 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6297 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6298 && !OBJECT_P (false_rtx
))
6299 || reg_mentioned_p (true_rtx
, false_rtx
)
6300 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6302 true_code
= reversed_comparison_code (cond
, NULL
);
6303 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6304 SUBST (XEXP (x
, 1), false_rtx
);
6305 SUBST (XEXP (x
, 2), true_rtx
);
6307 std::swap (true_rtx
, false_rtx
);
6310 /* It is possible that the conditional has been simplified out. */
6311 true_code
= GET_CODE (cond
);
6312 comparison_p
= COMPARISON_P (cond
);
6315 /* If the two arms are identical, we don't need the comparison. */
6317 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6320 /* Convert a == b ? b : a to "a". */
6321 if (true_code
== EQ
&& ! side_effects_p (cond
)
6322 && !HONOR_NANS (mode
)
6323 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6324 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6326 else if (true_code
== NE
&& ! side_effects_p (cond
)
6327 && !HONOR_NANS (mode
)
6328 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6329 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6332 /* Look for cases where we have (abs x) or (neg (abs X)). */
6334 if (GET_MODE_CLASS (mode
) == MODE_INT
6336 && XEXP (cond
, 1) == const0_rtx
6337 && GET_CODE (false_rtx
) == NEG
6338 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6339 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6340 && ! side_effects_p (true_rtx
))
6345 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6349 simplify_gen_unary (NEG
, mode
,
6350 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6356 /* Look for MIN or MAX. */
6358 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6360 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6361 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6362 && ! side_effects_p (cond
))
6367 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6370 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6373 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6376 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6381 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6382 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6383 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6384 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6385 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6386 neither 1 or -1, but it isn't worth checking for. */
6388 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6390 && GET_MODE_CLASS (mode
) == MODE_INT
6391 && ! side_effects_p (x
))
6393 rtx t
= make_compound_operation (true_rtx
, SET
);
6394 rtx f
= make_compound_operation (false_rtx
, SET
);
6395 rtx cond_op0
= XEXP (cond
, 0);
6396 rtx cond_op1
= XEXP (cond
, 1);
6397 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6398 machine_mode m
= mode
;
6399 rtx z
= 0, c1
= NULL_RTX
;
6401 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6402 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6403 || GET_CODE (t
) == ASHIFT
6404 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6405 && rtx_equal_p (XEXP (t
, 0), f
))
6406 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6408 /* If an identity-zero op is commutative, check whether there
6409 would be a match if we swapped the operands. */
6410 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6411 || GET_CODE (t
) == XOR
)
6412 && rtx_equal_p (XEXP (t
, 1), f
))
6413 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6414 else if (GET_CODE (t
) == SIGN_EXTEND
6415 && (GET_CODE (XEXP (t
, 0)) == PLUS
6416 || GET_CODE (XEXP (t
, 0)) == MINUS
6417 || GET_CODE (XEXP (t
, 0)) == IOR
6418 || GET_CODE (XEXP (t
, 0)) == XOR
6419 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6420 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6421 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6422 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6423 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6424 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6425 && (num_sign_bit_copies (f
, GET_MODE (f
))
6427 (GET_MODE_PRECISION (mode
)
6428 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6430 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6431 extend_op
= SIGN_EXTEND
;
6432 m
= GET_MODE (XEXP (t
, 0));
6434 else if (GET_CODE (t
) == SIGN_EXTEND
6435 && (GET_CODE (XEXP (t
, 0)) == PLUS
6436 || GET_CODE (XEXP (t
, 0)) == IOR
6437 || GET_CODE (XEXP (t
, 0)) == XOR
)
6438 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6439 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6440 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6441 && (num_sign_bit_copies (f
, GET_MODE (f
))
6443 (GET_MODE_PRECISION (mode
)
6444 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6446 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6447 extend_op
= SIGN_EXTEND
;
6448 m
= GET_MODE (XEXP (t
, 0));
6450 else if (GET_CODE (t
) == ZERO_EXTEND
6451 && (GET_CODE (XEXP (t
, 0)) == PLUS
6452 || GET_CODE (XEXP (t
, 0)) == MINUS
6453 || GET_CODE (XEXP (t
, 0)) == IOR
6454 || GET_CODE (XEXP (t
, 0)) == XOR
6455 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6456 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6457 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6458 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6459 && HWI_COMPUTABLE_MODE_P (mode
)
6460 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6461 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6462 && ((nonzero_bits (f
, GET_MODE (f
))
6463 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6466 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6467 extend_op
= ZERO_EXTEND
;
6468 m
= GET_MODE (XEXP (t
, 0));
6470 else if (GET_CODE (t
) == ZERO_EXTEND
6471 && (GET_CODE (XEXP (t
, 0)) == PLUS
6472 || GET_CODE (XEXP (t
, 0)) == IOR
6473 || GET_CODE (XEXP (t
, 0)) == XOR
)
6474 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6475 && HWI_COMPUTABLE_MODE_P (mode
)
6476 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6477 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6478 && ((nonzero_bits (f
, GET_MODE (f
))
6479 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6482 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6483 extend_op
= ZERO_EXTEND
;
6484 m
= GET_MODE (XEXP (t
, 0));
6489 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6490 cond_op0
, cond_op1
),
6491 pc_rtx
, pc_rtx
, 0, 0, 0);
6492 temp
= simplify_gen_binary (MULT
, m
, temp
,
6493 simplify_gen_binary (MULT
, m
, c1
,
6495 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6496 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6498 if (extend_op
!= UNKNOWN
)
6499 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6505 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6506 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6507 negation of a single bit, we can convert this operation to a shift. We
6508 can actually do this more generally, but it doesn't seem worth it. */
6510 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6511 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6512 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6513 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6514 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6515 == GET_MODE_PRECISION (mode
))
6516 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6518 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6519 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6521 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6522 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6523 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6524 && GET_MODE (XEXP (cond
, 0)) == mode
6525 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6526 == nonzero_bits (XEXP (cond
, 0), mode
)
6527 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6528 return XEXP (cond
, 0);
6533 /* Simplify X, a SET expression. Return the new expression. */
6536 simplify_set (rtx x
)
6538 rtx src
= SET_SRC (x
);
6539 rtx dest
= SET_DEST (x
);
6541 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6542 rtx_insn
*other_insn
;
6545 /* (set (pc) (return)) gets written as (return). */
6546 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6549 /* Now that we know for sure which bits of SRC we are using, see if we can
6550 simplify the expression for the object knowing that we only need the
6553 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6555 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6556 SUBST (SET_SRC (x
), src
);
6559 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6560 the comparison result and try to simplify it unless we already have used
6561 undobuf.other_insn. */
6562 if ((GET_MODE_CLASS (mode
) == MODE_CC
6563 || GET_CODE (src
) == COMPARE
6565 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6566 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6567 && COMPARISON_P (*cc_use
)
6568 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6570 enum rtx_code old_code
= GET_CODE (*cc_use
);
6571 enum rtx_code new_code
;
6573 int other_changed
= 0;
6574 rtx inner_compare
= NULL_RTX
;
6575 machine_mode compare_mode
= GET_MODE (dest
);
6577 if (GET_CODE (src
) == COMPARE
)
6579 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6580 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6582 inner_compare
= op0
;
6583 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6587 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6589 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6592 new_code
= old_code
;
6593 else if (!CONSTANT_P (tmp
))
6595 new_code
= GET_CODE (tmp
);
6596 op0
= XEXP (tmp
, 0);
6597 op1
= XEXP (tmp
, 1);
6601 rtx pat
= PATTERN (other_insn
);
6602 undobuf
.other_insn
= other_insn
;
6603 SUBST (*cc_use
, tmp
);
6605 /* Attempt to simplify CC user. */
6606 if (GET_CODE (pat
) == SET
)
6608 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6609 if (new_rtx
!= NULL_RTX
)
6610 SUBST (SET_SRC (pat
), new_rtx
);
6613 /* Convert X into a no-op move. */
6614 SUBST (SET_DEST (x
), pc_rtx
);
6615 SUBST (SET_SRC (x
), pc_rtx
);
6619 /* Simplify our comparison, if possible. */
6620 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6622 #ifdef SELECT_CC_MODE
6623 /* If this machine has CC modes other than CCmode, check to see if we
6624 need to use a different CC mode here. */
6625 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6626 compare_mode
= GET_MODE (op0
);
6627 else if (inner_compare
6628 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6629 && new_code
== old_code
6630 && op0
== XEXP (inner_compare
, 0)
6631 && op1
== XEXP (inner_compare
, 1))
6632 compare_mode
= GET_MODE (inner_compare
);
6634 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6636 /* If the mode changed, we have to change SET_DEST, the mode in the
6637 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6638 a hard register, just build new versions with the proper mode. If it
6639 is a pseudo, we lose unless it is only time we set the pseudo, in
6640 which case we can safely change its mode. */
6641 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6643 if (can_change_dest_mode (dest
, 0, compare_mode
))
6645 unsigned int regno
= REGNO (dest
);
6648 if (regno
< FIRST_PSEUDO_REGISTER
)
6649 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6652 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6653 new_dest
= regno_reg_rtx
[regno
];
6656 SUBST (SET_DEST (x
), new_dest
);
6657 SUBST (XEXP (*cc_use
, 0), new_dest
);
6663 #endif /* SELECT_CC_MODE */
6665 /* If the code changed, we have to build a new comparison in
6666 undobuf.other_insn. */
6667 if (new_code
!= old_code
)
6669 int other_changed_previously
= other_changed
;
6670 unsigned HOST_WIDE_INT mask
;
6671 rtx old_cc_use
= *cc_use
;
6673 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6677 /* If the only change we made was to change an EQ into an NE or
6678 vice versa, OP0 has only one bit that might be nonzero, and OP1
6679 is zero, check if changing the user of the condition code will
6680 produce a valid insn. If it won't, we can keep the original code
6681 in that insn by surrounding our operation with an XOR. */
6683 if (((old_code
== NE
&& new_code
== EQ
)
6684 || (old_code
== EQ
&& new_code
== NE
))
6685 && ! other_changed_previously
&& op1
== const0_rtx
6686 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6687 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6689 rtx pat
= PATTERN (other_insn
), note
= 0;
6691 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6692 && ! check_asm_operands (pat
)))
6694 *cc_use
= old_cc_use
;
6697 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6705 undobuf
.other_insn
= other_insn
;
6707 /* Don't generate a compare of a CC with 0, just use that CC. */
6708 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6710 SUBST (SET_SRC (x
), op0
);
6713 /* Otherwise, if we didn't previously have the same COMPARE we
6714 want, create it from scratch. */
6715 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6716 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6718 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6724 /* Get SET_SRC in a form where we have placed back any
6725 compound expressions. Then do the checks below. */
6726 src
= make_compound_operation (src
, SET
);
6727 SUBST (SET_SRC (x
), src
);
6730 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6731 and X being a REG or (subreg (reg)), we may be able to convert this to
6732 (set (subreg:m2 x) (op)).
6734 We can always do this if M1 is narrower than M2 because that means that
6735 we only care about the low bits of the result.
6737 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6738 perform a narrower operation than requested since the high-order bits will
6739 be undefined. On machine where it is defined, this transformation is safe
6740 as long as M1 and M2 have the same number of words. */
6742 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6743 && !OBJECT_P (SUBREG_REG (src
))
6744 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6746 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6747 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6748 #ifndef WORD_REGISTER_OPERATIONS
6749 && (GET_MODE_SIZE (GET_MODE (src
))
6750 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6752 #ifdef CANNOT_CHANGE_MODE_CLASS
6753 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6754 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6755 GET_MODE (SUBREG_REG (src
)),
6759 || (GET_CODE (dest
) == SUBREG
6760 && REG_P (SUBREG_REG (dest
)))))
6762 SUBST (SET_DEST (x
),
6763 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6765 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6767 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6770 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6773 && GET_CODE (src
) == SUBREG
6774 && subreg_lowpart_p (src
)
6775 && (GET_MODE_PRECISION (GET_MODE (src
))
6776 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6778 rtx inner
= SUBREG_REG (src
);
6779 machine_mode inner_mode
= GET_MODE (inner
);
6781 /* Here we make sure that we don't have a sign bit on. */
6782 if (val_signbit_known_clear_p (GET_MODE (src
),
6783 nonzero_bits (inner
, inner_mode
)))
6785 SUBST (SET_SRC (x
), inner
);
6790 #ifdef LOAD_EXTEND_OP
6791 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6792 would require a paradoxical subreg. Replace the subreg with a
6793 zero_extend to avoid the reload that would otherwise be required. */
6795 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6796 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6797 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6798 && SUBREG_BYTE (src
) == 0
6799 && paradoxical_subreg_p (src
)
6800 && MEM_P (SUBREG_REG (src
)))
6803 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6804 GET_MODE (src
), SUBREG_REG (src
)));
6810 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6811 are comparing an item known to be 0 or -1 against 0, use a logical
6812 operation instead. Check for one of the arms being an IOR of the other
6813 arm with some value. We compute three terms to be IOR'ed together. In
6814 practice, at most two will be nonzero. Then we do the IOR's. */
6816 if (GET_CODE (dest
) != PC
6817 && GET_CODE (src
) == IF_THEN_ELSE
6818 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6819 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6820 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6821 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6822 && (!HAVE_conditional_move
6823 || ! can_conditionally_move_p (GET_MODE (src
)))
6824 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6825 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6826 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6827 && ! side_effects_p (src
))
6829 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6830 ? XEXP (src
, 1) : XEXP (src
, 2));
6831 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6832 ? XEXP (src
, 2) : XEXP (src
, 1));
6833 rtx term1
= const0_rtx
, term2
, term3
;
6835 if (GET_CODE (true_rtx
) == IOR
6836 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6837 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6838 else if (GET_CODE (true_rtx
) == IOR
6839 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6840 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6841 else if (GET_CODE (false_rtx
) == IOR
6842 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6843 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6844 else if (GET_CODE (false_rtx
) == IOR
6845 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6846 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6848 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6849 XEXP (XEXP (src
, 0), 0), true_rtx
);
6850 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6851 simplify_gen_unary (NOT
, GET_MODE (src
),
6852 XEXP (XEXP (src
, 0), 0),
6857 simplify_gen_binary (IOR
, GET_MODE (src
),
6858 simplify_gen_binary (IOR
, GET_MODE (src
),
6865 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6866 whole thing fail. */
6867 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6869 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6872 /* Convert this into a field assignment operation, if possible. */
6873 return make_field_assignment (x
);
6876 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6880 simplify_logical (rtx x
)
6882 machine_mode mode
= GET_MODE (x
);
6883 rtx op0
= XEXP (x
, 0);
6884 rtx op1
= XEXP (x
, 1);
6886 switch (GET_CODE (x
))
6889 /* We can call simplify_and_const_int only if we don't lose
6890 any (sign) bits when converting INTVAL (op1) to
6891 "unsigned HOST_WIDE_INT". */
6892 if (CONST_INT_P (op1
)
6893 && (HWI_COMPUTABLE_MODE_P (mode
)
6894 || INTVAL (op1
) > 0))
6896 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6897 if (GET_CODE (x
) != AND
)
6904 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6905 apply the distributive law and then the inverse distributive
6906 law to see if things simplify. */
6907 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6909 rtx result
= distribute_and_simplify_rtx (x
, 0);
6913 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6915 rtx result
= distribute_and_simplify_rtx (x
, 1);
6922 /* If we have (ior (and A B) C), apply the distributive law and then
6923 the inverse distributive law to see if things simplify. */
6925 if (GET_CODE (op0
) == AND
)
6927 rtx result
= distribute_and_simplify_rtx (x
, 0);
6932 if (GET_CODE (op1
) == AND
)
6934 rtx result
= distribute_and_simplify_rtx (x
, 1);
6947 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6948 operations" because they can be replaced with two more basic operations.
6949 ZERO_EXTEND is also considered "compound" because it can be replaced with
6950 an AND operation, which is simpler, though only one operation.
6952 The function expand_compound_operation is called with an rtx expression
6953 and will convert it to the appropriate shifts and AND operations,
6954 simplifying at each stage.
6956 The function make_compound_operation is called to convert an expression
6957 consisting of shifts and ANDs into the equivalent compound expression.
6958 It is the inverse of this function, loosely speaking. */
6961 expand_compound_operation (rtx x
)
6963 unsigned HOST_WIDE_INT pos
= 0, len
;
6965 unsigned int modewidth
;
6968 switch (GET_CODE (x
))
6973 /* We can't necessarily use a const_int for a multiword mode;
6974 it depends on implicitly extending the value.
6975 Since we don't know the right way to extend it,
6976 we can't tell whether the implicit way is right.
6978 Even for a mode that is no wider than a const_int,
6979 we can't win, because we need to sign extend one of its bits through
6980 the rest of it, and we don't know which bit. */
6981 if (CONST_INT_P (XEXP (x
, 0)))
6984 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6985 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6986 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6987 reloaded. If not for that, MEM's would very rarely be safe.
6989 Reject MODEs bigger than a word, because we might not be able
6990 to reference a two-register group starting with an arbitrary register
6991 (and currently gen_lowpart might crash for a SUBREG). */
6993 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6996 /* Reject MODEs that aren't scalar integers because turning vector
6997 or complex modes into shifts causes problems. */
6999 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7002 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7003 /* If the inner object has VOIDmode (the only way this can happen
7004 is if it is an ASM_OPERANDS), we can't do anything since we don't
7005 know how much masking to do. */
7014 /* ... fall through ... */
7017 /* If the operand is a CLOBBER, just return it. */
7018 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7021 if (!CONST_INT_P (XEXP (x
, 1))
7022 || !CONST_INT_P (XEXP (x
, 2))
7023 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7026 /* Reject MODEs that aren't scalar integers because turning vector
7027 or complex modes into shifts causes problems. */
7029 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7032 len
= INTVAL (XEXP (x
, 1));
7033 pos
= INTVAL (XEXP (x
, 2));
7035 /* This should stay within the object being extracted, fail otherwise. */
7036 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7039 if (BITS_BIG_ENDIAN
)
7040 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7047 /* Convert sign extension to zero extension, if we know that the high
7048 bit is not set, as this is easier to optimize. It will be converted
7049 back to cheaper alternative in make_extraction. */
7050 if (GET_CODE (x
) == SIGN_EXTEND
7051 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7052 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7053 & ~(((unsigned HOST_WIDE_INT
)
7054 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7058 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
7059 rtx temp2
= expand_compound_operation (temp
);
7061 /* Make sure this is a profitable operation. */
7062 if (set_src_cost (x
, optimize_this_for_speed_p
)
7063 > set_src_cost (temp2
, optimize_this_for_speed_p
))
7065 else if (set_src_cost (x
, optimize_this_for_speed_p
)
7066 > set_src_cost (temp
, optimize_this_for_speed_p
))
7072 /* We can optimize some special cases of ZERO_EXTEND. */
7073 if (GET_CODE (x
) == ZERO_EXTEND
)
7075 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7076 know that the last value didn't have any inappropriate bits
7078 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7079 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7080 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7081 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7082 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7083 return XEXP (XEXP (x
, 0), 0);
7085 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7086 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7087 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7088 && subreg_lowpart_p (XEXP (x
, 0))
7089 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7090 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7091 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7092 return SUBREG_REG (XEXP (x
, 0));
7094 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7095 is a comparison and STORE_FLAG_VALUE permits. This is like
7096 the first case, but it works even when GET_MODE (x) is larger
7097 than HOST_WIDE_INT. */
7098 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7099 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7100 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7101 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7102 <= HOST_BITS_PER_WIDE_INT
)
7103 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7104 return XEXP (XEXP (x
, 0), 0);
7106 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7107 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7108 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7109 && subreg_lowpart_p (XEXP (x
, 0))
7110 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7111 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7112 <= HOST_BITS_PER_WIDE_INT
)
7113 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7114 return SUBREG_REG (XEXP (x
, 0));
7118 /* If we reach here, we want to return a pair of shifts. The inner
7119 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7120 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7121 logical depending on the value of UNSIGNEDP.
7123 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7124 converted into an AND of a shift.
7126 We must check for the case where the left shift would have a negative
7127 count. This can happen in a case like (x >> 31) & 255 on machines
7128 that can't shift by a constant. On those machines, we would first
7129 combine the shift with the AND to produce a variable-position
7130 extraction. Then the constant of 31 would be substituted in
7131 to produce such a position. */
7133 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7134 if (modewidth
>= pos
+ len
)
7136 machine_mode mode
= GET_MODE (x
);
7137 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7138 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7140 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7141 tem
, modewidth
- pos
- len
);
7142 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7143 mode
, tem
, modewidth
- len
);
7145 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7146 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7147 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7150 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7152 /* Any other cases we can't handle. */
7155 /* If we couldn't do this for some reason, return the original
7157 if (GET_CODE (tem
) == CLOBBER
)
7163 /* X is a SET which contains an assignment of one object into
7164 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7165 or certain SUBREGS). If possible, convert it into a series of
7168 We half-heartedly support variable positions, but do not at all
7169 support variable lengths. */
7172 expand_field_assignment (const_rtx x
)
7175 rtx pos
; /* Always counts from low bit. */
7177 rtx mask
, cleared
, masked
;
7178 machine_mode compute_mode
;
7180 /* Loop until we find something we can't simplify. */
7183 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7184 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7186 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7187 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7188 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7190 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7191 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7193 inner
= XEXP (SET_DEST (x
), 0);
7194 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7195 pos
= XEXP (SET_DEST (x
), 2);
7197 /* A constant position should stay within the width of INNER. */
7198 if (CONST_INT_P (pos
)
7199 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7202 if (BITS_BIG_ENDIAN
)
7204 if (CONST_INT_P (pos
))
7205 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7207 else if (GET_CODE (pos
) == MINUS
7208 && CONST_INT_P (XEXP (pos
, 1))
7209 && (INTVAL (XEXP (pos
, 1))
7210 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7211 /* If position is ADJUST - X, new position is X. */
7212 pos
= XEXP (pos
, 0);
7215 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7216 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7217 gen_int_mode (prec
- len
,
7224 /* A SUBREG between two modes that occupy the same numbers of words
7225 can be done by moving the SUBREG to the source. */
7226 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7227 /* We need SUBREGs to compute nonzero_bits properly. */
7228 && nonzero_sign_valid
7229 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7230 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7231 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7232 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7234 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7236 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7243 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7244 inner
= SUBREG_REG (inner
);
7246 compute_mode
= GET_MODE (inner
);
7248 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7249 if (! SCALAR_INT_MODE_P (compute_mode
))
7253 /* Don't do anything for vector or complex integral types. */
7254 if (! FLOAT_MODE_P (compute_mode
))
7257 /* Try to find an integral mode to pun with. */
7258 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7259 if (imode
== BLKmode
)
7262 compute_mode
= imode
;
7263 inner
= gen_lowpart (imode
, inner
);
7266 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7267 if (len
>= HOST_BITS_PER_WIDE_INT
)
7270 /* Now compute the equivalent expression. Make a copy of INNER
7271 for the SET_DEST in case it is a MEM into which we will substitute;
7272 we don't want shared RTL in that case. */
7273 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7275 cleared
= simplify_gen_binary (AND
, compute_mode
,
7276 simplify_gen_unary (NOT
, compute_mode
,
7277 simplify_gen_binary (ASHIFT
,
7282 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7283 simplify_gen_binary (
7285 gen_lowpart (compute_mode
, SET_SRC (x
)),
7289 x
= gen_rtx_SET (copy_rtx (inner
),
7290 simplify_gen_binary (IOR
, compute_mode
,
7297 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7298 it is an RTX that represents the (variable) starting position; otherwise,
7299 POS is the (constant) starting bit position. Both are counted from the LSB.
7301 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7303 IN_DEST is nonzero if this is a reference in the destination of a SET.
7304 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7305 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7308 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7309 ZERO_EXTRACT should be built even for bits starting at bit 0.
7311 MODE is the desired mode of the result (if IN_DEST == 0).
7313 The result is an RTX for the extraction or NULL_RTX if the target
7317 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7318 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7319 int in_dest
, int in_compare
)
7321 /* This mode describes the size of the storage area
7322 to fetch the overall value from. Within that, we
7323 ignore the POS lowest bits, etc. */
7324 machine_mode is_mode
= GET_MODE (inner
);
7325 machine_mode inner_mode
;
7326 machine_mode wanted_inner_mode
;
7327 machine_mode wanted_inner_reg_mode
= word_mode
;
7328 machine_mode pos_mode
= word_mode
;
7329 machine_mode extraction_mode
= word_mode
;
7330 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7332 rtx orig_pos_rtx
= pos_rtx
;
7333 HOST_WIDE_INT orig_pos
;
7335 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7336 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7338 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7340 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7341 consider just the QI as the memory to extract from.
7342 The subreg adds or removes high bits; its mode is
7343 irrelevant to the meaning of this extraction,
7344 since POS and LEN count from the lsb. */
7345 if (MEM_P (SUBREG_REG (inner
)))
7346 is_mode
= GET_MODE (SUBREG_REG (inner
));
7347 inner
= SUBREG_REG (inner
);
7349 else if (GET_CODE (inner
) == ASHIFT
7350 && CONST_INT_P (XEXP (inner
, 1))
7351 && pos_rtx
== 0 && pos
== 0
7352 && len
> UINTVAL (XEXP (inner
, 1)))
7354 /* We're extracting the least significant bits of an rtx
7355 (ashift X (const_int C)), where LEN > C. Extract the
7356 least significant (LEN - C) bits of X, giving an rtx
7357 whose mode is MODE, then shift it left C times. */
7358 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7359 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7360 unsignedp
, in_dest
, in_compare
);
7362 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7364 else if (GET_CODE (inner
) == TRUNCATE
)
7365 inner
= XEXP (inner
, 0);
7367 inner_mode
= GET_MODE (inner
);
7369 /* See if this can be done without an extraction. We never can if the
7370 width of the field is not the same as that of some integer mode. For
7371 registers, we can only avoid the extraction if the position is at the
7372 low-order bit and this is either not in the destination or we have the
7373 appropriate STRICT_LOW_PART operation available.
7375 For MEM, we can avoid an extract if the field starts on an appropriate
7376 boundary and we can change the mode of the memory reference. */
7378 if (tmode
!= BLKmode
7379 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7381 && (inner_mode
== tmode
7383 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7384 || reg_truncated_to_mode (tmode
, inner
))
7387 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7388 || (MEM_P (inner
) && pos_rtx
== 0
7390 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7391 : BITS_PER_UNIT
)) == 0
7392 /* We can't do this if we are widening INNER_MODE (it
7393 may not be aligned, for one thing). */
7394 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7395 && (inner_mode
== tmode
7396 || (! mode_dependent_address_p (XEXP (inner
, 0),
7397 MEM_ADDR_SPACE (inner
))
7398 && ! MEM_VOLATILE_P (inner
))))))
7400 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7401 field. If the original and current mode are the same, we need not
7402 adjust the offset. Otherwise, we do if bytes big endian.
7404 If INNER is not a MEM, get a piece consisting of just the field
7405 of interest (in this case POS % BITS_PER_WORD must be 0). */
7409 HOST_WIDE_INT offset
;
7411 /* POS counts from lsb, but make OFFSET count in memory order. */
7412 if (BYTES_BIG_ENDIAN
)
7413 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7415 offset
= pos
/ BITS_PER_UNIT
;
7417 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7419 else if (REG_P (inner
))
7421 if (tmode
!= inner_mode
)
7423 /* We can't call gen_lowpart in a DEST since we
7424 always want a SUBREG (see below) and it would sometimes
7425 return a new hard register. */
7428 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7430 if (WORDS_BIG_ENDIAN
7431 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7432 final_word
= ((GET_MODE_SIZE (inner_mode
)
7433 - GET_MODE_SIZE (tmode
))
7434 / UNITS_PER_WORD
) - final_word
;
7436 final_word
*= UNITS_PER_WORD
;
7437 if (BYTES_BIG_ENDIAN
&&
7438 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7439 final_word
+= (GET_MODE_SIZE (inner_mode
)
7440 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7442 /* Avoid creating invalid subregs, for example when
7443 simplifying (x>>32)&255. */
7444 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7447 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7450 new_rtx
= gen_lowpart (tmode
, inner
);
7456 new_rtx
= force_to_mode (inner
, tmode
,
7457 len
>= HOST_BITS_PER_WIDE_INT
7458 ? ~(unsigned HOST_WIDE_INT
) 0
7459 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7462 /* If this extraction is going into the destination of a SET,
7463 make a STRICT_LOW_PART unless we made a MEM. */
7466 return (MEM_P (new_rtx
) ? new_rtx
7467 : (GET_CODE (new_rtx
) != SUBREG
7468 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7469 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7474 if (CONST_SCALAR_INT_P (new_rtx
))
7475 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7476 mode
, new_rtx
, tmode
);
7478 /* If we know that no extraneous bits are set, and that the high
7479 bit is not set, convert the extraction to the cheaper of
7480 sign and zero extension, that are equivalent in these cases. */
7481 if (flag_expensive_optimizations
7482 && (HWI_COMPUTABLE_MODE_P (tmode
)
7483 && ((nonzero_bits (new_rtx
, tmode
)
7484 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7487 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7488 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7490 /* Prefer ZERO_EXTENSION, since it gives more information to
7492 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7493 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7498 /* Otherwise, sign- or zero-extend unless we already are in the
7501 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7505 /* Unless this is a COMPARE or we have a funny memory reference,
7506 don't do anything with zero-extending field extracts starting at
7507 the low-order bit since they are simple AND operations. */
7508 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7509 && ! in_compare
&& unsignedp
)
7512 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7513 if the position is not a constant and the length is not 1. In all
7514 other cases, we would only be going outside our object in cases when
7515 an original shift would have been undefined. */
7517 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7518 || (pos_rtx
!= 0 && len
!= 1)))
7521 enum extraction_pattern pattern
= (in_dest
? EP_insv
7522 : unsignedp
? EP_extzv
: EP_extv
);
7524 /* If INNER is not from memory, we want it to have the mode of a register
7525 extraction pattern's structure operand, or word_mode if there is no
7526 such pattern. The same applies to extraction_mode and pos_mode
7527 and their respective operands.
7529 For memory, assume that the desired extraction_mode and pos_mode
7530 are the same as for a register operation, since at present we don't
7531 have named patterns for aligned memory structures. */
7532 struct extraction_insn insn
;
7533 if (get_best_reg_extraction_insn (&insn
, pattern
,
7534 GET_MODE_BITSIZE (inner_mode
), mode
))
7536 wanted_inner_reg_mode
= insn
.struct_mode
;
7537 pos_mode
= insn
.pos_mode
;
7538 extraction_mode
= insn
.field_mode
;
7541 /* Never narrow an object, since that might not be safe. */
7543 if (mode
!= VOIDmode
7544 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7545 extraction_mode
= mode
;
7548 wanted_inner_mode
= wanted_inner_reg_mode
;
7551 /* Be careful not to go beyond the extracted object and maintain the
7552 natural alignment of the memory. */
7553 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7554 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7555 > GET_MODE_BITSIZE (wanted_inner_mode
))
7557 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7558 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7564 if (BITS_BIG_ENDIAN
)
7566 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7567 BITS_BIG_ENDIAN style. If position is constant, compute new
7568 position. Otherwise, build subtraction.
7569 Note that POS is relative to the mode of the original argument.
7570 If it's a MEM we need to recompute POS relative to that.
7571 However, if we're extracting from (or inserting into) a register,
7572 we want to recompute POS relative to wanted_inner_mode. */
7573 int width
= (MEM_P (inner
)
7574 ? GET_MODE_BITSIZE (is_mode
)
7575 : GET_MODE_BITSIZE (wanted_inner_mode
));
7578 pos
= width
- len
- pos
;
7581 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7582 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7584 /* POS may be less than 0 now, but we check for that below.
7585 Note that it can only be less than 0 if !MEM_P (inner). */
7588 /* If INNER has a wider mode, and this is a constant extraction, try to
7589 make it smaller and adjust the byte to point to the byte containing
7591 if (wanted_inner_mode
!= VOIDmode
7592 && inner_mode
!= wanted_inner_mode
7594 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7596 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7597 && ! MEM_VOLATILE_P (inner
))
7601 /* The computations below will be correct if the machine is big
7602 endian in both bits and bytes or little endian in bits and bytes.
7603 If it is mixed, we must adjust. */
7605 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7606 adjust OFFSET to compensate. */
7607 if (BYTES_BIG_ENDIAN
7608 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7609 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7611 /* We can now move to the desired byte. */
7612 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7613 * GET_MODE_SIZE (wanted_inner_mode
);
7614 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7616 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7617 && is_mode
!= wanted_inner_mode
)
7618 offset
= (GET_MODE_SIZE (is_mode
)
7619 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7621 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7624 /* If INNER is not memory, get it into the proper mode. If we are changing
7625 its mode, POS must be a constant and smaller than the size of the new
7627 else if (!MEM_P (inner
))
7629 /* On the LHS, don't create paradoxical subregs implicitely truncating
7630 the register unless TRULY_NOOP_TRUNCATION. */
7632 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7636 if (GET_MODE (inner
) != wanted_inner_mode
7638 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7644 inner
= force_to_mode (inner
, wanted_inner_mode
,
7646 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7647 ? ~(unsigned HOST_WIDE_INT
) 0
7648 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7653 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7654 have to zero extend. Otherwise, we can just use a SUBREG. */
7656 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7658 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7659 GET_MODE (pos_rtx
));
7661 /* If we know that no extraneous bits are set, and that the high
7662 bit is not set, convert extraction to cheaper one - either
7663 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7665 if (flag_expensive_optimizations
7666 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7667 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7668 & ~(((unsigned HOST_WIDE_INT
)
7669 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7673 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7674 GET_MODE (pos_rtx
));
7676 /* Prefer ZERO_EXTENSION, since it gives more information to
7678 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7679 < set_src_cost (temp
, optimize_this_for_speed_p
))
7685 /* Make POS_RTX unless we already have it and it is correct. If we don't
7686 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7688 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7689 pos_rtx
= orig_pos_rtx
;
7691 else if (pos_rtx
== 0)
7692 pos_rtx
= GEN_INT (pos
);
7694 /* Make the required operation. See if we can use existing rtx. */
7695 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7696 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7698 new_rtx
= gen_lowpart (mode
, new_rtx
);
7703 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7704 with any other operations in X. Return X without that shift if so. */
7707 extract_left_shift (rtx x
, int count
)
7709 enum rtx_code code
= GET_CODE (x
);
7710 machine_mode mode
= GET_MODE (x
);
7716 /* This is the shift itself. If it is wide enough, we will return
7717 either the value being shifted if the shift count is equal to
7718 COUNT or a shift for the difference. */
7719 if (CONST_INT_P (XEXP (x
, 1))
7720 && INTVAL (XEXP (x
, 1)) >= count
)
7721 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7722 INTVAL (XEXP (x
, 1)) - count
);
7726 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7727 return simplify_gen_unary (code
, mode
, tem
, mode
);
7731 case PLUS
: case IOR
: case XOR
: case AND
:
7732 /* If we can safely shift this constant and we find the inner shift,
7733 make a new operation. */
7734 if (CONST_INT_P (XEXP (x
, 1))
7735 && (UINTVAL (XEXP (x
, 1))
7736 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7737 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7739 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7740 return simplify_gen_binary (code
, mode
, tem
,
7741 gen_int_mode (val
, mode
));
7752 /* Look at the expression rooted at X. Look for expressions
7753 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7754 Form these expressions.
7756 Return the new rtx, usually just X.
7758 Also, for machines like the VAX that don't have logical shift insns,
7759 try to convert logical to arithmetic shift operations in cases where
7760 they are equivalent. This undoes the canonicalizations to logical
7761 shifts done elsewhere.
7763 We try, as much as possible, to re-use rtl expressions to save memory.
7765 IN_CODE says what kind of expression we are processing. Normally, it is
7766 SET. In a memory address it is MEM. When processing the arguments of
7767 a comparison or a COMPARE against zero, it is COMPARE. */
7770 make_compound_operation (rtx x
, enum rtx_code in_code
)
7772 enum rtx_code code
= GET_CODE (x
);
7773 machine_mode mode
= GET_MODE (x
);
7774 int mode_width
= GET_MODE_PRECISION (mode
);
7776 enum rtx_code next_code
;
7782 /* Select the code to be used in recursive calls. Once we are inside an
7783 address, we stay there. If we have a comparison, set to COMPARE,
7784 but once inside, go back to our default of SET. */
7786 next_code
= (code
== MEM
? MEM
7787 : ((code
== COMPARE
|| COMPARISON_P (x
))
7788 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7789 : in_code
== COMPARE
? SET
: in_code
);
7791 /* Process depending on the code of this operation. If NEW is set
7792 nonzero, it will be returned. */
7797 /* Convert shifts by constants into multiplications if inside
7799 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7800 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7801 && INTVAL (XEXP (x
, 1)) >= 0
7802 && SCALAR_INT_MODE_P (mode
))
7804 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7805 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7807 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7808 if (GET_CODE (new_rtx
) == NEG
)
7810 new_rtx
= XEXP (new_rtx
, 0);
7813 multval
= trunc_int_for_mode (multval
, mode
);
7814 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7821 lhs
= make_compound_operation (lhs
, next_code
);
7822 rhs
= make_compound_operation (rhs
, next_code
);
7823 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7824 && SCALAR_INT_MODE_P (mode
))
7826 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7828 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7830 else if (GET_CODE (lhs
) == MULT
7831 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7833 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7834 simplify_gen_unary (NEG
, mode
,
7837 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7841 SUBST (XEXP (x
, 0), lhs
);
7842 SUBST (XEXP (x
, 1), rhs
);
7845 x
= gen_lowpart (mode
, new_rtx
);
7851 lhs
= make_compound_operation (lhs
, next_code
);
7852 rhs
= make_compound_operation (rhs
, next_code
);
7853 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7854 && SCALAR_INT_MODE_P (mode
))
7856 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7858 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7860 else if (GET_CODE (rhs
) == MULT
7861 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7863 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7864 simplify_gen_unary (NEG
, mode
,
7867 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7871 SUBST (XEXP (x
, 0), lhs
);
7872 SUBST (XEXP (x
, 1), rhs
);
7875 return gen_lowpart (mode
, new_rtx
);
7878 /* If the second operand is not a constant, we can't do anything
7880 if (!CONST_INT_P (XEXP (x
, 1)))
7883 /* If the constant is a power of two minus one and the first operand
7884 is a logical right shift, make an extraction. */
7885 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7886 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7888 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7889 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7890 0, in_code
== COMPARE
);
7893 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7894 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7895 && subreg_lowpart_p (XEXP (x
, 0))
7896 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7897 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7899 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7901 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7902 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7903 0, in_code
== COMPARE
);
7905 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7906 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7907 || GET_CODE (XEXP (x
, 0)) == IOR
)
7908 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7909 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7910 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7912 /* Apply the distributive law, and then try to make extractions. */
7913 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7914 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7916 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7918 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7921 /* If we are have (and (rotate X C) M) and C is larger than the number
7922 of bits in M, this is an extraction. */
7924 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7925 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7926 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7927 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7929 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7930 new_rtx
= make_extraction (mode
, new_rtx
,
7931 (GET_MODE_PRECISION (mode
)
7932 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7933 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7936 /* On machines without logical shifts, if the operand of the AND is
7937 a logical shift and our mask turns off all the propagated sign
7938 bits, we can replace the logical shift with an arithmetic shift. */
7939 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7940 && !have_insn_for (LSHIFTRT
, mode
)
7941 && have_insn_for (ASHIFTRT
, mode
)
7942 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7943 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7944 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7945 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7947 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7949 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7950 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7952 gen_rtx_ASHIFTRT (mode
,
7953 make_compound_operation
7954 (XEXP (XEXP (x
, 0), 0), next_code
),
7955 XEXP (XEXP (x
, 0), 1)));
7958 /* If the constant is one less than a power of two, this might be
7959 representable by an extraction even if no shift is present.
7960 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7961 we are in a COMPARE. */
7962 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7963 new_rtx
= make_extraction (mode
,
7964 make_compound_operation (XEXP (x
, 0),
7966 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7968 /* If we are in a comparison and this is an AND with a power of two,
7969 convert this into the appropriate bit extract. */
7970 else if (in_code
== COMPARE
7971 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7972 new_rtx
= make_extraction (mode
,
7973 make_compound_operation (XEXP (x
, 0),
7975 i
, NULL_RTX
, 1, 1, 0, 1);
7980 /* If the sign bit is known to be zero, replace this with an
7981 arithmetic shift. */
7982 if (have_insn_for (ASHIFTRT
, mode
)
7983 && ! have_insn_for (LSHIFTRT
, mode
)
7984 && mode_width
<= HOST_BITS_PER_WIDE_INT
7985 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7987 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7988 make_compound_operation (XEXP (x
, 0),
7994 /* ... fall through ... */
8000 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8001 this is a SIGN_EXTRACT. */
8002 if (CONST_INT_P (rhs
)
8003 && GET_CODE (lhs
) == ASHIFT
8004 && CONST_INT_P (XEXP (lhs
, 1))
8005 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8006 && INTVAL (XEXP (lhs
, 1)) >= 0
8007 && INTVAL (rhs
) < mode_width
)
8009 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8010 new_rtx
= make_extraction (mode
, new_rtx
,
8011 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8012 NULL_RTX
, mode_width
- INTVAL (rhs
),
8013 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8017 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8018 If so, try to merge the shifts into a SIGN_EXTEND. We could
8019 also do this for some cases of SIGN_EXTRACT, but it doesn't
8020 seem worth the effort; the case checked for occurs on Alpha. */
8023 && ! (GET_CODE (lhs
) == SUBREG
8024 && (OBJECT_P (SUBREG_REG (lhs
))))
8025 && CONST_INT_P (rhs
)
8026 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8027 && INTVAL (rhs
) < mode_width
8028 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8029 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8030 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8031 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8036 /* Call ourselves recursively on the inner expression. If we are
8037 narrowing the object and it has a different RTL code from
8038 what it originally did, do this SUBREG as a force_to_mode. */
8040 rtx inner
= SUBREG_REG (x
), simplified
;
8041 enum rtx_code subreg_code
= in_code
;
8043 /* If in_code is COMPARE, it isn't always safe to pass it through
8044 to the recursive make_compound_operation call. */
8045 if (subreg_code
== COMPARE
8046 && (!subreg_lowpart_p (x
)
8047 || GET_CODE (inner
) == SUBREG
8048 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8049 is (const_int 0), rather than
8050 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8051 || (GET_CODE (inner
) == AND
8052 && CONST_INT_P (XEXP (inner
, 1))
8053 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8054 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8055 >= GET_MODE_BITSIZE (mode
))))
8058 tem
= make_compound_operation (inner
, subreg_code
);
8061 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8065 if (GET_CODE (tem
) != GET_CODE (inner
)
8066 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8067 && subreg_lowpart_p (x
))
8070 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
8072 /* If we have something other than a SUBREG, we might have
8073 done an expansion, so rerun ourselves. */
8074 if (GET_CODE (newer
) != SUBREG
)
8075 newer
= make_compound_operation (newer
, in_code
);
8077 /* force_to_mode can expand compounds. If it just re-expanded the
8078 compound, use gen_lowpart to convert to the desired mode. */
8079 if (rtx_equal_p (newer
, x
)
8080 /* Likewise if it re-expanded the compound only partially.
8081 This happens for SUBREG of ZERO_EXTRACT if they extract
8082 the same number of bits. */
8083 || (GET_CODE (newer
) == SUBREG
8084 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8085 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8086 && GET_CODE (inner
) == AND
8087 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8088 return gen_lowpart (GET_MODE (x
), tem
);
8104 x
= gen_lowpart (mode
, new_rtx
);
8105 code
= GET_CODE (x
);
8108 /* Now recursively process each operand of this operation. We need to
8109 handle ZERO_EXTEND specially so that we don't lose track of the
8111 if (GET_CODE (x
) == ZERO_EXTEND
)
8113 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8114 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8115 new_rtx
, GET_MODE (XEXP (x
, 0)));
8118 SUBST (XEXP (x
, 0), new_rtx
);
8122 fmt
= GET_RTX_FORMAT (code
);
8123 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8126 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8127 SUBST (XEXP (x
, i
), new_rtx
);
8129 else if (fmt
[i
] == 'E')
8130 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8132 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8133 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8137 /* If this is a commutative operation, the changes to the operands
8138 may have made it noncanonical. */
8139 if (COMMUTATIVE_ARITH_P (x
)
8140 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8143 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8144 SUBST (XEXP (x
, 1), tem
);
8150 /* Given M see if it is a value that would select a field of bits
8151 within an item, but not the entire word. Return -1 if not.
8152 Otherwise, return the starting position of the field, where 0 is the
8155 *PLEN is set to the length of the field. */
8158 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8160 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8161 int pos
= m
? ctz_hwi (m
) : -1;
8165 /* Now shift off the low-order zero bits and see if we have a
8166 power of two minus 1. */
8167 len
= exact_log2 ((m
>> pos
) + 1);
8176 /* If X refers to a register that equals REG in value, replace these
8177 references with REG. */
8179 canon_reg_for_combine (rtx x
, rtx reg
)
8186 enum rtx_code code
= GET_CODE (x
);
8187 switch (GET_RTX_CLASS (code
))
8190 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8191 if (op0
!= XEXP (x
, 0))
8192 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8197 case RTX_COMM_ARITH
:
8198 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8199 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8200 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8201 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8205 case RTX_COMM_COMPARE
:
8206 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8207 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8208 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8209 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8210 GET_MODE (op0
), op0
, op1
);
8214 case RTX_BITFIELD_OPS
:
8215 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8216 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8217 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8218 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8219 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8220 GET_MODE (op0
), op0
, op1
, op2
);
8225 if (rtx_equal_p (get_last_value (reg
), x
)
8226 || rtx_equal_p (reg
, get_last_value (x
)))
8235 fmt
= GET_RTX_FORMAT (code
);
8237 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8240 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8241 if (op
!= XEXP (x
, i
))
8251 else if (fmt
[i
] == 'E')
8254 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8256 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8257 if (op
!= XVECEXP (x
, i
, j
))
8264 XVECEXP (x
, i
, j
) = op
;
8275 /* Return X converted to MODE. If the value is already truncated to
8276 MODE we can just return a subreg even though in the general case we
8277 would need an explicit truncation. */
8280 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8282 if (!CONST_INT_P (x
)
8283 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8284 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8285 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8287 /* Bit-cast X into an integer mode. */
8288 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8289 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8290 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8294 return gen_lowpart (mode
, x
);
8297 /* See if X can be simplified knowing that we will only refer to it in
8298 MODE and will only refer to those bits that are nonzero in MASK.
8299 If other bits are being computed or if masking operations are done
8300 that select a superset of the bits in MASK, they can sometimes be
8303 Return a possibly simplified expression, but always convert X to
8304 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8306 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8307 are all off in X. This is used when X will be complemented, by either
8308 NOT, NEG, or XOR. */
8311 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8314 enum rtx_code code
= GET_CODE (x
);
8315 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8316 machine_mode op_mode
;
8317 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8320 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8321 code below will do the wrong thing since the mode of such an
8322 expression is VOIDmode.
8324 Also do nothing if X is a CLOBBER; this can happen if X was
8325 the return value from a call to gen_lowpart. */
8326 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8329 /* We want to perform the operation in its present mode unless we know
8330 that the operation is valid in MODE, in which case we do the operation
8332 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8333 && have_insn_for (code
, mode
))
8334 ? mode
: GET_MODE (x
));
8336 /* It is not valid to do a right-shift in a narrower mode
8337 than the one it came in with. */
8338 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8339 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8340 op_mode
= GET_MODE (x
);
8342 /* Truncate MASK to fit OP_MODE. */
8344 mask
&= GET_MODE_MASK (op_mode
);
8346 /* When we have an arithmetic operation, or a shift whose count we
8347 do not know, we need to assume that all bits up to the highest-order
8348 bit in MASK will be needed. This is how we form such a mask. */
8349 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8350 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8352 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8355 /* Determine what bits of X are guaranteed to be (non)zero. */
8356 nonzero
= nonzero_bits (x
, mode
);
8358 /* If none of the bits in X are needed, return a zero. */
8359 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8362 /* If X is a CONST_INT, return a new one. Do this here since the
8363 test below will fail. */
8364 if (CONST_INT_P (x
))
8366 if (SCALAR_INT_MODE_P (mode
))
8367 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8370 x
= GEN_INT (INTVAL (x
) & mask
);
8371 return gen_lowpart_common (mode
, x
);
8375 /* If X is narrower than MODE and we want all the bits in X's mode, just
8376 get X in the proper mode. */
8377 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8378 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8379 return gen_lowpart (mode
, x
);
8381 /* We can ignore the effect of a SUBREG if it narrows the mode or
8382 if the constant masks to zero all the bits the mode doesn't have. */
8383 if (GET_CODE (x
) == SUBREG
8384 && subreg_lowpart_p (x
)
8385 && ((GET_MODE_SIZE (GET_MODE (x
))
8386 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8388 & GET_MODE_MASK (GET_MODE (x
))
8389 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8390 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8392 /* The arithmetic simplifications here only work for scalar integer modes. */
8393 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8394 return gen_lowpart_or_truncate (mode
, x
);
8399 /* If X is a (clobber (const_int)), return it since we know we are
8400 generating something that won't match. */
8407 x
= expand_compound_operation (x
);
8408 if (GET_CODE (x
) != code
)
8409 return force_to_mode (x
, mode
, mask
, next_select
);
8413 /* Similarly for a truncate. */
8414 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8417 /* If this is an AND with a constant, convert it into an AND
8418 whose constant is the AND of that constant with MASK. If it
8419 remains an AND of MASK, delete it since it is redundant. */
8421 if (CONST_INT_P (XEXP (x
, 1)))
8423 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8424 mask
& INTVAL (XEXP (x
, 1)));
8426 /* If X is still an AND, see if it is an AND with a mask that
8427 is just some low-order bits. If so, and it is MASK, we don't
8430 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8431 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8435 /* If it remains an AND, try making another AND with the bits
8436 in the mode mask that aren't in MASK turned on. If the
8437 constant in the AND is wide enough, this might make a
8438 cheaper constant. */
8440 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8441 && GET_MODE_MASK (GET_MODE (x
)) != mask
8442 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8444 unsigned HOST_WIDE_INT cval
8445 = UINTVAL (XEXP (x
, 1))
8446 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8449 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8450 gen_int_mode (cval
, GET_MODE (x
)));
8451 if (set_src_cost (y
, optimize_this_for_speed_p
)
8452 < set_src_cost (x
, optimize_this_for_speed_p
))
8462 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8463 low-order bits (as in an alignment operation) and FOO is already
8464 aligned to that boundary, mask C1 to that boundary as well.
8465 This may eliminate that PLUS and, later, the AND. */
8468 unsigned int width
= GET_MODE_PRECISION (mode
);
8469 unsigned HOST_WIDE_INT smask
= mask
;
8471 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8472 number, sign extend it. */
8474 if (width
< HOST_BITS_PER_WIDE_INT
8475 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8476 smask
|= HOST_WIDE_INT_M1U
<< width
;
8478 if (CONST_INT_P (XEXP (x
, 1))
8479 && exact_log2 (- smask
) >= 0
8480 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8481 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8482 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8483 (INTVAL (XEXP (x
, 1)) & smask
)),
8484 mode
, smask
, next_select
);
8487 /* ... fall through ... */
8490 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8491 most significant bit in MASK since carries from those bits will
8492 affect the bits we are interested in. */
8497 /* If X is (minus C Y) where C's least set bit is larger than any bit
8498 in the mask, then we may replace with (neg Y). */
8499 if (CONST_INT_P (XEXP (x
, 0))
8500 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8502 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8504 return force_to_mode (x
, mode
, mask
, next_select
);
8507 /* Similarly, if C contains every bit in the fuller_mask, then we may
8508 replace with (not Y). */
8509 if (CONST_INT_P (XEXP (x
, 0))
8510 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8512 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8513 XEXP (x
, 1), GET_MODE (x
));
8514 return force_to_mode (x
, mode
, mask
, next_select
);
8522 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8523 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8524 operation which may be a bitfield extraction. Ensure that the
8525 constant we form is not wider than the mode of X. */
8527 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8528 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8529 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8530 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8531 && CONST_INT_P (XEXP (x
, 1))
8532 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8533 + floor_log2 (INTVAL (XEXP (x
, 1))))
8534 < GET_MODE_PRECISION (GET_MODE (x
)))
8535 && (UINTVAL (XEXP (x
, 1))
8536 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8538 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8539 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8541 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8542 XEXP (XEXP (x
, 0), 0), temp
);
8543 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8544 XEXP (XEXP (x
, 0), 1));
8545 return force_to_mode (x
, mode
, mask
, next_select
);
8549 /* For most binary operations, just propagate into the operation and
8550 change the mode if we have an operation of that mode. */
8552 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8553 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8555 /* If we ended up truncating both operands, truncate the result of the
8556 operation instead. */
8557 if (GET_CODE (op0
) == TRUNCATE
8558 && GET_CODE (op1
) == TRUNCATE
)
8560 op0
= XEXP (op0
, 0);
8561 op1
= XEXP (op1
, 0);
8564 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8565 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8567 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8568 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8572 /* For left shifts, do the same, but just for the first operand.
8573 However, we cannot do anything with shifts where we cannot
8574 guarantee that the counts are smaller than the size of the mode
8575 because such a count will have a different meaning in a
8578 if (! (CONST_INT_P (XEXP (x
, 1))
8579 && INTVAL (XEXP (x
, 1)) >= 0
8580 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8581 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8582 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8583 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8586 /* If the shift count is a constant and we can do arithmetic in
8587 the mode of the shift, refine which bits we need. Otherwise, use the
8588 conservative form of the mask. */
8589 if (CONST_INT_P (XEXP (x
, 1))
8590 && INTVAL (XEXP (x
, 1)) >= 0
8591 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8592 && HWI_COMPUTABLE_MODE_P (op_mode
))
8593 mask
>>= INTVAL (XEXP (x
, 1));
8597 op0
= gen_lowpart_or_truncate (op_mode
,
8598 force_to_mode (XEXP (x
, 0), op_mode
,
8599 mask
, next_select
));
8601 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8602 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8606 /* Here we can only do something if the shift count is a constant,
8607 this shift constant is valid for the host, and we can do arithmetic
8610 if (CONST_INT_P (XEXP (x
, 1))
8611 && INTVAL (XEXP (x
, 1)) >= 0
8612 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8613 && HWI_COMPUTABLE_MODE_P (op_mode
))
8615 rtx inner
= XEXP (x
, 0);
8616 unsigned HOST_WIDE_INT inner_mask
;
8618 /* Select the mask of the bits we need for the shift operand. */
8619 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8621 /* We can only change the mode of the shift if we can do arithmetic
8622 in the mode of the shift and INNER_MASK is no wider than the
8623 width of X's mode. */
8624 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8625 op_mode
= GET_MODE (x
);
8627 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8629 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8630 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8633 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8634 shift and AND produces only copies of the sign bit (C2 is one less
8635 than a power of two), we can do this with just a shift. */
8637 if (GET_CODE (x
) == LSHIFTRT
8638 && CONST_INT_P (XEXP (x
, 1))
8639 /* The shift puts one of the sign bit copies in the least significant
8641 && ((INTVAL (XEXP (x
, 1))
8642 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8643 >= GET_MODE_PRECISION (GET_MODE (x
)))
8644 && exact_log2 (mask
+ 1) >= 0
8645 /* Number of bits left after the shift must be more than the mask
8647 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8648 <= GET_MODE_PRECISION (GET_MODE (x
)))
8649 /* Must be more sign bit copies than the mask needs. */
8650 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8651 >= exact_log2 (mask
+ 1)))
8652 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8653 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8654 - exact_log2 (mask
+ 1)));
8659 /* If we are just looking for the sign bit, we don't need this shift at
8660 all, even if it has a variable count. */
8661 if (val_signbit_p (GET_MODE (x
), mask
))
8662 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8664 /* If this is a shift by a constant, get a mask that contains those bits
8665 that are not copies of the sign bit. We then have two cases: If
8666 MASK only includes those bits, this can be a logical shift, which may
8667 allow simplifications. If MASK is a single-bit field not within
8668 those bits, we are requesting a copy of the sign bit and hence can
8669 shift the sign bit to the appropriate location. */
8671 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8672 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8676 /* If the considered data is wider than HOST_WIDE_INT, we can't
8677 represent a mask for all its bits in a single scalar.
8678 But we only care about the lower bits, so calculate these. */
8680 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8682 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8684 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8685 is the number of bits a full-width mask would have set.
8686 We need only shift if these are fewer than nonzero can
8687 hold. If not, we must keep all bits set in nonzero. */
8689 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8690 < HOST_BITS_PER_WIDE_INT
)
8691 nonzero
>>= INTVAL (XEXP (x
, 1))
8692 + HOST_BITS_PER_WIDE_INT
8693 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8697 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8698 nonzero
>>= INTVAL (XEXP (x
, 1));
8701 if ((mask
& ~nonzero
) == 0)
8703 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8704 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8705 if (GET_CODE (x
) != ASHIFTRT
)
8706 return force_to_mode (x
, mode
, mask
, next_select
);
8709 else if ((i
= exact_log2 (mask
)) >= 0)
8711 x
= simplify_shift_const
8712 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8713 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8715 if (GET_CODE (x
) != ASHIFTRT
)
8716 return force_to_mode (x
, mode
, mask
, next_select
);
8720 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8721 even if the shift count isn't a constant. */
8723 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8724 XEXP (x
, 0), XEXP (x
, 1));
8728 /* If this is a zero- or sign-extension operation that just affects bits
8729 we don't care about, remove it. Be sure the call above returned
8730 something that is still a shift. */
8732 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8733 && CONST_INT_P (XEXP (x
, 1))
8734 && INTVAL (XEXP (x
, 1)) >= 0
8735 && (INTVAL (XEXP (x
, 1))
8736 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8737 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8738 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8739 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8746 /* If the shift count is constant and we can do computations
8747 in the mode of X, compute where the bits we care about are.
8748 Otherwise, we can't do anything. Don't change the mode of
8749 the shift or propagate MODE into the shift, though. */
8750 if (CONST_INT_P (XEXP (x
, 1))
8751 && INTVAL (XEXP (x
, 1)) >= 0)
8753 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8755 gen_int_mode (mask
, GET_MODE (x
)),
8757 if (temp
&& CONST_INT_P (temp
))
8758 x
= simplify_gen_binary (code
, GET_MODE (x
),
8759 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8760 INTVAL (temp
), next_select
),
8766 /* If we just want the low-order bit, the NEG isn't needed since it
8767 won't change the low-order bit. */
8769 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8771 /* We need any bits less significant than the most significant bit in
8772 MASK since carries from those bits will affect the bits we are
8778 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8779 same as the XOR case above. Ensure that the constant we form is not
8780 wider than the mode of X. */
8782 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8783 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8784 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8785 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8786 < GET_MODE_PRECISION (GET_MODE (x
)))
8787 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8789 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8791 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8792 XEXP (XEXP (x
, 0), 0), temp
);
8793 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8794 temp
, XEXP (XEXP (x
, 0), 1));
8796 return force_to_mode (x
, mode
, mask
, next_select
);
8799 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8800 use the full mask inside the NOT. */
8804 op0
= gen_lowpart_or_truncate (op_mode
,
8805 force_to_mode (XEXP (x
, 0), mode
, mask
,
8807 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8808 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8812 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8813 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8814 which is equal to STORE_FLAG_VALUE. */
8815 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8816 && XEXP (x
, 1) == const0_rtx
8817 && GET_MODE (XEXP (x
, 0)) == mode
8818 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8819 && (nonzero_bits (XEXP (x
, 0), mode
)
8820 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8821 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8826 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8827 written in a narrower mode. We play it safe and do not do so. */
8829 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8830 force_to_mode (XEXP (x
, 1), mode
,
8831 mask
, next_select
));
8832 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8833 force_to_mode (XEXP (x
, 2), mode
,
8834 mask
, next_select
));
8835 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8836 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8837 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8845 /* Ensure we return a value of the proper mode. */
8846 return gen_lowpart_or_truncate (mode
, x
);
8849 /* Return nonzero if X is an expression that has one of two values depending on
8850 whether some other value is zero or nonzero. In that case, we return the
8851 value that is being tested, *PTRUE is set to the value if the rtx being
8852 returned has a nonzero value, and *PFALSE is set to the other alternative.
8854 If we return zero, we set *PTRUE and *PFALSE to X. */
8857 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8859 machine_mode mode
= GET_MODE (x
);
8860 enum rtx_code code
= GET_CODE (x
);
8861 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8862 unsigned HOST_WIDE_INT nz
;
8864 /* If we are comparing a value against zero, we are done. */
8865 if ((code
== NE
|| code
== EQ
)
8866 && XEXP (x
, 1) == const0_rtx
)
8868 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8869 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8873 /* If this is a unary operation whose operand has one of two values, apply
8874 our opcode to compute those values. */
8875 else if (UNARY_P (x
)
8876 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8878 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8879 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8880 GET_MODE (XEXP (x
, 0)));
8884 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8885 make can't possibly match and would suppress other optimizations. */
8886 else if (code
== COMPARE
)
8889 /* If this is a binary operation, see if either side has only one of two
8890 values. If either one does or if both do and they are conditional on
8891 the same value, compute the new true and false values. */
8892 else if (BINARY_P (x
))
8894 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8895 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8897 if ((cond0
!= 0 || cond1
!= 0)
8898 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8900 /* If if_then_else_cond returned zero, then true/false are the
8901 same rtl. We must copy one of them to prevent invalid rtl
8904 true0
= copy_rtx (true0
);
8905 else if (cond1
== 0)
8906 true1
= copy_rtx (true1
);
8908 if (COMPARISON_P (x
))
8910 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8912 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8917 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8918 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8921 return cond0
? cond0
: cond1
;
8924 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8925 operands is zero when the other is nonzero, and vice-versa,
8926 and STORE_FLAG_VALUE is 1 or -1. */
8928 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8929 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8931 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8933 rtx op0
= XEXP (XEXP (x
, 0), 1);
8934 rtx op1
= XEXP (XEXP (x
, 1), 1);
8936 cond0
= XEXP (XEXP (x
, 0), 0);
8937 cond1
= XEXP (XEXP (x
, 1), 0);
8939 if (COMPARISON_P (cond0
)
8940 && COMPARISON_P (cond1
)
8941 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8942 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8943 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8944 || ((swap_condition (GET_CODE (cond0
))
8945 == reversed_comparison_code (cond1
, NULL
))
8946 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8947 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8948 && ! side_effects_p (x
))
8950 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8951 *pfalse
= simplify_gen_binary (MULT
, mode
,
8953 ? simplify_gen_unary (NEG
, mode
,
8961 /* Similarly for MULT, AND and UMIN, except that for these the result
8963 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8964 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8965 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8967 cond0
= XEXP (XEXP (x
, 0), 0);
8968 cond1
= XEXP (XEXP (x
, 1), 0);
8970 if (COMPARISON_P (cond0
)
8971 && COMPARISON_P (cond1
)
8972 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8973 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8974 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8975 || ((swap_condition (GET_CODE (cond0
))
8976 == reversed_comparison_code (cond1
, NULL
))
8977 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8978 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8979 && ! side_effects_p (x
))
8981 *ptrue
= *pfalse
= const0_rtx
;
8987 else if (code
== IF_THEN_ELSE
)
8989 /* If we have IF_THEN_ELSE already, extract the condition and
8990 canonicalize it if it is NE or EQ. */
8991 cond0
= XEXP (x
, 0);
8992 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8993 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8994 return XEXP (cond0
, 0);
8995 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8997 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8998 return XEXP (cond0
, 0);
9004 /* If X is a SUBREG, we can narrow both the true and false values
9005 if the inner expression, if there is a condition. */
9006 else if (code
== SUBREG
9007 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9010 true0
= simplify_gen_subreg (mode
, true0
,
9011 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9012 false0
= simplify_gen_subreg (mode
, false0
,
9013 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9014 if (true0
&& false0
)
9022 /* If X is a constant, this isn't special and will cause confusions
9023 if we treat it as such. Likewise if it is equivalent to a constant. */
9024 else if (CONSTANT_P (x
)
9025 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9028 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9029 will be least confusing to the rest of the compiler. */
9030 else if (mode
== BImode
)
9032 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9036 /* If X is known to be either 0 or -1, those are the true and
9037 false values when testing X. */
9038 else if (x
== constm1_rtx
|| x
== const0_rtx
9039 || (mode
!= VOIDmode
9040 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9042 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9046 /* Likewise for 0 or a single bit. */
9047 else if (HWI_COMPUTABLE_MODE_P (mode
)
9048 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
9050 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9054 /* Otherwise fail; show no condition with true and false values the same. */
9055 *ptrue
= *pfalse
= x
;
9059 /* Return the value of expression X given the fact that condition COND
9060 is known to be true when applied to REG as its first operand and VAL
9061 as its second. X is known to not be shared and so can be modified in
9064 We only handle the simplest cases, and specifically those cases that
9065 arise with IF_THEN_ELSE expressions. */
9068 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9070 enum rtx_code code
= GET_CODE (x
);
9074 if (side_effects_p (x
))
9077 /* If either operand of the condition is a floating point value,
9078 then we have to avoid collapsing an EQ comparison. */
9080 && rtx_equal_p (x
, reg
)
9081 && ! FLOAT_MODE_P (GET_MODE (x
))
9082 && ! FLOAT_MODE_P (GET_MODE (val
)))
9085 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9088 /* If X is (abs REG) and we know something about REG's relationship
9089 with zero, we may be able to simplify this. */
9091 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9094 case GE
: case GT
: case EQ
:
9097 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9099 GET_MODE (XEXP (x
, 0)));
9104 /* The only other cases we handle are MIN, MAX, and comparisons if the
9105 operands are the same as REG and VAL. */
9107 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9109 if (rtx_equal_p (XEXP (x
, 0), val
))
9111 std::swap (val
, reg
);
9112 cond
= swap_condition (cond
);
9115 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9117 if (COMPARISON_P (x
))
9119 if (comparison_dominates_p (cond
, code
))
9120 return const_true_rtx
;
9122 code
= reversed_comparison_code (x
, NULL
);
9124 && comparison_dominates_p (cond
, code
))
9129 else if (code
== SMAX
|| code
== SMIN
9130 || code
== UMIN
|| code
== UMAX
)
9132 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9134 /* Do not reverse the condition when it is NE or EQ.
9135 This is because we cannot conclude anything about
9136 the value of 'SMAX (x, y)' when x is not equal to y,
9137 but we can when x equals y. */
9138 if ((code
== SMAX
|| code
== UMAX
)
9139 && ! (cond
== EQ
|| cond
== NE
))
9140 cond
= reverse_condition (cond
);
9145 return unsignedp
? x
: XEXP (x
, 1);
9147 return unsignedp
? x
: XEXP (x
, 0);
9149 return unsignedp
? XEXP (x
, 1) : x
;
9151 return unsignedp
? XEXP (x
, 0) : x
;
9158 else if (code
== SUBREG
)
9160 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9161 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9163 if (SUBREG_REG (x
) != r
)
9165 /* We must simplify subreg here, before we lose track of the
9166 original inner_mode. */
9167 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9168 inner_mode
, SUBREG_BYTE (x
));
9172 SUBST (SUBREG_REG (x
), r
);
9177 /* We don't have to handle SIGN_EXTEND here, because even in the
9178 case of replacing something with a modeless CONST_INT, a
9179 CONST_INT is already (supposed to be) a valid sign extension for
9180 its narrower mode, which implies it's already properly
9181 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9182 story is different. */
9183 else if (code
== ZERO_EXTEND
)
9185 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9186 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9188 if (XEXP (x
, 0) != r
)
9190 /* We must simplify the zero_extend here, before we lose
9191 track of the original inner_mode. */
9192 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9197 SUBST (XEXP (x
, 0), r
);
9203 fmt
= GET_RTX_FORMAT (code
);
9204 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9207 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9208 else if (fmt
[i
] == 'E')
9209 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9210 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9217 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9218 assignment as a field assignment. */
9221 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9223 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9225 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9227 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9229 /* For big endian, adjust the memory offset. */
9230 if (BYTES_BIG_ENDIAN
)
9231 x
= adjust_address_nv (x
, GET_MODE (y
),
9232 -subreg_lowpart_offset (GET_MODE (x
),
9235 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9238 if (x
== y
|| rtx_equal_p (x
, y
))
9241 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9244 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9245 Note that all SUBREGs of MEM are paradoxical; otherwise they
9246 would have been rewritten. */
9247 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9248 && MEM_P (SUBREG_REG (y
))
9249 && rtx_equal_p (SUBREG_REG (y
),
9250 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9253 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9254 && MEM_P (SUBREG_REG (x
))
9255 && rtx_equal_p (SUBREG_REG (x
),
9256 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9259 /* We used to see if get_last_value of X and Y were the same but that's
9260 not correct. In one direction, we'll cause the assignment to have
9261 the wrong destination and in the case, we'll import a register into this
9262 insn that might have already have been dead. So fail if none of the
9263 above cases are true. */
9267 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9268 Return that assignment if so.
9270 We only handle the most common cases. */
9273 make_field_assignment (rtx x
)
9275 rtx dest
= SET_DEST (x
);
9276 rtx src
= SET_SRC (x
);
9281 unsigned HOST_WIDE_INT len
;
9285 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9286 a clear of a one-bit field. We will have changed it to
9287 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9290 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9291 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9292 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9293 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9295 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9298 return gen_rtx_SET (assign
, const0_rtx
);
9302 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9303 && subreg_lowpart_p (XEXP (src
, 0))
9304 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9305 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9306 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9307 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9308 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9309 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9311 assign
= make_extraction (VOIDmode
, dest
, 0,
9312 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9315 return gen_rtx_SET (assign
, const0_rtx
);
9319 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9321 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9322 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9323 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9325 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9328 return gen_rtx_SET (assign
, const1_rtx
);
9332 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9333 SRC is an AND with all bits of that field set, then we can discard
9335 if (GET_CODE (dest
) == ZERO_EXTRACT
9336 && CONST_INT_P (XEXP (dest
, 1))
9337 && GET_CODE (src
) == AND
9338 && CONST_INT_P (XEXP (src
, 1)))
9340 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9341 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9342 unsigned HOST_WIDE_INT ze_mask
;
9344 if (width
>= HOST_BITS_PER_WIDE_INT
)
9347 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9349 /* Complete overlap. We can remove the source AND. */
9350 if ((and_mask
& ze_mask
) == ze_mask
)
9351 return gen_rtx_SET (dest
, XEXP (src
, 0));
9353 /* Partial overlap. We can reduce the source AND. */
9354 if ((and_mask
& ze_mask
) != and_mask
)
9356 mode
= GET_MODE (src
);
9357 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9358 gen_int_mode (and_mask
& ze_mask
, mode
));
9359 return gen_rtx_SET (dest
, src
);
9363 /* The other case we handle is assignments into a constant-position
9364 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9365 a mask that has all one bits except for a group of zero bits and
9366 OTHER is known to have zeros where C1 has ones, this is such an
9367 assignment. Compute the position and length from C1. Shift OTHER
9368 to the appropriate position, force it to the required mode, and
9369 make the extraction. Check for the AND in both operands. */
9371 /* One or more SUBREGs might obscure the constant-position field
9372 assignment. The first one we are likely to encounter is an outer
9373 narrowing SUBREG, which we can just strip for the purposes of
9374 identifying the constant-field assignment. */
9375 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9376 src
= SUBREG_REG (src
);
9378 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9381 rhs
= expand_compound_operation (XEXP (src
, 0));
9382 lhs
= expand_compound_operation (XEXP (src
, 1));
9384 if (GET_CODE (rhs
) == AND
9385 && CONST_INT_P (XEXP (rhs
, 1))
9386 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9387 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9388 /* The second SUBREG that might get in the way is a paradoxical
9389 SUBREG around the first operand of the AND. We want to
9390 pretend the operand is as wide as the destination here. We
9391 do this by adjusting the MEM to wider mode for the sole
9392 purpose of the call to rtx_equal_for_field_assignment_p. Also
9393 note this trick only works for MEMs. */
9394 else if (GET_CODE (rhs
) == AND
9395 && paradoxical_subreg_p (XEXP (rhs
, 0))
9396 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9397 && CONST_INT_P (XEXP (rhs
, 1))
9398 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9400 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9401 else if (GET_CODE (lhs
) == AND
9402 && CONST_INT_P (XEXP (lhs
, 1))
9403 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9404 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9405 /* The second SUBREG that might get in the way is a paradoxical
9406 SUBREG around the first operand of the AND. We want to
9407 pretend the operand is as wide as the destination here. We
9408 do this by adjusting the MEM to wider mode for the sole
9409 purpose of the call to rtx_equal_for_field_assignment_p. Also
9410 note this trick only works for MEMs. */
9411 else if (GET_CODE (lhs
) == AND
9412 && paradoxical_subreg_p (XEXP (lhs
, 0))
9413 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9414 && CONST_INT_P (XEXP (lhs
, 1))
9415 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9417 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9421 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9422 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9423 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9424 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9427 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9431 /* The mode to use for the source is the mode of the assignment, or of
9432 what is inside a possible STRICT_LOW_PART. */
9433 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9434 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9436 /* Shift OTHER right POS places and make it the source, restricting it
9437 to the proper length and mode. */
9439 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9443 src
= force_to_mode (src
, mode
,
9444 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9445 ? ~(unsigned HOST_WIDE_INT
) 0
9446 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9449 /* If SRC is masked by an AND that does not make a difference in
9450 the value being stored, strip it. */
9451 if (GET_CODE (assign
) == ZERO_EXTRACT
9452 && CONST_INT_P (XEXP (assign
, 1))
9453 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9454 && GET_CODE (src
) == AND
9455 && CONST_INT_P (XEXP (src
, 1))
9456 && UINTVAL (XEXP (src
, 1))
9457 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9458 src
= XEXP (src
, 0);
9460 return gen_rtx_SET (assign
, src
);
9463 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9467 apply_distributive_law (rtx x
)
9469 enum rtx_code code
= GET_CODE (x
);
9470 enum rtx_code inner_code
;
9471 rtx lhs
, rhs
, other
;
9474 /* Distributivity is not true for floating point as it can change the
9475 value. So we don't do it unless -funsafe-math-optimizations. */
9476 if (FLOAT_MODE_P (GET_MODE (x
))
9477 && ! flag_unsafe_math_optimizations
)
9480 /* The outer operation can only be one of the following: */
9481 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9482 && code
!= PLUS
&& code
!= MINUS
)
9488 /* If either operand is a primitive we can't do anything, so get out
9490 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9493 lhs
= expand_compound_operation (lhs
);
9494 rhs
= expand_compound_operation (rhs
);
9495 inner_code
= GET_CODE (lhs
);
9496 if (inner_code
!= GET_CODE (rhs
))
9499 /* See if the inner and outer operations distribute. */
9506 /* These all distribute except over PLUS. */
9507 if (code
== PLUS
|| code
== MINUS
)
9512 if (code
!= PLUS
&& code
!= MINUS
)
9517 /* This is also a multiply, so it distributes over everything. */
9520 /* This used to handle SUBREG, but this turned out to be counter-
9521 productive, since (subreg (op ...)) usually is not handled by
9522 insn patterns, and this "optimization" therefore transformed
9523 recognizable patterns into unrecognizable ones. Therefore the
9524 SUBREG case was removed from here.
9526 It is possible that distributing SUBREG over arithmetic operations
9527 leads to an intermediate result than can then be optimized further,
9528 e.g. by moving the outer SUBREG to the other side of a SET as done
9529 in simplify_set. This seems to have been the original intent of
9530 handling SUBREGs here.
9532 However, with current GCC this does not appear to actually happen,
9533 at least on major platforms. If some case is found where removing
9534 the SUBREG case here prevents follow-on optimizations, distributing
9535 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9541 /* Set LHS and RHS to the inner operands (A and B in the example
9542 above) and set OTHER to the common operand (C in the example).
9543 There is only one way to do this unless the inner operation is
9545 if (COMMUTATIVE_ARITH_P (lhs
)
9546 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9547 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9548 else if (COMMUTATIVE_ARITH_P (lhs
)
9549 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9550 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9551 else if (COMMUTATIVE_ARITH_P (lhs
)
9552 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9553 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9554 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9555 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9559 /* Form the new inner operation, seeing if it simplifies first. */
9560 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9562 /* There is one exception to the general way of distributing:
9563 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9564 if (code
== XOR
&& inner_code
== IOR
)
9567 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9570 /* We may be able to continuing distributing the result, so call
9571 ourselves recursively on the inner operation before forming the
9572 outer operation, which we return. */
9573 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9574 apply_distributive_law (tem
), other
);
9577 /* See if X is of the form (* (+ A B) C), and if so convert to
9578 (+ (* A C) (* B C)) and try to simplify.
9580 Most of the time, this results in no change. However, if some of
9581 the operands are the same or inverses of each other, simplifications
9584 For example, (and (ior A B) (not B)) can occur as the result of
9585 expanding a bit field assignment. When we apply the distributive
9586 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9587 which then simplifies to (and (A (not B))).
9589 Note that no checks happen on the validity of applying the inverse
9590 distributive law. This is pointless since we can do it in the
9591 few places where this routine is called.
9593 N is the index of the term that is decomposed (the arithmetic operation,
9594 i.e. (+ A B) in the first example above). !N is the index of the term that
9595 is distributed, i.e. of C in the first example above. */
9597 distribute_and_simplify_rtx (rtx x
, int n
)
9600 enum rtx_code outer_code
, inner_code
;
9601 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9603 /* Distributivity is not true for floating point as it can change the
9604 value. So we don't do it unless -funsafe-math-optimizations. */
9605 if (FLOAT_MODE_P (GET_MODE (x
))
9606 && ! flag_unsafe_math_optimizations
)
9609 decomposed
= XEXP (x
, n
);
9610 if (!ARITHMETIC_P (decomposed
))
9613 mode
= GET_MODE (x
);
9614 outer_code
= GET_CODE (x
);
9615 distributed
= XEXP (x
, !n
);
9617 inner_code
= GET_CODE (decomposed
);
9618 inner_op0
= XEXP (decomposed
, 0);
9619 inner_op1
= XEXP (decomposed
, 1);
9621 /* Special case (and (xor B C) (not A)), which is equivalent to
9622 (xor (ior A B) (ior A C)) */
9623 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9625 distributed
= XEXP (distributed
, 0);
9631 /* Distribute the second term. */
9632 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9633 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9637 /* Distribute the first term. */
9638 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9639 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9642 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9644 if (GET_CODE (tmp
) != outer_code
9645 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9646 < set_src_cost (x
, optimize_this_for_speed_p
)))
9652 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9653 in MODE. Return an equivalent form, if different from (and VAROP
9654 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9657 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9658 unsigned HOST_WIDE_INT constop
)
9660 unsigned HOST_WIDE_INT nonzero
;
9661 unsigned HOST_WIDE_INT orig_constop
;
9666 orig_constop
= constop
;
9667 if (GET_CODE (varop
) == CLOBBER
)
9670 /* Simplify VAROP knowing that we will be only looking at some of the
9673 Note by passing in CONSTOP, we guarantee that the bits not set in
9674 CONSTOP are not significant and will never be examined. We must
9675 ensure that is the case by explicitly masking out those bits
9676 before returning. */
9677 varop
= force_to_mode (varop
, mode
, constop
, 0);
9679 /* If VAROP is a CLOBBER, we will fail so return it. */
9680 if (GET_CODE (varop
) == CLOBBER
)
9683 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9684 to VAROP and return the new constant. */
9685 if (CONST_INT_P (varop
))
9686 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9688 /* See what bits may be nonzero in VAROP. Unlike the general case of
9689 a call to nonzero_bits, here we don't care about bits outside
9692 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9694 /* Turn off all bits in the constant that are known to already be zero.
9695 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9696 which is tested below. */
9700 /* If we don't have any bits left, return zero. */
9704 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9705 a power of two, we can replace this with an ASHIFT. */
9706 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9707 && (i
= exact_log2 (constop
)) >= 0)
9708 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9710 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9711 or XOR, then try to apply the distributive law. This may eliminate
9712 operations if either branch can be simplified because of the AND.
9713 It may also make some cases more complex, but those cases probably
9714 won't match a pattern either with or without this. */
9716 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9720 apply_distributive_law
9721 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9722 simplify_and_const_int (NULL_RTX
,
9726 simplify_and_const_int (NULL_RTX
,
9731 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9732 the AND and see if one of the operands simplifies to zero. If so, we
9733 may eliminate it. */
9735 if (GET_CODE (varop
) == PLUS
9736 && exact_log2 (constop
+ 1) >= 0)
9740 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9741 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9742 if (o0
== const0_rtx
)
9744 if (o1
== const0_rtx
)
9748 /* Make a SUBREG if necessary. If we can't make it, fail. */
9749 varop
= gen_lowpart (mode
, varop
);
9750 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9753 /* If we are only masking insignificant bits, return VAROP. */
9754 if (constop
== nonzero
)
9757 if (varop
== orig_varop
&& constop
== orig_constop
)
9760 /* Otherwise, return an AND. */
9761 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9765 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9768 Return an equivalent form, if different from X. Otherwise, return X. If
9769 X is zero, we are to always construct the equivalent form. */
9772 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9773 unsigned HOST_WIDE_INT constop
)
9775 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9780 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9781 gen_int_mode (constop
, mode
));
9782 if (GET_MODE (x
) != mode
)
9783 x
= gen_lowpart (mode
, x
);
9787 /* Given a REG, X, compute which bits in X can be nonzero.
9788 We don't care about bits outside of those defined in MODE.
9790 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9791 a shift, AND, or zero_extract, we can do better. */
9794 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9795 const_rtx known_x ATTRIBUTE_UNUSED
,
9796 machine_mode known_mode ATTRIBUTE_UNUSED
,
9797 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9798 unsigned HOST_WIDE_INT
*nonzero
)
9803 /* If X is a register whose nonzero bits value is current, use it.
9804 Otherwise, if X is a register whose value we can find, use that
9805 value. Otherwise, use the previously-computed global nonzero bits
9806 for this register. */
9808 rsp
= ®_stat
[REGNO (x
)];
9809 if (rsp
->last_set_value
!= 0
9810 && (rsp
->last_set_mode
== mode
9811 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9812 && GET_MODE_CLASS (mode
) == MODE_INT
))
9813 && ((rsp
->last_set_label
>= label_tick_ebb_start
9814 && rsp
->last_set_label
< label_tick
)
9815 || (rsp
->last_set_label
== label_tick
9816 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9817 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9818 && REGNO (x
) < reg_n_sets_max
9819 && REG_N_SETS (REGNO (x
)) == 1
9821 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9824 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9826 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9827 /* We don't know anything about the upper bits. */
9828 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9834 tem
= get_last_value (x
);
9838 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9839 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9840 GET_MODE_PRECISION (mode
));
9844 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9846 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9848 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9849 /* We don't know anything about the upper bits. */
9850 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9858 /* Return the number of bits at the high-order end of X that are known to
9859 be equal to the sign bit. X will be used in mode MODE; if MODE is
9860 VOIDmode, X will be used in its own mode. The returned value will always
9861 be between 1 and the number of bits in MODE. */
9864 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9865 const_rtx known_x ATTRIBUTE_UNUSED
,
9866 machine_mode known_mode
9868 unsigned int known_ret ATTRIBUTE_UNUSED
,
9869 unsigned int *result
)
9874 rsp
= ®_stat
[REGNO (x
)];
9875 if (rsp
->last_set_value
!= 0
9876 && rsp
->last_set_mode
== mode
9877 && ((rsp
->last_set_label
>= label_tick_ebb_start
9878 && rsp
->last_set_label
< label_tick
)
9879 || (rsp
->last_set_label
== label_tick
9880 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9881 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9882 && REGNO (x
) < reg_n_sets_max
9883 && REG_N_SETS (REGNO (x
)) == 1
9885 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9888 *result
= rsp
->last_set_sign_bit_copies
;
9892 tem
= get_last_value (x
);
9896 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9897 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9898 *result
= rsp
->sign_bit_copies
;
9903 /* Return the number of "extended" bits there are in X, when interpreted
9904 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9905 unsigned quantities, this is the number of high-order zero bits.
9906 For signed quantities, this is the number of copies of the sign bit
9907 minus 1. In both case, this function returns the number of "spare"
9908 bits. For example, if two quantities for which this function returns
9909 at least 1 are added, the addition is known not to overflow.
9911 This function will always return 0 unless called during combine, which
9912 implies that it must be called from a define_split. */
9915 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9917 if (nonzero_sign_valid
== 0)
9921 ? (HWI_COMPUTABLE_MODE_P (mode
)
9922 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9923 - floor_log2 (nonzero_bits (x
, mode
)))
9925 : num_sign_bit_copies (x
, mode
) - 1);
9928 /* This function is called from `simplify_shift_const' to merge two
9929 outer operations. Specifically, we have already found that we need
9930 to perform operation *POP0 with constant *PCONST0 at the outermost
9931 position. We would now like to also perform OP1 with constant CONST1
9932 (with *POP0 being done last).
9934 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9935 the resulting operation. *PCOMP_P is set to 1 if we would need to
9936 complement the innermost operand, otherwise it is unchanged.
9938 MODE is the mode in which the operation will be done. No bits outside
9939 the width of this mode matter. It is assumed that the width of this mode
9940 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9942 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9943 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9944 result is simply *PCONST0.
9946 If the resulting operation cannot be expressed as one operation, we
9947 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9950 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9952 enum rtx_code op0
= *pop0
;
9953 HOST_WIDE_INT const0
= *pconst0
;
9955 const0
&= GET_MODE_MASK (mode
);
9956 const1
&= GET_MODE_MASK (mode
);
9958 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9962 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9965 if (op1
== UNKNOWN
|| op0
== SET
)
9968 else if (op0
== UNKNOWN
)
9969 op0
= op1
, const0
= const1
;
9971 else if (op0
== op1
)
9995 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9996 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9999 /* If the two constants aren't the same, we can't do anything. The
10000 remaining six cases can all be done. */
10001 else if (const0
!= const1
)
10009 /* (a & b) | b == b */
10011 else /* op1 == XOR */
10012 /* (a ^ b) | b == a | b */
10018 /* (a & b) ^ b == (~a) & b */
10019 op0
= AND
, *pcomp_p
= 1;
10020 else /* op1 == IOR */
10021 /* (a | b) ^ b == a & ~b */
10022 op0
= AND
, const0
= ~const0
;
10027 /* (a | b) & b == b */
10029 else /* op1 == XOR */
10030 /* (a ^ b) & b) == (~a) & b */
10037 /* Check for NO-OP cases. */
10038 const0
&= GET_MODE_MASK (mode
);
10040 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10042 else if (const0
== 0 && op0
== AND
)
10044 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10050 /* ??? Slightly redundant with the above mask, but not entirely.
10051 Moving this above means we'd have to sign-extend the mode mask
10052 for the final test. */
10053 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10054 *pconst0
= trunc_int_for_mode (const0
, mode
);
10059 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10060 the shift in. The original shift operation CODE is performed on OP in
10061 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10062 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10063 result of the shift is subject to operation OUTER_CODE with operand
10066 static machine_mode
10067 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10068 machine_mode orig_mode
, machine_mode mode
,
10069 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10071 if (orig_mode
== mode
)
10073 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10075 /* In general we can't perform in wider mode for right shift and rotate. */
10079 /* We can still widen if the bits brought in from the left are identical
10080 to the sign bit of ORIG_MODE. */
10081 if (num_sign_bit_copies (op
, mode
)
10082 > (unsigned) (GET_MODE_PRECISION (mode
)
10083 - GET_MODE_PRECISION (orig_mode
)))
10088 /* Similarly here but with zero bits. */
10089 if (HWI_COMPUTABLE_MODE_P (mode
)
10090 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10093 /* We can also widen if the bits brought in will be masked off. This
10094 operation is performed in ORIG_MODE. */
10095 if (outer_code
== AND
)
10097 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10100 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10109 gcc_unreachable ();
10116 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10117 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10118 if we cannot simplify it. Otherwise, return a simplified value.
10120 The shift is normally computed in the widest mode we find in VAROP, as
10121 long as it isn't a different number of words than RESULT_MODE. Exceptions
10122 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10125 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10126 rtx varop
, int orig_count
)
10128 enum rtx_code orig_code
= code
;
10129 rtx orig_varop
= varop
;
10131 machine_mode mode
= result_mode
;
10132 machine_mode shift_mode
, tmode
;
10133 unsigned int mode_words
10134 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10135 /* We form (outer_op (code varop count) (outer_const)). */
10136 enum rtx_code outer_op
= UNKNOWN
;
10137 HOST_WIDE_INT outer_const
= 0;
10138 int complement_p
= 0;
10141 /* Make sure and truncate the "natural" shift on the way in. We don't
10142 want to do this inside the loop as it makes it more difficult to
10144 if (SHIFT_COUNT_TRUNCATED
)
10145 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10147 /* If we were given an invalid count, don't do anything except exactly
10148 what was requested. */
10150 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10153 count
= orig_count
;
10155 /* Unless one of the branches of the `if' in this loop does a `continue',
10156 we will `break' the loop after the `if'. */
10160 /* If we have an operand of (clobber (const_int 0)), fail. */
10161 if (GET_CODE (varop
) == CLOBBER
)
10164 /* Convert ROTATERT to ROTATE. */
10165 if (code
== ROTATERT
)
10167 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10169 if (VECTOR_MODE_P (result_mode
))
10170 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10172 count
= bitsize
- count
;
10175 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10176 mode
, outer_op
, outer_const
);
10178 /* Handle cases where the count is greater than the size of the mode
10179 minus 1. For ASHIFT, use the size minus one as the count (this can
10180 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10181 take the count modulo the size. For other shifts, the result is
10184 Since these shifts are being produced by the compiler by combining
10185 multiple operations, each of which are defined, we know what the
10186 result is supposed to be. */
10188 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10190 if (code
== ASHIFTRT
)
10191 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10192 else if (code
== ROTATE
|| code
== ROTATERT
)
10193 count
%= GET_MODE_PRECISION (shift_mode
);
10196 /* We can't simply return zero because there may be an
10198 varop
= const0_rtx
;
10204 /* If we discovered we had to complement VAROP, leave. Making a NOT
10205 here would cause an infinite loop. */
10209 /* An arithmetic right shift of a quantity known to be -1 or 0
10211 if (code
== ASHIFTRT
10212 && (num_sign_bit_copies (varop
, shift_mode
)
10213 == GET_MODE_PRECISION (shift_mode
)))
10219 /* If we are doing an arithmetic right shift and discarding all but
10220 the sign bit copies, this is equivalent to doing a shift by the
10221 bitsize minus one. Convert it into that shift because it will often
10222 allow other simplifications. */
10224 if (code
== ASHIFTRT
10225 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10226 >= GET_MODE_PRECISION (shift_mode
)))
10227 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10229 /* We simplify the tests below and elsewhere by converting
10230 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10231 `make_compound_operation' will convert it to an ASHIFTRT for
10232 those machines (such as VAX) that don't have an LSHIFTRT. */
10233 if (code
== ASHIFTRT
10234 && val_signbit_known_clear_p (shift_mode
,
10235 nonzero_bits (varop
, shift_mode
)))
10238 if (((code
== LSHIFTRT
10239 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10240 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10242 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10243 && !((nonzero_bits (varop
, shift_mode
) << count
)
10244 & GET_MODE_MASK (shift_mode
))))
10245 && !side_effects_p (varop
))
10246 varop
= const0_rtx
;
10248 switch (GET_CODE (varop
))
10254 new_rtx
= expand_compound_operation (varop
);
10255 if (new_rtx
!= varop
)
10263 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10264 minus the width of a smaller mode, we can do this with a
10265 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10266 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10267 && ! mode_dependent_address_p (XEXP (varop
, 0),
10268 MEM_ADDR_SPACE (varop
))
10269 && ! MEM_VOLATILE_P (varop
)
10270 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10271 MODE_INT
, 1)) != BLKmode
)
10273 new_rtx
= adjust_address_nv (varop
, tmode
,
10274 BYTES_BIG_ENDIAN
? 0
10275 : count
/ BITS_PER_UNIT
);
10277 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10278 : ZERO_EXTEND
, mode
, new_rtx
);
10285 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10286 the same number of words as what we've seen so far. Then store
10287 the widest mode in MODE. */
10288 if (subreg_lowpart_p (varop
)
10289 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10290 > GET_MODE_SIZE (GET_MODE (varop
)))
10291 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10292 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10294 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10295 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10297 varop
= SUBREG_REG (varop
);
10298 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10299 mode
= GET_MODE (varop
);
10305 /* Some machines use MULT instead of ASHIFT because MULT
10306 is cheaper. But it is still better on those machines to
10307 merge two shifts into one. */
10308 if (CONST_INT_P (XEXP (varop
, 1))
10309 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10312 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10314 GEN_INT (exact_log2 (
10315 UINTVAL (XEXP (varop
, 1)))));
10321 /* Similar, for when divides are cheaper. */
10322 if (CONST_INT_P (XEXP (varop
, 1))
10323 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10326 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10328 GEN_INT (exact_log2 (
10329 UINTVAL (XEXP (varop
, 1)))));
10335 /* If we are extracting just the sign bit of an arithmetic
10336 right shift, that shift is not needed. However, the sign
10337 bit of a wider mode may be different from what would be
10338 interpreted as the sign bit in a narrower mode, so, if
10339 the result is narrower, don't discard the shift. */
10340 if (code
== LSHIFTRT
10341 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10342 && (GET_MODE_BITSIZE (result_mode
)
10343 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10345 varop
= XEXP (varop
, 0);
10349 /* ... fall through ... */
10354 /* Here we have two nested shifts. The result is usually the
10355 AND of a new shift with a mask. We compute the result below. */
10356 if (CONST_INT_P (XEXP (varop
, 1))
10357 && INTVAL (XEXP (varop
, 1)) >= 0
10358 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10359 && HWI_COMPUTABLE_MODE_P (result_mode
)
10360 && HWI_COMPUTABLE_MODE_P (mode
)
10361 && !VECTOR_MODE_P (result_mode
))
10363 enum rtx_code first_code
= GET_CODE (varop
);
10364 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10365 unsigned HOST_WIDE_INT mask
;
10368 /* We have one common special case. We can't do any merging if
10369 the inner code is an ASHIFTRT of a smaller mode. However, if
10370 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10371 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10372 we can convert it to
10373 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10374 This simplifies certain SIGN_EXTEND operations. */
10375 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10376 && count
== (GET_MODE_PRECISION (result_mode
)
10377 - GET_MODE_PRECISION (GET_MODE (varop
))))
10379 /* C3 has the low-order C1 bits zero. */
10381 mask
= GET_MODE_MASK (mode
)
10382 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10384 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10385 XEXP (varop
, 0), mask
);
10386 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10388 count
= first_count
;
10393 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10394 than C1 high-order bits equal to the sign bit, we can convert
10395 this to either an ASHIFT or an ASHIFTRT depending on the
10398 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10400 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10401 && GET_MODE (varop
) == shift_mode
10402 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10405 varop
= XEXP (varop
, 0);
10406 count
-= first_count
;
10416 /* There are some cases we can't do. If CODE is ASHIFTRT,
10417 we can only do this if FIRST_CODE is also ASHIFTRT.
10419 We can't do the case when CODE is ROTATE and FIRST_CODE is
10422 If the mode of this shift is not the mode of the outer shift,
10423 we can't do this if either shift is a right shift or ROTATE.
10425 Finally, we can't do any of these if the mode is too wide
10426 unless the codes are the same.
10428 Handle the case where the shift codes are the same
10431 if (code
== first_code
)
10433 if (GET_MODE (varop
) != result_mode
10434 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10435 || code
== ROTATE
))
10438 count
+= first_count
;
10439 varop
= XEXP (varop
, 0);
10443 if (code
== ASHIFTRT
10444 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10445 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10446 || (GET_MODE (varop
) != result_mode
10447 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10448 || first_code
== ROTATE
10449 || code
== ROTATE
)))
10452 /* To compute the mask to apply after the shift, shift the
10453 nonzero bits of the inner shift the same way the
10454 outer shift will. */
10456 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10460 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10463 /* Give up if we can't compute an outer operation to use. */
10465 || !CONST_INT_P (mask_rtx
)
10466 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10468 result_mode
, &complement_p
))
10471 /* If the shifts are in the same direction, we add the
10472 counts. Otherwise, we subtract them. */
10473 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10474 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10475 count
+= first_count
;
10477 count
-= first_count
;
10479 /* If COUNT is positive, the new shift is usually CODE,
10480 except for the two exceptions below, in which case it is
10481 FIRST_CODE. If the count is negative, FIRST_CODE should
10484 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10485 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10487 else if (count
< 0)
10488 code
= first_code
, count
= -count
;
10490 varop
= XEXP (varop
, 0);
10494 /* If we have (A << B << C) for any shift, we can convert this to
10495 (A << C << B). This wins if A is a constant. Only try this if
10496 B is not a constant. */
10498 else if (GET_CODE (varop
) == code
10499 && CONST_INT_P (XEXP (varop
, 0))
10500 && !CONST_INT_P (XEXP (varop
, 1)))
10502 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10505 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10512 if (VECTOR_MODE_P (mode
))
10515 /* Make this fit the case below. */
10516 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10522 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10523 with C the size of VAROP - 1 and the shift is logical if
10524 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10525 we have an (le X 0) operation. If we have an arithmetic shift
10526 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10527 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10529 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10530 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10531 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10532 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10533 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10534 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10537 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10540 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10541 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10546 /* If we have (shift (logical)), move the logical to the outside
10547 to allow it to possibly combine with another logical and the
10548 shift to combine with another shift. This also canonicalizes to
10549 what a ZERO_EXTRACT looks like. Also, some machines have
10550 (and (shift)) insns. */
10552 if (CONST_INT_P (XEXP (varop
, 1))
10553 /* We can't do this if we have (ashiftrt (xor)) and the
10554 constant has its sign bit set in shift_mode with shift_mode
10555 wider than result_mode. */
10556 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10557 && result_mode
!= shift_mode
10558 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10560 && (new_rtx
= simplify_const_binary_operation
10561 (code
, result_mode
,
10562 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10563 GEN_INT (count
))) != 0
10564 && CONST_INT_P (new_rtx
)
10565 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10566 INTVAL (new_rtx
), result_mode
, &complement_p
))
10568 varop
= XEXP (varop
, 0);
10572 /* If we can't do that, try to simplify the shift in each arm of the
10573 logical expression, make a new logical expression, and apply
10574 the inverse distributive law. This also can't be done for
10575 (ashiftrt (xor)) where we've widened the shift and the constant
10576 changes the sign bit. */
10577 if (CONST_INT_P (XEXP (varop
, 1))
10578 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10579 && result_mode
!= shift_mode
10580 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10583 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10584 XEXP (varop
, 0), count
);
10585 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10586 XEXP (varop
, 1), count
);
10588 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10590 varop
= apply_distributive_law (varop
);
10598 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10599 says that the sign bit can be tested, FOO has mode MODE, C is
10600 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10601 that may be nonzero. */
10602 if (code
== LSHIFTRT
10603 && XEXP (varop
, 1) == const0_rtx
10604 && GET_MODE (XEXP (varop
, 0)) == result_mode
10605 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10606 && HWI_COMPUTABLE_MODE_P (result_mode
)
10607 && STORE_FLAG_VALUE
== -1
10608 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10609 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10612 varop
= XEXP (varop
, 0);
10619 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10620 than the number of bits in the mode is equivalent to A. */
10621 if (code
== LSHIFTRT
10622 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10623 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10625 varop
= XEXP (varop
, 0);
10630 /* NEG commutes with ASHIFT since it is multiplication. Move the
10631 NEG outside to allow shifts to combine. */
10633 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10636 varop
= XEXP (varop
, 0);
10642 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10643 is one less than the number of bits in the mode is
10644 equivalent to (xor A 1). */
10645 if (code
== LSHIFTRT
10646 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10647 && XEXP (varop
, 1) == constm1_rtx
10648 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10649 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10653 varop
= XEXP (varop
, 0);
10657 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10658 that might be nonzero in BAR are those being shifted out and those
10659 bits are known zero in FOO, we can replace the PLUS with FOO.
10660 Similarly in the other operand order. This code occurs when
10661 we are computing the size of a variable-size array. */
10663 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10664 && count
< HOST_BITS_PER_WIDE_INT
10665 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10666 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10667 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10669 varop
= XEXP (varop
, 0);
10672 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10673 && count
< HOST_BITS_PER_WIDE_INT
10674 && HWI_COMPUTABLE_MODE_P (result_mode
)
10675 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10677 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10678 & nonzero_bits (XEXP (varop
, 1),
10681 varop
= XEXP (varop
, 1);
10685 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10687 && CONST_INT_P (XEXP (varop
, 1))
10688 && (new_rtx
= simplify_const_binary_operation
10689 (ASHIFT
, result_mode
,
10690 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10691 GEN_INT (count
))) != 0
10692 && CONST_INT_P (new_rtx
)
10693 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10694 INTVAL (new_rtx
), result_mode
, &complement_p
))
10696 varop
= XEXP (varop
, 0);
10700 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10701 signbit', and attempt to change the PLUS to an XOR and move it to
10702 the outer operation as is done above in the AND/IOR/XOR case
10703 leg for shift(logical). See details in logical handling above
10704 for reasoning in doing so. */
10705 if (code
== LSHIFTRT
10706 && CONST_INT_P (XEXP (varop
, 1))
10707 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10708 && (new_rtx
= simplify_const_binary_operation
10709 (code
, result_mode
,
10710 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10711 GEN_INT (count
))) != 0
10712 && CONST_INT_P (new_rtx
)
10713 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10714 INTVAL (new_rtx
), result_mode
, &complement_p
))
10716 varop
= XEXP (varop
, 0);
10723 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10724 with C the size of VAROP - 1 and the shift is logical if
10725 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10726 we have a (gt X 0) operation. If the shift is arithmetic with
10727 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10728 we have a (neg (gt X 0)) operation. */
10730 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10731 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10732 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10733 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10734 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10735 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10736 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10739 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10742 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10743 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10750 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10751 if the truncate does not affect the value. */
10752 if (code
== LSHIFTRT
10753 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10754 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10755 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10756 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10757 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10759 rtx varop_inner
= XEXP (varop
, 0);
10762 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10763 XEXP (varop_inner
, 0),
10765 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10766 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10779 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10780 outer_op
, outer_const
);
10782 /* We have now finished analyzing the shift. The result should be
10783 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10784 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10785 to the result of the shift. OUTER_CONST is the relevant constant,
10786 but we must turn off all bits turned off in the shift. */
10788 if (outer_op
== UNKNOWN
10789 && orig_code
== code
&& orig_count
== count
10790 && varop
== orig_varop
10791 && shift_mode
== GET_MODE (varop
))
10794 /* Make a SUBREG if necessary. If we can't make it, fail. */
10795 varop
= gen_lowpart (shift_mode
, varop
);
10796 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10799 /* If we have an outer operation and we just made a shift, it is
10800 possible that we could have simplified the shift were it not
10801 for the outer operation. So try to do the simplification
10804 if (outer_op
!= UNKNOWN
)
10805 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10810 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10812 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10813 turn off all the bits that the shift would have turned off. */
10814 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10815 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10816 GET_MODE_MASK (result_mode
) >> orig_count
);
10818 /* Do the remainder of the processing in RESULT_MODE. */
10819 x
= gen_lowpart_or_truncate (result_mode
, x
);
10821 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10824 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10826 if (outer_op
!= UNKNOWN
)
10828 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10829 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10830 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10832 if (outer_op
== AND
)
10833 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10834 else if (outer_op
== SET
)
10836 /* This means that we have determined that the result is
10837 equivalent to a constant. This should be rare. */
10838 if (!side_effects_p (x
))
10839 x
= GEN_INT (outer_const
);
10841 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10842 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10844 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10845 GEN_INT (outer_const
));
10851 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10852 The result of the shift is RESULT_MODE. If we cannot simplify it,
10853 return X or, if it is NULL, synthesize the expression with
10854 simplify_gen_binary. Otherwise, return a simplified value.
10856 The shift is normally computed in the widest mode we find in VAROP, as
10857 long as it isn't a different number of words than RESULT_MODE. Exceptions
10858 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10861 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10862 rtx varop
, int count
)
10864 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10869 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10870 if (GET_MODE (x
) != result_mode
)
10871 x
= gen_lowpart (result_mode
, x
);
10876 /* A subroutine of recog_for_combine. See there for arguments and
10880 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10882 rtx pat
= *pnewpat
;
10883 rtx pat_without_clobbers
;
10884 int insn_code_number
;
10885 int num_clobbers_to_add
= 0;
10887 rtx notes
= NULL_RTX
;
10888 rtx old_notes
, old_pat
;
10891 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10892 we use to indicate that something didn't match. If we find such a
10893 thing, force rejection. */
10894 if (GET_CODE (pat
) == PARALLEL
)
10895 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10896 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10897 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10900 old_pat
= PATTERN (insn
);
10901 old_notes
= REG_NOTES (insn
);
10902 PATTERN (insn
) = pat
;
10903 REG_NOTES (insn
) = NULL_RTX
;
10905 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10906 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10908 if (insn_code_number
< 0)
10909 fputs ("Failed to match this instruction:\n", dump_file
);
10911 fputs ("Successfully matched this instruction:\n", dump_file
);
10912 print_rtl_single (dump_file
, pat
);
10915 /* If it isn't, there is the possibility that we previously had an insn
10916 that clobbered some register as a side effect, but the combined
10917 insn doesn't need to do that. So try once more without the clobbers
10918 unless this represents an ASM insn. */
10920 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10921 && GET_CODE (pat
) == PARALLEL
)
10925 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10926 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10929 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10933 SUBST_INT (XVECLEN (pat
, 0), pos
);
10936 pat
= XVECEXP (pat
, 0, 0);
10938 PATTERN (insn
) = pat
;
10939 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10940 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10942 if (insn_code_number
< 0)
10943 fputs ("Failed to match this instruction:\n", dump_file
);
10945 fputs ("Successfully matched this instruction:\n", dump_file
);
10946 print_rtl_single (dump_file
, pat
);
10950 pat_without_clobbers
= pat
;
10952 PATTERN (insn
) = old_pat
;
10953 REG_NOTES (insn
) = old_notes
;
10955 /* Recognize all noop sets, these will be killed by followup pass. */
10956 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10957 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10959 /* If we had any clobbers to add, make a new pattern than contains
10960 them. Then check to make sure that all of them are dead. */
10961 if (num_clobbers_to_add
)
10963 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10964 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10965 ? (XVECLEN (pat
, 0)
10966 + num_clobbers_to_add
)
10967 : num_clobbers_to_add
+ 1));
10969 if (GET_CODE (pat
) == PARALLEL
)
10970 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10971 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10973 XVECEXP (newpat
, 0, 0) = pat
;
10975 add_clobbers (newpat
, insn_code_number
);
10977 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10978 i
< XVECLEN (newpat
, 0); i
++)
10980 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10981 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10983 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10985 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10986 notes
= alloc_reg_note (REG_UNUSED
,
10987 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10993 if (insn_code_number
>= 0
10994 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10996 old_pat
= PATTERN (insn
);
10997 old_notes
= REG_NOTES (insn
);
10998 old_icode
= INSN_CODE (insn
);
10999 PATTERN (insn
) = pat
;
11000 REG_NOTES (insn
) = notes
;
11002 /* Allow targets to reject combined insn. */
11003 if (!targetm
.legitimate_combined_insn (insn
))
11005 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11006 fputs ("Instruction not appropriate for target.",
11009 /* Callers expect recog_for_combine to strip
11010 clobbers from the pattern on failure. */
11011 pat
= pat_without_clobbers
;
11014 insn_code_number
= -1;
11017 PATTERN (insn
) = old_pat
;
11018 REG_NOTES (insn
) = old_notes
;
11019 INSN_CODE (insn
) = old_icode
;
11025 return insn_code_number
;
11028 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11029 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11030 Return whether anything was so changed. */
11033 change_zero_ext (rtx
*src
)
11035 bool changed
= false;
11037 subrtx_ptr_iterator::array_type array
;
11038 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11041 machine_mode mode
= GET_MODE (x
);
11044 if (GET_CODE (x
) == ZERO_EXTRACT
11045 && CONST_INT_P (XEXP (x
, 1))
11046 && CONST_INT_P (XEXP (x
, 2))
11047 && GET_MODE (XEXP (x
, 0)) == mode
)
11049 size
= INTVAL (XEXP (x
, 1));
11051 int start
= INTVAL (XEXP (x
, 2));
11052 if (BITS_BIG_ENDIAN
)
11053 start
= GET_MODE_PRECISION (mode
) - size
- start
;
11055 x
= gen_rtx_LSHIFTRT (mode
, XEXP (x
, 0), GEN_INT (start
));
11057 else if (GET_CODE (x
) == ZERO_EXTEND
11058 && GET_CODE (XEXP (x
, 0)) == SUBREG
11059 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
11060 && subreg_lowpart_p (XEXP (x
, 0)))
11062 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11063 x
= SUBREG_REG (XEXP (x
, 0));
11068 unsigned HOST_WIDE_INT mask
= 1;
11072 x
= gen_rtx_AND (mode
, x
, GEN_INT (mask
));
11081 /* Like recog, but we receive the address of a pointer to a new pattern.
11082 We try to match the rtx that the pointer points to.
11083 If that fails, we may try to modify or replace the pattern,
11084 storing the replacement into the same pointer object.
11086 Modifications include deletion or addition of CLOBBERs. If the
11087 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11088 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11089 (and undo if that fails).
11091 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11092 the CLOBBERs are placed.
11094 The value is the final insn code from the pattern ultimately matched,
11098 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11100 rtx pat
= PATTERN (insn
);
11101 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11102 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11103 return insn_code_number
;
11105 void *marker
= get_undo_marker ();
11106 bool changed
= false;
11108 if (GET_CODE (pat
) == SET
)
11109 changed
= change_zero_ext (&SET_SRC (pat
));
11110 else if (GET_CODE (pat
) == PARALLEL
)
11113 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11115 rtx set
= XVECEXP (pat
, 0, i
);
11116 if (GET_CODE (set
) == SET
)
11117 changed
|= change_zero_ext (&SET_SRC (set
));
11123 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11125 if (insn_code_number
< 0)
11126 undo_to_marker (marker
);
11129 return insn_code_number
;
11132 /* Like gen_lowpart_general but for use by combine. In combine it
11133 is not possible to create any new pseudoregs. However, it is
11134 safe to create invalid memory addresses, because combine will
11135 try to recognize them and all they will do is make the combine
11138 If for some reason this cannot do its job, an rtx
11139 (clobber (const_int 0)) is returned.
11140 An insn containing that will not be recognized. */
11143 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11145 machine_mode imode
= GET_MODE (x
);
11146 unsigned int osize
= GET_MODE_SIZE (omode
);
11147 unsigned int isize
= GET_MODE_SIZE (imode
);
11150 if (omode
== imode
)
11153 /* We can only support MODE being wider than a word if X is a
11154 constant integer or has a mode the same size. */
11155 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11156 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11159 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11160 won't know what to do. So we will strip off the SUBREG here and
11161 process normally. */
11162 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11164 x
= SUBREG_REG (x
);
11166 /* For use in case we fall down into the address adjustments
11167 further below, we need to adjust the known mode and size of
11168 x; imode and isize, since we just adjusted x. */
11169 imode
= GET_MODE (x
);
11171 if (imode
== omode
)
11174 isize
= GET_MODE_SIZE (imode
);
11177 result
= gen_lowpart_common (omode
, x
);
11186 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11188 if (MEM_VOLATILE_P (x
)
11189 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11192 /* If we want to refer to something bigger than the original memref,
11193 generate a paradoxical subreg instead. That will force a reload
11194 of the original memref X. */
11196 return gen_rtx_SUBREG (omode
, x
, 0);
11198 if (WORDS_BIG_ENDIAN
)
11199 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11201 /* Adjust the address so that the address-after-the-data is
11203 if (BYTES_BIG_ENDIAN
)
11204 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11206 return adjust_address_nv (x
, omode
, offset
);
11209 /* If X is a comparison operator, rewrite it in a new mode. This
11210 probably won't match, but may allow further simplifications. */
11211 else if (COMPARISON_P (x
))
11212 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11214 /* If we couldn't simplify X any other way, just enclose it in a
11215 SUBREG. Normally, this SUBREG won't match, but some patterns may
11216 include an explicit SUBREG or we may simplify it further in combine. */
11222 offset
= subreg_lowpart_offset (omode
, imode
);
11223 if (imode
== VOIDmode
)
11225 imode
= int_mode_for_mode (omode
);
11226 x
= gen_lowpart_common (imode
, x
);
11230 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
11236 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11239 /* Try to simplify a comparison between OP0 and a constant OP1,
11240 where CODE is the comparison code that will be tested, into a
11241 (CODE OP0 const0_rtx) form.
11243 The result is a possibly different comparison code to use.
11244 *POP1 may be updated. */
11246 static enum rtx_code
11247 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11248 rtx op0
, rtx
*pop1
)
11250 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11251 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11253 /* Get the constant we are comparing against and turn off all bits
11254 not on in our mode. */
11255 if (mode
!= VOIDmode
)
11256 const_op
= trunc_int_for_mode (const_op
, mode
);
11258 /* If we are comparing against a constant power of two and the value
11259 being compared can only have that single bit nonzero (e.g., it was
11260 `and'ed with that bit), we can replace this with a comparison
11263 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11264 || code
== LT
|| code
== LTU
)
11265 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11266 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
11267 && (nonzero_bits (op0
, mode
)
11268 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11270 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11274 /* Similarly, if we are comparing a value known to be either -1 or
11275 0 with -1, change it to the opposite comparison against zero. */
11277 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11278 || code
== GEU
|| code
== LTU
)
11279 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11281 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11285 /* Do some canonicalizations based on the comparison code. We prefer
11286 comparisons against zero and then prefer equality comparisons.
11287 If we can reduce the size of a constant, we will do that too. */
11291 /* < C is equivalent to <= (C - 1) */
11296 /* ... fall through to LE case below. */
11302 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11309 /* If we are doing a <= 0 comparison on a value known to have
11310 a zero sign bit, we can replace this with == 0. */
11311 else if (const_op
== 0
11312 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11313 && (nonzero_bits (op0
, mode
)
11314 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11320 /* >= C is equivalent to > (C - 1). */
11325 /* ... fall through to GT below. */
11331 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11338 /* If we are doing a > 0 comparison on a value known to have
11339 a zero sign bit, we can replace this with != 0. */
11340 else if (const_op
== 0
11341 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11342 && (nonzero_bits (op0
, mode
)
11343 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11349 /* < C is equivalent to <= (C - 1). */
11354 /* ... fall through ... */
11356 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11357 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11358 && (unsigned HOST_WIDE_INT
) const_op
11359 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11369 /* unsigned <= 0 is equivalent to == 0 */
11372 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11373 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11374 && (unsigned HOST_WIDE_INT
) const_op
11375 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11383 /* >= C is equivalent to > (C - 1). */
11388 /* ... fall through ... */
11391 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11392 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11393 && (unsigned HOST_WIDE_INT
) const_op
11394 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11404 /* unsigned > 0 is equivalent to != 0 */
11407 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11408 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11409 && (unsigned HOST_WIDE_INT
) const_op
11410 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11421 *pop1
= GEN_INT (const_op
);
11425 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11426 comparison code that will be tested.
11428 The result is a possibly different comparison code to use. *POP0 and
11429 *POP1 may be updated.
11431 It is possible that we might detect that a comparison is either always
11432 true or always false. However, we do not perform general constant
11433 folding in combine, so this knowledge isn't useful. Such tautologies
11434 should have been detected earlier. Hence we ignore all such cases. */
11436 static enum rtx_code
11437 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11443 machine_mode mode
, tmode
;
11445 /* Try a few ways of applying the same transformation to both operands. */
11448 #ifndef WORD_REGISTER_OPERATIONS
11449 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11450 so check specially. */
11451 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11452 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11453 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11454 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11455 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11456 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11457 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11458 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11459 && CONST_INT_P (XEXP (op0
, 1))
11460 && XEXP (op0
, 1) == XEXP (op1
, 1)
11461 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11462 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11463 && (INTVAL (XEXP (op0
, 1))
11464 == (GET_MODE_PRECISION (GET_MODE (op0
))
11465 - (GET_MODE_PRECISION
11466 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11468 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11469 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11473 /* If both operands are the same constant shift, see if we can ignore the
11474 shift. We can if the shift is a rotate or if the bits shifted out of
11475 this shift are known to be zero for both inputs and if the type of
11476 comparison is compatible with the shift. */
11477 if (GET_CODE (op0
) == GET_CODE (op1
)
11478 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11479 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11480 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11481 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11482 || (GET_CODE (op0
) == ASHIFTRT
11483 && (code
!= GTU
&& code
!= LTU
11484 && code
!= GEU
&& code
!= LEU
)))
11485 && CONST_INT_P (XEXP (op0
, 1))
11486 && INTVAL (XEXP (op0
, 1)) >= 0
11487 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11488 && XEXP (op0
, 1) == XEXP (op1
, 1))
11490 machine_mode mode
= GET_MODE (op0
);
11491 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11492 int shift_count
= INTVAL (XEXP (op0
, 1));
11494 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11495 mask
&= (mask
>> shift_count
) << shift_count
;
11496 else if (GET_CODE (op0
) == ASHIFT
)
11497 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11499 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11500 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11501 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11506 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11507 SUBREGs are of the same mode, and, in both cases, the AND would
11508 be redundant if the comparison was done in the narrower mode,
11509 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11510 and the operand's possibly nonzero bits are 0xffffff01; in that case
11511 if we only care about QImode, we don't need the AND). This case
11512 occurs if the output mode of an scc insn is not SImode and
11513 STORE_FLAG_VALUE == 1 (e.g., the 386).
11515 Similarly, check for a case where the AND's are ZERO_EXTEND
11516 operations from some narrower mode even though a SUBREG is not
11519 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11520 && CONST_INT_P (XEXP (op0
, 1))
11521 && CONST_INT_P (XEXP (op1
, 1)))
11523 rtx inner_op0
= XEXP (op0
, 0);
11524 rtx inner_op1
= XEXP (op1
, 0);
11525 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11526 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11529 if (paradoxical_subreg_p (inner_op0
)
11530 && GET_CODE (inner_op1
) == SUBREG
11531 && (GET_MODE (SUBREG_REG (inner_op0
))
11532 == GET_MODE (SUBREG_REG (inner_op1
)))
11533 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11534 <= HOST_BITS_PER_WIDE_INT
)
11535 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11536 GET_MODE (SUBREG_REG (inner_op0
)))))
11537 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11538 GET_MODE (SUBREG_REG (inner_op1
))))))
11540 op0
= SUBREG_REG (inner_op0
);
11541 op1
= SUBREG_REG (inner_op1
);
11543 /* The resulting comparison is always unsigned since we masked
11544 off the original sign bit. */
11545 code
= unsigned_condition (code
);
11551 for (tmode
= GET_CLASS_NARROWEST_MODE
11552 (GET_MODE_CLASS (GET_MODE (op0
)));
11553 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11554 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11556 op0
= gen_lowpart (tmode
, inner_op0
);
11557 op1
= gen_lowpart (tmode
, inner_op1
);
11558 code
= unsigned_condition (code
);
11567 /* If both operands are NOT, we can strip off the outer operation
11568 and adjust the comparison code for swapped operands; similarly for
11569 NEG, except that this must be an equality comparison. */
11570 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11571 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11572 && (code
== EQ
|| code
== NE
)))
11573 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11579 /* If the first operand is a constant, swap the operands and adjust the
11580 comparison code appropriately, but don't do this if the second operand
11581 is already a constant integer. */
11582 if (swap_commutative_operands_p (op0
, op1
))
11584 std::swap (op0
, op1
);
11585 code
= swap_condition (code
);
11588 /* We now enter a loop during which we will try to simplify the comparison.
11589 For the most part, we only are concerned with comparisons with zero,
11590 but some things may really be comparisons with zero but not start
11591 out looking that way. */
11593 while (CONST_INT_P (op1
))
11595 machine_mode mode
= GET_MODE (op0
);
11596 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11597 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11598 int equality_comparison_p
;
11599 int sign_bit_comparison_p
;
11600 int unsigned_comparison_p
;
11601 HOST_WIDE_INT const_op
;
11603 /* We only want to handle integral modes. This catches VOIDmode,
11604 CCmode, and the floating-point modes. An exception is that we
11605 can handle VOIDmode if OP0 is a COMPARE or a comparison
11608 if (GET_MODE_CLASS (mode
) != MODE_INT
11609 && ! (mode
== VOIDmode
11610 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11613 /* Try to simplify the compare to constant, possibly changing the
11614 comparison op, and/or changing op1 to zero. */
11615 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11616 const_op
= INTVAL (op1
);
11618 /* Compute some predicates to simplify code below. */
11620 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11621 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11622 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11625 /* If this is a sign bit comparison and we can do arithmetic in
11626 MODE, say that we will only be needing the sign bit of OP0. */
11627 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11628 op0
= force_to_mode (op0
, mode
,
11629 (unsigned HOST_WIDE_INT
) 1
11630 << (GET_MODE_PRECISION (mode
) - 1),
11633 /* Now try cases based on the opcode of OP0. If none of the cases
11634 does a "continue", we exit this loop immediately after the
11637 switch (GET_CODE (op0
))
11640 /* If we are extracting a single bit from a variable position in
11641 a constant that has only a single bit set and are comparing it
11642 with zero, we can convert this into an equality comparison
11643 between the position and the location of the single bit. */
11644 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11645 have already reduced the shift count modulo the word size. */
11646 if (!SHIFT_COUNT_TRUNCATED
11647 && CONST_INT_P (XEXP (op0
, 0))
11648 && XEXP (op0
, 1) == const1_rtx
11649 && equality_comparison_p
&& const_op
== 0
11650 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11652 if (BITS_BIG_ENDIAN
)
11653 i
= BITS_PER_WORD
- 1 - i
;
11655 op0
= XEXP (op0
, 2);
11659 /* Result is nonzero iff shift count is equal to I. */
11660 code
= reverse_condition (code
);
11664 /* ... fall through ... */
11667 tem
= expand_compound_operation (op0
);
11676 /* If testing for equality, we can take the NOT of the constant. */
11677 if (equality_comparison_p
11678 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11680 op0
= XEXP (op0
, 0);
11685 /* If just looking at the sign bit, reverse the sense of the
11687 if (sign_bit_comparison_p
)
11689 op0
= XEXP (op0
, 0);
11690 code
= (code
== GE
? LT
: GE
);
11696 /* If testing for equality, we can take the NEG of the constant. */
11697 if (equality_comparison_p
11698 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11700 op0
= XEXP (op0
, 0);
11705 /* The remaining cases only apply to comparisons with zero. */
11709 /* When X is ABS or is known positive,
11710 (neg X) is < 0 if and only if X != 0. */
11712 if (sign_bit_comparison_p
11713 && (GET_CODE (XEXP (op0
, 0)) == ABS
11714 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11715 && (nonzero_bits (XEXP (op0
, 0), mode
)
11716 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11719 op0
= XEXP (op0
, 0);
11720 code
= (code
== LT
? NE
: EQ
);
11724 /* If we have NEG of something whose two high-order bits are the
11725 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11726 if (num_sign_bit_copies (op0
, mode
) >= 2)
11728 op0
= XEXP (op0
, 0);
11729 code
= swap_condition (code
);
11735 /* If we are testing equality and our count is a constant, we
11736 can perform the inverse operation on our RHS. */
11737 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11738 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11739 op1
, XEXP (op0
, 1))) != 0)
11741 op0
= XEXP (op0
, 0);
11746 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11747 a particular bit. Convert it to an AND of a constant of that
11748 bit. This will be converted into a ZERO_EXTRACT. */
11749 if (const_op
== 0 && sign_bit_comparison_p
11750 && CONST_INT_P (XEXP (op0
, 1))
11751 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11753 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11754 ((unsigned HOST_WIDE_INT
) 1
11756 - INTVAL (XEXP (op0
, 1)))));
11757 code
= (code
== LT
? NE
: EQ
);
11761 /* Fall through. */
11764 /* ABS is ignorable inside an equality comparison with zero. */
11765 if (const_op
== 0 && equality_comparison_p
)
11767 op0
= XEXP (op0
, 0);
11773 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11774 (compare FOO CONST) if CONST fits in FOO's mode and we
11775 are either testing inequality or have an unsigned
11776 comparison with ZERO_EXTEND or a signed comparison with
11777 SIGN_EXTEND. But don't do it if we don't have a compare
11778 insn of the given mode, since we'd have to revert it
11779 later on, and then we wouldn't know whether to sign- or
11781 mode
= GET_MODE (XEXP (op0
, 0));
11782 if (GET_MODE_CLASS (mode
) == MODE_INT
11783 && ! unsigned_comparison_p
11784 && HWI_COMPUTABLE_MODE_P (mode
)
11785 && trunc_int_for_mode (const_op
, mode
) == const_op
11786 && have_insn_for (COMPARE
, mode
))
11788 op0
= XEXP (op0
, 0);
11794 /* Check for the case where we are comparing A - C1 with C2, that is
11796 (subreg:MODE (plus (A) (-C1))) op (C2)
11798 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11799 comparison in the wider mode. One of the following two conditions
11800 must be true in order for this to be valid:
11802 1. The mode extension results in the same bit pattern being added
11803 on both sides and the comparison is equality or unsigned. As
11804 C2 has been truncated to fit in MODE, the pattern can only be
11807 2. The mode extension results in the sign bit being copied on
11810 The difficulty here is that we have predicates for A but not for
11811 (A - C1) so we need to check that C1 is within proper bounds so
11812 as to perturbate A as little as possible. */
11814 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11815 && subreg_lowpart_p (op0
)
11816 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11817 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11818 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11820 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11821 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11822 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11825 && (unsigned HOST_WIDE_INT
) c1
11826 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11827 && (equality_comparison_p
|| unsigned_comparison_p
)
11828 /* (A - C1) zero-extends if it is positive and sign-extends
11829 if it is negative, C2 both zero- and sign-extends. */
11830 && ((0 == (nonzero_bits (a
, inner_mode
)
11831 & ~GET_MODE_MASK (mode
))
11833 /* (A - C1) sign-extends if it is positive and 1-extends
11834 if it is negative, C2 both sign- and 1-extends. */
11835 || (num_sign_bit_copies (a
, inner_mode
)
11836 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11839 || ((unsigned HOST_WIDE_INT
) c1
11840 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11841 /* (A - C1) always sign-extends, like C2. */
11842 && num_sign_bit_copies (a
, inner_mode
)
11843 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11844 - (mode_width
- 1))))
11846 op0
= SUBREG_REG (op0
);
11851 /* If the inner mode is narrower and we are extracting the low part,
11852 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11853 if (subreg_lowpart_p (op0
)
11854 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11855 /* Fall through */ ;
11859 /* ... fall through ... */
11862 mode
= GET_MODE (XEXP (op0
, 0));
11863 if (GET_MODE_CLASS (mode
) == MODE_INT
11864 && (unsigned_comparison_p
|| equality_comparison_p
)
11865 && HWI_COMPUTABLE_MODE_P (mode
)
11866 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11868 && have_insn_for (COMPARE
, mode
))
11870 op0
= XEXP (op0
, 0);
11876 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11877 this for equality comparisons due to pathological cases involving
11879 if (equality_comparison_p
11880 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11881 op1
, XEXP (op0
, 1))))
11883 op0
= XEXP (op0
, 0);
11888 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11889 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11890 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11892 op0
= XEXP (XEXP (op0
, 0), 0);
11893 code
= (code
== LT
? EQ
: NE
);
11899 /* We used to optimize signed comparisons against zero, but that
11900 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11901 arrive here as equality comparisons, or (GEU, LTU) are
11902 optimized away. No need to special-case them. */
11904 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11905 (eq B (minus A C)), whichever simplifies. We can only do
11906 this for equality comparisons due to pathological cases involving
11908 if (equality_comparison_p
11909 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11910 XEXP (op0
, 1), op1
)))
11912 op0
= XEXP (op0
, 0);
11917 if (equality_comparison_p
11918 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11919 XEXP (op0
, 0), op1
)))
11921 op0
= XEXP (op0
, 1);
11926 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11927 of bits in X minus 1, is one iff X > 0. */
11928 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11929 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11930 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11931 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11933 op0
= XEXP (op0
, 1);
11934 code
= (code
== GE
? LE
: GT
);
11940 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11941 if C is zero or B is a constant. */
11942 if (equality_comparison_p
11943 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11944 XEXP (op0
, 1), op1
)))
11946 op0
= XEXP (op0
, 0);
11953 case UNEQ
: case LTGT
:
11954 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11955 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11956 case UNORDERED
: case ORDERED
:
11957 /* We can't do anything if OP0 is a condition code value, rather
11958 than an actual data value. */
11960 || CC0_P (XEXP (op0
, 0))
11961 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11964 /* Get the two operands being compared. */
11965 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11966 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11968 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11970 /* Check for the cases where we simply want the result of the
11971 earlier test or the opposite of that result. */
11972 if (code
== NE
|| code
== EQ
11973 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11974 && (code
== LT
|| code
== GE
)))
11976 enum rtx_code new_code
;
11977 if (code
== LT
|| code
== NE
)
11978 new_code
= GET_CODE (op0
);
11980 new_code
= reversed_comparison_code (op0
, NULL
);
11982 if (new_code
!= UNKNOWN
)
11993 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11995 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11996 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11997 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11999 op0
= XEXP (op0
, 1);
12000 code
= (code
== GE
? GT
: LE
);
12006 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12007 will be converted to a ZERO_EXTRACT later. */
12008 if (const_op
== 0 && equality_comparison_p
12009 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12010 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12012 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12013 XEXP (XEXP (op0
, 0), 1));
12014 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12018 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12019 zero and X is a comparison and C1 and C2 describe only bits set
12020 in STORE_FLAG_VALUE, we can compare with X. */
12021 if (const_op
== 0 && equality_comparison_p
12022 && mode_width
<= HOST_BITS_PER_WIDE_INT
12023 && CONST_INT_P (XEXP (op0
, 1))
12024 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12025 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12026 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12027 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12029 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12030 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12031 if ((~STORE_FLAG_VALUE
& mask
) == 0
12032 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12033 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12034 && COMPARISON_P (tem
))))
12036 op0
= XEXP (XEXP (op0
, 0), 0);
12041 /* If we are doing an equality comparison of an AND of a bit equal
12042 to the sign bit, replace this with a LT or GE comparison of
12043 the underlying value. */
12044 if (equality_comparison_p
12046 && CONST_INT_P (XEXP (op0
, 1))
12047 && mode_width
<= HOST_BITS_PER_WIDE_INT
12048 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12049 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
12051 op0
= XEXP (op0
, 0);
12052 code
= (code
== EQ
? GE
: LT
);
12056 /* If this AND operation is really a ZERO_EXTEND from a narrower
12057 mode, the constant fits within that mode, and this is either an
12058 equality or unsigned comparison, try to do this comparison in
12063 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12064 -> (ne:DI (reg:SI 4) (const_int 0))
12066 unless TRULY_NOOP_TRUNCATION allows it or the register is
12067 known to hold a value of the required mode the
12068 transformation is invalid. */
12069 if ((equality_comparison_p
|| unsigned_comparison_p
)
12070 && CONST_INT_P (XEXP (op0
, 1))
12071 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12072 & GET_MODE_MASK (mode
))
12074 && const_op
>> i
== 0
12075 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
12076 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
12077 || (REG_P (XEXP (op0
, 0))
12078 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
12080 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
12084 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12085 fits in both M1 and M2 and the SUBREG is either paradoxical
12086 or represents the low part, permute the SUBREG and the AND
12088 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
12090 unsigned HOST_WIDE_INT c1
;
12091 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12092 /* Require an integral mode, to avoid creating something like
12094 if (SCALAR_INT_MODE_P (tmode
)
12095 /* It is unsafe to commute the AND into the SUBREG if the
12096 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12097 not defined. As originally written the upper bits
12098 have a defined value due to the AND operation.
12099 However, if we commute the AND inside the SUBREG then
12100 they no longer have defined values and the meaning of
12101 the code has been changed. */
12103 #ifdef WORD_REGISTER_OPERATIONS
12104 || (mode_width
> GET_MODE_PRECISION (tmode
)
12105 && mode_width
<= BITS_PER_WORD
)
12107 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12108 && subreg_lowpart_p (XEXP (op0
, 0))))
12109 && CONST_INT_P (XEXP (op0
, 1))
12110 && mode_width
<= HOST_BITS_PER_WIDE_INT
12111 && HWI_COMPUTABLE_MODE_P (tmode
)
12112 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
12113 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12115 && c1
!= GET_MODE_MASK (tmode
))
12117 op0
= simplify_gen_binary (AND
, tmode
,
12118 SUBREG_REG (XEXP (op0
, 0)),
12119 gen_int_mode (c1
, tmode
));
12120 op0
= gen_lowpart (mode
, op0
);
12125 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12126 if (const_op
== 0 && equality_comparison_p
12127 && XEXP (op0
, 1) == const1_rtx
12128 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12130 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12131 XEXP (XEXP (op0
, 0), 0), 1);
12132 code
= (code
== NE
? EQ
: NE
);
12136 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12137 (eq (and (lshiftrt X) 1) 0).
12138 Also handle the case where (not X) is expressed using xor. */
12139 if (const_op
== 0 && equality_comparison_p
12140 && XEXP (op0
, 1) == const1_rtx
12141 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12143 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12144 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12146 if (GET_CODE (shift_op
) == NOT
12147 || (GET_CODE (shift_op
) == XOR
12148 && CONST_INT_P (XEXP (shift_op
, 1))
12149 && CONST_INT_P (shift_count
)
12150 && HWI_COMPUTABLE_MODE_P (mode
)
12151 && (UINTVAL (XEXP (shift_op
, 1))
12152 == (unsigned HOST_WIDE_INT
) 1
12153 << INTVAL (shift_count
))))
12156 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12157 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12158 code
= (code
== NE
? EQ
: NE
);
12165 /* If we have (compare (ashift FOO N) (const_int C)) and
12166 the high order N bits of FOO (N+1 if an inequality comparison)
12167 are known to be zero, we can do this by comparing FOO with C
12168 shifted right N bits so long as the low-order N bits of C are
12170 if (CONST_INT_P (XEXP (op0
, 1))
12171 && INTVAL (XEXP (op0
, 1)) >= 0
12172 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12173 < HOST_BITS_PER_WIDE_INT
)
12174 && (((unsigned HOST_WIDE_INT
) const_op
12175 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
12177 && mode_width
<= HOST_BITS_PER_WIDE_INT
12178 && (nonzero_bits (XEXP (op0
, 0), mode
)
12179 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12180 + ! equality_comparison_p
))) == 0)
12182 /* We must perform a logical shift, not an arithmetic one,
12183 as we want the top N bits of C to be zero. */
12184 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12186 temp
>>= INTVAL (XEXP (op0
, 1));
12187 op1
= gen_int_mode (temp
, mode
);
12188 op0
= XEXP (op0
, 0);
12192 /* If we are doing a sign bit comparison, it means we are testing
12193 a particular bit. Convert it to the appropriate AND. */
12194 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12195 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12197 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12198 ((unsigned HOST_WIDE_INT
) 1
12200 - INTVAL (XEXP (op0
, 1)))));
12201 code
= (code
== LT
? NE
: EQ
);
12205 /* If this an equality comparison with zero and we are shifting
12206 the low bit to the sign bit, we can convert this to an AND of the
12208 if (const_op
== 0 && equality_comparison_p
12209 && CONST_INT_P (XEXP (op0
, 1))
12210 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12212 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12218 /* If this is an equality comparison with zero, we can do this
12219 as a logical shift, which might be much simpler. */
12220 if (equality_comparison_p
&& const_op
== 0
12221 && CONST_INT_P (XEXP (op0
, 1)))
12223 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12225 INTVAL (XEXP (op0
, 1)));
12229 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12230 do the comparison in a narrower mode. */
12231 if (! unsigned_comparison_p
12232 && CONST_INT_P (XEXP (op0
, 1))
12233 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12234 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12235 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12236 MODE_INT
, 1)) != BLKmode
12237 && (((unsigned HOST_WIDE_INT
) const_op
12238 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12239 <= GET_MODE_MASK (tmode
)))
12241 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12245 /* Likewise if OP0 is a PLUS of a sign extension with a
12246 constant, which is usually represented with the PLUS
12247 between the shifts. */
12248 if (! unsigned_comparison_p
12249 && CONST_INT_P (XEXP (op0
, 1))
12250 && GET_CODE (XEXP (op0
, 0)) == PLUS
12251 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12252 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12253 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12254 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12255 MODE_INT
, 1)) != BLKmode
12256 && (((unsigned HOST_WIDE_INT
) const_op
12257 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12258 <= GET_MODE_MASK (tmode
)))
12260 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12261 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12262 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12263 add_const
, XEXP (op0
, 1));
12265 op0
= simplify_gen_binary (PLUS
, tmode
,
12266 gen_lowpart (tmode
, inner
),
12271 /* ... fall through ... */
12273 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12274 the low order N bits of FOO are known to be zero, we can do this
12275 by comparing FOO with C shifted left N bits so long as no
12276 overflow occurs. Even if the low order N bits of FOO aren't known
12277 to be zero, if the comparison is >= or < we can use the same
12278 optimization and for > or <= by setting all the low
12279 order N bits in the comparison constant. */
12280 if (CONST_INT_P (XEXP (op0
, 1))
12281 && INTVAL (XEXP (op0
, 1)) > 0
12282 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12283 && mode_width
<= HOST_BITS_PER_WIDE_INT
12284 && (((unsigned HOST_WIDE_INT
) const_op
12285 + (GET_CODE (op0
) != LSHIFTRT
12286 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12289 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12291 unsigned HOST_WIDE_INT low_bits
12292 = (nonzero_bits (XEXP (op0
, 0), mode
)
12293 & (((unsigned HOST_WIDE_INT
) 1
12294 << INTVAL (XEXP (op0
, 1))) - 1));
12295 if (low_bits
== 0 || !equality_comparison_p
)
12297 /* If the shift was logical, then we must make the condition
12299 if (GET_CODE (op0
) == LSHIFTRT
)
12300 code
= unsigned_condition (code
);
12302 const_op
<<= INTVAL (XEXP (op0
, 1));
12304 && (code
== GT
|| code
== GTU
12305 || code
== LE
|| code
== LEU
))
12307 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12308 op1
= GEN_INT (const_op
);
12309 op0
= XEXP (op0
, 0);
12314 /* If we are using this shift to extract just the sign bit, we
12315 can replace this with an LT or GE comparison. */
12317 && (equality_comparison_p
|| sign_bit_comparison_p
)
12318 && CONST_INT_P (XEXP (op0
, 1))
12319 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12321 op0
= XEXP (op0
, 0);
12322 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12334 /* Now make any compound operations involved in this comparison. Then,
12335 check for an outmost SUBREG on OP0 that is not doing anything or is
12336 paradoxical. The latter transformation must only be performed when
12337 it is known that the "extra" bits will be the same in op0 and op1 or
12338 that they don't matter. There are three cases to consider:
12340 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12341 care bits and we can assume they have any convenient value. So
12342 making the transformation is safe.
12344 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12345 In this case the upper bits of op0 are undefined. We should not make
12346 the simplification in that case as we do not know the contents of
12349 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12350 UNKNOWN. In that case we know those bits are zeros or ones. We must
12351 also be sure that they are the same as the upper bits of op1.
12353 We can never remove a SUBREG for a non-equality comparison because
12354 the sign bit is in a different place in the underlying object. */
12356 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12357 op1
= make_compound_operation (op1
, SET
);
12359 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12360 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12361 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12362 && (code
== NE
|| code
== EQ
))
12364 if (paradoxical_subreg_p (op0
))
12366 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12368 if (REG_P (SUBREG_REG (op0
)))
12370 op0
= SUBREG_REG (op0
);
12371 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12374 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12375 <= HOST_BITS_PER_WIDE_INT
)
12376 && (nonzero_bits (SUBREG_REG (op0
),
12377 GET_MODE (SUBREG_REG (op0
)))
12378 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12380 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12382 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12383 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12384 op0
= SUBREG_REG (op0
), op1
= tem
;
12388 /* We now do the opposite procedure: Some machines don't have compare
12389 insns in all modes. If OP0's mode is an integer mode smaller than a
12390 word and we can't do a compare in that mode, see if there is a larger
12391 mode for which we can do the compare. There are a number of cases in
12392 which we can use the wider mode. */
12394 mode
= GET_MODE (op0
);
12395 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12396 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12397 && ! have_insn_for (COMPARE
, mode
))
12398 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12399 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12400 tmode
= GET_MODE_WIDER_MODE (tmode
))
12401 if (have_insn_for (COMPARE
, tmode
))
12405 /* If this is a test for negative, we can make an explicit
12406 test of the sign bit. Test this first so we can use
12407 a paradoxical subreg to extend OP0. */
12409 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12410 && HWI_COMPUTABLE_MODE_P (mode
))
12412 unsigned HOST_WIDE_INT sign
12413 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12414 op0
= simplify_gen_binary (AND
, tmode
,
12415 gen_lowpart (tmode
, op0
),
12416 gen_int_mode (sign
, tmode
));
12417 code
= (code
== LT
) ? NE
: EQ
;
12421 /* If the only nonzero bits in OP0 and OP1 are those in the
12422 narrower mode and this is an equality or unsigned comparison,
12423 we can use the wider mode. Similarly for sign-extended
12424 values, in which case it is true for all comparisons. */
12425 zero_extended
= ((code
== EQ
|| code
== NE
12426 || code
== GEU
|| code
== GTU
12427 || code
== LEU
|| code
== LTU
)
12428 && (nonzero_bits (op0
, tmode
)
12429 & ~GET_MODE_MASK (mode
)) == 0
12430 && ((CONST_INT_P (op1
)
12431 || (nonzero_bits (op1
, tmode
)
12432 & ~GET_MODE_MASK (mode
)) == 0)));
12435 || ((num_sign_bit_copies (op0
, tmode
)
12436 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12437 - GET_MODE_PRECISION (mode
)))
12438 && (num_sign_bit_copies (op1
, tmode
)
12439 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12440 - GET_MODE_PRECISION (mode
)))))
12442 /* If OP0 is an AND and we don't have an AND in MODE either,
12443 make a new AND in the proper mode. */
12444 if (GET_CODE (op0
) == AND
12445 && !have_insn_for (AND
, mode
))
12446 op0
= simplify_gen_binary (AND
, tmode
,
12447 gen_lowpart (tmode
,
12449 gen_lowpart (tmode
,
12455 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12456 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12460 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12461 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12468 /* We may have changed the comparison operands. Re-canonicalize. */
12469 if (swap_commutative_operands_p (op0
, op1
))
12471 std::swap (op0
, op1
);
12472 code
= swap_condition (code
);
12475 /* If this machine only supports a subset of valid comparisons, see if we
12476 can convert an unsupported one into a supported one. */
12477 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12485 /* Utility function for record_value_for_reg. Count number of
12490 enum rtx_code code
= GET_CODE (x
);
12494 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12495 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12497 rtx x0
= XEXP (x
, 0);
12498 rtx x1
= XEXP (x
, 1);
12501 return 1 + 2 * count_rtxs (x0
);
12503 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12504 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12505 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12506 return 2 + 2 * count_rtxs (x0
)
12507 + count_rtxs (x
== XEXP (x1
, 0)
12508 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12510 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12511 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12512 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12513 return 2 + 2 * count_rtxs (x1
)
12514 + count_rtxs (x
== XEXP (x0
, 0)
12515 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12518 fmt
= GET_RTX_FORMAT (code
);
12519 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12521 ret
+= count_rtxs (XEXP (x
, i
));
12522 else if (fmt
[i
] == 'E')
12523 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12524 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12529 /* Utility function for following routine. Called when X is part of a value
12530 being stored into last_set_value. Sets last_set_table_tick
12531 for each register mentioned. Similar to mention_regs in cse.c */
12534 update_table_tick (rtx x
)
12536 enum rtx_code code
= GET_CODE (x
);
12537 const char *fmt
= GET_RTX_FORMAT (code
);
12542 unsigned int regno
= REGNO (x
);
12543 unsigned int endregno
= END_REGNO (x
);
12546 for (r
= regno
; r
< endregno
; r
++)
12548 reg_stat_type
*rsp
= ®_stat
[r
];
12549 rsp
->last_set_table_tick
= label_tick
;
12555 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12558 /* Check for identical subexpressions. If x contains
12559 identical subexpression we only have to traverse one of
12561 if (i
== 0 && ARITHMETIC_P (x
))
12563 /* Note that at this point x1 has already been
12565 rtx x0
= XEXP (x
, 0);
12566 rtx x1
= XEXP (x
, 1);
12568 /* If x0 and x1 are identical then there is no need to
12573 /* If x0 is identical to a subexpression of x1 then while
12574 processing x1, x0 has already been processed. Thus we
12575 are done with x. */
12576 if (ARITHMETIC_P (x1
)
12577 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12580 /* If x1 is identical to a subexpression of x0 then we
12581 still have to process the rest of x0. */
12582 if (ARITHMETIC_P (x0
)
12583 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12585 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12590 update_table_tick (XEXP (x
, i
));
12592 else if (fmt
[i
] == 'E')
12593 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12594 update_table_tick (XVECEXP (x
, i
, j
));
12597 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12598 are saying that the register is clobbered and we no longer know its
12599 value. If INSN is zero, don't update reg_stat[].last_set; this is
12600 only permitted with VALUE also zero and is used to invalidate the
12604 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12606 unsigned int regno
= REGNO (reg
);
12607 unsigned int endregno
= END_REGNO (reg
);
12609 reg_stat_type
*rsp
;
12611 /* If VALUE contains REG and we have a previous value for REG, substitute
12612 the previous value. */
12613 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12617 /* Set things up so get_last_value is allowed to see anything set up to
12619 subst_low_luid
= DF_INSN_LUID (insn
);
12620 tem
= get_last_value (reg
);
12622 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12623 it isn't going to be useful and will take a lot of time to process,
12624 so just use the CLOBBER. */
12628 if (ARITHMETIC_P (tem
)
12629 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12630 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12631 tem
= XEXP (tem
, 0);
12632 else if (count_occurrences (value
, reg
, 1) >= 2)
12634 /* If there are two or more occurrences of REG in VALUE,
12635 prevent the value from growing too much. */
12636 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12637 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12640 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12644 /* For each register modified, show we don't know its value, that
12645 we don't know about its bitwise content, that its value has been
12646 updated, and that we don't know the location of the death of the
12648 for (i
= regno
; i
< endregno
; i
++)
12650 rsp
= ®_stat
[i
];
12653 rsp
->last_set
= insn
;
12655 rsp
->last_set_value
= 0;
12656 rsp
->last_set_mode
= VOIDmode
;
12657 rsp
->last_set_nonzero_bits
= 0;
12658 rsp
->last_set_sign_bit_copies
= 0;
12659 rsp
->last_death
= 0;
12660 rsp
->truncated_to_mode
= VOIDmode
;
12663 /* Mark registers that are being referenced in this value. */
12665 update_table_tick (value
);
12667 /* Now update the status of each register being set.
12668 If someone is using this register in this block, set this register
12669 to invalid since we will get confused between the two lives in this
12670 basic block. This makes using this register always invalid. In cse, we
12671 scan the table to invalidate all entries using this register, but this
12672 is too much work for us. */
12674 for (i
= regno
; i
< endregno
; i
++)
12676 rsp
= ®_stat
[i
];
12677 rsp
->last_set_label
= label_tick
;
12679 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12680 rsp
->last_set_invalid
= 1;
12682 rsp
->last_set_invalid
= 0;
12685 /* The value being assigned might refer to X (like in "x++;"). In that
12686 case, we must replace it with (clobber (const_int 0)) to prevent
12688 rsp
= ®_stat
[regno
];
12689 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12691 value
= copy_rtx (value
);
12692 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12696 /* For the main register being modified, update the value, the mode, the
12697 nonzero bits, and the number of sign bit copies. */
12699 rsp
->last_set_value
= value
;
12703 machine_mode mode
= GET_MODE (reg
);
12704 subst_low_luid
= DF_INSN_LUID (insn
);
12705 rsp
->last_set_mode
= mode
;
12706 if (GET_MODE_CLASS (mode
) == MODE_INT
12707 && HWI_COMPUTABLE_MODE_P (mode
))
12708 mode
= nonzero_bits_mode
;
12709 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12710 rsp
->last_set_sign_bit_copies
12711 = num_sign_bit_copies (value
, GET_MODE (reg
));
12715 /* Called via note_stores from record_dead_and_set_regs to handle one
12716 SET or CLOBBER in an insn. DATA is the instruction in which the
12717 set is occurring. */
12720 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12722 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12724 if (GET_CODE (dest
) == SUBREG
)
12725 dest
= SUBREG_REG (dest
);
12727 if (!record_dead_insn
)
12730 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12736 /* If we are setting the whole register, we know its value. Otherwise
12737 show that we don't know the value. We can handle SUBREG in
12739 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12740 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12741 else if (GET_CODE (setter
) == SET
12742 && GET_CODE (SET_DEST (setter
)) == SUBREG
12743 && SUBREG_REG (SET_DEST (setter
)) == dest
12744 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12745 && subreg_lowpart_p (SET_DEST (setter
)))
12746 record_value_for_reg (dest
, record_dead_insn
,
12747 gen_lowpart (GET_MODE (dest
),
12748 SET_SRC (setter
)));
12750 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12752 else if (MEM_P (dest
)
12753 /* Ignore pushes, they clobber nothing. */
12754 && ! push_operand (dest
, GET_MODE (dest
)))
12755 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12758 /* Update the records of when each REG was most recently set or killed
12759 for the things done by INSN. This is the last thing done in processing
12760 INSN in the combiner loop.
12762 We update reg_stat[], in particular fields last_set, last_set_value,
12763 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12764 last_death, and also the similar information mem_last_set (which insn
12765 most recently modified memory) and last_call_luid (which insn was the
12766 most recent subroutine call). */
12769 record_dead_and_set_regs (rtx_insn
*insn
)
12774 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12776 if (REG_NOTE_KIND (link
) == REG_DEAD
12777 && REG_P (XEXP (link
, 0)))
12779 unsigned int regno
= REGNO (XEXP (link
, 0));
12780 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12782 for (i
= regno
; i
< endregno
; i
++)
12784 reg_stat_type
*rsp
;
12786 rsp
= ®_stat
[i
];
12787 rsp
->last_death
= insn
;
12790 else if (REG_NOTE_KIND (link
) == REG_INC
)
12791 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12796 hard_reg_set_iterator hrsi
;
12797 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12799 reg_stat_type
*rsp
;
12801 rsp
= ®_stat
[i
];
12802 rsp
->last_set_invalid
= 1;
12803 rsp
->last_set
= insn
;
12804 rsp
->last_set_value
= 0;
12805 rsp
->last_set_mode
= VOIDmode
;
12806 rsp
->last_set_nonzero_bits
= 0;
12807 rsp
->last_set_sign_bit_copies
= 0;
12808 rsp
->last_death
= 0;
12809 rsp
->truncated_to_mode
= VOIDmode
;
12812 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12814 /* We can't combine into a call pattern. Remember, though, that
12815 the return value register is set at this LUID. We could
12816 still replace a register with the return value from the
12817 wrong subroutine call! */
12818 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12821 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12824 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12825 register present in the SUBREG, so for each such SUBREG go back and
12826 adjust nonzero and sign bit information of the registers that are
12827 known to have some zero/sign bits set.
12829 This is needed because when combine blows the SUBREGs away, the
12830 information on zero/sign bits is lost and further combines can be
12831 missed because of that. */
12834 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12836 struct insn_link
*links
;
12838 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12839 machine_mode mode
= GET_MODE (subreg
);
12841 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12844 for (links
= LOG_LINKS (insn
); links
;)
12846 reg_stat_type
*rsp
;
12848 insn
= links
->insn
;
12849 set
= single_set (insn
);
12851 if (! set
|| !REG_P (SET_DEST (set
))
12852 || REGNO (SET_DEST (set
)) != regno
12853 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12855 links
= links
->next
;
12859 rsp
= ®_stat
[regno
];
12860 if (rsp
->last_set
== insn
)
12862 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12863 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12866 if (REG_P (SET_SRC (set
)))
12868 regno
= REGNO (SET_SRC (set
));
12869 links
= LOG_LINKS (insn
);
12876 /* Check if X, a register, is known to contain a value already
12877 truncated to MODE. In this case we can use a subreg to refer to
12878 the truncated value even though in the generic case we would need
12879 an explicit truncation. */
12882 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12884 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12885 machine_mode truncated
= rsp
->truncated_to_mode
;
12888 || rsp
->truncation_label
< label_tick_ebb_start
)
12890 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12892 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12897 /* If X is a hard reg or a subreg record the mode that the register is
12898 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12899 to turn a truncate into a subreg using this information. Return true
12900 if traversing X is complete. */
12903 record_truncated_value (rtx x
)
12905 machine_mode truncated_mode
;
12906 reg_stat_type
*rsp
;
12908 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12910 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12911 truncated_mode
= GET_MODE (x
);
12913 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12916 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12919 x
= SUBREG_REG (x
);
12921 /* ??? For hard-regs we now record everything. We might be able to
12922 optimize this using last_set_mode. */
12923 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12924 truncated_mode
= GET_MODE (x
);
12928 rsp
= ®_stat
[REGNO (x
)];
12929 if (rsp
->truncated_to_mode
== 0
12930 || rsp
->truncation_label
< label_tick_ebb_start
12931 || (GET_MODE_SIZE (truncated_mode
)
12932 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12934 rsp
->truncated_to_mode
= truncated_mode
;
12935 rsp
->truncation_label
= label_tick
;
12941 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12942 the modes they are used in. This can help truning TRUNCATEs into
12946 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12948 subrtx_var_iterator::array_type array
;
12949 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12950 if (record_truncated_value (*iter
))
12951 iter
.skip_subrtxes ();
12954 /* Scan X for promoted SUBREGs. For each one found,
12955 note what it implies to the registers used in it. */
12958 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12960 if (GET_CODE (x
) == SUBREG
12961 && SUBREG_PROMOTED_VAR_P (x
)
12962 && REG_P (SUBREG_REG (x
)))
12963 record_promoted_value (insn
, x
);
12966 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12969 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12973 check_promoted_subreg (insn
, XEXP (x
, i
));
12977 if (XVEC (x
, i
) != 0)
12978 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12979 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12985 /* Verify that all the registers and memory references mentioned in *LOC are
12986 still valid. *LOC was part of a value set in INSN when label_tick was
12987 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12988 the invalid references with (clobber (const_int 0)) and return 1. This
12989 replacement is useful because we often can get useful information about
12990 the form of a value (e.g., if it was produced by a shift that always
12991 produces -1 or 0) even though we don't know exactly what registers it
12992 was produced from. */
12995 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12998 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12999 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13004 unsigned int regno
= REGNO (x
);
13005 unsigned int endregno
= END_REGNO (x
);
13008 for (j
= regno
; j
< endregno
; j
++)
13010 reg_stat_type
*rsp
= ®_stat
[j
];
13011 if (rsp
->last_set_invalid
13012 /* If this is a pseudo-register that was only set once and not
13013 live at the beginning of the function, it is always valid. */
13014 || (! (regno
>= FIRST_PSEUDO_REGISTER
13015 && regno
< reg_n_sets_max
13016 && REG_N_SETS (regno
) == 1
13017 && (!REGNO_REG_SET_P
13018 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13020 && rsp
->last_set_label
> tick
))
13023 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13030 /* If this is a memory reference, make sure that there were no stores after
13031 it that might have clobbered the value. We don't have alias info, so we
13032 assume any store invalidates it. Moreover, we only have local UIDs, so
13033 we also assume that there were stores in the intervening basic blocks. */
13034 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13035 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13038 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13042 for (i
= 0; i
< len
; i
++)
13046 /* Check for identical subexpressions. If x contains
13047 identical subexpression we only have to traverse one of
13049 if (i
== 1 && ARITHMETIC_P (x
))
13051 /* Note that at this point x0 has already been checked
13052 and found valid. */
13053 rtx x0
= XEXP (x
, 0);
13054 rtx x1
= XEXP (x
, 1);
13056 /* If x0 and x1 are identical then x is also valid. */
13060 /* If x1 is identical to a subexpression of x0 then
13061 while checking x0, x1 has already been checked. Thus
13062 it is valid and so as x. */
13063 if (ARITHMETIC_P (x0
)
13064 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13067 /* If x0 is identical to a subexpression of x1 then x is
13068 valid iff the rest of x1 is valid. */
13069 if (ARITHMETIC_P (x1
)
13070 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13072 get_last_value_validate (&XEXP (x1
,
13073 x0
== XEXP (x1
, 0) ? 1 : 0),
13074 insn
, tick
, replace
);
13077 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13081 else if (fmt
[i
] == 'E')
13082 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13083 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13084 insn
, tick
, replace
) == 0)
13088 /* If we haven't found a reason for it to be invalid, it is valid. */
13092 /* Get the last value assigned to X, if known. Some registers
13093 in the value may be replaced with (clobber (const_int 0)) if their value
13094 is known longer known reliably. */
13097 get_last_value (const_rtx x
)
13099 unsigned int regno
;
13101 reg_stat_type
*rsp
;
13103 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13104 then convert it to the desired mode. If this is a paradoxical SUBREG,
13105 we cannot predict what values the "extra" bits might have. */
13106 if (GET_CODE (x
) == SUBREG
13107 && subreg_lowpart_p (x
)
13108 && !paradoxical_subreg_p (x
)
13109 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13110 return gen_lowpart (GET_MODE (x
), value
);
13116 rsp
= ®_stat
[regno
];
13117 value
= rsp
->last_set_value
;
13119 /* If we don't have a value, or if it isn't for this basic block and
13120 it's either a hard register, set more than once, or it's a live
13121 at the beginning of the function, return 0.
13123 Because if it's not live at the beginning of the function then the reg
13124 is always set before being used (is never used without being set).
13125 And, if it's set only once, and it's always set before use, then all
13126 uses must have the same last value, even if it's not from this basic
13130 || (rsp
->last_set_label
< label_tick_ebb_start
13131 && (regno
< FIRST_PSEUDO_REGISTER
13132 || regno
>= reg_n_sets_max
13133 || REG_N_SETS (regno
) != 1
13135 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13138 /* If the value was set in a later insn than the ones we are processing,
13139 we can't use it even if the register was only set once. */
13140 if (rsp
->last_set_label
== label_tick
13141 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13144 /* If the value has all its registers valid, return it. */
13145 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13148 /* Otherwise, make a copy and replace any invalid register with
13149 (clobber (const_int 0)). If that fails for some reason, return 0. */
13151 value
= copy_rtx (value
);
13152 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13158 /* Return nonzero if expression X refers to a REG or to memory
13159 that is set in an instruction more recent than FROM_LUID. */
13162 use_crosses_set_p (const_rtx x
, int from_luid
)
13166 enum rtx_code code
= GET_CODE (x
);
13170 unsigned int regno
= REGNO (x
);
13171 unsigned endreg
= END_REGNO (x
);
13173 #ifdef PUSH_ROUNDING
13174 /* Don't allow uses of the stack pointer to be moved,
13175 because we don't know whether the move crosses a push insn. */
13176 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13179 for (; regno
< endreg
; regno
++)
13181 reg_stat_type
*rsp
= ®_stat
[regno
];
13183 && rsp
->last_set_label
== label_tick
13184 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13190 if (code
== MEM
&& mem_last_set
> from_luid
)
13193 fmt
= GET_RTX_FORMAT (code
);
13195 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13200 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13201 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13204 else if (fmt
[i
] == 'e'
13205 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13211 /* Define three variables used for communication between the following
13214 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13215 static int reg_dead_flag
;
13217 /* Function called via note_stores from reg_dead_at_p.
13219 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13220 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13223 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13225 unsigned int regno
, endregno
;
13230 regno
= REGNO (dest
);
13231 endregno
= END_REGNO (dest
);
13232 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13233 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13236 /* Return nonzero if REG is known to be dead at INSN.
13238 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13239 referencing REG, it is dead. If we hit a SET referencing REG, it is
13240 live. Otherwise, see if it is live or dead at the start of the basic
13241 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13242 must be assumed to be always live. */
13245 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13250 /* Set variables for reg_dead_at_p_1. */
13251 reg_dead_regno
= REGNO (reg
);
13252 reg_dead_endregno
= END_REGNO (reg
);
13256 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13257 we allow the machine description to decide whether use-and-clobber
13258 patterns are OK. */
13259 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13261 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13262 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13266 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13267 beginning of basic block. */
13268 block
= BLOCK_FOR_INSN (insn
);
13273 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13276 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13278 return reg_dead_flag
== 1 ? 1 : 0;
13280 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13284 if (insn
== BB_HEAD (block
))
13287 insn
= PREV_INSN (insn
);
13290 /* Look at live-in sets for the basic block that we were in. */
13291 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13292 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13298 /* Note hard registers in X that are used. */
13301 mark_used_regs_combine (rtx x
)
13303 RTX_CODE code
= GET_CODE (x
);
13304 unsigned int regno
;
13315 case ADDR_DIFF_VEC
:
13317 /* CC0 must die in the insn after it is set, so we don't need to take
13318 special note of it here. */
13323 /* If we are clobbering a MEM, mark any hard registers inside the
13324 address as used. */
13325 if (MEM_P (XEXP (x
, 0)))
13326 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13331 /* A hard reg in a wide mode may really be multiple registers.
13332 If so, mark all of them just like the first. */
13333 if (regno
< FIRST_PSEUDO_REGISTER
)
13335 /* None of this applies to the stack, frame or arg pointers. */
13336 if (regno
== STACK_POINTER_REGNUM
13337 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13338 || regno
== HARD_FRAME_POINTER_REGNUM
13340 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13341 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13342 || regno
== FRAME_POINTER_REGNUM
)
13345 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13351 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13353 rtx testreg
= SET_DEST (x
);
13355 while (GET_CODE (testreg
) == SUBREG
13356 || GET_CODE (testreg
) == ZERO_EXTRACT
13357 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13358 testreg
= XEXP (testreg
, 0);
13360 if (MEM_P (testreg
))
13361 mark_used_regs_combine (XEXP (testreg
, 0));
13363 mark_used_regs_combine (SET_SRC (x
));
13371 /* Recursively scan the operands of this expression. */
13374 const char *fmt
= GET_RTX_FORMAT (code
);
13376 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13379 mark_used_regs_combine (XEXP (x
, i
));
13380 else if (fmt
[i
] == 'E')
13384 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13385 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13391 /* Remove register number REGNO from the dead registers list of INSN.
13393 Return the note used to record the death, if there was one. */
13396 remove_death (unsigned int regno
, rtx_insn
*insn
)
13398 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13401 remove_note (insn
, note
);
13406 /* For each register (hardware or pseudo) used within expression X, if its
13407 death is in an instruction with luid between FROM_LUID (inclusive) and
13408 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13409 list headed by PNOTES.
13411 That said, don't move registers killed by maybe_kill_insn.
13413 This is done when X is being merged by combination into TO_INSN. These
13414 notes will then be distributed as needed. */
13417 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13422 enum rtx_code code
= GET_CODE (x
);
13426 unsigned int regno
= REGNO (x
);
13427 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13429 /* Don't move the register if it gets killed in between from and to. */
13430 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13431 && ! reg_referenced_p (x
, maybe_kill_insn
))
13435 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13436 && DF_INSN_LUID (where_dead
) >= from_luid
13437 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13439 rtx note
= remove_death (regno
, where_dead
);
13441 /* It is possible for the call above to return 0. This can occur
13442 when last_death points to I2 or I1 that we combined with.
13443 In that case make a new note.
13445 We must also check for the case where X is a hard register
13446 and NOTE is a death note for a range of hard registers
13447 including X. In that case, we must put REG_DEAD notes for
13448 the remaining registers in place of NOTE. */
13450 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13451 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13452 > GET_MODE_SIZE (GET_MODE (x
))))
13454 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13455 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13456 unsigned int ourend
= END_REGNO (x
);
13459 for (i
= deadregno
; i
< deadend
; i
++)
13460 if (i
< regno
|| i
>= ourend
)
13461 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13464 /* If we didn't find any note, or if we found a REG_DEAD note that
13465 covers only part of the given reg, and we have a multi-reg hard
13466 register, then to be safe we must check for REG_DEAD notes
13467 for each register other than the first. They could have
13468 their own REG_DEAD notes lying around. */
13469 else if ((note
== 0
13471 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13472 < GET_MODE_SIZE (GET_MODE (x
)))))
13473 && regno
< FIRST_PSEUDO_REGISTER
13474 && REG_NREGS (x
) > 1)
13476 unsigned int ourend
= END_REGNO (x
);
13477 unsigned int i
, offset
;
13481 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13485 for (i
= regno
+ offset
; i
< ourend
; i
++)
13486 move_deaths (regno_reg_rtx
[i
],
13487 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13490 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13492 XEXP (note
, 1) = *pnotes
;
13496 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13502 else if (GET_CODE (x
) == SET
)
13504 rtx dest
= SET_DEST (x
);
13506 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13508 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13509 that accesses one word of a multi-word item, some
13510 piece of everything register in the expression is used by
13511 this insn, so remove any old death. */
13512 /* ??? So why do we test for equality of the sizes? */
13514 if (GET_CODE (dest
) == ZERO_EXTRACT
13515 || GET_CODE (dest
) == STRICT_LOW_PART
13516 || (GET_CODE (dest
) == SUBREG
13517 && (((GET_MODE_SIZE (GET_MODE (dest
))
13518 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13519 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13520 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13522 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13526 /* If this is some other SUBREG, we know it replaces the entire
13527 value, so use that as the destination. */
13528 if (GET_CODE (dest
) == SUBREG
)
13529 dest
= SUBREG_REG (dest
);
13531 /* If this is a MEM, adjust deaths of anything used in the address.
13532 For a REG (the only other possibility), the entire value is
13533 being replaced so the old value is not used in this insn. */
13536 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13541 else if (GET_CODE (x
) == CLOBBER
)
13544 len
= GET_RTX_LENGTH (code
);
13545 fmt
= GET_RTX_FORMAT (code
);
13547 for (i
= 0; i
< len
; i
++)
13552 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13553 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13556 else if (fmt
[i
] == 'e')
13557 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13561 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13562 pattern of an insn. X must be a REG. */
13565 reg_bitfield_target_p (rtx x
, rtx body
)
13569 if (GET_CODE (body
) == SET
)
13571 rtx dest
= SET_DEST (body
);
13573 unsigned int regno
, tregno
, endregno
, endtregno
;
13575 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13576 target
= XEXP (dest
, 0);
13577 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13578 target
= SUBREG_REG (XEXP (dest
, 0));
13582 if (GET_CODE (target
) == SUBREG
)
13583 target
= SUBREG_REG (target
);
13585 if (!REG_P (target
))
13588 tregno
= REGNO (target
), regno
= REGNO (x
);
13589 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13590 return target
== x
;
13592 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13593 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13595 return endregno
> tregno
&& regno
< endtregno
;
13598 else if (GET_CODE (body
) == PARALLEL
)
13599 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13600 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13606 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13607 as appropriate. I3 and I2 are the insns resulting from the combination
13608 insns including FROM (I2 may be zero).
13610 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13611 not need REG_DEAD notes because they are being substituted for. This
13612 saves searching in the most common cases.
13614 Each note in the list is either ignored or placed on some insns, depending
13615 on the type of note. */
13618 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13619 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13621 rtx note
, next_note
;
13623 rtx_insn
*tem_insn
;
13625 for (note
= notes
; note
; note
= next_note
)
13627 rtx_insn
*place
= 0, *place2
= 0;
13629 next_note
= XEXP (note
, 1);
13630 switch (REG_NOTE_KIND (note
))
13634 /* Doesn't matter much where we put this, as long as it's somewhere.
13635 It is preferable to keep these notes on branches, which is most
13636 likely to be i3. */
13640 case REG_NON_LOCAL_GOTO
:
13645 gcc_assert (i2
&& JUMP_P (i2
));
13650 case REG_EH_REGION
:
13651 /* These notes must remain with the call or trapping instruction. */
13654 else if (i2
&& CALL_P (i2
))
13658 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13659 if (may_trap_p (i3
))
13661 else if (i2
&& may_trap_p (i2
))
13663 /* ??? Otherwise assume we've combined things such that we
13664 can now prove that the instructions can't trap. Drop the
13665 note in this case. */
13669 case REG_ARGS_SIZE
:
13670 /* ??? How to distribute between i3-i1. Assume i3 contains the
13671 entire adjustment. Assert i3 contains at least some adjust. */
13672 if (!noop_move_p (i3
))
13674 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13675 /* fixup_args_size_notes looks at REG_NORETURN note,
13676 so ensure the note is placed there first. */
13680 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13681 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13685 XEXP (n
, 1) = REG_NOTES (i3
);
13686 REG_NOTES (i3
) = n
;
13690 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13691 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13692 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13693 gcc_assert (old_size
!= args_size
13695 && !ACCUMULATE_OUTGOING_ARGS
13696 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13703 case REG_CALL_DECL
:
13704 /* These notes must remain with the call. It should not be
13705 possible for both I2 and I3 to be a call. */
13710 gcc_assert (i2
&& CALL_P (i2
));
13716 /* Any clobbers for i3 may still exist, and so we must process
13717 REG_UNUSED notes from that insn.
13719 Any clobbers from i2 or i1 can only exist if they were added by
13720 recog_for_combine. In that case, recog_for_combine created the
13721 necessary REG_UNUSED notes. Trying to keep any original
13722 REG_UNUSED notes from these insns can cause incorrect output
13723 if it is for the same register as the original i3 dest.
13724 In that case, we will notice that the register is set in i3,
13725 and then add a REG_UNUSED note for the destination of i3, which
13726 is wrong. However, it is possible to have REG_UNUSED notes from
13727 i2 or i1 for register which were both used and clobbered, so
13728 we keep notes from i2 or i1 if they will turn into REG_DEAD
13731 /* If this register is set or clobbered in I3, put the note there
13732 unless there is one already. */
13733 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13735 if (from_insn
!= i3
)
13738 if (! (REG_P (XEXP (note
, 0))
13739 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13740 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13743 /* Otherwise, if this register is used by I3, then this register
13744 now dies here, so we must put a REG_DEAD note here unless there
13746 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13747 && ! (REG_P (XEXP (note
, 0))
13748 ? find_regno_note (i3
, REG_DEAD
,
13749 REGNO (XEXP (note
, 0)))
13750 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13752 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13760 /* These notes say something about results of an insn. We can
13761 only support them if they used to be on I3 in which case they
13762 remain on I3. Otherwise they are ignored.
13764 If the note refers to an expression that is not a constant, we
13765 must also ignore the note since we cannot tell whether the
13766 equivalence is still true. It might be possible to do
13767 slightly better than this (we only have a problem if I2DEST
13768 or I1DEST is present in the expression), but it doesn't
13769 seem worth the trouble. */
13771 if (from_insn
== i3
13772 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13777 /* These notes say something about how a register is used. They must
13778 be present on any use of the register in I2 or I3. */
13779 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13782 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13791 case REG_LABEL_TARGET
:
13792 case REG_LABEL_OPERAND
:
13793 /* This can show up in several ways -- either directly in the
13794 pattern, or hidden off in the constant pool with (or without?)
13795 a REG_EQUAL note. */
13796 /* ??? Ignore the without-reg_equal-note problem for now. */
13797 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13798 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13799 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13800 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13804 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13805 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13806 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13807 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13815 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13816 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13818 if (place
&& JUMP_P (place
)
13819 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13820 && (JUMP_LABEL (place
) == NULL
13821 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13823 rtx label
= JUMP_LABEL (place
);
13826 JUMP_LABEL (place
) = XEXP (note
, 0);
13827 else if (LABEL_P (label
))
13828 LABEL_NUSES (label
)--;
13831 if (place2
&& JUMP_P (place2
)
13832 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13833 && (JUMP_LABEL (place2
) == NULL
13834 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13836 rtx label
= JUMP_LABEL (place2
);
13839 JUMP_LABEL (place2
) = XEXP (note
, 0);
13840 else if (LABEL_P (label
))
13841 LABEL_NUSES (label
)--;
13847 /* This note says something about the value of a register prior
13848 to the execution of an insn. It is too much trouble to see
13849 if the note is still correct in all situations. It is better
13850 to simply delete it. */
13854 /* If we replaced the right hand side of FROM_INSN with a
13855 REG_EQUAL note, the original use of the dying register
13856 will not have been combined into I3 and I2. In such cases,
13857 FROM_INSN is guaranteed to be the first of the combined
13858 instructions, so we simply need to search back before
13859 FROM_INSN for the previous use or set of this register,
13860 then alter the notes there appropriately.
13862 If the register is used as an input in I3, it dies there.
13863 Similarly for I2, if it is nonzero and adjacent to I3.
13865 If the register is not used as an input in either I3 or I2
13866 and it is not one of the registers we were supposed to eliminate,
13867 there are two possibilities. We might have a non-adjacent I2
13868 or we might have somehow eliminated an additional register
13869 from a computation. For example, we might have had A & B where
13870 we discover that B will always be zero. In this case we will
13871 eliminate the reference to A.
13873 In both cases, we must search to see if we can find a previous
13874 use of A and put the death note there. */
13877 && from_insn
== i2mod
13878 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13879 tem_insn
= from_insn
;
13883 && CALL_P (from_insn
)
13884 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13886 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13888 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13889 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13891 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13893 && reg_overlap_mentioned_p (XEXP (note
, 0),
13895 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13896 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13899 /* If the new I2 sets the same register that is marked dead
13900 in the note, the note now should not be put on I2, as the
13901 note refers to a previous incarnation of the reg. */
13902 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
13908 basic_block bb
= this_basic_block
;
13910 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13912 if (!NONDEBUG_INSN_P (tem_insn
))
13914 if (tem_insn
== BB_HEAD (bb
))
13919 /* If the register is being set at TEM_INSN, see if that is all
13920 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13921 into a REG_UNUSED note instead. Don't delete sets to
13922 global register vars. */
13923 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13924 || !global_regs
[REGNO (XEXP (note
, 0))])
13925 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13927 rtx set
= single_set (tem_insn
);
13928 rtx inner_dest
= 0;
13929 rtx_insn
*cc0_setter
= NULL
;
13932 for (inner_dest
= SET_DEST (set
);
13933 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13934 || GET_CODE (inner_dest
) == SUBREG
13935 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13936 inner_dest
= XEXP (inner_dest
, 0))
13939 /* Verify that it was the set, and not a clobber that
13940 modified the register.
13942 CC0 targets must be careful to maintain setter/user
13943 pairs. If we cannot delete the setter due to side
13944 effects, mark the user with an UNUSED note instead
13947 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13948 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13950 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13951 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13952 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13956 /* Move the notes and links of TEM_INSN elsewhere.
13957 This might delete other dead insns recursively.
13958 First set the pattern to something that won't use
13960 rtx old_notes
= REG_NOTES (tem_insn
);
13962 PATTERN (tem_insn
) = pc_rtx
;
13963 REG_NOTES (tem_insn
) = NULL
;
13965 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13966 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13967 distribute_links (LOG_LINKS (tem_insn
));
13969 SET_INSN_DELETED (tem_insn
);
13970 if (tem_insn
== i2
)
13973 /* Delete the setter too. */
13976 PATTERN (cc0_setter
) = pc_rtx
;
13977 old_notes
= REG_NOTES (cc0_setter
);
13978 REG_NOTES (cc0_setter
) = NULL
;
13980 distribute_notes (old_notes
, cc0_setter
,
13982 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13983 distribute_links (LOG_LINKS (cc0_setter
));
13985 SET_INSN_DELETED (cc0_setter
);
13986 if (cc0_setter
== i2
)
13992 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13994 /* If there isn't already a REG_UNUSED note, put one
13995 here. Do not place a REG_DEAD note, even if
13996 the register is also used here; that would not
13997 match the algorithm used in lifetime analysis
13998 and can cause the consistency check in the
13999 scheduler to fail. */
14000 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14001 REGNO (XEXP (note
, 0))))
14006 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14007 || (CALL_P (tem_insn
)
14008 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14012 /* If we are doing a 3->2 combination, and we have a
14013 register which formerly died in i3 and was not used
14014 by i2, which now no longer dies in i3 and is used in
14015 i2 but does not die in i2, and place is between i2
14016 and i3, then we may need to move a link from place to
14018 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14020 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14021 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14023 struct insn_link
*links
= LOG_LINKS (place
);
14024 LOG_LINKS (place
) = NULL
;
14025 distribute_links (links
);
14030 if (tem_insn
== BB_HEAD (bb
))
14036 /* If the register is set or already dead at PLACE, we needn't do
14037 anything with this note if it is still a REG_DEAD note.
14038 We check here if it is set at all, not if is it totally replaced,
14039 which is what `dead_or_set_p' checks, so also check for it being
14042 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14044 unsigned int regno
= REGNO (XEXP (note
, 0));
14045 reg_stat_type
*rsp
= ®_stat
[regno
];
14047 if (dead_or_set_p (place
, XEXP (note
, 0))
14048 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14050 /* Unless the register previously died in PLACE, clear
14051 last_death. [I no longer understand why this is
14053 if (rsp
->last_death
!= place
)
14054 rsp
->last_death
= 0;
14058 rsp
->last_death
= place
;
14060 /* If this is a death note for a hard reg that is occupying
14061 multiple registers, ensure that we are still using all
14062 parts of the object. If we find a piece of the object
14063 that is unused, we must arrange for an appropriate REG_DEAD
14064 note to be added for it. However, we can't just emit a USE
14065 and tag the note to it, since the register might actually
14066 be dead; so we recourse, and the recursive call then finds
14067 the previous insn that used this register. */
14069 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14071 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14072 bool all_used
= true;
14075 for (i
= regno
; i
< endregno
; i
++)
14076 if ((! refers_to_regno_p (i
, PATTERN (place
))
14077 && ! find_regno_fusage (place
, USE
, i
))
14078 || dead_or_set_regno_p (place
, i
))
14086 /* Put only REG_DEAD notes for pieces that are
14087 not already dead or set. */
14089 for (i
= regno
; i
< endregno
;
14090 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14092 rtx piece
= regno_reg_rtx
[i
];
14093 basic_block bb
= this_basic_block
;
14095 if (! dead_or_set_p (place
, piece
)
14096 && ! reg_bitfield_target_p (piece
,
14099 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14102 distribute_notes (new_note
, place
, place
,
14103 NULL
, NULL_RTX
, NULL_RTX
,
14106 else if (! refers_to_regno_p (i
, PATTERN (place
))
14107 && ! find_regno_fusage (place
, USE
, i
))
14108 for (tem_insn
= PREV_INSN (place
); ;
14109 tem_insn
= PREV_INSN (tem_insn
))
14111 if (!NONDEBUG_INSN_P (tem_insn
))
14113 if (tem_insn
== BB_HEAD (bb
))
14117 if (dead_or_set_p (tem_insn
, piece
)
14118 || reg_bitfield_target_p (piece
,
14119 PATTERN (tem_insn
)))
14121 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14134 /* Any other notes should not be present at this point in the
14136 gcc_unreachable ();
14141 XEXP (note
, 1) = REG_NOTES (place
);
14142 REG_NOTES (place
) = note
;
14146 add_shallow_copy_of_reg_note (place2
, note
);
14150 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14151 I3, I2, and I1 to new locations. This is also called to add a link
14152 pointing at I3 when I3's destination is changed. */
14155 distribute_links (struct insn_link
*links
)
14157 struct insn_link
*link
, *next_link
;
14159 for (link
= links
; link
; link
= next_link
)
14161 rtx_insn
*place
= 0;
14165 next_link
= link
->next
;
14167 /* If the insn that this link points to is a NOTE, ignore it. */
14168 if (NOTE_P (link
->insn
))
14172 rtx pat
= PATTERN (link
->insn
);
14173 if (GET_CODE (pat
) == SET
)
14175 else if (GET_CODE (pat
) == PARALLEL
)
14178 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14180 set
= XVECEXP (pat
, 0, i
);
14181 if (GET_CODE (set
) != SET
)
14184 reg
= SET_DEST (set
);
14185 while (GET_CODE (reg
) == ZERO_EXTRACT
14186 || GET_CODE (reg
) == STRICT_LOW_PART
14187 || GET_CODE (reg
) == SUBREG
)
14188 reg
= XEXP (reg
, 0);
14193 if (REGNO (reg
) == link
->regno
)
14196 if (i
== XVECLEN (pat
, 0))
14202 reg
= SET_DEST (set
);
14204 while (GET_CODE (reg
) == ZERO_EXTRACT
14205 || GET_CODE (reg
) == STRICT_LOW_PART
14206 || GET_CODE (reg
) == SUBREG
)
14207 reg
= XEXP (reg
, 0);
14209 /* A LOG_LINK is defined as being placed on the first insn that uses
14210 a register and points to the insn that sets the register. Start
14211 searching at the next insn after the target of the link and stop
14212 when we reach a set of the register or the end of the basic block.
14214 Note that this correctly handles the link that used to point from
14215 I3 to I2. Also note that not much searching is typically done here
14216 since most links don't point very far away. */
14218 for (insn
= NEXT_INSN (link
->insn
);
14219 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14220 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14221 insn
= NEXT_INSN (insn
))
14222 if (DEBUG_INSN_P (insn
))
14224 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14226 if (reg_referenced_p (reg
, PATTERN (insn
)))
14230 else if (CALL_P (insn
)
14231 && find_reg_fusage (insn
, USE
, reg
))
14236 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14239 /* If we found a place to put the link, place it there unless there
14240 is already a link to the same insn as LINK at that point. */
14244 struct insn_link
*link2
;
14246 FOR_EACH_LOG_LINK (link2
, place
)
14247 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14252 link
->next
= LOG_LINKS (place
);
14253 LOG_LINKS (place
) = link
;
14255 /* Set added_links_insn to the earliest insn we added a
14257 if (added_links_insn
== 0
14258 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14259 added_links_insn
= place
;
14265 /* Check for any register or memory mentioned in EQUIV that is not
14266 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14267 of EXPR where some registers may have been replaced by constants. */
14270 unmentioned_reg_p (rtx equiv
, rtx expr
)
14272 subrtx_iterator::array_type array
;
14273 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14275 const_rtx x
= *iter
;
14276 if ((REG_P (x
) || MEM_P (x
))
14277 && !reg_mentioned_p (x
, expr
))
14283 DEBUG_FUNCTION
void
14284 dump_combine_stats (FILE *file
)
14288 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14289 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14293 dump_combine_total_stats (FILE *file
)
14297 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14298 total_attempts
, total_merges
, total_extras
, total_successes
);
14301 /* Try combining insns through substitution. */
14302 static unsigned int
14303 rest_of_handle_combine (void)
14305 int rebuild_jump_labels_after_combine
;
14307 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14308 df_note_add_problem ();
14311 regstat_init_n_sets_and_refs ();
14312 reg_n_sets_max
= max_reg_num ();
14314 rebuild_jump_labels_after_combine
14315 = combine_instructions (get_insns (), max_reg_num ());
14317 /* Combining insns may have turned an indirect jump into a
14318 direct jump. Rebuild the JUMP_LABEL fields of jumping
14320 if (rebuild_jump_labels_after_combine
)
14322 timevar_push (TV_JUMP
);
14323 rebuild_jump_labels (get_insns ());
14325 timevar_pop (TV_JUMP
);
14328 regstat_free_n_sets_and_refs ();
14334 const pass_data pass_data_combine
=
14336 RTL_PASS
, /* type */
14337 "combine", /* name */
14338 OPTGROUP_NONE
, /* optinfo_flags */
14339 TV_COMBINE
, /* tv_id */
14340 PROP_cfglayout
, /* properties_required */
14341 0, /* properties_provided */
14342 0, /* properties_destroyed */
14343 0, /* todo_flags_start */
14344 TODO_df_finish
, /* todo_flags_finish */
14347 class pass_combine
: public rtl_opt_pass
14350 pass_combine (gcc::context
*ctxt
)
14351 : rtl_opt_pass (pass_data_combine
, ctxt
)
14354 /* opt_pass methods: */
14355 virtual bool gate (function
*) { return (optimize
> 0); }
14356 virtual unsigned int execute (function
*)
14358 return rest_of_handle_combine ();
14361 }; // class pass_combine
14363 } // anon namespace
14366 make_pass_combine (gcc::context
*ctxt
)
14368 return new pass_combine (ctxt
);