1 ;; Scheduling description for Niagara.
2 ;; Copyright (C) 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Niagara is a single-issue processor.
23 (define_automaton "niagara_0")
25 (define_cpu_unit "niag_pipe" "niagara_0")
27 (define_insn_reservation "niag_5cycle" 5
28 (and (eq_attr "cpu" "niagara")
29 (eq_attr "type" "multi,flushw,iflush,trap"))
32 (define_insn_reservation "niag_4cycle" 4
33 (and (eq_attr "cpu" "niagara")
34 (eq_attr "type" "savew"))
37 /* Most basic operations are single-cycle. */
38 (define_insn_reservation "niag_ialu" 1
39 (and (eq_attr "cpu" "niagara")
40 (eq_attr "type" "ialu,shift,compare,cmove"))
43 (define_insn_reservation "niag_imul" 11
44 (and (eq_attr "cpu" "niagara")
45 (eq_attr "type" "imul"))
48 (define_insn_reservation "niag_idiv" 72
49 (and (eq_attr "cpu" "niagara")
50 (eq_attr "type" "idiv"))
53 (define_insn_reservation "niag_branch" 3
54 (and (eq_attr "cpu" "niagara")
55 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
58 (define_insn_reservation "niag_3cycle_load" 3
59 (and (eq_attr "cpu" "niagara")
60 (eq_attr "type" "load"))
63 (define_insn_reservation "niag_9cycle_load" 9
64 (and (eq_attr "cpu" "niagara")
65 (eq_attr "type" "fpload"))
68 (define_insn_reservation "niag_1cycle_store" 1
69 (and (eq_attr "cpu" "niagara")
70 (eq_attr "type" "store"))
73 (define_insn_reservation "niag_8cycle_store" 8
74 (and (eq_attr "cpu" "niagara")
75 (eq_attr "type" "fpstore"))
78 /* Things incorrectly modelled here:
79 * FPADD{s,d}: 26 cycles
80 * FPSUB{s,d}: 26 cycles
82 * F{s,d}TO{s,d}: 26 cycles
83 * F{s,d}TO{i,x}: 26 cycles
86 (define_insn_reservation "niag_fmov" 8
87 (and (eq_attr "cpu" "niagara")
88 (eq_attr "type" "fpmove,fpcmove,fpcrmove"))
91 (define_insn_reservation "niag_fpcmp" 26
92 (and (eq_attr "cpu" "niagara")
93 (eq_attr "type" "fpcmp"))
96 (define_insn_reservation "niag_fmult" 29
97 (and (eq_attr "cpu" "niagara")
98 (eq_attr "type" "fpmul"))
101 (define_insn_reservation "niag_fdivs" 54
102 (and (eq_attr "cpu" "niagara")
103 (eq_attr "type" "fpdivs"))
106 (define_insn_reservation "niag_fdivd" 83
107 (and (eq_attr "cpu" "niagara")
108 (eq_attr "type" "fpdivd"))
111 /* Things incorrectly modelled here:
112 * FPADD{16,32}: 10 cycles
113 * FPSUB{16,32}: 10 cycles
114 * FALIGNDATA: 10 cycles
116 (define_insn_reservation "niag_vis" 8
117 (and (eq_attr "cpu" "niagara")
118 (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))