| blob | da1155395626dae9b7a27c6e0b1147cb103f2c54 |
1 ;; Machine description for Tilera TILE-Gx chip for GCC.
2 ;; Copyright (C) 2011-2013 Free Software Foundation, Inc.
3 ;; Contributed by Walter Lee (walt@tilera.com)
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_constants [
22 ;;
23 ;; The following represent intrinsic insns, organized by latency.
24 ;;
26 ;; single cycle
27 (UNSPEC_INSN_ADDR_SHL16INSLI 1)
28 (UNSPEC_INSN_BFEXTS 2)
29 (UNSPEC_INSN_BFEXTU 3)
30 (UNSPEC_INSN_BFINS 4)
31 (UNSPEC_INSN_CRC32_32 5)
32 (UNSPEC_INSN_CRC32_8 6)
33 (UNSPEC_INSN_DBLALIGN 7)
34 (UNSPEC_INSN_DBLALIGN2 8)
35 (UNSPEC_INSN_DBLALIGN4 9)
36 (UNSPEC_INSN_DBLALIGN6 10)
37 (UNSPEC_INSN_DRAIN 11)
38 (UNSPEC_INSN_DTLBPR 12)
39 (UNSPEC_INSN_FINV 13)
40 (UNSPEC_INSN_FLUSH 14)
41 (UNSPEC_INSN_FLUSHWB 15)
42 (UNSPEC_INSN_FNOP 16)
43 (UNSPEC_INSN_ICOH 17)
44 (UNSPEC_INSN_ILL 18)
45 (UNSPEC_INSN_INFO 19)
46 (UNSPEC_INSN_INFOL 20)
47 (UNSPEC_INSN_INV 21)
48 (UNSPEC_INSN_LNK 22)
49 (UNSPEC_INSN_MFSPR 23)
50 (UNSPEC_INSN_MM 24)
51 (UNSPEC_INSN_MTSPR 25)
52 (UNSPEC_INSN_NAP 26)
53 (UNSPEC_INSN_PREFETCH_L1_FAULT 27)
54 (UNSPEC_INSN_PREFETCH_L2_FAULT 28)
55 (UNSPEC_INSN_PREFETCH_L3_FAULT 29)
56 (UNSPEC_INSN_REVBITS 30)
57 (UNSPEC_INSN_SHUFFLEBYTES 31)
58 (UNSPEC_INSN_TBLIDXB0 32)
59 (UNSPEC_INSN_TBLIDXB1 33)
60 (UNSPEC_INSN_TBLIDXB2 34)
61 (UNSPEC_INSN_TBLIDXB3 35)
62 (UNSPEC_INSN_V1AVGU 36)
63 (UNSPEC_INSN_V2AVGS 37)
64 (UNSPEC_INSN_WH64 38)
66 ;; 2 cycles
67 (UNSPEC_INSN_CMUL 100)
68 (UNSPEC_INSN_CMULA 101)
69 (UNSPEC_INSN_CMULAF 102)
70 (UNSPEC_INSN_CMULFR 103)
71 (UNSPEC_INSN_CMULHR 104)
72 (UNSPEC_INSN_CMULF 105)
73 (UNSPEC_INSN_CMULH 106)
74 (UNSPEC_INSN_EXCH 107)
75 (UNSPEC_INSN_FDOUBLE_ADDSUB 108)
76 (UNSPEC_INSN_FDOUBLE_ADD_FLAGS 109)
77 (UNSPEC_INSN_FDOUBLE_MUL_FLAGS 110)
78 (UNSPEC_INSN_FDOUBLE_PACK1 111)
79 (UNSPEC_INSN_FDOUBLE_PACK2 112)
80 (UNSPEC_INSN_FDOUBLE_SUB_FLAGS 113)
81 (UNSPEC_INSN_FDOUBLE_UNPACK_MAX 114)
82 (UNSPEC_INSN_FDOUBLE_UNPACK_MIN 115)
83 (UNSPEC_INSN_FETCHADDGEZ 116)
84 (UNSPEC_INSN_FSINGLE_ADD1 117)
85 (UNSPEC_INSN_FSINGLE_ADDSUB2 118)
86 (UNSPEC_INSN_FSINGLE_MUL1 119)
87 (UNSPEC_INSN_FSINGLE_MUL2 120)
88 (UNSPEC_INSN_FSINGLE_PACK1 121)
89 (UNSPEC_INSN_FSINGLE_PACK2 122)
90 (UNSPEC_INSN_FSINGLE_SUB1 123)
91 (UNSPEC_INSN_MULAX 124)
92 (UNSPEC_INSN_MULA_HS_HS 125)
93 (UNSPEC_INSN_MULA_HS_HU 126)
94 (UNSPEC_INSN_MULA_HS_LS 127)
95 (UNSPEC_INSN_MULA_HS_LU 128)
96 (UNSPEC_INSN_MULA_HU_HU 129)
97 (UNSPEC_INSN_MULA_HU_LS 130)
98 (UNSPEC_INSN_MULA_HU_LU 131)
99 (UNSPEC_INSN_MULA_LS_LS 132)
100 (UNSPEC_INSN_MULA_LS_LU 133)
101 (UNSPEC_INSN_MULA_LU_LU 134)
102 (UNSPEC_INSN_MUL_HS_HS 135)
103 (UNSPEC_INSN_MUL_HS_HU 136)
104 (UNSPEC_INSN_MUL_HS_LS 137)
105 (UNSPEC_INSN_MUL_HS_LU 138)
106 (UNSPEC_INSN_MUL_HU_HU 139)
107 (UNSPEC_INSN_MUL_HU_LS 140)
108 (UNSPEC_INSN_MUL_HU_LU 141)
109 (UNSPEC_INSN_MUL_LS_LS 142)
110 (UNSPEC_INSN_MUL_LS_LU 143)
111 (UNSPEC_INSN_MUL_LU_LU 144)
112 (UNSPEC_INSN_V1ADIFFU 145)
113 (UNSPEC_INSN_V1DDOTPU 146)
114 (UNSPEC_INSN_V1DDOTPUA 147)
115 (UNSPEC_INSN_V1DDOTPUS 148)
116 (UNSPEC_INSN_V1DDOTPUSA 149)
117 (UNSPEC_INSN_V1DOTP 150)
118 (UNSPEC_INSN_V1DOTPA 151)
119 (UNSPEC_INSN_V1DOTPU 152)
120 (UNSPEC_INSN_V1DOTPUA 153)
121 (UNSPEC_INSN_V1DOTPUS 154)
122 (UNSPEC_INSN_V1DOTPUSA 155)
123 (UNSPEC_INSN_V1SADAU 156)
124 (UNSPEC_INSN_V1SADU 157)
125 (UNSPEC_INSN_V2ADIFFS 158)
126 (UNSPEC_INSN_V2DOTP 159)
127 (UNSPEC_INSN_V2DOTPA 160)
128 (UNSPEC_INSN_V2MULFSC 161)
129 (UNSPEC_INSN_V2SADAS 162)
130 (UNSPEC_INSN_V2SADAU 163)
131 (UNSPEC_INSN_V2SADS 164)
132 (UNSPEC_INSN_V2SADU 165)
134 ;; 11 cycles
135 (UNSPEC_INSN_CMPEXCH 200)
137 ;;
138 ;; The following are special insns.
139 ;;
141 ;; Blockage
142 (UNSPEC_BLOCKAGE 201)
144 ;; Lnk and its label
145 (UNSPEC_LNK_AND_LABEL 202)
147 ;; Memory fence
148 (UNSPEC_MF 203)
150 ;; Insns generating difference of two labels
151 (UNSPEC_MOV_PCREL_STEP3 204)
152 (UNSPEC_MOV_LARGE_PCREL_STEP4 205)
154 ;; Latency specifying loads.
155 (UNSPEC_LATENCY_L2 206)
156 (UNSPEC_LATENCY_MISS 207)
158 ;; A pseudo-op that prevents network operations from being ordered.
159 (UNSPEC_NETWORK_BARRIER 208)
161 ;; Operations that access network registers.
162 (UNSPEC_NETWORK_RECEIVE 209)
163 (UNSPEC_NETWORK_SEND 210)
165 ;; Stack protector operations
166 (UNSPEC_SP_SET 211)
167 (UNSPEC_SP_TEST 212)
169 ;; This is used to move a value to a SPR.
170 (UNSPEC_SPR_MOVE 213)
172 ;; A call to __tls_get_addr
173 (UNSPEC_TLS_GD_CALL 214)
175 ;; An opaque TLS "add" operation for TLS general dynamic model
176 ;; access.
177 (UNSPEC_TLS_GD_ADD 215)
179 ;; An opaque TLS "load" operation for TLS initial exec model access.
180 (UNSPEC_TLS_IE_LOAD 216)
182 ;; An opaque TLS "add" operation for TLS access.
183 (UNSPEC_TLS_ADD 217)
185 ;; Atomics
186 (UNSPEC_ATOMIC 218)
187 (UNSPEC_CMPXCHG 219)
188 (UNSPEC_XCHG 220)
190 ;;
191 ;; The following are operands.
192 ;;
193 (UNSPEC_HW0 300)
194 (UNSPEC_HW1 301)
195 (UNSPEC_HW2 302)
196 (UNSPEC_HW3 303)
197 (UNSPEC_HW0_LAST 304)
198 (UNSPEC_HW1_LAST 305)
199 (UNSPEC_HW2_LAST 306)
201 (UNSPEC_HW0_PCREL 307)
202 (UNSPEC_HW1_PCREL 308)
203 (UNSPEC_HW1_LAST_PCREL 309)
204 (UNSPEC_HW2_LAST_PCREL 310)
206 (UNSPEC_HW0_GOT 311)
207 (UNSPEC_HW0_LAST_GOT 312)
208 (UNSPEC_HW1_LAST_GOT 313)
210 (UNSPEC_HW0_TLS_GD 314)
211 (UNSPEC_HW1_LAST_TLS_GD 315)
213 (UNSPEC_HW0_TLS_IE 316)
214 (UNSPEC_HW1_LAST_TLS_IE 317)
216 (UNSPEC_HW0_TLS_LE 318)
217 (UNSPEC_HW1_LAST_TLS_LE 319)
219 (UNSPEC_HW0_PLT_PCREL 320)
220 (UNSPEC_HW1_PLT_PCREL 321)
222 (UNSPEC_HW1_LAST_PLT_PCREL 322)
223 (UNSPEC_HW2_LAST_PLT_PCREL 323)
225 ;; This is used to wrap around the addresses of non-temporal load/store
226 ;; intrinsics.
227 (UNSPEC_NON_TEMPORAL 324)
228 ])
230 ;; Mark the last instruction of various latencies, used to
231 ;; determine the rtx costs of unspec insns.
232 (define_constants [
233 (TILEGX_LAST_LATENCY_1_INSN 99)
234 (TILEGX_LAST_LATENCY_2_INSN 199)
235 (TILEGX_LAST_LATENCY_INSN 299)
236 ])
238 (define_constants [
239 (TILEGX_NETREG_IDN0 0)
240 (TILEGX_NETREG_IDN1 1)
241 (TILEGX_NETREG_UDN0 2)
242 (TILEGX_NETREG_UDN1 3)
243 (TILEGX_NETREG_UDN2 4)
244 (TILEGX_NETREG_UDN3 5)
245 ])
247 (define_constants [
248 (TILEGX_CMPEXCH_REG 66)
249 (TILEGX_NETORDER_REG 67)
250 ])
253 ;; Operand and operator predicates and constraints
255 (include "predicates.md")
256 (include "constraints.md")
257 (include "tilegx-generic.md")
259 ;; Define an insn type attribute. This defines what pipes things can go in.
260 (define_attr "type"
261 "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_remote,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing"
262 (const_string "Y01"))
264 (define_attr "length" ""
265 (cond [(eq_attr "type" "X1_branch")
266 (if_then_else
267 (and (le (minus (match_dup 0) (pc)) (const_int 524280))
268 (le (minus (pc) (match_dup 0)) (const_int 524288)))
269 (const_int 8)
270 (const_int 16))
271 ]
272 (const_int 8)))
275 ;; Define some iterators.
276 (define_mode_iterator IVMODE [SI DI V8QI V4HI V2SI])
277 (define_mode_iterator IVNMODE [SI V8QI V4HI V2SI])
278 (define_mode_iterator I48MODE [SI DI])
279 (define_mode_iterator I48MODE2 [SI DI])
280 (define_mode_iterator I124MODE [QI HI SI])
281 (define_mode_iterator FI48MODE [SF DF SI DI])
282 (define_mode_iterator VEC48MODE [V8QI V4HI])
283 (define_mode_iterator VEC248MODE [V8QI V4HI V2SI])
285 (define_mode_attr n [(QI "1") (HI "2") (SI "4") (DI "")
286 (V8QI "1") (V4HI "2") (V2SI "4")])
287 (define_mode_attr x [(SI "x") (DI "")])
288 (define_mode_attr bitsuffix [(SI "_32bit") (DI "")])
289 (define_mode_attr four_if_si [(SI "4") (DI "")])
290 (define_mode_attr four_s_if_si [(SI "4s") (DI "")])
291 (define_mode_attr nbits [(SI "5") (DI "6")])
292 (define_mode_attr shift_pipe [(SI "X01") (DI "*")])
294 ;; Code iterator for either extend.
295 (define_code_iterator any_extend [sign_extend zero_extend])
297 ;; Code iterator for all three shifts.
298 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
300 ;; Code iterator for all byte ops without immediate variants.
301 (define_code_iterator v1op [us_minus us_plus minus ne le leu mult])
303 ;; Code iterator for all 2-byte vector ops without immediate variants.
304 (define_code_iterator v2op [ss_minus ss_plus minus ne le leu])
306 ;; Code iterator for all 4-byte vector ops without immediate variants.
307 (define_code_iterator v4op [ss_minus ss_plus minus plus])
309 ;; Code iterator for all byte vector ops with immediate variants.
310 (define_code_iterator v1op_immed [plus umax umin eq lt ltu])
312 ;; Code iterator for all 2-byte vector ops with immediate variants.
313 (define_code_iterator v2op_immed [plus smax smin eq lt ltu])
315 ;; Code iterator for all 2-byte vector shifts without immediate variants.
316 (define_code_iterator v2shift [ss_ashift])
318 ;; Code iterator for all 4-byte vector shifts without immediate variants.
319 (define_code_iterator v4shift [ashift ashiftrt lshiftrt ss_ashift])
321 ;; <optab> expands to the name of the optab for a particular code.
322 (define_code_attr optab [(ashift "ashl")
323 (ashiftrt "ashr")
324 (lshiftrt "lshr")
325 (ss_ashift "ssashl")
326 (eq "seq")
327 (ne "sne")
328 (lt "slt")
329 (ltu "sltu")
330 (le "sle")
331 (leu "sleu")
332 (minus "sub")
333 (plus "add")
334 (mult "mul")
335 (smax "smax")
336 (smin "smin")
337 (ss_minus "sssub")
338 (ss_plus "ssadd")
339 (umax "umax")
340 (umin "umin")
341 (us_minus "ussub")
342 (us_plus "usadd")
343 ])
345 ;; <insn> expands to the name of the insn that implements a particular
346 ;; code.
347 (define_code_attr insn [(ashift "shl")
348 (ashiftrt "shrs")
349 (lshiftrt "shru")
350 (ss_ashift "shlsc")
351 (eq "cmpeq")
352 (ne "cmpne")
353 (lt "cmplts")
354 (ltu "cmpltu")
355 (le "cmples")
356 (leu "cmpleu")
357 (minus "sub")
358 (plus "add")
359 (mult "multu")
360 (smax "maxs")
361 (smin "mins")
362 (umax "maxu")
363 (umin "minu")
364 (ss_minus "subsc")
365 (ss_plus "addsc")
366 (us_minus "subuc")
367 (us_plus "adduc")
368 ])
370 ;; <pipe> expands to the pipeline resource that contains the
371 ;; particular code.
372 (define_code_attr pipe [(ashift "X01")
373 (ashiftrt "X01")
374 (lshiftrt "X01")
375 (ss_ashift "X01")
376 (eq "X01")
377 (ne "X01")
378 (lt "X01")
379 (ltu "X01")
380 (le "X01")
381 (leu "X01")
382 (minus "X01")
383 (plus "X01")
384 (mult "X0_2cycle")
385 (smax "X01")
386 (smin "X01")
387 (umax "X01")
388 (umin "X01")
389 (ss_minus "X01")
390 (ss_plus "X01")
391 (us_minus "X01")
392 (us_plus "X01")
393 ])
395 ;; <comm> indicates whether a particular code is commutative, using
396 ;; the "%" commutative opterator constraint.
397 (define_code_attr comm [(ashift "")
398 (ashiftrt "")
399 (lshiftrt "")
400 (ss_ashift "")
401 (eq "%")
402 (ne "%")
403 (lt "")
404 (ltu "")
405 (le "")
406 (leu "")
407 (minus "")
408 (plus "%")
409 (mult "%")
410 (smin "%")
411 (umin "%")
412 (smax "%")
413 (umax "%")
414 (ss_plus "%")
415 (us_plus "%")
416 (ss_minus "")
417 (us_minus "")
418 ])
420 ;; <s> is the load/store extension suffix.
421 (define_code_attr s [(zero_extend "u")
422 (sign_extend "s")])
424 ;; Code for packing two 2-byte vectors.
425 (define_code_iterator v2pack [truncate us_truncate])
427 ;; <pack_optab> expands to the part of the optab name describing how
428 ;; two vectors are packed.
429 (define_code_attr pack_optab [(truncate "trunc")
430 (us_truncate "usat")
431 (ss_truncate "ssat")])
433 ;; <pack_insn> expands to the insn that implements a particular vector
434 ;; packing code.
435 (define_code_attr pack_insn [(truncate "packl")
436 (us_truncate "packuc")
437 (ss_truncate "packsc")])
438 \f
439 ;;
440 ;; The basic data move insns.
441 ;;
443 (define_expand "movqi"
444 [(set (match_operand:QI 0 "nonimmediate_operand" "")
445 (match_operand:QI 1 "nonautoinc_operand" ""))]
446 ""
447 {
448 if (tilegx_expand_mov (QImode, operands))
449 DONE;
450 })
452 (define_insn "*movqi_insn"
453 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,U,m")
454 (match_operand:QI 1 "move_operand" "r,I,U,m,rO,rO"))]
455 "(register_operand (operands[0], QImode)
456 || reg_or_0_operand (operands[1], QImode))"
457 "@
458 move\t%0, %r1
459 movei\t%0, %1
460 ld1u\t%0, %1
461 ld1u_add\t%0, %I1, %i1
462 st1\t%0, %r1
463 st1_add\t%I0, %r1, %i0"
464 [(set_attr "type" "*,*,Y2_2cycle,X1_2cycle,Y2,X1")])
466 (define_expand "movhi"
467 [(set (match_operand:HI 0 "nonimmediate_operand" "")
468 (match_operand:HI 1 "nonautoinc_operand" ""))]
469 ""
470 {
471 if (tilegx_expand_mov (HImode, operands))
472 DONE;
473 })
475 (define_insn "*movhi_insn"
476 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,U,m")
477 (match_operand:HI 1 "move_operand" "r,I,JT,U,m,rO,rO"))]
478 "(register_operand (operands[0], HImode)
479 || reg_or_0_operand (operands[1], HImode))"
480 "@
481 move\t%0, %r1
482 movei\t%0, %1
483 moveli\t%0, %H1
484 ld2u\t%0, %1
485 ld2u_add\t%0, %I1, %i1
486 st2\t%0, %r1
487 st2_add\t%I0, %r1, %i0"
488 [(set_attr "type" "*,*,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
490 (define_expand "movsi"
491 [(set (match_operand:SI 0 "nonimmediate_operand" "")
492 (match_operand:SI 1 "nonautoinc_operand" ""))]
493 ""
494 {
495 if (tilegx_expand_mov (SImode, operands))
496 DONE;
497 })
499 (define_insn "*movsi_insn"
500 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,U,m")
501 (match_operand:SI 1 "move_operand" "r,I,JT,K,U,m,rO,rO"))]
502 "(register_operand (operands[0], SImode)
503 || reg_or_0_operand (operands[1], SImode))"
504 "@
505 move\t%0, %r1
506 movei\t%0, %1
507 moveli\t%0, %H1
508 shl16insli\t%0, zero, %h1
509 ld4s\t%0, %1
510 ld4s_add\t%0, %I1, %i1
511 st4\t%0, %r1
512 st4_add\t%I0, %r1, %i0"
513 [(set_attr "type" "*,*,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
515 (define_expand "movdi"
516 [(set (match_operand:DI 0 "nonimmediate_operand" "")
517 (match_operand:DI 1 "nonautoinc_operand" ""))]
518 ""
519 {
520 if (tilegx_expand_mov (DImode, operands))
521 DONE;
522 })
524 (define_insn "*movdi_insn"
525 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,r,U,m")
526 (match_operand:DI 1 "move_operand" "r,I,JT,K,N,P,U,m,rO,rO"))]
527 "(register_operand (operands[0], DImode)
528 || reg_or_0_operand (operands[1], DImode))"
529 "@
530 move\t%0, %r1
531 movei\t%0, %1
532 moveli\t%0, %H1
533 shl16insli\t%0, zero, %h1
534 v1addi\t%0, zero, %j1
535 v2addi\t%0, zero, %h1
536 ld\t%0, %1
537 ld_add\t%0, %I1, %i1
538 st\t%0, %r1
539 st_add\t%I0, %r1, %i0"
540 [(set_attr "type" "*,*,X01,X01,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
542 (define_expand "movmisalign<mode>"
543 [(set (match_operand:VEC248MODE 0 "nonautoincmem_nonimmediate_operand" "")
544 (match_operand:VEC248MODE 1 "nonautoincmem_general_operand" ""))]
545 ""
546 {
547 tilegx_expand_movmisalign (<MODE>mode, operands);
548 DONE;
549 })
551 (define_expand "movsf"
552 [(set (match_operand:SF 0 "nonimmediate_operand" "")
553 (match_operand:SF 1 "general_operand" ""))]
554 ""
555 {
556 /* Materialize immediates using clever SImode code, but don't
557 do this after reload starts, since gen_lowpart will choke
558 during reload if given an illegitimate address. */
559 if (immediate_operand (operands[1], SFmode)
560 && operands[1] != const0_rtx
561 && (register_operand (operands[0], SFmode)
562 || (!reload_in_progress && !reload_completed)))
563 {
564 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
565 gen_lowpart (SImode, operands[1])));
566 DONE;
567 }
568 })
570 (define_insn "*movsf"
571 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,U,m")
572 (match_operand:SF 1 "general_operand" "rO,U,m,rO,rO"))]
573 ""
574 "@
575 move\t%0, %r1
576 ld4s\t%0, %1
577 ld4s_add\t%0, %I1, %i1
578 st4\t%0, %r1
579 st4_add\t%I0, %r1, %i0"
580 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
582 (define_expand "movdf"
583 [(set (match_operand:DF 0 "nonimmediate_operand" "")
584 (match_operand:DF 1 "general_operand" ""))]
585 ""
586 {
587 /* Materialize immediates using clever DImode code, but don't
588 do this after reload starts, since gen_lowpart will choke
589 during reload if given an illegitimate address. */
590 if (immediate_operand (operands[1], DFmode)
591 && operands[1] != const0_rtx
592 && (register_operand (operands[0], DFmode)
593 || (!reload_in_progress && !reload_completed)))
594 {
595 emit_insn (gen_movdi (gen_lowpart (DImode, operands[0]),
596 gen_lowpart (DImode, operands[1])));
597 DONE;
598 }
599 })
601 (define_insn "*movdf"
602 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,r,U,m")
603 (match_operand:DF 1 "general_operand" "rO,U,m,rO,rO"))]
604 ""
605 "@
606 move\t%0, %r1
607 ld\t%0, %1
608 ld_add\t%0, %I1, %i1
609 st\t%0, %r1
610 st_add\t%I0, %r1, %i0"
611 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
613 (define_expand "mov<mode>"
614 [(set (match_operand:VEC248MODE 0 "nonimmediate_operand" "")
615 (match_operand:VEC248MODE 1 "general_operand" ""))]
616 ""
617 {
618 /* Materialize immediates using clever DImode code, but don't
619 do this after reload starts, since gen_lowpart will choke
620 during reload if given an illegitimate address. */
621 if (immediate_operand (operands[1], <MODE>mode)
622 && operands[1] != const0_rtx
623 && (register_operand (operands[0], <MODE>mode)
624 || (!reload_in_progress && !reload_completed)))
625 {
626 emit_insn (gen_movdi (gen_lowpart (DImode, operands[0]),
627 gen_lowpart (DImode, operands[1])));
628 DONE;
629 }
630 })
632 (define_insn "*mov<mode>"
633 [(set (match_operand:VEC248MODE 0 "nonimmediate_operand" "=r,r,r,U,m")
634 (match_operand:VEC248MODE 1 "general_operand" "rO,U,m,rO,rO"))]
635 ""
636 "@
637 move\t%0, %r1
638 ld\t%0, %1
639 ld_add\t%0, %I1, %i1
640 st\t%0, %r1
641 st_add\t%I0, %r1, %i0"
642 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
644 (define_insn "movstrictqi"
645 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
646 (match_operand:QI 1 "reg_or_0_operand" "rO"))]
647 ""
648 "bfins\t%0, %r1, 0, 7"
649 [(set_attr "type" "X0")])
651 (define_insn "movstricthi"
652 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
653 (match_operand:HI 1 "reg_or_0_operand" "rO"))]
654 ""
655 "bfins\t%0, %r1, 0, 15"
656 [(set_attr "type" "X0")])
658 (define_insn "movstrictsi"
659 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+r"))
660 (match_operand:SI 1 "reg_or_0_operand" "rO"))]
661 ""
662 "bfins\t%0, %r1, 0, 31"
663 [(set_attr "type" "X0")])
665 \f
666 ;;
667 ;; Bit-field extracts/inserts
668 ;;
670 (define_expand "insv"
671 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
672 (match_operand:DI 1 "u6bit_cint_operand" "")
673 (match_operand:DI 2 "u6bit_cint_operand" ""))
674 (match_operand:DI 3 "reg_or_cint_operand" ""))]
675 ""
676 {
677 rtx first_rtx = operands[2];
678 HOST_WIDE_INT first = INTVAL (first_rtx);
679 HOST_WIDE_INT width = INTVAL (operands[1]);
680 rtx v = operands[3];
682 if (CONST_INT_P (v))
683 {
684 /* Which bits are we affecting? */
685 HOST_WIDE_INT mask = ((((HOST_WIDE_INT) 1) << width) - 1) << first;
687 /* Extract just the bits we need, sign extending them to make the
688 constant easier to materialize in a register. */
689 int shift = sizeof(HOST_WIDE_INT) * 8 - width;
690 HOST_WIDE_INT n = (INTVAL (v) << shift) >> shift;
692 if (n == 0)
693 {
694 /* We are setting every bit in the bitfield to zero. Try to use
695 andi instead, since that is more efficient. */
696 rtx mask_rtx = GEN_INT (~mask);
697 if (satisfies_constraint_I (mask_rtx))
698 {
699 emit_insn (gen_anddi3 (operands[0], operands[0], mask_rtx));
700 DONE;
701 }
703 operands[3] = const0_rtx;
704 }
705 else
706 {
707 if (n == -1)
708 {
709 /* We are setting every bit in the bitfield to one. Try to use
710 ori instead, since that is more efficient. */
711 rtx mask_rtx = GEN_INT (mask);
712 if (satisfies_constraint_I (mask_rtx))
713 {
714 emit_insn (gen_iordi3 (operands[0], operands[0], mask_rtx));
715 DONE;
716 }
717 }
719 if (!can_create_pseudo_p ())
720 FAIL;
722 operands[3] = force_reg (DImode, GEN_INT (n));
723 }
724 }
725 })
727 (define_insn "*insv_tblidxb0"
728 [(set (zero_extract:DI
729 (match_operand:DI 0 "register_operand" "+r")
730 (const_int 8)
731 (const_int 2))
732 (match_operand:DI 1 "register_operand" "rO"))]
733 ""
734 "tblidxb0\t%0, %r1"
735 [(set_attr "type" "Y0")])
737 (define_insn "*insv_tblidxb1"
738 [(set (zero_extract:DI
739 (match_operand:DI 0 "register_operand" "+r")
740 (const_int 8)
741 (const_int 2))
742 (zero_extract:DI
743 (const_int 8)
744 (const_int 8)
745 (match_operand:DI 1 "register_operand" "rO")))]
746 ""
747 "tblidxb1\t%0, %r1"
748 [(set_attr "type" "Y0")])
750 (define_insn "*insv_tblidxb2"
751 [(set (zero_extract:DI
752 (match_operand:DI 0 "register_operand" "+r")
753 (const_int 8)
754 (const_int 2))
755 (zero_extract:DI
756 (const_int 8)
757 (const_int 16)
758 (match_operand:DI 1 "register_operand" "rO")))]
759 ""
760 "tblidxb2\t%0, %r1"
761 [(set_attr "type" "Y0")])
763 (define_insn "*insv_tblidxb3"
764 [(set (zero_extract:DI
765 (match_operand:DI 0 "register_operand" "+r")
766 (const_int 8)
767 (const_int 2))
768 (zero_extract:DI
769 (const_int 8)
770 (const_int 24)
771 (match_operand:DI 1 "register_operand" "rO")))]
772 ""
773 "tblidxb3\t%0, %r1"
774 [(set_attr "type" "Y0")])
776 (define_insn "*insv_bfins"
777 [(set (zero_extract:DI
778 (match_operand:DI 0 "register_operand" "+r")
779 (match_operand:DI 1 "u6bit_cint_operand" "n")
780 (match_operand:DI 2 "u6bit_cint_operand" "n"))
781 (match_operand:DI 3 "reg_or_cint_operand" "rO"))]
782 ""
783 "bfins\t%0, %r3, %2, %2+%1-1"
784 [(set_attr "type" "X0")])
786 (define_insn "*insv_mm"
787 [(set (zero_extract:DI
788 (match_operand:DI 0 "register_operand" "+r")
789 (match_operand:DI 1 "u6bit_cint_operand" "n")
790 (match_operand:DI 2 "u6bit_cint_operand" "n"))
791 (zero_extract:DI
792 (match_operand:DI 3 "register_operand" "rO")
793 (match_dup 1)
794 (match_dup 2)))]
795 ""
796 {
797 int n;
799 operands[1] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]));
801 n = INTVAL (operands[2]);
802 n = (n == 0) ? 63 : n - 1;
803 operands[2] = GEN_INT (n);
805 return "mm\t%0, %r3, %1, %2";
806 }
807 [(set_attr "type" "X0")])
809 (define_expand "extv"
810 [(set (match_operand:DI 0 "register_operand" "")
811 (sign_extract:DI (match_operand 1 "nonautoincmem_general_operand" "")
812 (match_operand:DI 2 "immediate_operand" "")
813 (match_operand:DI 3 "immediate_operand" "")))]
814 ""
815 {
816 if (MEM_P (operands[1]))
817 {
818 HOST_WIDE_INT bit_offset, bit_width;
819 HOST_WIDE_INT first_byte_offset, last_byte_offset;
821 if (GET_MODE (operands[1]) != QImode)
822 FAIL;
824 bit_width = INTVAL (operands[2]);
825 bit_offset = INTVAL (operands[3]);
827 /* Reject bitfields that can be done with a normal load. */
828 if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
829 FAIL;
831 /* The value in memory cannot span more than 8 bytes. */
832 first_byte_offset = bit_offset / BITS_PER_UNIT;
833 last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
834 if (last_byte_offset - first_byte_offset > 7)
835 FAIL;
837 tilegx_expand_unaligned_load (operands[0], operands[1],
838 bit_width, bit_offset, 1);
840 DONE;
841 }
843 operands[1] = force_reg (DImode, operands[1]);
844 })
846 (define_expand "extzv"
847 [(set (match_operand:DI 0 "register_operand" "")
848 (zero_extract:DI (match_operand 1 "nonautoincmem_general_operand" "")
849 (match_operand:DI 2 "immediate_operand" "")
850 (match_operand:DI 3 "immediate_operand" "")))]
851 ""
852 {
853 HOST_WIDE_INT bit_width = INTVAL (operands[2]);
854 HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
856 if (MEM_P (operands[1]))
857 {
858 HOST_WIDE_INT first_byte_offset, last_byte_offset;
860 if (GET_MODE (operands[1]) != QImode)
861 FAIL;
863 /* Reject bitfields that can be done with a normal load. */
864 if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
865 FAIL;
867 /* The value in memory cannot span more than 8 bytes. */
868 first_byte_offset = bit_offset / BITS_PER_UNIT;
869 last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
870 if (last_byte_offset - first_byte_offset > 7)
871 FAIL;
873 tilegx_expand_unaligned_load (operands[0], operands[1],
874 bit_width, bit_offset, 0);
876 DONE;
877 }
879 operands[1] = force_reg (DImode, operands[1]);
881 if (bit_offset == 0)
882 {
883 /* Extracting the low bits is just a bitwise AND. */
884 HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << bit_width) - 1;
885 emit_insn (gen_anddi3 (operands[0], operands[1], GEN_INT (mask)));
886 DONE;
887 }
888 })
890 \f
891 ;;
892 ;; Addresses
893 ;;
895 ;; The next three patterns are used to to materialize a position
896 ;; independent address by adding the difference of two labels to a base
897 ;; label in the text segment, assuming that the difference fits in 32
898 ;; signed bits.
899 (define_expand "mov_address_step1"
900 [(set (match_operand:DI 0 "register_operand" "")
901 (const:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
902 UNSPEC_HW2_LAST)))])
904 (define_expand "mov_address_step2"
905 [(set (match_operand:DI 0 "register_operand" "")
906 (unspec:DI
907 [(match_operand:DI 1 "reg_or_0_operand" "")
908 (const:DI (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
909 UNSPEC_HW1))]
910 UNSPEC_INSN_ADDR_SHL16INSLI))])
912 (define_expand "mov_address_step3"
913 [(set (match_operand:DI 0 "register_operand" "")
914 (unspec:DI
915 [(match_operand:DI 1 "reg_or_0_operand" "")
916 (const:DI (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
917 UNSPEC_HW0))]
918 UNSPEC_INSN_ADDR_SHL16INSLI))])
920 ;; First step of the 2-insn sequence to materialize a 32-bit symbolic
921 ;; address.
922 (define_expand "mov_address_32bit_step1"
923 [(set (match_operand:SI 0 "register_operand" "")
924 (const:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "")]
925 UNSPEC_HW1_LAST)))])
927 ;; Second step of the 2-insn sequence to materialize a 32-bit symbolic
928 ;; address.
929 (define_expand "mov_address_32bit_step2"
930 [(set (match_operand:SI 0 "register_operand" "")
931 (unspec:SI
932 [(match_operand:SI 1 "reg_or_0_operand" "")
933 (const:SI (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")]
934 UNSPEC_HW0))]
935 UNSPEC_INSN_ADDR_SHL16INSLI))])
937 \f
938 ;;
939 ;; pic related instructions
940 ;;
942 ;; NOTE: We compute the label in this unusual way because if we place
943 ;; the label after the lnk, whether it is at the same address as the
944 ;; lnk will vary depending on whether the optimization level chooses
945 ;; to insert bundling braces.
946 (define_insn "insn_lnk_and_label<bitsuffix>"
947 [(set (match_operand:I48MODE 0 "register_operand" "=r")
948 (unspec_volatile:I48MODE
949 [(match_operand:I48MODE 1 "symbolic_operand" "")]
950 UNSPEC_LNK_AND_LABEL))]
951 ""
952 "%1 = . + 8\n\tlnk\t%0"
953 [(set_attr "type" "Y1")])
955 ;; The next three patterns are used to to materialize a position
956 ;; independent address by adding the difference of two labels to a
957 ;; base label in the text segment, assuming that the difference fits
958 ;; in 32 signed bits.
959 (define_expand "mov_pcrel_step1<bitsuffix>"
960 [(set (match_operand:I48MODE 0 "register_operand" "")
961 (const:I48MODE (unspec:I48MODE
962 [(match_operand:I48MODE 1 "symbolic_operand" "")
963 (match_operand:I48MODE 2 "symbolic_operand" "")]
964 UNSPEC_HW1_LAST_PCREL)))]
965 "flag_pic")
967 (define_expand "mov_pcrel_step2<bitsuffix>"
968 [(set (match_operand:I48MODE 0 "register_operand" "")
969 (unspec:I48MODE
970 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
971 (const:I48MODE
972 (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")
973 (match_operand:I48MODE 3 "symbolic_operand" "")]
974 UNSPEC_HW0_PCREL))]
975 UNSPEC_INSN_ADDR_SHL16INSLI))]
976 "flag_pic")
978 (define_insn "mov_pcrel_step3<bitsuffix>"
979 [(set (match_operand:I48MODE 0 "register_operand" "=r")
980 (unspec:I48MODE [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
981 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")
982 (match_operand:I48MODE 3 "symbolic_operand" "in")
983 (match_operand:I48MODE 4 "symbolic_operand" "in")]
984 UNSPEC_MOV_PCREL_STEP3))]
985 "flag_pic"
986 "add<x>\t%0, %r1, %r2")
988 ;; The next three patterns are used to to materialize a position
989 ;; independent 64-bit address by adding the difference of two labels to
990 ;; a base label in the text segment, without any limitation on the size
991 ;; of the difference.
992 (define_expand "mov_large_pcrel_step1"
993 [(set (match_operand:DI 0 "register_operand" "")
994 (const:DI (unspec:DI
995 [(match_operand:DI 1 "symbolic_operand" "")
996 (match_operand:DI 2 "symbolic_operand" "")]
997 UNSPEC_HW2_LAST_PCREL)))]
998 "flag_pic")
1000 (define_expand "mov_large_pcrel_step2"
1001 [(set (match_operand:DI 0 "register_operand" "")
1002 (unspec:DI
1003 [(match_operand:DI 1 "reg_or_0_operand" "")
1004 (const:DI
1005 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1006 (match_operand:DI 3 "symbolic_operand" "")]
1007 UNSPEC_HW1_PCREL))]
1008 UNSPEC_INSN_ADDR_SHL16INSLI))]
1009 "flag_pic")
1011 ;; Note: step 3 is same as move_pcrel_step2.
1012 (define_expand "mov_large_pcrel_step3"
1013 [(set (match_operand:DI 0 "register_operand" "")
1014 (unspec:DI
1015 [(match_operand:DI 1 "reg_or_0_operand" "")
1016 (const:DI
1017 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1018 (match_operand:DI 3 "symbolic_operand" "")]
1019 UNSPEC_HW0_PCREL))]
1020 UNSPEC_INSN_ADDR_SHL16INSLI))]
1021 "flag_pic")
1023 (define_insn "mov_large_pcrel_step4"
1024 [(set (match_operand:DI 0 "register_operand" "=r")
1025 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
1026 (match_operand:DI 2 "reg_or_0_operand" "rO")
1027 (match_operand:DI 3 "symbolic_operand" "in")
1028 (match_operand:DI 4 "symbolic_operand" "in")]
1029 UNSPEC_MOV_LARGE_PCREL_STEP4))]
1030 "flag_pic"
1031 "add\t%0, %r1, %r2")
1033 ;; The next three patterns are used to materialize a position
1034 ;; independent 64-bit plt address by adding the difference of two
1035 ;; labels to a base label in the text segment.
1036 (define_expand "mov_plt_pcrel_step1"
1037 [(set (match_operand:DI 0 "register_operand" "")
1038 (const:DI (unspec:DI
1039 [(match_operand:DI 1 "symbolic_operand" "")
1040 (match_operand:DI 2 "symbolic_operand" "")]
1041 UNSPEC_HW2_LAST_PLT_PCREL)))]
1042 "flag_pic")
1044 (define_expand "mov_plt_pcrel_step2"
1045 [(set (match_operand:DI 0 "register_operand" "")
1046 (unspec:DI
1047 [(match_operand:DI 1 "reg_or_0_operand" "")
1048 (const:DI
1049 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1050 (match_operand:DI 3 "symbolic_operand" "")]
1051 UNSPEC_HW1_PLT_PCREL))]
1052 UNSPEC_INSN_ADDR_SHL16INSLI))]
1053 "flag_pic")
1055 (define_expand "mov_plt_pcrel_step3"
1056 [(set (match_operand:DI 0 "register_operand" "")
1057 (unspec:DI
1058 [(match_operand:DI 1 "reg_or_0_operand" "")
1059 (const:DI
1060 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1061 (match_operand:DI 3 "symbolic_operand" "")]
1062 UNSPEC_HW0_PLT_PCREL))]
1063 UNSPEC_INSN_ADDR_SHL16INSLI))]
1064 "flag_pic")
1066 ;; The next two patterns are used to materialize a position independent
1067 ;; 32-bit plt address by adding the difference of two labels to a base
1068 ;; label in the text segment.
1069 (define_expand "mov_plt_pcrel_step1_32bit"
1070 [(set (match_operand:SI 0 "register_operand" "")
1071 (const:SI (unspec:SI
1072 [(match_operand:SI 1 "symbolic_operand" "")
1073 (match_operand:SI 2 "symbolic_operand" "")]
1074 UNSPEC_HW1_LAST_PLT_PCREL)))]
1075 "flag_pic")
1077 (define_expand "mov_plt_pcrel_step2_32bit"
1078 [(set (match_operand:SI 0 "register_operand" "")
1079 (unspec:SI
1080 [(match_operand:SI 1 "reg_or_0_operand" "")
1081 (const:SI
1082 (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")
1083 (match_operand:SI 3 "symbolic_operand" "")]
1084 UNSPEC_HW0_PLT_PCREL))]
1085 UNSPEC_INSN_ADDR_SHL16INSLI))]
1086 "flag_pic")
1088 (define_expand "add_got16<bitsuffix>"
1089 [(set (match_operand:I48MODE 0 "register_operand" "")
1090 (plus:I48MODE
1091 (match_operand:I48MODE 1 "reg_or_0_operand" "")
1092 (const:I48MODE
1093 (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")]
1094 UNSPEC_HW0_LAST_GOT))))]
1095 "flag_pic == 1")
1097 (define_expand "mov_got32_step1<bitsuffix>"
1098 [(set (match_operand:I48MODE 0 "register_operand" "")
1099 (const:I48MODE
1100 (unspec:I48MODE [(match_operand:I48MODE 1 "symbolic_operand" "")]
1101 UNSPEC_HW1_LAST_GOT)))]
1102 "flag_pic == 2")
1104 (define_expand "mov_got32_step2<bitsuffix>"
1105 [(set (match_operand:I48MODE 0 "register_operand" "")
1106 (unspec:I48MODE
1107 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1108 (const:I48MODE
1109 (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")]
1110 UNSPEC_HW0_GOT))]
1111 UNSPEC_INSN_ADDR_SHL16INSLI))]
1112 "flag_pic == 2")
1114 \f
1115 ;;
1116 ;; TLS
1117 ;;
1119 (define_expand "mov_tls_gd_step1<bitsuffix>"
1120 [(set (match_operand:I48MODE 0 "register_operand" "")
1121 (const:I48MODE
1122 (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1123 UNSPEC_HW1_LAST_TLS_GD)))]
1124 "HAVE_AS_TLS")
1126 (define_expand "mov_tls_gd_step2<bitsuffix>"
1127 [(set (match_operand:I48MODE 0 "register_operand" "")
1128 (unspec:I48MODE
1129 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1130 (const:I48MODE
1131 (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1132 UNSPEC_HW0_TLS_GD))]
1133 UNSPEC_INSN_ADDR_SHL16INSLI))]
1134 "HAVE_AS_TLS")
1136 (define_expand "mov_tls_ie_step1<bitsuffix>"
1137 [(set (match_operand:I48MODE 0 "register_operand" "")
1138 (const:I48MODE
1139 (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1140 UNSPEC_HW1_LAST_TLS_IE)))]
1141 "HAVE_AS_TLS")
1143 (define_expand "mov_tls_ie_step2<bitsuffix>"
1144 [(set (match_operand:I48MODE 0 "register_operand" "")
1145 (unspec:I48MODE
1146 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1147 (const:I48MODE
1148 (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1149 UNSPEC_HW0_TLS_IE))]
1150 UNSPEC_INSN_ADDR_SHL16INSLI))]
1151 "HAVE_AS_TLS")
1153 (define_expand "mov_tls_le_step1<bitsuffix>"
1154 [(set (match_operand:I48MODE 0 "register_operand" "")
1155 (const:I48MODE
1156 (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1157 UNSPEC_HW1_LAST_TLS_LE)))]
1158 "HAVE_AS_TLS")
1160 (define_expand "mov_tls_le_step2<bitsuffix>"
1161 [(set (match_operand:I48MODE 0 "register_operand" "")
1162 (unspec:I48MODE
1163 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1164 (const:I48MODE
1165 (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1166 UNSPEC_HW0_TLS_LE))]
1167 UNSPEC_INSN_ADDR_SHL16INSLI))]
1168 "HAVE_AS_TLS")
1170 (define_expand "tls_gd_call<bitsuffix>"
1171 [(parallel
1172 [(set (reg:I48MODE 0)
1173 (unspec:I48MODE [(match_operand:I48MODE 0 "tls_symbolic_operand" "")
1174 (reg:I48MODE 0)]
1175 UNSPEC_TLS_GD_CALL))
1176 (clobber (reg:I48MODE 25))
1177 (clobber (reg:I48MODE 26))
1178 (clobber (reg:I48MODE 27))
1179 (clobber (reg:I48MODE 28))
1180 (clobber (reg:I48MODE 29))
1181 (clobber (reg:I48MODE 55))])]
1182 ""
1183 {
1184 cfun->machine->calls_tls_get_addr = true;
1185 })
1187 (define_insn "*tls_gd_call<bitsuffix>"
1188 [(set (reg:I48MODE 0)
1189 (unspec:I48MODE [(match_operand:I48MODE 0 "tls_symbolic_operand" "")
1190 (reg:I48MODE 0)]
1191 UNSPEC_TLS_GD_CALL))
1192 (clobber (reg:I48MODE 25))
1193 (clobber (reg:I48MODE 26))
1194 (clobber (reg:I48MODE 27))
1195 (clobber (reg:I48MODE 28))
1196 (clobber (reg:I48MODE 29))
1197 (clobber (reg:I48MODE 55))]
1198 ""
1199 "jal\ttls_gd_call(%0)"
1200 [(set_attr "type" "X1")])
1202 (define_insn "tls_gd_add<bitsuffix>"
1203 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1204 (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1205 (match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1206 UNSPEC_TLS_GD_ADD))]
1207 "HAVE_AS_TLS"
1208 "add<x>i\t%0, %1, tls_gd_add(%2)")
1210 (define_insn "tls_add<bitsuffix>"
1211 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1212 (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1213 (match_operand:I48MODE 2 "register_operand" "0")
1214 (match_operand:I48MODE 3 "tls_symbolic_operand" "")]
1215 UNSPEC_TLS_ADD))]
1216 "HAVE_AS_TLS"
1217 "add<x>i\t%0, %1, tls_add(%3)")
1219 (define_insn "tls_ie_load<bitsuffix>"
1220 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1221 (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1222 (match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1223 UNSPEC_TLS_IE_LOAD))]
1224 "HAVE_AS_TLS"
1225 "ld<four_s_if_si>_tls\t%0, %1, tls_ie_load(%2)"
1226 [(set_attr "type" "X1_2cycle")])
1228 (define_insn "*zero_extract<mode>"
1229 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1230 (zero_extract:I48MODE
1231 (match_operand:I48MODE 1 "reg_or_0_operand" "r")
1232 (match_operand:I48MODE 2 "u6bit_cint_operand" "n")
1233 (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
1234 ""
1235 "bfextu\t%0, %r1, %3, %3+%2-1"
1236 [(set_attr "type" "X0")])
1238 (define_insn "*sign_extract_low32"
1239 [(set (match_operand:DI 0 "register_operand" "=r")
1240 (sign_extract:DI
1241 (match_operand:DI 1 "reg_or_0_operand" "r")
1242 (match_operand:DI 2 "u6bit_cint_operand" "n")
1243 (match_operand:DI 3 "u6bit_cint_operand" "n")))]
1244 "INTVAL (operands[3]) == 0 && INTVAL (operands[2]) == 32"
1245 "addxi\t%0, %r1, 0")
1247 (define_insn "*sign_extract"
1248 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1249 (sign_extract:I48MODE
1250 (match_operand:I48MODE 1 "reg_or_0_operand" "r")
1251 (match_operand:I48MODE 2 "u6bit_cint_operand" "n")
1252 (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
1253 ""
1254 "bfexts\t%0, %r1, %3, %3+%2-1"
1255 [(set_attr "type" "X0")])
1257 \f
1258 ;;
1259 ;; Arithmetic ops
1260 ;;
1262 (define_insn "add<mode>3"
1263 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1264 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rO,rO,rO")
1265 (match_operand:I48MODE 2 "add_operand" "r,I,JT")))]
1266 ""
1267 "@
1268 add<x>\t%0, %r1, %r2
1269 add<x>i\t%0, %r1, %2
1270 add<x>li\t%0, %r1, %H2"
1271 [(set_attr "type" "*,*,X01")])
1273 (define_insn "*addsi3_sext"
1274 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1275 (sign_extend:DI
1276 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,rO")
1277 (match_operand:SI 2 "add_operand" "r,I,JT"))))]
1278 ""
1279 "@
1280 addx\t%0, %r1, %r2
1281 addxi\t%0, %r1, %2
1282 addxli\t%0, %r1, %H2"
1283 [(set_attr "type" "*,*,X01")])
1285 (define_insn "sub<mode>3"
1286 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1287 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1288 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
1289 ""
1290 "sub<x>\t%0, %r1, %r2")
1292 (define_insn "*subsi3_sext"
1293 [(set (match_operand:DI 0 "register_operand" "=r")
1294 (sign_extend:DI
1295 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1296 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1297 ""
1298 "subx\t%0, %r1, %r2")
1300 (define_insn "neg<mode>2"
1301 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1302 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO")))]
1303 ""
1304 "sub<x>\t%0, zero, %r1")
1306 (define_insn "*negsi2_sext"
1307 [(set (match_operand:DI 0 "register_operand" "=r")
1308 (sign_extend:DI
1309 (neg:SI (match_operand:SI 1 "reg_or_0_operand" "rO"))))]
1310 ""
1311 "subx\t%0, zero, %r1")
1313 (define_insn "ssaddsi3"
1314 [(set (match_operand:SI 0 "register_operand" "=r")
1315 (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1316 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
1317 ""
1318 "addxsc\t%0, %r1, %r2"
1319 [(set_attr "type" "X01")])
1321 (define_insn "*ssaddsi3_sext"
1322 [(set (match_operand:DI 0 "register_operand" "=r")
1323 (sign_extend:DI
1324 (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1325 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1326 ""
1327 "addxsc\t%0, %r1, %r2"
1328 [(set_attr "type" "X01")])
1330 (define_insn "sssubsi3"
1331 [(set (match_operand:SI 0 "register_operand" "=r")
1332 (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1333 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
1334 ""
1335 "subxsc\t%0, %r1, %r2"
1336 [(set_attr "type" "X01")])
1338 (define_insn "*sssubsi3_sext"
1339 [(set (match_operand:DI 0 "register_operand" "=r")
1340 (sign_extend:DI
1341 (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1342 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1343 ""
1344 "subxsc\t%0, %r1, %r2"
1345 [(set_attr "type" "X01")])
1347 (define_expand "addsf3"
1348 [(set (match_operand:SF 0 "register_operand" "")
1349 (plus:SF (match_operand:SF 1 "register_operand" "")
1350 (match_operand:SF 2 "register_operand" "")))]
1351 ""
1352 {
1353 rtx result = gen_lowpart (DImode, operands[0]);
1354 rtx a = gen_lowpart (DImode, operands[1]);
1355 rtx b = gen_lowpart (DImode, operands[2]);
1357 rtx tmp = gen_reg_rtx (DImode);
1358 rtx flags = gen_reg_rtx (DImode);
1360 emit_insn (gen_insn_fsingle_add1 (tmp, a, b));
1361 emit_insn (gen_insn_fsingle_addsub2 (tmp, tmp, a, b));
1362 emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
1363 emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
1365 DONE;
1366 })
1368 (define_expand "subsf3"
1369 [(set (match_operand:SF 0 "register_operand" "")
1370 (minus:SF (match_operand:SF 1 "register_operand" "")
1371 (match_operand:SF 2 "register_operand" "")))]
1372 ""
1373 {
1374 rtx result = gen_lowpart (DImode, operands[0]);
1375 rtx a = gen_lowpart (DImode, operands[1]);
1376 rtx b = gen_lowpart (DImode, operands[2]);
1378 rtx tmp = gen_reg_rtx (DImode);
1379 rtx flags = gen_reg_rtx (DImode);
1381 emit_insn (gen_insn_fsingle_sub1 (tmp, a, b));
1382 emit_insn (gen_insn_fsingle_addsub2 (tmp, tmp, a, b));
1383 emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
1384 emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
1386 DONE;
1387 })
1389 (define_expand "mulsf3"
1390 [(set (match_operand:SF 0 "register_operand" "")
1391 (mult:SF (match_operand:SF 1 "register_operand" "")
1392 (match_operand:SF 2 "register_operand" "")))]
1393 ""
1394 {
1395 rtx result = gen_lowpart (DImode, operands[0]);
1396 rtx a = gen_lowpart (DImode, operands[1]);
1397 rtx b = gen_lowpart (DImode, operands[2]);
1399 rtx tmp1 = gen_reg_rtx (DImode);
1400 rtx tmp2 = gen_reg_rtx (DImode);
1401 rtx flags = gen_reg_rtx (DImode);
1403 emit_insn (gen_insn_fsingle_mul1 (tmp1, a, b));
1404 emit_insn (gen_insn_fsingle_mul2 (tmp2, tmp1, b));
1405 emit_insn (gen_insn_fsingle_pack1 (flags, tmp2));
1406 emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags));
1408 DONE;
1409 })
1411 (define_expand "adddf3"
1412 [(set (match_operand:DF 0 "register_operand" "")
1413 (plus:DF (match_operand:DF 1 "register_operand" "")
1414 (match_operand:DF 2 "register_operand" "")))]
1415 ""
1416 {
1417 rtx result = gen_lowpart (DImode, operands[0]);
1418 rtx a = gen_lowpart (DImode, operands[1]);
1419 rtx b = gen_lowpart (DImode, operands[2]);
1421 rtx min = gen_reg_rtx (DImode);
1422 rtx max = gen_reg_rtx (DImode);
1423 rtx flags = gen_reg_rtx (DImode);
1425 emit_insn (gen_insn_fdouble_unpack_min (min, a, b));
1426 emit_insn (gen_insn_fdouble_unpack_max (max, a, b));
1427 emit_insn (gen_insn_fdouble_add_flags (flags, a, b));
1428 emit_insn (gen_insn_fdouble_addsub (max, max, min, flags));
1429 emit_insn (gen_insn_fdouble_pack1 (result, max, flags));
1430 emit_insn (gen_insn_fdouble_pack2 (result, result, max, const0_rtx));
1432 DONE;
1433 })
1435 (define_expand "subdf3"
1436 [(set (match_operand:DF 0 "register_operand" "")
1437 (minus:DF (match_operand:DF 1 "register_operand" "")
1438 (match_operand:DF 2 "register_operand" "")))]
1439 ""
1440 {
1441 rtx result = gen_lowpart (DImode, operands[0]);
1442 rtx a = gen_lowpart (DImode, operands[1]);
1443 rtx b = gen_lowpart (DImode, operands[2]);
1445 rtx min = gen_reg_rtx (DImode);
1446 rtx max = gen_reg_rtx (DImode);
1447 rtx flags = gen_reg_rtx (DImode);
1449 emit_insn (gen_insn_fdouble_unpack_min (min, a, b));
1450 emit_insn (gen_insn_fdouble_unpack_max (max, a, b));
1451 emit_insn (gen_insn_fdouble_sub_flags (flags, a, b));
1452 emit_insn (gen_insn_fdouble_addsub (max, max, min, flags));
1453 emit_insn (gen_insn_fdouble_pack1 (result, max, flags));
1454 emit_insn (gen_insn_fdouble_pack2 (result, result, max, const0_rtx));
1456 DONE;
1457 })
1459 (define_expand "muldf3"
1460 [(set (match_operand:DF 0 "register_operand" "")
1461 (mult:DF (match_operand:DF 1 "register_operand" "")
1462 (match_operand:DF 2 "register_operand" "")))]
1463 ""
1464 ;; TODO: Decide if we should not inline this with -Os.
1465 ;; "optimize_function_for_speed_p (cfun)"
1466 {
1467 rtx result = gen_lowpart (DImode, operands[0]);
1468 rtx a = gen_lowpart (DImode, operands[1]);
1469 rtx b = gen_lowpart (DImode, operands[2]);
1471 rtx a_unpacked = gen_reg_rtx (DImode);
1472 rtx b_unpacked = gen_reg_rtx (DImode);
1473 rtx flags = gen_reg_rtx (DImode);
1475 rtx low1 = gen_reg_rtx (DImode);
1476 rtx low = gen_reg_rtx (DImode);
1477 rtx low_carry = gen_reg_rtx (DImode);
1479 rtx mid = gen_reg_rtx (DImode);
1480 rtx mid_l32 = gen_reg_rtx (DImode);
1481 rtx mid_r32 = gen_reg_rtx (DImode);
1483 rtx high1 = gen_reg_rtx (DImode);
1484 rtx high = gen_reg_rtx (DImode);
1485 rtx high1_plus_mid_r32 = gen_reg_rtx (DImode);
1487 /* NOTE: We compute using max(a, 0) and max(b, 0) rather than
1488 min(a, b) and max(a, b) because for multiply we just need to unpack,
1489 we don't actually care which is min and which is max. And this
1490 formulation gives the scheduler more freedom in case one of a or b
1491 would stall at the start of this code sequence. */
1492 emit_insn (gen_insn_fdouble_unpack_max (a_unpacked, a, const0_rtx));
1493 emit_insn (gen_insn_fdouble_unpack_max (b_unpacked, b, const0_rtx));
1494 emit_insn (gen_insn_fdouble_mul_flags (flags, a, b));
1496 /* This depends on the fact that the high few bits of the unpacked
1497 mantissa are zero, so we can't have a carry out from the mid sum. */
1498 emit_insn (gen_insn_mul_lu_lu (low1, a_unpacked, b_unpacked));
1499 emit_insn (gen_insn_mul_hu_lu (mid, a_unpacked, b_unpacked));
1500 emit_insn (gen_insn_mula_hu_lu (mid, mid, b_unpacked, a_unpacked));
1501 emit_insn (gen_insn_mul_hu_hu (high1, a_unpacked, b_unpacked));
1503 emit_insn (gen_ashldi3 (mid_l32, mid, GEN_INT (32)));
1504 emit_insn (gen_lshrdi3 (mid_r32, mid, GEN_INT (32)));
1506 emit_insn (gen_adddi3 (high1_plus_mid_r32, high1, mid_r32));
1508 emit_insn (gen_adddi3 (low, low1, mid_l32));
1509 emit_insn (gen_insn_cmpltu_didi (low_carry, low, mid_l32));
1511 emit_insn (gen_adddi3 (high, high1_plus_mid_r32, low_carry));
1513 emit_insn (gen_insn_fdouble_pack1 (result, high, flags));
1514 emit_insn (gen_insn_fdouble_pack2 (result, result, high, low));
1516 DONE;
1517 })
1519 \f
1520 ;;
1521 ;; Shifts
1522 ;;
1524 (define_insn "ashl<mode>3"
1525 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1526 (ashift:I48MODE
1527 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1528 (match_operand:SI 2 "reg_or_u<nbits>bit_operand" "I,rO")))]
1529 ""
1530 "@
1531 shl<x>i\t%0, %r1, %2
1532 shl<x>\t%0, %r1, %r2"
1533 [(set_attr "type" "<shift_pipe>,<shift_pipe>")])
1535 (define_insn "*ashlsi3_sext"
1536 [(set (match_operand:DI 0 "register_operand" "=r,r")
1537 (sign_extend:DI
1538 (ashift:SI
1539 (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1540 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1541 ""
1542 "@
1543 shlxi\t%0, %r1, %2
1544 shlx\t%0, %r1, %r2"
1545 [(set_attr "type" "X01,X01")])
1547 (define_insn "ashr<mode>3"
1548 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1549 (ashiftrt:I48MODE
1550 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1551 (match_operand:SI 2 "reg_or_u<nbits>bit_operand" "I,rO")))]
1552 ""
1553 "@
1554 shrsi\t%0, %r1, %2
1555 shrs\t%0, %r1, %r2")
1557 (define_insn "*ashrsi3_sext"
1558 [(set (match_operand:DI 0 "register_operand" "=r,r")
1559 (sign_extend:DI
1560 (ashiftrt:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1561 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1562 ""
1563 "@
1564 shrsi\t%0, %r1, %2
1565 shrs\t%0, %r1, %r2")
1567 (define_insn "lshr<mode>3"
1568 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1569 (lshiftrt:I48MODE
1570 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1571 (match_operand:SI 2 "reg_or_u<nbits>bit_operand" "I,rO")))]
1572 ""
1573 "@
1574 shru<x>i\t%0, %r1, %2
1575 shru<x>\t%0, %r1, %r2"
1576 [(set_attr "type" "<shift_pipe>,<shift_pipe>")])
1578 (define_insn "*lshrsi3_sext"
1579 [(set (match_operand:DI 0 "register_operand" "=r,r")
1580 (sign_extend:DI
1581 (lshiftrt:SI
1582 (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1583 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1584 ""
1585 "@
1586 shruxi\t%0, %r1, %2
1587 shrux\t%0, %r1, %r2"
1588 [(set_attr "type" "X01,X01")])
1590 (define_insn "rotldi3"
1591 [(set (match_operand:DI 0 "register_operand" "=r,r")
1592 (rotate:DI (match_operand:DI 1 "reg_or_0_operand" "rO,rO")
1593 (match_operand:SI 2 "reg_or_u6bit_operand" "I,rO")))]
1594 ""
1595 "@
1596 rotli\t%0, %r1, %2
1597 rotl\t%0, %r1, %r2")
1599 (define_insn "insn_shl16insli"
1600 [(set (match_operand:DI 0 "register_operand" "=r,r")
1601 (ior:DI
1602 (ashift:DI
1603 (match_operand:DI 1 "reg_or_0_operand" "rO,rO")
1604 (const_int 16))
1605 (match_operand:DI 2 "u16bit_or_const_symbolic_operand" "O,KT")))]
1606 ""
1607 "@
1608 shli\t%0, %r1, 16
1609 shl16insli\t%0, %r1, %H2"
1610 [(set_attr "type" "*,X01")])
1612 (define_insn "insn_addr_shl16insli<bitsuffix>"
1613 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1614 (unspec:I48MODE
1615 [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1616 (match_operand:I48MODE 2 "const_symbolic_operand" "T")]
1617 UNSPEC_INSN_ADDR_SHL16INSLI))]
1618 ""
1619 "shl16insli\t%0, %r1, %H2"
1620 [(set_attr "type" "X01")])
1622 \f
1623 ;;
1624 ;; Compares
1625 ;;
1627 (define_expand "cstore<mode>4"
1628 [(set (match_operand:DI 0 "register_operand" "")
1629 (match_operator:DI 1 "ordered_comparison_operator"
1630 [(match_operand:FI48MODE 2 "reg_or_cint_operand" "")
1631 (match_operand:FI48MODE 3 "reg_or_cint_operand" "")]))]
1632 ""
1633 {
1634 if (!tilegx_emit_setcc (operands, GET_MODE (operands[2])))
1635 FAIL;
1636 else
1637 DONE;
1638 })
1641 (define_insn "insn_cmpne_<I48MODE:mode><I48MODE2:mode>"
1642 [(set (match_operand:I48MODE2 0 "register_operand" "=r")
1643 (ne:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1644 (match_operand:I48MODE 2 "reg_or_cint_operand" "rO")))]
1645 ""
1646 "cmpne\t%0, %r1, %r2")
1648 (define_insn "insn_cmpeq_<I48MODE:mode><I48MODE2:mode>"
1649 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1650 (eq:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "%rO,rO")
1651 (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1652 ""
1653 "@
1654 cmpeqi\t%0, %r1, %2
1655 cmpeq\t%0, %r1, %r2")
1657 (define_insn "insn_cmplts_<I48MODE:mode><I48MODE2:mode>"
1658 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1659 (lt:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1660 (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1661 ""
1662 "@
1663 cmpltsi\t%0, %r1, %2
1664 cmplts\t%0, %r1, %r2")
1666 (define_insn "insn_cmpltu_<I48MODE:mode><I48MODE2:mode>"
1667 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1668 (ltu:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1669 (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1670 ""
1671 "@
1672 cmpltui\t%0, %r1, %2
1673 cmpltu\t%0, %r1, %r2"
1674 [(set_attr "type" "X01,*")])
1676 (define_insn "insn_cmples_<I48MODE:mode><I48MODE2:mode>"
1677 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1678 (le:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1679 (match_operand:I48MODE 2 "reg_or_cint_operand" "L,rO")))]
1680 ""
1681 "@
1682 cmpltsi\t%0, %r1, %P2
1683 cmples\t%0, %r1, %r2")
1685 (define_insn "insn_cmpleu_<I48MODE:mode><I48MODE2:mode>"
1686 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1687 (leu:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1688 (match_operand:I48MODE 2 "reg_or_cint_operand" "Q,rO")))]
1689 ""
1690 "@
1691 cmpltui\t%0, %r1, %P2
1692 cmpleu\t%0, %r1, %r2"
1693 [(set_attr "type" "X01,*")])
1695 \f
1696 ;;
1697 ;; Logical ops
1698 ;;
1700 (define_insn "and<mode>3"
1701 [(set (match_operand:IVNMODE 0 "register_operand" "=r,r,r,r")
1702 (and:IVNMODE (match_operand:IVNMODE 1 "reg_or_0_operand" "%rO,rO,0,rO")
1703 (match_operand:IVNMODE 2 "and_operand" "I,S,M,rO")))]
1704 ""
1705 "@
1706 andi\t%0, %r1, %2
1707 bfextu\t%0, %r1, %M2
1708 bfins\t%0, zero, %m2
1709 and\t%0, %r1, %r2"
1710 [(set_attr "type" "*,X0,X0,*")])
1712 (define_insn "*andsi3_sext"
1713 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
1714 (sign_extend:DI
1715 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,0,rO")
1716 (match_operand:SI 2 "and_operand" "I,S,M,rO"))))]
1717 ""
1718 "@
1719 andi\t%0, %r1, %2
1720 bfextu\t%0, %r1, %M2
1721 bfins\t%0, zero, %m2
1722 and\t%0, %r1, %r2"
1723 [(set_attr "type" "*,X0,X0,*")])
1725 (define_insn "anddi3"
1726 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
1727 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO,rO,0,rO")
1728 (match_operand:DI 2 "and_operand" "I,Z0,Z1,S,M,rO")))]
1729 ""
1730 "@
1731 andi\t%0, %r1, %2
1732 v4int_l\t%0, zero, %r1
1733 v4int_h\t%0, %r1, zero
1734 bfextu\t%0, %r1, %M2
1735 bfins\t%0, zero, %m2
1736 and\t%0, %r1, %r2"
1737 [(set_attr "type" "*,X01,X01,X0,X0,*")])
1739 (define_insn "ior<mode>3"
1740 [(set (match_operand:IVMODE 0 "register_operand" "=r,r")
1741 (ior:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "%rO,rO")
1742 (match_operand:IVMODE 2 "reg_or_s8bit_operand" "rO,I")))]
1743 ""
1744 "@
1745 or\t%0, %r1, %r2
1746 ori\t%0, %r1, %2"
1747 [(set_attr "type" "*,X01")])
1749 (define_insn "*iorsi3_sext"
1750 [(set (match_operand:DI 0 "register_operand" "=r,r")
1751 (sign_extend:DI
1752 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
1753 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I"))))]
1754 ""
1755 "@
1756 or\t%0, %r1, %r2
1757 ori\t%0, %r1, %2"
1758 [(set_attr "type" "*,X01")])
1760 (define_insn "xor<mode>3"
1761 [(set (match_operand:IVMODE 0 "register_operand" "=r,r")
1762 (xor:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "%rO,rO")
1763 (match_operand:IVMODE 2 "reg_or_s8bit_operand" "rO,I")))]
1764 ""
1765 "@
1766 xor\t%0, %r1, %r2
1767 xori\t%0, %r1, %2"
1768 [(set_attr "type" "*,X01")])
1770 (define_insn "*xorsi3_sext"
1771 [(set (match_operand:DI 0 "register_operand" "=r,r")
1772 (sign_extend:DI
1773 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
1774 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I"))))]
1775 ""
1776 "@
1777 xor\t%0, %r1, %r2
1778 xori\t%0, %r1, %2"
1779 [(set_attr "type" "*,X01")])
1781 (define_insn "clzdi2"
1782 [(set (match_operand:DI 0 "register_operand" "=r")
1783 (clz:DI (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1784 ""
1785 "clz\t%0, %r1"
1786 [(set_attr "type" "Y0")])
1788 (define_expand "clzsi2"
1789 [(set (match_dup 2)
1790 (ashift:DI (match_operand:SI 1 "reg_or_0_operand" "")
1791 (const_int 32)))
1792 (set (subreg:DI (match_operand:SI 0 "register_operand" "") 0)
1793 (clz:DI (match_dup 2)))]
1794 ""
1795 {
1796 operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);
1797 operands[2] = gen_reg_rtx (DImode);
1798 })
1800 (define_insn "ctz<mode>2"
1801 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1802 (ctz:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1803 ""
1804 "ctz\t%0, %r1"
1805 [(set_attr "type" "Y0")])
1807 (define_insn "popcount<mode>2"
1808 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1809 (popcount:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1810 ""
1811 "pcnt\t%0, %r1"
1812 [(set_attr "type" "Y0")])
1814 (define_expand "parity<mode>2"
1815 [(set (match_operand:I48MODE 0 "register_operand" "")
1816 (parity:I48MODE (match_operand:DI 1 "reg_or_0_operand" "")))]
1817 ""
1818 {
1819 rtx tmp = gen_reg_rtx (<MODE>mode);
1820 emit_insn (gen_popcount<mode>2 (tmp, operands[1]));
1821 emit_insn (gen_and<mode>3 (operands[0], tmp, const1_rtx));
1822 DONE;
1823 })
1825 (define_insn "bswapdi2"
1826 [(set (match_operand:DI 0 "register_operand" "=r")
1827 (bswap:DI (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1828 ""
1829 "revbytes\t%0, %r1"
1830 [(set_attr "type" "Y0")])
1832 (define_expand "bswapsi2"
1833 [(set (match_operand:SI 0 "register_operand" "")
1834 (bswap:SI (match_operand:SI 1 "reg_or_0_operand" "")))]
1835 ""
1836 {
1837 rtx tmp = gen_reg_rtx (DImode);
1838 emit_insn (gen_bswapdi2 (tmp, gen_lowpart (DImode, operands[1])));
1839 emit_insn (gen_ashrdi3 (gen_lowpart (DImode, operands[0]),
1840 tmp, GEN_INT (32)));
1841 DONE;
1842 })
1844 (define_insn "one_cmpl<mode>2"
1845 [(set (match_operand:IVMODE 0 "register_operand" "=r")
1846 (not:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "rO")))]
1847 ""
1848 "nor\t%0, %r1, zero")
1850 \f
1851 ;;
1852 ;; Conditional moves
1853 ;;
1855 (define_expand "mov<mode>cc"
1856 [(set (match_operand:I48MODE 0 "register_operand" "")
1857 (if_then_else:I48MODE
1858 (match_operand 1 "comparison_operator" "")
1859 (match_operand:I48MODE 2 "reg_or_0_operand" "")
1860 (match_operand:I48MODE 3 "reg_or_0_operand" "")))]
1861 ""
1862 { operands[1] = tilegx_emit_conditional_move (operands[1]); })
1864 (define_insn "movcc_insn_<I48MODE2:mode><I48MODE:mode>"
1865 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r,r")
1866 (if_then_else:I48MODE
1867 (match_operator 4 "eqne_operator"
1868 [(match_operand:I48MODE2 1 "reg_or_0_operand" "rO,rO,rO,rO")
1869 (const_int 0)])
1870 (match_operand:I48MODE 2 "reg_or_0_operand" "rO,O,rO,0")
1871 (match_operand:I48MODE 3 "reg_or_0_operand" "O,rO,0,rO")))]
1872 ""
1873 "@
1874 m%c4\t%0, %r1, %r2
1875 m%C4\t%0, %r1, %r3
1876 cmov%d4z\t%0, %r1, %r2
1877 cmov%D4z\t%0, %r1, %r3"
1878 [(set_attr "type" "*,*,Y0,Y0")])
1880 (define_expand "insn_mz"
1881 [(set (match_operand:DI 0 "register_operand" "")
1882 (if_then_else:DI
1883 (eq (match_operand:DI 1 "reg_or_0_operand" "")
1884 (const_int 0))
1885 (match_operand:DI 2 "reg_or_0_operand" "")
1886 (const_int 0)))])
1888 (define_expand "insn_mnz"
1889 [(set (match_operand:DI 0 "register_operand" "")
1890 (if_then_else:DI
1891 (ne (match_operand:DI 1 "reg_or_0_operand" "")
1892 (const_int 0))
1893 (match_operand:DI 2 "reg_or_0_operand" "")
1894 (const_int 0)))])
1896 (define_expand "insn_cmoveqz"
1897 [(set (match_operand:DI 0 "register_operand" "")
1898 (if_then_else:DI
1899 (eq (match_operand:DI 2 "reg_or_0_operand" "")
1900 (const_int 0))
1901 (match_operand:DI 3 "reg_or_0_operand" "")
1902 (match_operand:DI 1 "reg_or_0_operand" "")))])
1904 (define_expand "insn_cmovnez"
1905 [(set (match_operand:DI 0 "register_operand" "")
1906 (if_then_else:DI
1907 (ne (match_operand:DI 2 "reg_or_0_operand" "")
1908 (const_int 0))
1909 (match_operand:DI 3 "reg_or_0_operand" "")
1910 (match_operand:DI 1 "reg_or_0_operand" "")))])
1912 \f
1913 ;;
1914 ;; Conversions
1915 ;;
1917 (define_insn "zero_extendqi<mode>2"
1918 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1919 (zero_extend:I48MODE (match_operand:QI 1 "move_operand" "rO,U,m")))]
1920 ""
1921 "@
1922 bfextu\t%0, %r1, 0, 7
1923 ld1u\t%0, %1
1924 ld1u_add\t%0, %I1, %i1"
1925 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1927 (define_insn "zero_extendhi<mode>2"
1928 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1929 (zero_extend:I48MODE (match_operand:HI 1 "move_operand" "rO,U,m")))]
1930 ""
1931 "@
1932 bfextu\t%0, %r1, 0, 15
1933 ld2u\t%0, %1
1934 ld2u_add\t%0, %I1, %i1"
1935 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1937 (define_insn "zero_extendsidi2"
1938 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1939 (zero_extend:DI (match_operand:SI 1 "move_operand" "rO,U,m")))]
1940 ""
1941 "@
1942 v4int_l\t%0, zero, %r1
1943 ld4u\t%0, %1
1944 ld4u_add\t%0, %I1, %i1"
1945 [(set_attr "type" "X01,Y2_2cycle,X1_2cycle")])
1947 (define_insn "extendqi<mode>2"
1948 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1949 (sign_extend:I48MODE (match_operand:QI 1 "move_operand" "rO,U,m")))]
1950 ""
1951 "@
1952 bfexts\t%0, %r1, 0, 7
1953 ld1s\t%0, %1
1954 ld1s_add\t%0, %I1, %i1"
1955 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1957 (define_insn "extendhi<mode>2"
1958 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1959 (sign_extend:I48MODE (match_operand:HI 1 "move_operand" "rO,U,m")))]
1960 ""
1961 "@
1962 bfexts\t%0, %r1, 0, 15
1963 ld2s\t%0, %1
1964 ld2s_add\t%0, %I1, %i1"
1965 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1967 ;; All SImode integer registers should already be in sign-extended
1968 ;; form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can therefore
1969 ;; get rid of register->register instructions if we constrain the
1970 ;; source to be in the same register as the destination.
1971 (define_insn_and_split "extendsidi2"
1972 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1973 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,U,m")))]
1974 ""
1975 "@
1976 #
1977 ld4s\t%0, %1
1978 ld4s_add\t%0, %I1, %i1"
1979 "&& reload_completed && register_operand (operands[1], VOIDmode)"
1980 [(const_int 0)]
1981 {
1982 emit_note (NOTE_INSN_DELETED);
1983 DONE;
1984 }
1985 [(set_attr "type" "*,Y2_2cycle,X1_2cycle")])
1987 ;; Integer truncation patterns. Truncating SImode values to smaller
1988 ;; modes is a no-op, as it is for most other GCC ports. Truncating
1989 ;; DImode values to SImode is not a no-op since we
1990 ;; need to make sure that the lower 32 bits are properly sign-extended
1991 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
1992 ;; smaller than SImode is equivalent to two separate truncations:
1993 ;;
1994 ;; A B
1995 ;; DI ---> HI == DI ---> SI ---> HI
1996 ;; DI ---> QI == DI ---> SI ---> QI
1997 ;;
1998 ;; Step A needs a real instruction but step B does not.
2000 (define_insn "truncdisi2"
2001 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,U,m")
2002 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
2003 ""
2004 "@
2005 addxi\t%0, %r1, 0
2006 st4\t%0, %r1
2007 st4_add\t%I0, %r1, %i0"
2008 [(set_attr "type" "Y01,Y2,X1")])
2010 (define_insn "truncdihi2"
2011 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,U,m")
2012 (truncate:HI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
2013 ""
2014 "@
2015 addxi\t%0, %r1, 0
2016 st2\t%0, %r1
2017 st2_add\t%I0, %r1, %i0"
2018 [(set_attr "type" "Y01,Y2,X1")])
2020 (define_insn "truncdiqi2"
2021 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,U,m")
2022 (truncate:QI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
2023 ""
2024 "@
2025 addxi\t%0, %r1, 0
2026 st1\t%0, %r1
2027 st1_add\t%I0, %r1, %i0"
2028 [(set_attr "type" "Y01,Y2,X1")])
2030 ;; Combiner patterns to optimize away unnecessary truncates.
2032 (define_insn "*zero_extendsidi_truncdisi"
2033 [(set (match_operand:DI 0 "register_operand" "=r")
2034 (zero_extend:DI
2035 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))))]
2036 ""
2037 "v4int_l\t%0, zero, %r1"
2038 [(set_attr "type" "X01")])
2040 (define_insn "*addsi_truncdisi"
2041 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2042 (plus:SI
2043 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO"))
2044 (match_operand:SI 2 "add_operand" "r,I,JT")))]
2045 ""
2046 "@
2047 addx\t%0, %r1, %r2
2048 addxi\t%0, %r1, %2
2049 addxli\t%0, %r1, %H2"
2050 [(set_attr "type" "*,*,X01")])
2052 (define_insn "*addsi_truncdisi2"
2053 [(set (match_operand:SI 0 "register_operand" "=r")
2054 (plus:SI
2055 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2056 (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2057 ""
2058 "addx\t%0, %r1, %r2")
2060 (define_insn "*ashldi_truncdisi"
2061 [(set (match_operand:DI 0 "register_operand" "=r")
2062 (ashift:DI
2063 (match_operand:DI 1 "reg_or_0_operand" "rO")
2064 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2065 ""
2066 "shl\t%0, %r1, %r2")
2068 (define_insn "*ashlsi_truncdisi"
2069 [(set (match_operand:SI 0 "register_operand" "=r,r")
2070 (ashift:SI
2071 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO"))
2072 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2073 ""
2074 "@
2075 shlxi\t%0, %r1, %2
2076 shlx\t%0, %r1, %r2"
2077 [(set_attr "type" "X01,X01")])
2079 (define_insn "*ashlsi_truncdisi2"
2080 [(set (match_operand:SI 0 "register_operand" "=r")
2081 (ashift:SI
2082 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2083 (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2084 ""
2085 "shlx\t%0, %r1, %r2"
2086 [(set_attr "type" "X01")])
2088 (define_insn "*ashrdi3_truncdisi"
2089 [(set (match_operand:DI 0 "register_operand" "=r")
2090 (ashiftrt:DI
2091 (match_operand:DI 1 "reg_or_0_operand" "rO")
2092 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2093 ""
2094 "shrs\t%0, %r1, %r2")
2096 (define_insn "*lshrsi_truncdisi"
2097 [(set (match_operand:SI 0 "register_operand" "=r,r")
2098 (lshiftrt:SI
2099 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO"))
2100 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2101 ""
2102 "@
2103 shruxi\t%0, %r1, %2
2104 shrux\t%0, %r1, %r2"
2105 [(set_attr "type" "X01,X01")])
2107 (define_insn "*lshrsi_truncdisi2"
2108 [(set (match_operand:SI 0 "register_operand" "=r")
2109 (lshiftrt:SI
2110 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2111 (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2112 ""
2113 "shrux\t%0, %r1, %r2"
2114 [(set_attr "type" "X01")])
2116 (define_insn "*lshrdi_truncdisi"
2117 [(set (match_operand:DI 0 "register_operand" "=r")
2118 (lshiftrt:DI
2119 (match_operand:DI 1 "reg_or_0_operand" "rO")
2120 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2121 ""
2122 "shru\t%0, %r1, %r2")
2124 (define_insn "*rotldi_truncdisi"
2125 [(set (match_operand:DI 0 "register_operand" "=r")
2126 (rotate:DI
2127 (match_operand:DI 1 "reg_or_0_operand" "rO")
2128 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2129 ""
2130 "rotl\t%0, %r1, %r2")
2132 \f
2133 ;;
2134 ;; Multiplies
2135 ;;
2137 (define_insn "mulsi3"
2138 [(set (match_operand:SI 0 "register_operand" "=r")
2139 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rO")
2140 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
2141 ""
2142 "mulx\t%0, %r1, %r2"
2143 [(set_attr "type" "Y0_2cycle")])
2145 (define_insn "mulsidi3"
2146 [(set (match_operand:DI 0 "register_operand" "=r")
2147 (mult:DI (sign_extend:DI
2148 (match_operand:SI 1 "reg_or_0_operand" "%rO"))
2149 (sign_extend:DI
2150 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2151 ""
2152 "mul_ls_ls\t%0, %r1, %r2"
2153 [(set_attr "type" "Y0_2cycle")])
2155 (define_insn "umulsidi3"
2156 [(set (match_operand:DI 0 "register_operand" "=r")
2157 (mult:DI (zero_extend:DI
2158 (match_operand:SI 1 "reg_or_0_operand" "%rO"))
2159 (zero_extend:DI
2160 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2161 ""
2162 "mul_lu_lu\t%0, %r1, %r2"
2163 [(set_attr "type" "Y0_2cycle")])
2165 (define_expand "muldi3"
2166 [(set (match_operand:DI 0 "register_operand" "")
2167 (unspec:DI [(match_operand:DI 1 "nonmemory_operand" "")
2168 (match_operand:DI 2 "nonmemory_operand" "")]
2169 UNSPEC_INSN_MUL_HU_LU))
2170 (set (match_dup 0)
2171 (unspec:DI [(match_dup 0) (match_dup 2) (match_dup 1)]
2172 UNSPEC_INSN_MULA_HU_LU))
2173 (set (match_dup 0)
2174 (ashift:DI (match_dup 0) (const_int 32)))
2175 (set (match_dup 0)
2176 (unspec:DI [(match_dup 0) (match_dup 2) (match_dup 1)]
2177 UNSPEC_INSN_MULA_LU_LU))]
2178 ""
2179 {
2180 operands[1] = force_reg (DImode, operands[1]);
2181 operands[1] = make_safe_from (operands[1], operands[0]);
2183 if (tilegx_expand_muldi (operands[0], operands[1], operands[2]))
2184 DONE;
2185 else
2186 {
2187 operands[2] = force_reg (DImode, operands[2]);
2188 operands[2] = make_safe_from (operands[2], operands[0]);
2189 }
2190 })
2192 (define_insn "usmulsidi3"
2193 [(set (match_operand:DI 0 "register_operand" "=r")
2194 (mult:DI (zero_extend:DI
2195 (match_operand:SI 1 "reg_or_0_operand" "rO"))
2196 (sign_extend:DI
2197 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2198 ""
2199 "mul_ls_lu\t%0, %r2, %r1"
2200 [(set_attr "type" "X0_2cycle")])
2202 (define_insn "maddsidi4"
2203 [(set (match_operand:DI 0 "register_operand" "=r")
2204 (plus:DI
2205 (mult:DI (sign_extend:DI
2206 (match_operand:SI 1 "reg_or_0_operand" "rO"))
2207 (sign_extend:DI
2208 (match_operand:SI 2 "reg_or_0_operand" "rO")))
2209 (match_operand:DI 3 "register_operand" "0")))]
2210 ""
2211 "mula_ls_ls\t%0, %r1, %r2"
2212 [(set_attr "type" "Y0_2cycle")])
2214 (define_insn "umaddsidi4"
2215 [(set (match_operand:DI 0 "register_operand" "=r")
2216 (plus:DI
2217 (mult:DI (zero_extend:DI
2218 (match_operand:SI 1 "reg_or_0_operand" "rO"))
2219 (zero_extend:DI
2220 (match_operand:SI 2 "reg_or_0_operand" "rO")))
2221 (match_operand:DI 3 "register_operand" "0")))]
2222 ""
2223 "mula_lu_lu\t%0, %r1, %r2"
2224 [(set_attr "type" "Y0_2cycle")])
2226 (define_expand "smulsi3_highpart"
2227 [(set (match_dup 3)
2228 (mult:DI (sign_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
2229 (sign_extend:DI (match_operand:SI 2 "reg_or_0_operand" ""))))
2230 (set (match_dup 4)
2231 (ashiftrt:DI (match_dup 3) (const_int 32)))
2232 (set (match_operand:SI 0 "register_operand" "")
2233 (truncate:SI (match_dup 4)))]
2234 ""
2235 {
2236 operands[3] = gen_reg_rtx (DImode);
2237 operands[4] = gen_reg_rtx (DImode);
2238 })
2240 (define_expand "umulsi3_highpart"
2241 [(set (match_dup 3)
2242 (mult:DI (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
2243 (zero_extend:DI (match_operand:SI 2 "reg_or_0_operand" ""))))
2244 (set (match_dup 4)
2245 (lshiftrt:DI (match_dup 3) (const_int 32)))
2246 (set (match_operand:SI 0 "register_operand" "")
2247 (truncate:SI (match_dup 4)))]
2248 ""
2249 {
2250 operands[3] = gen_reg_rtx (DImode);
2251 operands[4] = gen_reg_rtx (DImode);
2252 })
2254 (define_expand "smuldi3_highpart"
2255 [(set (match_operand:DI 0 "register_operand" "")
2256 (truncate:DI
2257 (ashiftrt:TI
2258 (mult:TI (sign_extend:TI (match_operand:DI 1 "reg_or_0_operand" ""))
2259 (sign_extend:TI (match_operand:DI 2 "reg_or_0_operand" "")))
2260 (const_int 64))))]
2261 ""
2262 {
2263 tilegx_expand_smuldi3_highpart (operands[0], operands[1], operands[2]);
2264 DONE;
2265 })
2267 (define_expand "umuldi3_highpart"
2268 [(set (match_operand:DI 0 "register_operand" "")
2269 (truncate:DI
2270 (lshiftrt:TI
2271 (mult:TI (zero_extend:TI (match_operand:DI 1 "reg_or_0_operand" ""))
2272 (zero_extend:TI (match_operand:DI 2 "reg_or_0_operand" "")))
2273 (const_int 64))))]
2274 ""
2275 {
2276 tilegx_expand_umuldi3_highpart (operands[0], operands[1], operands[2]);
2277 DONE;
2278 })
2280 \f
2281 ;;
2282 ;; Divide stubs. These exist to work around a bug in expmed.c, which
2283 ;; will not attempt to convert a divide by constant into a multiply
2284 ;; unless there is a pattern for a divide of the same mode. The end
2285 ;; result is a 32-bit divide turns into 64-bit multiply.
2286 ;;
2288 (define_expand "divsi3"
2289 [(set (match_operand:SI 0 "register_operand" "")
2290 (div:SI (match_operand:SI 1 "reg_or_0_operand" "")
2291 (match_operand:SI 2 "reg_or_0_operand" "")))]
2292 ""
2293 {
2294 FAIL;
2295 })
2297 (define_expand "udivsi3"
2298 [(set (match_operand:SI 0 "register_operand" "")
2299 (udiv:SI (match_operand:SI 1 "reg_or_0_operand" "")
2300 (match_operand:SI 2 "reg_or_0_operand" "")))]
2301 ""
2302 {
2303 FAIL;
2304 })
2306 \f
2307 ;;
2308 ;; Loops
2309 ;;
2311 ;; Define the subtract-one-and-jump insns so loop.c knows what to
2312 ;; generate.
2313 (define_expand "doloop_end"
2314 [(use (match_operand 0 "" "")) ;; loop pseudo
2315 (use (match_operand 1 "" "")) ;; iterations; zero if unknown
2316 (use (match_operand 2 "" "")) ;; max iterations
2317 (use (match_operand 3 "" "")) ;; loop level
2318 (use (match_operand 4 "" "")) ;; label
2319 (use (match_operand 5 "" ""))] ;; flag: 1 if loop entered at top, else 0
2320 ""
2321 {
2322 if (optimize > 0 && flag_modulo_sched)
2323 {
2324 rtx s0;
2325 rtx bcomp;
2326 rtx loc_ref;
2327 enum machine_mode mode = GET_MODE (operands[0]);
2329 /* only do inner loop */
2330 if (INTVAL (operands[3]) > 1)
2331 FAIL;
2332 /* only deal with loop counters in SImode or DImode */
2333 if (mode != SImode && mode != DImode)
2334 FAIL;
2336 s0 = operands [0];
2337 emit_move_insn (s0, gen_rtx_PLUS (mode, s0, GEN_INT (-1)));
2338 bcomp = gen_rtx_NE(mode, s0, const0_rtx);
2339 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
2340 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2341 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
2342 loc_ref, pc_rtx)));
2343 DONE;
2344 }
2345 else
2346 FAIL;
2348 })
2350 ;;
2351 ;; Prologue/epilogue
2352 ;;
2353 (define_expand "prologue"
2354 [(const_int 0)]
2355 ""
2356 {
2357 tilegx_expand_prologue ();
2358 DONE;
2359 })
2361 (define_expand "epilogue"
2362 [(const_int 0)]
2363 ""
2364 {
2365 tilegx_expand_epilogue (false);
2366 DONE;
2367 })
2369 (define_expand "sibcall_epilogue"
2370 [(const_int 0)]
2371 ""
2372 {
2373 tilegx_expand_epilogue (true);
2374 DONE;
2375 })
2377 ;;
2378 ;; Stack manipulations
2379 ;;
2381 ;; An insn to allocate new stack space for dynamic use (e.g., alloca).
2382 (define_expand "allocate_stack"
2383 [(set (match_operand 0 "register_operand" "")
2384 (minus (reg 54) (match_operand 1 "nonmemory_operand" "")))
2385 (set (reg 54)
2386 (minus (reg 54) (match_dup 1)))]
2387 ""
2388 "tilegx_allocate_stack (operands[0], operands[1]); DONE;")
2390 ;;
2391 ;; Branches
2392 ;;
2394 (define_expand "call"
2395 [(parallel [(call (match_operand:DI 0 "call_operand" "")
2396 (match_operand 1 "" ""))
2397 (use (reg:DI 54))
2398 (clobber (reg:DI 55))])]
2399 ""
2400 {
2401 rtx orig_addr = XEXP (operands[0], 0);
2402 rtx addr;
2403 if (GET_CODE (orig_addr) == SYMBOL_REF)
2404 {
2405 if (tilegx_cmodel == CM_LARGE)
2406 {
2407 addr = gen_reg_rtx (Pmode);
2408 tilegx_expand_set_const64 (addr, orig_addr);
2409 operands[0] = gen_rtx_MEM (DImode, addr);
2410 }
2411 else if (tilegx_cmodel == CM_LARGE_PIC)
2412 {
2413 crtl->uses_pic_offset_table = 1;
2414 addr = gen_reg_rtx (Pmode);
2415 if (SYMBOL_REF_LOCAL_P (orig_addr))
2416 tilegx_compute_pcrel_address (addr, orig_addr);
2417 else
2418 tilegx_compute_pcrel_plt_address (addr, orig_addr);
2419 operands[0] = gen_rtx_MEM (DImode, addr);
2420 }
2421 }
2422 })
2424 (define_insn "*call_insn"
2425 [(call (mem:DI (match_operand:I48MODE 0 "call_address_operand" "rO,i"))
2426 (match_operand 1 "" ""))
2427 (use (reg:DI 54))
2428 (clobber (reg:DI 55))]
2429 ""
2430 "@
2431 jalr\t%r0
2432 jal\t%p0"
2433 [(set_attr "type" "Y1,X1")])
2435 (define_expand "call_value"
2436 [(parallel [(set (match_operand 0 "register_operand" "")
2437 (call (match_operand:DI 1 "call_operand" "")
2438 (match_operand 2 "" "")))
2439 (use (reg:DI 54))
2440 (clobber (reg:DI 55))])]
2441 ""
2442 {
2443 rtx orig_addr = XEXP (operands[1], 0);
2444 rtx addr;
2445 if (GET_CODE (orig_addr) == SYMBOL_REF)
2446 {
2447 if (tilegx_cmodel == CM_LARGE)
2448 {
2449 addr = gen_reg_rtx (Pmode);
2450 tilegx_expand_set_const64 (addr, orig_addr);
2451 operands[1] = gen_rtx_MEM (DImode, addr);
2452 }
2453 else if (tilegx_cmodel == CM_LARGE_PIC)
2454 {
2455 crtl->uses_pic_offset_table = 1;
2456 addr = gen_reg_rtx (Pmode);
2457 if (SYMBOL_REF_LOCAL_P (orig_addr))
2458 tilegx_compute_pcrel_address (addr, orig_addr);
2459 else
2460 tilegx_compute_pcrel_plt_address (addr, orig_addr);
2461 operands[1] = gen_rtx_MEM (DImode, addr);
2462 }
2463 }
2464 })
2466 (define_insn "*call_value_insn"
2467 [(set (match_operand 0 "register_operand" "=r,r")
2468 (call (mem:DI (match_operand:I48MODE 1 "call_address_operand" "rO,i"))
2469 (match_operand 2 "" "")))
2470 (use (reg:DI 54))
2471 (clobber (reg:DI 55))]
2472 ""
2473 "@
2474 jalr\t%r1
2475 jal\t%p1"
2476 [(set_attr "type" "Y1,X1")])
2478 (define_expand "sibcall"
2479 [(parallel [(call (match_operand:DI 0 "call_operand" "")
2480 (match_operand 1 "" ""))
2481 (use (reg:DI 54))])]
2482 ""
2483 "")
2485 (define_insn "*sibcall_insn"
2486 [(call (mem:DI (match_operand:I48MODE 0 "call_address_operand" "rO,i"))
2487 (match_operand 1 "" ""))
2488 (use (reg:DI 54))]
2489 "SIBLING_CALL_P(insn)"
2490 "@
2491 jr\t%r0
2492 j\t%p0"
2493 [(set_attr "type" "X1,X1")])
2495 (define_expand "sibcall_value"
2496 [(parallel [(set (match_operand 0 "" "")
2497 (call (match_operand:DI 1 "call_operand" "")
2498 (match_operand 2 "" "")))
2499 (use (reg:DI 54))])]
2500 ""
2501 "")
2503 (define_insn "*sibcall_value"
2504 [(set (match_operand 0 "" "")
2505 (call (mem:DI (match_operand:I48MODE 1 "call_address_operand" "rO,i"))
2506 (match_operand 2 "" "")))
2507 (use (reg:DI 54))]
2508 "SIBLING_CALL_P(insn)"
2509 "@
2510 jr\t%r1
2511 j\t%p1"
2512 [(set_attr "type" "X1,X1")])
2514 (define_insn "jump"
2515 [(set (pc) (label_ref (match_operand 0 "" "")))]
2516 ""
2517 "j\t%l0"
2518 [(set_attr "type" "X1")])
2520 (define_insn "indirect_jump"
2521 [(set (pc) (match_operand 0 "pointer_operand" "rO"))]
2522 ""
2523 "jr\t%r0"
2524 [(set_attr "type" "Y1")])
2526 (define_expand "return"
2527 [(parallel
2528 [(return)
2529 (use (reg:DI 55))])]
2530 "tilegx_can_use_return_insn_p ()"
2531 "")
2533 (define_insn "_return"
2534 [(return)
2535 (use (reg:DI 55))]
2536 "reload_completed"
2537 "jrp\tlr"
2538 [(set_attr "type" "Y1")])
2540 (define_expand "tablejump"
2541 [(set (pc) (match_operand 0 "pointer_operand" ""))
2542 (use (label_ref (match_operand 1 "" "")))]
2543 ""
2544 {
2545 tilegx_expand_tablejump (operands[0], operands[1]);
2546 DONE;
2547 })
2549 (define_insn "tablejump_aux"
2550 [(set (pc) (match_operand 0 "pointer_operand" "rO"))
2551 (use (label_ref (match_operand 1 "" "")))]
2552 ""
2553 "jr\t%r0"
2554 [(set_attr "type" "Y1")])
2556 ;; Call subroutine returning any type.
2557 (define_expand "untyped_call"
2558 [(parallel [(call (match_operand 0 "" "")
2559 (const_int 0))
2560 (match_operand 1 "" "")
2561 (match_operand 2 "" "")])]
2562 ""
2563 {
2564 int i;
2566 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2568 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2569 {
2570 rtx set = XVECEXP (operands[2], 0, i);
2571 emit_move_insn (SET_DEST (set), SET_SRC (set));
2572 }
2574 /* The optimizer does not know that the call sets the function value
2575 registers we stored in the result block. We avoid problems by
2576 claiming that all hard registers are used and clobbered at this
2577 point. */
2578 emit_insn (gen_blockage ());
2580 DONE;
2581 })
2583 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers
2584 ;; and all of memory. This blocks insns from being moved across this
2585 ;; point.
2586 (define_insn "blockage"
2587 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
2588 ""
2589 "pseudo"
2590 [(set_attr "type" "nothing")
2591 (set_attr "length" "0")])
2593 ;; Internal expanders to prevent memory ops from moving around frame
2594 ;; allocation/deallocation.
2595 ;;
2596 ;; TODO: really this clobber should just clobber the frame memory. Is
2597 ;; this possibly by clobbering memory @ the sp reg (as alpha does?)
2598 ;; or by explicitly setting the alias set to the frame?
2599 (define_insn "sp_adjust"
2600 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
2601 (plus:DI
2602 (match_operand:DI 1 "register_operand" "%r,r,r")
2603 (match_operand:DI 2 "add_operand" "r,I,JT")))
2604 (clobber (mem:BLK (scratch)))]
2605 ""
2606 "@
2607 add\t%0, %1, %2
2608 addi\t%0, %1, %2
2609 addli\t%0, %1, %H2"
2610 [(set_attr "type" "*,*,X01")])
2612 (define_insn "sp_adjust_32bit"
2613 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2614 (plus:SI
2615 (match_operand:SI 1 "register_operand" "%r,r,r")
2616 (match_operand:SI 2 "add_operand" "r,I,JT")))
2617 (clobber (mem:BLK (scratch)))]
2618 ""
2619 "@
2620 addx\t%0, %1, %2
2621 addxi\t%0, %1, %2
2622 addxli\t%0, %1, %H2"
2623 [(set_attr "type" "*,*,X01")])
2625 ;; Used for move sp, r52, to pop a stack frame. We need to make sure
2626 ;; that stack frame memory operations have been issued before we do
2627 ;; this. TODO: see above TODO.
2628 (define_insn "sp_restore<bitsuffix>"
2629 [(set (match_operand:I48MODE 0 "register_operand" "=r")
2630 (match_operand:I48MODE 1 "register_operand" "r"))
2631 (clobber (mem:BLK (scratch)))]
2632 ""
2633 "move\t%0, %1")
2635 (define_insn "nop"
2636 [(const_int 0)]
2637 ""
2638 "nop"
2639 [(set_attr "type" "Y01")])
2641 \f
2642 ;;
2643 ;; Conditional branches
2644 ;;
2646 (define_expand "cbranch<mode>4"
2647 [(set (pc)
2648 (if_then_else (match_operator 0 "ordered_comparison_operator"
2649 [(match_operand:FI48MODE 1 "reg_or_cint_operand")
2650 (match_operand:FI48MODE 2 "reg_or_cint_operand")])
2651 (label_ref (match_operand 3 ""))
2652 (pc)))]
2653 ""
2654 {
2655 tilegx_emit_conditional_branch (operands, GET_MODE (operands[1]));
2656 DONE;
2657 })
2659 (define_insn "*bcc_normal<mode>"
2660 [(set (pc)
2661 (if_then_else
2662 (match_operator 1 "signed_comparison_operator"
2663 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2664 (const_int 0)])
2665 (label_ref (match_operand 0 "" ""))
2666 (pc)))]
2667 ""
2668 { return tilegx_output_cbranch (insn, operands, false); }
2669 [(set_attr "type" "X1_branch")])
2671 (define_insn "*bcc_reverse<mode>"
2672 [(set (pc)
2673 (if_then_else
2674 (match_operator 1 "signed_comparison_operator"
2675 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2676 (const_int 0)])
2677 (pc)
2678 (label_ref (match_operand 0 "" ""))))]
2679 ""
2680 { return tilegx_output_cbranch (insn, operands, true); }
2681 [(set_attr "type" "X1_branch")])
2683 (define_insn "*blbs_normal<mode>"
2684 [(set (pc)
2685 (if_then_else
2686 (ne (zero_extract:I48MODE
2687 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
2688 (const_int 1)
2689 (const_int 0))
2690 (const_int 0))
2691 (label_ref (match_operand 0 "" ""))
2692 (pc)))]
2693 ""
2694 { return tilegx_output_cbranch_with_opcode (insn, operands, "blbs", "blbc",
2695 1); }
2696 [(set_attr "type" "X1_branch")])
2698 (define_insn "*blbc_normal<mode>"
2699 [(set (pc)
2700 (if_then_else
2701 (eq (zero_extract:I48MODE
2702 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
2703 (const_int 1)
2704 (const_int 0))
2705 (const_int 0))
2706 (label_ref (match_operand 0 "" ""))
2707 (pc)))]
2708 ""
2709 { return tilegx_output_cbranch_with_opcode (insn, operands, "blbc", "blbs",
2710 1); }
2711 [(set_attr "type" "X1_branch")])
2713 ;; Note that __insn_mf() expands to this.
2714 (define_expand "memory_barrier"
2715 [(set (match_dup 0)
2716 (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
2717 ""
2718 {
2719 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
2720 MEM_VOLATILE_P (operands[0]) = 1;
2721 })
2723 (define_insn "*memory_barrier"
2724 [(set (match_operand:BLK 0 "" "")
2725 (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
2726 ""
2727 "mf"
2728 [(set_attr "type" "X1")])
2730 (define_insn "prefetch"
2731 [(prefetch (match_operand 0 "address_operand" "rO")
2732 (match_operand 1 "const_int_operand" "")
2733 (match_operand 2 "const_int_operand" ""))]
2734 ""
2735 {
2736 switch (INTVAL (operands[2]))
2737 {
2738 case 0:
2739 case 1: return "prefetch_l3\t%r0";
2740 case 2: return "prefetch_l2\t%r0";
2741 case 3: return "prefetch_l1\t%r0";
2742 default: gcc_unreachable ();
2743 }
2744 }
2745 [(set_attr "type" "Y2")])
2747 \f
2748 ;;
2749 ;; "__insn" Intrinsics (some expand directly to normal patterns above).
2750 ;;
2752 (define_insn "insn_bfexts"
2753 [(set (match_operand:DI 0 "register_operand" "=r")
2754 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2755 (match_operand:DI 2 "u6bit_cint_operand" "n")
2756 (match_operand:DI 3 "u6bit_cint_operand" "n")]
2757 UNSPEC_INSN_BFEXTS))]
2758 ""
2759 "bfexts\t%0, %r1, %2, %3"
2760 [(set_attr "type" "X0")])
2762 (define_insn "insn_bfextu"
2763 [(set (match_operand:DI 0 "register_operand" "=r")
2764 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2765 (match_operand:DI 2 "u6bit_cint_operand" "n")
2766 (match_operand:DI 3 "u6bit_cint_operand" "n")]
2767 UNSPEC_INSN_BFEXTU))]
2768 ""
2769 "bfextu\t%0, %r1, %2, %3"
2770 [(set_attr "type" "X0")])
2772 (define_insn "insn_bfins"
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2775 (match_operand:DI 2 "reg_or_0_operand" "rO")
2776 (match_operand:DI 3 "u6bit_cint_operand" "n")
2777 (match_operand:DI 4 "u6bit_cint_operand" "n")]
2778 UNSPEC_INSN_BFINS))]
2779 ""
2780 "bfins\t%0, %r2, %3, %4"
2781 [(set_attr "type" "X0")])
2783 (define_insn "insn_cmpexch<four_if_si>"
2784 [(set (match_operand:I48MODE 0 "register_operand" "=r")
2785 (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
2786 (set (mem:I48MODE (match_dup 1))
2787 (unspec_volatile:I48MODE
2788 [(mem:I48MODE (match_dup 1))
2789 (reg:I48MODE TILEGX_CMPEXCH_REG)
2790 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
2791 UNSPEC_INSN_CMPEXCH))]
2792 ""
2793 "cmpexch<four_if_si>\t%0, %r1, %r2"
2794 [(set_attr "type" "X1_remote")])
2796 (define_insn "insn_cmul"
2797 [(set (match_operand:DI 0 "register_operand" "=r")
2798 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2799 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2800 UNSPEC_INSN_CMUL))]
2801 ""
2802 "cmul\t%0, %r1, %r2"
2803 [(set_attr "type" "X0_2cycle")])
2805 (define_insn "insn_cmula"
2806 [(set (match_operand:DI 0 "register_operand" "=r")
2807 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2808 (match_operand:DI 2 "reg_or_0_operand" "rO")
2809 (match_operand:DI 3 "reg_or_0_operand" "rO")]
2810 UNSPEC_INSN_CMULA))]
2811 ""
2812 "cmula\t%0, %r2, %r3"
2813 [(set_attr "type" "X0_2cycle")])
2815 (define_insn "insn_cmulaf"
2816 [(set (match_operand:DI 0 "register_operand" "=r")
2817 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2818 (match_operand:DI 2 "reg_or_0_operand" "rO")
2819 (match_operand:DI 3 "reg_or_0_operand" "rO")]
2820 UNSPEC_INSN_CMULAF))]
2821 ""
2822 "cmulaf\t%0, %r2, %r3"
2823 [(set_attr "type" "X0_2cycle")])
2825 (define_insn "insn_cmulf"
2826 [(set (match_operand:DI 0 "register_operand" "=r")
2827 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2828 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2829 UNSPEC_INSN_CMULF))]
2830 ""
2831 "cmulf\t%0, %r1, %r2"
2832 [(set_attr "type" "X0_2cycle")])
2834 (define_insn "insn_cmulfr"
2835 [(set (match_operand:DI 0 "register_operand" "=r")
2836 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2837 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2838 UNSPEC_INSN_CMULFR))]
2839 ""
2840 "cmulfr\t%0, %r1, %r2"
2841 [(set_attr "type" "X0_2cycle")])
2843 (define_insn "insn_cmulh"
2844 [(set (match_operand:DI 0 "register_operand" "=r")
2845 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2846 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2847 UNSPEC_INSN_CMULH))]
2848 ""
2849 "cmulh\t%0, %r1, %r2"
2850 [(set_attr "type" "X0_2cycle")])
2852 (define_insn "insn_cmulhr"
2853 [(set (match_operand:DI 0 "register_operand" "=r")
2854 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2855 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2856 UNSPEC_INSN_CMULHR))]
2857 ""
2858 "cmulhr\t%0, %r1, %r2"
2859 [(set_attr "type" "X0_2cycle")])
2861 (define_insn "insn_crc32_32"
2862 [(set (match_operand:DI 0 "register_operand" "=r")
2863 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2864 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2865 UNSPEC_INSN_CRC32_32))]
2866 ""
2867 "crc32_32\t%0, %r1, %r2"
2868 [(set_attr "type" "X0")])
2870 (define_insn "insn_crc32_8"
2871 [(set (match_operand:DI 0 "register_operand" "=r")
2872 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2873 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2874 UNSPEC_INSN_CRC32_8))]
2875 ""
2876 "crc32_8\t%0, %r1, %r2"
2877 [(set_attr "type" "X0")])
2879 (define_insn "insn_dblalign"
2880 [(set (match_operand:DI 0 "register_operand" "=r")
2881 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2882 (match_operand:DI 2 "reg_or_0_operand" "rO")
2883 (match_operand 3 "pointer_operand" "rO")]
2884 UNSPEC_INSN_DBLALIGN))]
2885 ""
2886 "dblalign\t%0, %r2, %r3"
2887 [(set_attr "type" "X0")])
2889 (define_insn "insn_dblalign2"
2890 [(set (match_operand:DI 0 "register_operand" "=r")
2891 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2892 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2893 UNSPEC_INSN_DBLALIGN2))]
2894 ""
2895 "dblalign2\t%0, %r1, %r2"
2896 [(set_attr "type" "X01")])
2898 (define_insn "insn_dblalign4"
2899 [(set (match_operand:DI 0 "register_operand" "=r")
2900 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2901 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2902 UNSPEC_INSN_DBLALIGN4))]
2903 ""
2904 "dblalign4\t%0, %r1, %r2"
2905 [(set_attr "type" "X01")])
2907 (define_insn "insn_dblalign6"
2908 [(set (match_operand:DI 0 "register_operand" "=r")
2909 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2910 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2911 UNSPEC_INSN_DBLALIGN6))]
2912 ""
2913 "dblalign6\t%0, %r1, %r2"
2914 [(set_attr "type" "X01")])
2916 (define_insn "insn_dtlbpr"
2917 [(unspec_volatile:VOID [(match_operand:DI 0 "reg_or_0_operand" "rO")]
2918 UNSPEC_INSN_DTLBPR)]
2919 ""
2920 "dtlbpr\t%r0"
2921 [(set_attr "type" "X1")])
2923 (define_insn "insn_exch<four_if_si>"
2924 [(set (match_operand:I48MODE 0 "register_operand" "=r")
2925 (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
2926 (set (mem:I48MODE (match_dup 1))
2927 (unspec_volatile:I48MODE
2928 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
2929 UNSPEC_INSN_EXCH))]
2930 ""
2931 "exch<four_if_si>\t%0, %r1, %r2"
2932 [(set_attr "type" "X1_remote")])
2934 (define_insn "insn_fdouble_add_flags"
2935 [(set (match_operand:DI 0 "register_operand" "=r")
2936 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2937 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2938 UNSPEC_INSN_FDOUBLE_ADD_FLAGS))]
2939 ""
2940 "fdouble_add_flags\t%0, %r1, %r2"
2941 [(set_attr "type" "X0_2cycle")])
2943 (define_insn "insn_fdouble_addsub"
2944 [(set (match_operand:DI 0 "register_operand" "=r")
2945 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2946 (match_operand:DI 2 "reg_or_0_operand" "rO")
2947 (match_operand:DI 3 "reg_or_0_operand" "rO")]
2948 UNSPEC_INSN_FDOUBLE_ADDSUB))]
2949 ""
2950 "fdouble_addsub\t%0, %r2, %r3"
2951 [(set_attr "type" "X0_2cycle")])
2953 (define_insn "insn_fdouble_mul_flags"
2954 [(set (match_operand:DI 0 "register_operand" "=r")
2955 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2956 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2957 UNSPEC_INSN_FDOUBLE_MUL_FLAGS))]
2958 ""
2959 "fdouble_mul_flags\t%0, %r1, %r2"
2960 [(set_attr "type" "X0_2cycle")])
2962 (define_insn "insn_fdouble_pack1"
2963 [(set (match_operand:DI 0 "register_operand" "=r")
2964 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2965 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2966 UNSPEC_INSN_FDOUBLE_PACK1))]
2967 ""
2968 "fdouble_pack1\t%0, %r1, %r2"
2969 [(set_attr "type" "X0_2cycle")])
2971 (define_insn "insn_fdouble_pack2"
2972 [(set (match_operand:DI 0 "register_operand" "=r")
2973 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2974 (match_operand:DI 2 "reg_or_0_operand" "rO")
2975 (match_operand:DI 3 "reg_or_0_operand" "rO")]
2976 UNSPEC_INSN_FDOUBLE_PACK2))]
2977 ""
2978 "fdouble_pack2\t%0, %r2, %r3"
2979 [(set_attr "type" "X0_2cycle")])
2981 (define_insn "insn_fdouble_sub_flags"
2982 [(set (match_operand:DI 0 "register_operand" "=r")
2983 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2984 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2985 UNSPEC_INSN_FDOUBLE_SUB_FLAGS))]
2986 ""
2987 "fdouble_sub_flags\t%0, %r1, %r2"
2988 [(set_attr "type" "X0_2cycle")])
2990 (define_insn "insn_fdouble_unpack_max"
2991 [(set (match_operand:DI 0 "register_operand" "=r")
2992 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2993 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2994 UNSPEC_INSN_FDOUBLE_UNPACK_MAX))]
2995 ""
2996 "fdouble_unpack_max\t%0, %r1, %r2"
2997 [(set_attr "type" "X0_2cycle")])
2999 (define_insn "insn_fdouble_unpack_min"
3000 [(set (match_operand:DI 0 "register_operand" "=r")
3001 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3002 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3003 UNSPEC_INSN_FDOUBLE_UNPACK_MIN))]
3004 ""
3005 "fdouble_unpack_min\t%0, %r1, %r2"
3006 [(set_attr "type" "X0_2cycle")])
3008 (define_insn "insn_fetchadd<four_if_si>"
3009 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3010 (unspec_volatile:I48MODE
3011 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3012 UNSPEC_ATOMIC))
3013 (set (mem:I48MODE (match_dup 1))
3014 (plus:I48MODE (mem:I48MODE (match_dup 1))
3015 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
3016 ""
3017 "fetchadd<four_if_si>\t%0, %r1, %r2"
3018 [(set_attr "type" "X1_remote")])
3020 (define_insn "insn_fetchaddgez<four_if_si>"
3021 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3022 (unspec_volatile:I48MODE
3023 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3024 UNSPEC_ATOMIC))
3025 (set (mem:I48MODE (match_dup 1))
3026 (unspec:I48MODE [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
3027 (mem:I48MODE (match_dup 1))]
3028 UNSPEC_INSN_FETCHADDGEZ))]
3029 ""
3030 "fetchaddgez<four_if_si>\t%0, %r1, %r2"
3031 [(set_attr "type" "X1_remote")])
3033 (define_insn "insn_fetchand<four_if_si>"
3034 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3035 (unspec_volatile:I48MODE
3036 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3037 UNSPEC_ATOMIC))
3038 (set (mem:I48MODE (match_dup 1))
3039 (and:I48MODE (mem:I48MODE (match_dup 1))
3040 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
3041 ""
3042 "fetchand<four_if_si>\t%0, %r1, %r2"
3043 [(set_attr "type" "X1_remote")])
3045 (define_insn "insn_fetchor<four_if_si>"
3046 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3047 (unspec_volatile:I48MODE
3048 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3049 UNSPEC_ATOMIC))
3050 (set (mem:I48MODE (match_dup 1))
3051 (ior:I48MODE (mem:I48MODE (match_dup 1))
3052 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
3053 ""
3054 "fetchor<four_if_si>\t%0, %r1, %r2"
3055 [(set_attr "type" "X1_remote")])
3057 (define_insn "insn_finv"
3058 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3059 UNSPEC_INSN_FINV)]
3060 ""
3061 "finv\t%r0"
3062 [(set_attr "type" "X1")])
3064 (define_insn "insn_flush"
3065 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3066 UNSPEC_INSN_FLUSH)]
3067 ""
3068 "flush\t%r0"
3069 [(set_attr "type" "X1")])
3071 (define_insn "insn_flushwb"
3072 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FLUSHWB)]
3073 ""
3074 "flushwb"
3075 [(set_attr "type" "X1")])
3077 (define_insn "insn_fnop"
3078 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FNOP)]
3079 ""
3080 "fnop")
3082 (define_insn "insn_fsingle_add1"
3083 [(set (match_operand:DI 0 "register_operand" "=r")
3084 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3085 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3086 UNSPEC_INSN_FSINGLE_ADD1))]
3087 ""
3088 "fsingle_add1\t%0, %r1, %r2"
3089 [(set_attr "type" "X0")])
3091 (define_insn "insn_fsingle_addsub2"
3092 [(set (match_operand:DI 0 "register_operand" "=r")
3093 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3094 (match_operand:DI 2 "reg_or_0_operand" "rO")
3095 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3096 UNSPEC_INSN_FSINGLE_ADDSUB2))]
3097 ""
3098 "fsingle_addsub2\t%0, %r2, %r3"
3099 [(set_attr "type" "X0_2cycle")])
3101 (define_insn "insn_fsingle_mul1"
3102 [(set (match_operand:DI 0 "register_operand" "=r")
3103 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3104 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3105 UNSPEC_INSN_FSINGLE_MUL1))]
3106 ""
3107 "fsingle_mul1\t%0, %r1, %r2"
3108 [(set_attr "type" "X0")])
3110 (define_insn "insn_fsingle_mul2"
3111 [(set (match_operand:DI 0 "register_operand" "=r")
3112 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3113 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3114 UNSPEC_INSN_FSINGLE_MUL2))]
3115 ""
3116 "fsingle_mul2\t%0, %r1, %r2"
3117 [(set_attr "type" "X0_2cycle")])
3119 (define_insn "insn_fsingle_pack1"
3120 [(set (match_operand:DI 0 "register_operand" "=r")
3121 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")]
3122 UNSPEC_INSN_FSINGLE_PACK1))]
3123 ""
3124 "fsingle_pack1\t%0, %r1"
3125 [(set_attr "type" "Y0_2cycle")])
3127 (define_insn "insn_fsingle_pack2"
3128 [(set (match_operand:DI 0 "register_operand" "=r")
3129 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3130 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3131 UNSPEC_INSN_FSINGLE_PACK2))]
3132 ""
3133 "fsingle_pack2\t%0, %r1, %r2"
3134 [(set_attr "type" "X0_2cycle")])
3136 (define_insn "insn_fsingle_sub1"
3137 [(set (match_operand:DI 0 "register_operand" "=r")
3138 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3139 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3140 UNSPEC_INSN_FSINGLE_SUB1))]
3141 ""
3142 "fsingle_sub1\t%0, %r1, %r2"
3143 [(set_attr "type" "X0")])
3145 (define_insn "insn_drain"
3146 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_DRAIN)]
3147 ""
3148 "drain"
3149 [(set_attr "type" "cannot_bundle")])
3151 (define_insn "insn_icoh"
3152 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3153 UNSPEC_INSN_ICOH)]
3154 ""
3155 "icoh\t%r0"
3156 [(set_attr "type" "X1")])
3158 (define_insn "insn_ill"
3159 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_ILL)]
3160 ""
3161 "ill"
3162 [(set_attr "type" "cannot_bundle")])
3164 (define_insn "insn_info"
3165 [(unspec_volatile:VOID [(match_operand:DI 0 "s8bit_cint_operand" "i")]
3166 UNSPEC_INSN_INFO)]
3167 ""
3168 "info\t%0")
3170 (define_insn "insn_infol"
3171 [(unspec_volatile:VOID [(match_operand:DI 0 "s16bit_cint_operand" "i")]
3172 UNSPEC_INSN_INFOL)]
3173 ""
3174 "infol\t%0"
3175 [(set_attr "type" "X01")])
3177 (define_insn "insn_inv"
3178 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3179 UNSPEC_INSN_INV)]
3180 ""
3181 "inv\t%r0"
3182 [(set_attr "type" "X1")])
3184 ;; loads
3186 (define_expand "insn_ld"
3187 [(set (match_operand:DI 0 "register_operand" "")
3188 (mem:DI (match_operand 1 "pointer_operand" "")))]
3189 "")
3191 (define_insn "insn_ld_add<bitsuffix>"
3192 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3193 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3194 (match_operand 2 "s8bit_cint_operand" "i")))
3195 (set (match_operand:DI 0 "register_operand" "=r")
3196 (mem:DI (match_dup 3)))]
3197 ""
3198 "ld_add\t%0, %1, %2"
3199 [(set_attr "type" "X1_2cycle")])
3201 (define_insn "insn_ldna"
3202 [(set (match_operand:DI 0 "register_operand" "=r")
3203 (mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3204 (const_int -8))))]
3205 ""
3206 "ldna\t%0, %r1"
3207 [(set_attr "type" "X1_2cycle")])
3209 (define_insn "insn_ldna_add<bitsuffix>"
3210 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3211 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3212 (match_operand 2 "s8bit_cint_operand" "i")))
3213 (set (match_operand:DI 0 "register_operand" "=r")
3214 (mem:DI (and:DI (match_dup 3) (const_int -8))))]
3215 ""
3216 "ldna_add\t%0, %1, %2"
3217 [(set_attr "type" "X1_2cycle")])
3219 (define_expand "insn_ld<n><s>"
3220 [(set (match_operand:DI 0 "register_operand" "")
3221 (any_extend:DI
3222 (mem:I124MODE (match_operand 1 "pointer_operand" ""))))]
3223 "")
3225 (define_insn "insn_ld<I124MODE:n><s>_add<I48MODE:bitsuffix>"
3226 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3227 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3228 (match_operand 2 "s8bit_cint_operand" "i")))
3229 (set (match_operand:DI 0 "register_operand" "=r")
3230 (any_extend:DI (mem:I124MODE (match_dup 3))))]
3231 ""
3232 "ld<I124MODE:n><s>_add\t%0, %1, %2"
3233 [(set_attr "type" "X1_2cycle")])
3235 ;; non temporal loads
3237 (define_insn "insn_ldnt"
3238 [(set (match_operand:DI 0 "register_operand" "=r")
3239 (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3240 UNSPEC_NON_TEMPORAL))]
3241 ""
3242 "ldnt\t%0, %r1"
3243 [(set_attr "type" "X1_2cycle")])
3245 (define_insn "insn_ldnt_add<bitsuffix>"
3246 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3247 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3248 (match_operand 2 "s8bit_cint_operand" "i")))
3249 (set (match_operand:DI 0 "register_operand" "=r")
3250 (unspec:DI [(mem:DI (match_dup 3))]
3251 UNSPEC_NON_TEMPORAL))]
3252 ""
3253 "ldnt_add\t%0, %1, %2"
3254 [(set_attr "type" "X1_2cycle")])
3256 (define_insn "insn_ldnt<n><s>"
3257 [(set (match_operand:DI 0 "register_operand" "=r")
3258 (any_extend:DI
3259 (unspec:I124MODE
3260 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3261 UNSPEC_NON_TEMPORAL)))]
3262 ""
3263 "ldnt<n><s>\t%0, %r1"
3264 [(set_attr "type" "X1_2cycle")])
3266 (define_insn "insn_ldnt<I124MODE:n><s>_add<I48MODE:bitsuffix>"
3267 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3268 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3269 (match_operand 2 "s8bit_cint_operand" "i")))
3270 (set (match_operand:DI 0 "register_operand" "=r")
3271 (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3272 UNSPEC_NON_TEMPORAL)))]
3273 ""
3274 "ldnt<I124MODE:n><s>_add\t%0, %1, %2"
3275 [(set_attr "type" "X1_2cycle")])
3277 ;; L2 hits
3279 (define_insn "insn_ld_L2"
3280 [(set (match_operand:DI 0 "register_operand" "=r")
3281 (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3282 UNSPEC_LATENCY_L2))]
3283 ""
3284 "ld\t%0, %r1"
3285 [(set_attr "type" "Y2_L2")])
3287 (define_insn "insn_ld_add_L2<bitsuffix>"
3288 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3289 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3290 (match_operand 2 "s8bit_cint_operand" "i")))
3291 (set (match_operand:DI 0 "register_operand" "=r")
3292 (unspec:DI [(mem:DI (match_dup 3))]
3293 UNSPEC_LATENCY_L2))]
3294 ""
3295 "ld_add\t%0, %1, %2"
3296 [(set_attr "type" "X1_L2")])
3298 (define_insn "insn_ldna_L2"
3299 [(set (match_operand:DI 0 "register_operand" "=r")
3300 (unspec:DI [(mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3301 (const_int -8)))]
3302 UNSPEC_LATENCY_L2))]
3303 ""
3304 "ldna\t%0, %r1"
3305 [(set_attr "type" "X1_L2")])
3307 (define_insn "insn_ldna_add_L2<bitsuffix>"
3308 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3309 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3310 (match_operand 2 "s8bit_cint_operand" "i")))
3311 (set (match_operand:DI 0 "register_operand" "=r")
3312 (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))]
3313 UNSPEC_LATENCY_L2))]
3314 ""
3315 "ldna_add\t%0, %1, %2"
3316 [(set_attr "type" "X1_L2")])
3318 (define_insn "insn_ld<n><s>_L2"
3319 [(set (match_operand:DI 0 "register_operand" "=r")
3320 (any_extend:DI
3321 (unspec:I124MODE
3322 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3323 UNSPEC_LATENCY_L2)))]
3324 ""
3325 "ld<n><s>\t%0, %r1"
3326 [(set_attr "type" "Y2_L2")])
3328 (define_insn "insn_ld<I124MODE:n><s>_add_L2<I48MODE:bitsuffix>"
3329 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3330 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3331 (match_operand 2 "s8bit_cint_operand" "i")))
3332 (set (match_operand:DI 0 "register_operand" "=r")
3333 (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3334 UNSPEC_LATENCY_L2)))]
3335 ""
3336 "ld<I124MODE:n><s>_add\t%0, %1, %2"
3337 [(set_attr "type" "X1_L2")])
3339 ;; L2 hits, non temporal loads
3341 (define_insn "insn_ldnt_L2"
3342 [(set (match_operand:DI 0 "register_operand" "=r")
3343 (unspec:DI [(unspec:DI
3344 [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3345 UNSPEC_NON_TEMPORAL)]
3346 UNSPEC_LATENCY_L2))]
3347 ""
3348 "ldnt\t%0, %r1"
3349 [(set_attr "type" "X1_L2")])
3351 (define_insn "insn_ldnt_add_L2<bitsuffix>"
3352 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3353 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3354 (match_operand 2 "s8bit_cint_operand" "i")))
3355 (set (match_operand:DI 0 "register_operand" "=r")
3356 (unspec:DI [(unspec:DI
3357 [(mem:DI (match_dup 3))]
3358 UNSPEC_NON_TEMPORAL)]
3359 UNSPEC_LATENCY_L2))]
3360 ""
3361 "ldnt_add\t%0, %1, %2"
3362 [(set_attr "type" "X1_L2")])
3364 (define_insn "insn_ldnt<n><s>_L2"
3365 [(set (match_operand:DI 0 "register_operand" "=r")
3366 (any_extend:DI
3367 (unspec:I124MODE
3368 [(unspec:I124MODE
3369 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3370 UNSPEC_NON_TEMPORAL)]
3371 UNSPEC_LATENCY_L2)))]
3372 ""
3373 "ldnt<n><s>\t%0, %r1"
3374 [(set_attr "type" "X1_L2")])
3376 (define_insn "insn_ldnt<I124MODE:n><s>_add_L2<I48MODE:bitsuffix>"
3377 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3378 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3379 (match_operand 2 "s8bit_cint_operand" "i")))
3380 (set (match_operand:DI 0 "register_operand" "=r")
3381 (any_extend:DI
3382 (unspec:I124MODE [(unspec:I124MODE
3383 [(mem:I124MODE (match_dup 3))]
3384 UNSPEC_NON_TEMPORAL)]
3385 UNSPEC_LATENCY_L2)))]
3386 ""
3387 "ldnt<I124MODE:n><s>_add\t%0, %1, %2"
3388 [(set_attr "type" "X1_L2")])
3390 ;; L2 miss
3392 (define_insn "insn_ld_miss"
3393 [(set (match_operand:DI 0 "register_operand" "=r")
3394 (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3395 UNSPEC_LATENCY_MISS))]
3396 ""
3397 "ld\t%0, %r1"
3398 [(set_attr "type" "Y2_miss")])
3400 (define_insn "insn_ld_add_miss<bitsuffix>"
3401 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3402 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3403 (match_operand 2 "s8bit_cint_operand" "i")))
3404 (set (match_operand:DI 0 "register_operand" "=r")
3405 (unspec:DI [(mem:DI (match_dup 3))]
3406 UNSPEC_LATENCY_MISS))]
3407 ""
3408 "ld_add\t%0, %1, %2"
3409 [(set_attr "type" "X1_miss")])
3411 (define_insn "insn_ldna_miss"
3412 [(set (match_operand:DI 0 "register_operand" "=r")
3413 (unspec:DI [(mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3414 (const_int -8)))]
3415 UNSPEC_LATENCY_MISS))]
3416 ""
3417 "ldna\t%0, %r1"
3418 [(set_attr "type" "X1_miss")])
3420 (define_insn "insn_ldna_add_miss<bitsuffix>"
3421 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3422 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3423 (match_operand 2 "s8bit_cint_operand" "i")))
3424 (set (match_operand:DI 0 "register_operand" "=r")
3425 (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))]
3426 UNSPEC_LATENCY_MISS))]
3427 ""
3428 "ldna_add\t%0, %1, %2"
3429 [(set_attr "type" "X1_miss")])
3431 (define_insn "insn_ld<n><s>_miss"
3432 [(set (match_operand:DI 0 "register_operand" "=r")
3433 (any_extend:DI
3434 (unspec:I124MODE
3435 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3436 UNSPEC_LATENCY_MISS)))]
3437 ""
3438 "ld<n><s>\t%0, %r1"
3439 [(set_attr "type" "Y2_miss")])
3441 (define_insn "insn_ld<I124MODE:n><s>_add_miss<I48MODE:bitsuffix>"
3442 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3443 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3444 (match_operand 2 "s8bit_cint_operand" "i")))
3445 (set (match_operand:DI 0 "register_operand" "=r")
3446 (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3447 UNSPEC_LATENCY_MISS)))]
3448 ""
3449 "ld<I124MODE:n><s>_add\t%0, %1, %2"
3450 [(set_attr "type" "X1_miss")])
3452 ;; L2 miss, non temporal loads
3454 (define_insn "insn_ldnt_miss"
3455 [(set (match_operand:DI 0 "register_operand" "=r")
3456 (unspec:DI [(unspec:DI
3457 [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3458 UNSPEC_NON_TEMPORAL)]
3459 UNSPEC_LATENCY_MISS))]
3460 ""
3461 "ldnt\t%0, %r1"
3462 [(set_attr "type" "X1_miss")])
3464 (define_insn "insn_ldnt_add_miss<bitsuffix>"
3465 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3466 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3467 (match_operand 2 "s8bit_cint_operand" "i")))
3468 (set (match_operand:DI 0 "register_operand" "=r")
3469 (unspec:DI [(unspec:DI
3470 [(mem:DI (match_dup 3))]
3471 UNSPEC_NON_TEMPORAL)]
3472 UNSPEC_LATENCY_MISS))]
3473 ""
3474 "ldnt_add\t%0, %1, %2"
3475 [(set_attr "type" "X1_miss")])
3477 (define_insn "insn_ldnt<n><s>_miss"
3478 [(set (match_operand:DI 0 "register_operand" "=r")
3479 (any_extend:DI
3480 (unspec:I124MODE
3481 [(unspec:I124MODE
3482 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3483 UNSPEC_NON_TEMPORAL)]
3484 UNSPEC_LATENCY_MISS)))]
3485 ""
3486 "ldnt<n><s>\t%0, %r1"
3487 [(set_attr "type" "X1_miss")])
3489 (define_insn "insn_ldnt<I124MODE:n><s>_add_miss<I48MODE:bitsuffix>"
3490 [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3491 (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3492 (match_operand 2 "s8bit_cint_operand" "i")))
3493 (set (match_operand:DI 0 "register_operand" "=r")
3494 (any_extend:DI
3495 (unspec:I124MODE [(unspec:I124MODE
3496 [(mem:I124MODE (match_dup 3))]
3497 UNSPEC_NON_TEMPORAL)]
3498 UNSPEC_LATENCY_MISS)))]
3499 ""
3500 "ldnt<I124MODE:n><s>_add\t%0, %1, %2"
3501 [(set_attr "type" "X1_miss")])
3503 ;; end loads
3505 (define_insn "insn_lnk"
3506 [(set (match_operand:DI 0 "register_operand" "=r")
3507 (unspec:DI [(const_int 0)] UNSPEC_INSN_LNK))]
3508 ""
3509 "lnk\t%0"
3510 [(set_attr "type" "Y1")])
3512 (define_insn "insn_mfspr"
3513 [(set (match_operand:DI 0 "register_operand" "=r")
3514 (unspec_volatile:DI [(match_operand:DI 1 "u14bit_cint_operand" "i")]
3515 UNSPEC_INSN_MFSPR))
3516 (clobber (mem:BLK (const_int 0)))]
3517 ""
3518 "mfspr\t%0, %1"
3519 [(set_attr "type" "X1")])
3521 (define_insn "insn_mtspr"
3522 [(unspec_volatile:DI [(match_operand:DI 0 "u14bit_cint_operand" "i")
3523 (match_operand:DI 1 "reg_or_0_operand" "rO")]
3524 UNSPEC_INSN_MTSPR)
3525 (clobber (mem:BLK (const_int 0)))]
3526 ""
3527 "mtspr\t%0, %r1"
3528 [(set_attr "type" "X1")])
3530 (define_insn "insn_mm"
3531 [(set (match_operand:DI 0 "register_operand" "=r")
3532 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3533 (match_operand:DI 2 "reg_or_0_operand" "rO")
3534 (match_operand:DI 3 "u6bit_cint_operand" "i")
3535 (match_operand:DI 4 "u6bit_cint_operand" "i")]
3536 UNSPEC_INSN_MM))]
3537 ""
3538 "mm\t%0, %r2, %3, %4"
3539 [(set_attr "type" "X0")])
3541 (define_insn "insn_mul_hs_hs"
3542 [(set (match_operand:DI 0 "register_operand" "=r")
3543 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3544 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3545 UNSPEC_INSN_MUL_HS_HS))]
3546 ""
3547 "mul_hs_hs\t%0, %r1, %r2"
3548 [(set_attr "type" "Y0_2cycle")])
3550 (define_insn "insn_mul_hs_hu"
3551 [(set (match_operand:DI 0 "register_operand" "=r")
3552 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3553 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3554 UNSPEC_INSN_MUL_HS_HU))]
3555 ""
3556 "mul_hs_hu\t%0, %r1, %r2"
3557 [(set_attr "type" "X0_2cycle")])
3559 (define_insn "insn_mul_hs_ls"
3560 [(set (match_operand:DI 0 "register_operand" "=r")
3561 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3562 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3563 UNSPEC_INSN_MUL_HS_LS))]
3564 ""
3565 "mul_hs_ls\t%0, %r1, %r2"
3566 [(set_attr "type" "X0_2cycle")])
3568 (define_insn "insn_mul_hs_lu"
3569 [(set (match_operand:DI 0 "register_operand" "=r")
3570 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3571 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3572 UNSPEC_INSN_MUL_HS_LU))]
3573 ""
3574 "mul_hs_lu\t%0, %r1, %r2"
3575 [(set_attr "type" "X0_2cycle")])
3577 (define_insn "insn_mul_hu_hu"
3578 [(set (match_operand:DI 0 "register_operand" "=r")
3579 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3580 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3581 UNSPEC_INSN_MUL_HU_HU))]
3582 ""
3583 "mul_hu_hu\t%0, %r1, %r2"
3584 [(set_attr "type" "Y0_2cycle")])
3586 (define_insn "insn_mul_hu_ls"
3587 [(set (match_operand:DI 0 "register_operand" "=r")
3588 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3589 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3590 UNSPEC_INSN_MUL_HU_LS))]
3591 ""
3592 "mul_hu_ls\t%0, %r1, %r2"
3593 [(set_attr "type" "X0_2cycle")])
3595 (define_insn "insn_mul_hu_lu"
3596 [(set (match_operand:DI 0 "register_operand" "=r")
3597 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3598 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3599 UNSPEC_INSN_MUL_HU_LU))]
3600 ""
3601 "mul_hu_lu\t%0, %r1, %r2"
3602 [(set_attr "type" "X0_2cycle")])
3604 (define_insn "insn_mul_ls_ls"
3605 [(set (match_operand:DI 0 "register_operand" "=r")
3606 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3607 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3608 UNSPEC_INSN_MUL_LS_LS))]
3609 ""
3610 "mul_ls_ls\t%0, %r1, %r2"
3611 [(set_attr "type" "Y0_2cycle")])
3613 (define_insn "insn_mul_ls_lu"
3614 [(set (match_operand:DI 0 "register_operand" "=r")
3615 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3616 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3617 UNSPEC_INSN_MUL_LS_LU))]
3618 ""
3619 "mul_ls_lu\t%0, %r1, %r2"
3620 [(set_attr "type" "X0_2cycle")])
3622 (define_insn "insn_mul_lu_lu"
3623 [(set (match_operand:DI 0 "register_operand" "=r")
3624 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3625 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3626 UNSPEC_INSN_MUL_LU_LU))]
3627 ""
3628 "mul_lu_lu\t%0, %r1, %r2"
3629 [(set_attr "type" "Y0_2cycle")])
3631 (define_insn "insn_mula_hs_hs"
3632 [(set (match_operand:DI 0 "register_operand" "=r")
3633 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3634 (match_operand:DI 2 "reg_or_0_operand" "rO")
3635 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3636 UNSPEC_INSN_MULA_HS_HS))]
3637 ""
3638 "mula_hs_hs\t%0, %r2, %r3"
3639 [(set_attr "type" "Y0_2cycle")])
3641 (define_insn "insn_mula_hs_hu"
3642 [(set (match_operand:DI 0 "register_operand" "=r")
3643 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3644 (match_operand:DI 2 "reg_or_0_operand" "rO")
3645 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3646 UNSPEC_INSN_MULA_HS_HU))]
3647 ""
3648 "mula_hs_hu\t%0, %r2, %r3"
3649 [(set_attr "type" "X0_2cycle")])
3651 (define_insn "insn_mula_hs_ls"
3652 [(set (match_operand:DI 0 "register_operand" "=r")
3653 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3654 (match_operand:DI 2 "reg_or_0_operand" "rO")
3655 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3656 UNSPEC_INSN_MULA_HS_LS))]
3657 ""
3658 "mula_hs_ls\t%0, %r2, %r3"
3659 [(set_attr "type" "X0_2cycle")])
3661 (define_insn "insn_mula_hs_lu"
3662 [(set (match_operand:DI 0 "register_operand" "=r")
3663 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3664 (match_operand:DI 2 "reg_or_0_operand" "rO")
3665 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3666 UNSPEC_INSN_MULA_HS_LU))]
3667 ""
3668 "mula_hs_lu\t%0, %r2, %r3"
3669 [(set_attr "type" "X0_2cycle")])
3671 (define_insn "insn_mula_hu_hu"
3672 [(set (match_operand:DI 0 "register_operand" "=r")
3673 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3674 (match_operand:DI 2 "reg_or_0_operand" "rO")
3675 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3676 UNSPEC_INSN_MULA_HU_HU))]
3677 ""
3678 "mula_hu_hu\t%0, %r2, %r3"
3679 [(set_attr "type" "Y0_2cycle")])
3681 (define_insn "insn_mula_hu_ls"
3682 [(set (match_operand:DI 0 "register_operand" "=r")
3683 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3684 (match_operand:DI 2 "reg_or_0_operand" "rO")
3685 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3686 UNSPEC_INSN_MULA_HU_LS))]
3687 ""
3688 "mula_hu_ls\t%0, %r2, %r3"
3689 [(set_attr "type" "X0_2cycle")])
3691 (define_insn "insn_mula_hu_lu"
3692 [(set (match_operand:DI 0 "register_operand" "=r")
3693 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3694 (match_operand:DI 2 "reg_or_0_operand" "rO")
3695 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3696 UNSPEC_INSN_MULA_HU_LU))]
3697 ""
3698 "mula_hu_lu\t%0, %r2, %r3"
3699 [(set_attr "type" "X0_2cycle")])
3701 (define_insn "insn_mula_ls_ls"
3702 [(set (match_operand:DI 0 "register_operand" "=r")
3703 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3704 (match_operand:DI 2 "reg_or_0_operand" "rO")
3705 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3706 UNSPEC_INSN_MULA_LS_LS))]
3707 ""
3708 "mula_ls_ls\t%0, %r2, %r3"
3709 [(set_attr "type" "Y0_2cycle")])
3711 (define_insn "insn_mula_ls_lu"
3712 [(set (match_operand:DI 0 "register_operand" "=r")
3713 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3714 (match_operand:DI 2 "reg_or_0_operand" "rO")
3715 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3716 UNSPEC_INSN_MULA_LS_LU))]
3717 ""
3718 "mula_ls_lu\t%0, %r2, %r3"
3719 [(set_attr "type" "X0_2cycle")])
3721 (define_insn "insn_mula_lu_lu"
3722 [(set (match_operand:DI 0 "register_operand" "=r")
3723 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3724 (match_operand:DI 2 "reg_or_0_operand" "rO")
3725 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3726 UNSPEC_INSN_MULA_LU_LU))]
3727 ""
3728 "mula_lu_lu\t%0, %r2, %r3"
3729 [(set_attr "type" "Y0_2cycle")])
3731 (define_insn "insn_mulax"
3732 [(set (match_operand:SI 0 "register_operand" "=r")
3733 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3734 (match_operand:SI 2 "reg_or_0_operand" "rO")
3735 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3736 UNSPEC_INSN_MULAX))]
3737 ""
3738 "mulax\t%0, %r2, %r3"
3739 [(set_attr "type" "Y0_2cycle")])
3741 (define_insn "insn_nap"
3742 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_NAP)]
3743 ""
3744 "nap"
3745 [(set_attr "type" "cannot_bundle")])
3747 (define_insn "insn_nor_<mode>"
3748 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3749 (and:I48MODE
3750 (not:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO"))
3751 (not:I48MODE (match_operand:I48MODE 2 "reg_or_0_operand" "rO"))))]
3752 ""
3753 "nor\t%0, %r1, %r2")
3755 (define_expand "insn_prefetch_l1"
3756 [(prefetch (match_operand 0 "pointer_operand" "")
3757 (const_int 0)
3758 (const_int 3))]
3759 "")
3761 (define_expand "insn_prefetch_l2"
3762 [(prefetch (match_operand 0 "pointer_operand" "")
3763 (const_int 0)
3764 (const_int 2))]
3765 "")
3767 (define_expand "insn_prefetch_l3"
3768 [(prefetch (match_operand 0 "pointer_operand" "")
3769 (const_int 0)
3770 (const_int 1))]
3771 "")
3773 (define_insn "insn_prefetch_l1_fault"
3774 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3775 UNSPEC_INSN_PREFETCH_L1_FAULT)]
3776 ""
3777 "prefetch_l1_fault\t%r0"
3778 [(set_attr "type" "Y2")])
3780 (define_insn "insn_prefetch_l2_fault"
3781 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3782 UNSPEC_INSN_PREFETCH_L2_FAULT)]
3783 ""
3784 "prefetch_l2_fault\t%r0"
3785 [(set_attr "type" "Y2")])
3787 (define_insn "insn_prefetch_l3_fault"
3788 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3789 UNSPEC_INSN_PREFETCH_L3_FAULT)]
3790 ""
3791 "prefetch_l3_fault\t%r0"
3792 [(set_attr "type" "Y2")])
3794 (define_insn "insn_revbits"
3795 [(set (match_operand:DI 0 "register_operand" "=r")
3796 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")]
3797 UNSPEC_INSN_REVBITS))]
3798 ""
3799 "revbits\t%0, %r1"
3800 [(set_attr "type" "Y0")])
3802 (define_insn "insn_shl1add"
3803 [(set (match_operand:DI 0 "register_operand" "=r")
3804 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3805 (const_int 2))
3806 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3807 ""
3808 "shl1add\t%0, %r1, %r2")
3810 (define_insn "insn_shl1addx"
3811 [(set (match_operand:SI 0 "register_operand" "=r")
3812 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3813 (const_int 2))
3814 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3815 ""
3816 "shl1addx\t%0, %r1, %r2")
3818 (define_insn "insn_shl2add"
3819 [(set (match_operand:DI 0 "register_operand" "=r")
3820 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3821 (const_int 4))
3822 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3823 ""
3824 "shl2add\t%0, %r1, %r2")
3826 (define_insn "insn_shl2addx"
3827 [(set (match_operand:SI 0 "register_operand" "=r")
3828 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3829 (const_int 4))
3830 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3831 ""
3832 "shl2addx\t%0, %r1, %r2")
3834 (define_insn "insn_shl3add"
3835 [(set (match_operand:DI 0 "register_operand" "=r")
3836 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3837 (const_int 8))
3838 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3839 ""
3840 "shl3add\t%0, %r1, %r2")
3842 (define_insn "insn_shl3addx"
3843 [(set (match_operand:SI 0 "register_operand" "=r")
3844 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3845 (const_int 8))
3846 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3847 ""
3848 "shl3addx\t%0, %r1, %r2")
3850 (define_insn "insn_shufflebytes"
3851 [(set (match_operand:DI 0 "register_operand" "=r")
3852 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3853 (match_operand:DI 2 "reg_or_0_operand" "rO")
3854 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3855 UNSPEC_INSN_SHUFFLEBYTES))]
3856 ""
3857 "shufflebytes\t%0, %r2, %r3"
3858 [(set_attr "type" "X0")])
3860 ;; stores
3862 (define_expand "insn_st"
3863 [(set (mem:DI (match_operand 0 "pointer_operand" ""))
3864 (match_operand:DI 1 "reg_or_0_operand" ""))]
3865 "")
3867 (define_insn "insn_st_add<bitsuffix>"
3868 [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3869 (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3870 (match_operand 2 "s8bit_cint_operand" "i")))
3871 (set (mem:DI (match_dup 3))
3872 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3873 ""
3874 "st_add\t%0, %r1, %2"
3875 [(set_attr "type" "X1")])
3877 (define_expand "insn_st<n>"
3878 [(set (mem:I124MODE (match_operand 0 "pointer_operand" ""))
3879 (match_operand:DI 1 "reg_or_0_operand" ""))]
3880 ""
3881 {
3882 operands[1] = simplify_gen_subreg (<MODE>mode, operands[1], DImode, 0);
3883 })
3885 (define_expand "insn_st<I124MODE:n>_add<I48MODE:bitsuffix>"
3886 [(parallel
3887 [(set (match_operand:I48MODE 0 "pointer_operand" "")
3888 (plus:I48MODE (match_operand 3 "pointer_operand" "")
3889 (match_operand 2 "s8bit_cint_operand" "")))
3890 (set (mem:I124MODE (match_dup 3))
3891 (match_operand:DI 1 "reg_or_0_operand" ""))])]
3892 ""
3893 {
3894 operands[1] = simplify_gen_subreg (<I124MODE:MODE>mode, operands[1],
3895 DImode, 0);
3896 })
3898 (define_insn "*insn_st<I124MODE:n>_add<I48MODE:bitsuffix>"
3899 [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3900 (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3901 (match_operand 2 "s8bit_cint_operand" "i")))
3902 (set (mem:I124MODE (match_dup 3))
3903 (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
3904 ""
3905 "st<I124MODE:n>_add\t%0, %r1, %2"
3906 [(set_attr "type" "X1")])
3908 ;; non-temporal stores
3910 (define_insn "insn_stnt"
3911 [(set (mem:DI (unspec [(match_operand 0 "pointer_operand" "rO")]
3912 UNSPEC_NON_TEMPORAL))
3913 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3914 ""
3915 "stnt\t%0, %r1"
3916 [(set_attr "type" "X1")])
3918 (define_insn "insn_stnt_add<bitsuffix>"
3919 [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3920 (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3921 (match_operand 2 "s8bit_cint_operand" "i")))
3922 (set (mem:DI (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
3923 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3924 ""
3925 "stnt_add\t%0, %r1, %2"
3926 [(set_attr "type" "X1")])
3928 (define_expand "insn_stnt<n>"
3929 [(set (mem:I124MODE (unspec [(match_operand 0 "pointer_operand" "")]
3930 UNSPEC_NON_TEMPORAL))
3931 (match_operand:DI 1 "reg_or_0_operand" ""))]
3932 ""
3933 {
3934 operands[1] = simplify_gen_subreg (<MODE>mode, operands[1], DImode, 0);
3935 })
3937 (define_insn "*insn_stnt<n>"
3938 [(set (mem:I124MODE (unspec [(match_operand 0 "pointer_operand" "rO")]
3939 UNSPEC_NON_TEMPORAL))
3940 (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
3941 ""
3942 "stnt<n>\t%0, %r1"
3943 [(set_attr "type" "X1")])
3945 (define_expand "insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>"
3946 [(parallel
3947 [(set (match_operand:I48MODE 0 "pointer_operand" "")
3948 (plus:I48MODE (match_operand 3 "pointer_operand" "")
3949 (match_operand 2 "s8bit_cint_operand" "")))
3950 (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
3951 (match_operand:DI 1 "reg_or_0_operand" "rO"))])]
3952 ""
3953 {
3954 operands[1] = simplify_gen_subreg (<I124MODE:MODE>mode, operands[1],
3955 DImode, 0);
3956 })
3958 (define_insn "*insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>"
3959 [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3960 (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3961 (match_operand 2 "s8bit_cint_operand" "i")))
3962 (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
3963 (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
3964 ""
3965 "stnt<I124MODE:n>_add\t%0, %r1, %2"
3966 [(set_attr "type" "X1")])
3968 ;; end stores
3970 (define_insn "insn_tblidxb0"
3971 [(set (match_operand:DI 0 "register_operand" "=r")
3972 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3973 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3974 UNSPEC_INSN_TBLIDXB0))]
3975 ""
3976 "tblidxb0\t%0, %r2"
3977 [(set_attr "type" "Y0")])
3979 (define_insn "insn_tblidxb1"
3980 [(set (match_operand:DI 0 "register_operand" "=r")
3981 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3982 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3983 UNSPEC_INSN_TBLIDXB1))]
3984 ""
3985 "tblidxb1\t%0, %r2"
3986 [(set_attr "type" "Y0")])
3988 (define_insn "insn_tblidxb2"
3989 [(set (match_operand:DI 0 "register_operand" "=r")
3990 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3991 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3992 UNSPEC_INSN_TBLIDXB2))]
3993 ""
3994 "tblidxb2\t%0, %r2"
3995 [(set_attr "type" "Y0")])
3997 (define_insn "insn_tblidxb3"
3998 [(set (match_operand:DI 0 "register_operand" "=r")
3999 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4000 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4001 UNSPEC_INSN_TBLIDXB3))]
4002 ""
4003 "tblidxb3\t%0, %r2"
4004 [(set_attr "type" "Y0")])
4006 ;; insn_v1add
4007 ;; insn_v1addi
4008 ;; insn_v1cmpeq
4009 ;; insn_v1cmpeqi
4010 ;; insn_v1cmplts
4011 ;; insn_v1cmpltsi
4012 ;; insn_v1cmpltu
4013 ;; insn_v1cmpltui
4014 ;; insn_v1maxu
4015 ;; insn_v1maxui
4016 ;; insn_v1minu
4017 ;; insn_v1minui
4018 (define_insn "<optab>v8qi3"
4019 [(set (match_operand:V8QI 0 "register_operand" "=r,r")
4020 (v1op_immed:V8QI
4021 (match_operand:V8QI 1 "reg_or_0_operand" "<comm>rO,rO")
4022 (match_operand:V8QI 2 "reg_or_v8s8bit_operand" "W,rO")))]
4023 ""
4024 "@
4025 v1<insn>i\t%0, %r1, %j2
4026 v1<insn>\t%0, %r1, %r2"
4027 [(set_attr "type" "<pipe>,<pipe>")])
4029 (define_expand "insn_v1<insn>"
4030 [(set (match_operand:DI 0 "register_operand" "")
4031 (v1op_immed:V8QI
4032 (match_operand:DI 1 "reg_or_0_operand" "")
4033 (match_operand:DI 2 "reg_or_0_operand" "")))]
4034 ""
4035 {
4036 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4037 V8QImode, operands[1], operands[2], true);
4038 DONE;
4039 })
4041 (define_expand "insn_v1<insn>i"
4042 [(set (match_operand:DI 0 "register_operand" "")
4043 (v1op_immed:V8QI
4044 (match_operand:DI 1 "reg_or_0_operand" "")
4045 (match_operand:DI 2 "s8bit_cint_operand" "")))]
4046 ""
4047 {
4048 /* Tile out immediate and expand to general case. */
4049 rtx n = tilegx_simd_int (operands[2], QImode);
4050 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4051 V8QImode, operands[1], n, true);
4052 DONE;
4053 })
4055 ;; insn_v1shl
4056 ;; insn_v1shli
4057 ;; insn_v1shrs
4058 ;; insn_v1shrsi
4059 ;; insn_v1shru
4060 ;; insn_v1shrui
4061 (define_insn "<optab>v8qi3"
4062 [(set (match_operand:V8QI 0 "register_operand" "=r,r")
4063 (any_shift:V8QI
4064 (match_operand:V8QI 1 "reg_or_0_operand" "rO,rO")
4065 (match_operand:DI 2 "reg_or_u5bit_operand" "I,rO")))]
4066 ""
4067 "@
4068 v1<insn>i\t%0, %r1, %2
4069 v1<insn>\t%0, %r1, %r2"
4070 [(set_attr "type" "<pipe>,<pipe>")])
4072 (define_expand "insn_v1<insn>"
4073 [(set (match_operand:DI 0 "register_operand" "")
4074 (any_shift:V8QI
4075 (match_operand:DI 1 "reg_or_0_operand" "")
4076 (match_operand:DI 2 "reg_or_u5bit_operand" "")))]
4077 ""
4078 {
4079 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4080 V8QImode, operands[1], operands[2], false);
4081 DONE;
4082 })
4084 ;; insn_v2add
4085 ;; insn_v2addi
4086 ;; insn_v2maxs
4087 ;; insn_v2maxsi
4088 ;; insn_v2mins
4089 ;; insn_v2minsi
4090 ;; insn_v2cmpeq
4091 ;; insn_v2cmpeqi
4092 ;; insn_v2cmplts
4093 ;; insn_v2cmpltsi
4094 ;; insn_v2cmpltu
4095 ;; insn_v2cmpltui
4096 (define_insn "<optab>v4hi3"
4097 [(set (match_operand:V4HI 0 "register_operand" "=r,r")
4098 (v2op_immed:V4HI
4099 (match_operand:V4HI 1 "reg_or_0_operand" "<comm>rO,rO")
4100 (match_operand:V4HI 2 "reg_or_v4s8bit_operand" "Y,rO")))]
4101 ""
4102 "@
4103 v2<insn>i\t%0, %r1, %j2
4104 v2<insn>\t%0, %r1, %r2"
4105 [(set_attr "type" "<pipe>,<pipe>")])
4107 (define_expand "insn_v2<insn>"
4108 [(set (match_operand:DI 0 "register_operand" "")
4109 (v2op_immed:V4HI
4110 (match_operand:DI 1 "reg_or_0_operand" "")
4111 (match_operand:DI 2 "reg_or_0_operand" "")))]
4112 ""
4113 {
4114 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4115 V4HImode, operands[1], operands[2], true);
4116 DONE;
4117 })
4119 (define_expand "insn_v2<insn>i"
4120 [(set (match_operand:DI 0 "register_operand" "")
4121 (v2op_immed:V4HI
4122 (match_operand:DI 1 "reg_or_0_operand" "")
4123 (match_operand:DI 2 "s8bit_cint_operand" "")))]
4124 ""
4125 {
4126 /* Tile out immediate and expand to general case. */
4127 rtx n = tilegx_simd_int (operands[2], HImode);
4128 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4129 V4HImode, operands[1], n, true);
4130 DONE;
4131 })
4133 ;; insn_v2shl
4134 ;; insn_v2shli
4135 ;; insn_v2shrs
4136 ;; insn_v2shrsi
4137 ;; insn_v2shru
4138 ;; insn_v2shrui
4139 (define_insn "<optab>v4hi3"
4140 [(set (match_operand:V4HI 0 "register_operand" "=r,r")
4141 (any_shift:V4HI
4142 (match_operand:V4HI 1 "reg_or_0_operand" "rO,rO")
4143 (match_operand:DI 2 "reg_or_u5bit_operand" "I,rO")))]
4144 ""
4145 "@
4146 v2<insn>i\t%0, %r1, %2
4147 v2<insn>\t%0, %r1, %r2"
4148 [(set_attr "type" "<pipe>,<pipe>")])
4150 (define_expand "insn_v2<insn>"
4151 [(set (match_operand:DI 0 "register_operand" "")
4152 (any_shift:V4HI
4153 (match_operand:DI 1 "reg_or_0_operand" "")
4154 (match_operand:DI 2 "reg_or_u5bit_operand" "")))]
4155 ""
4156 {
4157 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4158 V4HImode, operands[1], operands[2], false);
4159 DONE;
4160 })
4162 ;; insn_v1adduc
4163 ;; insn_v1subuc
4164 ;; insn_v1sub
4165 ;; insn_v1cmpne
4166 ;; insn_v1cmples
4167 ;; insn_v1cmpleu
4168 ;; insn_v1multu
4169 (define_insn "<optab>v8qi3"
4170 [(set (match_operand:V8QI 0 "register_operand" "=r")
4171 (v1op:V8QI
4172 (match_operand:V8QI 1 "reg_or_0_operand" "<comm>rO")
4173 (match_operand:V8QI 2 "reg_or_0_operand" "rO")))]
4174 ""
4175 "v1<insn>\t%0, %r1, %r2"
4176 [(set_attr "type" "<pipe>")])
4178 (define_expand "insn_v1<insn>"
4179 [(set (match_operand:DI 0 "register_operand" "")
4180 (v1op:V8QI
4181 (match_operand:DI 1 "reg_or_0_operand" "")
4182 (match_operand:DI 2 "reg_or_0_operand" "")))]
4183 ""
4184 {
4185 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4186 V8QImode, operands[1], operands[2], true);
4187 DONE;
4188 })
4190 ;; insn_v2addsc
4191 ;; insn_v2subsc
4192 ;; insn_v2sub
4193 ;; insn_v2cmpne
4194 ;; insn_v2cmples
4195 ;; insn_v2cmpleu
4196 (define_insn "<optab>v4hi3"
4197 [(set (match_operand:V4HI 0 "register_operand" "=r")
4198 (v2op:V4HI
4199 (match_operand:V4HI 1 "reg_or_0_operand" "<comm>rO")
4200 (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4201 ""
4202 "v2<insn>\t%0, %r1, %r2"
4203 [(set_attr "type" "<pipe>")])
4205 (define_expand "insn_v2<insn>"
4206 [(set (match_operand:DI 0 "register_operand" "")
4207 (v2op:V4HI
4208 (match_operand:DI 1 "reg_or_0_operand" "")
4209 (match_operand:DI 2 "reg_or_0_operand" "")))]
4210 ""
4211 {
4212 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4213 V4HImode, operands[1], operands[2], true);
4214 DONE;
4215 })
4217 ;; insn_v2mults
4218 (define_insn "mulv4hi3"
4219 [(set (match_operand:V4HI 0 "register_operand" "=r")
4220 (mult:V4HI
4221 (match_operand:V4HI 1 "reg_or_0_operand" "%rO")
4222 (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4223 ""
4224 "v2mults\t%0, %r1, %r2"
4225 [(set_attr "type" "X0_2cycle")])
4227 (define_expand "insn_v2mults"
4228 [(set (match_operand:DI 0 "register_operand" "")
4229 (mult:V4HI
4230 (match_operand:DI 1 "reg_or_0_operand" "")
4231 (match_operand:DI 2 "reg_or_0_operand" "")))]
4232 ""
4233 {
4234 tilegx_expand_builtin_vector_binop (gen_mulv4hi3, V4HImode, operands[0],
4235 V4HImode, operands[1], operands[2], true);
4236 DONE;
4237 })
4239 ;; insn_v2shlsc
4240 (define_insn "<optab>v4hi3"
4241 [(set (match_operand:V4HI 0 "register_operand" "=r")
4242 (v2shift:V4HI
4243 (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4244 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
4245 ""
4246 "v2<insn>\t%0, %r1, %r2"
4247 [(set_attr "type" "<pipe>")])
4249 (define_expand "insn_v2<insn>"
4250 [(set (match_operand:DI 0 "register_operand" "")
4251 (v2shift:V4HI
4252 (match_operand:DI 1 "reg_or_0_operand" "")
4253 (match_operand:DI 2 "reg_or_0_operand" "")))]
4254 ""
4255 {
4256 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4257 V4HImode, operands[1], operands[2], false);
4258 DONE;
4259 })
4261 ;; insn_v4addsc
4262 ;; insn_v4subsc
4263 ;; insn_v4add
4264 ;; insn_v4sub
4265 (define_insn "<optab>v2si3"
4266 [(set (match_operand:V2SI 0 "register_operand" "=r")
4267 (v4op:V2SI
4268 (match_operand:V2SI 1 "reg_or_0_operand" "<comm>rO")
4269 (match_operand:V2SI 2 "reg_or_0_operand" "rO")))]
4270 ""
4271 "v4<insn>\t%0, %r1, %r2"
4272 [(set_attr "type" "<pipe>")])
4274 (define_expand "insn_v4<insn>"
4275 [(set (match_operand:DI 0 "register_operand" "")
4276 (v4op:V2SI
4277 (match_operand:DI 1 "reg_or_0_operand" "")
4278 (match_operand:DI 2 "reg_or_0_operand" "")))]
4279 ""
4280 {
4281 tilegx_expand_builtin_vector_binop (gen_<optab>v2si3, V2SImode, operands[0],
4282 V2SImode, operands[1], operands[2], true);
4283 DONE;
4284 })
4286 ;; insn_v4shl
4287 ;; insn_v4shrs
4288 ;; insn_v4shru
4289 ;; insn_v4shlsc
4290 (define_insn "<optab>v2si3"
4291 [(set (match_operand:V2SI 0 "register_operand" "=r")
4292 (v4shift:V2SI
4293 (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4294 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
4295 ""
4296 "v4<insn>\t%0, %r1, %r2"
4297 [(set_attr "type" "<pipe>")])
4299 (define_expand "insn_v4<insn>"
4300 [(set (match_operand:DI 0 "register_operand" "")
4301 (v4shift:V2SI
4302 (match_operand:DI 1 "reg_or_0_operand" "")
4303 (match_operand:DI 2 "reg_or_0_operand" "")))]
4304 ""
4305 {
4306 tilegx_expand_builtin_vector_binop (gen_<optab>v2si3, V2SImode, operands[0],
4307 V2SImode, operands[1], operands[2], false);
4308 DONE;
4309 })
4311 ;; insn_v1int_h
4312 ;; {B7,B6,B5,B4,B3,B2,B1,B0} {A7,A6,A5,A4,A3,A2,A1,A0}
4313 ;; => {A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0}
4314 ;; => {A7,B7,A6,B6,A5,B5,A4,B4}
4315 (define_insn "vec_interleave_highv8qi"
4316 [(set (match_operand:V8QI 0 "register_operand" "=r")
4317 (vec_select:V8QI
4318 (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4319 (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4320 (parallel [(const_int 4) (const_int 12)
4321 (const_int 5) (const_int 13)
4322 (const_int 6) (const_int 14)
4323 (const_int 7) (const_int 15)])))]
4324 ""
4325 "v1int_h\t%0, %r2, %r1"
4326 [(set_attr "type" "X01")])
4328 (define_expand "insn_v1int_h"
4329 [(match_operand:DI 0 "register_operand" "")
4330 (match_operand:DI 1 "reg_or_0_operand" "")
4331 (match_operand:DI 2 "reg_or_0_operand" "")]
4332 ""
4333 {
4334 /* Our instruction interleaves opposite of the way vec_interleave
4335 works, so we need to reverse the source operands. */
4336 tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv8qi, V8QImode,
4337 operands[0], V8QImode, operands[2],
4338 operands[1], true);
4339 DONE;
4340 })
4342 ;; insn_v1int_l
4343 ;; {B7,B6,B5,B4,B3,B2,B1,B0} {A7,A6,A5,A4,A3,A2,A1,A0}
4344 ;; => {A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0}
4345 ;; => {A3,B3,A2,B2,A1,B1,A0,B0}
4346 (define_insn "vec_interleave_lowv8qi"
4347 [(set (match_operand:V8QI 0 "register_operand" "=r")
4348 (vec_select:V8QI
4349 (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4350 (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4351 (parallel [(const_int 0) (const_int 8)
4352 (const_int 1) (const_int 9)
4353 (const_int 2) (const_int 10)
4354 (const_int 3) (const_int 11)])))]
4355 ""
4356 "v1int_l\t%0, %r2, %r1"
4357 [(set_attr "type" "X01")])
4359 (define_expand "insn_v1int_l"
4360 [(match_operand:DI 0 "register_operand" "")
4361 (match_operand:DI 1 "reg_or_0_operand" "")
4362 (match_operand:DI 2 "reg_or_0_operand" "")]
4363 ""
4364 {
4365 /* Our instruction interleaves opposite of the way vec_interleave
4366 works, so we need to reverse the source operands. */
4367 tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv8qi, V8QImode,
4368 operands[0], V8QImode, operands[2],
4369 operands[1], true);
4370 DONE;
4371 })
4373 ;; insn_v2int_h
4374 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
4375 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4376 ;; => {A3,B3,A2,B2}
4377 (define_insn "vec_interleave_highv4hi"
4378 [(set (match_operand:V4HI 0 "register_operand" "=r")
4379 (vec_select:V4HI
4380 (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4381 (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4382 (parallel [(const_int 2) (const_int 6)
4383 (const_int 3) (const_int 7)])))]
4384 ""
4385 "v2int_h\t%0, %r2, %r1"
4386 [(set_attr "type" "X01")])
4388 (define_expand "insn_v2int_h"
4389 [(match_operand:DI 0 "register_operand" "")
4390 (match_operand:DI 1 "reg_or_0_operand" "")
4391 (match_operand:DI 2 "reg_or_0_operand" "")]
4392 ""
4393 {
4394 /* Our instruction interleaves opposite of the way vec_interleave
4395 works, so we need to reverse the source operands. */
4396 tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv4hi, V4HImode,
4397 operands[0], V4HImode, operands[2],
4398 operands[1], true);
4399 DONE;
4400 })
4402 ;; insn_v2int_l
4403 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
4404 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4405 ;; => {A1,B1,A0,B0}
4406 (define_insn "vec_interleave_lowv4hi"
4407 [(set (match_operand:V4HI 0 "register_operand" "=r")
4408 (vec_select:V4HI
4409 (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4410 (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4411 (parallel [(const_int 0) (const_int 4)
4412 (const_int 1) (const_int 5)])))]
4413 ""
4414 "v2int_l\t%0, %r2, %r1"
4415 [(set_attr "type" "X01")])
4417 (define_expand "insn_v2int_l"
4418 [(match_operand:DI 0 "register_operand" "")
4419 (match_operand:DI 1 "reg_or_0_operand" "")
4420 (match_operand:DI 2 "reg_or_0_operand" "")]
4421 ""
4422 {
4423 tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv4hi, V4HImode,
4424 operands[0], V4HImode, operands[2],
4425 operands[1], true);
4426 DONE;
4427 })
4429 ;; insn_v4int_h
4430 ;; {B1,B0} {A1,A0}
4431 ;; => {A1,A0,B1,B0}
4432 ;; => {A1,B1}
4433 (define_insn "vec_interleave_highv2si"
4434 [(set (match_operand:V2SI 0 "register_operand" "=r")
4435 (vec_select:V2SI
4436 (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4437 (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4438 (parallel [(const_int 1) (const_int 3)])))]
4439 ""
4440 "v4int_h\t%0, %r2, %r1"
4441 [(set_attr "type" "X01")])
4443 (define_expand "insn_v4int_h"
4444 [(match_operand:DI 0 "register_operand" "")
4445 (match_operand:DI 1 "reg_or_0_operand" "")
4446 (match_operand:DI 2 "reg_or_0_operand" "")]
4447 ""
4448 {
4449 /* Our instruction interleaves opposite of the way vec_interleave
4450 works, so we need to reverse the source operands. */
4451 tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv2si, V2SImode,
4452 operands[0], V2SImode, operands[2],
4453 operands[1], true);
4454 DONE;
4455 })
4457 ;; insn_v4int_l
4458 ;; {B1,B0} {A1,A0}
4459 ;; => {A1,A0,B1,B0}
4460 ;; => {A0,B0}
4461 (define_insn "vec_interleave_lowv2si"
4462 [(set (match_operand:V2SI 0 "register_operand" "=r")
4463 (vec_select:V2SI
4464 (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4465 (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4466 (parallel [(const_int 0) (const_int 2)])))]
4467 ""
4468 "v4int_l\t%0, %r2, %r1"
4469 [(set_attr "type" "X01")])
4471 (define_expand "insn_v4int_l"
4472 [(match_operand:DI 0 "register_operand" "")
4473 (match_operand:DI 1 "reg_or_0_operand" "")
4474 (match_operand:DI 2 "reg_or_0_operand" "")]
4475 ""
4476 {
4477 /* Our instruction interleaves opposite of the way vec_interleave
4478 works, so we need to reverse the source operands. */
4479 tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv2si, V2SImode,
4480 operands[0], V2SImode, operands[2],
4481 operands[1], true);
4482 DONE;
4483 })
4485 ;; insn_v1mnz
4486 ;; insn_v1mz
4487 ;; insn_v2mnz
4488 ;; insn_v2mz
4489 (define_insn "insn_mnz_<mode>"
4490 [(set (match_operand:VEC48MODE 0 "register_operand" "=r")
4491 (if_then_else:VEC48MODE
4492 (ne:VEC48MODE
4493 (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
4494 (const_int 0))
4495 (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")
4496 (const_int 0)))]
4497 ""
4498 "v<n>mnz\t%0, %r1, %r2"
4499 [(set_attr "type" "X01")])
4501 (define_expand "insn_v<n>mnz"
4502 [(set (match_operand:DI 0 "register_operand" "")
4503 (if_then_else:VEC48MODE
4504 (ne:VEC48MODE
4505 (match_operand:DI 1 "reg_or_0_operand" "")
4506 (const_int 0))
4507 (match_operand:DI 2 "reg_or_0_operand" "")
4508 (const_int 0)))]
4509 ""
4510 {
4511 tilegx_expand_builtin_vector_binop (gen_insn_mnz_<mode>, <MODE>mode,
4512 operands[0], <MODE>mode, operands[1],
4513 operands[2], true);
4514 DONE;
4515 })
4517 (define_insn "insn_mz_<mode>"
4518 [(set (match_operand:VEC48MODE 0 "register_operand" "=r")
4519 (if_then_else:VEC48MODE
4520 (ne:VEC48MODE
4521 (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
4522 (const_int 0))
4523 (const_int 0)
4524 (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")))]
4525 ""
4526 "v<n>mz\t%0, %r1, %r2"
4527 [(set_attr "type" "X01")])
4528 (define_expand "insn_v<n>mz"
4529 [(set (match_operand:DI 0 "register_operand" "")
4530 (if_then_else:VEC48MODE
4531 (ne:VEC48MODE
4532 (match_operand:DI 1 "reg_or_0_operand" "")
4533 (const_int 0))
4534 (const_int 0)
4535 (match_operand:DI 2 "reg_or_0_operand" "")))]
4536 ""
4537 {
4538 tilegx_expand_builtin_vector_binop (gen_insn_mz_<mode>, <MODE>mode,
4539 operands[0], <MODE>mode, operands[1],
4540 operands[2], true);
4541 DONE;
4542 })
4544 ;; insn_v1mulu
4545 (define_insn "vec_widen_umult_lo_v8qi"
4546 [(set (match_operand:V4HI 0 "register_operand" "=r")
4547 (mult:V4HI
4548 (zero_extend:V4HI
4549 (vec_select:V4QI
4550 (match_operand:V8QI 1 "register_operand" "r")
4551 (parallel [(const_int 0) (const_int 1)
4552 (const_int 2) (const_int 3)])))
4553 (zero_extend:V4HI
4554 (vec_select:V4QI
4555 (match_operand:V8QI 2 "register_operand" "r")
4556 (parallel [(const_int 0) (const_int 1)
4557 (const_int 2) (const_int 3)])))))]
4558 ""
4559 "v1mulu\t%0, %r1, %r2"
4560 [(set_attr "type" "X0_2cycle")])
4562 (define_expand "insn_v1mulu"
4563 [(match_operand:DI 0 "register_operand" "")
4564 (match_operand:DI 1 "reg_or_0_operand" "")
4565 (match_operand:DI 2 "reg_or_0_operand" "")]
4566 ""
4567 {
4568 tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
4569 operands[0], V8QImode, operands[1],
4570 operands[2], true);
4571 DONE;
4572 })
4574 ;; insn_v1mulus
4575 (define_insn "vec_widen_usmult_lo_v8qi"
4576 [(set (match_operand:V4HI 0 "register_operand" "=r")
4577 (mult:V4HI
4578 (zero_extend:V4HI
4579 (vec_select:V4QI
4580 (match_operand:V8QI 1 "register_operand" "r")
4581 (parallel [(const_int 0) (const_int 1)
4582 (const_int 2) (const_int 3)])))
4583 (sign_extend:V4HI
4584 (vec_select:V4QI
4585 (match_operand:V8QI 2 "register_operand" "r")
4586 (parallel [(const_int 0) (const_int 1)
4587 (const_int 2) (const_int 3)])))))]
4588 ""
4589 "v1mulus\t%0, %r1, %r2"
4590 [(set_attr "type" "X0_2cycle")])
4592 (define_expand "insn_v1mulus"
4593 [(match_operand:DI 0 "register_operand" "")
4594 (match_operand:DI 1 "reg_or_0_operand" "")
4595 (match_operand:DI 2 "reg_or_0_operand" "")]
4596 ""
4597 {
4598 tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
4599 operands[0], V8QImode, operands[1],
4600 operands[2], true);
4601 DONE;
4602 })
4604 ;; insn_v2muls
4605 (define_insn "vec_widen_smult_lo_v4qi"
4606 [(set (match_operand:V2SI 0 "register_operand" "=r")
4607 (mult:V2SI
4608 (sign_extend:V2SI
4609 (vec_select:V2HI
4610 (match_operand:V4HI 1 "register_operand" "r")
4611 (parallel [(const_int 0) (const_int 1)])))
4612 (sign_extend:V2SI
4613 (vec_select:V2HI
4614 (match_operand:V4HI 2 "register_operand" "r")
4615 (parallel [(const_int 0) (const_int 1)])))))]
4616 ""
4617 "v2muls\t%0, %r1, %r2"
4618 [(set_attr "type" "X0_2cycle")])
4620 (define_expand "insn_v2muls"
4621 [(match_operand:DI 0 "register_operand" "")
4622 (match_operand:DI 1 "reg_or_0_operand" "")
4623 (match_operand:DI 2 "reg_or_0_operand" "")]
4624 ""
4625 {
4626 tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,
4627 operands[0], V4HImode, operands[1],
4628 operands[2], true);
4629 DONE;
4630 })
4632 ;; v2packl
4633 ;; v2packuc
4634 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
4635 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4636 (define_insn "vec_pack_<pack_optab>_v4hi"
4637 [(set (match_operand:V8QI 0 "reg_or_0_operand" "=r")
4638 (vec_concat:V8QI
4639 (v2pack:V4QI (match_operand:V4HI 1 "reg_or_0_operand" "rO"))
4640 (v2pack:V4QI (match_operand:V4HI 2 "reg_or_0_operand" "rO"))))]
4641 ""
4642 "v2<pack_insn>\t%0, %r2, %r1"
4643 [(set_attr "type" "X01")])
4645 (define_expand "insn_v2<pack_insn>"
4646 [(set (match_operand:DI 0 "reg_or_0_operand" "")
4647 (vec_concat:V8QI
4648 (v2pack:V4QI (match_operand:DI 2 "reg_or_0_operand" ""))
4649 (v2pack:V4QI (match_operand:DI 1 "reg_or_0_operand" ""))))]
4650 ""
4651 {
4652 /* Our instruction concats opposite of the way vec_pack works, so we
4653 need to reverse the source operands. */
4654 tilegx_expand_builtin_vector_binop (gen_vec_pack_<pack_optab>_v4hi,
4655 V8QImode, operands[0], V4HImode,
4656 operands[2], operands[1], true);
4657 DONE;
4658 })
4660 ;; v2packh
4661 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
4662 ;; => {A3_hi,A2_hi,A1_hi,A0_hi,B3_hi,B2_hi,B1_hi,B0_hi}
4663 (define_insn "vec_pack_hipart_v4hi"
4664 [(set (match_operand:V8QI 0 "reg_or_0_operand" "=r")
4665 (vec_concat:V8QI
4666 (truncate:V4QI
4667 (ashiftrt:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4668 (const_int 8)))
4669 (truncate:V4QI
4670 (ashiftrt:V4HI (match_operand:V4HI 2 "reg_or_0_operand" "rO")
4671 (const_int 8)))))]
4672 ""
4673 "v2packh\t%0, %r2, %r1"
4674 [(set_attr "type" "X01")])
4676 (define_expand "insn_v2packh"
4677 [(set (match_operand:DI 0 "reg_or_0_operand" "")
4678 (vec_concat:V8QI
4679 (truncate:V4QI
4680 (ashiftrt:V4HI (match_operand:DI 2 "reg_or_0_operand" "")
4681 (const_int 8)))
4682 (truncate:V4QI
4683 (ashiftrt:V4HI (match_operand:DI 1 "reg_or_0_operand" "")
4684 (const_int 8)))))]
4685 ""
4686 {
4687 /* Our instruction concats opposite of the way vec_pack works, so we
4688 need to reverse the source operands. */
4689 tilegx_expand_builtin_vector_binop (gen_vec_pack_hipart_v4hi, V8QImode,
4690 operands[0], V4HImode, operands[2],
4691 operands[1], true);
4692 DONE;
4693 })
4695 ;; v4packsc
4696 ;; {B1,B0} {A1,A0}
4697 ;; => {A1,A0,B1,B0}
4698 (define_insn "vec_pack_ssat_v2si"
4699 [(set (match_operand:V4HI 0 "reg_or_0_operand" "=r")
4700 (vec_concat:V4HI
4701 (us_truncate:V2HI (match_operand:V2SI 1 "reg_or_0_operand" "rO"))
4702 (us_truncate:V2HI (match_operand:V2SI 2 "reg_or_0_operand" "rO"))))]
4703 ""
4704 "v4packsc\t%0, %r2, %r1"
4705 [(set_attr "type" "X01")])
4707 (define_expand "insn_v4packsc"
4708 [(set (match_operand:DI 0 "reg_or_0_operand" "")
4709 (vec_concat:V4HI
4710 (us_truncate:V2HI (match_operand:DI 2 "reg_or_0_operand" ""))
4711 (us_truncate:V2HI (match_operand:DI 1 "reg_or_0_operand" ""))))]
4712 ""
4713 {
4714 /* Our instruction concats opposite of the way vec_pack works, so we
4715 need to reverse the source operands. */
4716 tilegx_expand_builtin_vector_binop (gen_vec_pack_ssat_v2si, V4HImode,
4717 operands[0], V2SImode, operands[2],
4718 operands[1], true);
4719 DONE;
4720 })
4722 ;; Rest of the vector intrinsics
4723 (define_insn "insn_v1adiffu"
4724 [(set (match_operand:DI 0 "register_operand" "=r")
4725 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4726 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4727 UNSPEC_INSN_V1ADIFFU))]
4728 ""
4729 "v1adiffu\t%0, %r1, %r2"
4730 [(set_attr "type" "X0_2cycle")])
4732 (define_insn "insn_v1avgu"
4733 [(set (match_operand:DI 0 "register_operand" "=r")
4734 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4735 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4736 UNSPEC_INSN_V1AVGU))]
4737 ""
4738 "v1avgu\t%0, %r1, %r2"
4739 [(set_attr "type" "X0")])
4741 (define_insn "insn_v1ddotpu"
4742 [(set (match_operand:DI 0 "register_operand" "=r")
4743 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4744 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4745 UNSPEC_INSN_V1DDOTPU))]
4746 ""
4747 "v1ddotpu\t%0, %r1, %r2"
4748 [(set_attr "type" "X0_2cycle")])
4750 (define_insn "insn_v1ddotpua"
4751 [(set (match_operand:DI 0 "register_operand" "=r")
4752 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4753 (match_operand:DI 2 "reg_or_0_operand" "rO")
4754 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4755 UNSPEC_INSN_V1DDOTPUA))]
4756 ""
4757 "v1ddotpua\t%0, %r2, %r3"
4758 [(set_attr "type" "X0_2cycle")])
4760 (define_insn "insn_v1ddotpus"
4761 [(set (match_operand:DI 0 "register_operand" "=r")
4762 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4763 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4764 UNSPEC_INSN_V1DDOTPUS))]
4765 ""
4766 "v1ddotpus\t%0, %r1, %r2"
4767 [(set_attr "type" "X0_2cycle")])
4769 (define_insn "insn_v1ddotpusa"
4770 [(set (match_operand:DI 0 "register_operand" "=r")
4771 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4772 (match_operand:DI 2 "reg_or_0_operand" "rO")
4773 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4774 UNSPEC_INSN_V1DDOTPUSA))]
4775 ""
4776 "v1ddotpusa\t%0, %r2, %r3"
4777 [(set_attr "type" "X0_2cycle")])
4779 (define_insn "insn_v1dotp"
4780 [(set (match_operand:DI 0 "register_operand" "=r")
4781 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4782 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4783 UNSPEC_INSN_V1DOTP))]
4784 ""
4785 "v1dotp\t%0, %r1, %r2"
4786 [(set_attr "type" "X0_2cycle")])
4788 (define_insn "insn_v1dotpa"
4789 [(set (match_operand:DI 0 "register_operand" "=r")
4790 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4791 (match_operand:DI 2 "reg_or_0_operand" "rO")
4792 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4793 UNSPEC_INSN_V1DOTPA))]
4794 ""
4795 "v1dotpa\t%0, %r2, %r3"
4796 [(set_attr "type" "X0_2cycle")])
4798 (define_insn "insn_v1dotpu"
4799 [(set (match_operand:DI 0 "register_operand" "=r")
4800 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4801 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4802 UNSPEC_INSN_V1DOTPU))]
4803 ""
4804 "v1dotpu\t%0, %r1, %r2"
4805 [(set_attr "type" "X0_2cycle")])
4807 (define_insn "insn_v1dotpua"
4808 [(set (match_operand:DI 0 "register_operand" "=r")
4809 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4810 (match_operand:DI 2 "reg_or_0_operand" "rO")
4811 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4812 UNSPEC_INSN_V1DOTPUA))]
4813 ""
4814 "v1dotpua\t%0, %r2, %r3"
4815 [(set_attr "type" "X0_2cycle")])
4817 (define_insn "insn_v1dotpus"
4818 [(set (match_operand:DI 0 "register_operand" "=r")
4819 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4820 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4821 UNSPEC_INSN_V1DOTPUS))]
4822 ""
4823 "v1dotpus\t%0, %r1, %r2"
4824 [(set_attr "type" "X0_2cycle")])
4826 (define_insn "insn_v1dotpusa"
4827 [(set (match_operand:DI 0 "register_operand" "=r")
4828 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4829 (match_operand:DI 2 "reg_or_0_operand" "rO")
4830 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4831 UNSPEC_INSN_V1DOTPUSA))]
4832 ""
4833 "v1dotpusa\t%0, %r2, %r3"
4834 [(set_attr "type" "X0_2cycle")])
4836 (define_insn "insn_v1sadau"
4837 [(set (match_operand:DI 0 "register_operand" "=r")
4838 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4839 (match_operand:DI 2 "reg_or_0_operand" "rO")
4840 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4841 UNSPEC_INSN_V1SADAU))]
4842 ""
4843 "v1sadau\t%0, %r2, %r3"
4844 [(set_attr "type" "X0_2cycle")])
4846 (define_insn "insn_v1sadu"
4847 [(set (match_operand:DI 0 "register_operand" "=r")
4848 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4849 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4850 UNSPEC_INSN_V1SADU))]
4851 ""
4852 "v1sadu\t%0, %r1, %r2"
4853 [(set_attr "type" "X0_2cycle")])
4855 (define_insn "*insn_v1sadu"
4856 [(set (match_operand:SI 0 "register_operand" "=r")
4857 (truncate:SI
4858 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4859 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4860 UNSPEC_INSN_V1SADU)))]
4861 ""
4862 "v1sadu\t%0, %r1, %r2"
4863 [(set_attr "type" "X0_2cycle")])
4865 (define_insn "insn_v2adiffs"
4866 [(set (match_operand:DI 0 "register_operand" "=r")
4867 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4868 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4869 UNSPEC_INSN_V2ADIFFS))]
4870 ""
4871 "v2adiffs\t%0, %r1, %r2"
4872 [(set_attr "type" "X0_2cycle")])
4874 (define_insn "insn_v2avgs"
4875 [(set (match_operand:DI 0 "register_operand" "=r")
4876 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4877 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4878 UNSPEC_INSN_V2AVGS))]
4879 ""
4880 "v2avgs\t%0, %r1, %r2"
4881 [(set_attr "type" "X0")])
4883 (define_insn "insn_v2dotp"
4884 [(set (match_operand:DI 0 "register_operand" "=r")
4885 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4886 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4887 UNSPEC_INSN_V2DOTP))]
4888 ""
4889 "v2dotp\t%0, %r1, %r2"
4890 [(set_attr "type" "X0_2cycle")])
4892 (define_insn "insn_v2dotpa"
4893 [(set (match_operand:DI 0 "register_operand" "=r")
4894 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4895 (match_operand:DI 2 "reg_or_0_operand" "rO")
4896 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4897 UNSPEC_INSN_V2DOTPA))]
4898 ""
4899 "v2dotpa\t%0, %r2, %r3"
4900 [(set_attr "type" "X0_2cycle")])
4902 (define_insn "insn_v2mulfsc"
4903 [(set (match_operand:DI 0 "register_operand" "=r")
4904 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4905 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4906 UNSPEC_INSN_V2MULFSC))]
4907 ""
4908 "v2mulfsc\t%0, %r1, %r2"
4909 [(set_attr "type" "X0_2cycle")])
4911 (define_insn "insn_v2sadas"
4912 [(set (match_operand:DI 0 "register_operand" "=r")
4913 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4914 (match_operand:DI 2 "reg_or_0_operand" "rO")
4915 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4916 UNSPEC_INSN_V2SADAS))]
4917 ""
4918 "v2sadas\t%0, %r2, %r3"
4919 [(set_attr "type" "X0_2cycle")])
4921 (define_insn "insn_v2sadau"
4922 [(set (match_operand:DI 0 "register_operand" "=r")
4923 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4924 (match_operand:DI 2 "reg_or_0_operand" "rO")
4925 (match_operand:DI 3 "reg_or_0_operand" "rO")]
4926 UNSPEC_INSN_V2SADAU))]
4927 ""
4928 "v2sadau\t%0, %r2, %r3"
4929 [(set_attr "type" "X0_2cycle")])
4931 (define_insn "insn_v2sads"
4932 [(set (match_operand:DI 0 "register_operand" "=r")
4933 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4934 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4935 UNSPEC_INSN_V2SADS))]
4936 ""
4937 "v2sads\t%0, %r1, %r2"
4938 [(set_attr "type" "X0_2cycle")])
4940 (define_insn "*insn_v2sads"
4941 [(set (match_operand:SI 0 "register_operand" "=r")
4942 (truncate:SI
4943 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4944 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4945 UNSPEC_INSN_V2SADS)))]
4946 ""
4947 "v2sads\t%0, %r1, %r2"
4948 [(set_attr "type" "X0_2cycle")])
4950 (define_insn "insn_v2sadu"
4951 [(set (match_operand:DI 0 "register_operand" "=r")
4952 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4953 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4954 UNSPEC_INSN_V2SADU))]
4955 ""
4956 "v2sadu\t%0, %r1, %r2"
4957 [(set_attr "type" "X0_2cycle")])
4959 (define_insn "*insn_v2sadu"
4960 [(set (match_operand:SI 0 "register_operand" "=r")
4961 (truncate:SI
4962 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4963 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4964 UNSPEC_INSN_V2SADU)))]
4965 ""
4966 "v2sadu\t%0, %r1, %r2"
4967 [(set_attr "type" "X0_2cycle")])
4969 (define_insn "insn_wh64"
4970 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
4971 UNSPEC_INSN_WH64)
4972 (clobber (mem:BLK (const_int 0)))]
4973 ""
4974 "wh64\t%r0"
4975 [(set_attr "type" "X1")])
4977 \f
4978 ;; Network intrinsics
4980 ;; Note the "pseudo" text is handled specially by the
4981 ;; asm_output_opcode routine. If the output is an empty string, the
4982 ;; instruction would bypass the asm_output_opcode routine, bypassing
4983 ;; the bundle handling code.
4984 (define_insn "tilegx_network_barrier"
4985 [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]
4986 ""
4987 "pseudo"
4988 [(set_attr "type" "nothing")
4989 (set_attr "length" "0")])
4991 (define_insn "*netreg_receive"
4992 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,U,m")
4993 (unspec_volatile:DI [(match_operand:DI 1 "netreg_operand" "i,i,i")
4994 (reg:DI TILEGX_NETORDER_REG)]
4995 UNSPEC_NETWORK_RECEIVE))
4996 (clobber (reg:DI TILEGX_NETORDER_REG))]
4998 ""
4999 "@
5000 move\t%0, %N1
5001 st\t%0, %N1
5002 st_add\t%I0, %N1, %i0"
5003 [(set_attr "type" "*,Y2,X1")])
5005 (define_insn "*netreg_send"
5006 [(unspec_volatile:DI
5007 [(match_operand:DI 0 "netreg_operand" "i,i,i,i,i,i")
5008 (match_operand:DI 1 "reg_or_cint_operand" "r,I,J,K,N,P")
5009 (reg:DI TILEGX_NETORDER_REG)]
5010 UNSPEC_NETWORK_SEND)
5011 (clobber (reg:DI TILEGX_NETORDER_REG))]
5012 ""
5013 "@
5014 move\t%N0, %r1
5015 movei\t%N0, %1
5016 moveli\t%N0, %1
5017 shl16insli\t%N0, zero, %h1
5018 v1addi\t%N0, zero, %j1
5019 v2addi\t%N0, zero, %h1"
5020 [(set_attr "type" "*,*,X01,X01,X01,X01")])
5022 (define_expand "tilegx_idn0_receive"
5023 [(parallel
5024 [(set (match_operand:DI 0 "register_operand" "")
5025 (unspec_volatile:DI [(const_int TILEGX_NETREG_IDN0)
5026 (reg:DI TILEGX_NETORDER_REG)]
5027 UNSPEC_NETWORK_RECEIVE))
5028 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5029 "")
5031 (define_expand "tilegx_idn1_receive"
5032 [(parallel
5033 [(set (match_operand:DI 0 "register_operand" "")
5034 (unspec_volatile:DI [(const_int TILEGX_NETREG_IDN1)
5035 (reg:DI TILEGX_NETORDER_REG)]
5036 UNSPEC_NETWORK_RECEIVE))
5037 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5038 "")
5040 (define_expand "tilegx_idn_send"
5041 [(parallel
5042 [(unspec_volatile:DI [(const_int TILEGX_NETREG_IDN0)
5043 (match_operand:DI 0 "reg_or_cint_operand" "")
5044 (reg:DI TILEGX_NETORDER_REG)]
5045 UNSPEC_NETWORK_SEND)
5046 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5047 "")
5049 (define_expand "tilegx_udn0_receive"
5050 [(parallel
5051 [(set (match_operand:DI 0 "register_operand" "")
5052 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN0)
5053 (reg:DI TILEGX_NETORDER_REG)]
5054 UNSPEC_NETWORK_RECEIVE))
5055 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5056 "")
5058 (define_expand "tilegx_udn1_receive"
5059 [(parallel
5060 [(set (match_operand:DI 0 "register_operand" "")
5061 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN1)
5062 (reg:DI TILEGX_NETORDER_REG)]
5063 UNSPEC_NETWORK_RECEIVE))
5064 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5065 "")
5067 (define_expand "tilegx_udn2_receive"
5068 [(parallel
5069 [(set (match_operand:DI 0 "register_operand" "")
5070 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN2)
5071 (reg:DI TILEGX_NETORDER_REG)]
5072 UNSPEC_NETWORK_RECEIVE))
5073 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5074 "")
5076 (define_expand "tilegx_udn3_receive"
5077 [(parallel
5078 [(set (match_operand:DI 0 "register_operand" "")
5079 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN3)
5080 (reg:DI TILEGX_NETORDER_REG)]
5081 UNSPEC_NETWORK_RECEIVE))
5082 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5083 "")
5085 (define_expand "tilegx_udn_send"
5086 [(parallel
5087 [(unspec_volatile:DI [(const_int TILEGX_NETREG_UDN0)
5088 (match_operand:DI 0 "reg_or_cint_operand" "")
5089 (reg:DI TILEGX_NETORDER_REG)]
5090 UNSPEC_NETWORK_SEND)
5091 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5092 "")
5094 (define_insn "*netreg_adddi_to_network"
5095 [(unspec_volatile:DI
5096 [(match_operand:DI 0 "netreg_operand" "i,i,i")
5097 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO")
5098 (match_operand:DI 2 "add_operand" "r,I,JT"))
5099 (reg:DI TILEGX_NETORDER_REG)]
5100 UNSPEC_NETWORK_SEND)
5101 (clobber (reg:DI TILEGX_NETORDER_REG))]
5102 ""
5103 "@
5104 add\t%N0, %r1, %2
5105 addi\t%N0, %r1, %2
5106 addli\t%N0, %r1, %H2"
5107 [(set_attr "type" "*,*,X01")])
5109 (define_insn "*netreg_adddi_from_network"
5110 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5111 (plus:DI (unspec_volatile:DI
5112 [(match_operand:DI 1 "netreg_operand" "%i,i,i")
5113 (reg:DI TILEGX_NETORDER_REG)]
5114 UNSPEC_NETWORK_RECEIVE)
5115 (match_operand:DI 2 "add_operand" "rO,I,JT")))
5116 (clobber (reg:DI TILEGX_NETORDER_REG))]
5117 ""
5118 "@
5119 add\t%0, %N1, %r2
5120 addi\t%0, %N1, %2
5121 addli\t%0, %N1, %H2"
5122 [(set_attr "type" "*,*,X01")])
5124 \f
5125 ;;
5126 ;; Stack protector instructions.
5127 ;;
5129 (define_expand "stack_protect_set"
5130 [(set (match_operand 0 "nonautoincmem_operand" "")
5131 (match_operand 1 "nonautoincmem_operand" ""))]
5132 ""
5133 {
5134 #ifdef TARGET_THREAD_SSP_OFFSET
5135 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
5136 rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
5137 rtx ssp = gen_reg_rtx (Pmode);
5139 emit_insn (gen_rtx_SET (VOIDmode, ssp, ssp_addr));
5141 operands[1] = gen_rtx_MEM (Pmode, ssp);
5142 #endif
5144 if (TARGET_32BIT)
5145 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
5146 else
5147 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
5149 DONE;
5150 })
5152 (define_insn "stack_protect_setsi"
5153 [(set (match_operand:SI 0 "nonautoincmem_operand" "=U")
5154 (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")]
5155 UNSPEC_SP_SET))
5156 (set (match_scratch:SI 2 "=&r") (const_int 0))]
5157 ""
5158 "ld4s\t%2, %1; { st4\t%0, %2; move\t%2, zero }"
5159 [(set_attr "length" "16")
5160 (set_attr "type" "cannot_bundle_3cycle")])
5162 (define_insn "stack_protect_setdi"
5163 [(set (match_operand:DI 0 "nonautoincmem_operand" "=U")
5164 (unspec:DI [(match_operand:DI 1 "nonautoincmem_operand" "U")]
5165 UNSPEC_SP_SET))
5166 (set (match_scratch:DI 2 "=&r") (const_int 0))]
5167 ""
5168 "ld\t%2, %1; { st\t%0, %2; move\t%2, zero }"
5169 [(set_attr "length" "16")
5170 (set_attr "type" "cannot_bundle_3cycle")])
5172 (define_expand "stack_protect_test"
5173 [(match_operand 0 "nonautoincmem_operand" "")
5174 (match_operand 1 "nonautoincmem_operand" "")
5175 (match_operand 2 "" "")]
5176 ""
5177 {
5178 rtx compare_result;
5179 rtx bcomp, loc_ref;
5181 #ifdef TARGET_THREAD_SSP_OFFSET
5182 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
5183 rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
5184 rtx ssp = gen_reg_rtx (Pmode);
5186 emit_insn (gen_rtx_SET (VOIDmode, ssp, ssp_addr));
5188 operands[1] = gen_rtx_MEM (Pmode, ssp);
5189 #endif
5191 compare_result = gen_reg_rtx (Pmode);
5193 if (TARGET_32BIT)
5194 emit_insn (gen_stack_protect_testsi (compare_result, operands[0],
5195 operands[1]));
5196 else
5197 emit_insn (gen_stack_protect_testdi (compare_result, operands[0],
5198 operands[1]));
5200 bcomp = gen_rtx_NE (SImode, compare_result, const0_rtx);
5202 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[2]);
5204 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
5205 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
5206 loc_ref, pc_rtx)));
5208 DONE;
5209 })
5211 (define_insn "stack_protect_testsi"
5212 [(set (match_operand:SI 0 "register_operand" "=&r")
5213 (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")
5214 (match_operand:SI 2 "nonautoincmem_operand" "U")]
5215 UNSPEC_SP_TEST))
5216 (set (match_scratch:SI 3 "=&r") (const_int 0))]
5217 ""
5218 "ld4s\t%0, %1; ld4s\t%3, %2; { cmpeq\t%0, %0, %3; move\t%3, zero }"
5219 [(set_attr "length" "24")
5220 (set_attr "type" "cannot_bundle_4cycle")])
5222 (define_insn "stack_protect_testdi"
5223 [(set (match_operand:DI 0 "register_operand" "=&r")
5224 (unspec:DI [(match_operand:DI 1 "nonautoincmem_operand" "U")
5225 (match_operand:DI 2 "nonautoincmem_operand" "U")]
5226 UNSPEC_SP_TEST))
5227 (set (match_scratch:DI 3 "=&r") (const_int 0))]
5228 ""
5229 "ld\t%0, %1; ld\t%3, %2; { cmpeq\t%0, %0, %3; move\t%3, zero }"
5230 [(set_attr "length" "24")
5231 (set_attr "type" "cannot_bundle_4cycle")])
5233 (include "sync.md")