1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001-2013 Free Software Foundation, Inc.
3 Contributed by Picochip Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "langhooks.h"
53 #include "picochip-protos.h"
55 #include "insn-attr.h" /* For DFA state_t. */
56 #include "insn-config.h" /* Required by recog.h */
57 #include "insn-codes.h" /* For CODE_FOR_? */
58 #include "optabs.h" /* For GEN_FCN */
59 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
60 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
61 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
62 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
65 /* Target AE ISA information. */
66 enum picochip_dfa_type picochip_schedule_type
;
68 bool picochip_has_mul_unit
= false;
69 bool picochip_has_mac_unit
= false;
71 /* targetm hook function prototypes. */
73 void picochip_asm_file_start (void);
74 void picochip_asm_file_end (void);
76 void picochip_init_libfuncs (void);
77 void picochip_reorg (void);
79 int picochip_arg_partial_bytes (cumulative_args_t p_cum
,
80 enum machine_mode mode
,
81 tree type
, bool named
);
82 rtx
picochip_function_arg (cumulative_args_t p_cum
,
83 enum machine_mode mode
,
84 const_tree type
, bool named
);
85 rtx
picochip_incoming_function_arg (cumulative_args_t p_cum
,
86 enum machine_mode mode
,
87 const_tree type
, bool named
);
88 void picochip_arg_advance (cumulative_args_t p_cum
, enum machine_mode mode
,
89 const_tree type
, bool named
);
90 unsigned int picochip_function_arg_boundary (enum machine_mode mode
,
93 int picochip_sched_lookahead (void);
94 int picochip_sched_issue_rate (void);
95 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
96 rtx dep_insn
, int cost
);
97 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
98 int *n_readyp
, int clock
);
100 void picochip_init_builtins (void);
101 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
103 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int opno
,
104 int* total
, bool speed
);
105 bool picochip_return_in_memory(const_tree type
,
106 const_tree fntype ATTRIBUTE_UNUSED
);
107 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
108 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
109 enum machine_mode mode
);
110 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
111 int opnum
, int type
, int ind_levels
);
113 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
114 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
115 bool outgoing ATTRIBUTE_UNUSED
);
117 picochip_secondary_reload (bool in_p
,
118 rtx x ATTRIBUTE_UNUSED
,
119 reg_class_t cla ATTRIBUTE_UNUSED
,
120 enum machine_mode mode
,
121 secondary_reload_info
*sri
);
123 picochip_asm_named_section (const char *name
,
124 unsigned int flags ATTRIBUTE_UNUSED
,
125 tree decl ATTRIBUTE_UNUSED
);
127 static rtx
picochip_static_chain (const_tree
, bool);
129 static void picochip_option_override (void);
131 /* Lookup table mapping a register number to the earliest containing
132 class. Used by REGNO_REG_CLASS. */
133 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
135 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
136 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
137 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
138 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
139 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
142 /* picoChip register names. */
143 const char *picochip_regnames
[] = REGISTER_NAMES
;
145 /* Define the maximum number of registers which may be used to pass
146 * parameters to functions. */
147 #define MAX_CALL_PARAMETER_REGS 6
150 /* Target scheduling information. */
152 /* This flag indicates whether the next instruction to be output is a
153 VLIW continuation instruction. It is used to communicate between
154 final_prescan_insn and asm_output_opcode. */
155 static int picochip_vliw_continuation
= 0;
157 /* This variable is used to communicate the current instruction
158 between final_prescan_insn and functions such as asm_output_opcode,
159 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
160 current instruction. */
161 static rtx picochip_current_prescan_insn
;
163 static bool picochip_is_delay_slot_pending
= 0;
165 /* When final_prescan_insn is called, it computes information about
166 the current VLIW packet, and stores it in this structure. When
167 instructions are output, this state is used to make sure that the
168 instructions are output in the correct way (e.g., which ALU to use,
169 whether a macro branch was ever previously a real branch, etc.). */
172 int contains_pico_alu_insn
;
173 int contains_non_cc_alu_insn
;
174 int num_alu_insns_so_far
;
176 /* Record how many instructions are contained in the packet. */
177 int num_insns_in_packet
;
179 /* There was a case for this to be more than 1 */
180 int num_cfi_labels_deferred
;
181 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
182 emitted inside a VLIW packet. */
183 char lm_label_name
[256]; /* Used to record the name of an LM label. */
186 struct vliw_state picochip_current_vliw_state
;
188 /* Save/restore recog_data. */
189 static int picochip_saved_which_alternative
;
190 static struct recog_data picochip_saved_recog_data
;
192 /* Determine which ALU to use for the instruction in
193 picochip_current_prescan_insn. */
194 static char picochip_get_vliw_alu_id (void);
196 /* Initialize the GCC target structure. */
198 #undef TARGET_ASM_FUNCTION_PROLOGUE
199 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
201 #undef TARGET_ASM_FUNCTION_EPILOGUE
202 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
204 #undef TARGET_ASM_INTERNAL_LABEL
205 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
207 #undef TARGET_ASM_GLOBALIZE_LABEL
208 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
210 #undef TARGET_ASM_BYTE_OP
211 #define TARGET_ASM_BYTE_OP ".initByte "
212 #undef TARGET_ASM_ALIGNED_HI_OP
213 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
216 #undef TARGET_ASM_ALIGNED_SI_OP
217 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
218 #undef TARGET_ASM_UNALIGNED_SI_OP
219 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
221 #undef TARGET_INIT_BUILTINS
222 #define TARGET_INIT_BUILTINS picochip_init_builtins
224 #undef TARGET_EXPAND_BUILTIN
225 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
227 #undef TARGET_RTX_COSTS
228 #define TARGET_RTX_COSTS picochip_rtx_costs
230 #undef TARGET_SCHED_ISSUE_RATE
231 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
233 #undef TARGET_SCHED_REORDER
234 #define TARGET_SCHED_REORDER picochip_sched_reorder
236 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
237 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
238 picochip_sched_lookahead
240 #undef TARGET_SCHED_ADJUST_COST
241 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
243 #undef TARGET_ASM_NAMED_SECTION
244 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
246 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
247 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
249 #undef TARGET_INIT_LIBFUNCS
250 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
252 #undef TARGET_ASM_FILE_START
253 #define TARGET_ASM_FILE_START picochip_asm_file_start
255 #undef TARGET_ASM_FILE_END
256 #define TARGET_ASM_FILE_END picochip_asm_file_end
258 #undef TARGET_MACHINE_DEPENDENT_REORG
259 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
261 #undef TARGET_ARG_PARTIAL_BYTES
262 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
264 #undef TARGET_FUNCTION_ARG
265 #define TARGET_FUNCTION_ARG picochip_function_arg
267 #undef TARGET_FUNCTION_INCOMING_ARG
268 #define TARGET_FUNCTION_INCOMING_ARG picochip_incoming_function_arg
270 #undef TARGET_FUNCTION_ARG_ADVANCE
271 #define TARGET_FUNCTION_ARG_ADVANCE picochip_arg_advance
273 #undef TARGET_FUNCTION_ARG_BOUNDARY
274 #define TARGET_FUNCTION_ARG_BOUNDARY picochip_function_arg_boundary
276 #undef TARGET_PROMOTE_FUNCTION_MODE
277 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
278 #undef TARGET_PROMOTE_PROTOTYPES
279 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
281 /* Target support for Anchored Addresses optimization */
282 #undef TARGET_MIN_ANCHOR_OFFSET
283 #define TARGET_MIN_ANCHOR_OFFSET 0
284 #undef TARGET_MAX_ANCHOR_OFFSET
285 #define TARGET_MAX_ANCHOR_OFFSET 7
286 #undef TARGET_ASM_OUTPUT_ANCHOR
287 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
289 #undef TARGET_FUNCTION_VALUE
290 #define TARGET_FUNCTION_VALUE picochip_function_value
292 #undef TARGET_LIBGCC_CMP_RETURN_MODE
293 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
296 #undef TARGET_LEGITIMATE_ADDRESS_P
297 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
299 #undef TARGET_LEGITIMIZE_ADDRESS
300 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
302 /* Loading and storing QImode values to and from memory
303 usually requires a scratch register. */
304 #undef TARGET_SECONDARY_RELOAD
305 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
307 /* How Large Values are Returned */
309 #undef TARGET_RETURN_IN_MEMORY
310 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
312 #undef TARGET_STATIC_CHAIN
313 #define TARGET_STATIC_CHAIN picochip_static_chain
315 #undef TARGET_OPTION_OVERRIDE
316 #define TARGET_OPTION_OVERRIDE picochip_option_override
318 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
319 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
321 /* The 2nd scheduling pass option is switched off, and a machine
322 dependent reorganisation ensures that it is run later on, after the
323 second jump optimisation. */
324 #undef TARGET_DELAY_SCHED2
325 #define TARGET_DELAY_SCHED2 true
327 /* Variable tracking should be run after all optimizations which
328 change order of insns. It also needs a valid CFG. */
329 #undef TARGET_DELAY_VARTRACK
330 #define TARGET_DELAY_VARTRACK true
332 struct gcc_target targetm
= TARGET_INITIALIZER
;
335 /* Only return a value in memory if it is greater than 4 bytes.
336 int_size_in_bytes returns -1 for variable size objects, which go in
337 memory always. The cast to unsigned makes -1 > 8. */
340 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
342 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
345 /* Allow some options to be overriden. */
348 picochip_option_override (void)
350 /* If we are optimizing for stack, dont let inliner to inline functions
351 that could potentially increase stack size.*/
352 if (flag_conserve_stack
)
354 maybe_set_param_value (PARAM_LARGE_STACK_FRAME
, 0,
355 global_options
.x_param_values
,
356 global_options_set
.x_param_values
);
357 maybe_set_param_value (PARAM_STACK_FRAME_GROWTH
, 0,
358 global_options
.x_param_values
,
359 global_options_set
.x_param_values
);
362 /* Turn off the elimination of unused types. The elaborator
363 generates various interesting types to represent constants,
364 generics, and so on, and it is useful to retain this information
365 in the debug output. The increased size of the debug information
366 is not really an issue for us. */
367 flag_eliminate_unused_debug_types
= 0;
369 /* Even if the user specifies a -fno-omit-frame-pointer on the
370 command line, we still want to go ahead and omit frame pointer
371 usages, since we dont really have a frame pointer register.
372 So, all accesses to FP need to be converted to accesses off
374 flag_omit_frame_pointer
= 1;
376 /* Turning on anchored addresses by default. This is an optimization
377 that could decrease the code size by placing anchors in data and
378 accessing offsets from the anchor for file local data variables.*/
380 flag_section_anchors
= 1;
382 /* The second scheduling pass runs within picochip_reorg, to avoid
383 having the second jump optimisation trash the instruction modes
384 (e.g., instructions are changed to TImode to mark the beginning
385 of cycles). Two types of DFA scheduling are possible: space and
386 speed. In both cases, instructions are reordered to avoid stalls
387 (e.g., memory loads stall for one cycle). Speed scheduling will
388 also enable VLIW instruction packing. VLIW instructions use more
389 code space, so VLIW scheduling is disabled when scheduling for
391 if (flag_schedule_insns_after_reload
)
394 picochip_schedule_type
= DFA_TYPE_SPACE
;
397 picochip_schedule_type
= DFA_TYPE_SPEED
;
398 flag_delayed_branch
= 0;
402 picochip_schedule_type
= DFA_TYPE_NONE
;
404 /* Ensure that the debug level is always at least -g2. The flow
405 analyser works at its best if it always has debug
406 information. DWARF is non-intrusive, so it makes no difference to
407 code quality if debug is always enabled. */
408 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
410 debug_info_level
= DINFO_LEVEL_NORMAL
;
411 write_symbols
= DWARF2_DEBUG
;
414 /* Options of the form -mae=mac, and so on will be substituted by
415 the compiler driver for the appropriate byte access and multiply
416 unit ISA options. Any unrecognised AE types will end up being
417 passed to the compiler, which should reject them as invalid. */
418 if (picochip_ae_type_string
!= NULL
)
419 error ("invalid AE type specified (%s)", picochip_ae_type_string
);
421 /* Override any specific capabilities of the instruction set. These
422 take precedence over any capabilities inferred from the AE type,
423 regardless of where the options appear on the command line. */
424 if (picochip_mul_type_string
== NULL
)
426 /* Default to MEM-type multiply, for historical compatibility. */
427 picochip_has_mac_unit
= false;
428 picochip_has_mul_unit
= true;
432 picochip_has_mac_unit
= false;
433 picochip_has_mul_unit
= false;
435 if (strcmp (picochip_mul_type_string
, "mul") == 0)
436 picochip_has_mul_unit
= true;
437 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
438 picochip_has_mac_unit
= true;
439 else if (strcmp (picochip_mul_type_string
, "none") == 0)
440 { /* Do nothing. Unit types already set to false. */ }
442 error ("invalid mul type specified (%s) - expected mac, mul or none",
443 picochip_mul_type_string
);
448 /* Initialise the library functions to handle arithmetic on some of
451 picochip_init_libfuncs (void)
454 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
455 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
456 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
458 /* 64-bit signed multiplication. */
459 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
461 /* Signed division */
462 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
463 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
466 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
467 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
469 /* 32-bit count leading Zeros*/
470 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
472 /* 64-bit comparison */
473 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
474 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
476 /* 64-bit addition and subtraction*/
477 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
478 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
481 /* Memcpy function */
483 picochip_expand_movmemhi (rtx
*operands
)
485 rtx src_addr_reg
, dst_addr_reg
, count_reg
, src_mem
, dst_mem
, tmp_reg
;
488 src_addr_reg
= gen_reg_rtx(HImode
);
489 dst_addr_reg
= gen_reg_rtx(HImode
);
490 count_reg
= gen_reg_rtx(HImode
);
491 emit_insn (gen_movhi (count_reg
, operands
[2]));
492 emit_insn (gen_movqi (src_addr_reg
, XEXP(operands
[1], 0)));
493 emit_insn (gen_movqi (dst_addr_reg
, XEXP(operands
[0], 0)));
494 gcc_assert (GET_CODE(count_reg
) == REG
);
495 start_label
= gen_label_rtx ();
496 emit_label (start_label
);
498 /* We can specialise the code for different alignments */
499 align
= INTVAL(operands
[3]);
500 size
= INTVAL(operands
[2]);
501 gcc_assert(align
>= 0 && size
>= 0);
504 if (size
% 4 == 0 && align
% 4 == 0)
506 src_mem
= gen_rtx_MEM(SImode
, src_addr_reg
);
507 dst_mem
= gen_rtx_MEM(SImode
, dst_addr_reg
);
508 tmp_reg
= gen_reg_rtx(SImode
);
509 emit_insn (gen_movsi (tmp_reg
, src_mem
));
510 emit_insn (gen_movsi (dst_mem
, tmp_reg
));
511 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, GEN_INT(4)));
512 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, GEN_INT(4)));
513 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-4)));
514 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
515 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
517 else if (size
% 2 == 0 && align
% 2 == 0)
519 src_mem
= gen_rtx_MEM(HImode
, src_addr_reg
);
520 dst_mem
= gen_rtx_MEM(HImode
, dst_addr_reg
);
521 tmp_reg
= gen_reg_rtx(HImode
);
522 emit_insn (gen_movhi (tmp_reg
, src_mem
));
523 emit_insn (gen_movhi (dst_mem
, tmp_reg
));
524 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const2_rtx
));
525 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const2_rtx
));
526 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-2)));
527 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
528 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
532 src_mem
= gen_rtx_MEM(QImode
, src_addr_reg
);
533 dst_mem
= gen_rtx_MEM(QImode
, dst_addr_reg
);
534 tmp_reg
= gen_reg_rtx(QImode
);
535 emit_insn (gen_movqi (tmp_reg
, src_mem
));
536 emit_insn (gen_movqi (dst_mem
, tmp_reg
));
537 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const1_rtx
));
538 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const1_rtx
));
539 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-1)));
540 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
541 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
548 /* Return the register class for letter C. */
550 picochip_reg_class_from_letter (unsigned c
)
568 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
570 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
573 picochip_order_regs_for_local_alloc (void)
575 /* We change the order for leaf functions alone. We put r12 at
576 the end since using it will prevent us to combine stw/ldws to
577 stl/ldl and it gives no benefit. In non-leaf functions, we
578 would anyway saveup/restore r12, so it makes sense to use it.*/
580 if (leaf_function_p())
582 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
583 FIRST_PSEUDO_REGISTER
* sizeof (int));
587 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
588 FIRST_PSEUDO_REGISTER
* sizeof (int));
592 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
594 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
599 case 'I': /* 4 bits signed. */
600 return value
+ 8 < 16;
601 case 'J': /* 4 bits unsigned. */
603 case 'K': /* 8 bits signed. */
604 return value
+ 128 < 256;
605 case 'M': /* 4-bit magnitude. */
606 return abs (value
) < 16;
607 case 'N': /* 10 bits signed. */
608 return value
+ 512 > 1024;
609 case 'O': /* 16 bits signed. */
610 return value
+ 32768 < 65536;
611 default: /* Unknown letter. */
616 /* Stack utility functions. */
618 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
621 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
627 /* Emit a set of parallel register expressions used to store
628 blockmode values to pass to functions. */
630 picochip_emit_register_parallel (int size_in_units
, int offset
)
634 rtx vector
[MAX_CALL_PARAMETER_REGS
];
638 /* Compute the base register, and number of required registers. */
639 base_reg
= offset
/ 2;
640 num_regs
= size_in_units
/ 2;
641 if (size_in_units
% 2 == 1)
644 /* Emit a register for each part of the block mode value to be
645 passed in a register. */
646 for (i
= 0; i
< num_regs
; i
++)
647 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
648 gen_rtx_REG (HImode
, base_reg
+ i
),
650 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
656 /* Emit an instruction to allocate a suitable amount of space on the
657 stack, by decrementing the stack pointer. */
659 picochip_emit_stack_allocate (int adjustment
)
662 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
664 /* Use an addition of a negative value. */
665 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
666 GEN_INT (-adjustment
)));
668 /* Make the instruction frame related. Also add an expression note,
669 so that the correct Dwarf information is generated (see documention
670 for RTX_FRAME_RELATED_P for more details). */
671 RTX_FRAME_RELATED_P (insn
) = 1;
672 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
673 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
674 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
675 GEN_INT (-adjustment
))));
679 /* Emit an instruction to save a register of the given mode. The
680 offset at which to save the register is given relative to the stack
683 picochip_emit_save_register (rtx reg
, int offset
)
685 rtx stack_pointer
, address
, mem
, insn
;
687 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
689 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
691 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
693 insn
= emit_move_insn (mem
, reg
);
694 RTX_FRAME_RELATED_P (insn
) = 1;
696 /* For modes other than HImode, create a note explaining that
697 multiple registers have been saved. This allows the correct DWARF
698 call frame information to be generated. */
699 switch (GET_MODE (reg
))
702 /* The RTL is sufficient to explain HImode register saves. */
706 /* SImode must be broken down into parallel HImode register saves. */
714 gen_rtx_PLUS (Pmode
, stack_pointer
,
716 gen_rtx_REG (HImode
, REGNO (reg
)));
717 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
720 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
725 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
726 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
728 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
729 gen_rtx_PARALLEL (VOIDmode
, p
));
736 ("unexpected mode %s encountered in picochip_emit_save_register",
737 GET_MODE_NAME (GET_MODE (reg
)));
742 /* Emit an instruction to restore a register of the given mode. The
743 offset from which to restore the register is given relative to the
746 picochip_emit_restore_register (rtx reg
, int offset
)
748 rtx stack_pointer
, address
, mem
;
750 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
752 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
754 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
756 emit_move_insn (reg
, mem
);
760 /* Check that the given byte offset is aligned to the given number of
763 picochip_is_aligned (int byte_offset
, int bit_alignment
)
765 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
766 return (byte_offset
% byte_alignment
) == 0;
769 /*****************************************************************************
772 * The following section contains code which controls how the stack is
775 * The stack is laid out as follows (high addresses first):
778 * Pretend arguments (ARG PTR)
782 * Outgoing arguments (SP)
784 * The (constant) offsets of the different areas must be calculated
785 * relative to the stack area immediately below, and aligned
786 * appropriately. For example, the frame offset is computed by
787 * determining the offset of the special register area, adding the
788 * size of the special register area, and then aligning the resulting
789 * offset correctly. In turn, the special register offset is computed
790 * from the general register offset, and so on. This enables the
791 * different offsets to change size and alignment, without requiring
792 * the code for other offset calculations to be rewritten.
794 * The argument pointer, and the frame pointer are eliminated wherever
795 * possible, by replacing them with a constant offset from the stack
796 * pointer. In the rare cases where constant offsets from the stack
797 * pointer cannot be computed, another register will be allocated to
798 * serve as the argument pointer, or the frame pointer.
800 * The save registers are stored at small offsets from the caller, to
801 * enable the more efficient SP-based ISA instructions to be used.
803 ****************************************************************************/
805 /* Compute the size of an argument in units. */
807 picochip_compute_arg_size (const_tree type
, enum machine_mode mode
)
809 int type_size_in_units
= 0;
812 type_size_in_units
= tree_low_cst (TYPE_SIZE_UNIT (type
), 1);
814 type_size_in_units
= GET_MODE_SIZE (mode
);
816 return type_size_in_units
;
820 /* Determine where the next outgoing arg should be placed. */
822 picochip_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
823 const_tree type
, bool named ATTRIBUTE_UNUSED
)
825 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
827 int type_align_in_units
= 0;
828 int type_size_in_units
;
830 int offset_overflow
= 0;
832 /* VOIDmode is passed when computing the second argument to a `call'
833 pattern. This can be ignored. */
834 if (mode
== VOIDmode
)
837 /* Compute the alignment and size of the parameter. */
838 type_align_in_units
=
839 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
840 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
842 /* Compute the correct offset (i.e., ensure that the offset meets
843 the alignment requirements). */
844 offset_overflow
= *cum
% type_align_in_units
;
845 if (offset_overflow
== 0)
848 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
852 printf ("Function arg:\n");
853 printf (" Type valid: %s\n", (type
? "yes" : "no"));
854 printf (" Cumulative Value: %d\n", *cum
);
855 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
856 printf (" Type size: %i units\n", type_size_in_units
);
857 printf (" Alignment: %i units\n", type_align_in_units
);
858 printf (" New offset: %i\n", new_offset
);
862 /* If the new offset is outside the register space, return. */
863 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
866 /* If the end of the argument is outside the register space, then
867 the argument must overlap the register space. Return the first
868 available register. */
869 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
870 return gen_rtx_REG (HImode
, new_offset
/ 2);
872 /* Create a register of the required mode to hold the parameter. */
873 reg
= new_offset
/ 2;
888 return gen_rtx_REG (mode
, reg
);
892 /* Empty blockmode values can be passed as arguments (e.g.,
893 * empty structs). These require no registers
894 * whatsoever. Non-empty blockmode values are passed in a set
895 * of parallel registers. */
896 if (type_size_in_units
== 0)
899 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
904 (0, "defaulting to stack for %s register creation",
905 GET_MODE_NAME (mode
));
913 /* Determine where the next incoming function argument will
914 appear. Normally, this works in exactly the same way as
915 picochip_function_arg, except when the function in question is a
916 varadic function. In this case, the incoming arguments all appear
917 to be passed on the stack (actually, some of the arguments are
918 passed in registers, which are then pushed onto the stack by the
919 function prologue). */
921 picochip_incoming_function_arg (cumulative_args_t cum
,
922 enum machine_mode mode
,
923 const_tree type
, bool named
)
929 return picochip_function_arg (cum
, mode
, type
, named
);
933 /* Gives the alignment boundary, in bits, of an argument with the
936 picochip_function_arg_boundary (enum machine_mode mode
,
937 const_tree type ATTRIBUTE_UNUSED
)
942 align
= STACK_BOUNDARY
;
944 align
= GET_MODE_ALIGNMENT (mode
);
946 if (align
< PARM_BOUNDARY
)
947 align
= PARM_BOUNDARY
;
953 /* Compute partial registers. */
955 picochip_arg_partial_bytes (cumulative_args_t p_cum
, enum machine_mode mode
,
956 tree type
, bool named ATTRIBUTE_UNUSED
)
958 int type_align_in_units
= 0;
959 int type_size_in_units
;
961 int offset_overflow
= 0;
963 unsigned cum
= *get_cumulative_args (p_cum
);
965 /* VOIDmode is passed when computing the second argument to a `call'
966 pattern. This can be ignored. */
967 if (mode
== VOIDmode
)
970 /* Compute the alignment and size of the parameter. */
971 type_align_in_units
=
972 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
973 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
975 /* Compute the correct offset (i.e., ensure that the offset meets
976 the alignment requirements). */
977 offset_overflow
= cum
% type_align_in_units
;
978 if (offset_overflow
== 0)
981 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
985 printf ("Partial function arg nregs:\n");
986 printf (" Type valid: %s\n", (type
? "yes" : "no"));
987 printf (" Cumulative Value: %d\n", cum
);
988 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
989 printf (" Type size: %i units\n", type_size_in_units
);
990 printf (" Alignment: %i units\n", type_align_in_units
);
991 printf (" New offset: %i\n", new_offset
);
995 /* If the new offset is outside the register space, return. */
996 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
999 /* If the end of the argument is outside the register space, then
1000 the argument must overlap the register space. Return the number
1001 of bytes which are passed in registers. */
1002 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
1003 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
1009 /* Advance the cumulative args counter CUM. */
1011 picochip_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1012 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1014 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1015 int type_align_in_units
= 0;
1016 int type_size_in_units
;
1018 int offset_overflow
= 0;
1020 /* VOIDmode is passed when computing the second argument to a `call'
1021 pattern. This can be ignored. */
1022 if (mode
== VOIDmode
)
1025 /* Compute the alignment and size of the parameter. */
1026 type_align_in_units
=
1027 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
1028 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
1030 /* Compute the correct offset (i.e., ensure that the offset meets
1031 the alignment requirements). */
1032 offset_overflow
= *cum
% type_align_in_units
;
1033 if (offset_overflow
== 0)
1036 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
1038 /* Advance past the last argument. */
1039 new_offset
+= type_size_in_units
;
1044 /* Determine whether a register needs saving/restoring. It does if it
1045 is live in a function, and isn't a call-used register. */
1047 picochip_reg_needs_saving (int reg_num
)
1049 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
1052 /* Compute and return offset of the main frame. */
1054 picochip_frame_byte_offset (void)
1056 gcc_assert(picochip_is_aligned
1057 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
1059 return crtl
->outgoing_args_size
;
1062 /* Return the size of the main frame. */
1064 picochip_frame_size_in_bytes (void)
1066 int frame_size
= get_frame_size();
1067 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
1068 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
1069 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
1070 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
1074 /* Compute and return the size (in bytes) of the register save/restore
1075 area for the current function. This only includes the general
1076 purpose registers - the special purpose stack pointer and link
1077 registers are not included in this area. */
1079 picochip_save_area_size_in_bytes (void)
1081 int num_regs_to_save
= 0;
1084 /* Read through all the registers, determining which need to be saved. */
1085 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1087 if (picochip_reg_needs_saving (i
))
1088 num_regs_to_save
+= 1;
1091 return num_regs_to_save
* UNITS_PER_WORD
;
1095 /* Compute and return offset of the save area base. */
1097 picochip_save_area_byte_offset (void)
1099 int base_offset
= (picochip_frame_byte_offset () +
1100 picochip_frame_size_in_bytes ());
1102 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1108 /* Compute and return offset of the special register save area. This
1109 area can be found immediately above the normal save area. It must
1110 be aligned, to allow the registers to be saved and restored as a
1113 picochip_special_save_area_byte_offset (void)
1115 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1116 int offset
= (picochip_save_area_byte_offset () +
1117 picochip_save_area_size_in_bytes ());
1119 if ((offset
% byte_alignment
) != 0)
1120 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1126 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1128 picochip_can_eliminate_link_sp_save (void)
1130 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1131 changing during optimizations phases. So, this function returns different
1132 values when called from initial_elimination_offset and then again when it
1133 is called from prologue/epilogue generation. This means that argument
1134 accesses become wrong. This wouldnt happen only if we were not using the
1135 stack at all. The following conditions ensures that.*/
1137 return (crtl
->is_leaf
&&
1138 !df_regs_ever_live_p(LINK_REGNUM
) &&
1139 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1140 (picochip_special_save_area_byte_offset() == 0) &&
1141 (crtl
->args
.size
== 0) &&
1142 (crtl
->args
.pretend_args_size
== 0));
1145 /* Compute the size of the special reg save area (SP and LNK). If the
1146 SP/LNK registers don't need to be saved, this area can shrink to
1149 picochip_special_save_area_size_in_bytes (void)
1153 if (picochip_can_eliminate_link_sp_save ())
1156 return 2 * UNITS_PER_WORD
;
1159 /* Return the number of pretend arguments. If this function is
1160 varadic, all the incoming arguments are effectively passed on the
1161 stack. If this function has real pretend arguments (caused by a
1162 value being passed partially on the stack and partially in
1163 registers), then return the number of registers used. */
1165 picochip_pretend_arg_area_size (void)
1168 if (crtl
->args
.pretend_args_size
!= 0)
1170 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1172 return crtl
->args
.pretend_args_size
;
1174 else if (cfun
->stdarg
)
1181 /* Compute and return the offset of the pretend arguments. The pretend
1182 arguments are contiguous with the incoming arguments, and must be
1183 correctly aligned. */
1185 picochip_pretend_arg_area_byte_offset (void)
1187 int base_offset
= 0;
1189 base_offset
= (picochip_special_save_area_byte_offset () +
1190 picochip_special_save_area_size_in_bytes ());
1192 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1193 gcc_assert(picochip_is_aligned
1194 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1200 /* Compute and return the offset of the incoming arguments. If a
1201 static chain is in use, this will be passed just before the other
1202 arguments. This means that the pretend argument mechanism, used in
1203 variadic functions, doesn't work properly. Thus, static chains work
1204 on their own, as do variadic functions, but not the combination of
1205 the two. This isn't really a problem. */
1207 picochip_arg_area_byte_offset (void)
1209 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1210 picochip_pretend_arg_area_size ());
1212 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1213 the alignment on a 32-bit boundary must be maintained. */
1214 if (cfun
->static_chain_decl
!= NULL
)
1216 gcc_assert (!cfun
->stdarg
);
1220 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1227 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1230 /* Special case - only one register needed. */
1231 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1234 /* We actually do not allocate acc0 ever. But, it seems like we need to
1235 make it look like a allocatable register for the dataflow checks to work
1236 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1241 /* General case - compute how much space in terms of units. */
1242 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1247 picochip_class_max_nregs (int reg_class
, int mode
)
1249 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1251 if (reg_class
== ACC_REGS
)
1254 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1261 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1262 argument pointer) by replacing it with a constant offset from the
1263 main stack register. */
1265 initial_elimination_offset (int from
, int to
)
1267 int offset_from_sp
= 0;
1269 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1270 offset_from_sp
= picochip_frame_byte_offset ();
1271 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1272 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1276 return offset_from_sp
;
1280 /* Compute and return the size of the incoming argument area. */
1282 picochip_arg_area_size_in_bytes (void)
1284 return crtl
->args
.size
;
1287 /* Determine whether the given register is valid. When the strict mode
1288 is used, only hard registers are valid, otherwise any register is
1291 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1294 /* Sanity check - non-registers shouldn't make it here, but... */
1295 if (REG
!= GET_CODE (x
))
1299 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1305 /* Determine whether the given constant is in the range required for
1306 the given base register. */
1308 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1310 HOST_WIDE_INT corrected_offset
;
1312 if (GET_MODE_SIZE (mode
) != 0)
1314 if (GET_MODE_SIZE(mode
) <= 4)
1316 /* We used to allow incorrect offsets if strict is 0. But, this would
1317 then rely on reload doing the right thing. We have had problems
1318 there before, and on > 4.3 compiler, there are no benefits. */
1319 if (offset
% GET_MODE_SIZE (mode
) != 0)
1321 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1325 if (offset
% 4 != 0)
1327 corrected_offset
= offset
/ 4;
1332 /* Default to the byte offset as supplied. */
1333 corrected_offset
= offset
;
1336 /* The offset from the base register can be different depending upon
1337 the base register. The stack/frame/argument pointer offsets can
1338 all be greater than a simple register-based offset. Note that the
1339 frame/argument pointer registers are actually eliminations of the
1340 stack pointer, so a value which is valid for an offset to, for
1341 example, the frame pointer, might be invalid for the stack
1342 pointer once the elimination has occurred. However, there is no
1343 need to handle this special case here, as the stack offset is
1344 always checked after elimination anyway, and the generated code
1345 seems to have identical performance. */
1346 if (regno
== STACK_POINTER_REGNUM
||
1347 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1348 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1350 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1354 /* Determine whether a given rtx is a legitimate address for machine_mode
1355 MODE. STRICT is non-zero if we're being strict - any pseudo that
1356 is not a hard register must be a memory reference. */
1358 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1362 switch (GET_CODE (x
))
1365 valid
= picochip_legitimate_address_register (x
, strict
);
1370 rtx base
= XEXP (x
, 0);
1371 rtx offset
= XEXP (x
, 1);
1372 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1378 valid
= (REG
== GET_CODE (base
) &&
1379 picochip_legitimate_address_register (base
, strict
) &&
1380 CONST_INT
== GET_CODE (offset
) &&
1381 picochip_const_ok_for_base (mode
, REGNO (base
),
1387 /* The user can select whether a symbol can be used as a memory
1388 address. Typically, this will decrease execution time (no
1389 register load is required first), but will increase code size
1390 (because the symbol will be used several times, rather than
1391 loaded once into a register.*/
1392 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1397 /* A constant memory address must be a (plus (symbol_ref)
1398 (const_int)), and is only allowed when the symbols are
1399 permitted addresses. */
1400 rtx inner
= XEXP (x
, 0);
1402 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1403 PLUS
== GET_CODE (inner
) &&
1404 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1405 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1419 /* For all memory operations, picochip allows a uconst4 offset value. It
1420 is hence beneficial to turn an
1421 addr = <reg + long_const>
1426 X = reg + long_const & FFF0
1427 diff = long_const - (long_const & FFF0)
1430 X can be reused in subsequent memory operations.
1433 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1434 enum machine_mode mode
)
1441 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1457 if (GET_CODE (x
) == PLUS
1458 && GET_CODE (XEXP (x
, 0)) == REG
1459 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1461 int high_val
, low_val
, offset
;
1462 offset
= INTVAL (XEXP (x
, 1));
1463 /* Ignore cases with negative offsets. */
1466 high_val
= offset
& mask_val
;
1467 low_val
= offset
- high_val
;
1470 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1471 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1478 /* For all memory operations, picochip allows a uconst4 offset value. It
1479 is hence beneficial to turn an
1480 addr = <reg + long_const>
1485 X = reg + long_const & FFF0
1486 diff = long_const - (long_const & FFF0)
1489 X can be reused in subsequent memory operations.
1492 picochip_legitimize_reload_address (rtx
*x
,
1493 enum machine_mode mode
,
1494 int opnum
, int type
,
1495 int ind_levels ATTRIBUTE_UNUSED
)
1499 if (picochip_symbol_offset(*x
))
1501 *x
= gen_rtx_CONST(mode
, *x
);
1507 /* We should recognise addresses that we created.*/
1508 if (GET_CODE (*x
) == PLUS
1509 && GET_CODE (XEXP (*x
, 0)) == PLUS
1510 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1511 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1512 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1514 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1515 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1516 opnum
, (enum reload_type
)type
);
1520 /* Depending on mode, the offsets allowed are either 16/32/64. */
1536 if (GET_CODE (*x
) == PLUS
1537 && GET_CODE (XEXP (*x
, 0)) == REG
1538 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1540 int high_val
, low_val
, offset
;
1541 offset
= INTVAL (XEXP (*x
, 1));
1542 /* Ignore cases with negative offsets. */
1545 high_val
= offset
& mask_val
;
1546 low_val
= offset
- high_val
;
1549 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1550 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1551 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1552 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1553 opnum
, (enum reload_type
)type
);
1561 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1563 picochip_symbol_offset (rtx operand
)
1566 return (PLUS
== GET_CODE (operand
) &&
1567 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1568 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1572 /* Assembly output. */
1574 /* The format here should match the format used in the output of
1575 symbol_ref's elsewhere in this file. */
1577 picochip_output_label (FILE * stream
, const char name
[])
1579 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1581 /* If VLIW scheduling is in use, any Call Frame Information labels
1582 generated inside a packet must have their output deferred until
1583 the end of the packet. */
1584 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1585 is_cfi_label
&& picochip_vliw_continuation
)
1587 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1589 internal_error ("LCFI labels have already been deferred");
1591 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1592 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1593 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1597 assemble_name (stream
, name
);
1599 if (strncmp (name
, "picoMark_", 9) == 0)
1600 fprintf (stream
, "=\n");
1602 fprintf (stream
, ":\n");
1608 /* The format here should match the format used in the output of
1609 symbol_ref's elsewhere in this file. */
1611 picochip_output_labelref (FILE * stream
, const char name
[])
1613 fprintf (stream
, "_%s", name
);
1617 picochip_weaken_label (FILE * stream
, const char name
[])
1619 fprintf (stream
, ".weak ");
1620 assemble_name (stream
, name
);
1621 fprintf (stream
, "\n");
1624 /* Return true if the given label (or label prefix) denotes a marker
1625 label which should be emitted in the form LABEL= */
1627 picochip_is_marker_prefix (const char *prefix
)
1629 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1630 && strcmp (prefix
, "LP") != 0);
1634 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1638 /* Emit different types of label, based upon their prefix. They
1639 are handled differently to allow the assembler to ensure that
1640 branch target labels are properly aligned, while other labels
1641 will only serve as code markers, not branch targets. Aligning
1642 labels unnecessarily can result in much code wastage. */
1643 if (picochip_is_marker_prefix (prefix
))
1645 /* Special label marker. If it appears in the middle of a VLIW
1646 packet, defer it until the end of the packet. There has
1647 never been a need to handle more than one lm label at a time. */
1648 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1649 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1651 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1652 internal_error ("LM label has already been deferred");
1654 sprintf (picochip_current_vliw_state
.lm_label_name
,
1655 "picoMark_%s%ld", prefix
, num
);
1657 else if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1658 (strcmp (prefix
, "LCFI")) == 0 && picochip_vliw_continuation
)
1660 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1662 internal_error ("LCFI labels have already been deferred.");
1664 sprintf(picochip_current_vliw_state
.cfi_label_name
[
1665 picochip_current_vliw_state
.num_cfi_labels_deferred
],
1666 "picoMark_%s%ld", prefix
, num
);
1667 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1672 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1679 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1685 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1687 /* Two types of internal label can be generated: branch target
1688 labels and code marker labels. Branch target labels must always
1689 be aligned (since code will execute at these
1690 points). Differentiate between the two by prepending markers with
1691 a unique prefix, which can later be used in output_label to
1692 figure out which label syntax to use. */
1693 if (picochip_is_marker_prefix (prefix
))
1694 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1696 sprintf (str
, "%s%ld", prefix
, num
);
1701 picochip_asm_output_anchor (rtx symbol
)
1703 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1704 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1708 picochip_output_aligned_common (FILE * stream
, const char *name
,
1709 unsigned size
, unsigned alignment
)
1712 fprintf (stream
, ".commonData ");
1713 assemble_name (stream
, name
);
1714 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1715 picochip_output_global (stream
, name
);
1720 picochip_output_aligned_local (FILE * stream
, const char *name
,
1721 unsigned size
, unsigned alignment
)
1724 fprintf (stream
, ".commonData ");
1725 assemble_name (stream
, name
);
1726 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1731 picochip_output_global (FILE * stream
, const char *name
)
1733 fprintf (stream
, ".global ");
1734 assemble_name (stream
, name
);
1735 fprintf (stream
, "\n");
1738 /* Output an assembly language string. Output as a sequence of decimal
1739 numbers, followed by the literal string to make it obvious what the
1740 numbers represent. */
1742 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1746 fprintf (file
, ".ascii ");
1748 for (i
= 0; i
< length
; ++i
)
1750 fprintf (file
, "16#%x# ", (char) (str
[i
]));
1753 fprintf (file
, " ; ");
1755 for (i
= 0; i
< length
; ++i
)
1762 fprintf (file
, "\\n");
1765 fprintf (file
, "\\t");
1768 fprintf (file
, "\\0");
1771 fprintf (file
, "%c", c
);
1776 fprintf (file
, "\n");
1780 /* Output the beginning of an ASM file. */
1782 picochip_asm_file_start (void)
1784 default_file_start ();
1786 fprintf (asm_out_file
, "// picoChip ASM file\n");
1787 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1789 fprintf (asm_out_file
, "// Has byte access: %s\n",
1790 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1792 if (TARGET_HAS_MUL_UNIT
)
1793 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1794 else if (TARGET_HAS_MAC_UNIT
)
1795 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1797 fprintf (asm_out_file
, "// Has multiply: No\n");
1800 /* Output the end of an ASM file. */
1802 picochip_asm_file_end (void)
1804 /* Include a segment end to make it easy for PERL scripts to grab
1805 segments. This is now done by assembler*/
1807 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1811 /* Output frame debug information to the given stream. */
1813 picochip_output_frame_debug (FILE * file
)
1818 fprintf (file
, "\t\t// Leaf function\n");
1820 fprintf (file
, "\t\t// Non-leaf function\n");
1822 if (picochip_can_eliminate_link_sp_save ())
1823 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1825 if (cfun
->static_chain_decl
!= NULL
)
1826 fprintf (file
, "\t\t// Static chain in use\n");
1828 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1829 picochip_arg_area_size_in_bytes ());
1830 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1831 picochip_arg_area_byte_offset ());
1832 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1833 picochip_pretend_arg_area_size ());
1834 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1835 picochip_pretend_arg_area_byte_offset ());
1836 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1837 picochip_special_save_area_size_in_bytes ());
1838 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1839 picochip_special_save_area_byte_offset ());
1841 /* Output which registers are saved. */
1842 fprintf (file
, "\t\t// Saved regs: ");
1843 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1845 if (picochip_reg_needs_saving (i
))
1846 fprintf (file
, "%s ", picochip_regnames
[i
]);
1848 fprintf (file
, "\t\t\n");
1850 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1851 picochip_save_area_size_in_bytes ());
1852 fprintf (file
, "\t\t// Save area offset: %d\n",
1853 picochip_save_area_byte_offset ());
1855 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1856 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1857 picochip_frame_byte_offset ());
1859 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1860 crtl
->outgoing_args_size
);
1864 /* Output picoChip function prologue. This contains human-readable
1865 information about the function. */
1867 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1869 /* Get the function's name, as described by its RTL. This may be
1870 different from the DECL_NAME name used in the source file. The
1871 real declaration name must be used, to ensure that the prologue
1872 emits the right information for the linker. */
1875 x
= DECL_RTL (current_function_decl
);
1876 gcc_assert (MEM_P (x
));
1878 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1879 fnname
= XSTR (x
, 0);
1881 /* Note that the name of the function is given in the &_%s
1882 form. This matches the name of the function as used in labels,
1883 and function calls, and enables processCallGraph to match
1884 function calls to the name of the function, as defined here. */
1885 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1886 fnname
, picochip_arg_area_byte_offset ());
1888 picochip_output_frame_debug (file
);
1889 fprintf (file
, "\n");
1893 /* Output picoChip function epilogue. */
1895 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1900 x
= DECL_RTL (current_function_decl
);
1901 gcc_assert (MEM_P (x
));
1903 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1904 fnname
= XSTR (x
, 0);
1905 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1909 /* Manipulate the asm output. Some machines only execute the code when
1910 there is actually a chance of needing it (e.g., FRV doesn't execute
1911 it if the scheduling pass wasn't used). We always execute it,
1912 simple to ensure that it is exercised more often, and bugs are more
1915 This function's prime reason for existence is to insert the VLIW
1916 separators where appropriate. The separators must be inserted
1917 before any comments which appear at the end of the file.
1921 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1925 /* Flag to specify when a VLIW continuation has been inserted onto
1926 the line. Continuations are either inserted before any comments,
1927 or before the end of the line is reached. The flag ensures that
1928 we don't insert continuations twice (i.e., at the comment and the
1930 int continuation_inserted
= 0;
1932 /* If the instruction uses multiple lines (i.e., a new line
1933 character appears in the opcode), then ensure that no attempt is
1934 made to pack it into a VLIW. */
1935 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1937 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s",
1941 /* If a delay slot is pending, output the directive to the assembler
1942 before the instruction. */
1943 if (picochip_is_delay_slot_pending
)
1945 picochip_is_delay_slot_pending
= 0;
1949 /* Keep going for entire opcode. All substitution performed ourselves. */
1954 /* Determine whether a VLIW continuation must be inserted before
1955 any comments, or the end of the opcode. A flag is set to show
1956 that we have inserted a continuation on this line, so that we
1957 don't try to insert another continuation when the end of the
1958 opcode is reached. The only other case for a continuation
1959 might have been a newline, but these aren't allowed in
1960 conjunction with VLIW continuations (see above code). */
1961 if (picochip_vliw_continuation
&&
1962 !continuation_inserted
&&
1963 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1966 continuation_inserted
= 1;
1969 /* Detect an explicit VLIW separator. */
1970 if (c
== '%' && (*ptr
== '|'))
1975 /* Detect the need for an ALU id operand. */
1976 else if (c
== '%' && (*ptr
== '#'))
1978 fputc (picochip_get_vliw_alu_id (), f
);
1981 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1982 INSN_UID (picochip_current_prescan_insn
));
1984 /* Skip past unwanted # */
1987 /* Detect the need for branch delay slot. */
1988 else if (c
== '%' && (*ptr
== '>'))
1990 /* Only emit delay slots (NOP's, or otherwise) when delay
1991 * slot scheduling has actually been enabled, otherwise VLIW
1992 * scheduling and delay slot scheduling output combine to
1993 * produce nasty effects. */
1994 if (flag_delayed_branch
)
1996 if (dbr_sequence_length () == 0)
1997 fputs ("\n=->\tNOP", f
);
1999 picochip_is_delay_slot_pending
= 1;
2002 /* Skip past unwanted > */
2005 /* Detect any %digit specifiers. */
2006 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
2009 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
2010 while ((c
= *ptr
) >= '0' && c
<= '9')
2013 /* Detect any %letterdigit specifiers. */
2014 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2015 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2017 int letter
= *ptr
++;
2024 output_asm_label (recog_data
.operand
[c
]);
2028 output_address (recog_data
.operand
[c
]);
2032 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
2035 while ((c
= *ptr
) >= '0' && c
<= '9')
2040 ("picochip_asm_output_opcode - can%'t output unknown operator %c",
2046 /* Reached the end of the packet. If any labels were deferred
2047 during output, emit them now. */
2048 if (!picochip_vliw_continuation
)
2050 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
2053 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
2055 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
2058 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
2063 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
2066 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
2071 /* Output an end-of-packet marker if requested. */
2072 if (!picochip_vliw_continuation
&&
2073 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
2074 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
2079 /* Function RTL expansion. */
2081 /* Expand the prologue into RTL. */
2083 picochip_expand_prologue (void)
2085 int stack_adjustment
= 0;
2086 int special_save_offset
= 0;
2087 int general_save_offset
= 0;
2088 int reg_save_offset
= 0;
2091 stack_adjustment
= picochip_arg_area_byte_offset ();
2092 general_save_offset
=
2093 -(stack_adjustment
- picochip_save_area_byte_offset ());
2094 special_save_offset
=
2095 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2097 /* Save the link registers. We could try to save just one register
2098 here. This would reduce the amount of stack space required.
2099 There hasnt been a good reason to do that so far. */
2100 if (!picochip_can_eliminate_link_sp_save ())
2101 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2102 special_save_offset
);
2104 /* Save callee-save registers. */
2105 reg_save_offset
= 0;
2106 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2108 if (picochip_reg_needs_saving (i
))
2111 /* If this register is an even numbered register, and the
2112 next register also needs to be saved, use a SImode save,
2113 which does both in one instruction. Note that a special
2114 check is performed to ensure that the double word aligned
2115 store is valid (e.g., it is possible that r6, r8, r9 need
2116 to be saved, in which case once r6 has been saved, the
2117 stored offset is no longer aligned, and an STL/LDL
2118 instruction becomes invalid). Alternately, we could store all
2119 aligned registers first and then save the single one(s). */
2121 picochip_reg_needs_saving (i
+ 1) &&
2122 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2124 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2125 general_save_offset
+
2127 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2132 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2133 general_save_offset
+
2135 reg_save_offset
+= UNITS_PER_WORD
;
2141 /* Emit a stack adjustment where required. */
2142 if (stack_adjustment
!= 0)
2143 picochip_emit_stack_allocate (stack_adjustment
);
2145 /* If this function uses varadic arguments, write any unnamed
2146 registers to the stack. */
2149 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2151 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2152 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2154 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2155 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2157 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2164 /* Expand the epilogue into RTL. */
2166 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2168 int stack_adjustment
= 0;
2169 int special_save_offset
= 0;
2170 int general_save_offset
= 0;
2171 int reg_save_offset
= 0;
2173 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2176 stack_adjustment
= picochip_arg_area_byte_offset ();
2177 general_save_offset
=
2178 -(stack_adjustment
- picochip_save_area_byte_offset ());
2179 special_save_offset
=
2180 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2182 /* Emit a stack adjustment where required. */
2183 if (stack_adjustment
!= 0)
2185 /* If the link/fp is already being restored, and the offset to
2186 their save location is small enough, don't bother adjusting
2187 the stack explicitly. */
2188 if (picochip_special_save_area_byte_offset () < 512 &&
2189 !picochip_can_eliminate_link_sp_save ())
2190 use_link_fp_restore_stack_adjust
= 1;
2192 /* Explicitly restore the stack. */
2193 picochip_emit_stack_allocate (-stack_adjustment
);
2196 /* Restore the Link/FP registers. Only save the link register? */
2197 if (!picochip_can_eliminate_link_sp_save ())
2199 if (use_link_fp_restore_stack_adjust
)
2200 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2201 picochip_special_save_area_byte_offset
2204 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2205 special_save_offset
);
2208 /* Restore callee-save registers. */
2209 reg_save_offset
= 0;
2210 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2212 if (picochip_reg_needs_saving (i
))
2215 /* If this register is an even numbered register, and the
2216 next register also needs to be saved, use a SImode save,
2217 which does both in one instruction. Note that a special
2218 check is performed to ensure that the double word aligned
2219 store is valid (e.g., it is possible that r6, r8, r9 need
2220 to be saved, in which case once r6 has been saved, the
2221 stored offset is no longer aligned, and an STL/LDL
2222 instruction becomes invalid). We could store all aligned
2223 registers first, and then save the single one(s). */
2225 picochip_reg_needs_saving (i
+ 1) &&
2226 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2228 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2229 general_save_offset
+
2231 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2236 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2237 general_save_offset
+
2239 reg_save_offset
+= UNITS_PER_WORD
;
2245 /* Emit a return instruction, which matches a (parallel
2246 [(return) (use r12)]) */
2249 p
= rtvec_alloc (2);
2251 RTVEC_ELT (p
, 0) = ret_rtx
;
2252 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2253 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2254 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2259 /* Assembly instruction output. */
2261 /* Test whether the given branch instruction is short, or long. Short
2262 * branches are equivalent to real branches, and may be DFA
2263 * scheduled. Long branches expand to a macro which is handled by the
2264 * elaborator, and cannot be scheduled. Occasionally, the branch
2265 * shortening pass, which is run after DFA scheduling, will change the
2266 * code layout and cause the short branch to be reverted into a long
2267 * branch. Instead of having to fix this up by emitting new assembly,
2268 * the short branch is emitted anyway. There is plenty of slack in the
2269 * calculation of long and short branches (10-bit offset, but only
2270 * 9-bits used in computation), so there is enough slack for this to
2273 picochip_is_short_branch (rtx insn
)
2275 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2277 return (isRealShortBranch
||
2278 picochip_current_vliw_state
.num_insns_in_packet
> 1);
2281 /* Output a compare-and-branch instruction (matching the cbranch
2284 picochip_output_cbranch (rtx operands
[])
2287 if (HImode
!= GET_MODE (operands
[1]) ||
2288 (HImode
!= GET_MODE (operands
[2]) &&
2289 GET_CODE (operands
[2]) != CONST_INT
))
2291 internal_error ("%s: at least one operand can%'t be handled",
2295 /* Use the type of comparison to output the appropriate condition
2297 switch (GET_CODE (operands
[0]))
2300 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2303 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2306 /* Reverse the operand order to be GE */
2307 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2310 /* Reverse operand order of GEU. */
2311 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2314 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2317 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2320 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2323 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2326 /* Reversed operand version of LT. */
2327 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2330 /* Reverse an LTU. */
2331 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2338 /* Output a compare-and-branch instruction (matching the cbranch
2339 pattern). This function is current unused since the cbranch
2340 split is disabled. The function is kept around so we can use
2341 it when we understand how to do cbranch split safely. */
2343 picochip_output_compare (rtx operands
[])
2347 if (HImode
!= GET_MODE (operands
[1]) ||
2348 (HImode
!= GET_MODE (operands
[2]) &&
2349 GET_CODE (operands
[2]) != CONST_INT
))
2351 internal_error ("%s: at least one operand can%'t be handled",
2355 code
= GET_CODE (operands
[0]);
2356 /* Use the type of comparison to output the appropriate condition
2361 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2364 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2367 /* Reverse the operand order to be GE */
2368 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2371 /* Reverse operand order of GEU. */
2372 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2375 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2378 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2381 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2384 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2387 /* Reversed operand version of LT. */
2388 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2391 /* Reverse an LTU. */
2392 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2399 /* Output the branch insn part of a compare-and-branch split. */
2401 picochip_output_branch (rtx operands
[], rtx insn
)
2404 int code
= GET_CODE(operands
[2]);
2405 if (picochip_is_short_branch (insn
))
2407 /* Short branches can be output directly using the
2408 appropriate instruction. */
2412 return ("BNE %l0 %>");
2414 return ("BEQ %l0 %>");
2416 return ("BGE %l0 %>");
2418 return ("BHS %l0 %>");
2420 return ("BGE %l0 %>");
2422 return ("BHS %l0 %>");
2424 return ("BLT %l0 %>");
2426 return ("BLO %l0 %>");
2428 return ("BLT %l0 %>");
2430 return ("BLO %l0 %>");
2432 internal_error ("unknown short branch in %s (type %d)",
2433 __FUNCTION__
, (int) INTVAL (operands
[1]));
2434 return "UNKNOWN_BRANCH";
2439 /* Long branches result in the emission of a special
2440 instruction, which the assembler expands into a suitable long
2443 /* Use the type of comparison to output the appropriate condition
2448 return ("JMPNE %l0 %>");
2450 return ("JMPEQ %l0 %>");
2452 return ("JMPGE %l0 %>");
2454 return ("JMPHS %l0 %>");
2456 return ("JMPGE %l0 %>");
2458 return ("JMPHS %l0 %>");
2460 return ("JMPLT %l0 %>");
2462 return ("JMPLO %l0 %>");
2464 return ("JMPLT %l0 %>");
2466 return ("JMPLO %l0 %>");
2469 internal_error ("unknown long branch in %s (type %d)",
2470 __FUNCTION__
, (int) INTVAL (operands
[1]));
2471 return "UNKNOWN_BRANCH";
2477 /* Output a jump instruction. */
2479 picochip_output_jump (rtx insn
)
2481 if (picochip_is_short_branch (insn
))
2484 return "JMPRA %l0%>";
2488 picochip_output_put_array (int alternative
, rtx operands
[])
2490 /* Local output buffer. */
2493 int portArraySize
= INTVAL(operands
[1]);
2494 int portBaseIndex
= INTVAL(operands
[2]);
2496 if (alternative
== 0)
2498 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2499 portArraySize
, portBaseIndex
);
2500 output_asm_insn (buf
, operands
);
2502 else if (alternative
== 1)
2504 /* Constant port id. Emit a real instruction. */
2505 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2506 if (portIndex
< portBaseIndex
||
2507 portIndex
>= (portBaseIndex
+ portArraySize
))
2509 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2510 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2512 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2513 output_asm_insn (buf
, operands
);
2518 /* Both alternatives output the insn directly. */
2522 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2524 /* Local output buffer. */
2527 int portArraySize
= INTVAL(operands
[1]);
2528 int portBaseIndex
= INTVAL(operands
[2]);
2530 if (alternative
== 0)
2532 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2533 portArraySize
, portBaseIndex
);
2534 output_asm_insn (buf
, operands
);
2536 else if (alternative
== 1)
2538 /* Constant port id. Emit a real instruction. */
2539 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2540 if (portIndex
< portBaseIndex
||
2541 portIndex
>= (portBaseIndex
+ portArraySize
))
2543 error ("GET uses port array index %d, which is out of range [%d..%d)",
2544 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2546 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2547 output_asm_insn (buf
, operands
);
2552 /* Both alternatives output the insn directly. */
2556 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2558 /* Local output buffer. */
2561 int portArraySize
= INTVAL(operands
[2]);
2562 int portBaseIndex
= INTVAL(operands
[3]);
2564 if (alternative
== 0)
2566 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2567 portArraySize
, portBaseIndex
);
2568 output_asm_insn (buf
, operands
);
2570 else if (alternative
== 1)
2572 /* Constant port id. Emit a real instruction. */
2573 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2574 if (portIndex
< portBaseIndex
||
2575 portIndex
>= (portBaseIndex
+ portArraySize
))
2577 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2578 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2580 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2581 output_asm_insn (buf
, operands
);
2586 /* Both alternatives output the insn directly. */
2590 /* Output a comparison operand as a symbol (e.g., >). */
2592 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2597 /* Output just the comparison symbol. */
2598 switch (GET_CODE (operand
))
2601 fprintf (file
, "!=");
2604 fprintf (file
, "==");
2607 fprintf (file
, ">=");
2610 fprintf (file
, ">={U}");
2613 fprintf (file
, "<");
2616 fprintf (file
, "<{U}");
2619 fprintf (file
, "<=");
2622 fprintf (file
, "<={U}");
2625 fprintf (file
, ">");
2628 fprintf (file
, ">{U}");
2636 /* Output the comparison formatted as operand,symbol,operand */
2637 rtx op0
= XEXP (operand
, 0);
2638 rtx op1
= XEXP (operand
, 1);
2640 picochip_print_operand (file
, op0
, 0);
2641 picochip_print_comparison (file
, operand
, 'i');
2642 picochip_print_operand (file
, op1
, 0);
2646 /* This function generates a memory address operand in the given
2647 mode. That is, if the address contains a constant offset, then the
2648 offset is divided by the required mode size to compute the
2649 mode specific offset. By default, picochip_print_operand_address calls
2650 this function using the natural mode of the operand, but special
2651 operand codes can be used to invoke the computation using an
2652 unnatural mode (e.g., compute the HI aligned address of an SI mode
2655 picochip_print_memory_address (FILE * file
, rtx operand
,
2656 enum machine_mode mode
)
2658 rtx address
= XEXP (operand
, 0);
2661 if (MEM
!= GET_CODE (operand
))
2662 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2667 printf ("picochip_print_memory_address: ");
2668 print_rtl (stdout
, operand
);
2672 switch (GET_CODE (address
))
2676 /* Grab the address components. */
2677 rtx base
= XEXP (address
, 0);
2678 rtx offset
= XEXP (address
, 1);
2680 /* Only handle reg+const addresses */
2681 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2683 /* Sanity check. If an FP+offset address is given, ensure
2684 that the offset lies within the given frame, or a lower
2686 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2687 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2690 /* Print the base register - identical for all modes. */
2691 fprintf (file
, "(");
2692 picochip_print_operand (file
, base
, 'r');
2693 fprintf (file
, ")");
2695 /* Print the constant offset with compensation for the mode. */
2699 picochip_print_operand (file
, offset
, 'Q');
2703 picochip_print_operand (file
, offset
, 'H');
2708 picochip_print_operand (file
, offset
, 'S');
2712 picochip_print_operand (file
, offset
, 'D');
2726 picochip_print_operand (file
, address
, 's');
2735 inner
= XEXP (address
, 0);
2737 /* Sanity check - the CONST memory address must be a base+offset. */
2738 gcc_assert (PLUS
== GET_CODE (inner
));
2740 base
= XEXP (inner
, 0);
2741 offset
= XEXP (inner
, 1);
2743 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2749 /* Register operand. Provide a zero offset. */
2750 fprintf (file
, "(");
2751 picochip_print_operand (file
, address
, 'r');
2752 fprintf (file
, ")0");
2761 /* Output an operand. Formatting letters allow particular parts of
2762 the operand to be output. */
2764 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2767 /* Handle special cases. */
2770 /* VLIW continuation, for explicit VLIW sequences. */
2772 fprintf (file
, "\\");
2777 fputc (picochip_get_vliw_alu_id (), file
);
2780 /* Delay slot specifier. */
2782 /* This should be handled in asm_output_opcode. */
2785 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2787 switch (GET_CODE (operand
))
2790 fprintf (file
, "AND");
2793 fprintf (file
, "OR");
2796 fprintf (file
, "XOR");
2799 fprintf (file
, "ADD");
2802 fprintf (file
, "SUB");
2809 /* Symbolic instructions (e.g., lshift becomes <<). */
2811 switch (GET_CODE (operand
))
2814 fprintf (file
, "&");
2817 fprintf (file
, "|");
2820 fprintf (file
, "^");
2823 fprintf (file
, "+");
2826 fprintf (file
, "-");
2829 fprintf (file
, "UNKNOWN_INSN");
2834 default: /* Not a punctuation character - process as normal. */
2838 switch (GET_CODE (operand
))
2844 /* Write a range of registers. */
2845 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2849 /* The upper register of a pair is requested. */
2850 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2854 /* The lower register of a pair is requested. Equivalent to the
2855 default, but included for completeness. */
2856 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2860 /* The 3rd register of a DI mode register. */
2861 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2865 /* The 4th register of a DI mode register. */
2866 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2870 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2875 /* A range of letters can be used to format integers. The
2876 letters Q/H/S are used to divide the constant by the width of
2877 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2878 to obtain the upper and lower 16-bits of a 32-bit
2879 constant. Where possible, signed numbers are used, since
2880 signed representations of numbers may be more compact (e.g.,
2881 65535 can be represented as -1, which fits into a small
2882 constant, whereas 65535 requires a large constant). */
2886 fprintf (file
, "%ld", INTVAL (operand
));
2890 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2894 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2898 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2902 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2906 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2910 fprintf (file
, "%ld", INTVAL (operand
));
2920 if (GET_MODE (operand
) != SFmode
)
2921 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2923 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2924 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2929 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2933 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2941 /* Output a symbol. The output format must match that of
2942 picochip_output_label. */
2944 /* Ensure that the symbol is marked as referenced. Gcc can
2945 occasionally omit the function bodies when it believes them
2946 to be unreferenced. */
2947 if (SYMBOL_REF_DECL (operand
))
2948 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2949 fprintf (file
, "&");
2950 assemble_name (file
, XSTR (operand
, 0));
2954 /* This format must match that of picochip_output_label. */
2955 fprintf (file
, "&");
2956 output_asm_label (operand
);
2961 rtx addr
= XEXP (operand
, 0);
2966 if (PLUS
!= GET_CODE (addr
))
2967 fatal_insn ("Bad address, not (reg+disp):", addr
);
2969 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2973 /* Output a memory address in byte mode notation (i.e., the
2974 constant address (if any) is the actual byte address. */
2975 picochip_print_memory_address (file
, operand
, QImode
);
2978 /* Output a constant offset of the given mode (i.e., divide
2979 the constant by the number of units in the mode to get the
2982 picochip_print_memory_address (file
, operand
, QImode
);
2986 picochip_print_memory_address (file
, operand
, HImode
);
2990 picochip_print_memory_address (file
, operand
, SImode
);
2994 picochip_print_memory_address (file
, operand
, SFmode
);
2998 if (PLUS
!= GET_CODE (addr
))
2999 fatal_insn ("Bad address, not (reg+disp):", addr
);
3001 picochip_print_operand (file
, XEXP (addr
, 0), 0);
3004 /* When the mem operand is (reg + big offset) which cannot
3005 be represented in an instruction as operand, the compiler
3006 automatically generates the instruction to put in (reg +
3007 big offset) into another register. In such cases, it
3008 returns '0' as the character. This needs to be handled
3012 if (REG
!= GET_CODE (addr
))
3013 fatal_insn ("Bad address, not register:", addr
);
3015 picochip_print_operand (file
, addr
, 0);
3019 fprintf (file
, "Unknown mem operand - letter %c ",
3021 print_rtl (file
, operand
);
3029 rtx const_exp
= XEXP (operand
, 0);
3031 /* Handle constant offsets to symbol references. */
3032 if (PLUS
== GET_CODE (const_exp
) &&
3033 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
3034 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
3037 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
3038 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
3039 fprintf (file
, "+");
3040 /* else use the - from the operand (i.e., AP-2)) */
3042 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
3051 /* PLUS expressions are of the form (base + offset). Different
3052 options (analagous to those of memory PLUS expressions) are used
3053 to extract the base and offset components. */
3058 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3062 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3067 /* If the expression is composed entirely of constants,
3068 evaluate the result. This should only occur with the
3069 picoChip specific comms instructions, which are emitted as
3070 base+offset expressions. */
3071 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
3072 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
3074 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
3075 XINT (XEXP (operand
, 1), 0));
3076 fprintf (file
, "%ld", result
);
3080 fprintf (file
, "(");
3081 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3082 fprintf (file
, "+");
3083 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3084 fprintf (file
, ")");
3091 /* Comparison operations. */
3102 picochip_print_comparison (file
, operand
, letter
);
3106 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3107 print_rtl (file
, operand
);
3114 /* Output an operand address */
3116 picochip_print_operand_address (FILE * file
, rtx operand
)
3119 switch (GET_CODE (operand
))
3123 /* This format must match that of picochip_output_label. */
3124 assemble_name (file
, XSTR (operand
, 0));
3128 /* Note this format must match that of picochip_output_label. */
3129 fprintf (file
, "_L%d", XINT (operand
, 5));
3133 /* Pass on to a specialised memory address generator. */
3134 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3145 /* Scheduling functions. */
3147 /* Save some of the contents of recog_data. */
3149 picochip_save_recog_data (void)
3151 picochip_saved_which_alternative
= which_alternative
;
3152 memcpy (&picochip_saved_recog_data
, &recog_data
,
3153 sizeof (struct recog_data
));
3156 /* Restore some of the contents of global variable recog_data. */
3158 picochip_restore_recog_data (void)
3160 which_alternative
= picochip_saved_which_alternative
;
3161 memcpy (&recog_data
, &picochip_saved_recog_data
,
3162 sizeof (struct recog_data
));
3165 /* Ensure that no var tracking notes are emitted in the middle of a
3166 three-instruction bundle. */
3168 reorder_var_tracking_notes (void)
3174 rtx insn
, next
, last_insn
= NULL_RTX
;
3175 rtx queue
= NULL_RTX
;
3177 /* Iterate through the bb and find the last non-debug insn */
3178 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= NEXT_INSN(insn
))
3180 if (NONDEBUG_INSN_P(insn
))
3184 /* In all normal cases, queue up notes and emit them just before a TImode
3185 instruction. For the last instruction, emit the queued notes just after
3186 the last instruction. */
3187 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= next
)
3189 next
= NEXT_INSN (insn
);
3191 if (insn
== last_insn
)
3195 rtx next_queue
= PREV_INSN (queue
);
3196 PREV_INSN (NEXT_INSN(insn
)) = queue
;
3197 NEXT_INSN(queue
) = NEXT_INSN(insn
);
3198 PREV_INSN(queue
) = insn
;
3199 NEXT_INSN(insn
) = queue
;
3202 /* There is no more to do for this bb. break*/
3205 else if (NONDEBUG_INSN_P (insn
))
3207 /* Emit queued up notes before the first instruction of a bundle. */
3208 if (GET_MODE (insn
) == TImode
)
3212 rtx next_queue
= PREV_INSN (queue
);
3213 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3214 PREV_INSN (queue
) = PREV_INSN(insn
);
3215 PREV_INSN (insn
) = queue
;
3216 NEXT_INSN (queue
) = insn
;
3221 else if (NOTE_P (insn
))
3223 rtx prev
= PREV_INSN (insn
);
3224 PREV_INSN (next
) = prev
;
3225 NEXT_INSN (prev
) = next
;
3226 /* Ignore call_arg notes. They are expected to be just after the
3227 call insn. If the call is start of a long VLIW, labels are
3228 emitted in the middle of a VLIW, which our assembler can not
3230 if (NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
3232 PREV_INSN (insn
) = queue
;
3237 /* Make sure we are not dropping debug instructions.*/
3238 gcc_assert (queue
== NULL_RTX
);
3242 /* Perform machine dependent operations on the rtl chain INSNS. */
3244 picochip_reorg (void)
3246 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3247 int vliw_insn_location
= 0;
3249 /* We are freeing block_for_insn in the toplev to keep compatibility
3250 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3251 compute_bb_for_insn ();
3256 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3258 timevar_push (TV_SCHED2
);
3260 /* Process the instruction list, computing the sizes of each
3261 instruction, and consequently branch distances. This can
3262 result in some branches becoming short enough to be treated
3263 as a real branch instruction, rather than an assembly branch
3264 macro which may expand into multiple instructions. The
3265 benefit of shortening branches is that real branch
3266 instructions can be properly DFA scheduled, whereas macro
3268 shorten_branches (get_insns ());
3270 /* Do control and data sched analysis again,
3271 and write some more of the results to dump file. */
3277 timevar_pop (TV_SCHED2
);
3281 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3283 /* Whenever a VLIW packet is generated, all instructions in
3284 that packet must appear to come from the same source
3285 location. The following code finds all the VLIW packets,
3286 and tags their instructions with the location of the first
3287 instruction from the packet. Clearly this will result in
3288 strange behaviour when debugging the code, but since
3289 debugging and optimisation are being used in conjunction,
3290 strange behaviour is certain to occur anyway. */
3291 /* Slight bit of change. If the vliw set contains a branch
3292 or call instruction, we pick its location.*/
3293 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3296 /* If this is the first instruction in the VLIW packet,
3297 extract its location. */
3298 if (GET_MODE (insn
) == TImode
)
3301 vliw_insn_location
= INSN_LOCATION (insn
);
3303 if (JUMP_P (insn
) || CALL_P(insn
))
3305 vliw_insn_location
= INSN_LOCATION (insn
);
3306 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3307 INSN_LOCATION (insn1
) = vliw_insn_location
;
3309 /* Tag subsequent instructions with the same location. */
3310 INSN_LOCATION (insn
) = vliw_insn_location
;
3316 /* Locate the note marking the end of the function's prologue. If
3317 the note appears in the middle of a VLIW packet, move the note to
3318 the end. This avoids unpleasant consequences such as trying to
3319 emit prologue markers (e.g., .loc/.file directives) in the middle
3321 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3323 rtx prologue_end_note
= NULL
;
3324 rtx last_insn_in_packet
= NULL
;
3326 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3328 /* The prologue end must be moved to the end of the VLIW packet. */
3329 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3331 prologue_end_note
= insn
;
3336 /* Find the last instruction in this packet. */
3337 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3339 if (GET_MODE (insn
) == TImode
)
3342 last_insn_in_packet
= insn
;
3345 if (last_insn_in_packet
!= NULL
)
3348 = emit_note_after ((enum insn_note
) NOTE_KIND (prologue_end_note
),
3349 last_insn_in_packet
);
3350 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3351 delete_insn (prologue_end_note
);
3355 if (flag_var_tracking
)
3357 timevar_push (TV_VAR_TRACKING
);
3358 variable_tracking_main ();
3359 /* We also have to deal with variable tracking notes in the
3360 middle of VLIW packets. */
3361 reorder_var_tracking_notes();
3362 timevar_pop (TV_VAR_TRACKING
);
3366 /* Return the ALU character identifier for the current
3367 instruction. This will be 0 or 1. */
3369 picochip_get_vliw_alu_id (void)
3373 /* Always use ALU 0 if VLIW scheduling is disabled. */
3374 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3377 /* Get the attribute type of the instruction. Note that this can
3378 ruin the contents of recog_data, so save/restore around the
3380 picochip_save_recog_data ();
3381 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3382 picochip_restore_recog_data ();
3384 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3387 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3388 else it must be the other ALU (either basic or nonCc)
3389 instruction which goes into 1. */
3390 if (attr_type
== TYPE_PICOALU
)
3396 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3398 /* Is this the non CC instruction? If it is, then stuff it into
3399 ALU 1, else it must be a picoAlu or basicAlu, in which case
3400 it goes into ALU 0. */
3401 if (attr_type
== TYPE_NONCCALU
)
3408 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3409 whether an ALU instruction has already been scheduled in this
3411 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3414 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3418 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3422 internal_error ("too many ALU instructions emitted (%d)",
3423 picochip_current_vliw_state
.num_alu_insns_so_far
);
3430 /* Reset any information about the current VLIW packing status. */
3432 picochip_reset_vliw (rtx insn
)
3434 rtx local_insn
= insn
;
3436 /* Nothing to do if VLIW scheduling isn't being used. */
3437 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3441 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3444 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3445 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3446 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3447 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3448 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3449 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3451 /* Read through the VLIW packet, classifying the instructions where
3456 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3458 local_insn
= NEXT_INSN (local_insn
);
3461 else if (!INSN_P (local_insn
))
3465 /* It is an instruction, but is it ours? */
3466 if (INSN_CODE (local_insn
) != -1)
3470 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3472 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3473 get_attr_type function can overwrite the values in
3474 the recog_data global, hence this is saved and
3475 restored around the call. Not doing so results in
3476 asm_output_opcode being called with a different
3477 instruction to final_prescan_insn, which is fatal. */
3478 picochip_save_recog_data ();
3479 attr_type
= get_attr_type (local_insn
);
3480 picochip_restore_recog_data ();
3482 if (attr_type
== TYPE_PICOALU
)
3483 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3484 if (attr_type
== TYPE_NONCCALU
)
3485 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3490 /* Get the next instruction. */
3491 local_insn
= NEXT_INSN (local_insn
);
3493 /* Keep going while the next instruction is part of the same
3494 VLIW packet (i.e., its a valid instruction and doesn't mark
3495 the start of a new VLIW packet. */
3497 while (local_insn
&&
3498 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3503 picochip_sched_reorder (FILE * file
, int verbose
,
3504 rtx
* ready ATTRIBUTE_UNUSED
,
3505 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3509 fprintf (file
, ";;\tClock %d\n", clock
);
3511 return picochip_sched_issue_rate ();
3516 picochip_sched_lookahead (void)
3518 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3524 picochip_sched_issue_rate (void)
3529 /* Adjust the scheduling cost between the two given instructions,
3530 which have the given dependency. */
3532 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3537 printf ("Sched Adjust Cost: %d->%d is %d\n",
3538 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3540 printf (" Dependency type:");
3541 switch (REG_NOTE_KIND (link
))
3549 case REG_DEP_OUTPUT
:
3550 printf ("OUTPUT\n");
3553 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3557 /* Anti-dependencies are used to enforce the ordering between a
3558 * branch, and any subsequent instructions. For example:
3563 * The ADD instruction must execute after the branch, and this is
3564 * enforced using an anti-dependency. Unfortunately, VLIW machines
3565 * are happy to execute anti-dependent instructions in the same
3566 * cycle, which then results in a schedule like the following being
3569 * BNE someLabel \ ADD.0 r0,r1,r2
3571 * The instruction which would normally be conditionally executed
3572 * depending upon the outcome of the branch, is now unconditionally
3573 * executed every time. To prevent this happening, any
3574 * anti-dependencies between a branch and another instruction are
3575 * promoted to become real dependencies.
3577 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3581 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3582 INSN_UID (insn
), INSN_UID (dep_insn
));
3591 /* Return the minimum of the two values */
3593 minimum (int a
, int b
)
3599 /* I dont expect to get to this function with a==b.*/
3604 /* This function checks if the memory of the two stores are just off by 2 bytes.
3605 It returns the lower memory operand's index.*/
3608 memory_just_off (rtx opnd1
, rtx opnd2
)
3610 int offset1
= 0, offset2
= 0;
3613 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3615 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3616 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3620 reg1
= REGNO(XEXP(opnd1
, 0));
3622 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3624 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3625 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3629 reg2
= REGNO(XEXP(opnd2
, 0));
3632 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3633 should be 4 byte aligned. We can currently guarentee that only if the base
3634 address is FP(R13) and the offset is aligned. */
3636 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3637 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3643 registers_just_off (rtx opnd1
, rtx opnd2
)
3646 reg1
= REGNO(opnd1
);
3647 reg2
= REGNO(opnd2
);
3648 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3649 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3653 /* Check to see if the two LDWs can be peepholed together into a LDL
3654 They can be if the registers getting loaded into are contiguous
3655 and the memory addresses are contiguous as well.
3659 can be merged together into
3663 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3664 aligned address. Only FP can be assumed to be 4 byte aligned.
3665 2. The progression of addresses and the register numbers should
3666 be similar. For eg., if you swap r2 and r3 in the above instructions,
3667 the resultant pair cannot be merged.
3671 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3673 int memtest
=0,regtest
=0;
3674 regtest
= registers_just_off(opnd1
,opnd3
);
3678 memtest
= memory_just_off(opnd0
,opnd2
);
3682 if (regtest
== memtest
)
3689 /* Similar to LDW peephole */
3691 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3693 int memtest
=0,regtest
=0;
3694 regtest
= registers_just_off(opnd1
,opnd3
);
3698 memtest
= memory_just_off(opnd0
,opnd2
);
3702 if (regtest
== memtest
)
3710 /* Generate a SImode register with the register number that is the smaller of the two */
3712 gen_min_reg(rtx opnd1
,rtx opnd2
)
3714 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3717 /* Generate a SImode memory with the address that is the smaller of the two */
3719 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3721 int offset1
=0,offset2
=0;
3724 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3726 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3727 reg
= XEXP(XEXP(opnd1
,0),0);
3731 reg
= XEXP(opnd1
,0);
3733 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3735 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3737 address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3738 return gen_rtx_MEM(SImode
,address
);
3742 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
3743 int opno ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3750 /* Need to penalize immediates that need to be encoded as long constants.*/
3751 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3753 *total
= COSTS_N_INSNS(1);
3761 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3766 /* if_then_else come out of cbranch instructions. It will get split into
3767 a condition code generating subtraction and a branch */
3768 *total
= COSTS_N_INSNS (2);
3775 if (GET_MODE(x
) == SImode
)
3776 *total
= COSTS_N_INSNS (2);
3777 if (GET_MODE(x
) == DImode
)
3778 *total
= COSTS_N_INSNS (4);
3782 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3783 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3784 *total
= COSTS_N_INSNS (10);
3786 /* 64-bit accesses have to be done through 2 32-bit access */
3787 if (GET_MODE(x
) == DImode
)
3788 *total
= COSTS_N_INSNS (2);
3794 /* SImode shifts are expensive */
3795 if (GET_MODE(x
) == SImode
)
3796 *total
= COSTS_N_INSNS (10);
3798 /* Register shift by constant is cheap. */
3799 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3800 && GET_CODE(XEXP(x
, 0)) == REG
3801 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3802 *total
= COSTS_N_INSNS (1);
3804 *total
= COSTS_N_INSNS (4);
3811 /* Divisions are more expensive than the default 7*/
3812 if (GET_MODE(x
) == SImode
)
3813 *total
= COSTS_N_INSNS (20);
3815 *total
= COSTS_N_INSNS (12);
3820 /* Look for the simple cases of multiplying register*register or
3821 register*constant. */
3822 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3823 && ((GET_CODE(XEXP(x
, 0)) == REG
3824 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3825 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3826 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3827 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3828 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3831 /* When optimising for size, multiplication by constant
3832 should be discouraged slightly over multiplication by a
3834 if (picochip_has_mac_unit
)
3836 /* Single cycle multiplication, but the result must be
3837 loaded back into a general register afterwards. */
3838 *total
= COSTS_N_INSNS(2);
3841 else if (picochip_has_mul_unit
)
3843 /* Single cycle multiplication. */
3844 *total
= COSTS_N_INSNS(1);
3847 /* Else no multiply available. Use default cost. */
3857 if (localTotal
!= 0)
3859 *total
= localTotal
;
3870 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3871 int num_operands ATTRIBUTE_UNUSED
)
3875 picochip_current_prescan_insn
= insn
;
3878 printf ("Final prescan on INSN %d with mode %s\n",
3879 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3881 /* If this is the start of a new instruction cycle, or no scheduling
3882 is used, then reset the VLIW status. */
3883 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3884 picochip_reset_vliw (insn
);
3886 /* No VLIW scheduling occured, so don't go any further. */
3887 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3890 /* Look for the next printable instruction. This loop terminates on
3891 any recognisable instruction, and on any unrecognisable
3892 instruction with TImode. */
3894 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3895 local_insn
= NEXT_INSN (local_insn
))
3897 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3899 else if (!INSN_P (local_insn
))
3901 else if (GET_MODE (local_insn
) == TImode
3902 || INSN_CODE (local_insn
) != -1)
3906 /* Set the continuation flag if the next instruction can be packed
3907 with the current instruction (i.e., the next instruction is
3908 valid, and isn't the start of a new cycle). */
3909 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3910 (GET_MODE (local_insn
) != TImode
));
3914 /* Builtin functions. */
3915 /* Given a builtin function taking 2 operands (i.e., target + source),
3916 emit the RTL for the underlying instruction. */
3918 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3922 enum machine_mode tmode
, mode0
;
3924 /* Grab the incoming argument and emit its RTL. */
3925 arg0
= CALL_EXPR_ARG (call
, 0);
3926 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3928 /* Determine the modes of the instruction operands. */
3929 tmode
= insn_data
[icode
].operand
[0].mode
;
3930 mode0
= insn_data
[icode
].operand
[1].mode
;
3932 /* Ensure that the incoming argument RTL is in a register of the
3934 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3935 op0
= copy_to_mode_reg (mode0
, op0
);
3937 /* If there isn't a suitable target, emit a target register. */
3939 || GET_MODE (target
) != tmode
3940 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3941 target
= gen_reg_rtx (tmode
);
3943 /* Emit and return the new instruction. */
3944 pat
= GEN_FCN (icode
) (target
, op0
);
3953 /* Given a builtin function taking 3 operands (i.e., target + two
3954 source), emit the RTL for the underlying instruction. */
3956 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3960 enum machine_mode tmode
, mode0
, mode1
;
3962 /* Grab the function's arguments. */
3963 arg0
= CALL_EXPR_ARG (call
, 0);
3964 arg1
= CALL_EXPR_ARG (call
, 1);
3966 /* Emit rtl sequences for the function arguments. */
3967 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3968 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3970 /* Get the mode's of each of the instruction operands. */
3971 tmode
= insn_data
[icode
].operand
[0].mode
;
3972 mode0
= insn_data
[icode
].operand
[1].mode
;
3973 mode1
= insn_data
[icode
].operand
[2].mode
;
3975 /* Ensure that each of the function argument rtl sequences are in a
3976 register of the correct mode. */
3977 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3978 op0
= copy_to_mode_reg (mode0
, op0
);
3979 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3980 op1
= copy_to_mode_reg (mode1
, op1
);
3982 /* If no target has been given, create a register to use as the target. */
3984 || GET_MODE (target
) != tmode
3985 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3986 target
= gen_reg_rtx (tmode
);
3988 /* Emit and return the new instruction. */
3989 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
3998 /* Expand a builtin function which takes two arguments, and returns a void. */
4000 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
4004 enum machine_mode mode0
, mode1
;
4006 /* Grab the function's arguments. */
4007 arg0
= CALL_EXPR_ARG (call
, 0);
4008 arg1
= CALL_EXPR_ARG (call
, 1);
4010 /* Emit rtl sequences for the function arguments. */
4011 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4012 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4014 /* Get the mode's of each of the instruction operands. */
4015 mode0
= insn_data
[icode
].operand
[0].mode
;
4016 mode1
= insn_data
[icode
].operand
[1].mode
;
4018 /* Ensure that each of the function argument rtl sequences are in a
4019 register of the correct mode. */
4020 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
4021 op0
= copy_to_mode_reg (mode0
, op0
);
4022 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
4023 op1
= copy_to_mode_reg (mode1
, op1
);
4025 /* Emit and return the new instruction. */
4026 pat
= GEN_FCN (icode
) (op0
, op1
);
4035 /* Expand an array get into the corresponding RTL. */
4037 picochip_expand_array_get (tree call
, rtx target
)
4039 tree arg0
, arg1
, arg2
;
4040 rtx op0
, op1
, op2
, pat
;
4042 /* Grab the function's arguments. */
4043 arg0
= CALL_EXPR_ARG (call
, 0);
4044 arg1
= CALL_EXPR_ARG (call
, 1);
4045 arg2
= CALL_EXPR_ARG (call
, 2) ;
4047 /* Emit rtl sequences for the function arguments. */
4048 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4049 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4050 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4052 /* The second and third operands must be constant. Nothing else will
4054 if (CONST_INT
!= GET_CODE (op1
))
4055 internal_error ("%s: Second source operand is not a constant",
4057 if (CONST_INT
!= GET_CODE (op2
))
4058 internal_error ("%s: Third source operand is not a constant",
4061 /* If no target has been given, create a register to use as the target. */
4062 if (target
== 0 || GET_MODE (target
) != SImode
)
4063 target
= gen_reg_rtx (SImode
);
4065 /* The first operand must be a HImode register or a constant. If it
4066 isn't, force it into a HImode register. */
4067 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4068 op0
= copy_to_mode_reg (HImode
, op0
);
4071 /* Emit and return the new instruction. */
4072 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
4079 /* Expand an array put into the corresponding RTL. */
4081 picochip_expand_array_put (tree call
, rtx target
)
4083 tree arg0
, arg1
, arg2
, arg3
;
4084 rtx op0
, op1
, op2
, op3
, pat
;
4086 /* Grab the function's arguments. */
4087 arg0
= CALL_EXPR_ARG (call
, 0);
4088 arg1
= CALL_EXPR_ARG (call
, 1);
4089 arg2
= CALL_EXPR_ARG (call
, 2);
4090 arg3
= CALL_EXPR_ARG (call
, 3);
4092 /* Emit rtl sequences for the function arguments. */
4093 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4094 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4095 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4096 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4098 /* The first operand must be an SImode register. */
4099 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
4100 op0
= copy_to_mode_reg (SImode
, op0
);
4102 /* The second (index) operand must be a HImode register, or a
4103 constant. If it isn't, force it into a HImode register. */
4104 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
4105 op1
= copy_to_mode_reg (HImode
, op1
);
4107 /* The remaining operands must be constant. Nothing else will do. */
4108 if (CONST_INT
!= GET_CODE (op2
))
4109 internal_error ("%s: Third source operand is not a constant",
4111 if (CONST_INT
!= GET_CODE (op3
))
4112 internal_error ("%s: Fourth source operand is not a constant",
4115 /* Emit and return the new instruction. */
4116 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
4123 /* Expand an array testport into the corresponding RTL. */
4125 picochip_expand_array_testport (tree call
, rtx target
)
4127 tree arg0
, arg1
, arg2
;
4128 rtx op0
, op1
, op2
, pat
;
4130 /* Grab the function's arguments. */
4131 arg0
= CALL_EXPR_ARG (call
, 0);
4132 arg1
= CALL_EXPR_ARG (call
, 1);
4133 arg2
= CALL_EXPR_ARG (call
, 2);
4135 /* Emit rtl sequences for the function arguments. */
4136 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4137 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4138 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4140 /* The first operand must be a HImode register, or a constant. If it
4141 isn't, force it into a HImode register. */
4142 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4143 op0
= copy_to_mode_reg (HImode
, op0
);
4145 /* The second and third operands must be constant. Nothing else will
4147 if (CONST_INT
!= GET_CODE (op1
))
4148 internal_error ("%s: Second source operand is not a constant",
4150 if (CONST_INT
!= GET_CODE (op2
))
4151 internal_error ("%s: Third source operand is not a constant",
4154 /* If no target has been given, create a HImode register to use as
4156 if (target
== 0 || GET_MODE (target
) != HImode
)
4157 target
= gen_reg_rtx (HImode
);
4159 /* Emit and return the new instruction. */
4160 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4167 /* Generate a unique HALT instruction by giving the instruction a
4168 unique integer. This integer makes no difference to the assembly
4169 output (other than a comment indicating the supplied id), but the
4170 presence of the unique integer prevents the compiler from combining
4171 several different halt instructions into one instruction. This
4172 means that each use of the halt instruction is unique, which in
4173 turn means that assertions work as expected. */
4175 picochip_generate_halt (void)
4177 static int currentId
= 0;
4179 rtx id
= GEN_INT (currentId
);
4183 emit_insn (gen_halt (id
));
4185 /* A barrier is inserted to prevent the compiler from thinking that
4186 it has to continue execution after the HALT.*/
4189 insns
= get_insns();
4196 /* Initialise the builtin functions. Start by initialising
4197 descriptions of different types of functions (e.g., void fn(int),
4198 int fn(void)), and then use these to define the builtins. */
4200 picochip_init_builtins (void)
4204 tree int_ftype_int
, int_ftype_int_int
;
4205 tree long_ftype_int
, long_ftype_int_int_int
;
4206 tree void_ftype_int_long
, int_ftype_int_int_int
,
4207 void_ftype_long_int_int_int
;
4208 tree void_ftype_void
, unsigned_ftype_unsigned
;
4210 /* void func (void) */
4211 void_ftype_void
= build_function_type_list (void_type_node
, NULL_TREE
);
4213 /* int func (int) */
4214 int_ftype_int
= build_function_type_list (integer_type_node
,
4215 integer_type_node
, NULL_TREE
);
4217 /* unsigned int func (unsigned int) */
4218 unsigned_ftype_unsigned
4219 = build_function_type_list (unsigned_type_node
,
4220 unsigned_type_node
, NULL_TREE
);
4222 /* int func(int, int) */
4224 = build_function_type_list (integer_type_node
,
4225 integer_type_node
, integer_type_node
,
4228 /* long func(int) */
4229 long_ftype_int
= build_function_type_list (long_integer_type_node
,
4230 integer_type_node
, NULL_TREE
);
4232 /* long func(int, int, int) */
4233 long_ftype_int_int_int
4234 = build_function_type_list (long_integer_type_node
,
4235 integer_type_node
, integer_type_node
,
4236 integer_type_node
, NULL_TREE
);
4238 /* int func(int, int, int) */
4239 int_ftype_int_int_int
4240 = build_function_type_list (integer_type_node
,
4241 integer_type_node
, integer_type_node
,
4242 integer_type_node
, NULL_TREE
);
4244 /* void func(int, long) */
4246 = build_function_type_list (void_type_node
,
4247 integer_type_node
, long_integer_type_node
,
4250 /* void func(long, int, int, int) */
4251 void_ftype_long_int_int_int
4252 = build_function_type_list (void_type_node
,
4253 long_integer_type_node
, integer_type_node
,
4254 integer_type_node
, integer_type_node
,
4257 /* Initialise the sign-bit-count function. */
4258 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4259 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4261 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4262 BUILT_IN_MD
, NULL
, NULL_TREE
);
4264 /* Initialise the bit reverse function. */
4265 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4266 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4268 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4269 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4272 /* Initialise the byte swap function. */
4273 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4274 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4276 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4277 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4280 /* Initialise the ASRI function (note that while this can be coded
4281 using a signed shift in C, extra scratch registers are required,
4282 which we avoid by having a direct builtin to map to the
4284 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4285 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4288 /* Initialise saturating addition. */
4289 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4290 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4292 add_builtin_function ("picoAdds", int_ftype_int_int
,
4293 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4296 /* Initialise saturating subtraction. */
4297 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4298 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4300 add_builtin_function ("picoSubs", int_ftype_int_int
,
4301 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4304 /* Scalar comms builtins. */
4305 add_builtin_function ("__builtin_get", long_ftype_int
,
4306 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4308 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4309 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4311 add_builtin_function ("__builtin_testport", int_ftype_int
,
4312 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4315 /* Array comms builtins. */
4316 add_builtin_function ("__builtin_put_array",
4317 void_ftype_long_int_int_int
,
4318 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4320 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4321 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4323 add_builtin_function ("__builtin_testport_array",
4324 int_ftype_int_int_int
,
4325 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4328 /* Halt instruction. Note that the builtin function is marked as
4329 having the attribute `noreturn' so that the compiler realises
4330 that the halt stops the program dead. */
4331 noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4332 add_builtin_function ("__builtin_halt", void_ftype_void
,
4333 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4335 add_builtin_function ("picoHalt", void_ftype_void
,
4336 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4341 /* Expand a call to a builtin function. */
4343 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4344 enum machine_mode mode ATTRIBUTE_UNUSED
,
4345 int ignore ATTRIBUTE_UNUSED
)
4347 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4348 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4352 case PICOCHIP_BUILTIN_ASRI
:
4353 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4356 case PICOCHIP_BUILTIN_ADDS
:
4357 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4360 case PICOCHIP_BUILTIN_SUBS
:
4361 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4364 case PICOCHIP_BUILTIN_SBC
:
4365 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4367 case PICOCHIP_BUILTIN_BREV
:
4368 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4370 case PICOCHIP_BUILTIN_BYTESWAP
:
4371 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4373 case PICOCHIP_BUILTIN_GET
:
4374 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4376 case PICOCHIP_BUILTIN_PUT
:
4377 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4379 case PICOCHIP_BUILTIN_TESTPORT
:
4380 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4383 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4384 return picochip_expand_array_put (exp
, target
);
4386 case PICOCHIP_BUILTIN_GET_ARRAY
:
4387 return picochip_expand_array_get (exp
, target
);
4389 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4390 return picochip_expand_array_testport (exp
, target
);
4392 case PICOCHIP_BUILTIN_HALT
:
4393 return picochip_generate_halt ();
4400 /* Should really do something sensible here. */
4404 /* Emit warnings. */
4406 picochip_warn_inefficient (const char *msg
)
4408 if (TARGET_INEFFICIENT_WARNINGS
)
4409 warning (OPT_minefficient_warnings
,
4410 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4414 warn_of_byte_access (void)
4416 static int warned
= 0;
4420 picochip_warn_inefficient
4421 ("byte access is synthesised - consider using MUL AE");
4428 picochip_function_value (const_tree valtype
, const_tree func
,
4429 bool outgoing ATTRIBUTE_UNUSED
)
4431 enum machine_mode mode
= TYPE_MODE (valtype
);
4432 int unsignedp
= TYPE_UNSIGNED (valtype
);
4434 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4435 just as PROMOTE_MODE does. */
4436 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4438 return gen_rtx_REG (mode
, 0);
4442 /* Check that the value of the given mode will fit in the register of
4445 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4448 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4449 return regno
== CC_REGNUM
;
4451 /* If the CC register is being used, then only CC mode values are
4452 allowed (which have already been tested). */
4453 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4456 /* Must be a valid register. */
4460 /* Modes QI and HI may be placed in any register except the CC. */
4461 if (mode
== QImode
|| mode
== HImode
)
4464 /* DI must be in a quad register. */
4466 return (regno
% 4 == 0);
4468 /* All other modes must be placed in a even numbered register. */
4469 return !(regno
& 1);
4473 /* Extract the lower and upper components of a constant value. */
4476 picochip_get_low_const (rtx value
)
4478 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4482 picochip_get_high_const (rtx value
)
4484 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4485 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4489 /* Loading and storing QImode values to and from memory in a machine
4490 without byte access requires might require a scratch
4491 register. However, the scratch register might correspond to the
4492 register in which the value is being loaded. To ensure that a
4493 scratch register is supplied which is definitely different to the
4494 output register, request a register pair. This effectively gives a
4495 choice of two registers to choose from, so that we a guaranteed to
4496 get at least one register which is different to the output
4497 register. This trick is taken from the alpha implementation. */
4499 picochip_secondary_reload (bool in_p
,
4500 rtx x ATTRIBUTE_UNUSED
,
4501 reg_class_t cla ATTRIBUTE_UNUSED
,
4502 enum machine_mode mode
,
4503 secondary_reload_info
*sri
)
4505 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4508 sri
->icode
= CODE_FOR_reload_outqi
;
4510 sri
->icode
= CODE_FOR_reload_inqi
;
4513 /* We dont need to return a register class type when we need only a
4514 scratch register. It realizes the scratch register type by looking
4515 at the instruction definition for sri->icode. We only need to
4516 return the register type when we need intermediaries for copies.*/
4520 /* Return true if the given memory operand can be aligned to a
4521 word+offset memory reference (e.g., FP+3 can be converted into the
4522 memory operand FP+2, with the offset 1). */
4524 picochip_alignable_memory_operand (rtx mem_operand
,
4525 enum machine_mode mode ATTRIBUTE_UNUSED
)
4529 /* Not a mem operand. Refuse immediately. */
4530 if (MEM
!= GET_CODE (mem_operand
))
4533 address
= XEXP (mem_operand
, 0);
4535 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4536 return ((PLUS
== GET_CODE (address
) &&
4537 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4538 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4539 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4540 || (REG
== GET_CODE (address
)
4541 && REGNO (address
) == STACK_POINTER_REGNUM
));
4545 /* Return true if the given memory reference is to a word aligned
4546 address. Currently this means it must be either SP, or
4547 SP+offset. We could replace this function with alignable
4548 memory references in the above function?. */
4550 picochip_word_aligned_memory_reference (rtx operand
)
4554 /* The address must be the SP register, or a constant, aligned
4555 offset from SP which doesn't exceed the FP+offset
4557 return ((PLUS
== GET_CODE (operand
)
4558 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4559 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4560 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4562 || (REG
== GET_CODE (operand
)
4563 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4567 /* Given an alignable memory location, convert the memory location
4568 into a HI mode access, storing the new memory reference in
4569 paligned_mem, and the number of bits by which to shift in pbitnum
4570 (i.e., given a reference to FP+3, this creates an aligned reference
4571 of FP+2, with an 8-bit shift). This code is a modification of that
4572 found in the Alpha port. */
4574 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4577 HOST_WIDE_INT offset
= 0;
4579 gcc_assert (GET_CODE (ref
) == MEM
);
4581 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4583 base
= find_replacement (&XEXP (ref
, 0));
4585 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4589 base
= XEXP (ref
, 0);
4592 if (GET_CODE (base
) == PLUS
)
4594 offset
+= INTVAL (XEXP (base
, 1));
4595 base
= XEXP (base
, 0);
4598 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4605 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4609 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4613 /* Return true if the given operand is an absolute address in memory
4614 (i.e., a symbolic offset). */
4616 picochip_absolute_memory_operand (rtx op
,
4617 enum machine_mode mode ATTRIBUTE_UNUSED
)
4620 if (MEM
== GET_CODE (op
))
4622 rtx address
= XEXP (op
, 0);
4624 /* Symbols are valid absolute addresses. */
4625 if (SYMBOL_REF
== GET_CODE (address
))
4628 /* Constant offsets to symbols are valid absolute addresses. */
4629 if (CONST
== GET_CODE (address
) &&
4630 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4631 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4632 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4639 /* Symbols are valid absolute addresses. */
4640 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4649 picochip_asm_named_section (const char *name
,
4650 unsigned int flags ATTRIBUTE_UNUSED
,
4651 tree decl ATTRIBUTE_UNUSED
)
4653 fprintf (asm_out_file
, ".section %s\n", name
);
4657 /* Check if we can make a conditional copy instruction. This is emitted as an
4658 instruction to set the condition register, followed by an instruction which
4659 uses the condition registers to perform the conditional move. */
4661 picochip_check_conditional_copy (rtx
* operands
)
4664 rtx branch_op_0
= XEXP (operands
[1], 0);
4665 rtx branch_op_1
= XEXP (operands
[1], 1);
4667 /* Only HI mode conditional moves are currently allowed. Can we add
4669 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4672 /* Is the comparison valid? Only allow operands which are registers
4673 if they are HImode. SI mode comparisons against 0 could be
4674 handled using logical operations (e.g., SIreg != 0 when low ||
4675 high). Need to find test cases to provoke this though (fixunssfdi
4676 in libgcc does, but is complicated). */
4677 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4678 GET_MODE(branch_op_0
) != HImode
)
4680 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4681 GET_MODE(branch_op_1
) != HImode
)
4690 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4694 addr
= arg_pointer_rtx
;
4696 addr
= plus_constant (Pmode
, stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4697 return gen_frame_mem (Pmode
, addr
);