gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003-2013 Free Software Foundation, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* Driver configuration.  */
  22
  23 /* A generic LIB_SPEC with -leval and --*group tacked on.  */
  24 #undef  LIB_SPEC
  25 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  26
  27 #undef STARTFILE_SPEC
  28 #undef ENDFILE_SPEC
  29
  30 #undef  LINK_SPEC
  31 #define LINK_SPEC "%{h*} %{v:-V} \
  32                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  33
  34 \f
  35 /* Run-time target specifications.  */
  36
  37 #define TARGET_CPU_CPP_BUILTINS()               \
  38   do                                            \
  39     {                                           \
  40       builtin_define ("__iq2000__");            \
  41       builtin_assert ("cpu=iq2000");            \
  42       builtin_assert ("machine=iq2000");        \
  43     }                                           \
  44   while (0)
  45
  46 /* Macros used in the machine description to test the flags.  */
  47
  48 #define TARGET_STATS            0
  49
  50 #define TARGET_DEBUG_MODE       0
  51 #define TARGET_DEBUG_A_MODE     0
  52 #define TARGET_DEBUG_B_MODE     0
  53 #define TARGET_DEBUG_C_MODE     0
  54 #define TARGET_DEBUG_D_MODE     0
  55
  56 #ifndef IQ2000_ISA_DEFAULT
  57 #define IQ2000_ISA_DEFAULT 1
  58 #endif
  59 \f
  60 /* Storage Layout.  */
  61
  62 #define BITS_BIG_ENDIAN                 0
  63 #define BYTES_BIG_ENDIAN                1
  64 #define WORDS_BIG_ENDIAN                1
  65 #define BITS_PER_WORD                   32
  66 #define MAX_BITS_PER_WORD               64
  67 #define UNITS_PER_WORD                  4
  68 #define MIN_UNITS_PER_WORD              4
  69 #define POINTER_SIZE                    32
  70
  71 /* Define this macro if it is advisable to hold scalars in registers
  72    in a wider mode than that declared by the program.  In such cases,
  73    the value is constrained to be within the bounds of the declared
  74    type, but kept valid in the wider mode.  The signedness of the
  75    extension may differ from that of the type.
  76
  77    We promote any value smaller than SImode up to SImode.  */
  78
  79 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  80   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  81       && GET_MODE_SIZE (MODE) < 4)              \
  82     (MODE) = SImode;
  83
  84 #define PARM_BOUNDARY 32
  85
  86 #define STACK_BOUNDARY 64
  87
  88 #define FUNCTION_BOUNDARY 32
  89
  90 #define BIGGEST_ALIGNMENT 64
  91
  92 #undef  DATA_ALIGNMENT
  93 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
  94   ((((ALIGN) < BITS_PER_WORD)                                           \
  95     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
  96         || TREE_CODE (TYPE) == UNION_TYPE                               \
  97         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
  98
  99 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 100   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 101    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 102
 103 #define EMPTY_FIELD_BOUNDARY 32
 104
 105 #define STRUCTURE_SIZE_BOUNDARY 8
 106
 107 #define STRICT_ALIGNMENT 1
 108
 109 #define PCC_BITFIELD_TYPE_MATTERS 1
 110
 111 \f
 112 /* Layout of Source Language Data Types.  */
 113
 114 #define INT_TYPE_SIZE           32
 115 #define SHORT_TYPE_SIZE         16
 116 #define LONG_TYPE_SIZE          32
 117 #define LONG_LONG_TYPE_SIZE     64
 118 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 119 #define FLOAT_TYPE_SIZE         32
 120 #define DOUBLE_TYPE_SIZE        64
 121 #define LONG_DOUBLE_TYPE_SIZE   64
 122 #define DEFAULT_SIGNED_CHAR     1
 123
 124 #undef  SIZE_TYPE
 125 #define SIZE_TYPE "unsigned int"
 126
 127 #undef  PTRDIFF_TYPE
 128 #define PTRDIFF_TYPE "int"
 129
 130 #undef  WCHAR_TYPE
 131 #define WCHAR_TYPE "long int"
 132
 133 #undef  WCHAR_TYPE_SIZE
 134 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 135
 136 \f
 137 /* Register Basics.  */
 138
 139 /* On the IQ2000, we have 32 integer registers.  */
 140 #define FIRST_PSEUDO_REGISTER 33
 141
 142 #define FIXED_REGISTERS                                                 \
 143 {                                                                       \
 144   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 145   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 146 }
 147
 148 #define CALL_USED_REGISTERS                                             \
 149 {                                                                       \
 150   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 151   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 152 }
 153
 154 \f
 155 /* Order of allocation of registers.  */
 156
 157 #define REG_ALLOC_ORDER                                                 \
 158 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 159   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 160 }
 161
 162 \f
 163 /* How Values Fit in Registers.  */
 164
 165 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 166   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 167
 168 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 169  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 170   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 171   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 172
 173 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 174   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 175     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 176    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 177        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 178
 179 #define AVOID_CCMODE_COPIES
 180
 181 \f
 182 /* Register Classes.  */
 183
 184 enum reg_class
 185 {
 186   NO_REGS,                      /* No registers in set.  */
 187   GR_REGS,                      /* Integer registers.  */
 188   ALL_REGS,                     /* All registers.  */
 189   LIM_REG_CLASSES               /* Max value + 1.  */
 190 };
 191
 192 #define GENERAL_REGS GR_REGS
 193
 194 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 195
 196 #define REG_CLASS_NAMES                                         \
 197 {                                                               \
 198   "NO_REGS",                                                    \
 199   "GR_REGS",                                                    \
 200   "ALL_REGS"                                                    \
 201 }
 202
 203 #define REG_CLASS_CONTENTS                                      \
 204 {                                                               \
 205   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 206   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 207   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 208 }
 209
 210 #define REGNO_REG_CLASS(REGNO) \
 211 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 212
 213 #define BASE_REG_CLASS  (GR_REGS)
 214
 215 #define INDEX_REG_CLASS NO_REGS
 216
 217 #define REGNO_OK_FOR_INDEX_P(regno)     0
 218
 219 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 220   ((CLASS) != ALL_REGS                                          \
 221    ? (CLASS)                                                    \
 222    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 223        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 224       ? (GR_REGS)                                               \
 225       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 226           || GET_MODE (X) == VOIDmode)                          \
 227          ? (GR_REGS)                                            \
 228          : (CLASS))))
 229
 230 \f
 231 /* Basic Stack Layout.  */
 232
 233 #define STACK_GROWS_DOWNWARD
 234
 235 #define FRAME_GROWS_DOWNWARD 0
 236
 237 #define STARTING_FRAME_OFFSET                                           \
 238   (crtl->outgoing_args_size)
 239
 240 /* Use the default value zero.  */
 241 /* #define STACK_POINTER_OFFSET 0 */
 242
 243 #define FIRST_PARM_OFFSET(FNDECL) 0
 244
 245 /* The return address for the current frame is in r31 if this is a leaf
 246    function.  Otherwise, it is on the stack.  It is at a variable offset
 247    from sp/fp/ap, so we define a fake hard register rap which is a
 248    pointer to the return address on the stack.  This always gets eliminated
 249    during reload to be either the frame pointer or the stack pointer plus
 250    an offset.  */
 251
 252 #define RETURN_ADDR_RTX(count, frame)                                   \
 253   (((count) == 0)                                                       \
 254    ? (leaf_function_p ()                                                \
 255       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 256       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 257                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 258     : (rtx) 0)
 259
 260 /* Before the prologue, RA lives in r31.  */
 261 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 262
 263 \f
 264 /* Register That Address the Stack Frame.  */
 265
 266 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 267 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 268 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 269 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 270 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 271 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 272
 273 \f
 274 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 275
 276 #define ELIMINABLE_REGS                                                 \
 277 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 278  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 279  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 280  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 281  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 282  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 283  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 284
 285 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 286         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 287 \f
 288 /* Passing Function Arguments on the Stack.  */
 289
 290 /* #define PUSH_ROUNDING(BYTES) 0 */
 291
 292 #define ACCUMULATE_OUTGOING_ARGS 1
 293
 294 #define REG_PARM_STACK_SPACE(FNDECL) 0
 295
 296 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 297
 298 \f
 299 /* Function Arguments in Registers.  */
 300
 301 #define MAX_ARGS_IN_REGISTERS 8
 302
 303 typedef struct iq2000_args
 304 {
 305   int gp_reg_found;             /* Whether a gp register was found yet.  */
 306   unsigned int arg_number;      /* Argument number.  */
 307   unsigned int arg_words;       /* # total words the arguments take.  */
 308   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 309   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 310   int fp_code;                  /* Mode of FP arguments.  */
 311   unsigned int num_adjusts;     /* Number of adjustments made.  */
 312                                 /* Adjustments made to args pass in regs.  */
 313   rtx adjust[MAX_ARGS_IN_REGISTERS * 2];
 314 } CUMULATIVE_ARGS;
 315
 316 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 317    for a call to a function whose data type is FNTYPE.
 318    For a library call, FNTYPE is 0.  */
 319 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 320   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 321
 322 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 323   (! BYTES_BIG_ENDIAN                                                   \
 324    ? upward                                                             \
 325    : (((MODE) == BLKmode                                                \
 326        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 327           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 328        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 329           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 330       ? downward : upward))
 331
 332 #define FUNCTION_ARG_REGNO_P(N)                                         \
 333   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 334
 335 \f
 336 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 337
 338 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N)
 339
 340 \f
 341 /* How Large Values are Returned.  */
 342
 343 #define DEFAULT_PCC_STRUCT_RETURN 0
 344 \f
 345 /* Function Entry and Exit.  */
 346
 347 #define EXIT_IGNORE_STACK 1
 348
 349 \f
 350 /* Generating Code for Profiling.  */
 351
 352 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 353 {                                                                       \
 354   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 355   fprintf (FILE, "\t.set\tnoat\n");                                     \
 356   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 357            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 358   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 359   fprintf (FILE,                                                        \
 360            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 361            "subu",                                                      \
 362            reg_names[STACK_POINTER_REGNUM],                             \
 363            reg_names[STACK_POINTER_REGNUM],                             \
 364            Pmode == DImode ? 16 : 8);                                   \
 365   fprintf (FILE, "\t.set\treorder\n");                                  \
 366   fprintf (FILE, "\t.set\tat\n");                                       \
 367 }
 368
 369 \f
 370 /* Trampolines for Nested Functions.  */
 371
 372 #define TRAMPOLINE_CODE_SIZE  (8*4)
 373 #define TRAMPOLINE_SIZE       (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode))
 374 #define TRAMPOLINE_ALIGNMENT  GET_MODE_ALIGNMENT (Pmode)
 375
 376 \f
 377 /* Addressing Modes.  */
 378
 379 #define CONSTANT_ADDRESS_P(X)                                           \
 380   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 381     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 382     || (GET_CODE (X) == CONST)))
 383
 384 #define MAX_REGS_PER_ADDRESS 1
 385
 386 #define REG_OK_FOR_INDEX_P(X) 0
 387
 388 \f
 389 /* Describing Relative Costs of Operations.  */
 390
 391 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 392
 393 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 394   (TO_P ? 2 : 16)
 395
 396 #define BRANCH_COST(speed_p, predictable_p) 2
 397
 398 #define SLOW_BYTE_ACCESS 1
 399
 400 #define NO_FUNCTION_CSE 1
 401
 402 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 403   if (REG_NOTE_KIND (LINK) != 0)                                        \
 404     (COST) = 0; /* Anti or output dependence.  */
 405
 406 \f
 407 /* Dividing the output into sections.  */
 408
 409 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 410
 411 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 412
 413 \f
 414 /* The Overall Framework of an Assembler File.  */
 415
 416 #define ASM_COMMENT_START " #"
 417
 418 #define ASM_APP_ON "#APP\n"
 419
 420 #define ASM_APP_OFF "#NO_APP\n"
 421
 422 \f
 423 /* Output and Generation of Labels.  */
 424
 425 #undef ASM_GENERATE_INTERNAL_LABEL
 426 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 427   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 428
 429 #define GLOBAL_ASM_OP "\t.globl\t"
 430
 431 \f
 432 /* Output of Assembler Instructions.  */
 433
 434 #define REGISTER_NAMES                                                  \
 435 {                                                                       \
 436  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 437  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 438  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 439  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 440 }
 441
 442 #define ADDITIONAL_REGISTER_NAMES                                       \
 443 {                                                                       \
 444   { "%0",        0 + GP_REG_FIRST },                                    \
 445   { "%1",        1 + GP_REG_FIRST },                                    \
 446   { "%2",        2 + GP_REG_FIRST },                                    \
 447   { "%3",        3 + GP_REG_FIRST },                                    \
 448   { "%4",        4 + GP_REG_FIRST },                                    \
 449   { "%5",        5 + GP_REG_FIRST },                                    \
 450   { "%6",        6 + GP_REG_FIRST },                                    \
 451   { "%7",        7 + GP_REG_FIRST },                                    \
 452   { "%8",        8 + GP_REG_FIRST },                                    \
 453   { "%9",        9 + GP_REG_FIRST },                                    \
 454   { "%10",      10 + GP_REG_FIRST },                                    \
 455   { "%11",      11 + GP_REG_FIRST },                                    \
 456   { "%12",      12 + GP_REG_FIRST },                                    \
 457   { "%13",      13 + GP_REG_FIRST },                                    \
 458   { "%14",      14 + GP_REG_FIRST },                                    \
 459   { "%15",      15 + GP_REG_FIRST },                                    \
 460   { "%16",      16 + GP_REG_FIRST },                                    \
 461   { "%17",      17 + GP_REG_FIRST },                                    \
 462   { "%18",      18 + GP_REG_FIRST },                                    \
 463   { "%19",      19 + GP_REG_FIRST },                                    \
 464   { "%20",      20 + GP_REG_FIRST },                                    \
 465   { "%21",      21 + GP_REG_FIRST },                                    \
 466   { "%22",      22 + GP_REG_FIRST },                                    \
 467   { "%23",      23 + GP_REG_FIRST },                                    \
 468   { "%24",      24 + GP_REG_FIRST },                                    \
 469   { "%25",      25 + GP_REG_FIRST },                                    \
 470   { "%26",      26 + GP_REG_FIRST },                                    \
 471   { "%27",      27 + GP_REG_FIRST },                                    \
 472   { "%28",      28 + GP_REG_FIRST },                                    \
 473   { "%29",      29 + GP_REG_FIRST },                                    \
 474   { "%30",      27 + GP_REG_FIRST },                                    \
 475   { "%31",      31 + GP_REG_FIRST },                                    \
 476   { "%rap",     32 + GP_REG_FIRST },                                    \
 477 }
 478
 479 /* Check if the current insn needs a nop in front of it
 480    because of load delays, and also update the delay slot statistics.  */
 481
 482 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 483   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 484
 485 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 486 do                                                                      \
 487   {                                                                     \
 488     fputs ("\n", STREAM);                                               \
 489   }                                                                     \
 490 while (0)
 491
 492 #define LOCAL_LABEL_PREFIX      "$"
 493
 494 #define USER_LABEL_PREFIX       ""
 495
 496 \f
 497 /* Output of dispatch tables.  */
 498
 499 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 500   do                                                                    \
 501     {                                                                   \
 502       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 503                Pmode == DImode ? ".dword" : ".word",                    \
 504                LOCAL_LABEL_PREFIX, VALUE);                              \
 505     }                                                                   \
 506   while (0)
 507
 508 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 509   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 510            Pmode == DImode ? ".dword" : ".word",                        \
 511            LOCAL_LABEL_PREFIX,                                          \
 512            VALUE)
 513
 514 \f
 515 /* Assembler Commands for Alignment.  */
 516
 517 #undef ASM_OUTPUT_SKIP
 518 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 519   fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",      \
 520            (unsigned HOST_WIDE_INT)(SIZE))
 521
 522 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 523   if ((LOG) != 0)                                                       \
 524     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 525
 526 \f
 527 /* Macros Affecting all Debug Formats.  */
 528
 529 #define DEBUGGER_AUTO_OFFSET(X)  \
 530   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 531
 532 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 533   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 534
 535 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 536
 537 #define DWARF2_DEBUGGING_INFO 1
 538
 539 \f
 540 /* Miscellaneous Parameters.  */
 541
 542 #define CASE_VECTOR_MODE SImode
 543
 544 #define WORD_REGISTER_OPERATIONS
 545
 546 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 547
 548 #define MOVE_MAX 4
 549
 550 #define MAX_MOVE_MAX 8
 551
 552 #define SHIFT_COUNT_TRUNCATED 1
 553
 554 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 555
 556 #define STORE_FLAG_VALUE 1
 557
 558 #define Pmode SImode
 559
 560 #define FUNCTION_MODE SImode
 561
 562 /* IQ2000 external variables defined in iq2000.c.  */
 563
 564 /* Comparison type.  */
 565 enum cmp_type
 566 {
 567   CMP_SI,                               /* Compare four byte integers.  */
 568   CMP_DI,                               /* Compare eight byte integers.  */
 569   CMP_SF,                               /* Compare single precision floats.  */
 570   CMP_DF,                               /* Compare double precision floats.  */
 571   CMP_MAX                               /* Max comparison type.  */
 572 };
 573
 574 /* Types of delay slot.  */
 575 enum delay_type
 576 {
 577   DELAY_NONE,                           /* No delay slot.  */
 578   DELAY_LOAD,                           /* Load from memory delay.  */
 579   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 580 };
 581
 582 /* Recast the cpu class to be the cpu attribute.  */
 583 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 584
 585 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 586 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 587
 588 \f
 589 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 590
 591 /* Macros to decide whether certain features are available or not,
 592    depending on the instruction set architecture level.  */
 593
 594 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 595
 596 /* ISA has branch likely instructions.  */
 597 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 598
 599 \f
 600 #undef ASM_SPEC
 601
 602 \f
 603 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 604 #define DWARF_FRAME_REGNUM(REG)        (REG)
 605
 606 /* The DWARF 2 CFA column which tracks the return address.  */
 607 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 608
 609 /* Describe how we implement __builtin_eh_return.  */
 610 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 611
 612 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 613    location used to store the amount to adjust the stack.  This is
 614    usually a register that is available from end of the function's body
 615    to the end of the epilogue. Thus, this cannot be a register used as a
 616    temporary by the epilogue.
 617
 618    This must be an integer register.  */
 619 #define EH_RETURN_STACKADJ_REGNO        3
 620 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 621
 622 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 623    location used to store the address the processor should jump to
 624    catch exception.  This is usually a registers that is available from
 625    end of the function's body to the end of the epilogue. Thus, this
 626    cannot be a register used as a temporary by the epilogue.
 627
 628    This must be an address register.  */
 629 #define EH_RETURN_HANDLER_REGNO         26
 630 #define EH_RETURN_HANDLER_RTX           \
 631         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 632
 633 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 634 #define DWARF_CIE_DATA_ALIGNMENT 4
 635
 636 /* For IQ2000, width of a floating point register.  */
 637 #define UNITS_PER_FPREG 4
 638
 639 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 640
 641 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 642
 643 /* Internal macros to classify a register number as to whether it's a
 644    general purpose register, a floating point register, a
 645    multiply/divide register, or a status register.  */
 646
 647 #define GP_REG_FIRST 0
 648 #define GP_REG_LAST  31
 649 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 650
 651 #define RAP_REG_NUM   32
 652 #define AT_REGNUM       (GP_REG_FIRST + 1)
 653
 654 #define GP_REG_P(REGNO) \
 655   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 656
 657 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 658    is larger than 32K bytes.  These registers must come from the
 659    scratch register set, and not used for passing and returning
 660    arguments and any other information used in the calling sequence.  */
 661
 662 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 663 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 664
 665 /* This macro is used later on in the file.  */
 666 #define GR_REG_CLASS_P(CLASS)                                           \
 667   ((CLASS) == GR_REGS)
 668
 669 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 670 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 671
 672 /* Certain machines have the property that some registers cannot be
 673    copied to some other registers without using memory.  Define this
 674    macro on those machines to be a C expression that is nonzero if
 675    objects of mode MODE in registers of CLASS1 can only be copied to
 676    registers of class CLASS2 by storing a register of CLASS1 into
 677    memory and loading that memory location into a register of CLASS2.
 678
 679    Do not define this macro if its value would always be zero.  */
 680
 681 /* Return the maximum number of consecutive registers
 682    needed to represent mode MODE in a register of class CLASS.  */
 683
 684 #define CLASS_UNITS(mode, size)                                         \
 685   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
 686
 687 /* If defined, gives a class of registers that cannot be used as the
 688    operand of a SUBREG that changes the mode of the object illegally.  */
 689
 690 #define CLASS_CANNOT_CHANGE_MODE 0
 691
 692 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
 693
 694 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
 695   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 696
 697 /* Make sure 4 words are always allocated on the stack.  */
 698
 699 #ifndef STACK_ARGS_ADJUST
 700 #define STACK_ARGS_ADJUST(SIZE)                                         \
 701   {                                                                     \
 702     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
 703       SIZE.constant = 4 * UNITS_PER_WORD;                               \
 704   }
 705 #endif
 706
 707 \f
 708 /* Symbolic macros for the registers used to return integer and floating
 709    point values.  */
 710
 711 #define GP_RETURN (GP_REG_FIRST + 2)
 712
 713 /* Symbolic macros for the first/last argument registers.  */
 714
 715 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
 716 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
 717
 718 #define MAX_ARGS_IN_REGISTERS   8
 719
 720 \f
 721 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
 722
 723 #define MUST_SAVE_REGISTER(regno) \
 724   ((df_regs_ever_live_p (regno) && !call_used_regs[regno])              \
 725   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
 726    || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
 727
 728 /* ALIGN FRAMES on double word boundaries */
 729 #ifndef IQ2000_STACK_ALIGN
 730 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
 731 #endif
 732
 733 \f
 734 /* These assume that REGNO is a hard or pseudo reg number.
 735    They give nonzero only if REGNO is a hard reg of the suitable class
 736    or a pseudo reg currently allocated to a suitable hard reg.
 737    These definitions are NOT overridden anywhere.  */
 738
 739 #define BASE_REG_P(regno, mode)                                 \
 740   (GP_REG_P (regno))
 741
 742 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
 743   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
 744              (mode))
 745
 746 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
 747   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
 748
 749 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
 750   GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode))
 751
 752 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 753    and check its validity for a certain class.
 754    We have two alternate definitions for each of them.
 755    The usual definition accepts all pseudo regs; the other rejects them all.
 756    The symbol REG_OK_STRICT causes the latter definition to be used.
 757
 758    Most source files want to accept pseudo regs in the hope that
 759    they will get allocated to the class that the insn wants them to be in.
 760    Some source files that are used after register allocation
 761    need to be strict.  */
 762
 763 #ifndef REG_OK_STRICT
 764 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 765   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
 766 #else
 767 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 768   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
 769 #endif
 770
 771 #if 1
 772 #define GO_PRINTF(x)    fprintf (stderr, (x))
 773 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
 774 #define GO_DEBUG_RTX(x) debug_rtx (x)
 775
 776 #else
 777 #define GO_PRINTF(x)
 778 #define GO_PRINTF2(x,y)
 779 #define GO_DEBUG_RTX(x)
 780 #endif
 781
 782 /* If defined, modifies the length assigned to instruction INSN as a
 783    function of the context in which it is used.  LENGTH is an lvalue
 784    that contains the initially computed length of the insn and should
 785    be updated with the correct length of the insn.  */
 786 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
 787   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
 788
 789 \f
 790
 791
 792 /* How to tell the debugger about changes of source files.  */
 793
 794 #ifndef SET_FILE_NUMBER
 795 #define SET_FILE_NUMBER() ++ num_source_filenames
 796 #endif
 797
 798 /* This is how to output a note the debugger telling it the line number
 799    to which the following sequence of instructions corresponds.  */
 800
 801 #ifndef LABEL_AFTER_LOC
 802 #define LABEL_AFTER_LOC(STREAM)
 803 #endif
 804
 805 \f
 806 /* Default to -G 8 */
 807 #ifndef IQ2000_DEFAULT_GVALUE
 808 #define IQ2000_DEFAULT_GVALUE 8
 809 #endif
 810
 811 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
 812
 813 \f
 814 /* Which instruction set architecture to use.  */
 815 extern int iq2000_isa;
 816
 817 enum iq2000_builtins
 818 {
 819   IQ2000_BUILTIN_ADO16,
 820   IQ2000_BUILTIN_CFC0,
 821   IQ2000_BUILTIN_CFC1,
 822   IQ2000_BUILTIN_CFC2,
 823   IQ2000_BUILTIN_CFC3,
 824   IQ2000_BUILTIN_CHKHDR,
 825   IQ2000_BUILTIN_CTC0,
 826   IQ2000_BUILTIN_CTC1,
 827   IQ2000_BUILTIN_CTC2,
 828   IQ2000_BUILTIN_CTC3,
 829   IQ2000_BUILTIN_LU,
 830   IQ2000_BUILTIN_LUC32L,
 831   IQ2000_BUILTIN_LUC64,
 832   IQ2000_BUILTIN_LUC64L,
 833   IQ2000_BUILTIN_LUK,
 834   IQ2000_BUILTIN_LULCK,
 835   IQ2000_BUILTIN_LUM32,
 836   IQ2000_BUILTIN_LUM32L,
 837   IQ2000_BUILTIN_LUM64,
 838   IQ2000_BUILTIN_LUM64L,
 839   IQ2000_BUILTIN_LUR,
 840   IQ2000_BUILTIN_LURL,
 841   IQ2000_BUILTIN_MFC0,
 842   IQ2000_BUILTIN_MFC1,
 843   IQ2000_BUILTIN_MFC2,
 844   IQ2000_BUILTIN_MFC3,
 845   IQ2000_BUILTIN_MRGB,
 846   IQ2000_BUILTIN_MTC0,
 847   IQ2000_BUILTIN_MTC1,
 848   IQ2000_BUILTIN_MTC2,
 849   IQ2000_BUILTIN_MTC3,
 850   IQ2000_BUILTIN_PKRL,
 851   IQ2000_BUILTIN_RAM,
 852   IQ2000_BUILTIN_RB,
 853   IQ2000_BUILTIN_RX,
 854   IQ2000_BUILTIN_SRRD,
 855   IQ2000_BUILTIN_SRRDL,
 856   IQ2000_BUILTIN_SRULC,
 857   IQ2000_BUILTIN_SRULCK,
 858   IQ2000_BUILTIN_SRWR,
 859   IQ2000_BUILTIN_SRWRU,
 860   IQ2000_BUILTIN_TRAPQF,
 861   IQ2000_BUILTIN_TRAPQFL,
 862   IQ2000_BUILTIN_TRAPQN,
 863   IQ2000_BUILTIN_TRAPQNE,
 864   IQ2000_BUILTIN_TRAPRE,
 865   IQ2000_BUILTIN_TRAPREL,
 866   IQ2000_BUILTIN_WB,
 867   IQ2000_BUILTIN_WBR,
 868   IQ2000_BUILTIN_WBU,
 869   IQ2000_BUILTIN_WX,
 870   IQ2000_BUILTIN_SYSCALL
 871 };