1 /* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
33 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
35 #include "addresses.h"
38 /* Forward declarations */
39 static void set_of_1 (rtx
, const_rtx
, void *);
40 static bool covers_regno_p (const_rtx
, unsigned int);
41 static bool covers_regno_no_parallel_p (const_rtx
, unsigned int);
42 static int computed_jump_p_1 (const_rtx
);
43 static void parms_set (rtx
, const_rtx
, void *);
45 static unsigned HOST_WIDE_INT
cached_nonzero_bits (const_rtx
, machine_mode
,
46 const_rtx
, machine_mode
,
47 unsigned HOST_WIDE_INT
);
48 static unsigned HOST_WIDE_INT
nonzero_bits1 (const_rtx
, machine_mode
,
49 const_rtx
, machine_mode
,
50 unsigned HOST_WIDE_INT
);
51 static unsigned int cached_num_sign_bit_copies (const_rtx
, machine_mode
, const_rtx
,
54 static unsigned int num_sign_bit_copies1 (const_rtx
, machine_mode
, const_rtx
,
55 machine_mode
, unsigned int);
57 rtx_subrtx_bound_info rtx_all_subrtx_bounds
[NUM_RTX_CODE
];
58 rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds
[NUM_RTX_CODE
];
60 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
61 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
62 SIGN_EXTEND then while narrowing we also have to enforce the
63 representation and sign-extend the value to mode DESTINATION_REP.
65 If the value is already sign-extended to DESTINATION_REP mode we
66 can just switch to DESTINATION mode on it. For each pair of
67 integral modes SOURCE and DESTINATION, when truncating from SOURCE
68 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
69 contains the number of high-order bits in SOURCE that have to be
70 copies of the sign-bit so that we can do this mode-switch to
74 num_sign_bit_copies_in_rep
[MAX_MODE_INT
+ 1][MAX_MODE_INT
+ 1];
76 /* Store X into index I of ARRAY. ARRAY is known to have at least I
77 elements. Return the new base of ARRAY. */
80 typename
T::value_type
*
81 generic_subrtx_iterator
<T
>::add_single_to_queue (array_type
&array
,
83 size_t i
, value_type x
)
85 if (base
== array
.stack
)
92 gcc_checking_assert (i
== LOCAL_ELEMS
);
93 /* A previous iteration might also have moved from the stack to the
94 heap, in which case the heap array will already be big enough. */
95 if (vec_safe_length (array
.heap
) <= i
)
96 vec_safe_grow (array
.heap
, i
+ 1);
97 base
= array
.heap
->address ();
98 memcpy (base
, array
.stack
, sizeof (array
.stack
));
99 base
[LOCAL_ELEMS
] = x
;
102 unsigned int length
= array
.heap
->length ();
105 gcc_checking_assert (base
== array
.heap
->address ());
111 gcc_checking_assert (i
== length
);
112 vec_safe_push (array
.heap
, x
);
113 return array
.heap
->address ();
117 /* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
118 number of elements added to the worklist. */
120 template <typename T
>
122 generic_subrtx_iterator
<T
>::add_subrtxes_to_queue (array_type
&array
,
124 size_t end
, rtx_type x
)
126 enum rtx_code code
= GET_CODE (x
);
127 const char *format
= GET_RTX_FORMAT (code
);
128 size_t orig_end
= end
;
129 if (__builtin_expect (INSN_P (x
), false))
131 /* Put the pattern at the top of the queue, since that's what
132 we're likely to want most. It also allows for the SEQUENCE
134 for (int i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; --i
)
135 if (format
[i
] == 'e')
137 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
138 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
141 base
= add_single_to_queue (array
, base
, end
++, subx
);
145 for (int i
= 0; format
[i
]; ++i
)
146 if (format
[i
] == 'e')
148 value_type subx
= T::get_value (x
->u
.fld
[i
].rt_rtx
);
149 if (__builtin_expect (end
< LOCAL_ELEMS
, true))
152 base
= add_single_to_queue (array
, base
, end
++, subx
);
154 else if (format
[i
] == 'E')
156 unsigned int length
= GET_NUM_ELEM (x
->u
.fld
[i
].rt_rtvec
);
157 rtx
*vec
= x
->u
.fld
[i
].rt_rtvec
->elem
;
158 if (__builtin_expect (end
+ length
<= LOCAL_ELEMS
, true))
159 for (unsigned int j
= 0; j
< length
; j
++)
160 base
[end
++] = T::get_value (vec
[j
]);
162 for (unsigned int j
= 0; j
< length
; j
++)
163 base
= add_single_to_queue (array
, base
, end
++,
164 T::get_value (vec
[j
]));
165 if (code
== SEQUENCE
&& end
== length
)
166 /* If the subrtxes of the sequence fill the entire array then
167 we know that no other parts of a containing insn are queued.
168 The caller is therefore iterating over the sequence as a
169 PATTERN (...), so we also want the patterns of the
171 for (unsigned int j
= 0; j
< length
; j
++)
173 typename
T::rtx_type x
= T::get_rtx (base
[j
]);
175 base
[j
] = T::get_value (PATTERN (x
));
178 return end
- orig_end
;
181 template <typename T
>
183 generic_subrtx_iterator
<T
>::free_array (array_type
&array
)
185 vec_free (array
.heap
);
188 template <typename T
>
189 const size_t generic_subrtx_iterator
<T
>::LOCAL_ELEMS
;
191 template class generic_subrtx_iterator
<const_rtx_accessor
>;
192 template class generic_subrtx_iterator
<rtx_var_accessor
>;
193 template class generic_subrtx_iterator
<rtx_ptr_accessor
>;
195 /* Return 1 if the value of X is unstable
196 (would be different at a different point in the program).
197 The frame pointer, arg pointer, etc. are considered stable
198 (within one function) and so is anything marked `unchanging'. */
201 rtx_unstable_p (const_rtx x
)
203 const RTX_CODE code
= GET_CODE (x
);
210 return !MEM_READONLY_P (x
) || rtx_unstable_p (XEXP (x
, 0));
219 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
220 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
221 /* The arg pointer varies if it is not a fixed register. */
222 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
224 /* ??? When call-clobbered, the value is stable modulo the restore
225 that must happen after a call. This currently screws up local-alloc
226 into believing that the restore is not needed. */
227 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
&& x
== pic_offset_table_rtx
)
232 if (MEM_VOLATILE_P (x
))
241 fmt
= GET_RTX_FORMAT (code
);
242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
245 if (rtx_unstable_p (XEXP (x
, i
)))
248 else if (fmt
[i
] == 'E')
251 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
252 if (rtx_unstable_p (XVECEXP (x
, i
, j
)))
259 /* Return 1 if X has a value that can vary even between two
260 executions of the program. 0 means X can be compared reliably
261 against certain constants or near-constants.
262 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
263 zero, we are slightly more conservative.
264 The frame pointer and the arg pointer are considered constant. */
267 rtx_varies_p (const_rtx x
, bool for_alias
)
280 return !MEM_READONLY_P (x
) || rtx_varies_p (XEXP (x
, 0), for_alias
);
289 /* Note that we have to test for the actual rtx used for the frame
290 and arg pointers and not just the register number in case we have
291 eliminated the frame and/or arg pointer and are using it
293 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
294 /* The arg pointer varies if it is not a fixed register. */
295 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
297 if (x
== pic_offset_table_rtx
298 /* ??? When call-clobbered, the value is stable modulo the restore
299 that must happen after a call. This currently screws up
300 local-alloc into believing that the restore is not needed, so we
301 must return 0 only if we are called from alias analysis. */
302 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
|| for_alias
))
307 /* The operand 0 of a LO_SUM is considered constant
308 (in fact it is related specifically to operand 1)
309 during alias analysis. */
310 return (! for_alias
&& rtx_varies_p (XEXP (x
, 0), for_alias
))
311 || rtx_varies_p (XEXP (x
, 1), for_alias
);
314 if (MEM_VOLATILE_P (x
))
323 fmt
= GET_RTX_FORMAT (code
);
324 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
327 if (rtx_varies_p (XEXP (x
, i
), for_alias
))
330 else if (fmt
[i
] == 'E')
333 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
334 if (rtx_varies_p (XVECEXP (x
, i
, j
), for_alias
))
341 /* Compute an approximation for the offset between the register
342 FROM and TO for the current function, as it was at the start
346 get_initial_register_offset (int from
, int to
)
348 static const struct elim_table_t
352 } table
[] = ELIMINABLE_REGS
;
353 HOST_WIDE_INT offset1
, offset2
;
359 /* It is not safe to call INITIAL_ELIMINATION_OFFSET
360 before the reload pass. We need to give at least
361 an estimation for the resulting frame size. */
362 if (! reload_completed
)
364 offset1
= crtl
->outgoing_args_size
+ get_frame_size ();
365 #if !STACK_GROWS_DOWNWARD
368 if (to
== STACK_POINTER_REGNUM
)
370 else if (from
== STACK_POINTER_REGNUM
)
376 for (i
= 0; i
< ARRAY_SIZE (table
); i
++)
377 if (table
[i
].from
== from
)
379 if (table
[i
].to
== to
)
381 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
385 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
387 if (table
[j
].to
== to
388 && table
[j
].from
== table
[i
].to
)
390 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
392 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
394 return offset1
+ offset2
;
396 if (table
[j
].from
== to
397 && table
[j
].to
== table
[i
].to
)
399 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
401 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
403 return offset1
- offset2
;
407 else if (table
[i
].to
== from
)
409 if (table
[i
].from
== to
)
411 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
415 for (j
= 0; j
< ARRAY_SIZE (table
); j
++)
417 if (table
[j
].to
== to
418 && table
[j
].from
== table
[i
].from
)
420 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
422 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
424 return - offset1
+ offset2
;
426 if (table
[j
].from
== to
427 && table
[j
].to
== table
[i
].from
)
429 INITIAL_ELIMINATION_OFFSET (table
[i
].from
, table
[i
].to
,
431 INITIAL_ELIMINATION_OFFSET (table
[j
].from
, table
[j
].to
,
433 return - offset1
- offset2
;
438 /* If the requested register combination was not found,
439 try a different more simple combination. */
440 if (from
== ARG_POINTER_REGNUM
)
441 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM
, to
);
442 else if (to
== ARG_POINTER_REGNUM
)
443 return get_initial_register_offset (from
, HARD_FRAME_POINTER_REGNUM
);
444 else if (from
== HARD_FRAME_POINTER_REGNUM
)
445 return get_initial_register_offset (FRAME_POINTER_REGNUM
, to
);
446 else if (to
== HARD_FRAME_POINTER_REGNUM
)
447 return get_initial_register_offset (from
, FRAME_POINTER_REGNUM
);
452 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
453 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
454 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
455 references on strict alignment machines. */
458 rtx_addr_can_trap_p_1 (const_rtx x
, HOST_WIDE_INT offset
, HOST_WIDE_INT size
,
459 machine_mode mode
, bool unaligned_mems
)
461 enum rtx_code code
= GET_CODE (x
);
463 /* The offset must be a multiple of the mode size if we are considering
464 unaligned memory references on strict alignment machines. */
465 if (STRICT_ALIGNMENT
&& unaligned_mems
&& GET_MODE_SIZE (mode
) != 0)
467 HOST_WIDE_INT actual_offset
= offset
;
469 #ifdef SPARC_STACK_BOUNDARY_HACK
470 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
471 the real alignment of %sp. However, when it does this, the
472 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
473 if (SPARC_STACK_BOUNDARY_HACK
474 && (x
== stack_pointer_rtx
|| x
== hard_frame_pointer_rtx
))
475 actual_offset
-= STACK_POINTER_OFFSET
;
478 if (actual_offset
% GET_MODE_SIZE (mode
) != 0)
485 if (SYMBOL_REF_WEAK (x
))
487 if (!CONSTANT_POOL_ADDRESS_P (x
))
490 HOST_WIDE_INT decl_size
;
495 size
= GET_MODE_SIZE (mode
);
499 /* If the size of the access or of the symbol is unknown,
501 decl
= SYMBOL_REF_DECL (x
);
503 /* Else check that the access is in bounds. TODO: restructure
504 expr_size/tree_expr_size/int_expr_size and just use the latter. */
507 else if (DECL_P (decl
) && DECL_SIZE_UNIT (decl
))
508 decl_size
= (tree_fits_shwi_p (DECL_SIZE_UNIT (decl
))
509 ? tree_to_shwi (DECL_SIZE_UNIT (decl
))
511 else if (TREE_CODE (decl
) == STRING_CST
)
512 decl_size
= TREE_STRING_LENGTH (decl
);
513 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl
)))
514 decl_size
= int_size_in_bytes (TREE_TYPE (decl
));
518 return (decl_size
<= 0 ? offset
!= 0 : offset
+ size
> decl_size
);
527 /* Stack references are assumed not to trap, but we need to deal with
528 nonsensical offsets. */
529 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
530 || x
== stack_pointer_rtx
531 /* The arg pointer varies if it is not a fixed register. */
532 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
535 HOST_WIDE_INT red_zone_size
= RED_ZONE_SIZE
;
537 HOST_WIDE_INT red_zone_size
= 0;
539 HOST_WIDE_INT stack_boundary
= PREFERRED_STACK_BOUNDARY
541 HOST_WIDE_INT low_bound
, high_bound
;
544 size
= GET_MODE_SIZE (mode
);
546 if (x
== frame_pointer_rtx
)
548 if (FRAME_GROWS_DOWNWARD
)
550 high_bound
= STARTING_FRAME_OFFSET
;
551 low_bound
= high_bound
- get_frame_size ();
555 low_bound
= STARTING_FRAME_OFFSET
;
556 high_bound
= low_bound
+ get_frame_size ();
559 else if (x
== hard_frame_pointer_rtx
)
561 HOST_WIDE_INT sp_offset
562 = get_initial_register_offset (STACK_POINTER_REGNUM
,
563 HARD_FRAME_POINTER_REGNUM
);
564 HOST_WIDE_INT ap_offset
565 = get_initial_register_offset (ARG_POINTER_REGNUM
,
566 HARD_FRAME_POINTER_REGNUM
);
568 #if STACK_GROWS_DOWNWARD
569 low_bound
= sp_offset
- red_zone_size
- stack_boundary
;
570 high_bound
= ap_offset
571 + FIRST_PARM_OFFSET (current_function_decl
)
572 #if !ARGS_GROW_DOWNWARD
577 high_bound
= sp_offset
+ red_zone_size
+ stack_boundary
;
578 low_bound
= ap_offset
579 + FIRST_PARM_OFFSET (current_function_decl
)
580 #if ARGS_GROW_DOWNWARD
586 else if (x
== stack_pointer_rtx
)
588 HOST_WIDE_INT ap_offset
589 = get_initial_register_offset (ARG_POINTER_REGNUM
,
590 STACK_POINTER_REGNUM
);
592 #if STACK_GROWS_DOWNWARD
593 low_bound
= - red_zone_size
- stack_boundary
;
594 high_bound
= ap_offset
595 + FIRST_PARM_OFFSET (current_function_decl
)
596 #if !ARGS_GROW_DOWNWARD
601 high_bound
= red_zone_size
+ stack_boundary
;
602 low_bound
= ap_offset
603 + FIRST_PARM_OFFSET (current_function_decl
)
604 #if ARGS_GROW_DOWNWARD
612 /* We assume that accesses are safe to at least the
614 Examples are varargs and __builtin_return_address. */
615 #if ARGS_GROW_DOWNWARD
616 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
618 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
619 - crtl
->args
.size
- stack_boundary
;
621 low_bound
= FIRST_PARM_OFFSET (current_function_decl
)
623 high_bound
= FIRST_PARM_OFFSET (current_function_decl
)
624 + crtl
->args
.size
+ stack_boundary
;
628 if (offset
>= low_bound
&& offset
<= high_bound
- size
)
632 /* All of the virtual frame registers are stack references. */
633 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
634 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
639 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
640 mode
, unaligned_mems
);
643 /* An address is assumed not to trap if:
644 - it is the pic register plus a constant. */
645 if (XEXP (x
, 0) == pic_offset_table_rtx
&& CONSTANT_P (XEXP (x
, 1)))
648 /* - or it is an address that can't trap plus a constant integer. */
649 if (CONST_INT_P (XEXP (x
, 1))
650 && !rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
+ INTVAL (XEXP (x
, 1)),
651 size
, mode
, unaligned_mems
))
658 return rtx_addr_can_trap_p_1 (XEXP (x
, 1), offset
, size
,
659 mode
, unaligned_mems
);
666 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), offset
, size
,
667 mode
, unaligned_mems
);
673 /* If it isn't one of the case above, it can cause a trap. */
677 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */
680 rtx_addr_can_trap_p (const_rtx x
)
682 return rtx_addr_can_trap_p_1 (x
, 0, 0, VOIDmode
, false);
685 /* Return true if X is an address that is known to not be zero. */
688 nonzero_address_p (const_rtx x
)
690 const enum rtx_code code
= GET_CODE (x
);
695 return flag_delete_null_pointer_checks
&& !SYMBOL_REF_WEAK (x
);
701 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
702 if (x
== frame_pointer_rtx
|| x
== hard_frame_pointer_rtx
703 || x
== stack_pointer_rtx
704 || (x
== arg_pointer_rtx
&& fixed_regs
[ARG_POINTER_REGNUM
]))
706 /* All of the virtual frame registers are stack references. */
707 if (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
708 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
)
713 return nonzero_address_p (XEXP (x
, 0));
716 /* Handle PIC references. */
717 if (XEXP (x
, 0) == pic_offset_table_rtx
718 && CONSTANT_P (XEXP (x
, 1)))
723 /* Similar to the above; allow positive offsets. Further, since
724 auto-inc is only allowed in memories, the register must be a
726 if (CONST_INT_P (XEXP (x
, 1))
727 && INTVAL (XEXP (x
, 1)) > 0)
729 return nonzero_address_p (XEXP (x
, 0));
732 /* Similarly. Further, the offset is always positive. */
739 return nonzero_address_p (XEXP (x
, 0));
742 return nonzero_address_p (XEXP (x
, 1));
748 /* If it isn't one of the case above, might be zero. */
752 /* Return 1 if X refers to a memory location whose address
753 cannot be compared reliably with constant addresses,
754 or if X refers to a BLKmode memory object.
755 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
756 zero, we are slightly more conservative. */
759 rtx_addr_varies_p (const_rtx x
, bool for_alias
)
770 return GET_MODE (x
) == BLKmode
|| rtx_varies_p (XEXP (x
, 0), for_alias
);
772 fmt
= GET_RTX_FORMAT (code
);
773 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
776 if (rtx_addr_varies_p (XEXP (x
, i
), for_alias
))
779 else if (fmt
[i
] == 'E')
782 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
783 if (rtx_addr_varies_p (XVECEXP (x
, i
, j
), for_alias
))
789 /* Return the CALL in X if there is one. */
792 get_call_rtx_from (rtx x
)
796 if (GET_CODE (x
) == PARALLEL
)
797 x
= XVECEXP (x
, 0, 0);
798 if (GET_CODE (x
) == SET
)
800 if (GET_CODE (x
) == CALL
&& MEM_P (XEXP (x
, 0)))
805 /* Return the value of the integer term in X, if one is apparent;
807 Only obvious integer terms are detected.
808 This is used in cse.c with the `related_value' field. */
811 get_integer_term (const_rtx x
)
813 if (GET_CODE (x
) == CONST
)
816 if (GET_CODE (x
) == MINUS
817 && CONST_INT_P (XEXP (x
, 1)))
818 return - INTVAL (XEXP (x
, 1));
819 if (GET_CODE (x
) == PLUS
820 && CONST_INT_P (XEXP (x
, 1)))
821 return INTVAL (XEXP (x
, 1));
825 /* If X is a constant, return the value sans apparent integer term;
827 Only obvious integer terms are detected. */
830 get_related_value (const_rtx x
)
832 if (GET_CODE (x
) != CONST
)
835 if (GET_CODE (x
) == PLUS
836 && CONST_INT_P (XEXP (x
, 1)))
838 else if (GET_CODE (x
) == MINUS
839 && CONST_INT_P (XEXP (x
, 1)))
844 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
845 to somewhere in the same object or object_block as SYMBOL. */
848 offset_within_block_p (const_rtx symbol
, HOST_WIDE_INT offset
)
852 if (GET_CODE (symbol
) != SYMBOL_REF
)
860 if (CONSTANT_POOL_ADDRESS_P (symbol
)
861 && offset
< (int) GET_MODE_SIZE (get_pool_mode (symbol
)))
864 decl
= SYMBOL_REF_DECL (symbol
);
865 if (decl
&& offset
< int_size_in_bytes (TREE_TYPE (decl
)))
869 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol
)
870 && SYMBOL_REF_BLOCK (symbol
)
871 && SYMBOL_REF_BLOCK_OFFSET (symbol
) >= 0
872 && ((unsigned HOST_WIDE_INT
) offset
+ SYMBOL_REF_BLOCK_OFFSET (symbol
)
873 < (unsigned HOST_WIDE_INT
) SYMBOL_REF_BLOCK (symbol
)->size
))
879 /* Split X into a base and a constant offset, storing them in *BASE_OUT
880 and *OFFSET_OUT respectively. */
883 split_const (rtx x
, rtx
*base_out
, rtx
*offset_out
)
885 if (GET_CODE (x
) == CONST
)
888 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
890 *base_out
= XEXP (x
, 0);
891 *offset_out
= XEXP (x
, 1);
896 *offset_out
= const0_rtx
;
899 /* Return the number of places FIND appears within X. If COUNT_DEST is
900 zero, we do not count occurrences inside the destination of a SET. */
903 count_occurrences (const_rtx x
, const_rtx find
, int count_dest
)
907 const char *format_ptr
;
926 count
= count_occurrences (XEXP (x
, 0), find
, count_dest
);
928 count
+= count_occurrences (XEXP (x
, 1), find
, count_dest
);
932 if (MEM_P (find
) && rtx_equal_p (x
, find
))
937 if (SET_DEST (x
) == find
&& ! count_dest
)
938 return count_occurrences (SET_SRC (x
), find
, count_dest
);
945 format_ptr
= GET_RTX_FORMAT (code
);
948 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
950 switch (*format_ptr
++)
953 count
+= count_occurrences (XEXP (x
, i
), find
, count_dest
);
957 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
958 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
, count_dest
);
966 /* Return TRUE if OP is a register or subreg of a register that
967 holds an unsigned quantity. Otherwise, return FALSE. */
970 unsigned_reg_p (rtx op
)
974 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op
))))
977 if (GET_CODE (op
) == SUBREG
978 && SUBREG_PROMOTED_SIGN (op
))
985 /* Nonzero if register REG appears somewhere within IN.
986 Also works if REG is not a register; in this case it checks
987 for a subexpression of IN that is Lisp "equal" to REG. */
990 reg_mentioned_p (const_rtx reg
, const_rtx in
)
1002 if (GET_CODE (in
) == LABEL_REF
)
1003 return reg
== LABEL_REF_LABEL (in
);
1005 code
= GET_CODE (in
);
1009 /* Compare registers by number. */
1011 return REG_P (reg
) && REGNO (in
) == REGNO (reg
);
1013 /* These codes have no constituent expressions
1021 /* These are kept unique for a given value. */
1028 if (GET_CODE (reg
) == code
&& rtx_equal_p (reg
, in
))
1031 fmt
= GET_RTX_FORMAT (code
);
1033 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1038 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
1039 if (reg_mentioned_p (reg
, XVECEXP (in
, i
, j
)))
1042 else if (fmt
[i
] == 'e'
1043 && reg_mentioned_p (reg
, XEXP (in
, i
)))
1049 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1050 no CODE_LABEL insn. */
1053 no_labels_between_p (const rtx_insn
*beg
, const rtx_insn
*end
)
1058 for (p
= NEXT_INSN (beg
); p
!= end
; p
= NEXT_INSN (p
))
1064 /* Nonzero if register REG is used in an insn between
1065 FROM_INSN and TO_INSN (exclusive of those two). */
1068 reg_used_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1069 const rtx_insn
*to_insn
)
1073 if (from_insn
== to_insn
)
1076 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1077 if (NONDEBUG_INSN_P (insn
)
1078 && (reg_overlap_mentioned_p (reg
, PATTERN (insn
))
1079 || (CALL_P (insn
) && find_reg_fusage (insn
, USE
, reg
))))
1084 /* Nonzero if the old value of X, a register, is referenced in BODY. If X
1085 is entirely replaced by a new value and the only use is as a SET_DEST,
1086 we do not consider it a reference. */
1089 reg_referenced_p (const_rtx x
, const_rtx body
)
1093 switch (GET_CODE (body
))
1096 if (reg_overlap_mentioned_p (x
, SET_SRC (body
)))
1099 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1100 of a REG that occupies all of the REG, the insn references X if
1101 it is mentioned in the destination. */
1102 if (GET_CODE (SET_DEST (body
)) != CC0
1103 && GET_CODE (SET_DEST (body
)) != PC
1104 && !REG_P (SET_DEST (body
))
1105 && ! (GET_CODE (SET_DEST (body
)) == SUBREG
1106 && REG_P (SUBREG_REG (SET_DEST (body
)))
1107 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body
))))
1108 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
1109 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body
)))
1110 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
1111 && reg_overlap_mentioned_p (x
, SET_DEST (body
)))
1116 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1117 if (reg_overlap_mentioned_p (x
, ASM_OPERANDS_INPUT (body
, i
)))
1124 return reg_overlap_mentioned_p (x
, body
);
1127 return reg_overlap_mentioned_p (x
, TRAP_CONDITION (body
));
1130 return reg_overlap_mentioned_p (x
, XEXP (body
, 0));
1133 case UNSPEC_VOLATILE
:
1134 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1135 if (reg_overlap_mentioned_p (x
, XVECEXP (body
, 0, i
)))
1140 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1141 if (reg_referenced_p (x
, XVECEXP (body
, 0, i
)))
1146 if (MEM_P (XEXP (body
, 0)))
1147 if (reg_overlap_mentioned_p (x
, XEXP (XEXP (body
, 0), 0)))
1152 if (reg_overlap_mentioned_p (x
, COND_EXEC_TEST (body
)))
1154 return reg_referenced_p (x
, COND_EXEC_CODE (body
));
1161 /* Nonzero if register REG is set or clobbered in an insn between
1162 FROM_INSN and TO_INSN (exclusive of those two). */
1165 reg_set_between_p (const_rtx reg
, const rtx_insn
*from_insn
,
1166 const rtx_insn
*to_insn
)
1168 const rtx_insn
*insn
;
1170 if (from_insn
== to_insn
)
1173 for (insn
= NEXT_INSN (from_insn
); insn
!= to_insn
; insn
= NEXT_INSN (insn
))
1174 if (INSN_P (insn
) && reg_set_p (reg
, insn
))
1179 /* Return true if REG is set or clobbered inside INSN. */
1182 reg_set_p (const_rtx reg
, const_rtx insn
)
1184 /* After delay slot handling, call and branch insns might be in a
1185 sequence. Check all the elements there. */
1186 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1188 for (int i
= 0; i
< XVECLEN (PATTERN (insn
), 0); ++i
)
1189 if (reg_set_p (reg
, XVECEXP (PATTERN (insn
), 0, i
)))
1195 /* We can be passed an insn or part of one. If we are passed an insn,
1196 check if a side-effect of the insn clobbers REG. */
1198 && (FIND_REG_INC_NOTE (insn
, reg
)
1201 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
1202 && overlaps_hard_reg_set_p (regs_invalidated_by_call
,
1203 GET_MODE (reg
), REGNO (reg
)))
1205 || find_reg_fusage (insn
, CLOBBER
, reg
)))))
1208 return set_of (reg
, insn
) != NULL_RTX
;
1211 /* Similar to reg_set_between_p, but check all registers in X. Return 0
1212 only if none of them are modified between START and END. Return 1 if
1213 X contains a MEM; this routine does use memory aliasing. */
1216 modified_between_p (const_rtx x
, const rtx_insn
*start
, const rtx_insn
*end
)
1218 const enum rtx_code code
= GET_CODE (x
);
1239 if (modified_between_p (XEXP (x
, 0), start
, end
))
1241 if (MEM_READONLY_P (x
))
1243 for (insn
= NEXT_INSN (start
); insn
!= end
; insn
= NEXT_INSN (insn
))
1244 if (memory_modified_in_insn_p (x
, insn
))
1249 return reg_set_between_p (x
, start
, end
);
1255 fmt
= GET_RTX_FORMAT (code
);
1256 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1258 if (fmt
[i
] == 'e' && modified_between_p (XEXP (x
, i
), start
, end
))
1261 else if (fmt
[i
] == 'E')
1262 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1263 if (modified_between_p (XVECEXP (x
, i
, j
), start
, end
))
1270 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1271 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1272 does use memory aliasing. */
1275 modified_in_p (const_rtx x
, const_rtx insn
)
1277 const enum rtx_code code
= GET_CODE (x
);
1294 if (modified_in_p (XEXP (x
, 0), insn
))
1296 if (MEM_READONLY_P (x
))
1298 if (memory_modified_in_insn_p (x
, insn
))
1303 return reg_set_p (x
, insn
);
1309 fmt
= GET_RTX_FORMAT (code
);
1310 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1312 if (fmt
[i
] == 'e' && modified_in_p (XEXP (x
, i
), insn
))
1315 else if (fmt
[i
] == 'E')
1316 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1317 if (modified_in_p (XVECEXP (x
, i
, j
), insn
))
1324 /* Helper function for set_of. */
1332 set_of_1 (rtx x
, const_rtx pat
, void *data1
)
1334 struct set_of_data
*const data
= (struct set_of_data
*) (data1
);
1335 if (rtx_equal_p (x
, data
->pat
)
1336 || (!MEM_P (x
) && reg_overlap_mentioned_p (data
->pat
, x
)))
1340 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1341 (either directly or via STRICT_LOW_PART and similar modifiers). */
1343 set_of (const_rtx pat
, const_rtx insn
)
1345 struct set_of_data data
;
1346 data
.found
= NULL_RTX
;
1348 note_stores (INSN_P (insn
) ? PATTERN (insn
) : insn
, set_of_1
, &data
);
1352 /* Add all hard register in X to *PSET. */
1354 find_all_hard_regs (const_rtx x
, HARD_REG_SET
*pset
)
1356 subrtx_iterator::array_type array
;
1357 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
1359 const_rtx x
= *iter
;
1360 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1361 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1365 /* This function, called through note_stores, collects sets and
1366 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1369 record_hard_reg_sets (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
1371 HARD_REG_SET
*pset
= (HARD_REG_SET
*)data
;
1372 if (REG_P (x
) && HARD_REGISTER_P (x
))
1373 add_to_hard_reg_set (pset
, GET_MODE (x
), REGNO (x
));
1376 /* Examine INSN, and compute the set of hard registers written by it.
1377 Store it in *PSET. Should only be called after reload. */
1379 find_all_hard_reg_sets (const rtx_insn
*insn
, HARD_REG_SET
*pset
, bool implicit
)
1383 CLEAR_HARD_REG_SET (*pset
);
1384 note_stores (PATTERN (insn
), record_hard_reg_sets
, pset
);
1388 IOR_HARD_REG_SET (*pset
, call_used_reg_set
);
1390 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
1391 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1393 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1394 if (REG_NOTE_KIND (link
) == REG_INC
)
1395 record_hard_reg_sets (XEXP (link
, 0), NULL
, pset
);
1398 /* Like record_hard_reg_sets, but called through note_uses. */
1400 record_hard_reg_uses (rtx
*px
, void *data
)
1402 find_all_hard_regs (*px
, (HARD_REG_SET
*) data
);
1405 /* Given an INSN, return a SET expression if this insn has only a single SET.
1406 It may also have CLOBBERs, USEs, or SET whose output
1407 will not be used, which we ignore. */
1410 single_set_2 (const rtx_insn
*insn
, const_rtx pat
)
1413 int set_verified
= 1;
1416 if (GET_CODE (pat
) == PARALLEL
)
1418 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1420 rtx sub
= XVECEXP (pat
, 0, i
);
1421 switch (GET_CODE (sub
))
1428 /* We can consider insns having multiple sets, where all
1429 but one are dead as single set insns. In common case
1430 only single set is present in the pattern so we want
1431 to avoid checking for REG_UNUSED notes unless necessary.
1433 When we reach set first time, we just expect this is
1434 the single set we are looking for and only when more
1435 sets are found in the insn, we check them. */
1438 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (set
))
1439 && !side_effects_p (set
))
1445 set
= sub
, set_verified
= 0;
1446 else if (!find_reg_note (insn
, REG_UNUSED
, SET_DEST (sub
))
1447 || side_effects_p (sub
))
1459 /* Given an INSN, return nonzero if it has more than one SET, else return
1463 multiple_sets (const_rtx insn
)
1468 /* INSN must be an insn. */
1469 if (! INSN_P (insn
))
1472 /* Only a PARALLEL can have multiple SETs. */
1473 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1475 for (i
= 0, found
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1476 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, i
)) == SET
)
1478 /* If we have already found a SET, then return now. */
1486 /* Either zero or one SET. */
1490 /* Return nonzero if the destination of SET equals the source
1491 and there are no side effects. */
1494 set_noop_p (const_rtx set
)
1496 rtx src
= SET_SRC (set
);
1497 rtx dst
= SET_DEST (set
);
1499 if (dst
== pc_rtx
&& src
== pc_rtx
)
1502 if (MEM_P (dst
) && MEM_P (src
))
1503 return rtx_equal_p (dst
, src
) && !side_effects_p (dst
);
1505 if (GET_CODE (dst
) == ZERO_EXTRACT
)
1506 return rtx_equal_p (XEXP (dst
, 0), src
)
1507 && !BITS_BIG_ENDIAN
&& XEXP (dst
, 2) == const0_rtx
1508 && !side_effects_p (src
);
1510 if (GET_CODE (dst
) == STRICT_LOW_PART
)
1511 dst
= XEXP (dst
, 0);
1513 if (GET_CODE (src
) == SUBREG
&& GET_CODE (dst
) == SUBREG
)
1515 if (SUBREG_BYTE (src
) != SUBREG_BYTE (dst
))
1517 src
= SUBREG_REG (src
);
1518 dst
= SUBREG_REG (dst
);
1521 /* It is a NOOP if destination overlaps with selected src vector
1523 if (GET_CODE (src
) == VEC_SELECT
1524 && REG_P (XEXP (src
, 0)) && REG_P (dst
)
1525 && HARD_REGISTER_P (XEXP (src
, 0))
1526 && HARD_REGISTER_P (dst
))
1529 rtx par
= XEXP (src
, 1);
1530 rtx src0
= XEXP (src
, 0);
1531 int c0
= INTVAL (XVECEXP (par
, 0, 0));
1532 HOST_WIDE_INT offset
= GET_MODE_UNIT_SIZE (GET_MODE (src0
)) * c0
;
1534 for (i
= 1; i
< XVECLEN (par
, 0); i
++)
1535 if (INTVAL (XVECEXP (par
, 0, i
)) != c0
+ i
)
1538 simplify_subreg_regno (REGNO (src0
), GET_MODE (src0
),
1539 offset
, GET_MODE (dst
)) == (int) REGNO (dst
);
1542 return (REG_P (src
) && REG_P (dst
)
1543 && REGNO (src
) == REGNO (dst
));
1546 /* Return nonzero if an insn consists only of SETs, each of which only sets a
1550 noop_move_p (const rtx_insn
*insn
)
1552 rtx pat
= PATTERN (insn
);
1554 if (INSN_CODE (insn
) == NOOP_MOVE_INSN_CODE
)
1557 /* Insns carrying these notes are useful later on. */
1558 if (find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1561 /* Check the code to be executed for COND_EXEC. */
1562 if (GET_CODE (pat
) == COND_EXEC
)
1563 pat
= COND_EXEC_CODE (pat
);
1565 if (GET_CODE (pat
) == SET
&& set_noop_p (pat
))
1568 if (GET_CODE (pat
) == PARALLEL
)
1571 /* If nothing but SETs of registers to themselves,
1572 this insn can also be deleted. */
1573 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1575 rtx tem
= XVECEXP (pat
, 0, i
);
1577 if (GET_CODE (tem
) == USE
1578 || GET_CODE (tem
) == CLOBBER
)
1581 if (GET_CODE (tem
) != SET
|| ! set_noop_p (tem
))
1591 /* Return nonzero if register in range [REGNO, ENDREGNO)
1592 appears either explicitly or implicitly in X
1593 other than being stored into.
1595 References contained within the substructure at LOC do not count.
1596 LOC may be zero, meaning don't ignore anything. */
1599 refers_to_regno_p (unsigned int regno
, unsigned int endregno
, const_rtx x
,
1603 unsigned int x_regno
;
1608 /* The contents of a REG_NONNEG note is always zero, so we must come here
1609 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1613 code
= GET_CODE (x
);
1618 x_regno
= REGNO (x
);
1620 /* If we modifying the stack, frame, or argument pointer, it will
1621 clobber a virtual register. In fact, we could be more precise,
1622 but it isn't worth it. */
1623 if ((x_regno
== STACK_POINTER_REGNUM
1624 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1625 && x_regno
== ARG_POINTER_REGNUM
)
1626 || x_regno
== FRAME_POINTER_REGNUM
)
1627 && regno
>= FIRST_VIRTUAL_REGISTER
&& regno
<= LAST_VIRTUAL_REGISTER
)
1630 return endregno
> x_regno
&& regno
< END_REGNO (x
);
1633 /* If this is a SUBREG of a hard reg, we can see exactly which
1634 registers are being modified. Otherwise, handle normally. */
1635 if (REG_P (SUBREG_REG (x
))
1636 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
1638 unsigned int inner_regno
= subreg_regno (x
);
1639 unsigned int inner_endregno
1640 = inner_regno
+ (inner_regno
< FIRST_PSEUDO_REGISTER
1641 ? subreg_nregs (x
) : 1);
1643 return endregno
> inner_regno
&& regno
< inner_endregno
;
1649 if (&SET_DEST (x
) != loc
1650 /* Note setting a SUBREG counts as referring to the REG it is in for
1651 a pseudo but not for hard registers since we can
1652 treat each word individually. */
1653 && ((GET_CODE (SET_DEST (x
)) == SUBREG
1654 && loc
!= &SUBREG_REG (SET_DEST (x
))
1655 && REG_P (SUBREG_REG (SET_DEST (x
)))
1656 && REGNO (SUBREG_REG (SET_DEST (x
))) >= FIRST_PSEUDO_REGISTER
1657 && refers_to_regno_p (regno
, endregno
,
1658 SUBREG_REG (SET_DEST (x
)), loc
))
1659 || (!REG_P (SET_DEST (x
))
1660 && refers_to_regno_p (regno
, endregno
, SET_DEST (x
), loc
))))
1663 if (code
== CLOBBER
|| loc
== &SET_SRC (x
))
1672 /* X does not match, so try its subexpressions. */
1674 fmt
= GET_RTX_FORMAT (code
);
1675 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1677 if (fmt
[i
] == 'e' && loc
!= &XEXP (x
, i
))
1685 if (refers_to_regno_p (regno
, endregno
, XEXP (x
, i
), loc
))
1688 else if (fmt
[i
] == 'E')
1691 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1692 if (loc
!= &XVECEXP (x
, i
, j
)
1693 && refers_to_regno_p (regno
, endregno
, XVECEXP (x
, i
, j
), loc
))
1700 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1701 we check if any register number in X conflicts with the relevant register
1702 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1703 contains a MEM (we don't bother checking for memory addresses that can't
1704 conflict because we expect this to be a rare case. */
1707 reg_overlap_mentioned_p (const_rtx x
, const_rtx in
)
1709 unsigned int regno
, endregno
;
1711 /* If either argument is a constant, then modifying X can not
1712 affect IN. Here we look at IN, we can profitably combine
1713 CONSTANT_P (x) with the switch statement below. */
1714 if (CONSTANT_P (in
))
1718 switch (GET_CODE (x
))
1720 case STRICT_LOW_PART
:
1723 /* Overly conservative. */
1728 regno
= REGNO (SUBREG_REG (x
));
1729 if (regno
< FIRST_PSEUDO_REGISTER
)
1730 regno
= subreg_regno (x
);
1731 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
1732 ? subreg_nregs (x
) : 1);
1737 endregno
= END_REGNO (x
);
1739 return refers_to_regno_p (regno
, endregno
, in
, (rtx
*) 0);
1749 fmt
= GET_RTX_FORMAT (GET_CODE (in
));
1750 for (i
= GET_RTX_LENGTH (GET_CODE (in
)) - 1; i
>= 0; i
--)
1753 if (reg_overlap_mentioned_p (x
, XEXP (in
, i
)))
1756 else if (fmt
[i
] == 'E')
1759 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; --j
)
1760 if (reg_overlap_mentioned_p (x
, XVECEXP (in
, i
, j
)))
1770 return reg_mentioned_p (x
, in
);
1776 /* If any register in here refers to it we return true. */
1777 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1778 if (XEXP (XVECEXP (x
, 0, i
), 0) != 0
1779 && reg_overlap_mentioned_p (XEXP (XVECEXP (x
, 0, i
), 0), in
))
1785 gcc_assert (CONSTANT_P (x
));
1790 /* Call FUN on each register or MEM that is stored into or clobbered by X.
1791 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1792 ignored by note_stores, but passed to FUN.
1794 FUN receives three arguments:
1795 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1796 2. the SET or CLOBBER rtx that does the store,
1797 3. the pointer DATA provided to note_stores.
1799 If the item being stored in or clobbered is a SUBREG of a hard register,
1800 the SUBREG will be passed. */
1803 note_stores (const_rtx x
, void (*fun
) (rtx
, const_rtx
, void *), void *data
)
1807 if (GET_CODE (x
) == COND_EXEC
)
1808 x
= COND_EXEC_CODE (x
);
1810 if (GET_CODE (x
) == SET
|| GET_CODE (x
) == CLOBBER
)
1812 rtx dest
= SET_DEST (x
);
1814 while ((GET_CODE (dest
) == SUBREG
1815 && (!REG_P (SUBREG_REG (dest
))
1816 || REGNO (SUBREG_REG (dest
)) >= FIRST_PSEUDO_REGISTER
))
1817 || GET_CODE (dest
) == ZERO_EXTRACT
1818 || GET_CODE (dest
) == STRICT_LOW_PART
)
1819 dest
= XEXP (dest
, 0);
1821 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1822 each of whose first operand is a register. */
1823 if (GET_CODE (dest
) == PARALLEL
)
1825 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
1826 if (XEXP (XVECEXP (dest
, 0, i
), 0) != 0)
1827 (*fun
) (XEXP (XVECEXP (dest
, 0, i
), 0), x
, data
);
1830 (*fun
) (dest
, x
, data
);
1833 else if (GET_CODE (x
) == PARALLEL
)
1834 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1835 note_stores (XVECEXP (x
, 0, i
), fun
, data
);
1838 /* Like notes_stores, but call FUN for each expression that is being
1839 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1840 FUN for each expression, not any interior subexpressions. FUN receives a
1841 pointer to the expression and the DATA passed to this function.
1843 Note that this is not quite the same test as that done in reg_referenced_p
1844 since that considers something as being referenced if it is being
1845 partially set, while we do not. */
1848 note_uses (rtx
*pbody
, void (*fun
) (rtx
*, void *), void *data
)
1853 switch (GET_CODE (body
))
1856 (*fun
) (&COND_EXEC_TEST (body
), data
);
1857 note_uses (&COND_EXEC_CODE (body
), fun
, data
);
1861 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1862 note_uses (&XVECEXP (body
, 0, i
), fun
, data
);
1866 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1867 note_uses (&PATTERN (XVECEXP (body
, 0, i
)), fun
, data
);
1871 (*fun
) (&XEXP (body
, 0), data
);
1875 for (i
= ASM_OPERANDS_INPUT_LENGTH (body
) - 1; i
>= 0; i
--)
1876 (*fun
) (&ASM_OPERANDS_INPUT (body
, i
), data
);
1880 (*fun
) (&TRAP_CONDITION (body
), data
);
1884 (*fun
) (&XEXP (body
, 0), data
);
1888 case UNSPEC_VOLATILE
:
1889 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
1890 (*fun
) (&XVECEXP (body
, 0, i
), data
);
1894 if (MEM_P (XEXP (body
, 0)))
1895 (*fun
) (&XEXP (XEXP (body
, 0), 0), data
);
1900 rtx dest
= SET_DEST (body
);
1902 /* For sets we replace everything in source plus registers in memory
1903 expression in store and operands of a ZERO_EXTRACT. */
1904 (*fun
) (&SET_SRC (body
), data
);
1906 if (GET_CODE (dest
) == ZERO_EXTRACT
)
1908 (*fun
) (&XEXP (dest
, 1), data
);
1909 (*fun
) (&XEXP (dest
, 2), data
);
1912 while (GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
)
1913 dest
= XEXP (dest
, 0);
1916 (*fun
) (&XEXP (dest
, 0), data
);
1921 /* All the other possibilities never store. */
1922 (*fun
) (pbody
, data
);
1927 /* Return nonzero if X's old contents don't survive after INSN.
1928 This will be true if X is (cc0) or if X is a register and
1929 X dies in INSN or because INSN entirely sets X.
1931 "Entirely set" means set directly and not through a SUBREG, or
1932 ZERO_EXTRACT, so no trace of the old contents remains.
1933 Likewise, REG_INC does not count.
1935 REG may be a hard or pseudo reg. Renumbering is not taken into account,
1936 but for this use that makes no difference, since regs don't overlap
1937 during their lifetimes. Therefore, this function may be used
1938 at any time after deaths have been computed.
1940 If REG is a hard reg that occupies multiple machine registers, this
1941 function will only return 1 if each of those registers will be replaced
1945 dead_or_set_p (const_rtx insn
, const_rtx x
)
1947 unsigned int regno
, end_regno
;
1950 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
1951 if (GET_CODE (x
) == CC0
)
1954 gcc_assert (REG_P (x
));
1957 end_regno
= END_REGNO (x
);
1958 for (i
= regno
; i
< end_regno
; i
++)
1959 if (! dead_or_set_regno_p (insn
, i
))
1965 /* Return TRUE iff DEST is a register or subreg of a register and
1966 doesn't change the number of words of the inner register, and any
1967 part of the register is TEST_REGNO. */
1970 covers_regno_no_parallel_p (const_rtx dest
, unsigned int test_regno
)
1972 unsigned int regno
, endregno
;
1974 if (GET_CODE (dest
) == SUBREG
1975 && (((GET_MODE_SIZE (GET_MODE (dest
))
1976 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
1977 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
1978 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)))
1979 dest
= SUBREG_REG (dest
);
1984 regno
= REGNO (dest
);
1985 endregno
= END_REGNO (dest
);
1986 return (test_regno
>= regno
&& test_regno
< endregno
);
1989 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where
1990 any member matches the covers_regno_no_parallel_p criteria. */
1993 covers_regno_p (const_rtx dest
, unsigned int test_regno
)
1995 if (GET_CODE (dest
) == PARALLEL
)
1997 /* Some targets place small structures in registers for return
1998 values of functions, and those registers are wrapped in
1999 PARALLELs that we may see as the destination of a SET. */
2002 for (i
= XVECLEN (dest
, 0) - 1; i
>= 0; i
--)
2004 rtx inner
= XEXP (XVECEXP (dest
, 0, i
), 0);
2005 if (inner
!= NULL_RTX
2006 && covers_regno_no_parallel_p (inner
, test_regno
))
2013 return covers_regno_no_parallel_p (dest
, test_regno
);
2016 /* Utility function for dead_or_set_p to check an individual register. */
2019 dead_or_set_regno_p (const_rtx insn
, unsigned int test_regno
)
2023 /* See if there is a death note for something that includes TEST_REGNO. */
2024 if (find_regno_note (insn
, REG_DEAD
, test_regno
))
2028 && find_regno_fusage (insn
, CLOBBER
, test_regno
))
2031 pattern
= PATTERN (insn
);
2033 /* If a COND_EXEC is not executed, the value survives. */
2034 if (GET_CODE (pattern
) == COND_EXEC
)
2037 if (GET_CODE (pattern
) == SET
)
2038 return covers_regno_p (SET_DEST (pattern
), test_regno
);
2039 else if (GET_CODE (pattern
) == PARALLEL
)
2043 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2045 rtx body
= XVECEXP (pattern
, 0, i
);
2047 if (GET_CODE (body
) == COND_EXEC
)
2048 body
= COND_EXEC_CODE (body
);
2050 if ((GET_CODE (body
) == SET
|| GET_CODE (body
) == CLOBBER
)
2051 && covers_regno_p (SET_DEST (body
), test_regno
))
2059 /* Return the reg-note of kind KIND in insn INSN, if there is one.
2060 If DATUM is nonzero, look for one whose datum is DATUM. */
2063 find_reg_note (const_rtx insn
, enum reg_note kind
, const_rtx datum
)
2067 gcc_checking_assert (insn
);
2069 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2070 if (! INSN_P (insn
))
2074 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2075 if (REG_NOTE_KIND (link
) == kind
)
2080 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2081 if (REG_NOTE_KIND (link
) == kind
&& datum
== XEXP (link
, 0))
2086 /* Return the reg-note of kind KIND in insn INSN which applies to register
2087 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2088 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2089 it might be the case that the note overlaps REGNO. */
2092 find_regno_note (const_rtx insn
, enum reg_note kind
, unsigned int regno
)
2096 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2097 if (! INSN_P (insn
))
2100 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2101 if (REG_NOTE_KIND (link
) == kind
2102 /* Verify that it is a register, so that scratch and MEM won't cause a
2104 && REG_P (XEXP (link
, 0))
2105 && REGNO (XEXP (link
, 0)) <= regno
2106 && END_REGNO (XEXP (link
, 0)) > regno
)
2111 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2115 find_reg_equal_equiv_note (const_rtx insn
)
2122 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2123 if (REG_NOTE_KIND (link
) == REG_EQUAL
2124 || REG_NOTE_KIND (link
) == REG_EQUIV
)
2126 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2127 insns that have multiple sets. Checking single_set to
2128 make sure of this is not the proper check, as explained
2129 in the comment in set_unique_reg_note.
2131 This should be changed into an assert. */
2132 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
2139 /* Check whether INSN is a single_set whose source is known to be
2140 equivalent to a constant. Return that constant if so, otherwise
2144 find_constant_src (const rtx_insn
*insn
)
2148 set
= single_set (insn
);
2151 x
= avoid_constant_pool_reference (SET_SRC (set
));
2156 note
= find_reg_equal_equiv_note (insn
);
2157 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2158 return XEXP (note
, 0);
2163 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2164 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2167 find_reg_fusage (const_rtx insn
, enum rtx_code code
, const_rtx datum
)
2169 /* If it's not a CALL_INSN, it can't possibly have a
2170 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2180 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
2182 link
= XEXP (link
, 1))
2183 if (GET_CODE (XEXP (link
, 0)) == code
2184 && rtx_equal_p (datum
, XEXP (XEXP (link
, 0), 0)))
2189 unsigned int regno
= REGNO (datum
);
2191 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2192 to pseudo registers, so don't bother checking. */
2194 if (regno
< FIRST_PSEUDO_REGISTER
)
2196 unsigned int end_regno
= END_REGNO (datum
);
2199 for (i
= regno
; i
< end_regno
; i
++)
2200 if (find_regno_fusage (insn
, code
, i
))
2208 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2209 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2212 find_regno_fusage (const_rtx insn
, enum rtx_code code
, unsigned int regno
)
2216 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2217 to pseudo registers, so don't bother checking. */
2219 if (regno
>= FIRST_PSEUDO_REGISTER
2223 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
2227 if (GET_CODE (op
= XEXP (link
, 0)) == code
2228 && REG_P (reg
= XEXP (op
, 0))
2229 && REGNO (reg
) <= regno
2230 && END_REGNO (reg
) > regno
)
2238 /* Return true if KIND is an integer REG_NOTE. */
2241 int_reg_note_p (enum reg_note kind
)
2243 return kind
== REG_BR_PROB
;
2246 /* Allocate a register note with kind KIND and datum DATUM. LIST is
2247 stored as the pointer to the next register note. */
2250 alloc_reg_note (enum reg_note kind
, rtx datum
, rtx list
)
2254 gcc_checking_assert (!int_reg_note_p (kind
));
2259 case REG_LABEL_TARGET
:
2260 case REG_LABEL_OPERAND
:
2262 /* These types of register notes use an INSN_LIST rather than an
2263 EXPR_LIST, so that copying is done right and dumps look
2265 note
= alloc_INSN_LIST (datum
, list
);
2266 PUT_REG_NOTE_KIND (note
, kind
);
2270 note
= alloc_EXPR_LIST (kind
, datum
, list
);
2277 /* Add register note with kind KIND and datum DATUM to INSN. */
2280 add_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
2282 REG_NOTES (insn
) = alloc_reg_note (kind
, datum
, REG_NOTES (insn
));
2285 /* Add an integer register note with kind KIND and datum DATUM to INSN. */
2288 add_int_reg_note (rtx insn
, enum reg_note kind
, int datum
)
2290 gcc_checking_assert (int_reg_note_p (kind
));
2291 REG_NOTES (insn
) = gen_rtx_INT_LIST ((machine_mode
) kind
,
2292 datum
, REG_NOTES (insn
));
2295 /* Add a register note like NOTE to INSN. */
2298 add_shallow_copy_of_reg_note (rtx_insn
*insn
, rtx note
)
2300 if (GET_CODE (note
) == INT_LIST
)
2301 add_int_reg_note (insn
, REG_NOTE_KIND (note
), XINT (note
, 0));
2303 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
2306 /* Remove register note NOTE from the REG_NOTES of INSN. */
2309 remove_note (rtx insn
, const_rtx note
)
2313 if (note
== NULL_RTX
)
2316 if (REG_NOTES (insn
) == note
)
2317 REG_NOTES (insn
) = XEXP (note
, 1);
2319 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2320 if (XEXP (link
, 1) == note
)
2322 XEXP (link
, 1) = XEXP (note
, 1);
2326 switch (REG_NOTE_KIND (note
))
2330 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
2337 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */
2340 remove_reg_equal_equiv_notes (rtx_insn
*insn
)
2344 loc
= ®_NOTES (insn
);
2347 enum reg_note kind
= REG_NOTE_KIND (*loc
);
2348 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
2349 *loc
= XEXP (*loc
, 1);
2351 loc
= &XEXP (*loc
, 1);
2355 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2358 remove_reg_equal_equiv_notes_for_regno (unsigned int regno
)
2365 /* This loop is a little tricky. We cannot just go down the chain because
2366 it is being modified by some actions in the loop. So we just iterate
2367 over the head. We plan to drain the list anyway. */
2368 while ((eq_use
= DF_REG_EQ_USE_CHAIN (regno
)) != NULL
)
2370 rtx_insn
*insn
= DF_REF_INSN (eq_use
);
2371 rtx note
= find_reg_equal_equiv_note (insn
);
2373 /* This assert is generally triggered when someone deletes a REG_EQUAL
2374 or REG_EQUIV note by hacking the list manually rather than calling
2378 remove_note (insn
, note
);
2382 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2383 return 1 if it is found. A simple equality test is used to determine if
2387 in_insn_list_p (const rtx_insn_list
*listp
, const rtx_insn
*node
)
2391 for (x
= listp
; x
; x
= XEXP (x
, 1))
2392 if (node
== XEXP (x
, 0))
2398 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2399 remove that entry from the list if it is found.
2401 A simple equality test is used to determine if NODE matches. */
2404 remove_node_from_expr_list (const_rtx node
, rtx_expr_list
**listp
)
2406 rtx_expr_list
*temp
= *listp
;
2407 rtx_expr_list
*prev
= NULL
;
2411 if (node
== temp
->element ())
2413 /* Splice the node out of the list. */
2415 XEXP (prev
, 1) = temp
->next ();
2417 *listp
= temp
->next ();
2423 temp
= temp
->next ();
2427 /* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2428 remove that entry from the list if it is found.
2430 A simple equality test is used to determine if NODE matches. */
2433 remove_node_from_insn_list (const rtx_insn
*node
, rtx_insn_list
**listp
)
2435 rtx_insn_list
*temp
= *listp
;
2436 rtx_insn_list
*prev
= NULL
;
2440 if (node
== temp
->insn ())
2442 /* Splice the node out of the list. */
2444 XEXP (prev
, 1) = temp
->next ();
2446 *listp
= temp
->next ();
2452 temp
= temp
->next ();
2456 /* Nonzero if X contains any volatile instructions. These are instructions
2457 which may cause unpredictable machine state instructions, and thus no
2458 instructions or register uses should be moved or combined across them.
2459 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2462 volatile_insn_p (const_rtx x
)
2464 const RTX_CODE code
= GET_CODE (x
);
2482 case UNSPEC_VOLATILE
:
2487 if (MEM_VOLATILE_P (x
))
2494 /* Recursively scan the operands of this expression. */
2497 const char *const fmt
= GET_RTX_FORMAT (code
);
2500 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2504 if (volatile_insn_p (XEXP (x
, i
)))
2507 else if (fmt
[i
] == 'E')
2510 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2511 if (volatile_insn_p (XVECEXP (x
, i
, j
)))
2519 /* Nonzero if X contains any volatile memory references
2520 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2523 volatile_refs_p (const_rtx x
)
2525 const RTX_CODE code
= GET_CODE (x
);
2541 case UNSPEC_VOLATILE
:
2547 if (MEM_VOLATILE_P (x
))
2554 /* Recursively scan the operands of this expression. */
2557 const char *const fmt
= GET_RTX_FORMAT (code
);
2560 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2564 if (volatile_refs_p (XEXP (x
, i
)))
2567 else if (fmt
[i
] == 'E')
2570 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2571 if (volatile_refs_p (XVECEXP (x
, i
, j
)))
2579 /* Similar to above, except that it also rejects register pre- and post-
2583 side_effects_p (const_rtx x
)
2585 const RTX_CODE code
= GET_CODE (x
);
2602 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
2603 when some combination can't be done. If we see one, don't think
2604 that we can simplify the expression. */
2605 return (GET_MODE (x
) != VOIDmode
);
2614 case UNSPEC_VOLATILE
:
2620 if (MEM_VOLATILE_P (x
))
2627 /* Recursively scan the operands of this expression. */
2630 const char *fmt
= GET_RTX_FORMAT (code
);
2633 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2637 if (side_effects_p (XEXP (x
, i
)))
2640 else if (fmt
[i
] == 'E')
2643 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2644 if (side_effects_p (XVECEXP (x
, i
, j
)))
2652 /* Return nonzero if evaluating rtx X might cause a trap.
2653 FLAGS controls how to consider MEMs. A nonzero means the context
2654 of the access may have changed from the original, such that the
2655 address may have become invalid. */
2658 may_trap_p_1 (const_rtx x
, unsigned flags
)
2664 /* We make no distinction currently, but this function is part of
2665 the internal target-hooks ABI so we keep the parameter as
2666 "unsigned flags". */
2667 bool code_changed
= flags
!= 0;
2671 code
= GET_CODE (x
);
2674 /* Handle these cases quickly. */
2686 return targetm
.unspec_may_trap_p (x
, flags
);
2688 case UNSPEC_VOLATILE
:
2694 return MEM_VOLATILE_P (x
);
2696 /* Memory ref can trap unless it's a static var or a stack slot. */
2698 /* Recognize specific pattern of stack checking probes. */
2699 if (flag_stack_check
2700 && MEM_VOLATILE_P (x
)
2701 && XEXP (x
, 0) == stack_pointer_rtx
)
2703 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
2704 reference; moving it out of context such as when moving code
2705 when optimizing, might cause its address to become invalid. */
2707 || !MEM_NOTRAP_P (x
))
2709 HOST_WIDE_INT size
= MEM_SIZE_KNOWN_P (x
) ? MEM_SIZE (x
) : 0;
2710 return rtx_addr_can_trap_p_1 (XEXP (x
, 0), 0, size
,
2711 GET_MODE (x
), code_changed
);
2716 /* Division by a non-constant might trap. */
2721 if (HONOR_SNANS (x
))
2723 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)))
2724 return flag_trapping_math
;
2725 if (!CONSTANT_P (XEXP (x
, 1)) || (XEXP (x
, 1) == const0_rtx
))
2730 /* An EXPR_LIST is used to represent a function call. This
2731 certainly may trap. */
2740 /* Some floating point comparisons may trap. */
2741 if (!flag_trapping_math
)
2743 /* ??? There is no machine independent way to check for tests that trap
2744 when COMPARE is used, though many targets do make this distinction.
2745 For instance, sparc uses CCFPE for compares which generate exceptions
2746 and CCFP for compares which do not generate exceptions. */
2749 /* But often the compare has some CC mode, so check operand
2751 if (HONOR_NANS (XEXP (x
, 0))
2752 || HONOR_NANS (XEXP (x
, 1)))
2758 if (HONOR_SNANS (x
))
2760 /* Often comparison is CC mode, so check operand modes. */
2761 if (HONOR_SNANS (XEXP (x
, 0))
2762 || HONOR_SNANS (XEXP (x
, 1)))
2767 /* Conversion of floating point might trap. */
2768 if (flag_trapping_math
&& HONOR_NANS (XEXP (x
, 0)))
2775 /* These operations don't trap even with floating point. */
2779 /* Any floating arithmetic may trap. */
2780 if (SCALAR_FLOAT_MODE_P (GET_MODE (x
)) && flag_trapping_math
)
2784 fmt
= GET_RTX_FORMAT (code
);
2785 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2789 if (may_trap_p_1 (XEXP (x
, i
), flags
))
2792 else if (fmt
[i
] == 'E')
2795 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2796 if (may_trap_p_1 (XVECEXP (x
, i
, j
), flags
))
2803 /* Return nonzero if evaluating rtx X might cause a trap. */
2806 may_trap_p (const_rtx x
)
2808 return may_trap_p_1 (x
, 0);
2811 /* Same as above, but additionally return nonzero if evaluating rtx X might
2812 cause a fault. We define a fault for the purpose of this function as a
2813 erroneous execution condition that cannot be encountered during the normal
2814 execution of a valid program; the typical example is an unaligned memory
2815 access on a strict alignment machine. The compiler guarantees that it
2816 doesn't generate code that will fault from a valid program, but this
2817 guarantee doesn't mean anything for individual instructions. Consider
2818 the following example:
2820 struct S { int d; union { char *cp; int *ip; }; };
2822 int foo(struct S *s)
2830 on a strict alignment machine. In a valid program, foo will never be
2831 invoked on a structure for which d is equal to 1 and the underlying
2832 unique field of the union not aligned on a 4-byte boundary, but the
2833 expression *s->ip might cause a fault if considered individually.
2835 At the RTL level, potentially problematic expressions will almost always
2836 verify may_trap_p; for example, the above dereference can be emitted as
2837 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
2838 However, suppose that foo is inlined in a caller that causes s->cp to
2839 point to a local character variable and guarantees that s->d is not set
2840 to 1; foo may have been effectively translated into pseudo-RTL as:
2843 (set (reg:SI) (mem:SI (%fp - 7)))
2845 (set (reg:QI) (mem:QI (%fp - 7)))
2847 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
2848 memory reference to a stack slot, but it will certainly cause a fault
2849 on a strict alignment machine. */
2852 may_trap_or_fault_p (const_rtx x
)
2854 return may_trap_p_1 (x
, 1);
2857 /* Return nonzero if X contains a comparison that is not either EQ or NE,
2858 i.e., an inequality. */
2861 inequality_comparisons_p (const_rtx x
)
2865 const enum rtx_code code
= GET_CODE (x
);
2893 len
= GET_RTX_LENGTH (code
);
2894 fmt
= GET_RTX_FORMAT (code
);
2896 for (i
= 0; i
< len
; i
++)
2900 if (inequality_comparisons_p (XEXP (x
, i
)))
2903 else if (fmt
[i
] == 'E')
2906 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2907 if (inequality_comparisons_p (XVECEXP (x
, i
, j
)))
2915 /* Replace any occurrence of FROM in X with TO. The function does
2916 not enter into CONST_DOUBLE for the replace.
2918 Note that copying is not done so X must not be shared unless all copies
2921 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
2922 those pointer-equal ones. */
2925 replace_rtx (rtx x
, rtx from
, rtx to
, bool all_regs
)
2933 /* Allow this function to make replacements in EXPR_LISTs. */
2940 && REGNO (x
) == REGNO (from
))
2942 gcc_assert (GET_MODE (x
) == GET_MODE (from
));
2945 else if (GET_CODE (x
) == SUBREG
)
2947 rtx new_rtx
= replace_rtx (SUBREG_REG (x
), from
, to
, all_regs
);
2949 if (CONST_INT_P (new_rtx
))
2951 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
2952 GET_MODE (SUBREG_REG (x
)),
2957 SUBREG_REG (x
) = new_rtx
;
2961 else if (GET_CODE (x
) == ZERO_EXTEND
)
2963 rtx new_rtx
= replace_rtx (XEXP (x
, 0), from
, to
, all_regs
);
2965 if (CONST_INT_P (new_rtx
))
2967 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
2968 new_rtx
, GET_MODE (XEXP (x
, 0)));
2972 XEXP (x
, 0) = new_rtx
;
2977 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
2978 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
2981 XEXP (x
, i
) = replace_rtx (XEXP (x
, i
), from
, to
, all_regs
);
2982 else if (fmt
[i
] == 'E')
2983 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2984 XVECEXP (x
, i
, j
) = replace_rtx (XVECEXP (x
, i
, j
),
2985 from
, to
, all_regs
);
2991 /* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
2992 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
2995 replace_label (rtx
*loc
, rtx old_label
, rtx new_label
, bool update_label_nuses
)
2997 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
2999 if (JUMP_TABLE_DATA_P (x
))
3002 rtvec vec
= XVEC (x
, GET_CODE (x
) == ADDR_DIFF_VEC
);
3003 int len
= GET_NUM_ELEM (vec
);
3004 for (int i
= 0; i
< len
; ++i
)
3006 rtx ref
= RTVEC_ELT (vec
, i
);
3007 if (XEXP (ref
, 0) == old_label
)
3009 XEXP (ref
, 0) = new_label
;
3010 if (update_label_nuses
)
3012 ++LABEL_NUSES (new_label
);
3013 --LABEL_NUSES (old_label
);
3020 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3021 field. This is not handled by the iterator because it doesn't
3022 handle unprinted ('0') fields. */
3023 if (JUMP_P (x
) && JUMP_LABEL (x
) == old_label
)
3024 JUMP_LABEL (x
) = new_label
;
3026 subrtx_ptr_iterator::array_type array
;
3027 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3032 if (GET_CODE (x
) == SYMBOL_REF
3033 && CONSTANT_POOL_ADDRESS_P (x
))
3035 rtx c
= get_pool_constant (x
);
3036 if (rtx_referenced_p (old_label
, c
))
3038 /* Create a copy of constant C; replace the label inside
3039 but do not update LABEL_NUSES because uses in constant pool
3041 rtx new_c
= copy_rtx (c
);
3042 replace_label (&new_c
, old_label
, new_label
, false);
3044 /* Add the new constant NEW_C to constant pool and replace
3045 the old reference to constant by new reference. */
3046 rtx new_mem
= force_const_mem (get_pool_mode (x
), new_c
);
3047 *loc
= replace_rtx (x
, x
, XEXP (new_mem
, 0));
3051 if ((GET_CODE (x
) == LABEL_REF
3052 || GET_CODE (x
) == INSN_LIST
)
3053 && XEXP (x
, 0) == old_label
)
3055 XEXP (x
, 0) = new_label
;
3056 if (update_label_nuses
)
3058 ++LABEL_NUSES (new_label
);
3059 --LABEL_NUSES (old_label
);
3067 replace_label_in_insn (rtx_insn
*insn
, rtx old_label
, rtx new_label
,
3068 bool update_label_nuses
)
3070 rtx insn_as_rtx
= insn
;
3071 replace_label (&insn_as_rtx
, old_label
, new_label
, update_label_nuses
);
3072 gcc_checking_assert (insn_as_rtx
== insn
);
3075 /* Return true if X is referenced in BODY. */
3078 rtx_referenced_p (const_rtx x
, const_rtx body
)
3080 subrtx_iterator::array_type array
;
3081 FOR_EACH_SUBRTX (iter
, array
, body
, ALL
)
3082 if (const_rtx y
= *iter
)
3084 /* Check if a label_ref Y refers to label X. */
3085 if (GET_CODE (y
) == LABEL_REF
3087 && LABEL_REF_LABEL (y
) == x
)
3090 if (rtx_equal_p (x
, y
))
3093 /* If Y is a reference to pool constant traverse the constant. */
3094 if (GET_CODE (y
) == SYMBOL_REF
3095 && CONSTANT_POOL_ADDRESS_P (y
))
3096 iter
.substitute (get_pool_constant (y
));
3101 /* If INSN is a tablejump return true and store the label (before jump table) to
3102 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3105 tablejump_p (const rtx_insn
*insn
, rtx
*labelp
, rtx_jump_table_data
**tablep
)
3113 label
= JUMP_LABEL (insn
);
3114 if (label
!= NULL_RTX
&& !ANY_RETURN_P (label
)
3115 && (table
= NEXT_INSN (as_a
<rtx_insn
*> (label
))) != NULL_RTX
3116 && JUMP_TABLE_DATA_P (table
))
3121 *tablep
= as_a
<rtx_jump_table_data
*> (table
);
3127 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3128 constant that is not in the constant pool and not in the condition
3129 of an IF_THEN_ELSE. */
3132 computed_jump_p_1 (const_rtx x
)
3134 const enum rtx_code code
= GET_CODE (x
);
3151 return ! (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
3152 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
3155 return (computed_jump_p_1 (XEXP (x
, 1))
3156 || computed_jump_p_1 (XEXP (x
, 2)));
3162 fmt
= GET_RTX_FORMAT (code
);
3163 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3166 && computed_jump_p_1 (XEXP (x
, i
)))
3169 else if (fmt
[i
] == 'E')
3170 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3171 if (computed_jump_p_1 (XVECEXP (x
, i
, j
)))
3178 /* Return nonzero if INSN is an indirect jump (aka computed jump).
3180 Tablejumps and casesi insns are not considered indirect jumps;
3181 we can recognize them by a (use (label_ref)). */
3184 computed_jump_p (const rtx_insn
*insn
)
3189 rtx pat
= PATTERN (insn
);
3191 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3192 if (JUMP_LABEL (insn
) != NULL
)
3195 if (GET_CODE (pat
) == PARALLEL
)
3197 int len
= XVECLEN (pat
, 0);
3198 int has_use_labelref
= 0;
3200 for (i
= len
- 1; i
>= 0; i
--)
3201 if (GET_CODE (XVECEXP (pat
, 0, i
)) == USE
3202 && (GET_CODE (XEXP (XVECEXP (pat
, 0, i
), 0))
3205 has_use_labelref
= 1;
3209 if (! has_use_labelref
)
3210 for (i
= len
- 1; i
>= 0; i
--)
3211 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3212 && SET_DEST (XVECEXP (pat
, 0, i
)) == pc_rtx
3213 && computed_jump_p_1 (SET_SRC (XVECEXP (pat
, 0, i
))))
3216 else if (GET_CODE (pat
) == SET
3217 && SET_DEST (pat
) == pc_rtx
3218 && computed_jump_p_1 (SET_SRC (pat
)))
3226 /* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3227 the equivalent add insn and pass the result to FN, using DATA as the
3231 for_each_inc_dec_find_inc_dec (rtx mem
, for_each_inc_dec_fn fn
, void *data
)
3233 rtx x
= XEXP (mem
, 0);
3234 switch (GET_CODE (x
))
3239 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3240 rtx r1
= XEXP (x
, 0);
3241 rtx c
= gen_int_mode (size
, GET_MODE (r1
));
3242 return fn (mem
, x
, r1
, r1
, c
, data
);
3248 int size
= GET_MODE_SIZE (GET_MODE (mem
));
3249 rtx r1
= XEXP (x
, 0);
3250 rtx c
= gen_int_mode (-size
, GET_MODE (r1
));
3251 return fn (mem
, x
, r1
, r1
, c
, data
);
3257 rtx r1
= XEXP (x
, 0);
3258 rtx add
= XEXP (x
, 1);
3259 return fn (mem
, x
, r1
, add
, NULL
, data
);
3267 /* Traverse *LOC looking for MEMs that have autoinc addresses.
3268 For each such autoinc operation found, call FN, passing it
3269 the innermost enclosing MEM, the operation itself, the RTX modified
3270 by the operation, two RTXs (the second may be NULL) that, once
3271 added, represent the value to be held by the modified RTX
3272 afterwards, and DATA. FN is to return 0 to continue the
3273 traversal or any other value to have it returned to the caller of
3274 for_each_inc_dec. */
3277 for_each_inc_dec (rtx x
,
3278 for_each_inc_dec_fn fn
,
3281 subrtx_var_iterator::array_type array
;
3282 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
3287 && GET_RTX_CLASS (GET_CODE (XEXP (mem
, 0))) == RTX_AUTOINC
)
3289 int res
= for_each_inc_dec_find_inc_dec (mem
, fn
, data
);
3292 iter
.skip_subrtxes ();
3299 /* Searches X for any reference to REGNO, returning the rtx of the
3300 reference found if any. Otherwise, returns NULL_RTX. */
3303 regno_use_in (unsigned int regno
, rtx x
)
3309 if (REG_P (x
) && REGNO (x
) == regno
)
3312 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3313 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3317 if ((tem
= regno_use_in (regno
, XEXP (x
, i
))))
3320 else if (fmt
[i
] == 'E')
3321 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3322 if ((tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
))))
3329 /* Return a value indicating whether OP, an operand of a commutative
3330 operation, is preferred as the first or second operand. The more
3331 positive the value, the stronger the preference for being the first
3335 commutative_operand_precedence (rtx op
)
3337 enum rtx_code code
= GET_CODE (op
);
3339 /* Constants always become the second operand. Prefer "nice" constants. */
3340 if (code
== CONST_INT
)
3342 if (code
== CONST_WIDE_INT
)
3344 if (code
== CONST_DOUBLE
)
3346 if (code
== CONST_FIXED
)
3348 op
= avoid_constant_pool_reference (op
);
3349 code
= GET_CODE (op
);
3351 switch (GET_RTX_CLASS (code
))
3354 if (code
== CONST_INT
)
3356 if (code
== CONST_WIDE_INT
)
3358 if (code
== CONST_DOUBLE
)
3360 if (code
== CONST_FIXED
)
3365 /* SUBREGs of objects should come second. */
3366 if (code
== SUBREG
&& OBJECT_P (SUBREG_REG (op
)))
3371 /* Complex expressions should be the first, so decrease priority
3372 of objects. Prefer pointer objects over non pointer objects. */
3373 if ((REG_P (op
) && REG_POINTER (op
))
3374 || (MEM_P (op
) && MEM_POINTER (op
)))
3378 case RTX_COMM_ARITH
:
3379 /* Prefer operands that are themselves commutative to be first.
3380 This helps to make things linear. In particular,
3381 (and (and (reg) (reg)) (not (reg))) is canonical. */
3385 /* If only one operand is a binary expression, it will be the first
3386 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3387 is canonical, although it will usually be further simplified. */
3391 /* Then prefer NEG and NOT. */
3392 if (code
== NEG
|| code
== NOT
)
3401 /* Return 1 iff it is necessary to swap operands of commutative operation
3402 in order to canonicalize expression. */
3405 swap_commutative_operands_p (rtx x
, rtx y
)
3407 return (commutative_operand_precedence (x
)
3408 < commutative_operand_precedence (y
));
3411 /* Return 1 if X is an autoincrement side effect and the register is
3412 not the stack pointer. */
3414 auto_inc_p (const_rtx x
)
3416 switch (GET_CODE (x
))
3424 /* There are no REG_INC notes for SP. */
3425 if (XEXP (x
, 0) != stack_pointer_rtx
)
3433 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3435 loc_mentioned_in_p (rtx
*loc
, const_rtx in
)
3444 code
= GET_CODE (in
);
3445 fmt
= GET_RTX_FORMAT (code
);
3446 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3450 if (loc
== &XEXP (in
, i
) || loc_mentioned_in_p (loc
, XEXP (in
, i
)))
3453 else if (fmt
[i
] == 'E')
3454 for (j
= XVECLEN (in
, i
) - 1; j
>= 0; j
--)
3455 if (loc
== &XVECEXP (in
, i
, j
)
3456 || loc_mentioned_in_p (loc
, XVECEXP (in
, i
, j
)))
3462 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE,
3463 and SUBREG_BYTE, return the bit offset where the subreg begins
3464 (counting from the least significant bit of the operand). */
3467 subreg_lsb_1 (machine_mode outer_mode
,
3468 machine_mode inner_mode
,
3469 unsigned int subreg_byte
)
3471 unsigned int bitpos
;
3475 /* A paradoxical subreg begins at bit position 0. */
3476 if (GET_MODE_PRECISION (outer_mode
) > GET_MODE_PRECISION (inner_mode
))
3479 if (WORDS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
3480 /* If the subreg crosses a word boundary ensure that
3481 it also begins and ends on a word boundary. */
3482 gcc_assert (!((subreg_byte
% UNITS_PER_WORD
3483 + GET_MODE_SIZE (outer_mode
)) > UNITS_PER_WORD
3484 && (subreg_byte
% UNITS_PER_WORD
3485 || GET_MODE_SIZE (outer_mode
) % UNITS_PER_WORD
)));
3487 if (WORDS_BIG_ENDIAN
)
3488 word
= (GET_MODE_SIZE (inner_mode
)
3489 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) / UNITS_PER_WORD
;
3491 word
= subreg_byte
/ UNITS_PER_WORD
;
3492 bitpos
= word
* BITS_PER_WORD
;
3494 if (BYTES_BIG_ENDIAN
)
3495 byte
= (GET_MODE_SIZE (inner_mode
)
3496 - (subreg_byte
+ GET_MODE_SIZE (outer_mode
))) % UNITS_PER_WORD
;
3498 byte
= subreg_byte
% UNITS_PER_WORD
;
3499 bitpos
+= byte
* BITS_PER_UNIT
;
3504 /* Given a subreg X, return the bit offset where the subreg begins
3505 (counting from the least significant bit of the reg). */
3508 subreg_lsb (const_rtx x
)
3510 return subreg_lsb_1 (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
3514 /* Fill in information about a subreg of a hard register.
3515 xregno - A regno of an inner hard subreg_reg (or what will become one).
3516 xmode - The mode of xregno.
3517 offset - The byte offset.
3518 ymode - The mode of a top level SUBREG (or what may become one).
3519 info - Pointer to structure to fill in.
3521 Rather than considering one particular inner register (and thus one
3522 particular "outer" register) in isolation, this function really uses
3523 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
3524 function does not check whether adding INFO->offset to XREGNO gives
3525 a valid hard register; even if INFO->offset + XREGNO is out of range,
3526 there might be another register of the same type that is in range.
3527 Likewise it doesn't check whether HARD_REGNO_MODE_OK accepts the new
3528 register, since that can depend on things like whether the final
3529 register number is even or odd. Callers that want to check whether
3530 this particular subreg can be replaced by a simple (reg ...) should
3531 use simplify_subreg_regno. */
3534 subreg_get_info (unsigned int xregno
, machine_mode xmode
,
3535 unsigned int offset
, machine_mode ymode
,
3536 struct subreg_info
*info
)
3538 int nregs_xmode
, nregs_ymode
;
3539 int mode_multiple
, nregs_multiple
;
3540 int offset_adj
, y_offset
, y_offset_adj
;
3541 int regsize_xmode
, regsize_ymode
;
3544 gcc_assert (xregno
< FIRST_PSEUDO_REGISTER
);
3548 /* If there are holes in a non-scalar mode in registers, we expect
3549 that it is made up of its units concatenated together. */
3550 if (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
))
3552 machine_mode xmode_unit
;
3554 nregs_xmode
= HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode
);
3555 xmode_unit
= GET_MODE_INNER (xmode
);
3556 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode_unit
));
3557 gcc_assert (nregs_xmode
3558 == (GET_MODE_NUNITS (xmode
)
3559 * HARD_REGNO_NREGS_WITH_PADDING (xregno
, xmode_unit
)));
3560 gcc_assert (hard_regno_nregs
[xregno
][xmode
]
3561 == (hard_regno_nregs
[xregno
][xmode_unit
]
3562 * GET_MODE_NUNITS (xmode
)));
3564 /* You can only ask for a SUBREG of a value with holes in the middle
3565 if you don't cross the holes. (Such a SUBREG should be done by
3566 picking a different register class, or doing it in memory if
3567 necessary.) An example of a value with holes is XCmode on 32-bit
3568 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3569 3 for each part, but in memory it's two 128-bit parts.
3570 Padding is assumed to be at the end (not necessarily the 'high part')
3572 if ((offset
/ GET_MODE_SIZE (xmode_unit
) + 1
3573 < GET_MODE_NUNITS (xmode
))
3574 && (offset
/ GET_MODE_SIZE (xmode_unit
)
3575 != ((offset
+ GET_MODE_SIZE (ymode
) - 1)
3576 / GET_MODE_SIZE (xmode_unit
))))
3578 info
->representable_p
= false;
3583 nregs_xmode
= hard_regno_nregs
[xregno
][xmode
];
3585 nregs_ymode
= hard_regno_nregs
[xregno
][ymode
];
3587 /* Paradoxical subregs are otherwise valid. */
3590 && GET_MODE_PRECISION (ymode
) > GET_MODE_PRECISION (xmode
))
3592 info
->representable_p
= true;
3593 /* If this is a big endian paradoxical subreg, which uses more
3594 actual hard registers than the original register, we must
3595 return a negative offset so that we find the proper highpart
3597 if (GET_MODE_SIZE (ymode
) > UNITS_PER_WORD
3598 ? REG_WORDS_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
3599 info
->offset
= nregs_xmode
- nregs_ymode
;
3602 info
->nregs
= nregs_ymode
;
3606 /* If registers store different numbers of bits in the different
3607 modes, we cannot generally form this subreg. */
3608 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno
, xmode
)
3609 && !HARD_REGNO_NREGS_HAS_PADDING (xregno
, ymode
)
3610 && (GET_MODE_SIZE (xmode
) % nregs_xmode
) == 0
3611 && (GET_MODE_SIZE (ymode
) % nregs_ymode
) == 0)
3613 regsize_xmode
= GET_MODE_SIZE (xmode
) / nregs_xmode
;
3614 regsize_ymode
= GET_MODE_SIZE (ymode
) / nregs_ymode
;
3615 if (!rknown
&& regsize_xmode
> regsize_ymode
&& nregs_ymode
> 1)
3617 info
->representable_p
= false;
3619 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3620 info
->offset
= offset
/ regsize_xmode
;
3623 if (!rknown
&& regsize_ymode
> regsize_xmode
&& nregs_xmode
> 1)
3625 info
->representable_p
= false;
3627 = (GET_MODE_SIZE (ymode
) + regsize_xmode
- 1) / regsize_xmode
;
3628 info
->offset
= offset
/ regsize_xmode
;
3631 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
3632 would go outside of XMODE. */
3634 && GET_MODE_SIZE (ymode
) + offset
> GET_MODE_SIZE (xmode
))
3636 info
->representable_p
= false;
3637 info
->nregs
= nregs_ymode
;
3638 info
->offset
= offset
/ regsize_xmode
;
3641 /* Quick exit for the simple and common case of extracting whole
3642 subregisters from a multiregister value. */
3643 /* ??? It would be better to integrate this into the code below,
3644 if we can generalize the concept enough and figure out how
3645 odd-sized modes can coexist with the other weird cases we support. */
3647 && WORDS_BIG_ENDIAN
== REG_WORDS_BIG_ENDIAN
3648 && regsize_xmode
== regsize_ymode
3649 && (offset
% regsize_ymode
) == 0)
3651 info
->representable_p
= true;
3652 info
->nregs
= nregs_ymode
;
3653 info
->offset
= offset
/ regsize_ymode
;
3654 gcc_assert (info
->offset
+ info
->nregs
<= nregs_xmode
);
3659 /* Lowpart subregs are otherwise valid. */
3660 if (!rknown
&& offset
== subreg_lowpart_offset (ymode
, xmode
))
3662 info
->representable_p
= true;
3665 if (offset
== 0 || nregs_xmode
== nregs_ymode
)
3668 info
->nregs
= nregs_ymode
;
3673 /* This should always pass, otherwise we don't know how to verify
3674 the constraint. These conditions may be relaxed but
3675 subreg_regno_offset would need to be redesigned. */
3676 gcc_assert ((GET_MODE_SIZE (xmode
) % GET_MODE_SIZE (ymode
)) == 0);
3677 gcc_assert ((nregs_xmode
% nregs_ymode
) == 0);
3679 if (WORDS_BIG_ENDIAN
!= REG_WORDS_BIG_ENDIAN
3680 && GET_MODE_SIZE (xmode
) > UNITS_PER_WORD
)
3682 HOST_WIDE_INT xsize
= GET_MODE_SIZE (xmode
);
3683 HOST_WIDE_INT ysize
= GET_MODE_SIZE (ymode
);
3684 HOST_WIDE_INT off_low
= offset
& (ysize
- 1);
3685 HOST_WIDE_INT off_high
= offset
& ~(ysize
- 1);
3686 offset
= (xsize
- ysize
- off_high
) | off_low
;
3688 /* The XMODE value can be seen as a vector of NREGS_XMODE
3689 values. The subreg must represent a lowpart of given field.
3690 Compute what field it is. */
3691 offset_adj
= offset
;
3692 offset_adj
-= subreg_lowpart_offset (ymode
,
3693 mode_for_size (GET_MODE_BITSIZE (xmode
)
3697 /* Size of ymode must not be greater than the size of xmode. */
3698 mode_multiple
= GET_MODE_SIZE (xmode
) / GET_MODE_SIZE (ymode
);
3699 gcc_assert (mode_multiple
!= 0);
3701 y_offset
= offset
/ GET_MODE_SIZE (ymode
);
3702 y_offset_adj
= offset_adj
/ GET_MODE_SIZE (ymode
);
3703 nregs_multiple
= nregs_xmode
/ nregs_ymode
;
3705 gcc_assert ((offset_adj
% GET_MODE_SIZE (ymode
)) == 0);
3706 gcc_assert ((mode_multiple
% nregs_multiple
) == 0);
3710 info
->representable_p
= (!(y_offset_adj
% (mode_multiple
/ nregs_multiple
)));
3713 info
->offset
= (y_offset
/ (mode_multiple
/ nregs_multiple
)) * nregs_ymode
;
3714 info
->nregs
= nregs_ymode
;
3717 /* This function returns the regno offset of a subreg expression.
3718 xregno - A regno of an inner hard subreg_reg (or what will become one).
3719 xmode - The mode of xregno.
3720 offset - The byte offset.
3721 ymode - The mode of a top level SUBREG (or what may become one).
3722 RETURN - The regno offset which would be used. */
3724 subreg_regno_offset (unsigned int xregno
, machine_mode xmode
,
3725 unsigned int offset
, machine_mode ymode
)
3727 struct subreg_info info
;
3728 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3732 /* This function returns true when the offset is representable via
3733 subreg_offset in the given regno.
3734 xregno - A regno of an inner hard subreg_reg (or what will become one).
3735 xmode - The mode of xregno.
3736 offset - The byte offset.
3737 ymode - The mode of a top level SUBREG (or what may become one).
3738 RETURN - Whether the offset is representable. */
3740 subreg_offset_representable_p (unsigned int xregno
, machine_mode xmode
,
3741 unsigned int offset
, machine_mode ymode
)
3743 struct subreg_info info
;
3744 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3745 return info
.representable_p
;
3748 /* Return the number of a YMODE register to which
3750 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
3752 can be simplified. Return -1 if the subreg can't be simplified.
3754 XREGNO is a hard register number. */
3757 simplify_subreg_regno (unsigned int xregno
, machine_mode xmode
,
3758 unsigned int offset
, machine_mode ymode
)
3760 struct subreg_info info
;
3761 unsigned int yregno
;
3763 #ifdef CANNOT_CHANGE_MODE_CLASS
3764 /* Give the backend a chance to disallow the mode change. */
3765 if (GET_MODE_CLASS (xmode
) != MODE_COMPLEX_INT
3766 && GET_MODE_CLASS (xmode
) != MODE_COMPLEX_FLOAT
3767 && REG_CANNOT_CHANGE_MODE_P (xregno
, xmode
, ymode
)
3768 /* We can use mode change in LRA for some transformations. */
3769 && ! lra_in_progress
)
3773 /* We shouldn't simplify stack-related registers. */
3774 if ((!reload_completed
|| frame_pointer_needed
)
3775 && xregno
== FRAME_POINTER_REGNUM
)
3778 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
3779 && xregno
== ARG_POINTER_REGNUM
)
3782 if (xregno
== STACK_POINTER_REGNUM
3783 /* We should convert hard stack register in LRA if it is
3785 && ! lra_in_progress
)
3788 /* Try to get the register offset. */
3789 subreg_get_info (xregno
, xmode
, offset
, ymode
, &info
);
3790 if (!info
.representable_p
)
3793 /* Make sure that the offsetted register value is in range. */
3794 yregno
= xregno
+ info
.offset
;
3795 if (!HARD_REGISTER_NUM_P (yregno
))
3798 /* See whether (reg:YMODE YREGNO) is valid.
3800 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
3801 This is a kludge to work around how complex FP arguments are passed
3802 on IA-64 and should be fixed. See PR target/49226. */
3803 if (!HARD_REGNO_MODE_OK (yregno
, ymode
)
3804 && HARD_REGNO_MODE_OK (xregno
, xmode
))
3807 return (int) yregno
;
3810 /* Return the final regno that a subreg expression refers to. */
3812 subreg_regno (const_rtx x
)
3815 rtx subreg
= SUBREG_REG (x
);
3816 int regno
= REGNO (subreg
);
3818 ret
= regno
+ subreg_regno_offset (regno
,
3826 /* Return the number of registers that a subreg expression refers
3829 subreg_nregs (const_rtx x
)
3831 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x
)), x
);
3834 /* Return the number of registers that a subreg REG with REGNO
3835 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
3836 changed so that the regno can be passed in. */
3839 subreg_nregs_with_regno (unsigned int regno
, const_rtx x
)
3841 struct subreg_info info
;
3842 rtx subreg
= SUBREG_REG (x
);
3844 subreg_get_info (regno
, GET_MODE (subreg
), SUBREG_BYTE (x
), GET_MODE (x
),
3850 struct parms_set_data
3856 /* Helper function for noticing stores to parameter registers. */
3858 parms_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
3860 struct parms_set_data
*const d
= (struct parms_set_data
*) data
;
3861 if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
3862 && TEST_HARD_REG_BIT (d
->regs
, REGNO (x
)))
3864 CLEAR_HARD_REG_BIT (d
->regs
, REGNO (x
));
3869 /* Look backward for first parameter to be loaded.
3870 Note that loads of all parameters will not necessarily be
3871 found if CSE has eliminated some of them (e.g., an argument
3872 to the outer function is passed down as a parameter).
3873 Do not skip BOUNDARY. */
3875 find_first_parameter_load (rtx_insn
*call_insn
, rtx_insn
*boundary
)
3877 struct parms_set_data parm
;
3879 rtx_insn
*before
, *first_set
;
3881 /* Since different machines initialize their parameter registers
3882 in different orders, assume nothing. Collect the set of all
3883 parameter registers. */
3884 CLEAR_HARD_REG_SET (parm
.regs
);
3886 for (p
= CALL_INSN_FUNCTION_USAGE (call_insn
); p
; p
= XEXP (p
, 1))
3887 if (GET_CODE (XEXP (p
, 0)) == USE
3888 && REG_P (XEXP (XEXP (p
, 0), 0)))
3890 gcc_assert (REGNO (XEXP (XEXP (p
, 0), 0)) < FIRST_PSEUDO_REGISTER
);
3892 /* We only care about registers which can hold function
3894 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p
, 0), 0))))
3897 SET_HARD_REG_BIT (parm
.regs
, REGNO (XEXP (XEXP (p
, 0), 0)));
3901 first_set
= call_insn
;
3903 /* Search backward for the first set of a register in this set. */
3904 while (parm
.nregs
&& before
!= boundary
)
3906 before
= PREV_INSN (before
);
3908 /* It is possible that some loads got CSEed from one call to
3909 another. Stop in that case. */
3910 if (CALL_P (before
))
3913 /* Our caller needs either ensure that we will find all sets
3914 (in case code has not been optimized yet), or take care
3915 for possible labels in a way by setting boundary to preceding
3917 if (LABEL_P (before
))
3919 gcc_assert (before
== boundary
);
3923 if (INSN_P (before
))
3925 int nregs_old
= parm
.nregs
;
3926 note_stores (PATTERN (before
), parms_set
, &parm
);
3927 /* If we found something that did not set a parameter reg,
3928 we're done. Do not keep going, as that might result
3929 in hoisting an insn before the setting of a pseudo
3930 that is used by the hoisted insn. */
3931 if (nregs_old
!= parm
.nregs
)
3940 /* Return true if we should avoid inserting code between INSN and preceding
3941 call instruction. */
3944 keep_with_call_p (const rtx_insn
*insn
)
3948 if (INSN_P (insn
) && (set
= single_set (insn
)) != NULL
)
3950 if (REG_P (SET_DEST (set
))
3951 && REGNO (SET_DEST (set
)) < FIRST_PSEUDO_REGISTER
3952 && fixed_regs
[REGNO (SET_DEST (set
))]
3953 && general_operand (SET_SRC (set
), VOIDmode
))
3955 if (REG_P (SET_SRC (set
))
3956 && targetm
.calls
.function_value_regno_p (REGNO (SET_SRC (set
)))
3957 && REG_P (SET_DEST (set
))
3958 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3960 /* There may be a stack pop just after the call and before the store
3961 of the return register. Search for the actual store when deciding
3962 if we can break or not. */
3963 if (SET_DEST (set
) == stack_pointer_rtx
)
3965 /* This CONST_CAST is okay because next_nonnote_insn just
3966 returns its argument and we assign it to a const_rtx
3969 = next_nonnote_insn (const_cast<rtx_insn
*> (insn
));
3970 if (i2
&& keep_with_call_p (i2
))
3977 /* Return true if LABEL is a target of JUMP_INSN. This applies only
3978 to non-complex jumps. That is, direct unconditional, conditional,
3979 and tablejumps, but not computed jumps or returns. It also does
3980 not apply to the fallthru case of a conditional jump. */
3983 label_is_jump_target_p (const_rtx label
, const rtx_insn
*jump_insn
)
3985 rtx tmp
= JUMP_LABEL (jump_insn
);
3986 rtx_jump_table_data
*table
;
3991 if (tablejump_p (jump_insn
, NULL
, &table
))
3993 rtvec vec
= table
->get_labels ();
3994 int i
, veclen
= GET_NUM_ELEM (vec
);
3996 for (i
= 0; i
< veclen
; ++i
)
3997 if (XEXP (RTVEC_ELT (vec
, i
), 0) == label
)
4001 if (find_reg_note (jump_insn
, REG_LABEL_TARGET
, label
))
4008 /* Return an estimate of the cost of computing rtx X.
4009 One use is in cse, to decide which expression to keep in the hash table.
4010 Another is in rtl generation, to pick the cheapest way to multiply.
4011 Other uses like the latter are expected in the future.
4013 X appears as operand OPNO in an expression with code OUTER_CODE.
4014 SPEED specifies whether costs optimized for speed or size should
4018 rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer_code
,
4019 int opno
, bool speed
)
4030 if (GET_MODE (x
) != VOIDmode
)
4031 mode
= GET_MODE (x
);
4033 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4034 many insns, taking N times as long. */
4035 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4039 /* Compute the default costs of certain things.
4040 Note that targetm.rtx_costs can override the defaults. */
4042 code
= GET_CODE (x
);
4046 /* Multiplication has time-complexity O(N*N), where N is the
4047 number of units (translated from digits) when using
4048 schoolbook long multiplication. */
4049 total
= factor
* factor
* COSTS_N_INSNS (5);
4055 /* Similarly, complexity for schoolbook long division. */
4056 total
= factor
* factor
* COSTS_N_INSNS (7);
4059 /* Used in combine.c as a marker. */
4063 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4064 the mode for the factor. */
4065 mode
= GET_MODE (SET_DEST (x
));
4066 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4071 total
= factor
* COSTS_N_INSNS (1);
4081 /* If we can't tie these modes, make this expensive. The larger
4082 the mode, the more expensive it is. */
4083 if (! MODES_TIEABLE_P (mode
, GET_MODE (SUBREG_REG (x
))))
4084 return COSTS_N_INSNS (2 + factor
);
4088 if (targetm
.rtx_costs (x
, mode
, outer_code
, opno
, &total
, speed
))
4093 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4094 which is already in total. */
4096 fmt
= GET_RTX_FORMAT (code
);
4097 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4099 total
+= rtx_cost (XEXP (x
, i
), mode
, code
, i
, speed
);
4100 else if (fmt
[i
] == 'E')
4101 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4102 total
+= rtx_cost (XVECEXP (x
, i
, j
), mode
, code
, i
, speed
);
4107 /* Fill in the structure C with information about both speed and size rtx
4108 costs for X, which is operand OPNO in an expression with code OUTER. */
4111 get_full_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
, int opno
,
4112 struct full_rtx_costs
*c
)
4114 c
->speed
= rtx_cost (x
, mode
, outer
, opno
, true);
4115 c
->size
= rtx_cost (x
, mode
, outer
, opno
, false);
4119 /* Return cost of address expression X.
4120 Expect that X is properly formed address reference.
4122 SPEED parameter specify whether costs optimized for speed or size should
4126 address_cost (rtx x
, machine_mode mode
, addr_space_t as
, bool speed
)
4128 /* We may be asked for cost of various unusual addresses, such as operands
4129 of push instruction. It is not worthwhile to complicate writing
4130 of the target hook by such cases. */
4132 if (!memory_address_addr_space_p (mode
, x
, as
))
4135 return targetm
.address_cost (x
, mode
, as
, speed
);
4138 /* If the target doesn't override, compute the cost as with arithmetic. */
4141 default_address_cost (rtx x
, machine_mode
, addr_space_t
, bool speed
)
4143 return rtx_cost (x
, Pmode
, MEM
, 0, speed
);
4147 unsigned HOST_WIDE_INT
4148 nonzero_bits (const_rtx x
, machine_mode mode
)
4150 return cached_nonzero_bits (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4154 num_sign_bit_copies (const_rtx x
, machine_mode mode
)
4156 return cached_num_sign_bit_copies (x
, mode
, NULL_RTX
, VOIDmode
, 0);
4159 /* Return true if nonzero_bits1 might recurse into both operands
4163 nonzero_bits_binary_arith_p (const_rtx x
)
4165 if (!ARITHMETIC_P (x
))
4167 switch (GET_CODE (x
))
4189 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4190 It avoids exponential behavior in nonzero_bits1 when X has
4191 identical subexpressions on the first or the second level. */
4193 static unsigned HOST_WIDE_INT
4194 cached_nonzero_bits (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4195 machine_mode known_mode
,
4196 unsigned HOST_WIDE_INT known_ret
)
4198 if (x
== known_x
&& mode
== known_mode
)
4201 /* Try to find identical subexpressions. If found call
4202 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4203 precomputed value for the subexpression as KNOWN_RET. */
4205 if (nonzero_bits_binary_arith_p (x
))
4207 rtx x0
= XEXP (x
, 0);
4208 rtx x1
= XEXP (x
, 1);
4210 /* Check the first level. */
4212 return nonzero_bits1 (x
, mode
, x0
, mode
,
4213 cached_nonzero_bits (x0
, mode
, known_x
,
4214 known_mode
, known_ret
));
4216 /* Check the second level. */
4217 if (nonzero_bits_binary_arith_p (x0
)
4218 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4219 return nonzero_bits1 (x
, mode
, x1
, mode
,
4220 cached_nonzero_bits (x1
, mode
, known_x
,
4221 known_mode
, known_ret
));
4223 if (nonzero_bits_binary_arith_p (x1
)
4224 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4225 return nonzero_bits1 (x
, mode
, x0
, mode
,
4226 cached_nonzero_bits (x0
, mode
, known_x
,
4227 known_mode
, known_ret
));
4230 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
4233 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4234 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4235 is less useful. We can't allow both, because that results in exponential
4236 run time recursion. There is a nullstone testcase that triggered
4237 this. This macro avoids accidental uses of num_sign_bit_copies. */
4238 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4240 /* Given an expression, X, compute which bits in X can be nonzero.
4241 We don't care about bits outside of those defined in MODE.
4243 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4244 an arithmetic operation, we can do better. */
4246 static unsigned HOST_WIDE_INT
4247 nonzero_bits1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4248 machine_mode known_mode
,
4249 unsigned HOST_WIDE_INT known_ret
)
4251 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
4252 unsigned HOST_WIDE_INT inner_nz
;
4254 machine_mode inner_mode
;
4255 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
4257 /* For floating-point and vector values, assume all bits are needed. */
4258 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
)
4259 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4262 /* If X is wider than MODE, use its mode instead. */
4263 if (GET_MODE_PRECISION (GET_MODE (x
)) > mode_width
)
4265 mode
= GET_MODE (x
);
4266 nonzero
= GET_MODE_MASK (mode
);
4267 mode_width
= GET_MODE_PRECISION (mode
);
4270 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
4271 /* Our only callers in this case look for single bit values. So
4272 just return the mode mask. Those tests will then be false. */
4275 /* If MODE is wider than X, but both are a single word for both the host
4276 and target machines, we can compute this from which bits of the
4277 object might be nonzero in its own mode, taking into account the fact
4278 that on many CISC machines, accessing an object in a wider mode
4279 causes the high-order bits to become undefined. So they are
4280 not known to be zero. */
4282 if (!WORD_REGISTER_OPERATIONS
4283 && GET_MODE (x
) != VOIDmode
4284 && GET_MODE (x
) != mode
4285 && GET_MODE_PRECISION (GET_MODE (x
)) <= BITS_PER_WORD
4286 && GET_MODE_PRECISION (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
4287 && GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (GET_MODE (x
)))
4289 nonzero
&= cached_nonzero_bits (x
, GET_MODE (x
),
4290 known_x
, known_mode
, known_ret
);
4291 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
4295 /* Please keep nonzero_bits_binary_arith_p above in sync with
4296 the code in the switch below. */
4297 code
= GET_CODE (x
);
4301 #if defined(POINTERS_EXTEND_UNSIGNED)
4302 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4303 all the bits above ptr_mode are known to be zero. */
4304 /* As we do not know which address space the pointer is referring to,
4305 we can do this only if the target does not support different pointer
4306 or address modes depending on the address space. */
4307 if (target_default_pointer_address_modes_p ()
4308 && POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4310 && !targetm
.have_ptr_extend ())
4311 nonzero
&= GET_MODE_MASK (ptr_mode
);
4314 /* Include declared information about alignment of pointers. */
4315 /* ??? We don't properly preserve REG_POINTER changes across
4316 pointer-to-integer casts, so we can't trust it except for
4317 things that we know must be pointers. See execute/960116-1.c. */
4318 if ((x
== stack_pointer_rtx
4319 || x
== frame_pointer_rtx
4320 || x
== arg_pointer_rtx
)
4321 && REGNO_POINTER_ALIGN (REGNO (x
)))
4323 unsigned HOST_WIDE_INT alignment
4324 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
4326 #ifdef PUSH_ROUNDING
4327 /* If PUSH_ROUNDING is defined, it is possible for the
4328 stack to be momentarily aligned only to that amount,
4329 so we pick the least alignment. */
4330 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
4331 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
4335 nonzero
&= ~(alignment
- 1);
4339 unsigned HOST_WIDE_INT nonzero_for_hook
= nonzero
;
4340 rtx new_rtx
= rtl_hooks
.reg_nonzero_bits (x
, mode
, known_x
,
4341 known_mode
, known_ret
,
4345 nonzero_for_hook
&= cached_nonzero_bits (new_rtx
, mode
, known_x
,
4346 known_mode
, known_ret
);
4348 return nonzero_for_hook
;
4352 /* If X is negative in MODE, sign-extend the value. */
4353 if (SHORT_IMMEDIATES_SIGN_EXTEND
&& INTVAL (x
) > 0
4354 && mode_width
< BITS_PER_WORD
4355 && (UINTVAL (x
) & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
4357 return UINTVAL (x
) | (HOST_WIDE_INT_M1U
<< mode_width
);
4362 #ifdef LOAD_EXTEND_OP
4363 /* In many, if not most, RISC machines, reading a byte from memory
4364 zeros the rest of the register. Noticing that fact saves a lot
4365 of extra zero-extends. */
4366 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
4367 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
4372 case UNEQ
: case LTGT
:
4373 case GT
: case GTU
: case UNGT
:
4374 case LT
: case LTU
: case UNLT
:
4375 case GE
: case GEU
: case UNGE
:
4376 case LE
: case LEU
: case UNLE
:
4377 case UNORDERED
: case ORDERED
:
4378 /* If this produces an integer result, we know which bits are set.
4379 Code here used to clear bits outside the mode of X, but that is
4381 /* Mind that MODE is the mode the caller wants to look at this
4382 operation in, and not the actual operation mode. We can wind
4383 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4384 that describes the results of a vector compare. */
4385 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
4386 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
4387 nonzero
= STORE_FLAG_VALUE
;
4392 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4393 and num_sign_bit_copies. */
4394 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4395 == GET_MODE_PRECISION (GET_MODE (x
)))
4399 if (GET_MODE_PRECISION (GET_MODE (x
)) < mode_width
)
4400 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
4405 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4406 and num_sign_bit_copies. */
4407 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
4408 == GET_MODE_PRECISION (GET_MODE (x
)))
4414 nonzero
&= (cached_nonzero_bits (XEXP (x
, 0), mode
,
4415 known_x
, known_mode
, known_ret
)
4416 & GET_MODE_MASK (mode
));
4420 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4421 known_x
, known_mode
, known_ret
);
4422 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4423 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4427 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4428 Otherwise, show all the bits in the outer mode but not the inner
4430 inner_nz
= cached_nonzero_bits (XEXP (x
, 0), mode
,
4431 known_x
, known_mode
, known_ret
);
4432 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
4434 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
4435 if (val_signbit_known_set_p (GET_MODE (XEXP (x
, 0)), inner_nz
))
4436 inner_nz
|= (GET_MODE_MASK (mode
)
4437 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
4440 nonzero
&= inner_nz
;
4444 nonzero
&= cached_nonzero_bits (XEXP (x
, 0), mode
,
4445 known_x
, known_mode
, known_ret
)
4446 & cached_nonzero_bits (XEXP (x
, 1), mode
,
4447 known_x
, known_mode
, known_ret
);
4451 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
4453 unsigned HOST_WIDE_INT nonzero0
4454 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4455 known_x
, known_mode
, known_ret
);
4457 /* Don't call nonzero_bits for the second time if it cannot change
4459 if ((nonzero
& nonzero0
) != nonzero
)
4461 | cached_nonzero_bits (XEXP (x
, 1), mode
,
4462 known_x
, known_mode
, known_ret
);
4466 case PLUS
: case MINUS
:
4468 case DIV
: case UDIV
:
4469 case MOD
: case UMOD
:
4470 /* We can apply the rules of arithmetic to compute the number of
4471 high- and low-order zero bits of these operations. We start by
4472 computing the width (position of the highest-order nonzero bit)
4473 and the number of low-order zero bits for each value. */
4475 unsigned HOST_WIDE_INT nz0
4476 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4477 known_x
, known_mode
, known_ret
);
4478 unsigned HOST_WIDE_INT nz1
4479 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4480 known_x
, known_mode
, known_ret
);
4481 int sign_index
= GET_MODE_PRECISION (GET_MODE (x
)) - 1;
4482 int width0
= floor_log2 (nz0
) + 1;
4483 int width1
= floor_log2 (nz1
) + 1;
4484 int low0
= ctz_or_zero (nz0
);
4485 int low1
= ctz_or_zero (nz1
);
4486 unsigned HOST_WIDE_INT op0_maybe_minusp
4487 = nz0
& (HOST_WIDE_INT_1U
<< sign_index
);
4488 unsigned HOST_WIDE_INT op1_maybe_minusp
4489 = nz1
& (HOST_WIDE_INT_1U
<< sign_index
);
4490 unsigned int result_width
= mode_width
;
4496 result_width
= MAX (width0
, width1
) + 1;
4497 result_low
= MIN (low0
, low1
);
4500 result_low
= MIN (low0
, low1
);
4503 result_width
= width0
+ width1
;
4504 result_low
= low0
+ low1
;
4509 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4510 result_width
= width0
;
4515 result_width
= width0
;
4520 if (!op0_maybe_minusp
&& !op1_maybe_minusp
)
4521 result_width
= MIN (width0
, width1
);
4522 result_low
= MIN (low0
, low1
);
4527 result_width
= MIN (width0
, width1
);
4528 result_low
= MIN (low0
, low1
);
4534 if (result_width
< mode_width
)
4535 nonzero
&= (HOST_WIDE_INT_1U
<< result_width
) - 1;
4538 nonzero
&= ~((HOST_WIDE_INT_1U
<< result_low
) - 1);
4543 if (CONST_INT_P (XEXP (x
, 1))
4544 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
4545 nonzero
&= (HOST_WIDE_INT_1U
<< INTVAL (XEXP (x
, 1))) - 1;
4549 /* If this is a SUBREG formed for a promoted variable that has
4550 been zero-extended, we know that at least the high-order bits
4551 are zero, though others might be too. */
4553 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
4554 nonzero
= GET_MODE_MASK (GET_MODE (x
))
4555 & cached_nonzero_bits (SUBREG_REG (x
), GET_MODE (x
),
4556 known_x
, known_mode
, known_ret
);
4558 inner_mode
= GET_MODE (SUBREG_REG (x
));
4559 /* If the inner mode is a single word for both the host and target
4560 machines, we can compute this from which bits of the inner
4561 object might be nonzero. */
4562 if (GET_MODE_PRECISION (inner_mode
) <= BITS_PER_WORD
4563 && (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
))
4565 nonzero
&= cached_nonzero_bits (SUBREG_REG (x
), mode
,
4566 known_x
, known_mode
, known_ret
);
4568 #ifdef LOAD_EXTEND_OP
4569 /* If this is a typical RISC machine, we only have to worry
4570 about the way loads are extended. */
4571 if (WORD_REGISTER_OPERATIONS
4572 && ((LOAD_EXTEND_OP (inner_mode
) == SIGN_EXTEND
4573 ? val_signbit_known_set_p (inner_mode
, nonzero
)
4574 : LOAD_EXTEND_OP (inner_mode
) != ZERO_EXTEND
)
4575 || !MEM_P (SUBREG_REG (x
))))
4578 /* On many CISC machines, accessing an object in a wider mode
4579 causes the high-order bits to become undefined. So they are
4580 not known to be zero. */
4581 if (GET_MODE_PRECISION (GET_MODE (x
))
4582 > GET_MODE_PRECISION (inner_mode
))
4583 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
4584 & ~GET_MODE_MASK (inner_mode
));
4593 /* The nonzero bits are in two classes: any bits within MODE
4594 that aren't in GET_MODE (x) are always significant. The rest of the
4595 nonzero bits are those that are significant in the operand of
4596 the shift when shifted the appropriate number of bits. This
4597 shows that high-order bits are cleared by the right shift and
4598 low-order bits by left shifts. */
4599 if (CONST_INT_P (XEXP (x
, 1))
4600 && INTVAL (XEXP (x
, 1)) >= 0
4601 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
4602 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
4604 machine_mode inner_mode
= GET_MODE (x
);
4605 unsigned int width
= GET_MODE_PRECISION (inner_mode
);
4606 int count
= INTVAL (XEXP (x
, 1));
4607 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
4608 unsigned HOST_WIDE_INT op_nonzero
4609 = cached_nonzero_bits (XEXP (x
, 0), mode
,
4610 known_x
, known_mode
, known_ret
);
4611 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
4612 unsigned HOST_WIDE_INT outer
= 0;
4614 if (mode_width
> width
)
4615 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
4617 if (code
== LSHIFTRT
)
4619 else if (code
== ASHIFTRT
)
4623 /* If the sign bit may have been nonzero before the shift, we
4624 need to mark all the places it could have been copied to
4625 by the shift as possibly nonzero. */
4626 if (inner
& (HOST_WIDE_INT_1U
<< (width
- 1 - count
)))
4627 inner
|= ((HOST_WIDE_INT_1U
<< count
) - 1)
4630 else if (code
== ASHIFT
)
4633 inner
= ((inner
<< (count
% width
)
4634 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
4636 nonzero
&= (outer
| inner
);
4642 /* This is at most the number of bits in the mode. */
4643 nonzero
= ((unsigned HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
4647 /* If CLZ has a known value at zero, then the nonzero bits are
4648 that value, plus the number of bits in the mode minus one. */
4649 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4651 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4657 /* If CTZ has a known value at zero, then the nonzero bits are
4658 that value, plus the number of bits in the mode minus one. */
4659 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
4661 |= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4667 /* This is at most the number of bits in the mode minus 1. */
4668 nonzero
= (HOST_WIDE_INT_1U
<< (floor_log2 (mode_width
))) - 1;
4677 unsigned HOST_WIDE_INT nonzero_true
4678 = cached_nonzero_bits (XEXP (x
, 1), mode
,
4679 known_x
, known_mode
, known_ret
);
4681 /* Don't call nonzero_bits for the second time if it cannot change
4683 if ((nonzero
& nonzero_true
) != nonzero
)
4684 nonzero
&= nonzero_true
4685 | cached_nonzero_bits (XEXP (x
, 2), mode
,
4686 known_x
, known_mode
, known_ret
);
4697 /* See the macro definition above. */
4698 #undef cached_num_sign_bit_copies
4701 /* Return true if num_sign_bit_copies1 might recurse into both operands
4705 num_sign_bit_copies_binary_arith_p (const_rtx x
)
4707 if (!ARITHMETIC_P (x
))
4709 switch (GET_CODE (x
))
4727 /* The function cached_num_sign_bit_copies is a wrapper around
4728 num_sign_bit_copies1. It avoids exponential behavior in
4729 num_sign_bit_copies1 when X has identical subexpressions on the
4730 first or the second level. */
4733 cached_num_sign_bit_copies (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4734 machine_mode known_mode
,
4735 unsigned int known_ret
)
4737 if (x
== known_x
&& mode
== known_mode
)
4740 /* Try to find identical subexpressions. If found call
4741 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
4742 the precomputed value for the subexpression as KNOWN_RET. */
4744 if (num_sign_bit_copies_binary_arith_p (x
))
4746 rtx x0
= XEXP (x
, 0);
4747 rtx x1
= XEXP (x
, 1);
4749 /* Check the first level. */
4752 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4753 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4757 /* Check the second level. */
4758 if (num_sign_bit_copies_binary_arith_p (x0
)
4759 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
4761 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
4762 cached_num_sign_bit_copies (x1
, mode
, known_x
,
4766 if (num_sign_bit_copies_binary_arith_p (x1
)
4767 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
4769 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
4770 cached_num_sign_bit_copies (x0
, mode
, known_x
,
4775 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
4778 /* Return the number of bits at the high-order end of X that are known to
4779 be equal to the sign bit. X will be used in mode MODE; if MODE is
4780 VOIDmode, X will be used in its own mode. The returned value will always
4781 be between 1 and the number of bits in MODE. */
4784 num_sign_bit_copies1 (const_rtx x
, machine_mode mode
, const_rtx known_x
,
4785 machine_mode known_mode
,
4786 unsigned int known_ret
)
4788 enum rtx_code code
= GET_CODE (x
);
4789 unsigned int bitwidth
= GET_MODE_PRECISION (mode
);
4790 int num0
, num1
, result
;
4791 unsigned HOST_WIDE_INT nonzero
;
4793 /* If we weren't given a mode, use the mode of X. If the mode is still
4794 VOIDmode, we don't know anything. Likewise if one of the modes is
4797 if (mode
== VOIDmode
)
4798 mode
= GET_MODE (x
);
4800 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
))
4801 || VECTOR_MODE_P (GET_MODE (x
)) || VECTOR_MODE_P (mode
))
4804 /* For a smaller object, just ignore the high bits. */
4805 if (bitwidth
< GET_MODE_PRECISION (GET_MODE (x
)))
4807 num0
= cached_num_sign_bit_copies (x
, GET_MODE (x
),
4808 known_x
, known_mode
, known_ret
);
4810 num0
- (int) (GET_MODE_PRECISION (GET_MODE (x
)) - bitwidth
));
4813 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_PRECISION (GET_MODE (x
)))
4815 /* If this machine does not do all register operations on the entire
4816 register and MODE is wider than the mode of X, we can say nothing
4817 at all about the high-order bits. */
4818 if (!WORD_REGISTER_OPERATIONS
)
4821 /* Likewise on machines that do, if the mode of the object is smaller
4822 than a word and loads of that size don't sign extend, we can say
4823 nothing about the high order bits. */
4824 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
4825 #ifdef LOAD_EXTEND_OP
4826 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
4832 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
4833 the code in the switch below. */
4838 #if defined(POINTERS_EXTEND_UNSIGNED)
4839 /* If pointers extend signed and this is a pointer in Pmode, say that
4840 all the bits above ptr_mode are known to be sign bit copies. */
4841 /* As we do not know which address space the pointer is referring to,
4842 we can do this only if the target does not support different pointer
4843 or address modes depending on the address space. */
4844 if (target_default_pointer_address_modes_p ()
4845 && ! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
4846 && mode
== Pmode
&& REG_POINTER (x
)
4847 && !targetm
.have_ptr_extend ())
4848 return GET_MODE_PRECISION (Pmode
) - GET_MODE_PRECISION (ptr_mode
) + 1;
4852 unsigned int copies_for_hook
= 1, copies
= 1;
4853 rtx new_rtx
= rtl_hooks
.reg_num_sign_bit_copies (x
, mode
, known_x
,
4854 known_mode
, known_ret
,
4858 copies
= cached_num_sign_bit_copies (new_rtx
, mode
, known_x
,
4859 known_mode
, known_ret
);
4861 if (copies
> 1 || copies_for_hook
> 1)
4862 return MAX (copies
, copies_for_hook
);
4864 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
4869 #ifdef LOAD_EXTEND_OP
4870 /* Some RISC machines sign-extend all loads of smaller than a word. */
4871 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
4872 return MAX (1, ((int) bitwidth
4873 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1));
4878 /* If the constant is negative, take its 1's complement and remask.
4879 Then see how many zero bits we have. */
4880 nonzero
= UINTVAL (x
) & GET_MODE_MASK (mode
);
4881 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
4882 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
4883 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
4885 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
4888 /* If this is a SUBREG for a promoted object that is sign-extended
4889 and we are looking at it in a wider mode, we know that at least the
4890 high-order bits are known to be sign bit copies. */
4892 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_SIGNED_P (x
))
4894 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4895 known_x
, known_mode
, known_ret
);
4896 return MAX ((int) bitwidth
4897 - (int) GET_MODE_PRECISION (GET_MODE (x
)) + 1,
4901 /* For a smaller object, just ignore the high bits. */
4902 if (bitwidth
<= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
))))
4904 num0
= cached_num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
,
4905 known_x
, known_mode
, known_ret
);
4906 return MAX (1, (num0
4907 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x
)))
4911 #ifdef LOAD_EXTEND_OP
4912 /* For paradoxical SUBREGs on machines where all register operations
4913 affect the entire register, just look inside. Note that we are
4914 passing MODE to the recursive call, so the number of sign bit copies
4915 will remain relative to that mode, not the inner mode. */
4917 /* This works only if loads sign extend. Otherwise, if we get a
4918 reload for the inner part, it may be loaded from the stack, and
4919 then we lose all sign bit copies that existed before the store
4922 if (WORD_REGISTER_OPERATIONS
4923 && paradoxical_subreg_p (x
)
4924 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
4925 && MEM_P (SUBREG_REG (x
)))
4926 return cached_num_sign_bit_copies (SUBREG_REG (x
), mode
,
4927 known_x
, known_mode
, known_ret
);
4932 if (CONST_INT_P (XEXP (x
, 1)))
4933 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
4937 return (bitwidth
- GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4938 + cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4939 known_x
, known_mode
, known_ret
));
4942 /* For a smaller object, just ignore the high bits. */
4943 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), VOIDmode
,
4944 known_x
, known_mode
, known_ret
);
4945 return MAX (1, (num0
- (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
4949 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4950 known_x
, known_mode
, known_ret
);
4952 case ROTATE
: case ROTATERT
:
4953 /* If we are rotating left by a number of bits less than the number
4954 of sign bit copies, we can just subtract that amount from the
4956 if (CONST_INT_P (XEXP (x
, 1))
4957 && INTVAL (XEXP (x
, 1)) >= 0
4958 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
4960 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4961 known_x
, known_mode
, known_ret
);
4962 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
4963 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
4968 /* In general, this subtracts one sign bit copy. But if the value
4969 is known to be positive, the number of sign bit copies is the
4970 same as that of the input. Finally, if the input has just one bit
4971 that might be nonzero, all the bits are copies of the sign bit. */
4972 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4973 known_x
, known_mode
, known_ret
);
4974 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
4975 return num0
> 1 ? num0
- 1 : 1;
4977 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
4982 && ((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
))
4987 case IOR
: case AND
: case XOR
:
4988 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
4989 /* Logical operations will preserve the number of sign-bit copies.
4990 MIN and MAX operations always return one of the operands. */
4991 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
4992 known_x
, known_mode
, known_ret
);
4993 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
4994 known_x
, known_mode
, known_ret
);
4996 /* If num1 is clearing some of the top bits then regardless of
4997 the other term, we are guaranteed to have at least that many
4998 high-order zero bits. */
5001 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5002 && CONST_INT_P (XEXP (x
, 1))
5003 && (UINTVAL (XEXP (x
, 1))
5004 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) == 0)
5007 /* Similarly for IOR when setting high-order bits. */
5010 && bitwidth
<= HOST_BITS_PER_WIDE_INT
5011 && CONST_INT_P (XEXP (x
, 1))
5012 && (UINTVAL (XEXP (x
, 1))
5013 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5016 return MIN (num0
, num1
);
5018 case PLUS
: case MINUS
:
5019 /* For addition and subtraction, we can have a 1-bit carry. However,
5020 if we are subtracting 1 from a positive number, there will not
5021 be such a carry. Furthermore, if the positive number is known to
5022 be 0 or 1, we know the result is either -1 or 0. */
5024 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
5025 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
5027 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
5028 if (((HOST_WIDE_INT_1U
<< (bitwidth
- 1)) & nonzero
) == 0)
5029 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
5030 : bitwidth
- floor_log2 (nonzero
) - 1);
5033 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5034 known_x
, known_mode
, known_ret
);
5035 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5036 known_x
, known_mode
, known_ret
);
5037 result
= MAX (1, MIN (num0
, num1
) - 1);
5042 /* The number of bits of the product is the sum of the number of
5043 bits of both terms. However, unless one of the terms if known
5044 to be positive, we must allow for an additional bit since negating
5045 a negative number can remove one sign bit copy. */
5047 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5048 known_x
, known_mode
, known_ret
);
5049 num1
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5050 known_x
, known_mode
, known_ret
);
5052 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
5054 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5055 || (((nonzero_bits (XEXP (x
, 0), mode
)
5056 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5057 && ((nonzero_bits (XEXP (x
, 1), mode
)
5058 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1)))
5062 return MAX (1, result
);
5065 /* The result must be <= the first operand. If the first operand
5066 has the high bit set, we know nothing about the number of sign
5068 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5070 else if ((nonzero_bits (XEXP (x
, 0), mode
)
5071 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5074 return cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5075 known_x
, known_mode
, known_ret
);
5078 /* The result must be <= the second operand. If the second operand
5079 has (or just might have) the high bit set, we know nothing about
5080 the number of sign bit copies. */
5081 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5083 else if ((nonzero_bits (XEXP (x
, 1), mode
)
5084 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5087 return cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5088 known_x
, known_mode
, known_ret
);
5091 /* Similar to unsigned division, except that we have to worry about
5092 the case where the divisor is negative, in which case we have
5094 result
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5095 known_x
, known_mode
, known_ret
);
5097 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5098 || (nonzero_bits (XEXP (x
, 1), mode
)
5099 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5105 result
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5106 known_x
, known_mode
, known_ret
);
5108 && (bitwidth
> HOST_BITS_PER_WIDE_INT
5109 || (nonzero_bits (XEXP (x
, 1), mode
)
5110 & (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0))
5116 /* Shifts by a constant add to the number of bits equal to the
5118 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5119 known_x
, known_mode
, known_ret
);
5120 if (CONST_INT_P (XEXP (x
, 1))
5121 && INTVAL (XEXP (x
, 1)) > 0
5122 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (GET_MODE (x
)))
5123 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
5128 /* Left shifts destroy copies. */
5129 if (!CONST_INT_P (XEXP (x
, 1))
5130 || INTVAL (XEXP (x
, 1)) < 0
5131 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
5132 || INTVAL (XEXP (x
, 1)) >= GET_MODE_PRECISION (GET_MODE (x
)))
5135 num0
= cached_num_sign_bit_copies (XEXP (x
, 0), mode
,
5136 known_x
, known_mode
, known_ret
);
5137 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
5140 num0
= cached_num_sign_bit_copies (XEXP (x
, 1), mode
,
5141 known_x
, known_mode
, known_ret
);
5142 num1
= cached_num_sign_bit_copies (XEXP (x
, 2), mode
,
5143 known_x
, known_mode
, known_ret
);
5144 return MIN (num0
, num1
);
5146 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
5147 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
5148 case GEU
: case GTU
: case LEU
: case LTU
:
5149 case UNORDERED
: case ORDERED
:
5150 /* If the constant is negative, take its 1's complement and remask.
5151 Then see how many zero bits we have. */
5152 nonzero
= STORE_FLAG_VALUE
;
5153 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
5154 && (nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))) != 0)
5155 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
5157 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
5163 /* If we haven't been able to figure it out by one of the above rules,
5164 see if some of the high-order bits are known to be zero. If so,
5165 count those bits and return one less than that amount. If we can't
5166 safely compute the mask for this mode, always return BITWIDTH. */
5168 bitwidth
= GET_MODE_PRECISION (mode
);
5169 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
5172 nonzero
= nonzero_bits (x
, mode
);
5173 return nonzero
& (HOST_WIDE_INT_1U
<< (bitwidth
- 1))
5174 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1;
5177 /* Calculate the rtx_cost of a single instruction. A return value of
5178 zero indicates an instruction pattern without a known cost. */
5181 insn_rtx_cost (rtx pat
, bool speed
)
5186 /* Extract the single set rtx from the instruction pattern.
5187 We can't use single_set since we only have the pattern. */
5188 if (GET_CODE (pat
) == SET
)
5190 else if (GET_CODE (pat
) == PARALLEL
)
5193 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
5195 rtx x
= XVECEXP (pat
, 0, i
);
5196 if (GET_CODE (x
) == SET
)
5209 cost
= set_src_cost (SET_SRC (set
), GET_MODE (SET_DEST (set
)), speed
);
5210 return cost
> 0 ? cost
: COSTS_N_INSNS (1);
5213 /* Returns estimate on cost of computing SEQ. */
5216 seq_cost (const rtx_insn
*seq
, bool speed
)
5221 for (; seq
; seq
= NEXT_INSN (seq
))
5223 set
= single_set (seq
);
5225 cost
+= set_rtx_cost (set
, speed
);
5233 /* Given an insn INSN and condition COND, return the condition in a
5234 canonical form to simplify testing by callers. Specifically:
5236 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5237 (2) Both operands will be machine operands; (cc0) will have been replaced.
5238 (3) If an operand is a constant, it will be the second operand.
5239 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5240 for GE, GEU, and LEU.
5242 If the condition cannot be understood, or is an inequality floating-point
5243 comparison which needs to be reversed, 0 will be returned.
5245 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5247 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5248 insn used in locating the condition was found. If a replacement test
5249 of the condition is desired, it should be placed in front of that
5250 insn and we will be sure that the inputs are still valid.
5252 If WANT_REG is nonzero, we wish the condition to be relative to that
5253 register, if possible. Therefore, do not canonicalize the condition
5254 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5255 to be a compare to a CC mode register.
5257 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5261 canonicalize_condition (rtx_insn
*insn
, rtx cond
, int reverse
,
5262 rtx_insn
**earliest
,
5263 rtx want_reg
, int allow_cc_mode
, int valid_at_insn_p
)
5266 rtx_insn
*prev
= insn
;
5270 int reverse_code
= 0;
5272 basic_block bb
= BLOCK_FOR_INSN (insn
);
5274 code
= GET_CODE (cond
);
5275 mode
= GET_MODE (cond
);
5276 op0
= XEXP (cond
, 0);
5277 op1
= XEXP (cond
, 1);
5280 code
= reversed_comparison_code (cond
, insn
);
5281 if (code
== UNKNOWN
)
5287 /* If we are comparing a register with zero, see if the register is set
5288 in the previous insn to a COMPARE or a comparison operation. Perform
5289 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5292 while ((GET_RTX_CLASS (code
) == RTX_COMPARE
5293 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
5294 && op1
== CONST0_RTX (GET_MODE (op0
))
5297 /* Set nonzero when we find something of interest. */
5300 /* If comparison with cc0, import actual comparison from compare
5304 if ((prev
= prev_nonnote_insn (prev
)) == 0
5305 || !NONJUMP_INSN_P (prev
)
5306 || (set
= single_set (prev
)) == 0
5307 || SET_DEST (set
) != cc0_rtx
)
5310 op0
= SET_SRC (set
);
5311 op1
= CONST0_RTX (GET_MODE (op0
));
5316 /* If this is a COMPARE, pick up the two things being compared. */
5317 if (GET_CODE (op0
) == COMPARE
)
5319 op1
= XEXP (op0
, 1);
5320 op0
= XEXP (op0
, 0);
5323 else if (!REG_P (op0
))
5326 /* Go back to the previous insn. Stop if it is not an INSN. We also
5327 stop if it isn't a single set or if it has a REG_INC note because
5328 we don't want to bother dealing with it. */
5330 prev
= prev_nonnote_nondebug_insn (prev
);
5333 || !NONJUMP_INSN_P (prev
)
5334 || FIND_REG_INC_NOTE (prev
, NULL_RTX
)
5335 /* In cfglayout mode, there do not have to be labels at the
5336 beginning of a block, or jumps at the end, so the previous
5337 conditions would not stop us when we reach bb boundary. */
5338 || BLOCK_FOR_INSN (prev
) != bb
)
5341 set
= set_of (op0
, prev
);
5344 && (GET_CODE (set
) != SET
5345 || !rtx_equal_p (SET_DEST (set
), op0
)))
5348 /* If this is setting OP0, get what it sets it to if it looks
5352 machine_mode inner_mode
= GET_MODE (SET_DEST (set
));
5353 #ifdef FLOAT_STORE_FLAG_VALUE
5354 REAL_VALUE_TYPE fsfv
;
5357 /* ??? We may not combine comparisons done in a CCmode with
5358 comparisons not done in a CCmode. This is to aid targets
5359 like Alpha that have an IEEE compliant EQ instruction, and
5360 a non-IEEE compliant BEQ instruction. The use of CCmode is
5361 actually artificial, simply to prevent the combination, but
5362 should not affect other platforms.
5364 However, we must allow VOIDmode comparisons to match either
5365 CCmode or non-CCmode comparison, because some ports have
5366 modeless comparisons inside branch patterns.
5368 ??? This mode check should perhaps look more like the mode check
5369 in simplify_comparison in combine. */
5370 if (((GET_MODE_CLASS (mode
) == MODE_CC
)
5371 != (GET_MODE_CLASS (inner_mode
) == MODE_CC
))
5373 && inner_mode
!= VOIDmode
)
5375 if (GET_CODE (SET_SRC (set
)) == COMPARE
5378 && val_signbit_known_set_p (inner_mode
,
5380 #ifdef FLOAT_STORE_FLAG_VALUE
5382 && SCALAR_FLOAT_MODE_P (inner_mode
)
5383 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5384 REAL_VALUE_NEGATIVE (fsfv
)))
5387 && COMPARISON_P (SET_SRC (set
))))
5389 else if (((code
== EQ
5391 && val_signbit_known_set_p (inner_mode
,
5393 #ifdef FLOAT_STORE_FLAG_VALUE
5395 && SCALAR_FLOAT_MODE_P (inner_mode
)
5396 && (fsfv
= FLOAT_STORE_FLAG_VALUE (inner_mode
),
5397 REAL_VALUE_NEGATIVE (fsfv
)))
5400 && COMPARISON_P (SET_SRC (set
)))
5405 else if ((code
== EQ
|| code
== NE
)
5406 && GET_CODE (SET_SRC (set
)) == XOR
)
5407 /* Handle sequences like:
5410 ...(eq|ne op0 (const_int 0))...
5414 (eq op0 (const_int 0)) reduces to (eq X Y)
5415 (ne op0 (const_int 0)) reduces to (ne X Y)
5417 This is the form used by MIPS16, for example. */
5423 else if (reg_set_p (op0
, prev
))
5424 /* If this sets OP0, but not directly, we have to give up. */
5429 /* If the caller is expecting the condition to be valid at INSN,
5430 make sure X doesn't change before INSN. */
5431 if (valid_at_insn_p
)
5432 if (modified_in_p (x
, prev
) || modified_between_p (x
, prev
, insn
))
5434 if (COMPARISON_P (x
))
5435 code
= GET_CODE (x
);
5438 code
= reversed_comparison_code (x
, prev
);
5439 if (code
== UNKNOWN
)
5444 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5450 /* If constant is first, put it last. */
5451 if (CONSTANT_P (op0
))
5452 code
= swap_condition (code
), tem
= op0
, op0
= op1
, op1
= tem
;
5454 /* If OP0 is the result of a comparison, we weren't able to find what
5455 was really being compared, so fail. */
5457 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5460 /* Canonicalize any ordered comparison with integers involving equality
5461 if we can do computations in the relevant mode and we do not
5464 if (GET_MODE_CLASS (GET_MODE (op0
)) != MODE_CC
5465 && CONST_INT_P (op1
)
5466 && GET_MODE (op0
) != VOIDmode
5467 && GET_MODE_PRECISION (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
)
5469 HOST_WIDE_INT const_val
= INTVAL (op1
);
5470 unsigned HOST_WIDE_INT uconst_val
= const_val
;
5471 unsigned HOST_WIDE_INT max_val
5472 = (unsigned HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (op0
));
5477 if ((unsigned HOST_WIDE_INT
) const_val
!= max_val
>> 1)
5478 code
= LT
, op1
= gen_int_mode (const_val
+ 1, GET_MODE (op0
));
5481 /* When cross-compiling, const_val might be sign-extended from
5482 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
5484 if ((const_val
& max_val
)
5485 != (HOST_WIDE_INT_1U
5486 << (GET_MODE_PRECISION (GET_MODE (op0
)) - 1)))
5487 code
= GT
, op1
= gen_int_mode (const_val
- 1, GET_MODE (op0
));
5491 if (uconst_val
< max_val
)
5492 code
= LTU
, op1
= gen_int_mode (uconst_val
+ 1, GET_MODE (op0
));
5496 if (uconst_val
!= 0)
5497 code
= GTU
, op1
= gen_int_mode (uconst_val
- 1, GET_MODE (op0
));
5505 /* Never return CC0; return zero instead. */
5509 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5512 /* Given a jump insn JUMP, return the condition that will cause it to branch
5513 to its JUMP_LABEL. If the condition cannot be understood, or is an
5514 inequality floating-point comparison which needs to be reversed, 0 will
5517 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5518 insn used in locating the condition was found. If a replacement test
5519 of the condition is desired, it should be placed in front of that
5520 insn and we will be sure that the inputs are still valid. If EARLIEST
5521 is null, the returned condition will be valid at INSN.
5523 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
5524 compare CC mode register.
5526 VALID_AT_INSN_P is the same as for canonicalize_condition. */
5529 get_condition (rtx_insn
*jump
, rtx_insn
**earliest
, int allow_cc_mode
,
5530 int valid_at_insn_p
)
5536 /* If this is not a standard conditional jump, we can't parse it. */
5538 || ! any_condjump_p (jump
))
5540 set
= pc_set (jump
);
5542 cond
= XEXP (SET_SRC (set
), 0);
5544 /* If this branches to JUMP_LABEL when the condition is false, reverse
5547 = GET_CODE (XEXP (SET_SRC (set
), 2)) == LABEL_REF
5548 && LABEL_REF_LABEL (XEXP (SET_SRC (set
), 2)) == JUMP_LABEL (jump
);
5550 return canonicalize_condition (jump
, cond
, reverse
, earliest
, NULL_RTX
,
5551 allow_cc_mode
, valid_at_insn_p
);
5554 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
5555 TARGET_MODE_REP_EXTENDED.
5557 Note that we assume that the property of
5558 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
5559 narrower than mode B. I.e., if A is a mode narrower than B then in
5560 order to be able to operate on it in mode B, mode A needs to
5561 satisfy the requirements set by the representation of mode B. */
5564 init_num_sign_bit_copies_in_rep (void)
5566 machine_mode mode
, in_mode
;
5568 for (in_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); in_mode
!= VOIDmode
;
5569 in_mode
= GET_MODE_WIDER_MODE (mode
))
5570 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= in_mode
;
5571 mode
= GET_MODE_WIDER_MODE (mode
))
5575 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
5576 extends to the next widest mode. */
5577 gcc_assert (targetm
.mode_rep_extended (mode
, in_mode
) == UNKNOWN
5578 || GET_MODE_WIDER_MODE (mode
) == in_mode
);
5580 /* We are in in_mode. Count how many bits outside of mode
5581 have to be copies of the sign-bit. */
5582 for (i
= mode
; i
!= in_mode
; i
= GET_MODE_WIDER_MODE (i
))
5584 machine_mode wider
= GET_MODE_WIDER_MODE (i
);
5586 if (targetm
.mode_rep_extended (i
, wider
) == SIGN_EXTEND
5587 /* We can only check sign-bit copies starting from the
5588 top-bit. In order to be able to check the bits we
5589 have already seen we pretend that subsequent bits
5590 have to be sign-bit copies too. */
5591 || num_sign_bit_copies_in_rep
[in_mode
][mode
])
5592 num_sign_bit_copies_in_rep
[in_mode
][mode
]
5593 += GET_MODE_PRECISION (wider
) - GET_MODE_PRECISION (i
);
5598 /* Suppose that truncation from the machine mode of X to MODE is not a
5599 no-op. See if there is anything special about X so that we can
5600 assume it already contains a truncated value of MODE. */
5603 truncated_to_mode (machine_mode mode
, const_rtx x
)
5605 /* This register has already been used in MODE without explicit
5607 if (REG_P (x
) && rtl_hooks
.reg_truncated_to_mode (mode
, x
))
5610 /* See if we already satisfy the requirements of MODE. If yes we
5611 can just switch to MODE. */
5612 if (num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
]
5613 && (num_sign_bit_copies (x
, GET_MODE (x
))
5614 >= num_sign_bit_copies_in_rep
[GET_MODE (x
)][mode
] + 1))
5620 /* Return true if RTX code CODE has a single sequence of zero or more
5621 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
5622 entry in that case. */
5625 setup_reg_subrtx_bounds (unsigned int code
)
5627 const char *format
= GET_RTX_FORMAT ((enum rtx_code
) code
);
5629 for (; format
[i
] != 'e'; ++i
)
5632 /* No subrtxes. Leave start and count as 0. */
5634 if (format
[i
] == 'E' || format
[i
] == 'V')
5638 /* Record the sequence of 'e's. */
5639 rtx_all_subrtx_bounds
[code
].start
= i
;
5642 while (format
[i
] == 'e');
5643 rtx_all_subrtx_bounds
[code
].count
= i
- rtx_all_subrtx_bounds
[code
].start
;
5644 /* rtl-iter.h relies on this. */
5645 gcc_checking_assert (rtx_all_subrtx_bounds
[code
].count
<= 3);
5647 for (; format
[i
]; ++i
)
5648 if (format
[i
] == 'E' || format
[i
] == 'V' || format
[i
] == 'e')
5654 /* Initialize rtx_all_subrtx_bounds. */
5659 for (i
= 0; i
< NUM_RTX_CODE
; i
++)
5661 if (!setup_reg_subrtx_bounds (i
))
5662 rtx_all_subrtx_bounds
[i
].count
= UCHAR_MAX
;
5663 if (GET_RTX_CLASS (i
) != RTX_CONST_OBJ
)
5664 rtx_nonconst_subrtx_bounds
[i
] = rtx_all_subrtx_bounds
[i
];
5667 init_num_sign_bit_copies_in_rep ();
5670 /* Check whether this is a constant pool constant. */
5672 constant_pool_constant_p (rtx x
)
5674 x
= avoid_constant_pool_reference (x
);
5675 return CONST_DOUBLE_P (x
);
5678 /* If M is a bitmask that selects a field of low-order bits within an item but
5679 not the entire word, return the length of the field. Return -1 otherwise.
5680 M is used in machine mode MODE. */
5683 low_bitmask_len (machine_mode mode
, unsigned HOST_WIDE_INT m
)
5685 if (mode
!= VOIDmode
)
5687 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
5689 m
&= GET_MODE_MASK (mode
);
5692 return exact_log2 (m
+ 1);
5695 /* Return the mode of MEM's address. */
5698 get_address_mode (rtx mem
)
5702 gcc_assert (MEM_P (mem
));
5703 mode
= GET_MODE (XEXP (mem
, 0));
5704 if (mode
!= VOIDmode
)
5706 return targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (mem
));
5709 /* Split up a CONST_DOUBLE or integer constant rtx
5710 into two rtx's for single words,
5711 storing in *FIRST the word that comes first in memory in the target
5712 and in *SECOND the other.
5714 TODO: This function needs to be rewritten to work on any size
5718 split_double (rtx value
, rtx
*first
, rtx
*second
)
5720 if (CONST_INT_P (value
))
5722 if (HOST_BITS_PER_WIDE_INT
>= (2 * BITS_PER_WORD
))
5724 /* In this case the CONST_INT holds both target words.
5725 Extract the bits from it into two word-sized pieces.
5726 Sign extend each half to HOST_WIDE_INT. */
5727 unsigned HOST_WIDE_INT low
, high
;
5728 unsigned HOST_WIDE_INT mask
, sign_bit
, sign_extend
;
5729 unsigned bits_per_word
= BITS_PER_WORD
;
5731 /* Set sign_bit to the most significant bit of a word. */
5733 sign_bit
<<= bits_per_word
- 1;
5735 /* Set mask so that all bits of the word are set. We could
5736 have used 1 << BITS_PER_WORD instead of basing the
5737 calculation on sign_bit. However, on machines where
5738 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
5739 compiler warning, even though the code would never be
5741 mask
= sign_bit
<< 1;
5744 /* Set sign_extend as any remaining bits. */
5745 sign_extend
= ~mask
;
5747 /* Pick the lower word and sign-extend it. */
5748 low
= INTVAL (value
);
5753 /* Pick the higher word, shifted to the least significant
5754 bits, and sign-extend it. */
5755 high
= INTVAL (value
);
5756 high
>>= bits_per_word
- 1;
5759 if (high
& sign_bit
)
5760 high
|= sign_extend
;
5762 /* Store the words in the target machine order. */
5763 if (WORDS_BIG_ENDIAN
)
5765 *first
= GEN_INT (high
);
5766 *second
= GEN_INT (low
);
5770 *first
= GEN_INT (low
);
5771 *second
= GEN_INT (high
);
5776 /* The rule for using CONST_INT for a wider mode
5777 is that we regard the value as signed.
5778 So sign-extend it. */
5779 rtx high
= (INTVAL (value
) < 0 ? constm1_rtx
: const0_rtx
);
5780 if (WORDS_BIG_ENDIAN
)
5792 else if (GET_CODE (value
) == CONST_WIDE_INT
)
5794 /* All of this is scary code and needs to be converted to
5795 properly work with any size integer. */
5796 gcc_assert (CONST_WIDE_INT_NUNITS (value
) == 2);
5797 if (WORDS_BIG_ENDIAN
)
5799 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5800 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5804 *first
= GEN_INT (CONST_WIDE_INT_ELT (value
, 0));
5805 *second
= GEN_INT (CONST_WIDE_INT_ELT (value
, 1));
5808 else if (!CONST_DOUBLE_P (value
))
5810 if (WORDS_BIG_ENDIAN
)
5812 *first
= const0_rtx
;
5818 *second
= const0_rtx
;
5821 else if (GET_MODE (value
) == VOIDmode
5822 /* This is the old way we did CONST_DOUBLE integers. */
5823 || GET_MODE_CLASS (GET_MODE (value
)) == MODE_INT
)
5825 /* In an integer, the words are defined as most and least significant.
5826 So order them by the target's convention. */
5827 if (WORDS_BIG_ENDIAN
)
5829 *first
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5830 *second
= GEN_INT (CONST_DOUBLE_LOW (value
));
5834 *first
= GEN_INT (CONST_DOUBLE_LOW (value
));
5835 *second
= GEN_INT (CONST_DOUBLE_HIGH (value
));
5842 /* Note, this converts the REAL_VALUE_TYPE to the target's
5843 format, splits up the floating point double and outputs
5844 exactly 32 bits of it into each of l[0] and l[1] --
5845 not necessarily BITS_PER_WORD bits. */
5846 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value
), l
);
5848 /* If 32 bits is an entire word for the target, but not for the host,
5849 then sign-extend on the host so that the number will look the same
5850 way on the host that it would on the target. See for instance
5851 simplify_unary_operation. The #if is needed to avoid compiler
5854 #if HOST_BITS_PER_LONG > 32
5855 if (BITS_PER_WORD
< HOST_BITS_PER_LONG
&& BITS_PER_WORD
== 32)
5857 if (l
[0] & ((long) 1 << 31))
5858 l
[0] |= ((unsigned long) (-1) << 32);
5859 if (l
[1] & ((long) 1 << 31))
5860 l
[1] |= ((unsigned long) (-1) << 32);
5864 *first
= GEN_INT (l
[0]);
5865 *second
= GEN_INT (l
[1]);
5869 /* Return true if X is a sign_extract or zero_extract from the least
5873 lsb_bitfield_op_p (rtx x
)
5875 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_BITFIELD_OPS
)
5877 machine_mode mode
= GET_MODE (XEXP (x
, 0));
5878 HOST_WIDE_INT len
= INTVAL (XEXP (x
, 1));
5879 HOST_WIDE_INT pos
= INTVAL (XEXP (x
, 2));
5881 return (pos
== (BITS_BIG_ENDIAN
? GET_MODE_PRECISION (mode
) - len
: 0));
5886 /* Strip outer address "mutations" from LOC and return a pointer to the
5887 inner value. If OUTER_CODE is nonnull, store the code of the innermost
5888 stripped expression there.
5890 "Mutations" either convert between modes or apply some kind of
5891 extension, truncation or alignment. */
5894 strip_address_mutations (rtx
*loc
, enum rtx_code
*outer_code
)
5898 enum rtx_code code
= GET_CODE (*loc
);
5899 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
5900 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
5901 used to convert between pointer sizes. */
5902 loc
= &XEXP (*loc
, 0);
5903 else if (lsb_bitfield_op_p (*loc
))
5904 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
5905 acts as a combined truncation and extension. */
5906 loc
= &XEXP (*loc
, 0);
5907 else if (code
== AND
&& CONST_INT_P (XEXP (*loc
, 1)))
5908 /* (and ... (const_int -X)) is used to align to X bytes. */
5909 loc
= &XEXP (*loc
, 0);
5910 else if (code
== SUBREG
5911 && !OBJECT_P (SUBREG_REG (*loc
))
5912 && subreg_lowpart_p (*loc
))
5913 /* (subreg (operator ...) ...) inside and is used for mode
5915 loc
= &SUBREG_REG (*loc
);
5923 /* Return true if CODE applies some kind of scale. The scaled value is
5924 is the first operand and the scale is the second. */
5927 binary_scale_code_p (enum rtx_code code
)
5929 return (code
== MULT
5931 /* Needed by ARM targets. */
5935 || code
== ROTATERT
);
5938 /* If *INNER can be interpreted as a base, return a pointer to the inner term
5939 (see address_info). Return null otherwise. */
5942 get_base_term (rtx
*inner
)
5944 if (GET_CODE (*inner
) == LO_SUM
)
5945 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5948 || GET_CODE (*inner
) == SUBREG
5949 || GET_CODE (*inner
) == SCRATCH
)
5954 /* If *INNER can be interpreted as an index, return a pointer to the inner term
5955 (see address_info). Return null otherwise. */
5958 get_index_term (rtx
*inner
)
5960 /* At present, only constant scales are allowed. */
5961 if (binary_scale_code_p (GET_CODE (*inner
)) && CONSTANT_P (XEXP (*inner
, 1)))
5962 inner
= strip_address_mutations (&XEXP (*inner
, 0));
5965 || GET_CODE (*inner
) == SUBREG
5966 || GET_CODE (*inner
) == SCRATCH
)
5971 /* Set the segment part of address INFO to LOC, given that INNER is the
5975 set_address_segment (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5977 gcc_assert (!info
->segment
);
5978 info
->segment
= loc
;
5979 info
->segment_term
= inner
;
5982 /* Set the base part of address INFO to LOC, given that INNER is the
5986 set_address_base (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5988 gcc_assert (!info
->base
);
5990 info
->base_term
= inner
;
5993 /* Set the index part of address INFO to LOC, given that INNER is the
5997 set_address_index (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
5999 gcc_assert (!info
->index
);
6001 info
->index_term
= inner
;
6004 /* Set the displacement part of address INFO to LOC, given that INNER
6005 is the constant term. */
6008 set_address_disp (struct address_info
*info
, rtx
*loc
, rtx
*inner
)
6010 gcc_assert (!info
->disp
);
6012 info
->disp_term
= inner
;
6015 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6016 rest of INFO accordingly. */
6019 decompose_incdec_address (struct address_info
*info
)
6021 info
->autoinc_p
= true;
6023 rtx
*base
= &XEXP (*info
->inner
, 0);
6024 set_address_base (info
, base
, base
);
6025 gcc_checking_assert (info
->base
== info
->base_term
);
6027 /* These addresses are only valid when the size of the addressed
6029 gcc_checking_assert (info
->mode
!= VOIDmode
);
6032 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6033 of INFO accordingly. */
6036 decompose_automod_address (struct address_info
*info
)
6038 info
->autoinc_p
= true;
6040 rtx
*base
= &XEXP (*info
->inner
, 0);
6041 set_address_base (info
, base
, base
);
6042 gcc_checking_assert (info
->base
== info
->base_term
);
6044 rtx plus
= XEXP (*info
->inner
, 1);
6045 gcc_assert (GET_CODE (plus
) == PLUS
);
6047 info
->base_term2
= &XEXP (plus
, 0);
6048 gcc_checking_assert (rtx_equal_p (*info
->base_term
, *info
->base_term2
));
6050 rtx
*step
= &XEXP (plus
, 1);
6051 rtx
*inner_step
= strip_address_mutations (step
);
6052 if (CONSTANT_P (*inner_step
))
6053 set_address_disp (info
, step
, inner_step
);
6055 set_address_index (info
, step
, inner_step
);
6058 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6059 values in [PTR, END). Return a pointer to the end of the used array. */
6062 extract_plus_operands (rtx
*loc
, rtx
**ptr
, rtx
**end
)
6065 if (GET_CODE (x
) == PLUS
)
6067 ptr
= extract_plus_operands (&XEXP (x
, 0), ptr
, end
);
6068 ptr
= extract_plus_operands (&XEXP (x
, 1), ptr
, end
);
6072 gcc_assert (ptr
!= end
);
6078 /* Evaluate the likelihood of X being a base or index value, returning
6079 positive if it is likely to be a base, negative if it is likely to be
6080 an index, and 0 if we can't tell. Make the magnitude of the return
6081 value reflect the amount of confidence we have in the answer.
6083 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6086 baseness (rtx x
, machine_mode mode
, addr_space_t as
,
6087 enum rtx_code outer_code
, enum rtx_code index_code
)
6089 /* Believe *_POINTER unless the address shape requires otherwise. */
6090 if (REG_P (x
) && REG_POINTER (x
))
6092 if (MEM_P (x
) && MEM_POINTER (x
))
6095 if (REG_P (x
) && HARD_REGISTER_P (x
))
6097 /* X is a hard register. If it only fits one of the base
6098 or index classes, choose that interpretation. */
6099 int regno
= REGNO (x
);
6100 bool base_p
= ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
6101 bool index_p
= REGNO_OK_FOR_INDEX_P (regno
);
6102 if (base_p
!= index_p
)
6103 return base_p
? 1 : -1;
6108 /* INFO->INNER describes a normal, non-automodified address.
6109 Fill in the rest of INFO accordingly. */
6112 decompose_normal_address (struct address_info
*info
)
6114 /* Treat the address as the sum of up to four values. */
6116 size_t n_ops
= extract_plus_operands (info
->inner
, ops
,
6117 ops
+ ARRAY_SIZE (ops
)) - ops
;
6119 /* If there is more than one component, any base component is in a PLUS. */
6121 info
->base_outer_code
= PLUS
;
6123 /* Try to classify each sum operand now. Leave those that could be
6124 either a base or an index in OPS. */
6127 for (size_t in
= 0; in
< n_ops
; ++in
)
6130 rtx
*inner
= strip_address_mutations (loc
);
6131 if (CONSTANT_P (*inner
))
6132 set_address_disp (info
, loc
, inner
);
6133 else if (GET_CODE (*inner
) == UNSPEC
)
6134 set_address_segment (info
, loc
, inner
);
6137 /* The only other possibilities are a base or an index. */
6138 rtx
*base_term
= get_base_term (inner
);
6139 rtx
*index_term
= get_index_term (inner
);
6140 gcc_assert (base_term
|| index_term
);
6142 set_address_index (info
, loc
, index_term
);
6143 else if (!index_term
)
6144 set_address_base (info
, loc
, base_term
);
6147 gcc_assert (base_term
== index_term
);
6149 inner_ops
[out
] = base_term
;
6155 /* Classify the remaining OPS members as bases and indexes. */
6158 /* If we haven't seen a base or an index yet, assume that this is
6159 the base. If we were confident that another term was the base
6160 or index, treat the remaining operand as the other kind. */
6162 set_address_base (info
, ops
[0], inner_ops
[0]);
6164 set_address_index (info
, ops
[0], inner_ops
[0]);
6168 /* In the event of a tie, assume the base comes first. */
6169 if (baseness (*inner_ops
[0], info
->mode
, info
->as
, PLUS
,
6171 >= baseness (*inner_ops
[1], info
->mode
, info
->as
, PLUS
,
6172 GET_CODE (*ops
[0])))
6174 set_address_base (info
, ops
[0], inner_ops
[0]);
6175 set_address_index (info
, ops
[1], inner_ops
[1]);
6179 set_address_base (info
, ops
[1], inner_ops
[1]);
6180 set_address_index (info
, ops
[0], inner_ops
[0]);
6184 gcc_assert (out
== 0);
6187 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6188 or VOIDmode if not known. AS is the address space associated with LOC.
6189 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6192 decompose_address (struct address_info
*info
, rtx
*loc
, machine_mode mode
,
6193 addr_space_t as
, enum rtx_code outer_code
)
6195 memset (info
, 0, sizeof (*info
));
6198 info
->addr_outer_code
= outer_code
;
6200 info
->inner
= strip_address_mutations (loc
, &outer_code
);
6201 info
->base_outer_code
= outer_code
;
6202 switch (GET_CODE (*info
->inner
))
6208 decompose_incdec_address (info
);
6213 decompose_automod_address (info
);
6217 decompose_normal_address (info
);
6222 /* Describe address operand LOC in INFO. */
6225 decompose_lea_address (struct address_info
*info
, rtx
*loc
)
6227 decompose_address (info
, loc
, VOIDmode
, ADDR_SPACE_GENERIC
, ADDRESS
);
6230 /* Describe the address of MEM X in INFO. */
6233 decompose_mem_address (struct address_info
*info
, rtx x
)
6235 gcc_assert (MEM_P (x
));
6236 decompose_address (info
, &XEXP (x
, 0), GET_MODE (x
),
6237 MEM_ADDR_SPACE (x
), MEM
);
6240 /* Update INFO after a change to the address it describes. */
6243 update_address (struct address_info
*info
)
6245 decompose_address (info
, info
->outer
, info
->mode
, info
->as
,
6246 info
->addr_outer_code
);
6249 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6250 more complicated than that. */
6253 get_index_scale (const struct address_info
*info
)
6255 rtx index
= *info
->index
;
6256 if (GET_CODE (index
) == MULT
6257 && CONST_INT_P (XEXP (index
, 1))
6258 && info
->index_term
== &XEXP (index
, 0))
6259 return INTVAL (XEXP (index
, 1));
6261 if (GET_CODE (index
) == ASHIFT
6262 && CONST_INT_P (XEXP (index
, 1))
6263 && info
->index_term
== &XEXP (index
, 0))
6264 return HOST_WIDE_INT_1
<< INTVAL (XEXP (index
, 1));
6266 if (info
->index
== info
->index_term
)
6272 /* Return the "index code" of INFO, in the form required by
6276 get_index_code (const struct address_info
*info
)
6279 return GET_CODE (*info
->index
);
6282 return GET_CODE (*info
->disp
);
6287 /* Return true if RTL X contains a SYMBOL_REF. */
6290 contains_symbol_ref_p (const_rtx x
)
6292 subrtx_iterator::array_type array
;
6293 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6294 if (SYMBOL_REF_P (*iter
))
6300 /* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6303 contains_symbolic_reference_p (const_rtx x
)
6305 subrtx_iterator::array_type array
;
6306 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6307 if (SYMBOL_REF_P (*iter
) || GET_CODE (*iter
) == LABEL_REF
)
6313 /* Return true if X contains a thread-local symbol. */
6316 tls_referenced_p (const_rtx x
)
6318 if (!targetm
.have_tls
)
6321 subrtx_iterator::array_type array
;
6322 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
6323 if (GET_CODE (*iter
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (*iter
) != 0)