poly_int: PUSH_ROUNDING
[official-gcc.git] / gcc / reload1.c
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1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "target.h"
25 #include "rtl.h"
26 #include "tree.h"
27 #include "predict.h"
28 #include "df.h"
29 #include "memmodel.h"
30 #include "tm_p.h"
31 #include "optabs.h"
32 #include "regs.h"
33 #include "ira.h"
34 #include "recog.h"
36 #include "rtl-error.h"
37 #include "expr.h"
38 #include "addresses.h"
39 #include "cfgrtl.h"
40 #include "cfgbuild.h"
41 #include "reload.h"
42 #include "except.h"
43 #include "dumpfile.h"
44 #include "rtl-iter.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
51 that need them.
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 struct target_reload default_target_reload;
81 #if SWITCHABLE_TARGET
82 struct target_reload *this_target_reload = &default_target_reload;
83 #endif
85 #define spill_indirect_levels \
86 (this_target_reload->x_spill_indirect_levels)
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static regset_head reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Widest mode in which each pseudo reg is referred to (via subreg). */
101 static machine_mode *reg_max_ref_mode;
103 /* Vector to remember old contents of reg_renumber before spilling. */
104 static short *reg_old_renumber;
106 /* During reload_as_needed, element N contains the last pseudo regno reloaded
107 into hard register N. If that pseudo reg occupied more than one register,
108 reg_reloaded_contents points to that pseudo for each spill register in
109 use; all of these must remain set for an inheritance to occur. */
110 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
112 /* During reload_as_needed, element N contains the insn for which
113 hard register N was last used. Its contents are significant only
114 when reg_reloaded_valid is set for this register. */
115 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
117 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
118 static HARD_REG_SET reg_reloaded_valid;
119 /* Indicate if the register was dead at the end of the reload.
120 This is only valid if reg_reloaded_contents is set and valid. */
121 static HARD_REG_SET reg_reloaded_dead;
123 /* Indicate whether the register's current value is one that is not
124 safe to retain across a call, even for registers that are normally
125 call-saved. This is only meaningful for members of reg_reloaded_valid. */
126 static HARD_REG_SET reg_reloaded_call_part_clobbered;
128 /* Number of spill-regs so far; number of valid elements of spill_regs. */
129 static int n_spills;
131 /* In parallel with spill_regs, contains REG rtx's for those regs.
132 Holds the last rtx used for any given reg, or 0 if it has never
133 been used for spilling yet. This rtx is reused, provided it has
134 the proper mode. */
135 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
137 /* In parallel with spill_regs, contains nonzero for a spill reg
138 that was stored after the last time it was used.
139 The precise value is the insn generated to do the store. */
140 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
142 /* This is the register that was stored with spill_reg_store. This is a
143 copy of reload_out / reload_out_reg when the value was stored; if
144 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
145 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
147 /* This table is the inverse mapping of spill_regs:
148 indexed by hard reg number,
149 it contains the position of that reg in spill_regs,
150 or -1 for something that is not in spill_regs.
152 ?!? This is no longer accurate. */
153 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
155 /* This reg set indicates registers that can't be used as spill registers for
156 the currently processed insn. These are the hard registers which are live
157 during the insn, but not allocated to pseudos, as well as fixed
158 registers. */
159 static HARD_REG_SET bad_spill_regs;
161 /* These are the hard registers that can't be used as spill register for any
162 insn. This includes registers used for user variables and registers that
163 we can't eliminate. A register that appears in this set also can't be used
164 to retry register allocation. */
165 static HARD_REG_SET bad_spill_regs_global;
167 /* Describes order of use of registers for reloading
168 of spilled pseudo-registers. `n_spills' is the number of
169 elements that are actually valid; new ones are added at the end.
171 Both spill_regs and spill_reg_order are used on two occasions:
172 once during find_reload_regs, where they keep track of the spill registers
173 for a single insn, but also during reload_as_needed where they show all
174 the registers ever used by reload. For the latter case, the information
175 is calculated during finish_spills. */
176 static short spill_regs[FIRST_PSEUDO_REGISTER];
178 /* This vector of reg sets indicates, for each pseudo, which hard registers
179 may not be used for retrying global allocation because the register was
180 formerly spilled from one of them. If we allowed reallocating a pseudo to
181 a register that it was already allocated to, reload might not
182 terminate. */
183 static HARD_REG_SET *pseudo_previous_regs;
185 /* This vector of reg sets indicates, for each pseudo, which hard
186 registers may not be used for retrying global allocation because they
187 are used as spill registers during one of the insns in which the
188 pseudo is live. */
189 static HARD_REG_SET *pseudo_forbidden_regs;
191 /* All hard regs that have been used as spill registers for any insn are
192 marked in this set. */
193 static HARD_REG_SET used_spill_regs;
195 /* Index of last register assigned as a spill register. We allocate in
196 a round-robin fashion. */
197 static int last_spill_reg;
199 /* Record the stack slot for each spilled hard register. */
200 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
202 /* Width allocated so far for that stack slot. */
203 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
205 /* Record which pseudos needed to be spilled. */
206 static regset_head spilled_pseudos;
208 /* Record which pseudos changed their allocation in finish_spills. */
209 static regset_head changed_allocation_pseudos;
211 /* Used for communication between order_regs_for_reload and count_pseudo.
212 Used to avoid counting one pseudo twice. */
213 static regset_head pseudos_counted;
215 /* First uid used by insns created by reload in this function.
216 Used in find_equiv_reg. */
217 int reload_first_uid;
219 /* Flag set by local-alloc or global-alloc if anything is live in
220 a call-clobbered reg across calls. */
221 int caller_save_needed;
223 /* Set to 1 while reload_as_needed is operating.
224 Required by some machines to handle any generated moves differently. */
225 int reload_in_progress = 0;
227 /* This obstack is used for allocation of rtl during register elimination.
228 The allocated storage can be freed once find_reloads has processed the
229 insn. */
230 static struct obstack reload_obstack;
232 /* Points to the beginning of the reload_obstack. All insn_chain structures
233 are allocated first. */
234 static char *reload_startobj;
236 /* The point after all insn_chain structures. Used to quickly deallocate
237 memory allocated in copy_reloads during calculate_needs_all_insns. */
238 static char *reload_firstobj;
240 /* This points before all local rtl generated by register elimination.
241 Used to quickly free all memory after processing one insn. */
242 static char *reload_insn_firstobj;
244 /* List of insn_chain instructions, one for every insn that reload needs to
245 examine. */
246 struct insn_chain *reload_insn_chain;
248 /* TRUE if we potentially left dead insns in the insn stream and want to
249 run DCE immediately after reload, FALSE otherwise. */
250 static bool need_dce;
252 /* List of all insns needing reloads. */
253 static struct insn_chain *insns_need_reload;
255 /* This structure is used to record information about register eliminations.
256 Each array entry describes one possible way of eliminating a register
257 in favor of another. If there is more than one way of eliminating a
258 particular register, the most preferred should be specified first. */
260 struct elim_table
262 int from; /* Register number to be eliminated. */
263 int to; /* Register number used as replacement. */
264 poly_int64_pod initial_offset; /* Initial difference between values. */
265 int can_eliminate; /* Nonzero if this elimination can be done. */
266 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
267 target hook in previous scan over insns
268 made by reload. */
269 poly_int64_pod offset; /* Current offset between the two regs. */
270 poly_int64_pod previous_offset; /* Offset at end of previous insn. */
271 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
272 rtx from_rtx; /* REG rtx for the register to be eliminated.
273 We cannot simply compare the number since
274 we might then spuriously replace a hard
275 register corresponding to a pseudo
276 assigned to the reg to be eliminated. */
277 rtx to_rtx; /* REG rtx for the replacement. */
280 static struct elim_table *reg_eliminate = 0;
282 /* This is an intermediate structure to initialize the table. It has
283 exactly the members provided by ELIMINABLE_REGS. */
284 static const struct elim_table_1
286 const int from;
287 const int to;
288 } reg_eliminate_1[] =
290 ELIMINABLE_REGS;
292 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
294 /* Record the number of pending eliminations that have an offset not equal
295 to their initial offset. If nonzero, we use a new copy of each
296 replacement result in any insns encountered. */
297 int num_not_at_initial_offset;
299 /* Count the number of registers that we may be able to eliminate. */
300 static int num_eliminable;
301 /* And the number of registers that are equivalent to a constant that
302 can be eliminated to frame_pointer / arg_pointer + constant. */
303 static int num_eliminable_invariants;
305 /* For each label, we record the offset of each elimination. If we reach
306 a label by more than one path and an offset differs, we cannot do the
307 elimination. This information is indexed by the difference of the
308 number of the label and the first label number. We can't offset the
309 pointer itself as this can cause problems on machines with segmented
310 memory. The first table is an array of flags that records whether we
311 have yet encountered a label and the second table is an array of arrays,
312 one entry in the latter array for each elimination. */
314 static int first_label_num;
315 static char *offsets_known_at;
316 static poly_int64_pod (*offsets_at)[NUM_ELIMINABLE_REGS];
318 vec<reg_equivs_t, va_gc> *reg_equivs;
320 /* Stack of addresses where an rtx has been changed. We can undo the
321 changes by popping items off the stack and restoring the original
322 value at each location.
324 We use this simplistic undo capability rather than copy_rtx as copy_rtx
325 will not make a deep copy of a normally sharable rtx, such as
326 (const (plus (symbol_ref) (const_int))). If such an expression appears
327 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
328 rtx expression would be changed. See PR 42431. */
330 typedef rtx *rtx_p;
331 static vec<rtx_p> substitute_stack;
333 /* Number of labels in the current function. */
335 static int num_labels;
337 static void replace_pseudos_in (rtx *, machine_mode, rtx);
338 static void maybe_fix_stack_asms (void);
339 static void copy_reloads (struct insn_chain *);
340 static void calculate_needs_all_insns (int);
341 static int find_reg (struct insn_chain *, int);
342 static void find_reload_regs (struct insn_chain *);
343 static void select_reload_regs (void);
344 static void delete_caller_save_insns (void);
346 static void spill_failure (rtx_insn *, enum reg_class);
347 static void count_spilled_pseudo (int, int, int);
348 static void delete_dead_insn (rtx_insn *);
349 static void alter_reg (int, int, bool);
350 static void set_label_offsets (rtx, rtx_insn *, int);
351 static void check_eliminable_occurrences (rtx);
352 static void elimination_effects (rtx, machine_mode);
353 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
354 static int eliminate_regs_in_insn (rtx_insn *, int);
355 static void update_eliminable_offsets (void);
356 static void mark_not_eliminable (rtx, const_rtx, void *);
357 static void set_initial_elim_offsets (void);
358 static bool verify_initial_elim_offsets (void);
359 static void set_initial_label_offsets (void);
360 static void set_offsets_for_label (rtx_insn *);
361 static void init_eliminable_invariants (rtx_insn *, bool);
362 static void init_elim_table (void);
363 static void free_reg_equiv (void);
364 static void update_eliminables (HARD_REG_SET *);
365 static bool update_eliminables_and_spill (void);
366 static void elimination_costs_in_insn (rtx_insn *);
367 static void spill_hard_reg (unsigned int, int);
368 static int finish_spills (int);
369 static void scan_paradoxical_subregs (rtx);
370 static void count_pseudo (int);
371 static void order_regs_for_reload (struct insn_chain *);
372 static void reload_as_needed (int);
373 static void forget_old_reloads_1 (rtx, const_rtx, void *);
374 static void forget_marked_reloads (regset);
375 static int reload_reg_class_lower (const void *, const void *);
376 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
377 machine_mode);
378 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
379 machine_mode);
380 static int reload_reg_free_p (unsigned int, int, enum reload_type);
381 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
382 rtx, rtx, int, int);
383 static int free_for_value_p (int, machine_mode, int, enum reload_type,
384 rtx, rtx, int, int);
385 static int allocate_reload_reg (struct insn_chain *, int, int);
386 static int conflicts_with_override (rtx);
387 static void failed_reload (rtx_insn *, int);
388 static int set_reload_reg (int, int);
389 static void choose_reload_regs_init (struct insn_chain *, rtx *);
390 static void choose_reload_regs (struct insn_chain *);
391 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
392 rtx, int);
393 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
394 int);
395 static void do_input_reload (struct insn_chain *, struct reload *, int);
396 static void do_output_reload (struct insn_chain *, struct reload *, int);
397 static void emit_reload_insns (struct insn_chain *);
398 static void delete_output_reload (rtx_insn *, int, int, rtx);
399 static void delete_address_reloads (rtx_insn *, rtx_insn *);
400 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
401 static void inc_for_reload (rtx, rtx, rtx, poly_int64);
402 static void add_auto_inc_notes (rtx_insn *, rtx);
403 static void substitute (rtx *, const_rtx, rtx);
404 static bool gen_reload_chain_without_interm_reg_p (int, int);
405 static int reloads_conflict (int, int);
406 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
407 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
409 /* Initialize the reload pass. This is called at the beginning of compilation
410 and may be called again if the target is reinitialized. */
412 void
413 init_reload (void)
415 int i;
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
421 rtx tem
422 = gen_rtx_MEM (Pmode,
423 gen_rtx_PLUS (Pmode,
424 gen_rtx_REG (Pmode,
425 LAST_VIRTUAL_REGISTER + 1),
426 gen_int_mode (4, Pmode)));
427 spill_indirect_levels = 0;
429 while (memory_address_p (QImode, tem))
431 spill_indirect_levels++;
432 tem = gen_rtx_MEM (Pmode, tem);
435 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
438 indirect_symref_ok = memory_address_p (QImode, tem);
440 /* See if reg+reg is a valid (and offsettable) address. */
442 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
444 tem = gen_rtx_PLUS (Pmode,
445 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
446 gen_rtx_REG (Pmode, i));
448 /* This way, we make sure that reg+reg is an offsettable address. */
449 tem = plus_constant (Pmode, tem, 4);
451 for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
452 if (!double_reg_address_ok[mode]
453 && memory_address_p ((enum machine_mode)mode, tem))
454 double_reg_address_ok[mode] = 1;
457 /* Initialize obstack for our rtl allocation. */
458 if (reload_startobj == NULL)
460 gcc_obstack_init (&reload_obstack);
461 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
464 INIT_REG_SET (&spilled_pseudos);
465 INIT_REG_SET (&changed_allocation_pseudos);
466 INIT_REG_SET (&pseudos_counted);
469 /* List of insn chains that are currently unused. */
470 static struct insn_chain *unused_insn_chains = 0;
472 /* Allocate an empty insn_chain structure. */
473 struct insn_chain *
474 new_insn_chain (void)
476 struct insn_chain *c;
478 if (unused_insn_chains == 0)
480 c = XOBNEW (&reload_obstack, struct insn_chain);
481 INIT_REG_SET (&c->live_throughout);
482 INIT_REG_SET (&c->dead_or_set);
484 else
486 c = unused_insn_chains;
487 unused_insn_chains = c->next;
489 c->is_caller_save_insn = 0;
490 c->need_operand_change = 0;
491 c->need_reload = 0;
492 c->need_elim = 0;
493 return c;
496 /* Small utility function to set all regs in hard reg set TO which are
497 allocated to pseudos in regset FROM. */
499 void
500 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
502 unsigned int regno;
503 reg_set_iterator rsi;
505 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
507 int r = reg_renumber[regno];
509 if (r < 0)
511 /* reload_combine uses the information from DF_LIVE_IN,
512 which might still contain registers that have not
513 actually been allocated since they have an
514 equivalence. */
515 gcc_assert (ira_conflicts_p || reload_completed);
517 else
518 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
522 /* Replace all pseudos found in LOC with their corresponding
523 equivalences. */
525 static void
526 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
528 rtx x = *loc;
529 enum rtx_code code;
530 const char *fmt;
531 int i, j;
533 if (! x)
534 return;
536 code = GET_CODE (x);
537 if (code == REG)
539 unsigned int regno = REGNO (x);
541 if (regno < FIRST_PSEUDO_REGISTER)
542 return;
544 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
545 if (x != *loc)
547 *loc = x;
548 replace_pseudos_in (loc, mem_mode, usage);
549 return;
552 if (reg_equiv_constant (regno))
553 *loc = reg_equiv_constant (regno);
554 else if (reg_equiv_invariant (regno))
555 *loc = reg_equiv_invariant (regno);
556 else if (reg_equiv_mem (regno))
557 *loc = reg_equiv_mem (regno);
558 else if (reg_equiv_address (regno))
559 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
560 else
562 gcc_assert (!REG_P (regno_reg_rtx[regno])
563 || REGNO (regno_reg_rtx[regno]) != regno);
564 *loc = regno_reg_rtx[regno];
567 return;
569 else if (code == MEM)
571 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
572 return;
575 /* Process each of our operands recursively. */
576 fmt = GET_RTX_FORMAT (code);
577 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
578 if (*fmt == 'e')
579 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
580 else if (*fmt == 'E')
581 for (j = 0; j < XVECLEN (x, i); j++)
582 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
585 /* Determine if the current function has an exception receiver block
586 that reaches the exit block via non-exceptional edges */
588 static bool
589 has_nonexceptional_receiver (void)
591 edge e;
592 edge_iterator ei;
593 basic_block *tos, *worklist, bb;
595 /* If we're not optimizing, then just err on the safe side. */
596 if (!optimize)
597 return true;
599 /* First determine which blocks can reach exit via normal paths. */
600 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
602 FOR_EACH_BB_FN (bb, cfun)
603 bb->flags &= ~BB_REACHABLE;
605 /* Place the exit block on our worklist. */
606 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
607 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
609 /* Iterate: find everything reachable from what we've already seen. */
610 while (tos != worklist)
612 bb = *--tos;
614 FOR_EACH_EDGE (e, ei, bb->preds)
615 if (!(e->flags & EDGE_ABNORMAL))
617 basic_block src = e->src;
619 if (!(src->flags & BB_REACHABLE))
621 src->flags |= BB_REACHABLE;
622 *tos++ = src;
626 free (worklist);
628 /* Now see if there's a reachable block with an exceptional incoming
629 edge. */
630 FOR_EACH_BB_FN (bb, cfun)
631 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
632 return true;
634 /* No exceptional block reached exit unexceptionally. */
635 return false;
638 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
639 zero elements) to MAX_REG_NUM elements.
641 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
642 void
643 grow_reg_equivs (void)
645 int old_size = vec_safe_length (reg_equivs);
646 int max_regno = max_reg_num ();
647 int i;
648 reg_equivs_t ze;
650 memset (&ze, 0, sizeof (reg_equivs_t));
651 vec_safe_reserve (reg_equivs, max_regno);
652 for (i = old_size; i < max_regno; i++)
653 reg_equivs->quick_insert (i, ze);
657 /* Global variables used by reload and its subroutines. */
659 /* The current basic block while in calculate_elim_costs_all_insns. */
660 static basic_block elim_bb;
662 /* Set during calculate_needs if an insn needs register elimination. */
663 static int something_needs_elimination;
664 /* Set during calculate_needs if an insn needs an operand changed. */
665 static int something_needs_operands_changed;
666 /* Set by alter_regs if we spilled a register to the stack. */
667 static bool something_was_spilled;
669 /* Nonzero means we couldn't get enough spill regs. */
670 static int failure;
672 /* Temporary array of pseudo-register number. */
673 static int *temp_pseudo_reg_arr;
675 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
676 If that insn didn't set the register (i.e., it copied the register to
677 memory), just delete that insn instead of the equivalencing insn plus
678 anything now dead. If we call delete_dead_insn on that insn, we may
679 delete the insn that actually sets the register if the register dies
680 there and that is incorrect. */
681 static void
682 remove_init_insns ()
684 for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
688 rtx list;
689 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
691 rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
693 /* If we already deleted the insn or if it may trap, we can't
694 delete it. The latter case shouldn't happen, but can
695 if an insn has a variable address, gets a REG_EH_REGION
696 note added to it, and then gets converted into a load
697 from a constant address. */
698 if (NOTE_P (equiv_insn)
699 || can_throw_internal (equiv_insn))
701 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
702 delete_dead_insn (equiv_insn);
703 else
704 SET_INSN_DELETED (equiv_insn);
710 /* Return true if remove_init_insns will delete INSN. */
711 static bool
712 will_delete_init_insn_p (rtx_insn *insn)
714 rtx set = single_set (insn);
715 if (!set || !REG_P (SET_DEST (set)))
716 return false;
717 unsigned regno = REGNO (SET_DEST (set));
719 if (can_throw_internal (insn))
720 return false;
722 if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
723 return false;
725 for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
727 rtx equiv_insn = XEXP (list, 0);
728 if (equiv_insn == insn)
729 return true;
731 return false;
734 /* Main entry point for the reload pass.
736 FIRST is the first insn of the function being compiled.
738 GLOBAL nonzero means we were called from global_alloc
739 and should attempt to reallocate any pseudoregs that we
740 displace from hard regs we will use for reloads.
741 If GLOBAL is zero, we do not have enough information to do that,
742 so any pseudo reg that is spilled must go to the stack.
744 Return value is TRUE if reload likely left dead insns in the
745 stream and a DCE pass should be run to elimiante them. Else the
746 return value is FALSE. */
748 bool
749 reload (rtx_insn *first, int global)
751 int i, n;
752 rtx_insn *insn;
753 struct elim_table *ep;
754 basic_block bb;
755 bool inserted;
757 /* Make sure even insns with volatile mem refs are recognizable. */
758 init_recog ();
760 failure = 0;
762 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
764 /* Make sure that the last insn in the chain
765 is not something that needs reloading. */
766 emit_note (NOTE_INSN_DELETED);
768 /* Enable find_equiv_reg to distinguish insns made by reload. */
769 reload_first_uid = get_max_uid ();
771 /* Initialize the secondary memory table. */
772 clear_secondary_mem ();
774 /* We don't have a stack slot for any spill reg yet. */
775 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
776 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
778 /* Initialize the save area information for caller-save, in case some
779 are needed. */
780 init_save_areas ();
782 /* Compute which hard registers are now in use
783 as homes for pseudo registers.
784 This is done here rather than (eg) in global_alloc
785 because this point is reached even if not optimizing. */
786 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
787 mark_home_live (i);
789 /* A function that has a nonlocal label that can reach the exit
790 block via non-exceptional paths must save all call-saved
791 registers. */
792 if (cfun->has_nonlocal_label
793 && has_nonexceptional_receiver ())
794 crtl->saves_all_registers = 1;
796 if (crtl->saves_all_registers)
797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
798 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
799 df_set_regs_ever_live (i, true);
801 /* Find all the pseudo registers that didn't get hard regs
802 but do have known equivalent constants or memory slots.
803 These include parameters (known equivalent to parameter slots)
804 and cse'd or loop-moved constant memory addresses.
806 Record constant equivalents in reg_equiv_constant
807 so they will be substituted by find_reloads.
808 Record memory equivalents in reg_mem_equiv so they can
809 be substituted eventually by altering the REG-rtx's. */
811 grow_reg_equivs ();
812 reg_old_renumber = XCNEWVEC (short, max_regno);
813 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
814 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
815 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
817 CLEAR_HARD_REG_SET (bad_spill_regs_global);
819 init_eliminable_invariants (first, true);
820 init_elim_table ();
822 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
823 stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
827 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
828 temp_pseudo_reg_arr[n++] = i;
830 if (ira_conflicts_p)
831 /* Ask IRA to order pseudo-registers for better stack slot
832 sharing. */
833 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);
835 for (i = 0; i < n; i++)
836 alter_reg (temp_pseudo_reg_arr[i], -1, false);
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
843 cannot be done. */
844 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 if (INSN_P (insn))
846 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
848 maybe_fix_stack_asms ();
850 insns_need_reload = 0;
851 something_needs_elimination = 0;
853 /* Initialize to -1, which means take the first spill register. */
854 last_spill_reg = -1;
856 /* Spill any hard regs that we know we can't eliminate. */
857 CLEAR_HARD_REG_SET (used_spill_regs);
858 /* There can be multiple ways to eliminate a register;
859 they should be listed adjacently.
860 Elimination for any register fails only if all possible ways fail. */
861 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
863 int from = ep->from;
864 int can_eliminate = 0;
867 can_eliminate |= ep->can_eliminate;
868 ep++;
870 while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 if (! can_eliminate)
872 spill_hard_reg (from, 1);
875 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
887 for (;;)
889 int something_changed;
890 poly_int64 starting_frame_size;
892 starting_frame_size = get_frame_size ();
893 something_was_spilled = false;
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
901 is the normal case.
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
925 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
926 NULL_RTX);
928 if (strict_memory_address_addr_space_p
929 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
930 MEM_ADDR_SPACE (x)))
931 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
932 else if (CONSTANT_P (XEXP (x, 0))
933 || (REG_P (XEXP (x, 0))
934 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
935 || (GET_CODE (XEXP (x, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x, 0), 0))
937 && (REGNO (XEXP (XEXP (x, 0), 0))
938 < FIRST_PSEUDO_REGISTER)
939 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
940 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
941 else
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
948 the loop. */
949 reg_equiv_memory_loc (i) = 0;
950 reg_equiv_init (i) = 0;
951 alter_reg (i, -1, true);
955 if (caller_save_needed)
956 setup_save_areas ();
958 if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed)
960 /* If we have a stack frame, we must align it now. The
961 stack size may be a part of the offset computation for
962 register elimination. So if this changes the stack size,
963 then repeat the elimination bookkeeping. We don't
964 realign when there is no stack, as that will cause a
965 stack frame when none is needed should
966 TARGET_STARTING_FRAME_OFFSET not be already aligned to
967 STACK_BOUNDARY. */
968 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
970 /* If we allocated another stack slot, redo elimination bookkeeping. */
971 if (something_was_spilled
972 || maybe_ne (starting_frame_size, get_frame_size ()))
974 if (update_eliminables_and_spill ())
975 finish_spills (0);
976 continue;
979 if (caller_save_needed)
981 save_call_clobbered_regs ();
982 /* That might have allocated new insn_chain structures. */
983 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
986 calculate_needs_all_insns (global);
988 if (! ira_conflicts_p)
989 /* Don't do it for IRA. We need this info because we don't
990 change live_throughout and dead_or_set for chains when IRA
991 is used. */
992 CLEAR_REG_SET (&spilled_pseudos);
994 something_changed = 0;
996 /* If we allocated any new memory locations, make another pass
997 since it might have changed elimination offsets. */
998 if (something_was_spilled
999 || maybe_ne (starting_frame_size, get_frame_size ()))
1000 something_changed = 1;
1002 /* Even if the frame size remained the same, we might still have
1003 changed elimination offsets, e.g. if find_reloads called
1004 force_const_mem requiring the back end to allocate a constant
1005 pool base register that needs to be saved on the stack. */
1006 else if (!verify_initial_elim_offsets ())
1007 something_changed = 1;
1009 if (update_eliminables_and_spill ())
1011 finish_spills (0);
1012 something_changed = 1;
1014 else
1016 select_reload_regs ();
1017 if (failure)
1018 goto failed;
1019 if (insns_need_reload)
1020 something_changed |= finish_spills (global);
1023 if (! something_changed)
1024 break;
1026 if (caller_save_needed)
1027 delete_caller_save_insns ();
1029 obstack_free (&reload_obstack, reload_firstobj);
1032 /* If global-alloc was run, notify it of any register eliminations we have
1033 done. */
1034 if (global)
1035 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1036 if (ep->can_eliminate)
1037 mark_elimination (ep->from, ep->to);
1039 remove_init_insns ();
1041 /* Use the reload registers where necessary
1042 by generating move instructions to move the must-be-register
1043 values into or out of the reload registers. */
1045 if (insns_need_reload != 0 || something_needs_elimination
1046 || something_needs_operands_changed)
1048 poly_int64 old_frame_size = get_frame_size ();
1050 reload_as_needed (global);
1052 gcc_assert (known_eq (old_frame_size, get_frame_size ()));
1054 gcc_assert (verify_initial_elim_offsets ());
1057 /* If we were able to eliminate the frame pointer, show that it is no
1058 longer live at the start of any basic block. If it ls live by
1059 virtue of being in a pseudo, that pseudo will be marked live
1060 and hence the frame pointer will be known to be live via that
1061 pseudo. */
1063 if (! frame_pointer_needed)
1064 FOR_EACH_BB_FN (bb, cfun)
1065 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1067 /* Come here (with failure set nonzero) if we can't get enough spill
1068 regs. */
1069 failed:
1071 CLEAR_REG_SET (&changed_allocation_pseudos);
1072 CLEAR_REG_SET (&spilled_pseudos);
1073 reload_in_progress = 0;
1075 /* Now eliminate all pseudo regs by modifying them into
1076 their equivalent memory references.
1077 The REG-rtx's for the pseudos are modified in place,
1078 so all insns that used to refer to them now refer to memory.
1080 For a reg that has a reg_equiv_address, all those insns
1081 were changed by reloading so that no insns refer to it any longer;
1082 but the DECL_RTL of a variable decl may refer to it,
1083 and if so this causes the debugging info to mention the variable. */
1085 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1087 rtx addr = 0;
1089 if (reg_equiv_mem (i))
1090 addr = XEXP (reg_equiv_mem (i), 0);
1092 if (reg_equiv_address (i))
1093 addr = reg_equiv_address (i);
1095 if (addr)
1097 if (reg_renumber[i] < 0)
1099 rtx reg = regno_reg_rtx[i];
1101 REG_USERVAR_P (reg) = 0;
1102 PUT_CODE (reg, MEM);
1103 XEXP (reg, 0) = addr;
1104 if (reg_equiv_memory_loc (i))
1105 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1106 else
1107 MEM_ATTRS (reg) = 0;
1108 MEM_NOTRAP_P (reg) = 1;
1110 else if (reg_equiv_mem (i))
1111 XEXP (reg_equiv_mem (i), 0) = addr;
1114 /* We don't want complex addressing modes in debug insns
1115 if simpler ones will do, so delegitimize equivalences
1116 in debug insns. */
1117 if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
1119 rtx reg = regno_reg_rtx[i];
1120 rtx equiv = 0;
1121 df_ref use, next;
1123 if (reg_equiv_constant (i))
1124 equiv = reg_equiv_constant (i);
1125 else if (reg_equiv_invariant (i))
1126 equiv = reg_equiv_invariant (i);
1127 else if (reg && MEM_P (reg))
1128 equiv = targetm.delegitimize_address (reg);
1129 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1130 equiv = reg;
1132 if (equiv == reg)
1133 continue;
1135 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1137 insn = DF_REF_INSN (use);
1139 /* Make sure the next ref is for a different instruction,
1140 so that we're not affected by the rescan. */
1141 next = DF_REF_NEXT_REG (use);
1142 while (next && DF_REF_INSN (next) == insn)
1143 next = DF_REF_NEXT_REG (next);
1145 if (DEBUG_BIND_INSN_P (insn))
1147 if (!equiv)
1149 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1150 df_insn_rescan_debug_internal (insn);
1152 else
1153 INSN_VAR_LOCATION_LOC (insn)
1154 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1155 reg, equiv);
1161 /* We must set reload_completed now since the cleanup_subreg_operands call
1162 below will re-recognize each insn and reload may have generated insns
1163 which are only valid during and after reload. */
1164 reload_completed = 1;
1166 /* Make a pass over all the insns and delete all USEs which we inserted
1167 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1168 notes. Delete all CLOBBER insns, except those that refer to the return
1169 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1170 from misarranging variable-array code, and simplify (subreg (reg))
1171 operands. Strip and regenerate REG_INC notes that may have been moved
1172 around. */
1174 for (insn = first; insn; insn = NEXT_INSN (insn))
1175 if (INSN_P (insn))
1177 rtx *pnote;
1179 if (CALL_P (insn))
1180 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1181 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1183 if ((GET_CODE (PATTERN (insn)) == USE
1184 /* We mark with QImode USEs introduced by reload itself. */
1185 && (GET_MODE (insn) == QImode
1186 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1187 || (GET_CODE (PATTERN (insn)) == CLOBBER
1188 && (!MEM_P (XEXP (PATTERN (insn), 0))
1189 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1190 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1191 && XEXP (XEXP (PATTERN (insn), 0), 0)
1192 != stack_pointer_rtx))
1193 && (!REG_P (XEXP (PATTERN (insn), 0))
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1196 delete_insn (insn);
1197 continue;
1200 /* Some CLOBBERs may survive until here and still reference unassigned
1201 pseudos with const equivalent, which may in turn cause ICE in later
1202 passes if the reference remains in place. */
1203 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1204 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1205 VOIDmode, PATTERN (insn));
1207 /* Discard obvious no-ops, even without -O. This optimization
1208 is fast and doesn't interfere with debugging. */
1209 if (NONJUMP_INSN_P (insn)
1210 && GET_CODE (PATTERN (insn)) == SET
1211 && REG_P (SET_SRC (PATTERN (insn)))
1212 && REG_P (SET_DEST (PATTERN (insn)))
1213 && (REGNO (SET_SRC (PATTERN (insn)))
1214 == REGNO (SET_DEST (PATTERN (insn)))))
1216 delete_insn (insn);
1217 continue;
1220 pnote = &REG_NOTES (insn);
1221 while (*pnote != 0)
1223 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1224 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1225 || REG_NOTE_KIND (*pnote) == REG_INC)
1226 *pnote = XEXP (*pnote, 1);
1227 else
1228 pnote = &XEXP (*pnote, 1);
1231 if (AUTO_INC_DEC)
1232 add_auto_inc_notes (insn, PATTERN (insn));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1238 See PR 21299. */
1239 if (asm_noperands (PATTERN (insn)) >= 0)
1241 extract_insn (insn);
1242 if (!constrain_operands (1, get_enabled_alternatives (insn)))
1244 error_for_asm (insn,
1245 "%<asm%> operand has impossible constraints");
1246 delete_insn (insn);
1247 continue;
1252 free (temp_pseudo_reg_arr);
1254 /* Indicate that we no longer have known memory locations or constants. */
1255 free_reg_equiv ();
1257 free (reg_max_ref_mode);
1258 free (reg_old_renumber);
1259 free (pseudo_previous_regs);
1260 free (pseudo_forbidden_regs);
1262 CLEAR_HARD_REG_SET (used_spill_regs);
1263 for (i = 0; i < n_spills; i++)
1264 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1266 /* Free all the insn_chain structures at once. */
1267 obstack_free (&reload_obstack, reload_startobj);
1268 unused_insn_chains = 0;
1270 inserted = fixup_abnormal_edges ();
1272 /* We've possibly turned single trapping insn into multiple ones. */
1273 if (cfun->can_throw_non_call_exceptions)
1275 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
1276 bitmap_ones (blocks);
1277 find_many_sub_basic_blocks (blocks);
1280 if (inserted)
1281 commit_edge_insertions ();
1283 /* Replacing pseudos with their memory equivalents might have
1284 created shared rtx. Subsequent passes would get confused
1285 by this, so unshare everything here. */
1286 unshare_all_rtl_again (first);
1288 #ifdef STACK_BOUNDARY
1289 /* init_emit has set the alignment of the hard frame pointer
1290 to STACK_BOUNDARY. It is very likely no longer valid if
1291 the hard frame pointer was used for register allocation. */
1292 if (!frame_pointer_needed)
1293 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1294 #endif
1296 substitute_stack.release ();
1298 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1300 reload_completed = !failure;
1302 return need_dce;
1305 /* Yet another special case. Unfortunately, reg-stack forces people to
1306 write incorrect clobbers in asm statements. These clobbers must not
1307 cause the register to appear in bad_spill_regs, otherwise we'll call
1308 fatal_insn later. We clear the corresponding regnos in the live
1309 register sets to avoid this.
1310 The whole thing is rather sick, I'm afraid. */
1312 static void
1313 maybe_fix_stack_asms (void)
1315 #ifdef STACK_REGS
1316 const char *constraints[MAX_RECOG_OPERANDS];
1317 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1318 struct insn_chain *chain;
1320 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1322 int i, noperands;
1323 HARD_REG_SET clobbered, allowed;
1324 rtx pat;
1326 if (! INSN_P (chain->insn)
1327 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1328 continue;
1329 pat = PATTERN (chain->insn);
1330 if (GET_CODE (pat) != PARALLEL)
1331 continue;
1333 CLEAR_HARD_REG_SET (clobbered);
1334 CLEAR_HARD_REG_SET (allowed);
1336 /* First, make a mask of all stack regs that are clobbered. */
1337 for (i = 0; i < XVECLEN (pat, 0); i++)
1339 rtx t = XVECEXP (pat, 0, i);
1340 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1341 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1344 /* Get the operand values and constraints out of the insn. */
1345 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1346 constraints, operand_mode, NULL);
1348 /* For every operand, see what registers are allowed. */
1349 for (i = 0; i < noperands; i++)
1351 const char *p = constraints[i];
1352 /* For every alternative, we compute the class of registers allowed
1353 for reloading in CLS, and merge its contents into the reg set
1354 ALLOWED. */
1355 int cls = (int) NO_REGS;
1357 for (;;)
1359 char c = *p;
1361 if (c == '\0' || c == ',' || c == '#')
1363 /* End of one alternative - mark the regs in the current
1364 class, and reset the class. */
1365 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1366 cls = NO_REGS;
1367 p++;
1368 if (c == '#')
1369 do {
1370 c = *p++;
1371 } while (c != '\0' && c != ',');
1372 if (c == '\0')
1373 break;
1374 continue;
1377 switch (c)
1379 case 'g':
1380 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1381 break;
1383 default:
1384 enum constraint_num cn = lookup_constraint (p);
1385 if (insn_extra_address_constraint (cn))
1386 cls = (int) reg_class_subunion[cls]
1387 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1388 ADDRESS, SCRATCH)];
1389 else
1390 cls = (int) reg_class_subunion[cls]
1391 [reg_class_for_constraint (cn)];
1392 break;
1394 p += CONSTRAINT_LEN (c, p);
1397 /* Those of the registers which are clobbered, but allowed by the
1398 constraints, must be usable as reload registers. So clear them
1399 out of the life information. */
1400 AND_HARD_REG_SET (allowed, clobbered);
1401 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1402 if (TEST_HARD_REG_BIT (allowed, i))
1404 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1405 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1409 #endif
1412 /* Copy the global variables n_reloads and rld into the corresponding elts
1413 of CHAIN. */
1414 static void
1415 copy_reloads (struct insn_chain *chain)
1417 chain->n_reloads = n_reloads;
1418 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1419 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1420 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1423 /* Walk the chain of insns, and determine for each whether it needs reloads
1424 and/or eliminations. Build the corresponding insns_need_reload list, and
1425 set something_needs_elimination as appropriate. */
1426 static void
1427 calculate_needs_all_insns (int global)
1429 struct insn_chain **pprev_reload = &insns_need_reload;
1430 struct insn_chain *chain, *next = 0;
1432 something_needs_elimination = 0;
1434 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1435 for (chain = reload_insn_chain; chain != 0; chain = next)
1437 rtx_insn *insn = chain->insn;
1439 next = chain->next;
1441 /* Clear out the shortcuts. */
1442 chain->n_reloads = 0;
1443 chain->need_elim = 0;
1444 chain->need_reload = 0;
1445 chain->need_operand_change = 0;
1447 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1448 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1449 what effects this has on the known offsets at labels. */
1451 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1452 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1453 set_label_offsets (insn, insn, 0);
1455 if (INSN_P (insn))
1457 rtx old_body = PATTERN (insn);
1458 int old_code = INSN_CODE (insn);
1459 rtx old_notes = REG_NOTES (insn);
1460 int did_elimination = 0;
1461 int operands_changed = 0;
1463 /* Skip insns that only set an equivalence. */
1464 if (will_delete_init_insn_p (insn))
1465 continue;
1467 /* If needed, eliminate any eliminable registers. */
1468 if (num_eliminable || num_eliminable_invariants)
1469 did_elimination = eliminate_regs_in_insn (insn, 0);
1471 /* Analyze the instruction. */
1472 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1473 global, spill_reg_order);
1475 /* If a no-op set needs more than one reload, this is likely
1476 to be something that needs input address reloads. We
1477 can't get rid of this cleanly later, and it is of no use
1478 anyway, so discard it now.
1479 We only do this when expensive_optimizations is enabled,
1480 since this complements reload inheritance / output
1481 reload deletion, and it can make debugging harder. */
1482 if (flag_expensive_optimizations && n_reloads > 1)
1484 rtx set = single_set (insn);
1485 if (set
1487 ((SET_SRC (set) == SET_DEST (set)
1488 && REG_P (SET_SRC (set))
1489 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1490 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1491 && reg_renumber[REGNO (SET_SRC (set))] < 0
1492 && reg_renumber[REGNO (SET_DEST (set))] < 0
1493 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1494 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1495 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1496 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1498 if (ira_conflicts_p)
1499 /* Inform IRA about the insn deletion. */
1500 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1501 REGNO (SET_SRC (set)));
1502 delete_insn (insn);
1503 /* Delete it from the reload chain. */
1504 if (chain->prev)
1505 chain->prev->next = next;
1506 else
1507 reload_insn_chain = next;
1508 if (next)
1509 next->prev = chain->prev;
1510 chain->next = unused_insn_chains;
1511 unused_insn_chains = chain;
1512 continue;
1515 if (num_eliminable)
1516 update_eliminable_offsets ();
1518 /* Remember for later shortcuts which insns had any reloads or
1519 register eliminations. */
1520 chain->need_elim = did_elimination;
1521 chain->need_reload = n_reloads > 0;
1522 chain->need_operand_change = operands_changed;
1524 /* Discard any register replacements done. */
1525 if (did_elimination)
1527 obstack_free (&reload_obstack, reload_insn_firstobj);
1528 PATTERN (insn) = old_body;
1529 INSN_CODE (insn) = old_code;
1530 REG_NOTES (insn) = old_notes;
1531 something_needs_elimination = 1;
1534 something_needs_operands_changed |= operands_changed;
1536 if (n_reloads != 0)
1538 copy_reloads (chain);
1539 *pprev_reload = chain;
1540 pprev_reload = &chain->next_need_reload;
1544 *pprev_reload = 0;
1547 /* This function is called from the register allocator to set up estimates
1548 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1549 an invariant. The structure is similar to calculate_needs_all_insns. */
1551 void
1552 calculate_elim_costs_all_insns (void)
1554 int *reg_equiv_init_cost;
1555 basic_block bb;
1556 int i;
1558 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1559 init_elim_table ();
1560 init_eliminable_invariants (get_insns (), false);
1562 set_initial_elim_offsets ();
1563 set_initial_label_offsets ();
1565 FOR_EACH_BB_FN (bb, cfun)
1567 rtx_insn *insn;
1568 elim_bb = bb;
1570 FOR_BB_INSNS (bb, insn)
1572 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1573 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1574 what effects this has on the known offsets at labels. */
1576 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1577 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1578 set_label_offsets (insn, insn, 0);
1580 if (INSN_P (insn))
1582 rtx set = single_set (insn);
1584 /* Skip insns that only set an equivalence. */
1585 if (set && REG_P (SET_DEST (set))
1586 && reg_renumber[REGNO (SET_DEST (set))] < 0
1587 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1588 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1590 unsigned regno = REGNO (SET_DEST (set));
1591 rtx_insn_list *init = reg_equiv_init (regno);
1592 if (init)
1594 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1595 false, true);
1596 machine_mode mode = GET_MODE (SET_DEST (set));
1597 int cost = set_src_cost (t, mode,
1598 optimize_bb_for_speed_p (bb));
1599 int freq = REG_FREQ_FROM_BB (bb);
1601 reg_equiv_init_cost[regno] = cost * freq;
1602 continue;
1605 /* If needed, eliminate any eliminable registers. */
1606 if (num_eliminable || num_eliminable_invariants)
1607 elimination_costs_in_insn (insn);
1609 if (num_eliminable)
1610 update_eliminable_offsets ();
1614 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1616 if (reg_equiv_invariant (i))
1618 if (reg_equiv_init (i))
1620 int cost = reg_equiv_init_cost[i];
1621 if (dump_file)
1622 fprintf (dump_file,
1623 "Reg %d has equivalence, initial gains %d\n", i, cost);
1624 if (cost != 0)
1625 ira_adjust_equiv_reg_cost (i, cost);
1627 else
1629 if (dump_file)
1630 fprintf (dump_file,
1631 "Reg %d had equivalence, but can't be eliminated\n",
1633 ira_adjust_equiv_reg_cost (i, 0);
1638 free (reg_equiv_init_cost);
1639 free (offsets_known_at);
1640 free (offsets_at);
1641 offsets_at = NULL;
1642 offsets_known_at = NULL;
1645 /* Comparison function for qsort to decide which of two reloads
1646 should be handled first. *P1 and *P2 are the reload numbers. */
1648 static int
1649 reload_reg_class_lower (const void *r1p, const void *r2p)
1651 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1652 int t;
1654 /* Consider required reloads before optional ones. */
1655 t = rld[r1].optional - rld[r2].optional;
1656 if (t != 0)
1657 return t;
1659 /* Count all solitary classes before non-solitary ones. */
1660 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1661 - (reg_class_size[(int) rld[r1].rclass] == 1));
1662 if (t != 0)
1663 return t;
1665 /* Aside from solitaires, consider all multi-reg groups first. */
1666 t = rld[r2].nregs - rld[r1].nregs;
1667 if (t != 0)
1668 return t;
1670 /* Consider reloads in order of increasing reg-class number. */
1671 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1672 if (t != 0)
1673 return t;
1675 /* If reloads are equally urgent, sort by reload number,
1676 so that the results of qsort leave nothing to chance. */
1677 return r1 - r2;
1680 /* The cost of spilling each hard reg. */
1681 static int spill_cost[FIRST_PSEUDO_REGISTER];
1683 /* When spilling multiple hard registers, we use SPILL_COST for the first
1684 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1685 only the first hard reg for a multi-reg pseudo. */
1686 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1688 /* Map of hard regno to pseudo regno currently occupying the hard
1689 reg. */
1690 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1692 /* Update the spill cost arrays, considering that pseudo REG is live. */
1694 static void
1695 count_pseudo (int reg)
1697 int freq = REG_FREQ (reg);
1698 int r = reg_renumber[reg];
1699 int nregs;
1701 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1702 if (ira_conflicts_p && r < 0)
1703 return;
1705 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1706 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1707 return;
1709 SET_REGNO_REG_SET (&pseudos_counted, reg);
1711 gcc_assert (r >= 0);
1713 spill_add_cost[r] += freq;
1714 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1715 while (nregs-- > 0)
1717 hard_regno_to_pseudo_regno[r + nregs] = reg;
1718 spill_cost[r + nregs] += freq;
1722 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1723 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1725 static void
1726 order_regs_for_reload (struct insn_chain *chain)
1728 unsigned i;
1729 HARD_REG_SET used_by_pseudos;
1730 HARD_REG_SET used_by_pseudos2;
1731 reg_set_iterator rsi;
1733 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1735 memset (spill_cost, 0, sizeof spill_cost);
1736 memset (spill_add_cost, 0, sizeof spill_add_cost);
1737 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1738 hard_regno_to_pseudo_regno[i] = -1;
1740 /* Count number of uses of each hard reg by pseudo regs allocated to it
1741 and then order them by decreasing use. First exclude hard registers
1742 that are live in or across this insn. */
1744 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1745 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1746 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1747 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1749 /* Now find out which pseudos are allocated to it, and update
1750 hard_reg_n_uses. */
1751 CLEAR_REG_SET (&pseudos_counted);
1753 EXECUTE_IF_SET_IN_REG_SET
1754 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1756 count_pseudo (i);
1758 EXECUTE_IF_SET_IN_REG_SET
1759 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1761 count_pseudo (i);
1763 CLEAR_REG_SET (&pseudos_counted);
1766 /* Vector of reload-numbers showing the order in which the reloads should
1767 be processed. */
1768 static short reload_order[MAX_RELOADS];
1770 /* This is used to keep track of the spill regs used in one insn. */
1771 static HARD_REG_SET used_spill_regs_local;
1773 /* We decided to spill hard register SPILLED, which has a size of
1774 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1775 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1776 update SPILL_COST/SPILL_ADD_COST. */
1778 static void
1779 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1781 int freq = REG_FREQ (reg);
1782 int r = reg_renumber[reg];
1783 int nregs;
1785 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1786 if (ira_conflicts_p && r < 0)
1787 return;
1789 gcc_assert (r >= 0);
1791 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1793 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1794 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1795 return;
1797 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1799 spill_add_cost[r] -= freq;
1800 while (nregs-- > 0)
1802 hard_regno_to_pseudo_regno[r + nregs] = -1;
1803 spill_cost[r + nregs] -= freq;
1807 /* Find reload register to use for reload number ORDER. */
1809 static int
1810 find_reg (struct insn_chain *chain, int order)
1812 int rnum = reload_order[order];
1813 struct reload *rl = rld + rnum;
1814 int best_cost = INT_MAX;
1815 int best_reg = -1;
1816 unsigned int i, j, n;
1817 int k;
1818 HARD_REG_SET not_usable;
1819 HARD_REG_SET used_by_other_reload;
1820 reg_set_iterator rsi;
1821 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1822 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1824 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1825 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1826 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1828 CLEAR_HARD_REG_SET (used_by_other_reload);
1829 for (k = 0; k < order; k++)
1831 int other = reload_order[k];
1833 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1834 for (j = 0; j < rld[other].nregs; j++)
1835 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1838 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1840 #ifdef REG_ALLOC_ORDER
1841 unsigned int regno = reg_alloc_order[i];
1842 #else
1843 unsigned int regno = i;
1844 #endif
1846 if (! TEST_HARD_REG_BIT (not_usable, regno)
1847 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1848 && targetm.hard_regno_mode_ok (regno, rl->mode))
1850 int this_cost = spill_cost[regno];
1851 int ok = 1;
1852 unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);
1854 for (j = 1; j < this_nregs; j++)
1856 this_cost += spill_add_cost[regno + j];
1857 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1858 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1859 ok = 0;
1861 if (! ok)
1862 continue;
1864 if (ira_conflicts_p)
1866 /* Ask IRA to find a better pseudo-register for
1867 spilling. */
1868 for (n = j = 0; j < this_nregs; j++)
1870 int r = hard_regno_to_pseudo_regno[regno + j];
1872 if (r < 0)
1873 continue;
1874 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1875 regno_pseudo_regs[n++] = r;
1877 regno_pseudo_regs[n++] = -1;
1878 if (best_reg < 0
1879 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1880 best_regno_pseudo_regs,
1881 rl->in, rl->out,
1882 chain->insn))
1884 best_reg = regno;
1885 for (j = 0;; j++)
1887 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1888 if (regno_pseudo_regs[j] < 0)
1889 break;
1892 continue;
1895 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1896 this_cost--;
1897 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1898 this_cost--;
1899 if (this_cost < best_cost
1900 /* Among registers with equal cost, prefer caller-saved ones, or
1901 use REG_ALLOC_ORDER if it is defined. */
1902 || (this_cost == best_cost
1903 #ifdef REG_ALLOC_ORDER
1904 && (inv_reg_alloc_order[regno]
1905 < inv_reg_alloc_order[best_reg])
1906 #else
1907 && call_used_regs[regno]
1908 && ! call_used_regs[best_reg]
1909 #endif
1912 best_reg = regno;
1913 best_cost = this_cost;
1917 if (best_reg == -1)
1918 return 0;
1920 if (dump_file)
1921 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1923 rl->nregs = hard_regno_nregs (best_reg, rl->mode);
1924 rl->regno = best_reg;
1926 EXECUTE_IF_SET_IN_REG_SET
1927 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1929 count_spilled_pseudo (best_reg, rl->nregs, j);
1932 EXECUTE_IF_SET_IN_REG_SET
1933 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1935 count_spilled_pseudo (best_reg, rl->nregs, j);
1938 for (i = 0; i < rl->nregs; i++)
1940 gcc_assert (spill_cost[best_reg + i] == 0);
1941 gcc_assert (spill_add_cost[best_reg + i] == 0);
1942 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1943 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1945 return 1;
1948 /* Find more reload regs to satisfy the remaining need of an insn, which
1949 is given by CHAIN.
1950 Do it by ascending class number, since otherwise a reg
1951 might be spilled for a big class and might fail to count
1952 for a smaller class even though it belongs to that class. */
1954 static void
1955 find_reload_regs (struct insn_chain *chain)
1957 int i;
1959 /* In order to be certain of getting the registers we need,
1960 we must sort the reloads into order of increasing register class.
1961 Then our grabbing of reload registers will parallel the process
1962 that provided the reload registers. */
1963 for (i = 0; i < chain->n_reloads; i++)
1965 /* Show whether this reload already has a hard reg. */
1966 if (chain->rld[i].reg_rtx)
1968 chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx);
1969 chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx);
1971 else
1972 chain->rld[i].regno = -1;
1973 reload_order[i] = i;
1976 n_reloads = chain->n_reloads;
1977 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1979 CLEAR_HARD_REG_SET (used_spill_regs_local);
1981 if (dump_file)
1982 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1984 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1986 /* Compute the order of preference for hard registers to spill. */
1988 order_regs_for_reload (chain);
1990 for (i = 0; i < n_reloads; i++)
1992 int r = reload_order[i];
1994 /* Ignore reloads that got marked inoperative. */
1995 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1996 && ! rld[r].optional
1997 && rld[r].regno == -1)
1998 if (! find_reg (chain, i))
2000 if (dump_file)
2001 fprintf (dump_file, "reload failure for reload %d\n", r);
2002 spill_failure (chain->insn, rld[r].rclass);
2003 failure = 1;
2004 return;
2008 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2009 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2011 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2014 static void
2015 select_reload_regs (void)
2017 struct insn_chain *chain;
2019 /* Try to satisfy the needs for each insn. */
2020 for (chain = insns_need_reload; chain != 0;
2021 chain = chain->next_need_reload)
2022 find_reload_regs (chain);
2025 /* Delete all insns that were inserted by emit_caller_save_insns during
2026 this iteration. */
2027 static void
2028 delete_caller_save_insns (void)
2030 struct insn_chain *c = reload_insn_chain;
2032 while (c != 0)
2034 while (c != 0 && c->is_caller_save_insn)
2036 struct insn_chain *next = c->next;
2037 rtx_insn *insn = c->insn;
2039 if (c == reload_insn_chain)
2040 reload_insn_chain = next;
2041 delete_insn (insn);
2043 if (next)
2044 next->prev = c->prev;
2045 if (c->prev)
2046 c->prev->next = next;
2047 c->next = unused_insn_chains;
2048 unused_insn_chains = c;
2049 c = next;
2051 if (c != 0)
2052 c = c->next;
2056 /* Handle the failure to find a register to spill.
2057 INSN should be one of the insns which needed this particular spill reg. */
2059 static void
2060 spill_failure (rtx_insn *insn, enum reg_class rclass)
2062 if (asm_noperands (PATTERN (insn)) >= 0)
2063 error_for_asm (insn, "can%'t find a register in class %qs while "
2064 "reloading %<asm%>",
2065 reg_class_names[rclass]);
2066 else
2068 error ("unable to find a register to spill in class %qs",
2069 reg_class_names[rclass]);
2071 if (dump_file)
2073 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2074 debug_reload_to_stream (dump_file);
2076 fatal_insn ("this is the insn:", insn);
2080 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2081 data that is dead in INSN. */
2083 static void
2084 delete_dead_insn (rtx_insn *insn)
2086 rtx_insn *prev = prev_active_insn (insn);
2087 rtx prev_dest;
2089 /* If the previous insn sets a register that dies in our insn make
2090 a note that we want to run DCE immediately after reload.
2092 We used to delete the previous insn & recurse, but that's wrong for
2093 block local equivalences. Instead of trying to figure out the exact
2094 circumstances where we can delete the potentially dead insns, just
2095 let DCE do the job. */
2096 if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2097 && GET_CODE (PATTERN (prev)) == SET
2098 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2099 && reg_mentioned_p (prev_dest, PATTERN (insn))
2100 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2101 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2102 need_dce = 1;
2104 SET_INSN_DELETED (insn);
2107 /* Modify the home of pseudo-reg I.
2108 The new home is present in reg_renumber[I].
2110 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2111 or it may be -1, meaning there is none or it is not relevant.
2112 This is used so that all pseudos spilled from a given hard reg
2113 can share one stack slot. */
2115 static void
2116 alter_reg (int i, int from_reg, bool dont_share_p)
2118 /* When outputting an inline function, this can happen
2119 for a reg that isn't actually used. */
2120 if (regno_reg_rtx[i] == 0)
2121 return;
2123 /* If the reg got changed to a MEM at rtl-generation time,
2124 ignore it. */
2125 if (!REG_P (regno_reg_rtx[i]))
2126 return;
2128 /* Modify the reg-rtx to contain the new hard reg
2129 number or else to contain its pseudo reg number. */
2130 SET_REGNO (regno_reg_rtx[i],
2131 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2133 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2134 allocate a stack slot for it. */
2136 if (reg_renumber[i] < 0
2137 && REG_N_REFS (i) > 0
2138 && reg_equiv_constant (i) == 0
2139 && (reg_equiv_invariant (i) == 0
2140 || reg_equiv_init (i) == 0)
2141 && reg_equiv_memory_loc (i) == 0)
2143 rtx x = NULL_RTX;
2144 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2145 unsigned HOST_WIDE_INT inherent_size = PSEUDO_REGNO_BYTES (i);
2146 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2147 machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
2148 unsigned HOST_WIDE_INT total_size = GET_MODE_SIZE (wider_mode);
2149 unsigned int min_align = GET_MODE_BITSIZE (reg_max_ref_mode[i]);
2150 poly_int64 adjust = 0;
2152 something_was_spilled = true;
2154 if (ira_conflicts_p)
2156 /* Mark the spill for IRA. */
2157 SET_REGNO_REG_SET (&spilled_pseudos, i);
2158 if (!dont_share_p)
2159 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2162 if (x)
2165 /* Each pseudo reg has an inherent size which comes from its own mode,
2166 and a total size which provides room for paradoxical subregs
2167 which refer to the pseudo reg in wider modes.
2169 We can use a slot already allocated if it provides both
2170 enough inherent space and enough total space.
2171 Otherwise, we allocate a new slot, making sure that it has no less
2172 inherent space, and no less total space, then the previous slot. */
2173 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2175 rtx stack_slot;
2177 /* No known place to spill from => no slot to reuse. */
2178 x = assign_stack_local (mode, total_size,
2179 min_align > inherent_align
2180 || total_size > inherent_size ? -1 : 0);
2182 stack_slot = x;
2184 /* Cancel the big-endian correction done in assign_stack_local.
2185 Get the address of the beginning of the slot. This is so we
2186 can do a big-endian correction unconditionally below. */
2187 if (BYTES_BIG_ENDIAN)
2189 adjust = inherent_size - total_size;
2190 if (maybe_ne (adjust, 0))
2192 unsigned int total_bits = total_size * BITS_PER_UNIT;
2193 machine_mode mem_mode
2194 = int_mode_for_size (total_bits, 1).else_blk ();
2195 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2199 if (! dont_share_p && ira_conflicts_p)
2200 /* Inform IRA about allocation a new stack slot. */
2201 ira_mark_new_stack_slot (stack_slot, i, total_size);
2204 /* Reuse a stack slot if possible. */
2205 else if (spill_stack_slot[from_reg] != 0
2206 && spill_stack_slot_width[from_reg] >= total_size
2207 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2208 >= inherent_size)
2209 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2210 x = spill_stack_slot[from_reg];
2212 /* Allocate a bigger slot. */
2213 else
2215 /* Compute maximum size needed, both for inherent size
2216 and for total size. */
2217 rtx stack_slot;
2219 if (spill_stack_slot[from_reg])
2221 if (partial_subreg_p (mode,
2222 GET_MODE (spill_stack_slot[from_reg])))
2223 mode = GET_MODE (spill_stack_slot[from_reg]);
2224 if (spill_stack_slot_width[from_reg] > total_size)
2225 total_size = spill_stack_slot_width[from_reg];
2226 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2227 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2230 /* Make a slot with that size. */
2231 x = assign_stack_local (mode, total_size,
2232 min_align > inherent_align
2233 || total_size > inherent_size ? -1 : 0);
2234 stack_slot = x;
2236 /* Cancel the big-endian correction done in assign_stack_local.
2237 Get the address of the beginning of the slot. This is so we
2238 can do a big-endian correction unconditionally below. */
2239 if (BYTES_BIG_ENDIAN)
2241 adjust = GET_MODE_SIZE (mode) - total_size;
2242 if (maybe_ne (adjust, 0))
2244 unsigned int total_bits = total_size * BITS_PER_UNIT;
2245 machine_mode mem_mode
2246 = int_mode_for_size (total_bits, 1).else_blk ();
2247 stack_slot = adjust_address_nv (x, mem_mode, adjust);
2251 spill_stack_slot[from_reg] = stack_slot;
2252 spill_stack_slot_width[from_reg] = total_size;
2255 /* On a big endian machine, the "address" of the slot
2256 is the address of the low part that fits its inherent mode. */
2257 adjust += subreg_size_lowpart_offset (inherent_size, total_size);
2259 /* If we have any adjustment to make, or if the stack slot is the
2260 wrong mode, make a new stack slot. */
2261 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2263 /* Set all of the memory attributes as appropriate for a spill. */
2264 set_mem_attrs_for_spill (x);
2266 /* Save the stack slot for later. */
2267 reg_equiv_memory_loc (i) = x;
2271 /* Mark the slots in regs_ever_live for the hard regs used by
2272 pseudo-reg number REGNO, accessed in MODE. */
2274 static void
2275 mark_home_live_1 (int regno, machine_mode mode)
2277 int i, lim;
2279 i = reg_renumber[regno];
2280 if (i < 0)
2281 return;
2282 lim = end_hard_regno (mode, i);
2283 while (i < lim)
2284 df_set_regs_ever_live (i++, true);
2287 /* Mark the slots in regs_ever_live for the hard regs
2288 used by pseudo-reg number REGNO. */
2290 void
2291 mark_home_live (int regno)
2293 if (reg_renumber[regno] >= 0)
2294 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2297 /* This function handles the tracking of elimination offsets around branches.
2299 X is a piece of RTL being scanned.
2301 INSN is the insn that it came from, if any.
2303 INITIAL_P is nonzero if we are to set the offset to be the initial
2304 offset and zero if we are setting the offset of the label to be the
2305 current offset. */
2307 static void
2308 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2310 enum rtx_code code = GET_CODE (x);
2311 rtx tem;
2312 unsigned int i;
2313 struct elim_table *p;
2315 switch (code)
2317 case LABEL_REF:
2318 if (LABEL_REF_NONLOCAL_P (x))
2319 return;
2321 x = label_ref_label (x);
2323 /* fall through */
2325 case CODE_LABEL:
2326 /* If we know nothing about this label, set the desired offsets. Note
2327 that this sets the offset at a label to be the offset before a label
2328 if we don't know anything about the label. This is not correct for
2329 the label after a BARRIER, but is the best guess we can make. If
2330 we guessed wrong, we will suppress an elimination that might have
2331 been possible had we been able to guess correctly. */
2333 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2335 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2336 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2337 = (initial_p ? reg_eliminate[i].initial_offset
2338 : reg_eliminate[i].offset);
2339 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2342 /* Otherwise, if this is the definition of a label and it is
2343 preceded by a BARRIER, set our offsets to the known offset of
2344 that label. */
2346 else if (x == insn
2347 && (tem = prev_nonnote_insn (insn)) != 0
2348 && BARRIER_P (tem))
2349 set_offsets_for_label (insn);
2350 else
2351 /* If neither of the above cases is true, compare each offset
2352 with those previously recorded and suppress any eliminations
2353 where the offsets disagree. */
2355 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2356 if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i],
2357 (initial_p ? reg_eliminate[i].initial_offset
2358 : reg_eliminate[i].offset)))
2359 reg_eliminate[i].can_eliminate = 0;
2361 return;
2363 case JUMP_TABLE_DATA:
2364 set_label_offsets (PATTERN (insn), insn, initial_p);
2365 return;
2367 case JUMP_INSN:
2368 set_label_offsets (PATTERN (insn), insn, initial_p);
2370 /* fall through */
2372 case INSN:
2373 case CALL_INSN:
2374 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2375 to indirectly and hence must have all eliminations at their
2376 initial offsets. */
2377 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2378 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2379 set_label_offsets (XEXP (tem, 0), insn, 1);
2380 return;
2382 case PARALLEL:
2383 case ADDR_VEC:
2384 case ADDR_DIFF_VEC:
2385 /* Each of the labels in the parallel or address vector must be
2386 at their initial offsets. We want the first field for PARALLEL
2387 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2389 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2390 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2391 insn, initial_p);
2392 return;
2394 case SET:
2395 /* We only care about setting PC. If the source is not RETURN,
2396 IF_THEN_ELSE, or a label, disable any eliminations not at
2397 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2398 isn't one of those possibilities. For branches to a label,
2399 call ourselves recursively.
2401 Note that this can disable elimination unnecessarily when we have
2402 a non-local goto since it will look like a non-constant jump to
2403 someplace in the current function. This isn't a significant
2404 problem since such jumps will normally be when all elimination
2405 pairs are back to their initial offsets. */
2407 if (SET_DEST (x) != pc_rtx)
2408 return;
2410 switch (GET_CODE (SET_SRC (x)))
2412 case PC:
2413 case RETURN:
2414 return;
2416 case LABEL_REF:
2417 set_label_offsets (SET_SRC (x), insn, initial_p);
2418 return;
2420 case IF_THEN_ELSE:
2421 tem = XEXP (SET_SRC (x), 1);
2422 if (GET_CODE (tem) == LABEL_REF)
2423 set_label_offsets (label_ref_label (tem), insn, initial_p);
2424 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2425 break;
2427 tem = XEXP (SET_SRC (x), 2);
2428 if (GET_CODE (tem) == LABEL_REF)
2429 set_label_offsets (label_ref_label (tem), insn, initial_p);
2430 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2431 break;
2432 return;
2434 default:
2435 break;
2438 /* If we reach here, all eliminations must be at their initial
2439 offset because we are doing a jump to a variable address. */
2440 for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2441 if (maybe_ne (p->offset, p->initial_offset))
2442 p->can_eliminate = 0;
2443 break;
2445 default:
2446 break;
2450 /* This function examines every reg that occurs in X and adjusts the
2451 costs for its elimination which are gathered by IRA. INSN is the
2452 insn in which X occurs. We do not recurse into MEM expressions. */
2454 static void
2455 note_reg_elim_costly (const_rtx x, rtx insn)
2457 subrtx_iterator::array_type array;
2458 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2460 const_rtx x = *iter;
2461 if (MEM_P (x))
2462 iter.skip_subrtxes ();
2463 else if (REG_P (x)
2464 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2465 && reg_equiv_init (REGNO (x))
2466 && reg_equiv_invariant (REGNO (x)))
2468 rtx t = reg_equiv_invariant (REGNO (x));
2469 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2470 int cost = set_src_cost (new_rtx, Pmode,
2471 optimize_bb_for_speed_p (elim_bb));
2472 int freq = REG_FREQ_FROM_BB (elim_bb);
2474 if (cost != 0)
2475 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2480 /* Scan X and replace any eliminable registers (such as fp) with a
2481 replacement (such as sp), plus an offset.
2483 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2484 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2485 MEM, we are allowed to replace a sum of a register and the constant zero
2486 with the register, which we cannot do outside a MEM. In addition, we need
2487 to record the fact that a register is referenced outside a MEM.
2489 If INSN is an insn, it is the insn containing X. If we replace a REG
2490 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2491 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2492 the REG is being modified.
2494 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2495 That's used when we eliminate in expressions stored in notes.
2496 This means, do not set ref_outside_mem even if the reference
2497 is outside of MEMs.
2499 If FOR_COSTS is true, we are being called before reload in order to
2500 estimate the costs of keeping registers with an equivalence unallocated.
2502 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2503 replacements done assuming all offsets are at their initial values. If
2504 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2505 encounter, return the actual location so that find_reloads will do
2506 the proper thing. */
2508 static rtx
2509 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2510 bool may_use_invariant, bool for_costs)
2512 enum rtx_code code = GET_CODE (x);
2513 struct elim_table *ep;
2514 int regno;
2515 rtx new_rtx;
2516 int i, j;
2517 const char *fmt;
2518 int copied = 0;
2520 if (! current_function_decl)
2521 return x;
2523 switch (code)
2525 CASE_CONST_ANY:
2526 case CONST:
2527 case SYMBOL_REF:
2528 case CODE_LABEL:
2529 case PC:
2530 case CC0:
2531 case ASM_INPUT:
2532 case ADDR_VEC:
2533 case ADDR_DIFF_VEC:
2534 case RETURN:
2535 return x;
2537 case REG:
2538 regno = REGNO (x);
2540 /* First handle the case where we encounter a bare register that
2541 is eliminable. Replace it with a PLUS. */
2542 if (regno < FIRST_PSEUDO_REGISTER)
2544 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2545 ep++)
2546 if (ep->from_rtx == x && ep->can_eliminate)
2547 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2550 else if (reg_renumber && reg_renumber[regno] < 0
2551 && reg_equivs
2552 && reg_equiv_invariant (regno))
2554 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2555 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2556 mem_mode, insn, true, for_costs);
2557 /* There exists at least one use of REGNO that cannot be
2558 eliminated. Prevent the defining insn from being deleted. */
2559 reg_equiv_init (regno) = NULL;
2560 if (!for_costs)
2561 alter_reg (regno, -1, true);
2563 return x;
2565 /* You might think handling MINUS in a manner similar to PLUS is a
2566 good idea. It is not. It has been tried multiple times and every
2567 time the change has had to have been reverted.
2569 Other parts of reload know a PLUS is special (gen_reload for example)
2570 and require special code to handle code a reloaded PLUS operand.
2572 Also consider backends where the flags register is clobbered by a
2573 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2574 lea instruction comes to mind). If we try to reload a MINUS, we
2575 may kill the flags register that was holding a useful value.
2577 So, please before trying to handle MINUS, consider reload as a
2578 whole instead of this little section as well as the backend issues. */
2579 case PLUS:
2580 /* If this is the sum of an eliminable register and a constant, rework
2581 the sum. */
2582 if (REG_P (XEXP (x, 0))
2583 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2584 && CONSTANT_P (XEXP (x, 1)))
2586 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2587 ep++)
2588 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2590 /* The only time we want to replace a PLUS with a REG (this
2591 occurs when the constant operand of the PLUS is the negative
2592 of the offset) is when we are inside a MEM. We won't want
2593 to do so at other times because that would change the
2594 structure of the insn in a way that reload can't handle.
2595 We special-case the commonest situation in
2596 eliminate_regs_in_insn, so just replace a PLUS with a
2597 PLUS here, unless inside a MEM. */
2598 if (mem_mode != 0
2599 && CONST_INT_P (XEXP (x, 1))
2600 && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset))
2601 return ep->to_rtx;
2602 else
2603 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2604 plus_constant (Pmode, XEXP (x, 1),
2605 ep->previous_offset));
2608 /* If the register is not eliminable, we are done since the other
2609 operand is a constant. */
2610 return x;
2613 /* If this is part of an address, we want to bring any constant to the
2614 outermost PLUS. We will do this by doing register replacement in
2615 our operands and seeing if a constant shows up in one of them.
2617 Note that there is no risk of modifying the structure of the insn,
2618 since we only get called for its operands, thus we are either
2619 modifying the address inside a MEM, or something like an address
2620 operand of a load-address insn. */
2623 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2624 for_costs);
2625 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2626 for_costs);
2628 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2630 /* If one side is a PLUS and the other side is a pseudo that
2631 didn't get a hard register but has a reg_equiv_constant,
2632 we must replace the constant here since it may no longer
2633 be in the position of any operand. */
2634 if (GET_CODE (new0) == PLUS && REG_P (new1)
2635 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2636 && reg_renumber[REGNO (new1)] < 0
2637 && reg_equivs
2638 && reg_equiv_constant (REGNO (new1)) != 0)
2639 new1 = reg_equiv_constant (REGNO (new1));
2640 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2641 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2642 && reg_renumber[REGNO (new0)] < 0
2643 && reg_equiv_constant (REGNO (new0)) != 0)
2644 new0 = reg_equiv_constant (REGNO (new0));
2646 new_rtx = form_sum (GET_MODE (x), new0, new1);
2648 /* As above, if we are not inside a MEM we do not want to
2649 turn a PLUS into something else. We might try to do so here
2650 for an addition of 0 if we aren't optimizing. */
2651 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2652 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2653 else
2654 return new_rtx;
2657 return x;
2659 case MULT:
2660 /* If this is the product of an eliminable register and a
2661 constant, apply the distribute law and move the constant out
2662 so that we have (plus (mult ..) ..). This is needed in order
2663 to keep load-address insns valid. This case is pathological.
2664 We ignore the possibility of overflow here. */
2665 if (REG_P (XEXP (x, 0))
2666 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2667 && CONST_INT_P (XEXP (x, 1)))
2668 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2669 ep++)
2670 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2672 if (! mem_mode
2673 /* Refs inside notes or in DEBUG_INSNs don't count for
2674 this purpose. */
2675 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2676 || GET_CODE (insn) == INSN_LIST
2677 || DEBUG_INSN_P (insn))))
2678 ep->ref_outside_mem = 1;
2680 return
2681 plus_constant (Pmode,
2682 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2683 ep->previous_offset * INTVAL (XEXP (x, 1)));
2686 /* fall through */
2688 case CALL:
2689 case COMPARE:
2690 /* See comments before PLUS about handling MINUS. */
2691 case MINUS:
2692 case DIV: case UDIV:
2693 case MOD: case UMOD:
2694 case AND: case IOR: case XOR:
2695 case ROTATERT: case ROTATE:
2696 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2697 case NE: case EQ:
2698 case GE: case GT: case GEU: case GTU:
2699 case LE: case LT: case LEU: case LTU:
2701 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2702 for_costs);
2703 rtx new1 = XEXP (x, 1)
2704 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2705 for_costs) : 0;
2707 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2708 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2710 return x;
2712 case EXPR_LIST:
2713 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2714 if (XEXP (x, 0))
2716 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2717 for_costs);
2718 if (new_rtx != XEXP (x, 0))
2720 /* If this is a REG_DEAD note, it is not valid anymore.
2721 Using the eliminated version could result in creating a
2722 REG_DEAD note for the stack or frame pointer. */
2723 if (REG_NOTE_KIND (x) == REG_DEAD)
2724 return (XEXP (x, 1)
2725 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2726 for_costs)
2727 : NULL_RTX);
2729 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2733 /* fall through */
2735 case INSN_LIST:
2736 case INT_LIST:
2737 /* Now do eliminations in the rest of the chain. If this was
2738 an EXPR_LIST, this might result in allocating more memory than is
2739 strictly needed, but it simplifies the code. */
2740 if (XEXP (x, 1))
2742 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2743 for_costs);
2744 if (new_rtx != XEXP (x, 1))
2745 return
2746 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2748 return x;
2750 case PRE_INC:
2751 case POST_INC:
2752 case PRE_DEC:
2753 case POST_DEC:
2754 /* We do not support elimination of a register that is modified.
2755 elimination_effects has already make sure that this does not
2756 happen. */
2757 return x;
2759 case PRE_MODIFY:
2760 case POST_MODIFY:
2761 /* We do not support elimination of a register that is modified.
2762 elimination_effects has already make sure that this does not
2763 happen. The only remaining case we need to consider here is
2764 that the increment value may be an eliminable register. */
2765 if (GET_CODE (XEXP (x, 1)) == PLUS
2766 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2768 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2769 insn, true, for_costs);
2771 if (new_rtx != XEXP (XEXP (x, 1), 1))
2772 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2773 gen_rtx_PLUS (GET_MODE (x),
2774 XEXP (x, 0), new_rtx));
2776 return x;
2778 case STRICT_LOW_PART:
2779 case NEG: case NOT:
2780 case SIGN_EXTEND: case ZERO_EXTEND:
2781 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2782 case FLOAT: case FIX:
2783 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2784 case ABS:
2785 case SQRT:
2786 case FFS:
2787 case CLZ:
2788 case CTZ:
2789 case POPCOUNT:
2790 case PARITY:
2791 case BSWAP:
2792 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2793 for_costs);
2794 if (new_rtx != XEXP (x, 0))
2795 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2796 return x;
2798 case SUBREG:
2799 /* Similar to above processing, but preserve SUBREG_BYTE.
2800 Convert (subreg (mem)) to (mem) if not paradoxical.
2801 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2802 pseudo didn't get a hard reg, we must replace this with the
2803 eliminated version of the memory location because push_reload
2804 may do the replacement in certain circumstances. */
2805 if (REG_P (SUBREG_REG (x))
2806 && !paradoxical_subreg_p (x)
2807 && reg_equivs
2808 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2810 new_rtx = SUBREG_REG (x);
2812 else
2813 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2815 if (new_rtx != SUBREG_REG (x))
2817 int x_size = GET_MODE_SIZE (GET_MODE (x));
2818 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2820 if (MEM_P (new_rtx)
2821 && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
2822 /* On RISC machines, combine can create rtl of the form
2823 (set (subreg:m1 (reg:m2 R) 0) ...)
2824 where m1 < m2, and expects something interesting to
2825 happen to the entire word. Moreover, it will use the
2826 (reg:m2 R) later, expecting all bits to be preserved.
2827 So if the number of words is the same, preserve the
2828 subreg so that push_reload can see it. */
2829 && !(WORD_REGISTER_OPERATIONS
2830 && (x_size - 1) / UNITS_PER_WORD
2831 == (new_size -1 ) / UNITS_PER_WORD))
2832 || x_size == new_size)
2834 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2835 else if (insn && GET_CODE (insn) == DEBUG_INSN)
2836 return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2837 else
2838 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2841 return x;
2843 case MEM:
2844 /* Our only special processing is to pass the mode of the MEM to our
2845 recursive call and copy the flags. While we are here, handle this
2846 case more efficiently. */
2848 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2849 for_costs);
2850 if (for_costs
2851 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2852 && !memory_address_p (GET_MODE (x), new_rtx))
2853 note_reg_elim_costly (XEXP (x, 0), insn);
2855 return replace_equiv_address_nv (x, new_rtx);
2857 case USE:
2858 /* Handle insn_list USE that a call to a pure function may generate. */
2859 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2860 for_costs);
2861 if (new_rtx != XEXP (x, 0))
2862 return gen_rtx_USE (GET_MODE (x), new_rtx);
2863 return x;
2865 case CLOBBER:
2866 case ASM_OPERANDS:
2867 gcc_assert (insn && DEBUG_INSN_P (insn));
2868 break;
2870 case SET:
2871 gcc_unreachable ();
2873 default:
2874 break;
2877 /* Process each of our operands recursively. If any have changed, make a
2878 copy of the rtx. */
2879 fmt = GET_RTX_FORMAT (code);
2880 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2882 if (*fmt == 'e')
2884 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2885 for_costs);
2886 if (new_rtx != XEXP (x, i) && ! copied)
2888 x = shallow_copy_rtx (x);
2889 copied = 1;
2891 XEXP (x, i) = new_rtx;
2893 else if (*fmt == 'E')
2895 int copied_vec = 0;
2896 for (j = 0; j < XVECLEN (x, i); j++)
2898 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2899 for_costs);
2900 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2902 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2903 XVEC (x, i)->elem);
2904 if (! copied)
2906 x = shallow_copy_rtx (x);
2907 copied = 1;
2909 XVEC (x, i) = new_v;
2910 copied_vec = 1;
2912 XVECEXP (x, i, j) = new_rtx;
2917 return x;
2921 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2923 if (reg_eliminate == NULL)
2925 gcc_assert (targetm.no_register_allocation);
2926 return x;
2928 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2931 /* Scan rtx X for modifications of elimination target registers. Update
2932 the table of eliminables to reflect the changed state. MEM_MODE is
2933 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2935 static void
2936 elimination_effects (rtx x, machine_mode mem_mode)
2938 enum rtx_code code = GET_CODE (x);
2939 struct elim_table *ep;
2940 int regno;
2941 int i, j;
2942 const char *fmt;
2944 switch (code)
2946 CASE_CONST_ANY:
2947 case CONST:
2948 case SYMBOL_REF:
2949 case CODE_LABEL:
2950 case PC:
2951 case CC0:
2952 case ASM_INPUT:
2953 case ADDR_VEC:
2954 case ADDR_DIFF_VEC:
2955 case RETURN:
2956 return;
2958 case REG:
2959 regno = REGNO (x);
2961 /* First handle the case where we encounter a bare register that
2962 is eliminable. Replace it with a PLUS. */
2963 if (regno < FIRST_PSEUDO_REGISTER)
2965 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2966 ep++)
2967 if (ep->from_rtx == x && ep->can_eliminate)
2969 if (! mem_mode)
2970 ep->ref_outside_mem = 1;
2971 return;
2975 else if (reg_renumber[regno] < 0
2976 && reg_equivs
2977 && reg_equiv_constant (regno)
2978 && ! function_invariant_p (reg_equiv_constant (regno)))
2979 elimination_effects (reg_equiv_constant (regno), mem_mode);
2980 return;
2982 case PRE_INC:
2983 case POST_INC:
2984 case PRE_DEC:
2985 case POST_DEC:
2986 case POST_MODIFY:
2987 case PRE_MODIFY:
2988 /* If we modify the source of an elimination rule, disable it. */
2989 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2990 if (ep->from_rtx == XEXP (x, 0))
2991 ep->can_eliminate = 0;
2993 /* If we modify the target of an elimination rule by adding a constant,
2994 update its offset. If we modify the target in any other way, we'll
2995 have to disable the rule as well. */
2996 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2997 if (ep->to_rtx == XEXP (x, 0))
2999 poly_int64 size = GET_MODE_SIZE (mem_mode);
3001 /* If more bytes than MEM_MODE are pushed, account for them. */
3002 #ifdef PUSH_ROUNDING
3003 if (ep->to_rtx == stack_pointer_rtx)
3004 size = PUSH_ROUNDING (size);
3005 #endif
3006 if (code == PRE_DEC || code == POST_DEC)
3007 ep->offset += size;
3008 else if (code == PRE_INC || code == POST_INC)
3009 ep->offset -= size;
3010 else if (code == PRE_MODIFY || code == POST_MODIFY)
3012 if (GET_CODE (XEXP (x, 1)) == PLUS
3013 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3014 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3015 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3016 else
3017 ep->can_eliminate = 0;
3021 /* These two aren't unary operators. */
3022 if (code == POST_MODIFY || code == PRE_MODIFY)
3023 break;
3025 /* Fall through to generic unary operation case. */
3026 gcc_fallthrough ();
3027 case STRICT_LOW_PART:
3028 case NEG: case NOT:
3029 case SIGN_EXTEND: case ZERO_EXTEND:
3030 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3031 case FLOAT: case FIX:
3032 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3033 case ABS:
3034 case SQRT:
3035 case FFS:
3036 case CLZ:
3037 case CTZ:
3038 case POPCOUNT:
3039 case PARITY:
3040 case BSWAP:
3041 elimination_effects (XEXP (x, 0), mem_mode);
3042 return;
3044 case SUBREG:
3045 if (REG_P (SUBREG_REG (x))
3046 && !paradoxical_subreg_p (x)
3047 && reg_equivs
3048 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3049 return;
3051 elimination_effects (SUBREG_REG (x), mem_mode);
3052 return;
3054 case USE:
3055 /* If using a register that is the source of an eliminate we still
3056 think can be performed, note it cannot be performed since we don't
3057 know how this register is used. */
3058 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3059 if (ep->from_rtx == XEXP (x, 0))
3060 ep->can_eliminate = 0;
3062 elimination_effects (XEXP (x, 0), mem_mode);
3063 return;
3065 case CLOBBER:
3066 /* If clobbering a register that is the replacement register for an
3067 elimination we still think can be performed, note that it cannot
3068 be performed. Otherwise, we need not be concerned about it. */
3069 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3070 if (ep->to_rtx == XEXP (x, 0))
3071 ep->can_eliminate = 0;
3073 elimination_effects (XEXP (x, 0), mem_mode);
3074 return;
3076 case SET:
3077 /* Check for setting a register that we know about. */
3078 if (REG_P (SET_DEST (x)))
3080 /* See if this is setting the replacement register for an
3081 elimination.
3083 If DEST is the hard frame pointer, we do nothing because we
3084 assume that all assignments to the frame pointer are for
3085 non-local gotos and are being done at a time when they are valid
3086 and do not disturb anything else. Some machines want to
3087 eliminate a fake argument pointer (or even a fake frame pointer)
3088 with either the real frame or the stack pointer. Assignments to
3089 the hard frame pointer must not prevent this elimination. */
3091 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3092 ep++)
3093 if (ep->to_rtx == SET_DEST (x)
3094 && SET_DEST (x) != hard_frame_pointer_rtx)
3096 /* If it is being incremented, adjust the offset. Otherwise,
3097 this elimination can't be done. */
3098 rtx src = SET_SRC (x);
3100 if (GET_CODE (src) == PLUS
3101 && XEXP (src, 0) == SET_DEST (x)
3102 && CONST_INT_P (XEXP (src, 1)))
3103 ep->offset -= INTVAL (XEXP (src, 1));
3104 else
3105 ep->can_eliminate = 0;
3109 elimination_effects (SET_DEST (x), VOIDmode);
3110 elimination_effects (SET_SRC (x), VOIDmode);
3111 return;
3113 case MEM:
3114 /* Our only special processing is to pass the mode of the MEM to our
3115 recursive call. */
3116 elimination_effects (XEXP (x, 0), GET_MODE (x));
3117 return;
3119 default:
3120 break;
3123 fmt = GET_RTX_FORMAT (code);
3124 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3126 if (*fmt == 'e')
3127 elimination_effects (XEXP (x, i), mem_mode);
3128 else if (*fmt == 'E')
3129 for (j = 0; j < XVECLEN (x, i); j++)
3130 elimination_effects (XVECEXP (x, i, j), mem_mode);
3134 /* Descend through rtx X and verify that no references to eliminable registers
3135 remain. If any do remain, mark the involved register as not
3136 eliminable. */
3138 static void
3139 check_eliminable_occurrences (rtx x)
3141 const char *fmt;
3142 int i;
3143 enum rtx_code code;
3145 if (x == 0)
3146 return;
3148 code = GET_CODE (x);
3150 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3152 struct elim_table *ep;
3154 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3155 if (ep->from_rtx == x)
3156 ep->can_eliminate = 0;
3157 return;
3160 fmt = GET_RTX_FORMAT (code);
3161 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3163 if (*fmt == 'e')
3164 check_eliminable_occurrences (XEXP (x, i));
3165 else if (*fmt == 'E')
3167 int j;
3168 for (j = 0; j < XVECLEN (x, i); j++)
3169 check_eliminable_occurrences (XVECEXP (x, i, j));
3174 /* Scan INSN and eliminate all eliminable registers in it.
3176 If REPLACE is nonzero, do the replacement destructively. Also
3177 delete the insn as dead it if it is setting an eliminable register.
3179 If REPLACE is zero, do all our allocations in reload_obstack.
3181 If no eliminations were done and this insn doesn't require any elimination
3182 processing (these are not identical conditions: it might be updating sp,
3183 but not referencing fp; this needs to be seen during reload_as_needed so
3184 that the offset between fp and sp can be taken into consideration), zero
3185 is returned. Otherwise, 1 is returned. */
3187 static int
3188 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3190 int icode = recog_memoized (insn);
3191 rtx old_body = PATTERN (insn);
3192 int insn_is_asm = asm_noperands (old_body) >= 0;
3193 rtx old_set = single_set (insn);
3194 rtx new_body;
3195 int val = 0;
3196 int i;
3197 rtx substed_operand[MAX_RECOG_OPERANDS];
3198 rtx orig_operand[MAX_RECOG_OPERANDS];
3199 struct elim_table *ep;
3200 rtx plus_src, plus_cst_src;
3202 if (! insn_is_asm && icode < 0)
3204 gcc_assert (DEBUG_INSN_P (insn)
3205 || GET_CODE (PATTERN (insn)) == USE
3206 || GET_CODE (PATTERN (insn)) == CLOBBER
3207 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3208 if (DEBUG_BIND_INSN_P (insn))
3209 INSN_VAR_LOCATION_LOC (insn)
3210 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3211 return 0;
3214 if (old_set != 0 && REG_P (SET_DEST (old_set))
3215 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3217 /* Check for setting an eliminable register. */
3218 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3221 /* If this is setting the frame pointer register to the
3222 hardware frame pointer register and this is an elimination
3223 that will be done (tested above), this insn is really
3224 adjusting the frame pointer downward to compensate for
3225 the adjustment done before a nonlocal goto. */
3226 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3227 && ep->from == FRAME_POINTER_REGNUM
3228 && ep->to == HARD_FRAME_POINTER_REGNUM)
3230 rtx base = SET_SRC (old_set);
3231 rtx_insn *base_insn = insn;
3232 HOST_WIDE_INT offset = 0;
3234 while (base != ep->to_rtx)
3236 rtx_insn *prev_insn;
3237 rtx prev_set;
3239 if (GET_CODE (base) == PLUS
3240 && CONST_INT_P (XEXP (base, 1)))
3242 offset += INTVAL (XEXP (base, 1));
3243 base = XEXP (base, 0);
3245 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3246 && (prev_set = single_set (prev_insn)) != 0
3247 && rtx_equal_p (SET_DEST (prev_set), base))
3249 base = SET_SRC (prev_set);
3250 base_insn = prev_insn;
3252 else
3253 break;
3256 if (base == ep->to_rtx)
3258 rtx src = plus_constant (Pmode, ep->to_rtx,
3259 offset - ep->offset);
3261 new_body = old_body;
3262 if (! replace)
3264 new_body = copy_insn (old_body);
3265 if (REG_NOTES (insn))
3266 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3268 PATTERN (insn) = new_body;
3269 old_set = single_set (insn);
3271 /* First see if this insn remains valid when we
3272 make the change. If not, keep the INSN_CODE
3273 the same and let reload fit it up. */
3274 validate_change (insn, &SET_SRC (old_set), src, 1);
3275 validate_change (insn, &SET_DEST (old_set),
3276 ep->to_rtx, 1);
3277 if (! apply_change_group ())
3279 SET_SRC (old_set) = src;
3280 SET_DEST (old_set) = ep->to_rtx;
3283 val = 1;
3284 goto done;
3288 /* In this case this insn isn't serving a useful purpose. We
3289 will delete it in reload_as_needed once we know that this
3290 elimination is, in fact, being done.
3292 If REPLACE isn't set, we can't delete this insn, but needn't
3293 process it since it won't be used unless something changes. */
3294 if (replace)
3296 delete_dead_insn (insn);
3297 return 1;
3299 val = 1;
3300 goto done;
3304 /* We allow one special case which happens to work on all machines we
3305 currently support: a single set with the source or a REG_EQUAL
3306 note being a PLUS of an eliminable register and a constant. */
3307 plus_src = plus_cst_src = 0;
3308 if (old_set && REG_P (SET_DEST (old_set)))
3310 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3311 plus_src = SET_SRC (old_set);
3312 /* First see if the source is of the form (plus (...) CST). */
3313 if (plus_src
3314 && CONST_INT_P (XEXP (plus_src, 1)))
3315 plus_cst_src = plus_src;
3316 else if (REG_P (SET_SRC (old_set))
3317 || plus_src)
3319 /* Otherwise, see if we have a REG_EQUAL note of the form
3320 (plus (...) CST). */
3321 rtx links;
3322 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3324 if ((REG_NOTE_KIND (links) == REG_EQUAL
3325 || REG_NOTE_KIND (links) == REG_EQUIV)
3326 && GET_CODE (XEXP (links, 0)) == PLUS
3327 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3329 plus_cst_src = XEXP (links, 0);
3330 break;
3335 /* Check that the first operand of the PLUS is a hard reg or
3336 the lowpart subreg of one. */
3337 if (plus_cst_src)
3339 rtx reg = XEXP (plus_cst_src, 0);
3340 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3341 reg = SUBREG_REG (reg);
3343 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3344 plus_cst_src = 0;
3347 if (plus_cst_src)
3349 rtx reg = XEXP (plus_cst_src, 0);
3350 poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
3352 if (GET_CODE (reg) == SUBREG)
3353 reg = SUBREG_REG (reg);
3355 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3356 if (ep->from_rtx == reg && ep->can_eliminate)
3358 rtx to_rtx = ep->to_rtx;
3359 offset += ep->offset;
3360 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3362 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3363 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3364 to_rtx);
3365 /* If we have a nonzero offset, and the source is already
3366 a simple REG, the following transformation would
3367 increase the cost of the insn by replacing a simple REG
3368 with (plus (reg sp) CST). So try only when we already
3369 had a PLUS before. */
3370 if (known_eq (offset, 0) || plus_src)
3372 rtx new_src = plus_constant (GET_MODE (to_rtx),
3373 to_rtx, offset);
3375 new_body = old_body;
3376 if (! replace)
3378 new_body = copy_insn (old_body);
3379 if (REG_NOTES (insn))
3380 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3382 PATTERN (insn) = new_body;
3383 old_set = single_set (insn);
3385 /* First see if this insn remains valid when we make the
3386 change. If not, try to replace the whole pattern with
3387 a simple set (this may help if the original insn was a
3388 PARALLEL that was only recognized as single_set due to
3389 REG_UNUSED notes). If this isn't valid either, keep
3390 the INSN_CODE the same and let reload fix it up. */
3391 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3393 rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3395 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3396 SET_SRC (old_set) = new_src;
3399 else
3400 break;
3402 val = 1;
3403 /* This can't have an effect on elimination offsets, so skip right
3404 to the end. */
3405 goto done;
3409 /* Determine the effects of this insn on elimination offsets. */
3410 elimination_effects (old_body, VOIDmode);
3412 /* Eliminate all eliminable registers occurring in operands that
3413 can be handled by reload. */
3414 extract_insn (insn);
3415 for (i = 0; i < recog_data.n_operands; i++)
3417 orig_operand[i] = recog_data.operand[i];
3418 substed_operand[i] = recog_data.operand[i];
3420 /* For an asm statement, every operand is eliminable. */
3421 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3423 bool is_set_src, in_plus;
3425 /* Check for setting a register that we know about. */
3426 if (recog_data.operand_type[i] != OP_IN
3427 && REG_P (orig_operand[i]))
3429 /* If we are assigning to a register that can be eliminated, it
3430 must be as part of a PARALLEL, since the code above handles
3431 single SETs. We must indicate that we can no longer
3432 eliminate this reg. */
3433 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3434 ep++)
3435 if (ep->from_rtx == orig_operand[i])
3436 ep->can_eliminate = 0;
3439 /* Companion to the above plus substitution, we can allow
3440 invariants as the source of a plain move. */
3441 is_set_src = false;
3442 if (old_set
3443 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3444 is_set_src = true;
3445 in_plus = false;
3446 if (plus_src
3447 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3448 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3449 in_plus = true;
3451 substed_operand[i]
3452 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3453 replace ? insn : NULL_RTX,
3454 is_set_src || in_plus, false);
3455 if (substed_operand[i] != orig_operand[i])
3456 val = 1;
3457 /* Terminate the search in check_eliminable_occurrences at
3458 this point. */
3459 *recog_data.operand_loc[i] = 0;
3461 /* If an output operand changed from a REG to a MEM and INSN is an
3462 insn, write a CLOBBER insn. */
3463 if (recog_data.operand_type[i] != OP_IN
3464 && REG_P (orig_operand[i])
3465 && MEM_P (substed_operand[i])
3466 && replace)
3467 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3471 for (i = 0; i < recog_data.n_dups; i++)
3472 *recog_data.dup_loc[i]
3473 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3475 /* If any eliminable remain, they aren't eliminable anymore. */
3476 check_eliminable_occurrences (old_body);
3478 /* Substitute the operands; the new values are in the substed_operand
3479 array. */
3480 for (i = 0; i < recog_data.n_operands; i++)
3481 *recog_data.operand_loc[i] = substed_operand[i];
3482 for (i = 0; i < recog_data.n_dups; i++)
3483 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3485 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3486 re-recognize the insn. We do this in case we had a simple addition
3487 but now can do this as a load-address. This saves an insn in this
3488 common case.
3489 If re-recognition fails, the old insn code number will still be used,
3490 and some register operands may have changed into PLUS expressions.
3491 These will be handled by find_reloads by loading them into a register
3492 again. */
3494 if (val)
3496 /* If we aren't replacing things permanently and we changed something,
3497 make another copy to ensure that all the RTL is new. Otherwise
3498 things can go wrong if find_reload swaps commutative operands
3499 and one is inside RTL that has been copied while the other is not. */
3500 new_body = old_body;
3501 if (! replace)
3503 new_body = copy_insn (old_body);
3504 if (REG_NOTES (insn))
3505 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3507 PATTERN (insn) = new_body;
3509 /* If we had a move insn but now we don't, rerecognize it. This will
3510 cause spurious re-recognition if the old move had a PARALLEL since
3511 the new one still will, but we can't call single_set without
3512 having put NEW_BODY into the insn and the re-recognition won't
3513 hurt in this rare case. */
3514 /* ??? Why this huge if statement - why don't we just rerecognize the
3515 thing always? */
3516 if (! insn_is_asm
3517 && old_set != 0
3518 && ((REG_P (SET_SRC (old_set))
3519 && (GET_CODE (new_body) != SET
3520 || !REG_P (SET_SRC (new_body))))
3521 /* If this was a load from or store to memory, compare
3522 the MEM in recog_data.operand to the one in the insn.
3523 If they are not equal, then rerecognize the insn. */
3524 || (old_set != 0
3525 && ((MEM_P (SET_SRC (old_set))
3526 && SET_SRC (old_set) != recog_data.operand[1])
3527 || (MEM_P (SET_DEST (old_set))
3528 && SET_DEST (old_set) != recog_data.operand[0])))
3529 /* If this was an add insn before, rerecognize. */
3530 || GET_CODE (SET_SRC (old_set)) == PLUS))
3532 int new_icode = recog (PATTERN (insn), insn, 0);
3533 if (new_icode >= 0)
3534 INSN_CODE (insn) = new_icode;
3538 /* Restore the old body. If there were any changes to it, we made a copy
3539 of it while the changes were still in place, so we'll correctly return
3540 a modified insn below. */
3541 if (! replace)
3543 /* Restore the old body. */
3544 for (i = 0; i < recog_data.n_operands; i++)
3545 /* Restoring a top-level match_parallel would clobber the new_body
3546 we installed in the insn. */
3547 if (recog_data.operand_loc[i] != &PATTERN (insn))
3548 *recog_data.operand_loc[i] = orig_operand[i];
3549 for (i = 0; i < recog_data.n_dups; i++)
3550 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3553 /* Update all elimination pairs to reflect the status after the current
3554 insn. The changes we make were determined by the earlier call to
3555 elimination_effects.
3557 We also detect cases where register elimination cannot be done,
3558 namely, if a register would be both changed and referenced outside a MEM
3559 in the resulting insn since such an insn is often undefined and, even if
3560 not, we cannot know what meaning will be given to it. Note that it is
3561 valid to have a register used in an address in an insn that changes it
3562 (presumably with a pre- or post-increment or decrement).
3564 If anything changes, return nonzero. */
3566 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3568 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3569 ep->can_eliminate = 0;
3571 ep->ref_outside_mem = 0;
3573 if (maybe_ne (ep->previous_offset, ep->offset))
3574 val = 1;
3577 done:
3578 /* If we changed something, perform elimination in REG_NOTES. This is
3579 needed even when REPLACE is zero because a REG_DEAD note might refer
3580 to a register that we eliminate and could cause a different number
3581 of spill registers to be needed in the final reload pass than in
3582 the pre-passes. */
3583 if (val && REG_NOTES (insn) != 0)
3584 REG_NOTES (insn)
3585 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3586 false);
3588 return val;
3591 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3592 register allocator. INSN is the instruction we need to examine, we perform
3593 eliminations in its operands and record cases where eliminating a reg with
3594 an invariant equivalence would add extra cost. */
3596 #pragma GCC diagnostic push
3597 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3598 static void
3599 elimination_costs_in_insn (rtx_insn *insn)
3601 int icode = recog_memoized (insn);
3602 rtx old_body = PATTERN (insn);
3603 int insn_is_asm = asm_noperands (old_body) >= 0;
3604 rtx old_set = single_set (insn);
3605 int i;
3606 rtx orig_operand[MAX_RECOG_OPERANDS];
3607 rtx orig_dup[MAX_RECOG_OPERANDS];
3608 struct elim_table *ep;
3609 rtx plus_src, plus_cst_src;
3610 bool sets_reg_p;
3612 if (! insn_is_asm && icode < 0)
3614 gcc_assert (DEBUG_INSN_P (insn)
3615 || GET_CODE (PATTERN (insn)) == USE
3616 || GET_CODE (PATTERN (insn)) == CLOBBER
3617 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3618 return;
3621 if (old_set != 0 && REG_P (SET_DEST (old_set))
3622 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3624 /* Check for setting an eliminable register. */
3625 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3626 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3627 return;
3630 /* We allow one special case which happens to work on all machines we
3631 currently support: a single set with the source or a REG_EQUAL
3632 note being a PLUS of an eliminable register and a constant. */
3633 plus_src = plus_cst_src = 0;
3634 sets_reg_p = false;
3635 if (old_set && REG_P (SET_DEST (old_set)))
3637 sets_reg_p = true;
3638 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3639 plus_src = SET_SRC (old_set);
3640 /* First see if the source is of the form (plus (...) CST). */
3641 if (plus_src
3642 && CONST_INT_P (XEXP (plus_src, 1)))
3643 plus_cst_src = plus_src;
3644 else if (REG_P (SET_SRC (old_set))
3645 || plus_src)
3647 /* Otherwise, see if we have a REG_EQUAL note of the form
3648 (plus (...) CST). */
3649 rtx links;
3650 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3652 if ((REG_NOTE_KIND (links) == REG_EQUAL
3653 || REG_NOTE_KIND (links) == REG_EQUIV)
3654 && GET_CODE (XEXP (links, 0)) == PLUS
3655 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3657 plus_cst_src = XEXP (links, 0);
3658 break;
3664 /* Determine the effects of this insn on elimination offsets. */
3665 elimination_effects (old_body, VOIDmode);
3667 /* Eliminate all eliminable registers occurring in operands that
3668 can be handled by reload. */
3669 extract_insn (insn);
3670 int n_dups = recog_data.n_dups;
3671 for (i = 0; i < n_dups; i++)
3672 orig_dup[i] = *recog_data.dup_loc[i];
3674 int n_operands = recog_data.n_operands;
3675 for (i = 0; i < n_operands; i++)
3677 orig_operand[i] = recog_data.operand[i];
3679 /* For an asm statement, every operand is eliminable. */
3680 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3682 bool is_set_src, in_plus;
3684 /* Check for setting a register that we know about. */
3685 if (recog_data.operand_type[i] != OP_IN
3686 && REG_P (orig_operand[i]))
3688 /* If we are assigning to a register that can be eliminated, it
3689 must be as part of a PARALLEL, since the code above handles
3690 single SETs. We must indicate that we can no longer
3691 eliminate this reg. */
3692 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3693 ep++)
3694 if (ep->from_rtx == orig_operand[i])
3695 ep->can_eliminate = 0;
3698 /* Companion to the above plus substitution, we can allow
3699 invariants as the source of a plain move. */
3700 is_set_src = false;
3701 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3702 is_set_src = true;
3703 if (is_set_src && !sets_reg_p)
3704 note_reg_elim_costly (SET_SRC (old_set), insn);
3705 in_plus = false;
3706 if (plus_src && sets_reg_p
3707 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3708 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3709 in_plus = true;
3711 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3712 NULL_RTX,
3713 is_set_src || in_plus, true);
3714 /* Terminate the search in check_eliminable_occurrences at
3715 this point. */
3716 *recog_data.operand_loc[i] = 0;
3720 for (i = 0; i < n_dups; i++)
3721 *recog_data.dup_loc[i]
3722 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3724 /* If any eliminable remain, they aren't eliminable anymore. */
3725 check_eliminable_occurrences (old_body);
3727 /* Restore the old body. */
3728 for (i = 0; i < n_operands; i++)
3729 *recog_data.operand_loc[i] = orig_operand[i];
3730 for (i = 0; i < n_dups; i++)
3731 *recog_data.dup_loc[i] = orig_dup[i];
3733 /* Update all elimination pairs to reflect the status after the current
3734 insn. The changes we make were determined by the earlier call to
3735 elimination_effects. */
3737 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3739 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3740 ep->can_eliminate = 0;
3742 ep->ref_outside_mem = 0;
3745 return;
3747 #pragma GCC diagnostic pop
3749 /* Loop through all elimination pairs.
3750 Recalculate the number not at initial offset.
3752 Compute the maximum offset (minimum offset if the stack does not
3753 grow downward) for each elimination pair. */
3755 static void
3756 update_eliminable_offsets (void)
3758 struct elim_table *ep;
3760 num_not_at_initial_offset = 0;
3761 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3763 ep->previous_offset = ep->offset;
3764 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3765 num_not_at_initial_offset++;
3769 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3770 replacement we currently believe is valid, mark it as not eliminable if X
3771 modifies DEST in any way other than by adding a constant integer to it.
3773 If DEST is the frame pointer, we do nothing because we assume that
3774 all assignments to the hard frame pointer are nonlocal gotos and are being
3775 done at a time when they are valid and do not disturb anything else.
3776 Some machines want to eliminate a fake argument pointer with either the
3777 frame or stack pointer. Assignments to the hard frame pointer must not
3778 prevent this elimination.
3780 Called via note_stores from reload before starting its passes to scan
3781 the insns of the function. */
3783 static void
3784 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3786 unsigned int i;
3788 /* A SUBREG of a hard register here is just changing its mode. We should
3789 not see a SUBREG of an eliminable hard register, but check just in
3790 case. */
3791 if (GET_CODE (dest) == SUBREG)
3792 dest = SUBREG_REG (dest);
3794 if (dest == hard_frame_pointer_rtx)
3795 return;
3797 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3798 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3799 && (GET_CODE (x) != SET
3800 || GET_CODE (SET_SRC (x)) != PLUS
3801 || XEXP (SET_SRC (x), 0) != dest
3802 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3804 reg_eliminate[i].can_eliminate_previous
3805 = reg_eliminate[i].can_eliminate = 0;
3806 num_eliminable--;
3810 /* Verify that the initial elimination offsets did not change since the
3811 last call to set_initial_elim_offsets. This is used to catch cases
3812 where something illegal happened during reload_as_needed that could
3813 cause incorrect code to be generated if we did not check for it. */
3815 static bool
3816 verify_initial_elim_offsets (void)
3818 poly_int64 t;
3819 struct elim_table *ep;
3821 if (!num_eliminable)
3822 return true;
3824 targetm.compute_frame_layout ();
3825 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3827 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3828 if (maybe_ne (t, ep->initial_offset))
3829 return false;
3832 return true;
3835 /* Reset all offsets on eliminable registers to their initial values. */
3837 static void
3838 set_initial_elim_offsets (void)
3840 struct elim_table *ep = reg_eliminate;
3842 targetm.compute_frame_layout ();
3843 for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3845 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3846 ep->previous_offset = ep->offset = ep->initial_offset;
3849 num_not_at_initial_offset = 0;
3852 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3854 static void
3855 set_initial_eh_label_offset (rtx label)
3857 set_label_offsets (label, NULL, 1);
3860 /* Initialize the known label offsets.
3861 Set a known offset for each forced label to be at the initial offset
3862 of each elimination. We do this because we assume that all
3863 computed jumps occur from a location where each elimination is
3864 at its initial offset.
3865 For all other labels, show that we don't know the offsets. */
3867 static void
3868 set_initial_label_offsets (void)
3870 memset (offsets_known_at, 0, num_labels);
3872 unsigned int i;
3873 rtx_insn *insn;
3874 FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)
3875 set_label_offsets (insn, NULL, 1);
3877 for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3878 if (x->insn ())
3879 set_label_offsets (x->insn (), NULL, 1);
3881 for_each_eh_label (set_initial_eh_label_offset);
3884 /* Set all elimination offsets to the known values for the code label given
3885 by INSN. */
3887 static void
3888 set_offsets_for_label (rtx_insn *insn)
3890 unsigned int i;
3891 int label_nr = CODE_LABEL_NUMBER (insn);
3892 struct elim_table *ep;
3894 num_not_at_initial_offset = 0;
3895 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3897 ep->offset = ep->previous_offset
3898 = offsets_at[label_nr - first_label_num][i];
3899 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3900 num_not_at_initial_offset++;
3904 /* See if anything that happened changes which eliminations are valid.
3905 For example, on the SPARC, whether or not the frame pointer can
3906 be eliminated can depend on what registers have been used. We need
3907 not check some conditions again (such as flag_omit_frame_pointer)
3908 since they can't have changed. */
3910 static void
3911 update_eliminables (HARD_REG_SET *pset)
3913 int previous_frame_pointer_needed = frame_pointer_needed;
3914 struct elim_table *ep;
3916 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3917 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3918 && targetm.frame_pointer_required ())
3919 || ! targetm.can_eliminate (ep->from, ep->to)
3921 ep->can_eliminate = 0;
3923 /* Look for the case where we have discovered that we can't replace
3924 register A with register B and that means that we will now be
3925 trying to replace register A with register C. This means we can
3926 no longer replace register C with register B and we need to disable
3927 such an elimination, if it exists. This occurs often with A == ap,
3928 B == sp, and C == fp. */
3930 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3932 struct elim_table *op;
3933 int new_to = -1;
3935 if (! ep->can_eliminate && ep->can_eliminate_previous)
3937 /* Find the current elimination for ep->from, if there is a
3938 new one. */
3939 for (op = reg_eliminate;
3940 op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3941 if (op->from == ep->from && op->can_eliminate)
3943 new_to = op->to;
3944 break;
3947 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3948 disable it. */
3949 for (op = reg_eliminate;
3950 op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3951 if (op->from == new_to && op->to == ep->to)
3952 op->can_eliminate = 0;
3956 /* See if any registers that we thought we could eliminate the previous
3957 time are no longer eliminable. If so, something has changed and we
3958 must spill the register. Also, recompute the number of eliminable
3959 registers and see if the frame pointer is needed; it is if there is
3960 no elimination of the frame pointer that we can perform. */
3962 frame_pointer_needed = 1;
3963 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3965 if (ep->can_eliminate
3966 && ep->from == FRAME_POINTER_REGNUM
3967 && ep->to != HARD_FRAME_POINTER_REGNUM
3968 && (! SUPPORTS_STACK_ALIGNMENT
3969 || ! crtl->stack_realign_needed))
3970 frame_pointer_needed = 0;
3972 if (! ep->can_eliminate && ep->can_eliminate_previous)
3974 ep->can_eliminate_previous = 0;
3975 SET_HARD_REG_BIT (*pset, ep->from);
3976 num_eliminable--;
3980 /* If we didn't need a frame pointer last time, but we do now, spill
3981 the hard frame pointer. */
3982 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3983 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3986 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3987 Return true iff a register was spilled. */
3989 static bool
3990 update_eliminables_and_spill (void)
3992 int i;
3993 bool did_spill = false;
3994 HARD_REG_SET to_spill;
3995 CLEAR_HARD_REG_SET (to_spill);
3996 update_eliminables (&to_spill);
3997 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
3999 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4000 if (TEST_HARD_REG_BIT (to_spill, i))
4002 spill_hard_reg (i, 1);
4003 did_spill = true;
4005 /* Regardless of the state of spills, if we previously had
4006 a register that we thought we could eliminate, but now can
4007 not eliminate, we must run another pass.
4009 Consider pseudos which have an entry in reg_equiv_* which
4010 reference an eliminable register. We must make another pass
4011 to update reg_equiv_* so that we do not substitute in the
4012 old value from when we thought the elimination could be
4013 performed. */
4015 return did_spill;
4018 /* Return true if X is used as the target register of an elimination. */
4020 bool
4021 elimination_target_reg_p (rtx x)
4023 struct elim_table *ep;
4025 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4026 if (ep->to_rtx == x && ep->can_eliminate)
4027 return true;
4029 return false;
4032 /* Initialize the table of registers to eliminate.
4033 Pre-condition: global flag frame_pointer_needed has been set before
4034 calling this function. */
4036 static void
4037 init_elim_table (void)
4039 struct elim_table *ep;
4040 const struct elim_table_1 *ep1;
4042 if (!reg_eliminate)
4043 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4045 num_eliminable = 0;
4047 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4048 ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4050 ep->from = ep1->from;
4051 ep->to = ep1->to;
4052 ep->can_eliminate = ep->can_eliminate_previous
4053 = (targetm.can_eliminate (ep->from, ep->to)
4054 && ! (ep->to == STACK_POINTER_REGNUM
4055 && frame_pointer_needed
4056 && (! SUPPORTS_STACK_ALIGNMENT
4057 || ! stack_realign_fp)));
4060 /* Count the number of eliminable registers and build the FROM and TO
4061 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4062 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4063 We depend on this. */
4064 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4066 num_eliminable += ep->can_eliminate;
4067 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4068 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4072 /* Find all the pseudo registers that didn't get hard regs
4073 but do have known equivalent constants or memory slots.
4074 These include parameters (known equivalent to parameter slots)
4075 and cse'd or loop-moved constant memory addresses.
4077 Record constant equivalents in reg_equiv_constant
4078 so they will be substituted by find_reloads.
4079 Record memory equivalents in reg_mem_equiv so they can
4080 be substituted eventually by altering the REG-rtx's. */
4082 static void
4083 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4085 int i;
4086 rtx_insn *insn;
4088 grow_reg_equivs ();
4089 if (do_subregs)
4090 reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);
4091 else
4092 reg_max_ref_mode = NULL;
4094 num_eliminable_invariants = 0;
4096 first_label_num = get_first_label_num ();
4097 num_labels = max_label_num () - first_label_num;
4099 /* Allocate the tables used to store offset information at labels. */
4100 offsets_known_at = XNEWVEC (char, num_labels);
4101 offsets_at = (poly_int64_pod (*)[NUM_ELIMINABLE_REGS])
4102 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64));
4104 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4105 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4106 find largest such for each pseudo. FIRST is the head of the insn
4107 list. */
4109 for (insn = first; insn; insn = NEXT_INSN (insn))
4111 rtx set = single_set (insn);
4113 /* We may introduce USEs that we want to remove at the end, so
4114 we'll mark them with QImode. Make sure there are no
4115 previously-marked insns left by say regmove. */
4116 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4117 && GET_MODE (insn) != VOIDmode)
4118 PUT_MODE (insn, VOIDmode);
4120 if (do_subregs && NONDEBUG_INSN_P (insn))
4121 scan_paradoxical_subregs (PATTERN (insn));
4123 if (set != 0 && REG_P (SET_DEST (set)))
4125 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4126 rtx x;
4128 if (! note)
4129 continue;
4131 i = REGNO (SET_DEST (set));
4132 x = XEXP (note, 0);
4134 if (i <= LAST_VIRTUAL_REGISTER)
4135 continue;
4137 /* If flag_pic and we have constant, verify it's legitimate. */
4138 if (!CONSTANT_P (x)
4139 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4141 /* It can happen that a REG_EQUIV note contains a MEM
4142 that is not a legitimate memory operand. As later
4143 stages of reload assume that all addresses found
4144 in the reg_equiv_* arrays were originally legitimate,
4145 we ignore such REG_EQUIV notes. */
4146 if (memory_operand (x, VOIDmode))
4148 /* Always unshare the equivalence, so we can
4149 substitute into this insn without touching the
4150 equivalence. */
4151 reg_equiv_memory_loc (i) = copy_rtx (x);
4153 else if (function_invariant_p (x))
4155 machine_mode mode;
4157 mode = GET_MODE (SET_DEST (set));
4158 if (GET_CODE (x) == PLUS)
4160 /* This is PLUS of frame pointer and a constant,
4161 and might be shared. Unshare it. */
4162 reg_equiv_invariant (i) = copy_rtx (x);
4163 num_eliminable_invariants++;
4165 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4167 reg_equiv_invariant (i) = x;
4168 num_eliminable_invariants++;
4170 else if (targetm.legitimate_constant_p (mode, x))
4171 reg_equiv_constant (i) = x;
4172 else
4174 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4175 if (! reg_equiv_memory_loc (i))
4176 reg_equiv_init (i) = NULL;
4179 else
4181 reg_equiv_init (i) = NULL;
4182 continue;
4185 else
4186 reg_equiv_init (i) = NULL;
4190 if (dump_file)
4191 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4192 if (reg_equiv_init (i))
4194 fprintf (dump_file, "init_insns for %u: ", i);
4195 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4196 fprintf (dump_file, "\n");
4200 /* Indicate that we no longer have known memory locations or constants.
4201 Free all data involved in tracking these. */
4203 static void
4204 free_reg_equiv (void)
4206 int i;
4208 free (offsets_known_at);
4209 free (offsets_at);
4210 offsets_at = 0;
4211 offsets_known_at = 0;
4213 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4214 if (reg_equiv_alt_mem_list (i))
4215 free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4216 vec_free (reg_equivs);
4219 /* Kick all pseudos out of hard register REGNO.
4221 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4222 because we found we can't eliminate some register. In the case, no pseudos
4223 are allowed to be in the register, even if they are only in a block that
4224 doesn't require spill registers, unlike the case when we are spilling this
4225 hard reg to produce another spill register.
4227 Return nonzero if any pseudos needed to be kicked out. */
4229 static void
4230 spill_hard_reg (unsigned int regno, int cant_eliminate)
4232 int i;
4234 if (cant_eliminate)
4236 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4237 df_set_regs_ever_live (regno, true);
4240 /* Spill every pseudo reg that was allocated to this reg
4241 or to something that overlaps this reg. */
4243 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4244 if (reg_renumber[i] >= 0
4245 && (unsigned int) reg_renumber[i] <= regno
4246 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4247 SET_REGNO_REG_SET (&spilled_pseudos, i);
4250 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4251 insns that need reloads, this function is used to actually spill pseudo
4252 registers and try to reallocate them. It also sets up the spill_regs
4253 array for use by choose_reload_regs.
4255 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4256 that we displace from hard registers. */
4258 static int
4259 finish_spills (int global)
4261 struct insn_chain *chain;
4262 int something_changed = 0;
4263 unsigned i;
4264 reg_set_iterator rsi;
4266 /* Build the spill_regs array for the function. */
4267 /* If there are some registers still to eliminate and one of the spill regs
4268 wasn't ever used before, additional stack space may have to be
4269 allocated to store this register. Thus, we may have changed the offset
4270 between the stack and frame pointers, so mark that something has changed.
4272 One might think that we need only set VAL to 1 if this is a call-used
4273 register. However, the set of registers that must be saved by the
4274 prologue is not identical to the call-used set. For example, the
4275 register used by the call insn for the return PC is a call-used register,
4276 but must be saved by the prologue. */
4278 n_spills = 0;
4279 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4280 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4282 spill_reg_order[i] = n_spills;
4283 spill_regs[n_spills++] = i;
4284 if (num_eliminable && ! df_regs_ever_live_p (i))
4285 something_changed = 1;
4286 df_set_regs_ever_live (i, true);
4288 else
4289 spill_reg_order[i] = -1;
4291 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4292 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4294 /* Record the current hard register the pseudo is allocated to
4295 in pseudo_previous_regs so we avoid reallocating it to the
4296 same hard reg in a later pass. */
4297 gcc_assert (reg_renumber[i] >= 0);
4299 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4300 /* Mark it as no longer having a hard register home. */
4301 reg_renumber[i] = -1;
4302 if (ira_conflicts_p)
4303 /* Inform IRA about the change. */
4304 ira_mark_allocation_change (i);
4305 /* We will need to scan everything again. */
4306 something_changed = 1;
4309 /* Retry global register allocation if possible. */
4310 if (global && ira_conflicts_p)
4312 unsigned int n;
4314 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4315 /* For every insn that needs reloads, set the registers used as spill
4316 regs in pseudo_forbidden_regs for every pseudo live across the
4317 insn. */
4318 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4320 EXECUTE_IF_SET_IN_REG_SET
4321 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4323 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4324 chain->used_spill_regs);
4326 EXECUTE_IF_SET_IN_REG_SET
4327 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4329 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4330 chain->used_spill_regs);
4334 /* Retry allocating the pseudos spilled in IRA and the
4335 reload. For each reg, merge the various reg sets that
4336 indicate which hard regs can't be used, and call
4337 ira_reassign_pseudos. */
4338 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4339 if (reg_old_renumber[i] != reg_renumber[i])
4341 if (reg_renumber[i] < 0)
4342 temp_pseudo_reg_arr[n++] = i;
4343 else
4344 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4346 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4347 bad_spill_regs_global,
4348 pseudo_forbidden_regs, pseudo_previous_regs,
4349 &spilled_pseudos))
4350 something_changed = 1;
4352 /* Fix up the register information in the insn chain.
4353 This involves deleting those of the spilled pseudos which did not get
4354 a new hard register home from the live_{before,after} sets. */
4355 for (chain = reload_insn_chain; chain; chain = chain->next)
4357 HARD_REG_SET used_by_pseudos;
4358 HARD_REG_SET used_by_pseudos2;
4360 if (! ira_conflicts_p)
4362 /* Don't do it for IRA because IRA and the reload still can
4363 assign hard registers to the spilled pseudos on next
4364 reload iterations. */
4365 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4366 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4368 /* Mark any unallocated hard regs as available for spills. That
4369 makes inheritance work somewhat better. */
4370 if (chain->need_reload)
4372 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4373 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4374 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4376 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4377 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4378 /* Value of chain->used_spill_regs from previous iteration
4379 may be not included in the value calculated here because
4380 of possible removing caller-saves insns (see function
4381 delete_caller_save_insns. */
4382 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4383 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4387 CLEAR_REG_SET (&changed_allocation_pseudos);
4388 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4389 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4391 int regno = reg_renumber[i];
4392 if (reg_old_renumber[i] == regno)
4393 continue;
4395 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4397 alter_reg (i, reg_old_renumber[i], false);
4398 reg_old_renumber[i] = regno;
4399 if (dump_file)
4401 if (regno == -1)
4402 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4403 else
4404 fprintf (dump_file, " Register %d now in %d.\n\n",
4405 i, reg_renumber[i]);
4409 return something_changed;
4412 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4414 static void
4415 scan_paradoxical_subregs (rtx x)
4417 int i;
4418 const char *fmt;
4419 enum rtx_code code = GET_CODE (x);
4421 switch (code)
4423 case REG:
4424 case CONST:
4425 case SYMBOL_REF:
4426 case LABEL_REF:
4427 CASE_CONST_ANY:
4428 case CC0:
4429 case PC:
4430 case USE:
4431 case CLOBBER:
4432 return;
4434 case SUBREG:
4435 if (REG_P (SUBREG_REG (x)))
4437 unsigned int regno = REGNO (SUBREG_REG (x));
4438 if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))
4440 reg_max_ref_mode[regno] = GET_MODE (x);
4441 mark_home_live_1 (regno, GET_MODE (x));
4444 return;
4446 default:
4447 break;
4450 fmt = GET_RTX_FORMAT (code);
4451 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4453 if (fmt[i] == 'e')
4454 scan_paradoxical_subregs (XEXP (x, i));
4455 else if (fmt[i] == 'E')
4457 int j;
4458 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4459 scan_paradoxical_subregs (XVECEXP (x, i, j));
4464 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4465 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4466 and apply the corresponding narrowing subreg to *OTHER_PTR.
4467 Return true if the operands were changed, false otherwise. */
4469 static bool
4470 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4472 rtx op, inner, other, tem;
4474 op = *op_ptr;
4475 if (!paradoxical_subreg_p (op))
4476 return false;
4477 inner = SUBREG_REG (op);
4479 other = *other_ptr;
4480 tem = gen_lowpart_common (GET_MODE (inner), other);
4481 if (!tem)
4482 return false;
4484 /* If the lowpart operation turned a hard register into a subreg,
4485 rather than simplifying it to another hard register, then the
4486 mode change cannot be properly represented. For example, OTHER
4487 might be valid in its current mode, but not in the new one. */
4488 if (GET_CODE (tem) == SUBREG
4489 && REG_P (other)
4490 && HARD_REGISTER_P (other))
4491 return false;
4493 *op_ptr = inner;
4494 *other_ptr = tem;
4495 return true;
4498 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4499 examine all of the reload insns between PREV and NEXT exclusive, and
4500 annotate all that may trap. */
4502 static void
4503 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4505 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4506 if (note == NULL)
4507 return;
4508 if (!insn_could_throw_p (insn))
4509 remove_note (insn, note);
4510 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4513 /* Reload pseudo-registers into hard regs around each insn as needed.
4514 Additional register load insns are output before the insn that needs it
4515 and perhaps store insns after insns that modify the reloaded pseudo reg.
4517 reg_last_reload_reg and reg_reloaded_contents keep track of
4518 which registers are already available in reload registers.
4519 We update these for the reloads that we perform,
4520 as the insns are scanned. */
4522 static void
4523 reload_as_needed (int live_known)
4525 struct insn_chain *chain;
4526 #if AUTO_INC_DEC
4527 int i;
4528 #endif
4529 rtx_note *marker;
4531 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4532 memset (spill_reg_store, 0, sizeof spill_reg_store);
4533 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4534 INIT_REG_SET (&reg_has_output_reload);
4535 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4536 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4538 set_initial_elim_offsets ();
4540 /* Generate a marker insn that we will move around. */
4541 marker = emit_note (NOTE_INSN_DELETED);
4542 unlink_insn_chain (marker, marker);
4544 for (chain = reload_insn_chain; chain; chain = chain->next)
4546 rtx_insn *prev = 0;
4547 rtx_insn *insn = chain->insn;
4548 rtx_insn *old_next = NEXT_INSN (insn);
4549 #if AUTO_INC_DEC
4550 rtx_insn *old_prev = PREV_INSN (insn);
4551 #endif
4553 if (will_delete_init_insn_p (insn))
4554 continue;
4556 /* If we pass a label, copy the offsets from the label information
4557 into the current offsets of each elimination. */
4558 if (LABEL_P (insn))
4559 set_offsets_for_label (insn);
4561 else if (INSN_P (insn))
4563 regset_head regs_to_forget;
4564 INIT_REG_SET (&regs_to_forget);
4565 note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4567 /* If this is a USE and CLOBBER of a MEM, ensure that any
4568 references to eliminable registers have been removed. */
4570 if ((GET_CODE (PATTERN (insn)) == USE
4571 || GET_CODE (PATTERN (insn)) == CLOBBER)
4572 && MEM_P (XEXP (PATTERN (insn), 0)))
4573 XEXP (XEXP (PATTERN (insn), 0), 0)
4574 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4575 GET_MODE (XEXP (PATTERN (insn), 0)),
4576 NULL_RTX);
4578 /* If we need to do register elimination processing, do so.
4579 This might delete the insn, in which case we are done. */
4580 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4582 eliminate_regs_in_insn (insn, 1);
4583 if (NOTE_P (insn))
4585 update_eliminable_offsets ();
4586 CLEAR_REG_SET (&regs_to_forget);
4587 continue;
4591 /* If need_elim is nonzero but need_reload is zero, one might think
4592 that we could simply set n_reloads to 0. However, find_reloads
4593 could have done some manipulation of the insn (such as swapping
4594 commutative operands), and these manipulations are lost during
4595 the first pass for every insn that needs register elimination.
4596 So the actions of find_reloads must be redone here. */
4598 if (! chain->need_elim && ! chain->need_reload
4599 && ! chain->need_operand_change)
4600 n_reloads = 0;
4601 /* First find the pseudo regs that must be reloaded for this insn.
4602 This info is returned in the tables reload_... (see reload.h).
4603 Also modify the body of INSN by substituting RELOAD
4604 rtx's for those pseudo regs. */
4605 else
4607 CLEAR_REG_SET (&reg_has_output_reload);
4608 CLEAR_HARD_REG_SET (reg_is_output_reload);
4610 find_reloads (insn, 1, spill_indirect_levels, live_known,
4611 spill_reg_order);
4614 if (n_reloads > 0)
4616 rtx_insn *next = NEXT_INSN (insn);
4618 /* ??? PREV can get deleted by reload inheritance.
4619 Work around this by emitting a marker note. */
4620 prev = PREV_INSN (insn);
4621 reorder_insns_nobb (marker, marker, prev);
4623 /* Now compute which reload regs to reload them into. Perhaps
4624 reusing reload regs from previous insns, or else output
4625 load insns to reload them. Maybe output store insns too.
4626 Record the choices of reload reg in reload_reg_rtx. */
4627 choose_reload_regs (chain);
4629 /* Generate the insns to reload operands into or out of
4630 their reload regs. */
4631 emit_reload_insns (chain);
4633 /* Substitute the chosen reload regs from reload_reg_rtx
4634 into the insn's body (or perhaps into the bodies of other
4635 load and store insn that we just made for reloading
4636 and that we moved the structure into). */
4637 subst_reloads (insn);
4639 prev = PREV_INSN (marker);
4640 unlink_insn_chain (marker, marker);
4642 /* Adjust the exception region notes for loads and stores. */
4643 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4644 fixup_eh_region_note (insn, prev, next);
4646 /* Adjust the location of REG_ARGS_SIZE. */
4647 rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4648 if (p)
4650 remove_note (insn, p);
4651 fixup_args_size_notes (prev, PREV_INSN (next),
4652 get_args_size (p));
4655 /* If this was an ASM, make sure that all the reload insns
4656 we have generated are valid. If not, give an error
4657 and delete them. */
4658 if (asm_noperands (PATTERN (insn)) >= 0)
4659 for (rtx_insn *p = NEXT_INSN (prev);
4660 p != next;
4661 p = NEXT_INSN (p))
4662 if (p != insn && INSN_P (p)
4663 && GET_CODE (PATTERN (p)) != USE
4664 && (recog_memoized (p) < 0
4665 || (extract_insn (p),
4666 !(constrain_operands (1,
4667 get_enabled_alternatives (p))))))
4669 error_for_asm (insn,
4670 "%<asm%> operand requires "
4671 "impossible reload");
4672 delete_insn (p);
4676 if (num_eliminable && chain->need_elim)
4677 update_eliminable_offsets ();
4679 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4680 is no longer validly lying around to save a future reload.
4681 Note that this does not detect pseudos that were reloaded
4682 for this insn in order to be stored in
4683 (obeying register constraints). That is correct; such reload
4684 registers ARE still valid. */
4685 forget_marked_reloads (&regs_to_forget);
4686 CLEAR_REG_SET (&regs_to_forget);
4688 /* There may have been CLOBBER insns placed after INSN. So scan
4689 between INSN and NEXT and use them to forget old reloads. */
4690 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4691 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4692 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4694 #if AUTO_INC_DEC
4695 /* Likewise for regs altered by auto-increment in this insn.
4696 REG_INC notes have been changed by reloading:
4697 find_reloads_address_1 records substitutions for them,
4698 which have been performed by subst_reloads above. */
4699 for (i = n_reloads - 1; i >= 0; i--)
4701 rtx in_reg = rld[i].in_reg;
4702 if (in_reg)
4704 enum rtx_code code = GET_CODE (in_reg);
4705 /* PRE_INC / PRE_DEC will have the reload register ending up
4706 with the same value as the stack slot, but that doesn't
4707 hold true for POST_INC / POST_DEC. Either we have to
4708 convert the memory access to a true POST_INC / POST_DEC,
4709 or we can't use the reload register for inheritance. */
4710 if ((code == POST_INC || code == POST_DEC)
4711 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4712 REGNO (rld[i].reg_rtx))
4713 /* Make sure it is the inc/dec pseudo, and not
4714 some other (e.g. output operand) pseudo. */
4715 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4716 == REGNO (XEXP (in_reg, 0))))
4719 rtx reload_reg = rld[i].reg_rtx;
4720 machine_mode mode = GET_MODE (reload_reg);
4721 int n = 0;
4722 rtx_insn *p;
4724 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4726 /* We really want to ignore REG_INC notes here, so
4727 use PATTERN (p) as argument to reg_set_p . */
4728 if (reg_set_p (reload_reg, PATTERN (p)))
4729 break;
4730 n = count_occurrences (PATTERN (p), reload_reg, 0);
4731 if (! n)
4732 continue;
4733 if (n == 1)
4735 rtx replace_reg
4736 = gen_rtx_fmt_e (code, mode, reload_reg);
4738 validate_replace_rtx_group (reload_reg,
4739 replace_reg, p);
4740 n = verify_changes (0);
4742 /* We must also verify that the constraints
4743 are met after the replacement. Make sure
4744 extract_insn is only called for an insn
4745 where the replacements were found to be
4746 valid so far. */
4747 if (n)
4749 extract_insn (p);
4750 n = constrain_operands (1,
4751 get_enabled_alternatives (p));
4754 /* If the constraints were not met, then
4755 undo the replacement, else confirm it. */
4756 if (!n)
4757 cancel_changes (0);
4758 else
4759 confirm_change_group ();
4761 break;
4763 if (n == 1)
4765 add_reg_note (p, REG_INC, reload_reg);
4766 /* Mark this as having an output reload so that the
4767 REG_INC processing code below won't invalidate
4768 the reload for inheritance. */
4769 SET_HARD_REG_BIT (reg_is_output_reload,
4770 REGNO (reload_reg));
4771 SET_REGNO_REG_SET (&reg_has_output_reload,
4772 REGNO (XEXP (in_reg, 0)));
4774 else
4775 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4776 NULL);
4778 else if ((code == PRE_INC || code == PRE_DEC)
4779 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4780 REGNO (rld[i].reg_rtx))
4781 /* Make sure it is the inc/dec pseudo, and not
4782 some other (e.g. output operand) pseudo. */
4783 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4784 == REGNO (XEXP (in_reg, 0))))
4786 SET_HARD_REG_BIT (reg_is_output_reload,
4787 REGNO (rld[i].reg_rtx));
4788 SET_REGNO_REG_SET (&reg_has_output_reload,
4789 REGNO (XEXP (in_reg, 0)));
4791 else if (code == PRE_INC || code == PRE_DEC
4792 || code == POST_INC || code == POST_DEC)
4794 int in_regno = REGNO (XEXP (in_reg, 0));
4796 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4798 int in_hard_regno;
4799 bool forget_p = true;
4801 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4802 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4803 in_hard_regno))
4805 for (rtx_insn *x = (old_prev ?
4806 NEXT_INSN (old_prev) : insn);
4807 x != old_next;
4808 x = NEXT_INSN (x))
4809 if (x == reg_reloaded_insn[in_hard_regno])
4811 forget_p = false;
4812 break;
4815 /* If for some reasons, we didn't set up
4816 reg_last_reload_reg in this insn,
4817 invalidate inheritance from previous
4818 insns for the incremented/decremented
4819 register. Such registers will be not in
4820 reg_has_output_reload. Invalidate it
4821 also if the corresponding element in
4822 reg_reloaded_insn is also
4823 invalidated. */
4824 if (forget_p)
4825 forget_old_reloads_1 (XEXP (in_reg, 0),
4826 NULL_RTX, NULL);
4831 /* If a pseudo that got a hard register is auto-incremented,
4832 we must purge records of copying it into pseudos without
4833 hard registers. */
4834 for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4835 if (REG_NOTE_KIND (x) == REG_INC)
4837 /* See if this pseudo reg was reloaded in this insn.
4838 If so, its last-reload info is still valid
4839 because it is based on this insn's reload. */
4840 for (i = 0; i < n_reloads; i++)
4841 if (rld[i].out == XEXP (x, 0))
4842 break;
4844 if (i == n_reloads)
4845 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4847 #endif
4849 /* A reload reg's contents are unknown after a label. */
4850 if (LABEL_P (insn))
4851 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4853 /* Don't assume a reload reg is still good after a call insn
4854 if it is a call-used reg, or if it contains a value that will
4855 be partially clobbered by the call. */
4856 else if (CALL_P (insn))
4858 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4859 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4861 /* If this is a call to a setjmp-type function, we must not
4862 reuse any reload reg contents across the call; that will
4863 just be clobbered by other uses of the register in later
4864 code, before the longjmp. */
4865 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4866 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4870 /* Clean up. */
4871 free (reg_last_reload_reg);
4872 CLEAR_REG_SET (&reg_has_output_reload);
4875 /* Discard all record of any value reloaded from X,
4876 or reloaded in X from someplace else;
4877 unless X is an output reload reg of the current insn.
4879 X may be a hard reg (the reload reg)
4880 or it may be a pseudo reg that was reloaded from.
4882 When DATA is non-NULL just mark the registers in regset
4883 to be forgotten later. */
4885 static void
4886 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4887 void *data)
4889 unsigned int regno;
4890 unsigned int nr;
4891 regset regs = (regset) data;
4893 /* note_stores does give us subregs of hard regs,
4894 subreg_regno_offset requires a hard reg. */
4895 while (GET_CODE (x) == SUBREG)
4897 /* We ignore the subreg offset when calculating the regno,
4898 because we are using the entire underlying hard register
4899 below. */
4900 x = SUBREG_REG (x);
4903 if (!REG_P (x))
4904 return;
4906 regno = REGNO (x);
4908 if (regno >= FIRST_PSEUDO_REGISTER)
4909 nr = 1;
4910 else
4912 unsigned int i;
4914 nr = REG_NREGS (x);
4915 /* Storing into a spilled-reg invalidates its contents.
4916 This can happen if a block-local pseudo is allocated to that reg
4917 and it wasn't spilled because this block's total need is 0.
4918 Then some insn might have an optional reload and use this reg. */
4919 if (!regs)
4920 for (i = 0; i < nr; i++)
4921 /* But don't do this if the reg actually serves as an output
4922 reload reg in the current instruction. */
4923 if (n_reloads == 0
4924 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4926 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4927 spill_reg_store[regno + i] = 0;
4931 if (regs)
4932 while (nr-- > 0)
4933 SET_REGNO_REG_SET (regs, regno + nr);
4934 else
4936 /* Since value of X has changed,
4937 forget any value previously copied from it. */
4939 while (nr-- > 0)
4940 /* But don't forget a copy if this is the output reload
4941 that establishes the copy's validity. */
4942 if (n_reloads == 0
4943 || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
4944 reg_last_reload_reg[regno + nr] = 0;
4948 /* Forget the reloads marked in regset by previous function. */
4949 static void
4950 forget_marked_reloads (regset regs)
4952 unsigned int reg;
4953 reg_set_iterator rsi;
4954 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4956 if (reg < FIRST_PSEUDO_REGISTER
4957 /* But don't do this if the reg actually serves as an output
4958 reload reg in the current instruction. */
4959 && (n_reloads == 0
4960 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4962 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4963 spill_reg_store[reg] = 0;
4965 if (n_reloads == 0
4966 || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
4967 reg_last_reload_reg[reg] = 0;
4971 /* The following HARD_REG_SETs indicate when each hard register is
4972 used for a reload of various parts of the current insn. */
4974 /* If reg is unavailable for all reloads. */
4975 static HARD_REG_SET reload_reg_unavailable;
4976 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4977 static HARD_REG_SET reload_reg_used;
4978 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4979 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4980 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4981 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4982 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4983 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4984 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4985 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4986 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4987 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4988 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4989 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4990 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4991 static HARD_REG_SET reload_reg_used_in_op_addr;
4992 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4993 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4994 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4995 static HARD_REG_SET reload_reg_used_in_insn;
4996 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4997 static HARD_REG_SET reload_reg_used_in_other_addr;
4999 /* If reg is in use as a reload reg for any sort of reload. */
5000 static HARD_REG_SET reload_reg_used_at_all;
5002 /* If reg is use as an inherited reload. We just mark the first register
5003 in the group. */
5004 static HARD_REG_SET reload_reg_used_for_inherit;
5006 /* Records which hard regs are used in any way, either as explicit use or
5007 by being allocated to a pseudo during any point of the current insn. */
5008 static HARD_REG_SET reg_used_in_insn;
5010 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5011 TYPE. MODE is used to indicate how many consecutive regs are
5012 actually used. */
5014 static void
5015 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5016 machine_mode mode)
5018 switch (type)
5020 case RELOAD_OTHER:
5021 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5022 break;
5024 case RELOAD_FOR_INPUT_ADDRESS:
5025 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5026 break;
5028 case RELOAD_FOR_INPADDR_ADDRESS:
5029 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5030 break;
5032 case RELOAD_FOR_OUTPUT_ADDRESS:
5033 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5034 break;
5036 case RELOAD_FOR_OUTADDR_ADDRESS:
5037 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5038 break;
5040 case RELOAD_FOR_OPERAND_ADDRESS:
5041 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5042 break;
5044 case RELOAD_FOR_OPADDR_ADDR:
5045 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5046 break;
5048 case RELOAD_FOR_OTHER_ADDRESS:
5049 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5050 break;
5052 case RELOAD_FOR_INPUT:
5053 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5054 break;
5056 case RELOAD_FOR_OUTPUT:
5057 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5058 break;
5060 case RELOAD_FOR_INSN:
5061 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5062 break;
5065 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5068 /* Similarly, but show REGNO is no longer in use for a reload. */
5070 static void
5071 clear_reload_reg_in_use (unsigned int regno, int opnum,
5072 enum reload_type type, machine_mode mode)
5074 unsigned int nregs = hard_regno_nregs (regno, mode);
5075 unsigned int start_regno, end_regno, r;
5076 int i;
5077 /* A complication is that for some reload types, inheritance might
5078 allow multiple reloads of the same types to share a reload register.
5079 We set check_opnum if we have to check only reloads with the same
5080 operand number, and check_any if we have to check all reloads. */
5081 int check_opnum = 0;
5082 int check_any = 0;
5083 HARD_REG_SET *used_in_set;
5085 switch (type)
5087 case RELOAD_OTHER:
5088 used_in_set = &reload_reg_used;
5089 break;
5091 case RELOAD_FOR_INPUT_ADDRESS:
5092 used_in_set = &reload_reg_used_in_input_addr[opnum];
5093 break;
5095 case RELOAD_FOR_INPADDR_ADDRESS:
5096 check_opnum = 1;
5097 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5098 break;
5100 case RELOAD_FOR_OUTPUT_ADDRESS:
5101 used_in_set = &reload_reg_used_in_output_addr[opnum];
5102 break;
5104 case RELOAD_FOR_OUTADDR_ADDRESS:
5105 check_opnum = 1;
5106 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5107 break;
5109 case RELOAD_FOR_OPERAND_ADDRESS:
5110 used_in_set = &reload_reg_used_in_op_addr;
5111 break;
5113 case RELOAD_FOR_OPADDR_ADDR:
5114 check_any = 1;
5115 used_in_set = &reload_reg_used_in_op_addr_reload;
5116 break;
5118 case RELOAD_FOR_OTHER_ADDRESS:
5119 used_in_set = &reload_reg_used_in_other_addr;
5120 check_any = 1;
5121 break;
5123 case RELOAD_FOR_INPUT:
5124 used_in_set = &reload_reg_used_in_input[opnum];
5125 break;
5127 case RELOAD_FOR_OUTPUT:
5128 used_in_set = &reload_reg_used_in_output[opnum];
5129 break;
5131 case RELOAD_FOR_INSN:
5132 used_in_set = &reload_reg_used_in_insn;
5133 break;
5134 default:
5135 gcc_unreachable ();
5137 /* We resolve conflicts with remaining reloads of the same type by
5138 excluding the intervals of reload registers by them from the
5139 interval of freed reload registers. Since we only keep track of
5140 one set of interval bounds, we might have to exclude somewhat
5141 more than what would be necessary if we used a HARD_REG_SET here.
5142 But this should only happen very infrequently, so there should
5143 be no reason to worry about it. */
5145 start_regno = regno;
5146 end_regno = regno + nregs;
5147 if (check_opnum || check_any)
5149 for (i = n_reloads - 1; i >= 0; i--)
5151 if (rld[i].when_needed == type
5152 && (check_any || rld[i].opnum == opnum)
5153 && rld[i].reg_rtx)
5155 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5156 unsigned int conflict_end
5157 = end_hard_regno (rld[i].mode, conflict_start);
5159 /* If there is an overlap with the first to-be-freed register,
5160 adjust the interval start. */
5161 if (conflict_start <= start_regno && conflict_end > start_regno)
5162 start_regno = conflict_end;
5163 /* Otherwise, if there is a conflict with one of the other
5164 to-be-freed registers, adjust the interval end. */
5165 if (conflict_start > start_regno && conflict_start < end_regno)
5166 end_regno = conflict_start;
5171 for (r = start_regno; r < end_regno; r++)
5172 CLEAR_HARD_REG_BIT (*used_in_set, r);
5175 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5176 specified by OPNUM and TYPE. */
5178 static int
5179 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5181 int i;
5183 /* In use for a RELOAD_OTHER means it's not available for anything. */
5184 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5185 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5186 return 0;
5188 switch (type)
5190 case RELOAD_OTHER:
5191 /* In use for anything means we can't use it for RELOAD_OTHER. */
5192 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5193 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5194 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5195 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5196 return 0;
5198 for (i = 0; i < reload_n_operands; i++)
5199 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5200 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5201 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5202 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5203 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5204 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5205 return 0;
5207 return 1;
5209 case RELOAD_FOR_INPUT:
5210 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5211 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5212 return 0;
5214 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5215 return 0;
5217 /* If it is used for some other input, can't use it. */
5218 for (i = 0; i < reload_n_operands; i++)
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5220 return 0;
5222 /* If it is used in a later operand's address, can't use it. */
5223 for (i = opnum + 1; i < reload_n_operands; i++)
5224 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5225 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5226 return 0;
5228 return 1;
5230 case RELOAD_FOR_INPUT_ADDRESS:
5231 /* Can't use a register if it is used for an input address for this
5232 operand or used as an input in an earlier one. */
5233 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5234 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5235 return 0;
5237 for (i = 0; i < opnum; i++)
5238 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5239 return 0;
5241 return 1;
5243 case RELOAD_FOR_INPADDR_ADDRESS:
5244 /* Can't use a register if it is used for an input address
5245 for this operand or used as an input in an earlier
5246 one. */
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5248 return 0;
5250 for (i = 0; i < opnum; i++)
5251 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5252 return 0;
5254 return 1;
5256 case RELOAD_FOR_OUTPUT_ADDRESS:
5257 /* Can't use a register if it is used for an output address for this
5258 operand or used as an output in this or a later operand. Note
5259 that multiple output operands are emitted in reverse order, so
5260 the conflicting ones are those with lower indices. */
5261 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5262 return 0;
5264 for (i = 0; i <= opnum; i++)
5265 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5266 return 0;
5268 return 1;
5270 case RELOAD_FOR_OUTADDR_ADDRESS:
5271 /* Can't use a register if it is used for an output address
5272 for this operand or used as an output in this or a
5273 later operand. Note that multiple output operands are
5274 emitted in reverse order, so the conflicting ones are
5275 those with lower indices. */
5276 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5277 return 0;
5279 for (i = 0; i <= opnum; i++)
5280 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5281 return 0;
5283 return 1;
5285 case RELOAD_FOR_OPERAND_ADDRESS:
5286 for (i = 0; i < reload_n_operands; i++)
5287 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5288 return 0;
5290 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5291 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5293 case RELOAD_FOR_OPADDR_ADDR:
5294 for (i = 0; i < reload_n_operands; i++)
5295 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5296 return 0;
5298 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5300 case RELOAD_FOR_OUTPUT:
5301 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5302 outputs, or an operand address for this or an earlier output.
5303 Note that multiple output operands are emitted in reverse order,
5304 so the conflicting ones are those with higher indices. */
5305 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5306 return 0;
5308 for (i = 0; i < reload_n_operands; i++)
5309 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5310 return 0;
5312 for (i = opnum; i < reload_n_operands; i++)
5313 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5314 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5315 return 0;
5317 return 1;
5319 case RELOAD_FOR_INSN:
5320 for (i = 0; i < reload_n_operands; i++)
5321 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5322 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5323 return 0;
5325 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5326 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5328 case RELOAD_FOR_OTHER_ADDRESS:
5329 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5331 default:
5332 gcc_unreachable ();
5336 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5337 the number RELOADNUM, is still available in REGNO at the end of the insn.
5339 We can assume that the reload reg was already tested for availability
5340 at the time it is needed, and we should not check this again,
5341 in case the reg has already been marked in use. */
5343 static int
5344 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5346 int opnum = rld[reloadnum].opnum;
5347 enum reload_type type = rld[reloadnum].when_needed;
5348 int i;
5350 /* See if there is a reload with the same type for this operand, using
5351 the same register. This case is not handled by the code below. */
5352 for (i = reloadnum + 1; i < n_reloads; i++)
5354 rtx reg;
5356 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5357 continue;
5358 reg = rld[i].reg_rtx;
5359 if (reg == NULL_RTX)
5360 continue;
5361 if (regno >= REGNO (reg) && regno < END_REGNO (reg))
5362 return 0;
5365 switch (type)
5367 case RELOAD_OTHER:
5368 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5369 its value must reach the end. */
5370 return 1;
5372 /* If this use is for part of the insn,
5373 its value reaches if no subsequent part uses the same register.
5374 Just like the above function, don't try to do this with lots
5375 of fallthroughs. */
5377 case RELOAD_FOR_OTHER_ADDRESS:
5378 /* Here we check for everything else, since these don't conflict
5379 with anything else and everything comes later. */
5381 for (i = 0; i < reload_n_operands; i++)
5382 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5383 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5384 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5385 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5386 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5387 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5388 return 0;
5390 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5391 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5392 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5393 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5395 case RELOAD_FOR_INPUT_ADDRESS:
5396 case RELOAD_FOR_INPADDR_ADDRESS:
5397 /* Similar, except that we check only for this and subsequent inputs
5398 and the address of only subsequent inputs and we do not need
5399 to check for RELOAD_OTHER objects since they are known not to
5400 conflict. */
5402 for (i = opnum; i < reload_n_operands; i++)
5403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5404 return 0;
5406 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5407 could be killed if the register is also used by reload with type
5408 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5409 if (type == RELOAD_FOR_INPADDR_ADDRESS
5410 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5411 return 0;
5413 for (i = opnum + 1; i < reload_n_operands; i++)
5414 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5416 return 0;
5418 for (i = 0; i < reload_n_operands; i++)
5419 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5420 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5421 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5422 return 0;
5424 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5425 return 0;
5427 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5428 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5429 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5431 case RELOAD_FOR_INPUT:
5432 /* Similar to input address, except we start at the next operand for
5433 both input and input address and we do not check for
5434 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5435 would conflict. */
5437 for (i = opnum + 1; i < reload_n_operands; i++)
5438 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5439 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5440 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5441 return 0;
5443 /* ... fall through ... */
5445 case RELOAD_FOR_OPERAND_ADDRESS:
5446 /* Check outputs and their addresses. */
5448 for (i = 0; i < reload_n_operands; i++)
5449 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5451 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5452 return 0;
5454 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5456 case RELOAD_FOR_OPADDR_ADDR:
5457 for (i = 0; i < reload_n_operands; i++)
5458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5459 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5460 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5461 return 0;
5463 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5464 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5465 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5467 case RELOAD_FOR_INSN:
5468 /* These conflict with other outputs with RELOAD_OTHER. So
5469 we need only check for output addresses. */
5471 opnum = reload_n_operands;
5473 /* fall through */
5475 case RELOAD_FOR_OUTPUT:
5476 case RELOAD_FOR_OUTPUT_ADDRESS:
5477 case RELOAD_FOR_OUTADDR_ADDRESS:
5478 /* We already know these can't conflict with a later output. So the
5479 only thing to check are later output addresses.
5480 Note that multiple output operands are emitted in reverse order,
5481 so the conflicting ones are those with lower indices. */
5482 for (i = 0; i < opnum; i++)
5483 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5484 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5485 return 0;
5487 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5488 could be killed if the register is also used by reload with type
5489 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5490 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5491 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5492 return 0;
5494 return 1;
5496 default:
5497 gcc_unreachable ();
5501 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5502 every register in REG. */
5504 static bool
5505 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5507 unsigned int i;
5509 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5510 if (!reload_reg_reaches_end_p (i, reloadnum))
5511 return false;
5512 return true;
5516 /* Returns whether R1 and R2 are uniquely chained: the value of one
5517 is used by the other, and that value is not used by any other
5518 reload for this insn. This is used to partially undo the decision
5519 made in find_reloads when in the case of multiple
5520 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5521 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5522 reloads. This code tries to avoid the conflict created by that
5523 change. It might be cleaner to explicitly keep track of which
5524 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5525 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5526 this after the fact. */
5527 static bool
5528 reloads_unique_chain_p (int r1, int r2)
5530 int i;
5532 /* We only check input reloads. */
5533 if (! rld[r1].in || ! rld[r2].in)
5534 return false;
5536 /* Avoid anything with output reloads. */
5537 if (rld[r1].out || rld[r2].out)
5538 return false;
5540 /* "chained" means one reload is a component of the other reload,
5541 not the same as the other reload. */
5542 if (rld[r1].opnum != rld[r2].opnum
5543 || rtx_equal_p (rld[r1].in, rld[r2].in)
5544 || rld[r1].optional || rld[r2].optional
5545 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5546 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5547 return false;
5549 /* The following loop assumes that r1 is the reload that feeds r2. */
5550 if (r1 > r2)
5551 std::swap (r1, r2);
5553 for (i = 0; i < n_reloads; i ++)
5554 /* Look for input reloads that aren't our two */
5555 if (i != r1 && i != r2 && rld[i].in)
5557 /* If our reload is mentioned at all, it isn't a simple chain. */
5558 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5559 return false;
5561 return true;
5564 /* The recursive function change all occurrences of WHAT in *WHERE
5565 to REPL. */
5566 static void
5567 substitute (rtx *where, const_rtx what, rtx repl)
5569 const char *fmt;
5570 int i;
5571 enum rtx_code code;
5573 if (*where == 0)
5574 return;
5576 if (*where == what || rtx_equal_p (*where, what))
5578 /* Record the location of the changed rtx. */
5579 substitute_stack.safe_push (where);
5580 *where = repl;
5581 return;
5584 code = GET_CODE (*where);
5585 fmt = GET_RTX_FORMAT (code);
5586 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5588 if (fmt[i] == 'E')
5590 int j;
5592 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5593 substitute (&XVECEXP (*where, i, j), what, repl);
5595 else if (fmt[i] == 'e')
5596 substitute (&XEXP (*where, i), what, repl);
5600 /* The function returns TRUE if chain of reload R1 and R2 (in any
5601 order) can be evaluated without usage of intermediate register for
5602 the reload containing another reload. It is important to see
5603 gen_reload to understand what the function is trying to do. As an
5604 example, let us have reload chain
5606 r2: const
5607 r1: <something> + const
5609 and reload R2 got reload reg HR. The function returns true if
5610 there is a correct insn HR = HR + <something>. Otherwise,
5611 gen_reload will use intermediate register (and this is the reload
5612 reg for R1) to reload <something>.
5614 We need this function to find a conflict for chain reloads. In our
5615 example, if HR = HR + <something> is incorrect insn, then we cannot
5616 use HR as a reload register for R2. If we do use it then we get a
5617 wrong code:
5619 HR = const
5620 HR = <something>
5621 HR = HR + HR
5624 static bool
5625 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5627 /* Assume other cases in gen_reload are not possible for
5628 chain reloads or do need an intermediate hard registers. */
5629 bool result = true;
5630 int regno, code;
5631 rtx out, in;
5632 rtx_insn *insn;
5633 rtx_insn *last = get_last_insn ();
5635 /* Make r2 a component of r1. */
5636 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5637 std::swap (r1, r2);
5639 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5640 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5641 gcc_assert (regno >= 0);
5642 out = gen_rtx_REG (rld[r1].mode, regno);
5643 in = rld[r1].in;
5644 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5646 /* If IN is a paradoxical SUBREG, remove it and try to put the
5647 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5648 strip_paradoxical_subreg (&in, &out);
5650 if (GET_CODE (in) == PLUS
5651 && (REG_P (XEXP (in, 0))
5652 || GET_CODE (XEXP (in, 0)) == SUBREG
5653 || MEM_P (XEXP (in, 0)))
5654 && (REG_P (XEXP (in, 1))
5655 || GET_CODE (XEXP (in, 1)) == SUBREG
5656 || CONSTANT_P (XEXP (in, 1))
5657 || MEM_P (XEXP (in, 1))))
5659 insn = emit_insn (gen_rtx_SET (out, in));
5660 code = recog_memoized (insn);
5661 result = false;
5663 if (code >= 0)
5665 extract_insn (insn);
5666 /* We want constrain operands to treat this insn strictly in
5667 its validity determination, i.e., the way it would after
5668 reload has completed. */
5669 result = constrain_operands (1, get_enabled_alternatives (insn));
5672 delete_insns_since (last);
5675 /* Restore the original value at each changed address within R1. */
5676 while (!substitute_stack.is_empty ())
5678 rtx *where = substitute_stack.pop ();
5679 *where = rld[r2].in;
5682 return result;
5685 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5686 Return 0 otherwise.
5688 This function uses the same algorithm as reload_reg_free_p above. */
5690 static int
5691 reloads_conflict (int r1, int r2)
5693 enum reload_type r1_type = rld[r1].when_needed;
5694 enum reload_type r2_type = rld[r2].when_needed;
5695 int r1_opnum = rld[r1].opnum;
5696 int r2_opnum = rld[r2].opnum;
5698 /* RELOAD_OTHER conflicts with everything. */
5699 if (r2_type == RELOAD_OTHER)
5700 return 1;
5702 /* Otherwise, check conflicts differently for each type. */
5704 switch (r1_type)
5706 case RELOAD_FOR_INPUT:
5707 return (r2_type == RELOAD_FOR_INSN
5708 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5709 || r2_type == RELOAD_FOR_OPADDR_ADDR
5710 || r2_type == RELOAD_FOR_INPUT
5711 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5712 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5713 && r2_opnum > r1_opnum));
5715 case RELOAD_FOR_INPUT_ADDRESS:
5716 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5717 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5719 case RELOAD_FOR_INPADDR_ADDRESS:
5720 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5721 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5723 case RELOAD_FOR_OUTPUT_ADDRESS:
5724 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5725 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5727 case RELOAD_FOR_OUTADDR_ADDRESS:
5728 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5729 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5731 case RELOAD_FOR_OPERAND_ADDRESS:
5732 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5733 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5734 && (!reloads_unique_chain_p (r1, r2)
5735 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5737 case RELOAD_FOR_OPADDR_ADDR:
5738 return (r2_type == RELOAD_FOR_INPUT
5739 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5741 case RELOAD_FOR_OUTPUT:
5742 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5743 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5744 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5745 && r2_opnum >= r1_opnum));
5747 case RELOAD_FOR_INSN:
5748 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5749 || r2_type == RELOAD_FOR_INSN
5750 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5752 case RELOAD_FOR_OTHER_ADDRESS:
5753 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5755 case RELOAD_OTHER:
5756 return 1;
5758 default:
5759 gcc_unreachable ();
5763 /* Indexed by reload number, 1 if incoming value
5764 inherited from previous insns. */
5765 static char reload_inherited[MAX_RELOADS];
5767 /* For an inherited reload, this is the insn the reload was inherited from,
5768 if we know it. Otherwise, this is 0. */
5769 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5771 /* If nonzero, this is a place to get the value of the reload,
5772 rather than using reload_in. */
5773 static rtx reload_override_in[MAX_RELOADS];
5775 /* For each reload, the hard register number of the register used,
5776 or -1 if we did not need a register for this reload. */
5777 static int reload_spill_index[MAX_RELOADS];
5779 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5780 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5782 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5783 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5785 /* Subroutine of free_for_value_p, used to check a single register.
5786 START_REGNO is the starting regno of the full reload register
5787 (possibly comprising multiple hard registers) that we are considering. */
5789 static int
5790 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5791 enum reload_type type, rtx value, rtx out,
5792 int reloadnum, int ignore_address_reloads)
5794 int time1;
5795 /* Set if we see an input reload that must not share its reload register
5796 with any new earlyclobber, but might otherwise share the reload
5797 register with an output or input-output reload. */
5798 int check_earlyclobber = 0;
5799 int i;
5800 int copy = 0;
5802 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5803 return 0;
5805 if (out == const0_rtx)
5807 copy = 1;
5808 out = NULL_RTX;
5811 /* We use some pseudo 'time' value to check if the lifetimes of the
5812 new register use would overlap with the one of a previous reload
5813 that is not read-only or uses a different value.
5814 The 'time' used doesn't have to be linear in any shape or form, just
5815 monotonic.
5816 Some reload types use different 'buckets' for each operand.
5817 So there are MAX_RECOG_OPERANDS different time values for each
5818 such reload type.
5819 We compute TIME1 as the time when the register for the prospective
5820 new reload ceases to be live, and TIME2 for each existing
5821 reload as the time when that the reload register of that reload
5822 becomes live.
5823 Where there is little to be gained by exact lifetime calculations,
5824 we just make conservative assumptions, i.e. a longer lifetime;
5825 this is done in the 'default:' cases. */
5826 switch (type)
5828 case RELOAD_FOR_OTHER_ADDRESS:
5829 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5830 time1 = copy ? 0 : 1;
5831 break;
5832 case RELOAD_OTHER:
5833 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5834 break;
5835 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5836 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5837 respectively, to the time values for these, we get distinct time
5838 values. To get distinct time values for each operand, we have to
5839 multiply opnum by at least three. We round that up to four because
5840 multiply by four is often cheaper. */
5841 case RELOAD_FOR_INPADDR_ADDRESS:
5842 time1 = opnum * 4 + 2;
5843 break;
5844 case RELOAD_FOR_INPUT_ADDRESS:
5845 time1 = opnum * 4 + 3;
5846 break;
5847 case RELOAD_FOR_INPUT:
5848 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5849 executes (inclusive). */
5850 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5851 break;
5852 case RELOAD_FOR_OPADDR_ADDR:
5853 /* opnum * 4 + 4
5854 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5855 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5856 break;
5857 case RELOAD_FOR_OPERAND_ADDRESS:
5858 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5859 is executed. */
5860 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5861 break;
5862 case RELOAD_FOR_OUTADDR_ADDRESS:
5863 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5864 break;
5865 case RELOAD_FOR_OUTPUT_ADDRESS:
5866 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5867 break;
5868 default:
5869 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5872 for (i = 0; i < n_reloads; i++)
5874 rtx reg = rld[i].reg_rtx;
5875 if (reg && REG_P (reg)
5876 && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg)
5877 && i != reloadnum)
5879 rtx other_input = rld[i].in;
5881 /* If the other reload loads the same input value, that
5882 will not cause a conflict only if it's loading it into
5883 the same register. */
5884 if (true_regnum (reg) != start_regno)
5885 other_input = NULL_RTX;
5886 if (! other_input || ! rtx_equal_p (other_input, value)
5887 || rld[i].out || out)
5889 int time2;
5890 switch (rld[i].when_needed)
5892 case RELOAD_FOR_OTHER_ADDRESS:
5893 time2 = 0;
5894 break;
5895 case RELOAD_FOR_INPADDR_ADDRESS:
5896 /* find_reloads makes sure that a
5897 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5898 by at most one - the first -
5899 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5900 address reload is inherited, the address address reload
5901 goes away, so we can ignore this conflict. */
5902 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5903 && ignore_address_reloads
5904 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5905 Then the address address is still needed to store
5906 back the new address. */
5907 && ! rld[reloadnum].out)
5908 continue;
5909 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5910 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5911 reloads go away. */
5912 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5913 && ignore_address_reloads
5914 /* Unless we are reloading an auto_inc expression. */
5915 && ! rld[reloadnum].out)
5916 continue;
5917 time2 = rld[i].opnum * 4 + 2;
5918 break;
5919 case RELOAD_FOR_INPUT_ADDRESS:
5920 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5921 && ignore_address_reloads
5922 && ! rld[reloadnum].out)
5923 continue;
5924 time2 = rld[i].opnum * 4 + 3;
5925 break;
5926 case RELOAD_FOR_INPUT:
5927 time2 = rld[i].opnum * 4 + 4;
5928 check_earlyclobber = 1;
5929 break;
5930 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5931 == MAX_RECOG_OPERAND * 4 */
5932 case RELOAD_FOR_OPADDR_ADDR:
5933 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5934 && ignore_address_reloads
5935 && ! rld[reloadnum].out)
5936 continue;
5937 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5938 break;
5939 case RELOAD_FOR_OPERAND_ADDRESS:
5940 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5941 check_earlyclobber = 1;
5942 break;
5943 case RELOAD_FOR_INSN:
5944 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5945 break;
5946 case RELOAD_FOR_OUTPUT:
5947 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5948 instruction is executed. */
5949 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5950 break;
5951 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5952 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5953 value. */
5954 case RELOAD_FOR_OUTADDR_ADDRESS:
5955 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5956 && ignore_address_reloads
5957 && ! rld[reloadnum].out)
5958 continue;
5959 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5960 break;
5961 case RELOAD_FOR_OUTPUT_ADDRESS:
5962 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5963 break;
5964 case RELOAD_OTHER:
5965 /* If there is no conflict in the input part, handle this
5966 like an output reload. */
5967 if (! rld[i].in || rtx_equal_p (other_input, value))
5969 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5970 /* Earlyclobbered outputs must conflict with inputs. */
5971 if (earlyclobber_operand_p (rld[i].out))
5972 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5974 break;
5976 time2 = 1;
5977 /* RELOAD_OTHER might be live beyond instruction execution,
5978 but this is not obvious when we set time2 = 1. So check
5979 here if there might be a problem with the new reload
5980 clobbering the register used by the RELOAD_OTHER. */
5981 if (out)
5982 return 0;
5983 break;
5984 default:
5985 return 0;
5987 if ((time1 >= time2
5988 && (! rld[i].in || rld[i].out
5989 || ! rtx_equal_p (other_input, value)))
5990 || (out && rld[reloadnum].out_reg
5991 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5992 return 0;
5997 /* Earlyclobbered outputs must conflict with inputs. */
5998 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5999 return 0;
6001 return 1;
6004 /* Return 1 if the value in reload reg REGNO, as used by a reload
6005 needed for the part of the insn specified by OPNUM and TYPE,
6006 may be used to load VALUE into it.
6008 MODE is the mode in which the register is used, this is needed to
6009 determine how many hard regs to test.
6011 Other read-only reloads with the same value do not conflict
6012 unless OUT is nonzero and these other reloads have to live while
6013 output reloads live.
6014 If OUT is CONST0_RTX, this is a special case: it means that the
6015 test should not be for using register REGNO as reload register, but
6016 for copying from register REGNO into the reload register.
6018 RELOADNUM is the number of the reload we want to load this value for;
6019 a reload does not conflict with itself.
6021 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6022 reloads that load an address for the very reload we are considering.
6024 The caller has to make sure that there is no conflict with the return
6025 register. */
6027 static int
6028 free_for_value_p (int regno, machine_mode mode, int opnum,
6029 enum reload_type type, rtx value, rtx out, int reloadnum,
6030 int ignore_address_reloads)
6032 int nregs = hard_regno_nregs (regno, mode);
6033 while (nregs-- > 0)
6034 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6035 value, out, reloadnum,
6036 ignore_address_reloads))
6037 return 0;
6038 return 1;
6041 /* Return nonzero if the rtx X is invariant over the current function. */
6042 /* ??? Actually, the places where we use this expect exactly what is
6043 tested here, and not everything that is function invariant. In
6044 particular, the frame pointer and arg pointer are special cased;
6045 pic_offset_table_rtx is not, and we must not spill these things to
6046 memory. */
6049 function_invariant_p (const_rtx x)
6051 if (CONSTANT_P (x))
6052 return 1;
6053 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6054 return 1;
6055 if (GET_CODE (x) == PLUS
6056 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6057 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6058 return 1;
6059 return 0;
6062 /* Determine whether the reload reg X overlaps any rtx'es used for
6063 overriding inheritance. Return nonzero if so. */
6065 static int
6066 conflicts_with_override (rtx x)
6068 int i;
6069 for (i = 0; i < n_reloads; i++)
6070 if (reload_override_in[i]
6071 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6072 return 1;
6073 return 0;
6076 /* Give an error message saying we failed to find a reload for INSN,
6077 and clear out reload R. */
6078 static void
6079 failed_reload (rtx_insn *insn, int r)
6081 if (asm_noperands (PATTERN (insn)) < 0)
6082 /* It's the compiler's fault. */
6083 fatal_insn ("could not find a spill register", insn);
6085 /* It's the user's fault; the operand's mode and constraint
6086 don't match. Disable this reload so we don't crash in final. */
6087 error_for_asm (insn,
6088 "%<asm%> operand constraint incompatible with operand size");
6089 rld[r].in = 0;
6090 rld[r].out = 0;
6091 rld[r].reg_rtx = 0;
6092 rld[r].optional = 1;
6093 rld[r].secondary_p = 1;
6096 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6097 for reload R. If it's valid, get an rtx for it. Return nonzero if
6098 successful. */
6099 static int
6100 set_reload_reg (int i, int r)
6102 int regno;
6103 rtx reg = spill_reg_rtx[i];
6105 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6106 spill_reg_rtx[i] = reg
6107 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6109 regno = true_regnum (reg);
6111 /* Detect when the reload reg can't hold the reload mode.
6112 This used to be one `if', but Sequent compiler can't handle that. */
6113 if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
6115 machine_mode test_mode = VOIDmode;
6116 if (rld[r].in)
6117 test_mode = GET_MODE (rld[r].in);
6118 /* If rld[r].in has VOIDmode, it means we will load it
6119 in whatever mode the reload reg has: to wit, rld[r].mode.
6120 We have already tested that for validity. */
6121 /* Aside from that, we need to test that the expressions
6122 to reload from or into have modes which are valid for this
6123 reload register. Otherwise the reload insns would be invalid. */
6124 if (! (rld[r].in != 0 && test_mode != VOIDmode
6125 && !targetm.hard_regno_mode_ok (regno, test_mode)))
6126 if (! (rld[r].out != 0
6127 && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
6129 /* The reg is OK. */
6130 last_spill_reg = i;
6132 /* Mark as in use for this insn the reload regs we use
6133 for this. */
6134 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6135 rld[r].when_needed, rld[r].mode);
6137 rld[r].reg_rtx = reg;
6138 reload_spill_index[r] = spill_regs[i];
6139 return 1;
6142 return 0;
6145 /* Find a spill register to use as a reload register for reload R.
6146 LAST_RELOAD is nonzero if this is the last reload for the insn being
6147 processed.
6149 Set rld[R].reg_rtx to the register allocated.
6151 We return 1 if successful, or 0 if we couldn't find a spill reg and
6152 we didn't change anything. */
6154 static int
6155 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6156 int last_reload)
6158 int i, pass, count;
6160 /* If we put this reload ahead, thinking it is a group,
6161 then insist on finding a group. Otherwise we can grab a
6162 reg that some other reload needs.
6163 (That can happen when we have a 68000 DATA_OR_FP_REG
6164 which is a group of data regs or one fp reg.)
6165 We need not be so restrictive if there are no more reloads
6166 for this insn.
6168 ??? Really it would be nicer to have smarter handling
6169 for that kind of reg class, where a problem like this is normal.
6170 Perhaps those classes should be avoided for reloading
6171 by use of more alternatives. */
6173 int force_group = rld[r].nregs > 1 && ! last_reload;
6175 /* If we want a single register and haven't yet found one,
6176 take any reg in the right class and not in use.
6177 If we want a consecutive group, here is where we look for it.
6179 We use three passes so we can first look for reload regs to
6180 reuse, which are already in use for other reloads in this insn,
6181 and only then use additional registers which are not "bad", then
6182 finally any register.
6184 I think that maximizing reuse is needed to make sure we don't
6185 run out of reload regs. Suppose we have three reloads, and
6186 reloads A and B can share regs. These need two regs.
6187 Suppose A and B are given different regs.
6188 That leaves none for C. */
6189 for (pass = 0; pass < 3; pass++)
6191 /* I is the index in spill_regs.
6192 We advance it round-robin between insns to use all spill regs
6193 equally, so that inherited reloads have a chance
6194 of leapfrogging each other. */
6196 i = last_spill_reg;
6198 for (count = 0; count < n_spills; count++)
6200 int rclass = (int) rld[r].rclass;
6201 int regnum;
6203 i++;
6204 if (i >= n_spills)
6205 i -= n_spills;
6206 regnum = spill_regs[i];
6208 if ((reload_reg_free_p (regnum, rld[r].opnum,
6209 rld[r].when_needed)
6210 || (rld[r].in
6211 /* We check reload_reg_used to make sure we
6212 don't clobber the return register. */
6213 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6214 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6215 rld[r].when_needed, rld[r].in,
6216 rld[r].out, r, 1)))
6217 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6218 && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
6219 /* Look first for regs to share, then for unshared. But
6220 don't share regs used for inherited reloads; they are
6221 the ones we want to preserve. */
6222 && (pass
6223 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6224 regnum)
6225 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6226 regnum))))
6228 int nr = hard_regno_nregs (regnum, rld[r].mode);
6230 /* During the second pass we want to avoid reload registers
6231 which are "bad" for this reload. */
6232 if (pass == 1
6233 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6234 continue;
6236 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6237 (on 68000) got us two FP regs. If NR is 1,
6238 we would reject both of them. */
6239 if (force_group)
6240 nr = rld[r].nregs;
6241 /* If we need only one reg, we have already won. */
6242 if (nr == 1)
6244 /* But reject a single reg if we demand a group. */
6245 if (force_group)
6246 continue;
6247 break;
6249 /* Otherwise check that as many consecutive regs as we need
6250 are available here. */
6251 while (nr > 1)
6253 int regno = regnum + nr - 1;
6254 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6255 && spill_reg_order[regno] >= 0
6256 && reload_reg_free_p (regno, rld[r].opnum,
6257 rld[r].when_needed)))
6258 break;
6259 nr--;
6261 if (nr == 1)
6262 break;
6266 /* If we found something on the current pass, omit later passes. */
6267 if (count < n_spills)
6268 break;
6271 /* We should have found a spill register by now. */
6272 if (count >= n_spills)
6273 return 0;
6275 /* I is the index in SPILL_REG_RTX of the reload register we are to
6276 allocate. Get an rtx for it and find its register number. */
6278 return set_reload_reg (i, r);
6281 /* Initialize all the tables needed to allocate reload registers.
6282 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6283 is the array we use to restore the reg_rtx field for every reload. */
6285 static void
6286 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6288 int i;
6290 for (i = 0; i < n_reloads; i++)
6291 rld[i].reg_rtx = save_reload_reg_rtx[i];
6293 memset (reload_inherited, 0, MAX_RELOADS);
6294 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6295 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6297 CLEAR_HARD_REG_SET (reload_reg_used);
6298 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6299 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6300 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6301 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6302 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6304 CLEAR_HARD_REG_SET (reg_used_in_insn);
6306 HARD_REG_SET tmp;
6307 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6308 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6309 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6310 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6311 compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6312 compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6315 for (i = 0; i < reload_n_operands; i++)
6317 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6318 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6319 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6320 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6321 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6322 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6325 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6327 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6329 for (i = 0; i < n_reloads; i++)
6330 /* If we have already decided to use a certain register,
6331 don't use it in another way. */
6332 if (rld[i].reg_rtx)
6333 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6334 rld[i].when_needed, rld[i].mode);
6337 /* If X is not a subreg, return it unmodified. If it is a subreg,
6338 look up whether we made a replacement for the SUBREG_REG. Return
6339 either the replacement or the SUBREG_REG. */
6341 static rtx
6342 replaced_subreg (rtx x)
6344 if (GET_CODE (x) == SUBREG)
6345 return find_replacement (&SUBREG_REG (x));
6346 return x;
6349 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6350 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6351 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6352 otherwise it is NULL. */
6354 static poly_int64
6355 compute_reload_subreg_offset (machine_mode outermode,
6356 rtx subreg,
6357 machine_mode innermode)
6359 poly_int64 outer_offset;
6360 machine_mode middlemode;
6362 if (!subreg)
6363 return subreg_lowpart_offset (outermode, innermode);
6365 outer_offset = SUBREG_BYTE (subreg);
6366 middlemode = GET_MODE (SUBREG_REG (subreg));
6368 /* If SUBREG is paradoxical then return the normal lowpart offset
6369 for OUTERMODE and INNERMODE. Our caller has already checked
6370 that OUTERMODE fits in INNERMODE. */
6371 if (paradoxical_subreg_p (outermode, middlemode))
6372 return subreg_lowpart_offset (outermode, innermode);
6374 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6375 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6376 return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6379 /* Assign hard reg targets for the pseudo-registers we must reload
6380 into hard regs for this insn.
6381 Also output the instructions to copy them in and out of the hard regs.
6383 For machines with register classes, we are responsible for
6384 finding a reload reg in the proper class. */
6386 static void
6387 choose_reload_regs (struct insn_chain *chain)
6389 rtx_insn *insn = chain->insn;
6390 int i, j;
6391 unsigned int max_group_size = 1;
6392 enum reg_class group_class = NO_REGS;
6393 int pass, win, inheritance;
6395 rtx save_reload_reg_rtx[MAX_RELOADS];
6397 /* In order to be certain of getting the registers we need,
6398 we must sort the reloads into order of increasing register class.
6399 Then our grabbing of reload registers will parallel the process
6400 that provided the reload registers.
6402 Also note whether any of the reloads wants a consecutive group of regs.
6403 If so, record the maximum size of the group desired and what
6404 register class contains all the groups needed by this insn. */
6406 for (j = 0; j < n_reloads; j++)
6408 reload_order[j] = j;
6409 if (rld[j].reg_rtx != NULL_RTX)
6411 gcc_assert (REG_P (rld[j].reg_rtx)
6412 && HARD_REGISTER_P (rld[j].reg_rtx));
6413 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6415 else
6416 reload_spill_index[j] = -1;
6418 if (rld[j].nregs > 1)
6420 max_group_size = MAX (rld[j].nregs, max_group_size);
6421 group_class
6422 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6425 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6428 if (n_reloads > 1)
6429 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6431 /* If -O, try first with inheritance, then turning it off.
6432 If not -O, don't do inheritance.
6433 Using inheritance when not optimizing leads to paradoxes
6434 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6435 because one side of the comparison might be inherited. */
6436 win = 0;
6437 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6439 choose_reload_regs_init (chain, save_reload_reg_rtx);
6441 /* Process the reloads in order of preference just found.
6442 Beyond this point, subregs can be found in reload_reg_rtx.
6444 This used to look for an existing reloaded home for all of the
6445 reloads, and only then perform any new reloads. But that could lose
6446 if the reloads were done out of reg-class order because a later
6447 reload with a looser constraint might have an old home in a register
6448 needed by an earlier reload with a tighter constraint.
6450 To solve this, we make two passes over the reloads, in the order
6451 described above. In the first pass we try to inherit a reload
6452 from a previous insn. If there is a later reload that needs a
6453 class that is a proper subset of the class being processed, we must
6454 also allocate a spill register during the first pass.
6456 Then make a second pass over the reloads to allocate any reloads
6457 that haven't been given registers yet. */
6459 for (j = 0; j < n_reloads; j++)
6461 int r = reload_order[j];
6462 rtx search_equiv = NULL_RTX;
6464 /* Ignore reloads that got marked inoperative. */
6465 if (rld[r].out == 0 && rld[r].in == 0
6466 && ! rld[r].secondary_p)
6467 continue;
6469 /* If find_reloads chose to use reload_in or reload_out as a reload
6470 register, we don't need to chose one. Otherwise, try even if it
6471 found one since we might save an insn if we find the value lying
6472 around.
6473 Try also when reload_in is a pseudo without a hard reg. */
6474 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6475 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6476 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6477 && !MEM_P (rld[r].in)
6478 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6479 continue;
6481 #if 0 /* No longer needed for correct operation.
6482 It might give better code, or might not; worth an experiment? */
6483 /* If this is an optional reload, we can't inherit from earlier insns
6484 until we are sure that any non-optional reloads have been allocated.
6485 The following code takes advantage of the fact that optional reloads
6486 are at the end of reload_order. */
6487 if (rld[r].optional != 0)
6488 for (i = 0; i < j; i++)
6489 if ((rld[reload_order[i]].out != 0
6490 || rld[reload_order[i]].in != 0
6491 || rld[reload_order[i]].secondary_p)
6492 && ! rld[reload_order[i]].optional
6493 && rld[reload_order[i]].reg_rtx == 0)
6494 allocate_reload_reg (chain, reload_order[i], 0);
6495 #endif
6497 /* First see if this pseudo is already available as reloaded
6498 for a previous insn. We cannot try to inherit for reloads
6499 that are smaller than the maximum number of registers needed
6500 for groups unless the register we would allocate cannot be used
6501 for the groups.
6503 We could check here to see if this is a secondary reload for
6504 an object that is already in a register of the desired class.
6505 This would avoid the need for the secondary reload register.
6506 But this is complex because we can't easily determine what
6507 objects might want to be loaded via this reload. So let a
6508 register be allocated here. In `emit_reload_insns' we suppress
6509 one of the loads in the case described above. */
6511 if (inheritance)
6513 poly_int64 byte = 0;
6514 int regno = -1;
6515 machine_mode mode = VOIDmode;
6516 rtx subreg = NULL_RTX;
6518 if (rld[r].in == 0)
6520 else if (REG_P (rld[r].in))
6522 regno = REGNO (rld[r].in);
6523 mode = GET_MODE (rld[r].in);
6525 else if (REG_P (rld[r].in_reg))
6527 regno = REGNO (rld[r].in_reg);
6528 mode = GET_MODE (rld[r].in_reg);
6530 else if (GET_CODE (rld[r].in_reg) == SUBREG
6531 && REG_P (SUBREG_REG (rld[r].in_reg)))
6533 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6534 if (regno < FIRST_PSEUDO_REGISTER)
6535 regno = subreg_regno (rld[r].in_reg);
6536 else
6538 subreg = rld[r].in_reg;
6539 byte = SUBREG_BYTE (subreg);
6541 mode = GET_MODE (rld[r].in_reg);
6543 #if AUTO_INC_DEC
6544 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6545 && REG_P (XEXP (rld[r].in_reg, 0)))
6547 regno = REGNO (XEXP (rld[r].in_reg, 0));
6548 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6549 rld[r].out = rld[r].in;
6551 #endif
6552 #if 0
6553 /* This won't work, since REGNO can be a pseudo reg number.
6554 Also, it takes much more hair to keep track of all the things
6555 that can invalidate an inherited reload of part of a pseudoreg. */
6556 else if (GET_CODE (rld[r].in) == SUBREG
6557 && REG_P (SUBREG_REG (rld[r].in)))
6558 regno = subreg_regno (rld[r].in);
6559 #endif
6561 if (regno >= 0
6562 && reg_last_reload_reg[regno] != 0
6563 && (known_ge
6564 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
6565 GET_MODE_SIZE (mode) + byte))
6566 /* Verify that the register it's in can be used in
6567 mode MODE. */
6568 && (REG_CAN_CHANGE_MODE_P
6569 (REGNO (reg_last_reload_reg[regno]),
6570 GET_MODE (reg_last_reload_reg[regno]),
6571 mode)))
6573 enum reg_class rclass = rld[r].rclass, last_class;
6574 rtx last_reg = reg_last_reload_reg[regno];
6576 i = REGNO (last_reg);
6577 byte = compute_reload_subreg_offset (mode,
6578 subreg,
6579 GET_MODE (last_reg));
6580 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6581 last_class = REGNO_REG_CLASS (i);
6583 if (reg_reloaded_contents[i] == regno
6584 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6585 && targetm.hard_regno_mode_ok (i, rld[r].mode)
6586 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6587 /* Even if we can't use this register as a reload
6588 register, we might use it for reload_override_in,
6589 if copying it to the desired class is cheap
6590 enough. */
6591 || ((register_move_cost (mode, last_class, rclass)
6592 < memory_move_cost (mode, rclass, true))
6593 && (secondary_reload_class (1, rclass, mode,
6594 last_reg)
6595 == NO_REGS)
6596 && !(targetm.secondary_memory_needed
6597 (mode, last_class, rclass))))
6598 && (rld[r].nregs == max_group_size
6599 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6601 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6602 rld[r].when_needed, rld[r].in,
6603 const0_rtx, r, 1))
6605 /* If a group is needed, verify that all the subsequent
6606 registers still have their values intact. */
6607 int nr = hard_regno_nregs (i, rld[r].mode);
6608 int k;
6610 for (k = 1; k < nr; k++)
6611 if (reg_reloaded_contents[i + k] != regno
6612 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6613 break;
6615 if (k == nr)
6617 int i1;
6618 int bad_for_class;
6620 last_reg = (GET_MODE (last_reg) == mode
6621 ? last_reg : gen_rtx_REG (mode, i));
6623 bad_for_class = 0;
6624 for (k = 0; k < nr; k++)
6625 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6626 i+k);
6628 /* We found a register that contains the
6629 value we need. If this register is the
6630 same as an `earlyclobber' operand of the
6631 current insn, just mark it as a place to
6632 reload from since we can't use it as the
6633 reload register itself. */
6635 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6636 if (reg_overlap_mentioned_for_reload_p
6637 (reg_last_reload_reg[regno],
6638 reload_earlyclobbers[i1]))
6639 break;
6641 if (i1 != n_earlyclobbers
6642 || ! (free_for_value_p (i, rld[r].mode,
6643 rld[r].opnum,
6644 rld[r].when_needed, rld[r].in,
6645 rld[r].out, r, 1))
6646 /* Don't use it if we'd clobber a pseudo reg. */
6647 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6648 && rld[r].out
6649 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6650 /* Don't clobber the frame pointer. */
6651 || (i == HARD_FRAME_POINTER_REGNUM
6652 && frame_pointer_needed
6653 && rld[r].out)
6654 /* Don't really use the inherited spill reg
6655 if we need it wider than we've got it. */
6656 || paradoxical_subreg_p (rld[r].mode, mode)
6657 || bad_for_class
6659 /* If find_reloads chose reload_out as reload
6660 register, stay with it - that leaves the
6661 inherited register for subsequent reloads. */
6662 || (rld[r].out && rld[r].reg_rtx
6663 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6665 if (! rld[r].optional)
6667 reload_override_in[r] = last_reg;
6668 reload_inheritance_insn[r]
6669 = reg_reloaded_insn[i];
6672 else
6674 int k;
6675 /* We can use this as a reload reg. */
6676 /* Mark the register as in use for this part of
6677 the insn. */
6678 mark_reload_reg_in_use (i,
6679 rld[r].opnum,
6680 rld[r].when_needed,
6681 rld[r].mode);
6682 rld[r].reg_rtx = last_reg;
6683 reload_inherited[r] = 1;
6684 reload_inheritance_insn[r]
6685 = reg_reloaded_insn[i];
6686 reload_spill_index[r] = i;
6687 for (k = 0; k < nr; k++)
6688 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6689 i + k);
6696 /* Here's another way to see if the value is already lying around. */
6697 if (inheritance
6698 && rld[r].in != 0
6699 && ! reload_inherited[r]
6700 && rld[r].out == 0
6701 && (CONSTANT_P (rld[r].in)
6702 || GET_CODE (rld[r].in) == PLUS
6703 || REG_P (rld[r].in)
6704 || MEM_P (rld[r].in))
6705 && (rld[r].nregs == max_group_size
6706 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6707 search_equiv = rld[r].in;
6709 if (search_equiv)
6711 rtx equiv
6712 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6713 -1, NULL, 0, rld[r].mode);
6714 int regno = 0;
6716 if (equiv != 0)
6718 if (REG_P (equiv))
6719 regno = REGNO (equiv);
6720 else
6722 /* This must be a SUBREG of a hard register.
6723 Make a new REG since this might be used in an
6724 address and not all machines support SUBREGs
6725 there. */
6726 gcc_assert (GET_CODE (equiv) == SUBREG);
6727 regno = subreg_regno (equiv);
6728 equiv = gen_rtx_REG (rld[r].mode, regno);
6729 /* If we choose EQUIV as the reload register, but the
6730 loop below decides to cancel the inheritance, we'll
6731 end up reloading EQUIV in rld[r].mode, not the mode
6732 it had originally. That isn't safe when EQUIV isn't
6733 available as a spill register since its value might
6734 still be live at this point. */
6735 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6736 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6737 equiv = 0;
6741 /* If we found a spill reg, reject it unless it is free
6742 and of the desired class. */
6743 if (equiv != 0)
6745 int regs_used = 0;
6746 int bad_for_class = 0;
6747 int max_regno = regno + rld[r].nregs;
6749 for (i = regno; i < max_regno; i++)
6751 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6753 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6757 if ((regs_used
6758 && ! free_for_value_p (regno, rld[r].mode,
6759 rld[r].opnum, rld[r].when_needed,
6760 rld[r].in, rld[r].out, r, 1))
6761 || bad_for_class)
6762 equiv = 0;
6765 if (equiv != 0
6766 && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
6767 equiv = 0;
6769 /* We found a register that contains the value we need.
6770 If this register is the same as an `earlyclobber' operand
6771 of the current insn, just mark it as a place to reload from
6772 since we can't use it as the reload register itself. */
6774 if (equiv != 0)
6775 for (i = 0; i < n_earlyclobbers; i++)
6776 if (reg_overlap_mentioned_for_reload_p (equiv,
6777 reload_earlyclobbers[i]))
6779 if (! rld[r].optional)
6780 reload_override_in[r] = equiv;
6781 equiv = 0;
6782 break;
6785 /* If the equiv register we have found is explicitly clobbered
6786 in the current insn, it depends on the reload type if we
6787 can use it, use it for reload_override_in, or not at all.
6788 In particular, we then can't use EQUIV for a
6789 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6791 if (equiv != 0)
6793 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6794 switch (rld[r].when_needed)
6796 case RELOAD_FOR_OTHER_ADDRESS:
6797 case RELOAD_FOR_INPADDR_ADDRESS:
6798 case RELOAD_FOR_INPUT_ADDRESS:
6799 case RELOAD_FOR_OPADDR_ADDR:
6800 break;
6801 case RELOAD_OTHER:
6802 case RELOAD_FOR_INPUT:
6803 case RELOAD_FOR_OPERAND_ADDRESS:
6804 if (! rld[r].optional)
6805 reload_override_in[r] = equiv;
6806 /* Fall through. */
6807 default:
6808 equiv = 0;
6809 break;
6811 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6812 switch (rld[r].when_needed)
6814 case RELOAD_FOR_OTHER_ADDRESS:
6815 case RELOAD_FOR_INPADDR_ADDRESS:
6816 case RELOAD_FOR_INPUT_ADDRESS:
6817 case RELOAD_FOR_OPADDR_ADDR:
6818 case RELOAD_FOR_OPERAND_ADDRESS:
6819 case RELOAD_FOR_INPUT:
6820 break;
6821 case RELOAD_OTHER:
6822 if (! rld[r].optional)
6823 reload_override_in[r] = equiv;
6824 /* Fall through. */
6825 default:
6826 equiv = 0;
6827 break;
6831 /* If we found an equivalent reg, say no code need be generated
6832 to load it, and use it as our reload reg. */
6833 if (equiv != 0
6834 && (regno != HARD_FRAME_POINTER_REGNUM
6835 || !frame_pointer_needed))
6837 int nr = hard_regno_nregs (regno, rld[r].mode);
6838 int k;
6839 rld[r].reg_rtx = equiv;
6840 reload_spill_index[r] = regno;
6841 reload_inherited[r] = 1;
6843 /* If reg_reloaded_valid is not set for this register,
6844 there might be a stale spill_reg_store lying around.
6845 We must clear it, since otherwise emit_reload_insns
6846 might delete the store. */
6847 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6848 spill_reg_store[regno] = NULL;
6849 /* If any of the hard registers in EQUIV are spill
6850 registers, mark them as in use for this insn. */
6851 for (k = 0; k < nr; k++)
6853 i = spill_reg_order[regno + k];
6854 if (i >= 0)
6856 mark_reload_reg_in_use (regno, rld[r].opnum,
6857 rld[r].when_needed,
6858 rld[r].mode);
6859 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6860 regno + k);
6866 /* If we found a register to use already, or if this is an optional
6867 reload, we are done. */
6868 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6869 continue;
6871 #if 0
6872 /* No longer needed for correct operation. Might or might
6873 not give better code on the average. Want to experiment? */
6875 /* See if there is a later reload that has a class different from our
6876 class that intersects our class or that requires less register
6877 than our reload. If so, we must allocate a register to this
6878 reload now, since that reload might inherit a previous reload
6879 and take the only available register in our class. Don't do this
6880 for optional reloads since they will force all previous reloads
6881 to be allocated. Also don't do this for reloads that have been
6882 turned off. */
6884 for (i = j + 1; i < n_reloads; i++)
6886 int s = reload_order[i];
6888 if ((rld[s].in == 0 && rld[s].out == 0
6889 && ! rld[s].secondary_p)
6890 || rld[s].optional)
6891 continue;
6893 if ((rld[s].rclass != rld[r].rclass
6894 && reg_classes_intersect_p (rld[r].rclass,
6895 rld[s].rclass))
6896 || rld[s].nregs < rld[r].nregs)
6897 break;
6900 if (i == n_reloads)
6901 continue;
6903 allocate_reload_reg (chain, r, j == n_reloads - 1);
6904 #endif
6907 /* Now allocate reload registers for anything non-optional that
6908 didn't get one yet. */
6909 for (j = 0; j < n_reloads; j++)
6911 int r = reload_order[j];
6913 /* Ignore reloads that got marked inoperative. */
6914 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6915 continue;
6917 /* Skip reloads that already have a register allocated or are
6918 optional. */
6919 if (rld[r].reg_rtx != 0 || rld[r].optional)
6920 continue;
6922 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6923 break;
6926 /* If that loop got all the way, we have won. */
6927 if (j == n_reloads)
6929 win = 1;
6930 break;
6933 /* Loop around and try without any inheritance. */
6936 if (! win)
6938 /* First undo everything done by the failed attempt
6939 to allocate with inheritance. */
6940 choose_reload_regs_init (chain, save_reload_reg_rtx);
6942 /* Some sanity tests to verify that the reloads found in the first
6943 pass are identical to the ones we have now. */
6944 gcc_assert (chain->n_reloads == n_reloads);
6946 for (i = 0; i < n_reloads; i++)
6948 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6949 continue;
6950 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6951 for (j = 0; j < n_spills; j++)
6952 if (spill_regs[j] == chain->rld[i].regno)
6953 if (! set_reload_reg (j, i))
6954 failed_reload (chain->insn, i);
6958 /* If we thought we could inherit a reload, because it seemed that
6959 nothing else wanted the same reload register earlier in the insn,
6960 verify that assumption, now that all reloads have been assigned.
6961 Likewise for reloads where reload_override_in has been set. */
6963 /* If doing expensive optimizations, do one preliminary pass that doesn't
6964 cancel any inheritance, but removes reloads that have been needed only
6965 for reloads that we know can be inherited. */
6966 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6968 for (j = 0; j < n_reloads; j++)
6970 int r = reload_order[j];
6971 rtx check_reg;
6972 rtx tem;
6973 if (reload_inherited[r] && rld[r].reg_rtx)
6974 check_reg = rld[r].reg_rtx;
6975 else if (reload_override_in[r]
6976 && (REG_P (reload_override_in[r])
6977 || GET_CODE (reload_override_in[r]) == SUBREG))
6978 check_reg = reload_override_in[r];
6979 else
6980 continue;
6981 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6982 rld[r].opnum, rld[r].when_needed, rld[r].in,
6983 (reload_inherited[r]
6984 ? rld[r].out : const0_rtx),
6985 r, 1))
6987 if (pass)
6988 continue;
6989 reload_inherited[r] = 0;
6990 reload_override_in[r] = 0;
6992 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6993 reload_override_in, then we do not need its related
6994 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6995 likewise for other reload types.
6996 We handle this by removing a reload when its only replacement
6997 is mentioned in reload_in of the reload we are going to inherit.
6998 A special case are auto_inc expressions; even if the input is
6999 inherited, we still need the address for the output. We can
7000 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7001 If we succeeded removing some reload and we are doing a preliminary
7002 pass just to remove such reloads, make another pass, since the
7003 removal of one reload might allow us to inherit another one. */
7004 else if (rld[r].in
7005 && rld[r].out != rld[r].in
7006 && remove_address_replacements (rld[r].in))
7008 if (pass)
7009 pass = 2;
7011 /* If we needed a memory location for the reload, we also have to
7012 remove its related reloads. */
7013 else if (rld[r].in
7014 && rld[r].out != rld[r].in
7015 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7016 && REGNO (tem) < FIRST_PSEUDO_REGISTER
7017 && (targetm.secondary_memory_needed
7018 (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)),
7019 rld[r].rclass))
7020 && remove_address_replacements
7021 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7022 rld[r].when_needed)))
7024 if (pass)
7025 pass = 2;
7030 /* Now that reload_override_in is known valid,
7031 actually override reload_in. */
7032 for (j = 0; j < n_reloads; j++)
7033 if (reload_override_in[j])
7034 rld[j].in = reload_override_in[j];
7036 /* If this reload won't be done because it has been canceled or is
7037 optional and not inherited, clear reload_reg_rtx so other
7038 routines (such as subst_reloads) don't get confused. */
7039 for (j = 0; j < n_reloads; j++)
7040 if (rld[j].reg_rtx != 0
7041 && ((rld[j].optional && ! reload_inherited[j])
7042 || (rld[j].in == 0 && rld[j].out == 0
7043 && ! rld[j].secondary_p)))
7045 int regno = true_regnum (rld[j].reg_rtx);
7047 if (spill_reg_order[regno] >= 0)
7048 clear_reload_reg_in_use (regno, rld[j].opnum,
7049 rld[j].when_needed, rld[j].mode);
7050 rld[j].reg_rtx = 0;
7051 reload_spill_index[j] = -1;
7054 /* Record which pseudos and which spill regs have output reloads. */
7055 for (j = 0; j < n_reloads; j++)
7057 int r = reload_order[j];
7059 i = reload_spill_index[r];
7061 /* I is nonneg if this reload uses a register.
7062 If rld[r].reg_rtx is 0, this is an optional reload
7063 that we opted to ignore. */
7064 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7065 && rld[r].reg_rtx != 0)
7067 int nregno = REGNO (rld[r].out_reg);
7068 int nr = 1;
7070 if (nregno < FIRST_PSEUDO_REGISTER)
7071 nr = hard_regno_nregs (nregno, rld[r].mode);
7073 while (--nr >= 0)
7074 SET_REGNO_REG_SET (&reg_has_output_reload,
7075 nregno + nr);
7077 if (i >= 0)
7078 add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7080 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7081 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7082 || rld[r].when_needed == RELOAD_FOR_INSN);
7087 /* Deallocate the reload register for reload R. This is called from
7088 remove_address_replacements. */
7090 void
7091 deallocate_reload_reg (int r)
7093 int regno;
7095 if (! rld[r].reg_rtx)
7096 return;
7097 regno = true_regnum (rld[r].reg_rtx);
7098 rld[r].reg_rtx = 0;
7099 if (spill_reg_order[regno] >= 0)
7100 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7101 rld[r].mode);
7102 reload_spill_index[r] = -1;
7105 /* These arrays are filled by emit_reload_insns and its subroutines. */
7106 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7107 static rtx_insn *other_input_address_reload_insns = 0;
7108 static rtx_insn *other_input_reload_insns = 0;
7109 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7110 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7111 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7112 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7113 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7114 static rtx_insn *operand_reload_insns = 0;
7115 static rtx_insn *other_operand_reload_insns = 0;
7116 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7118 /* Values to be put in spill_reg_store are put here first. Instructions
7119 must only be placed here if the associated reload register reaches
7120 the end of the instruction's reload sequence. */
7121 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7122 static HARD_REG_SET reg_reloaded_died;
7124 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7125 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7126 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7127 adjusted register, and return true. Otherwise, return false. */
7128 static bool
7129 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7130 enum reg_class new_class,
7131 machine_mode new_mode)
7134 rtx reg;
7136 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7138 unsigned regno = REGNO (reg);
7140 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7141 continue;
7142 if (GET_MODE (reg) != new_mode)
7144 if (!targetm.hard_regno_mode_ok (regno, new_mode))
7145 continue;
7146 if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg))
7147 continue;
7148 reg = reload_adjust_reg_for_mode (reg, new_mode);
7150 *reload_reg = reg;
7151 return true;
7153 return false;
7156 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7157 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7158 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7159 adjusted register, and return true. Otherwise, return false. */
7160 static bool
7161 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7162 enum insn_code icode)
7165 enum reg_class new_class = scratch_reload_class (icode);
7166 machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7168 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7169 new_class, new_mode);
7172 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7173 has the number J. OLD contains the value to be used as input. */
7175 static void
7176 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7177 rtx old, int j)
7179 rtx_insn *insn = chain->insn;
7180 rtx reloadreg;
7181 rtx oldequiv_reg = 0;
7182 rtx oldequiv = 0;
7183 int special = 0;
7184 machine_mode mode;
7185 rtx_insn **where;
7187 /* delete_output_reload is only invoked properly if old contains
7188 the original pseudo register. Since this is replaced with a
7189 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7190 find the pseudo in RELOAD_IN_REG. This is also used to
7191 determine whether a secondary reload is needed. */
7192 if (reload_override_in[j]
7193 && (REG_P (rl->in_reg)
7194 || (GET_CODE (rl->in_reg) == SUBREG
7195 && REG_P (SUBREG_REG (rl->in_reg)))))
7197 oldequiv = old;
7198 old = rl->in_reg;
7200 if (oldequiv == 0)
7201 oldequiv = old;
7202 else if (REG_P (oldequiv))
7203 oldequiv_reg = oldequiv;
7204 else if (GET_CODE (oldequiv) == SUBREG)
7205 oldequiv_reg = SUBREG_REG (oldequiv);
7207 reloadreg = reload_reg_rtx_for_input[j];
7208 mode = GET_MODE (reloadreg);
7210 /* If we are reloading from a register that was recently stored in
7211 with an output-reload, see if we can prove there was
7212 actually no need to store the old value in it. */
7214 if (optimize && REG_P (oldequiv)
7215 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7216 && spill_reg_store[REGNO (oldequiv)]
7217 && REG_P (old)
7218 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7219 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7220 rl->out_reg)))
7221 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7223 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7224 OLDEQUIV. */
7226 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7227 oldequiv = SUBREG_REG (oldequiv);
7228 if (GET_MODE (oldequiv) != VOIDmode
7229 && mode != GET_MODE (oldequiv))
7230 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7232 /* Switch to the right place to emit the reload insns. */
7233 switch (rl->when_needed)
7235 case RELOAD_OTHER:
7236 where = &other_input_reload_insns;
7237 break;
7238 case RELOAD_FOR_INPUT:
7239 where = &input_reload_insns[rl->opnum];
7240 break;
7241 case RELOAD_FOR_INPUT_ADDRESS:
7242 where = &input_address_reload_insns[rl->opnum];
7243 break;
7244 case RELOAD_FOR_INPADDR_ADDRESS:
7245 where = &inpaddr_address_reload_insns[rl->opnum];
7246 break;
7247 case RELOAD_FOR_OUTPUT_ADDRESS:
7248 where = &output_address_reload_insns[rl->opnum];
7249 break;
7250 case RELOAD_FOR_OUTADDR_ADDRESS:
7251 where = &outaddr_address_reload_insns[rl->opnum];
7252 break;
7253 case RELOAD_FOR_OPERAND_ADDRESS:
7254 where = &operand_reload_insns;
7255 break;
7256 case RELOAD_FOR_OPADDR_ADDR:
7257 where = &other_operand_reload_insns;
7258 break;
7259 case RELOAD_FOR_OTHER_ADDRESS:
7260 where = &other_input_address_reload_insns;
7261 break;
7262 default:
7263 gcc_unreachable ();
7266 push_to_sequence (*where);
7268 /* Auto-increment addresses must be reloaded in a special way. */
7269 if (rl->out && ! rl->out_reg)
7271 /* We are not going to bother supporting the case where a
7272 incremented register can't be copied directly from
7273 OLDEQUIV since this seems highly unlikely. */
7274 gcc_assert (rl->secondary_in_reload < 0);
7276 if (reload_inherited[j])
7277 oldequiv = reloadreg;
7279 old = XEXP (rl->in_reg, 0);
7281 /* Prevent normal processing of this reload. */
7282 special = 1;
7283 /* Output a special code sequence for this case. */
7284 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7287 /* If we are reloading a pseudo-register that was set by the previous
7288 insn, see if we can get rid of that pseudo-register entirely
7289 by redirecting the previous insn into our reload register. */
7291 else if (optimize && REG_P (old)
7292 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7293 && dead_or_set_p (insn, old)
7294 /* This is unsafe if some other reload
7295 uses the same reg first. */
7296 && ! conflicts_with_override (reloadreg)
7297 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7298 rl->when_needed, old, rl->out, j, 0))
7300 rtx_insn *temp = PREV_INSN (insn);
7301 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7302 temp = PREV_INSN (temp);
7303 if (temp
7304 && NONJUMP_INSN_P (temp)
7305 && GET_CODE (PATTERN (temp)) == SET
7306 && SET_DEST (PATTERN (temp)) == old
7307 /* Make sure we can access insn_operand_constraint. */
7308 && asm_noperands (PATTERN (temp)) < 0
7309 /* This is unsafe if operand occurs more than once in current
7310 insn. Perhaps some occurrences aren't reloaded. */
7311 && count_occurrences (PATTERN (insn), old, 0) == 1)
7313 rtx old = SET_DEST (PATTERN (temp));
7314 /* Store into the reload register instead of the pseudo. */
7315 SET_DEST (PATTERN (temp)) = reloadreg;
7317 /* Verify that resulting insn is valid.
7319 Note that we have replaced the destination of TEMP with
7320 RELOADREG. If TEMP references RELOADREG within an
7321 autoincrement addressing mode, then the resulting insn
7322 is ill-formed and we must reject this optimization. */
7323 extract_insn (temp);
7324 if (constrain_operands (1, get_enabled_alternatives (temp))
7325 && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7327 /* If the previous insn is an output reload, the source is
7328 a reload register, and its spill_reg_store entry will
7329 contain the previous destination. This is now
7330 invalid. */
7331 if (REG_P (SET_SRC (PATTERN (temp)))
7332 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7334 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7335 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7338 /* If these are the only uses of the pseudo reg,
7339 pretend for GDB it lives in the reload reg we used. */
7340 if (REG_N_DEATHS (REGNO (old)) == 1
7341 && REG_N_SETS (REGNO (old)) == 1)
7343 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7344 if (ira_conflicts_p)
7345 /* Inform IRA about the change. */
7346 ira_mark_allocation_change (REGNO (old));
7347 alter_reg (REGNO (old), -1, false);
7349 special = 1;
7351 /* Adjust any debug insns between temp and insn. */
7352 while ((temp = NEXT_INSN (temp)) != insn)
7353 if (DEBUG_BIND_INSN_P (temp))
7354 INSN_VAR_LOCATION_LOC (temp)
7355 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
7356 old, reloadreg);
7357 else
7358 gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
7360 else
7362 SET_DEST (PATTERN (temp)) = old;
7367 /* We can't do that, so output an insn to load RELOADREG. */
7369 /* If we have a secondary reload, pick up the secondary register
7370 and icode, if any. If OLDEQUIV and OLD are different or
7371 if this is an in-out reload, recompute whether or not we
7372 still need a secondary register and what the icode should
7373 be. If we still need a secondary register and the class or
7374 icode is different, go back to reloading from OLD if using
7375 OLDEQUIV means that we got the wrong type of register. We
7376 cannot have different class or icode due to an in-out reload
7377 because we don't make such reloads when both the input and
7378 output need secondary reload registers. */
7380 if (! special && rl->secondary_in_reload >= 0)
7382 rtx second_reload_reg = 0;
7383 rtx third_reload_reg = 0;
7384 int secondary_reload = rl->secondary_in_reload;
7385 rtx real_oldequiv = oldequiv;
7386 rtx real_old = old;
7387 rtx tmp;
7388 enum insn_code icode;
7389 enum insn_code tertiary_icode = CODE_FOR_nothing;
7391 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7392 and similarly for OLD.
7393 See comments in get_secondary_reload in reload.c. */
7394 /* If it is a pseudo that cannot be replaced with its
7395 equivalent MEM, we must fall back to reload_in, which
7396 will have all the necessary substitutions registered.
7397 Likewise for a pseudo that can't be replaced with its
7398 equivalent constant.
7400 Take extra care for subregs of such pseudos. Note that
7401 we cannot use reg_equiv_mem in this case because it is
7402 not in the right mode. */
7404 tmp = oldequiv;
7405 if (GET_CODE (tmp) == SUBREG)
7406 tmp = SUBREG_REG (tmp);
7407 if (REG_P (tmp)
7408 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7409 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7410 || reg_equiv_constant (REGNO (tmp)) != 0))
7412 if (! reg_equiv_mem (REGNO (tmp))
7413 || num_not_at_initial_offset
7414 || GET_CODE (oldequiv) == SUBREG)
7415 real_oldequiv = rl->in;
7416 else
7417 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7420 tmp = old;
7421 if (GET_CODE (tmp) == SUBREG)
7422 tmp = SUBREG_REG (tmp);
7423 if (REG_P (tmp)
7424 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7425 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7426 || reg_equiv_constant (REGNO (tmp)) != 0))
7428 if (! reg_equiv_mem (REGNO (tmp))
7429 || num_not_at_initial_offset
7430 || GET_CODE (old) == SUBREG)
7431 real_old = rl->in;
7432 else
7433 real_old = reg_equiv_mem (REGNO (tmp));
7436 second_reload_reg = rld[secondary_reload].reg_rtx;
7437 if (rld[secondary_reload].secondary_in_reload >= 0)
7439 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7441 third_reload_reg = rld[tertiary_reload].reg_rtx;
7442 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7443 /* We'd have to add more code for quartary reloads. */
7444 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7446 icode = rl->secondary_in_icode;
7448 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7449 || (rl->in != 0 && rl->out != 0))
7451 secondary_reload_info sri, sri2;
7452 enum reg_class new_class, new_t_class;
7454 sri.icode = CODE_FOR_nothing;
7455 sri.prev_sri = NULL;
7456 new_class
7457 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7458 rl->rclass, mode,
7459 &sri);
7461 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7462 second_reload_reg = 0;
7463 else if (new_class == NO_REGS)
7465 if (reload_adjust_reg_for_icode (&second_reload_reg,
7466 third_reload_reg,
7467 (enum insn_code) sri.icode))
7469 icode = (enum insn_code) sri.icode;
7470 third_reload_reg = 0;
7472 else
7474 oldequiv = old;
7475 real_oldequiv = real_old;
7478 else if (sri.icode != CODE_FOR_nothing)
7479 /* We currently lack a way to express this in reloads. */
7480 gcc_unreachable ();
7481 else
7483 sri2.icode = CODE_FOR_nothing;
7484 sri2.prev_sri = &sri;
7485 new_t_class
7486 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7487 new_class, mode,
7488 &sri);
7489 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7491 if (reload_adjust_reg_for_temp (&second_reload_reg,
7492 third_reload_reg,
7493 new_class, mode))
7495 third_reload_reg = 0;
7496 tertiary_icode = (enum insn_code) sri2.icode;
7498 else
7500 oldequiv = old;
7501 real_oldequiv = real_old;
7504 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7506 rtx intermediate = second_reload_reg;
7508 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7509 new_class, mode)
7510 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7511 ((enum insn_code)
7512 sri2.icode)))
7514 second_reload_reg = intermediate;
7515 tertiary_icode = (enum insn_code) sri2.icode;
7517 else
7519 oldequiv = old;
7520 real_oldequiv = real_old;
7523 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7525 rtx intermediate = second_reload_reg;
7527 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7528 new_class, mode)
7529 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7530 new_t_class, mode))
7532 second_reload_reg = intermediate;
7533 tertiary_icode = (enum insn_code) sri2.icode;
7535 else
7537 oldequiv = old;
7538 real_oldequiv = real_old;
7541 else
7543 /* This could be handled more intelligently too. */
7544 oldequiv = old;
7545 real_oldequiv = real_old;
7550 /* If we still need a secondary reload register, check
7551 to see if it is being used as a scratch or intermediate
7552 register and generate code appropriately. If we need
7553 a scratch register, use REAL_OLDEQUIV since the form of
7554 the insn may depend on the actual address if it is
7555 a MEM. */
7557 if (second_reload_reg)
7559 if (icode != CODE_FOR_nothing)
7561 /* We'd have to add extra code to handle this case. */
7562 gcc_assert (!third_reload_reg);
7564 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7565 second_reload_reg));
7566 special = 1;
7568 else
7570 /* See if we need a scratch register to load the
7571 intermediate register (a tertiary reload). */
7572 if (tertiary_icode != CODE_FOR_nothing)
7574 emit_insn ((GEN_FCN (tertiary_icode)
7575 (second_reload_reg, real_oldequiv,
7576 third_reload_reg)));
7578 else if (third_reload_reg)
7580 gen_reload (third_reload_reg, real_oldequiv,
7581 rl->opnum,
7582 rl->when_needed);
7583 gen_reload (second_reload_reg, third_reload_reg,
7584 rl->opnum,
7585 rl->when_needed);
7587 else
7588 gen_reload (second_reload_reg, real_oldequiv,
7589 rl->opnum,
7590 rl->when_needed);
7592 oldequiv = second_reload_reg;
7597 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7599 rtx real_oldequiv = oldequiv;
7601 if ((REG_P (oldequiv)
7602 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7603 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7604 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7605 || (GET_CODE (oldequiv) == SUBREG
7606 && REG_P (SUBREG_REG (oldequiv))
7607 && (REGNO (SUBREG_REG (oldequiv))
7608 >= FIRST_PSEUDO_REGISTER)
7609 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7610 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7611 || (CONSTANT_P (oldequiv)
7612 && (targetm.preferred_reload_class (oldequiv,
7613 REGNO_REG_CLASS (REGNO (reloadreg)))
7614 == NO_REGS)))
7615 real_oldequiv = rl->in;
7616 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7617 rl->when_needed);
7620 if (cfun->can_throw_non_call_exceptions)
7621 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7623 /* End this sequence. */
7624 *where = get_insns ();
7625 end_sequence ();
7627 /* Update reload_override_in so that delete_address_reloads_1
7628 can see the actual register usage. */
7629 if (oldequiv_reg)
7630 reload_override_in[j] = oldequiv;
7633 /* Generate insns to for the output reload RL, which is for the insn described
7634 by CHAIN and has the number J. */
7635 static void
7636 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7637 int j)
7639 rtx reloadreg;
7640 rtx_insn *insn = chain->insn;
7641 int special = 0;
7642 rtx old = rl->out;
7643 machine_mode mode;
7644 rtx_insn *p;
7645 rtx rl_reg_rtx;
7647 if (rl->when_needed == RELOAD_OTHER)
7648 start_sequence ();
7649 else
7650 push_to_sequence (output_reload_insns[rl->opnum]);
7652 rl_reg_rtx = reload_reg_rtx_for_output[j];
7653 mode = GET_MODE (rl_reg_rtx);
7655 reloadreg = rl_reg_rtx;
7657 /* If we need two reload regs, set RELOADREG to the intermediate
7658 one, since it will be stored into OLD. We might need a secondary
7659 register only for an input reload, so check again here. */
7661 if (rl->secondary_out_reload >= 0)
7663 rtx real_old = old;
7664 int secondary_reload = rl->secondary_out_reload;
7665 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7667 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7668 && reg_equiv_mem (REGNO (old)) != 0)
7669 real_old = reg_equiv_mem (REGNO (old));
7671 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7673 rtx second_reloadreg = reloadreg;
7674 reloadreg = rld[secondary_reload].reg_rtx;
7676 /* See if RELOADREG is to be used as a scratch register
7677 or as an intermediate register. */
7678 if (rl->secondary_out_icode != CODE_FOR_nothing)
7680 /* We'd have to add extra code to handle this case. */
7681 gcc_assert (tertiary_reload < 0);
7683 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7684 (real_old, second_reloadreg, reloadreg)));
7685 special = 1;
7687 else
7689 /* See if we need both a scratch and intermediate reload
7690 register. */
7692 enum insn_code tertiary_icode
7693 = rld[secondary_reload].secondary_out_icode;
7695 /* We'd have to add more code for quartary reloads. */
7696 gcc_assert (tertiary_reload < 0
7697 || rld[tertiary_reload].secondary_out_reload < 0);
7699 if (GET_MODE (reloadreg) != mode)
7700 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7702 if (tertiary_icode != CODE_FOR_nothing)
7704 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7706 /* Copy primary reload reg to secondary reload reg.
7707 (Note that these have been swapped above, then
7708 secondary reload reg to OLD using our insn.) */
7710 /* If REAL_OLD is a paradoxical SUBREG, remove it
7711 and try to put the opposite SUBREG on
7712 RELOADREG. */
7713 strip_paradoxical_subreg (&real_old, &reloadreg);
7715 gen_reload (reloadreg, second_reloadreg,
7716 rl->opnum, rl->when_needed);
7717 emit_insn ((GEN_FCN (tertiary_icode)
7718 (real_old, reloadreg, third_reloadreg)));
7719 special = 1;
7722 else
7724 /* Copy between the reload regs here and then to
7725 OUT later. */
7727 gen_reload (reloadreg, second_reloadreg,
7728 rl->opnum, rl->when_needed);
7729 if (tertiary_reload >= 0)
7731 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7733 gen_reload (third_reloadreg, reloadreg,
7734 rl->opnum, rl->when_needed);
7735 reloadreg = third_reloadreg;
7742 /* Output the last reload insn. */
7743 if (! special)
7745 rtx set;
7747 /* Don't output the last reload if OLD is not the dest of
7748 INSN and is in the src and is clobbered by INSN. */
7749 if (! flag_expensive_optimizations
7750 || !REG_P (old)
7751 || !(set = single_set (insn))
7752 || rtx_equal_p (old, SET_DEST (set))
7753 || !reg_mentioned_p (old, SET_SRC (set))
7754 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7755 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7756 gen_reload (old, reloadreg, rl->opnum,
7757 rl->when_needed);
7760 /* Look at all insns we emitted, just to be safe. */
7761 for (p = get_insns (); p; p = NEXT_INSN (p))
7762 if (INSN_P (p))
7764 rtx pat = PATTERN (p);
7766 /* If this output reload doesn't come from a spill reg,
7767 clear any memory of reloaded copies of the pseudo reg.
7768 If this output reload comes from a spill reg,
7769 reg_has_output_reload will make this do nothing. */
7770 note_stores (pat, forget_old_reloads_1, NULL);
7772 if (reg_mentioned_p (rl_reg_rtx, pat))
7774 rtx set = single_set (insn);
7775 if (reload_spill_index[j] < 0
7776 && set
7777 && SET_SRC (set) == rl_reg_rtx)
7779 int src = REGNO (SET_SRC (set));
7781 reload_spill_index[j] = src;
7782 SET_HARD_REG_BIT (reg_is_output_reload, src);
7783 if (find_regno_note (insn, REG_DEAD, src))
7784 SET_HARD_REG_BIT (reg_reloaded_died, src);
7786 if (HARD_REGISTER_P (rl_reg_rtx))
7788 int s = rl->secondary_out_reload;
7789 set = single_set (p);
7790 /* If this reload copies only to the secondary reload
7791 register, the secondary reload does the actual
7792 store. */
7793 if (s >= 0 && set == NULL_RTX)
7794 /* We can't tell what function the secondary reload
7795 has and where the actual store to the pseudo is
7796 made; leave new_spill_reg_store alone. */
7798 else if (s >= 0
7799 && SET_SRC (set) == rl_reg_rtx
7800 && SET_DEST (set) == rld[s].reg_rtx)
7802 /* Usually the next instruction will be the
7803 secondary reload insn; if we can confirm
7804 that it is, setting new_spill_reg_store to
7805 that insn will allow an extra optimization. */
7806 rtx s_reg = rld[s].reg_rtx;
7807 rtx_insn *next = NEXT_INSN (p);
7808 rld[s].out = rl->out;
7809 rld[s].out_reg = rl->out_reg;
7810 set = single_set (next);
7811 if (set && SET_SRC (set) == s_reg
7812 && reload_reg_rtx_reaches_end_p (s_reg, s))
7814 SET_HARD_REG_BIT (reg_is_output_reload,
7815 REGNO (s_reg));
7816 new_spill_reg_store[REGNO (s_reg)] = next;
7819 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7820 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7825 if (rl->when_needed == RELOAD_OTHER)
7827 emit_insn (other_output_reload_insns[rl->opnum]);
7828 other_output_reload_insns[rl->opnum] = get_insns ();
7830 else
7831 output_reload_insns[rl->opnum] = get_insns ();
7833 if (cfun->can_throw_non_call_exceptions)
7834 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7836 end_sequence ();
7839 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7840 and has the number J. */
7841 static void
7842 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7844 rtx_insn *insn = chain->insn;
7845 rtx old = (rl->in && MEM_P (rl->in)
7846 ? rl->in_reg : rl->in);
7847 rtx reg_rtx = rl->reg_rtx;
7849 if (old && reg_rtx)
7851 machine_mode mode;
7853 /* Determine the mode to reload in.
7854 This is very tricky because we have three to choose from.
7855 There is the mode the insn operand wants (rl->inmode).
7856 There is the mode of the reload register RELOADREG.
7857 There is the intrinsic mode of the operand, which we could find
7858 by stripping some SUBREGs.
7859 It turns out that RELOADREG's mode is irrelevant:
7860 we can change that arbitrarily.
7862 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7863 then the reload reg may not support QImode moves, so use SImode.
7864 If foo is in memory due to spilling a pseudo reg, this is safe,
7865 because the QImode value is in the least significant part of a
7866 slot big enough for a SImode. If foo is some other sort of
7867 memory reference, then it is impossible to reload this case,
7868 so previous passes had better make sure this never happens.
7870 Then consider a one-word union which has SImode and one of its
7871 members is a float, being fetched as (SUBREG:SF union:SI).
7872 We must fetch that as SFmode because we could be loading into
7873 a float-only register. In this case OLD's mode is correct.
7875 Consider an immediate integer: it has VOIDmode. Here we need
7876 to get a mode from something else.
7878 In some cases, there is a fourth mode, the operand's
7879 containing mode. If the insn specifies a containing mode for
7880 this operand, it overrides all others.
7882 I am not sure whether the algorithm here is always right,
7883 but it does the right things in those cases. */
7885 mode = GET_MODE (old);
7886 if (mode == VOIDmode)
7887 mode = rl->inmode;
7889 /* We cannot use gen_lowpart_common since it can do the wrong thing
7890 when REG_RTX has a multi-word mode. Note that REG_RTX must
7891 always be a REG here. */
7892 if (GET_MODE (reg_rtx) != mode)
7893 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7895 reload_reg_rtx_for_input[j] = reg_rtx;
7897 if (old != 0
7898 /* AUTO_INC reloads need to be handled even if inherited. We got an
7899 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7900 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7901 && ! rtx_equal_p (reg_rtx, old)
7902 && reg_rtx != 0)
7903 emit_input_reload_insns (chain, rld + j, old, j);
7905 /* When inheriting a wider reload, we have a MEM in rl->in,
7906 e.g. inheriting a SImode output reload for
7907 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7908 if (optimize && reload_inherited[j] && rl->in
7909 && MEM_P (rl->in)
7910 && MEM_P (rl->in_reg)
7911 && reload_spill_index[j] >= 0
7912 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7913 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7915 /* If we are reloading a register that was recently stored in with an
7916 output-reload, see if we can prove there was
7917 actually no need to store the old value in it. */
7919 if (optimize
7920 && (reload_inherited[j] || reload_override_in[j])
7921 && reg_rtx
7922 && REG_P (reg_rtx)
7923 && spill_reg_store[REGNO (reg_rtx)] != 0
7924 #if 0
7925 /* There doesn't seem to be any reason to restrict this to pseudos
7926 and doing so loses in the case where we are copying from a
7927 register of the wrong class. */
7928 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7929 #endif
7930 /* The insn might have already some references to stackslots
7931 replaced by MEMs, while reload_out_reg still names the
7932 original pseudo. */
7933 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7934 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7935 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7938 /* Do output reloading for reload RL, which is for the insn described by
7939 CHAIN and has the number J.
7940 ??? At some point we need to support handling output reloads of
7941 JUMP_INSNs or insns that set cc0. */
7942 static void
7943 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7945 rtx note, old;
7946 rtx_insn *insn = chain->insn;
7947 /* If this is an output reload that stores something that is
7948 not loaded in this same reload, see if we can eliminate a previous
7949 store. */
7950 rtx pseudo = rl->out_reg;
7951 rtx reg_rtx = rl->reg_rtx;
7953 if (rl->out && reg_rtx)
7955 machine_mode mode;
7957 /* Determine the mode to reload in.
7958 See comments above (for input reloading). */
7959 mode = GET_MODE (rl->out);
7960 if (mode == VOIDmode)
7962 /* VOIDmode should never happen for an output. */
7963 if (asm_noperands (PATTERN (insn)) < 0)
7964 /* It's the compiler's fault. */
7965 fatal_insn ("VOIDmode on an output", insn);
7966 error_for_asm (insn, "output operand is constant in %<asm%>");
7967 /* Prevent crash--use something we know is valid. */
7968 mode = word_mode;
7969 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7971 if (GET_MODE (reg_rtx) != mode)
7972 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7974 reload_reg_rtx_for_output[j] = reg_rtx;
7976 if (pseudo
7977 && optimize
7978 && REG_P (pseudo)
7979 && ! rtx_equal_p (rl->in_reg, pseudo)
7980 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7981 && reg_last_reload_reg[REGNO (pseudo)])
7983 int pseudo_no = REGNO (pseudo);
7984 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7986 /* We don't need to test full validity of last_regno for
7987 inherit here; we only want to know if the store actually
7988 matches the pseudo. */
7989 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7990 && reg_reloaded_contents[last_regno] == pseudo_no
7991 && spill_reg_store[last_regno]
7992 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7993 delete_output_reload (insn, j, last_regno, reg_rtx);
7996 old = rl->out_reg;
7997 if (old == 0
7998 || reg_rtx == 0
7999 || rtx_equal_p (old, reg_rtx))
8000 return;
8002 /* An output operand that dies right away does need a reload,
8003 but need not be copied from it. Show the new location in the
8004 REG_UNUSED note. */
8005 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8006 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8008 XEXP (note, 0) = reg_rtx;
8009 return;
8011 /* Likewise for a SUBREG of an operand that dies. */
8012 else if (GET_CODE (old) == SUBREG
8013 && REG_P (SUBREG_REG (old))
8014 && (note = find_reg_note (insn, REG_UNUSED,
8015 SUBREG_REG (old))) != 0)
8017 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8018 return;
8020 else if (GET_CODE (old) == SCRATCH)
8021 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8022 but we don't want to make an output reload. */
8023 return;
8025 /* If is a JUMP_INSN, we can't support output reloads yet. */
8026 gcc_assert (NONJUMP_INSN_P (insn));
8028 emit_output_reload_insns (chain, rld + j, j);
8031 /* A reload copies values of MODE from register SRC to register DEST.
8032 Return true if it can be treated for inheritance purposes like a
8033 group of reloads, each one reloading a single hard register. The
8034 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8035 occupy the same number of hard registers. */
8037 static bool
8038 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8039 int src ATTRIBUTE_UNUSED,
8040 machine_mode mode ATTRIBUTE_UNUSED)
8042 return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8043 && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8046 /* Output insns to reload values in and out of the chosen reload regs. */
8048 static void
8049 emit_reload_insns (struct insn_chain *chain)
8051 rtx_insn *insn = chain->insn;
8053 int j;
8055 CLEAR_HARD_REG_SET (reg_reloaded_died);
8057 for (j = 0; j < reload_n_operands; j++)
8058 input_reload_insns[j] = input_address_reload_insns[j]
8059 = inpaddr_address_reload_insns[j]
8060 = output_reload_insns[j] = output_address_reload_insns[j]
8061 = outaddr_address_reload_insns[j]
8062 = other_output_reload_insns[j] = 0;
8063 other_input_address_reload_insns = 0;
8064 other_input_reload_insns = 0;
8065 operand_reload_insns = 0;
8066 other_operand_reload_insns = 0;
8068 /* Dump reloads into the dump file. */
8069 if (dump_file)
8071 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8072 debug_reload_to_stream (dump_file);
8075 for (j = 0; j < n_reloads; j++)
8076 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8078 unsigned int i;
8080 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8081 new_spill_reg_store[i] = 0;
8084 /* Now output the instructions to copy the data into and out of the
8085 reload registers. Do these in the order that the reloads were reported,
8086 since reloads of base and index registers precede reloads of operands
8087 and the operands may need the base and index registers reloaded. */
8089 for (j = 0; j < n_reloads; j++)
8091 do_input_reload (chain, rld + j, j);
8092 do_output_reload (chain, rld + j, j);
8095 /* Now write all the insns we made for reloads in the order expected by
8096 the allocation functions. Prior to the insn being reloaded, we write
8097 the following reloads:
8099 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8101 RELOAD_OTHER reloads.
8103 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8104 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8105 RELOAD_FOR_INPUT reload for the operand.
8107 RELOAD_FOR_OPADDR_ADDRS reloads.
8109 RELOAD_FOR_OPERAND_ADDRESS reloads.
8111 After the insn being reloaded, we write the following:
8113 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8114 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8115 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8116 reloads for the operand. The RELOAD_OTHER output reloads are
8117 output in descending order by reload number. */
8119 emit_insn_before (other_input_address_reload_insns, insn);
8120 emit_insn_before (other_input_reload_insns, insn);
8122 for (j = 0; j < reload_n_operands; j++)
8124 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8125 emit_insn_before (input_address_reload_insns[j], insn);
8126 emit_insn_before (input_reload_insns[j], insn);
8129 emit_insn_before (other_operand_reload_insns, insn);
8130 emit_insn_before (operand_reload_insns, insn);
8132 for (j = 0; j < reload_n_operands; j++)
8134 rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8135 x = emit_insn_after (output_address_reload_insns[j], x);
8136 x = emit_insn_after (output_reload_insns[j], x);
8137 emit_insn_after (other_output_reload_insns[j], x);
8140 /* For all the spill regs newly reloaded in this instruction,
8141 record what they were reloaded from, so subsequent instructions
8142 can inherit the reloads.
8144 Update spill_reg_store for the reloads of this insn.
8145 Copy the elements that were updated in the loop above. */
8147 for (j = 0; j < n_reloads; j++)
8149 int r = reload_order[j];
8150 int i = reload_spill_index[r];
8152 /* If this is a non-inherited input reload from a pseudo, we must
8153 clear any memory of a previous store to the same pseudo. Only do
8154 something if there will not be an output reload for the pseudo
8155 being reloaded. */
8156 if (rld[r].in_reg != 0
8157 && ! (reload_inherited[r] || reload_override_in[r]))
8159 rtx reg = rld[r].in_reg;
8161 if (GET_CODE (reg) == SUBREG)
8162 reg = SUBREG_REG (reg);
8164 if (REG_P (reg)
8165 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8166 && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8168 int nregno = REGNO (reg);
8170 if (reg_last_reload_reg[nregno])
8172 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8174 if (reg_reloaded_contents[last_regno] == nregno)
8175 spill_reg_store[last_regno] = 0;
8180 /* I is nonneg if this reload used a register.
8181 If rld[r].reg_rtx is 0, this is an optional reload
8182 that we opted to ignore. */
8184 if (i >= 0 && rld[r].reg_rtx != 0)
8186 int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx));
8187 int k;
8189 /* For a multi register reload, we need to check if all or part
8190 of the value lives to the end. */
8191 for (k = 0; k < nr; k++)
8192 if (reload_reg_reaches_end_p (i + k, r))
8193 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8195 /* Maybe the spill reg contains a copy of reload_out. */
8196 if (rld[r].out != 0
8197 && (REG_P (rld[r].out)
8198 || (rld[r].out_reg
8199 ? REG_P (rld[r].out_reg)
8200 /* The reload value is an auto-modification of
8201 some kind. For PRE_INC, POST_INC, PRE_DEC
8202 and POST_DEC, we record an equivalence
8203 between the reload register and the operand
8204 on the optimistic assumption that we can make
8205 the equivalence hold. reload_as_needed must
8206 then either make it hold or invalidate the
8207 equivalence.
8209 PRE_MODIFY and POST_MODIFY addresses are reloaded
8210 somewhat differently, and allowing them here leads
8211 to problems. */
8212 : (GET_CODE (rld[r].out) != POST_MODIFY
8213 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8215 rtx reg;
8217 reg = reload_reg_rtx_for_output[r];
8218 if (reload_reg_rtx_reaches_end_p (reg, r))
8220 machine_mode mode = GET_MODE (reg);
8221 int regno = REGNO (reg);
8222 int nregs = REG_NREGS (reg);
8223 rtx out = (REG_P (rld[r].out)
8224 ? rld[r].out
8225 : rld[r].out_reg
8226 ? rld[r].out_reg
8227 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8228 int out_regno = REGNO (out);
8229 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8230 : hard_regno_nregs (out_regno, mode));
8231 bool piecemeal;
8233 spill_reg_store[regno] = new_spill_reg_store[regno];
8234 spill_reg_stored_to[regno] = out;
8235 reg_last_reload_reg[out_regno] = reg;
8237 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8238 && nregs == out_nregs
8239 && inherit_piecemeal_p (out_regno, regno, mode));
8241 /* If OUT_REGNO is a hard register, it may occupy more than
8242 one register. If it does, say what is in the
8243 rest of the registers assuming that both registers
8244 agree on how many words the object takes. If not,
8245 invalidate the subsequent registers. */
8247 if (HARD_REGISTER_NUM_P (out_regno))
8248 for (k = 1; k < out_nregs; k++)
8249 reg_last_reload_reg[out_regno + k]
8250 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8252 /* Now do the inverse operation. */
8253 for (k = 0; k < nregs; k++)
8255 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8256 reg_reloaded_contents[regno + k]
8257 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8258 ? out_regno
8259 : out_regno + k);
8260 reg_reloaded_insn[regno + k] = insn;
8261 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8262 if (targetm.hard_regno_call_part_clobbered (regno + k,
8263 mode))
8264 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8265 regno + k);
8266 else
8267 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8268 regno + k);
8272 /* Maybe the spill reg contains a copy of reload_in. Only do
8273 something if there will not be an output reload for
8274 the register being reloaded. */
8275 else if (rld[r].out_reg == 0
8276 && rld[r].in != 0
8277 && ((REG_P (rld[r].in)
8278 && !HARD_REGISTER_P (rld[r].in)
8279 && !REGNO_REG_SET_P (&reg_has_output_reload,
8280 REGNO (rld[r].in)))
8281 || (REG_P (rld[r].in_reg)
8282 && !REGNO_REG_SET_P (&reg_has_output_reload,
8283 REGNO (rld[r].in_reg))))
8284 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8286 rtx reg;
8288 reg = reload_reg_rtx_for_input[r];
8289 if (reload_reg_rtx_reaches_end_p (reg, r))
8291 machine_mode mode;
8292 int regno;
8293 int nregs;
8294 int in_regno;
8295 int in_nregs;
8296 rtx in;
8297 bool piecemeal;
8299 mode = GET_MODE (reg);
8300 regno = REGNO (reg);
8301 nregs = REG_NREGS (reg);
8302 if (REG_P (rld[r].in)
8303 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8304 in = rld[r].in;
8305 else if (REG_P (rld[r].in_reg))
8306 in = rld[r].in_reg;
8307 else
8308 in = XEXP (rld[r].in_reg, 0);
8309 in_regno = REGNO (in);
8311 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8312 : hard_regno_nregs (in_regno, mode));
8314 reg_last_reload_reg[in_regno] = reg;
8316 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8317 && nregs == in_nregs
8318 && inherit_piecemeal_p (regno, in_regno, mode));
8320 if (HARD_REGISTER_NUM_P (in_regno))
8321 for (k = 1; k < in_nregs; k++)
8322 reg_last_reload_reg[in_regno + k]
8323 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8325 /* Unless we inherited this reload, show we haven't
8326 recently done a store.
8327 Previous stores of inherited auto_inc expressions
8328 also have to be discarded. */
8329 if (! reload_inherited[r]
8330 || (rld[r].out && ! rld[r].out_reg))
8331 spill_reg_store[regno] = 0;
8333 for (k = 0; k < nregs; k++)
8335 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8336 reg_reloaded_contents[regno + k]
8337 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8338 ? in_regno
8339 : in_regno + k);
8340 reg_reloaded_insn[regno + k] = insn;
8341 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8342 if (targetm.hard_regno_call_part_clobbered (regno + k,
8343 mode))
8344 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8345 regno + k);
8346 else
8347 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8348 regno + k);
8354 /* The following if-statement was #if 0'd in 1.34 (or before...).
8355 It's reenabled in 1.35 because supposedly nothing else
8356 deals with this problem. */
8358 /* If a register gets output-reloaded from a non-spill register,
8359 that invalidates any previous reloaded copy of it.
8360 But forget_old_reloads_1 won't get to see it, because
8361 it thinks only about the original insn. So invalidate it here.
8362 Also do the same thing for RELOAD_OTHER constraints where the
8363 output is discarded. */
8364 if (i < 0
8365 && ((rld[r].out != 0
8366 && (REG_P (rld[r].out)
8367 || (MEM_P (rld[r].out)
8368 && REG_P (rld[r].out_reg))))
8369 || (rld[r].out == 0 && rld[r].out_reg
8370 && REG_P (rld[r].out_reg))))
8372 rtx out = ((rld[r].out && REG_P (rld[r].out))
8373 ? rld[r].out : rld[r].out_reg);
8374 int out_regno = REGNO (out);
8375 machine_mode mode = GET_MODE (out);
8377 /* REG_RTX is now set or clobbered by the main instruction.
8378 As the comment above explains, forget_old_reloads_1 only
8379 sees the original instruction, and there is no guarantee
8380 that the original instruction also clobbered REG_RTX.
8381 For example, if find_reloads sees that the input side of
8382 a matched operand pair dies in this instruction, it may
8383 use the input register as the reload register.
8385 Calling forget_old_reloads_1 is a waste of effort if
8386 REG_RTX is also the output register.
8388 If we know that REG_RTX holds the value of a pseudo
8389 register, the code after the call will record that fact. */
8390 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8391 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8393 if (!HARD_REGISTER_NUM_P (out_regno))
8395 rtx src_reg;
8396 rtx_insn *store_insn = NULL;
8398 reg_last_reload_reg[out_regno] = 0;
8400 /* If we can find a hard register that is stored, record
8401 the storing insn so that we may delete this insn with
8402 delete_output_reload. */
8403 src_reg = reload_reg_rtx_for_output[r];
8405 if (src_reg)
8407 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8408 store_insn = new_spill_reg_store[REGNO (src_reg)];
8409 else
8410 src_reg = NULL_RTX;
8412 else
8414 /* If this is an optional reload, try to find the
8415 source reg from an input reload. */
8416 rtx set = single_set (insn);
8417 if (set && SET_DEST (set) == rld[r].out)
8419 int k;
8421 src_reg = SET_SRC (set);
8422 store_insn = insn;
8423 for (k = 0; k < n_reloads; k++)
8425 if (rld[k].in == src_reg)
8427 src_reg = reload_reg_rtx_for_input[k];
8428 break;
8433 if (src_reg && REG_P (src_reg)
8434 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8436 int src_regno, src_nregs, k;
8437 rtx note;
8439 gcc_assert (GET_MODE (src_reg) == mode);
8440 src_regno = REGNO (src_reg);
8441 src_nregs = hard_regno_nregs (src_regno, mode);
8442 /* The place where to find a death note varies with
8443 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8444 necessarily checked exactly in the code that moves
8445 notes, so just check both locations. */
8446 note = find_regno_note (insn, REG_DEAD, src_regno);
8447 if (! note && store_insn)
8448 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8449 for (k = 0; k < src_nregs; k++)
8451 spill_reg_store[src_regno + k] = store_insn;
8452 spill_reg_stored_to[src_regno + k] = out;
8453 reg_reloaded_contents[src_regno + k] = out_regno;
8454 reg_reloaded_insn[src_regno + k] = store_insn;
8455 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8456 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8457 if (targetm.hard_regno_call_part_clobbered
8458 (src_regno + k, mode))
8459 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8460 src_regno + k);
8461 else
8462 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8463 src_regno + k);
8464 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8465 if (note)
8466 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8467 else
8468 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8470 reg_last_reload_reg[out_regno] = src_reg;
8471 /* We have to set reg_has_output_reload here, or else
8472 forget_old_reloads_1 will clear reg_last_reload_reg
8473 right away. */
8474 SET_REGNO_REG_SET (&reg_has_output_reload,
8475 out_regno);
8478 else
8480 int k, out_nregs = hard_regno_nregs (out_regno, mode);
8482 for (k = 0; k < out_nregs; k++)
8483 reg_last_reload_reg[out_regno + k] = 0;
8487 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8490 /* Go through the motions to emit INSN and test if it is strictly valid.
8491 Return the emitted insn if valid, else return NULL. */
8493 static rtx_insn *
8494 emit_insn_if_valid_for_reload (rtx pat)
8496 rtx_insn *last = get_last_insn ();
8497 int code;
8499 rtx_insn *insn = emit_insn (pat);
8500 code = recog_memoized (insn);
8502 if (code >= 0)
8504 extract_insn (insn);
8505 /* We want constrain operands to treat this insn strictly in its
8506 validity determination, i.e., the way it would after reload has
8507 completed. */
8508 if (constrain_operands (1, get_enabled_alternatives (insn)))
8509 return insn;
8512 delete_insns_since (last);
8513 return NULL;
8516 /* Emit code to perform a reload from IN (which may be a reload register) to
8517 OUT (which may also be a reload register). IN or OUT is from operand
8518 OPNUM with reload type TYPE.
8520 Returns first insn emitted. */
8522 static rtx_insn *
8523 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8525 rtx_insn *last = get_last_insn ();
8526 rtx_insn *tem;
8527 rtx tem1, tem2;
8529 /* If IN is a paradoxical SUBREG, remove it and try to put the
8530 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8531 if (!strip_paradoxical_subreg (&in, &out))
8532 strip_paradoxical_subreg (&out, &in);
8534 /* How to do this reload can get quite tricky. Normally, we are being
8535 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8536 register that didn't get a hard register. In that case we can just
8537 call emit_move_insn.
8539 We can also be asked to reload a PLUS that adds a register or a MEM to
8540 another register, constant or MEM. This can occur during frame pointer
8541 elimination and while reloading addresses. This case is handled by
8542 trying to emit a single insn to perform the add. If it is not valid,
8543 we use a two insn sequence.
8545 Or we can be asked to reload an unary operand that was a fragment of
8546 an addressing mode, into a register. If it isn't recognized as-is,
8547 we try making the unop operand and the reload-register the same:
8548 (set reg:X (unop:X expr:Y))
8549 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8551 Finally, we could be called to handle an 'o' constraint by putting
8552 an address into a register. In that case, we first try to do this
8553 with a named pattern of "reload_load_address". If no such pattern
8554 exists, we just emit a SET insn and hope for the best (it will normally
8555 be valid on machines that use 'o').
8557 This entire process is made complex because reload will never
8558 process the insns we generate here and so we must ensure that
8559 they will fit their constraints and also by the fact that parts of
8560 IN might be being reloaded separately and replaced with spill registers.
8561 Because of this, we are, in some sense, just guessing the right approach
8562 here. The one listed above seems to work.
8564 ??? At some point, this whole thing needs to be rethought. */
8566 if (GET_CODE (in) == PLUS
8567 && (REG_P (XEXP (in, 0))
8568 || GET_CODE (XEXP (in, 0)) == SUBREG
8569 || MEM_P (XEXP (in, 0)))
8570 && (REG_P (XEXP (in, 1))
8571 || GET_CODE (XEXP (in, 1)) == SUBREG
8572 || CONSTANT_P (XEXP (in, 1))
8573 || MEM_P (XEXP (in, 1))))
8575 /* We need to compute the sum of a register or a MEM and another
8576 register, constant, or MEM, and put it into the reload
8577 register. The best possible way of doing this is if the machine
8578 has a three-operand ADD insn that accepts the required operands.
8580 The simplest approach is to try to generate such an insn and see if it
8581 is recognized and matches its constraints. If so, it can be used.
8583 It might be better not to actually emit the insn unless it is valid,
8584 but we need to pass the insn as an operand to `recog' and
8585 `extract_insn' and it is simpler to emit and then delete the insn if
8586 not valid than to dummy things up. */
8588 rtx op0, op1, tem;
8589 rtx_insn *insn;
8590 enum insn_code code;
8592 op0 = find_replacement (&XEXP (in, 0));
8593 op1 = find_replacement (&XEXP (in, 1));
8595 /* Since constraint checking is strict, commutativity won't be
8596 checked, so we need to do that here to avoid spurious failure
8597 if the add instruction is two-address and the second operand
8598 of the add is the same as the reload reg, which is frequently
8599 the case. If the insn would be A = B + A, rearrange it so
8600 it will be A = A + B as constrain_operands expects. */
8602 if (REG_P (XEXP (in, 1))
8603 && REGNO (out) == REGNO (XEXP (in, 1)))
8604 tem = op0, op0 = op1, op1 = tem;
8606 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8607 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8609 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8610 if (insn)
8611 return insn;
8613 /* If that failed, we must use a conservative two-insn sequence.
8615 Use a move to copy one operand into the reload register. Prefer
8616 to reload a constant, MEM or pseudo since the move patterns can
8617 handle an arbitrary operand. If OP1 is not a constant, MEM or
8618 pseudo and OP1 is not a valid operand for an add instruction, then
8619 reload OP1.
8621 After reloading one of the operands into the reload register, add
8622 the reload register to the output register.
8624 If there is another way to do this for a specific machine, a
8625 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8626 we emit below. */
8628 code = optab_handler (add_optab, GET_MODE (out));
8630 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8631 || (REG_P (op1)
8632 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8633 || (code != CODE_FOR_nothing
8634 && !insn_operand_matches (code, 2, op1)))
8635 tem = op0, op0 = op1, op1 = tem;
8637 gen_reload (out, op0, opnum, type);
8639 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8640 This fixes a problem on the 32K where the stack pointer cannot
8641 be used as an operand of an add insn. */
8643 if (rtx_equal_p (op0, op1))
8644 op1 = out;
8646 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8647 if (insn)
8649 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8650 set_dst_reg_note (insn, REG_EQUIV, in, out);
8651 return insn;
8654 /* If that failed, copy the address register to the reload register.
8655 Then add the constant to the reload register. */
8657 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8658 gen_reload (out, op1, opnum, type);
8659 insn = emit_insn (gen_add2_insn (out, op0));
8660 set_dst_reg_note (insn, REG_EQUIV, in, out);
8663 /* If we need a memory location to do the move, do it that way. */
8664 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8665 (REG_P (tem1) && REG_P (tem2)))
8666 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8667 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8668 && targetm.secondary_memory_needed (GET_MODE (out),
8669 REGNO_REG_CLASS (REGNO (tem1)),
8670 REGNO_REG_CLASS (REGNO (tem2))))
8672 /* Get the memory to use and rewrite both registers to its mode. */
8673 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8675 if (GET_MODE (loc) != GET_MODE (out))
8676 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8678 if (GET_MODE (loc) != GET_MODE (in))
8679 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8681 gen_reload (loc, in, opnum, type);
8682 gen_reload (out, loc, opnum, type);
8684 else if (REG_P (out) && UNARY_P (in))
8686 rtx op1;
8687 rtx out_moded;
8688 rtx_insn *set;
8690 op1 = find_replacement (&XEXP (in, 0));
8691 if (op1 != XEXP (in, 0))
8692 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8694 /* First, try a plain SET. */
8695 set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8696 if (set)
8697 return set;
8699 /* If that failed, move the inner operand to the reload
8700 register, and try the same unop with the inner expression
8701 replaced with the reload register. */
8703 if (GET_MODE (op1) != GET_MODE (out))
8704 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8705 else
8706 out_moded = out;
8708 gen_reload (out_moded, op1, opnum, type);
8710 rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8711 out_moded));
8712 rtx_insn *insn = emit_insn_if_valid_for_reload (temp);
8713 if (insn)
8715 set_unique_reg_note (insn, REG_EQUIV, in);
8716 return insn;
8719 fatal_insn ("failure trying to reload:", set);
8721 /* If IN is a simple operand, use gen_move_insn. */
8722 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8724 tem = emit_insn (gen_move_insn (out, in));
8725 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8726 mark_jump_label (in, tem, 0);
8729 else if (targetm.have_reload_load_address ())
8730 emit_insn (targetm.gen_reload_load_address (out, in));
8732 /* Otherwise, just write (set OUT IN) and hope for the best. */
8733 else
8734 emit_insn (gen_rtx_SET (out, in));
8736 /* Return the first insn emitted.
8737 We can not just return get_last_insn, because there may have
8738 been multiple instructions emitted. Also note that gen_move_insn may
8739 emit more than one insn itself, so we can not assume that there is one
8740 insn emitted per emit_insn_before call. */
8742 return last ? NEXT_INSN (last) : get_insns ();
8745 /* Delete a previously made output-reload whose result we now believe
8746 is not needed. First we double-check.
8748 INSN is the insn now being processed.
8749 LAST_RELOAD_REG is the hard register number for which we want to delete
8750 the last output reload.
8751 J is the reload-number that originally used REG. The caller has made
8752 certain that reload J doesn't use REG any longer for input.
8753 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8755 static void
8756 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8757 rtx new_reload_reg)
8759 rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8760 rtx reg = spill_reg_stored_to[last_reload_reg];
8761 int k;
8762 int n_occurrences;
8763 int n_inherited = 0;
8764 rtx substed;
8765 unsigned regno;
8766 int nregs;
8768 /* It is possible that this reload has been only used to set another reload
8769 we eliminated earlier and thus deleted this instruction too. */
8770 if (output_reload_insn->deleted ())
8771 return;
8773 /* Get the raw pseudo-register referred to. */
8775 while (GET_CODE (reg) == SUBREG)
8776 reg = SUBREG_REG (reg);
8777 substed = reg_equiv_memory_loc (REGNO (reg));
8779 /* This is unsafe if the operand occurs more often in the current
8780 insn than it is inherited. */
8781 for (k = n_reloads - 1; k >= 0; k--)
8783 rtx reg2 = rld[k].in;
8784 if (! reg2)
8785 continue;
8786 if (MEM_P (reg2) || reload_override_in[k])
8787 reg2 = rld[k].in_reg;
8789 if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8790 reg2 = XEXP (rld[k].in_reg, 0);
8792 while (GET_CODE (reg2) == SUBREG)
8793 reg2 = SUBREG_REG (reg2);
8794 if (rtx_equal_p (reg2, reg))
8796 if (reload_inherited[k] || reload_override_in[k] || k == j)
8797 n_inherited++;
8798 else
8799 return;
8802 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8803 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8804 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8805 reg, 0);
8806 if (substed)
8807 n_occurrences += count_occurrences (PATTERN (insn),
8808 eliminate_regs (substed, VOIDmode,
8809 NULL_RTX), 0);
8810 for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8812 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8813 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8815 if (n_occurrences > n_inherited)
8816 return;
8818 regno = REGNO (reg);
8819 nregs = REG_NREGS (reg);
8821 /* If the pseudo-reg we are reloading is no longer referenced
8822 anywhere between the store into it and here,
8823 and we're within the same basic block, then the value can only
8824 pass through the reload reg and end up here.
8825 Otherwise, give up--return. */
8826 for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8827 i1 != insn; i1 = NEXT_INSN (i1))
8829 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8830 return;
8831 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8832 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8834 /* If this is USE in front of INSN, we only have to check that
8835 there are no more references than accounted for by inheritance. */
8836 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8838 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8839 i1 = NEXT_INSN (i1);
8841 if (n_occurrences <= n_inherited && i1 == insn)
8842 break;
8843 return;
8847 /* We will be deleting the insn. Remove the spill reg information. */
8848 for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; )
8850 spill_reg_store[last_reload_reg + k] = 0;
8851 spill_reg_stored_to[last_reload_reg + k] = 0;
8854 /* The caller has already checked that REG dies or is set in INSN.
8855 It has also checked that we are optimizing, and thus some
8856 inaccuracies in the debugging information are acceptable.
8857 So we could just delete output_reload_insn. But in some cases
8858 we can improve the debugging information without sacrificing
8859 optimization - maybe even improving the code: See if the pseudo
8860 reg has been completely replaced with reload regs. If so, delete
8861 the store insn and forget we had a stack slot for the pseudo. */
8862 if (rld[j].out != rld[j].in
8863 && REG_N_DEATHS (REGNO (reg)) == 1
8864 && REG_N_SETS (REGNO (reg)) == 1
8865 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8866 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8868 rtx_insn *i2;
8870 /* We know that it was used only between here and the beginning of
8871 the current basic block. (We also know that the last use before
8872 INSN was the output reload we are thinking of deleting, but never
8873 mind that.) Search that range; see if any ref remains. */
8874 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8876 rtx set = single_set (i2);
8878 /* Uses which just store in the pseudo don't count,
8879 since if they are the only uses, they are dead. */
8880 if (set != 0 && SET_DEST (set) == reg)
8881 continue;
8882 if (LABEL_P (i2) || JUMP_P (i2))
8883 break;
8884 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8885 && reg_mentioned_p (reg, PATTERN (i2)))
8887 /* Some other ref remains; just delete the output reload we
8888 know to be dead. */
8889 delete_address_reloads (output_reload_insn, insn);
8890 delete_insn (output_reload_insn);
8891 return;
8895 /* Delete the now-dead stores into this pseudo. Note that this
8896 loop also takes care of deleting output_reload_insn. */
8897 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8899 rtx set = single_set (i2);
8901 if (set != 0 && SET_DEST (set) == reg)
8903 delete_address_reloads (i2, insn);
8904 delete_insn (i2);
8906 if (LABEL_P (i2) || JUMP_P (i2))
8907 break;
8910 /* For the debugging info, say the pseudo lives in this reload reg. */
8911 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8912 if (ira_conflicts_p)
8913 /* Inform IRA about the change. */
8914 ira_mark_allocation_change (REGNO (reg));
8915 alter_reg (REGNO (reg), -1, false);
8917 else
8919 delete_address_reloads (output_reload_insn, insn);
8920 delete_insn (output_reload_insn);
8924 /* We are going to delete DEAD_INSN. Recursively delete loads of
8925 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8926 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8927 static void
8928 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
8930 rtx set = single_set (dead_insn);
8931 rtx set2, dst;
8932 rtx_insn *prev, *next;
8933 if (set)
8935 rtx dst = SET_DEST (set);
8936 if (MEM_P (dst))
8937 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8939 /* If we deleted the store from a reloaded post_{in,de}c expression,
8940 we can delete the matching adds. */
8941 prev = PREV_INSN (dead_insn);
8942 next = NEXT_INSN (dead_insn);
8943 if (! prev || ! next)
8944 return;
8945 set = single_set (next);
8946 set2 = single_set (prev);
8947 if (! set || ! set2
8948 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8949 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8950 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8951 return;
8952 dst = SET_DEST (set);
8953 if (! rtx_equal_p (dst, SET_DEST (set2))
8954 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8955 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8956 || (INTVAL (XEXP (SET_SRC (set), 1))
8957 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8958 return;
8959 delete_related_insns (prev);
8960 delete_related_insns (next);
8963 /* Subfunction of delete_address_reloads: process registers found in X. */
8964 static void
8965 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
8967 rtx_insn *prev, *i2;
8968 rtx set, dst;
8969 int i, j;
8970 enum rtx_code code = GET_CODE (x);
8972 if (code != REG)
8974 const char *fmt = GET_RTX_FORMAT (code);
8975 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8977 if (fmt[i] == 'e')
8978 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8979 else if (fmt[i] == 'E')
8981 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8982 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8983 current_insn);
8986 return;
8989 if (spill_reg_order[REGNO (x)] < 0)
8990 return;
8992 /* Scan backwards for the insn that sets x. This might be a way back due
8993 to inheritance. */
8994 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8996 code = GET_CODE (prev);
8997 if (code == CODE_LABEL || code == JUMP_INSN)
8998 return;
8999 if (!INSN_P (prev))
9000 continue;
9001 if (reg_set_p (x, PATTERN (prev)))
9002 break;
9003 if (reg_referenced_p (x, PATTERN (prev)))
9004 return;
9006 if (! prev || INSN_UID (prev) < reload_first_uid)
9007 return;
9008 /* Check that PREV only sets the reload register. */
9009 set = single_set (prev);
9010 if (! set)
9011 return;
9012 dst = SET_DEST (set);
9013 if (!REG_P (dst)
9014 || ! rtx_equal_p (dst, x))
9015 return;
9016 if (! reg_set_p (dst, PATTERN (dead_insn)))
9018 /* Check if DST was used in a later insn -
9019 it might have been inherited. */
9020 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9022 if (LABEL_P (i2))
9023 break;
9024 if (! INSN_P (i2))
9025 continue;
9026 if (reg_referenced_p (dst, PATTERN (i2)))
9028 /* If there is a reference to the register in the current insn,
9029 it might be loaded in a non-inherited reload. If no other
9030 reload uses it, that means the register is set before
9031 referenced. */
9032 if (i2 == current_insn)
9034 for (j = n_reloads - 1; j >= 0; j--)
9035 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9036 || reload_override_in[j] == dst)
9037 return;
9038 for (j = n_reloads - 1; j >= 0; j--)
9039 if (rld[j].in && rld[j].reg_rtx == dst)
9040 break;
9041 if (j >= 0)
9042 break;
9044 return;
9046 if (JUMP_P (i2))
9047 break;
9048 /* If DST is still live at CURRENT_INSN, check if it is used for
9049 any reload. Note that even if CURRENT_INSN sets DST, we still
9050 have to check the reloads. */
9051 if (i2 == current_insn)
9053 for (j = n_reloads - 1; j >= 0; j--)
9054 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9055 || reload_override_in[j] == dst)
9056 return;
9057 /* ??? We can't finish the loop here, because dst might be
9058 allocated to a pseudo in this block if no reload in this
9059 block needs any of the classes containing DST - see
9060 spill_hard_reg. There is no easy way to tell this, so we
9061 have to scan till the end of the basic block. */
9063 if (reg_set_p (dst, PATTERN (i2)))
9064 break;
9067 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9068 reg_reloaded_contents[REGNO (dst)] = -1;
9069 delete_insn (prev);
9072 /* Output reload-insns to reload VALUE into RELOADREG.
9073 VALUE is an autoincrement or autodecrement RTX whose operand
9074 is a register or memory location;
9075 so reloading involves incrementing that location.
9076 IN is either identical to VALUE, or some cheaper place to reload from.
9078 INC_AMOUNT is the number to increment or decrement by (always positive).
9079 This cannot be deduced from VALUE. */
9081 static void
9082 inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount)
9084 /* REG or MEM to be copied and incremented. */
9085 rtx incloc = find_replacement (&XEXP (value, 0));
9086 /* Nonzero if increment after copying. */
9087 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9088 || GET_CODE (value) == POST_MODIFY);
9089 rtx_insn *last;
9090 rtx inc;
9091 rtx_insn *add_insn;
9092 int code;
9093 rtx real_in = in == value ? incloc : in;
9095 /* No hard register is equivalent to this register after
9096 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9097 we could inc/dec that register as well (maybe even using it for
9098 the source), but I'm not sure it's worth worrying about. */
9099 if (REG_P (incloc))
9100 reg_last_reload_reg[REGNO (incloc)] = 0;
9102 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9104 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9105 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9107 else
9109 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9110 inc_amount = -inc_amount;
9112 inc = gen_int_mode (inc_amount, Pmode);
9115 /* If this is post-increment, first copy the location to the reload reg. */
9116 if (post && real_in != reloadreg)
9117 emit_insn (gen_move_insn (reloadreg, real_in));
9119 if (in == value)
9121 /* See if we can directly increment INCLOC. Use a method similar to
9122 that in gen_reload. */
9124 last = get_last_insn ();
9125 add_insn = emit_insn (gen_rtx_SET (incloc,
9126 gen_rtx_PLUS (GET_MODE (incloc),
9127 incloc, inc)));
9129 code = recog_memoized (add_insn);
9130 if (code >= 0)
9132 extract_insn (add_insn);
9133 if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9135 /* If this is a pre-increment and we have incremented the value
9136 where it lives, copy the incremented value to RELOADREG to
9137 be used as an address. */
9139 if (! post)
9140 emit_insn (gen_move_insn (reloadreg, incloc));
9141 return;
9144 delete_insns_since (last);
9147 /* If couldn't do the increment directly, must increment in RELOADREG.
9148 The way we do this depends on whether this is pre- or post-increment.
9149 For pre-increment, copy INCLOC to the reload register, increment it
9150 there, then save back. */
9152 if (! post)
9154 if (in != reloadreg)
9155 emit_insn (gen_move_insn (reloadreg, real_in));
9156 emit_insn (gen_add2_insn (reloadreg, inc));
9157 emit_insn (gen_move_insn (incloc, reloadreg));
9159 else
9161 /* Postincrement.
9162 Because this might be a jump insn or a compare, and because RELOADREG
9163 may not be available after the insn in an input reload, we must do
9164 the incrementation before the insn being reloaded for.
9166 We have already copied IN to RELOADREG. Increment the copy in
9167 RELOADREG, save that back, then decrement RELOADREG so it has
9168 the original value. */
9170 emit_insn (gen_add2_insn (reloadreg, inc));
9171 emit_insn (gen_move_insn (incloc, reloadreg));
9172 if (CONST_INT_P (inc))
9173 emit_insn (gen_add2_insn (reloadreg,
9174 gen_int_mode (-INTVAL (inc),
9175 GET_MODE (reloadreg))));
9176 else
9177 emit_insn (gen_sub2_insn (reloadreg, inc));
9181 static void
9182 add_auto_inc_notes (rtx_insn *insn, rtx x)
9184 enum rtx_code code = GET_CODE (x);
9185 const char *fmt;
9186 int i, j;
9188 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9190 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9191 return;
9194 /* Scan all the operand sub-expressions. */
9195 fmt = GET_RTX_FORMAT (code);
9196 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9198 if (fmt[i] == 'e')
9199 add_auto_inc_notes (insn, XEXP (x, i));
9200 else if (fmt[i] == 'E')
9201 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9202 add_auto_inc_notes (insn, XVECEXP (x, i, j));