Merge trunk version 194076 into gupc branch.
[official-gcc.git] / gcc / config / rs6000 / rs6000.c
blobb4217237566230f8165383e8a07546a212f61832
1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2012 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "tm.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
31 #include "flags.h"
32 #include "recog.h"
33 #include "obstack.h"
34 #include "tree.h"
35 #include "expr.h"
36 #include "optabs.h"
37 #include "except.h"
38 #include "function.h"
39 #include "output.h"
40 #include "dbxout.h"
41 #include "basic-block.h"
42 #include "diagnostic-core.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "hashtab.h"
46 #include "tm_p.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "common/common-target.h"
50 #include "langhooks.h"
51 #include "reload.h"
52 #include "cfgloop.h"
53 #include "sched-int.h"
54 #include "gimple.h"
55 #include "tree-flow.h"
56 #include "intl.h"
57 #include "params.h"
58 #include "tm-constrs.h"
59 #include "opts.h"
60 #include "tree-vectorizer.h"
61 #include "dumpfile.h"
62 #if TARGET_XCOFF
63 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #endif
65 #if TARGET_MACHO
66 #include "gstab.h" /* for N_SLINE */
67 #endif
69 #ifndef TARGET_NO_PROTOTYPE
70 #define TARGET_NO_PROTOTYPE 0
71 #endif
73 #define min(A,B) ((A) < (B) ? (A) : (B))
74 #define max(A,B) ((A) > (B) ? (A) : (B))
76 /* Structure used to define the rs6000 stack */
77 typedef struct rs6000_stack {
78 int reload_completed; /* stack info won't change from here on */
79 int first_gp_reg_save; /* first callee saved GP register used */
80 int first_fp_reg_save; /* first callee saved FP register used */
81 int first_altivec_reg_save; /* first callee saved AltiVec register used */
82 int lr_save_p; /* true if the link reg needs to be saved */
83 int cr_save_p; /* true if the CR reg needs to be saved */
84 unsigned int vrsave_mask; /* mask of vec registers to save */
85 int push_p; /* true if we need to allocate stack space */
86 int calls_p; /* true if the function makes any calls */
87 int world_save_p; /* true if we're saving *everything*:
88 r13-r31, cr, f14-f31, vrsave, v20-v31 */
89 enum rs6000_abi abi; /* which ABI to use */
90 int gp_save_offset; /* offset to save GP regs from initial SP */
91 int fp_save_offset; /* offset to save FP regs from initial SP */
92 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
93 int lr_save_offset; /* offset to save LR from initial SP */
94 int cr_save_offset; /* offset to save CR from initial SP */
95 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
96 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
97 int varargs_save_offset; /* offset to save the varargs registers */
98 int ehrd_offset; /* offset to EH return data */
99 int reg_size; /* register size (4 or 8) */
100 HOST_WIDE_INT vars_size; /* variable save area size */
101 int parm_size; /* outgoing parameter size */
102 int save_size; /* save area size */
103 int fixed_size; /* fixed size of stack frame */
104 int gp_size; /* size of saved GP registers */
105 int fp_size; /* size of saved FP registers */
106 int altivec_size; /* size of saved AltiVec registers */
107 int cr_size; /* size to hold CR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
110 not in save_size */
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
114 int spe_64bit_regs_used;
115 int savres_strategy;
116 } rs6000_stack_t;
118 /* A C structure for machine-specific, per-function data.
119 This is added to the cfun structure. */
120 typedef struct GTY(()) machine_function
122 /* Some local-dynamic symbol. */
123 const char *some_ld_name;
124 /* Whether the instruction chain has been scanned already. */
125 int insn_chain_scanned_p;
126 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
127 int ra_needs_full_frame;
128 /* Flags if __builtin_return_address (0) was used. */
129 int ra_need_lr;
130 /* Cache lr_save_p after expansion of builtin_eh_return. */
131 int lr_save_state;
132 /* Whether we need to save the TOC to the reserved stack location in the
133 function prologue. */
134 bool save_toc_in_prologue;
135 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
136 varargs save area. */
137 HOST_WIDE_INT varargs_save_offset;
138 /* Temporary stack slot to use for SDmode copies. This slot is
139 64-bits wide and is allocated early enough so that the offset
140 does not overflow the 16-bit load/store offset field. */
141 rtx sdmode_stack_slot;
142 } machine_function;
144 /* Support targetm.vectorize.builtin_mask_for_load. */
145 static GTY(()) tree altivec_builtin_mask_for_load;
147 /* Set to nonzero once AIX common-mode calls have been defined. */
148 static GTY(()) int common_mode_defined;
150 /* Label number of label created for -mrelocatable, to call to so we can
151 get the address of the GOT section */
152 static int rs6000_pic_labelno;
154 #ifdef USING_ELFOS_H
155 /* Counter for labels which are to be placed in .fixup. */
156 int fixuplabelno = 0;
157 #endif
159 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
160 int dot_symbols;
162 /* Specify the machine mode that pointers have. After generation of rtl, the
163 compiler makes no further distinction between pointers and any other objects
164 of this machine mode. The type is unsigned since not all things that
165 include rs6000.h also include machmode.h. */
166 unsigned rs6000_pmode;
168 /* Width in bits of a pointer. */
169 unsigned rs6000_pointer_size;
171 #ifdef HAVE_AS_GNU_ATTRIBUTE
172 /* Flag whether floating point values have been passed/returned. */
173 static bool rs6000_passes_float;
174 /* Flag whether vector values have been passed/returned. */
175 static bool rs6000_passes_vector;
176 /* Flag whether small (<= 8 byte) structures have been returned. */
177 static bool rs6000_returns_struct;
178 #endif
180 /* Value is TRUE if register/mode pair is acceptable. */
181 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
183 /* Maximum number of registers needed for a given register class and mode. */
184 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
186 /* How many registers are needed for a given register and mode. */
187 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
189 /* Map register number to register class. */
190 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
192 /* Reload functions based on the type and the vector unit. */
193 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
195 static int dbg_cost_ctrl;
197 /* Built in types. */
198 tree rs6000_builtin_types[RS6000_BTI_MAX];
199 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
201 /* Flag to say the TOC is initialized */
202 int toc_initialized;
203 char toc_label_name[10];
205 /* Cached value of rs6000_variable_issue. This is cached in
206 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
207 static short cached_can_issue_more;
209 static GTY(()) section *read_only_data_section;
210 static GTY(()) section *private_data_section;
211 static GTY(()) section *tls_data_section;
212 static GTY(()) section *read_only_private_data_section;
213 static GTY(()) section *sdata2_section;
214 static GTY(()) section *toc_section;
216 struct builtin_description
218 const HOST_WIDE_INT mask;
219 const enum insn_code icode;
220 const char *const name;
221 const enum rs6000_builtins code;
224 /* Describe the vector unit used for modes. */
225 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
226 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
228 /* Register classes for various constraints that are based on the target
229 switches. */
230 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
232 /* Describe the alignment of a vector. */
233 int rs6000_vector_align[NUM_MACHINE_MODES];
235 /* Map selected modes to types for builtins. */
236 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
238 /* What modes to automatically generate reciprocal divide estimate (fre) and
239 reciprocal sqrt (frsqrte) for. */
240 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
242 /* Masks to determine which reciprocal esitmate instructions to generate
243 automatically. */
244 enum rs6000_recip_mask {
245 RECIP_SF_DIV = 0x001, /* Use divide estimate */
246 RECIP_DF_DIV = 0x002,
247 RECIP_V4SF_DIV = 0x004,
248 RECIP_V2DF_DIV = 0x008,
250 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
251 RECIP_DF_RSQRT = 0x020,
252 RECIP_V4SF_RSQRT = 0x040,
253 RECIP_V2DF_RSQRT = 0x080,
255 /* Various combination of flags for -mrecip=xxx. */
256 RECIP_NONE = 0,
257 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
258 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
259 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
261 RECIP_HIGH_PRECISION = RECIP_ALL,
263 /* On low precision machines like the power5, don't enable double precision
264 reciprocal square root estimate, since it isn't accurate enough. */
265 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
268 /* -mrecip options. */
269 static struct
271 const char *string; /* option name */
272 unsigned int mask; /* mask bits to set */
273 } recip_options[] = {
274 { "all", RECIP_ALL },
275 { "none", RECIP_NONE },
276 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
277 | RECIP_V2DF_DIV) },
278 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
279 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
280 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
281 | RECIP_V2DF_RSQRT) },
282 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
283 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
286 /* 2 argument gen function typedef. */
287 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
289 /* Pointer to function (in rs6000-c.c) that can define or undefine target
290 macros that have changed. Languages that don't support the preprocessor
291 don't link in rs6000-c.c, so we can't call it directly. */
292 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
295 /* Target cpu costs. */
297 struct processor_costs {
298 const int mulsi; /* cost of SImode multiplication. */
299 const int mulsi_const; /* cost of SImode multiplication by constant. */
300 const int mulsi_const9; /* cost of SImode mult by short constant. */
301 const int muldi; /* cost of DImode multiplication. */
302 const int divsi; /* cost of SImode division. */
303 const int divdi; /* cost of DImode division. */
304 const int fp; /* cost of simple SFmode and DFmode insns. */
305 const int dmul; /* cost of DFmode multiplication (and fmadd). */
306 const int sdiv; /* cost of SFmode division (fdivs). */
307 const int ddiv; /* cost of DFmode division (fdiv). */
308 const int cache_line_size; /* cache line size in bytes. */
309 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
310 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
311 const int simultaneous_prefetches; /* number of parallel prefetch
312 operations. */
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
320 static const
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
338 /* Instruction size costs on 64bit processors. */
339 static const
340 struct processor_costs size64_cost = {
341 COSTS_N_INSNS (1), /* mulsi */
342 COSTS_N_INSNS (1), /* mulsi_const */
343 COSTS_N_INSNS (1), /* mulsi_const9 */
344 COSTS_N_INSNS (1), /* muldi */
345 COSTS_N_INSNS (1), /* divsi */
346 COSTS_N_INSNS (1), /* divdi */
347 COSTS_N_INSNS (1), /* fp */
348 COSTS_N_INSNS (1), /* dmul */
349 COSTS_N_INSNS (1), /* sdiv */
350 COSTS_N_INSNS (1), /* ddiv */
351 128,
357 /* Instruction costs on RS64A processors. */
358 static const
359 struct processor_costs rs64a_cost = {
360 COSTS_N_INSNS (20), /* mulsi */
361 COSTS_N_INSNS (12), /* mulsi_const */
362 COSTS_N_INSNS (8), /* mulsi_const9 */
363 COSTS_N_INSNS (34), /* muldi */
364 COSTS_N_INSNS (65), /* divsi */
365 COSTS_N_INSNS (67), /* divdi */
366 COSTS_N_INSNS (4), /* fp */
367 COSTS_N_INSNS (4), /* dmul */
368 COSTS_N_INSNS (31), /* sdiv */
369 COSTS_N_INSNS (31), /* ddiv */
370 128, /* cache line size */
371 128, /* l1 cache */
372 2048, /* l2 cache */
373 1, /* streams */
376 /* Instruction costs on MPCCORE processors. */
377 static const
378 struct processor_costs mpccore_cost = {
379 COSTS_N_INSNS (2), /* mulsi */
380 COSTS_N_INSNS (2), /* mulsi_const */
381 COSTS_N_INSNS (2), /* mulsi_const9 */
382 COSTS_N_INSNS (2), /* muldi */
383 COSTS_N_INSNS (6), /* divsi */
384 COSTS_N_INSNS (6), /* divdi */
385 COSTS_N_INSNS (4), /* fp */
386 COSTS_N_INSNS (5), /* dmul */
387 COSTS_N_INSNS (10), /* sdiv */
388 COSTS_N_INSNS (17), /* ddiv */
389 32, /* cache line size */
390 4, /* l1 cache */
391 16, /* l2 cache */
392 1, /* streams */
395 /* Instruction costs on PPC403 processors. */
396 static const
397 struct processor_costs ppc403_cost = {
398 COSTS_N_INSNS (4), /* mulsi */
399 COSTS_N_INSNS (4), /* mulsi_const */
400 COSTS_N_INSNS (4), /* mulsi_const9 */
401 COSTS_N_INSNS (4), /* muldi */
402 COSTS_N_INSNS (33), /* divsi */
403 COSTS_N_INSNS (33), /* divdi */
404 COSTS_N_INSNS (11), /* fp */
405 COSTS_N_INSNS (11), /* dmul */
406 COSTS_N_INSNS (11), /* sdiv */
407 COSTS_N_INSNS (11), /* ddiv */
408 32, /* cache line size */
409 4, /* l1 cache */
410 16, /* l2 cache */
411 1, /* streams */
414 /* Instruction costs on PPC405 processors. */
415 static const
416 struct processor_costs ppc405_cost = {
417 COSTS_N_INSNS (5), /* mulsi */
418 COSTS_N_INSNS (4), /* mulsi_const */
419 COSTS_N_INSNS (3), /* mulsi_const9 */
420 COSTS_N_INSNS (5), /* muldi */
421 COSTS_N_INSNS (35), /* divsi */
422 COSTS_N_INSNS (35), /* divdi */
423 COSTS_N_INSNS (11), /* fp */
424 COSTS_N_INSNS (11), /* dmul */
425 COSTS_N_INSNS (11), /* sdiv */
426 COSTS_N_INSNS (11), /* ddiv */
427 32, /* cache line size */
428 16, /* l1 cache */
429 128, /* l2 cache */
430 1, /* streams */
433 /* Instruction costs on PPC440 processors. */
434 static const
435 struct processor_costs ppc440_cost = {
436 COSTS_N_INSNS (3), /* mulsi */
437 COSTS_N_INSNS (2), /* mulsi_const */
438 COSTS_N_INSNS (2), /* mulsi_const9 */
439 COSTS_N_INSNS (3), /* muldi */
440 COSTS_N_INSNS (34), /* divsi */
441 COSTS_N_INSNS (34), /* divdi */
442 COSTS_N_INSNS (5), /* fp */
443 COSTS_N_INSNS (5), /* dmul */
444 COSTS_N_INSNS (19), /* sdiv */
445 COSTS_N_INSNS (33), /* ddiv */
446 32, /* cache line size */
447 32, /* l1 cache */
448 256, /* l2 cache */
449 1, /* streams */
452 /* Instruction costs on PPC476 processors. */
453 static const
454 struct processor_costs ppc476_cost = {
455 COSTS_N_INSNS (4), /* mulsi */
456 COSTS_N_INSNS (4), /* mulsi_const */
457 COSTS_N_INSNS (4), /* mulsi_const9 */
458 COSTS_N_INSNS (4), /* muldi */
459 COSTS_N_INSNS (11), /* divsi */
460 COSTS_N_INSNS (11), /* divdi */
461 COSTS_N_INSNS (6), /* fp */
462 COSTS_N_INSNS (6), /* dmul */
463 COSTS_N_INSNS (19), /* sdiv */
464 COSTS_N_INSNS (33), /* ddiv */
465 32, /* l1 cache line size */
466 32, /* l1 cache */
467 512, /* l2 cache */
468 1, /* streams */
471 /* Instruction costs on PPC601 processors. */
472 static const
473 struct processor_costs ppc601_cost = {
474 COSTS_N_INSNS (5), /* mulsi */
475 COSTS_N_INSNS (5), /* mulsi_const */
476 COSTS_N_INSNS (5), /* mulsi_const9 */
477 COSTS_N_INSNS (5), /* muldi */
478 COSTS_N_INSNS (36), /* divsi */
479 COSTS_N_INSNS (36), /* divdi */
480 COSTS_N_INSNS (4), /* fp */
481 COSTS_N_INSNS (5), /* dmul */
482 COSTS_N_INSNS (17), /* sdiv */
483 COSTS_N_INSNS (31), /* ddiv */
484 32, /* cache line size */
485 32, /* l1 cache */
486 256, /* l2 cache */
487 1, /* streams */
490 /* Instruction costs on PPC603 processors. */
491 static const
492 struct processor_costs ppc603_cost = {
493 COSTS_N_INSNS (5), /* mulsi */
494 COSTS_N_INSNS (3), /* mulsi_const */
495 COSTS_N_INSNS (2), /* mulsi_const9 */
496 COSTS_N_INSNS (5), /* muldi */
497 COSTS_N_INSNS (37), /* divsi */
498 COSTS_N_INSNS (37), /* divdi */
499 COSTS_N_INSNS (3), /* fp */
500 COSTS_N_INSNS (4), /* dmul */
501 COSTS_N_INSNS (18), /* sdiv */
502 COSTS_N_INSNS (33), /* ddiv */
503 32, /* cache line size */
504 8, /* l1 cache */
505 64, /* l2 cache */
506 1, /* streams */
509 /* Instruction costs on PPC604 processors. */
510 static const
511 struct processor_costs ppc604_cost = {
512 COSTS_N_INSNS (4), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (4), /* mulsi_const9 */
515 COSTS_N_INSNS (4), /* muldi */
516 COSTS_N_INSNS (20), /* divsi */
517 COSTS_N_INSNS (20), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (18), /* sdiv */
521 COSTS_N_INSNS (32), /* ddiv */
522 32, /* cache line size */
523 16, /* l1 cache */
524 512, /* l2 cache */
525 1, /* streams */
528 /* Instruction costs on PPC604e processors. */
529 static const
530 struct processor_costs ppc604e_cost = {
531 COSTS_N_INSNS (2), /* mulsi */
532 COSTS_N_INSNS (2), /* mulsi_const */
533 COSTS_N_INSNS (2), /* mulsi_const9 */
534 COSTS_N_INSNS (2), /* muldi */
535 COSTS_N_INSNS (20), /* divsi */
536 COSTS_N_INSNS (20), /* divdi */
537 COSTS_N_INSNS (3), /* fp */
538 COSTS_N_INSNS (3), /* dmul */
539 COSTS_N_INSNS (18), /* sdiv */
540 COSTS_N_INSNS (32), /* ddiv */
541 32, /* cache line size */
542 32, /* l1 cache */
543 1024, /* l2 cache */
544 1, /* streams */
547 /* Instruction costs on PPC620 processors. */
548 static const
549 struct processor_costs ppc620_cost = {
550 COSTS_N_INSNS (5), /* mulsi */
551 COSTS_N_INSNS (4), /* mulsi_const */
552 COSTS_N_INSNS (3), /* mulsi_const9 */
553 COSTS_N_INSNS (7), /* muldi */
554 COSTS_N_INSNS (21), /* divsi */
555 COSTS_N_INSNS (37), /* divdi */
556 COSTS_N_INSNS (3), /* fp */
557 COSTS_N_INSNS (3), /* dmul */
558 COSTS_N_INSNS (18), /* sdiv */
559 COSTS_N_INSNS (32), /* ddiv */
560 128, /* cache line size */
561 32, /* l1 cache */
562 1024, /* l2 cache */
563 1, /* streams */
566 /* Instruction costs on PPC630 processors. */
567 static const
568 struct processor_costs ppc630_cost = {
569 COSTS_N_INSNS (5), /* mulsi */
570 COSTS_N_INSNS (4), /* mulsi_const */
571 COSTS_N_INSNS (3), /* mulsi_const9 */
572 COSTS_N_INSNS (7), /* muldi */
573 COSTS_N_INSNS (21), /* divsi */
574 COSTS_N_INSNS (37), /* divdi */
575 COSTS_N_INSNS (3), /* fp */
576 COSTS_N_INSNS (3), /* dmul */
577 COSTS_N_INSNS (17), /* sdiv */
578 COSTS_N_INSNS (21), /* ddiv */
579 128, /* cache line size */
580 64, /* l1 cache */
581 1024, /* l2 cache */
582 1, /* streams */
585 /* Instruction costs on Cell processor. */
586 /* COSTS_N_INSNS (1) ~ one add. */
587 static const
588 struct processor_costs ppccell_cost = {
589 COSTS_N_INSNS (9/2)+2, /* mulsi */
590 COSTS_N_INSNS (6/2), /* mulsi_const */
591 COSTS_N_INSNS (6/2), /* mulsi_const9 */
592 COSTS_N_INSNS (15/2)+2, /* muldi */
593 COSTS_N_INSNS (38/2), /* divsi */
594 COSTS_N_INSNS (70/2), /* divdi */
595 COSTS_N_INSNS (10/2), /* fp */
596 COSTS_N_INSNS (10/2), /* dmul */
597 COSTS_N_INSNS (74/2), /* sdiv */
598 COSTS_N_INSNS (74/2), /* ddiv */
599 128, /* cache line size */
600 32, /* l1 cache */
601 512, /* l2 cache */
602 6, /* streams */
605 /* Instruction costs on PPC750 and PPC7400 processors. */
606 static const
607 struct processor_costs ppc750_cost = {
608 COSTS_N_INSNS (5), /* mulsi */
609 COSTS_N_INSNS (3), /* mulsi_const */
610 COSTS_N_INSNS (2), /* mulsi_const9 */
611 COSTS_N_INSNS (5), /* muldi */
612 COSTS_N_INSNS (17), /* divsi */
613 COSTS_N_INSNS (17), /* divdi */
614 COSTS_N_INSNS (3), /* fp */
615 COSTS_N_INSNS (3), /* dmul */
616 COSTS_N_INSNS (17), /* sdiv */
617 COSTS_N_INSNS (31), /* ddiv */
618 32, /* cache line size */
619 32, /* l1 cache */
620 512, /* l2 cache */
621 1, /* streams */
624 /* Instruction costs on PPC7450 processors. */
625 static const
626 struct processor_costs ppc7450_cost = {
627 COSTS_N_INSNS (4), /* mulsi */
628 COSTS_N_INSNS (3), /* mulsi_const */
629 COSTS_N_INSNS (3), /* mulsi_const9 */
630 COSTS_N_INSNS (4), /* muldi */
631 COSTS_N_INSNS (23), /* divsi */
632 COSTS_N_INSNS (23), /* divdi */
633 COSTS_N_INSNS (5), /* fp */
634 COSTS_N_INSNS (5), /* dmul */
635 COSTS_N_INSNS (21), /* sdiv */
636 COSTS_N_INSNS (35), /* ddiv */
637 32, /* cache line size */
638 32, /* l1 cache */
639 1024, /* l2 cache */
640 1, /* streams */
643 /* Instruction costs on PPC8540 processors. */
644 static const
645 struct processor_costs ppc8540_cost = {
646 COSTS_N_INSNS (4), /* mulsi */
647 COSTS_N_INSNS (4), /* mulsi_const */
648 COSTS_N_INSNS (4), /* mulsi_const9 */
649 COSTS_N_INSNS (4), /* muldi */
650 COSTS_N_INSNS (19), /* divsi */
651 COSTS_N_INSNS (19), /* divdi */
652 COSTS_N_INSNS (4), /* fp */
653 COSTS_N_INSNS (4), /* dmul */
654 COSTS_N_INSNS (29), /* sdiv */
655 COSTS_N_INSNS (29), /* ddiv */
656 32, /* cache line size */
657 32, /* l1 cache */
658 256, /* l2 cache */
659 1, /* prefetch streams /*/
662 /* Instruction costs on E300C2 and E300C3 cores. */
663 static const
664 struct processor_costs ppce300c2c3_cost = {
665 COSTS_N_INSNS (4), /* mulsi */
666 COSTS_N_INSNS (4), /* mulsi_const */
667 COSTS_N_INSNS (4), /* mulsi_const9 */
668 COSTS_N_INSNS (4), /* muldi */
669 COSTS_N_INSNS (19), /* divsi */
670 COSTS_N_INSNS (19), /* divdi */
671 COSTS_N_INSNS (3), /* fp */
672 COSTS_N_INSNS (4), /* dmul */
673 COSTS_N_INSNS (18), /* sdiv */
674 COSTS_N_INSNS (33), /* ddiv */
676 16, /* l1 cache */
677 16, /* l2 cache */
678 1, /* prefetch streams /*/
681 /* Instruction costs on PPCE500MC processors. */
682 static const
683 struct processor_costs ppce500mc_cost = {
684 COSTS_N_INSNS (4), /* mulsi */
685 COSTS_N_INSNS (4), /* mulsi_const */
686 COSTS_N_INSNS (4), /* mulsi_const9 */
687 COSTS_N_INSNS (4), /* muldi */
688 COSTS_N_INSNS (14), /* divsi */
689 COSTS_N_INSNS (14), /* divdi */
690 COSTS_N_INSNS (8), /* fp */
691 COSTS_N_INSNS (10), /* dmul */
692 COSTS_N_INSNS (36), /* sdiv */
693 COSTS_N_INSNS (66), /* ddiv */
694 64, /* cache line size */
695 32, /* l1 cache */
696 128, /* l2 cache */
697 1, /* prefetch streams /*/
700 /* Instruction costs on PPCE500MC64 processors. */
701 static const
702 struct processor_costs ppce500mc64_cost = {
703 COSTS_N_INSNS (4), /* mulsi */
704 COSTS_N_INSNS (4), /* mulsi_const */
705 COSTS_N_INSNS (4), /* mulsi_const9 */
706 COSTS_N_INSNS (4), /* muldi */
707 COSTS_N_INSNS (14), /* divsi */
708 COSTS_N_INSNS (14), /* divdi */
709 COSTS_N_INSNS (4), /* fp */
710 COSTS_N_INSNS (10), /* dmul */
711 COSTS_N_INSNS (36), /* sdiv */
712 COSTS_N_INSNS (66), /* ddiv */
713 64, /* cache line size */
714 32, /* l1 cache */
715 128, /* l2 cache */
716 1, /* prefetch streams /*/
719 /* Instruction costs on PPCE5500 processors. */
720 static const
721 struct processor_costs ppce5500_cost = {
722 COSTS_N_INSNS (5), /* mulsi */
723 COSTS_N_INSNS (5), /* mulsi_const */
724 COSTS_N_INSNS (4), /* mulsi_const9 */
725 COSTS_N_INSNS (5), /* muldi */
726 COSTS_N_INSNS (14), /* divsi */
727 COSTS_N_INSNS (14), /* divdi */
728 COSTS_N_INSNS (7), /* fp */
729 COSTS_N_INSNS (10), /* dmul */
730 COSTS_N_INSNS (36), /* sdiv */
731 COSTS_N_INSNS (66), /* ddiv */
732 64, /* cache line size */
733 32, /* l1 cache */
734 128, /* l2 cache */
735 1, /* prefetch streams /*/
738 /* Instruction costs on PPCE6500 processors. */
739 static const
740 struct processor_costs ppce6500_cost = {
741 COSTS_N_INSNS (5), /* mulsi */
742 COSTS_N_INSNS (5), /* mulsi_const */
743 COSTS_N_INSNS (4), /* mulsi_const9 */
744 COSTS_N_INSNS (5), /* muldi */
745 COSTS_N_INSNS (14), /* divsi */
746 COSTS_N_INSNS (14), /* divdi */
747 COSTS_N_INSNS (7), /* fp */
748 COSTS_N_INSNS (10), /* dmul */
749 COSTS_N_INSNS (36), /* sdiv */
750 COSTS_N_INSNS (66), /* ddiv */
751 64, /* cache line size */
752 32, /* l1 cache */
753 128, /* l2 cache */
754 1, /* prefetch streams /*/
757 /* Instruction costs on AppliedMicro Titan processors. */
758 static const
759 struct processor_costs titan_cost = {
760 COSTS_N_INSNS (5), /* mulsi */
761 COSTS_N_INSNS (5), /* mulsi_const */
762 COSTS_N_INSNS (5), /* mulsi_const9 */
763 COSTS_N_INSNS (5), /* muldi */
764 COSTS_N_INSNS (18), /* divsi */
765 COSTS_N_INSNS (18), /* divdi */
766 COSTS_N_INSNS (10), /* fp */
767 COSTS_N_INSNS (10), /* dmul */
768 COSTS_N_INSNS (46), /* sdiv */
769 COSTS_N_INSNS (72), /* ddiv */
770 32, /* cache line size */
771 32, /* l1 cache */
772 512, /* l2 cache */
773 1, /* prefetch streams /*/
776 /* Instruction costs on POWER4 and POWER5 processors. */
777 static const
778 struct processor_costs power4_cost = {
779 COSTS_N_INSNS (3), /* mulsi */
780 COSTS_N_INSNS (2), /* mulsi_const */
781 COSTS_N_INSNS (2), /* mulsi_const9 */
782 COSTS_N_INSNS (4), /* muldi */
783 COSTS_N_INSNS (18), /* divsi */
784 COSTS_N_INSNS (34), /* divdi */
785 COSTS_N_INSNS (3), /* fp */
786 COSTS_N_INSNS (3), /* dmul */
787 COSTS_N_INSNS (17), /* sdiv */
788 COSTS_N_INSNS (17), /* ddiv */
789 128, /* cache line size */
790 32, /* l1 cache */
791 1024, /* l2 cache */
792 8, /* prefetch streams /*/
795 /* Instruction costs on POWER6 processors. */
796 static const
797 struct processor_costs power6_cost = {
798 COSTS_N_INSNS (8), /* mulsi */
799 COSTS_N_INSNS (8), /* mulsi_const */
800 COSTS_N_INSNS (8), /* mulsi_const9 */
801 COSTS_N_INSNS (8), /* muldi */
802 COSTS_N_INSNS (22), /* divsi */
803 COSTS_N_INSNS (28), /* divdi */
804 COSTS_N_INSNS (3), /* fp */
805 COSTS_N_INSNS (3), /* dmul */
806 COSTS_N_INSNS (13), /* sdiv */
807 COSTS_N_INSNS (16), /* ddiv */
808 128, /* cache line size */
809 64, /* l1 cache */
810 2048, /* l2 cache */
811 16, /* prefetch streams */
814 /* Instruction costs on POWER7 processors. */
815 static const
816 struct processor_costs power7_cost = {
817 COSTS_N_INSNS (2), /* mulsi */
818 COSTS_N_INSNS (2), /* mulsi_const */
819 COSTS_N_INSNS (2), /* mulsi_const9 */
820 COSTS_N_INSNS (2), /* muldi */
821 COSTS_N_INSNS (18), /* divsi */
822 COSTS_N_INSNS (34), /* divdi */
823 COSTS_N_INSNS (3), /* fp */
824 COSTS_N_INSNS (3), /* dmul */
825 COSTS_N_INSNS (13), /* sdiv */
826 COSTS_N_INSNS (16), /* ddiv */
827 128, /* cache line size */
828 32, /* l1 cache */
829 256, /* l2 cache */
830 12, /* prefetch streams */
833 /* Instruction costs on POWER A2 processors. */
834 static const
835 struct processor_costs ppca2_cost = {
836 COSTS_N_INSNS (16), /* mulsi */
837 COSTS_N_INSNS (16), /* mulsi_const */
838 COSTS_N_INSNS (16), /* mulsi_const9 */
839 COSTS_N_INSNS (16), /* muldi */
840 COSTS_N_INSNS (22), /* divsi */
841 COSTS_N_INSNS (28), /* divdi */
842 COSTS_N_INSNS (3), /* fp */
843 COSTS_N_INSNS (3), /* dmul */
844 COSTS_N_INSNS (59), /* sdiv */
845 COSTS_N_INSNS (72), /* ddiv */
847 16, /* l1 cache */
848 2048, /* l2 cache */
849 16, /* prefetch streams */
853 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
854 #undef RS6000_BUILTIN_1
855 #undef RS6000_BUILTIN_2
856 #undef RS6000_BUILTIN_3
857 #undef RS6000_BUILTIN_A
858 #undef RS6000_BUILTIN_D
859 #undef RS6000_BUILTIN_E
860 #undef RS6000_BUILTIN_P
861 #undef RS6000_BUILTIN_Q
862 #undef RS6000_BUILTIN_S
863 #undef RS6000_BUILTIN_X
865 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
866 { NAME, ICODE, MASK, ATTR },
868 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
869 { NAME, ICODE, MASK, ATTR },
871 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
872 { NAME, ICODE, MASK, ATTR },
874 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
875 { NAME, ICODE, MASK, ATTR },
877 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
878 { NAME, ICODE, MASK, ATTR },
880 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
881 { NAME, ICODE, MASK, ATTR },
883 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
884 { NAME, ICODE, MASK, ATTR },
886 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
887 { NAME, ICODE, MASK, ATTR },
889 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
890 { NAME, ICODE, MASK, ATTR },
892 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
893 { NAME, ICODE, MASK, ATTR },
895 struct rs6000_builtin_info_type {
896 const char *name;
897 const enum insn_code icode;
898 const HOST_WIDE_INT mask;
899 const unsigned attr;
902 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
904 #include "rs6000-builtin.def"
907 #undef RS6000_BUILTIN_1
908 #undef RS6000_BUILTIN_2
909 #undef RS6000_BUILTIN_3
910 #undef RS6000_BUILTIN_A
911 #undef RS6000_BUILTIN_D
912 #undef RS6000_BUILTIN_E
913 #undef RS6000_BUILTIN_P
914 #undef RS6000_BUILTIN_Q
915 #undef RS6000_BUILTIN_S
916 #undef RS6000_BUILTIN_X
918 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
919 static tree (*rs6000_veclib_handler) (tree, tree, tree);
922 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
923 static bool spe_func_has_64bit_regs_p (void);
924 static struct machine_function * rs6000_init_machine_status (void);
925 static int rs6000_ra_ever_killed (void);
926 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
927 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
928 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
929 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
930 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
931 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
932 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
933 static int rs6000_debug_address_cost (rtx, enum machine_mode, addr_space_t,
934 bool);
935 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
936 static bool is_microcoded_insn (rtx);
937 static bool is_nonpipeline_insn (rtx);
938 static bool is_cracked_insn (rtx);
939 static bool is_load_insn (rtx, rtx *);
940 static bool is_store_insn (rtx, rtx *);
941 static bool set_to_load_agen (rtx,rtx);
942 static bool insn_terminates_group_p (rtx , enum group_termination);
943 static bool insn_must_be_first_in_group (rtx);
944 static bool insn_must_be_last_in_group (rtx);
945 static void altivec_init_builtins (void);
946 static tree builtin_function_type (enum machine_mode, enum machine_mode,
947 enum machine_mode, enum machine_mode,
948 enum rs6000_builtins, const char *name);
949 static void rs6000_common_init_builtins (void);
950 static void paired_init_builtins (void);
951 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
952 static void spe_init_builtins (void);
953 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
954 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
955 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
956 static rs6000_stack_t *rs6000_stack_info (void);
957 static void is_altivec_return_reg (rtx, void *);
958 int easy_vector_constant (rtx, enum machine_mode);
959 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
960 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
961 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
962 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
963 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
964 bool, bool);
965 #if TARGET_MACHO
966 static void macho_branch_islands (void);
967 #endif
968 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
969 int, int *);
970 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
971 int, int, int *);
972 static bool rs6000_mode_dependent_address (const_rtx);
973 static bool rs6000_debug_mode_dependent_address (const_rtx);
974 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
975 enum machine_mode, rtx);
976 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
977 enum machine_mode,
978 rtx);
979 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
980 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
981 enum reg_class);
982 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
983 enum machine_mode);
984 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
985 enum reg_class,
986 enum machine_mode);
987 static bool rs6000_cannot_change_mode_class (enum machine_mode,
988 enum machine_mode,
989 enum reg_class);
990 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
991 enum machine_mode,
992 enum reg_class);
993 static bool rs6000_save_toc_in_prologue_p (void);
995 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
996 int, int *)
997 = rs6000_legitimize_reload_address;
999 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1000 = rs6000_mode_dependent_address;
1002 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1003 enum machine_mode, rtx)
1004 = rs6000_secondary_reload_class;
1006 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1007 = rs6000_preferred_reload_class;
1009 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1010 enum machine_mode)
1011 = rs6000_secondary_memory_needed;
1013 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1014 enum machine_mode,
1015 enum reg_class)
1016 = rs6000_cannot_change_mode_class;
1018 const int INSN_NOT_AVAILABLE = -1;
1020 static void rs6000_print_isa_options (FILE *, int, const char *,
1021 HOST_WIDE_INT);
1022 static void rs6000_print_builtin_options (FILE *, int, const char *,
1023 HOST_WIDE_INT);
1025 /* Hash table stuff for keeping track of TOC entries. */
1027 struct GTY(()) toc_hash_struct
1029 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1030 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1031 rtx key;
1032 enum machine_mode key_mode;
1033 int labelno;
1036 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1038 /* Hash table to keep track of the argument types for builtin functions. */
1040 struct GTY(()) builtin_hash_struct
1042 tree type;
1043 enum machine_mode mode[4]; /* return value + 3 arguments. */
1044 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1047 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1050 /* Default register names. */
1051 char rs6000_reg_names[][8] =
1053 "0", "1", "2", "3", "4", "5", "6", "7",
1054 "8", "9", "10", "11", "12", "13", "14", "15",
1055 "16", "17", "18", "19", "20", "21", "22", "23",
1056 "24", "25", "26", "27", "28", "29", "30", "31",
1057 "0", "1", "2", "3", "4", "5", "6", "7",
1058 "8", "9", "10", "11", "12", "13", "14", "15",
1059 "16", "17", "18", "19", "20", "21", "22", "23",
1060 "24", "25", "26", "27", "28", "29", "30", "31",
1061 "mq", "lr", "ctr","ap",
1062 "0", "1", "2", "3", "4", "5", "6", "7",
1063 "ca",
1064 /* AltiVec registers. */
1065 "0", "1", "2", "3", "4", "5", "6", "7",
1066 "8", "9", "10", "11", "12", "13", "14", "15",
1067 "16", "17", "18", "19", "20", "21", "22", "23",
1068 "24", "25", "26", "27", "28", "29", "30", "31",
1069 "vrsave", "vscr",
1070 /* SPE registers. */
1071 "spe_acc", "spefscr",
1072 /* Soft frame pointer. */
1073 "sfp"
1076 #ifdef TARGET_REGNAMES
1077 static const char alt_reg_names[][8] =
1079 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1080 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1081 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1082 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1083 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1084 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1085 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1086 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1087 "mq", "lr", "ctr", "ap",
1088 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1089 "ca",
1090 /* AltiVec registers. */
1091 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1092 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1093 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1094 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1095 "vrsave", "vscr",
1096 /* SPE registers. */
1097 "spe_acc", "spefscr",
1098 /* Soft frame pointer. */
1099 "sfp"
1101 #endif
1103 /* Table of valid machine attributes. */
1105 static const struct attribute_spec rs6000_attribute_table[] =
1107 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1108 affects_type_identity } */
1109 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1110 false },
1111 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1112 false },
1113 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1114 false },
1115 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1116 false },
1117 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1118 false },
1119 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1120 SUBTARGET_ATTRIBUTE_TABLE,
1121 #endif
1122 { NULL, 0, 0, false, false, false, NULL, false }
1125 #ifndef TARGET_PROFILE_KERNEL
1126 #define TARGET_PROFILE_KERNEL 0
1127 #endif
1129 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1130 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1132 /* Initialize the GCC target structure. */
1133 #undef TARGET_ATTRIBUTE_TABLE
1134 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1135 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1136 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1137 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1138 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1140 #undef TARGET_ASM_ALIGNED_DI_OP
1141 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1143 /* Default unaligned ops are only provided for ELF. Find the ops needed
1144 for non-ELF systems. */
1145 #ifndef OBJECT_FORMAT_ELF
1146 #if TARGET_XCOFF
1147 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1148 64-bit targets. */
1149 #undef TARGET_ASM_UNALIGNED_HI_OP
1150 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1151 #undef TARGET_ASM_UNALIGNED_SI_OP
1152 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1153 #undef TARGET_ASM_UNALIGNED_DI_OP
1154 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1155 #else
1156 /* For Darwin. */
1157 #undef TARGET_ASM_UNALIGNED_HI_OP
1158 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1159 #undef TARGET_ASM_UNALIGNED_SI_OP
1160 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1161 #undef TARGET_ASM_UNALIGNED_DI_OP
1162 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1163 #undef TARGET_ASM_ALIGNED_DI_OP
1164 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1165 #endif
1166 #endif
1168 /* This hook deals with fixups for relocatable code and DI-mode objects
1169 in 64-bit code. */
1170 #undef TARGET_ASM_INTEGER
1171 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1173 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1174 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1175 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1176 #endif
1178 #undef TARGET_SET_UP_BY_PROLOGUE
1179 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1181 #undef TARGET_HAVE_TLS
1182 #define TARGET_HAVE_TLS HAVE_AS_TLS
1184 #undef TARGET_CANNOT_FORCE_CONST_MEM
1185 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1187 #undef TARGET_DELEGITIMIZE_ADDRESS
1188 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1190 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1191 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1193 #undef TARGET_ASM_FUNCTION_PROLOGUE
1194 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1195 #undef TARGET_ASM_FUNCTION_EPILOGUE
1196 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1198 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1199 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1201 #undef TARGET_LEGITIMIZE_ADDRESS
1202 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1204 #undef TARGET_SCHED_VARIABLE_ISSUE
1205 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1207 #undef TARGET_SCHED_ISSUE_RATE
1208 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1209 #undef TARGET_SCHED_ADJUST_COST
1210 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1211 #undef TARGET_SCHED_ADJUST_PRIORITY
1212 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1213 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1214 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1215 #undef TARGET_SCHED_INIT
1216 #define TARGET_SCHED_INIT rs6000_sched_init
1217 #undef TARGET_SCHED_FINISH
1218 #define TARGET_SCHED_FINISH rs6000_sched_finish
1219 #undef TARGET_SCHED_REORDER
1220 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1221 #undef TARGET_SCHED_REORDER2
1222 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1224 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1225 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1227 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1228 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1230 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1231 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1232 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1233 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1234 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1235 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1236 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1237 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1239 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1240 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1241 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1242 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1243 rs6000_builtin_support_vector_misalignment
1244 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1245 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1246 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1247 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1248 rs6000_builtin_vectorization_cost
1249 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1250 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1251 rs6000_preferred_simd_mode
1252 #undef TARGET_VECTORIZE_INIT_COST
1253 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1254 #undef TARGET_VECTORIZE_ADD_STMT_COST
1255 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1256 #undef TARGET_VECTORIZE_FINISH_COST
1257 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1258 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1259 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1261 #undef TARGET_INIT_BUILTINS
1262 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1263 #undef TARGET_BUILTIN_DECL
1264 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1266 #undef TARGET_EXPAND_BUILTIN
1267 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1269 #undef TARGET_MANGLE_TYPE
1270 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1272 #undef TARGET_INIT_LIBFUNCS
1273 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1275 #if TARGET_MACHO
1276 #undef TARGET_BINDS_LOCAL_P
1277 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1278 #endif
1280 #undef TARGET_MS_BITFIELD_LAYOUT_P
1281 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1283 #undef TARGET_ASM_OUTPUT_MI_THUNK
1284 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1286 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1287 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1289 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1290 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1292 #undef TARGET_INVALID_WITHIN_DOLOOP
1293 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1295 #undef TARGET_REGISTER_MOVE_COST
1296 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1297 #undef TARGET_MEMORY_MOVE_COST
1298 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1299 #undef TARGET_RTX_COSTS
1300 #define TARGET_RTX_COSTS rs6000_rtx_costs
1301 #undef TARGET_ADDRESS_COST
1302 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1304 #undef TARGET_DWARF_REGISTER_SPAN
1305 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1307 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1308 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1310 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1311 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1313 /* On rs6000, function arguments are promoted, as are function return
1314 values. */
1315 #undef TARGET_PROMOTE_FUNCTION_MODE
1316 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1318 #undef TARGET_RETURN_IN_MEMORY
1319 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1321 #undef TARGET_SETUP_INCOMING_VARARGS
1322 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1324 /* Always strict argument naming on rs6000. */
1325 #undef TARGET_STRICT_ARGUMENT_NAMING
1326 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1327 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1328 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1329 #undef TARGET_SPLIT_COMPLEX_ARG
1330 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1331 #undef TARGET_MUST_PASS_IN_STACK
1332 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1333 #undef TARGET_PASS_BY_REFERENCE
1334 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1335 #undef TARGET_ARG_PARTIAL_BYTES
1336 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1337 #undef TARGET_FUNCTION_ARG_ADVANCE
1338 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1339 #undef TARGET_FUNCTION_ARG
1340 #define TARGET_FUNCTION_ARG rs6000_function_arg
1341 #undef TARGET_FUNCTION_ARG_BOUNDARY
1342 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1344 #undef TARGET_BUILD_BUILTIN_VA_LIST
1345 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1347 #undef TARGET_EXPAND_BUILTIN_VA_START
1348 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1350 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1351 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1353 #undef TARGET_EH_RETURN_FILTER_MODE
1354 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1356 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1357 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1359 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1360 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1362 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1363 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1365 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1366 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1368 #undef TARGET_OPTION_OVERRIDE
1369 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1371 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1372 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1373 rs6000_builtin_vectorized_function
1375 #if !TARGET_MACHO
1376 #undef TARGET_STACK_PROTECT_FAIL
1377 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1378 #endif
1380 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1381 The PowerPC architecture requires only weak consistency among
1382 processors--that is, memory accesses between processors need not be
1383 sequentially consistent and memory accesses among processors can occur
1384 in any order. The ability to order memory accesses weakly provides
1385 opportunities for more efficient use of the system bus. Unless a
1386 dependency exists, the 604e allows read operations to precede store
1387 operations. */
1388 #undef TARGET_RELAXED_ORDERING
1389 #define TARGET_RELAXED_ORDERING true
1391 #ifdef HAVE_AS_TLS
1392 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1393 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1394 #endif
1396 /* Use a 32-bit anchor range. This leads to sequences like:
1398 addis tmp,anchor,high
1399 add dest,tmp,low
1401 where tmp itself acts as an anchor, and can be shared between
1402 accesses to the same 64k page. */
1403 #undef TARGET_MIN_ANCHOR_OFFSET
1404 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1405 #undef TARGET_MAX_ANCHOR_OFFSET
1406 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1407 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1408 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1409 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1410 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1412 #undef TARGET_BUILTIN_RECIPROCAL
1413 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1415 #undef TARGET_EXPAND_TO_RTL_HOOK
1416 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1418 #undef TARGET_INSTANTIATE_DECLS
1419 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1421 #undef TARGET_SECONDARY_RELOAD
1422 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1424 #undef TARGET_LEGITIMATE_ADDRESS_P
1425 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1427 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1428 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1430 #undef TARGET_CAN_ELIMINATE
1431 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1433 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1434 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1436 #undef TARGET_TRAMPOLINE_INIT
1437 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1439 #undef TARGET_FUNCTION_VALUE
1440 #define TARGET_FUNCTION_VALUE rs6000_function_value
1442 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1443 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1445 #undef TARGET_OPTION_SAVE
1446 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1448 #undef TARGET_OPTION_RESTORE
1449 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1451 #undef TARGET_OPTION_PRINT
1452 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1454 #undef TARGET_CAN_INLINE_P
1455 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1457 #undef TARGET_SET_CURRENT_FUNCTION
1458 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1460 #undef TARGET_LEGITIMATE_CONSTANT_P
1461 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1463 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1464 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1467 /* Processor table. */
1468 struct rs6000_ptt
1470 const char *const name; /* Canonical processor name. */
1471 const enum processor_type processor; /* Processor type enum value. */
1472 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1475 static struct rs6000_ptt const processor_target_table[] =
1477 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1478 #include "rs6000-cpus.def"
1479 #undef RS6000_CPU
1482 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1483 name is invalid. */
1485 static int
1486 rs6000_cpu_name_lookup (const char *name)
1488 size_t i;
1490 if (name != NULL)
1492 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1493 if (! strcmp (name, processor_target_table[i].name))
1494 return (int)i;
1497 return -1;
1501 /* Return number of consecutive hard regs needed starting at reg REGNO
1502 to hold something of mode MODE.
1503 This is ordinarily the length in words of a value of mode MODE
1504 but can be less for certain modes in special long registers.
1506 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1507 scalar instructions. The upper 32 bits are only available to the
1508 SIMD instructions.
1510 POWER and PowerPC GPRs hold 32 bits worth;
1511 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1513 static int
1514 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1516 unsigned HOST_WIDE_INT reg_size;
1518 if (FP_REGNO_P (regno))
1519 reg_size = (VECTOR_MEM_VSX_P (mode)
1520 ? UNITS_PER_VSX_WORD
1521 : UNITS_PER_FP_WORD);
1523 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1524 reg_size = UNITS_PER_SPE_WORD;
1526 else if (ALTIVEC_REGNO_P (regno))
1527 reg_size = UNITS_PER_ALTIVEC_WORD;
1529 /* The value returned for SCmode in the E500 double case is 2 for
1530 ABI compatibility; storing an SCmode value in a single register
1531 would require function_arg and rs6000_spe_function_arg to handle
1532 SCmode so as to pass the value correctly in a pair of
1533 registers. */
1534 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1535 && !DECIMAL_FLOAT_MODE_P (mode))
1536 reg_size = UNITS_PER_FP_WORD;
1538 else
1539 reg_size = UNITS_PER_WORD;
1541 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1544 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1545 MODE. */
1546 static int
1547 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1549 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1551 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1552 implementations. Don't allow an item to be split between a FP register
1553 and an Altivec register. */
1554 if (VECTOR_MEM_VSX_P (mode))
1556 if (FP_REGNO_P (regno))
1557 return FP_REGNO_P (last_regno);
1559 if (ALTIVEC_REGNO_P (regno))
1560 return ALTIVEC_REGNO_P (last_regno);
1563 /* The GPRs can hold any mode, but values bigger than one register
1564 cannot go past R31. */
1565 if (INT_REGNO_P (regno))
1566 return INT_REGNO_P (last_regno);
1568 /* The float registers (except for VSX vector modes) can only hold floating
1569 modes and DImode. This excludes the 32-bit decimal float mode for
1570 now. */
1571 if (FP_REGNO_P (regno))
1573 if (SCALAR_FLOAT_MODE_P (mode)
1574 && (mode != TDmode || (regno % 2) == 0)
1575 && FP_REGNO_P (last_regno))
1576 return 1;
1578 if (GET_MODE_CLASS (mode) == MODE_INT
1579 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1580 return 1;
1582 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1583 && PAIRED_VECTOR_MODE (mode))
1584 return 1;
1586 return 0;
1589 /* The CR register can only hold CC modes. */
1590 if (CR_REGNO_P (regno))
1591 return GET_MODE_CLASS (mode) == MODE_CC;
1593 if (CA_REGNO_P (regno))
1594 return mode == BImode;
1596 /* AltiVec only in AldyVec registers. */
1597 if (ALTIVEC_REGNO_P (regno))
1598 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1600 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1601 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1602 return 1;
1604 /* We cannot put TImode anywhere except general register and it must be able
1605 to fit within the register set. In the future, allow TImode in the
1606 Altivec or VSX registers. */
1608 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1611 /* Print interesting facts about registers. */
1612 static void
1613 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1615 int r, m;
1617 for (r = first_regno; r <= last_regno; ++r)
1619 const char *comma = "";
1620 int len;
1622 if (first_regno == last_regno)
1623 fprintf (stderr, "%s:\t", reg_name);
1624 else
1625 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1627 len = 8;
1628 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1629 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1631 if (len > 70)
1633 fprintf (stderr, ",\n\t");
1634 len = 8;
1635 comma = "";
1638 if (rs6000_hard_regno_nregs[m][r] > 1)
1639 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1640 rs6000_hard_regno_nregs[m][r]);
1641 else
1642 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1644 comma = ", ";
1647 if (call_used_regs[r])
1649 if (len > 70)
1651 fprintf (stderr, ",\n\t");
1652 len = 8;
1653 comma = "";
1656 len += fprintf (stderr, "%s%s", comma, "call-used");
1657 comma = ", ";
1660 if (fixed_regs[r])
1662 if (len > 70)
1664 fprintf (stderr, ",\n\t");
1665 len = 8;
1666 comma = "";
1669 len += fprintf (stderr, "%s%s", comma, "fixed");
1670 comma = ", ";
1673 if (len > 70)
1675 fprintf (stderr, ",\n\t");
1676 comma = "";
1679 fprintf (stderr, "%sregno = %d\n", comma, r);
1683 #define DEBUG_FMT_ID "%-32s= "
1684 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1685 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1686 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1688 /* Print various interesting information with -mdebug=reg. */
1689 static void
1690 rs6000_debug_reg_global (void)
1692 static const char *const tf[2] = { "false", "true" };
1693 const char *nl = (const char *)0;
1694 int m;
1695 char costly_num[20];
1696 char nop_num[20];
1697 char flags_buffer[40];
1698 const char *costly_str;
1699 const char *nop_str;
1700 const char *trace_str;
1701 const char *abi_str;
1702 const char *cmodel_str;
1703 struct cl_target_option cl_opts;
1705 /* Map enum rs6000_vector to string. */
1706 static const char *rs6000_debug_vector_unit[] = {
1707 "none",
1708 "altivec",
1709 "vsx",
1710 "paired",
1711 "spe",
1712 "other"
1715 fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1716 LAST_VIRTUAL_REGISTER);
1717 rs6000_debug_reg_print (0, 31, "gr");
1718 rs6000_debug_reg_print (32, 63, "fp");
1719 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1720 LAST_ALTIVEC_REGNO,
1721 "vs");
1722 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1723 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1724 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1725 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1726 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1727 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1728 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1729 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1731 fprintf (stderr,
1732 "\n"
1733 "d reg_class = %s\n"
1734 "f reg_class = %s\n"
1735 "v reg_class = %s\n"
1736 "wa reg_class = %s\n"
1737 "wd reg_class = %s\n"
1738 "wf reg_class = %s\n"
1739 "ws reg_class = %s\n\n",
1740 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1741 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1742 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1743 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1744 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1745 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1746 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1748 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1749 if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
1751 nl = "\n";
1752 fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1753 GET_MODE_NAME (m),
1754 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
1755 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
1758 if (nl)
1759 fputs (nl, stderr);
1761 if (rs6000_recip_control)
1763 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
1765 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1766 if (rs6000_recip_bits[m])
1768 fprintf (stderr,
1769 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
1770 GET_MODE_NAME (m),
1771 (RS6000_RECIP_AUTO_RE_P (m)
1772 ? "auto"
1773 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
1774 (RS6000_RECIP_AUTO_RSQRTE_P (m)
1775 ? "auto"
1776 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
1779 fputs ("\n", stderr);
1782 if (rs6000_cpu_index >= 0)
1784 const char *name = processor_target_table[rs6000_cpu_index].name;
1785 HOST_WIDE_INT flags
1786 = processor_target_table[rs6000_cpu_index].target_enable;
1788 sprintf (flags_buffer, "-mcpu=%s flags", name);
1789 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
1791 else
1792 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
1794 if (rs6000_tune_index >= 0)
1796 const char *name = processor_target_table[rs6000_tune_index].name;
1797 HOST_WIDE_INT flags
1798 = processor_target_table[rs6000_tune_index].target_enable;
1800 sprintf (flags_buffer, "-mtune=%s flags", name);
1801 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
1803 else
1804 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
1806 cl_target_option_save (&cl_opts, &global_options);
1807 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
1808 rs6000_isa_flags);
1810 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
1811 rs6000_isa_flags_explicit);
1813 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
1814 rs6000_builtin_mask);
1816 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
1818 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
1819 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
1821 switch (rs6000_sched_costly_dep)
1823 case max_dep_latency:
1824 costly_str = "max_dep_latency";
1825 break;
1827 case no_dep_costly:
1828 costly_str = "no_dep_costly";
1829 break;
1831 case all_deps_costly:
1832 costly_str = "all_deps_costly";
1833 break;
1835 case true_store_to_load_dep_costly:
1836 costly_str = "true_store_to_load_dep_costly";
1837 break;
1839 case store_to_load_dep_costly:
1840 costly_str = "store_to_load_dep_costly";
1841 break;
1843 default:
1844 costly_str = costly_num;
1845 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
1846 break;
1849 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
1851 switch (rs6000_sched_insert_nops)
1853 case sched_finish_regroup_exact:
1854 nop_str = "sched_finish_regroup_exact";
1855 break;
1857 case sched_finish_pad_groups:
1858 nop_str = "sched_finish_pad_groups";
1859 break;
1861 case sched_finish_none:
1862 nop_str = "sched_finish_none";
1863 break;
1865 default:
1866 nop_str = nop_num;
1867 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
1868 break;
1871 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
1873 switch (rs6000_sdata)
1875 default:
1876 case SDATA_NONE:
1877 break;
1879 case SDATA_DATA:
1880 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
1881 break;
1883 case SDATA_SYSV:
1884 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
1885 break;
1887 case SDATA_EABI:
1888 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
1889 break;
1893 switch (rs6000_traceback)
1895 case traceback_default: trace_str = "default"; break;
1896 case traceback_none: trace_str = "none"; break;
1897 case traceback_part: trace_str = "part"; break;
1898 case traceback_full: trace_str = "full"; break;
1899 default: trace_str = "unknown"; break;
1902 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
1904 switch (rs6000_current_cmodel)
1906 case CMODEL_SMALL: cmodel_str = "small"; break;
1907 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
1908 case CMODEL_LARGE: cmodel_str = "large"; break;
1909 default: cmodel_str = "unknown"; break;
1912 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
1914 switch (rs6000_current_abi)
1916 case ABI_NONE: abi_str = "none"; break;
1917 case ABI_AIX: abi_str = "aix"; break;
1918 case ABI_V4: abi_str = "V4"; break;
1919 case ABI_DARWIN: abi_str = "darwin"; break;
1920 default: abi_str = "unknown"; break;
1923 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
1925 if (rs6000_altivec_abi)
1926 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
1928 if (rs6000_spe_abi)
1929 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
1931 if (rs6000_darwin64_abi)
1932 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
1934 if (rs6000_float_gprs)
1935 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
1937 if (TARGET_LINK_STACK)
1938 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
1940 fprintf (stderr, DEBUG_FMT_S, "plt-format",
1941 TARGET_SECURE_PLT ? "secure" : "bss");
1942 fprintf (stderr, DEBUG_FMT_S, "struct-return",
1943 aix_struct_return ? "aix" : "sysv");
1944 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
1945 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
1946 fprintf (stderr, DEBUG_FMT_S, "align_branch",
1947 tf[!!rs6000_align_branch_targets]);
1948 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
1949 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
1950 rs6000_long_double_type_size);
1951 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
1952 (int)rs6000_sched_restricted_insns_priority);
1953 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
1954 (int)END_BUILTINS);
1955 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
1956 (int)RS6000_BUILTIN_COUNT);
1959 /* Initialize the various global tables that are based on register size. */
1960 static void
1961 rs6000_init_hard_regno_mode_ok (bool global_init_p)
1963 int r, m, c;
1964 int align64;
1965 int align32;
1967 /* Precalculate REGNO_REG_CLASS. */
1968 rs6000_regno_regclass[0] = GENERAL_REGS;
1969 for (r = 1; r < 32; ++r)
1970 rs6000_regno_regclass[r] = BASE_REGS;
1972 for (r = 32; r < 64; ++r)
1973 rs6000_regno_regclass[r] = FLOAT_REGS;
1975 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
1976 rs6000_regno_regclass[r] = NO_REGS;
1978 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
1979 rs6000_regno_regclass[r] = ALTIVEC_REGS;
1981 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
1982 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
1983 rs6000_regno_regclass[r] = CR_REGS;
1985 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
1986 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
1987 rs6000_regno_regclass[CA_REGNO] = CA_REGS;
1988 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
1989 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
1990 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
1991 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
1992 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
1993 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
1995 /* Precalculate vector information, this must be set up before the
1996 rs6000_hard_regno_nregs_internal below. */
1997 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1999 rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
2000 rs6000_vector_reload[m][0] = CODE_FOR_nothing;
2001 rs6000_vector_reload[m][1] = CODE_FOR_nothing;
2004 for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
2005 rs6000_constraints[c] = NO_REGS;
2007 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2008 believes it can use native alignment or still uses 128-bit alignment. */
2009 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2011 align64 = 64;
2012 align32 = 32;
2014 else
2016 align64 = 128;
2017 align32 = 128;
2020 /* V2DF mode, VSX only. */
2021 if (TARGET_VSX)
2023 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2024 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2025 rs6000_vector_align[V2DFmode] = align64;
2028 /* V4SF mode, either VSX or Altivec. */
2029 if (TARGET_VSX)
2031 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2032 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2033 rs6000_vector_align[V4SFmode] = align32;
2035 else if (TARGET_ALTIVEC)
2037 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2038 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2039 rs6000_vector_align[V4SFmode] = align32;
2042 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2043 and stores. */
2044 if (TARGET_ALTIVEC)
2046 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2047 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2048 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2049 rs6000_vector_align[V4SImode] = align32;
2050 rs6000_vector_align[V8HImode] = align32;
2051 rs6000_vector_align[V16QImode] = align32;
2053 if (TARGET_VSX)
2055 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2056 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2057 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2059 else
2061 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2062 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2063 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2067 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2068 Altivec doesn't have 64-bit support. */
2069 if (TARGET_VSX)
2071 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2072 rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2073 rs6000_vector_align[V2DImode] = align64;
2076 /* DFmode, see if we want to use the VSX unit. */
2077 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2079 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2080 rs6000_vector_mem[DFmode]
2081 = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2082 rs6000_vector_align[DFmode] = align64;
2085 /* TODO add SPE and paired floating point vector support. */
2087 /* Register class constraints for the constraints that depend on compile
2088 switches. */
2089 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2090 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2092 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2093 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2095 if (TARGET_VSX)
2097 /* At present, we just use VSX_REGS, but we have different constraints
2098 based on the use, in case we want to fine tune the default register
2099 class used. wa = any VSX register, wf = register class to use for
2100 V4SF, wd = register class to use for V2DF, and ws = register classs to
2101 use for DF scalars. */
2102 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2103 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2104 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2105 rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2106 ? VSX_REGS
2107 : FLOAT_REGS);
2110 if (TARGET_ALTIVEC)
2111 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2113 /* Set up the reload helper functions. */
2114 if (TARGET_VSX || TARGET_ALTIVEC)
2116 if (TARGET_64BIT)
2118 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2119 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2120 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
2121 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
2122 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
2123 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
2124 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
2125 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
2126 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
2127 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
2128 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
2129 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
2130 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2132 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;
2133 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;
2136 else
2138 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2139 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2140 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
2141 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
2142 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
2143 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
2144 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
2145 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
2146 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
2147 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
2148 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
2149 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
2150 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2152 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;
2153 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;
2158 /* Precalculate HARD_REGNO_NREGS. */
2159 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2160 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2161 rs6000_hard_regno_nregs[m][r]
2162 = rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2164 /* Precalculate HARD_REGNO_MODE_OK. */
2165 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2166 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2167 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2168 rs6000_hard_regno_mode_ok_p[m][r] = true;
2170 /* Precalculate CLASS_MAX_NREGS sizes. */
2171 for (c = 0; c < LIM_REG_CLASSES; ++c)
2173 int reg_size;
2175 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2176 reg_size = UNITS_PER_VSX_WORD;
2178 else if (c == ALTIVEC_REGS)
2179 reg_size = UNITS_PER_ALTIVEC_WORD;
2181 else if (c == FLOAT_REGS)
2182 reg_size = UNITS_PER_FP_WORD;
2184 else
2185 reg_size = UNITS_PER_WORD;
2187 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2188 rs6000_class_max_nregs[m][c]
2189 = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size;
2192 if (TARGET_E500_DOUBLE)
2193 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2195 /* Calculate which modes to automatically generate code to use a the
2196 reciprocal divide and square root instructions. In the future, possibly
2197 automatically generate the instructions even if the user did not specify
2198 -mrecip. The older machines double precision reciprocal sqrt estimate is
2199 not accurate enough. */
2200 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2201 if (TARGET_FRES)
2202 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2203 if (TARGET_FRE)
2204 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2205 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2206 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2207 if (VECTOR_UNIT_VSX_P (V2DFmode))
2208 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2210 if (TARGET_FRSQRTES)
2211 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2212 if (TARGET_FRSQRTE)
2213 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2214 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2215 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2216 if (VECTOR_UNIT_VSX_P (V2DFmode))
2217 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2219 if (rs6000_recip_control)
2221 if (!flag_finite_math_only)
2222 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2223 if (flag_trapping_math)
2224 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2225 if (!flag_reciprocal_math)
2226 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2227 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2229 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2230 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2231 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2233 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2234 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2235 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2237 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2238 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2239 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2241 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2242 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2243 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2245 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2246 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2247 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2249 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2250 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2251 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2253 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2254 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2255 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2257 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2258 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2259 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2263 if (global_init_p || TARGET_DEBUG_TARGET)
2265 if (TARGET_DEBUG_REG)
2266 rs6000_debug_reg_global ();
2268 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2269 fprintf (stderr,
2270 "SImode variable mult cost = %d\n"
2271 "SImode constant mult cost = %d\n"
2272 "SImode short constant mult cost = %d\n"
2273 "DImode multipliciation cost = %d\n"
2274 "SImode division cost = %d\n"
2275 "DImode division cost = %d\n"
2276 "Simple fp operation cost = %d\n"
2277 "DFmode multiplication cost = %d\n"
2278 "SFmode division cost = %d\n"
2279 "DFmode division cost = %d\n"
2280 "cache line size = %d\n"
2281 "l1 cache size = %d\n"
2282 "l2 cache size = %d\n"
2283 "simultaneous prefetches = %d\n"
2284 "\n",
2285 rs6000_cost->mulsi,
2286 rs6000_cost->mulsi_const,
2287 rs6000_cost->mulsi_const9,
2288 rs6000_cost->muldi,
2289 rs6000_cost->divsi,
2290 rs6000_cost->divdi,
2291 rs6000_cost->fp,
2292 rs6000_cost->dmul,
2293 rs6000_cost->sdiv,
2294 rs6000_cost->ddiv,
2295 rs6000_cost->cache_line_size,
2296 rs6000_cost->l1_cache_size,
2297 rs6000_cost->l2_cache_size,
2298 rs6000_cost->simultaneous_prefetches);
2302 #if TARGET_MACHO
2303 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2305 static void
2306 darwin_rs6000_override_options (void)
2308 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2309 off. */
2310 rs6000_altivec_abi = 1;
2311 TARGET_ALTIVEC_VRSAVE = 1;
2312 rs6000_current_abi = ABI_DARWIN;
2314 if (DEFAULT_ABI == ABI_DARWIN
2315 && TARGET_64BIT)
2316 darwin_one_byte_bool = 1;
2318 if (TARGET_64BIT && ! TARGET_POWERPC64)
2320 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
2321 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2323 if (flag_mkernel)
2325 rs6000_default_long_calls = 1;
2326 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
2329 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2330 Altivec. */
2331 if (!flag_mkernel && !flag_apple_kext
2332 && TARGET_64BIT
2333 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
2334 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
2336 /* Unless the user (not the configurer) has explicitly overridden
2337 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2338 G4 unless targeting the kernel. */
2339 if (!flag_mkernel
2340 && !flag_apple_kext
2341 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2342 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
2343 && ! global_options_set.x_rs6000_cpu_index)
2345 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
2348 #endif
2350 /* If not otherwise specified by a target, make 'long double' equivalent to
2351 'double'. */
2353 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2354 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2355 #endif
2357 /* Return the builtin mask of the various options used that could affect which
2358 builtins were used. In the past we used target_flags, but we've run out of
2359 bits, and some options like SPE and PAIRED are no longer in
2360 target_flags. */
2362 HOST_WIDE_INT
2363 rs6000_builtin_mask_calculate (void)
2365 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
2366 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
2367 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
2368 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
2369 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
2370 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
2371 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
2372 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
2373 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
2374 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
2377 /* Override command line options. Mostly we process the processor type and
2378 sometimes adjust other TARGET_ options. */
2380 static bool
2381 rs6000_option_override_internal (bool global_init_p)
2383 bool ret = true;
2384 bool have_cpu = false;
2386 /* The default cpu requested at configure time, if any. */
2387 const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
2389 HOST_WIDE_INT set_masks;
2390 int cpu_index;
2391 int tune_index;
2392 struct cl_target_option *main_target_opt
2393 = ((global_init_p || target_option_default_node == NULL)
2394 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2396 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2397 library functions, so warn about it. The flag may be useful for
2398 performance studies from time to time though, so don't disable it
2399 entirely. */
2400 if (global_options_set.x_rs6000_alignment_flags
2401 && rs6000_alignment_flags == MASK_ALIGN_POWER
2402 && DEFAULT_ABI == ABI_DARWIN
2403 && TARGET_64BIT)
2404 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2405 " it is incompatible with the installed C and C++ libraries");
2407 /* Numerous experiment shows that IRA based loop pressure
2408 calculation works better for RTL loop invariant motion on targets
2409 with enough (>= 32) registers. It is an expensive optimization.
2410 So it is on only for peak performance. */
2411 if (optimize >= 3 && global_init_p)
2412 flag_ira_loop_pressure = 1;
2414 /* Set the pointer size. */
2415 if (TARGET_64BIT)
2417 rs6000_pmode = (int)DImode;
2418 rs6000_pointer_size = 64;
2420 else
2422 rs6000_pmode = (int)SImode;
2423 rs6000_pointer_size = 32;
2426 /* Some OSs don't support saving the high part of 64-bit registers on context
2427 switch. Other OSs don't support saving Altivec registers. On those OSs,
2428 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
2429 if the user wants either, the user must explicitly specify them and we
2430 won't interfere with the user's specification. */
2432 set_masks = POWERPC_MASKS;
2433 #ifdef OS_MISSING_POWERPC64
2434 if (OS_MISSING_POWERPC64)
2435 set_masks &= ~OPTION_MASK_POWERPC64;
2436 #endif
2437 #ifdef OS_MISSING_ALTIVEC
2438 if (OS_MISSING_ALTIVEC)
2439 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX);
2440 #endif
2442 /* Don't override by the processor default if given explicitly. */
2443 set_masks &= ~rs6000_isa_flags_explicit;
2445 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2446 the cpu in a target attribute or pragma, but did not specify a tuning
2447 option, use the cpu for the tuning option rather than the option specified
2448 with -mtune on the command line. Process a '--with-cpu' configuration
2449 request as an implicit --cpu. */
2450 if (rs6000_cpu_index >= 0)
2452 cpu_index = rs6000_cpu_index;
2453 have_cpu = true;
2455 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
2457 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2458 have_cpu = true;
2460 else if (implicit_cpu)
2462 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (implicit_cpu);
2463 have_cpu = true;
2465 else
2467 const char *default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
2468 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2469 have_cpu = false;
2472 gcc_assert (cpu_index >= 0);
2474 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
2475 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
2476 with those from the cpu, except for options that were explicitly set. If
2477 we don't have a cpu, do not override the target bits set in
2478 TARGET_DEFAULT. */
2479 if (have_cpu)
2481 rs6000_isa_flags &= ~set_masks;
2482 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
2483 & set_masks);
2485 else
2486 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
2487 & ~rs6000_isa_flags_explicit);
2489 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
2490 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
2491 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
2492 to using rs6000_isa_flags, we need to do the initialization here. */
2493 if (!have_cpu)
2494 rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit);
2496 if (rs6000_tune_index >= 0)
2497 tune_index = rs6000_tune_index;
2498 else if (have_cpu)
2499 rs6000_tune_index = tune_index = cpu_index;
2500 else
2502 size_t i;
2503 enum processor_type tune_proc
2504 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
2506 tune_index = -1;
2507 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2508 if (processor_target_table[i].processor == tune_proc)
2510 rs6000_tune_index = tune_index = i;
2511 break;
2515 gcc_assert (tune_index >= 0);
2516 rs6000_cpu = processor_target_table[tune_index].processor;
2518 /* Pick defaults for SPE related control flags. Do this early to make sure
2519 that the TARGET_ macros are representative ASAP. */
2521 int spe_capable_cpu =
2522 (rs6000_cpu == PROCESSOR_PPC8540
2523 || rs6000_cpu == PROCESSOR_PPC8548);
2525 if (!global_options_set.x_rs6000_spe_abi)
2526 rs6000_spe_abi = spe_capable_cpu;
2528 if (!global_options_set.x_rs6000_spe)
2529 rs6000_spe = spe_capable_cpu;
2531 if (!global_options_set.x_rs6000_float_gprs)
2532 rs6000_float_gprs =
2533 (rs6000_cpu == PROCESSOR_PPC8540 ? 1
2534 : rs6000_cpu == PROCESSOR_PPC8548 ? 2
2535 : 0);
2538 if (global_options_set.x_rs6000_spe_abi
2539 && rs6000_spe_abi
2540 && !TARGET_SPE_ABI)
2541 error ("not configured for SPE ABI");
2543 if (global_options_set.x_rs6000_spe
2544 && rs6000_spe
2545 && !TARGET_SPE)
2546 error ("not configured for SPE instruction set");
2548 if (main_target_opt != NULL
2549 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2550 || (main_target_opt->x_rs6000_spe != rs6000_spe)
2551 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2552 error ("target attribute or pragma changes SPE ABI");
2554 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2555 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
2556 || rs6000_cpu == PROCESSOR_PPCE5500)
2558 if (TARGET_ALTIVEC)
2559 error ("AltiVec not supported in this target");
2560 if (TARGET_SPE)
2561 error ("SPE not supported in this target");
2563 if (rs6000_cpu == PROCESSOR_PPCE6500)
2565 if (TARGET_SPE)
2566 error ("SPE not supported in this target");
2569 /* Disable Cell microcode if we are optimizing for the Cell
2570 and not optimizing for size. */
2571 if (rs6000_gen_cell_microcode == -1)
2572 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2573 && !optimize_size);
2575 /* If we are optimizing big endian systems for space and it's OK to
2576 use instructions that would be microcoded on the Cell, use the
2577 load/store multiple and string instructions. */
2578 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2579 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
2580 | OPTION_MASK_STRING);
2582 /* Don't allow -mmultiple or -mstring on little endian systems
2583 unless the cpu is a 750, because the hardware doesn't support the
2584 instructions used in little endian mode, and causes an alignment
2585 trap. The 750 does not cause an alignment trap (except when the
2586 target is unaligned). */
2588 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2590 if (TARGET_MULTIPLE)
2592 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
2593 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
2594 warning (0, "-mmultiple is not supported on little endian systems");
2597 if (TARGET_STRING)
2599 rs6000_isa_flags &= ~OPTION_MASK_STRING;
2600 if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
2601 warning (0, "-mstring is not supported on little endian systems");
2605 /* Add some warnings for VSX. */
2606 if (TARGET_VSX)
2608 const char *msg = NULL;
2609 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2610 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2612 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
2613 msg = N_("-mvsx requires hardware floating point");
2614 else
2615 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
2617 else if (TARGET_PAIRED_FLOAT)
2618 msg = N_("-mvsx and -mpaired are incompatible");
2619 /* The hardware will allow VSX and little endian, but until we make sure
2620 things like vector select, etc. work don't allow VSX on little endian
2621 systems at this point. */
2622 else if (!BYTES_BIG_ENDIAN)
2623 msg = N_("-mvsx used with little endian code");
2624 else if (TARGET_AVOID_XFORM > 0)
2625 msg = N_("-mvsx needs indexed addressing");
2626 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
2627 & OPTION_MASK_ALTIVEC))
2629 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
2630 msg = N_("-mvsx and -mno-altivec are incompatible");
2631 else
2632 msg = N_("-mno-altivec disables vsx");
2635 if (msg)
2637 warning (0, msg);
2638 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
2639 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
2643 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2644 unless the user explicitly used the -mno-<option> to disable the code. */
2645 if (TARGET_VSX)
2646 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
2647 else if (TARGET_POPCNTD)
2648 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
2649 else if (TARGET_DFP)
2650 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit);
2651 else if (TARGET_CMPB)
2652 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
2653 else if (TARGET_FPRND)
2654 rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit);
2655 else if (TARGET_POPCNTB)
2656 rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit);
2657 else if (TARGET_ALTIVEC)
2658 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
2660 /* E500mc does "better" if we inline more aggressively. Respect the
2661 user's opinion, though. */
2662 if (rs6000_block_move_inline_limit == 0
2663 && (rs6000_cpu == PROCESSOR_PPCE500MC
2664 || rs6000_cpu == PROCESSOR_PPCE500MC64
2665 || rs6000_cpu == PROCESSOR_PPCE5500
2666 || rs6000_cpu == PROCESSOR_PPCE6500))
2667 rs6000_block_move_inline_limit = 128;
2669 /* store_one_arg depends on expand_block_move to handle at least the
2670 size of reg_parm_stack_space. */
2671 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2672 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2674 if (global_init_p)
2676 /* If the appropriate debug option is enabled, replace the target hooks
2677 with debug versions that call the real version and then prints
2678 debugging information. */
2679 if (TARGET_DEBUG_COST)
2681 targetm.rtx_costs = rs6000_debug_rtx_costs;
2682 targetm.address_cost = rs6000_debug_address_cost;
2683 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2686 if (TARGET_DEBUG_ADDR)
2688 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2689 targetm.legitimize_address = rs6000_debug_legitimize_address;
2690 rs6000_secondary_reload_class_ptr
2691 = rs6000_debug_secondary_reload_class;
2692 rs6000_secondary_memory_needed_ptr
2693 = rs6000_debug_secondary_memory_needed;
2694 rs6000_cannot_change_mode_class_ptr
2695 = rs6000_debug_cannot_change_mode_class;
2696 rs6000_preferred_reload_class_ptr
2697 = rs6000_debug_preferred_reload_class;
2698 rs6000_legitimize_reload_address_ptr
2699 = rs6000_debug_legitimize_reload_address;
2700 rs6000_mode_dependent_address_ptr
2701 = rs6000_debug_mode_dependent_address;
2704 if (rs6000_veclibabi_name)
2706 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2707 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2708 else
2710 error ("unknown vectorization library ABI type (%s) for "
2711 "-mveclibabi= switch", rs6000_veclibabi_name);
2712 ret = false;
2717 if (!global_options_set.x_rs6000_long_double_type_size)
2719 if (main_target_opt != NULL
2720 && (main_target_opt->x_rs6000_long_double_type_size
2721 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2722 error ("target attribute or pragma changes long double size");
2723 else
2724 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2727 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
2728 if (!global_options_set.x_rs6000_ieeequad)
2729 rs6000_ieeequad = 1;
2730 #endif
2732 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2733 target attribute or pragma which automatically enables both options,
2734 unless the altivec ABI was set. This is set by default for 64-bit, but
2735 not for 32-bit. */
2736 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2737 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
2738 & ~rs6000_isa_flags_explicit);
2740 /* Enable Altivec ABI for AIX -maltivec. */
2741 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2743 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2744 error ("target attribute or pragma changes AltiVec ABI");
2745 else
2746 rs6000_altivec_abi = 1;
2749 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2750 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2751 be explicitly overridden in either case. */
2752 if (TARGET_ELF)
2754 if (!global_options_set.x_rs6000_altivec_abi
2755 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2757 if (main_target_opt != NULL &&
2758 !main_target_opt->x_rs6000_altivec_abi)
2759 error ("target attribute or pragma changes AltiVec ABI");
2760 else
2761 rs6000_altivec_abi = 1;
2765 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2766 So far, the only darwin64 targets are also MACH-O. */
2767 if (TARGET_MACHO
2768 && DEFAULT_ABI == ABI_DARWIN
2769 && TARGET_64BIT)
2771 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2772 error ("target attribute or pragma changes darwin64 ABI");
2773 else
2775 rs6000_darwin64_abi = 1;
2776 /* Default to natural alignment, for better performance. */
2777 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2781 /* Place FP constants in the constant pool instead of TOC
2782 if section anchors enabled. */
2783 if (flag_section_anchors)
2784 TARGET_NO_FP_IN_TOC = 1;
2786 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2787 SUBTARGET_OVERRIDE_OPTIONS;
2788 #endif
2789 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2790 SUBSUBTARGET_OVERRIDE_OPTIONS;
2791 #endif
2792 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2793 SUB3TARGET_OVERRIDE_OPTIONS;
2794 #endif
2796 /* For the E500 family of cores, reset the single/double FP flags to let us
2797 check that they remain constant across attributes or pragmas. Also,
2798 clear a possible request for string instructions, not supported and which
2799 we might have silently queried above for -Os.
2801 For other families, clear ISEL in case it was set implicitly.
2804 switch (rs6000_cpu)
2806 case PROCESSOR_PPC8540:
2807 case PROCESSOR_PPC8548:
2808 case PROCESSOR_PPCE500MC:
2809 case PROCESSOR_PPCE500MC64:
2810 case PROCESSOR_PPCE5500:
2811 case PROCESSOR_PPCE6500:
2813 rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
2814 rs6000_double_float = TARGET_E500_DOUBLE;
2816 rs6000_isa_flags &= ~OPTION_MASK_STRING;
2818 break;
2820 default:
2822 if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
2823 rs6000_isa_flags &= ~OPTION_MASK_ISEL;
2825 break;
2828 if (main_target_opt)
2830 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
2831 error ("target attribute or pragma changes single precision floating "
2832 "point");
2833 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
2834 error ("target attribute or pragma changes double precision floating "
2835 "point");
2838 /* Detect invalid option combinations with E500. */
2839 CHECK_E500_OPTIONS;
2841 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2842 && rs6000_cpu != PROCESSOR_POWER5
2843 && rs6000_cpu != PROCESSOR_POWER6
2844 && rs6000_cpu != PROCESSOR_POWER7
2845 && rs6000_cpu != PROCESSOR_PPCA2
2846 && rs6000_cpu != PROCESSOR_CELL
2847 && rs6000_cpu != PROCESSOR_PPC476);
2848 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2849 || rs6000_cpu == PROCESSOR_POWER5
2850 || rs6000_cpu == PROCESSOR_POWER7);
2851 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2852 || rs6000_cpu == PROCESSOR_POWER5
2853 || rs6000_cpu == PROCESSOR_POWER6
2854 || rs6000_cpu == PROCESSOR_POWER7
2855 || rs6000_cpu == PROCESSOR_PPCE500MC
2856 || rs6000_cpu == PROCESSOR_PPCE500MC64
2857 || rs6000_cpu == PROCESSOR_PPCE5500
2858 || rs6000_cpu == PROCESSOR_PPCE6500);
2860 /* Allow debug switches to override the above settings. These are set to -1
2861 in rs6000.opt to indicate the user hasn't directly set the switch. */
2862 if (TARGET_ALWAYS_HINT >= 0)
2863 rs6000_always_hint = TARGET_ALWAYS_HINT;
2865 if (TARGET_SCHED_GROUPS >= 0)
2866 rs6000_sched_groups = TARGET_SCHED_GROUPS;
2868 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2869 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2871 rs6000_sched_restricted_insns_priority
2872 = (rs6000_sched_groups ? 1 : 0);
2874 /* Handle -msched-costly-dep option. */
2875 rs6000_sched_costly_dep
2876 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
2878 if (rs6000_sched_costly_dep_str)
2880 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
2881 rs6000_sched_costly_dep = no_dep_costly;
2882 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
2883 rs6000_sched_costly_dep = all_deps_costly;
2884 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
2885 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
2886 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
2887 rs6000_sched_costly_dep = store_to_load_dep_costly;
2888 else
2889 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
2890 atoi (rs6000_sched_costly_dep_str));
2893 /* Handle -minsert-sched-nops option. */
2894 rs6000_sched_insert_nops
2895 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
2897 if (rs6000_sched_insert_nops_str)
2899 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
2900 rs6000_sched_insert_nops = sched_finish_none;
2901 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
2902 rs6000_sched_insert_nops = sched_finish_pad_groups;
2903 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
2904 rs6000_sched_insert_nops = sched_finish_regroup_exact;
2905 else
2906 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
2907 atoi (rs6000_sched_insert_nops_str));
2910 if (global_init_p)
2912 #ifdef TARGET_REGNAMES
2913 /* If the user desires alternate register names, copy in the
2914 alternate names now. */
2915 if (TARGET_REGNAMES)
2916 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
2917 #endif
2919 /* Set aix_struct_return last, after the ABI is determined.
2920 If -maix-struct-return or -msvr4-struct-return was explicitly
2921 used, don't override with the ABI default. */
2922 if (!global_options_set.x_aix_struct_return)
2923 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
2925 #if 0
2926 /* IBM XL compiler defaults to unsigned bitfields. */
2927 if (TARGET_XL_COMPAT)
2928 flag_signed_bitfields = 0;
2929 #endif
2931 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
2932 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
2934 if (TARGET_TOC)
2935 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
2937 /* We can only guarantee the availability of DI pseudo-ops when
2938 assembling for 64-bit targets. */
2939 if (!TARGET_64BIT)
2941 targetm.asm_out.aligned_op.di = NULL;
2942 targetm.asm_out.unaligned_op.di = NULL;
2946 /* Set branch target alignment, if not optimizing for size. */
2947 if (!optimize_size)
2949 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
2950 aligned 8byte to avoid misprediction by the branch predictor. */
2951 if (rs6000_cpu == PROCESSOR_TITAN
2952 || rs6000_cpu == PROCESSOR_CELL)
2954 if (align_functions <= 0)
2955 align_functions = 8;
2956 if (align_jumps <= 0)
2957 align_jumps = 8;
2958 if (align_loops <= 0)
2959 align_loops = 8;
2961 if (rs6000_align_branch_targets)
2963 if (align_functions <= 0)
2964 align_functions = 16;
2965 if (align_jumps <= 0)
2966 align_jumps = 16;
2967 if (align_loops <= 0)
2969 can_override_loop_align = 1;
2970 align_loops = 16;
2973 if (align_jumps_max_skip <= 0)
2974 align_jumps_max_skip = 15;
2975 if (align_loops_max_skip <= 0)
2976 align_loops_max_skip = 15;
2979 /* Arrange to save and restore machine status around nested functions. */
2980 init_machine_status = rs6000_init_machine_status;
2982 /* We should always be splitting complex arguments, but we can't break
2983 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
2984 if (DEFAULT_ABI != ABI_AIX)
2985 targetm.calls.split_complex_arg = NULL;
2988 /* Initialize rs6000_cost with the appropriate target costs. */
2989 if (optimize_size)
2990 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
2991 else
2992 switch (rs6000_cpu)
2994 case PROCESSOR_RS64A:
2995 rs6000_cost = &rs64a_cost;
2996 break;
2998 case PROCESSOR_MPCCORE:
2999 rs6000_cost = &mpccore_cost;
3000 break;
3002 case PROCESSOR_PPC403:
3003 rs6000_cost = &ppc403_cost;
3004 break;
3006 case PROCESSOR_PPC405:
3007 rs6000_cost = &ppc405_cost;
3008 break;
3010 case PROCESSOR_PPC440:
3011 rs6000_cost = &ppc440_cost;
3012 break;
3014 case PROCESSOR_PPC476:
3015 rs6000_cost = &ppc476_cost;
3016 break;
3018 case PROCESSOR_PPC601:
3019 rs6000_cost = &ppc601_cost;
3020 break;
3022 case PROCESSOR_PPC603:
3023 rs6000_cost = &ppc603_cost;
3024 break;
3026 case PROCESSOR_PPC604:
3027 rs6000_cost = &ppc604_cost;
3028 break;
3030 case PROCESSOR_PPC604e:
3031 rs6000_cost = &ppc604e_cost;
3032 break;
3034 case PROCESSOR_PPC620:
3035 rs6000_cost = &ppc620_cost;
3036 break;
3038 case PROCESSOR_PPC630:
3039 rs6000_cost = &ppc630_cost;
3040 break;
3042 case PROCESSOR_CELL:
3043 rs6000_cost = &ppccell_cost;
3044 break;
3046 case PROCESSOR_PPC750:
3047 case PROCESSOR_PPC7400:
3048 rs6000_cost = &ppc750_cost;
3049 break;
3051 case PROCESSOR_PPC7450:
3052 rs6000_cost = &ppc7450_cost;
3053 break;
3055 case PROCESSOR_PPC8540:
3056 case PROCESSOR_PPC8548:
3057 rs6000_cost = &ppc8540_cost;
3058 break;
3060 case PROCESSOR_PPCE300C2:
3061 case PROCESSOR_PPCE300C3:
3062 rs6000_cost = &ppce300c2c3_cost;
3063 break;
3065 case PROCESSOR_PPCE500MC:
3066 rs6000_cost = &ppce500mc_cost;
3067 break;
3069 case PROCESSOR_PPCE500MC64:
3070 rs6000_cost = &ppce500mc64_cost;
3071 break;
3073 case PROCESSOR_PPCE5500:
3074 rs6000_cost = &ppce5500_cost;
3075 break;
3077 case PROCESSOR_PPCE6500:
3078 rs6000_cost = &ppce6500_cost;
3079 break;
3081 case PROCESSOR_TITAN:
3082 rs6000_cost = &titan_cost;
3083 break;
3085 case PROCESSOR_POWER4:
3086 case PROCESSOR_POWER5:
3087 rs6000_cost = &power4_cost;
3088 break;
3090 case PROCESSOR_POWER6:
3091 rs6000_cost = &power6_cost;
3092 break;
3094 case PROCESSOR_POWER7:
3095 rs6000_cost = &power7_cost;
3096 break;
3098 case PROCESSOR_PPCA2:
3099 rs6000_cost = &ppca2_cost;
3100 break;
3102 default:
3103 gcc_unreachable ();
3106 if (global_init_p)
3108 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3109 rs6000_cost->simultaneous_prefetches,
3110 global_options.x_param_values,
3111 global_options_set.x_param_values);
3112 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3113 global_options.x_param_values,
3114 global_options_set.x_param_values);
3115 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3116 rs6000_cost->cache_line_size,
3117 global_options.x_param_values,
3118 global_options_set.x_param_values);
3119 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3120 global_options.x_param_values,
3121 global_options_set.x_param_values);
3123 /* If using typedef char *va_list, signal that
3124 __builtin_va_start (&ap, 0) can be optimized to
3125 ap = __builtin_next_arg (0). */
3126 if (DEFAULT_ABI != ABI_V4)
3127 targetm.expand_builtin_va_start = NULL;
3130 /* Set up single/double float flags.
3131 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3132 then set both flags. */
3133 if (TARGET_HARD_FLOAT && TARGET_FPRS
3134 && rs6000_single_float == 0 && rs6000_double_float == 0)
3135 rs6000_single_float = rs6000_double_float = 1;
3137 /* If not explicitly specified via option, decide whether to generate indexed
3138 load/store instructions. */
3139 if (TARGET_AVOID_XFORM == -1)
3140 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3141 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3142 need indexed accesses and the type used is the scalar type of the element
3143 being loaded or stored. */
3144 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3145 && !TARGET_ALTIVEC);
3147 /* Set the -mrecip options. */
3148 if (rs6000_recip_name)
3150 char *p = ASTRDUP (rs6000_recip_name);
3151 char *q;
3152 unsigned int mask, i;
3153 bool invert;
3155 while ((q = strtok (p, ",")) != NULL)
3157 p = NULL;
3158 if (*q == '!')
3160 invert = true;
3161 q++;
3163 else
3164 invert = false;
3166 if (!strcmp (q, "default"))
3167 mask = ((TARGET_RECIP_PRECISION)
3168 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3169 else
3171 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3172 if (!strcmp (q, recip_options[i].string))
3174 mask = recip_options[i].mask;
3175 break;
3178 if (i == ARRAY_SIZE (recip_options))
3180 error ("unknown option for -mrecip=%s", q);
3181 invert = false;
3182 mask = 0;
3183 ret = false;
3187 if (invert)
3188 rs6000_recip_control &= ~mask;
3189 else
3190 rs6000_recip_control |= mask;
3194 /* Set the builtin mask of the various options used that could affect which
3195 builtins were used. In the past we used target_flags, but we've run out
3196 of bits, and some options like SPE and PAIRED are no longer in
3197 target_flags. */
3198 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3199 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3201 fprintf (stderr,
3202 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ",
3203 rs6000_builtin_mask);
3204 rs6000_print_builtin_options (stderr, 0, NULL, rs6000_builtin_mask);
3207 /* Initialize all of the registers. */
3208 rs6000_init_hard_regno_mode_ok (global_init_p);
3210 /* Save the initial options in case the user does function specific options */
3211 if (global_init_p)
3212 target_option_default_node = target_option_current_node
3213 = build_target_option_node ();
3215 /* If not explicitly specified via option, decide whether to generate the
3216 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3217 if (TARGET_LINK_STACK == -1)
3218 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3220 return ret;
3223 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3224 define the target cpu type. */
3226 static void
3227 rs6000_option_override (void)
3229 (void) rs6000_option_override_internal (true);
3233 /* Implement targetm.vectorize.builtin_mask_for_load. */
3234 static tree
3235 rs6000_builtin_mask_for_load (void)
3237 if (TARGET_ALTIVEC || TARGET_VSX)
3238 return altivec_builtin_mask_for_load;
3239 else
3240 return 0;
3243 /* Implement LOOP_ALIGN. */
3245 rs6000_loop_align (rtx label)
3247 basic_block bb;
3248 int ninsns;
3250 /* Don't override loop alignment if -falign-loops was specified. */
3251 if (!can_override_loop_align)
3252 return align_loops_log;
3254 bb = BLOCK_FOR_INSN (label);
3255 ninsns = num_loop_insns(bb->loop_father);
3257 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3258 if (ninsns > 4 && ninsns <= 8
3259 && (rs6000_cpu == PROCESSOR_POWER4
3260 || rs6000_cpu == PROCESSOR_POWER5
3261 || rs6000_cpu == PROCESSOR_POWER6
3262 || rs6000_cpu == PROCESSOR_POWER7))
3263 return 5;
3264 else
3265 return align_loops_log;
3268 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3269 static int
3270 rs6000_loop_align_max_skip (rtx label)
3272 return (1 << rs6000_loop_align (label)) - 1;
3275 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3276 after applying N number of iterations. This routine does not determine
3277 how may iterations are required to reach desired alignment. */
3279 static bool
3280 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3282 if (is_packed)
3283 return false;
3285 if (TARGET_32BIT)
3287 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3288 return true;
3290 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
3291 return true;
3293 return false;
3295 else
3297 if (TARGET_MACHO)
3298 return false;
3300 /* Assuming that all other types are naturally aligned. CHECKME! */
3301 return true;
3305 /* Return true if the vector misalignment factor is supported by the
3306 target. */
3307 static bool
3308 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3309 const_tree type,
3310 int misalignment,
3311 bool is_packed)
3313 if (TARGET_VSX)
3315 /* Return if movmisalign pattern is not supported for this mode. */
3316 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3317 return false;
3319 if (misalignment == -1)
3321 /* Misalignment factor is unknown at compile time but we know
3322 it's word aligned. */
3323 if (rs6000_vector_alignment_reachable (type, is_packed))
3325 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3327 if (element_size == 64 || element_size == 32)
3328 return true;
3331 return false;
3334 /* VSX supports word-aligned vector. */
3335 if (misalignment % 4 == 0)
3336 return true;
3338 return false;
3341 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3342 static int
3343 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3344 tree vectype, int misalign)
3346 unsigned elements;
3347 tree elem_type;
3349 switch (type_of_cost)
3351 case scalar_stmt:
3352 case scalar_load:
3353 case scalar_store:
3354 case vector_stmt:
3355 case vector_load:
3356 case vector_store:
3357 case vec_to_scalar:
3358 case scalar_to_vec:
3359 case cond_branch_not_taken:
3360 return 1;
3362 case vec_perm:
3363 if (TARGET_VSX)
3364 return 3;
3365 else
3366 return 1;
3368 case vec_promote_demote:
3369 if (TARGET_VSX)
3370 return 4;
3371 else
3372 return 1;
3374 case cond_branch_taken:
3375 return 3;
3377 case unaligned_load:
3378 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3380 elements = TYPE_VECTOR_SUBPARTS (vectype);
3381 if (elements == 2)
3382 /* Double word aligned. */
3383 return 2;
3385 if (elements == 4)
3387 switch (misalign)
3389 case 8:
3390 /* Double word aligned. */
3391 return 2;
3393 case -1:
3394 /* Unknown misalignment. */
3395 case 4:
3396 case 12:
3397 /* Word aligned. */
3398 return 22;
3400 default:
3401 gcc_unreachable ();
3406 if (TARGET_ALTIVEC)
3407 /* Misaligned loads are not supported. */
3408 gcc_unreachable ();
3410 return 2;
3412 case unaligned_store:
3413 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3415 elements = TYPE_VECTOR_SUBPARTS (vectype);
3416 if (elements == 2)
3417 /* Double word aligned. */
3418 return 2;
3420 if (elements == 4)
3422 switch (misalign)
3424 case 8:
3425 /* Double word aligned. */
3426 return 2;
3428 case -1:
3429 /* Unknown misalignment. */
3430 case 4:
3431 case 12:
3432 /* Word aligned. */
3433 return 23;
3435 default:
3436 gcc_unreachable ();
3441 if (TARGET_ALTIVEC)
3442 /* Misaligned stores are not supported. */
3443 gcc_unreachable ();
3445 return 2;
3447 case vec_construct:
3448 elements = TYPE_VECTOR_SUBPARTS (vectype);
3449 elem_type = TREE_TYPE (vectype);
3450 /* 32-bit vectors loaded into registers are stored as double
3451 precision, so we need n/2 converts in addition to the usual
3452 n/2 merges to construct a vector of short floats from them. */
3453 if (SCALAR_FLOAT_TYPE_P (elem_type)
3454 && TYPE_PRECISION (elem_type) == 32)
3455 return elements + 1;
3456 else
3457 return elements / 2 + 1;
3459 default:
3460 gcc_unreachable ();
3464 /* Implement targetm.vectorize.preferred_simd_mode. */
3466 static enum machine_mode
3467 rs6000_preferred_simd_mode (enum machine_mode mode)
3469 if (TARGET_VSX)
3470 switch (mode)
3472 case DFmode:
3473 return V2DFmode;
3474 default:;
3476 if (TARGET_ALTIVEC || TARGET_VSX)
3477 switch (mode)
3479 case SFmode:
3480 return V4SFmode;
3481 case DImode:
3482 return V2DImode;
3483 case SImode:
3484 return V4SImode;
3485 case HImode:
3486 return V8HImode;
3487 case QImode:
3488 return V16QImode;
3489 default:;
3491 if (TARGET_SPE)
3492 switch (mode)
3494 case SFmode:
3495 return V2SFmode;
3496 case SImode:
3497 return V2SImode;
3498 default:;
3500 if (TARGET_PAIRED_FLOAT
3501 && mode == SFmode)
3502 return V2SFmode;
3503 return word_mode;
3506 typedef struct _rs6000_cost_data
3508 struct loop *loop_info;
3509 unsigned cost[3];
3510 } rs6000_cost_data;
3512 /* Test for likely overcommitment of vector hardware resources. If a
3513 loop iteration is relatively large, and too large a percentage of
3514 instructions in the loop are vectorized, the cost model may not
3515 adequately reflect delays from unavailable vector resources.
3516 Penalize the loop body cost for this case. */
3518 static void
3519 rs6000_density_test (rs6000_cost_data *data)
3521 const int DENSITY_PCT_THRESHOLD = 85;
3522 const int DENSITY_SIZE_THRESHOLD = 70;
3523 const int DENSITY_PENALTY = 10;
3524 struct loop *loop = data->loop_info;
3525 basic_block *bbs = get_loop_body (loop);
3526 int nbbs = loop->num_nodes;
3527 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
3528 int i, density_pct;
3530 for (i = 0; i < nbbs; i++)
3532 basic_block bb = bbs[i];
3533 gimple_stmt_iterator gsi;
3535 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
3537 gimple stmt = gsi_stmt (gsi);
3538 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
3540 if (!STMT_VINFO_RELEVANT_P (stmt_info)
3541 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
3542 not_vec_cost++;
3546 free (bbs);
3547 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
3549 if (density_pct > DENSITY_PCT_THRESHOLD
3550 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
3552 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
3553 if (dump_enabled_p ())
3554 dump_printf_loc (MSG_NOTE, vect_location,
3555 "density %d%%, cost %d exceeds threshold, penalizing "
3556 "loop body cost by %d%%", density_pct,
3557 vec_cost + not_vec_cost, DENSITY_PENALTY);
3561 /* Implement targetm.vectorize.init_cost. */
3563 static void *
3564 rs6000_init_cost (struct loop *loop_info)
3566 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
3567 data->loop_info = loop_info;
3568 data->cost[vect_prologue] = 0;
3569 data->cost[vect_body] = 0;
3570 data->cost[vect_epilogue] = 0;
3571 return data;
3574 /* Implement targetm.vectorize.add_stmt_cost. */
3576 static unsigned
3577 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
3578 struct _stmt_vec_info *stmt_info, int misalign,
3579 enum vect_cost_model_location where)
3581 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
3582 unsigned retval = 0;
3584 if (flag_vect_cost_model)
3586 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
3587 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
3588 misalign);
3589 /* Statements in an inner loop relative to the loop being
3590 vectorized are weighted more heavily. The value here is
3591 arbitrary and could potentially be improved with analysis. */
3592 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
3593 count *= 50; /* FIXME. */
3595 retval = (unsigned) (count * stmt_cost);
3596 cost_data->cost[where] += retval;
3599 return retval;
3602 /* Implement targetm.vectorize.finish_cost. */
3604 static void
3605 rs6000_finish_cost (void *data, unsigned *prologue_cost,
3606 unsigned *body_cost, unsigned *epilogue_cost)
3608 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
3610 if (cost_data->loop_info)
3611 rs6000_density_test (cost_data);
3613 *prologue_cost = cost_data->cost[vect_prologue];
3614 *body_cost = cost_data->cost[vect_body];
3615 *epilogue_cost = cost_data->cost[vect_epilogue];
3618 /* Implement targetm.vectorize.destroy_cost_data. */
3620 static void
3621 rs6000_destroy_cost_data (void *data)
3623 free (data);
3626 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3627 library with vectorized intrinsics. */
3629 static tree
3630 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3632 char name[32];
3633 const char *suffix = NULL;
3634 tree fntype, new_fndecl, bdecl = NULL_TREE;
3635 int n_args = 1;
3636 const char *bname;
3637 enum machine_mode el_mode, in_mode;
3638 int n, in_n;
3640 /* Libmass is suitable for unsafe math only as it does not correctly support
3641 parts of IEEE with the required precision such as denormals. Only support
3642 it if we have VSX to use the simd d2 or f4 functions.
3643 XXX: Add variable length support. */
3644 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3645 return NULL_TREE;
3647 el_mode = TYPE_MODE (TREE_TYPE (type_out));
3648 n = TYPE_VECTOR_SUBPARTS (type_out);
3649 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3650 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3651 if (el_mode != in_mode
3652 || n != in_n)
3653 return NULL_TREE;
3655 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3657 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3658 switch (fn)
3660 case BUILT_IN_ATAN2:
3661 case BUILT_IN_HYPOT:
3662 case BUILT_IN_POW:
3663 n_args = 2;
3664 /* fall through */
3666 case BUILT_IN_ACOS:
3667 case BUILT_IN_ACOSH:
3668 case BUILT_IN_ASIN:
3669 case BUILT_IN_ASINH:
3670 case BUILT_IN_ATAN:
3671 case BUILT_IN_ATANH:
3672 case BUILT_IN_CBRT:
3673 case BUILT_IN_COS:
3674 case BUILT_IN_COSH:
3675 case BUILT_IN_ERF:
3676 case BUILT_IN_ERFC:
3677 case BUILT_IN_EXP2:
3678 case BUILT_IN_EXP:
3679 case BUILT_IN_EXPM1:
3680 case BUILT_IN_LGAMMA:
3681 case BUILT_IN_LOG10:
3682 case BUILT_IN_LOG1P:
3683 case BUILT_IN_LOG2:
3684 case BUILT_IN_LOG:
3685 case BUILT_IN_SIN:
3686 case BUILT_IN_SINH:
3687 case BUILT_IN_SQRT:
3688 case BUILT_IN_TAN:
3689 case BUILT_IN_TANH:
3690 bdecl = builtin_decl_implicit (fn);
3691 suffix = "d2"; /* pow -> powd2 */
3692 if (el_mode != DFmode
3693 || n != 2)
3694 return NULL_TREE;
3695 break;
3697 case BUILT_IN_ATAN2F:
3698 case BUILT_IN_HYPOTF:
3699 case BUILT_IN_POWF:
3700 n_args = 2;
3701 /* fall through */
3703 case BUILT_IN_ACOSF:
3704 case BUILT_IN_ACOSHF:
3705 case BUILT_IN_ASINF:
3706 case BUILT_IN_ASINHF:
3707 case BUILT_IN_ATANF:
3708 case BUILT_IN_ATANHF:
3709 case BUILT_IN_CBRTF:
3710 case BUILT_IN_COSF:
3711 case BUILT_IN_COSHF:
3712 case BUILT_IN_ERFF:
3713 case BUILT_IN_ERFCF:
3714 case BUILT_IN_EXP2F:
3715 case BUILT_IN_EXPF:
3716 case BUILT_IN_EXPM1F:
3717 case BUILT_IN_LGAMMAF:
3718 case BUILT_IN_LOG10F:
3719 case BUILT_IN_LOG1PF:
3720 case BUILT_IN_LOG2F:
3721 case BUILT_IN_LOGF:
3722 case BUILT_IN_SINF:
3723 case BUILT_IN_SINHF:
3724 case BUILT_IN_SQRTF:
3725 case BUILT_IN_TANF:
3726 case BUILT_IN_TANHF:
3727 bdecl = builtin_decl_implicit (fn);
3728 suffix = "4"; /* powf -> powf4 */
3729 if (el_mode != SFmode
3730 || n != 4)
3731 return NULL_TREE;
3732 break;
3734 default:
3735 return NULL_TREE;
3738 else
3739 return NULL_TREE;
3741 gcc_assert (suffix != NULL);
3742 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3743 strcpy (name, bname + sizeof ("__builtin_") - 1);
3744 strcat (name, suffix);
3746 if (n_args == 1)
3747 fntype = build_function_type_list (type_out, type_in, NULL);
3748 else if (n_args == 2)
3749 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3750 else
3751 gcc_unreachable ();
3753 /* Build a function declaration for the vectorized function. */
3754 new_fndecl = build_decl (BUILTINS_LOCATION,
3755 FUNCTION_DECL, get_identifier (name), fntype);
3756 TREE_PUBLIC (new_fndecl) = 1;
3757 DECL_EXTERNAL (new_fndecl) = 1;
3758 DECL_IS_NOVOPS (new_fndecl) = 1;
3759 TREE_READONLY (new_fndecl) = 1;
3761 return new_fndecl;
3764 /* Returns a function decl for a vectorized version of the builtin function
3765 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3766 if it is not available. */
3768 static tree
3769 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3770 tree type_in)
3772 enum machine_mode in_mode, out_mode;
3773 int in_n, out_n;
3775 if (TARGET_DEBUG_BUILTIN)
3776 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3777 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3778 GET_MODE_NAME (TYPE_MODE (type_out)),
3779 GET_MODE_NAME (TYPE_MODE (type_in)));
3781 if (TREE_CODE (type_out) != VECTOR_TYPE
3782 || TREE_CODE (type_in) != VECTOR_TYPE
3783 || !TARGET_VECTORIZE_BUILTINS)
3784 return NULL_TREE;
3786 out_mode = TYPE_MODE (TREE_TYPE (type_out));
3787 out_n = TYPE_VECTOR_SUBPARTS (type_out);
3788 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3789 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3791 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3793 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3794 switch (fn)
3796 case BUILT_IN_COPYSIGN:
3797 if (VECTOR_UNIT_VSX_P (V2DFmode)
3798 && out_mode == DFmode && out_n == 2
3799 && in_mode == DFmode && in_n == 2)
3800 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3801 break;
3802 case BUILT_IN_COPYSIGNF:
3803 if (out_mode != SFmode || out_n != 4
3804 || in_mode != SFmode || in_n != 4)
3805 break;
3806 if (VECTOR_UNIT_VSX_P (V4SFmode))
3807 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3808 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3809 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3810 break;
3811 case BUILT_IN_SQRT:
3812 if (VECTOR_UNIT_VSX_P (V2DFmode)
3813 && out_mode == DFmode && out_n == 2
3814 && in_mode == DFmode && in_n == 2)
3815 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3816 break;
3817 case BUILT_IN_SQRTF:
3818 if (VECTOR_UNIT_VSX_P (V4SFmode)
3819 && out_mode == SFmode && out_n == 4
3820 && in_mode == SFmode && in_n == 4)
3821 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3822 break;
3823 case BUILT_IN_CEIL:
3824 if (VECTOR_UNIT_VSX_P (V2DFmode)
3825 && out_mode == DFmode && out_n == 2
3826 && in_mode == DFmode && in_n == 2)
3827 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3828 break;
3829 case BUILT_IN_CEILF:
3830 if (out_mode != SFmode || out_n != 4
3831 || in_mode != SFmode || in_n != 4)
3832 break;
3833 if (VECTOR_UNIT_VSX_P (V4SFmode))
3834 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3835 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3836 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3837 break;
3838 case BUILT_IN_FLOOR:
3839 if (VECTOR_UNIT_VSX_P (V2DFmode)
3840 && out_mode == DFmode && out_n == 2
3841 && in_mode == DFmode && in_n == 2)
3842 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3843 break;
3844 case BUILT_IN_FLOORF:
3845 if (out_mode != SFmode || out_n != 4
3846 || in_mode != SFmode || in_n != 4)
3847 break;
3848 if (VECTOR_UNIT_VSX_P (V4SFmode))
3849 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3850 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3851 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3852 break;
3853 case BUILT_IN_FMA:
3854 if (VECTOR_UNIT_VSX_P (V2DFmode)
3855 && out_mode == DFmode && out_n == 2
3856 && in_mode == DFmode && in_n == 2)
3857 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3858 break;
3859 case BUILT_IN_FMAF:
3860 if (VECTOR_UNIT_VSX_P (V4SFmode)
3861 && out_mode == SFmode && out_n == 4
3862 && in_mode == SFmode && in_n == 4)
3863 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3864 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3865 && out_mode == SFmode && out_n == 4
3866 && in_mode == SFmode && in_n == 4)
3867 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3868 break;
3869 case BUILT_IN_TRUNC:
3870 if (VECTOR_UNIT_VSX_P (V2DFmode)
3871 && out_mode == DFmode && out_n == 2
3872 && in_mode == DFmode && in_n == 2)
3873 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3874 break;
3875 case BUILT_IN_TRUNCF:
3876 if (out_mode != SFmode || out_n != 4
3877 || in_mode != SFmode || in_n != 4)
3878 break;
3879 if (VECTOR_UNIT_VSX_P (V4SFmode))
3880 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3881 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3882 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3883 break;
3884 case BUILT_IN_NEARBYINT:
3885 if (VECTOR_UNIT_VSX_P (V2DFmode)
3886 && flag_unsafe_math_optimizations
3887 && out_mode == DFmode && out_n == 2
3888 && in_mode == DFmode && in_n == 2)
3889 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3890 break;
3891 case BUILT_IN_NEARBYINTF:
3892 if (VECTOR_UNIT_VSX_P (V4SFmode)
3893 && flag_unsafe_math_optimizations
3894 && out_mode == SFmode && out_n == 4
3895 && in_mode == SFmode && in_n == 4)
3896 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3897 break;
3898 case BUILT_IN_RINT:
3899 if (VECTOR_UNIT_VSX_P (V2DFmode)
3900 && !flag_trapping_math
3901 && out_mode == DFmode && out_n == 2
3902 && in_mode == DFmode && in_n == 2)
3903 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3904 break;
3905 case BUILT_IN_RINTF:
3906 if (VECTOR_UNIT_VSX_P (V4SFmode)
3907 && !flag_trapping_math
3908 && out_mode == SFmode && out_n == 4
3909 && in_mode == SFmode && in_n == 4)
3910 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3911 break;
3912 default:
3913 break;
3917 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3919 enum rs6000_builtins fn
3920 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3921 switch (fn)
3923 case RS6000_BUILTIN_RSQRTF:
3924 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3925 && out_mode == SFmode && out_n == 4
3926 && in_mode == SFmode && in_n == 4)
3927 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3928 break;
3929 case RS6000_BUILTIN_RSQRT:
3930 if (VECTOR_UNIT_VSX_P (V2DFmode)
3931 && out_mode == DFmode && out_n == 2
3932 && in_mode == DFmode && in_n == 2)
3933 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3934 break;
3935 case RS6000_BUILTIN_RECIPF:
3936 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3937 && out_mode == SFmode && out_n == 4
3938 && in_mode == SFmode && in_n == 4)
3939 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3940 break;
3941 case RS6000_BUILTIN_RECIP:
3942 if (VECTOR_UNIT_VSX_P (V2DFmode)
3943 && out_mode == DFmode && out_n == 2
3944 && in_mode == DFmode && in_n == 2)
3945 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3946 break;
3947 default:
3948 break;
3952 /* Generate calls to libmass if appropriate. */
3953 if (rs6000_veclib_handler)
3954 return rs6000_veclib_handler (fndecl, type_out, type_in);
3956 return NULL_TREE;
3959 /* Default CPU string for rs6000*_file_start functions. */
3960 static const char *rs6000_default_cpu;
3962 /* Do anything needed at the start of the asm file. */
3964 static void
3965 rs6000_file_start (void)
3967 char buffer[80];
3968 const char *start = buffer;
3969 FILE *file = asm_out_file;
3971 rs6000_default_cpu = TARGET_CPU_DEFAULT;
3973 default_file_start ();
3975 if (flag_verbose_asm)
3977 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
3979 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
3981 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
3982 start = "";
3985 if (global_options_set.x_rs6000_cpu_index)
3987 fprintf (file, "%s -mcpu=%s", start,
3988 processor_target_table[rs6000_cpu_index].name);
3989 start = "";
3992 if (global_options_set.x_rs6000_tune_index)
3994 fprintf (file, "%s -mtune=%s", start,
3995 processor_target_table[rs6000_tune_index].name);
3996 start = "";
3999 if (PPC405_ERRATUM77)
4001 fprintf (file, "%s PPC405CR_ERRATUM77", start);
4002 start = "";
4005 #ifdef USING_ELFOS_H
4006 switch (rs6000_sdata)
4008 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
4009 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
4010 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
4011 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
4014 if (rs6000_sdata && g_switch_value)
4016 fprintf (file, "%s -G %d", start,
4017 g_switch_value);
4018 start = "";
4020 #endif
4022 if (*start == '\0')
4023 putc ('\n', file);
4026 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
4028 switch_to_section (toc_section);
4029 switch_to_section (text_section);
4034 /* Return nonzero if this function is known to have a null epilogue. */
4037 direct_return (void)
4039 if (reload_completed)
4041 rs6000_stack_t *info = rs6000_stack_info ();
4043 if (info->first_gp_reg_save == 32
4044 && info->first_fp_reg_save == 64
4045 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
4046 && ! info->lr_save_p
4047 && ! info->cr_save_p
4048 && info->vrsave_mask == 0
4049 && ! info->push_p)
4050 return 1;
4053 return 0;
4056 /* Return the number of instructions it takes to form a constant in an
4057 integer register. */
4060 num_insns_constant_wide (HOST_WIDE_INT value)
4062 /* signed constant loadable with addi */
4063 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
4064 return 1;
4066 /* constant loadable with addis */
4067 else if ((value & 0xffff) == 0
4068 && (value >> 31 == -1 || value >> 31 == 0))
4069 return 1;
4071 #if HOST_BITS_PER_WIDE_INT == 64
4072 else if (TARGET_POWERPC64)
4074 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
4075 HOST_WIDE_INT high = value >> 31;
4077 if (high == 0 || high == -1)
4078 return 2;
4080 high >>= 1;
4082 if (low == 0)
4083 return num_insns_constant_wide (high) + 1;
4084 else if (high == 0)
4085 return num_insns_constant_wide (low) + 1;
4086 else
4087 return (num_insns_constant_wide (high)
4088 + num_insns_constant_wide (low) + 1);
4090 #endif
4092 else
4093 return 2;
4097 num_insns_constant (rtx op, enum machine_mode mode)
4099 HOST_WIDE_INT low, high;
4101 switch (GET_CODE (op))
4103 case CONST_INT:
4104 #if HOST_BITS_PER_WIDE_INT == 64
4105 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4106 && mask64_operand (op, mode))
4107 return 2;
4108 else
4109 #endif
4110 return num_insns_constant_wide (INTVAL (op));
4112 case CONST_DOUBLE:
4113 if (mode == SFmode || mode == SDmode)
4115 long l;
4116 REAL_VALUE_TYPE rv;
4118 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4119 if (DECIMAL_FLOAT_MODE_P (mode))
4120 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
4121 else
4122 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4123 return num_insns_constant_wide ((HOST_WIDE_INT) l);
4126 if (mode == VOIDmode || mode == DImode)
4128 high = CONST_DOUBLE_HIGH (op);
4129 low = CONST_DOUBLE_LOW (op);
4131 else
4133 long l[2];
4134 REAL_VALUE_TYPE rv;
4136 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4137 if (DECIMAL_FLOAT_MODE_P (mode))
4138 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4139 else
4140 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4141 high = l[WORDS_BIG_ENDIAN == 0];
4142 low = l[WORDS_BIG_ENDIAN != 0];
4145 if (TARGET_32BIT)
4146 return (num_insns_constant_wide (low)
4147 + num_insns_constant_wide (high));
4148 else
4150 if ((high == 0 && low >= 0)
4151 || (high == -1 && low < 0))
4152 return num_insns_constant_wide (low);
4154 else if (mask64_operand (op, mode))
4155 return 2;
4157 else if (low == 0)
4158 return num_insns_constant_wide (high) + 1;
4160 else
4161 return (num_insns_constant_wide (high)
4162 + num_insns_constant_wide (low) + 1);
4165 default:
4166 gcc_unreachable ();
4170 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4171 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4172 corresponding element of the vector, but for V4SFmode and V2SFmode,
4173 the corresponding "float" is interpreted as an SImode integer. */
4175 HOST_WIDE_INT
4176 const_vector_elt_as_int (rtx op, unsigned int elt)
4178 rtx tmp;
4180 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4181 gcc_assert (GET_MODE (op) != V2DImode
4182 && GET_MODE (op) != V2DFmode);
4184 tmp = CONST_VECTOR_ELT (op, elt);
4185 if (GET_MODE (op) == V4SFmode
4186 || GET_MODE (op) == V2SFmode)
4187 tmp = gen_lowpart (SImode, tmp);
4188 return INTVAL (tmp);
4191 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4192 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4193 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4194 all items are set to the same value and contain COPIES replicas of the
4195 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4196 operand and the others are set to the value of the operand's msb. */
4198 static bool
4199 vspltis_constant (rtx op, unsigned step, unsigned copies)
4201 enum machine_mode mode = GET_MODE (op);
4202 enum machine_mode inner = GET_MODE_INNER (mode);
4204 unsigned i;
4205 unsigned nunits;
4206 unsigned bitsize;
4207 unsigned mask;
4209 HOST_WIDE_INT val;
4210 HOST_WIDE_INT splat_val;
4211 HOST_WIDE_INT msb_val;
4213 if (mode == V2DImode || mode == V2DFmode)
4214 return false;
4216 nunits = GET_MODE_NUNITS (mode);
4217 bitsize = GET_MODE_BITSIZE (inner);
4218 mask = GET_MODE_MASK (inner);
4220 val = const_vector_elt_as_int (op, nunits - 1);
4221 splat_val = val;
4222 msb_val = val > 0 ? 0 : -1;
4224 /* Construct the value to be splatted, if possible. If not, return 0. */
4225 for (i = 2; i <= copies; i *= 2)
4227 HOST_WIDE_INT small_val;
4228 bitsize /= 2;
4229 small_val = splat_val >> bitsize;
4230 mask >>= bitsize;
4231 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4232 return false;
4233 splat_val = small_val;
4236 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4237 if (EASY_VECTOR_15 (splat_val))
4240 /* Also check if we can splat, and then add the result to itself. Do so if
4241 the value is positive, of if the splat instruction is using OP's mode;
4242 for splat_val < 0, the splat and the add should use the same mode. */
4243 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4244 && (splat_val >= 0 || (step == 1 && copies == 1)))
4247 /* Also check if are loading up the most significant bit which can be done by
4248 loading up -1 and shifting the value left by -1. */
4249 else if (EASY_VECTOR_MSB (splat_val, inner))
4252 else
4253 return false;
4255 /* Check if VAL is present in every STEP-th element, and the
4256 other elements are filled with its most significant bit. */
4257 for (i = 0; i < nunits - 1; ++i)
4259 HOST_WIDE_INT desired_val;
4260 if (((i + 1) & (step - 1)) == 0)
4261 desired_val = val;
4262 else
4263 desired_val = msb_val;
4265 if (desired_val != const_vector_elt_as_int (op, i))
4266 return false;
4269 return true;
4273 /* Return true if OP is of the given MODE and can be synthesized
4274 with a vspltisb, vspltish or vspltisw. */
4276 bool
4277 easy_altivec_constant (rtx op, enum machine_mode mode)
4279 unsigned step, copies;
4281 if (mode == VOIDmode)
4282 mode = GET_MODE (op);
4283 else if (mode != GET_MODE (op))
4284 return false;
4286 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4287 constants. */
4288 if (mode == V2DFmode)
4289 return zero_constant (op, mode);
4291 if (mode == V2DImode)
4293 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4294 easy. */
4295 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4296 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4297 return false;
4299 if (zero_constant (op, mode))
4300 return true;
4302 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4303 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4304 return true;
4306 return false;
4309 /* Start with a vspltisw. */
4310 step = GET_MODE_NUNITS (mode) / 4;
4311 copies = 1;
4313 if (vspltis_constant (op, step, copies))
4314 return true;
4316 /* Then try with a vspltish. */
4317 if (step == 1)
4318 copies <<= 1;
4319 else
4320 step >>= 1;
4322 if (vspltis_constant (op, step, copies))
4323 return true;
4325 /* And finally a vspltisb. */
4326 if (step == 1)
4327 copies <<= 1;
4328 else
4329 step >>= 1;
4331 if (vspltis_constant (op, step, copies))
4332 return true;
4334 return false;
4337 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4338 result is OP. Abort if it is not possible. */
4341 gen_easy_altivec_constant (rtx op)
4343 enum machine_mode mode = GET_MODE (op);
4344 int nunits = GET_MODE_NUNITS (mode);
4345 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4346 unsigned step = nunits / 4;
4347 unsigned copies = 1;
4349 /* Start with a vspltisw. */
4350 if (vspltis_constant (op, step, copies))
4351 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4353 /* Then try with a vspltish. */
4354 if (step == 1)
4355 copies <<= 1;
4356 else
4357 step >>= 1;
4359 if (vspltis_constant (op, step, copies))
4360 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4362 /* And finally a vspltisb. */
4363 if (step == 1)
4364 copies <<= 1;
4365 else
4366 step >>= 1;
4368 if (vspltis_constant (op, step, copies))
4369 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4371 gcc_unreachable ();
4374 const char *
4375 output_vec_const_move (rtx *operands)
4377 int cst, cst2;
4378 enum machine_mode mode;
4379 rtx dest, vec;
4381 dest = operands[0];
4382 vec = operands[1];
4383 mode = GET_MODE (dest);
4385 if (TARGET_VSX)
4387 if (zero_constant (vec, mode))
4388 return "xxlxor %x0,%x0,%x0";
4390 if (mode == V2DImode
4391 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4392 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4393 return "vspltisw %0,-1";
4396 if (TARGET_ALTIVEC)
4398 rtx splat_vec;
4399 if (zero_constant (vec, mode))
4400 return "vxor %0,%0,%0";
4402 splat_vec = gen_easy_altivec_constant (vec);
4403 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4404 operands[1] = XEXP (splat_vec, 0);
4405 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4406 return "#";
4408 switch (GET_MODE (splat_vec))
4410 case V4SImode:
4411 return "vspltisw %0,%1";
4413 case V8HImode:
4414 return "vspltish %0,%1";
4416 case V16QImode:
4417 return "vspltisb %0,%1";
4419 default:
4420 gcc_unreachable ();
4424 gcc_assert (TARGET_SPE);
4426 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4427 pattern of V1DI, V4HI, and V2SF.
4429 FIXME: We should probably return # and add post reload
4430 splitters for these, but this way is so easy ;-). */
4431 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4432 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4433 operands[1] = CONST_VECTOR_ELT (vec, 0);
4434 operands[2] = CONST_VECTOR_ELT (vec, 1);
4435 if (cst == cst2)
4436 return "li %0,%1\n\tevmergelo %0,%0,%0";
4437 else
4438 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4441 /* Initialize TARGET of vector PAIRED to VALS. */
4443 void
4444 paired_expand_vector_init (rtx target, rtx vals)
4446 enum machine_mode mode = GET_MODE (target);
4447 int n_elts = GET_MODE_NUNITS (mode);
4448 int n_var = 0;
4449 rtx x, new_rtx, tmp, constant_op, op1, op2;
4450 int i;
4452 for (i = 0; i < n_elts; ++i)
4454 x = XVECEXP (vals, 0, i);
4455 if (!(CONST_INT_P (x)
4456 || GET_CODE (x) == CONST_DOUBLE
4457 || GET_CODE (x) == CONST_FIXED))
4458 ++n_var;
4460 if (n_var == 0)
4462 /* Load from constant pool. */
4463 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4464 return;
4467 if (n_var == 2)
4469 /* The vector is initialized only with non-constants. */
4470 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4471 XVECEXP (vals, 0, 1));
4473 emit_move_insn (target, new_rtx);
4474 return;
4477 /* One field is non-constant and the other one is a constant. Load the
4478 constant from the constant pool and use ps_merge instruction to
4479 construct the whole vector. */
4480 op1 = XVECEXP (vals, 0, 0);
4481 op2 = XVECEXP (vals, 0, 1);
4483 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4485 tmp = gen_reg_rtx (GET_MODE (constant_op));
4486 emit_move_insn (tmp, constant_op);
4488 if (CONSTANT_P (op1))
4489 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4490 else
4491 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4493 emit_move_insn (target, new_rtx);
4496 void
4497 paired_expand_vector_move (rtx operands[])
4499 rtx op0 = operands[0], op1 = operands[1];
4501 emit_move_insn (op0, op1);
4504 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4505 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4506 operands for the relation operation COND. This is a recursive
4507 function. */
4509 static void
4510 paired_emit_vector_compare (enum rtx_code rcode,
4511 rtx dest, rtx op0, rtx op1,
4512 rtx cc_op0, rtx cc_op1)
4514 rtx tmp = gen_reg_rtx (V2SFmode);
4515 rtx tmp1, max, min;
4517 gcc_assert (TARGET_PAIRED_FLOAT);
4518 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4520 switch (rcode)
4522 case LT:
4523 case LTU:
4524 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4525 return;
4526 case GE:
4527 case GEU:
4528 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4529 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4530 return;
4531 case LE:
4532 case LEU:
4533 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4534 return;
4535 case GT:
4536 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4537 return;
4538 case EQ:
4539 tmp1 = gen_reg_rtx (V2SFmode);
4540 max = gen_reg_rtx (V2SFmode);
4541 min = gen_reg_rtx (V2SFmode);
4542 gen_reg_rtx (V2SFmode);
4544 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4545 emit_insn (gen_selv2sf4
4546 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4547 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4548 emit_insn (gen_selv2sf4
4549 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4550 emit_insn (gen_subv2sf3 (tmp1, min, max));
4551 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4552 return;
4553 case NE:
4554 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4555 return;
4556 case UNLE:
4557 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4558 return;
4559 case UNLT:
4560 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4561 return;
4562 case UNGE:
4563 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4564 return;
4565 case UNGT:
4566 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4567 return;
4568 default:
4569 gcc_unreachable ();
4572 return;
4575 /* Emit vector conditional expression.
4576 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4577 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4580 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4581 rtx cond, rtx cc_op0, rtx cc_op1)
4583 enum rtx_code rcode = GET_CODE (cond);
4585 if (!TARGET_PAIRED_FLOAT)
4586 return 0;
4588 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4590 return 1;
4593 /* Initialize vector TARGET to VALS. */
4595 void
4596 rs6000_expand_vector_init (rtx target, rtx vals)
4598 enum machine_mode mode = GET_MODE (target);
4599 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4600 int n_elts = GET_MODE_NUNITS (mode);
4601 int n_var = 0, one_var = -1;
4602 bool all_same = true, all_const_zero = true;
4603 rtx x, mem;
4604 int i;
4606 for (i = 0; i < n_elts; ++i)
4608 x = XVECEXP (vals, 0, i);
4609 if (!(CONST_INT_P (x)
4610 || GET_CODE (x) == CONST_DOUBLE
4611 || GET_CODE (x) == CONST_FIXED))
4612 ++n_var, one_var = i;
4613 else if (x != CONST0_RTX (inner_mode))
4614 all_const_zero = false;
4616 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4617 all_same = false;
4620 if (n_var == 0)
4622 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4623 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4624 if ((int_vector_p || TARGET_VSX) && all_const_zero)
4626 /* Zero register. */
4627 emit_insn (gen_rtx_SET (VOIDmode, target,
4628 gen_rtx_XOR (mode, target, target)));
4629 return;
4631 else if (int_vector_p && easy_vector_constant (const_vec, mode))
4633 /* Splat immediate. */
4634 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4635 return;
4637 else
4639 /* Load from constant pool. */
4640 emit_move_insn (target, const_vec);
4641 return;
4645 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4646 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4648 rtx op0 = XVECEXP (vals, 0, 0);
4649 rtx op1 = XVECEXP (vals, 0, 1);
4650 if (all_same)
4652 if (!MEM_P (op0) && !REG_P (op0))
4653 op0 = force_reg (inner_mode, op0);
4654 if (mode == V2DFmode)
4655 emit_insn (gen_vsx_splat_v2df (target, op0));
4656 else
4657 emit_insn (gen_vsx_splat_v2di (target, op0));
4659 else
4661 op0 = force_reg (inner_mode, op0);
4662 op1 = force_reg (inner_mode, op1);
4663 if (mode == V2DFmode)
4664 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4665 else
4666 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4668 return;
4671 /* With single precision floating point on VSX, know that internally single
4672 precision is actually represented as a double, and either make 2 V2DF
4673 vectors, and convert these vectors to single precision, or do one
4674 conversion, and splat the result to the other elements. */
4675 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4677 if (all_same)
4679 rtx freg = gen_reg_rtx (V4SFmode);
4680 rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
4682 emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4683 emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4685 else
4687 rtx dbl_even = gen_reg_rtx (V2DFmode);
4688 rtx dbl_odd = gen_reg_rtx (V2DFmode);
4689 rtx flt_even = gen_reg_rtx (V4SFmode);
4690 rtx flt_odd = gen_reg_rtx (V4SFmode);
4691 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
4692 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
4693 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
4694 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
4696 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
4697 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
4698 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4699 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4700 rs6000_expand_extract_even (target, flt_even, flt_odd);
4702 return;
4705 /* Store value to stack temp. Load vector element. Splat. However, splat
4706 of 64-bit items is not supported on Altivec. */
4707 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4709 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
4710 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4711 XVECEXP (vals, 0, 0));
4712 x = gen_rtx_UNSPEC (VOIDmode,
4713 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4714 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4715 gen_rtvec (2,
4716 gen_rtx_SET (VOIDmode,
4717 target, mem),
4718 x)));
4719 x = gen_rtx_VEC_SELECT (inner_mode, target,
4720 gen_rtx_PARALLEL (VOIDmode,
4721 gen_rtvec (1, const0_rtx)));
4722 emit_insn (gen_rtx_SET (VOIDmode, target,
4723 gen_rtx_VEC_DUPLICATE (mode, x)));
4724 return;
4727 /* One field is non-constant. Load constant then overwrite
4728 varying field. */
4729 if (n_var == 1)
4731 rtx copy = copy_rtx (vals);
4733 /* Load constant part of vector, substitute neighboring value for
4734 varying element. */
4735 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4736 rs6000_expand_vector_init (target, copy);
4738 /* Insert variable. */
4739 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4740 return;
4743 /* Construct the vector in memory one field at a time
4744 and load the whole vector. */
4745 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
4746 for (i = 0; i < n_elts; i++)
4747 emit_move_insn (adjust_address_nv (mem, inner_mode,
4748 i * GET_MODE_SIZE (inner_mode)),
4749 XVECEXP (vals, 0, i));
4750 emit_move_insn (target, mem);
4753 /* Set field ELT of TARGET to VAL. */
4755 void
4756 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4758 enum machine_mode mode = GET_MODE (target);
4759 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4760 rtx reg = gen_reg_rtx (mode);
4761 rtx mask, mem, x;
4762 int width = GET_MODE_SIZE (inner_mode);
4763 int i;
4765 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4767 rtx (*set_func) (rtx, rtx, rtx, rtx)
4768 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4769 emit_insn (set_func (target, target, val, GEN_INT (elt)));
4770 return;
4773 /* Load single variable value. */
4774 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
4775 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4776 x = gen_rtx_UNSPEC (VOIDmode,
4777 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4778 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4779 gen_rtvec (2,
4780 gen_rtx_SET (VOIDmode,
4781 reg, mem),
4782 x)));
4784 /* Linear sequence. */
4785 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4786 for (i = 0; i < 16; ++i)
4787 XVECEXP (mask, 0, i) = GEN_INT (i);
4789 /* Set permute mask to insert element into target. */
4790 for (i = 0; i < width; ++i)
4791 XVECEXP (mask, 0, elt*width + i)
4792 = GEN_INT (i + 0x10);
4793 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4794 x = gen_rtx_UNSPEC (mode,
4795 gen_rtvec (3, target, reg,
4796 force_reg (V16QImode, x)),
4797 UNSPEC_VPERM);
4798 emit_insn (gen_rtx_SET (VOIDmode, target, x));
4801 /* Extract field ELT from VEC into TARGET. */
4803 void
4804 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4806 enum machine_mode mode = GET_MODE (vec);
4807 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4808 rtx mem;
4810 if (VECTOR_MEM_VSX_P (mode))
4812 switch (mode)
4814 default:
4815 break;
4816 case V2DFmode:
4817 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4818 return;
4819 case V2DImode:
4820 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4821 return;
4822 case V4SFmode:
4823 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4824 return;
4828 /* Allocate mode-sized buffer. */
4829 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
4831 emit_move_insn (mem, vec);
4833 /* Add offset to field within buffer matching vector element. */
4834 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4836 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4839 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4840 implement ANDing by the mask IN. */
4841 void
4842 build_mask64_2_operands (rtx in, rtx *out)
4844 #if HOST_BITS_PER_WIDE_INT >= 64
4845 unsigned HOST_WIDE_INT c, lsb, m1, m2;
4846 int shift;
4848 gcc_assert (GET_CODE (in) == CONST_INT);
4850 c = INTVAL (in);
4851 if (c & 1)
4853 /* Assume c initially something like 0x00fff000000fffff. The idea
4854 is to rotate the word so that the middle ^^^^^^ group of zeros
4855 is at the MS end and can be cleared with an rldicl mask. We then
4856 rotate back and clear off the MS ^^ group of zeros with a
4857 second rldicl. */
4858 c = ~c; /* c == 0xff000ffffff00000 */
4859 lsb = c & -c; /* lsb == 0x0000000000100000 */
4860 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
4861 c = ~c; /* c == 0x00fff000000fffff */
4862 c &= -lsb; /* c == 0x00fff00000000000 */
4863 lsb = c & -c; /* lsb == 0x0000100000000000 */
4864 c = ~c; /* c == 0xff000fffffffffff */
4865 c &= -lsb; /* c == 0xff00000000000000 */
4866 shift = 0;
4867 while ((lsb >>= 1) != 0)
4868 shift++; /* shift == 44 on exit from loop */
4869 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
4870 m1 = ~m1; /* m1 == 0x000000ffffffffff */
4871 m2 = ~c; /* m2 == 0x00ffffffffffffff */
4873 else
4875 /* Assume c initially something like 0xff000f0000000000. The idea
4876 is to rotate the word so that the ^^^ middle group of zeros
4877 is at the LS end and can be cleared with an rldicr mask. We then
4878 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4879 a second rldicr. */
4880 lsb = c & -c; /* lsb == 0x0000010000000000 */
4881 m2 = -lsb; /* m2 == 0xffffff0000000000 */
4882 c = ~c; /* c == 0x00fff0ffffffffff */
4883 c &= -lsb; /* c == 0x00fff00000000000 */
4884 lsb = c & -c; /* lsb == 0x0000100000000000 */
4885 c = ~c; /* c == 0xff000fffffffffff */
4886 c &= -lsb; /* c == 0xff00000000000000 */
4887 shift = 0;
4888 while ((lsb >>= 1) != 0)
4889 shift++; /* shift == 44 on exit from loop */
4890 m1 = ~c; /* m1 == 0x00ffffffffffffff */
4891 m1 >>= shift; /* m1 == 0x0000000000000fff */
4892 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
4895 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4896 masks will be all 1's. We are guaranteed more than one transition. */
4897 out[0] = GEN_INT (64 - shift);
4898 out[1] = GEN_INT (m1);
4899 out[2] = GEN_INT (shift);
4900 out[3] = GEN_INT (m2);
4901 #else
4902 (void)in;
4903 (void)out;
4904 gcc_unreachable ();
4905 #endif
4908 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4910 bool
4911 invalid_e500_subreg (rtx op, enum machine_mode mode)
4913 if (TARGET_E500_DOUBLE)
4915 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4916 subreg:TI and reg:TF. Decimal float modes are like integer
4917 modes (only low part of each register used) for this
4918 purpose. */
4919 if (GET_CODE (op) == SUBREG
4920 && (mode == SImode || mode == DImode || mode == TImode
4921 || mode == DDmode || mode == TDmode)
4922 && REG_P (SUBREG_REG (op))
4923 && (GET_MODE (SUBREG_REG (op)) == DFmode
4924 || GET_MODE (SUBREG_REG (op)) == TFmode))
4925 return true;
4927 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4928 reg:TI. */
4929 if (GET_CODE (op) == SUBREG
4930 && (mode == DFmode || mode == TFmode)
4931 && REG_P (SUBREG_REG (op))
4932 && (GET_MODE (SUBREG_REG (op)) == DImode
4933 || GET_MODE (SUBREG_REG (op)) == TImode
4934 || GET_MODE (SUBREG_REG (op)) == DDmode
4935 || GET_MODE (SUBREG_REG (op)) == TDmode))
4936 return true;
4939 if (TARGET_SPE
4940 && GET_CODE (op) == SUBREG
4941 && mode == SImode
4942 && REG_P (SUBREG_REG (op))
4943 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
4944 return true;
4946 return false;
4949 /* AIX increases natural record alignment to doubleword if the first
4950 field is an FP double while the FP fields remain word aligned. */
4952 unsigned int
4953 rs6000_special_round_type_align (tree type, unsigned int computed,
4954 unsigned int specified)
4956 unsigned int align = MAX (computed, specified);
4957 tree field = TYPE_FIELDS (type);
4959 /* Skip all non field decls */
4960 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4961 field = DECL_CHAIN (field);
4963 if (field != NULL && field != type)
4965 type = TREE_TYPE (field);
4966 while (TREE_CODE (type) == ARRAY_TYPE)
4967 type = TREE_TYPE (type);
4969 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
4970 align = MAX (align, 64);
4973 return align;
4976 /* Darwin increases record alignment to the natural alignment of
4977 the first field. */
4979 unsigned int
4980 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
4981 unsigned int specified)
4983 unsigned int align = MAX (computed, specified);
4985 if (TYPE_PACKED (type))
4986 return align;
4988 /* Find the first field, looking down into aggregates. */
4989 do {
4990 tree field = TYPE_FIELDS (type);
4991 /* Skip all non field decls */
4992 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4993 field = DECL_CHAIN (field);
4994 if (! field)
4995 break;
4996 /* A packed field does not contribute any extra alignment. */
4997 if (DECL_PACKED (field))
4998 return align;
4999 type = TREE_TYPE (field);
5000 while (TREE_CODE (type) == ARRAY_TYPE)
5001 type = TREE_TYPE (type);
5002 } while (AGGREGATE_TYPE_P (type));
5004 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
5005 align = MAX (align, TYPE_ALIGN (type));
5007 return align;
5010 /* Return 1 for an operand in small memory on V.4/eabi. */
5013 small_data_operand (rtx op ATTRIBUTE_UNUSED,
5014 enum machine_mode mode ATTRIBUTE_UNUSED)
5016 #if TARGET_ELF
5017 rtx sym_ref;
5019 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
5020 return 0;
5022 if (DEFAULT_ABI != ABI_V4)
5023 return 0;
5025 /* Vector and float memory instructions have a limited offset on the
5026 SPE, so using a vector or float variable directly as an operand is
5027 not useful. */
5028 if (TARGET_SPE
5029 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
5030 return 0;
5032 if (GET_CODE (op) == SYMBOL_REF)
5033 sym_ref = op;
5035 else if (GET_CODE (op) != CONST
5036 || GET_CODE (XEXP (op, 0)) != PLUS
5037 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
5038 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
5039 return 0;
5041 else
5043 rtx sum = XEXP (op, 0);
5044 HOST_WIDE_INT summand;
5046 /* We have to be careful here, because it is the referenced address
5047 that must be 32k from _SDA_BASE_, not just the symbol. */
5048 summand = INTVAL (XEXP (sum, 1));
5049 if (summand < 0 || summand > g_switch_value)
5050 return 0;
5052 sym_ref = XEXP (sum, 0);
5055 return SYMBOL_REF_SMALL_P (sym_ref);
5056 #else
5057 return 0;
5058 #endif
5061 /* Return true if either operand is a general purpose register. */
5063 bool
5064 gpr_or_gpr_p (rtx op0, rtx op1)
5066 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
5067 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
5070 /* Given an address, return a constant offset term if one exists. */
5072 static rtx
5073 address_offset (rtx op)
5075 if (GET_CODE (op) == PRE_INC
5076 || GET_CODE (op) == PRE_DEC)
5077 op = XEXP (op, 0);
5078 else if (GET_CODE (op) == PRE_MODIFY
5079 || GET_CODE (op) == LO_SUM)
5080 op = XEXP (op, 1);
5082 if (GET_CODE (op) == CONST)
5083 op = XEXP (op, 0);
5085 if (GET_CODE (op) == PLUS)
5086 op = XEXP (op, 1);
5088 if (CONST_INT_P (op))
5089 return op;
5091 return NULL_RTX;
5094 /* Return true if the MEM operand is a memory operand suitable for use
5095 with a (full width, possibly multiple) gpr load/store. On
5096 powerpc64 this means the offset must be divisible by 4.
5097 Implements 'Y' constraint.
5099 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5100 a constraint function we know the operand has satisfied a suitable
5101 memory predicate. Also accept some odd rtl generated by reload
5102 (see rs6000_legitimize_reload_address for various forms). It is
5103 important that reload rtl be accepted by appropriate constraints
5104 but not by the operand predicate.
5106 Offsetting a lo_sum should not be allowed, except where we know by
5107 alignment that a 32k boundary is not crossed, but see the ???
5108 comment in rs6000_legitimize_reload_address. Note that by
5109 "offsetting" here we mean a further offset to access parts of the
5110 MEM. It's fine to have a lo_sum where the inner address is offset
5111 from a sym, since the same sym+offset will appear in the high part
5112 of the address calculation. */
5114 bool
5115 mem_operand_gpr (rtx op, enum machine_mode mode)
5117 unsigned HOST_WIDE_INT offset;
5118 int extra;
5119 rtx addr = XEXP (op, 0);
5121 op = address_offset (addr);
5122 if (op == NULL_RTX)
5123 return true;
5125 offset = INTVAL (op);
5126 if (TARGET_POWERPC64 && (offset & 3) != 0)
5127 return false;
5129 if (GET_CODE (addr) == LO_SUM)
5130 /* We know by alignment that ABI_AIX medium/large model toc refs
5131 will not cross a 32k boundary, since all entries in the
5132 constant pool are naturally aligned and we check alignment for
5133 other medium model toc-relative addresses. For ABI_V4 and
5134 ABI_DARWIN lo_sum addresses, we just check that 64-bit
5135 offsets are 4-byte aligned. */
5136 return true;
5138 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
5139 gcc_assert (extra >= 0);
5140 return offset + 0x8000 < 0x10000u - extra;
5143 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5145 static bool
5146 reg_offset_addressing_ok_p (enum machine_mode mode)
5148 switch (mode)
5150 case V16QImode:
5151 case V8HImode:
5152 case V4SFmode:
5153 case V4SImode:
5154 case V2DFmode:
5155 case V2DImode:
5156 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5157 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
5158 return false;
5159 break;
5161 case V4HImode:
5162 case V2SImode:
5163 case V1DImode:
5164 case V2SFmode:
5165 /* Paired vector modes. Only reg+reg addressing is valid. */
5166 if (TARGET_PAIRED_FLOAT)
5167 return false;
5168 break;
5170 default:
5171 break;
5174 return true;
5177 static bool
5178 virtual_stack_registers_memory_p (rtx op)
5180 int regnum;
5182 if (GET_CODE (op) == REG)
5183 regnum = REGNO (op);
5185 else if (GET_CODE (op) == PLUS
5186 && GET_CODE (XEXP (op, 0)) == REG
5187 && GET_CODE (XEXP (op, 1)) == CONST_INT)
5188 regnum = REGNO (XEXP (op, 0));
5190 else
5191 return false;
5193 return (regnum >= FIRST_VIRTUAL_REGISTER
5194 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
5197 /* Return true if memory accesses to OP are known to never straddle
5198 a 32k boundary. */
5200 static bool
5201 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5202 enum machine_mode mode)
5204 tree decl, type;
5205 unsigned HOST_WIDE_INT dsize, dalign;
5207 if (GET_CODE (op) != SYMBOL_REF)
5208 return false;
5210 decl = SYMBOL_REF_DECL (op);
5211 if (!decl)
5213 if (GET_MODE_SIZE (mode) == 0)
5214 return false;
5216 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5217 replacing memory addresses with an anchor plus offset. We
5218 could find the decl by rummaging around in the block->objects
5219 VEC for the given offset but that seems like too much work. */
5220 dalign = 1;
5221 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5222 && SYMBOL_REF_ANCHOR_P (op)
5223 && SYMBOL_REF_BLOCK (op) != NULL)
5225 struct object_block *block = SYMBOL_REF_BLOCK (op);
5226 HOST_WIDE_INT lsb, mask;
5228 /* Given the alignment of the block.. */
5229 dalign = block->alignment;
5230 mask = dalign / BITS_PER_UNIT - 1;
5232 /* ..and the combined offset of the anchor and any offset
5233 to this block object.. */
5234 offset += SYMBOL_REF_BLOCK_OFFSET (op);
5235 lsb = offset & -offset;
5237 /* ..find how many bits of the alignment we know for the
5238 object. */
5239 mask &= lsb - 1;
5240 dalign = mask + 1;
5242 return dalign >= GET_MODE_SIZE (mode);
5245 if (DECL_P (decl))
5247 if (TREE_CODE (decl) == FUNCTION_DECL)
5248 return true;
5250 if (!DECL_SIZE_UNIT (decl))
5251 return false;
5253 if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5254 return false;
5256 dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5257 if (dsize > 32768)
5258 return false;
5260 dalign = DECL_ALIGN_UNIT (decl);
5261 return dalign >= dsize;
5264 type = TREE_TYPE (decl);
5266 if (TREE_CODE (decl) == STRING_CST)
5267 dsize = TREE_STRING_LENGTH (decl);
5268 else if (TYPE_SIZE_UNIT (type)
5269 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5270 dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5271 else
5272 return false;
5273 if (dsize > 32768)
5274 return false;
5276 dalign = TYPE_ALIGN (type);
5277 if (CONSTANT_CLASS_P (decl))
5278 dalign = CONSTANT_ALIGNMENT (decl, dalign);
5279 else
5280 dalign = DATA_ALIGNMENT (decl, dalign);
5281 dalign /= BITS_PER_UNIT;
5282 return dalign >= dsize;
5285 static bool
5286 constant_pool_expr_p (rtx op)
5288 rtx base, offset;
5290 split_const (op, &base, &offset);
5291 return (GET_CODE (base) == SYMBOL_REF
5292 && CONSTANT_POOL_ADDRESS_P (base)
5293 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5296 static const_rtx tocrel_base, tocrel_offset;
5298 /* Return true if OP is a toc pointer relative address (the output
5299 of create_TOC_reference). If STRICT, do not match high part or
5300 non-split -mcmodel=large/medium toc pointer relative addresses. */
5302 bool
5303 toc_relative_expr_p (const_rtx op, bool strict)
5305 if (!TARGET_TOC)
5306 return false;
5308 if (TARGET_CMODEL != CMODEL_SMALL)
5310 /* Only match the low part. */
5311 if (GET_CODE (op) == LO_SUM
5312 && REG_P (XEXP (op, 0))
5313 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict))
5314 op = XEXP (op, 1);
5315 else if (strict)
5316 return false;
5319 tocrel_base = op;
5320 tocrel_offset = const0_rtx;
5321 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
5323 tocrel_base = XEXP (op, 0);
5324 tocrel_offset = XEXP (op, 1);
5327 return (GET_CODE (tocrel_base) == UNSPEC
5328 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5331 /* Return true if X is a constant pool address, and also for cmodel=medium
5332 if X is a toc-relative address known to be offsettable within MODE. */
5334 bool
5335 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5336 bool strict)
5338 return (toc_relative_expr_p (x, strict)
5339 && (TARGET_CMODEL != CMODEL_MEDIUM
5340 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5341 || mode == QImode
5342 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5343 INTVAL (tocrel_offset), mode)));
5346 static bool
5347 legitimate_small_data_p (enum machine_mode mode, rtx x)
5349 return (DEFAULT_ABI == ABI_V4
5350 && !flag_pic && !TARGET_TOC
5351 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5352 && small_data_operand (x, mode));
5355 /* SPE offset addressing is limited to 5-bits worth of double words. */
5356 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5358 bool
5359 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x,
5360 bool strict, bool worst_case)
5362 unsigned HOST_WIDE_INT offset;
5363 unsigned int extra;
5365 if (GET_CODE (x) != PLUS)
5366 return false;
5367 if (!REG_P (XEXP (x, 0)))
5368 return false;
5369 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5370 return false;
5371 if (!reg_offset_addressing_ok_p (mode))
5372 return virtual_stack_registers_memory_p (x);
5373 if (legitimate_constant_pool_address_p (x, mode, strict))
5374 return true;
5375 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5376 return false;
5378 offset = INTVAL (XEXP (x, 1));
5379 extra = 0;
5380 switch (mode)
5382 case V4HImode:
5383 case V2SImode:
5384 case V1DImode:
5385 case V2SFmode:
5386 /* SPE vector modes. */
5387 return SPE_CONST_OFFSET_OK (offset);
5389 case DFmode:
5390 case DDmode:
5391 case DImode:
5392 /* On e500v2, we may have:
5394 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5396 Which gets addressed with evldd instructions. */
5397 if (TARGET_E500_DOUBLE)
5398 return SPE_CONST_OFFSET_OK (offset);
5400 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5401 addressing. */
5402 if (mode == DFmode && VECTOR_MEM_VSX_P (DFmode))
5403 return false;
5405 if (!worst_case)
5406 break;
5407 if (!TARGET_POWERPC64)
5408 extra = 4;
5409 else if (offset & 3)
5410 return false;
5411 break;
5413 case TFmode:
5414 case TDmode:
5415 case TImode:
5416 if (TARGET_E500_DOUBLE)
5417 return (SPE_CONST_OFFSET_OK (offset)
5418 && SPE_CONST_OFFSET_OK (offset + 8));
5420 extra = 8;
5421 if (!worst_case)
5422 break;
5423 if (!TARGET_POWERPC64)
5424 extra = 12;
5425 else if (offset & 3)
5426 return false;
5427 break;
5429 default:
5430 break;
5433 offset += 0x8000;
5434 return offset < 0x10000 - extra;
5437 bool
5438 legitimate_indexed_address_p (rtx x, int strict)
5440 rtx op0, op1;
5442 if (GET_CODE (x) != PLUS)
5443 return false;
5445 op0 = XEXP (x, 0);
5446 op1 = XEXP (x, 1);
5448 /* Recognize the rtl generated by reload which we know will later be
5449 replaced with proper base and index regs. */
5450 if (!strict
5451 && reload_in_progress
5452 && (REG_P (op0) || GET_CODE (op0) == PLUS)
5453 && REG_P (op1))
5454 return true;
5456 return (REG_P (op0) && REG_P (op1)
5457 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5458 && INT_REG_OK_FOR_INDEX_P (op1, strict))
5459 || (INT_REG_OK_FOR_BASE_P (op1, strict)
5460 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5463 bool
5464 avoiding_indexed_address_p (enum machine_mode mode)
5466 /* Avoid indexed addressing for modes that have non-indexed
5467 load/store instruction forms. */
5468 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5471 bool
5472 legitimate_indirect_address_p (rtx x, int strict)
5474 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5477 bool
5478 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5480 if (!TARGET_MACHO || !flag_pic
5481 || mode != SImode || GET_CODE (x) != MEM)
5482 return false;
5483 x = XEXP (x, 0);
5485 if (GET_CODE (x) != LO_SUM)
5486 return false;
5487 if (GET_CODE (XEXP (x, 0)) != REG)
5488 return false;
5489 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5490 return false;
5491 x = XEXP (x, 1);
5493 return CONSTANT_P (x);
5496 static bool
5497 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5499 if (GET_CODE (x) != LO_SUM)
5500 return false;
5501 if (GET_CODE (XEXP (x, 0)) != REG)
5502 return false;
5503 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5504 return false;
5505 /* Restrict addressing for DI because of our SUBREG hackery. */
5506 if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
5507 return false;
5508 x = XEXP (x, 1);
5510 if (TARGET_ELF || TARGET_MACHO)
5512 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5513 return false;
5514 if (TARGET_TOC)
5515 return false;
5516 if (GET_MODE_NUNITS (mode) != 1)
5517 return false;
5518 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5519 && !(/* ??? Assume floating point reg based on mode? */
5520 TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5521 && (mode == DFmode || mode == DDmode)))
5522 return false;
5524 return CONSTANT_P (x);
5527 return false;
5531 /* Try machine-dependent ways of modifying an illegitimate address
5532 to be legitimate. If we find one, return the new, valid address.
5533 This is used from only one place: `memory_address' in explow.c.
5535 OLDX is the address as it was before break_out_memory_refs was
5536 called. In some cases it is useful to look at this to decide what
5537 needs to be done.
5539 It is always safe for this function to do nothing. It exists to
5540 recognize opportunities to optimize the output.
5542 On RS/6000, first check for the sum of a register with a constant
5543 integer that is out of range. If so, generate code to add the
5544 constant with the low-order 16 bits masked to the register and force
5545 this result into another register (this can be done with `cau').
5546 Then generate an address of REG+(CONST&0xffff), allowing for the
5547 possibility of bit 16 being a one.
5549 Then check for the sum of a register and something not constant, try to
5550 load the other things into a register and return the sum. */
5552 static rtx
5553 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5554 enum machine_mode mode)
5556 unsigned int extra;
5558 if (!reg_offset_addressing_ok_p (mode))
5560 if (virtual_stack_registers_memory_p (x))
5561 return x;
5563 /* In theory we should not be seeing addresses of the form reg+0,
5564 but just in case it is generated, optimize it away. */
5565 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5566 return force_reg (Pmode, XEXP (x, 0));
5568 /* Make sure both operands are registers. */
5569 else if (GET_CODE (x) == PLUS)
5570 return gen_rtx_PLUS (Pmode,
5571 force_reg (Pmode, XEXP (x, 0)),
5572 force_reg (Pmode, XEXP (x, 1)));
5573 else
5574 return force_reg (Pmode, x);
5576 if (GET_CODE (x) == SYMBOL_REF)
5578 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5579 if (model != 0)
5580 return rs6000_legitimize_tls_address (x, model);
5583 extra = 0;
5584 switch (mode)
5586 case TFmode:
5587 case TDmode:
5588 case TImode:
5589 /* As in legitimate_offset_address_p we do not assume
5590 worst-case. The mode here is just a hint as to the registers
5591 used. A TImode is usually in gprs, but may actually be in
5592 fprs. Leave worst-case scenario for reload to handle via
5593 insn constraints. */
5594 extra = 8;
5595 break;
5596 default:
5597 break;
5600 if (GET_CODE (x) == PLUS
5601 && GET_CODE (XEXP (x, 0)) == REG
5602 && GET_CODE (XEXP (x, 1)) == CONST_INT
5603 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5604 >= 0x10000 - extra)
5605 && !(SPE_VECTOR_MODE (mode)
5606 || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)))
5608 HOST_WIDE_INT high_int, low_int;
5609 rtx sum;
5610 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5611 if (low_int >= 0x8000 - extra)
5612 low_int = 0;
5613 high_int = INTVAL (XEXP (x, 1)) - low_int;
5614 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5615 GEN_INT (high_int)), 0);
5616 return plus_constant (Pmode, sum, low_int);
5618 else if (GET_CODE (x) == PLUS
5619 && GET_CODE (XEXP (x, 0)) == REG
5620 && GET_CODE (XEXP (x, 1)) != CONST_INT
5621 && GET_MODE_NUNITS (mode) == 1
5622 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
5623 || (/* ??? Assume floating point reg based on mode? */
5624 (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5625 && (mode == DFmode || mode == DDmode)))
5626 && !avoiding_indexed_address_p (mode))
5628 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5629 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5631 else if (SPE_VECTOR_MODE (mode)
5632 || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD))
5634 if (mode == DImode)
5635 return x;
5636 /* We accept [reg + reg] and [reg + OFFSET]. */
5638 if (GET_CODE (x) == PLUS)
5640 rtx op1 = XEXP (x, 0);
5641 rtx op2 = XEXP (x, 1);
5642 rtx y;
5644 op1 = force_reg (Pmode, op1);
5646 if (GET_CODE (op2) != REG
5647 && (GET_CODE (op2) != CONST_INT
5648 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5649 || (GET_MODE_SIZE (mode) > 8
5650 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5651 op2 = force_reg (Pmode, op2);
5653 /* We can't always do [reg + reg] for these, because [reg +
5654 reg + offset] is not a legitimate addressing mode. */
5655 y = gen_rtx_PLUS (Pmode, op1, op2);
5657 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5658 return force_reg (Pmode, y);
5659 else
5660 return y;
5663 return force_reg (Pmode, x);
5665 else if ((TARGET_ELF
5666 #if TARGET_MACHO
5667 || !MACHO_DYNAMIC_NO_PIC_P
5668 #endif
5670 && TARGET_32BIT
5671 && TARGET_NO_TOC
5672 && ! flag_pic
5673 && GET_CODE (x) != CONST_INT
5674 && GET_CODE (x) != CONST_DOUBLE
5675 && CONSTANT_P (x)
5676 && GET_MODE_NUNITS (mode) == 1
5677 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
5678 || (/* ??? Assume floating point reg based on mode? */
5679 (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5680 && (mode == DFmode || mode == DDmode))))
5682 rtx reg = gen_reg_rtx (Pmode);
5683 if (TARGET_ELF)
5684 emit_insn (gen_elf_high (reg, x));
5685 else
5686 emit_insn (gen_macho_high (reg, x));
5687 return gen_rtx_LO_SUM (Pmode, reg, x);
5689 else if (TARGET_TOC
5690 && GET_CODE (x) == SYMBOL_REF
5691 && constant_pool_expr_p (x)
5692 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5693 return create_TOC_reference (x, NULL_RTX);
5694 else
5695 return x;
5698 /* Debug version of rs6000_legitimize_address. */
5699 static rtx
5700 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5702 rtx ret;
5703 rtx insns;
5705 start_sequence ();
5706 ret = rs6000_legitimize_address (x, oldx, mode);
5707 insns = get_insns ();
5708 end_sequence ();
5710 if (ret != x)
5712 fprintf (stderr,
5713 "\nrs6000_legitimize_address: mode %s, old code %s, "
5714 "new code %s, modified\n",
5715 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5716 GET_RTX_NAME (GET_CODE (ret)));
5718 fprintf (stderr, "Original address:\n");
5719 debug_rtx (x);
5721 fprintf (stderr, "oldx:\n");
5722 debug_rtx (oldx);
5724 fprintf (stderr, "New address:\n");
5725 debug_rtx (ret);
5727 if (insns)
5729 fprintf (stderr, "Insns added:\n");
5730 debug_rtx_list (insns, 20);
5733 else
5735 fprintf (stderr,
5736 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5737 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5739 debug_rtx (x);
5742 if (insns)
5743 emit_insn (insns);
5745 return ret;
5748 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5749 We need to emit DTP-relative relocations. */
5751 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5752 static void
5753 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5755 switch (size)
5757 case 4:
5758 fputs ("\t.long\t", file);
5759 break;
5760 case 8:
5761 fputs (DOUBLE_INT_ASM_OP, file);
5762 break;
5763 default:
5764 gcc_unreachable ();
5766 output_addr_const (file, x);
5767 fputs ("@dtprel+0x8000", file);
5770 /* In the name of slightly smaller debug output, and to cater to
5771 general assembler lossage, recognize various UNSPEC sequences
5772 and turn them back into a direct symbol reference. */
5774 static rtx
5775 rs6000_delegitimize_address (rtx orig_x)
5777 rtx x, y, offset;
5779 orig_x = delegitimize_mem_from_attrs (orig_x);
5780 x = orig_x;
5781 if (MEM_P (x))
5782 x = XEXP (x, 0);
5784 y = x;
5785 if (TARGET_CMODEL != CMODEL_SMALL
5786 && GET_CODE (y) == LO_SUM)
5787 y = XEXP (y, 1);
5789 offset = NULL_RTX;
5790 if (GET_CODE (y) == PLUS
5791 && GET_MODE (y) == Pmode
5792 && CONST_INT_P (XEXP (y, 1)))
5794 offset = XEXP (y, 1);
5795 y = XEXP (y, 0);
5798 if (GET_CODE (y) == UNSPEC
5799 && XINT (y, 1) == UNSPEC_TOCREL)
5801 #ifdef ENABLE_CHECKING
5802 if (REG_P (XVECEXP (y, 0, 1))
5803 && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER)
5805 /* All good. */
5807 else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR)
5809 /* Weirdness alert. df_note_compute can replace r2 with a
5810 debug_expr when this unspec is in a debug_insn.
5811 Seen in gcc.dg/pr51957-1.c */
5813 else
5815 debug_rtx (orig_x);
5816 abort ();
5818 #endif
5819 y = XVECEXP (y, 0, 0);
5820 if (offset != NULL_RTX)
5821 y = gen_rtx_PLUS (Pmode, y, offset);
5822 if (!MEM_P (orig_x))
5823 return y;
5824 else
5825 return replace_equiv_address_nv (orig_x, y);
5828 if (TARGET_MACHO
5829 && GET_CODE (orig_x) == LO_SUM
5830 && GET_CODE (XEXP (orig_x, 1)) == CONST)
5832 y = XEXP (XEXP (orig_x, 1), 0);
5833 if (GET_CODE (y) == UNSPEC
5834 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5835 return XVECEXP (y, 0, 0);
5838 return orig_x;
5841 /* Return true if X shouldn't be emitted into the debug info.
5842 The linker doesn't like .toc section references from
5843 .debug_* sections, so reject .toc section symbols. */
5845 static bool
5846 rs6000_const_not_ok_for_debug_p (rtx x)
5848 if (GET_CODE (x) == SYMBOL_REF
5849 && CONSTANT_POOL_ADDRESS_P (x))
5851 rtx c = get_pool_constant (x);
5852 enum machine_mode cmode = get_pool_mode (x);
5853 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
5854 return true;
5857 return false;
5860 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5862 static GTY(()) rtx rs6000_tls_symbol;
5863 static rtx
5864 rs6000_tls_get_addr (void)
5866 if (!rs6000_tls_symbol)
5867 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5869 return rs6000_tls_symbol;
5872 /* Construct the SYMBOL_REF for TLS GOT references. */
5874 static GTY(()) rtx rs6000_got_symbol;
5875 static rtx
5876 rs6000_got_sym (void)
5878 if (!rs6000_got_symbol)
5880 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5881 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5882 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5885 return rs6000_got_symbol;
5888 /* AIX Thread-Local Address support. */
5890 static rtx
5891 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
5893 rtx sym, mem, tocref, tlsreg, tmpreg, dest;
5895 /* Place addr into TOC constant pool. */
5896 sym = force_const_mem (GET_MODE (addr), addr);
5898 /* Output the TOC entry and create the MEM referencing the value. */
5899 if (constant_pool_expr_p (XEXP (sym, 0))
5900 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
5902 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
5903 mem = gen_const_mem (Pmode, tocref);
5904 set_mem_alias_set (mem, get_TOC_alias_set ());
5906 else
5907 return sym;
5909 /* Use global-dynamic for local-dynamic. */
5910 if (model == TLS_MODEL_GLOBAL_DYNAMIC
5911 || model == TLS_MODEL_LOCAL_DYNAMIC)
5913 rtx module = gen_reg_rtx (Pmode);
5914 /* Create new TOC reference for @m symbol. */
5915 const char *name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
5916 char *name2 = XALLOCAVEC (char, strlen (name) + 1);
5917 strcpy (name2, "*LCM");
5918 strcat (name2, name + 3);
5919 tocref = create_TOC_reference (gen_rtx_SYMBOL_REF (Pmode,
5920 ggc_alloc_string (name2,
5921 strlen (name2))),
5922 NULL_RTX);
5923 rtx mem2 = gen_const_mem (Pmode, tocref);
5924 set_mem_alias_set (mem2, get_TOC_alias_set ());
5926 dest = gen_reg_rtx (Pmode);
5927 tmpreg = gen_reg_rtx (Pmode);
5928 emit_insn (gen_rtx_SET (VOIDmode, tmpreg, mem));
5929 emit_insn (gen_rtx_SET (VOIDmode, module, mem2));
5930 if (TARGET_32BIT)
5931 emit_insn (gen_tls_get_addrsi (dest, module, tmpreg));
5932 else
5933 emit_insn (gen_tls_get_addrdi (dest, module, tmpreg));
5934 return dest;
5936 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
5937 else if (TARGET_32BIT)
5939 tlsreg = gen_reg_rtx (SImode);
5940 emit_insn (gen_tls_get_tpointer (tlsreg));
5942 else
5943 tlsreg = gen_rtx_REG (DImode, 13);
5945 /* Load the TOC value into temporary register. */
5946 tmpreg = gen_reg_rtx (Pmode);
5947 emit_insn (gen_rtx_SET (VOIDmode, tmpreg, mem));
5948 set_unique_reg_note (get_last_insn (), REG_EQUAL,
5949 gen_rtx_MINUS (Pmode, addr, tlsreg));
5951 /* Add TOC symbol value to TLS pointer. */
5952 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
5954 return dest;
5957 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5958 this (thread-local) address. */
5960 static rtx
5961 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
5963 rtx dest, insn;
5965 if (TARGET_XCOFF)
5966 return rs6000_legitimize_tls_address_aix (addr, model);
5968 dest = gen_reg_rtx (Pmode);
5969 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
5971 rtx tlsreg;
5973 if (TARGET_64BIT)
5975 tlsreg = gen_rtx_REG (Pmode, 13);
5976 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
5978 else
5980 tlsreg = gen_rtx_REG (Pmode, 2);
5981 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
5983 emit_insn (insn);
5985 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
5987 rtx tlsreg, tmp;
5989 tmp = gen_reg_rtx (Pmode);
5990 if (TARGET_64BIT)
5992 tlsreg = gen_rtx_REG (Pmode, 13);
5993 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
5995 else
5997 tlsreg = gen_rtx_REG (Pmode, 2);
5998 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
6000 emit_insn (insn);
6001 if (TARGET_64BIT)
6002 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
6003 else
6004 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
6005 emit_insn (insn);
6007 else
6009 rtx r3, got, tga, tmp1, tmp2, call_insn;
6011 /* We currently use relocations like @got@tlsgd for tls, which
6012 means the linker will handle allocation of tls entries, placing
6013 them in the .got section. So use a pointer to the .got section,
6014 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6015 or to secondary GOT sections used by 32-bit -fPIC. */
6016 if (TARGET_64BIT)
6017 got = gen_rtx_REG (Pmode, 2);
6018 else
6020 if (flag_pic == 1)
6021 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
6022 else
6024 rtx gsym = rs6000_got_sym ();
6025 got = gen_reg_rtx (Pmode);
6026 if (flag_pic == 0)
6027 rs6000_emit_move (got, gsym, Pmode);
6028 else
6030 rtx mem, lab, last;
6032 tmp1 = gen_reg_rtx (Pmode);
6033 tmp2 = gen_reg_rtx (Pmode);
6034 mem = gen_const_mem (Pmode, tmp1);
6035 lab = gen_label_rtx ();
6036 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
6037 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
6038 if (TARGET_LINK_STACK)
6039 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
6040 emit_move_insn (tmp2, mem);
6041 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
6042 set_unique_reg_note (last, REG_EQUAL, gsym);
6047 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
6049 tga = rs6000_tls_get_addr ();
6050 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
6051 1, const0_rtx, Pmode);
6053 r3 = gen_rtx_REG (Pmode, 3);
6054 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
6055 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
6056 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
6057 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
6058 else if (DEFAULT_ABI == ABI_V4)
6059 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
6060 else
6061 gcc_unreachable ();
6062 call_insn = last_call_insn ();
6063 PATTERN (call_insn) = insn;
6064 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
6065 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6066 pic_offset_table_rtx);
6068 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
6070 tga = rs6000_tls_get_addr ();
6071 tmp1 = gen_reg_rtx (Pmode);
6072 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
6073 1, const0_rtx, Pmode);
6075 r3 = gen_rtx_REG (Pmode, 3);
6076 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
6077 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
6078 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
6079 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
6080 else if (DEFAULT_ABI == ABI_V4)
6081 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
6082 else
6083 gcc_unreachable ();
6084 call_insn = last_call_insn ();
6085 PATTERN (call_insn) = insn;
6086 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
6087 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6088 pic_offset_table_rtx);
6090 if (rs6000_tls_size == 16)
6092 if (TARGET_64BIT)
6093 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
6094 else
6095 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
6097 else if (rs6000_tls_size == 32)
6099 tmp2 = gen_reg_rtx (Pmode);
6100 if (TARGET_64BIT)
6101 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
6102 else
6103 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
6104 emit_insn (insn);
6105 if (TARGET_64BIT)
6106 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
6107 else
6108 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
6110 else
6112 tmp2 = gen_reg_rtx (Pmode);
6113 if (TARGET_64BIT)
6114 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
6115 else
6116 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
6117 emit_insn (insn);
6118 insn = gen_rtx_SET (Pmode, dest,
6119 gen_rtx_PLUS (Pmode, tmp2, tmp1));
6121 emit_insn (insn);
6123 else
6125 /* IE, or 64-bit offset LE. */
6126 tmp2 = gen_reg_rtx (Pmode);
6127 if (TARGET_64BIT)
6128 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
6129 else
6130 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
6131 emit_insn (insn);
6132 if (TARGET_64BIT)
6133 insn = gen_tls_tls_64 (dest, tmp2, addr);
6134 else
6135 insn = gen_tls_tls_32 (dest, tmp2, addr);
6136 emit_insn (insn);
6140 return dest;
6143 /* Return 1 if X contains a thread-local symbol. */
6145 static bool
6146 rs6000_tls_referenced_p (rtx x)
6148 if (! TARGET_HAVE_TLS)
6149 return false;
6151 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
6154 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6156 static bool
6157 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6159 if (GET_CODE (x) == HIGH
6160 && GET_CODE (XEXP (x, 0)) == UNSPEC)
6161 return true;
6163 /* A TLS symbol in the TOC cannot contain a sum. */
6164 if (GET_CODE (x) == CONST
6165 && GET_CODE (XEXP (x, 0)) == PLUS
6166 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6167 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
6168 return true;
6170 /* Do not place an ELF TLS symbol in the constant pool. */
6171 return TARGET_ELF && rs6000_tls_referenced_p (x);
6174 /* Return 1 if *X is a thread-local symbol. This is the same as
6175 rs6000_tls_symbol_ref except for the type of the unused argument. */
6177 static int
6178 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6180 return RS6000_SYMBOL_REF_TLS_P (*x);
6183 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
6184 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
6185 can be addressed relative to the toc pointer. */
6187 static bool
6188 use_toc_relative_ref (rtx sym)
6190 return ((constant_pool_expr_p (sym)
6191 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
6192 get_pool_mode (sym)))
6193 || (TARGET_CMODEL == CMODEL_MEDIUM
6194 && !CONSTANT_POOL_ADDRESS_P (sym)
6195 && SYMBOL_REF_LOCAL_P (sym)));
6198 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6199 replace the input X, or the original X if no replacement is called for.
6200 The output parameter *WIN is 1 if the calling macro should goto WIN,
6201 0 if it should not.
6203 For RS/6000, we wish to handle large displacements off a base
6204 register by splitting the addend across an addiu/addis and the mem insn.
6205 This cuts number of extra insns needed from 3 to 1.
6207 On Darwin, we use this to generate code for floating point constants.
6208 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6209 The Darwin code is inside #if TARGET_MACHO because only then are the
6210 machopic_* functions defined. */
6211 static rtx
6212 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
6213 int opnum, int type,
6214 int ind_levels ATTRIBUTE_UNUSED, int *win)
6216 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6218 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6219 DFmode/DImode MEM. */
6220 if (reg_offset_p
6221 && opnum == 1
6222 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
6223 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
6224 reg_offset_p = false;
6226 /* We must recognize output that we have already generated ourselves. */
6227 if (GET_CODE (x) == PLUS
6228 && GET_CODE (XEXP (x, 0)) == PLUS
6229 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6230 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6231 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6233 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6234 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6235 opnum, (enum reload_type) type);
6236 *win = 1;
6237 return x;
6240 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6241 if (GET_CODE (x) == LO_SUM
6242 && GET_CODE (XEXP (x, 0)) == HIGH)
6244 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6245 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6246 opnum, (enum reload_type) type);
6247 *win = 1;
6248 return x;
6251 #if TARGET_MACHO
6252 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
6253 && GET_CODE (x) == LO_SUM
6254 && GET_CODE (XEXP (x, 0)) == PLUS
6255 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6256 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6257 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6258 && machopic_operand_p (XEXP (x, 1)))
6260 /* Result of previous invocation of this function on Darwin
6261 floating point constant. */
6262 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6263 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6264 opnum, (enum reload_type) type);
6265 *win = 1;
6266 return x;
6268 #endif
6270 if (TARGET_CMODEL != CMODEL_SMALL
6271 && reg_offset_p
6272 && small_toc_ref (x, VOIDmode))
6274 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
6275 x = gen_rtx_LO_SUM (Pmode, hi, x);
6276 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6277 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6278 opnum, (enum reload_type) type);
6279 *win = 1;
6280 return x;
6283 if (GET_CODE (x) == PLUS
6284 && GET_CODE (XEXP (x, 0)) == REG
6285 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6286 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6287 && GET_CODE (XEXP (x, 1)) == CONST_INT
6288 && reg_offset_p
6289 && !SPE_VECTOR_MODE (mode)
6290 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6291 || mode == DDmode || mode == TDmode
6292 || mode == DImode))
6293 && VECTOR_MEM_NONE_P (mode))
6295 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6296 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6297 HOST_WIDE_INT high
6298 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6300 /* Check for 32-bit overflow. */
6301 if (high + low != val)
6303 *win = 0;
6304 return x;
6307 /* Reload the high part into a base reg; leave the low part
6308 in the mem directly. */
6310 x = gen_rtx_PLUS (GET_MODE (x),
6311 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6312 GEN_INT (high)),
6313 GEN_INT (low));
6315 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6316 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6317 opnum, (enum reload_type) type);
6318 *win = 1;
6319 return x;
6322 if (GET_CODE (x) == SYMBOL_REF
6323 && reg_offset_p
6324 && VECTOR_MEM_NONE_P (mode)
6325 && !SPE_VECTOR_MODE (mode)
6326 #if TARGET_MACHO
6327 && DEFAULT_ABI == ABI_DARWIN
6328 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6329 && machopic_symbol_defined_p (x)
6330 #else
6331 && DEFAULT_ABI == ABI_V4
6332 && !flag_pic
6333 #endif
6334 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6335 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6336 without fprs.
6337 ??? Assume floating point reg based on mode? This assumption is
6338 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
6339 where reload ends up doing a DFmode load of a constant from
6340 mem using two gprs. Unfortunately, at this point reload
6341 hasn't yet selected regs so poking around in reload data
6342 won't help and even if we could figure out the regs reliably,
6343 we'd still want to allow this transformation when the mem is
6344 naturally aligned. Since we say the address is good here, we
6345 can't disable offsets from LO_SUMs in mem_operand_gpr.
6346 FIXME: Allow offset from lo_sum for other modes too, when
6347 mem is sufficiently aligned. */
6348 && mode != TFmode
6349 && mode != TDmode
6350 && (mode != DImode || TARGET_POWERPC64)
6351 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6352 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6354 #if TARGET_MACHO
6355 if (flag_pic)
6357 rtx offset = machopic_gen_offset (x);
6358 x = gen_rtx_LO_SUM (GET_MODE (x),
6359 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6360 gen_rtx_HIGH (Pmode, offset)), offset);
6362 else
6363 #endif
6364 x = gen_rtx_LO_SUM (GET_MODE (x),
6365 gen_rtx_HIGH (Pmode, x), x);
6367 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6368 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6369 opnum, (enum reload_type) type);
6370 *win = 1;
6371 return x;
6374 /* Reload an offset address wrapped by an AND that represents the
6375 masking of the lower bits. Strip the outer AND and let reload
6376 convert the offset address into an indirect address. For VSX,
6377 force reload to create the address with an AND in a separate
6378 register, because we can't guarantee an altivec register will
6379 be used. */
6380 if (VECTOR_MEM_ALTIVEC_P (mode)
6381 && GET_CODE (x) == AND
6382 && GET_CODE (XEXP (x, 0)) == PLUS
6383 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6384 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6385 && GET_CODE (XEXP (x, 1)) == CONST_INT
6386 && INTVAL (XEXP (x, 1)) == -16)
6388 x = XEXP (x, 0);
6389 *win = 1;
6390 return x;
6393 if (TARGET_TOC
6394 && reg_offset_p
6395 && GET_CODE (x) == SYMBOL_REF
6396 && use_toc_relative_ref (x))
6398 x = create_TOC_reference (x, NULL_RTX);
6399 if (TARGET_CMODEL != CMODEL_SMALL)
6400 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6401 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6402 opnum, (enum reload_type) type);
6403 *win = 1;
6404 return x;
6406 *win = 0;
6407 return x;
6410 /* Debug version of rs6000_legitimize_reload_address. */
6411 static rtx
6412 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6413 int opnum, int type,
6414 int ind_levels, int *win)
6416 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6417 ind_levels, win);
6418 fprintf (stderr,
6419 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6420 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6421 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6422 debug_rtx (x);
6424 if (x == ret)
6425 fprintf (stderr, "Same address returned\n");
6426 else if (!ret)
6427 fprintf (stderr, "NULL returned\n");
6428 else
6430 fprintf (stderr, "New address:\n");
6431 debug_rtx (ret);
6434 return ret;
6437 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6438 that is a valid memory address for an instruction.
6439 The MODE argument is the machine mode for the MEM expression
6440 that wants to use this address.
6442 On the RS/6000, there are four valid address: a SYMBOL_REF that
6443 refers to a constant pool entry of an address (or the sum of it
6444 plus a constant), a short (16-bit signed) constant plus a register,
6445 the sum of two registers, or a register indirect, possibly with an
6446 auto-increment. For DFmode, DDmode and DImode with a constant plus
6447 register, we must ensure that both words are addressable or PowerPC64
6448 with offset word aligned.
6450 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6451 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6452 because adjacent memory cells are accessed by adding word-sized offsets
6453 during assembly output. */
6454 static bool
6455 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6457 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6459 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6460 if (VECTOR_MEM_ALTIVEC_P (mode)
6461 && GET_CODE (x) == AND
6462 && GET_CODE (XEXP (x, 1)) == CONST_INT
6463 && INTVAL (XEXP (x, 1)) == -16)
6464 x = XEXP (x, 0);
6466 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
6467 return 0;
6468 if (legitimate_indirect_address_p (x, reg_ok_strict))
6469 return 1;
6470 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6471 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6472 && !SPE_VECTOR_MODE (mode)
6473 && mode != TFmode
6474 && mode != TDmode
6475 /* Restrict addressing for DI because of our SUBREG hackery. */
6476 && !(TARGET_E500_DOUBLE
6477 && (mode == DFmode || mode == DDmode || mode == DImode))
6478 && TARGET_UPDATE
6479 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6480 return 1;
6481 if (virtual_stack_registers_memory_p (x))
6482 return 1;
6483 if (reg_offset_p && legitimate_small_data_p (mode, x))
6484 return 1;
6485 if (reg_offset_p
6486 && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6487 return 1;
6488 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6489 if (! reg_ok_strict
6490 && reg_offset_p
6491 && GET_CODE (x) == PLUS
6492 && GET_CODE (XEXP (x, 0)) == REG
6493 && (XEXP (x, 0) == virtual_stack_vars_rtx
6494 || XEXP (x, 0) == arg_pointer_rtx)
6495 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6496 return 1;
6497 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
6498 return 1;
6499 if (mode != TImode
6500 && mode != TFmode
6501 && mode != TDmode
6502 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6503 || TARGET_POWERPC64
6504 || (mode != DFmode && mode != DDmode)
6505 || (TARGET_E500_DOUBLE && mode != DDmode))
6506 && (TARGET_POWERPC64 || mode != DImode)
6507 && !avoiding_indexed_address_p (mode)
6508 && legitimate_indexed_address_p (x, reg_ok_strict))
6509 return 1;
6510 if (GET_CODE (x) == PRE_MODIFY
6511 && mode != TImode
6512 && mode != TFmode
6513 && mode != TDmode
6514 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6515 || TARGET_POWERPC64
6516 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6517 && (TARGET_POWERPC64 || mode != DImode)
6518 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6519 && !SPE_VECTOR_MODE (mode)
6520 /* Restrict addressing for DI because of our SUBREG hackery. */
6521 && !(TARGET_E500_DOUBLE
6522 && (mode == DFmode || mode == DDmode || mode == DImode))
6523 && TARGET_UPDATE
6524 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6525 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
6526 reg_ok_strict, false)
6527 || (!avoiding_indexed_address_p (mode)
6528 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6529 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6530 return 1;
6531 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6532 return 1;
6533 return 0;
6536 /* Debug version of rs6000_legitimate_address_p. */
6537 static bool
6538 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6539 bool reg_ok_strict)
6541 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6542 fprintf (stderr,
6543 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6544 "strict = %d, code = %s\n",
6545 ret ? "true" : "false",
6546 GET_MODE_NAME (mode),
6547 reg_ok_strict,
6548 GET_RTX_NAME (GET_CODE (x)));
6549 debug_rtx (x);
6551 return ret;
6554 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6556 static bool
6557 rs6000_mode_dependent_address_p (const_rtx addr,
6558 addr_space_t as ATTRIBUTE_UNUSED)
6560 return rs6000_mode_dependent_address_ptr (addr);
6563 /* Go to LABEL if ADDR (a legitimate address expression)
6564 has an effect that depends on the machine mode it is used for.
6566 On the RS/6000 this is true of all integral offsets (since AltiVec
6567 and VSX modes don't allow them) or is a pre-increment or decrement.
6569 ??? Except that due to conceptual problems in offsettable_address_p
6570 we can't really report the problems of integral offsets. So leave
6571 this assuming that the adjustable offset must be valid for the
6572 sub-words of a TFmode operand, which is what we had before. */
6574 static bool
6575 rs6000_mode_dependent_address (const_rtx addr)
6577 switch (GET_CODE (addr))
6579 case PLUS:
6580 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6581 is considered a legitimate address before reload, so there
6582 are no offset restrictions in that case. Note that this
6583 condition is safe in strict mode because any address involving
6584 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6585 been rejected as illegitimate. */
6586 if (XEXP (addr, 0) != virtual_stack_vars_rtx
6587 && XEXP (addr, 0) != arg_pointer_rtx
6588 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6590 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6591 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
6593 break;
6595 case LO_SUM:
6596 /* Anything in the constant pool is sufficiently aligned that
6597 all bytes have the same high part address. */
6598 return !legitimate_constant_pool_address_p (addr, QImode, false);
6600 /* Auto-increment cases are now treated generically in recog.c. */
6601 case PRE_MODIFY:
6602 return TARGET_UPDATE;
6604 /* AND is only allowed in Altivec loads. */
6605 case AND:
6606 return true;
6608 default:
6609 break;
6612 return false;
6615 /* Debug version of rs6000_mode_dependent_address. */
6616 static bool
6617 rs6000_debug_mode_dependent_address (const_rtx addr)
6619 bool ret = rs6000_mode_dependent_address (addr);
6621 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6622 ret ? "true" : "false");
6623 debug_rtx (addr);
6625 return ret;
6628 /* Implement FIND_BASE_TERM. */
6631 rs6000_find_base_term (rtx op)
6633 rtx base;
6635 base = op;
6636 if (GET_CODE (base) == CONST)
6637 base = XEXP (base, 0);
6638 if (GET_CODE (base) == PLUS)
6639 base = XEXP (base, 0);
6640 if (GET_CODE (base) == UNSPEC)
6641 switch (XINT (base, 1))
6643 case UNSPEC_TOCREL:
6644 case UNSPEC_MACHOPIC_OFFSET:
6645 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6646 for aliasing purposes. */
6647 return XVECEXP (base, 0, 0);
6650 return op;
6653 /* More elaborate version of recog's offsettable_memref_p predicate
6654 that works around the ??? note of rs6000_mode_dependent_address.
6655 In particular it accepts
6657 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6659 in 32-bit mode, that the recog predicate rejects. */
6661 static bool
6662 rs6000_offsettable_memref_p (rtx op, enum machine_mode reg_mode)
6664 bool worst_case;
6666 if (!MEM_P (op))
6667 return false;
6669 /* First mimic offsettable_memref_p. */
6670 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
6671 return true;
6673 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6674 the latter predicate knows nothing about the mode of the memory
6675 reference and, therefore, assumes that it is the largest supported
6676 mode (TFmode). As a consequence, legitimate offsettable memory
6677 references are rejected. rs6000_legitimate_offset_address_p contains
6678 the correct logic for the PLUS case of rs6000_mode_dependent_address,
6679 at least with a little bit of help here given that we know the
6680 actual registers used. */
6681 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
6682 || GET_MODE_SIZE (reg_mode) == 4);
6683 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
6684 true, worst_case);
6687 /* Change register usage conditional on target flags. */
6688 static void
6689 rs6000_conditional_register_usage (void)
6691 int i;
6693 if (TARGET_DEBUG_TARGET)
6694 fprintf (stderr, "rs6000_conditional_register_usage called\n");
6696 /* Set MQ register fixed (already call_used) so that it will not be
6697 allocated. */
6698 fixed_regs[64] = 1;
6700 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6701 if (TARGET_64BIT)
6702 fixed_regs[13] = call_used_regs[13]
6703 = call_really_used_regs[13] = 1;
6705 /* Conditionally disable FPRs. */
6706 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6707 for (i = 32; i < 64; i++)
6708 fixed_regs[i] = call_used_regs[i]
6709 = call_really_used_regs[i] = 1;
6711 /* The TOC register is not killed across calls in a way that is
6712 visible to the compiler. */
6713 if (DEFAULT_ABI == ABI_AIX)
6714 call_really_used_regs[2] = 0;
6716 if (DEFAULT_ABI == ABI_V4
6717 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6718 && flag_pic == 2)
6719 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6721 if (DEFAULT_ABI == ABI_V4
6722 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6723 && flag_pic == 1)
6724 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6725 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6726 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6728 if (DEFAULT_ABI == ABI_DARWIN
6729 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6730 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6731 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6732 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6734 if (TARGET_TOC && TARGET_MINIMAL_TOC)
6735 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6736 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6738 if (TARGET_SPE)
6740 global_regs[SPEFSCR_REGNO] = 1;
6741 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6742 registers in prologues and epilogues. We no longer use r14
6743 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6744 pool for link-compatibility with older versions of GCC. Once
6745 "old" code has died out, we can return r14 to the allocation
6746 pool. */
6747 fixed_regs[14]
6748 = call_used_regs[14]
6749 = call_really_used_regs[14] = 1;
6752 if (!TARGET_ALTIVEC && !TARGET_VSX)
6754 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6755 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6756 call_really_used_regs[VRSAVE_REGNO] = 1;
6759 if (TARGET_ALTIVEC || TARGET_VSX)
6760 global_regs[VSCR_REGNO] = 1;
6762 if (TARGET_ALTIVEC_ABI)
6764 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6765 call_used_regs[i] = call_really_used_regs[i] = 1;
6767 /* AIX reserves VR20:31 in non-extended ABI mode. */
6768 if (TARGET_XCOFF)
6769 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6770 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6774 /* Try to output insns to set TARGET equal to the constant C if it can
6775 be done in less than N insns. Do all computations in MODE.
6776 Returns the place where the output has been placed if it can be
6777 done and the insns have been emitted. If it would take more than N
6778 insns, zero is returned and no insns and emitted. */
6781 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6782 rtx source, int n ATTRIBUTE_UNUSED)
6784 rtx result, insn, set;
6785 HOST_WIDE_INT c0, c1;
6787 switch (mode)
6789 case QImode:
6790 case HImode:
6791 if (dest == NULL)
6792 dest = gen_reg_rtx (mode);
6793 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6794 return dest;
6796 case SImode:
6797 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6799 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6800 GEN_INT (INTVAL (source)
6801 & (~ (HOST_WIDE_INT) 0xffff))));
6802 emit_insn (gen_rtx_SET (VOIDmode, dest,
6803 gen_rtx_IOR (SImode, copy_rtx (result),
6804 GEN_INT (INTVAL (source) & 0xffff))));
6805 result = dest;
6806 break;
6808 case DImode:
6809 switch (GET_CODE (source))
6811 case CONST_INT:
6812 c0 = INTVAL (source);
6813 c1 = -(c0 < 0);
6814 break;
6816 case CONST_DOUBLE:
6817 #if HOST_BITS_PER_WIDE_INT >= 64
6818 c0 = CONST_DOUBLE_LOW (source);
6819 c1 = -(c0 < 0);
6820 #else
6821 c0 = CONST_DOUBLE_LOW (source);
6822 c1 = CONST_DOUBLE_HIGH (source);
6823 #endif
6824 break;
6826 default:
6827 gcc_unreachable ();
6830 result = rs6000_emit_set_long_const (dest, c0, c1);
6831 break;
6833 default:
6834 gcc_unreachable ();
6837 insn = get_last_insn ();
6838 set = single_set (insn);
6839 if (! CONSTANT_P (SET_SRC (set)))
6840 set_unique_reg_note (insn, REG_EQUAL, source);
6842 return result;
6845 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6846 fall back to a straight forward decomposition. We do this to avoid
6847 exponential run times encountered when looking for longer sequences
6848 with rs6000_emit_set_const. */
6849 static rtx
6850 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6852 if (!TARGET_POWERPC64)
6854 rtx operand1, operand2;
6856 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6857 DImode);
6858 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6859 DImode);
6860 emit_move_insn (operand1, GEN_INT (c1));
6861 emit_move_insn (operand2, GEN_INT (c2));
6863 else
6865 HOST_WIDE_INT ud1, ud2, ud3, ud4;
6867 ud1 = c1 & 0xffff;
6868 ud2 = (c1 & 0xffff0000) >> 16;
6869 #if HOST_BITS_PER_WIDE_INT >= 64
6870 c2 = c1 >> 32;
6871 #endif
6872 ud3 = c2 & 0xffff;
6873 ud4 = (c2 & 0xffff0000) >> 16;
6875 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6876 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6878 if (ud1 & 0x8000)
6879 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
6880 else
6881 emit_move_insn (dest, GEN_INT (ud1));
6884 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6885 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6887 if (ud2 & 0x8000)
6888 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6889 - 0x80000000));
6890 else
6891 emit_move_insn (dest, GEN_INT (ud2 << 16));
6892 if (ud1 != 0)
6893 emit_move_insn (copy_rtx (dest),
6894 gen_rtx_IOR (DImode, copy_rtx (dest),
6895 GEN_INT (ud1)));
6897 else if (ud3 == 0 && ud4 == 0)
6899 gcc_assert (ud2 & 0x8000);
6900 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6901 - 0x80000000));
6902 if (ud1 != 0)
6903 emit_move_insn (copy_rtx (dest),
6904 gen_rtx_IOR (DImode, copy_rtx (dest),
6905 GEN_INT (ud1)));
6906 emit_move_insn (copy_rtx (dest),
6907 gen_rtx_ZERO_EXTEND (DImode,
6908 gen_lowpart (SImode,
6909 copy_rtx (dest))));
6911 else if ((ud4 == 0xffff && (ud3 & 0x8000))
6912 || (ud4 == 0 && ! (ud3 & 0x8000)))
6914 if (ud3 & 0x8000)
6915 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6916 - 0x80000000));
6917 else
6918 emit_move_insn (dest, GEN_INT (ud3 << 16));
6920 if (ud2 != 0)
6921 emit_move_insn (copy_rtx (dest),
6922 gen_rtx_IOR (DImode, copy_rtx (dest),
6923 GEN_INT (ud2)));
6924 emit_move_insn (copy_rtx (dest),
6925 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6926 GEN_INT (16)));
6927 if (ud1 != 0)
6928 emit_move_insn (copy_rtx (dest),
6929 gen_rtx_IOR (DImode, copy_rtx (dest),
6930 GEN_INT (ud1)));
6932 else
6934 if (ud4 & 0x8000)
6935 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6936 - 0x80000000));
6937 else
6938 emit_move_insn (dest, GEN_INT (ud4 << 16));
6940 if (ud3 != 0)
6941 emit_move_insn (copy_rtx (dest),
6942 gen_rtx_IOR (DImode, copy_rtx (dest),
6943 GEN_INT (ud3)));
6945 emit_move_insn (copy_rtx (dest),
6946 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6947 GEN_INT (32)));
6948 if (ud2 != 0)
6949 emit_move_insn (copy_rtx (dest),
6950 gen_rtx_IOR (DImode, copy_rtx (dest),
6951 GEN_INT (ud2 << 16)));
6952 if (ud1 != 0)
6953 emit_move_insn (copy_rtx (dest),
6954 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
6957 return dest;
6960 /* Helper for the following. Get rid of [r+r] memory refs
6961 in cases where it won't work (TImode, TFmode, TDmode). */
6963 static void
6964 rs6000_eliminate_indexed_memrefs (rtx operands[2])
6966 if (reload_in_progress)
6967 return;
6969 if (GET_CODE (operands[0]) == MEM
6970 && GET_CODE (XEXP (operands[0], 0)) != REG
6971 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
6972 GET_MODE (operands[0]), false))
6973 operands[0]
6974 = replace_equiv_address (operands[0],
6975 copy_addr_to_reg (XEXP (operands[0], 0)));
6977 if (GET_CODE (operands[1]) == MEM
6978 && GET_CODE (XEXP (operands[1], 0)) != REG
6979 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
6980 GET_MODE (operands[1]), false))
6981 operands[1]
6982 = replace_equiv_address (operands[1],
6983 copy_addr_to_reg (XEXP (operands[1], 0)));
6986 /* Emit a move from SOURCE to DEST in mode MODE. */
6987 void
6988 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
6990 rtx operands[2];
6991 operands[0] = dest;
6992 operands[1] = source;
6994 if (TARGET_DEBUG_ADDR)
6996 fprintf (stderr,
6997 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6998 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6999 GET_MODE_NAME (mode),
7000 reload_in_progress,
7001 reload_completed,
7002 can_create_pseudo_p ());
7003 debug_rtx (dest);
7004 fprintf (stderr, "source:\n");
7005 debug_rtx (source);
7008 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
7009 if (GET_CODE (operands[1]) == CONST_DOUBLE
7010 && ! FLOAT_MODE_P (mode)
7011 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7013 /* FIXME. This should never happen. */
7014 /* Since it seems that it does, do the safe thing and convert
7015 to a CONST_INT. */
7016 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
7018 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
7019 || FLOAT_MODE_P (mode)
7020 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
7021 || CONST_DOUBLE_LOW (operands[1]) < 0)
7022 && (CONST_DOUBLE_HIGH (operands[1]) != -1
7023 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
7025 /* Check if GCC is setting up a block move that will end up using FP
7026 registers as temporaries. We must make sure this is acceptable. */
7027 if (GET_CODE (operands[0]) == MEM
7028 && GET_CODE (operands[1]) == MEM
7029 && mode == DImode
7030 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
7031 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
7032 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
7033 ? 32 : MEM_ALIGN (operands[0])))
7034 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
7035 ? 32
7036 : MEM_ALIGN (operands[1]))))
7037 && ! MEM_VOLATILE_P (operands [0])
7038 && ! MEM_VOLATILE_P (operands [1]))
7040 emit_move_insn (adjust_address (operands[0], SImode, 0),
7041 adjust_address (operands[1], SImode, 0));
7042 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
7043 adjust_address (copy_rtx (operands[1]), SImode, 4));
7044 return;
7047 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
7048 && !gpc_reg_operand (operands[1], mode))
7049 operands[1] = force_reg (mode, operands[1]);
7051 /* Recognize the case where operand[1] is a reference to thread-local
7052 data and load its address to a register. */
7053 if (rs6000_tls_referenced_p (operands[1]))
7055 enum tls_model model;
7056 rtx tmp = operands[1];
7057 rtx addend = NULL;
7059 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
7061 addend = XEXP (XEXP (tmp, 0), 1);
7062 tmp = XEXP (XEXP (tmp, 0), 0);
7065 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
7066 model = SYMBOL_REF_TLS_MODEL (tmp);
7067 gcc_assert (model != 0);
7069 tmp = rs6000_legitimize_tls_address (tmp, model);
7070 if (addend)
7072 tmp = gen_rtx_PLUS (mode, tmp, addend);
7073 tmp = force_operand (tmp, operands[0]);
7075 operands[1] = tmp;
7078 /* Handle the case where reload calls us with an invalid address. */
7079 if (reload_in_progress && mode == Pmode
7080 && (! general_operand (operands[1], mode)
7081 || ! nonimmediate_operand (operands[0], mode)))
7082 goto emit_set;
7084 /* 128-bit constant floating-point values on Darwin should really be
7085 loaded as two parts. */
7086 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
7087 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
7089 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
7090 simplify_gen_subreg (DFmode, operands[1], mode, 0),
7091 DFmode);
7092 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
7093 GET_MODE_SIZE (DFmode)),
7094 simplify_gen_subreg (DFmode, operands[1], mode,
7095 GET_MODE_SIZE (DFmode)),
7096 DFmode);
7097 return;
7100 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
7101 cfun->machine->sdmode_stack_slot =
7102 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
7104 if (reload_in_progress
7105 && mode == SDmode
7106 && MEM_P (operands[0])
7107 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
7108 && REG_P (operands[1]))
7110 if (FP_REGNO_P (REGNO (operands[1])))
7112 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
7113 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7114 emit_insn (gen_movsd_store (mem, operands[1]));
7116 else if (INT_REGNO_P (REGNO (operands[1])))
7118 rtx mem = adjust_address_nv (operands[0], mode, 4);
7119 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7120 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
7122 else
7123 gcc_unreachable();
7124 return;
7126 if (reload_in_progress
7127 && mode == SDmode
7128 && REG_P (operands[0])
7129 && MEM_P (operands[1])
7130 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
7132 if (FP_REGNO_P (REGNO (operands[0])))
7134 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
7135 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7136 emit_insn (gen_movsd_load (operands[0], mem));
7138 else if (INT_REGNO_P (REGNO (operands[0])))
7140 rtx mem = adjust_address_nv (operands[1], mode, 4);
7141 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7142 emit_insn (gen_movsd_hardfloat (operands[0], mem));
7144 else
7145 gcc_unreachable();
7146 return;
7149 /* FIXME: In the long term, this switch statement should go away
7150 and be replaced by a sequence of tests based on things like
7151 mode == Pmode. */
7152 switch (mode)
7154 case HImode:
7155 case QImode:
7156 if (CONSTANT_P (operands[1])
7157 && GET_CODE (operands[1]) != CONST_INT)
7158 operands[1] = force_const_mem (mode, operands[1]);
7159 break;
7161 case TFmode:
7162 case TDmode:
7163 rs6000_eliminate_indexed_memrefs (operands);
7164 /* fall through */
7166 case DFmode:
7167 case DDmode:
7168 case SFmode:
7169 case SDmode:
7170 if (CONSTANT_P (operands[1])
7171 && ! easy_fp_constant (operands[1], mode))
7172 operands[1] = force_const_mem (mode, operands[1]);
7173 break;
7175 case V16QImode:
7176 case V8HImode:
7177 case V4SFmode:
7178 case V4SImode:
7179 case V4HImode:
7180 case V2SFmode:
7181 case V2SImode:
7182 case V1DImode:
7183 case V2DFmode:
7184 case V2DImode:
7185 if (CONSTANT_P (operands[1])
7186 && !easy_vector_constant (operands[1], mode))
7187 operands[1] = force_const_mem (mode, operands[1]);
7188 break;
7190 case SImode:
7191 case DImode:
7192 /* Use default pattern for address of ELF small data */
7193 if (TARGET_ELF
7194 && mode == Pmode
7195 && DEFAULT_ABI == ABI_V4
7196 && (GET_CODE (operands[1]) == SYMBOL_REF
7197 || GET_CODE (operands[1]) == CONST)
7198 && small_data_operand (operands[1], mode))
7200 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7201 return;
7204 if (DEFAULT_ABI == ABI_V4
7205 && mode == Pmode && mode == SImode
7206 && flag_pic == 1 && got_operand (operands[1], mode))
7208 emit_insn (gen_movsi_got (operands[0], operands[1]));
7209 return;
7212 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
7213 && TARGET_NO_TOC
7214 && ! flag_pic
7215 && mode == Pmode
7216 && CONSTANT_P (operands[1])
7217 && GET_CODE (operands[1]) != HIGH
7218 && GET_CODE (operands[1]) != CONST_INT)
7220 rtx target = (!can_create_pseudo_p ()
7221 ? operands[0]
7222 : gen_reg_rtx (mode));
7224 /* If this is a function address on -mcall-aixdesc,
7225 convert it to the address of the descriptor. */
7226 if (DEFAULT_ABI == ABI_AIX
7227 && GET_CODE (operands[1]) == SYMBOL_REF
7228 && XSTR (operands[1], 0)[0] == '.')
7230 const char *name = XSTR (operands[1], 0);
7231 rtx new_ref;
7232 while (*name == '.')
7233 name++;
7234 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7235 CONSTANT_POOL_ADDRESS_P (new_ref)
7236 = CONSTANT_POOL_ADDRESS_P (operands[1]);
7237 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7238 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7239 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7240 operands[1] = new_ref;
7243 if (DEFAULT_ABI == ABI_DARWIN)
7245 #if TARGET_MACHO
7246 if (MACHO_DYNAMIC_NO_PIC_P)
7248 /* Take care of any required data indirection. */
7249 operands[1] = rs6000_machopic_legitimize_pic_address (
7250 operands[1], mode, operands[0]);
7251 if (operands[0] != operands[1])
7252 emit_insn (gen_rtx_SET (VOIDmode,
7253 operands[0], operands[1]));
7254 return;
7256 #endif
7257 emit_insn (gen_macho_high (target, operands[1]));
7258 emit_insn (gen_macho_low (operands[0], target, operands[1]));
7259 return;
7262 emit_insn (gen_elf_high (target, operands[1]));
7263 emit_insn (gen_elf_low (operands[0], target, operands[1]));
7264 return;
7267 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7268 and we have put it in the TOC, we just need to make a TOC-relative
7269 reference to it. */
7270 if (TARGET_TOC
7271 && GET_CODE (operands[1]) == SYMBOL_REF
7272 && use_toc_relative_ref (operands[1]))
7273 operands[1] = create_TOC_reference (operands[1], operands[0]);
7274 else if (mode == Pmode
7275 && CONSTANT_P (operands[1])
7276 && GET_CODE (operands[1]) != HIGH
7277 && ((GET_CODE (operands[1]) != CONST_INT
7278 && ! easy_fp_constant (operands[1], mode))
7279 || (GET_CODE (operands[1]) == CONST_INT
7280 && (num_insns_constant (operands[1], mode)
7281 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7282 || (GET_CODE (operands[0]) == REG
7283 && FP_REGNO_P (REGNO (operands[0]))))
7284 && !toc_relative_expr_p (operands[1], false)
7285 && (TARGET_CMODEL == CMODEL_SMALL
7286 || can_create_pseudo_p ()
7287 || (REG_P (operands[0])
7288 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7291 #if TARGET_MACHO
7292 /* Darwin uses a special PIC legitimizer. */
7293 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7295 operands[1] =
7296 rs6000_machopic_legitimize_pic_address (operands[1], mode,
7297 operands[0]);
7298 if (operands[0] != operands[1])
7299 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7300 return;
7302 #endif
7304 /* If we are to limit the number of things we put in the TOC and
7305 this is a symbol plus a constant we can add in one insn,
7306 just put the symbol in the TOC and add the constant. Don't do
7307 this if reload is in progress. */
7308 if (GET_CODE (operands[1]) == CONST
7309 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7310 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7311 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7312 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7313 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7314 && ! side_effects_p (operands[0]))
7316 rtx sym =
7317 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7318 rtx other = XEXP (XEXP (operands[1], 0), 1);
7320 sym = force_reg (mode, sym);
7321 emit_insn (gen_add3_insn (operands[0], sym, other));
7322 return;
7325 operands[1] = force_const_mem (mode, operands[1]);
7327 if (TARGET_TOC
7328 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7329 && constant_pool_expr_p (XEXP (operands[1], 0))
7330 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7331 get_pool_constant (XEXP (operands[1], 0)),
7332 get_pool_mode (XEXP (operands[1], 0))))
7334 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
7335 operands[0]);
7336 operands[1] = gen_const_mem (mode, tocref);
7337 set_mem_alias_set (operands[1], get_TOC_alias_set ());
7340 break;
7342 case TImode:
7343 rs6000_eliminate_indexed_memrefs (operands);
7344 break;
7346 default:
7347 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7350 /* Above, we may have called force_const_mem which may have returned
7351 an invalid address. If we can, fix this up; otherwise, reload will
7352 have to deal with it. */
7353 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7354 operands[1] = validize_mem (operands[1]);
7356 emit_set:
7357 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7360 /* Return true if a structure, union or array containing FIELD should be
7361 accessed using `BLKMODE'.
7363 For the SPE, simd types are V2SI, and gcc can be tempted to put the
7364 entire thing in a DI and use subregs to access the internals.
7365 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
7366 back-end. Because a single GPR can hold a V2SI, but not a DI, the
7367 best thing to do is set structs to BLKmode and avoid Severe Tire
7368 Damage.
7370 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
7371 fit into 1, whereas DI still needs two. */
7373 static bool
7374 rs6000_member_type_forces_blk (const_tree field, enum machine_mode mode)
7376 return ((TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
7377 || (TARGET_E500_DOUBLE && mode == DFmode));
7380 /* Nonzero if we can use a floating-point register to pass this arg. */
7381 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7382 (SCALAR_FLOAT_MODE_P (MODE) \
7383 && (CUM)->fregno <= FP_ARG_MAX_REG \
7384 && TARGET_HARD_FLOAT && TARGET_FPRS)
7386 /* Nonzero if we can use an AltiVec register to pass this arg. */
7387 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7388 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7389 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7390 && TARGET_ALTIVEC_ABI \
7391 && (NAMED))
7393 /* Return a nonzero value to say to return the function value in
7394 memory, just as large structures are always returned. TYPE will be
7395 the data type of the value, and FNTYPE will be the type of the
7396 function doing the returning, or @code{NULL} for libcalls.
7398 The AIX ABI for the RS/6000 specifies that all structures are
7399 returned in memory. The Darwin ABI does the same.
7401 For the Darwin 64 Bit ABI, a function result can be returned in
7402 registers or in memory, depending on the size of the return data
7403 type. If it is returned in registers, the value occupies the same
7404 registers as it would if it were the first and only function
7405 argument. Otherwise, the function places its result in memory at
7406 the location pointed to by GPR3.
7408 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7409 but a draft put them in memory, and GCC used to implement the draft
7410 instead of the final standard. Therefore, aix_struct_return
7411 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7412 compatibility can change DRAFT_V4_STRUCT_RET to override the
7413 default, and -m switches get the final word. See
7414 rs6000_option_override_internal for more details.
7416 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7417 long double support is enabled. These values are returned in memory.
7419 int_size_in_bytes returns -1 for variable size objects, which go in
7420 memory always. The cast to unsigned makes -1 > 8. */
7422 static bool
7423 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7425 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7426 if (TARGET_MACHO
7427 && rs6000_darwin64_abi
7428 && TREE_CODE (type) == RECORD_TYPE
7429 && int_size_in_bytes (type) > 0)
7431 CUMULATIVE_ARGS valcum;
7432 rtx valret;
7434 valcum.words = 0;
7435 valcum.fregno = FP_ARG_MIN_REG;
7436 valcum.vregno = ALTIVEC_ARG_MIN_REG;
7437 /* Do a trial code generation as if this were going to be passed
7438 as an argument; if any part goes in memory, we return NULL. */
7439 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7440 if (valret)
7441 return false;
7442 /* Otherwise fall through to more conventional ABI rules. */
7445 #if HAVE_UPC_PTS_STRUCT_REP
7446 if (POINTER_TYPE_P (type) && upc_shared_type_p (TREE_TYPE (type)))
7447 return true;
7448 #endif
7450 if (AGGREGATE_TYPE_P (type)
7451 && (aix_struct_return
7452 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7453 return true;
7455 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7456 modes only exist for GCC vector types if -maltivec. */
7457 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7458 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7459 return false;
7461 /* Return synthetic vectors in memory. */
7462 if (TREE_CODE (type) == VECTOR_TYPE
7463 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7465 static bool warned_for_return_big_vectors = false;
7466 if (!warned_for_return_big_vectors)
7468 warning (0, "GCC vector returned by reference: "
7469 "non-standard ABI extension with no compatibility guarantee");
7470 warned_for_return_big_vectors = true;
7472 return true;
7475 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7476 return true;
7478 return false;
7481 #ifdef HAVE_AS_GNU_ATTRIBUTE
7482 /* Return TRUE if a call to function FNDECL may be one that
7483 potentially affects the function calling ABI of the object file. */
7485 static bool
7486 call_ABI_of_interest (tree fndecl)
7488 if (cgraph_state == CGRAPH_STATE_EXPANSION)
7490 struct cgraph_node *c_node;
7492 /* Libcalls are always interesting. */
7493 if (fndecl == NULL_TREE)
7494 return true;
7496 /* Any call to an external function is interesting. */
7497 if (DECL_EXTERNAL (fndecl))
7498 return true;
7500 /* Interesting functions that we are emitting in this object file. */
7501 c_node = cgraph_get_node (fndecl);
7502 c_node = cgraph_function_or_thunk_node (c_node, NULL);
7503 return !cgraph_only_called_directly_p (c_node);
7505 return false;
7507 #endif
7509 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7510 for a call to a function whose data type is FNTYPE.
7511 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7513 For incoming args we set the number of arguments in the prototype large
7514 so we never return a PARALLEL. */
7516 void
7517 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7518 rtx libname ATTRIBUTE_UNUSED, int incoming,
7519 int libcall, int n_named_args,
7520 tree fndecl ATTRIBUTE_UNUSED,
7521 enum machine_mode return_mode ATTRIBUTE_UNUSED)
7523 static CUMULATIVE_ARGS zero_cumulative;
7525 *cum = zero_cumulative;
7526 cum->words = 0;
7527 cum->fregno = FP_ARG_MIN_REG;
7528 cum->vregno = ALTIVEC_ARG_MIN_REG;
7529 cum->prototype = (fntype && prototype_p (fntype));
7530 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7531 ? CALL_LIBCALL : CALL_NORMAL);
7532 cum->sysv_gregno = GP_ARG_MIN_REG;
7533 cum->stdarg = stdarg_p (fntype);
7535 cum->nargs_prototype = 0;
7536 if (incoming || cum->prototype)
7537 cum->nargs_prototype = n_named_args;
7539 /* Check for a longcall attribute. */
7540 if ((!fntype && rs6000_default_long_calls)
7541 || (fntype
7542 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7543 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7544 cum->call_cookie |= CALL_LONG;
7546 if (TARGET_DEBUG_ARG)
7548 fprintf (stderr, "\ninit_cumulative_args:");
7549 if (fntype)
7551 tree ret_type = TREE_TYPE (fntype);
7552 fprintf (stderr, " ret code = %s,",
7553 tree_code_name[ (int)TREE_CODE (ret_type) ]);
7556 if (cum->call_cookie & CALL_LONG)
7557 fprintf (stderr, " longcall,");
7559 fprintf (stderr, " proto = %d, nargs = %d\n",
7560 cum->prototype, cum->nargs_prototype);
7563 #ifdef HAVE_AS_GNU_ATTRIBUTE
7564 if (DEFAULT_ABI == ABI_V4)
7566 cum->escapes = call_ABI_of_interest (fndecl);
7567 if (cum->escapes)
7569 tree return_type;
7571 if (fntype)
7573 return_type = TREE_TYPE (fntype);
7574 return_mode = TYPE_MODE (return_type);
7576 else
7577 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7579 if (return_type != NULL)
7581 if (TREE_CODE (return_type) == RECORD_TYPE
7582 && TYPE_TRANSPARENT_AGGR (return_type))
7584 return_type = TREE_TYPE (first_field (return_type));
7585 return_mode = TYPE_MODE (return_type);
7587 if (AGGREGATE_TYPE_P (return_type)
7588 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7589 <= 8))
7590 rs6000_returns_struct = true;
7592 if (SCALAR_FLOAT_MODE_P (return_mode))
7593 rs6000_passes_float = true;
7594 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7595 || SPE_VECTOR_MODE (return_mode))
7596 rs6000_passes_vector = true;
7599 #endif
7601 if (fntype
7602 && !TARGET_ALTIVEC
7603 && TARGET_ALTIVEC_ABI
7604 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7606 error ("cannot return value in vector register because"
7607 " altivec instructions are disabled, use -maltivec"
7608 " to enable them");
7612 /* Return true if TYPE must be passed on the stack and not in registers. */
7614 static bool
7615 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7617 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7618 return must_pass_in_stack_var_size (mode, type);
7619 else
7620 return must_pass_in_stack_var_size_or_pad (mode, type);
7623 /* If defined, a C expression which determines whether, and in which
7624 direction, to pad out an argument with extra space. The value
7625 should be of type `enum direction': either `upward' to pad above
7626 the argument, `downward' to pad below, or `none' to inhibit
7627 padding.
7629 For the AIX ABI structs are always stored left shifted in their
7630 argument slot. */
7632 enum direction
7633 function_arg_padding (enum machine_mode mode, const_tree type)
7635 #ifndef AGGREGATE_PADDING_FIXED
7636 #define AGGREGATE_PADDING_FIXED 0
7637 #endif
7638 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7639 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7640 #endif
7642 if (!AGGREGATE_PADDING_FIXED)
7644 /* GCC used to pass structures of the same size as integer types as
7645 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7646 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7647 passed padded downward, except that -mstrict-align further
7648 muddied the water in that multi-component structures of 2 and 4
7649 bytes in size were passed padded upward.
7651 The following arranges for best compatibility with previous
7652 versions of gcc, but removes the -mstrict-align dependency. */
7653 if (BYTES_BIG_ENDIAN)
7655 HOST_WIDE_INT size = 0;
7657 if (mode == BLKmode)
7659 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7660 size = int_size_in_bytes (type);
7662 else
7663 size = GET_MODE_SIZE (mode);
7665 if (size == 1 || size == 2 || size == 4)
7666 return downward;
7668 return upward;
7671 if (AGGREGATES_PAD_UPWARD_ALWAYS)
7673 if (type != 0 && AGGREGATE_TYPE_P (type))
7674 return upward;
7677 /* Fall back to the default. */
7678 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7681 /* If defined, a C expression that gives the alignment boundary, in bits,
7682 of an argument with the specified mode and type. If it is not defined,
7683 PARM_BOUNDARY is used for all arguments.
7685 V.4 wants long longs and doubles to be double word aligned. Just
7686 testing the mode size is a boneheaded way to do this as it means
7687 that other types such as complex int are also double word aligned.
7688 However, we're stuck with this because changing the ABI might break
7689 existing library interfaces.
7691 Doubleword align SPE vectors.
7692 Quadword align Altivec/VSX vectors.
7693 Quadword align large synthetic vector types. */
7695 static unsigned int
7696 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7698 if (DEFAULT_ABI == ABI_V4
7699 && (GET_MODE_SIZE (mode) == 8
7700 || (TARGET_HARD_FLOAT
7701 && TARGET_FPRS
7702 && (mode == TFmode || mode == TDmode))))
7703 return 64;
7704 else if (SPE_VECTOR_MODE (mode)
7705 || (type && TREE_CODE (type) == VECTOR_TYPE
7706 && int_size_in_bytes (type) >= 8
7707 && int_size_in_bytes (type) < 16))
7708 return 64;
7709 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7710 || (type && TREE_CODE (type) == VECTOR_TYPE
7711 && int_size_in_bytes (type) >= 16))
7712 return 128;
7713 else if (TARGET_MACHO
7714 && rs6000_darwin64_abi
7715 && mode == BLKmode
7716 && type && TYPE_ALIGN (type) > 64)
7717 return 128;
7718 else
7719 return PARM_BOUNDARY;
7722 /* For a function parm of MODE and TYPE, return the starting word in
7723 the parameter area. NWORDS of the parameter area are already used. */
7725 static unsigned int
7726 rs6000_parm_start (enum machine_mode mode, const_tree type,
7727 unsigned int nwords)
7729 unsigned int align;
7730 unsigned int parm_offset;
7732 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7733 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7734 return nwords + (-(parm_offset + nwords) & align);
7737 /* Compute the size (in words) of a function argument. */
7739 static unsigned long
7740 rs6000_arg_size (enum machine_mode mode, const_tree type)
7742 unsigned long size;
7744 if (mode != BLKmode)
7745 size = GET_MODE_SIZE (mode);
7746 else
7747 size = int_size_in_bytes (type);
7749 if (TARGET_32BIT)
7750 return (size + 3) >> 2;
7751 else
7752 return (size + 7) >> 3;
7755 /* Use this to flush pending int fields. */
7757 static void
7758 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7759 HOST_WIDE_INT bitpos, int final)
7761 unsigned int startbit, endbit;
7762 int intregs, intoffset;
7763 enum machine_mode mode;
7765 /* Handle the situations where a float is taking up the first half
7766 of the GPR, and the other half is empty (typically due to
7767 alignment restrictions). We can detect this by a 8-byte-aligned
7768 int field, or by seeing that this is the final flush for this
7769 argument. Count the word and continue on. */
7770 if (cum->floats_in_gpr == 1
7771 && (cum->intoffset % 64 == 0
7772 || (cum->intoffset == -1 && final)))
7774 cum->words++;
7775 cum->floats_in_gpr = 0;
7778 if (cum->intoffset == -1)
7779 return;
7781 intoffset = cum->intoffset;
7782 cum->intoffset = -1;
7783 cum->floats_in_gpr = 0;
7785 if (intoffset % BITS_PER_WORD != 0)
7787 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7788 MODE_INT, 0);
7789 if (mode == BLKmode)
7791 /* We couldn't find an appropriate mode, which happens,
7792 e.g., in packed structs when there are 3 bytes to load.
7793 Back intoffset back to the beginning of the word in this
7794 case. */
7795 intoffset = intoffset & -BITS_PER_WORD;
7799 startbit = intoffset & -BITS_PER_WORD;
7800 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7801 intregs = (endbit - startbit) / BITS_PER_WORD;
7802 cum->words += intregs;
7803 /* words should be unsigned. */
7804 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7806 int pad = (endbit/BITS_PER_WORD) - cum->words;
7807 cum->words += pad;
7811 /* The darwin64 ABI calls for us to recurse down through structs,
7812 looking for elements passed in registers. Unfortunately, we have
7813 to track int register count here also because of misalignments
7814 in powerpc alignment mode. */
7816 static void
7817 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7818 const_tree type,
7819 HOST_WIDE_INT startbitpos)
7821 tree f;
7823 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7824 if (TREE_CODE (f) == FIELD_DECL)
7826 HOST_WIDE_INT bitpos = startbitpos;
7827 tree ftype = TREE_TYPE (f);
7828 enum machine_mode mode;
7829 if (ftype == error_mark_node)
7830 continue;
7831 mode = TYPE_MODE (ftype);
7833 if (DECL_SIZE (f) != 0
7834 && host_integerp (bit_position (f), 1))
7835 bitpos += int_bit_position (f);
7837 /* ??? FIXME: else assume zero offset. */
7839 if (TREE_CODE (ftype) == RECORD_TYPE)
7840 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7841 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7843 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7844 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7845 cum->fregno += n_fpregs;
7846 /* Single-precision floats present a special problem for
7847 us, because they are smaller than an 8-byte GPR, and so
7848 the structure-packing rules combined with the standard
7849 varargs behavior mean that we want to pack float/float
7850 and float/int combinations into a single register's
7851 space. This is complicated by the arg advance flushing,
7852 which works on arbitrarily large groups of int-type
7853 fields. */
7854 if (mode == SFmode)
7856 if (cum->floats_in_gpr == 1)
7858 /* Two floats in a word; count the word and reset
7859 the float count. */
7860 cum->words++;
7861 cum->floats_in_gpr = 0;
7863 else if (bitpos % 64 == 0)
7865 /* A float at the beginning of an 8-byte word;
7866 count it and put off adjusting cum->words until
7867 we see if a arg advance flush is going to do it
7868 for us. */
7869 cum->floats_in_gpr++;
7871 else
7873 /* The float is at the end of a word, preceded
7874 by integer fields, so the arg advance flush
7875 just above has already set cum->words and
7876 everything is taken care of. */
7879 else
7880 cum->words += n_fpregs;
7882 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7884 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7885 cum->vregno++;
7886 cum->words += 2;
7888 else if (cum->intoffset == -1)
7889 cum->intoffset = bitpos;
7893 /* Check for an item that needs to be considered specially under the darwin 64
7894 bit ABI. These are record types where the mode is BLK or the structure is
7895 8 bytes in size. */
7896 static int
7897 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7899 return rs6000_darwin64_abi
7900 && ((mode == BLKmode
7901 && TREE_CODE (type) == RECORD_TYPE
7902 && int_size_in_bytes (type) > 0)
7903 || (type && TREE_CODE (type) == RECORD_TYPE
7904 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7907 /* Update the data in CUM to advance over an argument
7908 of mode MODE and data type TYPE.
7909 (TYPE is null for libcalls where that information may not be available.)
7911 Note that for args passed by reference, function_arg will be called
7912 with MODE and TYPE set to that of the pointer to the arg, not the arg
7913 itself. */
7915 static void
7916 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7917 const_tree type, bool named, int depth)
7919 /* Only tick off an argument if we're not recursing. */
7920 if (depth == 0)
7921 cum->nargs_prototype--;
7923 #ifdef HAVE_AS_GNU_ATTRIBUTE
7924 if (DEFAULT_ABI == ABI_V4
7925 && cum->escapes)
7927 if (SCALAR_FLOAT_MODE_P (mode))
7928 rs6000_passes_float = true;
7929 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7930 rs6000_passes_vector = true;
7931 else if (SPE_VECTOR_MODE (mode)
7932 && !cum->stdarg
7933 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7934 rs6000_passes_vector = true;
7936 #endif
7938 if (TARGET_ALTIVEC_ABI
7939 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7940 || (type && TREE_CODE (type) == VECTOR_TYPE
7941 && int_size_in_bytes (type) == 16)))
7943 bool stack = false;
7945 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7947 cum->vregno++;
7948 if (!TARGET_ALTIVEC)
7949 error ("cannot pass argument in vector register because"
7950 " altivec instructions are disabled, use -maltivec"
7951 " to enable them");
7953 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7954 even if it is going to be passed in a vector register.
7955 Darwin does the same for variable-argument functions. */
7956 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
7957 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7958 stack = true;
7960 else
7961 stack = true;
7963 if (stack)
7965 int align;
7967 /* Vector parameters must be 16-byte aligned. This places
7968 them at 2 mod 4 in terms of words in 32-bit mode, since
7969 the parameter save area starts at offset 24 from the
7970 stack. In 64-bit mode, they just have to start on an
7971 even word, since the parameter save area is 16-byte
7972 aligned. Space for GPRs is reserved even if the argument
7973 will be passed in memory. */
7974 if (TARGET_32BIT)
7975 align = (2 - cum->words) & 3;
7976 else
7977 align = cum->words & 1;
7978 cum->words += align + rs6000_arg_size (mode, type);
7980 if (TARGET_DEBUG_ARG)
7982 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7983 cum->words, align);
7984 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7985 cum->nargs_prototype, cum->prototype,
7986 GET_MODE_NAME (mode));
7990 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
7991 && !cum->stdarg
7992 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7993 cum->sysv_gregno++;
7995 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7997 int size = int_size_in_bytes (type);
7998 /* Variable sized types have size == -1 and are
7999 treated as if consisting entirely of ints.
8000 Pad to 16 byte boundary if needed. */
8001 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8002 && (cum->words % 2) != 0)
8003 cum->words++;
8004 /* For varargs, we can just go up by the size of the struct. */
8005 if (!named)
8006 cum->words += (size + 7) / 8;
8007 else
8009 /* It is tempting to say int register count just goes up by
8010 sizeof(type)/8, but this is wrong in a case such as
8011 { int; double; int; } [powerpc alignment]. We have to
8012 grovel through the fields for these too. */
8013 cum->intoffset = 0;
8014 cum->floats_in_gpr = 0;
8015 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
8016 rs6000_darwin64_record_arg_advance_flush (cum,
8017 size * BITS_PER_UNIT, 1);
8019 if (TARGET_DEBUG_ARG)
8021 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
8022 cum->words, TYPE_ALIGN (type), size);
8023 fprintf (stderr,
8024 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
8025 cum->nargs_prototype, cum->prototype,
8026 GET_MODE_NAME (mode));
8029 else if (DEFAULT_ABI == ABI_V4)
8031 if (TARGET_HARD_FLOAT && TARGET_FPRS
8032 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8033 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8034 || (mode == TFmode && !TARGET_IEEEQUAD)
8035 || mode == SDmode || mode == DDmode || mode == TDmode))
8037 /* _Decimal128 must use an even/odd register pair. This assumes
8038 that the register number is odd when fregno is odd. */
8039 if (mode == TDmode && (cum->fregno % 2) == 1)
8040 cum->fregno++;
8042 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8043 <= FP_ARG_V4_MAX_REG)
8044 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8045 else
8047 cum->fregno = FP_ARG_V4_MAX_REG + 1;
8048 if (mode == DFmode || mode == TFmode
8049 || mode == DDmode || mode == TDmode)
8050 cum->words += cum->words & 1;
8051 cum->words += rs6000_arg_size (mode, type);
8054 else
8056 int n_words = rs6000_arg_size (mode, type);
8057 int gregno = cum->sysv_gregno;
8059 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8060 (r7,r8) or (r9,r10). As does any other 2 word item such
8061 as complex int due to a historical mistake. */
8062 if (n_words == 2)
8063 gregno += (1 - gregno) & 1;
8065 /* Multi-reg args are not split between registers and stack. */
8066 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8068 /* Long long and SPE vectors are aligned on the stack.
8069 So are other 2 word items such as complex int due to
8070 a historical mistake. */
8071 if (n_words == 2)
8072 cum->words += cum->words & 1;
8073 cum->words += n_words;
8076 /* Note: continuing to accumulate gregno past when we've started
8077 spilling to the stack indicates the fact that we've started
8078 spilling to the stack to expand_builtin_saveregs. */
8079 cum->sysv_gregno = gregno + n_words;
8082 if (TARGET_DEBUG_ARG)
8084 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8085 cum->words, cum->fregno);
8086 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
8087 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
8088 fprintf (stderr, "mode = %4s, named = %d\n",
8089 GET_MODE_NAME (mode), named);
8092 else
8094 int n_words = rs6000_arg_size (mode, type);
8095 int start_words = cum->words;
8096 int align_words = rs6000_parm_start (mode, type, start_words);
8098 cum->words = align_words + n_words;
8100 if (SCALAR_FLOAT_MODE_P (mode)
8101 && TARGET_HARD_FLOAT && TARGET_FPRS)
8103 /* _Decimal128 must be passed in an even/odd float register pair.
8104 This assumes that the register number is odd when fregno is
8105 odd. */
8106 if (mode == TDmode && (cum->fregno % 2) == 1)
8107 cum->fregno++;
8108 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8111 if (TARGET_DEBUG_ARG)
8113 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8114 cum->words, cum->fregno);
8115 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
8116 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
8117 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
8118 named, align_words - start_words, depth);
8123 static void
8124 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
8125 const_tree type, bool named)
8127 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
8131 static rtx
8132 spe_build_register_parallel (enum machine_mode mode, int gregno)
8134 rtx r1, r3, r5, r7;
8136 switch (mode)
8138 case DFmode:
8139 r1 = gen_rtx_REG (DImode, gregno);
8140 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8141 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
8143 case DCmode:
8144 case TFmode:
8145 r1 = gen_rtx_REG (DImode, gregno);
8146 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8147 r3 = gen_rtx_REG (DImode, gregno + 2);
8148 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8149 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
8151 case TCmode:
8152 r1 = gen_rtx_REG (DImode, gregno);
8153 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8154 r3 = gen_rtx_REG (DImode, gregno + 2);
8155 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8156 r5 = gen_rtx_REG (DImode, gregno + 4);
8157 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
8158 r7 = gen_rtx_REG (DImode, gregno + 6);
8159 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
8160 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
8162 default:
8163 gcc_unreachable ();
8167 /* Determine where to put a SIMD argument on the SPE. */
8168 static rtx
8169 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8170 const_tree type)
8172 int gregno = cum->sysv_gregno;
8174 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8175 are passed and returned in a pair of GPRs for ABI compatibility. */
8176 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
8177 || mode == DCmode || mode == TCmode))
8179 int n_words = rs6000_arg_size (mode, type);
8181 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8182 if (mode == DFmode)
8183 gregno += (1 - gregno) & 1;
8185 /* Multi-reg args are not split between registers and stack. */
8186 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8187 return NULL_RTX;
8189 return spe_build_register_parallel (mode, gregno);
8191 if (cum->stdarg)
8193 int n_words = rs6000_arg_size (mode, type);
8195 /* SPE vectors are put in odd registers. */
8196 if (n_words == 2 && (gregno & 1) == 0)
8197 gregno += 1;
8199 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
8201 rtx r1, r2;
8202 enum machine_mode m = SImode;
8204 r1 = gen_rtx_REG (m, gregno);
8205 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
8206 r2 = gen_rtx_REG (m, gregno + 1);
8207 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
8208 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
8210 else
8211 return NULL_RTX;
8213 else
8215 if (gregno <= GP_ARG_MAX_REG)
8216 return gen_rtx_REG (mode, gregno);
8217 else
8218 return NULL_RTX;
8222 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8223 structure between cum->intoffset and bitpos to integer registers. */
8225 static void
8226 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
8227 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
8229 enum machine_mode mode;
8230 unsigned int regno;
8231 unsigned int startbit, endbit;
8232 int this_regno, intregs, intoffset;
8233 rtx reg;
8235 if (cum->intoffset == -1)
8236 return;
8238 intoffset = cum->intoffset;
8239 cum->intoffset = -1;
8241 /* If this is the trailing part of a word, try to only load that
8242 much into the register. Otherwise load the whole register. Note
8243 that in the latter case we may pick up unwanted bits. It's not a
8244 problem at the moment but may wish to revisit. */
8246 if (intoffset % BITS_PER_WORD != 0)
8248 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8249 MODE_INT, 0);
8250 if (mode == BLKmode)
8252 /* We couldn't find an appropriate mode, which happens,
8253 e.g., in packed structs when there are 3 bytes to load.
8254 Back intoffset back to the beginning of the word in this
8255 case. */
8256 intoffset = intoffset & -BITS_PER_WORD;
8257 mode = word_mode;
8260 else
8261 mode = word_mode;
8263 startbit = intoffset & -BITS_PER_WORD;
8264 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8265 intregs = (endbit - startbit) / BITS_PER_WORD;
8266 this_regno = cum->words + intoffset / BITS_PER_WORD;
8268 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8269 cum->use_stack = 1;
8271 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8272 if (intregs <= 0)
8273 return;
8275 intoffset /= BITS_PER_UNIT;
8278 regno = GP_ARG_MIN_REG + this_regno;
8279 reg = gen_rtx_REG (mode, regno);
8280 rvec[(*k)++] =
8281 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8283 this_regno += 1;
8284 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8285 mode = word_mode;
8286 intregs -= 1;
8288 while (intregs > 0);
8291 /* Recursive workhorse for the following. */
8293 static void
8294 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8295 HOST_WIDE_INT startbitpos, rtx rvec[],
8296 int *k)
8298 tree f;
8300 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8301 if (TREE_CODE (f) == FIELD_DECL)
8303 HOST_WIDE_INT bitpos = startbitpos;
8304 tree ftype = TREE_TYPE (f);
8305 enum machine_mode mode;
8306 if (ftype == error_mark_node)
8307 continue;
8308 mode = TYPE_MODE (ftype);
8310 if (DECL_SIZE (f) != 0
8311 && host_integerp (bit_position (f), 1))
8312 bitpos += int_bit_position (f);
8314 /* ??? FIXME: else assume zero offset. */
8316 if (TREE_CODE (ftype) == RECORD_TYPE)
8317 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8318 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8320 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8321 #if 0
8322 switch (mode)
8324 case SCmode: mode = SFmode; break;
8325 case DCmode: mode = DFmode; break;
8326 case TCmode: mode = TFmode; break;
8327 default: break;
8329 #endif
8330 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8331 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8333 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8334 && (mode == TFmode || mode == TDmode));
8335 /* Long double or _Decimal128 split over regs and memory. */
8336 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8337 cum->use_stack=1;
8339 rvec[(*k)++]
8340 = gen_rtx_EXPR_LIST (VOIDmode,
8341 gen_rtx_REG (mode, cum->fregno++),
8342 GEN_INT (bitpos / BITS_PER_UNIT));
8343 if (mode == TFmode || mode == TDmode)
8344 cum->fregno++;
8346 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8348 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8349 rvec[(*k)++]
8350 = gen_rtx_EXPR_LIST (VOIDmode,
8351 gen_rtx_REG (mode, cum->vregno++),
8352 GEN_INT (bitpos / BITS_PER_UNIT));
8354 else if (cum->intoffset == -1)
8355 cum->intoffset = bitpos;
8359 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8360 the register(s) to be used for each field and subfield of a struct
8361 being passed by value, along with the offset of where the
8362 register's value may be found in the block. FP fields go in FP
8363 register, vector fields go in vector registers, and everything
8364 else goes in int registers, packed as in memory.
8366 This code is also used for function return values. RETVAL indicates
8367 whether this is the case.
8369 Much of this is taken from the SPARC V9 port, which has a similar
8370 calling convention. */
8372 static rtx
8373 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8374 bool named, bool retval)
8376 rtx rvec[FIRST_PSEUDO_REGISTER];
8377 int k = 1, kbase = 1;
8378 HOST_WIDE_INT typesize = int_size_in_bytes (type);
8379 /* This is a copy; modifications are not visible to our caller. */
8380 CUMULATIVE_ARGS copy_cum = *orig_cum;
8381 CUMULATIVE_ARGS *cum = &copy_cum;
8383 /* Pad to 16 byte boundary if needed. */
8384 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8385 && (cum->words % 2) != 0)
8386 cum->words++;
8388 cum->intoffset = 0;
8389 cum->use_stack = 0;
8390 cum->named = named;
8392 /* Put entries into rvec[] for individual FP and vector fields, and
8393 for the chunks of memory that go in int regs. Note we start at
8394 element 1; 0 is reserved for an indication of using memory, and
8395 may or may not be filled in below. */
8396 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8397 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8399 /* If any part of the struct went on the stack put all of it there.
8400 This hack is because the generic code for
8401 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8402 parts of the struct are not at the beginning. */
8403 if (cum->use_stack)
8405 if (retval)
8406 return NULL_RTX; /* doesn't go in registers at all */
8407 kbase = 0;
8408 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8410 if (k > 1 || cum->use_stack)
8411 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8412 else
8413 return NULL_RTX;
8416 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8418 static rtx
8419 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8420 int align_words)
8422 int n_units;
8423 int i, k;
8424 rtx rvec[GP_ARG_NUM_REG + 1];
8426 if (align_words >= GP_ARG_NUM_REG)
8427 return NULL_RTX;
8429 n_units = rs6000_arg_size (mode, type);
8431 /* Optimize the simple case where the arg fits in one gpr, except in
8432 the case of BLKmode due to assign_parms assuming that registers are
8433 BITS_PER_WORD wide. */
8434 if (n_units == 0
8435 || (n_units == 1 && mode != BLKmode))
8436 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8438 k = 0;
8439 if (align_words + n_units > GP_ARG_NUM_REG)
8440 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8441 using a magic NULL_RTX component.
8442 This is not strictly correct. Only some of the arg belongs in
8443 memory, not all of it. However, the normal scheme using
8444 function_arg_partial_nregs can result in unusual subregs, eg.
8445 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8446 store the whole arg to memory is often more efficient than code
8447 to store pieces, and we know that space is available in the right
8448 place for the whole arg. */
8449 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8451 i = 0;
8454 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8455 rtx off = GEN_INT (i++ * 4);
8456 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8458 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8460 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8463 /* Determine where to put an argument to a function.
8464 Value is zero to push the argument on the stack,
8465 or a hard register in which to store the argument.
8467 MODE is the argument's machine mode.
8468 TYPE is the data type of the argument (as a tree).
8469 This is null for libcalls where that information may
8470 not be available.
8471 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8472 the preceding args and about the function being called. It is
8473 not modified in this routine.
8474 NAMED is nonzero if this argument is a named parameter
8475 (otherwise it is an extra parameter matching an ellipsis).
8477 On RS/6000 the first eight words of non-FP are normally in registers
8478 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8479 Under V.4, the first 8 FP args are in registers.
8481 If this is floating-point and no prototype is specified, we use
8482 both an FP and integer register (or possibly FP reg and stack). Library
8483 functions (when CALL_LIBCALL is set) always have the proper types for args,
8484 so we can pass the FP value just in one register. emit_library_function
8485 doesn't support PARALLEL anyway.
8487 Note that for args passed by reference, function_arg will be called
8488 with MODE and TYPE set to that of the pointer to the arg, not the arg
8489 itself. */
8491 static rtx
8492 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8493 const_tree type, bool named)
8495 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8496 enum rs6000_abi abi = DEFAULT_ABI;
8498 /* Return a marker to indicate whether CR1 needs to set or clear the
8499 bit that V.4 uses to say fp args were passed in registers.
8500 Assume that we don't need the marker for software floating point,
8501 or compiler generated library calls. */
8502 if (mode == VOIDmode)
8504 if (abi == ABI_V4
8505 && (cum->call_cookie & CALL_LIBCALL) == 0
8506 && (cum->stdarg
8507 || (cum->nargs_prototype < 0
8508 && (cum->prototype || TARGET_NO_PROTOTYPE))))
8510 /* For the SPE, we need to crxor CR6 always. */
8511 if (TARGET_SPE_ABI)
8512 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8513 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8514 return GEN_INT (cum->call_cookie
8515 | ((cum->fregno == FP_ARG_MIN_REG)
8516 ? CALL_V4_SET_FP_ARGS
8517 : CALL_V4_CLEAR_FP_ARGS));
8520 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8523 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8525 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8526 if (rslt != NULL_RTX)
8527 return rslt;
8528 /* Else fall through to usual handling. */
8531 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8532 if (TARGET_64BIT && ! cum->prototype)
8534 /* Vector parameters get passed in vector register
8535 and also in GPRs or memory, in absence of prototype. */
8536 int align_words;
8537 rtx slot;
8538 align_words = (cum->words + 1) & ~1;
8540 if (align_words >= GP_ARG_NUM_REG)
8542 slot = NULL_RTX;
8544 else
8546 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8548 return gen_rtx_PARALLEL (mode,
8549 gen_rtvec (2,
8550 gen_rtx_EXPR_LIST (VOIDmode,
8551 slot, const0_rtx),
8552 gen_rtx_EXPR_LIST (VOIDmode,
8553 gen_rtx_REG (mode, cum->vregno),
8554 const0_rtx)));
8556 else
8557 return gen_rtx_REG (mode, cum->vregno);
8558 else if (TARGET_ALTIVEC_ABI
8559 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8560 || (type && TREE_CODE (type) == VECTOR_TYPE
8561 && int_size_in_bytes (type) == 16)))
8563 if (named || abi == ABI_V4)
8564 return NULL_RTX;
8565 else
8567 /* Vector parameters to varargs functions under AIX or Darwin
8568 get passed in memory and possibly also in GPRs. */
8569 int align, align_words, n_words;
8570 enum machine_mode part_mode;
8572 /* Vector parameters must be 16-byte aligned. This places them at
8573 2 mod 4 in terms of words in 32-bit mode, since the parameter
8574 save area starts at offset 24 from the stack. In 64-bit mode,
8575 they just have to start on an even word, since the parameter
8576 save area is 16-byte aligned. */
8577 if (TARGET_32BIT)
8578 align = (2 - cum->words) & 3;
8579 else
8580 align = cum->words & 1;
8581 align_words = cum->words + align;
8583 /* Out of registers? Memory, then. */
8584 if (align_words >= GP_ARG_NUM_REG)
8585 return NULL_RTX;
8587 if (TARGET_32BIT && TARGET_POWERPC64)
8588 return rs6000_mixed_function_arg (mode, type, align_words);
8590 /* The vector value goes in GPRs. Only the part of the
8591 value in GPRs is reported here. */
8592 part_mode = mode;
8593 n_words = rs6000_arg_size (mode, type);
8594 if (align_words + n_words > GP_ARG_NUM_REG)
8595 /* Fortunately, there are only two possibilities, the value
8596 is either wholly in GPRs or half in GPRs and half not. */
8597 part_mode = DImode;
8599 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8602 else if (TARGET_SPE_ABI && TARGET_SPE
8603 && (SPE_VECTOR_MODE (mode)
8604 || (TARGET_E500_DOUBLE && (mode == DFmode
8605 || mode == DCmode
8606 || mode == TFmode
8607 || mode == TCmode))))
8608 return rs6000_spe_function_arg (cum, mode, type);
8610 else if (abi == ABI_V4)
8612 if (TARGET_HARD_FLOAT && TARGET_FPRS
8613 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8614 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8615 || (mode == TFmode && !TARGET_IEEEQUAD)
8616 || mode == SDmode || mode == DDmode || mode == TDmode))
8618 /* _Decimal128 must use an even/odd register pair. This assumes
8619 that the register number is odd when fregno is odd. */
8620 if (mode == TDmode && (cum->fregno % 2) == 1)
8621 cum->fregno++;
8623 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8624 <= FP_ARG_V4_MAX_REG)
8625 return gen_rtx_REG (mode, cum->fregno);
8626 else
8627 return NULL_RTX;
8629 else
8631 int n_words = rs6000_arg_size (mode, type);
8632 int gregno = cum->sysv_gregno;
8634 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8635 (r7,r8) or (r9,r10). As does any other 2 word item such
8636 as complex int due to a historical mistake. */
8637 if (n_words == 2)
8638 gregno += (1 - gregno) & 1;
8640 /* Multi-reg args are not split between registers and stack. */
8641 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8642 return NULL_RTX;
8644 if (TARGET_32BIT && TARGET_POWERPC64)
8645 return rs6000_mixed_function_arg (mode, type,
8646 gregno - GP_ARG_MIN_REG);
8647 return gen_rtx_REG (mode, gregno);
8650 else
8652 int align_words = rs6000_parm_start (mode, type, cum->words);
8654 /* _Decimal128 must be passed in an even/odd float register pair.
8655 This assumes that the register number is odd when fregno is odd. */
8656 if (mode == TDmode && (cum->fregno % 2) == 1)
8657 cum->fregno++;
8659 if (USE_FP_FOR_ARG_P (cum, mode, type))
8661 rtx rvec[GP_ARG_NUM_REG + 1];
8662 rtx r;
8663 int k;
8664 bool needs_psave;
8665 enum machine_mode fmode = mode;
8666 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8668 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8670 /* Currently, we only ever need one reg here because complex
8671 doubles are split. */
8672 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8673 && (fmode == TFmode || fmode == TDmode));
8675 /* Long double or _Decimal128 split over regs and memory. */
8676 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8679 /* Do we also need to pass this arg in the parameter save
8680 area? */
8681 needs_psave = (type
8682 && (cum->nargs_prototype <= 0
8683 || (DEFAULT_ABI == ABI_AIX
8684 && TARGET_XL_COMPAT
8685 && align_words >= GP_ARG_NUM_REG)));
8687 if (!needs_psave && mode == fmode)
8688 return gen_rtx_REG (fmode, cum->fregno);
8690 k = 0;
8691 if (needs_psave)
8693 /* Describe the part that goes in gprs or the stack.
8694 This piece must come first, before the fprs. */
8695 if (align_words < GP_ARG_NUM_REG)
8697 unsigned long n_words = rs6000_arg_size (mode, type);
8699 if (align_words + n_words > GP_ARG_NUM_REG
8700 || (TARGET_32BIT && TARGET_POWERPC64))
8702 /* If this is partially on the stack, then we only
8703 include the portion actually in registers here. */
8704 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8705 rtx off;
8706 int i = 0;
8707 if (align_words + n_words > GP_ARG_NUM_REG)
8708 /* Not all of the arg fits in gprs. Say that it
8709 goes in memory too, using a magic NULL_RTX
8710 component. Also see comment in
8711 rs6000_mixed_function_arg for why the normal
8712 function_arg_partial_nregs scheme doesn't work
8713 in this case. */
8714 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8715 const0_rtx);
8718 r = gen_rtx_REG (rmode,
8719 GP_ARG_MIN_REG + align_words);
8720 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8721 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8723 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8725 else
8727 /* The whole arg fits in gprs. */
8728 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8729 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8732 else
8733 /* It's entirely in memory. */
8734 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8737 /* Describe where this piece goes in the fprs. */
8738 r = gen_rtx_REG (fmode, cum->fregno);
8739 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8741 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8743 else if (align_words < GP_ARG_NUM_REG)
8745 if (TARGET_32BIT && TARGET_POWERPC64)
8746 return rs6000_mixed_function_arg (mode, type, align_words);
8748 if (mode == BLKmode)
8749 mode = Pmode;
8751 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8753 else
8754 return NULL_RTX;
8758 /* For an arg passed partly in registers and partly in memory, this is
8759 the number of bytes passed in registers. For args passed entirely in
8760 registers or entirely in memory, zero. When an arg is described by a
8761 PARALLEL, perhaps using more than one register type, this function
8762 returns the number of bytes used by the first element of the PARALLEL. */
8764 static int
8765 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8766 tree type, bool named)
8768 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8769 int ret = 0;
8770 int align_words;
8772 if (DEFAULT_ABI == ABI_V4)
8773 return 0;
8775 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8776 && cum->nargs_prototype >= 0)
8777 return 0;
8779 /* In this complicated case we just disable the partial_nregs code. */
8780 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8781 return 0;
8783 align_words = rs6000_parm_start (mode, type, cum->words);
8785 if (USE_FP_FOR_ARG_P (cum, mode, type))
8787 /* If we are passing this arg in the fixed parameter save area
8788 (gprs or memory) as well as fprs, then this function should
8789 return the number of partial bytes passed in the parameter
8790 save area rather than partial bytes passed in fprs. */
8791 if (type
8792 && (cum->nargs_prototype <= 0
8793 || (DEFAULT_ABI == ABI_AIX
8794 && TARGET_XL_COMPAT
8795 && align_words >= GP_ARG_NUM_REG)))
8796 return 0;
8797 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8798 > FP_ARG_MAX_REG + 1)
8799 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8800 else if (cum->nargs_prototype >= 0)
8801 return 0;
8804 if (align_words < GP_ARG_NUM_REG
8805 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8806 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8808 if (ret != 0 && TARGET_DEBUG_ARG)
8809 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8811 return ret;
8814 /* A C expression that indicates when an argument must be passed by
8815 reference. If nonzero for an argument, a copy of that argument is
8816 made in memory and a pointer to the argument is passed instead of
8817 the argument itself. The pointer is passed in whatever way is
8818 appropriate for passing a pointer to that type.
8820 Under V.4, aggregates and long double are passed by reference.
8822 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8823 reference unless the AltiVec vector extension ABI is in force.
8825 As an extension to all ABIs, variable sized types are passed by
8826 reference. */
8828 static bool
8829 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8830 enum machine_mode mode, const_tree type,
8831 bool named ATTRIBUTE_UNUSED)
8833 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8835 if (TARGET_DEBUG_ARG)
8836 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8837 return 1;
8840 if (!type)
8841 return 0;
8843 #if HAVE_UPC_PTS_STRUCT_REP
8844 if (DEFAULT_ABI == ABI_V4 && POINTER_TYPE_P (type)
8845 && upc_shared_type_p (TREE_TYPE (type)))
8847 if (TARGET_DEBUG_ARG)
8848 fprintf (stderr,
8849 "function_arg_pass_by_reference: V4 UPC ptr to shared\n");
8850 return 1;
8852 #endif
8854 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8856 if (TARGET_DEBUG_ARG)
8857 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8858 return 1;
8861 if (int_size_in_bytes (type) < 0)
8863 if (TARGET_DEBUG_ARG)
8864 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8865 return 1;
8868 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8869 modes only exist for GCC vector types if -maltivec. */
8870 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8872 if (TARGET_DEBUG_ARG)
8873 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8874 return 1;
8877 /* Pass synthetic vectors in memory. */
8878 if (TREE_CODE (type) == VECTOR_TYPE
8879 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8881 static bool warned_for_pass_big_vectors = false;
8882 if (TARGET_DEBUG_ARG)
8883 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8884 if (!warned_for_pass_big_vectors)
8886 warning (0, "GCC vector passed by reference: "
8887 "non-standard ABI extension with no compatibility guarantee");
8888 warned_for_pass_big_vectors = true;
8890 return 1;
8893 return 0;
8896 static void
8897 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8899 int i;
8900 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8902 if (nregs == 0)
8903 return;
8905 for (i = 0; i < nregs; i++)
8907 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8908 if (reload_completed)
8910 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8911 tem = NULL_RTX;
8912 else
8913 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8914 i * GET_MODE_SIZE (reg_mode));
8916 else
8917 tem = replace_equiv_address (tem, XEXP (tem, 0));
8919 gcc_assert (tem);
8921 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8925 /* Perform any needed actions needed for a function that is receiving a
8926 variable number of arguments.
8928 CUM is as above.
8930 MODE and TYPE are the mode and type of the current parameter.
8932 PRETEND_SIZE is a variable that should be set to the amount of stack
8933 that must be pushed by the prolog to pretend that our caller pushed
8936 Normally, this macro will push all remaining incoming registers on the
8937 stack and set PRETEND_SIZE to the length of the registers pushed. */
8939 static void
8940 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8941 tree type, int *pretend_size ATTRIBUTE_UNUSED,
8942 int no_rtl)
8944 CUMULATIVE_ARGS next_cum;
8945 int reg_size = TARGET_32BIT ? 4 : 8;
8946 rtx save_area = NULL_RTX, mem;
8947 int first_reg_offset;
8948 alias_set_type set;
8950 /* Skip the last named argument. */
8951 next_cum = *get_cumulative_args (cum);
8952 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8954 if (DEFAULT_ABI == ABI_V4)
8956 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8958 if (! no_rtl)
8960 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8961 HOST_WIDE_INT offset = 0;
8963 /* Try to optimize the size of the varargs save area.
8964 The ABI requires that ap.reg_save_area is doubleword
8965 aligned, but we don't need to allocate space for all
8966 the bytes, only those to which we actually will save
8967 anything. */
8968 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8969 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8970 if (TARGET_HARD_FLOAT && TARGET_FPRS
8971 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8972 && cfun->va_list_fpr_size)
8974 if (gpr_reg_num)
8975 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8976 * UNITS_PER_FP_WORD;
8977 if (cfun->va_list_fpr_size
8978 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8979 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8980 else
8981 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8982 * UNITS_PER_FP_WORD;
8984 if (gpr_reg_num)
8986 offset = -((first_reg_offset * reg_size) & ~7);
8987 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8989 gpr_reg_num = cfun->va_list_gpr_size;
8990 if (reg_size == 4 && (first_reg_offset & 1))
8991 gpr_reg_num++;
8993 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8995 else if (fpr_size)
8996 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8997 * UNITS_PER_FP_WORD
8998 - (int) (GP_ARG_NUM_REG * reg_size);
9000 if (gpr_size + fpr_size)
9002 rtx reg_save_area
9003 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
9004 gcc_assert (GET_CODE (reg_save_area) == MEM);
9005 reg_save_area = XEXP (reg_save_area, 0);
9006 if (GET_CODE (reg_save_area) == PLUS)
9008 gcc_assert (XEXP (reg_save_area, 0)
9009 == virtual_stack_vars_rtx);
9010 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
9011 offset += INTVAL (XEXP (reg_save_area, 1));
9013 else
9014 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
9017 cfun->machine->varargs_save_offset = offset;
9018 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
9021 else
9023 first_reg_offset = next_cum.words;
9024 save_area = virtual_incoming_args_rtx;
9026 if (targetm.calls.must_pass_in_stack (mode, type))
9027 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
9030 set = get_varargs_alias_set ();
9031 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
9032 && cfun->va_list_gpr_size)
9034 int nregs = GP_ARG_NUM_REG - first_reg_offset;
9036 if (va_list_gpr_counter_field)
9038 /* V4 va_list_gpr_size counts number of registers needed. */
9039 if (nregs > cfun->va_list_gpr_size)
9040 nregs = cfun->va_list_gpr_size;
9042 else
9044 /* char * va_list instead counts number of bytes needed. */
9045 if (nregs > cfun->va_list_gpr_size / reg_size)
9046 nregs = cfun->va_list_gpr_size / reg_size;
9049 mem = gen_rtx_MEM (BLKmode,
9050 plus_constant (Pmode, save_area,
9051 first_reg_offset * reg_size));
9052 MEM_NOTRAP_P (mem) = 1;
9053 set_mem_alias_set (mem, set);
9054 set_mem_align (mem, BITS_PER_WORD);
9056 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
9057 nregs);
9060 /* Save FP registers if needed. */
9061 if (DEFAULT_ABI == ABI_V4
9062 && TARGET_HARD_FLOAT && TARGET_FPRS
9063 && ! no_rtl
9064 && next_cum.fregno <= FP_ARG_V4_MAX_REG
9065 && cfun->va_list_fpr_size)
9067 int fregno = next_cum.fregno, nregs;
9068 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
9069 rtx lab = gen_label_rtx ();
9070 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
9071 * UNITS_PER_FP_WORD);
9073 emit_jump_insn
9074 (gen_rtx_SET (VOIDmode,
9075 pc_rtx,
9076 gen_rtx_IF_THEN_ELSE (VOIDmode,
9077 gen_rtx_NE (VOIDmode, cr1,
9078 const0_rtx),
9079 gen_rtx_LABEL_REF (VOIDmode, lab),
9080 pc_rtx)));
9082 for (nregs = 0;
9083 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
9084 fregno++, off += UNITS_PER_FP_WORD, nregs++)
9086 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9087 ? DFmode : SFmode,
9088 plus_constant (Pmode, save_area, off));
9089 MEM_NOTRAP_P (mem) = 1;
9090 set_mem_alias_set (mem, set);
9091 set_mem_align (mem, GET_MODE_ALIGNMENT (
9092 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9093 ? DFmode : SFmode));
9094 emit_move_insn (mem, gen_rtx_REG (
9095 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9096 ? DFmode : SFmode, fregno));
9099 emit_label (lab);
9103 /* Create the va_list data type. */
9105 static tree
9106 rs6000_build_builtin_va_list (void)
9108 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
9110 /* For AIX, prefer 'char *' because that's what the system
9111 header files like. */
9112 if (DEFAULT_ABI != ABI_V4)
9113 return build_pointer_type (char_type_node);
9115 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
9116 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
9117 get_identifier ("__va_list_tag"), record);
9119 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
9120 unsigned_char_type_node);
9121 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
9122 unsigned_char_type_node);
9123 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9124 every user file. */
9125 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9126 get_identifier ("reserved"), short_unsigned_type_node);
9127 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9128 get_identifier ("overflow_arg_area"),
9129 ptr_type_node);
9130 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9131 get_identifier ("reg_save_area"),
9132 ptr_type_node);
9134 va_list_gpr_counter_field = f_gpr;
9135 va_list_fpr_counter_field = f_fpr;
9137 DECL_FIELD_CONTEXT (f_gpr) = record;
9138 DECL_FIELD_CONTEXT (f_fpr) = record;
9139 DECL_FIELD_CONTEXT (f_res) = record;
9140 DECL_FIELD_CONTEXT (f_ovf) = record;
9141 DECL_FIELD_CONTEXT (f_sav) = record;
9143 TYPE_STUB_DECL (record) = type_decl;
9144 TYPE_NAME (record) = type_decl;
9145 TYPE_FIELDS (record) = f_gpr;
9146 DECL_CHAIN (f_gpr) = f_fpr;
9147 DECL_CHAIN (f_fpr) = f_res;
9148 DECL_CHAIN (f_res) = f_ovf;
9149 DECL_CHAIN (f_ovf) = f_sav;
9151 layout_type (record);
9153 /* The correct type is an array type of one element. */
9154 return build_array_type (record, build_index_type (size_zero_node));
9157 /* Implement va_start. */
9159 static void
9160 rs6000_va_start (tree valist, rtx nextarg)
9162 HOST_WIDE_INT words, n_gpr, n_fpr;
9163 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9164 tree gpr, fpr, ovf, sav, t;
9166 /* Only SVR4 needs something special. */
9167 if (DEFAULT_ABI != ABI_V4)
9169 std_expand_builtin_va_start (valist, nextarg);
9170 return;
9173 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9174 f_fpr = DECL_CHAIN (f_gpr);
9175 f_res = DECL_CHAIN (f_fpr);
9176 f_ovf = DECL_CHAIN (f_res);
9177 f_sav = DECL_CHAIN (f_ovf);
9179 valist = build_simple_mem_ref (valist);
9180 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9181 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9182 f_fpr, NULL_TREE);
9183 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9184 f_ovf, NULL_TREE);
9185 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9186 f_sav, NULL_TREE);
9188 /* Count number of gp and fp argument registers used. */
9189 words = crtl->args.info.words;
9190 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
9191 GP_ARG_NUM_REG);
9192 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
9193 FP_ARG_NUM_REG);
9195 if (TARGET_DEBUG_ARG)
9196 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
9197 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
9198 words, n_gpr, n_fpr);
9200 if (cfun->va_list_gpr_size)
9202 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9203 build_int_cst (NULL_TREE, n_gpr));
9204 TREE_SIDE_EFFECTS (t) = 1;
9205 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9208 if (cfun->va_list_fpr_size)
9210 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9211 build_int_cst (NULL_TREE, n_fpr));
9212 TREE_SIDE_EFFECTS (t) = 1;
9213 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9215 #ifdef HAVE_AS_GNU_ATTRIBUTE
9216 if (call_ABI_of_interest (cfun->decl))
9217 rs6000_passes_float = true;
9218 #endif
9221 /* Find the overflow area. */
9222 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9223 if (words != 0)
9224 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
9225 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9226 TREE_SIDE_EFFECTS (t) = 1;
9227 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9229 /* If there were no va_arg invocations, don't set up the register
9230 save area. */
9231 if (!cfun->va_list_gpr_size
9232 && !cfun->va_list_fpr_size
9233 && n_gpr < GP_ARG_NUM_REG
9234 && n_fpr < FP_ARG_V4_MAX_REG)
9235 return;
9237 /* Find the register save area. */
9238 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
9239 if (cfun->machine->varargs_save_offset)
9240 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
9241 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9242 TREE_SIDE_EFFECTS (t) = 1;
9243 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9246 /* Implement va_arg. */
9248 static tree
9249 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9250 gimple_seq *post_p)
9252 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9253 tree gpr, fpr, ovf, sav, reg, t, u;
9254 int size, rsize, n_reg, sav_ofs, sav_scale;
9255 tree lab_false, lab_over, addr;
9256 int align;
9257 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9258 int regalign = 0;
9259 gimple stmt;
9261 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9263 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9264 return build_va_arg_indirect_ref (t);
9267 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9268 earlier version of gcc, with the property that it always applied alignment
9269 adjustments to the va-args (even for zero-sized types). The cheapest way
9270 to deal with this is to replicate the effect of the part of
9271 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9272 of relevance.
9273 We don't need to check for pass-by-reference because of the test above.
9274 We can return a simplifed answer, since we know there's no offset to add. */
9276 if (TARGET_MACHO
9277 && rs6000_darwin64_abi
9278 && integer_zerop (TYPE_SIZE (type)))
9280 unsigned HOST_WIDE_INT align, boundary;
9281 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9282 align = PARM_BOUNDARY / BITS_PER_UNIT;
9283 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9284 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9285 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9286 boundary /= BITS_PER_UNIT;
9287 if (boundary > align)
9289 tree t ;
9290 /* This updates arg ptr by the amount that would be necessary
9291 to align the zero-sized (but not zero-alignment) item. */
9292 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9293 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9294 gimplify_and_add (t, pre_p);
9296 t = fold_convert (sizetype, valist_tmp);
9297 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9298 fold_convert (TREE_TYPE (valist),
9299 fold_build2 (BIT_AND_EXPR, sizetype, t,
9300 size_int (-boundary))));
9301 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9302 gimplify_and_add (t, pre_p);
9304 /* Since it is zero-sized there's no increment for the item itself. */
9305 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9306 return build_va_arg_indirect_ref (valist_tmp);
9309 if (DEFAULT_ABI != ABI_V4)
9311 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9313 tree elem_type = TREE_TYPE (type);
9314 enum machine_mode elem_mode = TYPE_MODE (elem_type);
9315 int elem_size = GET_MODE_SIZE (elem_mode);
9317 if (elem_size < UNITS_PER_WORD)
9319 tree real_part, imag_part;
9320 gimple_seq post = NULL;
9322 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9323 &post);
9324 /* Copy the value into a temporary, lest the formal temporary
9325 be reused out from under us. */
9326 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9327 gimple_seq_add_seq (pre_p, post);
9329 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9330 post_p);
9332 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9336 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9339 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9340 f_fpr = DECL_CHAIN (f_gpr);
9341 f_res = DECL_CHAIN (f_fpr);
9342 f_ovf = DECL_CHAIN (f_res);
9343 f_sav = DECL_CHAIN (f_ovf);
9345 valist = build_va_arg_indirect_ref (valist);
9346 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9347 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9348 f_fpr, NULL_TREE);
9349 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9350 f_ovf, NULL_TREE);
9351 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9352 f_sav, NULL_TREE);
9354 size = int_size_in_bytes (type);
9355 rsize = (size + 3) / 4;
9356 align = 1;
9358 if (TARGET_HARD_FLOAT && TARGET_FPRS
9359 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9360 || (TARGET_DOUBLE_FLOAT
9361 && (TYPE_MODE (type) == DFmode
9362 || TYPE_MODE (type) == TFmode
9363 || TYPE_MODE (type) == SDmode
9364 || TYPE_MODE (type) == DDmode
9365 || TYPE_MODE (type) == TDmode))))
9367 /* FP args go in FP registers, if present. */
9368 reg = fpr;
9369 n_reg = (size + 7) / 8;
9370 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9371 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9372 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9373 align = 8;
9375 else
9377 /* Otherwise into GP registers. */
9378 reg = gpr;
9379 n_reg = rsize;
9380 sav_ofs = 0;
9381 sav_scale = 4;
9382 if (n_reg == 2)
9383 align = 8;
9386 /* Pull the value out of the saved registers.... */
9388 lab_over = NULL;
9389 addr = create_tmp_var (ptr_type_node, "addr");
9391 /* AltiVec vectors never go in registers when -mabi=altivec. */
9392 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9393 align = 16;
9394 else
9396 lab_false = create_artificial_label (input_location);
9397 lab_over = create_artificial_label (input_location);
9399 /* Long long and SPE vectors are aligned in the registers.
9400 As are any other 2 gpr item such as complex int due to a
9401 historical mistake. */
9402 u = reg;
9403 if (n_reg == 2 && reg == gpr)
9405 regalign = 1;
9406 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9407 build_int_cst (TREE_TYPE (reg), n_reg - 1));
9408 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9409 unshare_expr (reg), u);
9411 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9412 reg number is 0 for f1, so we want to make it odd. */
9413 else if (reg == fpr && TYPE_MODE (type) == TDmode)
9415 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9416 build_int_cst (TREE_TYPE (reg), 1));
9417 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9420 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9421 t = build2 (GE_EXPR, boolean_type_node, u, t);
9422 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9423 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9424 gimplify_and_add (t, pre_p);
9426 t = sav;
9427 if (sav_ofs)
9428 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9430 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9431 build_int_cst (TREE_TYPE (reg), n_reg));
9432 u = fold_convert (sizetype, u);
9433 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9434 t = fold_build_pointer_plus (t, u);
9436 /* _Decimal32 varargs are located in the second word of the 64-bit
9437 FP register for 32-bit binaries. */
9438 if (!TARGET_POWERPC64
9439 && TARGET_HARD_FLOAT && TARGET_FPRS
9440 && TYPE_MODE (type) == SDmode)
9441 t = fold_build_pointer_plus_hwi (t, size);
9443 gimplify_assign (addr, t, pre_p);
9445 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9447 stmt = gimple_build_label (lab_false);
9448 gimple_seq_add_stmt (pre_p, stmt);
9450 if ((n_reg == 2 && !regalign) || n_reg > 2)
9452 /* Ensure that we don't find any more args in regs.
9453 Alignment has taken care of for special cases. */
9454 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9458 /* ... otherwise out of the overflow area. */
9460 /* Care for on-stack alignment if needed. */
9461 t = ovf;
9462 if (align != 1)
9464 t = fold_build_pointer_plus_hwi (t, align - 1);
9465 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9466 build_int_cst (TREE_TYPE (t), -align));
9468 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9470 gimplify_assign (unshare_expr (addr), t, pre_p);
9472 t = fold_build_pointer_plus_hwi (t, size);
9473 gimplify_assign (unshare_expr (ovf), t, pre_p);
9475 if (lab_over)
9477 stmt = gimple_build_label (lab_over);
9478 gimple_seq_add_stmt (pre_p, stmt);
9481 if (STRICT_ALIGNMENT
9482 && (TYPE_ALIGN (type)
9483 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9485 /* The value (of type complex double, for example) may not be
9486 aligned in memory in the saved registers, so copy via a
9487 temporary. (This is the same code as used for SPARC.) */
9488 tree tmp = create_tmp_var (type, "va_arg_tmp");
9489 tree dest_addr = build_fold_addr_expr (tmp);
9491 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9492 3, dest_addr, addr, size_int (rsize * 4));
9494 gimplify_and_add (copy, pre_p);
9495 addr = dest_addr;
9498 addr = fold_convert (ptrtype, addr);
9499 return build_va_arg_indirect_ref (addr);
9502 /* Builtins. */
9504 static void
9505 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9507 tree t;
9508 unsigned classify = rs6000_builtin_info[(int)code].attr;
9509 const char *attr_string = "";
9511 gcc_assert (name != NULL);
9512 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9514 if (rs6000_builtin_decls[(int)code])
9515 fatal_error ("internal error: builtin function %s already processed", name);
9517 rs6000_builtin_decls[(int)code] = t =
9518 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9520 /* Set any special attributes. */
9521 if ((classify & RS6000_BTC_CONST) != 0)
9523 /* const function, function only depends on the inputs. */
9524 TREE_READONLY (t) = 1;
9525 TREE_NOTHROW (t) = 1;
9526 attr_string = ", pure";
9528 else if ((classify & RS6000_BTC_PURE) != 0)
9530 /* pure function, function can read global memory, but does not set any
9531 external state. */
9532 DECL_PURE_P (t) = 1;
9533 TREE_NOTHROW (t) = 1;
9534 attr_string = ", const";
9536 else if ((classify & RS6000_BTC_FP) != 0)
9538 /* Function is a math function. If rounding mode is on, then treat the
9539 function as not reading global memory, but it can have arbitrary side
9540 effects. If it is off, then assume the function is a const function.
9541 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9542 builtin-attribute.def that is used for the math functions. */
9543 TREE_NOTHROW (t) = 1;
9544 if (flag_rounding_math)
9546 DECL_PURE_P (t) = 1;
9547 DECL_IS_NOVOPS (t) = 1;
9548 attr_string = ", fp, pure";
9550 else
9552 TREE_READONLY (t) = 1;
9553 attr_string = ", fp, const";
9556 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9557 gcc_unreachable ();
9559 if (TARGET_DEBUG_BUILTIN)
9560 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9561 (int)code, name, attr_string);
9564 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9566 #undef RS6000_BUILTIN_1
9567 #undef RS6000_BUILTIN_2
9568 #undef RS6000_BUILTIN_3
9569 #undef RS6000_BUILTIN_A
9570 #undef RS6000_BUILTIN_D
9571 #undef RS6000_BUILTIN_E
9572 #undef RS6000_BUILTIN_P
9573 #undef RS6000_BUILTIN_Q
9574 #undef RS6000_BUILTIN_S
9575 #undef RS6000_BUILTIN_X
9577 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9578 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9579 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9580 { MASK, ICODE, NAME, ENUM },
9582 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9583 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9584 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9585 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9586 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9587 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9588 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9590 static const struct builtin_description bdesc_3arg[] =
9592 #include "rs6000-builtin.def"
9595 /* DST operations: void foo (void *, const int, const char). */
9597 #undef RS6000_BUILTIN_1
9598 #undef RS6000_BUILTIN_2
9599 #undef RS6000_BUILTIN_3
9600 #undef RS6000_BUILTIN_A
9601 #undef RS6000_BUILTIN_D
9602 #undef RS6000_BUILTIN_E
9603 #undef RS6000_BUILTIN_P
9604 #undef RS6000_BUILTIN_Q
9605 #undef RS6000_BUILTIN_S
9606 #undef RS6000_BUILTIN_X
9608 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9609 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9610 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9611 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9612 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9613 { MASK, ICODE, NAME, ENUM },
9615 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9616 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9617 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9618 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9619 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9621 static const struct builtin_description bdesc_dst[] =
9623 #include "rs6000-builtin.def"
9626 /* Simple binary operations: VECc = foo (VECa, VECb). */
9628 #undef RS6000_BUILTIN_1
9629 #undef RS6000_BUILTIN_2
9630 #undef RS6000_BUILTIN_3
9631 #undef RS6000_BUILTIN_A
9632 #undef RS6000_BUILTIN_D
9633 #undef RS6000_BUILTIN_E
9634 #undef RS6000_BUILTIN_P
9635 #undef RS6000_BUILTIN_Q
9636 #undef RS6000_BUILTIN_S
9637 #undef RS6000_BUILTIN_X
9639 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9640 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9641 { MASK, ICODE, NAME, ENUM },
9643 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9644 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9645 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9646 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9647 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9648 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9649 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9650 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9652 static const struct builtin_description bdesc_2arg[] =
9654 #include "rs6000-builtin.def"
9657 #undef RS6000_BUILTIN_1
9658 #undef RS6000_BUILTIN_2
9659 #undef RS6000_BUILTIN_3
9660 #undef RS6000_BUILTIN_A
9661 #undef RS6000_BUILTIN_D
9662 #undef RS6000_BUILTIN_E
9663 #undef RS6000_BUILTIN_P
9664 #undef RS6000_BUILTIN_Q
9665 #undef RS6000_BUILTIN_S
9666 #undef RS6000_BUILTIN_X
9668 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9669 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9670 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9671 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9672 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9673 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9674 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9675 { MASK, ICODE, NAME, ENUM },
9677 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9678 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9679 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9681 /* AltiVec predicates. */
9683 static const struct builtin_description bdesc_altivec_preds[] =
9685 #include "rs6000-builtin.def"
9688 /* SPE predicates. */
9689 #undef RS6000_BUILTIN_1
9690 #undef RS6000_BUILTIN_2
9691 #undef RS6000_BUILTIN_3
9692 #undef RS6000_BUILTIN_A
9693 #undef RS6000_BUILTIN_D
9694 #undef RS6000_BUILTIN_E
9695 #undef RS6000_BUILTIN_P
9696 #undef RS6000_BUILTIN_Q
9697 #undef RS6000_BUILTIN_S
9698 #undef RS6000_BUILTIN_X
9700 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9701 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9702 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9703 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9704 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9705 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9706 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9707 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9708 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9709 { MASK, ICODE, NAME, ENUM },
9711 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9713 static const struct builtin_description bdesc_spe_predicates[] =
9715 #include "rs6000-builtin.def"
9718 /* SPE evsel predicates. */
9719 #undef RS6000_BUILTIN_1
9720 #undef RS6000_BUILTIN_2
9721 #undef RS6000_BUILTIN_3
9722 #undef RS6000_BUILTIN_A
9723 #undef RS6000_BUILTIN_D
9724 #undef RS6000_BUILTIN_E
9725 #undef RS6000_BUILTIN_P
9726 #undef RS6000_BUILTIN_Q
9727 #undef RS6000_BUILTIN_S
9728 #undef RS6000_BUILTIN_X
9730 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9731 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9732 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9733 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9734 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9735 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9736 { MASK, ICODE, NAME, ENUM },
9738 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9739 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9740 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9741 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9743 static const struct builtin_description bdesc_spe_evsel[] =
9745 #include "rs6000-builtin.def"
9748 /* PAIRED predicates. */
9749 #undef RS6000_BUILTIN_1
9750 #undef RS6000_BUILTIN_2
9751 #undef RS6000_BUILTIN_3
9752 #undef RS6000_BUILTIN_A
9753 #undef RS6000_BUILTIN_D
9754 #undef RS6000_BUILTIN_E
9755 #undef RS6000_BUILTIN_P
9756 #undef RS6000_BUILTIN_Q
9757 #undef RS6000_BUILTIN_S
9758 #undef RS6000_BUILTIN_X
9760 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9761 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9762 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9763 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9764 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9765 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9766 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9767 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9768 { MASK, ICODE, NAME, ENUM },
9770 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9771 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9773 static const struct builtin_description bdesc_paired_preds[] =
9775 #include "rs6000-builtin.def"
9778 /* ABS* operations. */
9780 #undef RS6000_BUILTIN_1
9781 #undef RS6000_BUILTIN_2
9782 #undef RS6000_BUILTIN_3
9783 #undef RS6000_BUILTIN_A
9784 #undef RS6000_BUILTIN_D
9785 #undef RS6000_BUILTIN_E
9786 #undef RS6000_BUILTIN_P
9787 #undef RS6000_BUILTIN_Q
9788 #undef RS6000_BUILTIN_S
9789 #undef RS6000_BUILTIN_X
9791 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9792 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9793 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9794 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9795 { MASK, ICODE, NAME, ENUM },
9797 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9798 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9799 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9800 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9801 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9802 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9804 static const struct builtin_description bdesc_abs[] =
9806 #include "rs6000-builtin.def"
9809 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9810 foo (VECa). */
9812 #undef RS6000_BUILTIN_1
9813 #undef RS6000_BUILTIN_2
9814 #undef RS6000_BUILTIN_3
9815 #undef RS6000_BUILTIN_A
9816 #undef RS6000_BUILTIN_E
9817 #undef RS6000_BUILTIN_D
9818 #undef RS6000_BUILTIN_P
9819 #undef RS6000_BUILTIN_Q
9820 #undef RS6000_BUILTIN_S
9821 #undef RS6000_BUILTIN_X
9823 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9824 { MASK, ICODE, NAME, ENUM },
9826 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9827 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9828 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9829 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9830 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9831 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9832 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9833 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9834 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9836 static const struct builtin_description bdesc_1arg[] =
9838 #include "rs6000-builtin.def"
9841 #undef RS6000_BUILTIN_1
9842 #undef RS6000_BUILTIN_2
9843 #undef RS6000_BUILTIN_3
9844 #undef RS6000_BUILTIN_A
9845 #undef RS6000_BUILTIN_D
9846 #undef RS6000_BUILTIN_E
9847 #undef RS6000_BUILTIN_P
9848 #undef RS6000_BUILTIN_Q
9849 #undef RS6000_BUILTIN_S
9850 #undef RS6000_BUILTIN_X
9852 /* Return true if a builtin function is overloaded. */
9853 bool
9854 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9856 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9859 /* Expand an expression EXP that calls a builtin without arguments. */
9860 static rtx
9861 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
9863 rtx pat;
9864 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9866 if (icode == CODE_FOR_nothing)
9867 /* Builtin not supported on this processor. */
9868 return 0;
9870 if (target == 0
9871 || GET_MODE (target) != tmode
9872 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9873 target = gen_reg_rtx (tmode);
9875 pat = GEN_FCN (icode) (target);
9876 if (! pat)
9877 return 0;
9878 emit_insn (pat);
9880 return target;
9884 static rtx
9885 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9887 rtx pat;
9888 tree arg0 = CALL_EXPR_ARG (exp, 0);
9889 rtx op0 = expand_normal (arg0);
9890 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9891 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9893 if (icode == CODE_FOR_nothing)
9894 /* Builtin not supported on this processor. */
9895 return 0;
9897 /* If we got invalid arguments bail out before generating bad rtl. */
9898 if (arg0 == error_mark_node)
9899 return const0_rtx;
9901 if (icode == CODE_FOR_altivec_vspltisb
9902 || icode == CODE_FOR_altivec_vspltish
9903 || icode == CODE_FOR_altivec_vspltisw
9904 || icode == CODE_FOR_spe_evsplatfi
9905 || icode == CODE_FOR_spe_evsplati)
9907 /* Only allow 5-bit *signed* literals. */
9908 if (GET_CODE (op0) != CONST_INT
9909 || INTVAL (op0) > 15
9910 || INTVAL (op0) < -16)
9912 error ("argument 1 must be a 5-bit signed literal");
9913 return const0_rtx;
9917 if (target == 0
9918 || GET_MODE (target) != tmode
9919 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9920 target = gen_reg_rtx (tmode);
9922 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9923 op0 = copy_to_mode_reg (mode0, op0);
9925 pat = GEN_FCN (icode) (target, op0);
9926 if (! pat)
9927 return 0;
9928 emit_insn (pat);
9930 return target;
9933 static rtx
9934 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9936 rtx pat, scratch1, scratch2;
9937 tree arg0 = CALL_EXPR_ARG (exp, 0);
9938 rtx op0 = expand_normal (arg0);
9939 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9940 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9942 /* If we have invalid arguments, bail out before generating bad rtl. */
9943 if (arg0 == error_mark_node)
9944 return const0_rtx;
9946 if (target == 0
9947 || GET_MODE (target) != tmode
9948 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9949 target = gen_reg_rtx (tmode);
9951 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9952 op0 = copy_to_mode_reg (mode0, op0);
9954 scratch1 = gen_reg_rtx (mode0);
9955 scratch2 = gen_reg_rtx (mode0);
9957 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9958 if (! pat)
9959 return 0;
9960 emit_insn (pat);
9962 return target;
9965 static rtx
9966 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9968 rtx pat;
9969 tree arg0 = CALL_EXPR_ARG (exp, 0);
9970 tree arg1 = CALL_EXPR_ARG (exp, 1);
9971 rtx op0 = expand_normal (arg0);
9972 rtx op1 = expand_normal (arg1);
9973 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9974 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9975 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9977 if (icode == CODE_FOR_nothing)
9978 /* Builtin not supported on this processor. */
9979 return 0;
9981 /* If we got invalid arguments bail out before generating bad rtl. */
9982 if (arg0 == error_mark_node || arg1 == error_mark_node)
9983 return const0_rtx;
9985 if (icode == CODE_FOR_altivec_vcfux
9986 || icode == CODE_FOR_altivec_vcfsx
9987 || icode == CODE_FOR_altivec_vctsxs
9988 || icode == CODE_FOR_altivec_vctuxs
9989 || icode == CODE_FOR_altivec_vspltb
9990 || icode == CODE_FOR_altivec_vsplth
9991 || icode == CODE_FOR_altivec_vspltw
9992 || icode == CODE_FOR_spe_evaddiw
9993 || icode == CODE_FOR_spe_evldd
9994 || icode == CODE_FOR_spe_evldh
9995 || icode == CODE_FOR_spe_evldw
9996 || icode == CODE_FOR_spe_evlhhesplat
9997 || icode == CODE_FOR_spe_evlhhossplat
9998 || icode == CODE_FOR_spe_evlhhousplat
9999 || icode == CODE_FOR_spe_evlwhe
10000 || icode == CODE_FOR_spe_evlwhos
10001 || icode == CODE_FOR_spe_evlwhou
10002 || icode == CODE_FOR_spe_evlwhsplat
10003 || icode == CODE_FOR_spe_evlwwsplat
10004 || icode == CODE_FOR_spe_evrlwi
10005 || icode == CODE_FOR_spe_evslwi
10006 || icode == CODE_FOR_spe_evsrwis
10007 || icode == CODE_FOR_spe_evsubifw
10008 || icode == CODE_FOR_spe_evsrwiu)
10010 /* Only allow 5-bit unsigned literals. */
10011 STRIP_NOPS (arg1);
10012 if (TREE_CODE (arg1) != INTEGER_CST
10013 || TREE_INT_CST_LOW (arg1) & ~0x1f)
10015 error ("argument 2 must be a 5-bit unsigned literal");
10016 return const0_rtx;
10020 if (target == 0
10021 || GET_MODE (target) != tmode
10022 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10023 target = gen_reg_rtx (tmode);
10025 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10026 op0 = copy_to_mode_reg (mode0, op0);
10027 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10028 op1 = copy_to_mode_reg (mode1, op1);
10030 pat = GEN_FCN (icode) (target, op0, op1);
10031 if (! pat)
10032 return 0;
10033 emit_insn (pat);
10035 return target;
10038 static rtx
10039 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
10041 rtx pat, scratch;
10042 tree cr6_form = CALL_EXPR_ARG (exp, 0);
10043 tree arg0 = CALL_EXPR_ARG (exp, 1);
10044 tree arg1 = CALL_EXPR_ARG (exp, 2);
10045 rtx op0 = expand_normal (arg0);
10046 rtx op1 = expand_normal (arg1);
10047 enum machine_mode tmode = SImode;
10048 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10049 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10050 int cr6_form_int;
10052 if (TREE_CODE (cr6_form) != INTEGER_CST)
10054 error ("argument 1 of __builtin_altivec_predicate must be a constant");
10055 return const0_rtx;
10057 else
10058 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
10060 gcc_assert (mode0 == mode1);
10062 /* If we have invalid arguments, bail out before generating bad rtl. */
10063 if (arg0 == error_mark_node || arg1 == error_mark_node)
10064 return const0_rtx;
10066 if (target == 0
10067 || GET_MODE (target) != tmode
10068 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10069 target = gen_reg_rtx (tmode);
10071 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10072 op0 = copy_to_mode_reg (mode0, op0);
10073 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10074 op1 = copy_to_mode_reg (mode1, op1);
10076 scratch = gen_reg_rtx (mode0);
10078 pat = GEN_FCN (icode) (scratch, op0, op1);
10079 if (! pat)
10080 return 0;
10081 emit_insn (pat);
10083 /* The vec_any* and vec_all* predicates use the same opcodes for two
10084 different operations, but the bits in CR6 will be different
10085 depending on what information we want. So we have to play tricks
10086 with CR6 to get the right bits out.
10088 If you think this is disgusting, look at the specs for the
10089 AltiVec predicates. */
10091 switch (cr6_form_int)
10093 case 0:
10094 emit_insn (gen_cr6_test_for_zero (target));
10095 break;
10096 case 1:
10097 emit_insn (gen_cr6_test_for_zero_reverse (target));
10098 break;
10099 case 2:
10100 emit_insn (gen_cr6_test_for_lt (target));
10101 break;
10102 case 3:
10103 emit_insn (gen_cr6_test_for_lt_reverse (target));
10104 break;
10105 default:
10106 error ("argument 1 of __builtin_altivec_predicate is out of range");
10107 break;
10110 return target;
10113 static rtx
10114 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
10116 rtx pat, addr;
10117 tree arg0 = CALL_EXPR_ARG (exp, 0);
10118 tree arg1 = CALL_EXPR_ARG (exp, 1);
10119 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10120 enum machine_mode mode0 = Pmode;
10121 enum machine_mode mode1 = Pmode;
10122 rtx op0 = expand_normal (arg0);
10123 rtx op1 = expand_normal (arg1);
10125 if (icode == CODE_FOR_nothing)
10126 /* Builtin not supported on this processor. */
10127 return 0;
10129 /* If we got invalid arguments bail out before generating bad rtl. */
10130 if (arg0 == error_mark_node || arg1 == error_mark_node)
10131 return const0_rtx;
10133 if (target == 0
10134 || GET_MODE (target) != tmode
10135 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10136 target = gen_reg_rtx (tmode);
10138 op1 = copy_to_mode_reg (mode1, op1);
10140 if (op0 == const0_rtx)
10142 addr = gen_rtx_MEM (tmode, op1);
10144 else
10146 op0 = copy_to_mode_reg (mode0, op0);
10147 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
10150 pat = GEN_FCN (icode) (target, addr);
10152 if (! pat)
10153 return 0;
10154 emit_insn (pat);
10156 return target;
10159 static rtx
10160 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
10162 rtx pat, addr;
10163 tree arg0 = CALL_EXPR_ARG (exp, 0);
10164 tree arg1 = CALL_EXPR_ARG (exp, 1);
10165 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10166 enum machine_mode mode0 = Pmode;
10167 enum machine_mode mode1 = Pmode;
10168 rtx op0 = expand_normal (arg0);
10169 rtx op1 = expand_normal (arg1);
10171 if (icode == CODE_FOR_nothing)
10172 /* Builtin not supported on this processor. */
10173 return 0;
10175 /* If we got invalid arguments bail out before generating bad rtl. */
10176 if (arg0 == error_mark_node || arg1 == error_mark_node)
10177 return const0_rtx;
10179 if (target == 0
10180 || GET_MODE (target) != tmode
10181 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10182 target = gen_reg_rtx (tmode);
10184 op1 = copy_to_mode_reg (mode1, op1);
10186 if (op0 == const0_rtx)
10188 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
10190 else
10192 op0 = copy_to_mode_reg (mode0, op0);
10193 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
10196 pat = GEN_FCN (icode) (target, addr);
10198 if (! pat)
10199 return 0;
10200 emit_insn (pat);
10202 return target;
10205 static rtx
10206 spe_expand_stv_builtin (enum insn_code icode, tree exp)
10208 tree arg0 = CALL_EXPR_ARG (exp, 0);
10209 tree arg1 = CALL_EXPR_ARG (exp, 1);
10210 tree arg2 = CALL_EXPR_ARG (exp, 2);
10211 rtx op0 = expand_normal (arg0);
10212 rtx op1 = expand_normal (arg1);
10213 rtx op2 = expand_normal (arg2);
10214 rtx pat;
10215 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10216 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
10217 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
10219 /* Invalid arguments. Bail before doing anything stoopid! */
10220 if (arg0 == error_mark_node
10221 || arg1 == error_mark_node
10222 || arg2 == error_mark_node)
10223 return const0_rtx;
10225 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
10226 op0 = copy_to_mode_reg (mode2, op0);
10227 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
10228 op1 = copy_to_mode_reg (mode0, op1);
10229 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
10230 op2 = copy_to_mode_reg (mode1, op2);
10232 pat = GEN_FCN (icode) (op1, op2, op0);
10233 if (pat)
10234 emit_insn (pat);
10235 return NULL_RTX;
10238 static rtx
10239 paired_expand_stv_builtin (enum insn_code icode, tree exp)
10241 tree arg0 = CALL_EXPR_ARG (exp, 0);
10242 tree arg1 = CALL_EXPR_ARG (exp, 1);
10243 tree arg2 = CALL_EXPR_ARG (exp, 2);
10244 rtx op0 = expand_normal (arg0);
10245 rtx op1 = expand_normal (arg1);
10246 rtx op2 = expand_normal (arg2);
10247 rtx pat, addr;
10248 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10249 enum machine_mode mode1 = Pmode;
10250 enum machine_mode mode2 = Pmode;
10252 /* Invalid arguments. Bail before doing anything stoopid! */
10253 if (arg0 == error_mark_node
10254 || arg1 == error_mark_node
10255 || arg2 == error_mark_node)
10256 return const0_rtx;
10258 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10259 op0 = copy_to_mode_reg (tmode, op0);
10261 op2 = copy_to_mode_reg (mode2, op2);
10263 if (op1 == const0_rtx)
10265 addr = gen_rtx_MEM (tmode, op2);
10267 else
10269 op1 = copy_to_mode_reg (mode1, op1);
10270 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10273 pat = GEN_FCN (icode) (addr, op0);
10274 if (pat)
10275 emit_insn (pat);
10276 return NULL_RTX;
10279 static rtx
10280 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10282 tree arg0 = CALL_EXPR_ARG (exp, 0);
10283 tree arg1 = CALL_EXPR_ARG (exp, 1);
10284 tree arg2 = CALL_EXPR_ARG (exp, 2);
10285 rtx op0 = expand_normal (arg0);
10286 rtx op1 = expand_normal (arg1);
10287 rtx op2 = expand_normal (arg2);
10288 rtx pat, addr;
10289 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10290 enum machine_mode smode = insn_data[icode].operand[1].mode;
10291 enum machine_mode mode1 = Pmode;
10292 enum machine_mode mode2 = Pmode;
10294 /* Invalid arguments. Bail before doing anything stoopid! */
10295 if (arg0 == error_mark_node
10296 || arg1 == error_mark_node
10297 || arg2 == error_mark_node)
10298 return const0_rtx;
10300 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10301 op0 = copy_to_mode_reg (smode, op0);
10303 op2 = copy_to_mode_reg (mode2, op2);
10305 if (op1 == const0_rtx)
10307 addr = gen_rtx_MEM (tmode, op2);
10309 else
10311 op1 = copy_to_mode_reg (mode1, op1);
10312 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10315 pat = GEN_FCN (icode) (addr, op0);
10316 if (pat)
10317 emit_insn (pat);
10318 return NULL_RTX;
10321 static rtx
10322 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10324 rtx pat;
10325 tree arg0 = CALL_EXPR_ARG (exp, 0);
10326 tree arg1 = CALL_EXPR_ARG (exp, 1);
10327 tree arg2 = CALL_EXPR_ARG (exp, 2);
10328 rtx op0 = expand_normal (arg0);
10329 rtx op1 = expand_normal (arg1);
10330 rtx op2 = expand_normal (arg2);
10331 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10332 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10333 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10334 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10336 if (icode == CODE_FOR_nothing)
10337 /* Builtin not supported on this processor. */
10338 return 0;
10340 /* If we got invalid arguments bail out before generating bad rtl. */
10341 if (arg0 == error_mark_node
10342 || arg1 == error_mark_node
10343 || arg2 == error_mark_node)
10344 return const0_rtx;
10346 /* Check and prepare argument depending on the instruction code.
10348 Note that a switch statement instead of the sequence of tests
10349 would be incorrect as many of the CODE_FOR values could be
10350 CODE_FOR_nothing and that would yield multiple alternatives
10351 with identical values. We'd never reach here at runtime in
10352 this case. */
10353 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10354 || icode == CODE_FOR_altivec_vsldoi_v4si
10355 || icode == CODE_FOR_altivec_vsldoi_v8hi
10356 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10358 /* Only allow 4-bit unsigned literals. */
10359 STRIP_NOPS (arg2);
10360 if (TREE_CODE (arg2) != INTEGER_CST
10361 || TREE_INT_CST_LOW (arg2) & ~0xf)
10363 error ("argument 3 must be a 4-bit unsigned literal");
10364 return const0_rtx;
10367 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10368 || icode == CODE_FOR_vsx_xxpermdi_v2di
10369 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10370 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10371 || icode == CODE_FOR_vsx_xxsldwi_v4si
10372 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10373 || icode == CODE_FOR_vsx_xxsldwi_v2di
10374 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10376 /* Only allow 2-bit unsigned literals. */
10377 STRIP_NOPS (arg2);
10378 if (TREE_CODE (arg2) != INTEGER_CST
10379 || TREE_INT_CST_LOW (arg2) & ~0x3)
10381 error ("argument 3 must be a 2-bit unsigned literal");
10382 return const0_rtx;
10385 else if (icode == CODE_FOR_vsx_set_v2df
10386 || icode == CODE_FOR_vsx_set_v2di)
10388 /* Only allow 1-bit unsigned literals. */
10389 STRIP_NOPS (arg2);
10390 if (TREE_CODE (arg2) != INTEGER_CST
10391 || TREE_INT_CST_LOW (arg2) & ~0x1)
10393 error ("argument 3 must be a 1-bit unsigned literal");
10394 return const0_rtx;
10398 if (target == 0
10399 || GET_MODE (target) != tmode
10400 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10401 target = gen_reg_rtx (tmode);
10403 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10404 op0 = copy_to_mode_reg (mode0, op0);
10405 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10406 op1 = copy_to_mode_reg (mode1, op1);
10407 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10408 op2 = copy_to_mode_reg (mode2, op2);
10410 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10411 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10412 else
10413 pat = GEN_FCN (icode) (target, op0, op1, op2);
10414 if (! pat)
10415 return 0;
10416 emit_insn (pat);
10418 return target;
10421 /* Expand the lvx builtins. */
10422 static rtx
10423 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10425 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10426 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10427 tree arg0;
10428 enum machine_mode tmode, mode0;
10429 rtx pat, op0;
10430 enum insn_code icode;
10432 switch (fcode)
10434 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10435 icode = CODE_FOR_vector_altivec_load_v16qi;
10436 break;
10437 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10438 icode = CODE_FOR_vector_altivec_load_v8hi;
10439 break;
10440 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10441 icode = CODE_FOR_vector_altivec_load_v4si;
10442 break;
10443 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10444 icode = CODE_FOR_vector_altivec_load_v4sf;
10445 break;
10446 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10447 icode = CODE_FOR_vector_altivec_load_v2df;
10448 break;
10449 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10450 icode = CODE_FOR_vector_altivec_load_v2di;
10451 break;
10452 default:
10453 *expandedp = false;
10454 return NULL_RTX;
10457 *expandedp = true;
10459 arg0 = CALL_EXPR_ARG (exp, 0);
10460 op0 = expand_normal (arg0);
10461 tmode = insn_data[icode].operand[0].mode;
10462 mode0 = insn_data[icode].operand[1].mode;
10464 if (target == 0
10465 || GET_MODE (target) != tmode
10466 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10467 target = gen_reg_rtx (tmode);
10469 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10470 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10472 pat = GEN_FCN (icode) (target, op0);
10473 if (! pat)
10474 return 0;
10475 emit_insn (pat);
10476 return target;
10479 /* Expand the stvx builtins. */
10480 static rtx
10481 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10482 bool *expandedp)
10484 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10485 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10486 tree arg0, arg1;
10487 enum machine_mode mode0, mode1;
10488 rtx pat, op0, op1;
10489 enum insn_code icode;
10491 switch (fcode)
10493 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10494 icode = CODE_FOR_vector_altivec_store_v16qi;
10495 break;
10496 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10497 icode = CODE_FOR_vector_altivec_store_v8hi;
10498 break;
10499 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10500 icode = CODE_FOR_vector_altivec_store_v4si;
10501 break;
10502 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10503 icode = CODE_FOR_vector_altivec_store_v4sf;
10504 break;
10505 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10506 icode = CODE_FOR_vector_altivec_store_v2df;
10507 break;
10508 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10509 icode = CODE_FOR_vector_altivec_store_v2di;
10510 break;
10511 default:
10512 *expandedp = false;
10513 return NULL_RTX;
10516 arg0 = CALL_EXPR_ARG (exp, 0);
10517 arg1 = CALL_EXPR_ARG (exp, 1);
10518 op0 = expand_normal (arg0);
10519 op1 = expand_normal (arg1);
10520 mode0 = insn_data[icode].operand[0].mode;
10521 mode1 = insn_data[icode].operand[1].mode;
10523 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10524 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10525 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10526 op1 = copy_to_mode_reg (mode1, op1);
10528 pat = GEN_FCN (icode) (op0, op1);
10529 if (pat)
10530 emit_insn (pat);
10532 *expandedp = true;
10533 return NULL_RTX;
10536 /* Expand the dst builtins. */
10537 static rtx
10538 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10539 bool *expandedp)
10541 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10542 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10543 tree arg0, arg1, arg2;
10544 enum machine_mode mode0, mode1;
10545 rtx pat, op0, op1, op2;
10546 const struct builtin_description *d;
10547 size_t i;
10549 *expandedp = false;
10551 /* Handle DST variants. */
10552 d = bdesc_dst;
10553 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10554 if (d->code == fcode)
10556 arg0 = CALL_EXPR_ARG (exp, 0);
10557 arg1 = CALL_EXPR_ARG (exp, 1);
10558 arg2 = CALL_EXPR_ARG (exp, 2);
10559 op0 = expand_normal (arg0);
10560 op1 = expand_normal (arg1);
10561 op2 = expand_normal (arg2);
10562 mode0 = insn_data[d->icode].operand[0].mode;
10563 mode1 = insn_data[d->icode].operand[1].mode;
10565 /* Invalid arguments, bail out before generating bad rtl. */
10566 if (arg0 == error_mark_node
10567 || arg1 == error_mark_node
10568 || arg2 == error_mark_node)
10569 return const0_rtx;
10571 *expandedp = true;
10572 STRIP_NOPS (arg2);
10573 if (TREE_CODE (arg2) != INTEGER_CST
10574 || TREE_INT_CST_LOW (arg2) & ~0x3)
10576 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10577 return const0_rtx;
10580 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10581 op0 = copy_to_mode_reg (Pmode, op0);
10582 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10583 op1 = copy_to_mode_reg (mode1, op1);
10585 pat = GEN_FCN (d->icode) (op0, op1, op2);
10586 if (pat != 0)
10587 emit_insn (pat);
10589 return NULL_RTX;
10592 return NULL_RTX;
10595 /* Expand vec_init builtin. */
10596 static rtx
10597 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10599 enum machine_mode tmode = TYPE_MODE (type);
10600 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10601 int i, n_elt = GET_MODE_NUNITS (tmode);
10602 rtvec v = rtvec_alloc (n_elt);
10604 gcc_assert (VECTOR_MODE_P (tmode));
10605 gcc_assert (n_elt == call_expr_nargs (exp));
10607 for (i = 0; i < n_elt; ++i)
10609 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10610 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10613 if (!target || !register_operand (target, tmode))
10614 target = gen_reg_rtx (tmode);
10616 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10617 return target;
10620 /* Return the integer constant in ARG. Constrain it to be in the range
10621 of the subparts of VEC_TYPE; issue an error if not. */
10623 static int
10624 get_element_number (tree vec_type, tree arg)
10626 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10628 if (!host_integerp (arg, 1)
10629 || (elt = tree_low_cst (arg, 1), elt > max))
10631 error ("selector must be an integer constant in the range 0..%wi", max);
10632 return 0;
10635 return elt;
10638 /* Expand vec_set builtin. */
10639 static rtx
10640 altivec_expand_vec_set_builtin (tree exp)
10642 enum machine_mode tmode, mode1;
10643 tree arg0, arg1, arg2;
10644 int elt;
10645 rtx op0, op1;
10647 arg0 = CALL_EXPR_ARG (exp, 0);
10648 arg1 = CALL_EXPR_ARG (exp, 1);
10649 arg2 = CALL_EXPR_ARG (exp, 2);
10651 tmode = TYPE_MODE (TREE_TYPE (arg0));
10652 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10653 gcc_assert (VECTOR_MODE_P (tmode));
10655 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10656 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10657 elt = get_element_number (TREE_TYPE (arg0), arg2);
10659 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10660 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10662 op0 = force_reg (tmode, op0);
10663 op1 = force_reg (mode1, op1);
10665 rs6000_expand_vector_set (op0, op1, elt);
10667 return op0;
10670 /* Expand vec_ext builtin. */
10671 static rtx
10672 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10674 enum machine_mode tmode, mode0;
10675 tree arg0, arg1;
10676 int elt;
10677 rtx op0;
10679 arg0 = CALL_EXPR_ARG (exp, 0);
10680 arg1 = CALL_EXPR_ARG (exp, 1);
10682 op0 = expand_normal (arg0);
10683 elt = get_element_number (TREE_TYPE (arg0), arg1);
10685 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10686 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10687 gcc_assert (VECTOR_MODE_P (mode0));
10689 op0 = force_reg (mode0, op0);
10691 if (optimize || !target || !register_operand (target, tmode))
10692 target = gen_reg_rtx (tmode);
10694 rs6000_expand_vector_extract (target, op0, elt);
10696 return target;
10699 /* Expand the builtin in EXP and store the result in TARGET. Store
10700 true in *EXPANDEDP if we found a builtin to expand. */
10701 static rtx
10702 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10704 const struct builtin_description *d;
10705 size_t i;
10706 enum insn_code icode;
10707 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10708 tree arg0;
10709 rtx op0, pat;
10710 enum machine_mode tmode, mode0;
10711 enum rs6000_builtins fcode
10712 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10714 if (rs6000_overloaded_builtin_p (fcode))
10716 *expandedp = true;
10717 error ("unresolved overload for Altivec builtin %qF", fndecl);
10719 /* Given it is invalid, just generate a normal call. */
10720 return expand_call (exp, target, false);
10723 target = altivec_expand_ld_builtin (exp, target, expandedp);
10724 if (*expandedp)
10725 return target;
10727 target = altivec_expand_st_builtin (exp, target, expandedp);
10728 if (*expandedp)
10729 return target;
10731 target = altivec_expand_dst_builtin (exp, target, expandedp);
10732 if (*expandedp)
10733 return target;
10735 *expandedp = true;
10737 switch (fcode)
10739 case ALTIVEC_BUILTIN_STVX:
10740 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10741 case ALTIVEC_BUILTIN_STVEBX:
10742 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10743 case ALTIVEC_BUILTIN_STVEHX:
10744 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10745 case ALTIVEC_BUILTIN_STVEWX:
10746 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10747 case ALTIVEC_BUILTIN_STVXL:
10748 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10750 case ALTIVEC_BUILTIN_STVLX:
10751 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10752 case ALTIVEC_BUILTIN_STVLXL:
10753 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10754 case ALTIVEC_BUILTIN_STVRX:
10755 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10756 case ALTIVEC_BUILTIN_STVRXL:
10757 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10759 case VSX_BUILTIN_STXVD2X_V2DF:
10760 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10761 case VSX_BUILTIN_STXVD2X_V2DI:
10762 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10763 case VSX_BUILTIN_STXVW4X_V4SF:
10764 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10765 case VSX_BUILTIN_STXVW4X_V4SI:
10766 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10767 case VSX_BUILTIN_STXVW4X_V8HI:
10768 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10769 case VSX_BUILTIN_STXVW4X_V16QI:
10770 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10772 case ALTIVEC_BUILTIN_MFVSCR:
10773 icode = CODE_FOR_altivec_mfvscr;
10774 tmode = insn_data[icode].operand[0].mode;
10776 if (target == 0
10777 || GET_MODE (target) != tmode
10778 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10779 target = gen_reg_rtx (tmode);
10781 pat = GEN_FCN (icode) (target);
10782 if (! pat)
10783 return 0;
10784 emit_insn (pat);
10785 return target;
10787 case ALTIVEC_BUILTIN_MTVSCR:
10788 icode = CODE_FOR_altivec_mtvscr;
10789 arg0 = CALL_EXPR_ARG (exp, 0);
10790 op0 = expand_normal (arg0);
10791 mode0 = insn_data[icode].operand[0].mode;
10793 /* If we got invalid arguments bail out before generating bad rtl. */
10794 if (arg0 == error_mark_node)
10795 return const0_rtx;
10797 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10798 op0 = copy_to_mode_reg (mode0, op0);
10800 pat = GEN_FCN (icode) (op0);
10801 if (pat)
10802 emit_insn (pat);
10803 return NULL_RTX;
10805 case ALTIVEC_BUILTIN_DSSALL:
10806 emit_insn (gen_altivec_dssall ());
10807 return NULL_RTX;
10809 case ALTIVEC_BUILTIN_DSS:
10810 icode = CODE_FOR_altivec_dss;
10811 arg0 = CALL_EXPR_ARG (exp, 0);
10812 STRIP_NOPS (arg0);
10813 op0 = expand_normal (arg0);
10814 mode0 = insn_data[icode].operand[0].mode;
10816 /* If we got invalid arguments bail out before generating bad rtl. */
10817 if (arg0 == error_mark_node)
10818 return const0_rtx;
10820 if (TREE_CODE (arg0) != INTEGER_CST
10821 || TREE_INT_CST_LOW (arg0) & ~0x3)
10823 error ("argument to dss must be a 2-bit unsigned literal");
10824 return const0_rtx;
10827 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10828 op0 = copy_to_mode_reg (mode0, op0);
10830 emit_insn (gen_altivec_dss (op0));
10831 return NULL_RTX;
10833 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10834 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10835 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10836 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10837 case VSX_BUILTIN_VEC_INIT_V2DF:
10838 case VSX_BUILTIN_VEC_INIT_V2DI:
10839 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10841 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10842 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10843 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10844 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10845 case VSX_BUILTIN_VEC_SET_V2DF:
10846 case VSX_BUILTIN_VEC_SET_V2DI:
10847 return altivec_expand_vec_set_builtin (exp);
10849 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10850 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10851 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10852 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10853 case VSX_BUILTIN_VEC_EXT_V2DF:
10854 case VSX_BUILTIN_VEC_EXT_V2DI:
10855 return altivec_expand_vec_ext_builtin (exp, target);
10857 default:
10858 break;
10859 /* Fall through. */
10862 /* Expand abs* operations. */
10863 d = bdesc_abs;
10864 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10865 if (d->code == fcode)
10866 return altivec_expand_abs_builtin (d->icode, exp, target);
10868 /* Expand the AltiVec predicates. */
10869 d = bdesc_altivec_preds;
10870 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10871 if (d->code == fcode)
10872 return altivec_expand_predicate_builtin (d->icode, exp, target);
10874 /* LV* are funky. We initialized them differently. */
10875 switch (fcode)
10877 case ALTIVEC_BUILTIN_LVSL:
10878 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10879 exp, target, false);
10880 case ALTIVEC_BUILTIN_LVSR:
10881 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10882 exp, target, false);
10883 case ALTIVEC_BUILTIN_LVEBX:
10884 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10885 exp, target, false);
10886 case ALTIVEC_BUILTIN_LVEHX:
10887 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10888 exp, target, false);
10889 case ALTIVEC_BUILTIN_LVEWX:
10890 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10891 exp, target, false);
10892 case ALTIVEC_BUILTIN_LVXL:
10893 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10894 exp, target, false);
10895 case ALTIVEC_BUILTIN_LVX:
10896 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10897 exp, target, false);
10898 case ALTIVEC_BUILTIN_LVLX:
10899 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10900 exp, target, true);
10901 case ALTIVEC_BUILTIN_LVLXL:
10902 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10903 exp, target, true);
10904 case ALTIVEC_BUILTIN_LVRX:
10905 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10906 exp, target, true);
10907 case ALTIVEC_BUILTIN_LVRXL:
10908 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10909 exp, target, true);
10910 case VSX_BUILTIN_LXVD2X_V2DF:
10911 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10912 exp, target, false);
10913 case VSX_BUILTIN_LXVD2X_V2DI:
10914 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10915 exp, target, false);
10916 case VSX_BUILTIN_LXVW4X_V4SF:
10917 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10918 exp, target, false);
10919 case VSX_BUILTIN_LXVW4X_V4SI:
10920 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10921 exp, target, false);
10922 case VSX_BUILTIN_LXVW4X_V8HI:
10923 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10924 exp, target, false);
10925 case VSX_BUILTIN_LXVW4X_V16QI:
10926 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10927 exp, target, false);
10928 break;
10929 default:
10930 break;
10931 /* Fall through. */
10934 *expandedp = false;
10935 return NULL_RTX;
10938 /* Expand the builtin in EXP and store the result in TARGET. Store
10939 true in *EXPANDEDP if we found a builtin to expand. */
10940 static rtx
10941 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10943 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10944 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10945 const struct builtin_description *d;
10946 size_t i;
10948 *expandedp = true;
10950 switch (fcode)
10952 case PAIRED_BUILTIN_STX:
10953 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10954 case PAIRED_BUILTIN_LX:
10955 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10956 default:
10957 break;
10958 /* Fall through. */
10961 /* Expand the paired predicates. */
10962 d = bdesc_paired_preds;
10963 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10964 if (d->code == fcode)
10965 return paired_expand_predicate_builtin (d->icode, exp, target);
10967 *expandedp = false;
10968 return NULL_RTX;
10971 /* Binops that need to be initialized manually, but can be expanded
10972 automagically by rs6000_expand_binop_builtin. */
10973 static const struct builtin_description bdesc_2arg_spe[] =
10975 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
10976 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
10977 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
10978 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
10979 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
10980 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
10981 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
10982 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
10983 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
10984 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
10985 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
10986 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
10987 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
10988 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
10989 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
10990 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
10991 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
10992 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
10993 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
10994 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
10995 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
10996 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
10999 /* Expand the builtin in EXP and store the result in TARGET. Store
11000 true in *EXPANDEDP if we found a builtin to expand.
11002 This expands the SPE builtins that are not simple unary and binary
11003 operations. */
11004 static rtx
11005 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
11007 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11008 tree arg1, arg0;
11009 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
11010 enum insn_code icode;
11011 enum machine_mode tmode, mode0;
11012 rtx pat, op0;
11013 const struct builtin_description *d;
11014 size_t i;
11016 *expandedp = true;
11018 /* Syntax check for a 5-bit unsigned immediate. */
11019 switch (fcode)
11021 case SPE_BUILTIN_EVSTDD:
11022 case SPE_BUILTIN_EVSTDH:
11023 case SPE_BUILTIN_EVSTDW:
11024 case SPE_BUILTIN_EVSTWHE:
11025 case SPE_BUILTIN_EVSTWHO:
11026 case SPE_BUILTIN_EVSTWWE:
11027 case SPE_BUILTIN_EVSTWWO:
11028 arg1 = CALL_EXPR_ARG (exp, 2);
11029 if (TREE_CODE (arg1) != INTEGER_CST
11030 || TREE_INT_CST_LOW (arg1) & ~0x1f)
11032 error ("argument 2 must be a 5-bit unsigned literal");
11033 return const0_rtx;
11035 break;
11036 default:
11037 break;
11040 /* The evsplat*i instructions are not quite generic. */
11041 switch (fcode)
11043 case SPE_BUILTIN_EVSPLATFI:
11044 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
11045 exp, target);
11046 case SPE_BUILTIN_EVSPLATI:
11047 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
11048 exp, target);
11049 default:
11050 break;
11053 d = bdesc_2arg_spe;
11054 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
11055 if (d->code == fcode)
11056 return rs6000_expand_binop_builtin (d->icode, exp, target);
11058 d = bdesc_spe_predicates;
11059 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
11060 if (d->code == fcode)
11061 return spe_expand_predicate_builtin (d->icode, exp, target);
11063 d = bdesc_spe_evsel;
11064 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
11065 if (d->code == fcode)
11066 return spe_expand_evsel_builtin (d->icode, exp, target);
11068 switch (fcode)
11070 case SPE_BUILTIN_EVSTDDX:
11071 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
11072 case SPE_BUILTIN_EVSTDHX:
11073 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
11074 case SPE_BUILTIN_EVSTDWX:
11075 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
11076 case SPE_BUILTIN_EVSTWHEX:
11077 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
11078 case SPE_BUILTIN_EVSTWHOX:
11079 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
11080 case SPE_BUILTIN_EVSTWWEX:
11081 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
11082 case SPE_BUILTIN_EVSTWWOX:
11083 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
11084 case SPE_BUILTIN_EVSTDD:
11085 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
11086 case SPE_BUILTIN_EVSTDH:
11087 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
11088 case SPE_BUILTIN_EVSTDW:
11089 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
11090 case SPE_BUILTIN_EVSTWHE:
11091 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
11092 case SPE_BUILTIN_EVSTWHO:
11093 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
11094 case SPE_BUILTIN_EVSTWWE:
11095 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
11096 case SPE_BUILTIN_EVSTWWO:
11097 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
11098 case SPE_BUILTIN_MFSPEFSCR:
11099 icode = CODE_FOR_spe_mfspefscr;
11100 tmode = insn_data[icode].operand[0].mode;
11102 if (target == 0
11103 || GET_MODE (target) != tmode
11104 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11105 target = gen_reg_rtx (tmode);
11107 pat = GEN_FCN (icode) (target);
11108 if (! pat)
11109 return 0;
11110 emit_insn (pat);
11111 return target;
11112 case SPE_BUILTIN_MTSPEFSCR:
11113 icode = CODE_FOR_spe_mtspefscr;
11114 arg0 = CALL_EXPR_ARG (exp, 0);
11115 op0 = expand_normal (arg0);
11116 mode0 = insn_data[icode].operand[0].mode;
11118 if (arg0 == error_mark_node)
11119 return const0_rtx;
11121 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11122 op0 = copy_to_mode_reg (mode0, op0);
11124 pat = GEN_FCN (icode) (op0);
11125 if (pat)
11126 emit_insn (pat);
11127 return NULL_RTX;
11128 default:
11129 break;
11132 *expandedp = false;
11133 return NULL_RTX;
11136 static rtx
11137 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11139 rtx pat, scratch, tmp;
11140 tree form = CALL_EXPR_ARG (exp, 0);
11141 tree arg0 = CALL_EXPR_ARG (exp, 1);
11142 tree arg1 = CALL_EXPR_ARG (exp, 2);
11143 rtx op0 = expand_normal (arg0);
11144 rtx op1 = expand_normal (arg1);
11145 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11146 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11147 int form_int;
11148 enum rtx_code code;
11150 if (TREE_CODE (form) != INTEGER_CST)
11152 error ("argument 1 of __builtin_paired_predicate must be a constant");
11153 return const0_rtx;
11155 else
11156 form_int = TREE_INT_CST_LOW (form);
11158 gcc_assert (mode0 == mode1);
11160 if (arg0 == error_mark_node || arg1 == error_mark_node)
11161 return const0_rtx;
11163 if (target == 0
11164 || GET_MODE (target) != SImode
11165 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
11166 target = gen_reg_rtx (SImode);
11167 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
11168 op0 = copy_to_mode_reg (mode0, op0);
11169 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
11170 op1 = copy_to_mode_reg (mode1, op1);
11172 scratch = gen_reg_rtx (CCFPmode);
11174 pat = GEN_FCN (icode) (scratch, op0, op1);
11175 if (!pat)
11176 return const0_rtx;
11178 emit_insn (pat);
11180 switch (form_int)
11182 /* LT bit. */
11183 case 0:
11184 code = LT;
11185 break;
11186 /* GT bit. */
11187 case 1:
11188 code = GT;
11189 break;
11190 /* EQ bit. */
11191 case 2:
11192 code = EQ;
11193 break;
11194 /* UN bit. */
11195 case 3:
11196 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11197 return target;
11198 default:
11199 error ("argument 1 of __builtin_paired_predicate is out of range");
11200 return const0_rtx;
11203 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11204 emit_move_insn (target, tmp);
11205 return target;
11208 static rtx
11209 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11211 rtx pat, scratch, tmp;
11212 tree form = CALL_EXPR_ARG (exp, 0);
11213 tree arg0 = CALL_EXPR_ARG (exp, 1);
11214 tree arg1 = CALL_EXPR_ARG (exp, 2);
11215 rtx op0 = expand_normal (arg0);
11216 rtx op1 = expand_normal (arg1);
11217 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11218 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11219 int form_int;
11220 enum rtx_code code;
11222 if (TREE_CODE (form) != INTEGER_CST)
11224 error ("argument 1 of __builtin_spe_predicate must be a constant");
11225 return const0_rtx;
11227 else
11228 form_int = TREE_INT_CST_LOW (form);
11230 gcc_assert (mode0 == mode1);
11232 if (arg0 == error_mark_node || arg1 == error_mark_node)
11233 return const0_rtx;
11235 if (target == 0
11236 || GET_MODE (target) != SImode
11237 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
11238 target = gen_reg_rtx (SImode);
11240 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11241 op0 = copy_to_mode_reg (mode0, op0);
11242 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11243 op1 = copy_to_mode_reg (mode1, op1);
11245 scratch = gen_reg_rtx (CCmode);
11247 pat = GEN_FCN (icode) (scratch, op0, op1);
11248 if (! pat)
11249 return const0_rtx;
11250 emit_insn (pat);
11252 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11253 _lower_. We use one compare, but look in different bits of the
11254 CR for each variant.
11256 There are 2 elements in each SPE simd type (upper/lower). The CR
11257 bits are set as follows:
11259 BIT0 | BIT 1 | BIT 2 | BIT 3
11260 U | L | (U | L) | (U & L)
11262 So, for an "all" relationship, BIT 3 would be set.
11263 For an "any" relationship, BIT 2 would be set. Etc.
11265 Following traditional nomenclature, these bits map to:
11267 BIT0 | BIT 1 | BIT 2 | BIT 3
11268 LT | GT | EQ | OV
11270 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11273 switch (form_int)
11275 /* All variant. OV bit. */
11276 case 0:
11277 /* We need to get to the OV bit, which is the ORDERED bit. We
11278 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11279 that's ugly and will make validate_condition_mode die.
11280 So let's just use another pattern. */
11281 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11282 return target;
11283 /* Any variant. EQ bit. */
11284 case 1:
11285 code = EQ;
11286 break;
11287 /* Upper variant. LT bit. */
11288 case 2:
11289 code = LT;
11290 break;
11291 /* Lower variant. GT bit. */
11292 case 3:
11293 code = GT;
11294 break;
11295 default:
11296 error ("argument 1 of __builtin_spe_predicate is out of range");
11297 return const0_rtx;
11300 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11301 emit_move_insn (target, tmp);
11303 return target;
11306 /* The evsel builtins look like this:
11308 e = __builtin_spe_evsel_OP (a, b, c, d);
11310 and work like this:
11312 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11313 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11316 static rtx
11317 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11319 rtx pat, scratch;
11320 tree arg0 = CALL_EXPR_ARG (exp, 0);
11321 tree arg1 = CALL_EXPR_ARG (exp, 1);
11322 tree arg2 = CALL_EXPR_ARG (exp, 2);
11323 tree arg3 = CALL_EXPR_ARG (exp, 3);
11324 rtx op0 = expand_normal (arg0);
11325 rtx op1 = expand_normal (arg1);
11326 rtx op2 = expand_normal (arg2);
11327 rtx op3 = expand_normal (arg3);
11328 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11329 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11331 gcc_assert (mode0 == mode1);
11333 if (arg0 == error_mark_node || arg1 == error_mark_node
11334 || arg2 == error_mark_node || arg3 == error_mark_node)
11335 return const0_rtx;
11337 if (target == 0
11338 || GET_MODE (target) != mode0
11339 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11340 target = gen_reg_rtx (mode0);
11342 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11343 op0 = copy_to_mode_reg (mode0, op0);
11344 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11345 op1 = copy_to_mode_reg (mode0, op1);
11346 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11347 op2 = copy_to_mode_reg (mode0, op2);
11348 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11349 op3 = copy_to_mode_reg (mode0, op3);
11351 /* Generate the compare. */
11352 scratch = gen_reg_rtx (CCmode);
11353 pat = GEN_FCN (icode) (scratch, op0, op1);
11354 if (! pat)
11355 return const0_rtx;
11356 emit_insn (pat);
11358 if (mode0 == V2SImode)
11359 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11360 else
11361 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11363 return target;
11366 /* Raise an error message for a builtin function that is called without the
11367 appropriate target options being set. */
11369 static void
11370 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11372 size_t uns_fncode = (size_t)fncode;
11373 const char *name = rs6000_builtin_info[uns_fncode].name;
11374 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
11376 gcc_assert (name != NULL);
11377 if ((fnmask & RS6000_BTM_CELL) != 0)
11378 error ("Builtin function %s is only valid for the cell processor", name);
11379 else if ((fnmask & RS6000_BTM_VSX) != 0)
11380 error ("Builtin function %s requires the -mvsx option", name);
11381 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11382 error ("Builtin function %s requires the -maltivec option", name);
11383 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11384 error ("Builtin function %s requires the -mpaired option", name);
11385 else if ((fnmask & RS6000_BTM_SPE) != 0)
11386 error ("Builtin function %s requires the -mspe option", name);
11387 else
11388 error ("Builtin function %s is not supported with the current options",
11389 name);
11392 /* Expand an expression EXP that calls a built-in function,
11393 with result going to TARGET if that's convenient
11394 (and in mode MODE if that's convenient).
11395 SUBTARGET may be used as the target for computing one of EXP's operands.
11396 IGNORE is nonzero if the value is to be ignored. */
11398 static rtx
11399 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11400 enum machine_mode mode ATTRIBUTE_UNUSED,
11401 int ignore ATTRIBUTE_UNUSED)
11403 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11404 enum rs6000_builtins fcode
11405 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11406 size_t uns_fcode = (size_t)fcode;
11407 const struct builtin_description *d;
11408 size_t i;
11409 rtx ret;
11410 bool success;
11411 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
11412 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11414 if (TARGET_DEBUG_BUILTIN)
11416 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11417 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11418 const char *name2 = ((icode != CODE_FOR_nothing)
11419 ? get_insn_name ((int)icode)
11420 : "nothing");
11421 const char *name3;
11423 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11425 default: name3 = "unknown"; break;
11426 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11427 case RS6000_BTC_UNARY: name3 = "unary"; break;
11428 case RS6000_BTC_BINARY: name3 = "binary"; break;
11429 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11430 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11431 case RS6000_BTC_ABS: name3 = "abs"; break;
11432 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
11433 case RS6000_BTC_DST: name3 = "dst"; break;
11437 fprintf (stderr,
11438 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11439 (name1) ? name1 : "---", fcode,
11440 (name2) ? name2 : "---", (int)icode,
11441 name3,
11442 func_valid_p ? "" : ", not valid");
11445 if (!func_valid_p)
11447 rs6000_invalid_builtin (fcode);
11449 /* Given it is invalid, just generate a normal call. */
11450 return expand_call (exp, target, ignore);
11453 switch (fcode)
11455 case RS6000_BUILTIN_RECIP:
11456 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11458 case RS6000_BUILTIN_RECIPF:
11459 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11461 case RS6000_BUILTIN_RSQRTF:
11462 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11464 case RS6000_BUILTIN_RSQRT:
11465 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11467 case POWER7_BUILTIN_BPERMD:
11468 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11469 ? CODE_FOR_bpermd_di
11470 : CODE_FOR_bpermd_si), exp, target);
11472 case RS6000_BUILTIN_GET_TB:
11473 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
11474 target);
11476 case RS6000_BUILTIN_MFTB:
11477 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
11478 ? CODE_FOR_rs6000_mftb_di
11479 : CODE_FOR_rs6000_mftb_si),
11480 target);
11482 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11483 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11485 int icode = (int) CODE_FOR_altivec_lvsr;
11486 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11487 enum machine_mode mode = insn_data[icode].operand[1].mode;
11488 tree arg;
11489 rtx op, addr, pat;
11491 gcc_assert (TARGET_ALTIVEC);
11493 arg = CALL_EXPR_ARG (exp, 0);
11494 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11495 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11496 addr = memory_address (mode, op);
11497 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11498 op = addr;
11499 else
11501 /* For the load case need to negate the address. */
11502 op = gen_reg_rtx (GET_MODE (addr));
11503 emit_insn (gen_rtx_SET (VOIDmode, op,
11504 gen_rtx_NEG (GET_MODE (addr), addr)));
11506 op = gen_rtx_MEM (mode, op);
11508 if (target == 0
11509 || GET_MODE (target) != tmode
11510 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11511 target = gen_reg_rtx (tmode);
11513 /*pat = gen_altivec_lvsr (target, op);*/
11514 pat = GEN_FCN (icode) (target, op);
11515 if (!pat)
11516 return 0;
11517 emit_insn (pat);
11519 return target;
11522 case ALTIVEC_BUILTIN_VCFUX:
11523 case ALTIVEC_BUILTIN_VCFSX:
11524 case ALTIVEC_BUILTIN_VCTUXS:
11525 case ALTIVEC_BUILTIN_VCTSXS:
11526 /* FIXME: There's got to be a nicer way to handle this case than
11527 constructing a new CALL_EXPR. */
11528 if (call_expr_nargs (exp) == 1)
11530 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11531 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11533 break;
11535 default:
11536 break;
11539 if (TARGET_ALTIVEC)
11541 ret = altivec_expand_builtin (exp, target, &success);
11543 if (success)
11544 return ret;
11546 if (TARGET_SPE)
11548 ret = spe_expand_builtin (exp, target, &success);
11550 if (success)
11551 return ret;
11553 if (TARGET_PAIRED_FLOAT)
11555 ret = paired_expand_builtin (exp, target, &success);
11557 if (success)
11558 return ret;
11561 gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11563 /* Handle simple unary operations. */
11564 d = bdesc_1arg;
11565 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11566 if (d->code == fcode)
11567 return rs6000_expand_unop_builtin (d->icode, exp, target);
11569 /* Handle simple binary operations. */
11570 d = bdesc_2arg;
11571 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11572 if (d->code == fcode)
11573 return rs6000_expand_binop_builtin (d->icode, exp, target);
11575 /* Handle simple ternary operations. */
11576 d = bdesc_3arg;
11577 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11578 if (d->code == fcode)
11579 return rs6000_expand_ternop_builtin (d->icode, exp, target);
11581 gcc_unreachable ();
11584 static void
11585 rs6000_init_builtins (void)
11587 tree tdecl;
11588 tree ftype;
11589 enum machine_mode mode;
11591 if (TARGET_DEBUG_BUILTIN)
11592 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11593 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
11594 (TARGET_SPE) ? ", spe" : "",
11595 (TARGET_ALTIVEC) ? ", altivec" : "",
11596 (TARGET_VSX) ? ", vsx" : "");
11598 V2SI_type_node = build_vector_type (intSI_type_node, 2);
11599 V2SF_type_node = build_vector_type (float_type_node, 2);
11600 V2DI_type_node = build_vector_type (intDI_type_node, 2);
11601 V2DF_type_node = build_vector_type (double_type_node, 2);
11602 V4HI_type_node = build_vector_type (intHI_type_node, 4);
11603 V4SI_type_node = build_vector_type (intSI_type_node, 4);
11604 V4SF_type_node = build_vector_type (float_type_node, 4);
11605 V8HI_type_node = build_vector_type (intHI_type_node, 8);
11606 V16QI_type_node = build_vector_type (intQI_type_node, 16);
11608 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11609 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11610 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11611 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11613 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11614 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11615 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11616 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11618 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11619 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11620 'vector unsigned short'. */
11622 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11623 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11624 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11625 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11626 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11628 long_integer_type_internal_node = long_integer_type_node;
11629 long_unsigned_type_internal_node = long_unsigned_type_node;
11630 long_long_integer_type_internal_node = long_long_integer_type_node;
11631 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11632 intQI_type_internal_node = intQI_type_node;
11633 uintQI_type_internal_node = unsigned_intQI_type_node;
11634 intHI_type_internal_node = intHI_type_node;
11635 uintHI_type_internal_node = unsigned_intHI_type_node;
11636 intSI_type_internal_node = intSI_type_node;
11637 uintSI_type_internal_node = unsigned_intSI_type_node;
11638 intDI_type_internal_node = intDI_type_node;
11639 uintDI_type_internal_node = unsigned_intDI_type_node;
11640 float_type_internal_node = float_type_node;
11641 double_type_internal_node = double_type_node;
11642 void_type_internal_node = void_type_node;
11644 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11645 tree type node. */
11646 builtin_mode_to_type[QImode][0] = integer_type_node;
11647 builtin_mode_to_type[HImode][0] = integer_type_node;
11648 builtin_mode_to_type[SImode][0] = intSI_type_node;
11649 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11650 builtin_mode_to_type[DImode][0] = intDI_type_node;
11651 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11652 builtin_mode_to_type[SFmode][0] = float_type_node;
11653 builtin_mode_to_type[DFmode][0] = double_type_node;
11654 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11655 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11656 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11657 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11658 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11659 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11660 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11661 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11662 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11663 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11664 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11665 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11666 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11668 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
11669 TYPE_NAME (bool_char_type_node) = tdecl;
11671 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
11672 TYPE_NAME (bool_short_type_node) = tdecl;
11674 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
11675 TYPE_NAME (bool_int_type_node) = tdecl;
11677 tdecl = add_builtin_type ("__pixel", pixel_type_node);
11678 TYPE_NAME (pixel_type_node) = tdecl;
11680 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11681 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11682 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11683 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11684 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11686 tdecl = add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node);
11687 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11689 tdecl = add_builtin_type ("__vector signed char", V16QI_type_node);
11690 TYPE_NAME (V16QI_type_node) = tdecl;
11692 tdecl = add_builtin_type ("__vector __bool char", bool_V16QI_type_node);
11693 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11695 tdecl = add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node);
11696 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11698 tdecl = add_builtin_type ("__vector signed short", V8HI_type_node);
11699 TYPE_NAME (V8HI_type_node) = tdecl;
11701 tdecl = add_builtin_type ("__vector __bool short", bool_V8HI_type_node);
11702 TYPE_NAME (bool_V8HI_type_node) = tdecl;
11704 tdecl = add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node);
11705 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11707 tdecl = add_builtin_type ("__vector signed int", V4SI_type_node);
11708 TYPE_NAME (V4SI_type_node) = tdecl;
11710 tdecl = add_builtin_type ("__vector __bool int", bool_V4SI_type_node);
11711 TYPE_NAME (bool_V4SI_type_node) = tdecl;
11713 tdecl = add_builtin_type ("__vector float", V4SF_type_node);
11714 TYPE_NAME (V4SF_type_node) = tdecl;
11716 tdecl = add_builtin_type ("__vector __pixel", pixel_V8HI_type_node);
11717 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11719 tdecl = add_builtin_type ("__vector double", V2DF_type_node);
11720 TYPE_NAME (V2DF_type_node) = tdecl;
11722 tdecl = add_builtin_type ("__vector long", V2DI_type_node);
11723 TYPE_NAME (V2DI_type_node) = tdecl;
11725 tdecl = add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node);
11726 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11728 tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
11729 TYPE_NAME (bool_V2DI_type_node) = tdecl;
11731 /* Paired and SPE builtins are only available if you build a compiler with
11732 the appropriate options, so only create those builtins with the
11733 appropriate compiler option. Create Altivec and VSX builtins on machines
11734 with at least the general purpose extensions (970 and newer) to allow the
11735 use of the target attribute. */
11736 if (TARGET_PAIRED_FLOAT)
11737 paired_init_builtins ();
11738 if (TARGET_SPE)
11739 spe_init_builtins ();
11740 if (TARGET_EXTRA_BUILTINS)
11741 altivec_init_builtins ();
11742 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11743 rs6000_common_init_builtins ();
11745 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11746 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11747 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11749 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11750 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11751 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11753 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11754 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11755 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11757 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11758 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11759 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11761 mode = (TARGET_64BIT) ? DImode : SImode;
11762 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11763 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11764 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11766 ftype = build_function_type_list (unsigned_intDI_type_node,
11767 NULL_TREE);
11768 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
11770 if (TARGET_64BIT)
11771 ftype = build_function_type_list (unsigned_intDI_type_node,
11772 NULL_TREE);
11773 else
11774 ftype = build_function_type_list (unsigned_intSI_type_node,
11775 NULL_TREE);
11776 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
11778 #if TARGET_XCOFF
11779 /* AIX libm provides clog as __clog. */
11780 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11781 set_user_assembler_name (tdecl, "__clog");
11782 #endif
11784 #ifdef SUBTARGET_INIT_BUILTINS
11785 SUBTARGET_INIT_BUILTINS;
11786 #endif
11789 /* Returns the rs6000 builtin decl for CODE. */
11791 static tree
11792 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11794 HOST_WIDE_INT fnmask;
11796 if (code >= RS6000_BUILTIN_COUNT)
11797 return error_mark_node;
11799 fnmask = rs6000_builtin_info[code].mask;
11800 if ((fnmask & rs6000_builtin_mask) != fnmask)
11802 rs6000_invalid_builtin ((enum rs6000_builtins)code);
11803 return error_mark_node;
11806 return rs6000_builtin_decls[code];
11809 static void
11810 spe_init_builtins (void)
11812 tree puint_type_node = build_pointer_type (unsigned_type_node);
11813 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11814 const struct builtin_description *d;
11815 size_t i;
11817 tree v2si_ftype_4_v2si
11818 = build_function_type_list (opaque_V2SI_type_node,
11819 opaque_V2SI_type_node,
11820 opaque_V2SI_type_node,
11821 opaque_V2SI_type_node,
11822 opaque_V2SI_type_node,
11823 NULL_TREE);
11825 tree v2sf_ftype_4_v2sf
11826 = build_function_type_list (opaque_V2SF_type_node,
11827 opaque_V2SF_type_node,
11828 opaque_V2SF_type_node,
11829 opaque_V2SF_type_node,
11830 opaque_V2SF_type_node,
11831 NULL_TREE);
11833 tree int_ftype_int_v2si_v2si
11834 = build_function_type_list (integer_type_node,
11835 integer_type_node,
11836 opaque_V2SI_type_node,
11837 opaque_V2SI_type_node,
11838 NULL_TREE);
11840 tree int_ftype_int_v2sf_v2sf
11841 = build_function_type_list (integer_type_node,
11842 integer_type_node,
11843 opaque_V2SF_type_node,
11844 opaque_V2SF_type_node,
11845 NULL_TREE);
11847 tree void_ftype_v2si_puint_int
11848 = build_function_type_list (void_type_node,
11849 opaque_V2SI_type_node,
11850 puint_type_node,
11851 integer_type_node,
11852 NULL_TREE);
11854 tree void_ftype_v2si_puint_char
11855 = build_function_type_list (void_type_node,
11856 opaque_V2SI_type_node,
11857 puint_type_node,
11858 char_type_node,
11859 NULL_TREE);
11861 tree void_ftype_v2si_pv2si_int
11862 = build_function_type_list (void_type_node,
11863 opaque_V2SI_type_node,
11864 opaque_p_V2SI_type_node,
11865 integer_type_node,
11866 NULL_TREE);
11868 tree void_ftype_v2si_pv2si_char
11869 = build_function_type_list (void_type_node,
11870 opaque_V2SI_type_node,
11871 opaque_p_V2SI_type_node,
11872 char_type_node,
11873 NULL_TREE);
11875 tree void_ftype_int
11876 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11878 tree int_ftype_void
11879 = build_function_type_list (integer_type_node, NULL_TREE);
11881 tree v2si_ftype_pv2si_int
11882 = build_function_type_list (opaque_V2SI_type_node,
11883 opaque_p_V2SI_type_node,
11884 integer_type_node,
11885 NULL_TREE);
11887 tree v2si_ftype_puint_int
11888 = build_function_type_list (opaque_V2SI_type_node,
11889 puint_type_node,
11890 integer_type_node,
11891 NULL_TREE);
11893 tree v2si_ftype_pushort_int
11894 = build_function_type_list (opaque_V2SI_type_node,
11895 pushort_type_node,
11896 integer_type_node,
11897 NULL_TREE);
11899 tree v2si_ftype_signed_char
11900 = build_function_type_list (opaque_V2SI_type_node,
11901 signed_char_type_node,
11902 NULL_TREE);
11904 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node);
11906 /* Initialize irregular SPE builtins. */
11908 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11909 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11910 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11911 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11912 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11913 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11914 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11915 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11916 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11917 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11918 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11919 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11920 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11921 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11922 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11923 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11924 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11925 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11927 /* Loads. */
11928 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11929 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11930 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11931 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11932 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11933 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11934 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11935 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11936 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11937 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11938 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11939 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11940 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11941 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11942 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11943 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11944 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11945 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11946 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11947 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11948 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11949 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11951 /* Predicates. */
11952 d = bdesc_spe_predicates;
11953 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11955 tree type;
11957 switch (insn_data[d->icode].operand[1].mode)
11959 case V2SImode:
11960 type = int_ftype_int_v2si_v2si;
11961 break;
11962 case V2SFmode:
11963 type = int_ftype_int_v2sf_v2sf;
11964 break;
11965 default:
11966 gcc_unreachable ();
11969 def_builtin (d->name, type, d->code);
11972 /* Evsel predicates. */
11973 d = bdesc_spe_evsel;
11974 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
11976 tree type;
11978 switch (insn_data[d->icode].operand[1].mode)
11980 case V2SImode:
11981 type = v2si_ftype_4_v2si;
11982 break;
11983 case V2SFmode:
11984 type = v2sf_ftype_4_v2sf;
11985 break;
11986 default:
11987 gcc_unreachable ();
11990 def_builtin (d->name, type, d->code);
11994 static void
11995 paired_init_builtins (void)
11997 const struct builtin_description *d;
11998 size_t i;
12000 tree int_ftype_int_v2sf_v2sf
12001 = build_function_type_list (integer_type_node,
12002 integer_type_node,
12003 V2SF_type_node,
12004 V2SF_type_node,
12005 NULL_TREE);
12006 tree pcfloat_type_node =
12007 build_pointer_type (build_qualified_type
12008 (float_type_node, TYPE_QUAL_CONST));
12010 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
12011 long_integer_type_node,
12012 pcfloat_type_node,
12013 NULL_TREE);
12014 tree void_ftype_v2sf_long_pcfloat =
12015 build_function_type_list (void_type_node,
12016 V2SF_type_node,
12017 long_integer_type_node,
12018 pcfloat_type_node,
12019 NULL_TREE);
12022 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
12023 PAIRED_BUILTIN_LX);
12026 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
12027 PAIRED_BUILTIN_STX);
12029 /* Predicates. */
12030 d = bdesc_paired_preds;
12031 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
12033 tree type;
12035 if (TARGET_DEBUG_BUILTIN)
12036 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
12037 (int)i, get_insn_name (d->icode), (int)d->icode,
12038 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
12040 switch (insn_data[d->icode].operand[1].mode)
12042 case V2SFmode:
12043 type = int_ftype_int_v2sf_v2sf;
12044 break;
12045 default:
12046 gcc_unreachable ();
12049 def_builtin (d->name, type, d->code);
12053 static void
12054 altivec_init_builtins (void)
12056 const struct builtin_description *d;
12057 size_t i;
12058 tree ftype;
12059 tree decl;
12061 tree pvoid_type_node = build_pointer_type (void_type_node);
12063 tree pcvoid_type_node
12064 = build_pointer_type (build_qualified_type (void_type_node,
12065 TYPE_QUAL_CONST));
12067 tree int_ftype_opaque
12068 = build_function_type_list (integer_type_node,
12069 opaque_V4SI_type_node, NULL_TREE);
12070 tree opaque_ftype_opaque
12071 = build_function_type_list (integer_type_node, NULL_TREE);
12072 tree opaque_ftype_opaque_int
12073 = build_function_type_list (opaque_V4SI_type_node,
12074 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
12075 tree opaque_ftype_opaque_opaque_int
12076 = build_function_type_list (opaque_V4SI_type_node,
12077 opaque_V4SI_type_node, opaque_V4SI_type_node,
12078 integer_type_node, NULL_TREE);
12079 tree int_ftype_int_opaque_opaque
12080 = build_function_type_list (integer_type_node,
12081 integer_type_node, opaque_V4SI_type_node,
12082 opaque_V4SI_type_node, NULL_TREE);
12083 tree int_ftype_int_v4si_v4si
12084 = build_function_type_list (integer_type_node,
12085 integer_type_node, V4SI_type_node,
12086 V4SI_type_node, NULL_TREE);
12087 tree void_ftype_v4si
12088 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
12089 tree v8hi_ftype_void
12090 = build_function_type_list (V8HI_type_node, NULL_TREE);
12091 tree void_ftype_void
12092 = build_function_type_list (void_type_node, NULL_TREE);
12093 tree void_ftype_int
12094 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
12096 tree opaque_ftype_long_pcvoid
12097 = build_function_type_list (opaque_V4SI_type_node,
12098 long_integer_type_node, pcvoid_type_node,
12099 NULL_TREE);
12100 tree v16qi_ftype_long_pcvoid
12101 = build_function_type_list (V16QI_type_node,
12102 long_integer_type_node, pcvoid_type_node,
12103 NULL_TREE);
12104 tree v8hi_ftype_long_pcvoid
12105 = build_function_type_list (V8HI_type_node,
12106 long_integer_type_node, pcvoid_type_node,
12107 NULL_TREE);
12108 tree v4si_ftype_long_pcvoid
12109 = build_function_type_list (V4SI_type_node,
12110 long_integer_type_node, pcvoid_type_node,
12111 NULL_TREE);
12112 tree v4sf_ftype_long_pcvoid
12113 = build_function_type_list (V4SF_type_node,
12114 long_integer_type_node, pcvoid_type_node,
12115 NULL_TREE);
12116 tree v2df_ftype_long_pcvoid
12117 = build_function_type_list (V2DF_type_node,
12118 long_integer_type_node, pcvoid_type_node,
12119 NULL_TREE);
12120 tree v2di_ftype_long_pcvoid
12121 = build_function_type_list (V2DI_type_node,
12122 long_integer_type_node, pcvoid_type_node,
12123 NULL_TREE);
12125 tree void_ftype_opaque_long_pvoid
12126 = build_function_type_list (void_type_node,
12127 opaque_V4SI_type_node, long_integer_type_node,
12128 pvoid_type_node, NULL_TREE);
12129 tree void_ftype_v4si_long_pvoid
12130 = build_function_type_list (void_type_node,
12131 V4SI_type_node, long_integer_type_node,
12132 pvoid_type_node, NULL_TREE);
12133 tree void_ftype_v16qi_long_pvoid
12134 = build_function_type_list (void_type_node,
12135 V16QI_type_node, long_integer_type_node,
12136 pvoid_type_node, NULL_TREE);
12137 tree void_ftype_v8hi_long_pvoid
12138 = build_function_type_list (void_type_node,
12139 V8HI_type_node, long_integer_type_node,
12140 pvoid_type_node, NULL_TREE);
12141 tree void_ftype_v4sf_long_pvoid
12142 = build_function_type_list (void_type_node,
12143 V4SF_type_node, long_integer_type_node,
12144 pvoid_type_node, NULL_TREE);
12145 tree void_ftype_v2df_long_pvoid
12146 = build_function_type_list (void_type_node,
12147 V2DF_type_node, long_integer_type_node,
12148 pvoid_type_node, NULL_TREE);
12149 tree void_ftype_v2di_long_pvoid
12150 = build_function_type_list (void_type_node,
12151 V2DI_type_node, long_integer_type_node,
12152 pvoid_type_node, NULL_TREE);
12153 tree int_ftype_int_v8hi_v8hi
12154 = build_function_type_list (integer_type_node,
12155 integer_type_node, V8HI_type_node,
12156 V8HI_type_node, NULL_TREE);
12157 tree int_ftype_int_v16qi_v16qi
12158 = build_function_type_list (integer_type_node,
12159 integer_type_node, V16QI_type_node,
12160 V16QI_type_node, NULL_TREE);
12161 tree int_ftype_int_v4sf_v4sf
12162 = build_function_type_list (integer_type_node,
12163 integer_type_node, V4SF_type_node,
12164 V4SF_type_node, NULL_TREE);
12165 tree int_ftype_int_v2df_v2df
12166 = build_function_type_list (integer_type_node,
12167 integer_type_node, V2DF_type_node,
12168 V2DF_type_node, NULL_TREE);
12169 tree v4si_ftype_v4si
12170 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12171 tree v8hi_ftype_v8hi
12172 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12173 tree v16qi_ftype_v16qi
12174 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12175 tree v4sf_ftype_v4sf
12176 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12177 tree v2df_ftype_v2df
12178 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12179 tree void_ftype_pcvoid_int_int
12180 = build_function_type_list (void_type_node,
12181 pcvoid_type_node, integer_type_node,
12182 integer_type_node, NULL_TREE);
12184 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12185 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12186 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12187 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12188 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12189 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12190 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12191 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12192 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12193 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12194 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12195 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12196 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12197 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12198 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
12199 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
12200 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
12201 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
12202 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
12203 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
12204 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
12205 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
12206 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
12207 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
12208 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
12209 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
12210 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
12211 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
12212 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
12213 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
12215 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
12216 VSX_BUILTIN_LXVD2X_V2DF);
12217 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
12218 VSX_BUILTIN_LXVD2X_V2DI);
12219 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
12220 VSX_BUILTIN_LXVW4X_V4SF);
12221 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
12222 VSX_BUILTIN_LXVW4X_V4SI);
12223 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
12224 VSX_BUILTIN_LXVW4X_V8HI);
12225 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
12226 VSX_BUILTIN_LXVW4X_V16QI);
12227 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
12228 VSX_BUILTIN_STXVD2X_V2DF);
12229 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12230 VSX_BUILTIN_STXVD2X_V2DI);
12231 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12232 VSX_BUILTIN_STXVW4X_V4SF);
12233 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12234 VSX_BUILTIN_STXVW4X_V4SI);
12235 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12236 VSX_BUILTIN_STXVW4X_V8HI);
12237 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12238 VSX_BUILTIN_STXVW4X_V16QI);
12239 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12240 VSX_BUILTIN_VEC_LD);
12241 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12242 VSX_BUILTIN_VEC_ST);
12244 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12245 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12246 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12248 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12249 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12250 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12251 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12252 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12253 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12254 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12255 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12256 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12257 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12258 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12259 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12261 /* Cell builtins. */
12262 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12263 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12264 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12265 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12267 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12268 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12269 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12270 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12272 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12273 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12274 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12275 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12277 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12278 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12279 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12280 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12282 /* Add the DST variants. */
12283 d = bdesc_dst;
12284 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12285 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12287 /* Initialize the predicates. */
12288 d = bdesc_altivec_preds;
12289 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12291 enum machine_mode mode1;
12292 tree type;
12294 if (rs6000_overloaded_builtin_p (d->code))
12295 mode1 = VOIDmode;
12296 else
12297 mode1 = insn_data[d->icode].operand[1].mode;
12299 switch (mode1)
12301 case VOIDmode:
12302 type = int_ftype_int_opaque_opaque;
12303 break;
12304 case V4SImode:
12305 type = int_ftype_int_v4si_v4si;
12306 break;
12307 case V8HImode:
12308 type = int_ftype_int_v8hi_v8hi;
12309 break;
12310 case V16QImode:
12311 type = int_ftype_int_v16qi_v16qi;
12312 break;
12313 case V4SFmode:
12314 type = int_ftype_int_v4sf_v4sf;
12315 break;
12316 case V2DFmode:
12317 type = int_ftype_int_v2df_v2df;
12318 break;
12319 default:
12320 gcc_unreachable ();
12323 def_builtin (d->name, type, d->code);
12326 /* Initialize the abs* operators. */
12327 d = bdesc_abs;
12328 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12330 enum machine_mode mode0;
12331 tree type;
12333 mode0 = insn_data[d->icode].operand[0].mode;
12335 switch (mode0)
12337 case V4SImode:
12338 type = v4si_ftype_v4si;
12339 break;
12340 case V8HImode:
12341 type = v8hi_ftype_v8hi;
12342 break;
12343 case V16QImode:
12344 type = v16qi_ftype_v16qi;
12345 break;
12346 case V4SFmode:
12347 type = v4sf_ftype_v4sf;
12348 break;
12349 case V2DFmode:
12350 type = v2df_ftype_v2df;
12351 break;
12352 default:
12353 gcc_unreachable ();
12356 def_builtin (d->name, type, d->code);
12359 /* Initialize target builtin that implements
12360 targetm.vectorize.builtin_mask_for_load. */
12362 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12363 v16qi_ftype_long_pcvoid,
12364 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12365 BUILT_IN_MD, NULL, NULL_TREE);
12366 TREE_READONLY (decl) = 1;
12367 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12368 altivec_builtin_mask_for_load = decl;
12370 /* Access to the vec_init patterns. */
12371 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12372 integer_type_node, integer_type_node,
12373 integer_type_node, NULL_TREE);
12374 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12376 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12377 short_integer_type_node,
12378 short_integer_type_node,
12379 short_integer_type_node,
12380 short_integer_type_node,
12381 short_integer_type_node,
12382 short_integer_type_node,
12383 short_integer_type_node, NULL_TREE);
12384 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12386 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12387 char_type_node, char_type_node,
12388 char_type_node, char_type_node,
12389 char_type_node, char_type_node,
12390 char_type_node, char_type_node,
12391 char_type_node, char_type_node,
12392 char_type_node, char_type_node,
12393 char_type_node, char_type_node,
12394 char_type_node, NULL_TREE);
12395 def_builtin ("__builtin_vec_init_v16qi", ftype,
12396 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12398 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12399 float_type_node, float_type_node,
12400 float_type_node, NULL_TREE);
12401 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12403 /* VSX builtins. */
12404 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12405 double_type_node, NULL_TREE);
12406 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12408 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12409 intDI_type_node, NULL_TREE);
12410 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12412 /* Access to the vec_set patterns. */
12413 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12414 intSI_type_node,
12415 integer_type_node, NULL_TREE);
12416 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12418 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12419 intHI_type_node,
12420 integer_type_node, NULL_TREE);
12421 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12423 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12424 intQI_type_node,
12425 integer_type_node, NULL_TREE);
12426 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12428 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12429 float_type_node,
12430 integer_type_node, NULL_TREE);
12431 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12433 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12434 double_type_node,
12435 integer_type_node, NULL_TREE);
12436 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12438 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12439 intDI_type_node,
12440 integer_type_node, NULL_TREE);
12441 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12443 /* Access to the vec_extract patterns. */
12444 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12445 integer_type_node, NULL_TREE);
12446 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12448 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12449 integer_type_node, NULL_TREE);
12450 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12452 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12453 integer_type_node, NULL_TREE);
12454 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12456 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12457 integer_type_node, NULL_TREE);
12458 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12460 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12461 integer_type_node, NULL_TREE);
12462 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12464 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12465 integer_type_node, NULL_TREE);
12466 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12469 /* Hash function for builtin functions with up to 3 arguments and a return
12470 type. */
12471 static unsigned
12472 builtin_hash_function (const void *hash_entry)
12474 unsigned ret = 0;
12475 int i;
12476 const struct builtin_hash_struct *bh =
12477 (const struct builtin_hash_struct *) hash_entry;
12479 for (i = 0; i < 4; i++)
12481 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12482 ret = (ret * 2) + bh->uns_p[i];
12485 return ret;
12488 /* Compare builtin hash entries H1 and H2 for equivalence. */
12489 static int
12490 builtin_hash_eq (const void *h1, const void *h2)
12492 const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12493 const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12495 return ((p1->mode[0] == p2->mode[0])
12496 && (p1->mode[1] == p2->mode[1])
12497 && (p1->mode[2] == p2->mode[2])
12498 && (p1->mode[3] == p2->mode[3])
12499 && (p1->uns_p[0] == p2->uns_p[0])
12500 && (p1->uns_p[1] == p2->uns_p[1])
12501 && (p1->uns_p[2] == p2->uns_p[2])
12502 && (p1->uns_p[3] == p2->uns_p[3]));
12505 /* Map types for builtin functions with an explicit return type and up to 3
12506 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12507 of the argument. */
12508 static tree
12509 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12510 enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12511 enum rs6000_builtins builtin, const char *name)
12513 struct builtin_hash_struct h;
12514 struct builtin_hash_struct *h2;
12515 void **found;
12516 int num_args = 3;
12517 int i;
12518 tree ret_type = NULL_TREE;
12519 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12521 /* Create builtin_hash_table. */
12522 if (builtin_hash_table == NULL)
12523 builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12524 builtin_hash_eq, NULL);
12526 h.type = NULL_TREE;
12527 h.mode[0] = mode_ret;
12528 h.mode[1] = mode_arg0;
12529 h.mode[2] = mode_arg1;
12530 h.mode[3] = mode_arg2;
12531 h.uns_p[0] = 0;
12532 h.uns_p[1] = 0;
12533 h.uns_p[2] = 0;
12534 h.uns_p[3] = 0;
12536 /* If the builtin is a type that produces unsigned results or takes unsigned
12537 arguments, and it is returned as a decl for the vectorizer (such as
12538 widening multiplies, permute), make sure the arguments and return value
12539 are type correct. */
12540 switch (builtin)
12542 /* unsigned 2 argument functions. */
12543 case ALTIVEC_BUILTIN_VMULEUB_UNS:
12544 case ALTIVEC_BUILTIN_VMULEUH_UNS:
12545 case ALTIVEC_BUILTIN_VMULOUB_UNS:
12546 case ALTIVEC_BUILTIN_VMULOUH_UNS:
12547 h.uns_p[0] = 1;
12548 h.uns_p[1] = 1;
12549 h.uns_p[2] = 1;
12550 break;
12552 /* unsigned 3 argument functions. */
12553 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12554 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12555 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12556 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12557 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12558 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12559 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12560 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12561 case VSX_BUILTIN_VPERM_16QI_UNS:
12562 case VSX_BUILTIN_VPERM_8HI_UNS:
12563 case VSX_BUILTIN_VPERM_4SI_UNS:
12564 case VSX_BUILTIN_VPERM_2DI_UNS:
12565 case VSX_BUILTIN_XXSEL_16QI_UNS:
12566 case VSX_BUILTIN_XXSEL_8HI_UNS:
12567 case VSX_BUILTIN_XXSEL_4SI_UNS:
12568 case VSX_BUILTIN_XXSEL_2DI_UNS:
12569 h.uns_p[0] = 1;
12570 h.uns_p[1] = 1;
12571 h.uns_p[2] = 1;
12572 h.uns_p[3] = 1;
12573 break;
12575 /* signed permute functions with unsigned char mask. */
12576 case ALTIVEC_BUILTIN_VPERM_16QI:
12577 case ALTIVEC_BUILTIN_VPERM_8HI:
12578 case ALTIVEC_BUILTIN_VPERM_4SI:
12579 case ALTIVEC_BUILTIN_VPERM_4SF:
12580 case ALTIVEC_BUILTIN_VPERM_2DI:
12581 case ALTIVEC_BUILTIN_VPERM_2DF:
12582 case VSX_BUILTIN_VPERM_16QI:
12583 case VSX_BUILTIN_VPERM_8HI:
12584 case VSX_BUILTIN_VPERM_4SI:
12585 case VSX_BUILTIN_VPERM_4SF:
12586 case VSX_BUILTIN_VPERM_2DI:
12587 case VSX_BUILTIN_VPERM_2DF:
12588 h.uns_p[3] = 1;
12589 break;
12591 /* unsigned args, signed return. */
12592 case VSX_BUILTIN_XVCVUXDDP_UNS:
12593 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12594 h.uns_p[1] = 1;
12595 break;
12597 /* signed args, unsigned return. */
12598 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12599 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12600 h.uns_p[0] = 1;
12601 break;
12603 default:
12604 break;
12607 /* Figure out how many args are present. */
12608 while (num_args > 0 && h.mode[num_args] == VOIDmode)
12609 num_args--;
12611 if (num_args == 0)
12612 fatal_error ("internal error: builtin function %s had no type", name);
12614 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12615 if (!ret_type && h.uns_p[0])
12616 ret_type = builtin_mode_to_type[h.mode[0]][0];
12618 if (!ret_type)
12619 fatal_error ("internal error: builtin function %s had an unexpected "
12620 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12622 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12623 arg_type[i] = NULL_TREE;
12625 for (i = 0; i < num_args; i++)
12627 int m = (int) h.mode[i+1];
12628 int uns_p = h.uns_p[i+1];
12630 arg_type[i] = builtin_mode_to_type[m][uns_p];
12631 if (!arg_type[i] && uns_p)
12632 arg_type[i] = builtin_mode_to_type[m][0];
12634 if (!arg_type[i])
12635 fatal_error ("internal error: builtin function %s, argument %d "
12636 "had unexpected argument type %s", name, i,
12637 GET_MODE_NAME (m));
12640 found = htab_find_slot (builtin_hash_table, &h, INSERT);
12641 if (*found == NULL)
12643 h2 = ggc_alloc_builtin_hash_struct ();
12644 *h2 = h;
12645 *found = (void *)h2;
12647 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12648 arg_type[2], NULL_TREE);
12651 return ((struct builtin_hash_struct *)(*found))->type;
12654 static void
12655 rs6000_common_init_builtins (void)
12657 const struct builtin_description *d;
12658 size_t i;
12660 tree opaque_ftype_opaque = NULL_TREE;
12661 tree opaque_ftype_opaque_opaque = NULL_TREE;
12662 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12663 tree v2si_ftype_qi = NULL_TREE;
12664 tree v2si_ftype_v2si_qi = NULL_TREE;
12665 tree v2si_ftype_int_qi = NULL_TREE;
12666 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
12668 if (!TARGET_PAIRED_FLOAT)
12670 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12671 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12674 /* Paired and SPE builtins are only available if you build a compiler with
12675 the appropriate options, so only create those builtins with the
12676 appropriate compiler option. Create Altivec and VSX builtins on machines
12677 with at least the general purpose extensions (970 and newer) to allow the
12678 use of the target attribute.. */
12680 if (TARGET_EXTRA_BUILTINS)
12681 builtin_mask |= RS6000_BTM_COMMON;
12683 /* Add the ternary operators. */
12684 d = bdesc_3arg;
12685 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12687 tree type;
12688 HOST_WIDE_INT mask = d->mask;
12690 if ((mask & builtin_mask) != mask)
12692 if (TARGET_DEBUG_BUILTIN)
12693 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12694 continue;
12697 if (rs6000_overloaded_builtin_p (d->code))
12699 if (! (type = opaque_ftype_opaque_opaque_opaque))
12700 type = opaque_ftype_opaque_opaque_opaque
12701 = build_function_type_list (opaque_V4SI_type_node,
12702 opaque_V4SI_type_node,
12703 opaque_V4SI_type_node,
12704 opaque_V4SI_type_node,
12705 NULL_TREE);
12707 else
12709 enum insn_code icode = d->icode;
12710 if (d->name == 0 || icode == CODE_FOR_nothing)
12711 continue;
12713 type = builtin_function_type (insn_data[icode].operand[0].mode,
12714 insn_data[icode].operand[1].mode,
12715 insn_data[icode].operand[2].mode,
12716 insn_data[icode].operand[3].mode,
12717 d->code, d->name);
12720 def_builtin (d->name, type, d->code);
12723 /* Add the binary operators. */
12724 d = bdesc_2arg;
12725 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12727 enum machine_mode mode0, mode1, mode2;
12728 tree type;
12729 HOST_WIDE_INT mask = d->mask;
12731 if ((mask & builtin_mask) != mask)
12733 if (TARGET_DEBUG_BUILTIN)
12734 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12735 continue;
12738 if (rs6000_overloaded_builtin_p (d->code))
12740 if (! (type = opaque_ftype_opaque_opaque))
12741 type = opaque_ftype_opaque_opaque
12742 = build_function_type_list (opaque_V4SI_type_node,
12743 opaque_V4SI_type_node,
12744 opaque_V4SI_type_node,
12745 NULL_TREE);
12747 else
12749 enum insn_code icode = d->icode;
12750 if (d->name == 0 || icode == CODE_FOR_nothing)
12751 continue;
12753 mode0 = insn_data[icode].operand[0].mode;
12754 mode1 = insn_data[icode].operand[1].mode;
12755 mode2 = insn_data[icode].operand[2].mode;
12757 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12759 if (! (type = v2si_ftype_v2si_qi))
12760 type = v2si_ftype_v2si_qi
12761 = build_function_type_list (opaque_V2SI_type_node,
12762 opaque_V2SI_type_node,
12763 char_type_node,
12764 NULL_TREE);
12767 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12768 && mode2 == QImode)
12770 if (! (type = v2si_ftype_int_qi))
12771 type = v2si_ftype_int_qi
12772 = build_function_type_list (opaque_V2SI_type_node,
12773 integer_type_node,
12774 char_type_node,
12775 NULL_TREE);
12778 else
12779 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12780 d->code, d->name);
12783 def_builtin (d->name, type, d->code);
12786 /* Add the simple unary operators. */
12787 d = bdesc_1arg;
12788 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12790 enum machine_mode mode0, mode1;
12791 tree type;
12792 HOST_WIDE_INT mask = d->mask;
12794 if ((mask & builtin_mask) != mask)
12796 if (TARGET_DEBUG_BUILTIN)
12797 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12798 continue;
12801 if (rs6000_overloaded_builtin_p (d->code))
12803 if (! (type = opaque_ftype_opaque))
12804 type = opaque_ftype_opaque
12805 = build_function_type_list (opaque_V4SI_type_node,
12806 opaque_V4SI_type_node,
12807 NULL_TREE);
12809 else
12811 enum insn_code icode = d->icode;
12812 if (d->name == 0 || icode == CODE_FOR_nothing)
12813 continue;
12815 mode0 = insn_data[icode].operand[0].mode;
12816 mode1 = insn_data[icode].operand[1].mode;
12818 if (mode0 == V2SImode && mode1 == QImode)
12820 if (! (type = v2si_ftype_qi))
12821 type = v2si_ftype_qi
12822 = build_function_type_list (opaque_V2SI_type_node,
12823 char_type_node,
12824 NULL_TREE);
12827 else
12828 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12829 d->code, d->name);
12832 def_builtin (d->name, type, d->code);
12836 static void
12837 rs6000_init_libfuncs (void)
12839 if (!TARGET_IEEEQUAD)
12840 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12841 if (!TARGET_XL_COMPAT)
12843 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12844 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12845 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12846 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12848 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12850 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12851 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12852 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12853 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12854 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12855 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12856 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12858 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12859 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12860 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12861 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12862 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12863 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12864 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12865 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12868 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12869 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12871 else
12873 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12874 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12875 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12876 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12878 else
12880 /* 32-bit SVR4 quad floating point routines. */
12882 set_optab_libfunc (add_optab, TFmode, "_q_add");
12883 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12884 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12885 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12886 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12887 if (TARGET_PPC_GPOPT)
12888 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12890 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12891 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12892 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12893 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12894 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12895 set_optab_libfunc (le_optab, TFmode, "_q_fle");
12897 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12898 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12899 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12900 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12901 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12902 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12903 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12904 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12909 /* Expand a block clear operation, and return 1 if successful. Return 0
12910 if we should let the compiler generate normal code.
12912 operands[0] is the destination
12913 operands[1] is the length
12914 operands[3] is the alignment */
12917 expand_block_clear (rtx operands[])
12919 rtx orig_dest = operands[0];
12920 rtx bytes_rtx = operands[1];
12921 rtx align_rtx = operands[3];
12922 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
12923 HOST_WIDE_INT align;
12924 HOST_WIDE_INT bytes;
12925 int offset;
12926 int clear_bytes;
12927 int clear_step;
12929 /* If this is not a fixed size move, just call memcpy */
12930 if (! constp)
12931 return 0;
12933 /* This must be a fixed size alignment */
12934 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12935 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12937 /* Anything to clear? */
12938 bytes = INTVAL (bytes_rtx);
12939 if (bytes <= 0)
12940 return 1;
12942 /* Use the builtin memset after a point, to avoid huge code bloat.
12943 When optimize_size, avoid any significant code bloat; calling
12944 memset is about 4 instructions, so allow for one instruction to
12945 load zero and three to do clearing. */
12946 if (TARGET_ALTIVEC && align >= 128)
12947 clear_step = 16;
12948 else if (TARGET_POWERPC64 && align >= 32)
12949 clear_step = 8;
12950 else if (TARGET_SPE && align >= 64)
12951 clear_step = 8;
12952 else
12953 clear_step = 4;
12955 if (optimize_size && bytes > 3 * clear_step)
12956 return 0;
12957 if (! optimize_size && bytes > 8 * clear_step)
12958 return 0;
12960 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12962 enum machine_mode mode = BLKmode;
12963 rtx dest;
12965 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
12967 clear_bytes = 16;
12968 mode = V4SImode;
12970 else if (bytes >= 8 && TARGET_SPE && align >= 64)
12972 clear_bytes = 8;
12973 mode = V2SImode;
12975 else if (bytes >= 8 && TARGET_POWERPC64
12976 /* 64-bit loads and stores require word-aligned
12977 displacements. */
12978 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12980 clear_bytes = 8;
12981 mode = DImode;
12983 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12984 { /* move 4 bytes */
12985 clear_bytes = 4;
12986 mode = SImode;
12988 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12989 { /* move 2 bytes */
12990 clear_bytes = 2;
12991 mode = HImode;
12993 else /* move 1 byte at a time */
12995 clear_bytes = 1;
12996 mode = QImode;
12999 dest = adjust_address (orig_dest, mode, offset);
13001 emit_move_insn (dest, CONST0_RTX (mode));
13004 return 1;
13008 /* Expand a block move operation, and return 1 if successful. Return 0
13009 if we should let the compiler generate normal code.
13011 operands[0] is the destination
13012 operands[1] is the source
13013 operands[2] is the length
13014 operands[3] is the alignment */
13016 #define MAX_MOVE_REG 4
13019 expand_block_move (rtx operands[])
13021 rtx orig_dest = operands[0];
13022 rtx orig_src = operands[1];
13023 rtx bytes_rtx = operands[2];
13024 rtx align_rtx = operands[3];
13025 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
13026 int align;
13027 int bytes;
13028 int offset;
13029 int move_bytes;
13030 rtx stores[MAX_MOVE_REG];
13031 int num_reg = 0;
13033 /* If this is not a fixed size move, just call memcpy */
13034 if (! constp)
13035 return 0;
13037 /* This must be a fixed size alignment */
13038 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
13039 align = INTVAL (align_rtx) * BITS_PER_UNIT;
13041 /* Anything to move? */
13042 bytes = INTVAL (bytes_rtx);
13043 if (bytes <= 0)
13044 return 1;
13046 if (bytes > rs6000_block_move_inline_limit)
13047 return 0;
13049 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
13051 union {
13052 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
13053 rtx (*mov) (rtx, rtx);
13054 } gen_func;
13055 enum machine_mode mode = BLKmode;
13056 rtx src, dest;
13058 /* Altivec first, since it will be faster than a string move
13059 when it applies, and usually not significantly larger. */
13060 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
13062 move_bytes = 16;
13063 mode = V4SImode;
13064 gen_func.mov = gen_movv4si;
13066 else if (TARGET_SPE && bytes >= 8 && align >= 64)
13068 move_bytes = 8;
13069 mode = V2SImode;
13070 gen_func.mov = gen_movv2si;
13072 else if (TARGET_STRING
13073 && bytes > 24 /* move up to 32 bytes at a time */
13074 && ! fixed_regs[5]
13075 && ! fixed_regs[6]
13076 && ! fixed_regs[7]
13077 && ! fixed_regs[8]
13078 && ! fixed_regs[9]
13079 && ! fixed_regs[10]
13080 && ! fixed_regs[11]
13081 && ! fixed_regs[12])
13083 move_bytes = (bytes > 32) ? 32 : bytes;
13084 gen_func.movmemsi = gen_movmemsi_8reg;
13086 else if (TARGET_STRING
13087 && bytes > 16 /* move up to 24 bytes at a time */
13088 && ! fixed_regs[5]
13089 && ! fixed_regs[6]
13090 && ! fixed_regs[7]
13091 && ! fixed_regs[8]
13092 && ! fixed_regs[9]
13093 && ! fixed_regs[10])
13095 move_bytes = (bytes > 24) ? 24 : bytes;
13096 gen_func.movmemsi = gen_movmemsi_6reg;
13098 else if (TARGET_STRING
13099 && bytes > 8 /* move up to 16 bytes at a time */
13100 && ! fixed_regs[5]
13101 && ! fixed_regs[6]
13102 && ! fixed_regs[7]
13103 && ! fixed_regs[8])
13105 move_bytes = (bytes > 16) ? 16 : bytes;
13106 gen_func.movmemsi = gen_movmemsi_4reg;
13108 else if (bytes >= 8 && TARGET_POWERPC64
13109 /* 64-bit loads and stores require word-aligned
13110 displacements. */
13111 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
13113 move_bytes = 8;
13114 mode = DImode;
13115 gen_func.mov = gen_movdi;
13117 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
13118 { /* move up to 8 bytes at a time */
13119 move_bytes = (bytes > 8) ? 8 : bytes;
13120 gen_func.movmemsi = gen_movmemsi_2reg;
13122 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
13123 { /* move 4 bytes */
13124 move_bytes = 4;
13125 mode = SImode;
13126 gen_func.mov = gen_movsi;
13128 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
13129 { /* move 2 bytes */
13130 move_bytes = 2;
13131 mode = HImode;
13132 gen_func.mov = gen_movhi;
13134 else if (TARGET_STRING && bytes > 1)
13135 { /* move up to 4 bytes at a time */
13136 move_bytes = (bytes > 4) ? 4 : bytes;
13137 gen_func.movmemsi = gen_movmemsi_1reg;
13139 else /* move 1 byte at a time */
13141 move_bytes = 1;
13142 mode = QImode;
13143 gen_func.mov = gen_movqi;
13146 src = adjust_address (orig_src, mode, offset);
13147 dest = adjust_address (orig_dest, mode, offset);
13149 if (mode != BLKmode)
13151 rtx tmp_reg = gen_reg_rtx (mode);
13153 emit_insn ((*gen_func.mov) (tmp_reg, src));
13154 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
13157 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
13159 int i;
13160 for (i = 0; i < num_reg; i++)
13161 emit_insn (stores[i]);
13162 num_reg = 0;
13165 if (mode == BLKmode)
13167 /* Move the address into scratch registers. The movmemsi
13168 patterns require zero offset. */
13169 if (!REG_P (XEXP (src, 0)))
13171 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
13172 src = replace_equiv_address (src, src_reg);
13174 set_mem_size (src, move_bytes);
13176 if (!REG_P (XEXP (dest, 0)))
13178 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
13179 dest = replace_equiv_address (dest, dest_reg);
13181 set_mem_size (dest, move_bytes);
13183 emit_insn ((*gen_func.movmemsi) (dest, src,
13184 GEN_INT (move_bytes & 31),
13185 align_rtx));
13189 return 1;
13193 /* Return a string to perform a load_multiple operation.
13194 operands[0] is the vector.
13195 operands[1] is the source address.
13196 operands[2] is the first destination register. */
13198 const char *
13199 rs6000_output_load_multiple (rtx operands[3])
13201 /* We have to handle the case where the pseudo used to contain the address
13202 is assigned to one of the output registers. */
13203 int i, j;
13204 int words = XVECLEN (operands[0], 0);
13205 rtx xop[10];
13207 if (XVECLEN (operands[0], 0) == 1)
13208 return "lwz %2,0(%1)";
13210 for (i = 0; i < words; i++)
13211 if (refers_to_regno_p (REGNO (operands[2]) + i,
13212 REGNO (operands[2]) + i + 1, operands[1], 0))
13214 if (i == words-1)
13216 xop[0] = GEN_INT (4 * (words-1));
13217 xop[1] = operands[1];
13218 xop[2] = operands[2];
13219 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop);
13220 return "";
13222 else if (i == 0)
13224 xop[0] = GEN_INT (4 * (words-1));
13225 xop[1] = operands[1];
13226 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
13227 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop);
13228 return "";
13230 else
13232 for (j = 0; j < words; j++)
13233 if (j != i)
13235 xop[0] = GEN_INT (j * 4);
13236 xop[1] = operands[1];
13237 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
13238 output_asm_insn ("lwz %2,%0(%1)", xop);
13240 xop[0] = GEN_INT (i * 4);
13241 xop[1] = operands[1];
13242 output_asm_insn ("lwz %1,%0(%1)", xop);
13243 return "";
13247 return "lswi %2,%1,%N0";
13251 /* A validation routine: say whether CODE, a condition code, and MODE
13252 match. The other alternatives either don't make sense or should
13253 never be generated. */
13255 void
13256 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
13258 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
13259 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
13260 && GET_MODE_CLASS (mode) == MODE_CC);
13262 /* These don't make sense. */
13263 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
13264 || mode != CCUNSmode);
13266 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
13267 || mode == CCUNSmode);
13269 gcc_assert (mode == CCFPmode
13270 || (code != ORDERED && code != UNORDERED
13271 && code != UNEQ && code != LTGT
13272 && code != UNGT && code != UNLT
13273 && code != UNGE && code != UNLE));
13275 /* These should never be generated except for
13276 flag_finite_math_only. */
13277 gcc_assert (mode != CCFPmode
13278 || flag_finite_math_only
13279 || (code != LE && code != GE
13280 && code != UNEQ && code != LTGT
13281 && code != UNGT && code != UNLT));
13283 /* These are invalid; the information is not there. */
13284 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13288 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13289 mask required to convert the result of a rotate insn into a shift
13290 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13293 includes_lshift_p (rtx shiftop, rtx andop)
13295 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13297 shift_mask <<= INTVAL (shiftop);
13299 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13302 /* Similar, but for right shift. */
13305 includes_rshift_p (rtx shiftop, rtx andop)
13307 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13309 shift_mask >>= INTVAL (shiftop);
13311 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13314 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13315 to perform a left shift. It must have exactly SHIFTOP least
13316 significant 0's, then one or more 1's, then zero or more 0's. */
13319 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13321 if (GET_CODE (andop) == CONST_INT)
13323 HOST_WIDE_INT c, lsb, shift_mask;
13325 c = INTVAL (andop);
13326 if (c == 0 || c == ~0)
13327 return 0;
13329 shift_mask = ~0;
13330 shift_mask <<= INTVAL (shiftop);
13332 /* Find the least significant one bit. */
13333 lsb = c & -c;
13335 /* It must coincide with the LSB of the shift mask. */
13336 if (-lsb != shift_mask)
13337 return 0;
13339 /* Invert to look for the next transition (if any). */
13340 c = ~c;
13342 /* Remove the low group of ones (originally low group of zeros). */
13343 c &= -lsb;
13345 /* Again find the lsb, and check we have all 1's above. */
13346 lsb = c & -c;
13347 return c == -lsb;
13349 else if (GET_CODE (andop) == CONST_DOUBLE
13350 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13352 HOST_WIDE_INT low, high, lsb;
13353 HOST_WIDE_INT shift_mask_low, shift_mask_high;
13355 low = CONST_DOUBLE_LOW (andop);
13356 if (HOST_BITS_PER_WIDE_INT < 64)
13357 high = CONST_DOUBLE_HIGH (andop);
13359 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13360 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13361 return 0;
13363 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13365 shift_mask_high = ~0;
13366 if (INTVAL (shiftop) > 32)
13367 shift_mask_high <<= INTVAL (shiftop) - 32;
13369 lsb = high & -high;
13371 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13372 return 0;
13374 high = ~high;
13375 high &= -lsb;
13377 lsb = high & -high;
13378 return high == -lsb;
13381 shift_mask_low = ~0;
13382 shift_mask_low <<= INTVAL (shiftop);
13384 lsb = low & -low;
13386 if (-lsb != shift_mask_low)
13387 return 0;
13389 if (HOST_BITS_PER_WIDE_INT < 64)
13390 high = ~high;
13391 low = ~low;
13392 low &= -lsb;
13394 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13396 lsb = high & -high;
13397 return high == -lsb;
13400 lsb = low & -low;
13401 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13403 else
13404 return 0;
13407 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13408 to perform a left shift. It must have SHIFTOP or more least
13409 significant 0's, with the remainder of the word 1's. */
13412 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13414 if (GET_CODE (andop) == CONST_INT)
13416 HOST_WIDE_INT c, lsb, shift_mask;
13418 shift_mask = ~0;
13419 shift_mask <<= INTVAL (shiftop);
13420 c = INTVAL (andop);
13422 /* Find the least significant one bit. */
13423 lsb = c & -c;
13425 /* It must be covered by the shift mask.
13426 This test also rejects c == 0. */
13427 if ((lsb & shift_mask) == 0)
13428 return 0;
13430 /* Check we have all 1's above the transition, and reject all 1's. */
13431 return c == -lsb && lsb != 1;
13433 else if (GET_CODE (andop) == CONST_DOUBLE
13434 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13436 HOST_WIDE_INT low, lsb, shift_mask_low;
13438 low = CONST_DOUBLE_LOW (andop);
13440 if (HOST_BITS_PER_WIDE_INT < 64)
13442 HOST_WIDE_INT high, shift_mask_high;
13444 high = CONST_DOUBLE_HIGH (andop);
13446 if (low == 0)
13448 shift_mask_high = ~0;
13449 if (INTVAL (shiftop) > 32)
13450 shift_mask_high <<= INTVAL (shiftop) - 32;
13452 lsb = high & -high;
13454 if ((lsb & shift_mask_high) == 0)
13455 return 0;
13457 return high == -lsb;
13459 if (high != ~0)
13460 return 0;
13463 shift_mask_low = ~0;
13464 shift_mask_low <<= INTVAL (shiftop);
13466 lsb = low & -low;
13468 if ((lsb & shift_mask_low) == 0)
13469 return 0;
13471 return low == -lsb && lsb != 1;
13473 else
13474 return 0;
13477 /* Return 1 if operands will generate a valid arguments to rlwimi
13478 instruction for insert with right shift in 64-bit mode. The mask may
13479 not start on the first bit or stop on the last bit because wrap-around
13480 effects of instruction do not correspond to semantics of RTL insn. */
13483 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13485 if (INTVAL (startop) > 32
13486 && INTVAL (startop) < 64
13487 && INTVAL (sizeop) > 1
13488 && INTVAL (sizeop) + INTVAL (startop) < 64
13489 && INTVAL (shiftop) > 0
13490 && INTVAL (sizeop) + INTVAL (shiftop) < 32
13491 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13492 return 1;
13494 return 0;
13497 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13498 for lfq and stfq insns iff the registers are hard registers. */
13501 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13503 /* We might have been passed a SUBREG. */
13504 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13505 return 0;
13507 /* We might have been passed non floating point registers. */
13508 if (!FP_REGNO_P (REGNO (reg1))
13509 || !FP_REGNO_P (REGNO (reg2)))
13510 return 0;
13512 return (REGNO (reg1) == REGNO (reg2) - 1);
13515 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13516 addr1 and addr2 must be in consecutive memory locations
13517 (addr2 == addr1 + 8). */
13520 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13522 rtx addr1, addr2;
13523 unsigned int reg1, reg2;
13524 int offset1, offset2;
13526 /* The mems cannot be volatile. */
13527 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13528 return 0;
13530 addr1 = XEXP (mem1, 0);
13531 addr2 = XEXP (mem2, 0);
13533 /* Extract an offset (if used) from the first addr. */
13534 if (GET_CODE (addr1) == PLUS)
13536 /* If not a REG, return zero. */
13537 if (GET_CODE (XEXP (addr1, 0)) != REG)
13538 return 0;
13539 else
13541 reg1 = REGNO (XEXP (addr1, 0));
13542 /* The offset must be constant! */
13543 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13544 return 0;
13545 offset1 = INTVAL (XEXP (addr1, 1));
13548 else if (GET_CODE (addr1) != REG)
13549 return 0;
13550 else
13552 reg1 = REGNO (addr1);
13553 /* This was a simple (mem (reg)) expression. Offset is 0. */
13554 offset1 = 0;
13557 /* And now for the second addr. */
13558 if (GET_CODE (addr2) == PLUS)
13560 /* If not a REG, return zero. */
13561 if (GET_CODE (XEXP (addr2, 0)) != REG)
13562 return 0;
13563 else
13565 reg2 = REGNO (XEXP (addr2, 0));
13566 /* The offset must be constant. */
13567 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13568 return 0;
13569 offset2 = INTVAL (XEXP (addr2, 1));
13572 else if (GET_CODE (addr2) != REG)
13573 return 0;
13574 else
13576 reg2 = REGNO (addr2);
13577 /* This was a simple (mem (reg)) expression. Offset is 0. */
13578 offset2 = 0;
13581 /* Both of these must have the same base register. */
13582 if (reg1 != reg2)
13583 return 0;
13585 /* The offset for the second addr must be 8 more than the first addr. */
13586 if (offset2 != offset1 + 8)
13587 return 0;
13589 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13590 instructions. */
13591 return 1;
13596 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13598 static bool eliminated = false;
13599 rtx ret;
13601 if (mode != SDmode)
13602 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13603 else
13605 rtx mem = cfun->machine->sdmode_stack_slot;
13606 gcc_assert (mem != NULL_RTX);
13608 if (!eliminated)
13610 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13611 cfun->machine->sdmode_stack_slot = mem;
13612 eliminated = true;
13614 ret = mem;
13617 if (TARGET_DEBUG_ADDR)
13619 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13620 GET_MODE_NAME (mode));
13621 if (!ret)
13622 fprintf (stderr, "\tNULL_RTX\n");
13623 else
13624 debug_rtx (ret);
13627 return ret;
13630 static tree
13631 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13633 /* Don't walk into types. */
13634 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13636 *walk_subtrees = 0;
13637 return NULL_TREE;
13640 switch (TREE_CODE (*tp))
13642 case VAR_DECL:
13643 case PARM_DECL:
13644 case FIELD_DECL:
13645 case RESULT_DECL:
13646 case SSA_NAME:
13647 case REAL_CST:
13648 case MEM_REF:
13649 case VIEW_CONVERT_EXPR:
13650 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13651 return *tp;
13652 break;
13653 default:
13654 break;
13657 return NULL_TREE;
13660 enum reload_reg_type {
13661 GPR_REGISTER_TYPE,
13662 VECTOR_REGISTER_TYPE,
13663 OTHER_REGISTER_TYPE
13666 static enum reload_reg_type
13667 rs6000_reload_register_type (enum reg_class rclass)
13669 switch (rclass)
13671 case GENERAL_REGS:
13672 case BASE_REGS:
13673 return GPR_REGISTER_TYPE;
13675 case FLOAT_REGS:
13676 case ALTIVEC_REGS:
13677 case VSX_REGS:
13678 return VECTOR_REGISTER_TYPE;
13680 default:
13681 return OTHER_REGISTER_TYPE;
13685 /* Inform reload about cases where moving X with a mode MODE to a register in
13686 RCLASS requires an extra scratch or immediate register. Return the class
13687 needed for the immediate register.
13689 For VSX and Altivec, we may need a register to convert sp+offset into
13690 reg+sp.
13692 For misaligned 64-bit gpr loads and stores we need a register to
13693 convert an offset address to indirect. */
13695 static reg_class_t
13696 rs6000_secondary_reload (bool in_p,
13697 rtx x,
13698 reg_class_t rclass_i,
13699 enum machine_mode mode,
13700 secondary_reload_info *sri)
13702 enum reg_class rclass = (enum reg_class) rclass_i;
13703 reg_class_t ret = ALL_REGS;
13704 enum insn_code icode;
13705 bool default_p = false;
13707 sri->icode = CODE_FOR_nothing;
13709 /* Convert vector loads and stores into gprs to use an additional base
13710 register. */
13711 icode = rs6000_vector_reload[mode][in_p != false];
13712 if (icode != CODE_FOR_nothing)
13714 ret = NO_REGS;
13715 sri->icode = CODE_FOR_nothing;
13716 sri->extra_cost = 0;
13718 if (GET_CODE (x) == MEM)
13720 rtx addr = XEXP (x, 0);
13722 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13723 an extra register in that case, but it would need an extra
13724 register if the addressing is reg+reg or (reg+reg)&(-16). */
13725 if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13727 if (!legitimate_indirect_address_p (addr, false)
13728 && !rs6000_legitimate_offset_address_p (TImode, addr,
13729 false, true))
13731 sri->icode = icode;
13732 /* account for splitting the loads, and converting the
13733 address from reg+reg to reg. */
13734 sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13735 + ((GET_CODE (addr) == AND) ? 1 : 0));
13738 /* Loads to and stores from vector registers can only do reg+reg
13739 addressing. Altivec registers can also do (reg+reg)&(-16). */
13740 else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13741 || rclass == FLOAT_REGS || rclass == NO_REGS)
13743 if (!VECTOR_MEM_ALTIVEC_P (mode)
13744 && GET_CODE (addr) == AND
13745 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13746 && INTVAL (XEXP (addr, 1)) == -16
13747 && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13748 || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13750 sri->icode = icode;
13751 sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13752 ? 2 : 1);
13754 else if (!legitimate_indirect_address_p (addr, false)
13755 && (rclass == NO_REGS
13756 || !legitimate_indexed_address_p (addr, false)))
13758 sri->icode = icode;
13759 sri->extra_cost = 1;
13761 else
13762 icode = CODE_FOR_nothing;
13764 /* Any other loads, including to pseudo registers which haven't been
13765 assigned to a register yet, default to require a scratch
13766 register. */
13767 else
13769 sri->icode = icode;
13770 sri->extra_cost = 2;
13773 else if (REG_P (x))
13775 int regno = true_regnum (x);
13777 icode = CODE_FOR_nothing;
13778 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13779 default_p = true;
13780 else
13782 enum reg_class xclass = REGNO_REG_CLASS (regno);
13783 enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13784 enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13786 /* If memory is needed, use default_secondary_reload to create the
13787 stack slot. */
13788 if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13789 default_p = true;
13790 else
13791 ret = NO_REGS;
13794 else
13795 default_p = true;
13797 else if (TARGET_POWERPC64
13798 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13799 && MEM_P (x)
13800 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13802 rtx off = address_offset (XEXP (x, 0));
13803 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
13805 if (off != NULL_RTX
13806 && (INTVAL (off) & 3) != 0
13807 && (unsigned HOST_WIDE_INT) INTVAL (off) + 0x8000 < 0x10000 - extra)
13809 if (in_p)
13810 sri->icode = CODE_FOR_reload_di_load;
13811 else
13812 sri->icode = CODE_FOR_reload_di_store;
13813 sri->extra_cost = 2;
13814 ret = NO_REGS;
13816 else
13817 default_p = true;
13819 else if (!TARGET_POWERPC64
13820 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13821 && MEM_P (x)
13822 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
13824 rtx off = address_offset (XEXP (x, 0));
13825 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
13827 /* We need a secondary reload only when our legitimate_address_p
13828 says the address is good (as otherwise the entire address
13829 will be reloaded). So for mode sizes of 8 and 16 this will
13830 be when the offset is in the ranges [0x7ffc,0x7fff] and
13831 [0x7ff4,0x7ff7] respectively. Note that the address we see
13832 here may have been manipulated by legitimize_reload_address. */
13833 if (off != NULL_RTX
13834 && ((unsigned HOST_WIDE_INT) INTVAL (off) - (0x8000 - extra)
13835 < UNITS_PER_WORD))
13837 if (in_p)
13838 sri->icode = CODE_FOR_reload_si_load;
13839 else
13840 sri->icode = CODE_FOR_reload_si_store;
13841 sri->extra_cost = 2;
13842 ret = NO_REGS;
13844 else
13845 default_p = true;
13847 else
13848 default_p = true;
13850 if (default_p)
13851 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13853 gcc_assert (ret != ALL_REGS);
13855 if (TARGET_DEBUG_ADDR)
13857 fprintf (stderr,
13858 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13859 "mode = %s",
13860 reg_class_names[ret],
13861 in_p ? "true" : "false",
13862 reg_class_names[rclass],
13863 GET_MODE_NAME (mode));
13865 if (default_p)
13866 fprintf (stderr, ", default secondary reload");
13868 if (sri->icode != CODE_FOR_nothing)
13869 fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13870 insn_data[sri->icode].name, sri->extra_cost);
13871 else
13872 fprintf (stderr, "\n");
13874 debug_rtx (x);
13877 return ret;
13880 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13881 to SP+reg addressing. */
13883 void
13884 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13886 int regno = true_regnum (reg);
13887 enum machine_mode mode = GET_MODE (reg);
13888 enum reg_class rclass;
13889 rtx addr;
13890 rtx and_op2 = NULL_RTX;
13891 rtx addr_op1;
13892 rtx addr_op2;
13893 rtx scratch_or_premodify = scratch;
13894 rtx and_rtx;
13895 rtx cc_clobber;
13897 if (TARGET_DEBUG_ADDR)
13899 fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13900 store_p ? "store" : "load");
13901 fprintf (stderr, "reg:\n");
13902 debug_rtx (reg);
13903 fprintf (stderr, "mem:\n");
13904 debug_rtx (mem);
13905 fprintf (stderr, "scratch:\n");
13906 debug_rtx (scratch);
13909 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13910 gcc_assert (GET_CODE (mem) == MEM);
13911 rclass = REGNO_REG_CLASS (regno);
13912 addr = XEXP (mem, 0);
13914 switch (rclass)
13916 /* GPRs can handle reg + small constant, all other addresses need to use
13917 the scratch register. */
13918 case GENERAL_REGS:
13919 case BASE_REGS:
13920 if (GET_CODE (addr) == AND)
13922 and_op2 = XEXP (addr, 1);
13923 addr = XEXP (addr, 0);
13926 if (GET_CODE (addr) == PRE_MODIFY)
13928 scratch_or_premodify = XEXP (addr, 0);
13929 gcc_assert (REG_P (scratch_or_premodify));
13930 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13931 addr = XEXP (addr, 1);
13934 if (GET_CODE (addr) == PLUS
13935 && (and_op2 != NULL_RTX
13936 || !rs6000_legitimate_offset_address_p (TImode, addr,
13937 false, true)))
13939 addr_op1 = XEXP (addr, 0);
13940 addr_op2 = XEXP (addr, 1);
13941 gcc_assert (legitimate_indirect_address_p (addr_op1, false));
13943 if (!REG_P (addr_op2)
13944 && (GET_CODE (addr_op2) != CONST_INT
13945 || !satisfies_constraint_I (addr_op2)))
13947 if (TARGET_DEBUG_ADDR)
13949 fprintf (stderr,
13950 "\nMove plus addr to register %s, mode = %s: ",
13951 rs6000_reg_names[REGNO (scratch)],
13952 GET_MODE_NAME (mode));
13953 debug_rtx (addr_op2);
13955 rs6000_emit_move (scratch, addr_op2, Pmode);
13956 addr_op2 = scratch;
13959 emit_insn (gen_rtx_SET (VOIDmode,
13960 scratch_or_premodify,
13961 gen_rtx_PLUS (Pmode,
13962 addr_op1,
13963 addr_op2)));
13965 addr = scratch_or_premodify;
13966 scratch_or_premodify = scratch;
13968 else if (!legitimate_indirect_address_p (addr, false)
13969 && !rs6000_legitimate_offset_address_p (TImode, addr,
13970 false, true))
13972 if (TARGET_DEBUG_ADDR)
13974 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13975 rs6000_reg_names[REGNO (scratch_or_premodify)],
13976 GET_MODE_NAME (mode));
13977 debug_rtx (addr);
13979 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13980 addr = scratch_or_premodify;
13981 scratch_or_premodify = scratch;
13983 break;
13985 /* Float/Altivec registers can only handle reg+reg addressing. Move
13986 other addresses into a scratch register. */
13987 case FLOAT_REGS:
13988 case VSX_REGS:
13989 case ALTIVEC_REGS:
13991 /* With float regs, we need to handle the AND ourselves, since we can't
13992 use the Altivec instruction with an implicit AND -16. Allow scalar
13993 loads to float registers to use reg+offset even if VSX. */
13994 if (GET_CODE (addr) == AND
13995 && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
13996 || GET_CODE (XEXP (addr, 1)) != CONST_INT
13997 || INTVAL (XEXP (addr, 1)) != -16
13998 || !VECTOR_MEM_ALTIVEC_P (mode)))
14000 and_op2 = XEXP (addr, 1);
14001 addr = XEXP (addr, 0);
14004 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
14005 as the address later. */
14006 if (GET_CODE (addr) == PRE_MODIFY
14007 && (!VECTOR_MEM_VSX_P (mode)
14008 || and_op2 != NULL_RTX
14009 || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
14011 scratch_or_premodify = XEXP (addr, 0);
14012 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
14013 false));
14014 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
14015 addr = XEXP (addr, 1);
14018 if (legitimate_indirect_address_p (addr, false) /* reg */
14019 || legitimate_indexed_address_p (addr, false) /* reg+reg */
14020 || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
14021 || (GET_CODE (addr) == AND /* Altivec memory */
14022 && GET_CODE (XEXP (addr, 1)) == CONST_INT
14023 && INTVAL (XEXP (addr, 1)) == -16
14024 && VECTOR_MEM_ALTIVEC_P (mode))
14025 || (rclass == FLOAT_REGS /* legacy float mem */
14026 && GET_MODE_SIZE (mode) == 8
14027 && and_op2 == NULL_RTX
14028 && scratch_or_premodify == scratch
14029 && rs6000_legitimate_offset_address_p (mode, addr, false, false)))
14032 else if (GET_CODE (addr) == PLUS)
14034 addr_op1 = XEXP (addr, 0);
14035 addr_op2 = XEXP (addr, 1);
14036 gcc_assert (REG_P (addr_op1));
14038 if (TARGET_DEBUG_ADDR)
14040 fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
14041 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
14042 debug_rtx (addr_op2);
14044 rs6000_emit_move (scratch, addr_op2, Pmode);
14045 emit_insn (gen_rtx_SET (VOIDmode,
14046 scratch_or_premodify,
14047 gen_rtx_PLUS (Pmode,
14048 addr_op1,
14049 scratch)));
14050 addr = scratch_or_premodify;
14051 scratch_or_premodify = scratch;
14054 else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
14055 || GET_CODE (addr) == CONST_INT || REG_P (addr))
14057 if (TARGET_DEBUG_ADDR)
14059 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
14060 rs6000_reg_names[REGNO (scratch_or_premodify)],
14061 GET_MODE_NAME (mode));
14062 debug_rtx (addr);
14065 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14066 addr = scratch_or_premodify;
14067 scratch_or_premodify = scratch;
14070 else
14071 gcc_unreachable ();
14073 break;
14075 default:
14076 gcc_unreachable ();
14079 /* If the original address involved a pre-modify that we couldn't use the VSX
14080 memory instruction with update, and we haven't taken care of already,
14081 store the address in the pre-modify register and use that as the
14082 address. */
14083 if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
14085 emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
14086 addr = scratch_or_premodify;
14089 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
14090 memory instruction, recreate the AND now, including the clobber which is
14091 generated by the general ANDSI3/ANDDI3 patterns for the
14092 andi. instruction. */
14093 if (and_op2 != NULL_RTX)
14095 if (! legitimate_indirect_address_p (addr, false))
14097 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
14098 addr = scratch;
14101 if (TARGET_DEBUG_ADDR)
14103 fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
14104 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
14105 debug_rtx (and_op2);
14108 and_rtx = gen_rtx_SET (VOIDmode,
14109 scratch,
14110 gen_rtx_AND (Pmode,
14111 addr,
14112 and_op2));
14114 cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
14115 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14116 gen_rtvec (2, and_rtx, cc_clobber)));
14117 addr = scratch;
14120 /* Adjust the address if it changed. */
14121 if (addr != XEXP (mem, 0))
14123 mem = change_address (mem, mode, addr);
14124 if (TARGET_DEBUG_ADDR)
14125 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14128 /* Now create the move. */
14129 if (store_p)
14130 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14131 else
14132 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14134 return;
14137 /* Convert reloads involving 64-bit gprs and misaligned offset
14138 addressing, or multiple 32-bit gprs and offsets that are too large,
14139 to use indirect addressing. */
14141 void
14142 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
14144 int regno = true_regnum (reg);
14145 enum reg_class rclass;
14146 rtx addr;
14147 rtx scratch_or_premodify = scratch;
14149 if (TARGET_DEBUG_ADDR)
14151 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
14152 store_p ? "store" : "load");
14153 fprintf (stderr, "reg:\n");
14154 debug_rtx (reg);
14155 fprintf (stderr, "mem:\n");
14156 debug_rtx (mem);
14157 fprintf (stderr, "scratch:\n");
14158 debug_rtx (scratch);
14161 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
14162 gcc_assert (GET_CODE (mem) == MEM);
14163 rclass = REGNO_REG_CLASS (regno);
14164 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
14165 addr = XEXP (mem, 0);
14167 if (GET_CODE (addr) == PRE_MODIFY)
14169 scratch_or_premodify = XEXP (addr, 0);
14170 gcc_assert (REG_P (scratch_or_premodify));
14171 addr = XEXP (addr, 1);
14173 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14175 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14177 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
14179 /* Now create the move. */
14180 if (store_p)
14181 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14182 else
14183 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14185 return;
14188 /* Allocate a 64-bit stack slot to be used for copying SDmode
14189 values through if this function has any SDmode references. */
14191 static void
14192 rs6000_alloc_sdmode_stack_slot (void)
14194 tree t;
14195 basic_block bb;
14196 gimple_stmt_iterator gsi;
14198 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
14200 FOR_EACH_BB (bb)
14201 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
14203 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
14204 if (ret)
14206 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14207 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14208 SDmode, 0);
14209 return;
14213 /* Check for any SDmode parameters of the function. */
14214 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
14216 if (TREE_TYPE (t) == error_mark_node)
14217 continue;
14219 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
14220 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
14222 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14223 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14224 SDmode, 0);
14225 return;
14230 static void
14231 rs6000_instantiate_decls (void)
14233 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
14234 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
14237 /* Given an rtx X being reloaded into a reg required to be
14238 in class CLASS, return the class of reg to actually use.
14239 In general this is just CLASS; but on some machines
14240 in some cases it is preferable to use a more restrictive class.
14242 On the RS/6000, we have to return NO_REGS when we want to reload a
14243 floating-point CONST_DOUBLE to force it to be copied to memory.
14245 We also don't want to reload integer values into floating-point
14246 registers if we can at all help it. In fact, this can
14247 cause reload to die, if it tries to generate a reload of CTR
14248 into a FP register and discovers it doesn't have the memory location
14249 required.
14251 ??? Would it be a good idea to have reload do the converse, that is
14252 try to reload floating modes into FP registers if possible?
14255 static enum reg_class
14256 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
14258 enum machine_mode mode = GET_MODE (x);
14260 if (VECTOR_UNIT_VSX_P (mode)
14261 && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
14262 return rclass;
14264 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
14265 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
14266 && easy_vector_constant (x, mode))
14267 return ALTIVEC_REGS;
14269 if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
14270 return NO_REGS;
14272 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
14273 return GENERAL_REGS;
14275 /* For VSX, prefer the traditional registers for 64-bit values because we can
14276 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14277 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14278 prefer Altivec loads.. */
14279 if (rclass == VSX_REGS)
14281 if (GET_MODE_SIZE (mode) <= 8)
14282 return FLOAT_REGS;
14284 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
14285 return ALTIVEC_REGS;
14287 return rclass;
14290 return rclass;
14293 /* Debug version of rs6000_preferred_reload_class. */
14294 static enum reg_class
14295 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
14297 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
14299 fprintf (stderr,
14300 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14301 "mode = %s, x:\n",
14302 reg_class_names[ret], reg_class_names[rclass],
14303 GET_MODE_NAME (GET_MODE (x)));
14304 debug_rtx (x);
14306 return ret;
14309 /* If we are copying between FP or AltiVec registers and anything else, we need
14310 a memory location. The exception is when we are targeting ppc64 and the
14311 move to/from fpr to gpr instructions are available. Also, under VSX, you
14312 can copy vector registers from the FP register set to the Altivec register
14313 set and vice versa. */
14315 static bool
14316 rs6000_secondary_memory_needed (enum reg_class class1,
14317 enum reg_class class2,
14318 enum machine_mode mode)
14320 if (class1 == class2)
14321 return false;
14323 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14324 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14325 between these classes. But we need memory for other things that can go in
14326 FLOAT_REGS like SFmode. */
14327 if (TARGET_VSX
14328 && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14329 && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14330 || class1 == FLOAT_REGS))
14331 return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14332 && class2 != FLOAT_REGS);
14334 if (class1 == VSX_REGS || class2 == VSX_REGS)
14335 return true;
14337 if (class1 == FLOAT_REGS
14338 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14339 || ((mode != DFmode)
14340 && (mode != DDmode)
14341 && (mode != DImode))))
14342 return true;
14344 if (class2 == FLOAT_REGS
14345 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14346 || ((mode != DFmode)
14347 && (mode != DDmode)
14348 && (mode != DImode))))
14349 return true;
14351 if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14352 return true;
14354 return false;
14357 /* Debug version of rs6000_secondary_memory_needed. */
14358 static bool
14359 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14360 enum reg_class class2,
14361 enum machine_mode mode)
14363 bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14365 fprintf (stderr,
14366 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14367 "class2 = %s, mode = %s\n",
14368 ret ? "true" : "false", reg_class_names[class1],
14369 reg_class_names[class2], GET_MODE_NAME (mode));
14371 return ret;
14374 /* Return the register class of a scratch register needed to copy IN into
14375 or out of a register in RCLASS in MODE. If it can be done directly,
14376 NO_REGS is returned. */
14378 static enum reg_class
14379 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14380 rtx in)
14382 int regno;
14384 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14385 #if TARGET_MACHO
14386 && MACHOPIC_INDIRECT
14387 #endif
14390 /* We cannot copy a symbolic operand directly into anything
14391 other than BASE_REGS for TARGET_ELF. So indicate that a
14392 register from BASE_REGS is needed as an intermediate
14393 register.
14395 On Darwin, pic addresses require a load from memory, which
14396 needs a base register. */
14397 if (rclass != BASE_REGS
14398 && (GET_CODE (in) == SYMBOL_REF
14399 || GET_CODE (in) == HIGH
14400 || GET_CODE (in) == LABEL_REF
14401 || GET_CODE (in) == CONST))
14402 return BASE_REGS;
14405 if (GET_CODE (in) == REG)
14407 regno = REGNO (in);
14408 if (regno >= FIRST_PSEUDO_REGISTER)
14410 regno = true_regnum (in);
14411 if (regno >= FIRST_PSEUDO_REGISTER)
14412 regno = -1;
14415 else if (GET_CODE (in) == SUBREG)
14417 regno = true_regnum (in);
14418 if (regno >= FIRST_PSEUDO_REGISTER)
14419 regno = -1;
14421 else
14422 regno = -1;
14424 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14425 into anything. */
14426 if (rclass == GENERAL_REGS || rclass == BASE_REGS
14427 || (regno >= 0 && INT_REGNO_P (regno)))
14428 return NO_REGS;
14430 /* Constants, memory, and FP registers can go into FP registers. */
14431 if ((regno == -1 || FP_REGNO_P (regno))
14432 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14433 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14435 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14436 VSX. */
14437 if (TARGET_VSX
14438 && (regno == -1 || VSX_REGNO_P (regno))
14439 && VSX_REG_CLASS_P (rclass))
14440 return NO_REGS;
14442 /* Memory, and AltiVec registers can go into AltiVec registers. */
14443 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14444 && rclass == ALTIVEC_REGS)
14445 return NO_REGS;
14447 /* We can copy among the CR registers. */
14448 if ((rclass == CR_REGS || rclass == CR0_REGS)
14449 && regno >= 0 && CR_REGNO_P (regno))
14450 return NO_REGS;
14452 /* Otherwise, we need GENERAL_REGS. */
14453 return GENERAL_REGS;
14456 /* Debug version of rs6000_secondary_reload_class. */
14457 static enum reg_class
14458 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14459 enum machine_mode mode, rtx in)
14461 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14462 fprintf (stderr,
14463 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14464 "mode = %s, input rtx:\n",
14465 reg_class_names[ret], reg_class_names[rclass],
14466 GET_MODE_NAME (mode));
14467 debug_rtx (in);
14469 return ret;
14472 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14474 static bool
14475 rs6000_cannot_change_mode_class (enum machine_mode from,
14476 enum machine_mode to,
14477 enum reg_class rclass)
14479 unsigned from_size = GET_MODE_SIZE (from);
14480 unsigned to_size = GET_MODE_SIZE (to);
14482 if (from_size != to_size)
14484 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14485 return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14486 && reg_classes_intersect_p (xclass, rclass));
14489 if (TARGET_E500_DOUBLE
14490 && ((((to) == DFmode) + ((from) == DFmode)) == 1
14491 || (((to) == TFmode) + ((from) == TFmode)) == 1
14492 || (((to) == DDmode) + ((from) == DDmode)) == 1
14493 || (((to) == TDmode) + ((from) == TDmode)) == 1
14494 || (((to) == DImode) + ((from) == DImode)) == 1))
14495 return true;
14497 /* Since the VSX register set includes traditional floating point registers
14498 and altivec registers, just check for the size being different instead of
14499 trying to check whether the modes are vector modes. Otherwise it won't
14500 allow say DF and DI to change classes. */
14501 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14502 return (from_size != 8 && from_size != 16);
14504 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14505 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14506 return true;
14508 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14509 && reg_classes_intersect_p (GENERAL_REGS, rclass))
14510 return true;
14512 return false;
14515 /* Debug version of rs6000_cannot_change_mode_class. */
14516 static bool
14517 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14518 enum machine_mode to,
14519 enum reg_class rclass)
14521 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14523 fprintf (stderr,
14524 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14525 "to = %s, rclass = %s\n",
14526 ret ? "true" : "false",
14527 GET_MODE_NAME (from), GET_MODE_NAME (to),
14528 reg_class_names[rclass]);
14530 return ret;
14533 /* Given a comparison operation, return the bit number in CCR to test. We
14534 know this is a valid comparison.
14536 SCC_P is 1 if this is for an scc. That means that %D will have been
14537 used instead of %C, so the bits will be in different places.
14539 Return -1 if OP isn't a valid comparison for some reason. */
14542 ccr_bit (rtx op, int scc_p)
14544 enum rtx_code code = GET_CODE (op);
14545 enum machine_mode cc_mode;
14546 int cc_regnum;
14547 int base_bit;
14548 rtx reg;
14550 if (!COMPARISON_P (op))
14551 return -1;
14553 reg = XEXP (op, 0);
14555 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14557 cc_mode = GET_MODE (reg);
14558 cc_regnum = REGNO (reg);
14559 base_bit = 4 * (cc_regnum - CR0_REGNO);
14561 validate_condition_mode (code, cc_mode);
14563 /* When generating a sCOND operation, only positive conditions are
14564 allowed. */
14565 gcc_assert (!scc_p
14566 || code == EQ || code == GT || code == LT || code == UNORDERED
14567 || code == GTU || code == LTU);
14569 switch (code)
14571 case NE:
14572 return scc_p ? base_bit + 3 : base_bit + 2;
14573 case EQ:
14574 return base_bit + 2;
14575 case GT: case GTU: case UNLE:
14576 return base_bit + 1;
14577 case LT: case LTU: case UNGE:
14578 return base_bit;
14579 case ORDERED: case UNORDERED:
14580 return base_bit + 3;
14582 case GE: case GEU:
14583 /* If scc, we will have done a cror to put the bit in the
14584 unordered position. So test that bit. For integer, this is ! LT
14585 unless this is an scc insn. */
14586 return scc_p ? base_bit + 3 : base_bit;
14588 case LE: case LEU:
14589 return scc_p ? base_bit + 3 : base_bit + 1;
14591 default:
14592 gcc_unreachable ();
14596 /* Return the GOT register. */
14599 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14601 /* The second flow pass currently (June 1999) can't update
14602 regs_ever_live without disturbing other parts of the compiler, so
14603 update it here to make the prolog/epilogue code happy. */
14604 if (!can_create_pseudo_p ()
14605 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14606 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14608 crtl->uses_pic_offset_table = 1;
14610 return pic_offset_table_rtx;
14613 static rs6000_stack_t stack_info;
14615 /* Function to init struct machine_function.
14616 This will be called, via a pointer variable,
14617 from push_function_context. */
14619 static struct machine_function *
14620 rs6000_init_machine_status (void)
14622 stack_info.reload_completed = 0;
14623 return ggc_alloc_cleared_machine_function ();
14626 /* These macros test for integers and extract the low-order bits. */
14627 #define INT_P(X) \
14628 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14629 && GET_MODE (X) == VOIDmode)
14631 #define INT_LOWPART(X) \
14632 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14635 extract_MB (rtx op)
14637 int i;
14638 unsigned long val = INT_LOWPART (op);
14640 /* If the high bit is zero, the value is the first 1 bit we find
14641 from the left. */
14642 if ((val & 0x80000000) == 0)
14644 gcc_assert (val & 0xffffffff);
14646 i = 1;
14647 while (((val <<= 1) & 0x80000000) == 0)
14648 ++i;
14649 return i;
14652 /* If the high bit is set and the low bit is not, or the mask is all
14653 1's, the value is zero. */
14654 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14655 return 0;
14657 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14658 from the right. */
14659 i = 31;
14660 while (((val >>= 1) & 1) != 0)
14661 --i;
14663 return i;
14667 extract_ME (rtx op)
14669 int i;
14670 unsigned long val = INT_LOWPART (op);
14672 /* If the low bit is zero, the value is the first 1 bit we find from
14673 the right. */
14674 if ((val & 1) == 0)
14676 gcc_assert (val & 0xffffffff);
14678 i = 30;
14679 while (((val >>= 1) & 1) == 0)
14680 --i;
14682 return i;
14685 /* If the low bit is set and the high bit is not, or the mask is all
14686 1's, the value is 31. */
14687 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14688 return 31;
14690 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14691 from the left. */
14692 i = 0;
14693 while (((val <<= 1) & 0x80000000) != 0)
14694 ++i;
14696 return i;
14699 /* Locate some local-dynamic symbol still in use by this function
14700 so that we can print its name in some tls_ld pattern. */
14702 static const char *
14703 rs6000_get_some_local_dynamic_name (void)
14705 rtx insn;
14707 if (cfun->machine->some_ld_name)
14708 return cfun->machine->some_ld_name;
14710 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14711 if (INSN_P (insn)
14712 && for_each_rtx (&PATTERN (insn),
14713 rs6000_get_some_local_dynamic_name_1, 0))
14714 return cfun->machine->some_ld_name;
14716 gcc_unreachable ();
14719 /* Helper function for rs6000_get_some_local_dynamic_name. */
14721 static int
14722 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14724 rtx x = *px;
14726 if (GET_CODE (x) == SYMBOL_REF)
14728 const char *str = XSTR (x, 0);
14729 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14731 cfun->machine->some_ld_name = str;
14732 return 1;
14736 return 0;
14739 /* Write out a function code label. */
14741 void
14742 rs6000_output_function_entry (FILE *file, const char *fname)
14744 if (fname[0] != '.')
14746 switch (DEFAULT_ABI)
14748 default:
14749 gcc_unreachable ();
14751 case ABI_AIX:
14752 if (DOT_SYMBOLS)
14753 putc ('.', file);
14754 else
14755 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14756 break;
14758 case ABI_V4:
14759 case ABI_DARWIN:
14760 break;
14764 RS6000_OUTPUT_BASENAME (file, fname);
14767 /* Print an operand. Recognize special options, documented below. */
14769 #if TARGET_ELF
14770 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14771 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14772 #else
14773 #define SMALL_DATA_RELOC "sda21"
14774 #define SMALL_DATA_REG 0
14775 #endif
14777 void
14778 print_operand (FILE *file, rtx x, int code)
14780 int i;
14781 unsigned HOST_WIDE_INT uval;
14783 switch (code)
14785 /* %a is output_address. */
14787 case 'b':
14788 /* If constant, low-order 16 bits of constant, unsigned.
14789 Otherwise, write normally. */
14790 if (INT_P (x))
14791 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14792 else
14793 print_operand (file, x, 0);
14794 return;
14796 case 'B':
14797 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14798 for 64-bit mask direction. */
14799 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14800 return;
14802 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14803 output_operand. */
14805 case 'D':
14806 /* Like 'J' but get to the GT bit only. */
14807 gcc_assert (REG_P (x));
14809 /* Bit 1 is GT bit. */
14810 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14812 /* Add one for shift count in rlinm for scc. */
14813 fprintf (file, "%d", i + 1);
14814 return;
14816 case 'E':
14817 /* X is a CR register. Print the number of the EQ bit of the CR */
14818 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14819 output_operand_lossage ("invalid %%E value");
14820 else
14821 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14822 return;
14824 case 'f':
14825 /* X is a CR register. Print the shift count needed to move it
14826 to the high-order four bits. */
14827 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14828 output_operand_lossage ("invalid %%f value");
14829 else
14830 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14831 return;
14833 case 'F':
14834 /* Similar, but print the count for the rotate in the opposite
14835 direction. */
14836 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14837 output_operand_lossage ("invalid %%F value");
14838 else
14839 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14840 return;
14842 case 'G':
14843 /* X is a constant integer. If it is negative, print "m",
14844 otherwise print "z". This is to make an aze or ame insn. */
14845 if (GET_CODE (x) != CONST_INT)
14846 output_operand_lossage ("invalid %%G value");
14847 else if (INTVAL (x) >= 0)
14848 putc ('z', file);
14849 else
14850 putc ('m', file);
14851 return;
14853 case 'h':
14854 /* If constant, output low-order five bits. Otherwise, write
14855 normally. */
14856 if (INT_P (x))
14857 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14858 else
14859 print_operand (file, x, 0);
14860 return;
14862 case 'H':
14863 /* If constant, output low-order six bits. Otherwise, write
14864 normally. */
14865 if (INT_P (x))
14866 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14867 else
14868 print_operand (file, x, 0);
14869 return;
14871 case 'I':
14872 /* Print `i' if this is a constant, else nothing. */
14873 if (INT_P (x))
14874 putc ('i', file);
14875 return;
14877 case 'j':
14878 /* Write the bit number in CCR for jump. */
14879 i = ccr_bit (x, 0);
14880 if (i == -1)
14881 output_operand_lossage ("invalid %%j code");
14882 else
14883 fprintf (file, "%d", i);
14884 return;
14886 case 'J':
14887 /* Similar, but add one for shift count in rlinm for scc and pass
14888 scc flag to `ccr_bit'. */
14889 i = ccr_bit (x, 1);
14890 if (i == -1)
14891 output_operand_lossage ("invalid %%J code");
14892 else
14893 /* If we want bit 31, write a shift count of zero, not 32. */
14894 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14895 return;
14897 case 'k':
14898 /* X must be a constant. Write the 1's complement of the
14899 constant. */
14900 if (! INT_P (x))
14901 output_operand_lossage ("invalid %%k value");
14902 else
14903 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14904 return;
14906 case 'K':
14907 /* X must be a symbolic constant on ELF. Write an
14908 expression suitable for an 'addi' that adds in the low 16
14909 bits of the MEM. */
14910 if (GET_CODE (x) == CONST)
14912 if (GET_CODE (XEXP (x, 0)) != PLUS
14913 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14914 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14915 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14916 output_operand_lossage ("invalid %%K value");
14918 print_operand_address (file, x);
14919 fputs ("@l", file);
14920 return;
14922 /* %l is output_asm_label. */
14924 case 'L':
14925 /* Write second word of DImode or DFmode reference. Works on register
14926 or non-indexed memory only. */
14927 if (REG_P (x))
14928 fputs (reg_names[REGNO (x) + 1], file);
14929 else if (MEM_P (x))
14931 /* Handle possible auto-increment. Since it is pre-increment and
14932 we have already done it, we can just use an offset of word. */
14933 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14934 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14935 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
14936 UNITS_PER_WORD));
14937 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14938 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
14939 UNITS_PER_WORD));
14940 else
14941 output_address (XEXP (adjust_address_nv (x, SImode,
14942 UNITS_PER_WORD),
14943 0));
14945 if (small_data_operand (x, GET_MODE (x)))
14946 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14947 reg_names[SMALL_DATA_REG]);
14949 return;
14951 case 'm':
14952 /* MB value for a mask operand. */
14953 if (! mask_operand (x, SImode))
14954 output_operand_lossage ("invalid %%m value");
14956 fprintf (file, "%d", extract_MB (x));
14957 return;
14959 case 'M':
14960 /* ME value for a mask operand. */
14961 if (! mask_operand (x, SImode))
14962 output_operand_lossage ("invalid %%M value");
14964 fprintf (file, "%d", extract_ME (x));
14965 return;
14967 /* %n outputs the negative of its operand. */
14969 case 'N':
14970 /* Write the number of elements in the vector times 4. */
14971 if (GET_CODE (x) != PARALLEL)
14972 output_operand_lossage ("invalid %%N value");
14973 else
14974 fprintf (file, "%d", XVECLEN (x, 0) * 4);
14975 return;
14977 case 'O':
14978 /* Similar, but subtract 1 first. */
14979 if (GET_CODE (x) != PARALLEL)
14980 output_operand_lossage ("invalid %%O value");
14981 else
14982 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
14983 return;
14985 case 'p':
14986 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14987 if (! INT_P (x)
14988 || INT_LOWPART (x) < 0
14989 || (i = exact_log2 (INT_LOWPART (x))) < 0)
14990 output_operand_lossage ("invalid %%p value");
14991 else
14992 fprintf (file, "%d", i);
14993 return;
14995 case 'P':
14996 /* The operand must be an indirect memory reference. The result
14997 is the register name. */
14998 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
14999 || REGNO (XEXP (x, 0)) >= 32)
15000 output_operand_lossage ("invalid %%P value");
15001 else
15002 fputs (reg_names[REGNO (XEXP (x, 0))], file);
15003 return;
15005 case 'q':
15006 /* This outputs the logical code corresponding to a boolean
15007 expression. The expression may have one or both operands
15008 negated (if one, only the first one). For condition register
15009 logical operations, it will also treat the negated
15010 CR codes as NOTs, but not handle NOTs of them. */
15012 const char *const *t = 0;
15013 const char *s;
15014 enum rtx_code code = GET_CODE (x);
15015 static const char * const tbl[3][3] = {
15016 { "and", "andc", "nor" },
15017 { "or", "orc", "nand" },
15018 { "xor", "eqv", "xor" } };
15020 if (code == AND)
15021 t = tbl[0];
15022 else if (code == IOR)
15023 t = tbl[1];
15024 else if (code == XOR)
15025 t = tbl[2];
15026 else
15027 output_operand_lossage ("invalid %%q value");
15029 if (GET_CODE (XEXP (x, 0)) != NOT)
15030 s = t[0];
15031 else
15033 if (GET_CODE (XEXP (x, 1)) == NOT)
15034 s = t[2];
15035 else
15036 s = t[1];
15039 fputs (s, file);
15041 return;
15043 case 'Q':
15044 if (! TARGET_MFCRF)
15045 return;
15046 fputc (',', file);
15047 /* FALLTHRU */
15049 case 'R':
15050 /* X is a CR register. Print the mask for `mtcrf'. */
15051 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
15052 output_operand_lossage ("invalid %%R value");
15053 else
15054 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
15055 return;
15057 case 's':
15058 /* Low 5 bits of 32 - value */
15059 if (! INT_P (x))
15060 output_operand_lossage ("invalid %%s value");
15061 else
15062 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
15063 return;
15065 case 'S':
15066 /* PowerPC64 mask position. All 0's is excluded.
15067 CONST_INT 32-bit mask is considered sign-extended so any
15068 transition must occur within the CONST_INT, not on the boundary. */
15069 if (! mask64_operand (x, DImode))
15070 output_operand_lossage ("invalid %%S value");
15072 uval = INT_LOWPART (x);
15074 if (uval & 1) /* Clear Left */
15076 #if HOST_BITS_PER_WIDE_INT > 64
15077 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15078 #endif
15079 i = 64;
15081 else /* Clear Right */
15083 uval = ~uval;
15084 #if HOST_BITS_PER_WIDE_INT > 64
15085 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15086 #endif
15087 i = 63;
15089 while (uval != 0)
15090 --i, uval >>= 1;
15091 gcc_assert (i >= 0);
15092 fprintf (file, "%d", i);
15093 return;
15095 case 't':
15096 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15097 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
15099 /* Bit 3 is OV bit. */
15100 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
15102 /* If we want bit 31, write a shift count of zero, not 32. */
15103 fprintf (file, "%d", i == 31 ? 0 : i + 1);
15104 return;
15106 case 'T':
15107 /* Print the symbolic name of a branch target register. */
15108 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
15109 && REGNO (x) != CTR_REGNO))
15110 output_operand_lossage ("invalid %%T value");
15111 else if (REGNO (x) == LR_REGNO)
15112 fputs ("lr", file);
15113 else
15114 fputs ("ctr", file);
15115 return;
15117 case 'u':
15118 /* High-order 16 bits of constant for use in unsigned operand. */
15119 if (! INT_P (x))
15120 output_operand_lossage ("invalid %%u value");
15121 else
15122 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15123 (INT_LOWPART (x) >> 16) & 0xffff);
15124 return;
15126 case 'v':
15127 /* High-order 16 bits of constant for use in signed operand. */
15128 if (! INT_P (x))
15129 output_operand_lossage ("invalid %%v value");
15130 else
15131 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15132 (INT_LOWPART (x) >> 16) & 0xffff);
15133 return;
15135 case 'U':
15136 /* Print `u' if this has an auto-increment or auto-decrement. */
15137 if (MEM_P (x)
15138 && (GET_CODE (XEXP (x, 0)) == PRE_INC
15139 || GET_CODE (XEXP (x, 0)) == PRE_DEC
15140 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
15141 putc ('u', file);
15142 return;
15144 case 'V':
15145 /* Print the trap code for this operand. */
15146 switch (GET_CODE (x))
15148 case EQ:
15149 fputs ("eq", file); /* 4 */
15150 break;
15151 case NE:
15152 fputs ("ne", file); /* 24 */
15153 break;
15154 case LT:
15155 fputs ("lt", file); /* 16 */
15156 break;
15157 case LE:
15158 fputs ("le", file); /* 20 */
15159 break;
15160 case GT:
15161 fputs ("gt", file); /* 8 */
15162 break;
15163 case GE:
15164 fputs ("ge", file); /* 12 */
15165 break;
15166 case LTU:
15167 fputs ("llt", file); /* 2 */
15168 break;
15169 case LEU:
15170 fputs ("lle", file); /* 6 */
15171 break;
15172 case GTU:
15173 fputs ("lgt", file); /* 1 */
15174 break;
15175 case GEU:
15176 fputs ("lge", file); /* 5 */
15177 break;
15178 default:
15179 gcc_unreachable ();
15181 break;
15183 case 'w':
15184 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15185 normally. */
15186 if (INT_P (x))
15187 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
15188 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
15189 else
15190 print_operand (file, x, 0);
15191 return;
15193 case 'W':
15194 /* MB value for a PowerPC64 rldic operand. */
15195 i = clz_hwi (GET_CODE (x) == CONST_INT
15196 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
15198 #if HOST_BITS_PER_WIDE_INT == 32
15199 if (GET_CODE (x) == CONST_INT && i > 0)
15200 i += 32; /* zero-extend high-part was all 0's */
15201 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
15202 i = clz_hwi (CONST_DOUBLE_LOW (x)) + 32;
15203 #endif
15205 fprintf (file, "%d", i);
15206 return;
15208 case 'x':
15209 /* X is a FPR or Altivec register used in a VSX context. */
15210 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
15211 output_operand_lossage ("invalid %%x value");
15212 else
15214 int reg = REGNO (x);
15215 int vsx_reg = (FP_REGNO_P (reg)
15216 ? reg - 32
15217 : reg - FIRST_ALTIVEC_REGNO + 32);
15219 #ifdef TARGET_REGNAMES
15220 if (TARGET_REGNAMES)
15221 fprintf (file, "%%vs%d", vsx_reg);
15222 else
15223 #endif
15224 fprintf (file, "%d", vsx_reg);
15226 return;
15228 case 'X':
15229 if (MEM_P (x)
15230 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
15231 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
15232 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
15233 putc ('x', file);
15234 return;
15236 case 'Y':
15237 /* Like 'L', for third word of TImode */
15238 if (REG_P (x))
15239 fputs (reg_names[REGNO (x) + 2], file);
15240 else if (MEM_P (x))
15242 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15243 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15244 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
15245 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15246 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
15247 else
15248 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
15249 if (small_data_operand (x, GET_MODE (x)))
15250 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15251 reg_names[SMALL_DATA_REG]);
15253 return;
15255 case 'z':
15256 /* X is a SYMBOL_REF. Write out the name preceded by a
15257 period and without any trailing data in brackets. Used for function
15258 names. If we are configured for System V (or the embedded ABI) on
15259 the PowerPC, do not emit the period, since those systems do not use
15260 TOCs and the like. */
15261 gcc_assert (GET_CODE (x) == SYMBOL_REF);
15263 /* Mark the decl as referenced so that cgraph will output the
15264 function. */
15265 if (SYMBOL_REF_DECL (x))
15266 mark_decl_referenced (SYMBOL_REF_DECL (x));
15268 /* For macho, check to see if we need a stub. */
15269 if (TARGET_MACHO)
15271 const char *name = XSTR (x, 0);
15272 #if TARGET_MACHO
15273 if (darwin_emit_branch_islands
15274 && MACHOPIC_INDIRECT
15275 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
15276 name = machopic_indirection_name (x, /*stub_p=*/true);
15277 #endif
15278 assemble_name (file, name);
15280 else if (!DOT_SYMBOLS)
15281 assemble_name (file, XSTR (x, 0));
15282 else
15283 rs6000_output_function_entry (file, XSTR (x, 0));
15284 return;
15286 case 'Z':
15287 /* Like 'L', for last word of TImode. */
15288 if (REG_P (x))
15289 fputs (reg_names[REGNO (x) + 3], file);
15290 else if (MEM_P (x))
15292 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15293 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15294 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15295 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15296 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
15297 else
15298 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15299 if (small_data_operand (x, GET_MODE (x)))
15300 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15301 reg_names[SMALL_DATA_REG]);
15303 return;
15305 /* Print AltiVec or SPE memory operand. */
15306 case 'y':
15308 rtx tmp;
15310 gcc_assert (MEM_P (x));
15312 tmp = XEXP (x, 0);
15314 /* Ugly hack because %y is overloaded. */
15315 if ((TARGET_SPE || TARGET_E500_DOUBLE)
15316 && (GET_MODE_SIZE (GET_MODE (x)) == 8
15317 || GET_MODE (x) == TFmode
15318 || GET_MODE (x) == TImode))
15320 /* Handle [reg]. */
15321 if (REG_P (tmp))
15323 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15324 break;
15326 /* Handle [reg+UIMM]. */
15327 else if (GET_CODE (tmp) == PLUS &&
15328 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15330 int x;
15332 gcc_assert (REG_P (XEXP (tmp, 0)));
15334 x = INTVAL (XEXP (tmp, 1));
15335 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15336 break;
15339 /* Fall through. Must be [reg+reg]. */
15341 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15342 && GET_CODE (tmp) == AND
15343 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15344 && INTVAL (XEXP (tmp, 1)) == -16)
15345 tmp = XEXP (tmp, 0);
15346 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15347 && GET_CODE (tmp) == PRE_MODIFY)
15348 tmp = XEXP (tmp, 1);
15349 if (REG_P (tmp))
15350 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15351 else
15353 if (!GET_CODE (tmp) == PLUS
15354 || !REG_P (XEXP (tmp, 0))
15355 || !REG_P (XEXP (tmp, 1)))
15357 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15358 break;
15361 if (REGNO (XEXP (tmp, 0)) == 0)
15362 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15363 reg_names[ REGNO (XEXP (tmp, 0)) ]);
15364 else
15365 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15366 reg_names[ REGNO (XEXP (tmp, 1)) ]);
15368 break;
15371 case 0:
15372 if (REG_P (x))
15373 fprintf (file, "%s", reg_names[REGNO (x)]);
15374 else if (MEM_P (x))
15376 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15377 know the width from the mode. */
15378 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15379 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15380 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15381 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15382 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15383 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15384 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15385 output_address (XEXP (XEXP (x, 0), 1));
15386 else
15387 output_address (XEXP (x, 0));
15389 else
15391 if (toc_relative_expr_p (x, false))
15392 /* This hack along with a corresponding hack in
15393 rs6000_output_addr_const_extra arranges to output addends
15394 where the assembler expects to find them. eg.
15395 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
15396 without this hack would be output as "x@toc+4". We
15397 want "x+4@toc". */
15398 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15399 else
15400 output_addr_const (file, x);
15402 return;
15404 case '&':
15405 assemble_name (file, rs6000_get_some_local_dynamic_name ());
15406 return;
15408 default:
15409 output_operand_lossage ("invalid %%xn code");
15413 /* Print the address of an operand. */
15415 void
15416 print_operand_address (FILE *file, rtx x)
15418 if (REG_P (x))
15419 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15420 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15421 || GET_CODE (x) == LABEL_REF)
15423 output_addr_const (file, x);
15424 if (small_data_operand (x, GET_MODE (x)))
15425 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15426 reg_names[SMALL_DATA_REG]);
15427 else
15428 gcc_assert (!TARGET_TOC);
15430 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15431 && REG_P (XEXP (x, 1)))
15433 if (REGNO (XEXP (x, 0)) == 0)
15434 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15435 reg_names[ REGNO (XEXP (x, 0)) ]);
15436 else
15437 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15438 reg_names[ REGNO (XEXP (x, 1)) ]);
15440 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
15441 && GET_CODE (XEXP (x, 1)) == CONST_INT)
15442 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15443 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15444 #if TARGET_MACHO
15445 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15446 && CONSTANT_P (XEXP (x, 1)))
15448 fprintf (file, "lo16(");
15449 output_addr_const (file, XEXP (x, 1));
15450 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15452 #endif
15453 #if TARGET_ELF
15454 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
15455 && CONSTANT_P (XEXP (x, 1)))
15457 output_addr_const (file, XEXP (x, 1));
15458 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15460 #endif
15461 else if (toc_relative_expr_p (x, false))
15463 /* This hack along with a corresponding hack in
15464 rs6000_output_addr_const_extra arranges to output addends
15465 where the assembler expects to find them. eg.
15466 (lo_sum (reg 9)
15467 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
15468 without this hack would be output as "x@toc+8@l(9)". We
15469 want "x+8@toc@l(9)". */
15470 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
15471 if (GET_CODE (x) == LO_SUM)
15472 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
15473 else
15474 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base, 0, 1))]);
15476 else
15477 gcc_unreachable ();
15480 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15482 static bool
15483 rs6000_output_addr_const_extra (FILE *file, rtx x)
15485 if (GET_CODE (x) == UNSPEC)
15486 switch (XINT (x, 1))
15488 case UNSPEC_TOCREL:
15489 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
15490 && REG_P (XVECEXP (x, 0, 1))
15491 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
15492 output_addr_const (file, XVECEXP (x, 0, 0));
15493 if (x == tocrel_base && tocrel_offset != const0_rtx)
15495 if (INTVAL (tocrel_offset) >= 0)
15496 fprintf (file, "+");
15497 output_addr_const (file, CONST_CAST_RTX (tocrel_offset));
15499 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15501 putc ('-', file);
15502 assemble_name (file, toc_label_name);
15504 else if (TARGET_ELF)
15505 fputs ("@toc", file);
15506 return true;
15508 #if TARGET_MACHO
15509 case UNSPEC_MACHOPIC_OFFSET:
15510 output_addr_const (file, XVECEXP (x, 0, 0));
15511 putc ('-', file);
15512 machopic_output_function_base_name (file);
15513 return true;
15514 #endif
15516 return false;
15519 /* Target hook for assembling integer objects. The PowerPC version has
15520 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15521 is defined. It also needs to handle DI-mode objects on 64-bit
15522 targets. */
15524 static bool
15525 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15527 #ifdef RELOCATABLE_NEEDS_FIXUP
15528 /* Special handling for SI values. */
15529 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15531 static int recurse = 0;
15533 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15534 the .fixup section. Since the TOC section is already relocated, we
15535 don't need to mark it here. We used to skip the text section, but it
15536 should never be valid for relocated addresses to be placed in the text
15537 section. */
15538 if (TARGET_RELOCATABLE
15539 && in_section != toc_section
15540 && !recurse
15541 && GET_CODE (x) != CONST_INT
15542 && GET_CODE (x) != CONST_DOUBLE
15543 && CONSTANT_P (x))
15545 char buf[256];
15547 recurse = 1;
15548 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15549 fixuplabelno++;
15550 ASM_OUTPUT_LABEL (asm_out_file, buf);
15551 fprintf (asm_out_file, "\t.long\t(");
15552 output_addr_const (asm_out_file, x);
15553 fprintf (asm_out_file, ")@fixup\n");
15554 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15555 ASM_OUTPUT_ALIGN (asm_out_file, 2);
15556 fprintf (asm_out_file, "\t.long\t");
15557 assemble_name (asm_out_file, buf);
15558 fprintf (asm_out_file, "\n\t.previous\n");
15559 recurse = 0;
15560 return true;
15562 /* Remove initial .'s to turn a -mcall-aixdesc function
15563 address into the address of the descriptor, not the function
15564 itself. */
15565 else if (GET_CODE (x) == SYMBOL_REF
15566 && XSTR (x, 0)[0] == '.'
15567 && DEFAULT_ABI == ABI_AIX)
15569 const char *name = XSTR (x, 0);
15570 while (*name == '.')
15571 name++;
15573 fprintf (asm_out_file, "\t.long\t%s\n", name);
15574 return true;
15577 #endif /* RELOCATABLE_NEEDS_FIXUP */
15578 return default_assemble_integer (x, size, aligned_p);
15581 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15582 /* Emit an assembler directive to set symbol visibility for DECL to
15583 VISIBILITY_TYPE. */
15585 static void
15586 rs6000_assemble_visibility (tree decl, int vis)
15588 if (TARGET_XCOFF)
15589 return;
15591 /* Functions need to have their entry point symbol visibility set as
15592 well as their descriptor symbol visibility. */
15593 if (DEFAULT_ABI == ABI_AIX
15594 && DOT_SYMBOLS
15595 && TREE_CODE (decl) == FUNCTION_DECL)
15597 static const char * const visibility_types[] = {
15598 NULL, "internal", "hidden", "protected"
15601 const char *name, *type;
15603 name = ((* targetm.strip_name_encoding)
15604 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15605 type = visibility_types[vis];
15607 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15608 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15610 else
15611 default_assemble_visibility (decl, vis);
15613 #endif
15615 enum rtx_code
15616 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15618 /* Reversal of FP compares takes care -- an ordered compare
15619 becomes an unordered compare and vice versa. */
15620 if (mode == CCFPmode
15621 && (!flag_finite_math_only
15622 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15623 || code == UNEQ || code == LTGT))
15624 return reverse_condition_maybe_unordered (code);
15625 else
15626 return reverse_condition (code);
15629 /* Generate a compare for CODE. Return a brand-new rtx that
15630 represents the result of the compare. */
15632 static rtx
15633 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15635 enum machine_mode comp_mode;
15636 rtx compare_result;
15637 enum rtx_code code = GET_CODE (cmp);
15638 rtx op0 = XEXP (cmp, 0);
15639 rtx op1 = XEXP (cmp, 1);
15641 if (FLOAT_MODE_P (mode))
15642 comp_mode = CCFPmode;
15643 else if (code == GTU || code == LTU
15644 || code == GEU || code == LEU)
15645 comp_mode = CCUNSmode;
15646 else if ((code == EQ || code == NE)
15647 && unsigned_reg_p (op0)
15648 && (unsigned_reg_p (op1)
15649 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
15650 /* These are unsigned values, perhaps there will be a later
15651 ordering compare that can be shared with this one. */
15652 comp_mode = CCUNSmode;
15653 else
15654 comp_mode = CCmode;
15656 /* If we have an unsigned compare, make sure we don't have a signed value as
15657 an immediate. */
15658 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
15659 && INTVAL (op1) < 0)
15661 op0 = copy_rtx_if_shared (op0);
15662 op1 = force_reg (GET_MODE (op0), op1);
15663 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
15666 /* First, the compare. */
15667 compare_result = gen_reg_rtx (comp_mode);
15669 /* E500 FP compare instructions on the GPRs. Yuck! */
15670 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15671 && FLOAT_MODE_P (mode))
15673 rtx cmp, or_result, compare_result2;
15674 enum machine_mode op_mode = GET_MODE (op0);
15676 if (op_mode == VOIDmode)
15677 op_mode = GET_MODE (op1);
15679 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15680 This explains the following mess. */
15682 switch (code)
15684 case EQ: case UNEQ: case NE: case LTGT:
15685 switch (op_mode)
15687 case SFmode:
15688 cmp = (flag_finite_math_only && !flag_trapping_math)
15689 ? gen_tstsfeq_gpr (compare_result, op0, op1)
15690 : gen_cmpsfeq_gpr (compare_result, op0, op1);
15691 break;
15693 case DFmode:
15694 cmp = (flag_finite_math_only && !flag_trapping_math)
15695 ? gen_tstdfeq_gpr (compare_result, op0, op1)
15696 : gen_cmpdfeq_gpr (compare_result, op0, op1);
15697 break;
15699 case TFmode:
15700 cmp = (flag_finite_math_only && !flag_trapping_math)
15701 ? gen_tsttfeq_gpr (compare_result, op0, op1)
15702 : gen_cmptfeq_gpr (compare_result, op0, op1);
15703 break;
15705 default:
15706 gcc_unreachable ();
15708 break;
15710 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15711 switch (op_mode)
15713 case SFmode:
15714 cmp = (flag_finite_math_only && !flag_trapping_math)
15715 ? gen_tstsfgt_gpr (compare_result, op0, op1)
15716 : gen_cmpsfgt_gpr (compare_result, op0, op1);
15717 break;
15719 case DFmode:
15720 cmp = (flag_finite_math_only && !flag_trapping_math)
15721 ? gen_tstdfgt_gpr (compare_result, op0, op1)
15722 : gen_cmpdfgt_gpr (compare_result, op0, op1);
15723 break;
15725 case TFmode:
15726 cmp = (flag_finite_math_only && !flag_trapping_math)
15727 ? gen_tsttfgt_gpr (compare_result, op0, op1)
15728 : gen_cmptfgt_gpr (compare_result, op0, op1);
15729 break;
15731 default:
15732 gcc_unreachable ();
15734 break;
15736 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15737 switch (op_mode)
15739 case SFmode:
15740 cmp = (flag_finite_math_only && !flag_trapping_math)
15741 ? gen_tstsflt_gpr (compare_result, op0, op1)
15742 : gen_cmpsflt_gpr (compare_result, op0, op1);
15743 break;
15745 case DFmode:
15746 cmp = (flag_finite_math_only && !flag_trapping_math)
15747 ? gen_tstdflt_gpr (compare_result, op0, op1)
15748 : gen_cmpdflt_gpr (compare_result, op0, op1);
15749 break;
15751 case TFmode:
15752 cmp = (flag_finite_math_only && !flag_trapping_math)
15753 ? gen_tsttflt_gpr (compare_result, op0, op1)
15754 : gen_cmptflt_gpr (compare_result, op0, op1);
15755 break;
15757 default:
15758 gcc_unreachable ();
15760 break;
15761 default:
15762 gcc_unreachable ();
15765 /* Synthesize LE and GE from LT/GT || EQ. */
15766 if (code == LE || code == GE || code == LEU || code == GEU)
15768 emit_insn (cmp);
15770 switch (code)
15772 case LE: code = LT; break;
15773 case GE: code = GT; break;
15774 case LEU: code = LT; break;
15775 case GEU: code = GT; break;
15776 default: gcc_unreachable ();
15779 compare_result2 = gen_reg_rtx (CCFPmode);
15781 /* Do the EQ. */
15782 switch (op_mode)
15784 case SFmode:
15785 cmp = (flag_finite_math_only && !flag_trapping_math)
15786 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
15787 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
15788 break;
15790 case DFmode:
15791 cmp = (flag_finite_math_only && !flag_trapping_math)
15792 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
15793 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
15794 break;
15796 case TFmode:
15797 cmp = (flag_finite_math_only && !flag_trapping_math)
15798 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
15799 : gen_cmptfeq_gpr (compare_result2, op0, op1);
15800 break;
15802 default:
15803 gcc_unreachable ();
15805 emit_insn (cmp);
15807 /* OR them together. */
15808 or_result = gen_reg_rtx (CCFPmode);
15809 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15810 compare_result2);
15811 compare_result = or_result;
15812 code = EQ;
15814 else
15816 if (code == NE || code == LTGT)
15817 code = NE;
15818 else
15819 code = EQ;
15822 emit_insn (cmp);
15824 else
15826 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15827 CLOBBERs to match cmptf_internal2 pattern. */
15828 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15829 && GET_MODE (op0) == TFmode
15830 && !TARGET_IEEEQUAD
15831 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15832 emit_insn (gen_rtx_PARALLEL (VOIDmode,
15833 gen_rtvec (10,
15834 gen_rtx_SET (VOIDmode,
15835 compare_result,
15836 gen_rtx_COMPARE (comp_mode, op0, op1)),
15837 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15838 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15839 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15840 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15841 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15842 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15843 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15844 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15845 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15846 else if (GET_CODE (op1) == UNSPEC
15847 && XINT (op1, 1) == UNSPEC_SP_TEST)
15849 rtx op1b = XVECEXP (op1, 0, 0);
15850 comp_mode = CCEQmode;
15851 compare_result = gen_reg_rtx (CCEQmode);
15852 if (TARGET_64BIT)
15853 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15854 else
15855 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15857 else
15858 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15859 gen_rtx_COMPARE (comp_mode, op0, op1)));
15862 /* Some kinds of FP comparisons need an OR operation;
15863 under flag_finite_math_only we don't bother. */
15864 if (FLOAT_MODE_P (mode)
15865 && !flag_finite_math_only
15866 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15867 && (code == LE || code == GE
15868 || code == UNEQ || code == LTGT
15869 || code == UNGT || code == UNLT))
15871 enum rtx_code or1, or2;
15872 rtx or1_rtx, or2_rtx, compare2_rtx;
15873 rtx or_result = gen_reg_rtx (CCEQmode);
15875 switch (code)
15877 case LE: or1 = LT; or2 = EQ; break;
15878 case GE: or1 = GT; or2 = EQ; break;
15879 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
15880 case LTGT: or1 = LT; or2 = GT; break;
15881 case UNGT: or1 = UNORDERED; or2 = GT; break;
15882 case UNLT: or1 = UNORDERED; or2 = LT; break;
15883 default: gcc_unreachable ();
15885 validate_condition_mode (or1, comp_mode);
15886 validate_condition_mode (or2, comp_mode);
15887 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15888 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15889 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15890 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15891 const_true_rtx);
15892 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15894 compare_result = or_result;
15895 code = EQ;
15898 validate_condition_mode (code, GET_MODE (compare_result));
15900 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15904 /* Emit the RTL for an sISEL pattern. */
15906 void
15907 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15909 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15912 void
15913 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15915 rtx condition_rtx;
15916 enum machine_mode op_mode;
15917 enum rtx_code cond_code;
15918 rtx result = operands[0];
15920 if (TARGET_ISEL && (mode == SImode || mode == DImode))
15922 rs6000_emit_sISEL (mode, operands);
15923 return;
15926 condition_rtx = rs6000_generate_compare (operands[1], mode);
15927 cond_code = GET_CODE (condition_rtx);
15929 if (FLOAT_MODE_P (mode)
15930 && !TARGET_FPRS && TARGET_HARD_FLOAT)
15932 rtx t;
15934 PUT_MODE (condition_rtx, SImode);
15935 t = XEXP (condition_rtx, 0);
15937 gcc_assert (cond_code == NE || cond_code == EQ);
15939 if (cond_code == NE)
15940 emit_insn (gen_e500_flip_gt_bit (t, t));
15942 emit_insn (gen_move_from_CR_gt_bit (result, t));
15943 return;
15946 if (cond_code == NE
15947 || cond_code == GE || cond_code == LE
15948 || cond_code == GEU || cond_code == LEU
15949 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
15951 rtx not_result = gen_reg_rtx (CCEQmode);
15952 rtx not_op, rev_cond_rtx;
15953 enum machine_mode cc_mode;
15955 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
15957 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
15958 SImode, XEXP (condition_rtx, 0), const0_rtx);
15959 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
15960 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
15961 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
15964 op_mode = GET_MODE (XEXP (operands[1], 0));
15965 if (op_mode == VOIDmode)
15966 op_mode = GET_MODE (XEXP (operands[1], 1));
15968 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
15970 PUT_MODE (condition_rtx, DImode);
15971 convert_move (result, condition_rtx, 0);
15973 else
15975 PUT_MODE (condition_rtx, SImode);
15976 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
15980 /* Emit a branch of kind CODE to location LOC. */
15982 void
15983 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
15985 rtx condition_rtx, loc_ref;
15987 condition_rtx = rs6000_generate_compare (operands[0], mode);
15988 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
15989 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
15990 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
15991 loc_ref, pc_rtx)));
15994 /* Return the string to output a conditional branch to LABEL, which is
15995 the operand template of the label, or NULL if the branch is really a
15996 conditional return.
15998 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15999 condition code register and its mode specifies what kind of
16000 comparison we made.
16002 REVERSED is nonzero if we should reverse the sense of the comparison.
16004 INSN is the insn. */
16006 char *
16007 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
16009 static char string[64];
16010 enum rtx_code code = GET_CODE (op);
16011 rtx cc_reg = XEXP (op, 0);
16012 enum machine_mode mode = GET_MODE (cc_reg);
16013 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
16014 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
16015 int really_reversed = reversed ^ need_longbranch;
16016 char *s = string;
16017 const char *ccode;
16018 const char *pred;
16019 rtx note;
16021 validate_condition_mode (code, mode);
16023 /* Work out which way this really branches. We could use
16024 reverse_condition_maybe_unordered here always but this
16025 makes the resulting assembler clearer. */
16026 if (really_reversed)
16028 /* Reversal of FP compares takes care -- an ordered compare
16029 becomes an unordered compare and vice versa. */
16030 if (mode == CCFPmode)
16031 code = reverse_condition_maybe_unordered (code);
16032 else
16033 code = reverse_condition (code);
16036 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
16038 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
16039 to the GT bit. */
16040 switch (code)
16042 case EQ:
16043 /* Opposite of GT. */
16044 code = GT;
16045 break;
16047 case NE:
16048 code = UNLE;
16049 break;
16051 default:
16052 gcc_unreachable ();
16056 switch (code)
16058 /* Not all of these are actually distinct opcodes, but
16059 we distinguish them for clarity of the resulting assembler. */
16060 case NE: case LTGT:
16061 ccode = "ne"; break;
16062 case EQ: case UNEQ:
16063 ccode = "eq"; break;
16064 case GE: case GEU:
16065 ccode = "ge"; break;
16066 case GT: case GTU: case UNGT:
16067 ccode = "gt"; break;
16068 case LE: case LEU:
16069 ccode = "le"; break;
16070 case LT: case LTU: case UNLT:
16071 ccode = "lt"; break;
16072 case UNORDERED: ccode = "un"; break;
16073 case ORDERED: ccode = "nu"; break;
16074 case UNGE: ccode = "nl"; break;
16075 case UNLE: ccode = "ng"; break;
16076 default:
16077 gcc_unreachable ();
16080 /* Maybe we have a guess as to how likely the branch is. */
16081 pred = "";
16082 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
16083 if (note != NULL_RTX)
16085 /* PROB is the difference from 50%. */
16086 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
16088 /* Only hint for highly probable/improbable branches on newer
16089 cpus as static prediction overrides processor dynamic
16090 prediction. For older cpus we may as well always hint, but
16091 assume not taken for branches that are very close to 50% as a
16092 mispredicted taken branch is more expensive than a
16093 mispredicted not-taken branch. */
16094 if (rs6000_always_hint
16095 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
16096 && br_prob_note_reliable_p (note)))
16098 if (abs (prob) > REG_BR_PROB_BASE / 20
16099 && ((prob > 0) ^ need_longbranch))
16100 pred = "+";
16101 else
16102 pred = "-";
16106 if (label == NULL)
16107 s += sprintf (s, "b%slr%s ", ccode, pred);
16108 else
16109 s += sprintf (s, "b%s%s ", ccode, pred);
16111 /* We need to escape any '%' characters in the reg_names string.
16112 Assume they'd only be the first character.... */
16113 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
16114 *s++ = '%';
16115 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
16117 if (label != NULL)
16119 /* If the branch distance was too far, we may have to use an
16120 unconditional branch to go the distance. */
16121 if (need_longbranch)
16122 s += sprintf (s, ",$+8\n\tb %s", label);
16123 else
16124 s += sprintf (s, ",%s", label);
16127 return string;
16130 /* Return the string to flip the GT bit on a CR. */
16131 char *
16132 output_e500_flip_gt_bit (rtx dst, rtx src)
16134 static char string[64];
16135 int a, b;
16137 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
16138 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
16140 /* GT bit. */
16141 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
16142 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
16144 sprintf (string, "crnot %d,%d", a, b);
16145 return string;
16148 /* Return insn for VSX or Altivec comparisons. */
16150 static rtx
16151 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
16153 rtx mask;
16154 enum machine_mode mode = GET_MODE (op0);
16156 switch (code)
16158 default:
16159 break;
16161 case GE:
16162 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
16163 return NULL_RTX;
16165 case EQ:
16166 case GT:
16167 case GTU:
16168 case ORDERED:
16169 case UNORDERED:
16170 case UNEQ:
16171 case LTGT:
16172 mask = gen_reg_rtx (mode);
16173 emit_insn (gen_rtx_SET (VOIDmode,
16174 mask,
16175 gen_rtx_fmt_ee (code, mode, op0, op1)));
16176 return mask;
16179 return NULL_RTX;
16182 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16183 DMODE is expected destination mode. This is a recursive function. */
16185 static rtx
16186 rs6000_emit_vector_compare (enum rtx_code rcode,
16187 rtx op0, rtx op1,
16188 enum machine_mode dmode)
16190 rtx mask;
16191 bool swap_operands = false;
16192 bool try_again = false;
16194 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
16195 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
16197 /* See if the comparison works as is. */
16198 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16199 if (mask)
16200 return mask;
16202 switch (rcode)
16204 case LT:
16205 rcode = GT;
16206 swap_operands = true;
16207 try_again = true;
16208 break;
16209 case LTU:
16210 rcode = GTU;
16211 swap_operands = true;
16212 try_again = true;
16213 break;
16214 case NE:
16215 case UNLE:
16216 case UNLT:
16217 case UNGE:
16218 case UNGT:
16219 /* Invert condition and try again.
16220 e.g., A != B becomes ~(A==B). */
16222 enum rtx_code rev_code;
16223 enum insn_code nor_code;
16224 rtx mask2;
16226 rev_code = reverse_condition_maybe_unordered (rcode);
16227 if (rev_code == UNKNOWN)
16228 return NULL_RTX;
16230 nor_code = optab_handler (one_cmpl_optab, dmode);
16231 if (nor_code == CODE_FOR_nothing)
16232 return NULL_RTX;
16234 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
16235 if (!mask2)
16236 return NULL_RTX;
16238 mask = gen_reg_rtx (dmode);
16239 emit_insn (GEN_FCN (nor_code) (mask, mask2));
16240 return mask;
16242 break;
16243 case GE:
16244 case GEU:
16245 case LE:
16246 case LEU:
16247 /* Try GT/GTU/LT/LTU OR EQ */
16249 rtx c_rtx, eq_rtx;
16250 enum insn_code ior_code;
16251 enum rtx_code new_code;
16253 switch (rcode)
16255 case GE:
16256 new_code = GT;
16257 break;
16259 case GEU:
16260 new_code = GTU;
16261 break;
16263 case LE:
16264 new_code = LT;
16265 break;
16267 case LEU:
16268 new_code = LTU;
16269 break;
16271 default:
16272 gcc_unreachable ();
16275 ior_code = optab_handler (ior_optab, dmode);
16276 if (ior_code == CODE_FOR_nothing)
16277 return NULL_RTX;
16279 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
16280 if (!c_rtx)
16281 return NULL_RTX;
16283 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
16284 if (!eq_rtx)
16285 return NULL_RTX;
16287 mask = gen_reg_rtx (dmode);
16288 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16289 return mask;
16291 break;
16292 default:
16293 return NULL_RTX;
16296 if (try_again)
16298 if (swap_operands)
16300 rtx tmp;
16301 tmp = op0;
16302 op0 = op1;
16303 op1 = tmp;
16306 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16307 if (mask)
16308 return mask;
16311 /* You only get two chances. */
16312 return NULL_RTX;
16315 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16316 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16317 operands for the relation operation COND. */
16320 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16321 rtx cond, rtx cc_op0, rtx cc_op1)
16323 enum machine_mode dest_mode = GET_MODE (dest);
16324 enum machine_mode mask_mode = GET_MODE (cc_op0);
16325 enum rtx_code rcode = GET_CODE (cond);
16326 enum machine_mode cc_mode = CCmode;
16327 rtx mask;
16328 rtx cond2;
16329 rtx tmp;
16330 bool invert_move = false;
16332 if (VECTOR_UNIT_NONE_P (dest_mode))
16333 return 0;
16335 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16336 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16338 switch (rcode)
16340 /* Swap operands if we can, and fall back to doing the operation as
16341 specified, and doing a NOR to invert the test. */
16342 case NE:
16343 case UNLE:
16344 case UNLT:
16345 case UNGE:
16346 case UNGT:
16347 /* Invert condition and try again.
16348 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16349 invert_move = true;
16350 rcode = reverse_condition_maybe_unordered (rcode);
16351 if (rcode == UNKNOWN)
16352 return 0;
16353 break;
16355 /* Mark unsigned tests with CCUNSmode. */
16356 case GTU:
16357 case GEU:
16358 case LTU:
16359 case LEU:
16360 cc_mode = CCUNSmode;
16361 break;
16363 default:
16364 break;
16367 /* Get the vector mask for the given relational operations. */
16368 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16370 if (!mask)
16371 return 0;
16373 if (invert_move)
16375 tmp = op_true;
16376 op_true = op_false;
16377 op_false = tmp;
16380 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16381 CONST0_RTX (dest_mode));
16382 emit_insn (gen_rtx_SET (VOIDmode,
16383 dest,
16384 gen_rtx_IF_THEN_ELSE (dest_mode,
16385 cond2,
16386 op_true,
16387 op_false)));
16388 return 1;
16391 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16392 operands of the last comparison is nonzero/true, FALSE_COND if it
16393 is zero/false. Return 0 if the hardware has no such operation. */
16396 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16398 enum rtx_code code = GET_CODE (op);
16399 rtx op0 = XEXP (op, 0);
16400 rtx op1 = XEXP (op, 1);
16401 REAL_VALUE_TYPE c1;
16402 enum machine_mode compare_mode = GET_MODE (op0);
16403 enum machine_mode result_mode = GET_MODE (dest);
16404 rtx temp;
16405 bool is_against_zero;
16407 /* These modes should always match. */
16408 if (GET_MODE (op1) != compare_mode
16409 /* In the isel case however, we can use a compare immediate, so
16410 op1 may be a small constant. */
16411 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16412 return 0;
16413 if (GET_MODE (true_cond) != result_mode)
16414 return 0;
16415 if (GET_MODE (false_cond) != result_mode)
16416 return 0;
16418 /* Don't allow using floating point comparisons for integer results for
16419 now. */
16420 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
16421 return 0;
16423 /* First, work out if the hardware can do this at all, or
16424 if it's too slow.... */
16425 if (!FLOAT_MODE_P (compare_mode))
16427 if (TARGET_ISEL)
16428 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16429 return 0;
16431 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16432 && SCALAR_FLOAT_MODE_P (compare_mode))
16433 return 0;
16435 is_against_zero = op1 == CONST0_RTX (compare_mode);
16437 /* A floating-point subtract might overflow, underflow, or produce
16438 an inexact result, thus changing the floating-point flags, so it
16439 can't be generated if we care about that. It's safe if one side
16440 of the construct is zero, since then no subtract will be
16441 generated. */
16442 if (SCALAR_FLOAT_MODE_P (compare_mode)
16443 && flag_trapping_math && ! is_against_zero)
16444 return 0;
16446 /* Eliminate half of the comparisons by switching operands, this
16447 makes the remaining code simpler. */
16448 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16449 || code == LTGT || code == LT || code == UNLE)
16451 code = reverse_condition_maybe_unordered (code);
16452 temp = true_cond;
16453 true_cond = false_cond;
16454 false_cond = temp;
16457 /* UNEQ and LTGT take four instructions for a comparison with zero,
16458 it'll probably be faster to use a branch here too. */
16459 if (code == UNEQ && HONOR_NANS (compare_mode))
16460 return 0;
16462 if (GET_CODE (op1) == CONST_DOUBLE)
16463 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16465 /* We're going to try to implement comparisons by performing
16466 a subtract, then comparing against zero. Unfortunately,
16467 Inf - Inf is NaN which is not zero, and so if we don't
16468 know that the operand is finite and the comparison
16469 would treat EQ different to UNORDERED, we can't do it. */
16470 if (HONOR_INFINITIES (compare_mode)
16471 && code != GT && code != UNGE
16472 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16473 /* Constructs of the form (a OP b ? a : b) are safe. */
16474 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16475 || (! rtx_equal_p (op0, true_cond)
16476 && ! rtx_equal_p (op1, true_cond))))
16477 return 0;
16479 /* At this point we know we can use fsel. */
16481 /* Reduce the comparison to a comparison against zero. */
16482 if (! is_against_zero)
16484 temp = gen_reg_rtx (compare_mode);
16485 emit_insn (gen_rtx_SET (VOIDmode, temp,
16486 gen_rtx_MINUS (compare_mode, op0, op1)));
16487 op0 = temp;
16488 op1 = CONST0_RTX (compare_mode);
16491 /* If we don't care about NaNs we can reduce some of the comparisons
16492 down to faster ones. */
16493 if (! HONOR_NANS (compare_mode))
16494 switch (code)
16496 case GT:
16497 code = LE;
16498 temp = true_cond;
16499 true_cond = false_cond;
16500 false_cond = temp;
16501 break;
16502 case UNGE:
16503 code = GE;
16504 break;
16505 case UNEQ:
16506 code = EQ;
16507 break;
16508 default:
16509 break;
16512 /* Now, reduce everything down to a GE. */
16513 switch (code)
16515 case GE:
16516 break;
16518 case LE:
16519 temp = gen_reg_rtx (compare_mode);
16520 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16521 op0 = temp;
16522 break;
16524 case ORDERED:
16525 temp = gen_reg_rtx (compare_mode);
16526 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16527 op0 = temp;
16528 break;
16530 case EQ:
16531 temp = gen_reg_rtx (compare_mode);
16532 emit_insn (gen_rtx_SET (VOIDmode, temp,
16533 gen_rtx_NEG (compare_mode,
16534 gen_rtx_ABS (compare_mode, op0))));
16535 op0 = temp;
16536 break;
16538 case UNGE:
16539 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16540 temp = gen_reg_rtx (result_mode);
16541 emit_insn (gen_rtx_SET (VOIDmode, temp,
16542 gen_rtx_IF_THEN_ELSE (result_mode,
16543 gen_rtx_GE (VOIDmode,
16544 op0, op1),
16545 true_cond, false_cond)));
16546 false_cond = true_cond;
16547 true_cond = temp;
16549 temp = gen_reg_rtx (compare_mode);
16550 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16551 op0 = temp;
16552 break;
16554 case GT:
16555 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16556 temp = gen_reg_rtx (result_mode);
16557 emit_insn (gen_rtx_SET (VOIDmode, temp,
16558 gen_rtx_IF_THEN_ELSE (result_mode,
16559 gen_rtx_GE (VOIDmode,
16560 op0, op1),
16561 true_cond, false_cond)));
16562 true_cond = false_cond;
16563 false_cond = temp;
16565 temp = gen_reg_rtx (compare_mode);
16566 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16567 op0 = temp;
16568 break;
16570 default:
16571 gcc_unreachable ();
16574 emit_insn (gen_rtx_SET (VOIDmode, dest,
16575 gen_rtx_IF_THEN_ELSE (result_mode,
16576 gen_rtx_GE (VOIDmode,
16577 op0, op1),
16578 true_cond, false_cond)));
16579 return 1;
16582 /* Same as above, but for ints (isel). */
16584 static int
16585 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16587 rtx condition_rtx, cr;
16588 enum machine_mode mode = GET_MODE (dest);
16589 enum rtx_code cond_code;
16590 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16591 bool signedp;
16593 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16594 return 0;
16596 /* We still have to do the compare, because isel doesn't do a
16597 compare, it just looks at the CRx bits set by a previous compare
16598 instruction. */
16599 condition_rtx = rs6000_generate_compare (op, mode);
16600 cond_code = GET_CODE (condition_rtx);
16601 cr = XEXP (condition_rtx, 0);
16602 signedp = GET_MODE (cr) == CCmode;
16604 isel_func = (mode == SImode
16605 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16606 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16608 switch (cond_code)
16610 case LT: case GT: case LTU: case GTU: case EQ:
16611 /* isel handles these directly. */
16612 break;
16614 default:
16615 /* We need to swap the sense of the comparison. */
16617 rtx t = true_cond;
16618 true_cond = false_cond;
16619 false_cond = t;
16620 PUT_CODE (condition_rtx, reverse_condition (cond_code));
16622 break;
16625 false_cond = force_reg (mode, false_cond);
16626 if (true_cond != const0_rtx)
16627 true_cond = force_reg (mode, true_cond);
16629 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16631 return 1;
16634 const char *
16635 output_isel (rtx *operands)
16637 enum rtx_code code;
16639 code = GET_CODE (operands[1]);
16641 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16643 gcc_assert (GET_CODE (operands[2]) == REG
16644 && GET_CODE (operands[3]) == REG);
16645 PUT_CODE (operands[1], reverse_condition (code));
16646 return "isel %0,%3,%2,%j1";
16649 return "isel %0,%2,%3,%j1";
16652 void
16653 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16655 enum machine_mode mode = GET_MODE (op0);
16656 enum rtx_code c;
16657 rtx target;
16659 /* VSX/altivec have direct min/max insns. */
16660 if ((code == SMAX || code == SMIN)
16661 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16662 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16664 emit_insn (gen_rtx_SET (VOIDmode,
16665 dest,
16666 gen_rtx_fmt_ee (code, mode, op0, op1)));
16667 return;
16670 if (code == SMAX || code == SMIN)
16671 c = GE;
16672 else
16673 c = GEU;
16675 if (code == SMAX || code == UMAX)
16676 target = emit_conditional_move (dest, c, op0, op1, mode,
16677 op0, op1, mode, 0);
16678 else
16679 target = emit_conditional_move (dest, c, op0, op1, mode,
16680 op1, op0, mode, 0);
16681 gcc_assert (target);
16682 if (target != dest)
16683 emit_move_insn (dest, target);
16686 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16687 COND is true. Mark the jump as unlikely to be taken. */
16689 static void
16690 emit_unlikely_jump (rtx cond, rtx label)
16692 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16693 rtx x;
16695 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16696 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16697 add_reg_note (x, REG_BR_PROB, very_unlikely);
16700 /* A subroutine of the atomic operation splitters. Emit a load-locked
16701 instruction in MODE. */
16703 static void
16704 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16706 rtx (*fn) (rtx, rtx) = NULL;
16708 switch (mode)
16710 case SImode:
16711 fn = gen_load_lockedsi;
16712 break;
16713 case DImode:
16714 fn = gen_load_lockeddi;
16715 break;
16716 default:
16717 gcc_unreachable ();
16719 emit_insn (fn (reg, mem));
16722 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16723 instruction in MODE. */
16725 static void
16726 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16728 rtx (*fn) (rtx, rtx, rtx) = NULL;
16730 switch (mode)
16732 case SImode:
16733 fn = gen_store_conditionalsi;
16734 break;
16735 case DImode:
16736 fn = gen_store_conditionaldi;
16737 break;
16738 default:
16739 gcc_unreachable ();
16742 /* Emit sync before stwcx. to address PPC405 Erratum. */
16743 if (PPC405_ERRATUM77)
16744 emit_insn (gen_hwsync ());
16746 emit_insn (fn (res, mem, val));
16749 /* Expand barriers before and after a load_locked/store_cond sequence. */
16751 static rtx
16752 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
16754 rtx addr = XEXP (mem, 0);
16755 int strict_p = (reload_in_progress || reload_completed);
16757 if (!legitimate_indirect_address_p (addr, strict_p)
16758 && !legitimate_indexed_address_p (addr, strict_p))
16760 addr = force_reg (Pmode, addr);
16761 mem = replace_equiv_address_nv (mem, addr);
16764 switch (model)
16766 case MEMMODEL_RELAXED:
16767 case MEMMODEL_CONSUME:
16768 case MEMMODEL_ACQUIRE:
16769 break;
16770 case MEMMODEL_RELEASE:
16771 case MEMMODEL_ACQ_REL:
16772 emit_insn (gen_lwsync ());
16773 break;
16774 case MEMMODEL_SEQ_CST:
16775 emit_insn (gen_hwsync ());
16776 break;
16777 default:
16778 gcc_unreachable ();
16780 return mem;
16783 static void
16784 rs6000_post_atomic_barrier (enum memmodel model)
16786 switch (model)
16788 case MEMMODEL_RELAXED:
16789 case MEMMODEL_CONSUME:
16790 case MEMMODEL_RELEASE:
16791 break;
16792 case MEMMODEL_ACQUIRE:
16793 case MEMMODEL_ACQ_REL:
16794 case MEMMODEL_SEQ_CST:
16795 emit_insn (gen_isync ());
16796 break;
16797 default:
16798 gcc_unreachable ();
16802 /* A subroutine of the various atomic expanders. For sub-word operations,
16803 we must adjust things to operate on SImode. Given the original MEM,
16804 return a new aligned memory. Also build and return the quantities by
16805 which to shift and mask. */
16807 static rtx
16808 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16810 rtx addr, align, shift, mask, mem;
16811 HOST_WIDE_INT shift_mask;
16812 enum machine_mode mode = GET_MODE (orig_mem);
16814 /* For smaller modes, we have to implement this via SImode. */
16815 shift_mask = (mode == QImode ? 0x18 : 0x10);
16817 addr = XEXP (orig_mem, 0);
16818 addr = force_reg (GET_MODE (addr), addr);
16820 /* Aligned memory containing subword. Generate a new memory. We
16821 do not want any of the existing MEM_ATTR data, as we're now
16822 accessing memory outside the original object. */
16823 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16824 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16825 mem = gen_rtx_MEM (SImode, align);
16826 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16827 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16828 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16830 /* Shift amount for subword relative to aligned word. */
16831 shift = gen_reg_rtx (SImode);
16832 addr = gen_lowpart (SImode, addr);
16833 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16834 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16835 shift, 1, OPTAB_LIB_WIDEN);
16836 *pshift = shift;
16838 /* Mask for insertion. */
16839 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16840 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16841 *pmask = mask;
16843 return mem;
16846 /* A subroutine of the various atomic expanders. For sub-word operands,
16847 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16849 static rtx
16850 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16852 rtx x;
16854 x = gen_reg_rtx (SImode);
16855 emit_insn (gen_rtx_SET (VOIDmode, x,
16856 gen_rtx_AND (SImode,
16857 gen_rtx_NOT (SImode, mask),
16858 oldval)));
16860 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16862 return x;
16865 /* A subroutine of the various atomic expanders. For sub-word operands,
16866 extract WIDE to NARROW via SHIFT. */
16868 static void
16869 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16871 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16872 wide, 1, OPTAB_LIB_WIDEN);
16873 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16876 /* Expand an atomic compare and swap operation. */
16878 void
16879 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16881 rtx boolval, retval, mem, oldval, newval, cond;
16882 rtx label1, label2, x, mask, shift;
16883 enum machine_mode mode;
16884 enum memmodel mod_s, mod_f;
16885 bool is_weak;
16887 boolval = operands[0];
16888 retval = operands[1];
16889 mem = operands[2];
16890 oldval = operands[3];
16891 newval = operands[4];
16892 is_weak = (INTVAL (operands[5]) != 0);
16893 mod_s = (enum memmodel) INTVAL (operands[6]);
16894 mod_f = (enum memmodel) INTVAL (operands[7]);
16895 mode = GET_MODE (mem);
16897 mask = shift = NULL_RTX;
16898 if (mode == QImode || mode == HImode)
16900 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16902 /* Shift and mask OLDVAL into position with the word. */
16903 oldval = convert_modes (SImode, mode, oldval, 1);
16904 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16905 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16907 /* Shift and mask NEWVAL into position within the word. */
16908 newval = convert_modes (SImode, mode, newval, 1);
16909 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16910 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16912 /* Prepare to adjust the return value. */
16913 retval = gen_reg_rtx (SImode);
16914 mode = SImode;
16916 else if (reg_overlap_mentioned_p (retval, oldval))
16917 oldval = copy_to_reg (oldval);
16919 mem = rs6000_pre_atomic_barrier (mem, mod_s);
16921 label1 = NULL_RTX;
16922 if (!is_weak)
16924 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16925 emit_label (XEXP (label1, 0));
16927 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16929 emit_load_locked (mode, retval, mem);
16931 x = retval;
16932 if (mask)
16934 x = expand_simple_binop (SImode, AND, retval, mask,
16935 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16938 cond = gen_reg_rtx (CCmode);
16939 x = gen_rtx_COMPARE (CCmode, x, oldval);
16940 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
16942 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16943 emit_unlikely_jump (x, label2);
16945 x = newval;
16946 if (mask)
16947 x = rs6000_mask_atomic_subword (retval, newval, mask);
16949 emit_store_conditional (mode, cond, mem, x);
16951 if (!is_weak)
16953 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16954 emit_unlikely_jump (x, label1);
16957 if (mod_f != MEMMODEL_RELAXED)
16958 emit_label (XEXP (label2, 0));
16960 rs6000_post_atomic_barrier (mod_s);
16962 if (mod_f == MEMMODEL_RELAXED)
16963 emit_label (XEXP (label2, 0));
16965 if (shift)
16966 rs6000_finish_atomic_subword (operands[1], retval, shift);
16968 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16969 x = gen_rtx_EQ (SImode, cond, const0_rtx);
16970 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
16973 /* Expand an atomic exchange operation. */
16975 void
16976 rs6000_expand_atomic_exchange (rtx operands[])
16978 rtx retval, mem, val, cond;
16979 enum machine_mode mode;
16980 enum memmodel model;
16981 rtx label, x, mask, shift;
16983 retval = operands[0];
16984 mem = operands[1];
16985 val = operands[2];
16986 model = (enum memmodel) INTVAL (operands[3]);
16987 mode = GET_MODE (mem);
16989 mask = shift = NULL_RTX;
16990 if (mode == QImode || mode == HImode)
16992 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16994 /* Shift and mask VAL into position with the word. */
16995 val = convert_modes (SImode, mode, val, 1);
16996 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16997 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16999 /* Prepare to adjust the return value. */
17000 retval = gen_reg_rtx (SImode);
17001 mode = SImode;
17004 mem = rs6000_pre_atomic_barrier (mem, model);
17006 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
17007 emit_label (XEXP (label, 0));
17009 emit_load_locked (mode, retval, mem);
17011 x = val;
17012 if (mask)
17013 x = rs6000_mask_atomic_subword (retval, val, mask);
17015 cond = gen_reg_rtx (CCmode);
17016 emit_store_conditional (mode, cond, mem, x);
17018 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17019 emit_unlikely_jump (x, label);
17021 rs6000_post_atomic_barrier (model);
17023 if (shift)
17024 rs6000_finish_atomic_subword (operands[0], retval, shift);
17027 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
17028 to perform. MEM is the memory on which to operate. VAL is the second
17029 operand of the binary operator. BEFORE and AFTER are optional locations to
17030 return the value of MEM either before of after the operation. MODEL_RTX
17031 is a CONST_INT containing the memory model to use. */
17033 void
17034 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
17035 rtx orig_before, rtx orig_after, rtx model_rtx)
17037 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
17038 enum machine_mode mode = GET_MODE (mem);
17039 rtx label, x, cond, mask, shift;
17040 rtx before = orig_before, after = orig_after;
17042 mask = shift = NULL_RTX;
17043 if (mode == QImode || mode == HImode)
17045 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
17047 /* Shift and mask VAL into position with the word. */
17048 val = convert_modes (SImode, mode, val, 1);
17049 val = expand_simple_binop (SImode, ASHIFT, val, shift,
17050 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17052 switch (code)
17054 case IOR:
17055 case XOR:
17056 /* We've already zero-extended VAL. That is sufficient to
17057 make certain that it does not affect other bits. */
17058 mask = NULL;
17059 break;
17061 case AND:
17062 /* If we make certain that all of the other bits in VAL are
17063 set, that will be sufficient to not affect other bits. */
17064 x = gen_rtx_NOT (SImode, mask);
17065 x = gen_rtx_IOR (SImode, x, val);
17066 emit_insn (gen_rtx_SET (VOIDmode, val, x));
17067 mask = NULL;
17068 break;
17070 case NOT:
17071 case PLUS:
17072 case MINUS:
17073 /* These will all affect bits outside the field and need
17074 adjustment via MASK within the loop. */
17075 break;
17077 default:
17078 gcc_unreachable ();
17081 /* Prepare to adjust the return value. */
17082 before = gen_reg_rtx (SImode);
17083 if (after)
17084 after = gen_reg_rtx (SImode);
17085 mode = SImode;
17088 mem = rs6000_pre_atomic_barrier (mem, model);
17090 label = gen_label_rtx ();
17091 emit_label (label);
17092 label = gen_rtx_LABEL_REF (VOIDmode, label);
17094 if (before == NULL_RTX)
17095 before = gen_reg_rtx (mode);
17097 emit_load_locked (mode, before, mem);
17099 if (code == NOT)
17101 x = expand_simple_binop (mode, AND, before, val,
17102 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17103 after = expand_simple_unop (mode, NOT, x, after, 1);
17105 else
17107 after = expand_simple_binop (mode, code, before, val,
17108 after, 1, OPTAB_LIB_WIDEN);
17111 x = after;
17112 if (mask)
17114 x = expand_simple_binop (SImode, AND, after, mask,
17115 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17116 x = rs6000_mask_atomic_subword (before, x, mask);
17119 cond = gen_reg_rtx (CCmode);
17120 emit_store_conditional (mode, cond, mem, x);
17122 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17123 emit_unlikely_jump (x, label);
17125 rs6000_post_atomic_barrier (model);
17127 if (shift)
17129 if (orig_before)
17130 rs6000_finish_atomic_subword (orig_before, before, shift);
17131 if (orig_after)
17132 rs6000_finish_atomic_subword (orig_after, after, shift);
17134 else if (orig_after && after != orig_after)
17135 emit_move_insn (orig_after, after);
17138 /* Emit instructions to move SRC to DST. Called by splitters for
17139 multi-register moves. It will emit at most one instruction for
17140 each register that is accessed; that is, it won't emit li/lis pairs
17141 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17142 register. */
17144 void
17145 rs6000_split_multireg_move (rtx dst, rtx src)
17147 /* The register number of the first register being moved. */
17148 int reg;
17149 /* The mode that is to be moved. */
17150 enum machine_mode mode;
17151 /* The mode that the move is being done in, and its size. */
17152 enum machine_mode reg_mode;
17153 int reg_mode_size;
17154 /* The number of registers that will be moved. */
17155 int nregs;
17157 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
17158 mode = GET_MODE (dst);
17159 nregs = hard_regno_nregs[reg][mode];
17160 if (FP_REGNO_P (reg))
17161 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
17162 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
17163 else if (ALTIVEC_REGNO_P (reg))
17164 reg_mode = V16QImode;
17165 else if (TARGET_E500_DOUBLE && mode == TFmode)
17166 reg_mode = DFmode;
17167 else
17168 reg_mode = word_mode;
17169 reg_mode_size = GET_MODE_SIZE (reg_mode);
17171 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
17173 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
17175 /* Move register range backwards, if we might have destructive
17176 overlap. */
17177 int i;
17178 for (i = nregs - 1; i >= 0; i--)
17179 emit_insn (gen_rtx_SET (VOIDmode,
17180 simplify_gen_subreg (reg_mode, dst, mode,
17181 i * reg_mode_size),
17182 simplify_gen_subreg (reg_mode, src, mode,
17183 i * reg_mode_size)));
17185 else
17187 int i;
17188 int j = -1;
17189 bool used_update = false;
17190 rtx restore_basereg = NULL_RTX;
17192 if (MEM_P (src) && INT_REGNO_P (reg))
17194 rtx breg;
17196 if (GET_CODE (XEXP (src, 0)) == PRE_INC
17197 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
17199 rtx delta_rtx;
17200 breg = XEXP (XEXP (src, 0), 0);
17201 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
17202 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
17203 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
17204 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17205 src = replace_equiv_address (src, breg);
17207 else if (! rs6000_offsettable_memref_p (src, reg_mode))
17209 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
17211 rtx basereg = XEXP (XEXP (src, 0), 0);
17212 if (TARGET_UPDATE)
17214 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
17215 emit_insn (gen_rtx_SET (VOIDmode, ndst,
17216 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
17217 used_update = true;
17219 else
17220 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17221 XEXP (XEXP (src, 0), 1)));
17222 src = replace_equiv_address (src, basereg);
17224 else
17226 rtx basereg = gen_rtx_REG (Pmode, reg);
17227 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
17228 src = replace_equiv_address (src, basereg);
17232 breg = XEXP (src, 0);
17233 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
17234 breg = XEXP (breg, 0);
17236 /* If the base register we are using to address memory is
17237 also a destination reg, then change that register last. */
17238 if (REG_P (breg)
17239 && REGNO (breg) >= REGNO (dst)
17240 && REGNO (breg) < REGNO (dst) + nregs)
17241 j = REGNO (breg) - REGNO (dst);
17243 else if (MEM_P (dst) && INT_REGNO_P (reg))
17245 rtx breg;
17247 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
17248 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
17250 rtx delta_rtx;
17251 breg = XEXP (XEXP (dst, 0), 0);
17252 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
17253 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
17254 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
17256 /* We have to update the breg before doing the store.
17257 Use store with update, if available. */
17259 if (TARGET_UPDATE)
17261 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17262 emit_insn (TARGET_32BIT
17263 ? (TARGET_POWERPC64
17264 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
17265 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
17266 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
17267 used_update = true;
17269 else
17270 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17271 dst = replace_equiv_address (dst, breg);
17273 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
17274 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
17276 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
17278 rtx basereg = XEXP (XEXP (dst, 0), 0);
17279 if (TARGET_UPDATE)
17281 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17282 emit_insn (gen_rtx_SET (VOIDmode,
17283 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
17284 used_update = true;
17286 else
17287 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17288 XEXP (XEXP (dst, 0), 1)));
17289 dst = replace_equiv_address (dst, basereg);
17291 else
17293 rtx basereg = XEXP (XEXP (dst, 0), 0);
17294 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
17295 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
17296 && REG_P (basereg)
17297 && REG_P (offsetreg)
17298 && REGNO (basereg) != REGNO (offsetreg));
17299 if (REGNO (basereg) == 0)
17301 rtx tmp = offsetreg;
17302 offsetreg = basereg;
17303 basereg = tmp;
17305 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
17306 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
17307 dst = replace_equiv_address (dst, basereg);
17310 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
17311 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
17314 for (i = 0; i < nregs; i++)
17316 /* Calculate index to next subword. */
17317 ++j;
17318 if (j == nregs)
17319 j = 0;
17321 /* If compiler already emitted move of first word by
17322 store with update, no need to do anything. */
17323 if (j == 0 && used_update)
17324 continue;
17326 emit_insn (gen_rtx_SET (VOIDmode,
17327 simplify_gen_subreg (reg_mode, dst, mode,
17328 j * reg_mode_size),
17329 simplify_gen_subreg (reg_mode, src, mode,
17330 j * reg_mode_size)));
17332 if (restore_basereg != NULL_RTX)
17333 emit_insn (restore_basereg);
17338 /* This page contains routines that are used to determine what the
17339 function prologue and epilogue code will do and write them out. */
17341 static inline bool
17342 save_reg_p (int r)
17344 return !call_used_regs[r] && df_regs_ever_live_p (r);
17347 /* Return the first fixed-point register that is required to be
17348 saved. 32 if none. */
17351 first_reg_to_save (void)
17353 int first_reg;
17355 /* Find lowest numbered live register. */
17356 for (first_reg = 13; first_reg <= 31; first_reg++)
17357 if (save_reg_p (first_reg))
17358 break;
17360 if (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM
17361 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17362 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17363 || (TARGET_TOC && TARGET_MINIMAL_TOC))
17364 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
17365 first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM;
17367 #if TARGET_MACHO
17368 if (flag_pic
17369 && crtl->uses_pic_offset_table
17370 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17371 return RS6000_PIC_OFFSET_TABLE_REGNUM;
17372 #endif
17374 return first_reg;
17377 /* Similar, for FP regs. */
17380 first_fp_reg_to_save (void)
17382 int first_reg;
17384 /* Find lowest numbered live register. */
17385 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17386 if (save_reg_p (first_reg))
17387 break;
17389 return first_reg;
17392 /* Similar, for AltiVec regs. */
17394 static int
17395 first_altivec_reg_to_save (void)
17397 int i;
17399 /* Stack frame remains as is unless we are in AltiVec ABI. */
17400 if (! TARGET_ALTIVEC_ABI)
17401 return LAST_ALTIVEC_REGNO + 1;
17403 /* On Darwin, the unwind routines are compiled without
17404 TARGET_ALTIVEC, and use save_world to save/restore the
17405 altivec registers when necessary. */
17406 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17407 && ! TARGET_ALTIVEC)
17408 return FIRST_ALTIVEC_REGNO + 20;
17410 /* Find lowest numbered live register. */
17411 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17412 if (save_reg_p (i))
17413 break;
17415 return i;
17418 /* Return a 32-bit mask of the AltiVec registers we need to set in
17419 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17420 the 32-bit word is 0. */
17422 static unsigned int
17423 compute_vrsave_mask (void)
17425 unsigned int i, mask = 0;
17427 /* On Darwin, the unwind routines are compiled without
17428 TARGET_ALTIVEC, and use save_world to save/restore the
17429 call-saved altivec registers when necessary. */
17430 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17431 && ! TARGET_ALTIVEC)
17432 mask |= 0xFFF;
17434 /* First, find out if we use _any_ altivec registers. */
17435 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17436 if (df_regs_ever_live_p (i))
17437 mask |= ALTIVEC_REG_BIT (i);
17439 if (mask == 0)
17440 return mask;
17442 /* Next, remove the argument registers from the set. These must
17443 be in the VRSAVE mask set by the caller, so we don't need to add
17444 them in again. More importantly, the mask we compute here is
17445 used to generate CLOBBERs in the set_vrsave insn, and we do not
17446 wish the argument registers to die. */
17447 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17448 mask &= ~ALTIVEC_REG_BIT (i);
17450 /* Similarly, remove the return value from the set. */
17452 bool yes = false;
17453 diddle_return_value (is_altivec_return_reg, &yes);
17454 if (yes)
17455 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17458 return mask;
17461 /* For a very restricted set of circumstances, we can cut down the
17462 size of prologues/epilogues by calling our own save/restore-the-world
17463 routines. */
17465 static void
17466 compute_save_world_info (rs6000_stack_t *info_ptr)
17468 info_ptr->world_save_p = 1;
17469 info_ptr->world_save_p
17470 = (WORLD_SAVE_P (info_ptr)
17471 && DEFAULT_ABI == ABI_DARWIN
17472 && !cfun->has_nonlocal_label
17473 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17474 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17475 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17476 && info_ptr->cr_save_p);
17478 /* This will not work in conjunction with sibcalls. Make sure there
17479 are none. (This check is expensive, but seldom executed.) */
17480 if (WORLD_SAVE_P (info_ptr))
17482 rtx insn;
17483 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17484 if ( GET_CODE (insn) == CALL_INSN
17485 && SIBLING_CALL_P (insn))
17487 info_ptr->world_save_p = 0;
17488 break;
17492 if (WORLD_SAVE_P (info_ptr))
17494 /* Even if we're not touching VRsave, make sure there's room on the
17495 stack for it, if it looks like we're calling SAVE_WORLD, which
17496 will attempt to save it. */
17497 info_ptr->vrsave_size = 4;
17499 /* If we are going to save the world, we need to save the link register too. */
17500 info_ptr->lr_save_p = 1;
17502 /* "Save" the VRsave register too if we're saving the world. */
17503 if (info_ptr->vrsave_mask == 0)
17504 info_ptr->vrsave_mask = compute_vrsave_mask ();
17506 /* Because the Darwin register save/restore routines only handle
17507 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17508 check. */
17509 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17510 && (info_ptr->first_altivec_reg_save
17511 >= FIRST_SAVED_ALTIVEC_REGNO));
17513 return;
17517 static void
17518 is_altivec_return_reg (rtx reg, void *xyes)
17520 bool *yes = (bool *) xyes;
17521 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17522 *yes = true;
17526 /* Look for user-defined global regs in the range FIRST to LAST-1.
17527 We should not restore these, and so cannot use lmw or out-of-line
17528 restore functions if there are any. We also can't save them
17529 (well, emit frame notes for them), because frame unwinding during
17530 exception handling will restore saved registers. */
17532 static bool
17533 global_regs_p (unsigned first, unsigned last)
17535 while (first < last)
17536 if (global_regs[first++])
17537 return true;
17538 return false;
17541 /* Determine the strategy for savings/restoring registers. */
17543 enum {
17544 SAVRES_MULTIPLE = 0x1,
17545 SAVE_INLINE_FPRS = 0x2,
17546 SAVE_INLINE_GPRS = 0x4,
17547 REST_INLINE_FPRS = 0x8,
17548 REST_INLINE_GPRS = 0x10,
17549 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17550 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17551 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80,
17552 SAVE_INLINE_VRS = 0x100,
17553 REST_INLINE_VRS = 0x200
17556 static int
17557 rs6000_savres_strategy (rs6000_stack_t *info,
17558 bool using_static_chain_p)
17560 int strategy = 0;
17561 bool lr_save_p;
17563 if (TARGET_MULTIPLE
17564 && !TARGET_POWERPC64
17565 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17566 && info->first_gp_reg_save < 31
17567 && !global_regs_p (info->first_gp_reg_save, 32))
17568 strategy |= SAVRES_MULTIPLE;
17570 if (crtl->calls_eh_return
17571 || cfun->machine->ra_need_lr)
17572 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17573 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
17574 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17576 if (info->first_fp_reg_save == 64
17577 /* The out-of-line FP routines use double-precision stores;
17578 we can't use those routines if we don't have such stores. */
17579 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17580 || global_regs_p (info->first_fp_reg_save, 64))
17581 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17583 if (info->first_gp_reg_save == 32
17584 || (!(strategy & SAVRES_MULTIPLE)
17585 && global_regs_p (info->first_gp_reg_save, 32)))
17586 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17588 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
17589 || global_regs_p (info->first_altivec_reg_save, LAST_ALTIVEC_REGNO + 1))
17590 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17592 /* Define cutoff for using out-of-line functions to save registers. */
17593 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
17595 if (!optimize_size)
17597 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17598 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17599 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17601 else
17603 /* Prefer out-of-line restore if it will exit. */
17604 if (info->first_fp_reg_save > 61)
17605 strategy |= SAVE_INLINE_FPRS;
17606 if (info->first_gp_reg_save > 29)
17608 if (info->first_fp_reg_save == 64)
17609 strategy |= SAVE_INLINE_GPRS;
17610 else
17611 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17613 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
17614 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17617 else if (DEFAULT_ABI == ABI_DARWIN)
17619 if (info->first_fp_reg_save > 60)
17620 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17621 if (info->first_gp_reg_save > 29)
17622 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17623 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17625 else
17627 gcc_checking_assert (DEFAULT_ABI == ABI_AIX);
17628 if (info->first_fp_reg_save > 61)
17629 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17630 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17631 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
17634 /* Don't bother to try to save things out-of-line if r11 is occupied
17635 by the static chain. It would require too much fiddling and the
17636 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17637 pointer on Darwin, and AIX uses r1 or r12. */
17638 if (using_static_chain_p && DEFAULT_ABI != ABI_AIX)
17639 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
17640 | SAVE_INLINE_GPRS
17641 | SAVE_INLINE_VRS | REST_INLINE_VRS);
17643 /* We can only use the out-of-line routines to restore if we've
17644 saved all the registers from first_fp_reg_save in the prologue.
17645 Otherwise, we risk loading garbage. */
17646 if ((strategy & (SAVE_INLINE_FPRS | REST_INLINE_FPRS)) == SAVE_INLINE_FPRS)
17648 int i;
17650 for (i = info->first_fp_reg_save; i < 64; i++)
17651 if (!save_reg_p (i))
17653 strategy |= REST_INLINE_FPRS;
17654 break;
17658 /* If we are going to use store multiple, then don't even bother
17659 with the out-of-line routines, since the store-multiple
17660 instruction will always be smaller. */
17661 if ((strategy & SAVRES_MULTIPLE))
17662 strategy |= SAVE_INLINE_GPRS;
17664 /* info->lr_save_p isn't yet set if the only reason lr needs to be
17665 saved is an out-of-line save or restore. Set up the value for
17666 the next test (excluding out-of-line gpr restore). */
17667 lr_save_p = (info->lr_save_p
17668 || !(strategy & SAVE_INLINE_GPRS)
17669 || !(strategy & SAVE_INLINE_FPRS)
17670 || !(strategy & SAVE_INLINE_VRS)
17671 || !(strategy & REST_INLINE_FPRS)
17672 || !(strategy & REST_INLINE_VRS));
17674 /* The situation is more complicated with load multiple. We'd
17675 prefer to use the out-of-line routines for restores, since the
17676 "exit" out-of-line routines can handle the restore of LR and the
17677 frame teardown. However if doesn't make sense to use the
17678 out-of-line routine if that is the only reason we'd need to save
17679 LR, and we can't use the "exit" out-of-line gpr restore if we
17680 have saved some fprs; In those cases it is advantageous to use
17681 load multiple when available. */
17682 if ((strategy & SAVRES_MULTIPLE)
17683 && (!lr_save_p
17684 || info->first_fp_reg_save != 64))
17685 strategy |= REST_INLINE_GPRS;
17687 /* Saving CR interferes with the exit routines used on the SPE, so
17688 just punt here. */
17689 if (TARGET_SPE_ABI
17690 && info->spe_64bit_regs_used
17691 && info->cr_save_p)
17692 strategy |= REST_INLINE_GPRS;
17694 /* We can only use load multiple or the out-of-line routines to
17695 restore if we've used store multiple or out-of-line routines
17696 in the prologue, i.e. if we've saved all the registers from
17697 first_gp_reg_save. Otherwise, we risk loading garbage. */
17698 if ((strategy & (SAVE_INLINE_GPRS | REST_INLINE_GPRS | SAVRES_MULTIPLE))
17699 == SAVE_INLINE_GPRS)
17701 int i;
17703 for (i = info->first_gp_reg_save; i < 32; i++)
17704 if (!save_reg_p (i))
17706 strategy |= REST_INLINE_GPRS;
17707 break;
17711 if (TARGET_ELF && TARGET_64BIT)
17713 if (!(strategy & SAVE_INLINE_FPRS))
17714 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17715 else if (!(strategy & SAVE_INLINE_GPRS)
17716 && info->first_fp_reg_save == 64)
17717 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17719 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17720 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17722 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17723 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17725 return strategy;
17728 /* Calculate the stack information for the current function. This is
17729 complicated by having two separate calling sequences, the AIX calling
17730 sequence and the V.4 calling sequence.
17732 AIX (and Darwin/Mac OS X) stack frames look like:
17733 32-bit 64-bit
17734 SP----> +---------------------------------------+
17735 | back chain to caller | 0 0
17736 +---------------------------------------+
17737 | saved CR | 4 8 (8-11)
17738 +---------------------------------------+
17739 | saved LR | 8 16
17740 +---------------------------------------+
17741 | reserved for compilers | 12 24
17742 +---------------------------------------+
17743 | reserved for binders | 16 32
17744 +---------------------------------------+
17745 | saved TOC pointer | 20 40
17746 +---------------------------------------+
17747 | Parameter save area (P) | 24 48
17748 +---------------------------------------+
17749 | Alloca space (A) | 24+P etc.
17750 +---------------------------------------+
17751 | Local variable space (L) | 24+P+A
17752 +---------------------------------------+
17753 | Float/int conversion temporary (X) | 24+P+A+L
17754 +---------------------------------------+
17755 | Save area for AltiVec registers (W) | 24+P+A+L+X
17756 +---------------------------------------+
17757 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17758 +---------------------------------------+
17759 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17760 +---------------------------------------+
17761 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17762 +---------------------------------------+
17763 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17764 +---------------------------------------+
17765 old SP->| back chain to caller's caller |
17766 +---------------------------------------+
17768 The required alignment for AIX configurations is two words (i.e., 8
17769 or 16 bytes).
17772 V.4 stack frames look like:
17774 SP----> +---------------------------------------+
17775 | back chain to caller | 0
17776 +---------------------------------------+
17777 | caller's saved LR | 4
17778 +---------------------------------------+
17779 | Parameter save area (P) | 8
17780 +---------------------------------------+
17781 | Alloca space (A) | 8+P
17782 +---------------------------------------+
17783 | Varargs save area (V) | 8+P+A
17784 +---------------------------------------+
17785 | Local variable space (L) | 8+P+A+V
17786 +---------------------------------------+
17787 | Float/int conversion temporary (X) | 8+P+A+V+L
17788 +---------------------------------------+
17789 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17790 +---------------------------------------+
17791 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17792 +---------------------------------------+
17793 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17794 +---------------------------------------+
17795 | SPE: area for 64-bit GP registers |
17796 +---------------------------------------+
17797 | SPE alignment padding |
17798 +---------------------------------------+
17799 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17800 +---------------------------------------+
17801 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17802 +---------------------------------------+
17803 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17804 +---------------------------------------+
17805 old SP->| back chain to caller's caller |
17806 +---------------------------------------+
17808 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17809 given. (But note below and in sysv4.h that we require only 8 and
17810 may round up the size of our stack frame anyways. The historical
17811 reason is early versions of powerpc-linux which didn't properly
17812 align the stack at program startup. A happy side-effect is that
17813 -mno-eabi libraries can be used with -meabi programs.)
17815 The EABI configuration defaults to the V.4 layout. However,
17816 the stack alignment requirements may differ. If -mno-eabi is not
17817 given, the required stack alignment is 8 bytes; if -mno-eabi is
17818 given, the required alignment is 16 bytes. (But see V.4 comment
17819 above.) */
17821 #ifndef ABI_STACK_BOUNDARY
17822 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17823 #endif
17825 static rs6000_stack_t *
17826 rs6000_stack_info (void)
17828 rs6000_stack_t *info_ptr = &stack_info;
17829 int reg_size = TARGET_32BIT ? 4 : 8;
17830 int ehrd_size;
17831 int save_align;
17832 int first_gp;
17833 HOST_WIDE_INT non_fixed_size;
17834 bool using_static_chain_p;
17836 if (reload_completed && info_ptr->reload_completed)
17837 return info_ptr;
17839 memset (info_ptr, 0, sizeof (*info_ptr));
17840 info_ptr->reload_completed = reload_completed;
17842 if (TARGET_SPE)
17844 /* Cache value so we don't rescan instruction chain over and over. */
17845 if (cfun->machine->insn_chain_scanned_p == 0)
17846 cfun->machine->insn_chain_scanned_p
17847 = spe_func_has_64bit_regs_p () + 1;
17848 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17851 /* Select which calling sequence. */
17852 info_ptr->abi = DEFAULT_ABI;
17854 /* Calculate which registers need to be saved & save area size. */
17855 info_ptr->first_gp_reg_save = first_reg_to_save ();
17856 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17857 even if it currently looks like we won't. Reload may need it to
17858 get at a constant; if so, it will have already created a constant
17859 pool entry for it. */
17860 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17861 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17862 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17863 && crtl->uses_const_pool
17864 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17865 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17866 else
17867 first_gp = info_ptr->first_gp_reg_save;
17869 info_ptr->gp_size = reg_size * (32 - first_gp);
17871 /* For the SPE, we have an additional upper 32-bits on each GPR.
17872 Ideally we should save the entire 64-bits only when the upper
17873 half is used in SIMD instructions. Since we only record
17874 registers live (not the size they are used in), this proves
17875 difficult because we'd have to traverse the instruction chain at
17876 the right time, taking reload into account. This is a real pain,
17877 so we opt to save the GPRs in 64-bits always if but one register
17878 gets used in 64-bits. Otherwise, all the registers in the frame
17879 get saved in 32-bits.
17881 So... since when we save all GPRs (except the SP) in 64-bits, the
17882 traditional GP save area will be empty. */
17883 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17884 info_ptr->gp_size = 0;
17886 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17887 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17889 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17890 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17891 - info_ptr->first_altivec_reg_save);
17893 /* Does this function call anything? */
17894 info_ptr->calls_p = (! crtl->is_leaf
17895 || cfun->machine->ra_needs_full_frame);
17897 /* Determine if we need to save the condition code registers. */
17898 if (df_regs_ever_live_p (CR2_REGNO)
17899 || df_regs_ever_live_p (CR3_REGNO)
17900 || df_regs_ever_live_p (CR4_REGNO))
17902 info_ptr->cr_save_p = 1;
17903 if (DEFAULT_ABI == ABI_V4)
17904 info_ptr->cr_size = reg_size;
17907 /* If the current function calls __builtin_eh_return, then we need
17908 to allocate stack space for registers that will hold data for
17909 the exception handler. */
17910 if (crtl->calls_eh_return)
17912 unsigned int i;
17913 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17914 continue;
17916 /* SPE saves EH registers in 64-bits. */
17917 ehrd_size = i * (TARGET_SPE_ABI
17918 && info_ptr->spe_64bit_regs_used != 0
17919 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17921 else
17922 ehrd_size = 0;
17924 /* Determine various sizes. */
17925 info_ptr->reg_size = reg_size;
17926 info_ptr->fixed_size = RS6000_SAVE_AREA;
17927 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
17928 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
17929 TARGET_ALTIVEC ? 16 : 8);
17930 if (FRAME_GROWS_DOWNWARD)
17931 info_ptr->vars_size
17932 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
17933 + info_ptr->parm_size,
17934 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
17935 - (info_ptr->fixed_size + info_ptr->vars_size
17936 + info_ptr->parm_size);
17938 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17939 info_ptr->spe_gp_size = 8 * (32 - first_gp);
17940 else
17941 info_ptr->spe_gp_size = 0;
17943 if (TARGET_ALTIVEC_ABI)
17944 info_ptr->vrsave_mask = compute_vrsave_mask ();
17945 else
17946 info_ptr->vrsave_mask = 0;
17948 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
17949 info_ptr->vrsave_size = 4;
17950 else
17951 info_ptr->vrsave_size = 0;
17953 compute_save_world_info (info_ptr);
17955 /* Calculate the offsets. */
17956 switch (DEFAULT_ABI)
17958 case ABI_NONE:
17959 default:
17960 gcc_unreachable ();
17962 case ABI_AIX:
17963 case ABI_DARWIN:
17964 info_ptr->fp_save_offset = - info_ptr->fp_size;
17965 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17967 if (TARGET_ALTIVEC_ABI)
17969 info_ptr->vrsave_save_offset
17970 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
17972 /* Align stack so vector save area is on a quadword boundary.
17973 The padding goes above the vectors. */
17974 if (info_ptr->altivec_size != 0)
17975 info_ptr->altivec_padding_size
17976 = info_ptr->vrsave_save_offset & 0xF;
17977 else
17978 info_ptr->altivec_padding_size = 0;
17980 info_ptr->altivec_save_offset
17981 = info_ptr->vrsave_save_offset
17982 - info_ptr->altivec_padding_size
17983 - info_ptr->altivec_size;
17984 gcc_assert (info_ptr->altivec_size == 0
17985 || info_ptr->altivec_save_offset % 16 == 0);
17987 /* Adjust for AltiVec case. */
17988 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
17990 else
17991 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
17992 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
17993 info_ptr->lr_save_offset = 2*reg_size;
17994 break;
17996 case ABI_V4:
17997 info_ptr->fp_save_offset = - info_ptr->fp_size;
17998 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17999 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
18001 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
18003 /* Align stack so SPE GPR save area is aligned on a
18004 double-word boundary. */
18005 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
18006 info_ptr->spe_padding_size
18007 = 8 - (-info_ptr->cr_save_offset % 8);
18008 else
18009 info_ptr->spe_padding_size = 0;
18011 info_ptr->spe_gp_save_offset
18012 = info_ptr->cr_save_offset
18013 - info_ptr->spe_padding_size
18014 - info_ptr->spe_gp_size;
18016 /* Adjust for SPE case. */
18017 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
18019 else if (TARGET_ALTIVEC_ABI)
18021 info_ptr->vrsave_save_offset
18022 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
18024 /* Align stack so vector save area is on a quadword boundary. */
18025 if (info_ptr->altivec_size != 0)
18026 info_ptr->altivec_padding_size
18027 = 16 - (-info_ptr->vrsave_save_offset % 16);
18028 else
18029 info_ptr->altivec_padding_size = 0;
18031 info_ptr->altivec_save_offset
18032 = info_ptr->vrsave_save_offset
18033 - info_ptr->altivec_padding_size
18034 - info_ptr->altivec_size;
18036 /* Adjust for AltiVec case. */
18037 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
18039 else
18040 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
18041 info_ptr->ehrd_offset -= ehrd_size;
18042 info_ptr->lr_save_offset = reg_size;
18043 break;
18046 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
18047 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
18048 + info_ptr->gp_size
18049 + info_ptr->altivec_size
18050 + info_ptr->altivec_padding_size
18051 + info_ptr->spe_gp_size
18052 + info_ptr->spe_padding_size
18053 + ehrd_size
18054 + info_ptr->cr_size
18055 + info_ptr->vrsave_size,
18056 save_align);
18058 non_fixed_size = (info_ptr->vars_size
18059 + info_ptr->parm_size
18060 + info_ptr->save_size);
18062 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
18063 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
18065 /* Determine if we need to save the link register. */
18066 if (info_ptr->calls_p
18067 || (DEFAULT_ABI == ABI_AIX
18068 && crtl->profile
18069 && !TARGET_PROFILE_KERNEL)
18070 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
18071 #ifdef TARGET_RELOCATABLE
18072 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
18073 #endif
18074 || rs6000_ra_ever_killed ())
18075 info_ptr->lr_save_p = 1;
18077 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
18078 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
18079 && call_used_regs[STATIC_CHAIN_REGNUM]);
18080 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
18081 using_static_chain_p);
18083 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
18084 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
18085 || !(info_ptr->savres_strategy & SAVE_INLINE_VRS)
18086 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
18087 || !(info_ptr->savres_strategy & REST_INLINE_FPRS)
18088 || !(info_ptr->savres_strategy & REST_INLINE_VRS))
18089 info_ptr->lr_save_p = 1;
18091 if (info_ptr->lr_save_p)
18092 df_set_regs_ever_live (LR_REGNO, true);
18094 /* Determine if we need to allocate any stack frame:
18096 For AIX we need to push the stack if a frame pointer is needed
18097 (because the stack might be dynamically adjusted), if we are
18098 debugging, if we make calls, or if the sum of fp_save, gp_save,
18099 and local variables are more than the space needed to save all
18100 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
18101 + 18*8 = 288 (GPR13 reserved).
18103 For V.4 we don't have the stack cushion that AIX uses, but assume
18104 that the debugger can handle stackless frames. */
18106 if (info_ptr->calls_p)
18107 info_ptr->push_p = 1;
18109 else if (DEFAULT_ABI == ABI_V4)
18110 info_ptr->push_p = non_fixed_size != 0;
18112 else if (frame_pointer_needed)
18113 info_ptr->push_p = 1;
18115 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
18116 info_ptr->push_p = 1;
18118 else
18119 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
18121 /* Zero offsets if we're not saving those registers. */
18122 if (info_ptr->fp_size == 0)
18123 info_ptr->fp_save_offset = 0;
18125 if (info_ptr->gp_size == 0)
18126 info_ptr->gp_save_offset = 0;
18128 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
18129 info_ptr->altivec_save_offset = 0;
18131 /* Zero VRSAVE offset if not saved and restored. */
18132 if (! TARGET_ALTIVEC_VRSAVE || info_ptr->vrsave_mask == 0)
18133 info_ptr->vrsave_save_offset = 0;
18135 if (! TARGET_SPE_ABI
18136 || info_ptr->spe_64bit_regs_used == 0
18137 || info_ptr->spe_gp_size == 0)
18138 info_ptr->spe_gp_save_offset = 0;
18140 if (! info_ptr->lr_save_p)
18141 info_ptr->lr_save_offset = 0;
18143 if (! info_ptr->cr_save_p)
18144 info_ptr->cr_save_offset = 0;
18146 return info_ptr;
18149 /* Return true if the current function uses any GPRs in 64-bit SIMD
18150 mode. */
18152 static bool
18153 spe_func_has_64bit_regs_p (void)
18155 rtx insns, insn;
18157 /* Functions that save and restore all the call-saved registers will
18158 need to save/restore the registers in 64-bits. */
18159 if (crtl->calls_eh_return
18160 || cfun->calls_setjmp
18161 || crtl->has_nonlocal_goto)
18162 return true;
18164 insns = get_insns ();
18166 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
18168 if (INSN_P (insn))
18170 rtx i;
18172 /* FIXME: This should be implemented with attributes...
18174 (set_attr "spe64" "true")....then,
18175 if (get_spe64(insn)) return true;
18177 It's the only reliable way to do the stuff below. */
18179 i = PATTERN (insn);
18180 if (GET_CODE (i) == SET)
18182 enum machine_mode mode = GET_MODE (SET_SRC (i));
18184 if (SPE_VECTOR_MODE (mode))
18185 return true;
18186 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
18187 return true;
18192 return false;
18195 static void
18196 debug_stack_info (rs6000_stack_t *info)
18198 const char *abi_string;
18200 if (! info)
18201 info = rs6000_stack_info ();
18203 fprintf (stderr, "\nStack information for function %s:\n",
18204 ((current_function_decl && DECL_NAME (current_function_decl))
18205 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
18206 : "<unknown>"));
18208 switch (info->abi)
18210 default: abi_string = "Unknown"; break;
18211 case ABI_NONE: abi_string = "NONE"; break;
18212 case ABI_AIX: abi_string = "AIX"; break;
18213 case ABI_DARWIN: abi_string = "Darwin"; break;
18214 case ABI_V4: abi_string = "V.4"; break;
18217 fprintf (stderr, "\tABI = %5s\n", abi_string);
18219 if (TARGET_ALTIVEC_ABI)
18220 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
18222 if (TARGET_SPE_ABI)
18223 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
18225 if (info->first_gp_reg_save != 32)
18226 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
18228 if (info->first_fp_reg_save != 64)
18229 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
18231 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
18232 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
18233 info->first_altivec_reg_save);
18235 if (info->lr_save_p)
18236 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
18238 if (info->cr_save_p)
18239 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
18241 if (info->vrsave_mask)
18242 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
18244 if (info->push_p)
18245 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
18247 if (info->calls_p)
18248 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
18250 if (info->gp_save_offset)
18251 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
18253 if (info->fp_save_offset)
18254 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
18256 if (info->altivec_save_offset)
18257 fprintf (stderr, "\taltivec_save_offset = %5d\n",
18258 info->altivec_save_offset);
18260 if (info->spe_gp_save_offset)
18261 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
18262 info->spe_gp_save_offset);
18264 if (info->vrsave_save_offset)
18265 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
18266 info->vrsave_save_offset);
18268 if (info->lr_save_offset)
18269 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
18271 if (info->cr_save_offset)
18272 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
18274 if (info->varargs_save_offset)
18275 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
18277 if (info->total_size)
18278 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18279 info->total_size);
18281 if (info->vars_size)
18282 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18283 info->vars_size);
18285 if (info->parm_size)
18286 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
18288 if (info->fixed_size)
18289 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
18291 if (info->gp_size)
18292 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
18294 if (info->spe_gp_size)
18295 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
18297 if (info->fp_size)
18298 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
18300 if (info->altivec_size)
18301 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
18303 if (info->vrsave_size)
18304 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
18306 if (info->altivec_padding_size)
18307 fprintf (stderr, "\taltivec_padding_size= %5d\n",
18308 info->altivec_padding_size);
18310 if (info->spe_padding_size)
18311 fprintf (stderr, "\tspe_padding_size = %5d\n",
18312 info->spe_padding_size);
18314 if (info->cr_size)
18315 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
18317 if (info->save_size)
18318 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
18320 if (info->reg_size != 4)
18321 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
18323 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
18325 fprintf (stderr, "\n");
18329 rs6000_return_addr (int count, rtx frame)
18331 /* Currently we don't optimize very well between prolog and body
18332 code and for PIC code the code can be actually quite bad, so
18333 don't try to be too clever here. */
18334 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
18336 cfun->machine->ra_needs_full_frame = 1;
18338 return
18339 gen_rtx_MEM
18340 (Pmode,
18341 memory_address
18342 (Pmode,
18343 plus_constant (Pmode,
18344 copy_to_reg
18345 (gen_rtx_MEM (Pmode,
18346 memory_address (Pmode, frame))),
18347 RETURN_ADDRESS_OFFSET)));
18350 cfun->machine->ra_need_lr = 1;
18351 return get_hard_reg_initial_val (Pmode, LR_REGNO);
18354 /* Say whether a function is a candidate for sibcall handling or not. */
18356 static bool
18357 rs6000_function_ok_for_sibcall (tree decl, tree exp)
18359 tree fntype;
18361 if (decl)
18362 fntype = TREE_TYPE (decl);
18363 else
18364 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
18366 /* We can't do it if the called function has more vector parameters
18367 than the current function; there's nowhere to put the VRsave code. */
18368 if (TARGET_ALTIVEC_ABI
18369 && TARGET_ALTIVEC_VRSAVE
18370 && !(decl && decl == current_function_decl))
18372 function_args_iterator args_iter;
18373 tree type;
18374 int nvreg = 0;
18376 /* Functions with vector parameters are required to have a
18377 prototype, so the argument type info must be available
18378 here. */
18379 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18380 if (TREE_CODE (type) == VECTOR_TYPE
18381 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18382 nvreg++;
18384 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18385 if (TREE_CODE (type) == VECTOR_TYPE
18386 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18387 nvreg--;
18389 if (nvreg > 0)
18390 return false;
18393 /* Under the AIX ABI we can't allow calls to non-local functions,
18394 because the callee may have a different TOC pointer to the
18395 caller and there's no way to ensure we restore the TOC when we
18396 return. With the secure-plt SYSV ABI we can't make non-local
18397 calls when -fpic/PIC because the plt call stubs use r30. */
18398 if (DEFAULT_ABI == ABI_DARWIN
18399 || (DEFAULT_ABI == ABI_AIX
18400 && decl
18401 && !DECL_EXTERNAL (decl)
18402 && (*targetm.binds_local_p) (decl))
18403 || (DEFAULT_ABI == ABI_V4
18404 && (!TARGET_SECURE_PLT
18405 || !flag_pic
18406 || (decl
18407 && (*targetm.binds_local_p) (decl)))))
18409 tree attr_list = TYPE_ATTRIBUTES (fntype);
18411 if (!lookup_attribute ("longcall", attr_list)
18412 || lookup_attribute ("shortcall", attr_list))
18413 return true;
18416 return false;
18419 /* NULL if INSN insn is valid within a low-overhead loop.
18420 Otherwise return why doloop cannot be applied.
18421 PowerPC uses the COUNT register for branch on table instructions. */
18423 static const char *
18424 rs6000_invalid_within_doloop (const_rtx insn)
18426 if (CALL_P (insn))
18427 return "Function call in the loop.";
18429 if (JUMP_P (insn)
18430 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18431 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18432 return "Computed branch in the loop.";
18434 return NULL;
18437 static int
18438 rs6000_ra_ever_killed (void)
18440 rtx top;
18441 rtx reg;
18442 rtx insn;
18444 if (cfun->is_thunk)
18445 return 0;
18447 if (cfun->machine->lr_save_state)
18448 return cfun->machine->lr_save_state - 1;
18450 /* regs_ever_live has LR marked as used if any sibcalls are present,
18451 but this should not force saving and restoring in the
18452 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18453 clobbers LR, so that is inappropriate. */
18455 /* Also, the prologue can generate a store into LR that
18456 doesn't really count, like this:
18458 move LR->R0
18459 bcl to set PIC register
18460 move LR->R31
18461 move R0->LR
18463 When we're called from the epilogue, we need to avoid counting
18464 this as a store. */
18466 push_topmost_sequence ();
18467 top = get_insns ();
18468 pop_topmost_sequence ();
18469 reg = gen_rtx_REG (Pmode, LR_REGNO);
18471 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18473 if (INSN_P (insn))
18475 if (CALL_P (insn))
18477 if (!SIBLING_CALL_P (insn))
18478 return 1;
18480 else if (find_regno_note (insn, REG_INC, LR_REGNO))
18481 return 1;
18482 else if (set_of (reg, insn) != NULL_RTX
18483 && !prologue_epilogue_contains (insn))
18484 return 1;
18487 return 0;
18490 /* Emit instructions needed to load the TOC register.
18491 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18492 a constant pool; or for SVR4 -fpic. */
18494 void
18495 rs6000_emit_load_toc_table (int fromprolog)
18497 rtx dest;
18498 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18500 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18502 char buf[30];
18503 rtx lab, tmp1, tmp2, got;
18505 lab = gen_label_rtx ();
18506 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18507 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18508 if (flag_pic == 2)
18509 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18510 else
18511 got = rs6000_got_sym ();
18512 tmp1 = tmp2 = dest;
18513 if (!fromprolog)
18515 tmp1 = gen_reg_rtx (Pmode);
18516 tmp2 = gen_reg_rtx (Pmode);
18518 emit_insn (gen_load_toc_v4_PIC_1 (lab));
18519 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18520 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18521 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18523 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18525 emit_insn (gen_load_toc_v4_pic_si ());
18526 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18528 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18530 char buf[30];
18531 rtx temp0 = (fromprolog
18532 ? gen_rtx_REG (Pmode, 0)
18533 : gen_reg_rtx (Pmode));
18535 if (fromprolog)
18537 rtx symF, symL;
18539 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18540 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18542 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18543 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18545 emit_insn (gen_load_toc_v4_PIC_1 (symF));
18546 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18547 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18549 else
18551 rtx tocsym, lab;
18553 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18554 lab = gen_label_rtx ();
18555 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18556 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18557 if (TARGET_LINK_STACK)
18558 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18559 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18561 emit_insn (gen_addsi3 (dest, temp0, dest));
18563 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18565 /* This is for AIX code running in non-PIC ELF32. */
18566 char buf[30];
18567 rtx realsym;
18568 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18569 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18571 emit_insn (gen_elf_high (dest, realsym));
18572 emit_insn (gen_elf_low (dest, dest, realsym));
18574 else
18576 gcc_assert (DEFAULT_ABI == ABI_AIX);
18578 if (TARGET_32BIT)
18579 emit_insn (gen_load_toc_aix_si (dest));
18580 else
18581 emit_insn (gen_load_toc_aix_di (dest));
18585 /* Emit instructions to restore the link register after determining where
18586 its value has been stored. */
18588 void
18589 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18591 rs6000_stack_t *info = rs6000_stack_info ();
18592 rtx operands[2];
18594 operands[0] = source;
18595 operands[1] = scratch;
18597 if (info->lr_save_p)
18599 rtx frame_rtx = stack_pointer_rtx;
18600 HOST_WIDE_INT sp_offset = 0;
18601 rtx tmp;
18603 if (frame_pointer_needed
18604 || cfun->calls_alloca
18605 || info->total_size > 32767)
18607 tmp = gen_frame_mem (Pmode, frame_rtx);
18608 emit_move_insn (operands[1], tmp);
18609 frame_rtx = operands[1];
18611 else if (info->push_p)
18612 sp_offset = info->total_size;
18614 tmp = plus_constant (Pmode, frame_rtx,
18615 info->lr_save_offset + sp_offset);
18616 tmp = gen_frame_mem (Pmode, tmp);
18617 emit_move_insn (tmp, operands[0]);
18619 else
18620 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18622 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18623 state of lr_save_p so any change from here on would be a bug. In
18624 particular, stop rs6000_ra_ever_killed from considering the SET
18625 of lr we may have added just above. */
18626 cfun->machine->lr_save_state = info->lr_save_p + 1;
18629 static GTY(()) alias_set_type set = -1;
18631 alias_set_type
18632 get_TOC_alias_set (void)
18634 if (set == -1)
18635 set = new_alias_set ();
18636 return set;
18639 /* This returns nonzero if the current function uses the TOC. This is
18640 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18641 is generated by the ABI_V4 load_toc_* patterns. */
18642 #if TARGET_ELF
18643 static int
18644 uses_TOC (void)
18646 rtx insn;
18648 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18649 if (INSN_P (insn))
18651 rtx pat = PATTERN (insn);
18652 int i;
18654 if (GET_CODE (pat) == PARALLEL)
18655 for (i = 0; i < XVECLEN (pat, 0); i++)
18657 rtx sub = XVECEXP (pat, 0, i);
18658 if (GET_CODE (sub) == USE)
18660 sub = XEXP (sub, 0);
18661 if (GET_CODE (sub) == UNSPEC
18662 && XINT (sub, 1) == UNSPEC_TOC)
18663 return 1;
18667 return 0;
18669 #endif
18672 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18674 rtx tocrel, tocreg, hi;
18676 if (TARGET_DEBUG_ADDR)
18678 if (GET_CODE (symbol) == SYMBOL_REF)
18679 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18680 XSTR (symbol, 0));
18681 else
18683 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18684 GET_RTX_NAME (GET_CODE (symbol)));
18685 debug_rtx (symbol);
18689 if (!can_create_pseudo_p ())
18690 df_set_regs_ever_live (TOC_REGISTER, true);
18692 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18693 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
18694 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
18695 return tocrel;
18697 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
18698 if (largetoc_reg != NULL)
18700 emit_move_insn (largetoc_reg, hi);
18701 hi = largetoc_reg;
18703 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
18706 /* Issue assembly directives that create a reference to the given DWARF
18707 FRAME_TABLE_LABEL from the current function section. */
18708 void
18709 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18711 fprintf (asm_out_file, "\t.ref %s\n",
18712 (* targetm.strip_name_encoding) (frame_table_label));
18715 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18716 and the change to the stack pointer. */
18718 static void
18719 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
18721 rtvec p;
18722 int i;
18723 rtx regs[3];
18725 i = 0;
18726 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18727 if (hard_frame_needed)
18728 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
18729 if (!(REGNO (fp) == STACK_POINTER_REGNUM
18730 || (hard_frame_needed
18731 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
18732 regs[i++] = fp;
18734 p = rtvec_alloc (i);
18735 while (--i >= 0)
18737 rtx mem = gen_frame_mem (BLKmode, regs[i]);
18738 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, const0_rtx);
18741 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
18744 /* Emit the correct code for allocating stack space, as insns.
18745 If COPY_REG, make sure a copy of the old frame is left there.
18746 The generated code may use hard register 0 as a temporary. */
18748 static void
18749 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
18751 rtx insn;
18752 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18753 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18754 rtx todec = gen_int_mode (-size, Pmode);
18755 rtx par, set, mem;
18757 if (INTVAL (todec) != -size)
18759 warning (0, "stack frame too large");
18760 emit_insn (gen_trap ());
18761 return;
18764 if (crtl->limit_stack)
18766 if (REG_P (stack_limit_rtx)
18767 && REGNO (stack_limit_rtx) > 1
18768 && REGNO (stack_limit_rtx) <= 31)
18770 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18771 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18772 const0_rtx));
18774 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18775 && TARGET_32BIT
18776 && DEFAULT_ABI == ABI_V4)
18778 rtx toload = gen_rtx_CONST (VOIDmode,
18779 gen_rtx_PLUS (Pmode,
18780 stack_limit_rtx,
18781 GEN_INT (size)));
18783 emit_insn (gen_elf_high (tmp_reg, toload));
18784 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18785 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18786 const0_rtx));
18788 else
18789 warning (0, "stack limit expression is not supported");
18792 if (copy_reg)
18794 if (copy_off != 0)
18795 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
18796 else
18797 emit_move_insn (copy_reg, stack_reg);
18800 if (size > 32767)
18802 /* Need a note here so that try_split doesn't get confused. */
18803 if (get_last_insn () == NULL_RTX)
18804 emit_note (NOTE_INSN_DELETED);
18805 insn = emit_move_insn (tmp_reg, todec);
18806 try_split (PATTERN (insn), insn, 0);
18807 todec = tmp_reg;
18810 insn = emit_insn (TARGET_32BIT
18811 ? gen_movsi_update_stack (stack_reg, stack_reg,
18812 todec, stack_reg)
18813 : gen_movdi_di_update_stack (stack_reg, stack_reg,
18814 todec, stack_reg));
18815 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18816 it now and set the alias set/attributes. The above gen_*_update
18817 calls will generate a PARALLEL with the MEM set being the first
18818 operation. */
18819 par = PATTERN (insn);
18820 gcc_assert (GET_CODE (par) == PARALLEL);
18821 set = XVECEXP (par, 0, 0);
18822 gcc_assert (GET_CODE (set) == SET);
18823 mem = SET_DEST (set);
18824 gcc_assert (MEM_P (mem));
18825 MEM_NOTRAP_P (mem) = 1;
18826 set_mem_alias_set (mem, get_frame_alias_set ());
18828 RTX_FRAME_RELATED_P (insn) = 1;
18829 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18830 gen_rtx_SET (VOIDmode, stack_reg,
18831 gen_rtx_PLUS (Pmode, stack_reg,
18832 GEN_INT (-size))));
18835 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18837 #if PROBE_INTERVAL > 32768
18838 #error Cannot use indexed addressing mode for stack probing
18839 #endif
18841 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18842 inclusive. These are offsets from the current stack pointer. */
18844 static void
18845 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18847 /* See if we have a constant small number of probes to generate. If so,
18848 that's the easy case. */
18849 if (first + size <= 32768)
18851 HOST_WIDE_INT i;
18853 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18854 it exceeds SIZE. If only one probe is needed, this will not
18855 generate any code. Then probe at FIRST + SIZE. */
18856 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18857 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18858 -(first + i)));
18860 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
18861 -(first + size)));
18864 /* Otherwise, do the same as above, but in a loop. Note that we must be
18865 extra careful with variables wrapping around because we might be at
18866 the very top (or the very bottom) of the address space and we have
18867 to be able to handle this case properly; in particular, we use an
18868 equality test for the loop condition. */
18869 else
18871 HOST_WIDE_INT rounded_size;
18872 rtx r12 = gen_rtx_REG (Pmode, 12);
18873 rtx r0 = gen_rtx_REG (Pmode, 0);
18875 /* Sanity check for the addressing mode we're going to use. */
18876 gcc_assert (first <= 32768);
18878 /* Step 1: round SIZE to the previous multiple of the interval. */
18880 rounded_size = size & -PROBE_INTERVAL;
18883 /* Step 2: compute initial and final value of the loop counter. */
18885 /* TEST_ADDR = SP + FIRST. */
18886 emit_insn (gen_rtx_SET (VOIDmode, r12,
18887 plus_constant (Pmode, stack_pointer_rtx,
18888 -first)));
18890 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18891 if (rounded_size > 32768)
18893 emit_move_insn (r0, GEN_INT (-rounded_size));
18894 emit_insn (gen_rtx_SET (VOIDmode, r0,
18895 gen_rtx_PLUS (Pmode, r12, r0)));
18897 else
18898 emit_insn (gen_rtx_SET (VOIDmode, r0,
18899 plus_constant (Pmode, r12, -rounded_size)));
18902 /* Step 3: the loop
18904 while (TEST_ADDR != LAST_ADDR)
18906 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18907 probe at TEST_ADDR
18910 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18911 until it is equal to ROUNDED_SIZE. */
18913 if (TARGET_64BIT)
18914 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18915 else
18916 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18919 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18920 that SIZE is equal to ROUNDED_SIZE. */
18922 if (size != rounded_size)
18923 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
18927 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18928 absolute addresses. */
18930 const char *
18931 output_probe_stack_range (rtx reg1, rtx reg2)
18933 static int labelno = 0;
18934 char loop_lab[32], end_lab[32];
18935 rtx xops[2];
18937 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
18938 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
18940 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
18942 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18943 xops[0] = reg1;
18944 xops[1] = reg2;
18945 if (TARGET_64BIT)
18946 output_asm_insn ("cmpd 0,%0,%1", xops);
18947 else
18948 output_asm_insn ("cmpw 0,%0,%1", xops);
18950 fputs ("\tbeq 0,", asm_out_file);
18951 assemble_name_raw (asm_out_file, end_lab);
18952 fputc ('\n', asm_out_file);
18954 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18955 xops[1] = GEN_INT (-PROBE_INTERVAL);
18956 output_asm_insn ("addi %0,%0,%1", xops);
18958 /* Probe at TEST_ADDR and branch. */
18959 xops[1] = gen_rtx_REG (Pmode, 0);
18960 output_asm_insn ("stw %1,0(%0)", xops);
18961 fprintf (asm_out_file, "\tb ");
18962 assemble_name_raw (asm_out_file, loop_lab);
18963 fputc ('\n', asm_out_file);
18965 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
18967 return "";
18970 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18971 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18972 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18973 deduce these equivalences by itself so it wasn't necessary to hold
18974 its hand so much. Don't be tempted to always supply d2_f_d_e with
18975 the actual cfa register, ie. r31 when we are using a hard frame
18976 pointer. That fails when saving regs off r1, and sched moves the
18977 r31 setup past the reg saves. */
18979 static rtx
18980 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
18981 rtx reg2, rtx rreg)
18983 rtx real, temp;
18985 if (REGNO (reg) == STACK_POINTER_REGNUM && reg2 == NULL_RTX)
18987 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
18988 int i;
18990 gcc_checking_assert (val == 0);
18991 real = PATTERN (insn);
18992 if (GET_CODE (real) == PARALLEL)
18993 for (i = 0; i < XVECLEN (real, 0); i++)
18994 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18996 rtx set = XVECEXP (real, 0, i);
18998 RTX_FRAME_RELATED_P (set) = 1;
19000 RTX_FRAME_RELATED_P (insn) = 1;
19001 return insn;
19004 /* copy_rtx will not make unique copies of registers, so we need to
19005 ensure we don't have unwanted sharing here. */
19006 if (reg == reg2)
19007 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
19009 if (reg == rreg)
19010 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
19012 real = copy_rtx (PATTERN (insn));
19014 if (reg2 != NULL_RTX)
19015 real = replace_rtx (real, reg2, rreg);
19017 if (REGNO (reg) == STACK_POINTER_REGNUM)
19018 gcc_checking_assert (val == 0);
19019 else
19020 real = replace_rtx (real, reg,
19021 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
19022 STACK_POINTER_REGNUM),
19023 GEN_INT (val)));
19025 /* We expect that 'real' is either a SET or a PARALLEL containing
19026 SETs (and possibly other stuff). In a PARALLEL, all the SETs
19027 are important so they all have to be marked RTX_FRAME_RELATED_P. */
19029 if (GET_CODE (real) == SET)
19031 rtx set = real;
19033 temp = simplify_rtx (SET_SRC (set));
19034 if (temp)
19035 SET_SRC (set) = temp;
19036 temp = simplify_rtx (SET_DEST (set));
19037 if (temp)
19038 SET_DEST (set) = temp;
19039 if (GET_CODE (SET_DEST (set)) == MEM)
19041 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
19042 if (temp)
19043 XEXP (SET_DEST (set), 0) = temp;
19046 else
19048 int i;
19050 gcc_assert (GET_CODE (real) == PARALLEL);
19051 for (i = 0; i < XVECLEN (real, 0); i++)
19052 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
19054 rtx set = XVECEXP (real, 0, i);
19056 temp = simplify_rtx (SET_SRC (set));
19057 if (temp)
19058 SET_SRC (set) = temp;
19059 temp = simplify_rtx (SET_DEST (set));
19060 if (temp)
19061 SET_DEST (set) = temp;
19062 if (GET_CODE (SET_DEST (set)) == MEM)
19064 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
19065 if (temp)
19066 XEXP (SET_DEST (set), 0) = temp;
19068 RTX_FRAME_RELATED_P (set) = 1;
19072 RTX_FRAME_RELATED_P (insn) = 1;
19073 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
19075 return insn;
19078 /* Returns an insn that has a vrsave set operation with the
19079 appropriate CLOBBERs. */
19081 static rtx
19082 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
19084 int nclobs, i;
19085 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
19086 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
19088 clobs[0]
19089 = gen_rtx_SET (VOIDmode,
19090 vrsave,
19091 gen_rtx_UNSPEC_VOLATILE (SImode,
19092 gen_rtvec (2, reg, vrsave),
19093 UNSPECV_SET_VRSAVE));
19095 nclobs = 1;
19097 /* We need to clobber the registers in the mask so the scheduler
19098 does not move sets to VRSAVE before sets of AltiVec registers.
19100 However, if the function receives nonlocal gotos, reload will set
19101 all call saved registers live. We will end up with:
19103 (set (reg 999) (mem))
19104 (parallel [ (set (reg vrsave) (unspec blah))
19105 (clobber (reg 999))])
19107 The clobber will cause the store into reg 999 to be dead, and
19108 flow will attempt to delete an epilogue insn. In this case, we
19109 need an unspec use/set of the register. */
19111 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
19112 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
19114 if (!epiloguep || call_used_regs [i])
19115 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
19116 gen_rtx_REG (V4SImode, i));
19117 else
19119 rtx reg = gen_rtx_REG (V4SImode, i);
19121 clobs[nclobs++]
19122 = gen_rtx_SET (VOIDmode,
19123 reg,
19124 gen_rtx_UNSPEC (V4SImode,
19125 gen_rtvec (1, reg), 27));
19129 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
19131 for (i = 0; i < nclobs; ++i)
19132 XVECEXP (insn, 0, i) = clobs[i];
19134 return insn;
19137 static rtx
19138 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
19140 rtx addr, mem;
19142 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
19143 mem = gen_frame_mem (GET_MODE (reg), addr);
19144 return gen_rtx_SET (VOIDmode, store ? mem : reg, store ? reg : mem);
19147 static rtx
19148 gen_frame_load (rtx reg, rtx frame_reg, int offset)
19150 return gen_frame_set (reg, frame_reg, offset, false);
19153 static rtx
19154 gen_frame_store (rtx reg, rtx frame_reg, int offset)
19156 return gen_frame_set (reg, frame_reg, offset, true);
19159 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
19160 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
19162 static rtx
19163 emit_frame_save (rtx frame_reg, enum machine_mode mode,
19164 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
19166 rtx reg, insn;
19168 /* Some cases that need register indexed addressing. */
19169 gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
19170 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
19171 || (TARGET_E500_DOUBLE && mode == DFmode)
19172 || (TARGET_SPE_ABI
19173 && SPE_VECTOR_MODE (mode)
19174 && !SPE_CONST_OFFSET_OK (offset))));
19176 reg = gen_rtx_REG (mode, regno);
19177 insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
19178 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
19179 NULL_RTX, NULL_RTX);
19182 /* Emit an offset memory reference suitable for a frame store, while
19183 converting to a valid addressing mode. */
19185 static rtx
19186 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
19188 rtx int_rtx, offset_rtx;
19190 int_rtx = GEN_INT (offset);
19192 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
19193 || (TARGET_E500_DOUBLE && mode == DFmode))
19195 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
19196 emit_move_insn (offset_rtx, int_rtx);
19198 else
19199 offset_rtx = int_rtx;
19201 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
19204 #ifndef TARGET_FIX_AND_CONTINUE
19205 #define TARGET_FIX_AND_CONTINUE 0
19206 #endif
19208 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
19209 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
19210 #define LAST_SAVRES_REGISTER 31
19211 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
19213 enum {
19214 SAVRES_LR = 0x1,
19215 SAVRES_SAVE = 0x2,
19216 SAVRES_REG = 0x0c,
19217 SAVRES_GPR = 0,
19218 SAVRES_FPR = 4,
19219 SAVRES_VR = 8
19222 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
19224 /* Temporary holding space for an out-of-line register save/restore
19225 routine name. */
19226 static char savres_routine_name[30];
19228 /* Return the name for an out-of-line register save/restore routine.
19229 We are saving/restoring GPRs if GPR is true. */
19231 static char *
19232 rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
19234 const char *prefix = "";
19235 const char *suffix = "";
19237 /* Different targets are supposed to define
19238 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
19239 routine name could be defined with:
19241 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
19243 This is a nice idea in practice, but in reality, things are
19244 complicated in several ways:
19246 - ELF targets have save/restore routines for GPRs.
19248 - SPE targets use different prefixes for 32/64-bit registers, and
19249 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
19251 - PPC64 ELF targets have routines for save/restore of GPRs that
19252 differ in what they do with the link register, so having a set
19253 prefix doesn't work. (We only use one of the save routines at
19254 the moment, though.)
19256 - PPC32 elf targets have "exit" versions of the restore routines
19257 that restore the link register and can save some extra space.
19258 These require an extra suffix. (There are also "tail" versions
19259 of the restore routines and "GOT" versions of the save routines,
19260 but we don't generate those at present. Same problems apply,
19261 though.)
19263 We deal with all this by synthesizing our own prefix/suffix and
19264 using that for the simple sprintf call shown above. */
19265 if (TARGET_SPE)
19267 /* No floating point saves on the SPE. */
19268 gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR);
19270 if ((sel & SAVRES_SAVE))
19271 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
19272 else
19273 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
19275 if ((sel & SAVRES_LR))
19276 suffix = "_x";
19278 else if (DEFAULT_ABI == ABI_V4)
19280 if (TARGET_64BIT)
19281 goto aix_names;
19283 if ((sel & SAVRES_REG) == SAVRES_GPR)
19284 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
19285 else if ((sel & SAVRES_REG) == SAVRES_FPR)
19286 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
19287 else if ((sel & SAVRES_REG) == SAVRES_VR)
19288 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
19289 else
19290 abort ();
19292 if ((sel & SAVRES_LR))
19293 suffix = "_x";
19295 else if (DEFAULT_ABI == ABI_AIX)
19297 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
19298 /* No out-of-line save/restore routines for GPRs on AIX. */
19299 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
19300 #endif
19302 aix_names:
19303 if ((sel & SAVRES_REG) == SAVRES_GPR)
19304 prefix = ((sel & SAVRES_SAVE)
19305 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
19306 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
19307 else if ((sel & SAVRES_REG) == SAVRES_FPR)
19309 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
19310 if ((sel & SAVRES_LR))
19311 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
19312 else
19313 #endif
19315 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
19316 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
19319 else if ((sel & SAVRES_REG) == SAVRES_VR)
19320 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
19321 else
19322 abort ();
19325 if (DEFAULT_ABI == ABI_DARWIN)
19327 /* The Darwin approach is (slightly) different, in order to be
19328 compatible with code generated by the system toolchain. There is a
19329 single symbol for the start of save sequence, and the code here
19330 embeds an offset into that code on the basis of the first register
19331 to be saved. */
19332 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
19333 if ((sel & SAVRES_REG) == SAVRES_GPR)
19334 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
19335 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
19336 (regno - 13) * 4, prefix, regno);
19337 else if ((sel & SAVRES_REG) == SAVRES_FPR)
19338 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
19339 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
19340 else if ((sel & SAVRES_REG) == SAVRES_VR)
19341 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
19342 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
19343 else
19344 abort ();
19346 else
19347 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
19349 return savres_routine_name;
19352 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19353 We are saving/restoring GPRs if GPR is true. */
19355 static rtx
19356 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
19358 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
19359 ? info->first_gp_reg_save
19360 : (sel & SAVRES_REG) == SAVRES_FPR
19361 ? info->first_fp_reg_save - 32
19362 : (sel & SAVRES_REG) == SAVRES_VR
19363 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
19364 : -1);
19365 rtx sym;
19366 int select = sel;
19368 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
19369 versions of the gpr routines. */
19370 if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR
19371 && info->spe_64bit_regs_used)
19372 select ^= SAVRES_FPR ^ SAVRES_GPR;
19374 /* Don't generate bogus routine names. */
19375 gcc_assert (FIRST_SAVRES_REGISTER <= regno
19376 && regno <= LAST_SAVRES_REGISTER
19377 && select >= 0 && select <= 12);
19379 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19381 if (sym == NULL)
19383 char *name;
19385 name = rs6000_savres_routine_name (info, regno, sel);
19387 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19388 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19389 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19392 return sym;
19395 /* Emit a sequence of insns, including a stack tie if needed, for
19396 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
19397 reset the stack pointer, but move the base of the frame into
19398 reg UPDT_REGNO for use by out-of-line register restore routines. */
19400 static rtx
19401 rs6000_emit_stack_reset (rs6000_stack_t *info,
19402 rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
19403 unsigned updt_regno)
19405 rtx updt_reg_rtx;
19407 /* This blockage is needed so that sched doesn't decide to move
19408 the sp change before the register restores. */
19409 if (DEFAULT_ABI == ABI_V4
19410 || (TARGET_SPE_ABI
19411 && info->spe_64bit_regs_used != 0
19412 && info->first_gp_reg_save != 32))
19413 rs6000_emit_stack_tie (frame_reg_rtx, frame_pointer_needed);
19415 /* If we are restoring registers out-of-line, we will be using the
19416 "exit" variants of the restore routines, which will reset the
19417 stack for us. But we do need to point updt_reg into the
19418 right place for those routines. */
19419 updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
19421 if (frame_off != 0)
19422 return emit_insn (gen_add3_insn (updt_reg_rtx,
19423 frame_reg_rtx, GEN_INT (frame_off)));
19424 else if (REGNO (frame_reg_rtx) != updt_regno)
19425 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
19427 return NULL_RTX;
19430 /* Return the register number used as a pointer by out-of-line
19431 save/restore functions. */
19433 static inline unsigned
19434 ptr_regno_for_savres (int sel)
19436 if (DEFAULT_ABI == ABI_AIX)
19437 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
19438 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
19441 /* Construct a parallel rtx describing the effect of a call to an
19442 out-of-line register save/restore routine, and emit the insn
19443 or jump_insn as appropriate. */
19445 static rtx
19446 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19447 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
19448 enum machine_mode reg_mode, int sel)
19450 int i;
19451 int offset, start_reg, end_reg, n_regs, use_reg;
19452 int reg_size = GET_MODE_SIZE (reg_mode);
19453 rtx sym;
19454 rtvec p;
19455 rtx par, insn;
19457 offset = 0;
19458 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19459 ? info->first_gp_reg_save
19460 : (sel & SAVRES_REG) == SAVRES_FPR
19461 ? info->first_fp_reg_save
19462 : (sel & SAVRES_REG) == SAVRES_VR
19463 ? info->first_altivec_reg_save
19464 : -1);
19465 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
19466 ? 32
19467 : (sel & SAVRES_REG) == SAVRES_FPR
19468 ? 64
19469 : (sel & SAVRES_REG) == SAVRES_VR
19470 ? LAST_ALTIVEC_REGNO + 1
19471 : -1);
19472 n_regs = end_reg - start_reg;
19473 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
19474 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
19475 + n_regs);
19477 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19478 RTVEC_ELT (p, offset++) = ret_rtx;
19480 RTVEC_ELT (p, offset++)
19481 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19483 sym = rs6000_savres_routine_sym (info, sel);
19484 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19486 use_reg = ptr_regno_for_savres (sel);
19487 if ((sel & SAVRES_REG) == SAVRES_VR)
19489 /* Vector regs are saved/restored using [reg+reg] addressing. */
19490 RTVEC_ELT (p, offset++)
19491 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19492 RTVEC_ELT (p, offset++)
19493 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
19495 else
19496 RTVEC_ELT (p, offset++)
19497 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
19499 for (i = 0; i < end_reg - start_reg; i++)
19500 RTVEC_ELT (p, i + offset)
19501 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
19502 frame_reg_rtx, save_area_offset + reg_size * i,
19503 (sel & SAVRES_SAVE) != 0);
19505 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19506 RTVEC_ELT (p, i + offset)
19507 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
19509 par = gen_rtx_PARALLEL (VOIDmode, p);
19511 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
19513 insn = emit_jump_insn (par);
19514 JUMP_LABEL (insn) = ret_rtx;
19516 else
19517 insn = emit_insn (par);
19518 return insn;
19521 /* Determine whether the gp REG is really used. */
19523 static bool
19524 rs6000_reg_live_or_pic_offset_p (int reg)
19526 /* If the function calls eh_return, claim used all the registers that would
19527 be checked for liveness otherwise. This is required for the PIC offset
19528 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19529 register allocation purposes in this case. */
19531 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19532 && (!call_used_regs[reg]
19533 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19534 && !TARGET_SINGLE_PIC_BASE
19535 && TARGET_TOC && TARGET_MINIMAL_TOC)))
19536 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19537 && !TARGET_SINGLE_PIC_BASE
19538 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19539 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19542 /* Emit function prologue as insns. */
19544 void
19545 rs6000_emit_prologue (void)
19547 rs6000_stack_t *info = rs6000_stack_info ();
19548 enum machine_mode reg_mode = Pmode;
19549 int reg_size = TARGET_32BIT ? 4 : 8;
19550 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19551 rtx frame_reg_rtx = sp_reg_rtx;
19552 unsigned int cr_save_regno;
19553 rtx cr_save_rtx = NULL_RTX;
19554 rtx insn;
19555 int strategy;
19556 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19557 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19558 && call_used_regs[STATIC_CHAIN_REGNUM]);
19559 /* Offset to top of frame for frame_reg and sp respectively. */
19560 HOST_WIDE_INT frame_off = 0;
19561 HOST_WIDE_INT sp_off = 0;
19563 #ifdef ENABLE_CHECKING
19564 /* Track and check usage of r0, r11, r12. */
19565 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
19566 #define START_USE(R) do \
19568 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19569 reg_inuse |= 1 << (R); \
19570 } while (0)
19571 #define END_USE(R) do \
19573 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
19574 reg_inuse &= ~(1 << (R)); \
19575 } while (0)
19576 #define NOT_INUSE(R) do \
19578 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
19579 } while (0)
19580 #else
19581 #define START_USE(R) do {} while (0)
19582 #define END_USE(R) do {} while (0)
19583 #define NOT_INUSE(R) do {} while (0)
19584 #endif
19586 if (flag_stack_usage_info)
19587 current_function_static_stack_size = info->total_size;
19589 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19590 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19592 if (TARGET_FIX_AND_CONTINUE)
19594 /* gdb on darwin arranges to forward a function from the old
19595 address by modifying the first 5 instructions of the function
19596 to branch to the overriding function. This is necessary to
19597 permit function pointers that point to the old function to
19598 actually forward to the new function. */
19599 emit_insn (gen_nop ());
19600 emit_insn (gen_nop ());
19601 emit_insn (gen_nop ());
19602 emit_insn (gen_nop ());
19603 emit_insn (gen_nop ());
19606 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19608 reg_mode = V2SImode;
19609 reg_size = 8;
19612 /* Handle world saves specially here. */
19613 if (WORLD_SAVE_P (info))
19615 int i, j, sz;
19616 rtx treg;
19617 rtvec p;
19618 rtx reg0;
19620 /* save_world expects lr in r0. */
19621 reg0 = gen_rtx_REG (Pmode, 0);
19622 if (info->lr_save_p)
19624 insn = emit_move_insn (reg0,
19625 gen_rtx_REG (Pmode, LR_REGNO));
19626 RTX_FRAME_RELATED_P (insn) = 1;
19629 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19630 assumptions about the offsets of various bits of the stack
19631 frame. */
19632 gcc_assert (info->gp_save_offset == -220
19633 && info->fp_save_offset == -144
19634 && info->lr_save_offset == 8
19635 && info->cr_save_offset == 4
19636 && info->push_p
19637 && info->lr_save_p
19638 && (!crtl->calls_eh_return
19639 || info->ehrd_offset == -432)
19640 && info->vrsave_save_offset == -224
19641 && info->altivec_save_offset == -416);
19643 treg = gen_rtx_REG (SImode, 11);
19644 emit_move_insn (treg, GEN_INT (-info->total_size));
19646 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19647 in R11. It also clobbers R12, so beware! */
19649 /* Preserve CR2 for save_world prologues */
19650 sz = 5;
19651 sz += 32 - info->first_gp_reg_save;
19652 sz += 64 - info->first_fp_reg_save;
19653 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19654 p = rtvec_alloc (sz);
19655 j = 0;
19656 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19657 gen_rtx_REG (SImode,
19658 LR_REGNO));
19659 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19660 gen_rtx_SYMBOL_REF (Pmode,
19661 "*save_world"));
19662 /* We do floats first so that the instruction pattern matches
19663 properly. */
19664 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19665 RTVEC_ELT (p, j++)
19666 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19667 ? DFmode : SFmode,
19668 info->first_fp_reg_save + i),
19669 frame_reg_rtx,
19670 info->fp_save_offset + frame_off + 8 * i);
19671 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19672 RTVEC_ELT (p, j++)
19673 = gen_frame_store (gen_rtx_REG (V4SImode,
19674 info->first_altivec_reg_save + i),
19675 frame_reg_rtx,
19676 info->altivec_save_offset + frame_off + 16 * i);
19677 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19678 RTVEC_ELT (p, j++)
19679 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19680 frame_reg_rtx,
19681 info->gp_save_offset + frame_off + reg_size * i);
19683 /* CR register traditionally saved as CR2. */
19684 RTVEC_ELT (p, j++)
19685 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
19686 frame_reg_rtx, info->cr_save_offset + frame_off);
19687 /* Explain about use of R0. */
19688 if (info->lr_save_p)
19689 RTVEC_ELT (p, j++)
19690 = gen_frame_store (reg0,
19691 frame_reg_rtx, info->lr_save_offset + frame_off);
19692 /* Explain what happens to the stack pointer. */
19694 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19695 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19698 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19699 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19700 treg, GEN_INT (-info->total_size));
19701 sp_off = frame_off = info->total_size;
19704 strategy = info->savres_strategy;
19706 /* For V.4, update stack before we do any saving and set back pointer. */
19707 if (! WORLD_SAVE_P (info)
19708 && info->push_p
19709 && (DEFAULT_ABI == ABI_V4
19710 || crtl->calls_eh_return))
19712 bool need_r11 = (TARGET_SPE
19713 ? (!(strategy & SAVE_INLINE_GPRS)
19714 && info->spe_64bit_regs_used == 0)
19715 : (!(strategy & SAVE_INLINE_FPRS)
19716 || !(strategy & SAVE_INLINE_GPRS)
19717 || !(strategy & SAVE_INLINE_VRS)));
19718 int ptr_regno = -1;
19719 rtx ptr_reg = NULL_RTX;
19720 int ptr_off = 0;
19722 if (info->total_size < 32767)
19723 frame_off = info->total_size;
19724 else if (need_r11)
19725 ptr_regno = 11;
19726 else if (info->cr_save_p
19727 || info->lr_save_p
19728 || info->first_fp_reg_save < 64
19729 || info->first_gp_reg_save < 32
19730 || info->altivec_size != 0
19731 || info->vrsave_mask != 0
19732 || crtl->calls_eh_return)
19733 ptr_regno = 12;
19734 else
19736 /* The prologue won't be saving any regs so there is no need
19737 to set up a frame register to access any frame save area.
19738 We also won't be using frame_off anywhere below, but set
19739 the correct value anyway to protect against future
19740 changes to this function. */
19741 frame_off = info->total_size;
19743 if (ptr_regno != -1)
19745 /* Set up the frame offset to that needed by the first
19746 out-of-line save function. */
19747 START_USE (ptr_regno);
19748 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19749 frame_reg_rtx = ptr_reg;
19750 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
19751 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
19752 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
19753 ptr_off = info->gp_save_offset + info->gp_size;
19754 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
19755 ptr_off = info->altivec_save_offset + info->altivec_size;
19756 frame_off = -ptr_off;
19758 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
19759 sp_off = info->total_size;
19760 if (frame_reg_rtx != sp_reg_rtx)
19761 rs6000_emit_stack_tie (frame_reg_rtx, false);
19764 /* If we use the link register, get it into r0. */
19765 if (!WORLD_SAVE_P (info) && info->lr_save_p)
19767 rtx addr, reg, mem;
19769 reg = gen_rtx_REG (Pmode, 0);
19770 START_USE (0);
19771 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
19772 RTX_FRAME_RELATED_P (insn) = 1;
19774 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19775 | SAVE_NOINLINE_FPRS_SAVES_LR)))
19777 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19778 GEN_INT (info->lr_save_offset + frame_off));
19779 mem = gen_rtx_MEM (Pmode, addr);
19780 /* This should not be of rs6000_sr_alias_set, because of
19781 __builtin_return_address. */
19783 insn = emit_move_insn (mem, reg);
19784 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19785 NULL_RTX, NULL_RTX);
19786 END_USE (0);
19790 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
19791 r12 will be needed by out-of-line gpr restore. */
19792 cr_save_regno = (DEFAULT_ABI == ABI_AIX
19793 && !(strategy & (SAVE_INLINE_GPRS
19794 | SAVE_NOINLINE_GPRS_SAVES_LR))
19795 ? 11 : 12);
19796 if (!WORLD_SAVE_P (info)
19797 && info->cr_save_p
19798 && REGNO (frame_reg_rtx) != cr_save_regno
19799 && !(using_static_chain_p && cr_save_regno == 11))
19801 rtx set;
19803 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
19804 START_USE (cr_save_regno);
19805 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19806 RTX_FRAME_RELATED_P (insn) = 1;
19807 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19808 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19809 But that's OK. All we have to do is specify that _one_ condition
19810 code register is saved in this stack slot. The thrower's epilogue
19811 will then restore all the call-saved registers.
19812 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19813 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19814 gen_rtx_REG (SImode, CR2_REGNO));
19815 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19818 /* Do any required saving of fpr's. If only one or two to save, do
19819 it ourselves. Otherwise, call function. */
19820 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
19822 int i;
19823 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19824 if (save_reg_p (info->first_fp_reg_save + i))
19825 emit_frame_save (frame_reg_rtx,
19826 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
19827 ? DFmode : SFmode),
19828 info->first_fp_reg_save + i,
19829 info->fp_save_offset + frame_off + 8 * i,
19830 sp_off - frame_off);
19832 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19834 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
19835 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
19836 unsigned ptr_regno = ptr_regno_for_savres (sel);
19837 rtx ptr_reg = frame_reg_rtx;
19839 if (REGNO (frame_reg_rtx) == ptr_regno)
19840 gcc_checking_assert (frame_off == 0);
19841 else
19843 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19844 NOT_INUSE (ptr_regno);
19845 emit_insn (gen_add3_insn (ptr_reg,
19846 frame_reg_rtx, GEN_INT (frame_off)));
19848 insn = rs6000_emit_savres_rtx (info, ptr_reg,
19849 info->fp_save_offset,
19850 info->lr_save_offset,
19851 DFmode, sel);
19852 rs6000_frame_related (insn, ptr_reg, sp_off,
19853 NULL_RTX, NULL_RTX);
19854 if (lr)
19855 END_USE (0);
19858 /* Save GPRs. This is done as a PARALLEL if we are using
19859 the store-multiple instructions. */
19860 if (!WORLD_SAVE_P (info)
19861 && TARGET_SPE_ABI
19862 && info->spe_64bit_regs_used != 0
19863 && info->first_gp_reg_save != 32)
19865 int i;
19866 rtx spe_save_area_ptr;
19867 HOST_WIDE_INT save_off;
19868 int ool_adjust = 0;
19870 /* Determine whether we can address all of the registers that need
19871 to be saved with an offset from frame_reg_rtx that fits in
19872 the small const field for SPE memory instructions. */
19873 int spe_regs_addressable
19874 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
19875 + reg_size * (32 - info->first_gp_reg_save - 1))
19876 && (strategy & SAVE_INLINE_GPRS));
19878 if (spe_regs_addressable)
19880 spe_save_area_ptr = frame_reg_rtx;
19881 save_off = frame_off;
19883 else
19885 /* Make r11 point to the start of the SPE save area. We need
19886 to be careful here if r11 is holding the static chain. If
19887 it is, then temporarily save it in r0. */
19888 HOST_WIDE_INT offset;
19890 if (!(strategy & SAVE_INLINE_GPRS))
19891 ool_adjust = 8 * (info->first_gp_reg_save
19892 - (FIRST_SAVRES_REGISTER + 1));
19893 offset = info->spe_gp_save_offset + frame_off - ool_adjust;
19894 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19895 save_off = frame_off - offset;
19897 if (using_static_chain_p)
19899 rtx r0 = gen_rtx_REG (Pmode, 0);
19901 START_USE (0);
19902 gcc_assert (info->first_gp_reg_save > 11);
19904 emit_move_insn (r0, spe_save_area_ptr);
19906 else if (REGNO (frame_reg_rtx) != 11)
19907 START_USE (11);
19909 emit_insn (gen_addsi3 (spe_save_area_ptr,
19910 frame_reg_rtx, GEN_INT (offset)));
19911 if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
19912 frame_off = -info->spe_gp_save_offset + ool_adjust;
19915 if ((strategy & SAVE_INLINE_GPRS))
19917 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19918 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19919 emit_frame_save (spe_save_area_ptr, reg_mode,
19920 info->first_gp_reg_save + i,
19921 (info->spe_gp_save_offset + save_off
19922 + reg_size * i),
19923 sp_off - save_off);
19925 else
19927 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19928 info->spe_gp_save_offset + save_off,
19929 0, reg_mode,
19930 SAVRES_SAVE | SAVRES_GPR);
19932 rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
19933 NULL_RTX, NULL_RTX);
19936 /* Move the static chain pointer back. */
19937 if (!spe_regs_addressable)
19939 if (using_static_chain_p)
19941 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
19942 END_USE (0);
19944 else if (REGNO (frame_reg_rtx) != 11)
19945 END_USE (11);
19948 else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
19950 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
19951 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
19952 unsigned ptr_regno = ptr_regno_for_savres (sel);
19953 rtx ptr_reg = frame_reg_rtx;
19954 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
19955 int end_save = info->gp_save_offset + info->gp_size;
19956 int ptr_off;
19958 if (!ptr_set_up)
19959 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
19961 /* Need to adjust r11 (r12) if we saved any FPRs. */
19962 if (end_save + frame_off != 0)
19964 rtx offset = GEN_INT (end_save + frame_off);
19966 if (ptr_set_up)
19967 frame_off = -end_save;
19968 else
19969 NOT_INUSE (ptr_regno);
19970 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
19972 else if (!ptr_set_up)
19974 NOT_INUSE (ptr_regno);
19975 emit_move_insn (ptr_reg, frame_reg_rtx);
19977 ptr_off = -end_save;
19978 insn = rs6000_emit_savres_rtx (info, ptr_reg,
19979 info->gp_save_offset + ptr_off,
19980 info->lr_save_offset + ptr_off,
19981 reg_mode, sel);
19982 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
19983 NULL_RTX, NULL_RTX);
19984 if (lr)
19985 END_USE (0);
19987 else if (!WORLD_SAVE_P (info) && (strategy & SAVRES_MULTIPLE))
19989 rtvec p;
19990 int i;
19991 p = rtvec_alloc (32 - info->first_gp_reg_save);
19992 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19993 RTVEC_ELT (p, i)
19994 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
19995 frame_reg_rtx,
19996 info->gp_save_offset + frame_off + reg_size * i);
19997 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19998 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
19999 NULL_RTX, NULL_RTX);
20001 else if (!WORLD_SAVE_P (info))
20003 int i;
20004 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20005 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20006 emit_frame_save (frame_reg_rtx, reg_mode,
20007 info->first_gp_reg_save + i,
20008 info->gp_save_offset + frame_off + reg_size * i,
20009 sp_off - frame_off);
20012 if (crtl->calls_eh_return)
20014 unsigned int i;
20015 rtvec p;
20017 for (i = 0; ; ++i)
20019 unsigned int regno = EH_RETURN_DATA_REGNO (i);
20020 if (regno == INVALID_REGNUM)
20021 break;
20024 p = rtvec_alloc (i);
20026 for (i = 0; ; ++i)
20028 unsigned int regno = EH_RETURN_DATA_REGNO (i);
20029 if (regno == INVALID_REGNUM)
20030 break;
20032 insn
20033 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
20034 sp_reg_rtx,
20035 info->ehrd_offset + sp_off + reg_size * (int) i);
20036 RTVEC_ELT (p, i) = insn;
20037 RTX_FRAME_RELATED_P (insn) = 1;
20040 insn = emit_insn (gen_blockage ());
20041 RTX_FRAME_RELATED_P (insn) = 1;
20042 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
20045 /* In AIX ABI we need to make sure r2 is really saved. */
20046 if (TARGET_AIX && crtl->calls_eh_return)
20048 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
20049 rtx save_insn, join_insn, note;
20050 long toc_restore_insn;
20052 tmp_reg = gen_rtx_REG (Pmode, 11);
20053 tmp_reg_si = gen_rtx_REG (SImode, 11);
20054 if (using_static_chain_p)
20056 START_USE (0);
20057 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
20059 else
20060 START_USE (11);
20061 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
20062 /* Peek at instruction to which this function returns. If it's
20063 restoring r2, then we know we've already saved r2. We can't
20064 unconditionally save r2 because the value we have will already
20065 be updated if we arrived at this function via a plt call or
20066 toc adjusting stub. */
20067 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
20068 toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
20069 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
20070 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
20071 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
20072 validate_condition_mode (EQ, CCUNSmode);
20073 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
20074 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
20075 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
20076 toc_save_done = gen_label_rtx ();
20077 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
20078 gen_rtx_EQ (VOIDmode, compare_result,
20079 const0_rtx),
20080 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
20081 pc_rtx);
20082 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
20083 JUMP_LABEL (jump) = toc_save_done;
20084 LABEL_NUSES (toc_save_done) += 1;
20086 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
20087 TOC_REGNUM, frame_off + 5 * reg_size,
20088 sp_off - frame_off);
20090 emit_label (toc_save_done);
20092 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
20093 have a CFG that has different saves along different paths.
20094 Move the note to a dummy blockage insn, which describes that
20095 R2 is unconditionally saved after the label. */
20096 /* ??? An alternate representation might be a special insn pattern
20097 containing both the branch and the store. That might let the
20098 code that minimizes the number of DW_CFA_advance opcodes better
20099 freedom in placing the annotations. */
20100 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
20101 if (note)
20102 remove_note (save_insn, note);
20103 else
20104 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
20105 copy_rtx (PATTERN (save_insn)), NULL_RTX);
20106 RTX_FRAME_RELATED_P (save_insn) = 0;
20108 join_insn = emit_insn (gen_blockage ());
20109 REG_NOTES (join_insn) = note;
20110 RTX_FRAME_RELATED_P (join_insn) = 1;
20112 if (using_static_chain_p)
20114 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
20115 END_USE (0);
20117 else
20118 END_USE (11);
20121 /* Save CR if we use any that must be preserved. */
20122 if (!WORLD_SAVE_P (info) && info->cr_save_p)
20124 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20125 GEN_INT (info->cr_save_offset + frame_off));
20126 rtx mem = gen_frame_mem (SImode, addr);
20127 /* See the large comment above about why CR2_REGNO is used. */
20128 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
20130 /* If we didn't copy cr before, do so now using r0. */
20131 if (cr_save_rtx == NULL_RTX)
20133 rtx set;
20135 START_USE (0);
20136 cr_save_rtx = gen_rtx_REG (SImode, 0);
20137 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
20138 RTX_FRAME_RELATED_P (insn) = 1;
20139 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
20140 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
20142 insn = emit_move_insn (mem, cr_save_rtx);
20143 END_USE (REGNO (cr_save_rtx));
20145 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20146 NULL_RTX, NULL_RTX);
20149 /* Update stack and set back pointer unless this is V.4,
20150 for which it was done previously. */
20151 if (!WORLD_SAVE_P (info) && info->push_p
20152 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
20154 rtx ptr_reg = NULL;
20155 int ptr_off = 0;
20157 /* If saving altivec regs we need to be able to address all save
20158 locations using a 16-bit offset. */
20159 if ((strategy & SAVE_INLINE_VRS) == 0
20160 || (info->altivec_size != 0
20161 && (info->altivec_save_offset + info->altivec_size - 16
20162 + info->total_size - frame_off) > 32767)
20163 || (info->vrsave_size != 0
20164 && (info->vrsave_save_offset
20165 + info->total_size - frame_off) > 32767))
20167 int sel = SAVRES_SAVE | SAVRES_VR;
20168 unsigned ptr_regno = ptr_regno_for_savres (sel);
20170 if (using_static_chain_p
20171 && ptr_regno == STATIC_CHAIN_REGNUM)
20172 ptr_regno = 12;
20173 if (REGNO (frame_reg_rtx) != ptr_regno)
20174 START_USE (ptr_regno);
20175 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
20176 frame_reg_rtx = ptr_reg;
20177 ptr_off = info->altivec_save_offset + info->altivec_size;
20178 frame_off = -ptr_off;
20180 else if (REGNO (frame_reg_rtx) == 1)
20181 frame_off = info->total_size;
20182 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
20183 sp_off = info->total_size;
20184 if (frame_reg_rtx != sp_reg_rtx)
20185 rs6000_emit_stack_tie (frame_reg_rtx, false);
20188 /* Set frame pointer, if needed. */
20189 if (frame_pointer_needed)
20191 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
20192 sp_reg_rtx);
20193 RTX_FRAME_RELATED_P (insn) = 1;
20196 /* Save AltiVec registers if needed. Save here because the red zone does
20197 not always include AltiVec registers. */
20198 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
20199 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
20201 int end_save = info->altivec_save_offset + info->altivec_size;
20202 int ptr_off;
20203 /* Oddly, the vector save/restore functions point r0 at the end
20204 of the save area, then use r11 or r12 to load offsets for
20205 [reg+reg] addressing. */
20206 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20207 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
20208 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20210 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
20211 NOT_INUSE (0);
20212 if (end_save + frame_off != 0)
20214 rtx offset = GEN_INT (end_save + frame_off);
20216 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20218 else
20219 emit_move_insn (ptr_reg, frame_reg_rtx);
20221 ptr_off = -end_save;
20222 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20223 info->altivec_save_offset + ptr_off,
20224 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
20225 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
20226 NULL_RTX, NULL_RTX);
20227 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20229 /* The oddity mentioned above clobbered our frame reg. */
20230 emit_move_insn (frame_reg_rtx, ptr_reg);
20231 frame_off = ptr_off;
20234 else if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
20235 && info->altivec_size != 0)
20237 int i;
20239 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20240 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20242 rtx areg, savereg, mem;
20243 int offset;
20245 offset = (info->altivec_save_offset + frame_off
20246 + 16 * (i - info->first_altivec_reg_save));
20248 savereg = gen_rtx_REG (V4SImode, i);
20250 NOT_INUSE (0);
20251 areg = gen_rtx_REG (Pmode, 0);
20252 emit_move_insn (areg, GEN_INT (offset));
20254 /* AltiVec addressing mode is [reg+reg]. */
20255 mem = gen_frame_mem (V4SImode,
20256 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
20258 insn = emit_move_insn (mem, savereg);
20260 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
20261 areg, GEN_INT (offset));
20265 /* VRSAVE is a bit vector representing which AltiVec registers
20266 are used. The OS uses this to determine which vector
20267 registers to save on a context switch. We need to save
20268 VRSAVE on the stack frame, add whatever AltiVec registers we
20269 used in this function, and do the corresponding magic in the
20270 epilogue. */
20272 if (!WORLD_SAVE_P (info)
20273 && TARGET_ALTIVEC
20274 && TARGET_ALTIVEC_VRSAVE
20275 && info->vrsave_mask != 0)
20277 rtx reg, vrsave;
20278 int offset;
20279 int save_regno;
20281 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
20282 be using r12 as frame_reg_rtx and r11 as the static chain
20283 pointer for nested functions. */
20284 save_regno = 12;
20285 if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p)
20286 save_regno = 11;
20287 else if (REGNO (frame_reg_rtx) == 12)
20289 save_regno = 11;
20290 if (using_static_chain_p)
20291 save_regno = 0;
20294 NOT_INUSE (save_regno);
20295 reg = gen_rtx_REG (SImode, save_regno);
20296 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
20297 if (TARGET_MACHO)
20298 emit_insn (gen_get_vrsave_internal (reg));
20299 else
20300 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
20302 /* Save VRSAVE. */
20303 offset = info->vrsave_save_offset + frame_off;
20304 insn = emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
20306 /* Include the registers in the mask. */
20307 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
20309 insn = emit_insn (generate_set_vrsave (reg, info, 0));
20312 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
20313 if (!TARGET_SINGLE_PIC_BASE
20314 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
20315 || (DEFAULT_ABI == ABI_V4
20316 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
20317 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
20319 /* If emit_load_toc_table will use the link register, we need to save
20320 it. We use R12 for this purpose because emit_load_toc_table
20321 can use register 0. This allows us to use a plain 'blr' to return
20322 from the procedure more often. */
20323 int save_LR_around_toc_setup = (TARGET_ELF
20324 && DEFAULT_ABI != ABI_AIX
20325 && flag_pic
20326 && ! info->lr_save_p
20327 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
20328 if (save_LR_around_toc_setup)
20330 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20331 rtx tmp = gen_rtx_REG (Pmode, 12);
20333 insn = emit_move_insn (tmp, lr);
20334 RTX_FRAME_RELATED_P (insn) = 1;
20336 rs6000_emit_load_toc_table (TRUE);
20338 insn = emit_move_insn (lr, tmp);
20339 add_reg_note (insn, REG_CFA_RESTORE, lr);
20340 RTX_FRAME_RELATED_P (insn) = 1;
20342 else
20343 rs6000_emit_load_toc_table (TRUE);
20346 #if TARGET_MACHO
20347 if (!TARGET_SINGLE_PIC_BASE
20348 && DEFAULT_ABI == ABI_DARWIN
20349 && flag_pic && crtl->uses_pic_offset_table)
20351 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20352 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
20354 /* Save and restore LR locally around this call (in R0). */
20355 if (!info->lr_save_p)
20356 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
20358 emit_insn (gen_load_macho_picbase (src));
20360 emit_move_insn (gen_rtx_REG (Pmode,
20361 RS6000_PIC_OFFSET_TABLE_REGNUM),
20362 lr);
20364 if (!info->lr_save_p)
20365 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
20367 #endif
20369 /* If we need to, save the TOC register after doing the stack setup.
20370 Do not emit eh frame info for this save. The unwinder wants info,
20371 conceptually attached to instructions in this function, about
20372 register values in the caller of this function. This R2 may have
20373 already been changed from the value in the caller.
20374 We don't attempt to write accurate DWARF EH frame info for R2
20375 because code emitted by gcc for a (non-pointer) function call
20376 doesn't save and restore R2. Instead, R2 is managed out-of-line
20377 by a linker generated plt call stub when the function resides in
20378 a shared library. This behaviour is costly to describe in DWARF,
20379 both in terms of the size of DWARF info and the time taken in the
20380 unwinder to interpret it. R2 changes, apart from the
20381 calls_eh_return case earlier in this function, are handled by
20382 linux-unwind.h frob_update_context. */
20383 if (rs6000_save_toc_in_prologue_p ())
20385 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
20386 emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size));
20390 /* Write function prologue. */
20392 static void
20393 rs6000_output_function_prologue (FILE *file,
20394 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20396 rs6000_stack_t *info = rs6000_stack_info ();
20398 if (TARGET_DEBUG_STACK)
20399 debug_stack_info (info);
20401 /* Write .extern for any function we will call to save and restore
20402 fp values. */
20403 if (info->first_fp_reg_save < 64
20404 && !TARGET_MACHO
20405 && !TARGET_ELF)
20407 char *name;
20408 int regno = info->first_fp_reg_save - 32;
20410 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20412 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
20413 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
20414 name = rs6000_savres_routine_name (info, regno, sel);
20415 fprintf (file, "\t.extern %s\n", name);
20417 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20419 bool lr = (info->savres_strategy
20420 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20421 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20422 name = rs6000_savres_routine_name (info, regno, sel);
20423 fprintf (file, "\t.extern %s\n", name);
20427 rs6000_pic_labelno++;
20430 /* Non-zero if vmx regs are restored before the frame pop, zero if
20431 we restore after the pop when possible. */
20432 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20434 /* Restoring cr is a two step process: loading a reg from the frame
20435 save, then moving the reg to cr. For ABI_V4 we must let the
20436 unwinder know that the stack location is no longer valid at or
20437 before the stack deallocation, but we can't emit a cfa_restore for
20438 cr at the stack deallocation like we do for other registers.
20439 The trouble is that it is possible for the move to cr to be
20440 scheduled after the stack deallocation. So say exactly where cr
20441 is located on each of the two insns. */
20443 static rtx
20444 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
20446 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
20447 rtx reg = gen_rtx_REG (SImode, regno);
20448 rtx insn = emit_move_insn (reg, mem);
20450 if (!exit_func && DEFAULT_ABI == ABI_V4)
20452 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20453 rtx set = gen_rtx_SET (VOIDmode, reg, cr);
20455 add_reg_note (insn, REG_CFA_REGISTER, set);
20456 RTX_FRAME_RELATED_P (insn) = 1;
20458 return reg;
20461 /* Reload CR from REG. */
20463 static void
20464 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
20466 int count = 0;
20467 int i;
20469 if (using_mfcr_multiple)
20471 for (i = 0; i < 8; i++)
20472 if (save_reg_p (CR0_REGNO + i))
20473 count++;
20474 gcc_assert (count);
20477 if (using_mfcr_multiple && count > 1)
20479 rtvec p;
20480 int ndx;
20482 p = rtvec_alloc (count);
20484 ndx = 0;
20485 for (i = 0; i < 8; i++)
20486 if (save_reg_p (CR0_REGNO + i))
20488 rtvec r = rtvec_alloc (2);
20489 RTVEC_ELT (r, 0) = reg;
20490 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20491 RTVEC_ELT (p, ndx) =
20492 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i),
20493 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20494 ndx++;
20496 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20497 gcc_assert (ndx == count);
20499 else
20500 for (i = 0; i < 8; i++)
20501 if (save_reg_p (CR0_REGNO + i))
20502 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i),
20503 reg));
20505 if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
20507 rtx insn = get_last_insn ();
20508 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
20510 add_reg_note (insn, REG_CFA_RESTORE, cr);
20511 RTX_FRAME_RELATED_P (insn) = 1;
20515 /* Like cr, the move to lr instruction can be scheduled after the
20516 stack deallocation, but unlike cr, its stack frame save is still
20517 valid. So we only need to emit the cfa_restore on the correct
20518 instruction. */
20520 static void
20521 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
20523 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
20524 rtx reg = gen_rtx_REG (Pmode, regno);
20526 emit_move_insn (reg, mem);
20529 static void
20530 restore_saved_lr (int regno, bool exit_func)
20532 rtx reg = gen_rtx_REG (Pmode, regno);
20533 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20534 rtx insn = emit_move_insn (lr, reg);
20536 if (!exit_func && flag_shrink_wrap)
20538 add_reg_note (insn, REG_CFA_RESTORE, lr);
20539 RTX_FRAME_RELATED_P (insn) = 1;
20543 static rtx
20544 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
20546 if (info->cr_save_p)
20547 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20548 gen_rtx_REG (SImode, CR2_REGNO),
20549 cfa_restores);
20550 if (info->lr_save_p)
20551 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20552 gen_rtx_REG (Pmode, LR_REGNO),
20553 cfa_restores);
20554 return cfa_restores;
20557 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20558 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20559 below stack pointer not cloberred by signals. */
20561 static inline bool
20562 offset_below_red_zone_p (HOST_WIDE_INT offset)
20564 return offset < (DEFAULT_ABI == ABI_V4
20566 : TARGET_32BIT ? -220 : -288);
20569 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20571 static void
20572 emit_cfa_restores (rtx cfa_restores)
20574 rtx insn = get_last_insn ();
20575 rtx *loc = &REG_NOTES (insn);
20577 while (*loc)
20578 loc = &XEXP (*loc, 1);
20579 *loc = cfa_restores;
20580 RTX_FRAME_RELATED_P (insn) = 1;
20583 /* Emit function epilogue as insns. */
20585 void
20586 rs6000_emit_epilogue (int sibcall)
20588 rs6000_stack_t *info;
20589 int restoring_GPRs_inline;
20590 int restoring_FPRs_inline;
20591 int using_load_multiple;
20592 int using_mtcr_multiple;
20593 int use_backchain_to_restore_sp;
20594 int restore_lr;
20595 int strategy;
20596 HOST_WIDE_INT frame_off = 0;
20597 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20598 rtx frame_reg_rtx = sp_reg_rtx;
20599 rtx cfa_restores = NULL_RTX;
20600 rtx insn;
20601 rtx cr_save_reg = NULL_RTX;
20602 enum machine_mode reg_mode = Pmode;
20603 int reg_size = TARGET_32BIT ? 4 : 8;
20604 int i;
20605 bool exit_func;
20606 unsigned ptr_regno;
20608 info = rs6000_stack_info ();
20610 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20612 reg_mode = V2SImode;
20613 reg_size = 8;
20616 strategy = info->savres_strategy;
20617 using_load_multiple = strategy & SAVRES_MULTIPLE;
20618 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20619 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20620 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20621 || rs6000_cpu == PROCESSOR_PPC603
20622 || rs6000_cpu == PROCESSOR_PPC750
20623 || optimize_size);
20624 /* Restore via the backchain when we have a large frame, since this
20625 is more efficient than an addis, addi pair. The second condition
20626 here will not trigger at the moment; We don't actually need a
20627 frame pointer for alloca, but the generic parts of the compiler
20628 give us one anyway. */
20629 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20630 || (cfun->calls_alloca
20631 && !frame_pointer_needed));
20632 restore_lr = (info->lr_save_p
20633 && (restoring_FPRs_inline
20634 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20635 && (restoring_GPRs_inline
20636 || info->first_fp_reg_save < 64));
20638 if (WORLD_SAVE_P (info))
20640 int i, j;
20641 char rname[30];
20642 const char *alloc_rname;
20643 rtvec p;
20645 /* eh_rest_world_r10 will return to the location saved in the LR
20646 stack slot (which is not likely to be our caller.)
20647 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20648 rest_world is similar, except any R10 parameter is ignored.
20649 The exception-handling stuff that was here in 2.95 is no
20650 longer necessary. */
20652 p = rtvec_alloc (9
20654 + 32 - info->first_gp_reg_save
20655 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20656 + 63 + 1 - info->first_fp_reg_save);
20658 strcpy (rname, ((crtl->calls_eh_return) ?
20659 "*eh_rest_world_r10" : "*rest_world"));
20660 alloc_rname = ggc_strdup (rname);
20662 j = 0;
20663 RTVEC_ELT (p, j++) = ret_rtx;
20664 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20665 gen_rtx_REG (Pmode,
20666 LR_REGNO));
20667 RTVEC_ELT (p, j++)
20668 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20669 /* The instruction pattern requires a clobber here;
20670 it is shared with the restVEC helper. */
20671 RTVEC_ELT (p, j++)
20672 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20675 /* CR register traditionally saved as CR2. */
20676 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
20677 RTVEC_ELT (p, j++)
20678 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
20679 if (flag_shrink_wrap)
20681 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20682 gen_rtx_REG (Pmode, LR_REGNO),
20683 cfa_restores);
20684 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20688 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20690 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20691 RTVEC_ELT (p, j++)
20692 = gen_frame_load (reg,
20693 frame_reg_rtx, info->gp_save_offset + reg_size * i);
20694 if (flag_shrink_wrap)
20695 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20697 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20699 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20700 RTVEC_ELT (p, j++)
20701 = gen_frame_load (reg,
20702 frame_reg_rtx, info->altivec_save_offset + 16 * i);
20703 if (flag_shrink_wrap)
20704 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20706 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20708 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
20709 ? DFmode : SFmode),
20710 info->first_fp_reg_save + i);
20711 RTVEC_ELT (p, j++)
20712 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
20713 if (flag_shrink_wrap)
20714 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20716 RTVEC_ELT (p, j++)
20717 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20718 RTVEC_ELT (p, j++)
20719 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20720 RTVEC_ELT (p, j++)
20721 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20722 RTVEC_ELT (p, j++)
20723 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20724 RTVEC_ELT (p, j++)
20725 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20726 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20728 if (flag_shrink_wrap)
20730 REG_NOTES (insn) = cfa_restores;
20731 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20732 RTX_FRAME_RELATED_P (insn) = 1;
20734 return;
20737 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
20738 if (info->push_p)
20739 frame_off = info->total_size;
20741 /* Restore AltiVec registers if we must do so before adjusting the
20742 stack. */
20743 if (TARGET_ALTIVEC_ABI
20744 && info->altivec_size != 0
20745 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20746 || (DEFAULT_ABI != ABI_V4
20747 && offset_below_red_zone_p (info->altivec_save_offset))))
20749 int i;
20750 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20752 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
20753 if (use_backchain_to_restore_sp)
20755 int frame_regno = 11;
20757 if ((strategy & REST_INLINE_VRS) == 0)
20759 /* Of r11 and r12, select the one not clobbered by an
20760 out-of-line restore function for the frame register. */
20761 frame_regno = 11 + 12 - scratch_regno;
20763 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
20764 emit_move_insn (frame_reg_rtx,
20765 gen_rtx_MEM (Pmode, sp_reg_rtx));
20766 frame_off = 0;
20768 else if (frame_pointer_needed)
20769 frame_reg_rtx = hard_frame_pointer_rtx;
20771 if ((strategy & REST_INLINE_VRS) == 0)
20773 int end_save = info->altivec_save_offset + info->altivec_size;
20774 int ptr_off;
20775 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20776 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20778 if (end_save + frame_off != 0)
20780 rtx offset = GEN_INT (end_save + frame_off);
20782 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20784 else
20785 emit_move_insn (ptr_reg, frame_reg_rtx);
20787 ptr_off = -end_save;
20788 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20789 info->altivec_save_offset + ptr_off,
20790 0, V4SImode, SAVRES_VR);
20792 else
20794 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20795 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20797 rtx addr, areg, mem, reg;
20799 areg = gen_rtx_REG (Pmode, 0);
20800 emit_move_insn
20801 (areg, GEN_INT (info->altivec_save_offset
20802 + frame_off
20803 + 16 * (i - info->first_altivec_reg_save)));
20805 /* AltiVec addressing mode is [reg+reg]. */
20806 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20807 mem = gen_frame_mem (V4SImode, addr);
20809 reg = gen_rtx_REG (V4SImode, i);
20810 emit_move_insn (reg, mem);
20814 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20815 if (((strategy & REST_INLINE_VRS) == 0
20816 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
20817 && (flag_shrink_wrap
20818 || (offset_below_red_zone_p
20819 (info->altivec_save_offset
20820 + 16 * (i - info->first_altivec_reg_save)))))
20822 rtx reg = gen_rtx_REG (V4SImode, i);
20823 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20827 /* Restore VRSAVE if we must do so before adjusting the stack. */
20828 if (TARGET_ALTIVEC
20829 && TARGET_ALTIVEC_VRSAVE
20830 && info->vrsave_mask != 0
20831 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20832 || (DEFAULT_ABI != ABI_V4
20833 && offset_below_red_zone_p (info->vrsave_save_offset))))
20835 rtx reg;
20837 if (frame_reg_rtx == sp_reg_rtx)
20839 if (use_backchain_to_restore_sp)
20841 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20842 emit_move_insn (frame_reg_rtx,
20843 gen_rtx_MEM (Pmode, sp_reg_rtx));
20844 frame_off = 0;
20846 else if (frame_pointer_needed)
20847 frame_reg_rtx = hard_frame_pointer_rtx;
20850 reg = gen_rtx_REG (SImode, 12);
20851 emit_insn (gen_frame_load (reg, frame_reg_rtx,
20852 info->vrsave_save_offset + frame_off));
20854 emit_insn (generate_set_vrsave (reg, info, 1));
20857 insn = NULL_RTX;
20858 /* If we have a large stack frame, restore the old stack pointer
20859 using the backchain. */
20860 if (use_backchain_to_restore_sp)
20862 if (frame_reg_rtx == sp_reg_rtx)
20864 /* Under V.4, don't reset the stack pointer until after we're done
20865 loading the saved registers. */
20866 if (DEFAULT_ABI == ABI_V4)
20867 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20869 insn = emit_move_insn (frame_reg_rtx,
20870 gen_rtx_MEM (Pmode, sp_reg_rtx));
20871 frame_off = 0;
20873 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20874 && DEFAULT_ABI == ABI_V4)
20875 /* frame_reg_rtx has been set up by the altivec restore. */
20877 else
20879 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20880 frame_reg_rtx = sp_reg_rtx;
20883 /* If we have a frame pointer, we can restore the old stack pointer
20884 from it. */
20885 else if (frame_pointer_needed)
20887 frame_reg_rtx = sp_reg_rtx;
20888 if (DEFAULT_ABI == ABI_V4)
20889 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20890 /* Prevent reordering memory accesses against stack pointer restore. */
20891 else if (cfun->calls_alloca
20892 || offset_below_red_zone_p (-info->total_size))
20893 rs6000_emit_stack_tie (frame_reg_rtx, true);
20895 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20896 GEN_INT (info->total_size)));
20897 frame_off = 0;
20899 else if (info->push_p
20900 && DEFAULT_ABI != ABI_V4
20901 && !crtl->calls_eh_return)
20903 /* Prevent reordering memory accesses against stack pointer restore. */
20904 if (cfun->calls_alloca
20905 || offset_below_red_zone_p (-info->total_size))
20906 rs6000_emit_stack_tie (frame_reg_rtx, false);
20907 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20908 GEN_INT (info->total_size)));
20909 frame_off = 0;
20911 if (insn && frame_reg_rtx == sp_reg_rtx)
20913 if (cfa_restores)
20915 REG_NOTES (insn) = cfa_restores;
20916 cfa_restores = NULL_RTX;
20918 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20919 RTX_FRAME_RELATED_P (insn) = 1;
20922 /* Restore AltiVec registers if we have not done so already. */
20923 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20924 && TARGET_ALTIVEC_ABI
20925 && info->altivec_size != 0
20926 && (DEFAULT_ABI == ABI_V4
20927 || !offset_below_red_zone_p (info->altivec_save_offset)))
20929 int i;
20931 if ((strategy & REST_INLINE_VRS) == 0)
20933 int end_save = info->altivec_save_offset + info->altivec_size;
20934 int ptr_off;
20935 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
20936 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
20937 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
20939 if (end_save + frame_off != 0)
20941 rtx offset = GEN_INT (end_save + frame_off);
20943 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
20945 else
20946 emit_move_insn (ptr_reg, frame_reg_rtx);
20948 ptr_off = -end_save;
20949 insn = rs6000_emit_savres_rtx (info, scratch_reg,
20950 info->altivec_save_offset + ptr_off,
20951 0, V4SImode, SAVRES_VR);
20952 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
20954 /* Frame reg was clobbered by out-of-line save. Restore it
20955 from ptr_reg, and if we are calling out-of-line gpr or
20956 fpr restore set up the correct pointer and offset. */
20957 unsigned newptr_regno = 1;
20958 if (!restoring_GPRs_inline)
20960 bool lr = info->gp_save_offset + info->gp_size == 0;
20961 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
20962 newptr_regno = ptr_regno_for_savres (sel);
20963 end_save = info->gp_save_offset + info->gp_size;
20965 else if (!restoring_FPRs_inline)
20967 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
20968 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
20969 newptr_regno = ptr_regno_for_savres (sel);
20970 end_save = info->gp_save_offset + info->gp_size;
20973 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
20974 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
20976 if (end_save + ptr_off != 0)
20978 rtx offset = GEN_INT (end_save + ptr_off);
20980 frame_off = -end_save;
20981 emit_insn (gen_add3_insn (frame_reg_rtx, ptr_reg, offset));
20983 else
20985 frame_off = ptr_off;
20986 emit_move_insn (frame_reg_rtx, ptr_reg);
20990 else
20992 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20993 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20995 rtx addr, areg, mem, reg;
20997 areg = gen_rtx_REG (Pmode, 0);
20998 emit_move_insn
20999 (areg, GEN_INT (info->altivec_save_offset
21000 + frame_off
21001 + 16 * (i - info->first_altivec_reg_save)));
21003 /* AltiVec addressing mode is [reg+reg]. */
21004 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
21005 mem = gen_frame_mem (V4SImode, addr);
21007 reg = gen_rtx_REG (V4SImode, i);
21008 emit_move_insn (reg, mem);
21012 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
21013 if (((strategy & REST_INLINE_VRS) == 0
21014 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
21015 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
21017 rtx reg = gen_rtx_REG (V4SImode, i);
21018 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21022 /* Restore VRSAVE if we have not done so already. */
21023 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
21024 && TARGET_ALTIVEC
21025 && TARGET_ALTIVEC_VRSAVE
21026 && info->vrsave_mask != 0
21027 && (DEFAULT_ABI == ABI_V4
21028 || !offset_below_red_zone_p (info->vrsave_save_offset)))
21030 rtx reg;
21032 reg = gen_rtx_REG (SImode, 12);
21033 emit_insn (gen_frame_load (reg, frame_reg_rtx,
21034 info->vrsave_save_offset + frame_off));
21036 emit_insn (generate_set_vrsave (reg, info, 1));
21039 /* If we exit by an out-of-line restore function on ABI_V4 then that
21040 function will deallocate the stack, so we don't need to worry
21041 about the unwinder restoring cr from an invalid stack frame
21042 location. */
21043 exit_func = (!restoring_FPRs_inline
21044 || (!restoring_GPRs_inline
21045 && info->first_fp_reg_save == 64));
21047 /* Get the old lr if we saved it. If we are restoring registers
21048 out-of-line, then the out-of-line routines can do this for us. */
21049 if (restore_lr && restoring_GPRs_inline)
21050 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
21052 /* Get the old cr if we saved it. */
21053 if (info->cr_save_p)
21055 unsigned cr_save_regno = 12;
21057 if (!restoring_GPRs_inline)
21059 /* Ensure we don't use the register used by the out-of-line
21060 gpr register restore below. */
21061 bool lr = info->gp_save_offset + info->gp_size == 0;
21062 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
21063 int gpr_ptr_regno = ptr_regno_for_savres (sel);
21065 if (gpr_ptr_regno == 12)
21066 cr_save_regno = 11;
21067 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
21069 else if (REGNO (frame_reg_rtx) == 12)
21070 cr_save_regno = 11;
21072 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
21073 info->cr_save_offset + frame_off,
21074 exit_func);
21077 /* Set LR here to try to overlap restores below. */
21078 if (restore_lr && restoring_GPRs_inline)
21079 restore_saved_lr (0, exit_func);
21081 /* Load exception handler data registers, if needed. */
21082 if (crtl->calls_eh_return)
21084 unsigned int i, regno;
21086 if (TARGET_AIX)
21088 rtx reg = gen_rtx_REG (reg_mode, 2);
21089 emit_insn (gen_frame_load (reg, frame_reg_rtx,
21090 frame_off + 5 * reg_size));
21093 for (i = 0; ; ++i)
21095 rtx mem;
21097 regno = EH_RETURN_DATA_REGNO (i);
21098 if (regno == INVALID_REGNUM)
21099 break;
21101 /* Note: possible use of r0 here to address SPE regs. */
21102 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
21103 info->ehrd_offset + frame_off
21104 + reg_size * (int) i);
21106 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
21110 /* Restore GPRs. This is done as a PARALLEL if we are using
21111 the load-multiple instructions. */
21112 if (TARGET_SPE_ABI
21113 && info->spe_64bit_regs_used
21114 && info->first_gp_reg_save != 32)
21116 /* Determine whether we can address all of the registers that need
21117 to be saved with an offset from frame_reg_rtx that fits in
21118 the small const field for SPE memory instructions. */
21119 int spe_regs_addressable
21120 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
21121 + reg_size * (32 - info->first_gp_reg_save - 1))
21122 && restoring_GPRs_inline);
21124 if (!spe_regs_addressable)
21126 int ool_adjust = 0;
21127 rtx old_frame_reg_rtx = frame_reg_rtx;
21128 /* Make r11 point to the start of the SPE save area. We worried about
21129 not clobbering it when we were saving registers in the prologue.
21130 There's no need to worry here because the static chain is passed
21131 anew to every function. */
21133 if (!restoring_GPRs_inline)
21134 ool_adjust = 8 * (info->first_gp_reg_save
21135 - (FIRST_SAVRES_REGISTER + 1));
21136 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
21137 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
21138 GEN_INT (info->spe_gp_save_offset
21139 + frame_off
21140 - ool_adjust)));
21141 /* Keep the invariant that frame_reg_rtx + frame_off points
21142 at the top of the stack frame. */
21143 frame_off = -info->spe_gp_save_offset + ool_adjust;
21146 if (restoring_GPRs_inline)
21148 HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off;
21150 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21151 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
21153 rtx offset, addr, mem, reg;
21155 /* We're doing all this to ensure that the immediate offset
21156 fits into the immediate field of 'evldd'. */
21157 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
21159 offset = GEN_INT (spe_offset + reg_size * i);
21160 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
21161 mem = gen_rtx_MEM (V2SImode, addr);
21162 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
21164 emit_move_insn (reg, mem);
21167 else
21168 rs6000_emit_savres_rtx (info, frame_reg_rtx,
21169 info->spe_gp_save_offset + frame_off,
21170 info->lr_save_offset + frame_off,
21171 reg_mode,
21172 SAVRES_GPR | SAVRES_LR);
21174 else if (!restoring_GPRs_inline)
21176 /* We are jumping to an out-of-line function. */
21177 rtx ptr_reg;
21178 int end_save = info->gp_save_offset + info->gp_size;
21179 bool can_use_exit = end_save == 0;
21180 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
21181 int ptr_off;
21183 /* Emit stack reset code if we need it. */
21184 ptr_regno = ptr_regno_for_savres (sel);
21185 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
21186 if (can_use_exit)
21187 rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
21188 else if (end_save + frame_off != 0)
21189 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
21190 GEN_INT (end_save + frame_off)));
21191 else if (REGNO (frame_reg_rtx) != ptr_regno)
21192 emit_move_insn (ptr_reg, frame_reg_rtx);
21193 if (REGNO (frame_reg_rtx) == ptr_regno)
21194 frame_off = -end_save;
21196 if (can_use_exit && info->cr_save_p)
21197 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
21199 ptr_off = -end_save;
21200 rs6000_emit_savres_rtx (info, ptr_reg,
21201 info->gp_save_offset + ptr_off,
21202 info->lr_save_offset + ptr_off,
21203 reg_mode, sel);
21205 else if (using_load_multiple)
21207 rtvec p;
21208 p = rtvec_alloc (32 - info->first_gp_reg_save);
21209 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21210 RTVEC_ELT (p, i)
21211 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
21212 frame_reg_rtx,
21213 info->gp_save_offset + frame_off + reg_size * i);
21214 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
21216 else
21218 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
21219 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
21220 emit_insn (gen_frame_load
21221 (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
21222 frame_reg_rtx,
21223 info->gp_save_offset + frame_off + reg_size * i));
21226 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
21228 /* If the frame pointer was used then we can't delay emitting
21229 a REG_CFA_DEF_CFA note. This must happen on the insn that
21230 restores the frame pointer, r31. We may have already emitted
21231 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
21232 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
21233 be harmless if emitted. */
21234 if (frame_pointer_needed)
21236 insn = get_last_insn ();
21237 add_reg_note (insn, REG_CFA_DEF_CFA,
21238 plus_constant (Pmode, frame_reg_rtx, frame_off));
21239 RTX_FRAME_RELATED_P (insn) = 1;
21242 /* Set up cfa_restores. We always need these when
21243 shrink-wrapping. If not shrink-wrapping then we only need
21244 the cfa_restore when the stack location is no longer valid.
21245 The cfa_restores must be emitted on or before the insn that
21246 invalidates the stack, and of course must not be emitted
21247 before the insn that actually does the restore. The latter
21248 is why it is a bad idea to emit the cfa_restores as a group
21249 on the last instruction here that actually does a restore:
21250 That insn may be reordered with respect to others doing
21251 restores. */
21252 if (flag_shrink_wrap
21253 && !restoring_GPRs_inline
21254 && info->first_fp_reg_save == 64)
21255 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21257 for (i = info->first_gp_reg_save; i < 32; i++)
21258 if (!restoring_GPRs_inline
21259 || using_load_multiple
21260 || rs6000_reg_live_or_pic_offset_p (i))
21262 rtx reg = gen_rtx_REG (reg_mode, i);
21264 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21268 if (!restoring_GPRs_inline
21269 && info->first_fp_reg_save == 64)
21271 /* We are jumping to an out-of-line function. */
21272 if (cfa_restores)
21273 emit_cfa_restores (cfa_restores);
21274 return;
21277 if (restore_lr && !restoring_GPRs_inline)
21279 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
21280 restore_saved_lr (0, exit_func);
21283 /* Restore fpr's if we need to do it without calling a function. */
21284 if (restoring_FPRs_inline)
21285 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21286 if (save_reg_p (info->first_fp_reg_save + i))
21288 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
21289 ? DFmode : SFmode),
21290 info->first_fp_reg_save + i);
21291 emit_insn (gen_frame_load (reg, frame_reg_rtx,
21292 info->fp_save_offset + frame_off + 8 * i));
21293 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
21294 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
21297 /* If we saved cr, restore it here. Just those that were used. */
21298 if (info->cr_save_p)
21299 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
21301 /* If this is V.4, unwind the stack pointer after all of the loads
21302 have been done, or set up r11 if we are restoring fp out of line. */
21303 ptr_regno = 1;
21304 if (!restoring_FPRs_inline)
21306 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
21307 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
21308 ptr_regno = ptr_regno_for_savres (sel);
21311 insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
21312 if (REGNO (frame_reg_rtx) == ptr_regno)
21313 frame_off = 0;
21315 if (insn && restoring_FPRs_inline)
21317 if (cfa_restores)
21319 REG_NOTES (insn) = cfa_restores;
21320 cfa_restores = NULL_RTX;
21322 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
21323 RTX_FRAME_RELATED_P (insn) = 1;
21326 if (crtl->calls_eh_return)
21328 rtx sa = EH_RETURN_STACKADJ_RTX;
21329 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
21332 if (!sibcall)
21334 rtvec p;
21335 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
21336 if (! restoring_FPRs_inline)
21338 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
21339 RTVEC_ELT (p, 0) = ret_rtx;
21341 else
21343 if (cfa_restores)
21345 /* We can't hang the cfa_restores off a simple return,
21346 since the shrink-wrap code sometimes uses an existing
21347 return. This means there might be a path from
21348 pre-prologue code to this return, and dwarf2cfi code
21349 wants the eh_frame unwinder state to be the same on
21350 all paths to any point. So we need to emit the
21351 cfa_restores before the return. For -m64 we really
21352 don't need epilogue cfa_restores at all, except for
21353 this irritating dwarf2cfi with shrink-wrap
21354 requirement; The stack red-zone means eh_frame info
21355 from the prologue telling the unwinder to restore
21356 from the stack is perfectly good right to the end of
21357 the function. */
21358 emit_insn (gen_blockage ());
21359 emit_cfa_restores (cfa_restores);
21360 cfa_restores = NULL_RTX;
21362 p = rtvec_alloc (2);
21363 RTVEC_ELT (p, 0) = simple_return_rtx;
21366 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
21367 ? gen_rtx_USE (VOIDmode,
21368 gen_rtx_REG (Pmode, LR_REGNO))
21369 : gen_rtx_CLOBBER (VOIDmode,
21370 gen_rtx_REG (Pmode, LR_REGNO)));
21372 /* If we have to restore more than two FP registers, branch to the
21373 restore function. It will return to our caller. */
21374 if (! restoring_FPRs_inline)
21376 int i;
21377 rtx sym;
21379 if (flag_shrink_wrap)
21380 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
21382 sym = rs6000_savres_routine_sym (info,
21383 SAVRES_FPR | (lr ? SAVRES_LR : 0));
21384 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
21385 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
21386 gen_rtx_REG (Pmode,
21387 DEFAULT_ABI == ABI_AIX
21388 ? 1 : 11));
21389 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
21391 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
21393 RTVEC_ELT (p, i + 4)
21394 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
21395 if (flag_shrink_wrap)
21396 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
21397 cfa_restores);
21401 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
21404 if (cfa_restores)
21406 if (sibcall)
21407 /* Ensure the cfa_restores are hung off an insn that won't
21408 be reordered above other restores. */
21409 emit_insn (gen_blockage ());
21411 emit_cfa_restores (cfa_restores);
21415 /* Write function epilogue. */
21417 static void
21418 rs6000_output_function_epilogue (FILE *file,
21419 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
21421 #if TARGET_MACHO
21422 macho_branch_islands ();
21423 /* Mach-O doesn't support labels at the end of objects, so if
21424 it looks like we might want one, insert a NOP. */
21426 rtx insn = get_last_insn ();
21427 rtx deleted_debug_label = NULL_RTX;
21428 while (insn
21429 && NOTE_P (insn)
21430 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
21432 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
21433 notes only, instead set their CODE_LABEL_NUMBER to -1,
21434 otherwise there would be code generation differences
21435 in between -g and -g0. */
21436 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21437 deleted_debug_label = insn;
21438 insn = PREV_INSN (insn);
21440 if (insn
21441 && (LABEL_P (insn)
21442 || (NOTE_P (insn)
21443 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
21444 fputs ("\tnop\n", file);
21445 else if (deleted_debug_label)
21446 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
21447 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
21448 CODE_LABEL_NUMBER (insn) = -1;
21450 #endif
21452 /* Output a traceback table here. See /usr/include/sys/debug.h for info
21453 on its format.
21455 We don't output a traceback table if -finhibit-size-directive was
21456 used. The documentation for -finhibit-size-directive reads
21457 ``don't output a @code{.size} assembler directive, or anything
21458 else that would cause trouble if the function is split in the
21459 middle, and the two halves are placed at locations far apart in
21460 memory.'' The traceback table has this property, since it
21461 includes the offset from the start of the function to the
21462 traceback table itself.
21464 System V.4 Powerpc's (and the embedded ABI derived from it) use a
21465 different traceback table. */
21466 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
21467 && rs6000_traceback != traceback_none && !cfun->is_thunk)
21469 const char *fname = NULL;
21470 const char *language_string = lang_hooks.name;
21471 int fixed_parms = 0, float_parms = 0, parm_info = 0;
21472 int i;
21473 int optional_tbtab;
21474 rs6000_stack_t *info = rs6000_stack_info ();
21476 if (rs6000_traceback == traceback_full)
21477 optional_tbtab = 1;
21478 else if (rs6000_traceback == traceback_part)
21479 optional_tbtab = 0;
21480 else
21481 optional_tbtab = !optimize_size && !TARGET_ELF;
21483 if (optional_tbtab)
21485 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
21486 while (*fname == '.') /* V.4 encodes . in the name */
21487 fname++;
21489 /* Need label immediately before tbtab, so we can compute
21490 its offset from the function start. */
21491 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21492 ASM_OUTPUT_LABEL (file, fname);
21495 /* The .tbtab pseudo-op can only be used for the first eight
21496 expressions, since it can't handle the possibly variable
21497 length fields that follow. However, if you omit the optional
21498 fields, the assembler outputs zeros for all optional fields
21499 anyways, giving each variable length field is minimum length
21500 (as defined in sys/debug.h). Thus we can not use the .tbtab
21501 pseudo-op at all. */
21503 /* An all-zero word flags the start of the tbtab, for debuggers
21504 that have to find it by searching forward from the entry
21505 point or from the current pc. */
21506 fputs ("\t.long 0\n", file);
21508 /* Tbtab format type. Use format type 0. */
21509 fputs ("\t.byte 0,", file);
21511 /* Language type. Unfortunately, there does not seem to be any
21512 official way to discover the language being compiled, so we
21513 use language_string.
21514 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21515 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21516 a number, so for now use 9. LTO, Go, and UPC aren't assigned numbers
21517 either, so for now use 0. */
21518 if (! strcmp (language_string, "GNU C")
21519 || ! strcmp (language_string, "GNU GIMPLE")
21520 || ! strcmp (language_string, "GNU Go")
21521 || ! strcmp (language_string, "GNU UPC"))
21522 i = 0;
21523 else if (! strcmp (language_string, "GNU F77")
21524 || ! strcmp (language_string, "GNU Fortran"))
21525 i = 1;
21526 else if (! strcmp (language_string, "GNU Pascal"))
21527 i = 2;
21528 else if (! strcmp (language_string, "GNU Ada"))
21529 i = 3;
21530 else if (! strcmp (language_string, "GNU C++")
21531 || ! strcmp (language_string, "GNU Objective-C++"))
21532 i = 9;
21533 else if (! strcmp (language_string, "GNU Java"))
21534 i = 13;
21535 else if (! strcmp (language_string, "GNU Objective-C"))
21536 i = 14;
21537 else
21538 gcc_unreachable ();
21539 fprintf (file, "%d,", i);
21541 /* 8 single bit fields: global linkage (not set for C extern linkage,
21542 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21543 from start of procedure stored in tbtab, internal function, function
21544 has controlled storage, function has no toc, function uses fp,
21545 function logs/aborts fp operations. */
21546 /* Assume that fp operations are used if any fp reg must be saved. */
21547 fprintf (file, "%d,",
21548 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21550 /* 6 bitfields: function is interrupt handler, name present in
21551 proc table, function calls alloca, on condition directives
21552 (controls stack walks, 3 bits), saves condition reg, saves
21553 link reg. */
21554 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21555 set up as a frame pointer, even when there is no alloca call. */
21556 fprintf (file, "%d,",
21557 ((optional_tbtab << 6)
21558 | ((optional_tbtab & frame_pointer_needed) << 5)
21559 | (info->cr_save_p << 1)
21560 | (info->lr_save_p)));
21562 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21563 (6 bits). */
21564 fprintf (file, "%d,",
21565 (info->push_p << 7) | (64 - info->first_fp_reg_save));
21567 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21568 fprintf (file, "%d,", (32 - first_reg_to_save ()));
21570 if (optional_tbtab)
21572 /* Compute the parameter info from the function decl argument
21573 list. */
21574 tree decl;
21575 int next_parm_info_bit = 31;
21577 for (decl = DECL_ARGUMENTS (current_function_decl);
21578 decl; decl = DECL_CHAIN (decl))
21580 rtx parameter = DECL_INCOMING_RTL (decl);
21581 enum machine_mode mode = GET_MODE (parameter);
21583 if (GET_CODE (parameter) == REG)
21585 if (SCALAR_FLOAT_MODE_P (mode))
21587 int bits;
21589 float_parms++;
21591 switch (mode)
21593 case SFmode:
21594 case SDmode:
21595 bits = 0x2;
21596 break;
21598 case DFmode:
21599 case DDmode:
21600 case TFmode:
21601 case TDmode:
21602 bits = 0x3;
21603 break;
21605 default:
21606 gcc_unreachable ();
21609 /* If only one bit will fit, don't or in this entry. */
21610 if (next_parm_info_bit > 0)
21611 parm_info |= (bits << (next_parm_info_bit - 1));
21612 next_parm_info_bit -= 2;
21614 else
21616 fixed_parms += ((GET_MODE_SIZE (mode)
21617 + (UNITS_PER_WORD - 1))
21618 / UNITS_PER_WORD);
21619 next_parm_info_bit -= 1;
21625 /* Number of fixed point parameters. */
21626 /* This is actually the number of words of fixed point parameters; thus
21627 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21628 fprintf (file, "%d,", fixed_parms);
21630 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21631 all on stack. */
21632 /* This is actually the number of fp registers that hold parameters;
21633 and thus the maximum value is 13. */
21634 /* Set parameters on stack bit if parameters are not in their original
21635 registers, regardless of whether they are on the stack? Xlc
21636 seems to set the bit when not optimizing. */
21637 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21639 if (! optional_tbtab)
21640 return;
21642 /* Optional fields follow. Some are variable length. */
21644 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21645 11 double float. */
21646 /* There is an entry for each parameter in a register, in the order that
21647 they occur in the parameter list. Any intervening arguments on the
21648 stack are ignored. If the list overflows a long (max possible length
21649 34 bits) then completely leave off all elements that don't fit. */
21650 /* Only emit this long if there was at least one parameter. */
21651 if (fixed_parms || float_parms)
21652 fprintf (file, "\t.long %d\n", parm_info);
21654 /* Offset from start of code to tb table. */
21655 fputs ("\t.long ", file);
21656 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21657 RS6000_OUTPUT_BASENAME (file, fname);
21658 putc ('-', file);
21659 rs6000_output_function_entry (file, fname);
21660 putc ('\n', file);
21662 /* Interrupt handler mask. */
21663 /* Omit this long, since we never set the interrupt handler bit
21664 above. */
21666 /* Number of CTL (controlled storage) anchors. */
21667 /* Omit this long, since the has_ctl bit is never set above. */
21669 /* Displacement into stack of each CTL anchor. */
21670 /* Omit this list of longs, because there are no CTL anchors. */
21672 /* Length of function name. */
21673 if (*fname == '*')
21674 ++fname;
21675 fprintf (file, "\t.short %d\n", (int) strlen (fname));
21677 /* Function name. */
21678 assemble_string (fname, strlen (fname));
21680 /* Register for alloca automatic storage; this is always reg 31.
21681 Only emit this if the alloca bit was set above. */
21682 if (frame_pointer_needed)
21683 fputs ("\t.byte 31\n", file);
21685 fputs ("\t.align 2\n", file);
21689 /* A C compound statement that outputs the assembler code for a thunk
21690 function, used to implement C++ virtual function calls with
21691 multiple inheritance. The thunk acts as a wrapper around a virtual
21692 function, adjusting the implicit object parameter before handing
21693 control off to the real function.
21695 First, emit code to add the integer DELTA to the location that
21696 contains the incoming first argument. Assume that this argument
21697 contains a pointer, and is the one used to pass the `this' pointer
21698 in C++. This is the incoming argument *before* the function
21699 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21700 values of all other incoming arguments.
21702 After the addition, emit code to jump to FUNCTION, which is a
21703 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21704 not touch the return address. Hence returning from FUNCTION will
21705 return to whoever called the current `thunk'.
21707 The effect must be as if FUNCTION had been called directly with the
21708 adjusted first argument. This macro is responsible for emitting
21709 all of the code for a thunk function; output_function_prologue()
21710 and output_function_epilogue() are not invoked.
21712 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21713 been extracted from it.) It might possibly be useful on some
21714 targets, but probably not.
21716 If you do not define this macro, the target-independent code in the
21717 C++ frontend will generate a less efficient heavyweight thunk that
21718 calls FUNCTION instead of jumping to it. The generic approach does
21719 not support varargs. */
21721 static void
21722 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21723 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21724 tree function)
21726 rtx this_rtx, insn, funexp;
21728 reload_completed = 1;
21729 epilogue_completed = 1;
21731 /* Mark the end of the (empty) prologue. */
21732 emit_note (NOTE_INSN_PROLOGUE_END);
21734 /* Find the "this" pointer. If the function returns a structure,
21735 the structure return pointer is in r3. */
21736 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21737 this_rtx = gen_rtx_REG (Pmode, 4);
21738 else
21739 this_rtx = gen_rtx_REG (Pmode, 3);
21741 /* Apply the constant offset, if required. */
21742 if (delta)
21743 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21745 /* Apply the offset from the vtable, if required. */
21746 if (vcall_offset)
21748 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21749 rtx tmp = gen_rtx_REG (Pmode, 12);
21751 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21752 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21754 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21755 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21757 else
21759 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21761 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21763 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21766 /* Generate a tail call to the target function. */
21767 if (!TREE_USED (function))
21769 assemble_external (function);
21770 TREE_USED (function) = 1;
21772 funexp = XEXP (DECL_RTL (function), 0);
21773 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21775 #if TARGET_MACHO
21776 if (MACHOPIC_INDIRECT)
21777 funexp = machopic_indirect_call_target (funexp);
21778 #endif
21780 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21781 generate sibcall RTL explicitly. */
21782 insn = emit_call_insn (
21783 gen_rtx_PARALLEL (VOIDmode,
21784 gen_rtvec (4,
21785 gen_rtx_CALL (VOIDmode,
21786 funexp, const0_rtx),
21787 gen_rtx_USE (VOIDmode, const0_rtx),
21788 gen_rtx_USE (VOIDmode,
21789 gen_rtx_REG (SImode,
21790 LR_REGNO)),
21791 simple_return_rtx)));
21792 SIBLING_CALL_P (insn) = 1;
21793 emit_barrier ();
21795 /* Run just enough of rest_of_compilation to get the insns emitted.
21796 There's not really enough bulk here to make other passes such as
21797 instruction scheduling worth while. Note that use_thunk calls
21798 assemble_start_function and assemble_end_function. */
21799 insn = get_insns ();
21800 shorten_branches (insn);
21801 final_start_function (insn, file, 1);
21802 final (insn, file, 1);
21803 final_end_function ();
21805 reload_completed = 0;
21806 epilogue_completed = 0;
21809 /* A quick summary of the various types of 'constant-pool tables'
21810 under PowerPC:
21812 Target Flags Name One table per
21813 AIX (none) AIX TOC object file
21814 AIX -mfull-toc AIX TOC object file
21815 AIX -mminimal-toc AIX minimal TOC translation unit
21816 SVR4/EABI (none) SVR4 SDATA object file
21817 SVR4/EABI -fpic SVR4 pic object file
21818 SVR4/EABI -fPIC SVR4 PIC translation unit
21819 SVR4/EABI -mrelocatable EABI TOC function
21820 SVR4/EABI -maix AIX TOC object file
21821 SVR4/EABI -maix -mminimal-toc
21822 AIX minimal TOC translation unit
21824 Name Reg. Set by entries contains:
21825 made by addrs? fp? sum?
21827 AIX TOC 2 crt0 as Y option option
21828 AIX minimal TOC 30 prolog gcc Y Y option
21829 SVR4 SDATA 13 crt0 gcc N Y N
21830 SVR4 pic 30 prolog ld Y not yet N
21831 SVR4 PIC 30 prolog gcc Y option option
21832 EABI TOC 30 prolog gcc Y option option
21836 /* Hash functions for the hash table. */
21838 static unsigned
21839 rs6000_hash_constant (rtx k)
21841 enum rtx_code code = GET_CODE (k);
21842 enum machine_mode mode = GET_MODE (k);
21843 unsigned result = (code << 3) ^ mode;
21844 const char *format;
21845 int flen, fidx;
21847 format = GET_RTX_FORMAT (code);
21848 flen = strlen (format);
21849 fidx = 0;
21851 switch (code)
21853 case LABEL_REF:
21854 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21856 case CONST_DOUBLE:
21857 if (mode != VOIDmode)
21858 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21859 flen = 2;
21860 break;
21862 case CODE_LABEL:
21863 fidx = 3;
21864 break;
21866 default:
21867 break;
21870 for (; fidx < flen; fidx++)
21871 switch (format[fidx])
21873 case 's':
21875 unsigned i, len;
21876 const char *str = XSTR (k, fidx);
21877 len = strlen (str);
21878 result = result * 613 + len;
21879 for (i = 0; i < len; i++)
21880 result = result * 613 + (unsigned) str[i];
21881 break;
21883 case 'u':
21884 case 'e':
21885 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21886 break;
21887 case 'i':
21888 case 'n':
21889 result = result * 613 + (unsigned) XINT (k, fidx);
21890 break;
21891 case 'w':
21892 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21893 result = result * 613 + (unsigned) XWINT (k, fidx);
21894 else
21896 size_t i;
21897 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21898 result = result * 613 + (unsigned) (XWINT (k, fidx)
21899 >> CHAR_BIT * i);
21901 break;
21902 case '0':
21903 break;
21904 default:
21905 gcc_unreachable ();
21908 return result;
21911 static unsigned
21912 toc_hash_function (const void *hash_entry)
21914 const struct toc_hash_struct *thc =
21915 (const struct toc_hash_struct *) hash_entry;
21916 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21919 /* Compare H1 and H2 for equivalence. */
21921 static int
21922 toc_hash_eq (const void *h1, const void *h2)
21924 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21925 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21927 if (((const struct toc_hash_struct *) h1)->key_mode
21928 != ((const struct toc_hash_struct *) h2)->key_mode)
21929 return 0;
21931 return rtx_equal_p (r1, r2);
21934 /* These are the names given by the C++ front-end to vtables, and
21935 vtable-like objects. Ideally, this logic should not be here;
21936 instead, there should be some programmatic way of inquiring as
21937 to whether or not an object is a vtable. */
21939 #define VTABLE_NAME_P(NAME) \
21940 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21941 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21942 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21943 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21944 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21946 #ifdef NO_DOLLAR_IN_LABEL
21947 /* Return a GGC-allocated character string translating dollar signs in
21948 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21950 const char *
21951 rs6000_xcoff_strip_dollar (const char *name)
21953 char *strip, *p;
21954 const char *q;
21955 size_t len;
21957 q = (const char *) strchr (name, '$');
21959 if (q == 0 || q == name)
21960 return name;
21962 len = strlen (name);
21963 strip = XALLOCAVEC (char, len + 1);
21964 strcpy (strip, name);
21965 p = strip + (q - name);
21966 while (p)
21968 *p = '_';
21969 p = strchr (p + 1, '$');
21972 return ggc_alloc_string (strip, len);
21974 #endif
21976 void
21977 rs6000_output_symbol_ref (FILE *file, rtx x)
21979 /* Currently C++ toc references to vtables can be emitted before it
21980 is decided whether the vtable is public or private. If this is
21981 the case, then the linker will eventually complain that there is
21982 a reference to an unknown section. Thus, for vtables only,
21983 we emit the TOC reference to reference the symbol and not the
21984 section. */
21985 const char *name = XSTR (x, 0);
21987 if (VTABLE_NAME_P (name))
21989 RS6000_OUTPUT_BASENAME (file, name);
21991 else
21992 assemble_name (file, name);
21995 /* Output a TOC entry. We derive the entry name from what is being
21996 written. */
21998 void
21999 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
22001 char buf[256];
22002 const char *name = buf;
22003 rtx base = x;
22004 HOST_WIDE_INT offset = 0;
22006 gcc_assert (!TARGET_NO_TOC);
22008 /* When the linker won't eliminate them, don't output duplicate
22009 TOC entries (this happens on AIX if there is any kind of TOC,
22010 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
22011 CODE_LABELs. */
22012 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
22014 struct toc_hash_struct *h;
22015 void * * found;
22017 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
22018 time because GGC is not initialized at that point. */
22019 if (toc_hash_table == NULL)
22020 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
22021 toc_hash_eq, NULL);
22023 h = ggc_alloc_toc_hash_struct ();
22024 h->key = x;
22025 h->key_mode = mode;
22026 h->labelno = labelno;
22028 found = htab_find_slot (toc_hash_table, h, INSERT);
22029 if (*found == NULL)
22030 *found = h;
22031 else /* This is indeed a duplicate.
22032 Set this label equal to that label. */
22034 fputs ("\t.set ", file);
22035 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
22036 fprintf (file, "%d,", labelno);
22037 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
22038 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
22039 found)->labelno));
22041 #ifdef HAVE_AS_TLS
22042 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
22043 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
22044 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
22046 fputs ("\t.set ", file);
22047 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
22048 fprintf (file, "%d,", labelno);
22049 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
22050 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
22051 found)->labelno));
22053 #endif
22054 return;
22058 /* If we're going to put a double constant in the TOC, make sure it's
22059 aligned properly when strict alignment is on. */
22060 if (GET_CODE (x) == CONST_DOUBLE
22061 && STRICT_ALIGNMENT
22062 && GET_MODE_BITSIZE (mode) >= 64
22063 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
22064 ASM_OUTPUT_ALIGN (file, 3);
22067 (*targetm.asm_out.internal_label) (file, "LC", labelno);
22069 /* Handle FP constants specially. Note that if we have a minimal
22070 TOC, things we put here aren't actually in the TOC, so we can allow
22071 FP constants. */
22072 if (GET_CODE (x) == CONST_DOUBLE &&
22073 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
22075 REAL_VALUE_TYPE rv;
22076 long k[4];
22078 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
22079 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
22080 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
22081 else
22082 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
22084 if (TARGET_64BIT)
22086 if (TARGET_MINIMAL_TOC)
22087 fputs (DOUBLE_INT_ASM_OP, file);
22088 else
22089 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22090 k[0] & 0xffffffff, k[1] & 0xffffffff,
22091 k[2] & 0xffffffff, k[3] & 0xffffffff);
22092 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
22093 k[0] & 0xffffffff, k[1] & 0xffffffff,
22094 k[2] & 0xffffffff, k[3] & 0xffffffff);
22095 return;
22097 else
22099 if (TARGET_MINIMAL_TOC)
22100 fputs ("\t.long ", file);
22101 else
22102 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
22103 k[0] & 0xffffffff, k[1] & 0xffffffff,
22104 k[2] & 0xffffffff, k[3] & 0xffffffff);
22105 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
22106 k[0] & 0xffffffff, k[1] & 0xffffffff,
22107 k[2] & 0xffffffff, k[3] & 0xffffffff);
22108 return;
22111 else if (GET_CODE (x) == CONST_DOUBLE &&
22112 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
22114 REAL_VALUE_TYPE rv;
22115 long k[2];
22117 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
22119 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
22120 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
22121 else
22122 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
22124 if (TARGET_64BIT)
22126 if (TARGET_MINIMAL_TOC)
22127 fputs (DOUBLE_INT_ASM_OP, file);
22128 else
22129 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
22130 k[0] & 0xffffffff, k[1] & 0xffffffff);
22131 fprintf (file, "0x%lx%08lx\n",
22132 k[0] & 0xffffffff, k[1] & 0xffffffff);
22133 return;
22135 else
22137 if (TARGET_MINIMAL_TOC)
22138 fputs ("\t.long ", file);
22139 else
22140 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
22141 k[0] & 0xffffffff, k[1] & 0xffffffff);
22142 fprintf (file, "0x%lx,0x%lx\n",
22143 k[0] & 0xffffffff, k[1] & 0xffffffff);
22144 return;
22147 else if (GET_CODE (x) == CONST_DOUBLE &&
22148 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
22150 REAL_VALUE_TYPE rv;
22151 long l;
22153 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
22154 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
22155 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
22156 else
22157 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
22159 if (TARGET_64BIT)
22161 if (TARGET_MINIMAL_TOC)
22162 fputs (DOUBLE_INT_ASM_OP, file);
22163 else
22164 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
22165 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
22166 return;
22168 else
22170 if (TARGET_MINIMAL_TOC)
22171 fputs ("\t.long ", file);
22172 else
22173 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
22174 fprintf (file, "0x%lx\n", l & 0xffffffff);
22175 return;
22178 else if (GET_MODE (x) == VOIDmode
22179 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
22181 unsigned HOST_WIDE_INT low;
22182 HOST_WIDE_INT high;
22184 if (GET_CODE (x) == CONST_DOUBLE)
22186 low = CONST_DOUBLE_LOW (x);
22187 high = CONST_DOUBLE_HIGH (x);
22189 else
22190 #if HOST_BITS_PER_WIDE_INT == 32
22192 low = INTVAL (x);
22193 high = (low & 0x80000000) ? ~0 : 0;
22195 #else
22197 low = INTVAL (x) & 0xffffffff;
22198 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
22200 #endif
22202 /* TOC entries are always Pmode-sized, but since this
22203 is a bigendian machine then if we're putting smaller
22204 integer constants in the TOC we have to pad them.
22205 (This is still a win over putting the constants in
22206 a separate constant pool, because then we'd have
22207 to have both a TOC entry _and_ the actual constant.)
22209 For a 32-bit target, CONST_INT values are loaded and shifted
22210 entirely within `low' and can be stored in one TOC entry. */
22212 /* It would be easy to make this work, but it doesn't now. */
22213 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
22215 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
22217 #if HOST_BITS_PER_WIDE_INT == 32
22218 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
22219 POINTER_SIZE, &low, &high, 0);
22220 #else
22221 low |= high << 32;
22222 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
22223 high = (HOST_WIDE_INT) low >> 32;
22224 low &= 0xffffffff;
22225 #endif
22228 if (TARGET_64BIT)
22230 if (TARGET_MINIMAL_TOC)
22231 fputs (DOUBLE_INT_ASM_OP, file);
22232 else
22233 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
22234 (long) high & 0xffffffff, (long) low & 0xffffffff);
22235 fprintf (file, "0x%lx%08lx\n",
22236 (long) high & 0xffffffff, (long) low & 0xffffffff);
22237 return;
22239 else
22241 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
22243 if (TARGET_MINIMAL_TOC)
22244 fputs ("\t.long ", file);
22245 else
22246 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
22247 (long) high & 0xffffffff, (long) low & 0xffffffff);
22248 fprintf (file, "0x%lx,0x%lx\n",
22249 (long) high & 0xffffffff, (long) low & 0xffffffff);
22251 else
22253 if (TARGET_MINIMAL_TOC)
22254 fputs ("\t.long ", file);
22255 else
22256 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
22257 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
22259 return;
22263 if (GET_CODE (x) == CONST)
22265 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
22266 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
22268 base = XEXP (XEXP (x, 0), 0);
22269 offset = INTVAL (XEXP (XEXP (x, 0), 1));
22272 switch (GET_CODE (base))
22274 case SYMBOL_REF:
22275 name = XSTR (base, 0);
22276 break;
22278 case LABEL_REF:
22279 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
22280 CODE_LABEL_NUMBER (XEXP (base, 0)));
22281 break;
22283 case CODE_LABEL:
22284 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
22285 break;
22287 default:
22288 gcc_unreachable ();
22291 if (TARGET_MINIMAL_TOC)
22292 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
22293 else
22295 fputs ("\t.tc ", file);
22296 RS6000_OUTPUT_BASENAME (file, name);
22298 if (offset < 0)
22299 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
22300 else if (offset)
22301 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
22303 /* Mark large TOC symbols on AIX with [TE] so they are mapped
22304 after other TOC symbols, reducing overflow of small TOC access
22305 to [TC] symbols. */
22306 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
22307 ? "[TE]," : "[TC],", file);
22310 /* Currently C++ toc references to vtables can be emitted before it
22311 is decided whether the vtable is public or private. If this is
22312 the case, then the linker will eventually complain that there is
22313 a TOC reference to an unknown section. Thus, for vtables only,
22314 we emit the TOC reference to reference the symbol and not the
22315 section. */
22316 if (VTABLE_NAME_P (name))
22318 RS6000_OUTPUT_BASENAME (file, name);
22319 if (offset < 0)
22320 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
22321 else if (offset > 0)
22322 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
22324 else
22325 output_addr_const (file, x);
22327 #if HAVE_AS_TLS
22328 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
22330 if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC)
22331 fputs ("[TL]@le", file);
22332 else if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_INITIAL_EXEC)
22333 fputs ("[TL]@ie", file);
22334 /* Use global-dynamic for local-dynamic. */
22335 else if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_GLOBAL_DYNAMIC
22336 || SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_DYNAMIC)
22338 fputs ("[TL]\n", file);
22339 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
22340 fputs ("\t.tc .", file);
22341 RS6000_OUTPUT_BASENAME (file, name);
22342 fputs ("[TC],", file);
22343 output_addr_const (file, x);
22344 fputs ("[TL]@m", file);
22347 #endif
22349 putc ('\n', file);
22352 /* Output an assembler pseudo-op to write an ASCII string of N characters
22353 starting at P to FILE.
22355 On the RS/6000, we have to do this using the .byte operation and
22356 write out special characters outside the quoted string.
22357 Also, the assembler is broken; very long strings are truncated,
22358 so we must artificially break them up early. */
22360 void
22361 output_ascii (FILE *file, const char *p, int n)
22363 char c;
22364 int i, count_string;
22365 const char *for_string = "\t.byte \"";
22366 const char *for_decimal = "\t.byte ";
22367 const char *to_close = NULL;
22369 count_string = 0;
22370 for (i = 0; i < n; i++)
22372 c = *p++;
22373 if (c >= ' ' && c < 0177)
22375 if (for_string)
22376 fputs (for_string, file);
22377 putc (c, file);
22379 /* Write two quotes to get one. */
22380 if (c == '"')
22382 putc (c, file);
22383 ++count_string;
22386 for_string = NULL;
22387 for_decimal = "\"\n\t.byte ";
22388 to_close = "\"\n";
22389 ++count_string;
22391 if (count_string >= 512)
22393 fputs (to_close, file);
22395 for_string = "\t.byte \"";
22396 for_decimal = "\t.byte ";
22397 to_close = NULL;
22398 count_string = 0;
22401 else
22403 if (for_decimal)
22404 fputs (for_decimal, file);
22405 fprintf (file, "%d", c);
22407 for_string = "\n\t.byte \"";
22408 for_decimal = ", ";
22409 to_close = "\n";
22410 count_string = 0;
22414 /* Now close the string if we have written one. Then end the line. */
22415 if (to_close)
22416 fputs (to_close, file);
22419 /* Generate a unique section name for FILENAME for a section type
22420 represented by SECTION_DESC. Output goes into BUF.
22422 SECTION_DESC can be any string, as long as it is different for each
22423 possible section type.
22425 We name the section in the same manner as xlc. The name begins with an
22426 underscore followed by the filename (after stripping any leading directory
22427 names) with the last period replaced by the string SECTION_DESC. If
22428 FILENAME does not contain a period, SECTION_DESC is appended to the end of
22429 the name. */
22431 void
22432 rs6000_gen_section_name (char **buf, const char *filename,
22433 const char *section_desc)
22435 const char *q, *after_last_slash, *last_period = 0;
22436 char *p;
22437 int len;
22439 after_last_slash = filename;
22440 for (q = filename; *q; q++)
22442 if (*q == '/')
22443 after_last_slash = q + 1;
22444 else if (*q == '.')
22445 last_period = q;
22448 len = strlen (after_last_slash) + strlen (section_desc) + 2;
22449 *buf = (char *) xmalloc (len);
22451 p = *buf;
22452 *p++ = '_';
22454 for (q = after_last_slash; *q; q++)
22456 if (q == last_period)
22458 strcpy (p, section_desc);
22459 p += strlen (section_desc);
22460 break;
22463 else if (ISALNUM (*q))
22464 *p++ = *q;
22467 if (last_period == 0)
22468 strcpy (p, section_desc);
22469 else
22470 *p = '\0';
22473 /* Emit profile function. */
22475 void
22476 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
22478 /* Non-standard profiling for kernels, which just saves LR then calls
22479 _mcount without worrying about arg saves. The idea is to change
22480 the function prologue as little as possible as it isn't easy to
22481 account for arg save/restore code added just for _mcount. */
22482 if (TARGET_PROFILE_KERNEL)
22483 return;
22485 if (DEFAULT_ABI == ABI_AIX)
22487 #ifndef NO_PROFILE_COUNTERS
22488 # define NO_PROFILE_COUNTERS 0
22489 #endif
22490 if (NO_PROFILE_COUNTERS)
22491 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22492 LCT_NORMAL, VOIDmode, 0);
22493 else
22495 char buf[30];
22496 const char *label_name;
22497 rtx fun;
22499 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22500 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
22501 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
22503 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22504 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
22507 else if (DEFAULT_ABI == ABI_DARWIN)
22509 const char *mcount_name = RS6000_MCOUNT;
22510 int caller_addr_regno = LR_REGNO;
22512 /* Be conservative and always set this, at least for now. */
22513 crtl->uses_pic_offset_table = 1;
22515 #if TARGET_MACHO
22516 /* For PIC code, set up a stub and collect the caller's address
22517 from r0, which is where the prologue puts it. */
22518 if (MACHOPIC_INDIRECT
22519 && crtl->uses_pic_offset_table)
22520 caller_addr_regno = 0;
22521 #endif
22522 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
22523 LCT_NORMAL, VOIDmode, 1,
22524 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
22528 /* Write function profiler code. */
22530 void
22531 output_function_profiler (FILE *file, int labelno)
22533 char buf[100];
22535 switch (DEFAULT_ABI)
22537 default:
22538 gcc_unreachable ();
22540 case ABI_V4:
22541 if (!TARGET_32BIT)
22543 warning (0, "no profiling of 64-bit code for this ABI");
22544 return;
22546 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22547 fprintf (file, "\tmflr %s\n", reg_names[0]);
22548 if (NO_PROFILE_COUNTERS)
22550 asm_fprintf (file, "\tstw %s,4(%s)\n",
22551 reg_names[0], reg_names[1]);
22553 else if (TARGET_SECURE_PLT && flag_pic)
22555 if (TARGET_LINK_STACK)
22557 char name[32];
22558 get_ppc476_thunk_name (name);
22559 asm_fprintf (file, "\tbl %s\n", name);
22561 else
22562 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22563 asm_fprintf (file, "\tstw %s,4(%s)\n",
22564 reg_names[0], reg_names[1]);
22565 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22566 asm_fprintf (file, "\taddis %s,%s,",
22567 reg_names[12], reg_names[12]);
22568 assemble_name (file, buf);
22569 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
22570 assemble_name (file, buf);
22571 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22573 else if (flag_pic == 1)
22575 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22576 asm_fprintf (file, "\tstw %s,4(%s)\n",
22577 reg_names[0], reg_names[1]);
22578 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22579 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
22580 assemble_name (file, buf);
22581 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22583 else if (flag_pic > 1)
22585 asm_fprintf (file, "\tstw %s,4(%s)\n",
22586 reg_names[0], reg_names[1]);
22587 /* Now, we need to get the address of the label. */
22588 if (TARGET_LINK_STACK)
22590 char name[32];
22591 get_ppc476_thunk_name (name);
22592 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22593 assemble_name (file, buf);
22594 fputs ("-.\n1:", file);
22595 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22596 asm_fprintf (file, "\taddi %s,%s,4\n",
22597 reg_names[11], reg_names[11]);
22599 else
22601 fputs ("\tbcl 20,31,1f\n\t.long ", file);
22602 assemble_name (file, buf);
22603 fputs ("-.\n1:", file);
22604 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22606 asm_fprintf (file, "\tlwz %s,0(%s)\n",
22607 reg_names[0], reg_names[11]);
22608 asm_fprintf (file, "\tadd %s,%s,%s\n",
22609 reg_names[0], reg_names[0], reg_names[11]);
22611 else
22613 asm_fprintf (file, "\tlis %s,", reg_names[12]);
22614 assemble_name (file, buf);
22615 fputs ("@ha\n", file);
22616 asm_fprintf (file, "\tstw %s,4(%s)\n",
22617 reg_names[0], reg_names[1]);
22618 asm_fprintf (file, "\tla %s,", reg_names[0]);
22619 assemble_name (file, buf);
22620 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22623 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22624 fprintf (file, "\tbl %s%s\n",
22625 RS6000_MCOUNT, flag_pic ? "@plt" : "");
22626 break;
22628 case ABI_AIX:
22629 case ABI_DARWIN:
22630 if (!TARGET_PROFILE_KERNEL)
22632 /* Don't do anything, done in output_profile_hook (). */
22634 else
22636 gcc_assert (!TARGET_32BIT);
22638 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22639 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22641 if (cfun->static_chain_decl != NULL)
22643 asm_fprintf (file, "\tstd %s,24(%s)\n",
22644 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22645 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22646 asm_fprintf (file, "\tld %s,24(%s)\n",
22647 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22649 else
22650 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22652 break;
22658 /* The following variable value is the last issued insn. */
22660 static rtx last_scheduled_insn;
22662 /* The following variable helps to balance issuing of load and
22663 store instructions */
22665 static int load_store_pendulum;
22667 /* Power4 load update and store update instructions are cracked into a
22668 load or store and an integer insn which are executed in the same cycle.
22669 Branches have their own dispatch slot which does not count against the
22670 GCC issue rate, but it changes the program flow so there are no other
22671 instructions to issue in this cycle. */
22673 static int
22674 rs6000_variable_issue_1 (rtx insn, int more)
22676 last_scheduled_insn = insn;
22677 if (GET_CODE (PATTERN (insn)) == USE
22678 || GET_CODE (PATTERN (insn)) == CLOBBER)
22680 cached_can_issue_more = more;
22681 return cached_can_issue_more;
22684 if (insn_terminates_group_p (insn, current_group))
22686 cached_can_issue_more = 0;
22687 return cached_can_issue_more;
22690 /* If no reservation, but reach here */
22691 if (recog_memoized (insn) < 0)
22692 return more;
22694 if (rs6000_sched_groups)
22696 if (is_microcoded_insn (insn))
22697 cached_can_issue_more = 0;
22698 else if (is_cracked_insn (insn))
22699 cached_can_issue_more = more > 2 ? more - 2 : 0;
22700 else
22701 cached_can_issue_more = more - 1;
22703 return cached_can_issue_more;
22706 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22707 return 0;
22709 cached_can_issue_more = more - 1;
22710 return cached_can_issue_more;
22713 static int
22714 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22716 int r = rs6000_variable_issue_1 (insn, more);
22717 if (verbose)
22718 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22719 return r;
22722 /* Adjust the cost of a scheduling dependency. Return the new cost of
22723 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22725 static int
22726 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22728 enum attr_type attr_type;
22730 if (! recog_memoized (insn))
22731 return 0;
22733 switch (REG_NOTE_KIND (link))
22735 case REG_DEP_TRUE:
22737 /* Data dependency; DEP_INSN writes a register that INSN reads
22738 some cycles later. */
22740 /* Separate a load from a narrower, dependent store. */
22741 if (rs6000_sched_groups
22742 && GET_CODE (PATTERN (insn)) == SET
22743 && GET_CODE (PATTERN (dep_insn)) == SET
22744 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22745 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22746 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22747 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22748 return cost + 14;
22750 attr_type = get_attr_type (insn);
22752 switch (attr_type)
22754 case TYPE_JMPREG:
22755 /* Tell the first scheduling pass about the latency between
22756 a mtctr and bctr (and mtlr and br/blr). The first
22757 scheduling pass will not know about this latency since
22758 the mtctr instruction, which has the latency associated
22759 to it, will be generated by reload. */
22760 return 4;
22761 case TYPE_BRANCH:
22762 /* Leave some extra cycles between a compare and its
22763 dependent branch, to inhibit expensive mispredicts. */
22764 if ((rs6000_cpu_attr == CPU_PPC603
22765 || rs6000_cpu_attr == CPU_PPC604
22766 || rs6000_cpu_attr == CPU_PPC604E
22767 || rs6000_cpu_attr == CPU_PPC620
22768 || rs6000_cpu_attr == CPU_PPC630
22769 || rs6000_cpu_attr == CPU_PPC750
22770 || rs6000_cpu_attr == CPU_PPC7400
22771 || rs6000_cpu_attr == CPU_PPC7450
22772 || rs6000_cpu_attr == CPU_PPCE5500
22773 || rs6000_cpu_attr == CPU_PPCE6500
22774 || rs6000_cpu_attr == CPU_POWER4
22775 || rs6000_cpu_attr == CPU_POWER5
22776 || rs6000_cpu_attr == CPU_POWER7
22777 || rs6000_cpu_attr == CPU_CELL)
22778 && recog_memoized (dep_insn)
22779 && (INSN_CODE (dep_insn) >= 0))
22781 switch (get_attr_type (dep_insn))
22783 case TYPE_CMP:
22784 case TYPE_COMPARE:
22785 case TYPE_DELAYED_COMPARE:
22786 case TYPE_IMUL_COMPARE:
22787 case TYPE_LMUL_COMPARE:
22788 case TYPE_FPCOMPARE:
22789 case TYPE_CR_LOGICAL:
22790 case TYPE_DELAYED_CR:
22791 return cost + 2;
22792 default:
22793 break;
22795 break;
22797 case TYPE_STORE:
22798 case TYPE_STORE_U:
22799 case TYPE_STORE_UX:
22800 case TYPE_FPSTORE:
22801 case TYPE_FPSTORE_U:
22802 case TYPE_FPSTORE_UX:
22803 if ((rs6000_cpu == PROCESSOR_POWER6)
22804 && recog_memoized (dep_insn)
22805 && (INSN_CODE (dep_insn) >= 0))
22808 if (GET_CODE (PATTERN (insn)) != SET)
22809 /* If this happens, we have to extend this to schedule
22810 optimally. Return default for now. */
22811 return cost;
22813 /* Adjust the cost for the case where the value written
22814 by a fixed point operation is used as the address
22815 gen value on a store. */
22816 switch (get_attr_type (dep_insn))
22818 case TYPE_LOAD:
22819 case TYPE_LOAD_U:
22820 case TYPE_LOAD_UX:
22821 case TYPE_CNTLZ:
22823 if (! store_data_bypass_p (dep_insn, insn))
22824 return 4;
22825 break;
22827 case TYPE_LOAD_EXT:
22828 case TYPE_LOAD_EXT_U:
22829 case TYPE_LOAD_EXT_UX:
22830 case TYPE_VAR_SHIFT_ROTATE:
22831 case TYPE_VAR_DELAYED_COMPARE:
22833 if (! store_data_bypass_p (dep_insn, insn))
22834 return 6;
22835 break;
22837 case TYPE_INTEGER:
22838 case TYPE_COMPARE:
22839 case TYPE_FAST_COMPARE:
22840 case TYPE_EXTS:
22841 case TYPE_SHIFT:
22842 case TYPE_INSERT_WORD:
22843 case TYPE_INSERT_DWORD:
22844 case TYPE_FPLOAD_U:
22845 case TYPE_FPLOAD_UX:
22846 case TYPE_STORE_U:
22847 case TYPE_STORE_UX:
22848 case TYPE_FPSTORE_U:
22849 case TYPE_FPSTORE_UX:
22851 if (! store_data_bypass_p (dep_insn, insn))
22852 return 3;
22853 break;
22855 case TYPE_IMUL:
22856 case TYPE_IMUL2:
22857 case TYPE_IMUL3:
22858 case TYPE_LMUL:
22859 case TYPE_IMUL_COMPARE:
22860 case TYPE_LMUL_COMPARE:
22862 if (! store_data_bypass_p (dep_insn, insn))
22863 return 17;
22864 break;
22866 case TYPE_IDIV:
22868 if (! store_data_bypass_p (dep_insn, insn))
22869 return 45;
22870 break;
22872 case TYPE_LDIV:
22874 if (! store_data_bypass_p (dep_insn, insn))
22875 return 57;
22876 break;
22878 default:
22879 break;
22882 break;
22884 case TYPE_LOAD:
22885 case TYPE_LOAD_U:
22886 case TYPE_LOAD_UX:
22887 case TYPE_LOAD_EXT:
22888 case TYPE_LOAD_EXT_U:
22889 case TYPE_LOAD_EXT_UX:
22890 if ((rs6000_cpu == PROCESSOR_POWER6)
22891 && recog_memoized (dep_insn)
22892 && (INSN_CODE (dep_insn) >= 0))
22895 /* Adjust the cost for the case where the value written
22896 by a fixed point instruction is used within the address
22897 gen portion of a subsequent load(u)(x) */
22898 switch (get_attr_type (dep_insn))
22900 case TYPE_LOAD:
22901 case TYPE_LOAD_U:
22902 case TYPE_LOAD_UX:
22903 case TYPE_CNTLZ:
22905 if (set_to_load_agen (dep_insn, insn))
22906 return 4;
22907 break;
22909 case TYPE_LOAD_EXT:
22910 case TYPE_LOAD_EXT_U:
22911 case TYPE_LOAD_EXT_UX:
22912 case TYPE_VAR_SHIFT_ROTATE:
22913 case TYPE_VAR_DELAYED_COMPARE:
22915 if (set_to_load_agen (dep_insn, insn))
22916 return 6;
22917 break;
22919 case TYPE_INTEGER:
22920 case TYPE_COMPARE:
22921 case TYPE_FAST_COMPARE:
22922 case TYPE_EXTS:
22923 case TYPE_SHIFT:
22924 case TYPE_INSERT_WORD:
22925 case TYPE_INSERT_DWORD:
22926 case TYPE_FPLOAD_U:
22927 case TYPE_FPLOAD_UX:
22928 case TYPE_STORE_U:
22929 case TYPE_STORE_UX:
22930 case TYPE_FPSTORE_U:
22931 case TYPE_FPSTORE_UX:
22933 if (set_to_load_agen (dep_insn, insn))
22934 return 3;
22935 break;
22937 case TYPE_IMUL:
22938 case TYPE_IMUL2:
22939 case TYPE_IMUL3:
22940 case TYPE_LMUL:
22941 case TYPE_IMUL_COMPARE:
22942 case TYPE_LMUL_COMPARE:
22944 if (set_to_load_agen (dep_insn, insn))
22945 return 17;
22946 break;
22948 case TYPE_IDIV:
22950 if (set_to_load_agen (dep_insn, insn))
22951 return 45;
22952 break;
22954 case TYPE_LDIV:
22956 if (set_to_load_agen (dep_insn, insn))
22957 return 57;
22958 break;
22960 default:
22961 break;
22964 break;
22966 case TYPE_FPLOAD:
22967 if ((rs6000_cpu == PROCESSOR_POWER6)
22968 && recog_memoized (dep_insn)
22969 && (INSN_CODE (dep_insn) >= 0)
22970 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
22971 return 2;
22973 default:
22974 break;
22977 /* Fall out to return default cost. */
22979 break;
22981 case REG_DEP_OUTPUT:
22982 /* Output dependency; DEP_INSN writes a register that INSN writes some
22983 cycles later. */
22984 if ((rs6000_cpu == PROCESSOR_POWER6)
22985 && recog_memoized (dep_insn)
22986 && (INSN_CODE (dep_insn) >= 0))
22988 attr_type = get_attr_type (insn);
22990 switch (attr_type)
22992 case TYPE_FP:
22993 if (get_attr_type (dep_insn) == TYPE_FP)
22994 return 1;
22995 break;
22996 case TYPE_FPLOAD:
22997 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
22998 return 2;
22999 break;
23000 default:
23001 break;
23004 case REG_DEP_ANTI:
23005 /* Anti dependency; DEP_INSN reads a register that INSN writes some
23006 cycles later. */
23007 return 0;
23009 default:
23010 gcc_unreachable ();
23013 return cost;
23016 /* Debug version of rs6000_adjust_cost. */
23018 static int
23019 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
23021 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
23023 if (ret != cost)
23025 const char *dep;
23027 switch (REG_NOTE_KIND (link))
23029 default: dep = "unknown depencency"; break;
23030 case REG_DEP_TRUE: dep = "data dependency"; break;
23031 case REG_DEP_OUTPUT: dep = "output dependency"; break;
23032 case REG_DEP_ANTI: dep = "anti depencency"; break;
23035 fprintf (stderr,
23036 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
23037 "%s, insn:\n", ret, cost, dep);
23039 debug_rtx (insn);
23042 return ret;
23045 /* The function returns a true if INSN is microcoded.
23046 Return false otherwise. */
23048 static bool
23049 is_microcoded_insn (rtx insn)
23051 if (!insn || !NONDEBUG_INSN_P (insn)
23052 || GET_CODE (PATTERN (insn)) == USE
23053 || GET_CODE (PATTERN (insn)) == CLOBBER)
23054 return false;
23056 if (rs6000_cpu_attr == CPU_CELL)
23057 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
23059 if (rs6000_sched_groups)
23061 enum attr_type type = get_attr_type (insn);
23062 if (type == TYPE_LOAD_EXT_U
23063 || type == TYPE_LOAD_EXT_UX
23064 || type == TYPE_LOAD_UX
23065 || type == TYPE_STORE_UX
23066 || type == TYPE_MFCR)
23067 return true;
23070 return false;
23073 /* The function returns true if INSN is cracked into 2 instructions
23074 by the processor (and therefore occupies 2 issue slots). */
23076 static bool
23077 is_cracked_insn (rtx insn)
23079 if (!insn || !NONDEBUG_INSN_P (insn)
23080 || GET_CODE (PATTERN (insn)) == USE
23081 || GET_CODE (PATTERN (insn)) == CLOBBER)
23082 return false;
23084 if (rs6000_sched_groups)
23086 enum attr_type type = get_attr_type (insn);
23087 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
23088 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
23089 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
23090 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
23091 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
23092 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
23093 || type == TYPE_IDIV || type == TYPE_LDIV
23094 || type == TYPE_INSERT_WORD)
23095 return true;
23098 return false;
23101 /* The function returns true if INSN can be issued only from
23102 the branch slot. */
23104 static bool
23105 is_branch_slot_insn (rtx insn)
23107 if (!insn || !NONDEBUG_INSN_P (insn)
23108 || GET_CODE (PATTERN (insn)) == USE
23109 || GET_CODE (PATTERN (insn)) == CLOBBER)
23110 return false;
23112 if (rs6000_sched_groups)
23114 enum attr_type type = get_attr_type (insn);
23115 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
23116 return true;
23117 return false;
23120 return false;
23123 /* The function returns true if out_inst sets a value that is
23124 used in the address generation computation of in_insn */
23125 static bool
23126 set_to_load_agen (rtx out_insn, rtx in_insn)
23128 rtx out_set, in_set;
23130 /* For performance reasons, only handle the simple case where
23131 both loads are a single_set. */
23132 out_set = single_set (out_insn);
23133 if (out_set)
23135 in_set = single_set (in_insn);
23136 if (in_set)
23137 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
23140 return false;
23143 /* Try to determine base/offset/size parts of the given MEM.
23144 Return true if successful, false if all the values couldn't
23145 be determined.
23147 This function only looks for REG or REG+CONST address forms.
23148 REG+REG address form will return false. */
23150 static bool
23151 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
23152 HOST_WIDE_INT *size)
23154 rtx addr_rtx;
23155 if MEM_SIZE_KNOWN_P (mem)
23156 *size = MEM_SIZE (mem);
23157 else
23158 return false;
23160 if (GET_CODE (XEXP (mem, 0)) == PRE_MODIFY)
23161 addr_rtx = XEXP (XEXP (mem, 0), 1);
23162 else
23163 addr_rtx = (XEXP (mem, 0));
23165 if (GET_CODE (addr_rtx) == REG)
23167 *base = addr_rtx;
23168 *offset = 0;
23170 else if (GET_CODE (addr_rtx) == PLUS
23171 && CONST_INT_P (XEXP (addr_rtx, 1)))
23173 *base = XEXP (addr_rtx, 0);
23174 *offset = INTVAL (XEXP (addr_rtx, 1));
23176 else
23177 return false;
23179 return true;
23182 /* The function returns true if the target storage location of
23183 mem1 is adjacent to the target storage location of mem2 */
23184 /* Return 1 if memory locations are adjacent. */
23186 static bool
23187 adjacent_mem_locations (rtx mem1, rtx mem2)
23189 rtx reg1, reg2;
23190 HOST_WIDE_INT off1, size1, off2, size2;
23192 if (get_memref_parts (mem1, &reg1, &off1, &size1)
23193 && get_memref_parts (mem2, &reg2, &off2, &size2))
23194 return ((REGNO (reg1) == REGNO (reg2))
23195 && ((off1 + size1 == off2)
23196 || (off2 + size2 == off1)));
23198 return false;
23201 /* This function returns true if it can be determined that the two MEM
23202 locations overlap by at least 1 byte based on base reg/offset/size. */
23204 static bool
23205 mem_locations_overlap (rtx mem1, rtx mem2)
23207 rtx reg1, reg2;
23208 HOST_WIDE_INT off1, size1, off2, size2;
23210 if (get_memref_parts (mem1, &reg1, &off1, &size1)
23211 && get_memref_parts (mem2, &reg2, &off2, &size2))
23212 return ((REGNO (reg1) == REGNO (reg2))
23213 && (((off1 <= off2) && (off1 + size1 > off2))
23214 || ((off2 <= off1) && (off2 + size2 > off1))));
23216 return false;
23219 /* A C statement (sans semicolon) to update the integer scheduling
23220 priority INSN_PRIORITY (INSN). Increase the priority to execute the
23221 INSN earlier, reduce the priority to execute INSN later. Do not
23222 define this macro if you do not need to adjust the scheduling
23223 priorities of insns. */
23225 static int
23226 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
23228 rtx load_mem, str_mem;
23229 /* On machines (like the 750) which have asymmetric integer units,
23230 where one integer unit can do multiply and divides and the other
23231 can't, reduce the priority of multiply/divide so it is scheduled
23232 before other integer operations. */
23234 #if 0
23235 if (! INSN_P (insn))
23236 return priority;
23238 if (GET_CODE (PATTERN (insn)) == USE)
23239 return priority;
23241 switch (rs6000_cpu_attr) {
23242 case CPU_PPC750:
23243 switch (get_attr_type (insn))
23245 default:
23246 break;
23248 case TYPE_IMUL:
23249 case TYPE_IDIV:
23250 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
23251 priority, priority);
23252 if (priority >= 0 && priority < 0x01000000)
23253 priority >>= 3;
23254 break;
23257 #endif
23259 if (insn_must_be_first_in_group (insn)
23260 && reload_completed
23261 && current_sched_info->sched_max_insns_priority
23262 && rs6000_sched_restricted_insns_priority)
23265 /* Prioritize insns that can be dispatched only in the first
23266 dispatch slot. */
23267 if (rs6000_sched_restricted_insns_priority == 1)
23268 /* Attach highest priority to insn. This means that in
23269 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
23270 precede 'priority' (critical path) considerations. */
23271 return current_sched_info->sched_max_insns_priority;
23272 else if (rs6000_sched_restricted_insns_priority == 2)
23273 /* Increase priority of insn by a minimal amount. This means that in
23274 haifa-sched.c:ready_sort(), only 'priority' (critical path)
23275 considerations precede dispatch-slot restriction considerations. */
23276 return (priority + 1);
23279 if (rs6000_cpu == PROCESSOR_POWER6
23280 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
23281 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
23282 /* Attach highest priority to insn if the scheduler has just issued two
23283 stores and this instruction is a load, or two loads and this instruction
23284 is a store. Power6 wants loads and stores scheduled alternately
23285 when possible */
23286 return current_sched_info->sched_max_insns_priority;
23288 return priority;
23291 /* Return true if the instruction is nonpipelined on the Cell. */
23292 static bool
23293 is_nonpipeline_insn (rtx insn)
23295 enum attr_type type;
23296 if (!insn || !NONDEBUG_INSN_P (insn)
23297 || GET_CODE (PATTERN (insn)) == USE
23298 || GET_CODE (PATTERN (insn)) == CLOBBER)
23299 return false;
23301 type = get_attr_type (insn);
23302 if (type == TYPE_IMUL
23303 || type == TYPE_IMUL2
23304 || type == TYPE_IMUL3
23305 || type == TYPE_LMUL
23306 || type == TYPE_IDIV
23307 || type == TYPE_LDIV
23308 || type == TYPE_SDIV
23309 || type == TYPE_DDIV
23310 || type == TYPE_SSQRT
23311 || type == TYPE_DSQRT
23312 || type == TYPE_MFCR
23313 || type == TYPE_MFCRF
23314 || type == TYPE_MFJMPR)
23316 return true;
23318 return false;
23322 /* Return how many instructions the machine can issue per cycle. */
23324 static int
23325 rs6000_issue_rate (void)
23327 /* Unless scheduling for register pressure, use issue rate of 1 for
23328 first scheduling pass to decrease degradation. */
23329 if (!reload_completed && !flag_sched_pressure)
23330 return 1;
23332 switch (rs6000_cpu_attr) {
23333 case CPU_RS64A:
23334 case CPU_PPC601: /* ? */
23335 case CPU_PPC7450:
23336 return 3;
23337 case CPU_PPC440:
23338 case CPU_PPC603:
23339 case CPU_PPC750:
23340 case CPU_PPC7400:
23341 case CPU_PPC8540:
23342 case CPU_PPC8548:
23343 case CPU_CELL:
23344 case CPU_PPCE300C2:
23345 case CPU_PPCE300C3:
23346 case CPU_PPCE500MC:
23347 case CPU_PPCE500MC64:
23348 case CPU_PPCE5500:
23349 case CPU_PPCE6500:
23350 case CPU_TITAN:
23351 return 2;
23352 case CPU_PPC476:
23353 case CPU_PPC604:
23354 case CPU_PPC604E:
23355 case CPU_PPC620:
23356 case CPU_PPC630:
23357 return 4;
23358 case CPU_POWER4:
23359 case CPU_POWER5:
23360 case CPU_POWER6:
23361 case CPU_POWER7:
23362 return 5;
23363 default:
23364 return 1;
23368 /* Return how many instructions to look ahead for better insn
23369 scheduling. */
23371 static int
23372 rs6000_use_sched_lookahead (void)
23374 switch (rs6000_cpu_attr)
23376 case CPU_PPC8540:
23377 case CPU_PPC8548:
23378 return 4;
23380 case CPU_CELL:
23381 return (reload_completed ? 8 : 0);
23383 default:
23384 return 0;
23388 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
23389 static int
23390 rs6000_use_sched_lookahead_guard (rtx insn)
23392 if (rs6000_cpu_attr != CPU_CELL)
23393 return 1;
23395 if (insn == NULL_RTX || !INSN_P (insn))
23396 abort ();
23398 if (!reload_completed
23399 || is_nonpipeline_insn (insn)
23400 || is_microcoded_insn (insn))
23401 return 0;
23403 return 1;
23406 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
23407 and return true. */
23409 static bool
23410 find_mem_ref (rtx pat, rtx *mem_ref)
23412 const char * fmt;
23413 int i, j;
23415 /* stack_tie does not produce any real memory traffic. */
23416 if (tie_operand (pat, VOIDmode))
23417 return false;
23419 if (GET_CODE (pat) == MEM)
23421 *mem_ref = pat;
23422 return true;
23425 /* Recursively process the pattern. */
23426 fmt = GET_RTX_FORMAT (GET_CODE (pat));
23428 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
23430 if (fmt[i] == 'e')
23432 if (find_mem_ref (XEXP (pat, i), mem_ref))
23433 return true;
23435 else if (fmt[i] == 'E')
23436 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
23438 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
23439 return true;
23443 return false;
23446 /* Determine if PAT is a PATTERN of a load insn. */
23448 static bool
23449 is_load_insn1 (rtx pat, rtx *load_mem)
23451 if (!pat || pat == NULL_RTX)
23452 return false;
23454 if (GET_CODE (pat) == SET)
23455 return find_mem_ref (SET_SRC (pat), load_mem);
23457 if (GET_CODE (pat) == PARALLEL)
23459 int i;
23461 for (i = 0; i < XVECLEN (pat, 0); i++)
23462 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
23463 return true;
23466 return false;
23469 /* Determine if INSN loads from memory. */
23471 static bool
23472 is_load_insn (rtx insn, rtx *load_mem)
23474 if (!insn || !INSN_P (insn))
23475 return false;
23477 if (GET_CODE (insn) == CALL_INSN)
23478 return false;
23480 return is_load_insn1 (PATTERN (insn), load_mem);
23483 /* Determine if PAT is a PATTERN of a store insn. */
23485 static bool
23486 is_store_insn1 (rtx pat, rtx *str_mem)
23488 if (!pat || pat == NULL_RTX)
23489 return false;
23491 if (GET_CODE (pat) == SET)
23492 return find_mem_ref (SET_DEST (pat), str_mem);
23494 if (GET_CODE (pat) == PARALLEL)
23496 int i;
23498 for (i = 0; i < XVECLEN (pat, 0); i++)
23499 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
23500 return true;
23503 return false;
23506 /* Determine if INSN stores to memory. */
23508 static bool
23509 is_store_insn (rtx insn, rtx *str_mem)
23511 if (!insn || !INSN_P (insn))
23512 return false;
23514 return is_store_insn1 (PATTERN (insn), str_mem);
23517 /* Returns whether the dependence between INSN and NEXT is considered
23518 costly by the given target. */
23520 static bool
23521 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
23523 rtx insn;
23524 rtx next;
23525 rtx load_mem, str_mem;
23527 /* If the flag is not enabled - no dependence is considered costly;
23528 allow all dependent insns in the same group.
23529 This is the most aggressive option. */
23530 if (rs6000_sched_costly_dep == no_dep_costly)
23531 return false;
23533 /* If the flag is set to 1 - a dependence is always considered costly;
23534 do not allow dependent instructions in the same group.
23535 This is the most conservative option. */
23536 if (rs6000_sched_costly_dep == all_deps_costly)
23537 return true;
23539 insn = DEP_PRO (dep);
23540 next = DEP_CON (dep);
23542 if (rs6000_sched_costly_dep == store_to_load_dep_costly
23543 && is_load_insn (next, &load_mem)
23544 && is_store_insn (insn, &str_mem))
23545 /* Prevent load after store in the same group. */
23546 return true;
23548 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
23549 && is_load_insn (next, &load_mem)
23550 && is_store_insn (insn, &str_mem)
23551 && DEP_TYPE (dep) == REG_DEP_TRUE
23552 && mem_locations_overlap(str_mem, load_mem))
23553 /* Prevent load after store in the same group if it is a true
23554 dependence. */
23555 return true;
23557 /* The flag is set to X; dependences with latency >= X are considered costly,
23558 and will not be scheduled in the same group. */
23559 if (rs6000_sched_costly_dep <= max_dep_latency
23560 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23561 return true;
23563 return false;
23566 /* Return the next insn after INSN that is found before TAIL is reached,
23567 skipping any "non-active" insns - insns that will not actually occupy
23568 an issue slot. Return NULL_RTX if such an insn is not found. */
23570 static rtx
23571 get_next_active_insn (rtx insn, rtx tail)
23573 if (insn == NULL_RTX || insn == tail)
23574 return NULL_RTX;
23576 while (1)
23578 insn = NEXT_INSN (insn);
23579 if (insn == NULL_RTX || insn == tail)
23580 return NULL_RTX;
23582 if (CALL_P (insn)
23583 || JUMP_P (insn)
23584 || (NONJUMP_INSN_P (insn)
23585 && GET_CODE (PATTERN (insn)) != USE
23586 && GET_CODE (PATTERN (insn)) != CLOBBER
23587 && INSN_CODE (insn) != CODE_FOR_stack_tie))
23588 break;
23590 return insn;
23593 /* We are about to begin issuing insns for this clock cycle. */
23595 static int
23596 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23597 rtx *ready ATTRIBUTE_UNUSED,
23598 int *pn_ready ATTRIBUTE_UNUSED,
23599 int clock_var ATTRIBUTE_UNUSED)
23601 int n_ready = *pn_ready;
23603 if (sched_verbose)
23604 fprintf (dump, "// rs6000_sched_reorder :\n");
23606 /* Reorder the ready list, if the second to last ready insn
23607 is a nonepipeline insn. */
23608 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23610 if (is_nonpipeline_insn (ready[n_ready - 1])
23611 && (recog_memoized (ready[n_ready - 2]) > 0))
23612 /* Simply swap first two insns. */
23614 rtx tmp = ready[n_ready - 1];
23615 ready[n_ready - 1] = ready[n_ready - 2];
23616 ready[n_ready - 2] = tmp;
23620 if (rs6000_cpu == PROCESSOR_POWER6)
23621 load_store_pendulum = 0;
23623 return rs6000_issue_rate ();
23626 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23628 static int
23629 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23630 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23632 if (sched_verbose)
23633 fprintf (dump, "// rs6000_sched_reorder2 :\n");
23635 /* For Power6, we need to handle some special cases to try and keep the
23636 store queue from overflowing and triggering expensive flushes.
23638 This code monitors how load and store instructions are being issued
23639 and skews the ready list one way or the other to increase the likelihood
23640 that a desired instruction is issued at the proper time.
23642 A couple of things are done. First, we maintain a "load_store_pendulum"
23643 to track the current state of load/store issue.
23645 - If the pendulum is at zero, then no loads or stores have been
23646 issued in the current cycle so we do nothing.
23648 - If the pendulum is 1, then a single load has been issued in this
23649 cycle and we attempt to locate another load in the ready list to
23650 issue with it.
23652 - If the pendulum is -2, then two stores have already been
23653 issued in this cycle, so we increase the priority of the first load
23654 in the ready list to increase it's likelihood of being chosen first
23655 in the next cycle.
23657 - If the pendulum is -1, then a single store has been issued in this
23658 cycle and we attempt to locate another store in the ready list to
23659 issue with it, preferring a store to an adjacent memory location to
23660 facilitate store pairing in the store queue.
23662 - If the pendulum is 2, then two loads have already been
23663 issued in this cycle, so we increase the priority of the first store
23664 in the ready list to increase it's likelihood of being chosen first
23665 in the next cycle.
23667 - If the pendulum < -2 or > 2, then do nothing.
23669 Note: This code covers the most common scenarios. There exist non
23670 load/store instructions which make use of the LSU and which
23671 would need to be accounted for to strictly model the behavior
23672 of the machine. Those instructions are currently unaccounted
23673 for to help minimize compile time overhead of this code.
23675 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23677 int pos;
23678 int i;
23679 rtx tmp, load_mem, str_mem;
23681 if (is_store_insn (last_scheduled_insn, &str_mem))
23682 /* Issuing a store, swing the load_store_pendulum to the left */
23683 load_store_pendulum--;
23684 else if (is_load_insn (last_scheduled_insn, &load_mem))
23685 /* Issuing a load, swing the load_store_pendulum to the right */
23686 load_store_pendulum++;
23687 else
23688 return cached_can_issue_more;
23690 /* If the pendulum is balanced, or there is only one instruction on
23691 the ready list, then all is well, so return. */
23692 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23693 return cached_can_issue_more;
23695 if (load_store_pendulum == 1)
23697 /* A load has been issued in this cycle. Scan the ready list
23698 for another load to issue with it */
23699 pos = *pn_ready-1;
23701 while (pos >= 0)
23703 if (is_load_insn (ready[pos], &load_mem))
23705 /* Found a load. Move it to the head of the ready list,
23706 and adjust it's priority so that it is more likely to
23707 stay there */
23708 tmp = ready[pos];
23709 for (i=pos; i<*pn_ready-1; i++)
23710 ready[i] = ready[i + 1];
23711 ready[*pn_ready-1] = tmp;
23713 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23714 INSN_PRIORITY (tmp)++;
23715 break;
23717 pos--;
23720 else if (load_store_pendulum == -2)
23722 /* Two stores have been issued in this cycle. Increase the
23723 priority of the first load in the ready list to favor it for
23724 issuing in the next cycle. */
23725 pos = *pn_ready-1;
23727 while (pos >= 0)
23729 if (is_load_insn (ready[pos], &load_mem)
23730 && !sel_sched_p ()
23731 && INSN_PRIORITY_KNOWN (ready[pos]))
23733 INSN_PRIORITY (ready[pos])++;
23735 /* Adjust the pendulum to account for the fact that a load
23736 was found and increased in priority. This is to prevent
23737 increasing the priority of multiple loads */
23738 load_store_pendulum--;
23740 break;
23742 pos--;
23745 else if (load_store_pendulum == -1)
23747 /* A store has been issued in this cycle. Scan the ready list for
23748 another store to issue with it, preferring a store to an adjacent
23749 memory location */
23750 int first_store_pos = -1;
23752 pos = *pn_ready-1;
23754 while (pos >= 0)
23756 if (is_store_insn (ready[pos], &str_mem))
23758 rtx str_mem2;
23759 /* Maintain the index of the first store found on the
23760 list */
23761 if (first_store_pos == -1)
23762 first_store_pos = pos;
23764 if (is_store_insn (last_scheduled_insn, &str_mem2)
23765 && adjacent_mem_locations (str_mem, str_mem2))
23767 /* Found an adjacent store. Move it to the head of the
23768 ready list, and adjust it's priority so that it is
23769 more likely to stay there */
23770 tmp = ready[pos];
23771 for (i=pos; i<*pn_ready-1; i++)
23772 ready[i] = ready[i + 1];
23773 ready[*pn_ready-1] = tmp;
23775 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23776 INSN_PRIORITY (tmp)++;
23778 first_store_pos = -1;
23780 break;
23783 pos--;
23786 if (first_store_pos >= 0)
23788 /* An adjacent store wasn't found, but a non-adjacent store was,
23789 so move the non-adjacent store to the front of the ready
23790 list, and adjust its priority so that it is more likely to
23791 stay there. */
23792 tmp = ready[first_store_pos];
23793 for (i=first_store_pos; i<*pn_ready-1; i++)
23794 ready[i] = ready[i + 1];
23795 ready[*pn_ready-1] = tmp;
23796 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23797 INSN_PRIORITY (tmp)++;
23800 else if (load_store_pendulum == 2)
23802 /* Two loads have been issued in this cycle. Increase the priority
23803 of the first store in the ready list to favor it for issuing in
23804 the next cycle. */
23805 pos = *pn_ready-1;
23807 while (pos >= 0)
23809 if (is_store_insn (ready[pos], &str_mem)
23810 && !sel_sched_p ()
23811 && INSN_PRIORITY_KNOWN (ready[pos]))
23813 INSN_PRIORITY (ready[pos])++;
23815 /* Adjust the pendulum to account for the fact that a store
23816 was found and increased in priority. This is to prevent
23817 increasing the priority of multiple stores */
23818 load_store_pendulum++;
23820 break;
23822 pos--;
23827 return cached_can_issue_more;
23830 /* Return whether the presence of INSN causes a dispatch group termination
23831 of group WHICH_GROUP.
23833 If WHICH_GROUP == current_group, this function will return true if INSN
23834 causes the termination of the current group (i.e, the dispatch group to
23835 which INSN belongs). This means that INSN will be the last insn in the
23836 group it belongs to.
23838 If WHICH_GROUP == previous_group, this function will return true if INSN
23839 causes the termination of the previous group (i.e, the dispatch group that
23840 precedes the group to which INSN belongs). This means that INSN will be
23841 the first insn in the group it belongs to). */
23843 static bool
23844 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23846 bool first, last;
23848 if (! insn)
23849 return false;
23851 first = insn_must_be_first_in_group (insn);
23852 last = insn_must_be_last_in_group (insn);
23854 if (first && last)
23855 return true;
23857 if (which_group == current_group)
23858 return last;
23859 else if (which_group == previous_group)
23860 return first;
23862 return false;
23866 static bool
23867 insn_must_be_first_in_group (rtx insn)
23869 enum attr_type type;
23871 if (!insn
23872 || GET_CODE (insn) == NOTE
23873 || DEBUG_INSN_P (insn)
23874 || GET_CODE (PATTERN (insn)) == USE
23875 || GET_CODE (PATTERN (insn)) == CLOBBER)
23876 return false;
23878 switch (rs6000_cpu)
23880 case PROCESSOR_POWER5:
23881 if (is_cracked_insn (insn))
23882 return true;
23883 case PROCESSOR_POWER4:
23884 if (is_microcoded_insn (insn))
23885 return true;
23887 if (!rs6000_sched_groups)
23888 return false;
23890 type = get_attr_type (insn);
23892 switch (type)
23894 case TYPE_MFCR:
23895 case TYPE_MFCRF:
23896 case TYPE_MTCR:
23897 case TYPE_DELAYED_CR:
23898 case TYPE_CR_LOGICAL:
23899 case TYPE_MTJMPR:
23900 case TYPE_MFJMPR:
23901 case TYPE_IDIV:
23902 case TYPE_LDIV:
23903 case TYPE_LOAD_L:
23904 case TYPE_STORE_C:
23905 case TYPE_ISYNC:
23906 case TYPE_SYNC:
23907 return true;
23908 default:
23909 break;
23911 break;
23912 case PROCESSOR_POWER6:
23913 type = get_attr_type (insn);
23915 switch (type)
23917 case TYPE_INSERT_DWORD:
23918 case TYPE_EXTS:
23919 case TYPE_CNTLZ:
23920 case TYPE_SHIFT:
23921 case TYPE_VAR_SHIFT_ROTATE:
23922 case TYPE_TRAP:
23923 case TYPE_IMUL:
23924 case TYPE_IMUL2:
23925 case TYPE_IMUL3:
23926 case TYPE_LMUL:
23927 case TYPE_IDIV:
23928 case TYPE_INSERT_WORD:
23929 case TYPE_DELAYED_COMPARE:
23930 case TYPE_IMUL_COMPARE:
23931 case TYPE_LMUL_COMPARE:
23932 case TYPE_FPCOMPARE:
23933 case TYPE_MFCR:
23934 case TYPE_MTCR:
23935 case TYPE_MFJMPR:
23936 case TYPE_MTJMPR:
23937 case TYPE_ISYNC:
23938 case TYPE_SYNC:
23939 case TYPE_LOAD_L:
23940 case TYPE_STORE_C:
23941 case TYPE_LOAD_U:
23942 case TYPE_LOAD_UX:
23943 case TYPE_LOAD_EXT_UX:
23944 case TYPE_STORE_U:
23945 case TYPE_STORE_UX:
23946 case TYPE_FPLOAD_U:
23947 case TYPE_FPLOAD_UX:
23948 case TYPE_FPSTORE_U:
23949 case TYPE_FPSTORE_UX:
23950 return true;
23951 default:
23952 break;
23954 break;
23955 case PROCESSOR_POWER7:
23956 type = get_attr_type (insn);
23958 switch (type)
23960 case TYPE_CR_LOGICAL:
23961 case TYPE_MFCR:
23962 case TYPE_MFCRF:
23963 case TYPE_MTCR:
23964 case TYPE_IDIV:
23965 case TYPE_LDIV:
23966 case TYPE_COMPARE:
23967 case TYPE_DELAYED_COMPARE:
23968 case TYPE_VAR_DELAYED_COMPARE:
23969 case TYPE_ISYNC:
23970 case TYPE_LOAD_L:
23971 case TYPE_STORE_C:
23972 case TYPE_LOAD_U:
23973 case TYPE_LOAD_UX:
23974 case TYPE_LOAD_EXT:
23975 case TYPE_LOAD_EXT_U:
23976 case TYPE_LOAD_EXT_UX:
23977 case TYPE_STORE_U:
23978 case TYPE_STORE_UX:
23979 case TYPE_FPLOAD_U:
23980 case TYPE_FPLOAD_UX:
23981 case TYPE_FPSTORE_U:
23982 case TYPE_FPSTORE_UX:
23983 case TYPE_MFJMPR:
23984 case TYPE_MTJMPR:
23985 return true;
23986 default:
23987 break;
23989 break;
23990 default:
23991 break;
23994 return false;
23997 static bool
23998 insn_must_be_last_in_group (rtx insn)
24000 enum attr_type type;
24002 if (!insn
24003 || GET_CODE (insn) == NOTE
24004 || DEBUG_INSN_P (insn)
24005 || GET_CODE (PATTERN (insn)) == USE
24006 || GET_CODE (PATTERN (insn)) == CLOBBER)
24007 return false;
24009 switch (rs6000_cpu) {
24010 case PROCESSOR_POWER4:
24011 case PROCESSOR_POWER5:
24012 if (is_microcoded_insn (insn))
24013 return true;
24015 if (is_branch_slot_insn (insn))
24016 return true;
24018 break;
24019 case PROCESSOR_POWER6:
24020 type = get_attr_type (insn);
24022 switch (type)
24024 case TYPE_EXTS:
24025 case TYPE_CNTLZ:
24026 case TYPE_SHIFT:
24027 case TYPE_VAR_SHIFT_ROTATE:
24028 case TYPE_TRAP:
24029 case TYPE_IMUL:
24030 case TYPE_IMUL2:
24031 case TYPE_IMUL3:
24032 case TYPE_LMUL:
24033 case TYPE_IDIV:
24034 case TYPE_DELAYED_COMPARE:
24035 case TYPE_IMUL_COMPARE:
24036 case TYPE_LMUL_COMPARE:
24037 case TYPE_FPCOMPARE:
24038 case TYPE_MFCR:
24039 case TYPE_MTCR:
24040 case TYPE_MFJMPR:
24041 case TYPE_MTJMPR:
24042 case TYPE_ISYNC:
24043 case TYPE_SYNC:
24044 case TYPE_LOAD_L:
24045 case TYPE_STORE_C:
24046 return true;
24047 default:
24048 break;
24050 break;
24051 case PROCESSOR_POWER7:
24052 type = get_attr_type (insn);
24054 switch (type)
24056 case TYPE_ISYNC:
24057 case TYPE_SYNC:
24058 case TYPE_LOAD_L:
24059 case TYPE_STORE_C:
24060 case TYPE_LOAD_EXT_U:
24061 case TYPE_LOAD_EXT_UX:
24062 case TYPE_STORE_UX:
24063 return true;
24064 default:
24065 break;
24067 break;
24068 default:
24069 break;
24072 return false;
24075 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
24076 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
24078 static bool
24079 is_costly_group (rtx *group_insns, rtx next_insn)
24081 int i;
24082 int issue_rate = rs6000_issue_rate ();
24084 for (i = 0; i < issue_rate; i++)
24086 sd_iterator_def sd_it;
24087 dep_t dep;
24088 rtx insn = group_insns[i];
24090 if (!insn)
24091 continue;
24093 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
24095 rtx next = DEP_CON (dep);
24097 if (next == next_insn
24098 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
24099 return true;
24103 return false;
24106 /* Utility of the function redefine_groups.
24107 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
24108 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
24109 to keep it "far" (in a separate group) from GROUP_INSNS, following
24110 one of the following schemes, depending on the value of the flag
24111 -minsert_sched_nops = X:
24112 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
24113 in order to force NEXT_INSN into a separate group.
24114 (2) X < sched_finish_regroup_exact: insert exactly X nops.
24115 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
24116 insertion (has a group just ended, how many vacant issue slots remain in the
24117 last group, and how many dispatch groups were encountered so far). */
24119 static int
24120 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
24121 rtx next_insn, bool *group_end, int can_issue_more,
24122 int *group_count)
24124 rtx nop;
24125 bool force;
24126 int issue_rate = rs6000_issue_rate ();
24127 bool end = *group_end;
24128 int i;
24130 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
24131 return can_issue_more;
24133 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
24134 return can_issue_more;
24136 force = is_costly_group (group_insns, next_insn);
24137 if (!force)
24138 return can_issue_more;
24140 if (sched_verbose > 6)
24141 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
24142 *group_count ,can_issue_more);
24144 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
24146 if (*group_end)
24147 can_issue_more = 0;
24149 /* Since only a branch can be issued in the last issue_slot, it is
24150 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
24151 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
24152 in this case the last nop will start a new group and the branch
24153 will be forced to the new group. */
24154 if (can_issue_more && !is_branch_slot_insn (next_insn))
24155 can_issue_more--;
24157 /* Power6 and Power7 have special group ending nop. */
24158 if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7)
24160 nop = gen_group_ending_nop ();
24161 emit_insn_before (nop, next_insn);
24162 can_issue_more = 0;
24164 else
24165 while (can_issue_more > 0)
24167 nop = gen_nop ();
24168 emit_insn_before (nop, next_insn);
24169 can_issue_more--;
24172 *group_end = true;
24173 return 0;
24176 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
24178 int n_nops = rs6000_sched_insert_nops;
24180 /* Nops can't be issued from the branch slot, so the effective
24181 issue_rate for nops is 'issue_rate - 1'. */
24182 if (can_issue_more == 0)
24183 can_issue_more = issue_rate;
24184 can_issue_more--;
24185 if (can_issue_more == 0)
24187 can_issue_more = issue_rate - 1;
24188 (*group_count)++;
24189 end = true;
24190 for (i = 0; i < issue_rate; i++)
24192 group_insns[i] = 0;
24196 while (n_nops > 0)
24198 nop = gen_nop ();
24199 emit_insn_before (nop, next_insn);
24200 if (can_issue_more == issue_rate - 1) /* new group begins */
24201 end = false;
24202 can_issue_more--;
24203 if (can_issue_more == 0)
24205 can_issue_more = issue_rate - 1;
24206 (*group_count)++;
24207 end = true;
24208 for (i = 0; i < issue_rate; i++)
24210 group_insns[i] = 0;
24213 n_nops--;
24216 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
24217 can_issue_more++;
24219 /* Is next_insn going to start a new group? */
24220 *group_end
24221 = (end
24222 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
24223 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
24224 || (can_issue_more < issue_rate &&
24225 insn_terminates_group_p (next_insn, previous_group)));
24226 if (*group_end && end)
24227 (*group_count)--;
24229 if (sched_verbose > 6)
24230 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
24231 *group_count, can_issue_more);
24232 return can_issue_more;
24235 return can_issue_more;
24238 /* This function tries to synch the dispatch groups that the compiler "sees"
24239 with the dispatch groups that the processor dispatcher is expected to
24240 form in practice. It tries to achieve this synchronization by forcing the
24241 estimated processor grouping on the compiler (as opposed to the function
24242 'pad_goups' which tries to force the scheduler's grouping on the processor).
24244 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
24245 examines the (estimated) dispatch groups that will be formed by the processor
24246 dispatcher. It marks these group boundaries to reflect the estimated
24247 processor grouping, overriding the grouping that the scheduler had marked.
24248 Depending on the value of the flag '-minsert-sched-nops' this function can
24249 force certain insns into separate groups or force a certain distance between
24250 them by inserting nops, for example, if there exists a "costly dependence"
24251 between the insns.
24253 The function estimates the group boundaries that the processor will form as
24254 follows: It keeps track of how many vacant issue slots are available after
24255 each insn. A subsequent insn will start a new group if one of the following
24256 4 cases applies:
24257 - no more vacant issue slots remain in the current dispatch group.
24258 - only the last issue slot, which is the branch slot, is vacant, but the next
24259 insn is not a branch.
24260 - only the last 2 or less issue slots, including the branch slot, are vacant,
24261 which means that a cracked insn (which occupies two issue slots) can't be
24262 issued in this group.
24263 - less than 'issue_rate' slots are vacant, and the next insn always needs to
24264 start a new group. */
24266 static int
24267 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
24269 rtx insn, next_insn;
24270 int issue_rate;
24271 int can_issue_more;
24272 int slot, i;
24273 bool group_end;
24274 int group_count = 0;
24275 rtx *group_insns;
24277 /* Initialize. */
24278 issue_rate = rs6000_issue_rate ();
24279 group_insns = XALLOCAVEC (rtx, issue_rate);
24280 for (i = 0; i < issue_rate; i++)
24282 group_insns[i] = 0;
24284 can_issue_more = issue_rate;
24285 slot = 0;
24286 insn = get_next_active_insn (prev_head_insn, tail);
24287 group_end = false;
24289 while (insn != NULL_RTX)
24291 slot = (issue_rate - can_issue_more);
24292 group_insns[slot] = insn;
24293 can_issue_more =
24294 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
24295 if (insn_terminates_group_p (insn, current_group))
24296 can_issue_more = 0;
24298 next_insn = get_next_active_insn (insn, tail);
24299 if (next_insn == NULL_RTX)
24300 return group_count + 1;
24302 /* Is next_insn going to start a new group? */
24303 group_end
24304 = (can_issue_more == 0
24305 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
24306 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
24307 || (can_issue_more < issue_rate &&
24308 insn_terminates_group_p (next_insn, previous_group)));
24310 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
24311 next_insn, &group_end, can_issue_more,
24312 &group_count);
24314 if (group_end)
24316 group_count++;
24317 can_issue_more = 0;
24318 for (i = 0; i < issue_rate; i++)
24320 group_insns[i] = 0;
24324 if (GET_MODE (next_insn) == TImode && can_issue_more)
24325 PUT_MODE (next_insn, VOIDmode);
24326 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
24327 PUT_MODE (next_insn, TImode);
24329 insn = next_insn;
24330 if (can_issue_more == 0)
24331 can_issue_more = issue_rate;
24332 } /* while */
24334 return group_count;
24337 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
24338 dispatch group boundaries that the scheduler had marked. Pad with nops
24339 any dispatch groups which have vacant issue slots, in order to force the
24340 scheduler's grouping on the processor dispatcher. The function
24341 returns the number of dispatch groups found. */
24343 static int
24344 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
24346 rtx insn, next_insn;
24347 rtx nop;
24348 int issue_rate;
24349 int can_issue_more;
24350 int group_end;
24351 int group_count = 0;
24353 /* Initialize issue_rate. */
24354 issue_rate = rs6000_issue_rate ();
24355 can_issue_more = issue_rate;
24357 insn = get_next_active_insn (prev_head_insn, tail);
24358 next_insn = get_next_active_insn (insn, tail);
24360 while (insn != NULL_RTX)
24362 can_issue_more =
24363 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
24365 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
24367 if (next_insn == NULL_RTX)
24368 break;
24370 if (group_end)
24372 /* If the scheduler had marked group termination at this location
24373 (between insn and next_insn), and neither insn nor next_insn will
24374 force group termination, pad the group with nops to force group
24375 termination. */
24376 if (can_issue_more
24377 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
24378 && !insn_terminates_group_p (insn, current_group)
24379 && !insn_terminates_group_p (next_insn, previous_group))
24381 if (!is_branch_slot_insn (next_insn))
24382 can_issue_more--;
24384 while (can_issue_more)
24386 nop = gen_nop ();
24387 emit_insn_before (nop, next_insn);
24388 can_issue_more--;
24392 can_issue_more = issue_rate;
24393 group_count++;
24396 insn = next_insn;
24397 next_insn = get_next_active_insn (insn, tail);
24400 return group_count;
24403 /* We're beginning a new block. Initialize data structures as necessary. */
24405 static void
24406 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
24407 int sched_verbose ATTRIBUTE_UNUSED,
24408 int max_ready ATTRIBUTE_UNUSED)
24410 last_scheduled_insn = NULL_RTX;
24411 load_store_pendulum = 0;
24414 /* The following function is called at the end of scheduling BB.
24415 After reload, it inserts nops at insn group bundling. */
24417 static void
24418 rs6000_sched_finish (FILE *dump, int sched_verbose)
24420 int n_groups;
24422 if (sched_verbose)
24423 fprintf (dump, "=== Finishing schedule.\n");
24425 if (reload_completed && rs6000_sched_groups)
24427 /* Do not run sched_finish hook when selective scheduling enabled. */
24428 if (sel_sched_p ())
24429 return;
24431 if (rs6000_sched_insert_nops == sched_finish_none)
24432 return;
24434 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
24435 n_groups = pad_groups (dump, sched_verbose,
24436 current_sched_info->prev_head,
24437 current_sched_info->next_tail);
24438 else
24439 n_groups = redefine_groups (dump, sched_verbose,
24440 current_sched_info->prev_head,
24441 current_sched_info->next_tail);
24443 if (sched_verbose >= 6)
24445 fprintf (dump, "ngroups = %d\n", n_groups);
24446 print_rtl (dump, current_sched_info->prev_head);
24447 fprintf (dump, "Done finish_sched\n");
24452 struct _rs6000_sched_context
24454 short cached_can_issue_more;
24455 rtx last_scheduled_insn;
24456 int load_store_pendulum;
24459 typedef struct _rs6000_sched_context rs6000_sched_context_def;
24460 typedef rs6000_sched_context_def *rs6000_sched_context_t;
24462 /* Allocate store for new scheduling context. */
24463 static void *
24464 rs6000_alloc_sched_context (void)
24466 return xmalloc (sizeof (rs6000_sched_context_def));
24469 /* If CLEAN_P is true then initializes _SC with clean data,
24470 and from the global context otherwise. */
24471 static void
24472 rs6000_init_sched_context (void *_sc, bool clean_p)
24474 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24476 if (clean_p)
24478 sc->cached_can_issue_more = 0;
24479 sc->last_scheduled_insn = NULL_RTX;
24480 sc->load_store_pendulum = 0;
24482 else
24484 sc->cached_can_issue_more = cached_can_issue_more;
24485 sc->last_scheduled_insn = last_scheduled_insn;
24486 sc->load_store_pendulum = load_store_pendulum;
24490 /* Sets the global scheduling context to the one pointed to by _SC. */
24491 static void
24492 rs6000_set_sched_context (void *_sc)
24494 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
24496 gcc_assert (sc != NULL);
24498 cached_can_issue_more = sc->cached_can_issue_more;
24499 last_scheduled_insn = sc->last_scheduled_insn;
24500 load_store_pendulum = sc->load_store_pendulum;
24503 /* Free _SC. */
24504 static void
24505 rs6000_free_sched_context (void *_sc)
24507 gcc_assert (_sc != NULL);
24509 free (_sc);
24513 /* Length in units of the trampoline for entering a nested function. */
24516 rs6000_trampoline_size (void)
24518 int ret = 0;
24520 switch (DEFAULT_ABI)
24522 default:
24523 gcc_unreachable ();
24525 case ABI_AIX:
24526 ret = (TARGET_32BIT) ? 12 : 24;
24527 break;
24529 case ABI_DARWIN:
24530 case ABI_V4:
24531 ret = (TARGET_32BIT) ? 40 : 48;
24532 break;
24535 return ret;
24538 /* Emit RTL insns to initialize the variable parts of a trampoline.
24539 FNADDR is an RTX for the address of the function's pure code.
24540 CXT is an RTX for the static chain value for the function. */
24542 static void
24543 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
24545 int regsize = (TARGET_32BIT) ? 4 : 8;
24546 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
24547 rtx ctx_reg = force_reg (Pmode, cxt);
24548 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
24550 switch (DEFAULT_ABI)
24552 default:
24553 gcc_unreachable ();
24555 /* Under AIX, just build the 3 word function descriptor */
24556 case ABI_AIX:
24558 rtx fnmem, fn_reg, toc_reg;
24560 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
24561 error ("You cannot take the address of a nested function if you use "
24562 "the -mno-pointers-to-nested-functions option.");
24564 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
24565 fn_reg = gen_reg_rtx (Pmode);
24566 toc_reg = gen_reg_rtx (Pmode);
24568 /* Macro to shorten the code expansions below. */
24569 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24571 m_tramp = replace_equiv_address (m_tramp, addr);
24573 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24574 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24575 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24576 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24577 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24579 # undef MEM_PLUS
24581 break;
24583 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24584 case ABI_DARWIN:
24585 case ABI_V4:
24586 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24587 LCT_NORMAL, VOIDmode, 4,
24588 addr, Pmode,
24589 GEN_INT (rs6000_trampoline_size ()), SImode,
24590 fnaddr, Pmode,
24591 ctx_reg, Pmode);
24592 break;
24597 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24598 identifier as an argument, so the front end shouldn't look it up. */
24600 static bool
24601 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24603 return is_attribute_p ("altivec", attr_id);
24606 /* Handle the "altivec" attribute. The attribute may have
24607 arguments as follows:
24609 __attribute__((altivec(vector__)))
24610 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24611 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24613 and may appear more than once (e.g., 'vector bool char') in a
24614 given declaration. */
24616 static tree
24617 rs6000_handle_altivec_attribute (tree *node,
24618 tree name ATTRIBUTE_UNUSED,
24619 tree args,
24620 int flags ATTRIBUTE_UNUSED,
24621 bool *no_add_attrs)
24623 tree type = *node, result = NULL_TREE;
24624 enum machine_mode mode;
24625 int unsigned_p;
24626 char altivec_type
24627 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24628 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24629 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24630 : '?');
24632 while (POINTER_TYPE_P (type)
24633 || TREE_CODE (type) == FUNCTION_TYPE
24634 || TREE_CODE (type) == METHOD_TYPE
24635 || TREE_CODE (type) == ARRAY_TYPE)
24636 type = TREE_TYPE (type);
24638 mode = TYPE_MODE (type);
24640 /* Check for invalid AltiVec type qualifiers. */
24641 if (type == long_double_type_node)
24642 error ("use of %<long double%> in AltiVec types is invalid");
24643 else if (type == boolean_type_node)
24644 error ("use of boolean types in AltiVec types is invalid");
24645 else if (TREE_CODE (type) == COMPLEX_TYPE)
24646 error ("use of %<complex%> in AltiVec types is invalid");
24647 else if (DECIMAL_FLOAT_MODE_P (mode))
24648 error ("use of decimal floating point types in AltiVec types is invalid");
24649 else if (!TARGET_VSX)
24651 if (type == long_unsigned_type_node || type == long_integer_type_node)
24653 if (TARGET_64BIT)
24654 error ("use of %<long%> in AltiVec types is invalid for "
24655 "64-bit code without -mvsx");
24656 else if (rs6000_warn_altivec_long)
24657 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24658 "use %<int%>");
24660 else if (type == long_long_unsigned_type_node
24661 || type == long_long_integer_type_node)
24662 error ("use of %<long long%> in AltiVec types is invalid without "
24663 "-mvsx");
24664 else if (type == double_type_node)
24665 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24668 switch (altivec_type)
24670 case 'v':
24671 unsigned_p = TYPE_UNSIGNED (type);
24672 switch (mode)
24674 case DImode:
24675 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24676 break;
24677 case SImode:
24678 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24679 break;
24680 case HImode:
24681 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24682 break;
24683 case QImode:
24684 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24685 break;
24686 case SFmode: result = V4SF_type_node; break;
24687 case DFmode: result = V2DF_type_node; break;
24688 /* If the user says 'vector int bool', we may be handed the 'bool'
24689 attribute _before_ the 'vector' attribute, and so select the
24690 proper type in the 'b' case below. */
24691 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24692 case V2DImode: case V2DFmode:
24693 result = type;
24694 default: break;
24696 break;
24697 case 'b':
24698 switch (mode)
24700 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24701 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24702 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24703 case QImode: case V16QImode: result = bool_V16QI_type_node;
24704 default: break;
24706 break;
24707 case 'p':
24708 switch (mode)
24710 case V8HImode: result = pixel_V8HI_type_node;
24711 default: break;
24713 default: break;
24716 /* Propagate qualifiers attached to the element type
24717 onto the vector type. */
24718 if (result && result != type && TYPE_QUALS (type))
24719 result = build_qualified_type (result, TYPE_QUALS (type));
24721 *no_add_attrs = true; /* No need to hang on to the attribute. */
24723 if (result)
24724 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24726 return NULL_TREE;
24729 /* AltiVec defines four built-in scalar types that serve as vector
24730 elements; we must teach the compiler how to mangle them. */
24732 static const char *
24733 rs6000_mangle_type (const_tree type)
24735 type = TYPE_MAIN_VARIANT (type);
24737 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24738 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24739 return NULL;
24741 if (type == bool_char_type_node) return "U6__boolc";
24742 if (type == bool_short_type_node) return "U6__bools";
24743 if (type == pixel_type_node) return "u7__pixel";
24744 if (type == bool_int_type_node) return "U6__booli";
24745 if (type == bool_long_type_node) return "U6__booll";
24747 /* Mangle IBM extended float long double as `g' (__float128) on
24748 powerpc*-linux where long-double-64 previously was the default. */
24749 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24750 && TARGET_ELF
24751 && TARGET_LONG_DOUBLE_128
24752 && !TARGET_IEEEQUAD)
24753 return "g";
24755 /* For all other types, use normal C++ mangling. */
24756 return NULL;
24759 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24760 struct attribute_spec.handler. */
24762 static tree
24763 rs6000_handle_longcall_attribute (tree *node, tree name,
24764 tree args ATTRIBUTE_UNUSED,
24765 int flags ATTRIBUTE_UNUSED,
24766 bool *no_add_attrs)
24768 if (TREE_CODE (*node) != FUNCTION_TYPE
24769 && TREE_CODE (*node) != FIELD_DECL
24770 && TREE_CODE (*node) != TYPE_DECL)
24772 warning (OPT_Wattributes, "%qE attribute only applies to functions",
24773 name);
24774 *no_add_attrs = true;
24777 return NULL_TREE;
24780 /* Set longcall attributes on all functions declared when
24781 rs6000_default_long_calls is true. */
24782 static void
24783 rs6000_set_default_type_attributes (tree type)
24785 if (rs6000_default_long_calls
24786 && (TREE_CODE (type) == FUNCTION_TYPE
24787 || TREE_CODE (type) == METHOD_TYPE))
24788 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24789 NULL_TREE,
24790 TYPE_ATTRIBUTES (type));
24792 #if TARGET_MACHO
24793 darwin_set_default_type_attributes (type);
24794 #endif
24797 /* Return a reference suitable for calling a function with the
24798 longcall attribute. */
24801 rs6000_longcall_ref (rtx call_ref)
24803 const char *call_name;
24804 tree node;
24806 if (GET_CODE (call_ref) != SYMBOL_REF)
24807 return call_ref;
24809 /* System V adds '.' to the internal name, so skip them. */
24810 call_name = XSTR (call_ref, 0);
24811 if (*call_name == '.')
24813 while (*call_name == '.')
24814 call_name++;
24816 node = get_identifier (call_name);
24817 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24820 return force_reg (Pmode, call_ref);
24823 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24824 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24825 #endif
24827 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24828 struct attribute_spec.handler. */
24829 static tree
24830 rs6000_handle_struct_attribute (tree *node, tree name,
24831 tree args ATTRIBUTE_UNUSED,
24832 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24834 tree *type = NULL;
24835 if (DECL_P (*node))
24837 if (TREE_CODE (*node) == TYPE_DECL)
24838 type = &TREE_TYPE (*node);
24840 else
24841 type = node;
24843 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24844 || TREE_CODE (*type) == UNION_TYPE)))
24846 warning (OPT_Wattributes, "%qE attribute ignored", name);
24847 *no_add_attrs = true;
24850 else if ((is_attribute_p ("ms_struct", name)
24851 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24852 || ((is_attribute_p ("gcc_struct", name)
24853 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24855 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24856 name);
24857 *no_add_attrs = true;
24860 return NULL_TREE;
24863 static bool
24864 rs6000_ms_bitfield_layout_p (const_tree record_type)
24866 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24867 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24868 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24871 #ifdef USING_ELFOS_H
24873 /* A get_unnamed_section callback, used for switching to toc_section. */
24875 static void
24876 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24878 if (DEFAULT_ABI == ABI_AIX
24879 && TARGET_MINIMAL_TOC
24880 && !TARGET_RELOCATABLE)
24882 if (!toc_initialized)
24884 toc_initialized = 1;
24885 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24886 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24887 fprintf (asm_out_file, "\t.tc ");
24888 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24889 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24890 fprintf (asm_out_file, "\n");
24892 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24893 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24894 fprintf (asm_out_file, " = .+32768\n");
24896 else
24897 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24899 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24900 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24901 else
24903 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24904 if (!toc_initialized)
24906 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24907 fprintf (asm_out_file, " = .+32768\n");
24908 toc_initialized = 1;
24913 /* Implement TARGET_ASM_INIT_SECTIONS. */
24915 static void
24916 rs6000_elf_asm_init_sections (void)
24918 toc_section
24919 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24921 sdata2_section
24922 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24923 SDATA2_SECTION_ASM_OP);
24926 /* Implement TARGET_SELECT_RTX_SECTION. */
24928 static section *
24929 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24930 unsigned HOST_WIDE_INT align)
24932 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
24933 return toc_section;
24934 else
24935 return default_elf_select_rtx_section (mode, x, align);
24938 /* For a SYMBOL_REF, set generic flags and then perform some
24939 target-specific processing.
24941 When the AIX ABI is requested on a non-AIX system, replace the
24942 function name with the real name (with a leading .) rather than the
24943 function descriptor name. This saves a lot of overriding code to
24944 read the prefixes. */
24946 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
24947 static void
24948 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
24950 default_encode_section_info (decl, rtl, first);
24952 if (first
24953 && TREE_CODE (decl) == FUNCTION_DECL
24954 && !TARGET_AIX
24955 && DEFAULT_ABI == ABI_AIX)
24957 rtx sym_ref = XEXP (rtl, 0);
24958 size_t len = strlen (XSTR (sym_ref, 0));
24959 char *str = XALLOCAVEC (char, len + 2);
24960 str[0] = '.';
24961 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
24962 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
24966 static inline bool
24967 compare_section_name (const char *section, const char *templ)
24969 int len;
24971 len = strlen (templ);
24972 return (strncmp (section, templ, len) == 0
24973 && (section[len] == 0 || section[len] == '.'));
24976 bool
24977 rs6000_elf_in_small_data_p (const_tree decl)
24979 if (rs6000_sdata == SDATA_NONE)
24980 return false;
24982 /* We want to merge strings, so we never consider them small data. */
24983 if (TREE_CODE (decl) == STRING_CST)
24984 return false;
24986 /* Functions are never in the small data area. */
24987 if (TREE_CODE (decl) == FUNCTION_DECL)
24988 return false;
24990 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
24992 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
24993 if (compare_section_name (section, ".sdata")
24994 || compare_section_name (section, ".sdata2")
24995 || compare_section_name (section, ".gnu.linkonce.s")
24996 || compare_section_name (section, ".sbss")
24997 || compare_section_name (section, ".sbss2")
24998 || compare_section_name (section, ".gnu.linkonce.sb")
24999 || strcmp (section, ".PPC.EMB.sdata0") == 0
25000 || strcmp (section, ".PPC.EMB.sbss0") == 0)
25001 return true;
25003 else
25005 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
25007 if (size > 0
25008 && size <= g_switch_value
25009 /* If it's not public, and we're not going to reference it there,
25010 there's no need to put it in the small data section. */
25011 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
25012 return true;
25015 return false;
25018 #endif /* USING_ELFOS_H */
25020 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
25022 static bool
25023 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
25025 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
25028 /* Do not place thread-local symbols refs in the object blocks. */
25030 static bool
25031 rs6000_use_blocks_for_decl_p (const_tree decl)
25033 return !DECL_THREAD_LOCAL_P (decl);
25036 /* Return a REG that occurs in ADDR with coefficient 1.
25037 ADDR can be effectively incremented by incrementing REG.
25039 r0 is special and we must not select it as an address
25040 register by this routine since our caller will try to
25041 increment the returned register via an "la" instruction. */
25044 find_addr_reg (rtx addr)
25046 while (GET_CODE (addr) == PLUS)
25048 if (GET_CODE (XEXP (addr, 0)) == REG
25049 && REGNO (XEXP (addr, 0)) != 0)
25050 addr = XEXP (addr, 0);
25051 else if (GET_CODE (XEXP (addr, 1)) == REG
25052 && REGNO (XEXP (addr, 1)) != 0)
25053 addr = XEXP (addr, 1);
25054 else if (CONSTANT_P (XEXP (addr, 0)))
25055 addr = XEXP (addr, 1);
25056 else if (CONSTANT_P (XEXP (addr, 1)))
25057 addr = XEXP (addr, 0);
25058 else
25059 gcc_unreachable ();
25061 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
25062 return addr;
25065 void
25066 rs6000_fatal_bad_address (rtx op)
25068 fatal_insn ("bad address", op);
25071 #if TARGET_MACHO
25073 typedef struct branch_island_d {
25074 tree function_name;
25075 tree label_name;
25076 int line_number;
25077 } branch_island;
25080 static vec<branch_island, va_gc> *branch_islands;
25082 /* Remember to generate a branch island for far calls to the given
25083 function. */
25085 static void
25086 add_compiler_branch_island (tree label_name, tree function_name,
25087 int line_number)
25089 branch_island bi = {function_name, label_name, line_number};
25090 vec_safe_push (branch_islands, bi);
25093 /* Generate far-jump branch islands for everything recorded in
25094 branch_islands. Invoked immediately after the last instruction of
25095 the epilogue has been emitted; the branch islands must be appended
25096 to, and contiguous with, the function body. Mach-O stubs are
25097 generated in machopic_output_stub(). */
25099 static void
25100 macho_branch_islands (void)
25102 char tmp_buf[512];
25104 while (!vec_safe_is_empty (branch_islands))
25106 branch_island *bi = &branch_islands->last ();
25107 const char *label = IDENTIFIER_POINTER (bi->label_name);
25108 const char *name = IDENTIFIER_POINTER (bi->function_name);
25109 char name_buf[512];
25110 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
25111 if (name[0] == '*' || name[0] == '&')
25112 strcpy (name_buf, name+1);
25113 else
25115 name_buf[0] = '_';
25116 strcpy (name_buf+1, name);
25118 strcpy (tmp_buf, "\n");
25119 strcat (tmp_buf, label);
25120 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25121 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
25122 dbxout_stabd (N_SLINE, bi->line_number);
25123 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25124 if (flag_pic)
25126 if (TARGET_LINK_STACK)
25128 char name[32];
25129 get_ppc476_thunk_name (name);
25130 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
25131 strcat (tmp_buf, name);
25132 strcat (tmp_buf, "\n");
25133 strcat (tmp_buf, label);
25134 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
25136 else
25138 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
25139 strcat (tmp_buf, label);
25140 strcat (tmp_buf, "_pic\n");
25141 strcat (tmp_buf, label);
25142 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
25145 strcat (tmp_buf, "\taddis r11,r11,ha16(");
25146 strcat (tmp_buf, name_buf);
25147 strcat (tmp_buf, " - ");
25148 strcat (tmp_buf, label);
25149 strcat (tmp_buf, "_pic)\n");
25151 strcat (tmp_buf, "\tmtlr r0\n");
25153 strcat (tmp_buf, "\taddi r12,r11,lo16(");
25154 strcat (tmp_buf, name_buf);
25155 strcat (tmp_buf, " - ");
25156 strcat (tmp_buf, label);
25157 strcat (tmp_buf, "_pic)\n");
25159 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
25161 else
25163 strcat (tmp_buf, ":\nlis r12,hi16(");
25164 strcat (tmp_buf, name_buf);
25165 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
25166 strcat (tmp_buf, name_buf);
25167 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
25169 output_asm_insn (tmp_buf, 0);
25170 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
25171 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
25172 dbxout_stabd (N_SLINE, bi->line_number);
25173 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
25174 branch_islands->pop ();
25178 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
25179 already there or not. */
25181 static int
25182 no_previous_def (tree function_name)
25184 branch_island *bi;
25185 unsigned ix;
25187 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
25188 if (function_name == bi->function_name)
25189 return 0;
25190 return 1;
25193 /* GET_PREV_LABEL gets the label name from the previous definition of
25194 the function. */
25196 static tree
25197 get_prev_label (tree function_name)
25199 branch_island *bi;
25200 unsigned ix;
25202 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
25203 if (function_name == bi->function_name)
25204 return bi->label_name;
25205 return NULL_TREE;
25208 /* INSN is either a function call or a millicode call. It may have an
25209 unconditional jump in its delay slot.
25211 CALL_DEST is the routine we are calling. */
25213 char *
25214 output_call (rtx insn, rtx *operands, int dest_operand_number,
25215 int cookie_operand_number)
25217 static char buf[256];
25218 if (darwin_emit_branch_islands
25219 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
25220 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
25222 tree labelname;
25223 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
25225 if (no_previous_def (funname))
25227 rtx label_rtx = gen_label_rtx ();
25228 char *label_buf, temp_buf[256];
25229 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
25230 CODE_LABEL_NUMBER (label_rtx));
25231 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
25232 labelname = get_identifier (label_buf);
25233 add_compiler_branch_island (labelname, funname, insn_line (insn));
25235 else
25236 labelname = get_prev_label (funname);
25238 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
25239 instruction will reach 'foo', otherwise link as 'bl L42'".
25240 "L42" should be a 'branch island', that will do a far jump to
25241 'foo'. Branch islands are generated in
25242 macho_branch_islands(). */
25243 sprintf (buf, "jbsr %%z%d,%.246s",
25244 dest_operand_number, IDENTIFIER_POINTER (labelname));
25246 else
25247 sprintf (buf, "bl %%z%d", dest_operand_number);
25248 return buf;
25251 /* Generate PIC and indirect symbol stubs. */
25253 void
25254 machopic_output_stub (FILE *file, const char *symb, const char *stub)
25256 unsigned int length;
25257 char *symbol_name, *lazy_ptr_name;
25258 char *local_label_0;
25259 static int label = 0;
25261 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25262 symb = (*targetm.strip_name_encoding) (symb);
25265 length = strlen (symb);
25266 symbol_name = XALLOCAVEC (char, length + 32);
25267 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
25269 lazy_ptr_name = XALLOCAVEC (char, length + 32);
25270 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
25272 if (flag_pic == 2)
25273 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
25274 else
25275 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
25277 if (flag_pic == 2)
25279 fprintf (file, "\t.align 5\n");
25281 fprintf (file, "%s:\n", stub);
25282 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25284 label++;
25285 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
25286 sprintf (local_label_0, "\"L%011d$spb\"", label);
25288 fprintf (file, "\tmflr r0\n");
25289 if (TARGET_LINK_STACK)
25291 char name[32];
25292 get_ppc476_thunk_name (name);
25293 fprintf (file, "\tbl %s\n", name);
25294 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
25296 else
25298 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
25299 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
25301 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
25302 lazy_ptr_name, local_label_0);
25303 fprintf (file, "\tmtlr r0\n");
25304 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
25305 (TARGET_64BIT ? "ldu" : "lwzu"),
25306 lazy_ptr_name, local_label_0);
25307 fprintf (file, "\tmtctr r12\n");
25308 fprintf (file, "\tbctr\n");
25310 else
25312 fprintf (file, "\t.align 4\n");
25314 fprintf (file, "%s:\n", stub);
25315 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25317 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
25318 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
25319 (TARGET_64BIT ? "ldu" : "lwzu"),
25320 lazy_ptr_name);
25321 fprintf (file, "\tmtctr r12\n");
25322 fprintf (file, "\tbctr\n");
25325 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
25326 fprintf (file, "%s:\n", lazy_ptr_name);
25327 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25328 fprintf (file, "%sdyld_stub_binding_helper\n",
25329 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
25332 /* Legitimize PIC addresses. If the address is already
25333 position-independent, we return ORIG. Newly generated
25334 position-independent addresses go into a reg. This is REG if non
25335 zero, otherwise we allocate register(s) as necessary. */
25337 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
25340 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
25341 rtx reg)
25343 rtx base, offset;
25345 if (reg == NULL && ! reload_in_progress && ! reload_completed)
25346 reg = gen_reg_rtx (Pmode);
25348 if (GET_CODE (orig) == CONST)
25350 rtx reg_temp;
25352 if (GET_CODE (XEXP (orig, 0)) == PLUS
25353 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
25354 return orig;
25356 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
25358 /* Use a different reg for the intermediate value, as
25359 it will be marked UNCHANGING. */
25360 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
25361 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
25362 Pmode, reg_temp);
25363 offset =
25364 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
25365 Pmode, reg);
25367 if (GET_CODE (offset) == CONST_INT)
25369 if (SMALL_INT (offset))
25370 return plus_constant (Pmode, base, INTVAL (offset));
25371 else if (! reload_in_progress && ! reload_completed)
25372 offset = force_reg (Pmode, offset);
25373 else
25375 rtx mem = force_const_mem (Pmode, orig);
25376 return machopic_legitimize_pic_address (mem, Pmode, reg);
25379 return gen_rtx_PLUS (Pmode, base, offset);
25382 /* Fall back on generic machopic code. */
25383 return machopic_legitimize_pic_address (orig, mode, reg);
25386 /* Output a .machine directive for the Darwin assembler, and call
25387 the generic start_file routine. */
25389 static void
25390 rs6000_darwin_file_start (void)
25392 static const struct
25394 const char *arg;
25395 const char *name;
25396 HOST_WIDE_INT if_set;
25397 } mapping[] = {
25398 { "ppc64", "ppc64", MASK_64BIT },
25399 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
25400 { "power4", "ppc970", 0 },
25401 { "G5", "ppc970", 0 },
25402 { "7450", "ppc7450", 0 },
25403 { "7400", "ppc7400", MASK_ALTIVEC },
25404 { "G4", "ppc7400", 0 },
25405 { "750", "ppc750", 0 },
25406 { "740", "ppc750", 0 },
25407 { "G3", "ppc750", 0 },
25408 { "604e", "ppc604e", 0 },
25409 { "604", "ppc604", 0 },
25410 { "603e", "ppc603", 0 },
25411 { "603", "ppc603", 0 },
25412 { "601", "ppc601", 0 },
25413 { NULL, "ppc", 0 } };
25414 const char *cpu_id = "";
25415 size_t i;
25417 rs6000_file_start ();
25418 darwin_file_start ();
25420 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
25422 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
25423 cpu_id = rs6000_default_cpu;
25425 if (global_options_set.x_rs6000_cpu_index)
25426 cpu_id = processor_target_table[rs6000_cpu_index].name;
25428 /* Look through the mapping array. Pick the first name that either
25429 matches the argument, has a bit set in IF_SET that is also set
25430 in the target flags, or has a NULL name. */
25432 i = 0;
25433 while (mapping[i].arg != NULL
25434 && strcmp (mapping[i].arg, cpu_id) != 0
25435 && (mapping[i].if_set & rs6000_isa_flags) == 0)
25436 i++;
25438 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
25441 #endif /* TARGET_MACHO */
25443 #if TARGET_ELF
25444 static int
25445 rs6000_elf_reloc_rw_mask (void)
25447 if (flag_pic)
25448 return 3;
25449 else if (DEFAULT_ABI == ABI_AIX)
25450 return 2;
25451 else
25452 return 0;
25455 /* Record an element in the table of global constructors. SYMBOL is
25456 a SYMBOL_REF of the function to be called; PRIORITY is a number
25457 between 0 and MAX_INIT_PRIORITY.
25459 This differs from default_named_section_asm_out_constructor in
25460 that we have special handling for -mrelocatable. */
25462 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
25463 static void
25464 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
25466 const char *section = ".ctors";
25467 char buf[16];
25469 if (priority != DEFAULT_INIT_PRIORITY)
25471 sprintf (buf, ".ctors.%.5u",
25472 /* Invert the numbering so the linker puts us in the proper
25473 order; constructors are run from right to left, and the
25474 linker sorts in increasing order. */
25475 MAX_INIT_PRIORITY - priority);
25476 section = buf;
25479 switch_to_section (get_section (section, SECTION_WRITE, NULL));
25480 assemble_align (POINTER_SIZE);
25482 if (TARGET_RELOCATABLE)
25484 fputs ("\t.long (", asm_out_file);
25485 output_addr_const (asm_out_file, symbol);
25486 fputs (")@fixup\n", asm_out_file);
25488 else
25489 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25492 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
25493 static void
25494 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
25496 const char *section = ".dtors";
25497 char buf[16];
25499 if (priority != DEFAULT_INIT_PRIORITY)
25501 sprintf (buf, ".dtors.%.5u",
25502 /* Invert the numbering so the linker puts us in the proper
25503 order; constructors are run from right to left, and the
25504 linker sorts in increasing order. */
25505 MAX_INIT_PRIORITY - priority);
25506 section = buf;
25509 switch_to_section (get_section (section, SECTION_WRITE, NULL));
25510 assemble_align (POINTER_SIZE);
25512 if (TARGET_RELOCATABLE)
25514 fputs ("\t.long (", asm_out_file);
25515 output_addr_const (asm_out_file, symbol);
25516 fputs (")@fixup\n", asm_out_file);
25518 else
25519 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
25522 void
25523 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
25525 if (TARGET_64BIT)
25527 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
25528 ASM_OUTPUT_LABEL (file, name);
25529 fputs (DOUBLE_INT_ASM_OP, file);
25530 rs6000_output_function_entry (file, name);
25531 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
25532 if (DOT_SYMBOLS)
25534 fputs ("\t.size\t", file);
25535 assemble_name (file, name);
25536 fputs (",24\n\t.type\t.", file);
25537 assemble_name (file, name);
25538 fputs (",@function\n", file);
25539 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
25541 fputs ("\t.globl\t.", file);
25542 assemble_name (file, name);
25543 putc ('\n', file);
25546 else
25547 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25548 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25549 rs6000_output_function_entry (file, name);
25550 fputs (":\n", file);
25551 return;
25554 if (TARGET_RELOCATABLE
25555 && !TARGET_SECURE_PLT
25556 && (get_pool_size () != 0 || crtl->profile)
25557 && uses_TOC ())
25559 char buf[256];
25561 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
25563 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
25564 fprintf (file, "\t.long ");
25565 assemble_name (file, buf);
25566 putc ('-', file);
25567 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25568 assemble_name (file, buf);
25569 putc ('\n', file);
25572 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25573 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25575 if (DEFAULT_ABI == ABI_AIX)
25577 const char *desc_name, *orig_name;
25579 orig_name = (*targetm.strip_name_encoding) (name);
25580 desc_name = orig_name;
25581 while (*desc_name == '.')
25582 desc_name++;
25584 if (TREE_PUBLIC (decl))
25585 fprintf (file, "\t.globl %s\n", desc_name);
25587 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25588 fprintf (file, "%s:\n", desc_name);
25589 fprintf (file, "\t.long %s\n", orig_name);
25590 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25591 if (DEFAULT_ABI == ABI_AIX)
25592 fputs ("\t.long 0\n", file);
25593 fprintf (file, "\t.previous\n");
25595 ASM_OUTPUT_LABEL (file, name);
25598 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
25599 static void
25600 rs6000_elf_file_end (void)
25602 #ifdef HAVE_AS_GNU_ATTRIBUTE
25603 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25605 if (rs6000_passes_float)
25606 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25607 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25608 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25609 : 2));
25610 if (rs6000_passes_vector)
25611 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25612 (TARGET_ALTIVEC_ABI ? 2
25613 : TARGET_SPE_ABI ? 3
25614 : 1));
25615 if (rs6000_returns_struct)
25616 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25617 aix_struct_return ? 2 : 1);
25619 #endif
25620 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25621 if (TARGET_32BIT)
25622 file_end_indicate_exec_stack ();
25623 #endif
25625 #endif
25627 #if TARGET_XCOFF
25628 static void
25629 rs6000_xcoff_asm_output_anchor (rtx symbol)
25631 char buffer[100];
25633 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25634 SYMBOL_REF_BLOCK_OFFSET (symbol));
25635 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25638 static void
25639 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25641 fputs (GLOBAL_ASM_OP, stream);
25642 RS6000_OUTPUT_BASENAME (stream, name);
25643 putc ('\n', stream);
25646 /* A get_unnamed_decl callback, used for read-only sections. PTR
25647 points to the section string variable. */
25649 static void
25650 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25652 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25653 *(const char *const *) directive,
25654 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25657 /* Likewise for read-write sections. */
25659 static void
25660 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25662 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25663 *(const char *const *) directive,
25664 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25667 static void
25668 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
25670 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
25671 *(const char *const *) directive,
25672 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25675 /* A get_unnamed_section callback, used for switching to toc_section. */
25677 static void
25678 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25680 if (TARGET_MINIMAL_TOC)
25682 /* toc_section is always selected at least once from
25683 rs6000_xcoff_file_start, so this is guaranteed to
25684 always be defined once and only once in each file. */
25685 if (!toc_initialized)
25687 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25688 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25689 toc_initialized = 1;
25691 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25692 (TARGET_32BIT ? "" : ",3"));
25694 else
25695 fputs ("\t.toc\n", asm_out_file);
25698 /* Implement TARGET_ASM_INIT_SECTIONS. */
25700 static void
25701 rs6000_xcoff_asm_init_sections (void)
25703 read_only_data_section
25704 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25705 &xcoff_read_only_section_name);
25707 private_data_section
25708 = get_unnamed_section (SECTION_WRITE,
25709 rs6000_xcoff_output_readwrite_section_asm_op,
25710 &xcoff_private_data_section_name);
25712 tls_data_section
25713 = get_unnamed_section (SECTION_TLS,
25714 rs6000_xcoff_output_tls_section_asm_op,
25715 &xcoff_tls_data_section_name);
25717 read_only_private_data_section
25718 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25719 &xcoff_private_data_section_name);
25721 toc_section
25722 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25724 readonly_data_section = read_only_data_section;
25725 exception_section = data_section;
25728 static int
25729 rs6000_xcoff_reloc_rw_mask (void)
25731 return 3;
25734 static void
25735 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25736 tree decl ATTRIBUTE_UNUSED)
25738 int smclass;
25739 static const char * const suffix[4] = { "PR", "RO", "RW", "TL" };
25741 if (flags & SECTION_CODE)
25742 smclass = 0;
25743 else if (flags & SECTION_TLS)
25744 smclass = 3;
25745 else if (flags & SECTION_WRITE)
25746 smclass = 2;
25747 else
25748 smclass = 1;
25750 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25751 (flags & SECTION_CODE) ? "." : "",
25752 name, suffix[smclass], flags & SECTION_ENTSIZE);
25755 static section *
25756 rs6000_xcoff_select_section (tree decl, int reloc,
25757 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25759 if (decl_readonly_section (decl, reloc))
25761 if (TREE_PUBLIC (decl))
25762 return read_only_data_section;
25763 else
25764 return read_only_private_data_section;
25766 else
25768 #if HAVE_AS_TLS
25769 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
25770 return tls_data_section;
25771 else
25772 #endif
25773 if (TREE_PUBLIC (decl))
25774 return data_section;
25775 else
25776 return private_data_section;
25780 static void
25781 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25783 const char *name;
25785 /* Use select_section for private and uninitialized data. */
25786 if (!TREE_PUBLIC (decl)
25787 || DECL_COMMON (decl)
25788 || DECL_INITIAL (decl) == NULL_TREE
25789 || DECL_INITIAL (decl) == error_mark_node
25790 || (flag_zero_initialized_in_bss
25791 && initializer_zerop (DECL_INITIAL (decl))))
25792 return;
25794 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25795 name = (*targetm.strip_name_encoding) (name);
25796 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25799 /* Select section for constant in constant pool.
25801 On RS/6000, all constants are in the private read-only data area.
25802 However, if this is being placed in the TOC it must be output as a
25803 toc entry. */
25805 static section *
25806 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25807 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25809 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25810 return toc_section;
25811 else
25812 return read_only_private_data_section;
25815 /* Remove any trailing [DS] or the like from the symbol name. */
25817 static const char *
25818 rs6000_xcoff_strip_name_encoding (const char *name)
25820 size_t len;
25821 if (*name == '*')
25822 name++;
25823 len = strlen (name);
25824 if (name[len - 1] == ']')
25825 return ggc_alloc_string (name, len - 4);
25826 else
25827 return name;
25830 /* Section attributes. AIX is always PIC. */
25832 static unsigned int
25833 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25835 unsigned int align;
25836 unsigned int flags = default_section_type_flags (decl, name, reloc);
25838 /* Align to at least UNIT size. */
25839 if (flags & SECTION_CODE || !decl)
25840 align = MIN_UNITS_PER_WORD;
25841 else
25842 /* Increase alignment of large objects if not already stricter. */
25843 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25844 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25845 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25847 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25850 /* Output at beginning of assembler file.
25852 Initialize the section names for the RS/6000 at this point.
25854 Specify filename, including full path, to assembler.
25856 We want to go into the TOC section so at least one .toc will be emitted.
25857 Also, in order to output proper .bs/.es pairs, we need at least one static
25858 [RW] section emitted.
25860 Finally, declare mcount when profiling to make the assembler happy. */
25862 static void
25863 rs6000_xcoff_file_start (void)
25865 rs6000_gen_section_name (&xcoff_bss_section_name,
25866 main_input_filename, ".bss_");
25867 rs6000_gen_section_name (&xcoff_private_data_section_name,
25868 main_input_filename, ".rw_");
25869 rs6000_gen_section_name (&xcoff_tls_data_section_name,
25870 main_input_filename, ".tls_");
25871 rs6000_gen_section_name (&xcoff_read_only_section_name,
25872 main_input_filename, ".ro_");
25874 fputs ("\t.file\t", asm_out_file);
25875 output_quoted_string (asm_out_file, main_input_filename);
25876 fputc ('\n', asm_out_file);
25877 if (write_symbols != NO_DEBUG)
25878 switch_to_section (private_data_section);
25879 switch_to_section (text_section);
25880 if (profile_flag)
25881 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25882 rs6000_file_start ();
25885 /* Output at end of assembler file.
25886 On the RS/6000, referencing data should automatically pull in text. */
25888 static void
25889 rs6000_xcoff_file_end (void)
25891 switch_to_section (text_section);
25892 fputs ("_section_.text:\n", asm_out_file);
25893 switch_to_section (data_section);
25894 fputs (TARGET_32BIT
25895 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25896 asm_out_file);
25898 #endif /* TARGET_XCOFF */
25900 /* Compute a (partial) cost for rtx X. Return true if the complete
25901 cost has been computed, and false if subexpressions should be
25902 scanned. In either case, *TOTAL contains the cost result. */
25904 static bool
25905 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
25906 int *total, bool speed)
25908 enum machine_mode mode = GET_MODE (x);
25910 switch (code)
25912 /* On the RS/6000, if it is valid in the insn, it is free. */
25913 case CONST_INT:
25914 if (((outer_code == SET
25915 || outer_code == PLUS
25916 || outer_code == MINUS)
25917 && (satisfies_constraint_I (x)
25918 || satisfies_constraint_L (x)))
25919 || (outer_code == AND
25920 && (satisfies_constraint_K (x)
25921 || (mode == SImode
25922 ? satisfies_constraint_L (x)
25923 : satisfies_constraint_J (x))
25924 || mask_operand (x, mode)
25925 || (mode == DImode
25926 && mask64_operand (x, DImode))))
25927 || ((outer_code == IOR || outer_code == XOR)
25928 && (satisfies_constraint_K (x)
25929 || (mode == SImode
25930 ? satisfies_constraint_L (x)
25931 : satisfies_constraint_J (x))))
25932 || outer_code == ASHIFT
25933 || outer_code == ASHIFTRT
25934 || outer_code == LSHIFTRT
25935 || outer_code == ROTATE
25936 || outer_code == ROTATERT
25937 || outer_code == ZERO_EXTRACT
25938 || (outer_code == MULT
25939 && satisfies_constraint_I (x))
25940 || ((outer_code == DIV || outer_code == UDIV
25941 || outer_code == MOD || outer_code == UMOD)
25942 && exact_log2 (INTVAL (x)) >= 0)
25943 || (outer_code == COMPARE
25944 && (satisfies_constraint_I (x)
25945 || satisfies_constraint_K (x)))
25946 || ((outer_code == EQ || outer_code == NE)
25947 && (satisfies_constraint_I (x)
25948 || satisfies_constraint_K (x)
25949 || (mode == SImode
25950 ? satisfies_constraint_L (x)
25951 : satisfies_constraint_J (x))))
25952 || (outer_code == GTU
25953 && satisfies_constraint_I (x))
25954 || (outer_code == LTU
25955 && satisfies_constraint_P (x)))
25957 *total = 0;
25958 return true;
25960 else if ((outer_code == PLUS
25961 && reg_or_add_cint_operand (x, VOIDmode))
25962 || (outer_code == MINUS
25963 && reg_or_sub_cint_operand (x, VOIDmode))
25964 || ((outer_code == SET
25965 || outer_code == IOR
25966 || outer_code == XOR)
25967 && (INTVAL (x)
25968 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
25970 *total = COSTS_N_INSNS (1);
25971 return true;
25973 /* FALLTHRU */
25975 case CONST_DOUBLE:
25976 if (mode == DImode && code == CONST_DOUBLE)
25978 if ((outer_code == IOR || outer_code == XOR)
25979 && CONST_DOUBLE_HIGH (x) == 0
25980 && (CONST_DOUBLE_LOW (x)
25981 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
25983 *total = 0;
25984 return true;
25986 else if ((outer_code == AND && and64_2_operand (x, DImode))
25987 || ((outer_code == SET
25988 || outer_code == IOR
25989 || outer_code == XOR)
25990 && CONST_DOUBLE_HIGH (x) == 0))
25992 *total = COSTS_N_INSNS (1);
25993 return true;
25996 /* FALLTHRU */
25998 case CONST:
25999 case HIGH:
26000 case SYMBOL_REF:
26001 case MEM:
26002 /* When optimizing for size, MEM should be slightly more expensive
26003 than generating address, e.g., (plus (reg) (const)).
26004 L1 cache latency is about two instructions. */
26005 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
26006 return true;
26008 case LABEL_REF:
26009 *total = 0;
26010 return true;
26012 case PLUS:
26013 case MINUS:
26014 if (FLOAT_MODE_P (mode))
26015 *total = rs6000_cost->fp;
26016 else
26017 *total = COSTS_N_INSNS (1);
26018 return false;
26020 case MULT:
26021 if (GET_CODE (XEXP (x, 1)) == CONST_INT
26022 && satisfies_constraint_I (XEXP (x, 1)))
26024 if (INTVAL (XEXP (x, 1)) >= -256
26025 && INTVAL (XEXP (x, 1)) <= 255)
26026 *total = rs6000_cost->mulsi_const9;
26027 else
26028 *total = rs6000_cost->mulsi_const;
26030 else if (mode == SFmode)
26031 *total = rs6000_cost->fp;
26032 else if (FLOAT_MODE_P (mode))
26033 *total = rs6000_cost->dmul;
26034 else if (mode == DImode)
26035 *total = rs6000_cost->muldi;
26036 else
26037 *total = rs6000_cost->mulsi;
26038 return false;
26040 case FMA:
26041 if (mode == SFmode)
26042 *total = rs6000_cost->fp;
26043 else
26044 *total = rs6000_cost->dmul;
26045 break;
26047 case DIV:
26048 case MOD:
26049 if (FLOAT_MODE_P (mode))
26051 *total = mode == DFmode ? rs6000_cost->ddiv
26052 : rs6000_cost->sdiv;
26053 return false;
26055 /* FALLTHRU */
26057 case UDIV:
26058 case UMOD:
26059 if (GET_CODE (XEXP (x, 1)) == CONST_INT
26060 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
26062 if (code == DIV || code == MOD)
26063 /* Shift, addze */
26064 *total = COSTS_N_INSNS (2);
26065 else
26066 /* Shift */
26067 *total = COSTS_N_INSNS (1);
26069 else
26071 if (GET_MODE (XEXP (x, 1)) == DImode)
26072 *total = rs6000_cost->divdi;
26073 else
26074 *total = rs6000_cost->divsi;
26076 /* Add in shift and subtract for MOD. */
26077 if (code == MOD || code == UMOD)
26078 *total += COSTS_N_INSNS (2);
26079 return false;
26081 case CTZ:
26082 case FFS:
26083 *total = COSTS_N_INSNS (4);
26084 return false;
26086 case POPCOUNT:
26087 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
26088 return false;
26090 case PARITY:
26091 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
26092 return false;
26094 case NOT:
26095 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
26097 *total = 0;
26098 return false;
26100 /* FALLTHRU */
26102 case AND:
26103 case CLZ:
26104 case IOR:
26105 case XOR:
26106 case ZERO_EXTRACT:
26107 *total = COSTS_N_INSNS (1);
26108 return false;
26110 case ASHIFT:
26111 case ASHIFTRT:
26112 case LSHIFTRT:
26113 case ROTATE:
26114 case ROTATERT:
26115 /* Handle mul_highpart. */
26116 if (outer_code == TRUNCATE
26117 && GET_CODE (XEXP (x, 0)) == MULT)
26119 if (mode == DImode)
26120 *total = rs6000_cost->muldi;
26121 else
26122 *total = rs6000_cost->mulsi;
26123 return true;
26125 else if (outer_code == AND)
26126 *total = 0;
26127 else
26128 *total = COSTS_N_INSNS (1);
26129 return false;
26131 case SIGN_EXTEND:
26132 case ZERO_EXTEND:
26133 if (GET_CODE (XEXP (x, 0)) == MEM)
26134 *total = 0;
26135 else
26136 *total = COSTS_N_INSNS (1);
26137 return false;
26139 case COMPARE:
26140 case NEG:
26141 case ABS:
26142 if (!FLOAT_MODE_P (mode))
26144 *total = COSTS_N_INSNS (1);
26145 return false;
26147 /* FALLTHRU */
26149 case FLOAT:
26150 case UNSIGNED_FLOAT:
26151 case FIX:
26152 case UNSIGNED_FIX:
26153 case FLOAT_TRUNCATE:
26154 *total = rs6000_cost->fp;
26155 return false;
26157 case FLOAT_EXTEND:
26158 if (mode == DFmode)
26159 *total = 0;
26160 else
26161 *total = rs6000_cost->fp;
26162 return false;
26164 case UNSPEC:
26165 switch (XINT (x, 1))
26167 case UNSPEC_FRSP:
26168 *total = rs6000_cost->fp;
26169 return true;
26171 default:
26172 break;
26174 break;
26176 case CALL:
26177 case IF_THEN_ELSE:
26178 if (!speed)
26180 *total = COSTS_N_INSNS (1);
26181 return true;
26183 else if (FLOAT_MODE_P (mode)
26184 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
26186 *total = rs6000_cost->fp;
26187 return false;
26189 break;
26191 case EQ:
26192 case GTU:
26193 case LTU:
26194 /* Carry bit requires mode == Pmode.
26195 NEG or PLUS already counted so only add one. */
26196 if (mode == Pmode
26197 && (outer_code == NEG || outer_code == PLUS))
26199 *total = COSTS_N_INSNS (1);
26200 return true;
26202 if (outer_code == SET)
26204 if (XEXP (x, 1) == const0_rtx)
26206 if (TARGET_ISEL && !TARGET_MFCRF)
26207 *total = COSTS_N_INSNS (8);
26208 else
26209 *total = COSTS_N_INSNS (2);
26210 return true;
26212 else if (mode == Pmode)
26214 *total = COSTS_N_INSNS (3);
26215 return false;
26218 /* FALLTHRU */
26220 case GT:
26221 case LT:
26222 case UNORDERED:
26223 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
26225 if (TARGET_ISEL && !TARGET_MFCRF)
26226 *total = COSTS_N_INSNS (8);
26227 else
26228 *total = COSTS_N_INSNS (2);
26229 return true;
26231 /* CC COMPARE. */
26232 if (outer_code == COMPARE)
26234 *total = 0;
26235 return true;
26237 break;
26239 default:
26240 break;
26243 return false;
26246 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
26248 static bool
26249 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
26250 bool speed)
26252 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
26254 fprintf (stderr,
26255 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
26256 "opno = %d, total = %d, speed = %s, x:\n",
26257 ret ? "complete" : "scan inner",
26258 GET_RTX_NAME (code),
26259 GET_RTX_NAME (outer_code),
26260 opno,
26261 *total,
26262 speed ? "true" : "false");
26264 debug_rtx (x);
26266 return ret;
26269 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
26271 static int
26272 rs6000_debug_address_cost (rtx x, enum machine_mode mode,
26273 addr_space_t as, bool speed)
26275 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
26277 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
26278 ret, speed ? "true" : "false");
26279 debug_rtx (x);
26281 return ret;
26285 /* A C expression returning the cost of moving data from a register of class
26286 CLASS1 to one of CLASS2. */
26288 static int
26289 rs6000_register_move_cost (enum machine_mode mode,
26290 reg_class_t from, reg_class_t to)
26292 int ret;
26294 if (TARGET_DEBUG_COST)
26295 dbg_cost_ctrl++;
26297 /* Moves from/to GENERAL_REGS. */
26298 if (reg_classes_intersect_p (to, GENERAL_REGS)
26299 || reg_classes_intersect_p (from, GENERAL_REGS))
26301 reg_class_t rclass = from;
26303 if (! reg_classes_intersect_p (to, GENERAL_REGS))
26304 rclass = to;
26306 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
26307 ret = (rs6000_memory_move_cost (mode, rclass, false)
26308 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
26310 /* It's more expensive to move CR_REGS than CR0_REGS because of the
26311 shift. */
26312 else if (rclass == CR_REGS)
26313 ret = 4;
26315 /* For those processors that have slow LR/CTR moves, make them more
26316 expensive than memory in order to bias spills to memory .*/
26317 else if ((rs6000_cpu == PROCESSOR_POWER6
26318 || rs6000_cpu == PROCESSOR_POWER7)
26319 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
26320 ret = 6 * hard_regno_nregs[0][mode];
26322 else
26323 /* A move will cost one instruction per GPR moved. */
26324 ret = 2 * hard_regno_nregs[0][mode];
26327 /* If we have VSX, we can easily move between FPR or Altivec registers. */
26328 else if (VECTOR_UNIT_VSX_P (mode)
26329 && reg_classes_intersect_p (to, VSX_REGS)
26330 && reg_classes_intersect_p (from, VSX_REGS))
26331 ret = 2 * hard_regno_nregs[32][mode];
26333 /* Moving between two similar registers is just one instruction. */
26334 else if (reg_classes_intersect_p (to, from))
26335 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
26337 /* Everything else has to go through GENERAL_REGS. */
26338 else
26339 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
26340 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
26342 if (TARGET_DEBUG_COST)
26344 if (dbg_cost_ctrl == 1)
26345 fprintf (stderr,
26346 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
26347 ret, GET_MODE_NAME (mode), reg_class_names[from],
26348 reg_class_names[to]);
26349 dbg_cost_ctrl--;
26352 return ret;
26355 /* A C expressions returning the cost of moving data of MODE from a register to
26356 or from memory. */
26358 static int
26359 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
26360 bool in ATTRIBUTE_UNUSED)
26362 int ret;
26364 if (TARGET_DEBUG_COST)
26365 dbg_cost_ctrl++;
26367 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
26368 ret = 4 * hard_regno_nregs[0][mode];
26369 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
26370 ret = 4 * hard_regno_nregs[32][mode];
26371 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
26372 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
26373 else
26374 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
26376 if (TARGET_DEBUG_COST)
26378 if (dbg_cost_ctrl == 1)
26379 fprintf (stderr,
26380 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
26381 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
26382 dbg_cost_ctrl--;
26385 return ret;
26388 /* Returns a code for a target-specific builtin that implements
26389 reciprocal of the function, or NULL_TREE if not available. */
26391 static tree
26392 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
26393 bool sqrt ATTRIBUTE_UNUSED)
26395 if (optimize_insn_for_size_p ())
26396 return NULL_TREE;
26398 if (md_fn)
26399 switch (fn)
26401 case VSX_BUILTIN_XVSQRTDP:
26402 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
26403 return NULL_TREE;
26405 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
26407 case VSX_BUILTIN_XVSQRTSP:
26408 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
26409 return NULL_TREE;
26411 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
26413 default:
26414 return NULL_TREE;
26417 else
26418 switch (fn)
26420 case BUILT_IN_SQRT:
26421 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
26422 return NULL_TREE;
26424 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
26426 case BUILT_IN_SQRTF:
26427 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
26428 return NULL_TREE;
26430 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
26432 default:
26433 return NULL_TREE;
26437 /* Load up a constant. If the mode is a vector mode, splat the value across
26438 all of the vector elements. */
26440 static rtx
26441 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
26443 rtx reg;
26445 if (mode == SFmode || mode == DFmode)
26447 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
26448 reg = force_reg (mode, d);
26450 else if (mode == V4SFmode)
26452 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
26453 rtvec v = gen_rtvec (4, d, d, d, d);
26454 reg = gen_reg_rtx (mode);
26455 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26457 else if (mode == V2DFmode)
26459 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
26460 rtvec v = gen_rtvec (2, d, d);
26461 reg = gen_reg_rtx (mode);
26462 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
26464 else
26465 gcc_unreachable ();
26467 return reg;
26470 /* Generate an FMA instruction. */
26472 static void
26473 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
26475 enum machine_mode mode = GET_MODE (target);
26476 rtx dst;
26478 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26479 gcc_assert (dst != NULL);
26481 if (dst != target)
26482 emit_move_insn (target, dst);
26485 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
26487 static void
26488 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
26490 enum machine_mode mode = GET_MODE (target);
26491 rtx dst;
26493 /* Altivec does not support fms directly;
26494 generate in terms of fma in that case. */
26495 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
26496 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
26497 else
26499 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
26500 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
26502 gcc_assert (dst != NULL);
26504 if (dst != target)
26505 emit_move_insn (target, dst);
26508 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
26510 static void
26511 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
26513 enum machine_mode mode = GET_MODE (dst);
26514 rtx r;
26516 /* This is a tad more complicated, since the fnma_optab is for
26517 a different expression: fma(-m1, m2, a), which is the same
26518 thing except in the case of signed zeros.
26520 Fortunately we know that if FMA is supported that FNMSUB is
26521 also supported in the ISA. Just expand it directly. */
26523 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
26525 r = gen_rtx_NEG (mode, a);
26526 r = gen_rtx_FMA (mode, m1, m2, r);
26527 r = gen_rtx_NEG (mode, r);
26528 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
26531 /* Newton-Raphson approximation of floating point divide with just 2 passes
26532 (either single precision floating point, or newer machines with higher
26533 accuracy estimates). Support both scalar and vector divide. Assumes no
26534 trapping math and finite arguments. */
26536 static void
26537 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
26539 enum machine_mode mode = GET_MODE (dst);
26540 rtx x0, e0, e1, y1, u0, v0;
26541 enum insn_code code = optab_handler (smul_optab, mode);
26542 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26543 rtx one = rs6000_load_constant_and_splat (mode, dconst1);
26545 gcc_assert (code != CODE_FOR_nothing);
26547 /* x0 = 1./d estimate */
26548 x0 = gen_reg_rtx (mode);
26549 emit_insn (gen_rtx_SET (VOIDmode, x0,
26550 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26551 UNSPEC_FRES)));
26553 e0 = gen_reg_rtx (mode);
26554 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
26556 e1 = gen_reg_rtx (mode);
26557 rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
26559 y1 = gen_reg_rtx (mode);
26560 rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
26562 u0 = gen_reg_rtx (mode);
26563 emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
26565 v0 = gen_reg_rtx (mode);
26566 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
26568 rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
26571 /* Newton-Raphson approximation of floating point divide that has a low
26572 precision estimate. Assumes no trapping math and finite arguments. */
26574 static void
26575 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
26577 enum machine_mode mode = GET_MODE (dst);
26578 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
26579 enum insn_code code = optab_handler (smul_optab, mode);
26580 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26582 gcc_assert (code != CODE_FOR_nothing);
26584 one = rs6000_load_constant_and_splat (mode, dconst1);
26586 /* x0 = 1./d estimate */
26587 x0 = gen_reg_rtx (mode);
26588 emit_insn (gen_rtx_SET (VOIDmode, x0,
26589 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26590 UNSPEC_FRES)));
26592 e0 = gen_reg_rtx (mode);
26593 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
26595 y1 = gen_reg_rtx (mode);
26596 rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
26598 e1 = gen_reg_rtx (mode);
26599 emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
26601 y2 = gen_reg_rtx (mode);
26602 rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
26604 e2 = gen_reg_rtx (mode);
26605 emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
26607 y3 = gen_reg_rtx (mode);
26608 rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
26610 u0 = gen_reg_rtx (mode);
26611 emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
26613 v0 = gen_reg_rtx (mode);
26614 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
26616 rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
26619 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26620 add a reg_note saying that this was a division. Support both scalar and
26621 vector divide. Assumes no trapping math and finite arguments. */
26623 void
26624 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26626 enum machine_mode mode = GET_MODE (dst);
26628 if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26629 rs6000_emit_swdiv_high_precision (dst, n, d);
26630 else
26631 rs6000_emit_swdiv_low_precision (dst, n, d);
26633 if (note_p)
26634 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26637 /* Newton-Raphson approximation of single/double-precision floating point
26638 rsqrt. Assumes no trapping math and finite arguments. */
26640 void
26641 rs6000_emit_swrsqrt (rtx dst, rtx src)
26643 enum machine_mode mode = GET_MODE (src);
26644 rtx x0 = gen_reg_rtx (mode);
26645 rtx y = gen_reg_rtx (mode);
26646 int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26647 REAL_VALUE_TYPE dconst3_2;
26648 int i;
26649 rtx halfthree;
26650 enum insn_code code = optab_handler (smul_optab, mode);
26651 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26653 gcc_assert (code != CODE_FOR_nothing);
26655 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26656 real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26657 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26659 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26661 /* x0 = rsqrt estimate */
26662 emit_insn (gen_rtx_SET (VOIDmode, x0,
26663 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26664 UNSPEC_RSQRT)));
26666 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26667 rs6000_emit_msub (y, src, halfthree, src);
26669 for (i = 0; i < passes; i++)
26671 rtx x1 = gen_reg_rtx (mode);
26672 rtx u = gen_reg_rtx (mode);
26673 rtx v = gen_reg_rtx (mode);
26675 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26676 emit_insn (gen_mul (u, x0, x0));
26677 rs6000_emit_nmsub (v, y, u, halfthree);
26678 emit_insn (gen_mul (x1, x0, v));
26679 x0 = x1;
26682 emit_move_insn (dst, x0);
26683 return;
26686 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26687 (Power7) targets. DST is the target, and SRC is the argument operand. */
26689 void
26690 rs6000_emit_popcount (rtx dst, rtx src)
26692 enum machine_mode mode = GET_MODE (dst);
26693 rtx tmp1, tmp2;
26695 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26696 if (TARGET_POPCNTD)
26698 if (mode == SImode)
26699 emit_insn (gen_popcntdsi2 (dst, src));
26700 else
26701 emit_insn (gen_popcntddi2 (dst, src));
26702 return;
26705 tmp1 = gen_reg_rtx (mode);
26707 if (mode == SImode)
26709 emit_insn (gen_popcntbsi2 (tmp1, src));
26710 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26711 NULL_RTX, 0);
26712 tmp2 = force_reg (SImode, tmp2);
26713 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26715 else
26717 emit_insn (gen_popcntbdi2 (tmp1, src));
26718 tmp2 = expand_mult (DImode, tmp1,
26719 GEN_INT ((HOST_WIDE_INT)
26720 0x01010101 << 32 | 0x01010101),
26721 NULL_RTX, 0);
26722 tmp2 = force_reg (DImode, tmp2);
26723 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26728 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26729 target, and SRC is the argument operand. */
26731 void
26732 rs6000_emit_parity (rtx dst, rtx src)
26734 enum machine_mode mode = GET_MODE (dst);
26735 rtx tmp;
26737 tmp = gen_reg_rtx (mode);
26739 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26740 if (TARGET_CMPB)
26742 if (mode == SImode)
26744 emit_insn (gen_popcntbsi2 (tmp, src));
26745 emit_insn (gen_paritysi2_cmpb (dst, tmp));
26747 else
26749 emit_insn (gen_popcntbdi2 (tmp, src));
26750 emit_insn (gen_paritydi2_cmpb (dst, tmp));
26752 return;
26755 if (mode == SImode)
26757 /* Is mult+shift >= shift+xor+shift+xor? */
26758 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26760 rtx tmp1, tmp2, tmp3, tmp4;
26762 tmp1 = gen_reg_rtx (SImode);
26763 emit_insn (gen_popcntbsi2 (tmp1, src));
26765 tmp2 = gen_reg_rtx (SImode);
26766 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26767 tmp3 = gen_reg_rtx (SImode);
26768 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26770 tmp4 = gen_reg_rtx (SImode);
26771 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26772 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26774 else
26775 rs6000_emit_popcount (tmp, src);
26776 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26778 else
26780 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26781 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26783 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26785 tmp1 = gen_reg_rtx (DImode);
26786 emit_insn (gen_popcntbdi2 (tmp1, src));
26788 tmp2 = gen_reg_rtx (DImode);
26789 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26790 tmp3 = gen_reg_rtx (DImode);
26791 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26793 tmp4 = gen_reg_rtx (DImode);
26794 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26795 tmp5 = gen_reg_rtx (DImode);
26796 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26798 tmp6 = gen_reg_rtx (DImode);
26799 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26800 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26802 else
26803 rs6000_emit_popcount (tmp, src);
26804 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26808 /* Expand an Altivec constant permutation. Return true if we match
26809 an efficient implementation; false to fall back to VPERM. */
26811 bool
26812 altivec_expand_vec_perm_const (rtx operands[4])
26814 struct altivec_perm_insn {
26815 enum insn_code impl;
26816 unsigned char perm[16];
26818 static const struct altivec_perm_insn patterns[] = {
26819 { CODE_FOR_altivec_vpkuhum,
26820 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26821 { CODE_FOR_altivec_vpkuwum,
26822 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26823 { CODE_FOR_altivec_vmrghb,
26824 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26825 { CODE_FOR_altivec_vmrghh,
26826 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26827 { CODE_FOR_altivec_vmrghw,
26828 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26829 { CODE_FOR_altivec_vmrglb,
26830 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26831 { CODE_FOR_altivec_vmrglh,
26832 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26833 { CODE_FOR_altivec_vmrglw,
26834 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26837 unsigned int i, j, elt, which;
26838 unsigned char perm[16];
26839 rtx target, op0, op1, sel, x;
26840 bool one_vec;
26842 target = operands[0];
26843 op0 = operands[1];
26844 op1 = operands[2];
26845 sel = operands[3];
26847 /* Unpack the constant selector. */
26848 for (i = which = 0; i < 16; ++i)
26850 rtx e = XVECEXP (sel, 0, i);
26851 elt = INTVAL (e) & 31;
26852 which |= (elt < 16 ? 1 : 2);
26853 perm[i] = elt;
26856 /* Simplify the constant selector based on operands. */
26857 switch (which)
26859 default:
26860 gcc_unreachable ();
26862 case 3:
26863 one_vec = false;
26864 if (!rtx_equal_p (op0, op1))
26865 break;
26866 /* FALLTHRU */
26868 case 2:
26869 for (i = 0; i < 16; ++i)
26870 perm[i] &= 15;
26871 op0 = op1;
26872 one_vec = true;
26873 break;
26875 case 1:
26876 op1 = op0;
26877 one_vec = true;
26878 break;
26881 /* Look for splat patterns. */
26882 if (one_vec)
26884 elt = perm[0];
26886 for (i = 0; i < 16; ++i)
26887 if (perm[i] != elt)
26888 break;
26889 if (i == 16)
26891 emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
26892 return true;
26895 if (elt % 2 == 0)
26897 for (i = 0; i < 16; i += 2)
26898 if (perm[i] != elt || perm[i + 1] != elt + 1)
26899 break;
26900 if (i == 16)
26902 x = gen_reg_rtx (V8HImode);
26903 emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
26904 GEN_INT (elt / 2)));
26905 emit_move_insn (target, gen_lowpart (V16QImode, x));
26906 return true;
26910 if (elt % 4 == 0)
26912 for (i = 0; i < 16; i += 4)
26913 if (perm[i] != elt
26914 || perm[i + 1] != elt + 1
26915 || perm[i + 2] != elt + 2
26916 || perm[i + 3] != elt + 3)
26917 break;
26918 if (i == 16)
26920 x = gen_reg_rtx (V4SImode);
26921 emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
26922 GEN_INT (elt / 4)));
26923 emit_move_insn (target, gen_lowpart (V16QImode, x));
26924 return true;
26929 /* Look for merge and pack patterns. */
26930 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
26932 bool swapped;
26934 elt = patterns[j].perm[0];
26935 if (perm[0] == elt)
26936 swapped = false;
26937 else if (perm[0] == elt + 16)
26938 swapped = true;
26939 else
26940 continue;
26941 for (i = 1; i < 16; ++i)
26943 elt = patterns[j].perm[i];
26944 if (swapped)
26945 elt = (elt >= 16 ? elt - 16 : elt + 16);
26946 else if (one_vec && elt >= 16)
26947 elt -= 16;
26948 if (perm[i] != elt)
26949 break;
26951 if (i == 16)
26953 enum insn_code icode = patterns[j].impl;
26954 enum machine_mode omode = insn_data[icode].operand[0].mode;
26955 enum machine_mode imode = insn_data[icode].operand[1].mode;
26957 if (swapped)
26958 x = op0, op0 = op1, op1 = x;
26959 if (imode != V16QImode)
26961 op0 = gen_lowpart (imode, op0);
26962 op1 = gen_lowpart (imode, op1);
26964 if (omode == V16QImode)
26965 x = target;
26966 else
26967 x = gen_reg_rtx (omode);
26968 emit_insn (GEN_FCN (icode) (x, op0, op1));
26969 if (omode != V16QImode)
26970 emit_move_insn (target, gen_lowpart (V16QImode, x));
26971 return true;
26975 return false;
26978 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
26979 Return true if we match an efficient implementation. */
26981 static bool
26982 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
26983 unsigned char perm0, unsigned char perm1)
26985 rtx x;
26987 /* If both selectors come from the same operand, fold to single op. */
26988 if ((perm0 & 2) == (perm1 & 2))
26990 if (perm0 & 2)
26991 op0 = op1;
26992 else
26993 op1 = op0;
26995 /* If both operands are equal, fold to simpler permutation. */
26996 if (rtx_equal_p (op0, op1))
26998 perm0 = perm0 & 1;
26999 perm1 = (perm1 & 1) + 2;
27001 /* If the first selector comes from the second operand, swap. */
27002 else if (perm0 & 2)
27004 if (perm1 & 2)
27005 return false;
27006 perm0 -= 2;
27007 perm1 += 2;
27008 x = op0, op0 = op1, op1 = x;
27010 /* If the second selector does not come from the second operand, fail. */
27011 else if ((perm1 & 2) == 0)
27012 return false;
27014 /* Success! */
27015 if (target != NULL)
27017 enum machine_mode vmode, dmode;
27018 rtvec v;
27020 vmode = GET_MODE (target);
27021 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
27022 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
27024 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
27025 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
27026 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
27027 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27029 return true;
27032 bool
27033 rs6000_expand_vec_perm_const (rtx operands[4])
27035 rtx target, op0, op1, sel;
27036 unsigned char perm0, perm1;
27038 target = operands[0];
27039 op0 = operands[1];
27040 op1 = operands[2];
27041 sel = operands[3];
27043 /* Unpack the constant selector. */
27044 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
27045 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
27047 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
27050 /* Test whether a constant permutation is supported. */
27052 static bool
27053 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode,
27054 const unsigned char *sel)
27056 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
27057 if (TARGET_ALTIVEC)
27058 return true;
27060 /* Check for ps_merge* or evmerge* insns. */
27061 if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
27062 || (TARGET_SPE && vmode == V2SImode))
27064 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
27065 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
27066 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
27069 return false;
27072 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
27074 static void
27075 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
27076 enum machine_mode vmode, unsigned nelt, rtx perm[])
27078 enum machine_mode imode;
27079 rtx x;
27081 imode = vmode;
27082 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
27084 imode = GET_MODE_INNER (vmode);
27085 imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
27086 imode = mode_for_vector (imode, nelt);
27089 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
27090 x = expand_vec_perm (vmode, op0, op1, x, target);
27091 if (x != target)
27092 emit_move_insn (target, x);
27095 /* Expand an extract even operation. */
27097 void
27098 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
27100 enum machine_mode vmode = GET_MODE (target);
27101 unsigned i, nelt = GET_MODE_NUNITS (vmode);
27102 rtx perm[16];
27104 for (i = 0; i < nelt; i++)
27105 perm[i] = GEN_INT (i * 2);
27107 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
27110 /* Expand a vector interleave operation. */
27112 void
27113 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
27115 enum machine_mode vmode = GET_MODE (target);
27116 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
27117 rtx perm[16];
27119 high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
27120 for (i = 0; i < nelt / 2; i++)
27122 perm[i * 2] = GEN_INT (i + high);
27123 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
27126 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
27129 /* Return an RTX representing where to find the function value of a
27130 function returning MODE. */
27131 static rtx
27132 rs6000_complex_function_value (enum machine_mode mode)
27134 unsigned int regno;
27135 rtx r1, r2;
27136 enum machine_mode inner = GET_MODE_INNER (mode);
27137 unsigned int inner_bytes = GET_MODE_SIZE (inner);
27139 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27140 regno = FP_ARG_RETURN;
27141 else
27143 regno = GP_ARG_RETURN;
27145 /* 32-bit is OK since it'll go in r3/r4. */
27146 if (TARGET_32BIT && inner_bytes >= 4)
27147 return gen_rtx_REG (mode, regno);
27150 if (inner_bytes >= 8)
27151 return gen_rtx_REG (mode, regno);
27153 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
27154 const0_rtx);
27155 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
27156 GEN_INT (inner_bytes));
27157 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
27160 /* Target hook for TARGET_FUNCTION_VALUE.
27162 On the SPE, both FPs and vectors are returned in r3.
27164 On RS/6000 an integer value is in r3 and a floating-point value is in
27165 fp1, unless -msoft-float. */
27167 static rtx
27168 rs6000_function_value (const_tree valtype,
27169 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
27170 bool outgoing ATTRIBUTE_UNUSED)
27172 enum machine_mode mode;
27173 unsigned int regno;
27175 /* Special handling for structs in darwin64. */
27176 if (TARGET_MACHO
27177 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
27179 CUMULATIVE_ARGS valcum;
27180 rtx valret;
27182 valcum.words = 0;
27183 valcum.fregno = FP_ARG_MIN_REG;
27184 valcum.vregno = ALTIVEC_ARG_MIN_REG;
27185 /* Do a trial code generation as if this were going to be passed as
27186 an argument; if any part goes in memory, we return NULL. */
27187 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
27188 if (valret)
27189 return valret;
27190 /* Otherwise fall through to standard ABI rules. */
27193 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
27195 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
27196 return gen_rtx_PARALLEL (DImode,
27197 gen_rtvec (2,
27198 gen_rtx_EXPR_LIST (VOIDmode,
27199 gen_rtx_REG (SImode, GP_ARG_RETURN),
27200 const0_rtx),
27201 gen_rtx_EXPR_LIST (VOIDmode,
27202 gen_rtx_REG (SImode,
27203 GP_ARG_RETURN + 1),
27204 GEN_INT (4))));
27206 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
27208 return gen_rtx_PARALLEL (DCmode,
27209 gen_rtvec (4,
27210 gen_rtx_EXPR_LIST (VOIDmode,
27211 gen_rtx_REG (SImode, GP_ARG_RETURN),
27212 const0_rtx),
27213 gen_rtx_EXPR_LIST (VOIDmode,
27214 gen_rtx_REG (SImode,
27215 GP_ARG_RETURN + 1),
27216 GEN_INT (4)),
27217 gen_rtx_EXPR_LIST (VOIDmode,
27218 gen_rtx_REG (SImode,
27219 GP_ARG_RETURN + 2),
27220 GEN_INT (8)),
27221 gen_rtx_EXPR_LIST (VOIDmode,
27222 gen_rtx_REG (SImode,
27223 GP_ARG_RETURN + 3),
27224 GEN_INT (12))));
27227 mode = TYPE_MODE (valtype);
27228 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
27229 || (POINTER_TYPE_P (valtype) && !upc_shared_type_p (TREE_TYPE (valtype))))
27230 mode = TARGET_32BIT ? SImode : DImode;
27232 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27233 /* _Decimal128 must use an even/odd register pair. */
27234 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
27235 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
27236 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
27237 regno = FP_ARG_RETURN;
27238 else if (TREE_CODE (valtype) == COMPLEX_TYPE
27239 && targetm.calls.split_complex_arg)
27240 return rs6000_complex_function_value (mode);
27241 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27242 return register is used in both cases, and we won't see V2DImode/V2DFmode
27243 for pure altivec, combine the two cases. */
27244 else if (TREE_CODE (valtype) == VECTOR_TYPE
27245 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
27246 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
27247 regno = ALTIVEC_ARG_RETURN;
27248 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
27249 && (mode == DFmode || mode == DCmode
27250 || mode == TFmode || mode == TCmode))
27251 return spe_build_register_parallel (mode, GP_ARG_RETURN);
27252 else
27253 regno = GP_ARG_RETURN;
27255 return gen_rtx_REG (mode, regno);
27258 /* Define how to find the value returned by a library function
27259 assuming the value has mode MODE. */
27261 rs6000_libcall_value (enum machine_mode mode)
27263 unsigned int regno;
27265 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
27267 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
27268 return gen_rtx_PARALLEL (DImode,
27269 gen_rtvec (2,
27270 gen_rtx_EXPR_LIST (VOIDmode,
27271 gen_rtx_REG (SImode, GP_ARG_RETURN),
27272 const0_rtx),
27273 gen_rtx_EXPR_LIST (VOIDmode,
27274 gen_rtx_REG (SImode,
27275 GP_ARG_RETURN + 1),
27276 GEN_INT (4))));
27279 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
27280 /* _Decimal128 must use an even/odd register pair. */
27281 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
27282 else if (SCALAR_FLOAT_MODE_P (mode)
27283 && TARGET_HARD_FLOAT && TARGET_FPRS
27284 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
27285 regno = FP_ARG_RETURN;
27286 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
27287 return register is used in both cases, and we won't see V2DImode/V2DFmode
27288 for pure altivec, combine the two cases. */
27289 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
27290 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
27291 regno = ALTIVEC_ARG_RETURN;
27292 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
27293 return rs6000_complex_function_value (mode);
27294 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
27295 && (mode == DFmode || mode == DCmode
27296 || mode == TFmode || mode == TCmode))
27297 return spe_build_register_parallel (mode, GP_ARG_RETURN);
27298 else
27299 regno = GP_ARG_RETURN;
27301 return gen_rtx_REG (mode, regno);
27305 /* Given FROM and TO register numbers, say whether this elimination is allowed.
27306 Frame pointer elimination is automatically handled.
27308 For the RS/6000, if frame pointer elimination is being done, we would like
27309 to convert ap into fp, not sp.
27311 We need r30 if -mminimal-toc was specified, and there are constant pool
27312 references. */
27314 static bool
27315 rs6000_can_eliminate (const int from, const int to)
27317 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
27318 ? ! frame_pointer_needed
27319 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
27320 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
27321 : true);
27324 /* Define the offset between two registers, FROM to be eliminated and its
27325 replacement TO, at the start of a routine. */
27326 HOST_WIDE_INT
27327 rs6000_initial_elimination_offset (int from, int to)
27329 rs6000_stack_t *info = rs6000_stack_info ();
27330 HOST_WIDE_INT offset;
27332 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27333 offset = info->push_p ? 0 : -info->total_size;
27334 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27336 offset = info->push_p ? 0 : -info->total_size;
27337 if (FRAME_GROWS_DOWNWARD)
27338 offset += info->fixed_size + info->vars_size + info->parm_size;
27340 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
27341 offset = FRAME_GROWS_DOWNWARD
27342 ? info->fixed_size + info->vars_size + info->parm_size
27343 : 0;
27344 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
27345 offset = info->total_size;
27346 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
27347 offset = info->push_p ? info->total_size : 0;
27348 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
27349 offset = 0;
27350 else
27351 gcc_unreachable ();
27353 return offset;
27356 static rtx
27357 rs6000_dwarf_register_span (rtx reg)
27359 rtx parts[8];
27360 int i, words;
27361 unsigned regno = REGNO (reg);
27362 enum machine_mode mode = GET_MODE (reg);
27364 if (TARGET_SPE
27365 && regno < 32
27366 && (SPE_VECTOR_MODE (GET_MODE (reg))
27367 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
27368 && mode != SFmode && mode != SDmode && mode != SCmode)))
27370 else
27371 return NULL_RTX;
27373 regno = REGNO (reg);
27375 /* The duality of the SPE register size wreaks all kinds of havoc.
27376 This is a way of distinguishing r0 in 32-bits from r0 in
27377 64-bits. */
27378 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
27379 gcc_assert (words <= 4);
27380 for (i = 0; i < words; i++, regno++)
27382 if (BYTES_BIG_ENDIAN)
27384 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
27385 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
27387 else
27389 parts[2 * i] = gen_rtx_REG (SImode, regno);
27390 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
27394 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
27397 /* Fill in sizes for SPE register high parts in table used by unwinder. */
27399 static void
27400 rs6000_init_dwarf_reg_sizes_extra (tree address)
27402 if (TARGET_SPE)
27404 int i;
27405 enum machine_mode mode = TYPE_MODE (char_type_node);
27406 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
27407 rtx mem = gen_rtx_MEM (BLKmode, addr);
27408 rtx value = gen_int_mode (4, mode);
27410 for (i = 1201; i < 1232; i++)
27412 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
27413 HOST_WIDE_INT offset
27414 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
27416 emit_move_insn (adjust_address (mem, mode, offset), value);
27421 /* Map internal gcc register numbers to DWARF2 register numbers. */
27423 unsigned int
27424 rs6000_dbx_register_number (unsigned int regno)
27426 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
27427 return regno;
27428 if (regno == LR_REGNO)
27429 return 108;
27430 if (regno == CTR_REGNO)
27431 return 109;
27432 if (CR_REGNO_P (regno))
27433 return regno - CR0_REGNO + 86;
27434 if (regno == CA_REGNO)
27435 return 101; /* XER */
27436 if (ALTIVEC_REGNO_P (regno))
27437 return regno - FIRST_ALTIVEC_REGNO + 1124;
27438 if (regno == VRSAVE_REGNO)
27439 return 356;
27440 if (regno == VSCR_REGNO)
27441 return 67;
27442 if (regno == SPE_ACC_REGNO)
27443 return 99;
27444 if (regno == SPEFSCR_REGNO)
27445 return 612;
27446 /* SPE high reg number. We get these values of regno from
27447 rs6000_dwarf_register_span. */
27448 gcc_assert (regno >= 1200 && regno < 1232);
27449 return regno;
27452 /* target hook eh_return_filter_mode */
27453 static enum machine_mode
27454 rs6000_eh_return_filter_mode (void)
27456 return TARGET_32BIT ? SImode : word_mode;
27459 /* Target hook for scalar_mode_supported_p. */
27460 static bool
27461 rs6000_scalar_mode_supported_p (enum machine_mode mode)
27463 if (DECIMAL_FLOAT_MODE_P (mode))
27464 return default_decimal_float_supported_p ();
27465 else
27466 return default_scalar_mode_supported_p (mode);
27469 /* Target hook for vector_mode_supported_p. */
27470 static bool
27471 rs6000_vector_mode_supported_p (enum machine_mode mode)
27474 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
27475 return true;
27477 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
27478 return true;
27480 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
27481 return true;
27483 else
27484 return false;
27487 /* Target hook for invalid_arg_for_unprototyped_fn. */
27488 static const char *
27489 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
27491 return (!rs6000_darwin64_abi
27492 && typelist == 0
27493 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
27494 && (funcdecl == NULL_TREE
27495 || (TREE_CODE (funcdecl) == FUNCTION_DECL
27496 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
27497 ? N_("AltiVec argument passed to unprototyped function")
27498 : NULL;
27501 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
27502 setup by using __stack_chk_fail_local hidden function instead of
27503 calling __stack_chk_fail directly. Otherwise it is better to call
27504 __stack_chk_fail directly. */
27506 static tree ATTRIBUTE_UNUSED
27507 rs6000_stack_protect_fail (void)
27509 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
27510 ? default_hidden_stack_protect_fail ()
27511 : default_external_stack_protect_fail ();
27514 void
27515 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
27516 int num_operands ATTRIBUTE_UNUSED)
27518 if (rs6000_warn_cell_microcode)
27520 const char *temp;
27521 int insn_code_number = recog_memoized (insn);
27522 location_t location = INSN_LOCATION (insn);
27524 /* Punt on insns we cannot recognize. */
27525 if (insn_code_number < 0)
27526 return;
27528 temp = get_insn_template (insn_code_number, insn);
27530 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
27531 warning_at (location, OPT_mwarn_cell_microcode,
27532 "emitting microcode insn %s\t[%s] #%d",
27533 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27534 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
27535 warning_at (location, OPT_mwarn_cell_microcode,
27536 "emitting conditional microcode insn %s\t[%s] #%d",
27537 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
27542 /* Mask options that we want to support inside of attribute((target)) and
27543 #pragma GCC target operations. Note, we do not include things like
27544 64/32-bit, endianess, hard/soft floating point, etc. that would have
27545 different calling sequences. */
27547 struct rs6000_opt_mask {
27548 const char *name; /* option name */
27549 HOST_WIDE_INT mask; /* mask to set */
27550 bool invert; /* invert sense of mask */
27551 bool valid_target; /* option is a target option */
27554 static struct rs6000_opt_mask const rs6000_opt_masks[] =
27556 { "altivec", OPTION_MASK_ALTIVEC, false, true },
27557 { "cmpb", OPTION_MASK_CMPB, false, true },
27558 { "dlmzb", OPTION_MASK_DLMZB, false, true },
27559 { "fprnd", OPTION_MASK_FPRND, false, true },
27560 { "hard-dfp", OPTION_MASK_DFP, false, true },
27561 { "isel", OPTION_MASK_ISEL, false, true },
27562 { "mfcrf", OPTION_MASK_MFCRF, false, true },
27563 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
27564 { "mulhw", OPTION_MASK_MULHW, false, true },
27565 { "multiple", OPTION_MASK_MULTIPLE, false, true },
27566 { "update", OPTION_MASK_NO_UPDATE, true , true },
27567 { "popcntb", OPTION_MASK_POPCNTB, false, true },
27568 { "popcntd", OPTION_MASK_POPCNTD, false, true },
27569 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
27570 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
27571 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
27572 { "string", OPTION_MASK_STRING, false, true },
27573 { "vsx", OPTION_MASK_VSX, false, true },
27574 #ifdef OPTION_MASK_64BIT
27575 #if TARGET_AIX_OS
27576 { "aix64", OPTION_MASK_64BIT, false, false },
27577 { "aix32", OPTION_MASK_64BIT, true, false },
27578 #else
27579 { "64", OPTION_MASK_64BIT, false, false },
27580 { "32", OPTION_MASK_64BIT, true, false },
27581 #endif
27582 #endif
27583 #ifdef OPTION_MASK_EABI
27584 { "eabi", OPTION_MASK_EABI, false, false },
27585 #endif
27586 #ifdef OPTION_MASK_LITTLE_ENDIAN
27587 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
27588 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
27589 #endif
27590 #ifdef OPTION_MASK_RELOCATABLE
27591 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
27592 #endif
27593 #ifdef OPTION_MASK_STRICT_ALIGN
27594 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
27595 #endif
27596 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
27597 { "string", OPTION_MASK_STRING, false, false },
27600 /* Builtin mask mapping for printing the flags. */
27601 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
27603 { "altivec", RS6000_BTM_ALTIVEC, false, false },
27604 { "vsx", RS6000_BTM_VSX, false, false },
27605 { "spe", RS6000_BTM_SPE, false, false },
27606 { "paired", RS6000_BTM_PAIRED, false, false },
27607 { "fre", RS6000_BTM_FRE, false, false },
27608 { "fres", RS6000_BTM_FRES, false, false },
27609 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
27610 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
27611 { "popcntd", RS6000_BTM_POPCNTD, false, false },
27612 { "cell", RS6000_BTM_CELL, false, false },
27615 /* Option variables that we want to support inside attribute((target)) and
27616 #pragma GCC target operations. */
27618 struct rs6000_opt_var {
27619 const char *name; /* option name */
27620 size_t global_offset; /* offset of the option in global_options. */
27621 size_t target_offset; /* offset of the option in target optiosn. */
27624 static struct rs6000_opt_var const rs6000_opt_vars[] =
27626 { "friz",
27627 offsetof (struct gcc_options, x_TARGET_FRIZ),
27628 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
27629 { "avoid-indexed-addresses",
27630 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
27631 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
27632 { "paired",
27633 offsetof (struct gcc_options, x_rs6000_paired_float),
27634 offsetof (struct cl_target_option, x_rs6000_paired_float), },
27635 { "longcall",
27636 offsetof (struct gcc_options, x_rs6000_default_long_calls),
27637 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
27640 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27641 parsing. Return true if there were no errors. */
27643 static bool
27644 rs6000_inner_target_options (tree args, bool attr_p)
27646 bool ret = true;
27648 if (args == NULL_TREE)
27651 else if (TREE_CODE (args) == STRING_CST)
27653 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27654 char *q;
27656 while ((q = strtok (p, ",")) != NULL)
27658 bool error_p = false;
27659 bool not_valid_p = false;
27660 const char *cpu_opt = NULL;
27662 p = NULL;
27663 if (strncmp (q, "cpu=", 4) == 0)
27665 int cpu_index = rs6000_cpu_name_lookup (q+4);
27666 if (cpu_index >= 0)
27667 rs6000_cpu_index = cpu_index;
27668 else
27670 error_p = true;
27671 cpu_opt = q+4;
27674 else if (strncmp (q, "tune=", 5) == 0)
27676 int tune_index = rs6000_cpu_name_lookup (q+5);
27677 if (tune_index >= 0)
27678 rs6000_tune_index = tune_index;
27679 else
27681 error_p = true;
27682 cpu_opt = q+5;
27685 else
27687 size_t i;
27688 bool invert = false;
27689 char *r = q;
27691 error_p = true;
27692 if (strncmp (r, "no-", 3) == 0)
27694 invert = true;
27695 r += 3;
27698 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27699 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
27701 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
27703 if (!rs6000_opt_masks[i].valid_target)
27704 not_valid_p = true;
27705 else
27707 error_p = false;
27708 rs6000_isa_flags_explicit |= mask;
27710 /* VSX needs altivec, so -mvsx automagically sets
27711 altivec. */
27712 if (mask == OPTION_MASK_VSX && !invert)
27713 mask |= OPTION_MASK_ALTIVEC;
27715 if (rs6000_opt_masks[i].invert)
27716 invert = !invert;
27718 if (invert)
27719 rs6000_isa_flags &= ~mask;
27720 else
27721 rs6000_isa_flags |= mask;
27723 break;
27726 if (error_p && !not_valid_p)
27728 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27729 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
27731 size_t j = rs6000_opt_vars[i].global_offset;
27732 *((int *) ((char *)&global_options + j)) = !invert;
27733 error_p = false;
27734 break;
27739 if (error_p)
27741 const char *eprefix, *esuffix;
27743 ret = false;
27744 if (attr_p)
27746 eprefix = "__attribute__((__target__(";
27747 esuffix = ")))";
27749 else
27751 eprefix = "#pragma GCC target ";
27752 esuffix = "";
27755 if (cpu_opt)
27756 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
27757 q, esuffix);
27758 else if (not_valid_p)
27759 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
27760 else
27761 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
27766 else if (TREE_CODE (args) == TREE_LIST)
27770 tree value = TREE_VALUE (args);
27771 if (value)
27773 bool ret2 = rs6000_inner_target_options (value, attr_p);
27774 if (!ret2)
27775 ret = false;
27777 args = TREE_CHAIN (args);
27779 while (args != NULL_TREE);
27782 else
27783 gcc_unreachable ();
27785 return ret;
27788 /* Print out the target options as a list for -mdebug=target. */
27790 static void
27791 rs6000_debug_target_options (tree args, const char *prefix)
27793 if (args == NULL_TREE)
27794 fprintf (stderr, "%s<NULL>", prefix);
27796 else if (TREE_CODE (args) == STRING_CST)
27798 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27799 char *q;
27801 while ((q = strtok (p, ",")) != NULL)
27803 p = NULL;
27804 fprintf (stderr, "%s\"%s\"", prefix, q);
27805 prefix = ", ";
27809 else if (TREE_CODE (args) == TREE_LIST)
27813 tree value = TREE_VALUE (args);
27814 if (value)
27816 rs6000_debug_target_options (value, prefix);
27817 prefix = ", ";
27819 args = TREE_CHAIN (args);
27821 while (args != NULL_TREE);
27824 else
27825 gcc_unreachable ();
27827 return;
27831 /* Hook to validate attribute((target("..."))). */
27833 static bool
27834 rs6000_valid_attribute_p (tree fndecl,
27835 tree ARG_UNUSED (name),
27836 tree args,
27837 int flags)
27839 struct cl_target_option cur_target;
27840 bool ret;
27841 tree old_optimize = build_optimization_node ();
27842 tree new_target, new_optimize;
27843 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27845 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
27847 if (TARGET_DEBUG_TARGET)
27849 tree tname = DECL_NAME (fndecl);
27850 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
27851 if (tname)
27852 fprintf (stderr, "function: %.*s\n",
27853 (int) IDENTIFIER_LENGTH (tname),
27854 IDENTIFIER_POINTER (tname));
27855 else
27856 fprintf (stderr, "function: unknown\n");
27858 fprintf (stderr, "args:");
27859 rs6000_debug_target_options (args, " ");
27860 fprintf (stderr, "\n");
27862 if (flags)
27863 fprintf (stderr, "flags: 0x%x\n", flags);
27865 fprintf (stderr, "--------------------\n");
27868 old_optimize = build_optimization_node ();
27869 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27871 /* If the function changed the optimization levels as well as setting target
27872 options, start with the optimizations specified. */
27873 if (func_optimize && func_optimize != old_optimize)
27874 cl_optimization_restore (&global_options,
27875 TREE_OPTIMIZATION (func_optimize));
27877 /* The target attributes may also change some optimization flags, so update
27878 the optimization options if necessary. */
27879 cl_target_option_save (&cur_target, &global_options);
27880 rs6000_cpu_index = rs6000_tune_index = -1;
27881 ret = rs6000_inner_target_options (args, true);
27883 /* Set up any additional state. */
27884 if (ret)
27886 ret = rs6000_option_override_internal (false);
27887 new_target = build_target_option_node ();
27889 else
27890 new_target = NULL;
27892 new_optimize = build_optimization_node ();
27894 if (!new_target)
27895 ret = false;
27897 else if (fndecl)
27899 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
27901 if (old_optimize != new_optimize)
27902 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
27905 cl_target_option_restore (&global_options, &cur_target);
27907 if (old_optimize != new_optimize)
27908 cl_optimization_restore (&global_options,
27909 TREE_OPTIMIZATION (old_optimize));
27911 return ret;
27915 /* Hook to validate the current #pragma GCC target and set the state, and
27916 update the macros based on what was changed. If ARGS is NULL, then
27917 POP_TARGET is used to reset the options. */
27919 bool
27920 rs6000_pragma_target_parse (tree args, tree pop_target)
27922 tree prev_tree = build_target_option_node ();
27923 tree cur_tree;
27924 struct cl_target_option *prev_opt, *cur_opt;
27925 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
27926 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
27928 if (TARGET_DEBUG_TARGET)
27930 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
27931 fprintf (stderr, "args:");
27932 rs6000_debug_target_options (args, " ");
27933 fprintf (stderr, "\n");
27935 if (pop_target)
27937 fprintf (stderr, "pop_target:\n");
27938 debug_tree (pop_target);
27940 else
27941 fprintf (stderr, "pop_target: <NULL>\n");
27943 fprintf (stderr, "--------------------\n");
27946 if (! args)
27948 cur_tree = ((pop_target)
27949 ? pop_target
27950 : target_option_default_node);
27951 cl_target_option_restore (&global_options,
27952 TREE_TARGET_OPTION (cur_tree));
27954 else
27956 rs6000_cpu_index = rs6000_tune_index = -1;
27957 if (!rs6000_inner_target_options (args, false)
27958 || !rs6000_option_override_internal (false)
27959 || (cur_tree = build_target_option_node ()) == NULL_TREE)
27961 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
27962 fprintf (stderr, "invalid pragma\n");
27964 return false;
27968 target_option_current_node = cur_tree;
27970 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27971 change the macros that are defined. */
27972 if (rs6000_target_modify_macros_ptr)
27974 prev_opt = TREE_TARGET_OPTION (prev_tree);
27975 prev_bumask = prev_opt->x_rs6000_builtin_mask;
27976 prev_flags = prev_opt->x_rs6000_isa_flags;
27978 cur_opt = TREE_TARGET_OPTION (cur_tree);
27979 cur_flags = cur_opt->x_rs6000_isa_flags;
27980 cur_bumask = cur_opt->x_rs6000_builtin_mask;
27982 diff_bumask = (prev_bumask ^ cur_bumask);
27983 diff_flags = (prev_flags ^ cur_flags);
27985 if ((diff_flags != 0) || (diff_bumask != 0))
27987 /* Delete old macros. */
27988 rs6000_target_modify_macros_ptr (false,
27989 prev_flags & diff_flags,
27990 prev_bumask & diff_bumask);
27992 /* Define new macros. */
27993 rs6000_target_modify_macros_ptr (true,
27994 cur_flags & diff_flags,
27995 cur_bumask & diff_bumask);
27999 return true;
28003 /* Remember the last target of rs6000_set_current_function. */
28004 static GTY(()) tree rs6000_previous_fndecl;
28006 /* Establish appropriate back-end context for processing the function
28007 FNDECL. The argument might be NULL to indicate processing at top
28008 level, outside of any function scope. */
28009 static void
28010 rs6000_set_current_function (tree fndecl)
28012 tree old_tree = (rs6000_previous_fndecl
28013 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
28014 : NULL_TREE);
28016 tree new_tree = (fndecl
28017 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
28018 : NULL_TREE);
28020 if (TARGET_DEBUG_TARGET)
28022 bool print_final = false;
28023 fprintf (stderr, "\n==================== rs6000_set_current_function");
28025 if (fndecl)
28026 fprintf (stderr, ", fndecl %s (%p)",
28027 (DECL_NAME (fndecl)
28028 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
28029 : "<unknown>"), (void *)fndecl);
28031 if (rs6000_previous_fndecl)
28032 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
28034 fprintf (stderr, "\n");
28035 if (new_tree)
28037 fprintf (stderr, "\nnew fndecl target specific options:\n");
28038 debug_tree (new_tree);
28039 print_final = true;
28042 if (old_tree)
28044 fprintf (stderr, "\nold fndecl target specific options:\n");
28045 debug_tree (old_tree);
28046 print_final = true;
28049 if (print_final)
28050 fprintf (stderr, "--------------------\n");
28053 /* Only change the context if the function changes. This hook is called
28054 several times in the course of compiling a function, and we don't want to
28055 slow things down too much or call target_reinit when it isn't safe. */
28056 if (fndecl && fndecl != rs6000_previous_fndecl)
28058 rs6000_previous_fndecl = fndecl;
28059 if (old_tree == new_tree)
28062 else if (new_tree)
28064 cl_target_option_restore (&global_options,
28065 TREE_TARGET_OPTION (new_tree));
28066 target_reinit ();
28069 else if (old_tree)
28071 struct cl_target_option *def
28072 = TREE_TARGET_OPTION (target_option_current_node);
28074 cl_target_option_restore (&global_options, def);
28075 target_reinit ();
28081 /* Save the current options */
28083 static void
28084 rs6000_function_specific_save (struct cl_target_option *ptr)
28086 ptr->x_rs6000_isa_flags = rs6000_isa_flags;
28087 ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit;
28090 /* Restore the current options */
28092 static void
28093 rs6000_function_specific_restore (struct cl_target_option *ptr)
28095 rs6000_isa_flags = ptr->x_rs6000_isa_flags;
28096 rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
28097 (void) rs6000_option_override_internal (false);
28100 /* Print the current options */
28102 static void
28103 rs6000_function_specific_print (FILE *file, int indent,
28104 struct cl_target_option *ptr)
28106 rs6000_print_isa_options (file, indent, "Isa options set",
28107 ptr->x_rs6000_isa_flags);
28109 rs6000_print_isa_options (file, indent, "Isa options explicit",
28110 ptr->x_rs6000_isa_flags_explicit);
28113 /* Helper function to print the current isa or misc options on a line. */
28115 static void
28116 rs6000_print_options_internal (FILE *file,
28117 int indent,
28118 const char *string,
28119 HOST_WIDE_INT flags,
28120 const char *prefix,
28121 const struct rs6000_opt_mask *opts,
28122 size_t num_elements)
28124 size_t i;
28125 size_t start_column = 0;
28126 size_t cur_column;
28127 size_t max_column = 76;
28128 const char *comma = "";
28129 const char *nl = "\n";
28131 if (indent)
28132 start_column += fprintf (file, "%*s", indent, "");
28134 if (!flags)
28136 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
28137 return;
28140 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
28142 /* Print the various mask options. */
28143 cur_column = start_column;
28144 for (i = 0; i < num_elements; i++)
28146 if ((flags & opts[i].mask) != 0)
28148 const char *no_str = rs6000_opt_masks[i].invert ? "no-" : "";
28149 size_t len = (strlen (comma)
28150 + strlen (prefix)
28151 + strlen (no_str)
28152 + strlen (rs6000_opt_masks[i].name));
28154 cur_column += len;
28155 if (cur_column > max_column)
28157 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
28158 cur_column = start_column + len;
28159 comma = "";
28160 nl = "\n\n";
28163 fprintf (file, "%s%s%s%s", comma, prefix, no_str,
28164 rs6000_opt_masks[i].name);
28165 flags &= ~ opts[i].mask;
28166 comma = ", ";
28170 fputs (nl, file);
28173 /* Helper function to print the current isa options on a line. */
28175 static void
28176 rs6000_print_isa_options (FILE *file, int indent, const char *string,
28177 HOST_WIDE_INT flags)
28179 rs6000_print_options_internal (file, indent, string, flags, "-m",
28180 &rs6000_opt_masks[0],
28181 ARRAY_SIZE (rs6000_opt_masks));
28184 static void
28185 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
28186 HOST_WIDE_INT flags)
28188 rs6000_print_options_internal (file, indent, string, flags, "",
28189 &rs6000_builtin_mask_names[0],
28190 ARRAY_SIZE (rs6000_builtin_mask_names));
28194 /* Hook to determine if one function can safely inline another. */
28196 static bool
28197 rs6000_can_inline_p (tree caller, tree callee)
28199 bool ret = false;
28200 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
28201 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
28203 /* If callee has no option attributes, then it is ok to inline. */
28204 if (!callee_tree)
28205 ret = true;
28207 /* If caller has no option attributes, but callee does then it is not ok to
28208 inline. */
28209 else if (!caller_tree)
28210 ret = false;
28212 else
28214 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
28215 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
28217 /* Callee's options should a subset of the caller's, i.e. a vsx function
28218 can inline an altivec function but a non-vsx function can't inline a
28219 vsx function. */
28220 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
28221 == callee_opts->x_rs6000_isa_flags)
28222 ret = true;
28225 if (TARGET_DEBUG_TARGET)
28226 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
28227 (DECL_NAME (caller)
28228 ? IDENTIFIER_POINTER (DECL_NAME (caller))
28229 : "<unknown>"),
28230 (DECL_NAME (callee)
28231 ? IDENTIFIER_POINTER (DECL_NAME (callee))
28232 : "<unknown>"),
28233 (ret ? "can" : "cannot"));
28235 return ret;
28238 /* Allocate a stack temp and fixup the address so it meets the particular
28239 memory requirements (either offetable or REG+REG addressing). */
28242 rs6000_allocate_stack_temp (enum machine_mode mode,
28243 bool offsettable_p,
28244 bool reg_reg_p)
28246 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
28247 rtx addr = XEXP (stack, 0);
28248 int strict_p = (reload_in_progress || reload_completed);
28250 if (!legitimate_indirect_address_p (addr, strict_p))
28252 if (offsettable_p
28253 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
28254 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
28256 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
28257 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
28260 return stack;
28263 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
28264 to such a form to deal with memory reference instructions like STFIWX that
28265 only take reg+reg addressing. */
28268 rs6000_address_for_fpconvert (rtx x)
28270 int strict_p = (reload_in_progress || reload_completed);
28271 rtx addr;
28273 gcc_assert (MEM_P (x));
28274 addr = XEXP (x, 0);
28275 if (! legitimate_indirect_address_p (addr, strict_p)
28276 && ! legitimate_indexed_address_p (addr, strict_p))
28278 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
28280 rtx reg = XEXP (addr, 0);
28281 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
28282 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
28283 gcc_assert (REG_P (reg));
28284 emit_insn (gen_add3_insn (reg, reg, size_rtx));
28285 addr = reg;
28287 else if (GET_CODE (addr) == PRE_MODIFY)
28289 rtx reg = XEXP (addr, 0);
28290 rtx expr = XEXP (addr, 1);
28291 gcc_assert (REG_P (reg));
28292 gcc_assert (GET_CODE (expr) == PLUS);
28293 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
28294 addr = reg;
28297 x = replace_equiv_address (x, copy_addr_to_reg (addr));
28300 return x;
28303 /* Given a memory reference, if it is not in the form for altivec memory
28304 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
28305 convert to the altivec format. */
28308 rs6000_address_for_altivec (rtx x)
28310 gcc_assert (MEM_P (x));
28311 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
28313 rtx addr = XEXP (x, 0);
28314 int strict_p = (reload_in_progress || reload_completed);
28316 if (!legitimate_indexed_address_p (addr, strict_p)
28317 && !legitimate_indirect_address_p (addr, strict_p))
28318 addr = copy_to_mode_reg (Pmode, addr);
28320 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
28321 x = change_address (x, GET_MODE (x), addr);
28324 return x;
28327 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
28329 On the RS/6000, all integer constants are acceptable, most won't be valid
28330 for particular insns, though. Only easy FP constants are acceptable. */
28332 static bool
28333 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
28335 if (TARGET_ELF && rs6000_tls_referenced_p (x))
28336 return false;
28338 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
28339 || GET_MODE (x) == VOIDmode
28340 || (TARGET_POWERPC64 && mode == DImode)
28341 || easy_fp_constant (x, mode)
28342 || easy_vector_constant (x, mode));
28346 /* A function pointer under AIX is a pointer to a data area whose first word
28347 contains the actual address of the function, whose second word contains a
28348 pointer to its TOC, and whose third word contains a value to place in the
28349 static chain register (r11). Note that if we load the static chain, our
28350 "trampoline" need not have any executable code. */
28352 void
28353 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
28355 rtx func_addr;
28356 rtx toc_reg;
28357 rtx sc_reg;
28358 rtx stack_ptr;
28359 rtx stack_toc_offset;
28360 rtx stack_toc_mem;
28361 rtx func_toc_offset;
28362 rtx func_toc_mem;
28363 rtx func_sc_offset;
28364 rtx func_sc_mem;
28365 rtx insn;
28366 rtx (*call_func) (rtx, rtx, rtx, rtx);
28367 rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
28369 stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
28370 toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
28372 /* Load up address of the actual function. */
28373 func_desc = force_reg (Pmode, func_desc);
28374 func_addr = gen_reg_rtx (Pmode);
28375 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
28377 if (TARGET_32BIT)
28380 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
28381 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
28382 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
28383 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28385 call_func = gen_call_indirect_aix32bit;
28386 call_value_func = gen_call_value_indirect_aix32bit;
28388 else
28390 call_func = gen_call_indirect_aix32bit_nor11;
28391 call_value_func = gen_call_value_indirect_aix32bit_nor11;
28394 else
28396 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
28397 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
28398 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
28399 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28401 call_func = gen_call_indirect_aix64bit;
28402 call_value_func = gen_call_value_indirect_aix64bit;
28404 else
28406 call_func = gen_call_indirect_aix64bit_nor11;
28407 call_value_func = gen_call_value_indirect_aix64bit_nor11;
28411 /* Reserved spot to store the TOC. */
28412 stack_toc_mem = gen_frame_mem (Pmode,
28413 gen_rtx_PLUS (Pmode,
28414 stack_ptr,
28415 stack_toc_offset));
28417 gcc_assert (cfun);
28418 gcc_assert (cfun->machine);
28420 /* Can we optimize saving the TOC in the prologue or do we need to do it at
28421 every call? */
28422 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
28423 cfun->machine->save_toc_in_prologue = true;
28425 else
28427 MEM_VOLATILE_P (stack_toc_mem) = 1;
28428 emit_move_insn (stack_toc_mem, toc_reg);
28431 /* Calculate the address to load the TOC of the called function. We don't
28432 actually load this until the split after reload. */
28433 func_toc_mem = gen_rtx_MEM (Pmode,
28434 gen_rtx_PLUS (Pmode,
28435 func_desc,
28436 func_toc_offset));
28438 /* If we have a static chain, load it up. */
28439 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28441 func_sc_mem = gen_rtx_MEM (Pmode,
28442 gen_rtx_PLUS (Pmode,
28443 func_desc,
28444 func_sc_offset));
28446 sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
28447 emit_move_insn (sc_reg, func_sc_mem);
28450 /* Create the call. */
28451 if (value)
28452 insn = call_value_func (value, func_addr, flag, func_toc_mem,
28453 stack_toc_mem);
28454 else
28455 insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
28457 emit_call_insn (insn);
28460 /* Return whether we need to always update the saved TOC pointer when we update
28461 the stack pointer. */
28463 static bool
28464 rs6000_save_toc_in_prologue_p (void)
28466 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
28469 #ifdef HAVE_GAS_HIDDEN
28470 # define USE_HIDDEN_LINKONCE 1
28471 #else
28472 # define USE_HIDDEN_LINKONCE 0
28473 #endif
28475 /* Fills in the label name that should be used for a 476 link stack thunk. */
28477 void
28478 get_ppc476_thunk_name (char name[32])
28480 gcc_assert (TARGET_LINK_STACK);
28482 if (USE_HIDDEN_LINKONCE)
28483 sprintf (name, "__ppc476.get_thunk");
28484 else
28485 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
28488 /* This function emits the simple thunk routine that is used to preserve
28489 the link stack on the 476 cpu. */
28491 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
28492 static void
28493 rs6000_code_end (void)
28495 char name[32];
28496 tree decl;
28498 if (!TARGET_LINK_STACK)
28499 return;
28501 get_ppc476_thunk_name (name);
28503 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
28504 build_function_type_list (void_type_node, NULL_TREE));
28505 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
28506 NULL_TREE, void_type_node);
28507 TREE_PUBLIC (decl) = 1;
28508 TREE_STATIC (decl) = 1;
28510 #if RS6000_WEAK
28511 if (USE_HIDDEN_LINKONCE)
28513 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
28514 targetm.asm_out.unique_section (decl, 0);
28515 switch_to_section (get_named_section (decl, NULL, 0));
28516 DECL_WEAK (decl) = 1;
28517 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
28518 targetm.asm_out.globalize_label (asm_out_file, name);
28519 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
28520 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
28522 else
28523 #endif
28525 switch_to_section (text_section);
28526 ASM_OUTPUT_LABEL (asm_out_file, name);
28529 DECL_INITIAL (decl) = make_node (BLOCK);
28530 current_function_decl = decl;
28531 init_function_start (decl);
28532 first_function_block_is_cold = false;
28533 /* Make sure unwind info is emitted for the thunk if needed. */
28534 final_start_function (emit_barrier (), asm_out_file, 1);
28536 fputs ("\tblr\n", asm_out_file);
28538 final_end_function ();
28539 init_insn_lengths ();
28540 free_after_compilation (cfun);
28541 set_cfun (NULL);
28542 current_function_decl = NULL;
28545 /* Add r30 to hard reg set if the prologue sets it up and it is not
28546 pic_offset_table_rtx. */
28548 static void
28549 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
28551 if (!TARGET_SINGLE_PIC_BASE
28552 && TARGET_TOC
28553 && TARGET_MINIMAL_TOC
28554 && get_pool_size () != 0)
28555 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
28558 struct gcc_target targetm = TARGET_INITIALIZER;
28560 #include "gt-rs6000.h"