1 ; Options for the SH port of the compiler.
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5 ; This file is part of GCC.
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21 ;; Used for various architecture options.
24 ;; Set if the default precision of the FPU is single.
27 ;; Set if the a double-precision FPU is present but is restricted to
28 ;; single precision usage only.
31 ;; Set if we should generate code using type 2A insns.
34 ;; Set if we should generate code using type 2A DF insns.
35 Mask(HARD_SH2A_DOUBLE)
37 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
41 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
45 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
49 Target RejectNegative Condition(SUPPORT_SH2A)
50 Generate default double-precision SH2a-FPU code.
53 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
54 Generate SH2a FPU-less code.
57 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
58 Generate default single-precision SH2a-FPU code.
61 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
62 Generate only single-precision SH2a-FPU code.
65 Target RejectNegative Condition(SUPPORT_SH2E)
69 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
73 Target RejectNegative Condition(SUPPORT_SH3E)
77 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
81 Target RejectNegative Condition(SUPPORT_SH4)
82 Generate SH4-100 code.
85 Target RejectNegative Condition(SUPPORT_SH4)
86 Generate SH4-200 code.
88 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
89 ;; pipeline - irrespective of ABI.
91 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
92 Generate SH4-300 code.
95 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
96 Generate SH4 FPU-less code.
99 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
100 Generate SH4-100 FPU-less code.
103 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
104 Generate SH4-200 FPU-less code.
107 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300)
108 Generate SH4-300 FPU-less code.
111 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300)
112 Generate code for SH4 340 series (MMU/FPU-less).
113 ;; passes -isa=sh4-nommu-nofpu to the assembler.
116 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
117 Generate code for SH4 400 series (MMU/FPU-less).
118 ;; passes -isa=sh4-nommu-nofpu to the assembler.
121 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
122 Generate code for SH4 500 series (FPU-less).
123 ;; passes -isa=sh4-nofpu to the assembler.
126 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
127 Generate default single-precision SH4 code.
130 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
131 Generate default single-precision SH4-100 code.
134 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
135 Generate default single-precision SH4-200 code.
138 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300)
139 Generate default single-precision SH4-300 code.
142 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
143 Generate only single-precision SH4 code.
146 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
147 Generate only single-precision SH4-100 code.
150 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
151 Generate only single-precision SH4-200 code.
154 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300)
155 Generate only single-precision SH4-300 code.
158 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
162 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
163 Generate SH4a FPU-less code.
166 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
167 Generate default single-precision SH4a code.
170 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
171 Generate only single-precision SH4a code.
174 Target RejectNegative Condition(SUPPORT_SH4AL)
175 Generate SH4al-dsp code.
177 maccumulate-outgoing-args
178 Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1)
179 Reserve space for outgoing arguments in the function prologue.
182 Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
183 Generate code in big endian mode.
186 Target Report RejectNegative Mask(BIGTABLE)
187 Generate 32-bit offsets in switch tables.
190 Target Report RejectNegative Mask(BITOPS)
191 Generate bit instructions.
194 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
195 Cost to assume for a branch insn.
198 Target Report Var(TARGET_ZDCBRANCH)
199 Assume that zero displacement conditional branches are fast.
201 mcbranch-force-delay-slot
202 Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0)
203 Force the usage of delay slots for conditional branches.
206 Target Report RejectNegative Mask(ALIGN_DOUBLE)
207 Align doubles at 64-bit boundaries.
210 Target RejectNegative Joined Var(sh_div_str) Init("")
211 Division strategy, one of: call-div1, call-fp, call-table.
214 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
215 Specify name for 32 bit signed division function.
218 Target Report Var(TARGET_FDPIC) Init(0)
219 Generate ELF FDPIC code.
222 Target RejectNegative Mask(FMOVD)
223 Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
226 Target RejectNegative Joined Var(sh_fixed_range_str)
227 Specify range of registers to make fixed.
230 Target Report RejectNegative Mask(HITACHI)
231 Follow Renesas (formerly Hitachi) / SuperH calling conventions.
234 Target Var(TARGET_IEEE)
235 Increase the IEEE compliance for floating-point comparisons.
237 minline-ic_invalidate
238 Target Report Var(TARGET_INLINE_IC_INVALIDATE)
239 inline code to invalidate instruction cache entries after setting up nested function trampolines.
242 Target Report RejectNegative Mask(DUMPISIZE)
243 Annotate assembler instructions with estimated addresses.
246 Target Report RejectNegative Mask(LITTLE_ENDIAN)
247 Generate code in little endian mode.
250 Target Report RejectNegative Mask(NOMACSAVE)
251 Mark MAC register as call-clobbered.
253 ;; ??? This option is not useful, but is retained in case there are people
254 ;; who are still relying on it. It may be deleted in the future.
256 Target Report RejectNegative Mask(PADSTRUCT)
257 Make structs a multiple of 4 bytes (warning: ABI altered).
260 Target Report RejectNegative Mask(PREFERGOT)
261 Emit function-calls using global offset table when generating PIC.
264 Target Report RejectNegative Mask(RELAX)
265 Shorten address references during linking.
269 Follow Renesas (formerly Hitachi) / SuperH calling conventions.
272 Target Report RejectNegative Joined Var(sh_atomic_model_str)
273 Specify the model for atomic operations.
276 Target Report RejectNegative Var(TARGET_ENABLE_TAS)
277 Use tas.b instruction for __atomic_test_and_set.
280 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
281 Cost to assume for a multiply insn.
284 Target Var(TARGET_USERMODE)
285 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
287 ;; We might want to enable this by default for TARGET_HARD_SH4, because
288 ;; zero-offset branches have zero latency. Needs some benchmarking.
290 Target Var(TARGET_PRETEND_CMOVE)
291 Pretend a branch-around-a-move is a conditional move.
294 Target Var(TARGET_FSCA)
295 Enable the use of the fsca instruction.
298 Target Var(TARGET_FSRRA)
299 Enable the use of the fsrra instruction.
302 Target Report Var(sh_lra_flag) Init(0) Save
303 Use LRA instead of reload (transitional).