| blob | 5a2ad7e9156a6f0389c09470cf1414bff45d8099 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
70 /* This file should be included last. */
73 /* Defined for convenience. */
74 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
76 /* Classifies an address.
78 ADDRESS_REG_IMM
79 A simple base register plus immediate offset.
81 ADDRESS_REG_WB
82 A base register indexed by immediate offset with writeback.
84 ADDRESS_REG_REG
85 A base register indexed by (optionally scaled) register.
87 ADDRESS_REG_UXTW
88 A base register indexed by (optionally scaled) zero-extended register.
90 ADDRESS_REG_SXTW
91 A base register indexed by (optionally scaled) sign-extended register.
93 ADDRESS_LO_SUM
94 A LO_SUM rtx with a base register and "LO12" symbol relocation.
96 ADDRESS_SYMBOLIC:
97 A constant symbolic address, in pc-relative literal pool. */
100 ADDRESS_REG_IMM,
101 ADDRESS_REG_WB,
102 ADDRESS_REG_REG,
103 ADDRESS_REG_UXTW,
104 ADDRESS_REG_SXTW,
105 ADDRESS_LO_SUM,
106 ADDRESS_SYMBOLIC
107 };
111 rtx base;
112 rtx offset;
115 };
117 struct simd_immediate_info
118 {
119 rtx value;
124 };
126 /* The current code model. */
129 #ifdef HAVE_AS_TLS
130 #undef TARGET_HAVE_TLS
131 #define TARGET_HAVE_TLS 1
132 #endif
136 const_tree,
147 const_tree type,
150 static machine_mode
153 /* Major revision number of the ARM Architecture implemented by the target. */
156 /* The processor for which instructions should be scheduled. */
159 /* Mask to specify which instruction scheduling options should be used. */
162 /* Global flag for PC relative loads. */
165 /* Support for command line parsing of boolean flags in the tuning
166 structures. */
167 struct aarch64_flag_desc
168 {
171 };
173 #define AARCH64_FUSION_PAIR(name, internal_name) \
174 { name, AARCH64_FUSE_##internal_name },
176 {
181 };
183 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
184 { name, AARCH64_EXTRA_TUNE_##internal_name },
186 {
191 };
193 /* Tuning parameters. */
196 {
197 {
202 },
209 };
212 {
213 {
218 },
225 };
228 {
229 {
234 },
241 };
244 {
245 {
250 },
257 };
260 {
262 /* Avoid the use of slow int<->fp moves for spilling by setting
263 their cost higher than memmov_cost. */
267 };
270 {
272 /* Avoid the use of slow int<->fp moves for spilling by setting
273 their cost higher than memmov_cost. */
277 };
280 {
282 /* Avoid the use of slow int<->fp moves for spilling by setting
283 their cost higher than memmov_cost. */
287 };
290 {
292 /* Avoid the use of slow int<->fp moves for spilling by setting
293 their cost higher than memmov_cost (actual, 4 and 9). */
297 };
300 {
305 };
308 {
310 /* Avoid the use of slow int<->fp moves for spilling by setting
311 their cost higher than memmov_cost. */
315 };
318 {
320 /* Avoid the use of int<->fp moves for spilling. */
324 };
327 {
329 /* Avoid the use of int<->fp moves for spilling. */
333 };
335 /* Generic costs for vector insn classes. */
337 {
353 };
355 /* ThunderX costs for vector insn classes. */
357 {
373 };
375 /* Generic costs for vector insn classes. */
377 {
393 };
396 {
412 };
414 /* Generic costs for vector insn classes. */
416 {
432 };
434 /* Costs for vector insn classes for Vulcan. */
436 {
452 };
454 /* Generic costs for branch instructions. */
456 {
459 };
461 /* Generic approximation modes. */
463 {
466 AARCH64_APPROX_NONE /* recip_sqrt */
467 };
469 /* Approximation modes for Exynos M1. */
471 {
474 AARCH64_APPROX_ALL /* recip_sqrt */
475 };
477 /* Approximation modes for X-Gene 1. */
479 {
482 AARCH64_APPROX_ALL /* recip_sqrt */
483 };
485 /* Generic prefetch settings (which disable prefetch). */
487 {
493 };
496 {
502 };
505 {
511 };
514 {
520 };
523 {
529 };
532 {
538 };
541 {
562 &generic_prefetch_tune
563 };
566 {
588 &generic_prefetch_tune
589 };
592 {
614 &generic_prefetch_tune
615 };
618 {
640 &generic_prefetch_tune
641 };
644 {
666 &generic_prefetch_tune
667 };
670 {
692 &generic_prefetch_tune
693 };
698 {
719 &exynosm1_prefetch_tune
720 };
723 {
744 &thunderxt88_prefetch_tune
745 };
748 {
768 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
770 &thunderx_prefetch_tune
771 };
774 {
795 &generic_prefetch_tune
796 };
799 {
821 &qdf24xx_prefetch_tune
822 };
825 {
847 &thunderx2t99_prefetch_tune
848 };
850 /* Support for fine-grained override of the tuning structures. */
851 struct aarch64_tuning_override_function
852 {
855 };
860 static const struct aarch64_tuning_override_function
861 aarch64_tuning_override_functions[] =
862 {
866 };
868 /* A processor implementing AArch64. */
869 struct processor
870 {
878 };
880 /* Architectures implementing AArch64. */
882 {
883 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
884 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
887 };
889 /* Processor cores implementing AArch64. */
891 {
892 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
893 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
894 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
895 FLAGS, &COSTS##_tunings},
900 };
903 /* Target specification. These are populated by the -march, -mtune, -mcpu
904 handling code or by target attributes. */
909 /* The current tuning set. */
912 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
914 /* An ISA extension in the co-processor and main instruction set space. */
915 struct aarch64_option_extension
916 {
920 };
923 {
927 }
928 aarch64_cc;
930 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
932 /* The condition codes of the processor, and the inverse function. */
934 {
937 };
939 /* Generate code to enable conditional branches in functions over 1 MiB. */
943 {
960 }
962 void
964 {
968 else
970 }
972 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
973 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
974 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
975 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
976 cost (in this case the best class is the lowest cost one). Using ALL_REGS
977 irrespectively of its cost results in bad allocations with many redundant
978 int<->FP moves which are expensive on various cores.
979 To avoid this we don't allow ALL_REGS as the allocno class, but force a
980 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
981 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
982 Otherwise set the allocno class depending on the mode.
983 The result of this is that it is no longer inefficient to have a higher
984 memory move cost than the register move cost.
985 */
987 static reg_class_t
989 reg_class_t best_class)
990 {
991 machine_mode mode;
1001 }
1003 static unsigned int
1005 {
1009 }
1011 static int
1013 machine_mode mode)
1014 {
1022 }
1024 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1025 unsigned
1027 {
1035 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1036 equivalent DWARF register. */
1038 }
1040 /* Return TRUE if MODE is any of the large INT modes. */
1041 static bool
1043 {
1045 }
1047 /* Return TRUE if MODE is any of the vector modes. */
1048 static bool
1050 {
1053 }
1055 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1056 static bool
1059 {
1067 }
1069 /* Implement HARD_REGNO_NREGS. */
1071 int
1073 {
1075 {
1081 }
1083 }
1085 /* Implement HARD_REGNO_MODE_OK. */
1087 int
1089 {
1094 /* The purpose of comparing with ptr_mode is to support the
1095 global register variable associated with the stack pointer
1096 register via the syntax of asm ("wsp") in ILP32. */
1106 {
1108 return
1110 else
1112 }
1115 }
1117 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1118 machine_mode
1120 machine_mode mode)
1121 {
1122 /* Handle modes that fit within single registers. */
1124 {
1127 else
1129 }
1130 /* Fall back to generic for multi-reg and very large modes. */
1131 else
1133 }
1135 /* Return true if calls to DECL should be treated as
1136 long-calls (ie called via a register). */
1137 static bool
1139 {
1141 }
1143 /* Return true if calls to symbol-ref SYM should be treated as
1144 long-calls (ie called via a register). */
1145 bool
1147 {
1149 }
1151 /* Return true if calls to symbol-ref SYM should not go through
1152 plt stubs. */
1154 bool
1156 {
1160 && decl
1161 && (!flag_plt
1167 }
1169 /* Return true if the offsets to a zero/sign-extract operation
1170 represent an expression that matches an extend operation. The
1171 operands represent the paramters from
1173 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1174 bool
1176 rtx extract_imm)
1177 {
1194 }
1196 /* Emit an insn that's a simple single-set. Both the operands must be
1197 known to be valid. */
1200 {
1202 }
1204 /* X and Y are two things to compare using CODE. Emit the compare insn and
1205 return the rtx for register 0 in the proper mode. */
1206 rtx
1208 {
1214 }
1216 /* Build the SYMBOL_REF for __tls_get_addr. */
1220 rtx
1222 {
1226 }
1228 /* Return the TLS model to use for ADDR. */
1230 static enum tls_model
1232 {
1237 {
1241 }
1246 }
1248 /* We'll allow lo_sum's in addresses in our legitimate addresses
1249 so that combine would take care of combining addresses where
1250 necessary, but for generation purposes, we'll generate the address
1251 as :
1252 RTL Absolute
1253 tmp = hi (symbol_ref); adrp x1, foo
1254 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1255 nop
1257 PIC TLS
1258 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1259 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1260 bl __tls_get_addr
1261 nop
1263 Load TLS symbol, depending on TLS mechanism and TLS access model.
1265 Global Dynamic - Traditional TLS:
1266 adrp tmp, :tlsgd:imm
1267 add dest, tmp, #:tlsgd_lo12:imm
1268 bl __tls_get_addr
1270 Global Dynamic - TLS Descriptors:
1271 adrp dest, :tlsdesc:imm
1272 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1273 add dest, dest, #:tlsdesc_lo12:imm
1274 blr tmp
1275 mrs tp, tpidr_el0
1276 add dest, dest, tp
1278 Initial Exec:
1279 mrs tp, tpidr_el0
1280 adrp tmp, :gottprel:imm
1281 ldr dest, [tmp, #:gottprel_lo12:imm]
1282 add dest, dest, tp
1284 Local Exec:
1285 mrs tp, tpidr_el0
1286 add t0, tp, #:tprel_hi12:imm, lsl #12
1287 add t0, t0, #:tprel_lo12_nc:imm
1288 */
1290 static void
1293 {
1295 {
1297 {
1298 /* In ILP32, the mode of dest can be either SImode or DImode. */
1310 }
1317 {
1320 rtx insn;
1321 rtx mem;
1323 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1324 here before rtl expand. Tree IVOPT will generate rtl pattern to
1325 decide rtx costs, in which case pic_offset_table_rtx is not
1326 initialized. For that case no need to generate the first adrp
1327 instruction as the final cost for global variable access is
1328 one instruction. */
1330 {
1331 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1332 using the page base as GOT base, the first page may be wasted,
1333 in the worst scenario, there is only 28K space for GOT).
1335 The generate instruction sequence for accessing global variable
1336 is:
1338 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1340 Only one instruction needed. But we must initialize
1341 pic_offset_table_rtx properly. We generate initialize insn for
1342 every global access, and allow CSE to remove all redundant.
1344 The final instruction sequences will look like the following
1345 for multiply global variables access.
1347 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1349 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1350 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1351 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1352 ... */
1361 }
1364 {
1367 else
1371 }
1372 else
1373 {
1378 }
1380 /* The operand is expected to be MEM. Whenever the related insn
1381 pattern changed, above code which calculate mem should be
1382 updated. */
1388 }
1391 {
1392 /* In ILP32, the mode of dest can be either SImode or DImode,
1393 while the got entry is always of SImode size. The mode of
1394 dest depends on how dest is used: if dest is assigned to a
1395 pointer (e.g. in the memory), it has SImode; it may have
1396 DImode if dest is dereferenced to access the memeory.
1397 This is why we have to handle three different ldr_got_small
1398 patterns here (two patterns for ILP32). */
1400 rtx insn;
1401 rtx mem;
1410 {
1413 else
1417 }
1418 else
1419 {
1424 }
1431 }
1434 {
1442 else
1450 }
1453 {
1456 rtx tp;
1460 /* In ILP32, the got entry is always of SImode size. Unlike
1461 small GOT, the dest is fixed at reg 0. */
1464 else
1474 }
1477 {
1478 /* In ILP32, the mode of dest can be either SImode or DImode,
1479 while the got entry is always of SImode size. The mode of
1480 dest depends on how dest is used: if dest is assigned to a
1481 pointer (e.g. in the memory), it has SImode; it may have
1482 DImode if dest is dereferenced to access the memeory.
1483 This is why we have to handle three different tlsie_small
1484 patterns here (two patterns for ILP32). */
1490 {
1493 else
1494 {
1497 }
1498 }
1499 else
1500 {
1503 }
1508 }
1514 {
1522 {
1545 }
1549 }
1556 {
1561 {
1564 else
1565 {
1568 }
1569 }
1570 else
1571 {
1574 }
1578 }
1582 }
1583 }
1585 /* Emit a move from SRC to DEST. Assume that the move expanders can
1586 handle all moves if !can_create_pseudo_p (). The distinction is
1587 important because, unlike emit_move_insn, the move expanders know
1588 how to force Pmode objects into the constant pool even when the
1589 constant pool address is not itself legitimate. */
1590 static rtx
1592 {
1596 }
1598 /* Split a 128-bit move operation into two 64-bit move operations,
1599 taking care to handle partial overlap of register to register
1600 copies. Special cases are needed when moving between GP regs and
1601 FP regs. SRC can be a register, constant or memory; DST a register
1602 or memory. If either operand is memory it must not have any side
1603 effects. */
1604 void
1606 {
1617 {
1621 /* Handle FP <-> GP regs. */
1623 {
1628 {
1631 }
1632 else
1633 {
1636 }
1638 }
1640 {
1645 {
1648 }
1649 else
1650 {
1653 }
1655 }
1656 }
1663 /* At most one pairing may overlap. */
1665 {
1668 }
1669 else
1670 {
1673 }
1674 }
1676 bool
1678 {
1681 }
1683 /* Split a complex SIMD combine. */
1685 void
1687 {
1699 {
1723 }
1727 }
1729 /* Split a complex SIMD move. */
1731 void
1733 {
1740 {
1746 {
1770 }
1774 }
1775 }
1777 bool
1780 {
1784 }
1787 static rtx
1789 {
1792 else
1793 {
1796 }
1797 }
1800 static rtx
1802 {
1804 {
1805 rtx high;
1806 /* Load the full offset into a register. This
1807 might be improvable in the future. */
1813 }
1815 }
1817 static int
1819 machine_mode mode)
1820 {
1829 {
1833 }
1835 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1836 (with XXXX non-zero). In that case check to see if the move can be done in
1837 a smaller mode. */
1842 {
1846 /* Check if we have to emit a second instruction by checking to see
1847 if any of the upper 32 bits of the original DI mode value is set. */
1858 }
1861 {
1863 {
1868 else
1871 }
1873 }
1875 /* Remaining cases are all for DImode. */
1884 {
1885 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1886 For a 64-bit bitmask try whether changing 16 bits to all ones or
1887 zeroes creates a valid bitmask. To check any repeated bitmask,
1888 try using 16 bits from the other 32-bit half of val. */
1891 {
1902 }
1904 {
1906 {
1910 }
1912 }
1913 }
1915 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1916 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1917 otherwise skip zero bits. */
1929 {
1935 num_insns ++;
1936 }
1939 }
1942 void
1944 {
1949 /* Check on what type of symbol it is. */
1953 {
1957 /* If we have (const (plus symbol offset)), separate out the offset
1958 before we start classifying the symbol. */
1963 {
1967 {
1973 }
1978 /* If we aren't generating PC relative literals, then
1979 we need to expand the literal pool access carefully.
1980 This is something that needs to be done in a number
1981 of places, so could well live as a separate function. */
1983 {
1990 }
2007 {
2013 }
2014 /* FALLTHRU */
2027 }
2028 }
2031 {
2034 else
2035 {
2039 }
2042 }
2045 }
2047 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2048 temporary value if necessary. FRAME_RELATED_P should be true if
2049 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2050 to the generated instructions. If SCRATCHREG is known to hold
2051 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2052 immediate again.
2054 Since this function may be used to adjust the stack pointer, we must
2055 ensure that it cannot cause transient stack deallocation (for example
2056 by first incrementing SP and then decrementing when adjusting by a
2057 large immediate). */
2059 static void
2063 {
2071 /* Single instruction adjustment. */
2073 {
2077 }
2079 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2080 Only do this if mdelta is not a 16-bit move as adjusting using a move
2081 is better. */
2083 {
2092 }
2094 /* Emit a move immediate if required and an addition/subtraction. */
2101 {
2105 }
2106 }
2110 HOST_WIDE_INT delta)
2111 {
2113 }
2117 {
2120 }
2124 {
2127 }
2129 static bool
2131 tree exp ATTRIBUTE_UNUSED)
2132 {
2133 /* Currently, always true. */
2135 }
2137 /* Implement TARGET_PASS_BY_REFERENCE. */
2139 static bool
2141 machine_mode mode,
2142 const_tree type,
2144 {
2145 HOST_WIDE_INT size;
2146 machine_mode dummymode;
2149 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2153 /* Aggregates are passed by reference based on their size. */
2155 {
2157 }
2159 /* Variable sized arguments are always returned by reference. */
2163 /* Can this be a candidate to be passed in fp/simd register(s)? */
2166 NULL))
2169 /* Arguments which are variable sized or larger than 2 registers are
2170 passed by reference unless they are a homogenous floating point
2171 aggregate. */
2173 }
2175 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2176 static bool
2178 {
2179 machine_mode dummy_mode;
2182 /* Never happens in little-endian mode. */
2186 /* Only composite types smaller than or equal to 16 bytes can
2187 be potentially returned in registers. */
2193 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2194 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2195 is always passed/returned in the least significant bits of fp/simd
2196 register(s). */
2202 }
2204 /* Implement TARGET_FUNCTION_VALUE.
2205 Define how to find the value returned by a function. */
2207 static rtx
2210 {
2211 machine_mode mode;
2214 machine_mode ag_mode;
2221 {
2225 {
2228 }
2229 }
2233 {
2235 {
2238 }
2239 else
2240 {
2242 rtx par;
2246 {
2251 }
2253 }
2254 }
2255 else
2257 }
2259 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2260 Return true if REGNO is the number of a hard register in which the values
2261 of called function may come back. */
2263 static bool
2265 {
2266 /* Maximum of 16 bytes can be returned in the general registers. Examples
2267 of 16-byte return values are: 128-bit integers and 16-byte small
2268 structures (excluding homogeneous floating-point aggregates). */
2272 /* Up to four fp/simd registers can return a function value, e.g. a
2273 homogeneous floating-point aggregate having four members. */
2278 }
2280 /* Implement TARGET_RETURN_IN_MEMORY.
2282 If the type T of the result of a function is such that
2283 void func (T arg)
2284 would require that arg be passed as a value in a register (or set of
2285 registers) according to the parameter passing rules, then the result
2286 is returned in the same registers as would be used for such an
2287 argument. */
2289 static bool
2291 {
2292 HOST_WIDE_INT size;
2293 machine_mode ag_mode;
2299 /* Simple scalar types always returned in registers. */
2303 type,
2306 NULL))
2309 /* Types larger than 2 registers returned in memory. */
2312 }
2314 static bool
2317 {
2320 type,
2322 nregs,
2323 NULL);
2324 }
2326 /* Given MODE and TYPE of a function argument, return the alignment in
2327 bits. The idea is to suppress any stronger alignment requested by
2328 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2329 This is a helper function for local use only. */
2331 static unsigned int
2333 {
2354 }
2356 /* Layout a function argument according to the AAPCS64 rules. The rule
2357 numbers refer to the rule numbers in the AAPCS64. */
2359 static void
2361 const_tree type,
2363 {
2367 HOST_WIDE_INT size;
2369 /* We need to do this once per argument. */
2375 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2376 size
2378 UNITS_PER_WORD);
2382 mode,
2383 type,
2386 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2387 The following code thus handles passing by SIMD/FP registers first. */
2391 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2392 and homogenous short-vector aggregates (HVA). */
2394 {
2399 {
2402 {
2405 }
2406 else
2407 {
2408 rtx par;
2412 {
2415 tmp = gen_rtx_EXPR_LIST
2419 }
2421 }
2423 }
2424 else
2425 {
2426 /* C.3 NSRN is set to 8. */
2429 }
2430 }
2435 /* C6 - C9. though the sign and zero extension semantics are
2436 handled elsewhere. This is the case where the argument fits
2437 entirely general registers. */
2439 {
2443 /* C.8 if the argument has an alignment of 16 then the NGRN is
2444 rounded up to the next even number. */
2447 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2448 comparison is there because for > 16 * BITS_PER_UNIT
2449 alignment nregs should be > 2 and therefore it should be
2450 passed by reference rather than value. */
2452 {
2455 }
2457 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2458 A reg is still generated for it, but the caller should be smart
2459 enough not to use it. */
2462 else
2463 {
2464 rtx par;
2469 {
2474 }
2476 }
2480 }
2482 /* C.11 */
2485 /* The argument is passed on stack; record the needed number of words for
2486 this argument and align the total size if necessary. */
2487 on_stack:
2494 }
2496 /* Implement TARGET_FUNCTION_ARG. */
2498 static rtx
2501 {
2510 }
2512 void
2514 const_tree fntype ATTRIBUTE_UNUSED,
2515 rtx libname ATTRIBUTE_UNUSED,
2516 const_tree fndecl ATTRIBUTE_UNUSED,
2518 {
2532 {
2539 }
2541 }
2543 static void
2545 machine_mode mode,
2546 const_tree type,
2548 {
2551 {
2561 }
2562 }
2564 bool
2566 {
2569 }
2571 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2572 PARM_BOUNDARY bits of alignment, but will be given anything up
2573 to STACK_BOUNDARY bits if the type requires it. This makes sure
2574 that both before and after the layout of each argument, the Next
2575 Stacked Argument Address (NSAA) will have a minimum alignment of
2576 8 bytes. */
2578 static unsigned int
2580 {
2583 }
2585 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2587 Return true if an argument passed on the stack should be padded upwards,
2588 i.e. if the least-significant byte of the stack slot has useful data.
2590 Small aggregate types are placed in the lowest memory address.
2592 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2594 bool
2596 {
2597 /* On little-endian targets, the least significant byte of every stack
2598 argument is passed at the lowest byte address of the stack slot. */
2602 /* Otherwise, integral, floating-point and pointer types are padded downward:
2603 the least significant byte of a stack argument is passed at the highest
2604 byte address of the stack slot. */
2611 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2613 }
2615 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2617 It specifies padding for the last (may also be the only)
2618 element of a block move between registers and memory. If
2619 assuming the block is in the memory, padding upward means that
2620 the last element is padded after its highest significant byte,
2621 while in downward padding, the last element is padded at the
2622 its least significant byte side.
2624 Small aggregates and small complex types are always padded
2625 upwards.
2627 We don't need to worry about homogeneous floating-point or
2628 short-vector aggregates; their move is not affected by the
2629 padding direction determined here. Regardless of endianness,
2630 each element of such an aggregate is put in the least
2631 significant bits of a fp/simd register.
2633 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2634 register has useful data, and return the opposite if the most
2635 significant byte does. */
2637 bool
2640 {
2642 /* Small composite types are always padded upward. */
2644 {
2649 }
2651 /* Otherwise, use the default padding. */
2653 }
2655 static machine_mode
2657 {
2659 }
2661 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2663 /* We use the 12-bit shifted immediate arithmetic instructions so values
2664 must be multiple of (1 << 12), i.e. 4096. */
2665 #define ARITH_FACTOR 4096
2667 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2668 #error Cannot use simple address calculation for stack probing
2669 #endif
2671 /* The pair of scratch registers used for stack probing. */
2672 #define PROBE_STACK_FIRST_REG 9
2673 #define PROBE_STACK_SECOND_REG 10
2675 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2676 inclusive. These are offsets from the current stack pointer. */
2678 static void
2680 {
2683 /* See the same assertion on PROBE_INTERVAL above. */
2686 /* See if we have a constant small number of probes to generate. If so,
2687 that's the easy case. */
2689 {
2696 }
2698 /* The run-time loop is made up of 8 insns in the generic case while the
2699 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2701 {
2706 stack_pointer_rtx,
2710 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2711 it exceeds SIZE. If only two probes are needed, this will not
2712 generate any code. Then probe at FIRST + SIZE. */
2714 {
2718 }
2722 {
2727 }
2728 else
2730 }
2732 /* Otherwise, do the same as above, but in a loop. Note that we must be
2733 extra careful with variables wrapping around because we might be at
2734 the very top (or the very bottom) of the address space and we have
2735 to be able to handle this case properly; in particular, we use an
2736 equality test for the loop condition. */
2737 else
2738 {
2741 /* Step 1: round SIZE to the previous multiple of the interval. */
2746 /* Step 2: compute initial and final value of the loop counter. */
2748 /* TEST_ADDR = SP + FIRST. */
2752 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2755 {
2759 }
2760 else
2761 {
2764 }
2766 /* Step 3: the loop
2768 do
2769 {
2770 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2771 probe at TEST_ADDR
2772 }
2773 while (TEST_ADDR != LAST_ADDR)
2775 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2776 until it is equal to ROUNDED_SIZE. */
2781 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2782 that SIZE is equal to ROUNDED_SIZE. */
2785 {
2789 {
2794 }
2795 else
2797 }
2798 }
2800 /* Make sure nothing is scheduled before we are done. */
2802 }
2804 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2805 absolute addresses. */
2809 {
2816 /* Loop. */
2819 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2824 /* Probe at TEST_ADDR. */
2827 /* Test if TEST_ADDR == LAST_ADDR. */
2831 /* Branch. */
2837 }
2839 static bool
2841 {
2842 /* In aarch64_override_options_after_change
2843 flag_omit_leaf_frame_pointer turns off the frame pointer by
2844 default. Turn it back on now if we've not got a leaf
2845 function. */
2850 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2855 }
2857 /* Mark the registers that need to be saved by the callee and calculate
2858 the size of the callee-saved registers area and frame record (both FP
2859 and LR may be omitted). */
2860 static void
2862 {
2869 #define SLOT_NOT_REQUIRED (-2)
2870 #define SLOT_REQUIRED (-1)
2875 /* First mark all the registers that really need to be saved... */
2882 /* ... that includes the eh data registers (if needed)... */
2888 /* ... and any callee saved register that dataflow says is live. */
2898 {
2901 }
2904 {
2905 /* FP and LR are placed in the linkage record. */
2911 }
2913 /* Now assign stack slots for them. */
2916 {
2923 }
2931 {
2932 /* If there is an alignment gap between integer and fp callee-saves,
2933 allocate the last fp register to it if possible. */
2935 {
2938 }
2947 }
2953 HOST_WIDE_INT varargs_and_saved_regs_size
2980 {
2981 /* Simple, small frame with no outgoing arguments:
2982 stp reg1, reg2, [sp, -frame_size]!
2983 stp reg3, reg4, [sp, 16] */
2985 }
2990 {
2991 /* Frame with small outgoing arguments:
2992 sub sp, sp, frame_size
2993 stp reg1, reg2, [sp, outgoing_args_size]
2994 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2998 }
3000 {
3001 /* Frame with large outgoing arguments but a small local area:
3002 stp reg1, reg2, [sp, -hard_fp_offset]!
3003 stp reg3, reg4, [sp, 16]
3004 sub sp, sp, outgoing_args_size */
3008 }
3011 {
3012 /* Frame with large local area and outgoing arguments (this pushes the
3013 callee-saves first, followed by the locals and outgoing area):
3014 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3015 stp reg3, reg4, [sp, 16]
3016 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3022 }
3023 else
3024 {
3025 /* Frame with large local area and outgoing arguments using frame pointer:
3026 sub sp, sp, hard_fp_offset
3027 stp x29, x30, [sp, 0]
3028 add x29, sp, 0
3029 stp reg3, reg4, [sp, 16]
3030 sub sp, sp, outgoing_args_size */
3034 }
3037 }
3039 /* Return true if the register REGNO is saved on entry to
3040 the current function. */
3042 static bool
3044 {
3046 }
3048 /* Return the next register up from REGNO up to LIMIT for the callee
3049 to save. */
3051 static unsigned
3053 {
3055 regno ++;
3057 }
3059 /* Push the register number REGNO of mode MODE to the stack with write-back
3060 adjusting the stack by ADJUSTMENT. */
3062 static void
3064 HOST_WIDE_INT adjustment)
3065 {
3076 }
3078 /* Generate and return an instruction to store the pair of registers
3079 REG and REG2 of mode MODE to location BASE with write-back adjusting
3080 the stack location BASE by ADJUSTMENT. */
3082 static rtx
3084 HOST_WIDE_INT adjustment)
3085 {
3087 {
3098 }
3099 }
3101 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3102 stack pointer by ADJUSTMENT. */
3104 static void
3106 {
3121 }
3123 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3124 adjusting it by ADJUSTMENT afterwards. */
3126 static rtx
3128 HOST_WIDE_INT adjustment)
3129 {
3131 {
3140 }
3141 }
3143 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3144 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3145 into CFI_OPS. */
3147 static void
3150 {
3157 {
3161 }
3162 else
3163 {
3168 }
3169 }
3171 /* Generate and return a store pair instruction of mode MODE to store
3172 register REG1 to MEM1 and register REG2 to MEM2. */
3174 static rtx
3176 rtx reg2)
3177 {
3179 {
3188 }
3189 }
3191 /* Generate and regurn a load pair isntruction of mode MODE to load register
3192 REG1 from MEM1 and register REG2 from MEM2. */
3194 static rtx
3196 rtx mem2)
3197 {
3199 {
3208 }
3209 }
3211 /* Return TRUE if return address signing should be enabled for the current
3212 function, otherwise return FALSE. */
3214 bool
3216 {
3217 /* This function should only be called after frame laid out. */
3220 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3221 if it's LR is pushed onto stack. */
3225 }
3227 /* Emit code to save the callee-saved registers from register number START
3228 to LIMIT to the stack at the location starting at offset START_OFFSET,
3229 skipping any write-back candidates if SKIP_WB is true. */
3231 static void
3234 {
3244 {
3246 HOST_WIDE_INT offset;
3259 offset));
3268 {
3270 rtx mem2;
3274 offset));
3276 reg2));
3278 /* The first part of a frame-related parallel insn is
3279 always assumed to be relevant to the frame
3280 calculations; subsequent parts, are only
3281 frame-related if explicitly marked. */
3284 }
3285 else
3289 }
3290 }
3292 /* Emit code to restore the callee registers of mode MODE from register
3293 number START up to and including LIMIT. Restore from the stack offset
3294 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3295 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3297 static void
3301 {
3307 HOST_WIDE_INT offset;
3312 {
3333 {
3335 rtx mem2;
3343 }
3344 else
3347 }
3348 }
3352 HOST_WIDE_INT offset)
3353 {
3355 }
3359 {
3363 }
3365 bool
3367 {
3371 }
3373 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3375 static sbitmap
3377 {
3383 /* The registers we need saved to the frame. */
3386 {
3391 /* Check that we can access the stack slot of the register with one
3392 direct load with no adjustments needed. */
3395 }
3397 /* Don't mess with the hard frame pointer. */
3403 /* If aarch64_layout_frame has chosen registers to store/restore with
3404 writeback don't interfere with them to avoid having to output explicit
3405 stack adjustment instructions. */
3415 }
3417 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3419 static sbitmap
3421 {
3429 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3438 }
3440 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3441 Nothing to do for aarch64. */
3443 static void
3445 {
3446 }
3448 /* Return the next set bit in BMP from START onwards. Return the total number
3449 of bits in BMP if no set bit is found at or after START. */
3451 static unsigned int
3453 {
3464 }
3466 /* Do the work for aarch64_emit_prologue_components and
3467 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3468 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3469 for these components or the epilogue sequence. That is, it determines
3470 whether we should emit stores or loads and what kind of CFA notes to attach
3471 to the insns. Otherwise the logic for the two sequences is very
3472 similar. */
3474 static void
3476 {
3478 ? HARD_FRAME_POINTER_REGNUM
3486 {
3487 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3488 so DFmode for the vector registers is enough. */
3500 /* No more registers to handle after REGNO.
3501 Emit a single save/restore and exit. */
3503 {
3508 else
3511 }
3514 /* The next register is not of the same class or its offset is not
3515 mergeable with the current one into a pair. */
3520 {
3525 else
3530 }
3532 /* REGNO2 can be saved/restored in a pair with REGNO. */
3544 else
3549 {
3552 }
3553 else
3554 {
3557 }
3560 }
3561 }
3563 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3565 static void
3567 {
3569 }
3571 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3573 static void
3575 {
3577 }
3579 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3581 static void
3583 {
3587 }
3589 /* AArch64 stack frames generated by this compiler look like:
3591 +-------------------------------+
3592 | |
3593 | incoming stack arguments |
3594 | |
3595 +-------------------------------+
3596 | | <-- incoming stack pointer (aligned)
3597 | callee-allocated save area |
3598 | for register varargs |
3599 | |
3600 +-------------------------------+
3601 | local variables | <-- frame_pointer_rtx
3602 | |
3603 +-------------------------------+
3604 | padding0 | \
3605 +-------------------------------+ |
3606 | callee-saved registers | | frame.saved_regs_size
3607 +-------------------------------+ |
3608 | LR' | |
3609 +-------------------------------+ |
3610 | FP' | / <- hard_frame_pointer_rtx (aligned)
3611 +-------------------------------+
3612 | dynamic allocation |
3613 +-------------------------------+
3614 | padding |
3615 +-------------------------------+
3616 | outgoing stack arguments | <-- arg_pointer
3617 | |
3618 +-------------------------------+
3619 | | <-- stack_pointer_rtx (aligned)
3621 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3622 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3623 unchanged. */
3625 /* Generate the prologue instructions for entry into a function.
3626 Establish the stack frame by decreasing the stack pointer with a
3627 properly calculated size and, if necessary, create a frame record
3628 filled with the values of LR and previous frame pointer. The
3629 current FP is also set up if it is in use. */
3631 void
3633 {
3645 /* Sign return address for functions. */
3647 {
3651 }
3657 {
3659 {
3663 }
3666 }
3674 {
3679 stack_pointer_rtx,
3683 }
3690 }
3692 /* Return TRUE if we can use a simple_return insn.
3694 This function checks whether the callee saved stack is empty, which
3695 means no restore actions are need. The pro_and_epilogue will use
3696 this to check whether shrink-wrapping opt is feasible. */
3698 bool
3700 {
3710 }
3712 /* Generate the epilogue instructions for returning from a function.
3713 This is almost exactly the reverse of the prolog sequence, except
3714 that we need to insert barriers to avoid scheduling loads that read
3715 from a deallocated stack, and we optimize the unwind records by
3716 emitting them all together if possible. */
3717 void
3719 {
3731 /* We need to add memory barrier to prevent read from deallocated stack. */
3735 /* Emit a barrier to prevent loads from a deallocated stack. */
3738 {
3741 }
3743 /* Restore the stack pointer from the frame pointer if it may not
3744 be the same as the stack pointer. */
3746 {
3748 hard_frame_pointer_rtx,
3750 /* If writeback is used when restoring callee-saves, the CFA
3751 is restored on the instruction doing the writeback. */
3753 }
3754 else
3769 {
3770 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3776 }
3781 {
3782 /* Emit delayed restores and reset the CFA to be SP. */
3787 }
3789 /* We prefer to emit the combined return/authenticate instruction RETAA,
3790 however there are three cases in which we must instead emit an explicit
3791 authentication instruction.
3793 1) Sibcalls don't return in a normal way, so if we're about to call one
3794 we must authenticate.
3796 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3797 generating code for !TARGET_ARMV8_3 we can't use it and must
3798 explicitly authenticate.
3800 3) On an eh_return path we make extra stack adjustments to update the
3801 canonical frame address to be the exception handler's CFA. We want
3802 to authenticate using the CFA of the function which calls eh_return.
3803 */
3806 {
3810 }
3812 /* Stack adjustment for exception handler. */
3814 {
3815 /* We need to unwind the stack by the offset computed by
3816 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3817 to be SP; letting the CFA move during this adjustment
3818 is just as correct as retaining the CFA from the body
3819 of the function. Therefore, do nothing special. */
3821 }
3826 }
3828 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3829 normally or return to a previous frame after unwinding.
3831 An EH return uses a single shared return sequence. The epilogue is
3832 exactly like a normal epilogue except that it has an extra input
3833 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3834 that must be applied after the frame has been destroyed. An extra label
3835 is inserted before the epilogue which initializes this register to zero,
3836 and this is the entry point for a normal return.
3838 An actual EH return updates the return address, initializes the stack
3839 adjustment and jumps directly into the epilogue (bypassing the zeroing
3840 of the adjustment). Since the return address is typically saved on the
3841 stack when a function makes a call, the saved LR must be updated outside
3842 the epilogue.
3844 This poses problems as the store is generated well before the epilogue,
3845 so the offset of LR is not known yet. Also optimizations will remove the
3846 store as it appears dead, even after the epilogue is generated (as the
3847 base or offset for loading LR is different in many cases).
3849 To avoid these problems this implementation forces the frame pointer
3850 in eh_return functions so that the location of LR is fixed and known early.
3851 It also marks the store volatile, so no optimization is permitted to
3852 remove the store. */
3853 rtx
3855 {
3859 /* Mark the store volatile, so no optimization is permitted to remove it. */
3862 }
3864 /* Output code to add DELTA to the first argument, and then jump
3865 to FUNCTION. Used for C++ multiple inheritance. */
3866 static void
3868 HOST_WIDE_INT delta,
3869 HOST_WIDE_INT vcall_offset,
3870 tree function)
3871 {
3872 /* The this pointer is always in x0. Note that this differs from
3873 Arm where the this pointer maybe bumped to r1 if r0 is required
3874 to return a pointer to an aggregate. On AArch64 a result value
3875 pointer will be in x8. */
3885 else
3886 {
3895 {
3899 else
3901 }
3905 else
3912 else
3913 {
3915 Pmode);
3917 }
3921 else
3927 }
3929 /* Generate a tail call to the target function. */
3931 {
3934 }
3946 /* Stop pretending to be a post-reload pass. */
3948 }
3950 static bool
3952 {
3957 {
3961 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3962 TLS offsets, not real symbol references. */
3965 }
3967 }
3970 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3971 a left shift of 0 or 12 bits. */
3972 bool
3974 {
3977 );
3978 }
3981 /* Return true if val is an immediate that can be loaded into a
3982 register by a MOVZ instruction. */
3983 static bool
3985 {
3987 {
3991 }
3992 else
3993 {
3994 /* Ignore sign extension. */
3996 }
3999 }
4001 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4004 {
4010 };
4013 /* Return true if val is a valid bitmask immediate. */
4015 bool
4017 {
4021 /* Check for a single sequence of one bits and return quickly if so.
4022 The special cases of all ones and all zeroes returns false. */
4029 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4033 /* Invert if the immediate doesn't start with a zero bit - this means we
4034 only need to search for sequences of one bits. */
4038 /* Find the first set bit and set tmp to val with the first sequence of one
4039 bits removed. Return success if there is a single sequence of ones. */
4046 /* Find the next set bit and compute the difference in bit position. */
4051 /* Check the bit position difference is a power of 2, and that the first
4052 sequence of one bits fits within 'bits' bits. */
4056 /* Check the sequence of one bits is repeated 64/bits times. */
4058 }
4060 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4061 Assumed precondition: VAL_IN Is not zero. */
4063 unsigned HOST_WIDE_INT
4065 {
4072 }
4074 /* Create constant where bits outside of lowest bit set to highest bit set
4075 are set to 1. */
4077 unsigned HOST_WIDE_INT
4079 {
4081 }
4083 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4085 bool
4087 {
4097 }
4099 /* Return true if val is an immediate that can be loaded into a
4100 register in a single instruction. */
4101 bool
4103 {
4107 }
4109 static bool
4111 {
4119 {
4123 else
4124 /* Avoid generating a 64-bit relocation in ILP32; leave
4125 to aarch64_expand_mov_immediate to handle it properly. */
4127 }
4130 }
4132 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4133 The expansion for a table switch is quite expensive due to the number
4134 of instructions, the table lookup and hard to predict indirect jump.
4135 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4136 set, otherwise use tables for > 16 cases as a tradeoff between size and
4137 performance. When optimizing for size, use the default setting. */
4139 static unsigned int
4141 {
4142 /* Use the specified limit for the number of cases before using jump
4143 tables at higher optimization levels. */
4147 else
4149 }
4151 /* Return true if register REGNO is a valid index register.
4152 STRICT_P is true if REG_OK_STRICT is in effect. */
4154 bool
4156 {
4158 {
4166 }
4168 }
4170 /* Return true if register REGNO is a valid base register for mode MODE.
4171 STRICT_P is true if REG_OK_STRICT is in effect. */
4173 bool
4175 {
4177 {
4185 }
4187 /* The fake registers will be eliminated to either the stack or
4188 hard frame pointer, both of which are usually valid base registers.
4189 Reload deals with the cases where the eliminated form isn't valid. */
4194 }
4196 /* Return true if X is a valid base register for mode MODE.
4197 STRICT_P is true if REG_OK_STRICT is in effect. */
4199 static bool
4201 {
4206 }
4208 /* Return true if address offset is a valid index. If it is, fill in INFO
4209 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4211 static bool
4214 {
4216 rtx index;
4219 /* (reg:P) */
4222 {
4226 }
4227 /* (sign_extend:DI (reg:SI)) */
4232 {
4237 }
4238 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4245 {
4250 }
4251 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4258 {
4263 }
4264 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4271 {
4279 }
4280 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4281 (const_int 0xffffffff<<shift)) */
4288 {
4294 }
4295 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4302 {
4310 }
4311 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4312 (const_int 0xffffffff<<shift)) */
4319 {
4325 }
4326 /* (mult:P (reg:P) (const_int scale)) */
4331 {
4335 }
4336 /* (ashift:P (reg:P) (const_int shift)) */
4341 {
4345 }
4346 else
4357 {
4362 }
4365 }
4367 /* Return true if MODE is one of the modes for which we
4368 support LDP/STP operations. */
4370 static bool
4372 {
4377 }
4379 /* Return true if REGNO is a virtual pointer register, or an eliminable
4380 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4381 include stack_pointer or hard_frame_pointer. */
4382 static bool
4384 {
4389 }
4391 /* Return true if X is a valid address for machine mode MODE. If it is,
4392 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4393 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4395 static bool
4399 {
4403 /* On BE, we use load/store pair for all large int mode load/stores.
4404 TI/TFmode may also use a load/store pair. */
4408 || (BYTES_BIG_ENDIAN
4412 !load_store_pair_p
4416 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4417 REG addressing. */
4423 {
4439 {
4445 }
4450 {
4457 /* TImode and TFmode values are allowed in both pairs of X
4458 registers and individual Q registers. The available
4459 address modes are:
4460 X,X: 7-bit signed scaled offset
4461 Q: 9-bit signed offset
4462 We conservatively require an offset representable in either mode.
4463 When performing the check for pairs of X registers i.e. LDP/STP
4464 pass down DImode since that is the natural size of the LDP/STP
4465 instruction memory accesses. */
4471 /* A 7bit offset check because OImode will emit a ldp/stp
4472 instruction (only big endian will get here).
4473 For ldp/stp instructions, the offset is scaled for the size of a
4474 single element of the pair. */
4478 /* Three 9/12 bit offsets checks because CImode will emit three
4479 ldr/str instructions (only big endian will get here). */
4486 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4487 instructions (only big endian will get here). */
4496 else
4499 }
4502 {
4503 /* Look for base + (scaled/extended) index register. */
4506 {
4509 }
4512 {
4515 }
4516 }
4537 {
4538 HOST_WIDE_INT offset;
4542 /* TImode and TFmode values are allowed in both pairs of X
4543 registers and individual Q registers. The available
4544 address modes are:
4545 X,X: 7-bit signed scaled offset
4546 Q: 9-bit signed offset
4547 We conservatively require an offset representable in either mode.
4548 */
4556 else
4558 }
4564 /* load literal: pc-relative constant pool entry. Only supported
4565 for SI mode or larger. */
4569 {
4577 }
4586 {
4591 {
4592 /* The symbol and offset must be aligned to the access size. */
4599 {
4603 }
4609 else
4618 }
4619 }
4624 }
4625 }
4627 /* Return true if the address X is valid for a PRFM instruction.
4628 STRICT_P is true if we should do strict checking with
4629 aarch64_classify_address. */
4631 bool
4633 {
4636 /* PRFM accepts the same addresses as DImode... */
4641 /* ... except writeback forms. */
4643 }
4645 bool
4647 {
4648 rtx offset;
4652 }
4654 /* Classify the base of symbolic expression X. */
4656 enum aarch64_symbol_type
4658 {
4659 rtx offset;
4663 }
4666 /* Return TRUE if X is a legitimate address for accessing memory in
4667 mode MODE. */
4668 static bool
4670 {
4674 }
4676 /* Return TRUE if X is a legitimate address for accessing memory in
4677 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4678 pair operation. */
4679 bool
4682 {
4686 }
4688 /* Split an out-of-range address displacement into a base and offset.
4689 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4690 to increase opportunities for sharing the base address of different sizes.
4691 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4692 static bool
4694 {
4705 }
4707 /* Return the binary representation of floating point constant VALUE in INTVAL.
4708 If the value cannot be converted, return false without setting INTVAL.
4709 The conversion is done in the given MODE. */
4710 bool
4712 {
4714 /* We make a general exception for 0. */
4716 {
4719 }
4725 /* Only support up to DF mode. */
4742 }
4744 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4745 single MOV(+MOVK) followed by an FMOV. */
4746 bool
4748 {
4753 /* Determine whether it's cheaper to write float constants as
4754 mov/movk pairs over ldr/adrp pairs. */
4760 {
4765 }
4768 }
4770 /* Return TRUE if rtx X is immediate constant 0.0 */
4771 bool
4773 {
4780 }
4782 /* Return TRUE if rtx X is immediate constant that fits in a single
4783 MOVI immediate operation. */
4784 bool
4786 {
4795 {
4799 /* We make a general exception for 0. */
4804 }
4807 {
4810 }
4811 else
4814 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4815 a 128 bit vector mode. */
4822 }
4825 /* Return the fixed registers used for condition codes. */
4827 static bool
4829 {
4833 }
4835 /* This function is used by the call expanders of the machine description.
4836 RESULT is the register in which the result is returned. It's NULL for
4837 "call" and "sibcall".
4838 MEM is the location of the function call.
4839 SIBCALL indicates whether this function call is normal call or sibling call.
4840 It will generate different pattern accordingly. */
4842 void
4844 {
4846 rtvec vec;
4847 machine_mode mode;
4854 /* Decide if we should generate indirect calls by loading the
4855 address of the callee into a register before performing
4856 the branch-and-link. */
4870 else
4877 }
4879 /* Emit call insn with PAT and do aarch64-specific handling. */
4881 void
4883 {
4889 }
4891 machine_mode
4893 {
4894 /* All floating point compares return CCFP if it is an equality
4895 comparison, and CCFPE otherwise. */
4897 {
4899 {
4920 }
4921 }
4923 /* Equality comparisons of short modes against zero can be performed
4924 using the TST instruction with the appropriate bitmask. */
4930 /* Similarly, comparisons of zero_extends from shorter modes can
4931 be performed using an ANDS with an immediate mask. */
4947 /* A compare with a shifted operand. Because of canonicalization,
4948 the comparison will have to be swapped when we emit the assembly
4949 code. */
4957 /* Similarly for a negated operand, but we can only do this for
4958 equalities. */
4965 /* A test for unsigned overflow. */
4972 /* For everything else, return CCmode. */
4974 }
4976 static int
4979 int
4981 {
4988 }
4990 static int
4992 {
4994 {
4998 {
5012 }
5017 {
5029 }
5034 {
5046 }
5051 {
5057 }
5062 {
5066 }
5071 {
5075 }
5080 }
5083 }
5085 bool
5087 HOST_WIDE_INT minval,
5088 HOST_WIDE_INT maxval)
5089 {
5090 HOST_WIDE_INT firstval;
5107 }
5109 bool
5111 {
5113 }
5116 /* N Z C V. */
5117 #define AARCH64_CC_V 1
5118 #define AARCH64_CC_C (1 << 1)
5119 #define AARCH64_CC_Z (1 << 2)
5120 #define AARCH64_CC_N (1 << 3)
5122 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5124 {
5141 };
5143 /* Print operand X to file F in a target specific manner according to CODE.
5144 The acceptable formatting commands given by CODE are:
5145 'c': An integer or symbol address without a preceding #
5146 sign.
5147 'e': Print the sign/zero-extend size as a character 8->b,
5148 16->h, 32->w.
5149 'p': Prints N such that 2^N == X (X must be power of 2 and
5150 const int).
5151 'P': Print the number of non-zero bits in X (a const_int).
5152 'H': Print the higher numbered register of a pair (TImode)
5153 of regs.
5154 'm': Print a condition (eq, ne, etc).
5155 'M': Same as 'm', but invert condition.
5156 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5157 'S/T/U/V': Print a FP/SIMD register name for a register list.
5158 The register printed is the FP/SIMD register name
5159 of X + 0/1/2/3 for S/T/U/V.
5160 'R': Print a scalar FP/SIMD register name + 1.
5161 'X': Print bottom 16 bits of integer constant in hex.
5162 'w/x': Print a general register name or the zero register
5163 (32-bit or 64-bit).
5164 '0': Print a normal operand, if it's a general register,
5165 then we assume DImode.
5166 'k': Print NZCV for conditional compare instructions.
5167 'A': Output address constant representing the first
5168 argument of X, specifying a relocation offset
5169 if appropriate.
5170 'L': Output constant address specified by X
5171 with a relocation offset if appropriate.
5172 'G': Prints address of X, specifying a PC relative
5173 relocation mode if appropriate. */
5175 static void
5177 {
5179 {
5182 {
5194 {
5197 }
5198 /* Fall through. */
5202 }
5206 {
5211 {
5214 }
5217 {
5230 }
5231 }
5235 {
5239 {
5242 }
5245 }
5250 {
5253 }
5260 {
5263 }
5270 {
5272 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5274 {
5278 }
5281 {
5284 }
5291 }
5300 {
5301 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5303 }
5312 {
5313 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5315 }
5321 {
5322 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5324 }
5330 {
5333 }
5341 {
5344 }
5347 {
5350 }
5353 {
5356 }
5358 /* Fall through */
5362 {
5365 }
5368 {
5375 /* Check all memory references are Pmode - even with ILP32. */
5391 {
5394 HOST_WIDE_INT_MIN,
5395 HOST_WIDE_INT_MAX));
5397 }
5399 {
5401 }
5402 else
5407 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5408 be getting CONST_DOUBLEs holding integers. */
5411 {
5414 }
5416 {
5417 #define buf_size 20
5425 #undef buf_size
5426 }
5432 }
5440 {
5467 }
5473 {
5508 }
5514 {
5520 }
5525 {
5526 HOST_WIDE_INT cond_code;
5529 {
5532 }
5537 }
5543 }
5544 }
5546 static void
5548 {
5553 {
5557 else
5566 else
5575 else
5584 else
5591 {
5618 }
5629 }
5632 }
5634 bool
5636 {
5643 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5644 referencing instruction, but they are constant offsets, not
5645 symbols. */
5651 {
5653 {
5659 }
5662 }
5665 }
5667 /* Implement REGNO_REG_CLASS. */
5669 enum reg_class
5671 {
5686 }
5688 static rtx
5690 {
5691 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5692 where mask is selected by alignment and size of the offset.
5693 We try to pick as large a range for the offset as possible to
5694 maximize the chance of a CSE. However, for aligned addresses
5695 we limit the range to 4k so that structures with different sized
5696 elements are likely to use the same base. We need to be careful
5697 not to split a CONST for some forms of address expression, otherwise
5698 it will generate sub-optimal code. */
5701 {
5707 {
5711 /* Force any scaling into a temp for CSE. */
5715 /* Let the pointer register be in op0. */
5719 /* If the pointer is virtual or frame related, then we know that
5720 virtual register instantiation or register elimination is going
5721 to apply a second constant. We want the two constants folded
5722 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5724 {
5728 }
5730 /* Otherwise, in order to encourage CSE (and thence loop strength
5731 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5735 }
5737 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5738 HOST_WIDE_INT base_offset;
5741 /* For offsets aren't a multiple of the access size, the limit is
5742 -256...255. */
5744 {
5747 /* BLKmode typically uses LDP of X-registers. */
5750 }
5751 /* Small negative offsets are supported. */
5756 /* Use 12-bit offset by access size. */
5757 else
5761 {
5765 }
5766 }
5769 }
5771 /* Return the reload icode required for a constant pool in mode. */
5772 static enum insn_code
5774 {
5776 {
5812 }
5815 }
5816 static reg_class_t
5818 reg_class_t rclass,
5819 machine_mode mode,
5821 {
5823 /* If we have to disable direct literal pool loads and stores because the
5824 function is too big, then we need a scratch register. */
5829 {
5832 }
5834 /* Without the TARGET_SIMD instructions we cannot move a Q register
5835 to a Q register directly. We need a scratch. */
5839 {
5845 }
5847 /* A TFmode or TImode memory access should be handled via an FP_REGS
5848 because AArch64 has richer addressing modes for LDR/STR instructions
5849 than LDP/STP instructions. */
5858 }
5860 static bool
5862 {
5863 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5864 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5867 {
5879 }
5880 else
5881 {
5882 /* If we decided that we didn't need a leaf frame pointer but then used
5883 LR in the function, then we'll want a frame pointer after all, so
5884 prevent this elimination to ensure a frame pointer is used. */
5886 && flag_omit_leaf_frame_pointer
5889 }
5892 }
5894 HOST_WIDE_INT
5896 {
5900 {
5907 }
5910 {
5914 }
5917 }
5919 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5920 previous frame. */
5922 rtx
5924 {
5928 }
5931 static void
5933 {
5935 {
5938 }
5939 else
5940 {
5943 }
5948 }
5950 static void
5952 {
5956 /* Don't need to copy the trailing D-words, we fill those in below. */
5968 /* XXX We should really define a "clear_cache" pattern and use
5969 gen_clear_cache(). */
5974 ptr_mode);
5975 }
5977 static unsigned char
5979 {
5981 {
5988 return
6000 }
6002 }
6004 static reg_class_t
6006 {
6011 {
6017 }
6019 /* Register eliminiation can result in a request for
6020 SP+constant->FP_REGS. We cannot support such operations which
6021 use SP as source and an FP_REG as destination, so reject out
6022 right now. */
6024 {
6027 /* Look through a possible SUBREG introduced by ILP32. */
6033 POINTER_REGS));
6035 }
6038 }
6040 void
6042 {
6044 }
6046 static void
6048 {
6051 else
6052 {
6054 /* While priority is known to be in range [0, 65535], so 18 bytes
6055 would be enough, the compiler might not know that. To avoid
6056 -Wformat-truncation false positive, use a larger size. */
6063 }
6064 }
6066 static void
6068 {
6071 else
6072 {
6074 /* While priority is known to be in range [0, 65535], so 18 bytes
6075 would be enough, the compiler might not know that. To avoid
6076 -Wformat-truncation false positive, use a larger size. */
6083 }
6084 }
6088 {
6094 {
6095 {
6098 },
6099 {
6102 },
6103 {
6106 },
6107 /* We assume that DImode is only generated when not optimizing and
6108 that we don't really need 64-bit address offsets. That would
6109 imply an object file with 8GB of code in a single function! */
6110 {
6113 }
6114 };
6122 /* Need to implement table size reduction, by chaning the code below. */
6132 }
6135 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6136 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6137 operator. */
6139 int
6141 {
6143 {
6146 {
6150 }
6151 }
6153 }
6155 /* Constant pools are per function only when PC relative
6156 literal loads are true or we are in the large memory
6157 model. */
6161 {
6164 }
6166 static bool
6168 {
6169 /* Fixme:: In an ideal world this would work similar
6170 to the logic in aarch64_select_rtx_section but this
6171 breaks bootstrap in gcc go. For now we workaround
6172 this by returning false here. */
6174 }
6176 /* Select appropriate section for constants depending
6177 on where we place literal pools. */
6181 rtx x,
6183 {
6188 }
6190 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6191 void
6193 HOST_WIDE_INT offset)
6194 {
6195 /* When using per-function literal pools, we must ensure that any code
6196 section is aligned to the minimal instruction length, lest we get
6197 errors from the assembler re "unaligned instructions". */
6200 }
6202 /* Costs. */
6204 /* Helper function for rtx cost calculation. Strip a shift expression
6205 from X. Returns the inner operand if successful, or the original
6206 expression on failure. */
6207 static rtx
6209 {
6212 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6213 we can convert both to ROR during final output. */
6228 }
6230 /* Helper function for rtx cost calculation. Strip an extend
6231 expression from X. Returns the inner operand if successful, or the
6232 original expression on failure. We deal with a number of possible
6233 canonicalization variations here. If STRIP_SHIFT is true, then
6234 we can strip off a shift also. */
6235 static rtx
6237 {
6240 /* Zero and sign extraction of a widened value. */
6248 /* It can also be represented (for zero-extend) as an AND with an
6249 immediate. */
6258 /* Now handle extended register, as this may also have an optional
6259 left shift by 1..4. */
6274 }
6276 /* Return true iff CODE is a shift supported in combination
6277 with arithmetic instructions. */
6279 static bool
6281 {
6283 }
6286 /* Return true iff X is a cheap shift without a sign extend. */
6288 static bool
6290 {
6316 }
6318 /* Helper function for rtx cost calculation. Calculate the cost of
6319 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6320 Return the calculated cost of the expression, recursing manually in to
6321 operands where needed. */
6323 static int
6325 {
6341 /* Integer multiply/fma. */
6343 {
6344 /* The multiply will be canonicalized as a shift, cost it as such. */
6348 {
6352 {
6354 {
6355 /* If the shift is considered cheap,
6356 then don't add any cost. */
6358 ;
6360 /* ARITH + shift-by-register. */
6363 /* ARITH + extended register. We don't have a cost field
6364 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6366 else
6367 /* ARITH + shift-by-immediate. */
6369 }
6370 else
6371 /* LSL (immediate). */
6374 }
6375 /* Strip extends as we will have costed them in the case above. */
6382 }
6384 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6385 compound and let the below cases handle it. After all, MNEG is a
6386 special-case alias of MSUB. */
6388 {
6391 }
6393 /* Integer multiplies or FMAs have zero/sign extending variants. */
6398 {
6403 {
6405 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6407 else
6408 /* MUL/SMULL/UMULL. */
6410 }
6413 }
6415 /* This is either an integer multiply or a MADD. In both cases
6416 we want to recurse and cost the operands. */
6421 {
6423 /* MADD/MSUB. */
6425 else
6426 /* MUL. */
6428 }
6431 }
6432 else
6433 {
6435 {
6436 /* Floating-point FMA/FMUL can also support negations of the
6437 operands, unless the rounding mode is upward or downward in
6438 which case FNMUL is different than FMUL with operand negation. */
6442 {
6447 }
6450 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6452 else
6453 /* FMUL/FNMUL. */
6455 }
6460 }
6461 }
6463 static int
6465 machine_mode mode,
6466 addr_space_t as ATTRIBUTE_UNUSED,
6468 {
6476 {
6478 {
6479 /* This is a CONST or SYMBOL ref which will be split
6480 in a different way depending on the code model in use.
6481 Cost it through the generic infrastructure. */
6483 /* Divide through by the cost of one instruction to
6484 bring it to the same units as the address costs. */
6486 /* The cost is then the cost of preparing the address,
6487 followed by an immediate (possibly 0) offset. */
6489 }
6490 else
6491 {
6492 /* This is most likely a jump table from a case
6493 statement. */
6495 }
6496 }
6499 {
6511 else
6530 }
6534 {
6535 /* For the sake of calculating the cost of the shifted register
6536 component, we can treat same sized modes in the same way. */
6538 {
6551 /* We can't tell, or this is a 128-bit vector. */
6555 }
6556 }
6559 }
6561 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6562 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6563 to be taken. */
6565 int
6567 {
6568 /* When optimizing for speed, use the cost of unpredictable branches. */
6574 else
6576 }
6578 /* Return true if the RTX X in mode MODE is a zero or sign extract
6579 usable in an ADD or SUB (extended register) instruction. */
6580 static bool
6582 {
6583 /* Catch add with a sign extract.
6584 This is add_<optab><mode>_multp2. */
6587 {
6598 op1))
6599 {
6601 }
6602 }
6603 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6604 No shift. */
6610 }
6612 static bool
6614 {
6616 {
6628 }
6629 }
6631 /* Return true iff X is an rtx that will match an extr instruction
6632 i.e. as described in the *extr<mode>5_insn family of patterns.
6633 OP0 and OP1 will be set to the operands of the shifts involved
6634 on success and will be NULL_RTX otherwise. */
6636 static bool
6638 {
6653 {
6654 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6666 {
6670 }
6671 }
6674 }
6676 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6677 storing it in *COST. Result is true if the total cost of the operation
6678 has now been calculated. */
6679 static bool
6681 {
6682 rtx inner;
6683 rtx comparator;
6687 {
6691 }
6692 else
6693 {
6697 }
6700 {
6701 /* Conditional branch. */
6704 else
6705 {
6707 {
6709 {
6710 /* TBZ/TBNZ/CBZ/CBNZ. */
6712 /* TBZ/TBNZ. */
6715 else
6716 /* CBZ/CBNZ. */
6720 }
6721 }
6723 {
6724 /* TBZ/TBNZ. */
6727 }
6728 }
6729 }
6731 {
6732 /* CCMP. */
6734 {
6735 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6739 {
6746 else
6748 }
6750 }
6752 /* It's a conditional operation based on the status flags,
6753 so it must be some flavor of CSEL. */
6755 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6761 {
6762 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6765 }
6770 }
6772 /* We don't know what this is, cost all operands. */
6774 }
6776 /* Check whether X is a bitfield operation of the form shift + extend that
6777 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6778 operand to which the bitfield operation is applied. Otherwise return
6779 NULL_RTX. */
6781 static rtx
6783 {
6797 {
6815 }
6818 }
6820 /* Return true if the mask and a shift amount from an RTX of the form
6821 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6822 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6824 bool
6826 {
6831 }
6833 /* Calculate the cost of calculating X, storing it in *COST. Result
6834 is true if the total cost of the operation has now been calculated. */
6835 static bool
6838 {
6844 /* By default, assume that everything has equivalent cost to the
6845 cheapest instruction. Any additional costs are applied as a delta
6846 above this default. */
6850 {
6852 /* The cost depends entirely on the operands to SET. */
6858 {
6861 {
6875 }
6884 /* Fall through. */
6886 /* The cost is one per vector-register copied. */
6888 {
6892 }
6893 /* const0_rtx is in general free, but we will use an
6894 instruction to set a register to 0. */
6896 {
6897 /* The cost is 1 per register copied. */
6901 }
6902 else
6903 /* Cost is just the cost of the RHS of the set. */
6909 /* Bit-field insertion. Strip any redundant widening of
6910 the RHS to meet the width of the target. */
6921 {
6922 /* MOV immediate is assumed to always be cheap. */
6924 }
6925 else
6926 {
6927 /* BFM. */
6931 }
6936 /* We can't make sense of this, assume default cost. */
6939 }
6943 /* If an instruction can incorporate a constant within the
6944 instruction, the instruction's expression avoids calling
6945 rtx_cost() on the constant. If rtx_cost() is called on a
6946 constant, then it is usually because the constant must be
6947 moved into a register by one or more instructions.
6949 The exception is constant 0, which can be expressed
6950 as XZR/WZR and is therefore free. The exception to this is
6951 if we have (set (reg) (const0_rtx)) in which case we must cost
6952 the move. However, we can catch that when we cost the SET, so
6953 we don't need to consider that here. */
6956 else
6957 {
6958 /* To an approximation, building any other constant is
6959 proportionally expensive to the number of instructions
6960 required to build that constant. This is true whether we
6961 are compiling for SPEED or otherwise. */
6964 }
6969 /* First determine number of instructions to do the move
6970 as an integer constant. */
6974 {
6985 }
6988 {
6989 /* mov[df,sf]_aarch64. */
6991 /* FMOV (scalar immediate). */
6994 {
6995 /* This will be a load from memory. */
6998 else
7000 }
7001 else
7002 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7003 or MOV v0.s[0], wzr - neither of which are modeled by the
7004 cost tables. Just use the default cost. */
7005 {
7006 }
7007 }
7013 {
7014 /* For loads we want the base cost of a load, plus an
7015 approximation for the additional cost of the addressing
7016 mode. */
7030 }
7038 {
7040 {
7041 /* FNEG. */
7043 }
7045 }
7048 {
7051 {
7052 /* CSETM. */
7055 }
7057 /* Cost this as SUB wzr, X. */
7061 }
7064 {
7065 /* Support (neg(fma...)) as a single instruction only if
7066 sign of zeros is unimportant. This matches the decision
7067 making in aarch64.md. */
7069 {
7070 /* FNMADD. */
7073 }
7075 {
7076 /* FNMUL. */
7079 }
7081 /* FNEG. */
7084 }
7091 {
7094 else
7096 }
7106 {
7110 }
7113 {
7114 /* TODO: A write to the CC flags possibly costs extra, this
7115 needs encoding in the cost tables. */
7118 /* ANDS. */
7120 {
7123 }
7126 {
7127 /* ADDS (and CMN alias). */
7130 }
7133 {
7134 /* SUBS. */
7137 }
7142 {
7143 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7144 Handle it here directly rather than going to cost_logic
7145 since we know the immediate generated for the TST is valid
7146 so we can avoid creating an intermediate rtx for it only
7147 for costing purposes. */
7154 }
7157 {
7158 /* CMN. */
7165 }
7167 /* CMP.
7169 Compare can freely swap the order of operands, and
7170 canonicalization puts the more complex operation first.
7171 But the integer MINUS logic expects the shift/extend
7172 operation in op1. */
7175 {
7178 }
7180 }
7183 {
7184 /* FCMP. */
7189 {
7191 /* FCMP supports constant 0.0 for no extra cost. */
7193 }
7195 }
7198 {
7199 /* Vector compare. */
7204 {
7205 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7206 cost. */
7208 }
7210 }
7214 {
7218 cost_minus:
7221 /* Detect valid immediates. */
7227 {
7229 /* SUB(S) (immediate). */
7232 }
7234 /* Look for SUB (extended register). */
7236 {
7244 }
7248 /* Cost this as an FMA-alike operation. */
7252 {
7255 speed);
7257 }
7262 {
7264 {
7265 /* Vector SUB. */
7267 }
7269 {
7270 /* SUB(S). */
7272 }
7274 {
7275 /* FSUB. */
7277 }
7278 }
7280 }
7283 {
7284 rtx new_op0;
7289 cost_plus:
7292 {
7293 /* CSINC. */
7297 }
7302 {
7306 /* ADD (immediate). */
7309 }
7313 /* Look for ADD (extended register). */
7315 {
7323 }
7325 /* Strip any extend, leave shifts behind as we will
7326 cost them through mult_cost. */
7331 {
7333 speed);
7335 }
7340 {
7342 {
7343 /* Vector ADD. */
7345 }
7347 {
7348 /* ADD. */
7350 }
7352 {
7353 /* FADD. */
7355 }
7356 }
7358 }
7364 {
7367 else
7369 }
7374 {
7378 {
7381 else
7383 }
7385 }
7388 {
7395 }
7396 /* Fall through. */
7399 cost_logic:
7404 {
7408 }
7416 {
7417 /* This is a UBFM/SBFM. */
7422 }
7425 {
7427 {
7428 /* We have a mask + shift version of a UBFIZ
7429 i.e. the *andim_ashift<mode>_bfiz pattern. */
7433 {
7440 }
7442 {
7443 /* We possibly get the immediate for free, this is not
7444 modelled. */
7450 }
7451 }
7452 else
7453 {
7456 /* Handle ORN, EON, or BIC. */
7462 /* If we had a shift on op0 then this is a logical-shift-
7463 by-register/immediate operation. Otherwise, this is just
7464 a logical operation. */
7466 {
7468 {
7469 /* Shift by immediate. */
7472 else
7474 }
7475 else
7477 }
7479 /* In both cases we want to cost both operands. */
7484 }
7485 }
7493 {
7494 /* Vector NOT. */
7497 }
7499 /* MVN-shifted-reg. */
7501 {
7508 }
7509 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7510 Handle the second form here taking care that 'a' in the above can
7511 be a shift. */
7513 {
7522 {
7525 else
7527 }
7530 }
7531 /* MVN. */
7540 /* If a value is written in SI mode, then zero extended to DI
7541 mode, the operation will in general be free as a write to
7542 a 'w' register implicitly zeroes the upper bits of an 'x'
7543 register. However, if this is
7545 (set (reg) (zero_extend (reg)))
7547 we must cost the explicit register move. */
7551 {
7554 /* If OP_COST is non-zero, then the cost of the zero extend
7555 is effectively the cost of the inner operation. Otherwise
7556 we have a MOV instruction and we take the cost from the MOV
7557 itself. This is true independently of whether we are
7558 optimizing for space or time. */
7563 }
7565 {
7566 /* All loads can zero extend to any size for free. */
7569 }
7573 {
7578 }
7581 {
7583 {
7584 /* UMOV. */
7586 }
7587 else
7588 {
7589 /* We generate an AND instead of UXTB/UXTH. */
7591 }
7592 }
7597 {
7598 /* LDRSH. */
7600 {
7607 }
7609 }
7613 {
7618 }
7621 {
7624 else
7626 }
7634 {
7636 {
7638 {
7639 /* Vector shift (immediate). */
7641 }
7642 else
7643 {
7644 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7645 aliases. */
7647 }
7648 }
7650 /* We can incorporate zero/sign extend for free. */
7657 }
7658 else
7659 {
7661 {
7663 /* Vector shift (register). */
7665 }
7666 else
7667 {
7669 /* LSLV. */
7675 {
7677 /* We already demanded XEXP (op1, 0) to be REG_P, so
7678 don't recurse into it. */
7680 }
7681 }
7683 }
7693 {
7694 /* ASR (immediate) and friends. */
7696 {
7699 else
7701 }
7705 }
7706 else
7707 {
7709 {
7711 /* Vector shift (register). */
7713 }
7714 else
7715 {
7717 /* ASR (register) and friends. */
7723 {
7725 /* We already demanded XEXP (op1, 0) to be REG_P, so
7726 don't recurse into it. */
7728 }
7729 }
7731 }
7737 {
7738 /* LDR. */
7741 }
7744 {
7745 /* ADRP, followed by ADD. */
7749 }
7752 {
7753 /* ADR. */
7756 }
7759 {
7760 /* One extra load instruction, after accessing the GOT. */
7764 }
7769 /* ADRP/ADD (immediate). */
7776 /* UBFX/SBFX. */
7778 {
7781 else
7783 }
7785 /* We can trust that the immediates used will be correct (there
7786 are no by-register forms), so we need only cost op0. */
7792 /* aarch64_rtx_mult_cost always handles recursion to its
7793 operands. */
7797 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7798 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7799 an unconditional negate. This case should only ever be reached through
7800 the set_smod_pow2_cheap check in expmed.c. */
7804 {
7805 /* We expand to 4 instructions. Reset the baseline. */
7813 }
7815 /* Fall-through. */
7818 {
7819 /* Slighly prefer UMOD over SMOD. */
7826 }
7833 {
7837 /* There is no integer SQRT, so only DIV and UDIV can get
7838 here. */
7840 /* Slighly prefer UDIV over SDIV. */
7842 else
7844 }
7870 {
7873 else
7875 }
7877 /* FMSUB, FNMADD, and FNMSUB are free. */
7884 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7885 and the by-element operand as operand 0. */
7889 /* Catch vector-by-element operations. The by-element operand can
7890 either be (vec_duplicate (vec_select (x))) or just
7891 (vec_select (x)), depending on whether we are multiplying by
7892 a vector or a scalar.
7894 Canonicalization is not very good in these cases, FMA4 will put the
7895 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7906 /* If the remaining parameters are not registers,
7907 get the cost to put them into registers. */
7921 {
7923 {
7924 /*Vector truncate. */
7926 }
7927 else
7929 }
7934 {
7936 {
7937 /*Vector conversion. */
7939 }
7940 else
7942 }
7948 /* Strip the rounding part. They will all be implemented
7949 by the fcvt* family of instructions anyway. */
7951 {
7960 }
7963 {
7966 else
7968 }
7970 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7971 fixed-point fcvt. */
7976 {
7980 }
7987 {
7988 /* ABS (vector). */
7991 }
7993 {
7996 /* FABD, which is analogous to FADD. */
7998 {
8005 }
8006 /* Simple FABS is analogous to FNEG. */
8009 }
8010 else
8011 {
8012 /* Integer ABS will either be split to
8013 two arithmetic instructions, or will be an ABS
8014 (scalar), which we don't model. */
8018 }
8024 {
8027 else
8028 {
8029 /* FMAXNM/FMINNM/FMAX/FMIN.
8030 TODO: This may not be accurate for all implementations, but
8031 we do not model this in the cost tables. */
8033 }
8034 }
8038 /* The floating point round to integer frint* instructions. */
8040 {
8045 }
8048 {
8053 }
8058 /* Decompose <su>muldi3_highpart. */
8060 mode == DImode
8061 /* (lshiftrt:TI */
8064 /* (mult:TI */
8066 /* (ANY_EXTEND:TI (reg:DI))
8067 (ANY_EXTEND:TI (reg:DI))) */
8074 /* (const_int 64) */
8077 {
8078 /* UMULH/SMULH. */
8086 }
8088 /* Fall through. */
8091 }
8099 }
8101 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8102 calculated for X. This cost is stored in *COST. Returns true
8103 if the total cost of X was calculated. */
8104 static bool
8107 {
8112 {
8117 }
8120 }
8122 static int
8125 {
8131 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8138 /* Moving between GPR and stack cost is the same as GP2GP. */
8143 /* To/From the stack register, we move via the gprs. */
8149 {
8150 /* 128-bit operations on general registers require 2 instructions. */
8158 /* When AdvSIMD instructions are disabled it is not possible to move
8159 a 128-bit value directly between Q registers. This is handled in
8160 secondary reload. A general register is used as a scratch to move
8161 the upper DI value and the lower DI value is moved directly,
8162 hence the cost is the sum of three moves. */
8167 }
8177 }
8179 static int
8181 reg_class_t rclass ATTRIBUTE_UNUSED,
8183 {
8185 }
8187 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8188 to optimize 1.0/sqrt. */
8190 static bool
8192 {
8194 && flag_unsafe_math_optimizations
8198 }
8200 /* Function to decide when to use the approximate reciprocal square root
8201 builtin. */
8203 static tree
8205 {
8211 }
8215 /* Select reciprocal square root initial estimate insn depending on machine
8216 mode. */
8218 static rsqrte_type
8220 {
8222 {
8229 }
8230 }
8234 /* Select reciprocal square root series step insn depending on machine mode. */
8236 static rsqrts_type
8238 {
8240 {
8247 }
8248 }
8250 /* Emit instruction sequence to compute either the approximate square root
8251 or its approximate reciprocal, depending on the flag RECP, and return
8252 whether the sequence was emitted or not. */
8254 bool
8256 {
8260 {
8263 }
8265 machine_mode mmsk
8269 {
8276 || flag_trapping_math
8277 || !flag_unsafe_math_optimizations
8280 }
8281 else
8282 /* Caller assumes we cannot fail. */
8288 /* When calculating the approximate square root, compare the
8289 argument with 0.0 and create a mask. */
8295 /* Estimate the approximate reciprocal square root. */
8299 /* Iterate over the series twice for SF and thrice for DF. */
8302 /* Optionally iterate over the series once less for faster performance
8303 while sacrificing the accuracy. */
8306 iterations--;
8308 /* Iterate over the series to calculate the approximate reciprocal square
8309 root. */
8312 {
8320 }
8323 {
8324 /* Qualify the approximate reciprocal square root when the argument is
8325 0.0 by squashing the intermediary result to 0.0. */
8331 /* Calculate the approximate square root. */
8333 }
8335 /* Finalize the approximation. */
8339 }
8343 /* Select reciprocal initial estimate insn depending on machine mode. */
8345 static recpe_type
8347 {
8349 {
8356 }
8357 }
8361 /* Select reciprocal series step insn depending on machine mode. */
8363 static recps_type
8365 {
8367 {
8374 }
8375 }
8377 /* Emit the instruction sequence to compute the approximation for the division
8378 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8380 bool
8382 {
8393 || flag_trapping_math
8394 || !flag_unsafe_math_optimizations
8399 /* Estimate the approximate reciprocal. */
8403 /* Iterate over the series twice for SF and thrice for DF. */
8406 /* Optionally iterate over the series once less for faster performance,
8407 while sacrificing the accuracy. */
8409 iterations--;
8411 /* Iterate over the series to calculate the approximate reciprocal. */
8414 {
8419 }
8422 {
8423 /* As the approximate reciprocal of DEN is already calculated, only
8424 calculate the approximate division when NUM is not 1.0. */
8427 }
8429 /* Finalize the approximation. */
8432 }
8434 /* Return the number of instructions that can be issued per cycle. */
8435 static int
8437 {
8439 }
8441 static int
8443 {
8447 }
8450 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8451 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8452 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8454 static int
8457 {
8459 }
8462 /* Vectorizer cost model target hooks. */
8464 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8465 static int
8467 tree vectype,
8469 {
8478 {
8527 }
8528 }
8530 /* Implement targetm.vectorize.add_stmt_cost. */
8531 static unsigned
8535 {
8540 {
8545 /* Statements in an inner loop relative to the loop being
8546 vectorized are weighted more heavily. The value here is
8547 arbitrary and could potentially be improved with analysis. */
8553 }
8556 }
8560 /* Parse the TO_PARSE string and put the architecture struct that it
8561 selects into RES and the architectural features into ISA_FLAGS.
8562 Return an aarch64_parse_opt_result describing the parse result.
8563 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8565 static enum aarch64_parse_opt_result
8568 {
8580 else
8587 /* Loop through the list of supported ARCHes to find a match. */
8589 {
8591 {
8595 {
8596 /* TO_PARSE string contains at least one extension. */
8597 enum aarch64_parse_opt_result ext_res
8602 }
8603 /* Extension parsing was successful. Confirm the result
8604 arch and ISA flags. */
8608 }
8609 }
8611 /* ARCH name not found in list. */
8613 }
8615 /* Parse the TO_PARSE string and put the result tuning in RES and the
8616 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8617 describing the parse result. If there is an error parsing, RES and
8618 ISA_FLAGS are left unchanged. */
8620 static enum aarch64_parse_opt_result
8623 {
8635 else
8642 /* Loop through the list of supported CPUs to find a match. */
8644 {
8646 {
8651 {
8652 /* TO_PARSE string contains at least one extension. */
8653 enum aarch64_parse_opt_result ext_res
8658 }
8659 /* Extension parsing was successfull. Confirm the result
8660 cpu and ISA flags. */
8664 }
8665 }
8667 /* CPU name not found in list. */
8669 }
8671 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8672 Return an aarch64_parse_opt_result describing the parse result.
8673 If the parsing fails the RES does not change. */
8675 static enum aarch64_parse_opt_result
8677 {
8683 /* Loop through the list of supported CPUs to find a match. */
8685 {
8687 {
8690 }
8691 }
8693 /* CPU name not found in list. */
8695 }
8697 /* Parse TOKEN, which has length LENGTH to see if it is an option
8698 described in FLAG. If it is, return the index bit for that fusion type.
8699 If not, error (printing OPTION_NAME) and return zero. */
8701 static unsigned int
8706 {
8708 {
8712 }
8716 }
8718 /* Parse OPTION which is a comma-separated list of flags to enable.
8719 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8720 default state we inherit from the CPU tuning structures. OPTION_NAME
8721 gives the top-level option we are parsing in the -moverride string,
8722 for use in error messages. */
8724 static unsigned int
8729 {
8736 {
8739 token_length,
8740 flags,
8741 option_name);
8742 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8743 in the token stream, reset the supported operations. So:
8745 adrp+add.cmp+branch.none.adrp+add
8747 would have the result of turning on only adrp+add fusion. */
8753 }
8755 /* We ended with a comma, print something. */
8757 {
8760 }
8762 /* We still have one more token to parse. */
8765 token_length,
8766 flags,
8767 option_name);
8773 }
8775 /* Support for overriding instruction fusion. */
8777 static void
8780 {
8782 aarch64_fusible_pairs,
8785 }
8787 /* Support for overriding other tuning flags. */
8789 static void
8792 {
8793 tune->extra_tuning_flags
8795 aarch64_tuning_flags,
8798 }
8800 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8801 we understand. If it is, extract the option string and handoff to
8802 the appropriate function. */
8804 void
8808 {
8814 {
8817 }
8819 /* Get the length of the option name. */
8821 /* Skip the '=' to get to the option string. */
8822 option_part++;
8825 {
8827 {
8830 }
8831 }
8835 }
8837 /* A checking mechanism for the implementation of the tls size. */
8839 static void
8841 {
8846 {
8848 /* Both the default and maximum TLS size allowed under tiny is 1M which
8849 needs two instructions to address, so we clamp the size to 24. */
8854 /* The maximum TLS size allowed under small is 4G. */
8859 /* The maximum TLS size allowed under large is 16E.
8860 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8866 }
8869 }
8871 /* Parse STRING looking for options in the format:
8872 string :: option:string
8873 option :: name=substring
8874 name :: {a-z}
8875 substring :: defined by option. */
8877 static void
8880 {
8891 {
8893 /* Make this substring look like a string. */
8897 }
8899 /* One last option to parse. */
8902 }
8905 static void
8907 {
8908 /* The logic here is that if we are disabling all frame pointer generation
8909 then we do not need to disable leaf frame pointer generation as a
8910 separate operation. But if we are *only* disabling leaf frame pointer
8911 generation then we set flag_omit_frame_pointer to true, but in
8912 aarch64_frame_pointer_required we return false only for leaf functions.
8914 PR 70044: We have to be careful about being called multiple times for the
8915 same function. Once we have decided to set flag_omit_frame_pointer just
8916 so that we can omit leaf frame pointers, we must then not interpret a
8917 second call as meaning that all frame pointer generation should be
8918 omitted. We do this by setting flag_omit_frame_pointer to a special,
8919 non-zero value. */
8928 /* If not optimizing for size, set the default
8929 alignment to what the target wants. */
8931 {
8938 }
8940 /* We default to no pc-relative literal loads. */
8944 /* If -mpc-relative-literal-loads is set on the command line, this
8945 implies that the user asked for PC relative literal loads. */
8949 /* This is PR70113. When building the Linux kernel with
8950 CONFIG_ARM64_ERRATUM_843419, support for relocations
8951 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8952 removed from the kernel to avoid loading objects with possibly
8953 offending sequences. Without -mpc-relative-literal-loads we would
8954 generate such relocations, preventing the kernel build from
8955 succeeding. */
8960 /* In the tiny memory model it makes no sense to disallow PC relative
8961 literal pool loads. */
8966 /* When enabling the lower precision Newton series for the square root, also
8967 enable it for the reciprocal square root, since the latter is an
8968 intermediary step for the former. */
8971 }
8973 /* 'Unpack' up the internal tuning structs and update the options
8974 in OPTS. The caller must have set up selected_tune and selected_arch
8975 as all the other target-specific codegen decisions are
8976 derived from them. */
8978 void
8980 {
8983 /* Make a copy of the tuning parameters attached to the core, which
8984 we may later overwrite. */
8992 /* This target defaults to strict volatile bitfields. */
9001 {
9013 }
9015 /* We don't mind passing in global_options_set here as we don't use
9016 the *options_set structs anyway. */
9018 queue_depth,
9022 /* Set up parameters to be used in prefetching algorithm. Do not
9023 override the defaults unless we are tuning for a core we have
9024 researched values for. */
9046 /* Enable sw prefetching at specified optimization level for
9047 CPUS that have prefetch. Lower optimization level threshold by 1
9048 when profiling is enabled. */
9056 }
9058 /* Print a hint with a suggestion for a core or architecture name that
9059 most closely resembles what the user passed in STR. ARCH is true if
9060 the user is asking for an architecture name. ARCH is false if the user
9061 is asking for a core name. */
9063 static void
9065 {
9076 }
9078 /* Print a hint with a suggestion for a core name that most closely resembles
9079 what the user passed in STR. */
9083 {
9085 }
9087 /* Print a hint with a suggestion for an architecture name that most closely
9088 resembles what the user passed in STR. */
9092 {
9094 }
9096 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9097 specified in STR and throw errors if appropriate. Put the results if
9098 they are valid in RES and ISA_FLAGS. Return whether the option is
9099 valid. */
9101 static bool
9104 {
9105 enum aarch64_parse_opt_result parse_res
9112 {
9125 }
9128 }
9130 /* Validate a command-line -march option. Parse the arch and extensions
9131 (if any) specified in STR and throw errors if appropriate. Put the
9132 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9133 option is valid. */
9135 static bool
9138 {
9139 enum aarch64_parse_opt_result parse_res
9146 {
9159 }
9162 }
9164 /* Validate a command-line -mtune option. Parse the cpu
9165 specified in STR and throw errors if appropriate. Put the
9166 result, if it is valid, in RES. Return whether the option is
9167 valid. */
9169 static bool
9171 {
9172 enum aarch64_parse_opt_result parse_res
9179 {
9189 }
9191 }
9193 /* Return the CPU corresponding to the enum CPU.
9194 If it doesn't specify a cpu, return the default. */
9198 {
9202 /* The & 0x3f is to extract the bottom 6 bits that encode the
9203 default cpu as selected by the --with-cpu GCC configure option
9204 in config.gcc.
9205 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9206 flags mechanism should be reworked to make it more sane. */
9208 }
9210 /* Return the architecture corresponding to the enum ARCH.
9211 If it doesn't specify a valid architecture, return the default. */
9215 {
9222 }
9224 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9225 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9226 tuning structs. In particular it must set selected_tune and
9227 aarch64_isa_flags that define the available ISA features and tuning
9228 decisions. It must also set selected_arch as this will be used to
9229 output the .arch asm tags for each function. */
9231 static void
9233 {
9246 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9247 If either of -march or -mtune is given, they override their
9248 respective component of -mcpu. */
9260 /* If the user did not specify a processor, choose the default
9261 one for them. This will be the CPU set during configuration using
9262 --with-cpu, otherwise it is "generic". */
9264 {
9266 {
9270 }
9271 else
9272 {
9273 /* Get default configure-time CPU. */
9276 }
9280 }
9281 /* If both -mcpu and -march are specified check that they are architecturally
9282 compatible, warn if they're not and prefer the -march ISA flags. */
9284 {
9286 {
9290 }
9295 }
9296 else
9297 {
9298 /* -mcpu but no -march. */
9305 }
9307 /* Set the arch as well as we will need it when outputing
9308 the .arch directive in assembly. */
9310 {
9313 }
9318 #ifndef HAVE_AS_MABI_OPTION
9319 /* The compiler may have been configured with 2.23.* binutils, which does
9320 not have support for ILP32. */
9323 #endif
9328 /* Make sure we properly set up the explicit options. */
9339 /* Save these options as the default ones in case we push and pop them later
9340 while processing functions with potential target attributes. */
9341 target_option_default_node = target_option_current_node
9343 }
9345 /* Implement targetm.override_options_after_change. */
9347 static void
9349 {
9351 }
9355 {
9359 }
9361 void
9363 {
9365 }
9367 /* A checking mechanism for the implementation of the various code models. */
9368 static void
9370 {
9372 {
9374 {
9379 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9381 ? AARCH64_CMODEL_SMALL_PIC
9383 #else
9385 #endif
9393 }
9394 }
9395 else
9397 }
9399 /* Implement TARGET_OPTION_SAVE. */
9401 static void
9403 {
9405 }
9407 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9408 using the information saved in PTR. */
9410 static void
9412 {
9420 }
9422 /* Implement TARGET_OPTION_PRINT. */
9424 static void
9426 {
9437 }
9441 void
9443 {
9445 }
9447 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9448 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9449 make sure optab availability predicates are recomputed when necessary. */
9451 void
9453 {
9458 else
9460 }
9462 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9463 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9464 of the function, if such exists. This function may be called multiple
9465 times on a single function so use aarch64_previous_fndecl to avoid
9466 setting up identical state. */
9468 static void
9470 {
9474 tree old_tree = (aarch64_previous_fndecl
9480 /* If current function has no attributes but the previous one did,
9481 use the default node. */
9485 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9486 the default have been handled by aarch64_save_restore_target_globals from
9487 aarch64_pragma_target_parse. */
9493 /* First set the target options. */
9497 }
9499 /* Enum describing the various ways we can handle attributes.
9500 In many cases we can reuse the generic option handling machinery. */
9502 enum aarch64_attr_opt_type
9503 {
9507 aarch64_attr_custom /* Attribute requires a custom handling function. */
9508 };
9510 /* All the information needed to handle a target attribute.
9511 NAME is the name of the attribute.
9512 ATTR_TYPE specifies the type of behavior of the attribute as described
9513 in the definition of enum aarch64_attr_opt_type.
9514 ALLOW_NEG is true if the attribute supports a "no-" form.
9515 HANDLER is the function that takes the attribute string and whether
9516 it is a pragma or attribute and handles the option. It is needed only
9517 when the ATTR_TYPE is aarch64_attr_custom.
9518 OPT_NUM is the enum specifying the option that the attribute modifies.
9519 This is needed for attributes that mirror the behavior of a command-line
9520 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9521 aarch64_attr_enum. */
9523 struct aarch64_attribute_info
9524 {
9530 };
9532 /* Handle the ARCH_STR argument to the arch= target attribute.
9533 PRAGMA_OR_ATTR is used in potential error messages. */
9535 static bool
9537 {
9539 enum aarch64_parse_opt_result parse_res
9543 {
9548 }
9551 {
9565 }
9568 }
9570 /* Handle the argument CPU_STR to the cpu= target attribute.
9571 PRAGMA_OR_ATTR is used in potential error messages. */
9573 static bool
9575 {
9577 enum aarch64_parse_opt_result parse_res
9581 {
9589 }
9592 {
9606 }
9609 }
9611 /* Handle the argument STR to the tune= target attribute.
9612 PRAGMA_OR_ATTR is used in potential error messages. */
9614 static bool
9616 {
9618 enum aarch64_parse_opt_result parse_res
9622 {
9627 }
9630 {
9637 }
9640 }
9642 /* Parse an architecture extensions target attribute string specified in STR.
9643 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9644 if successful. Update aarch64_isa_flags to reflect the ISA features
9645 modified.
9646 PRAGMA_OR_ATTR is used in potential error messages. */
9648 static bool
9650 {
9654 /* We allow "+nothing" in the beginning to clear out all architectural
9655 features if the user wants to handpick specific features. */
9657 {
9660 }
9665 {
9668 }
9671 {
9684 }
9687 }
9689 /* The target attributes that we support. On top of these we also support just
9690 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9691 handled explicitly in aarch64_process_one_target_attr. */
9694 {
9696 OPT_mgeneral_regs_only },
9698 OPT_mfix_cortex_a53_835769 },
9700 OPT_mfix_cortex_a53_843419 },
9704 OPT_momit_leaf_frame_pointer },
9707 OPT_march_ },
9710 OPT_mtune_ },
9712 OPT_msign_return_address_ },
9714 };
9716 /* Parse ARG_STR which contains the definition of one target attribute.
9717 Show appropriate errors if any or return true if the attribute is valid.
9718 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9719 we're processing a target attribute or pragma. */
9721 static bool
9723 {
9729 {
9732 }
9737 /* Skip leading whitespace. */
9739 str_to_check++;
9741 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9742 It is easier to detect and handle it explicitly here rather than going
9743 through the machinery for the rest of the target attributes in this
9744 function. */
9749 {
9752 }
9755 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9756 and point ARG to "foo". */
9758 {
9760 arg++;
9761 }
9765 {
9766 /* If the names don't match up, or the user has given an argument
9767 to an attribute that doesn't accept one, or didn't give an argument
9768 to an attribute that expects one, fail to match. */
9777 {
9781 }
9783 /* If the name matches but the attribute does not allow "no-" versions
9784 then we can't match. */
9786 {
9790 }
9793 {
9794 /* Has a custom handler registered.
9795 For example, cpu=, arch=, tune=. */
9802 /* Either set or unset a boolean option. */
9804 {
9812 }
9813 /* Set or unset a bit in the target_flags. aarch64_handle_option
9814 should know what mask to apply given the option number. */
9816 {
9818 /* We only need to specify the option number.
9819 aarch64_handle_option will know which mask to apply. */
9825 }
9826 /* Use the option setting machinery to set an option to an enum. */
9828 {
9835 {
9838 global_dc);
9839 }
9840 else
9841 {
9844 }
9846 }
9849 }
9850 }
9852 /* If we reached here we either have found an attribute and validated
9853 it or didn't match any. If we matched an attribute but its arguments
9854 were malformed we will have returned false already. */
9856 }
9858 /* Count how many times the character C appears in
9859 NULL-terminated string STR. */
9861 static unsigned int
9863 {
9866 {
9868 res++;
9870 str++;
9871 }
9874 }
9876 /* Parse the tree in ARGS that contains the target attribute information
9877 and update the global target options space. PRAGMA_OR_ATTR is a string
9878 to be used in error messages, specifying whether this is processing
9879 a target attribute or a target pragma. */
9881 bool
9883 {
9885 {
9886 do
9887 {
9890 {
9893 }
9898 }
9901 {
9904 }
9911 {
9914 }
9916 /* Used to catch empty spaces between commas i.e.
9917 attribute ((target ("attr1,,attr2"))). */
9920 /* Handle multiple target attributes separated by ','. */
9925 {
9926 num_attrs++;
9928 {
9931 }
9934 }
9937 {
9941 }
9944 }
9946 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9947 process attribute ((target ("..."))). */
9949 static bool
9951 {
9954 tree old_optimize;
9958 /* If what we're processing is the current pragma string then the
9959 target option node is already stored in target_option_current_node
9960 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9961 having to re-parse the string. This is especially useful to keep
9962 arm_neon.h compile times down since that header contains a lot
9963 of intrinsics enclosed in pragmas. */
9965 {
9968 }
9974 /* If the function changed the optimization levels as well as setting
9975 target options, start with the optimizations specified. */
9980 /* Save the current target options to restore at the end. */
9983 /* If fndecl already has some target attributes applied to it, unpack
9984 them so that we add this attribute on top of them, rather than
9985 overwriting them. */
9987 {
9993 }
9994 else
10001 /* Set up any additional state. */
10003 {
10005 /* Initialize SIMD builtins if we haven't already.
10006 Set current_target_pragma to NULL for the duration so that
10007 the builtin initialization code doesn't try to tag the functions
10008 being built with the attributes specified by any current pragma, thus
10009 going into an infinite recursion. */
10011 {
10016 }
10018 }
10019 else
10025 {
10030 }
10038 }
10040 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10041 tri-bool options (yes, no, don't care) and the default value is
10042 DEF, determine whether to reject inlining. */
10044 static bool
10047 {
10048 /* If the callee doesn't care, always allow inlining. */
10052 /* If the caller doesn't care, always allow inlining. */
10056 /* Otherwise, allow inlining if either the callee and caller values
10057 agree, or if the callee is using the default value. */
10059 }
10061 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10062 to inline CALLEE into CALLER based on target-specific info.
10063 Make sure that the caller and callee have compatible architectural
10064 features. Then go through the other possible target attributes
10065 and see if they can block inlining. Try not to reject always_inline
10066 callees unless they are incompatible architecturally. */
10068 static bool
10070 {
10074 /* If callee has no option attributes, then it is ok to inline. */
10085 /* Callee's ISA flags should be a subset of the caller's. */
10090 /* Allow non-strict aligned functions inlining into strict
10091 aligned ones. */
10101 /* If the architectural features match up and the callee is always_inline
10102 then the other attributes don't matter. */
10114 /* Honour explicit requests to workaround errata. */
10127 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10128 caller and calle and they don't match up, reject inlining. */
10135 /* If the callee has specific tuning overrides, respect them. */
10140 /* If the user specified tuning override strings for the
10141 caller and callee and they don't match up, reject inlining.
10142 We just do a string compare here, we don't analyze the meaning
10143 of the string, as it would be too costly for little gain. */
10151 }
10153 /* Return true if SYMBOL_REF X binds locally. */
10155 static bool
10157 {
10161 }
10163 /* Return true if SYMBOL_REF X is thread local */
10164 static bool
10166 {
10174 }
10176 /* Classify a TLS symbol into one of the TLS kinds. */
10177 enum aarch64_symbol_type
10179 {
10183 {
10190 {
10196 }
10207 else
10216 }
10217 }
10219 /* Return the method that should be used to access SYMBOL_REF or
10220 LABEL_REF X. */
10222 enum aarch64_symbol_type
10224 {
10226 {
10228 {
10243 }
10244 }
10247 {
10252 {
10254 /* When we retrieve symbol + offset address, we have to make sure
10255 the offset does not cause overflow of the final address. But
10256 we have no way of knowing the address of symbol at compile time
10257 so we can't accurately say if the distance between the PC and
10258 symbol + offset is outside the addressible range of +/-1M in the
10259 TINY code model. So we rely on images not being greater than
10260 1M and cap the offset at 1M and anything beyond 1M will have to
10261 be loaded using an alternative mechanism. Furthermore if the
10262 symbol is a weak reference to something that isn't known to
10263 resolve to a symbol in this module, then force to memory. */
10271 /* Same reasoning as the tiny code model, but the offset cap here is
10272 4G. */
10293 /* This is alright even in PIC code as the constant
10294 pool reference is always PC relative and within
10295 the same translation unit. */
10298 else
10303 }
10304 }
10306 /* By default push everything into the constant pool. */
10308 }
10310 bool
10312 {
10314 }
10316 bool
10318 {
10326 }
10328 /* Return true if X holds either a quarter-precision or
10329 floating-point +0.0 constant. */
10330 static bool
10332 {
10336 /* This call determines which constants can be used in mov<mode>
10337 as integer moves instead of constant loads. */
10342 }
10344 static bool
10346 {
10347 /* Do not allow vector struct mode constants. We could support
10348 0 and -1 easily, but they need support in aarch64-simd.md. */
10352 /* For these cases we never want to use a literal load.
10353 As such we have to prevent the compiler from forcing these
10354 to memory. */
10367 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10368 so spilling them is better than rematerialization. */
10373 }
10375 rtx
10377 {
10383 /* Can return in any reg. */
10386 }
10388 /* On AAPCS systems, this is the "struct __va_list". */
10391 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10392 Return the type to use as __builtin_va_list.
10394 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10396 struct __va_list
10397 {
10398 void *__stack;
10399 void *__gr_top;
10400 void *__vr_top;
10401 int __gr_offs;
10402 int __vr_offs;
10403 }; */
10405 static tree
10407 {
10408 tree va_list_name;
10411 /* Create the type. */
10413 /* Give it the required name. */
10415 TYPE_DECL,
10417 va_list_type);
10422 /* Create the fields. */
10425 ptr_type_node);
10428 ptr_type_node);
10431 ptr_type_node);
10434 integer_type_node);
10437 integer_type_node);
10439 /* Tell tree-stdarg pass about our internal offset fields.
10440 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10441 purpose to identify whether the code is updating va_list internal
10442 offset fields through irregular way. */
10464 /* Compute its layout. */
10468 }
10470 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10471 static void
10473 {
10477 tree t;
10491 {
10494 }
10503 NULL_TREE);
10505 NULL_TREE);
10507 NULL_TREE);
10509 NULL_TREE);
10511 NULL_TREE);
10513 /* Emit code to initialize STACK, which points to the next varargs stack
10514 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10515 by named arguments. STACK is 8-byte aligned. */
10522 /* Emit code to initialize GRTOP, the top of the GR save area.
10523 virtual_incoming_args_rtx should have been 16 byte aligned. */
10528 /* Emit code to initialize VRTOP, the top of the VR save area.
10529 This address is gr_save_area_bytes below GRTOP, rounded
10530 down to the next 16-byte boundary. */
10540 /* Emit code to initialize GROFF, the offset from GRTOP of the
10541 next GPR argument. */
10546 /* Likewise emit code to initialize VROFF, the offset from FTOP
10547 of the next VR argument. */
10551 }
10553 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10555 static tree
10558 {
10559 tree addr;
10565 machine_mode mode;
10592 type,
10596 {
10597 /* TYPE passed in fp/simd registers. */
10609 {
10612 }
10615 {
10617 }
10618 }
10619 else
10620 {
10621 /* TYPE passed in general registers. */
10634 {
10636 }
10637 }
10639 /* Get a local temporary for the field value. */
10642 /* Emit code to branch if off >= 0. */
10648 {
10649 /* Emit: offs = (offs + 15) & -16. */
10655 }
10656 else
10659 /* Update ap.__[g|v]r_offs */
10664 /* String up. */
10668 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10673 /* String up: make sure the assignment happens before the use. */
10677 /* Prepare the trees handling the argument that is passed on the stack;
10678 the top level node will store in ON_STACK. */
10681 {
10682 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10690 }
10691 else
10693 /* Advance ap.__stack */
10701 /* String up roundup and advance. */
10704 /* String up with arg */
10706 /* Big-endianness related address adjustment. */
10709 {
10713 }
10718 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10728 {
10729 /* type ha; // treat as "struct {ftype field[n];}"
10730 ... [computing offs]
10731 for (i = 0; i <nregs; ++i, offs += 16)
10732 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10733 return ha; */
10737 /* Declare a local variable. */
10741 /* Establish the base type. */
10743 {
10762 {
10766 }
10770 }
10772 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10780 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10782 {
10792 }
10796 }
10806 }
10808 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10810 static void
10814 {
10816 CUMULATIVE_ARGS local_cum;
10820 /* The caller has advanced CUM up to, but not beyond, the last named
10821 argument. Advance a local copy of CUM past the last "real" named
10822 argument, to find out how many registers are left over. */
10826 /* Found out how many registers we need to save.
10827 Honor tree-stdvar analysis results. */
10836 {
10839 }
10842 {
10844 {
10847 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10855 }
10857 {
10858 /* We can't use move_block_from_reg, because it will use
10859 the wrong mode, storing D regs only. */
10863 /* Set OFF to the offset from virtual_incoming_args_rtx of
10864 the first vector register. The VR save area lies below
10865 the GR one, and is aligned to 16 bytes. */
10872 {
10880 }
10881 }
10882 }
10884 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10885 any complication of having crtl->args.pretend_args_size changed. */
10890 }
10892 static void
10894 {
10897 {
10899 {
10902 }
10903 }
10904 }
10906 /* Walk down the type tree of TYPE counting consecutive base elements.
10907 If *MODEP is VOIDmode, then set it to the first valid floating point
10908 type. If a non-floating point type is found, or if a floating point
10909 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10910 otherwise return the count in the sub-tree. */
10911 static int
10913 {
10914 machine_mode mode;
10915 HOST_WIDE_INT size;
10918 {
10948 /* Use V2SImode and V4SImode as representatives of all 64-bit
10949 and 128-bit vector types. */
10952 {
10961 }
10966 /* Vector modes are considered to be opaque: two vectors are
10967 equivalent for the purposes of being homogeneous aggregates
10968 if they are the same size. */
10975 {
10979 /* Can't handle incomplete types nor sizes that are not
10980 fixed. */
10987 || !index
10998 /* There must be no padding. */
11003 }
11006 {
11009 tree field;
11011 /* Can't handle incomplete types nor sizes that are not
11012 fixed. */
11018 {
11026 }
11028 /* There must be no padding. */
11033 }
11037 {
11038 /* These aren't very interesting except in a degenerate case. */
11041 tree field;
11043 /* Can't handle incomplete types nor sizes that are not
11044 fixed. */
11050 {
11058 }
11060 /* There must be no padding. */
11065 }
11069 }
11072 }
11074 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11075 type as described in AAPCS64 \S 4.1.2.
11077 See the comment above aarch64_composite_type_p for the notes on MODE. */
11079 static bool
11081 machine_mode mode)
11082 {
11092 }
11094 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11095 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11096 array types. The C99 floating-point complex types are also considered
11097 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11098 types, which are GCC extensions and out of the scope of AAPCS64, are
11099 treated as composite types here as well.
11101 Note that MODE itself is not sufficient in determining whether a type
11102 is such a composite type or not. This is because
11103 stor-layout.c:compute_record_mode may have already changed the MODE
11104 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11105 structure with only one field may have its MODE set to the mode of the
11106 field. Also an integer mode whose size matches the size of the
11107 RECORD_TYPE type may be used to substitute the original mode
11108 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11109 solely relied on. */
11111 static bool
11113 machine_mode mode)
11114 {
11127 }
11129 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11130 shall be passed or returned in simd/fp register(s) (providing these
11131 parameter passing registers are available).
11133 Upon successful return, *COUNT returns the number of needed registers,
11134 *BASE_MODE returns the mode of the individual register and when IS_HAF
11135 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11136 floating-point aggregate or a homogeneous short-vector aggregate. */
11138 static bool
11140 const_tree type,
11144 {
11152 {
11155 }
11157 {
11161 }
11163 {
11167 {
11170 }
11171 else
11173 }
11174 else
11179 }
11181 /* Implement TARGET_STRUCT_VALUE_RTX. */
11183 static rtx
11186 {
11188 }
11190 /* Implements target hook vector_mode_supported_p. */
11191 static bool
11193 {
11205 }
11207 /* Return appropriate SIMD container
11208 for MODE within a vector of WIDTH bits. */
11209 static machine_mode
11211 {
11214 {
11217 {
11234 }
11235 else
11237 {
11250 }
11251 }
11253 }
11255 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11256 static machine_mode
11258 {
11260 }
11262 /* Return the bitmask of possible vector sizes for the vectorizer
11263 to iterate over. */
11264 static unsigned int
11266 {
11268 }
11270 /* Implement TARGET_MANGLE_TYPE. */
11274 {
11275 /* The AArch64 ABI documents say that "__va_list" has to be
11276 managled as if it is in the "std" namespace. */
11280 /* Half-precision float. */
11284 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11285 builtin types. */
11289 /* Use the default mangling. */
11291 }
11293 /* Find the first rtx_insn before insn that will generate an assembly
11294 instruction. */
11298 {
11302 do
11303 {
11305 }
11309 }
11311 static bool
11313 {
11315 /* A number of these may be AArch32 only. */
11320 };
11323 {
11326 }
11329 }
11331 /* Check if there is a register dependency between a load and the insn
11332 for which we hold recog_data. */
11334 static bool
11336 {
11337 rtx load_reg;
11347 {
11353 }
11355 }
11358 /* When working around the Cortex-A53 erratum 835769,
11359 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11360 instruction and has a preceding memory instruction such that a NOP
11361 should be inserted between them. */
11363 bool
11365 {
11368 rtx body;
11381 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11382 Restore recog state to INSN to avoid state corruption. */
11390 /* If the previous insn is a memory op and there is no dependency between
11391 it and the DImode madd, emit a NOP between them. If body is NULL then we
11392 have a complex memory operation, probably a load/store pair.
11393 Be conservative for now and emit a NOP. */
11400 }
11403 /* Implement FINAL_PRESCAN_INSN. */
11405 void
11407 {
11410 }
11413 /* Return the equivalent letter for size. */
11414 static char
11416 {
11418 {
11424 }
11425 }
11427 /* Return true iff x is a uniform vector of floating-point
11428 constants, and the constant can be represented in
11429 quarter-precision form. Note, as aarch64_float_const_representable
11430 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11431 static bool
11433 {
11434 rtx elt;
11438 }
11440 /* Return true for valid and false for invalid. */
11441 bool
11444 {
11445 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11446 matches = 1; \
11447 for (i = 0; i < idx; i += (STRIDE)) \
11448 if (!(TEST)) \
11449 matches = 0; \
11450 if (matches) \
11451 { \
11452 immtype = (CLASS); \
11453 elsize = (ELSIZE); \
11454 eshift = (SHIFT); \
11455 emvn = (NEG); \
11456 break; \
11457 }
11467 {
11473 {
11478 }
11481 }
11483 /* Splat vector constant out into a byte vector. */
11485 {
11486 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11487 it must be laid out in the vector register in reverse order. */
11495 {
11498 }
11500 }
11502 /* Sanity check. */
11505 do
11506 {
11555 }
11562 {
11572 /* Un-invert bytes of recognized vector, if necessary. */
11578 {
11579 /* FIXME: Broken on 32-bit H_W_I hosts. */
11588 }
11589 else
11590 {
11594 /* Construct 'abcdefgh' because the assembler cannot handle
11595 generic constants. */
11600 }
11601 }
11604 #undef CHECK
11605 }
11607 /* Check of immediate shift constants are within range. */
11608 bool
11610 {
11614 else
11616 }
11618 /* Return true if X is a uniform vector where all elements
11619 are either the floating-point constant 0.0 or the
11620 integer constant 0. */
11621 bool
11623 {
11625 }
11628 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11629 operation of width WIDTH at bit position POS. */
11631 rtx
11633 {
11637 unsigned HOST_WIDE_INT mask
11640 }
11642 bool
11644 {
11657 }
11659 /* Return a const_int vector of VAL. */
11660 rtx
11662 {
11673 }
11675 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11677 bool
11679 {
11680 machine_mode vmode;
11686 }
11688 /* Construct and return a PARALLEL RTX vector with elements numbering the
11689 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11690 the vector - from the perspective of the architecture. This does not
11691 line up with GCC's perspective on lane numbers, so we end up with
11692 different masks depending on our target endian-ness. The diagram
11693 below may help. We must draw the distinction when building masks
11694 which select one half of the vector. An instruction selecting
11695 architectural low-lanes for a big-endian target, must be described using
11696 a mask selecting GCC high-lanes.
11698 Big-Endian Little-Endian
11700 GCC 0 1 2 3 3 2 1 0
11701 | x | x | x | x | | x | x | x | x |
11702 Architecture 3 2 1 0 3 2 1 0
11704 Low Mask: { 2, 3 } { 0, 1 }
11705 High Mask: { 0, 1 } { 2, 3 }
11706 */
11708 rtx
11710 {
11716 rtx t1;
11721 else
11729 }
11731 /* Check OP for validity as a PARALLEL RTX vector with elements
11732 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11733 from the perspective of the architecture. See the diagram above
11734 aarch64_simd_vect_par_cnst_half for more details. */
11736 bool
11739 {
11752 {
11759 }
11761 }
11763 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11764 HIGH (exclusive). */
11765 void
11767 const_tree exp)
11768 {
11769 HOST_WIDE_INT lane;
11774 {
11777 else
11779 }
11780 }
11782 /* Return TRUE if OP is a valid vector addressing mode. */
11783 bool
11785 {
11788 }
11790 /* Emit a register copy from operand to operand, taking care not to
11791 early-clobber source registers in the process.
11793 COUNT is the number of components into which the copy needs to be
11794 decomposed. */
11795 void
11798 {
11808 else
11812 }
11814 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11815 one of VSTRUCT modes: OI, CI, or XI. */
11816 int
11818 {
11820 }
11822 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11823 alignment of a vector to 128 bits. */
11824 static HOST_WIDE_INT
11826 {
11829 }
11831 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11832 static bool
11834 {
11838 /* We guarantee alignment for vectors up to 128-bits. */
11843 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11845 }
11847 /* Return true if the vector misalignment factor is supported by the
11848 target. */
11849 static bool
11853 {
11855 {
11856 /* Return if movmisalign pattern is not supported for this mode. */
11861 {
11862 /* Misalignment factor is unknown at compile time but we know
11863 it's word aligned. */
11865 {
11870 }
11872 }
11873 }
11875 is_packed);
11876 }
11878 /* If VALS is a vector constant that can be loaded into a register
11879 using DUP, generate instructions to do so and return an RTX to
11880 assign to the register. Otherwise return NULL_RTX. */
11881 static rtx
11883 {
11886 rtx x;
11891 /* We can load this constant by using DUP and a constant in a
11892 single ARM register. This will be cheaper than a vector
11893 load. */
11896 }
11899 /* Generate code to load VALS, which is a PARALLEL containing only
11900 constants (for vec_init) or CONST_VECTOR, efficiently into a
11901 register. Returns an RTX to copy into the register, or NULL_RTX
11902 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11903 static rtx
11905 {
11907 rtx const_dup;
11916 {
11917 /* A CONST_VECTOR must contain only CONST_INTs and
11918 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11919 Only store valid constants in a CONST_VECTOR. */
11921 {
11924 n_const++;
11925 }
11928 }
11929 else
11934 /* Load using MOVI/MVNI. */
11937 /* Loaded using DUP. */
11940 /* Load from constant pool. We can not take advantage of single-cycle
11941 LD1 because we need a PC-relative addressing mode. */
11943 else
11944 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11945 We can not construct an initializer. */
11947 }
11949 /* Expand a vector initialisation sequence, such that TARGET is
11950 initialised to contain VALS. */
11952 void
11954 {
11957 /* The number of vector elements. */
11959 /* The number of vector elements which are not constant. */
11962 /* The first element of vals. */
11966 /* Count the number of variable elements to initialise. */
11968 {
11972 else
11976 }
11978 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11979 how best to handle this. */
11981 {
11984 {
11987 }
11988 }
11990 /* Splat a single non-constant element if we can. */
11992 {
11996 }
12001 /* If there are only variable elements, try to optimize
12002 the insertion using dup for the most common element
12003 followed by insertions. */
12005 /* The algorithm will fill matches[*][0] with the earliest matching element,
12006 and matches[X][1] with the count of duplicate elements (if X is the
12007 earliest element which has duplicates). */
12010 {
12013 {
12015 {
12017 {
12021 }
12022 }
12023 }
12028 {
12031 }
12033 /* Create a duplicate of the most common element. */
12037 /* Insert the rest. */
12039 {
12045 }
12047 }
12049 /* Initialise a vector which is part-variable. We want to first try
12050 to build those lanes which are constant in the most efficient way we
12051 can. */
12053 {
12056 /* Load constant part of vector. We really don't care what goes into the
12057 parts we will overwrite, but we're more likely to be able to load the
12058 constant efficiently if it has fewer, larger, repeating parts
12059 (see aarch64_simd_valid_immediate). */
12061 {
12067 {
12068 /* Look in the copied vector, as more elements are const. */
12071 {
12074 }
12075 }
12077 }
12079 }
12081 /* Insert the variable lanes directly. */
12083 {
12089 }
12090 }
12092 static unsigned HOST_WIDE_INT
12094 {
12095 return
12096 (!SHIFT_COUNT_TRUNCATED
12099 }
12101 /* Select a format to encode pointers in exception handling data. */
12102 int
12104 {
12107 {
12113 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12114 for everything. */
12118 /* No assumptions here. 8-byte relocs required. */
12121 }
12123 }
12125 /* The last .arch and .tune assembly strings that we printed. */
12129 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12130 by the function fndecl. */
12132 void
12134 tree fndecl)
12135 {
12141 else
12152 /* Only update the assembler .arch string if it is distinct from the last
12153 such string we printed. */
12156 {
12159 }
12161 /* Print the cpu name we're tuning for in the comments, might be
12162 useful to readers of the generated asm. Do it only when it changes
12163 from function to function and verbose assembly is requested. */
12168 {
12172 }
12174 /* Don't forget the type directive for ELF. */
12177 }
12179 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12181 static void
12183 {
12200 }
12202 /* Emit load exclusive. */
12204 static void
12207 {
12211 {
12218 }
12221 }
12223 /* Emit store exclusive. */
12225 static void
12228 {
12232 {
12239 }
12242 }
12244 /* Mark the previous jump instruction as unlikely. */
12246 static void
12248 {
12251 }
12253 /* Expand a compare and swap pattern. */
12255 void
12257 {
12262 gen_cas_fn gen;
12264 {
12265 gen_aarch64_compare_and_swapqi,
12266 gen_aarch64_compare_and_swaphi,
12267 gen_aarch64_compare_and_swapsi,
12268 gen_aarch64_compare_and_swapdi
12269 };
12271 {
12272 gen_aarch64_compare_and_swapqi_lse,
12273 gen_aarch64_compare_and_swaphi_lse,
12274 gen_aarch64_compare_and_swapsi_lse,
12275 gen_aarch64_compare_and_swapdi_lse
12276 };
12289 /* Normally the succ memory model must be stronger than fail, but in the
12290 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12291 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12298 {
12301 /* For short modes, we're going to perform the comparison in SImode,
12302 so do the zero-extension now. */
12306 /* Fall through. */
12310 /* Force the value into a register if needed. */
12317 }
12320 {
12327 }
12330 else
12341 }
12343 /* Test whether the target supports using a atomic load-operate instruction.
12344 CODE is the operation and AFTER is TRUE if the data in memory after the
12345 operation should be returned and FALSE if the data before the operation
12346 should be returned. Returns FALSE if the operation isn't supported by the
12347 architecture. */
12349 bool
12351 {
12356 {
12366 }
12367 }
12369 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12370 sequence implementing an atomic operation. */
12372 static void
12374 {
12381 {
12383 }
12384 }
12386 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12387 for the data in memory. EXPECTED is the value expected to be in memory.
12388 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12389 is the memory ordering to use. */
12391 void
12394 rtx model)
12395 {
12397 machine_mode mode;
12402 {
12409 }
12411 /* Move the expected value into the CAS destination register. */
12414 /* Emit the CAS. */
12417 /* Compare the expected value with the value loaded by the CAS, to establish
12418 whether the swap was made. */
12420 }
12422 /* Split a compare and swap pattern. */
12424 void
12426 {
12428 machine_mode mode;
12433 rtx model_rtx;
12445 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12446 loop:
12447 .label1:
12448 LD[A]XR rval, [mem]
12449 CBNZ rval, .label2
12450 ST[L]XR scratch, newval, [mem]
12451 CBNZ scratch, .label1
12452 .label2:
12453 CMP rval, 0. */
12458 {
12461 }
12464 /* The initial load can be relaxed for a __sync operation since a final
12465 barrier will be emitted to stop code hoisting. */
12469 else
12473 {
12478 }
12479 else
12480 {
12486 }
12491 {
12496 }
12497 else
12498 {
12502 }
12505 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12506 to set the condition flags. If this is not used it will be removed by
12507 later passes. */
12509 {
12513 }
12514 /* Emit any final barrier needed for a __sync operation. */
12517 }
12519 /* Emit a BIC instruction. */
12521 static void
12523 {
12528 {
12533 }
12536 }
12538 /* Emit an atomic swap. */
12540 static void
12543 {
12547 {
12554 }
12557 }
12559 /* Operations supported by aarch64_emit_atomic_load_op. */
12561 enum aarch64_atomic_load_op_code
12562 {
12566 AARCH64_LDOP_BIC /* A & ~B */
12567 };
12569 /* Emit an atomic load-operate. */
12571 static void
12575 {
12578 {
12579 gen_aarch64_atomic_loadaddqi,
12580 gen_aarch64_atomic_loadaddhi,
12581 gen_aarch64_atomic_loadaddsi,
12582 gen_aarch64_atomic_loadadddi
12583 };
12585 {
12586 gen_aarch64_atomic_loadeorqi,
12587 gen_aarch64_atomic_loadeorhi,
12588 gen_aarch64_atomic_loadeorsi,
12589 gen_aarch64_atomic_loadeordi
12590 };
12592 {
12593 gen_aarch64_atomic_loadsetqi,
12594 gen_aarch64_atomic_loadsethi,
12595 gen_aarch64_atomic_loadsetsi,
12596 gen_aarch64_atomic_loadsetdi
12597 };
12599 {
12600 gen_aarch64_atomic_loadclrqi,
12601 gen_aarch64_atomic_loadclrhi,
12602 gen_aarch64_atomic_loadclrsi,
12603 gen_aarch64_atomic_loadclrdi
12604 };
12605 aarch64_atomic_load_op_fn gen;
12609 {
12616 }
12619 {
12626 }
12629 }
12631 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12632 location to store the data read from memory. OUT_RESULT is the location to
12633 store the result of the operation. MEM is the memory location to read and
12634 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12635 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12636 be NULL. */
12638 void
12641 {
12645 aarch64_atomic_load_op_code ldop_code;
12646 rtx src;
12647 rtx x;
12655 /* Make sure the value is in a register, putting it into a destination
12656 register if it needs to be manipulated. */
12659 {
12662 }
12663 else
12667 /* Preprocess the data for the operation as necessary. If the operation is
12668 a SET then emit a swap instruction and finish. */
12670 {
12676 /* Negate the value and treat it as a PLUS. */
12677 {
12678 rtx neg_src;
12680 /* Resize the value if necessary. */
12689 }
12690 /* Fall-through. */
12704 {
12705 rtx not_src;
12707 /* Resize the value if necessary. */
12716 }
12721 /* The operation can't be done with atomic instructions. */
12723 }
12727 /* If necessary, calculate the data in memory after the update by redoing the
12728 operation from values in registers. */
12733 {
12737 }
12742 {
12758 }
12763 }
12765 /* Split an atomic operation. */
12767 void
12770 {
12776 rtx x;
12778 /* Split the atomic operation into a sequence. */
12786 else
12790 /* The initial load can be relaxed for a __sync operation since a final
12791 barrier will be emitted to stop code hoisting. */
12795 else
12799 {
12813 {
12816 }
12817 /* Fall through. */
12823 }
12833 /* Emit any final barrier needed for a __sync operation. */
12836 }
12838 static void
12840 {
12841 /* Half-precision float operations. The compiler handles all operations
12842 with NULL libfuncs by converting to SFmode. */
12844 /* Conversions. */
12848 /* Arithmetic. */
12855 /* Comparisons. */
12863 }
12865 /* Target hook for c_mode_for_suffix. */
12866 static machine_mode
12868 {
12873 }
12875 /* We can only represent floating point constants which will fit in
12876 "quarter-precision" values. These values are characterised by
12877 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12878 by:
12880 (-1)^s * (n/16) * 2^r
12882 Where:
12883 's' is the sign bit.
12884 'n' is an integer in the range 16 <= n <= 31.
12885 'r' is an integer in the range -3 <= r <= 4. */
12887 /* Return true iff X can be represented by a quarter-precision
12888 floating point immediate operand X. Note, we cannot represent 0.0. */
12889 bool
12891 {
12892 /* This represents our current view of how many bits
12893 make up the mantissa. */
12903 /* We don't support HFmode constants yet. */
12909 /* We cannot represent infinities, NaNs or +/-zero. We won't
12910 know if we have +zero until we analyse the mantissa, but we
12911 can reject the other invalid values. */
12916 /* Extract exponent. */
12920 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12921 highest (sign) bit, with a fixed binary point at bit point_pos.
12922 m1 holds the low part of the mantissa, m2 the high part.
12923 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12924 bits for the mantissa, this can fail (low bits will be lost). */
12928 /* If the low part of the mantissa has bits set we cannot represent
12929 the value. */
12932 /* We have rejected the lower HOST_WIDE_INT, so update our
12933 understanding of how many bits lie in the mantissa and
12934 look only at the high HOST_WIDE_INT. */
12938 /* We can only represent values with a mantissa of the form 1.xxxx. */
12943 /* Having filtered unrepresentable values, we may now remove all
12944 but the highest 5 bits. */
12947 /* We cannot represent the value 0.0, so reject it. This is handled
12948 elsewhere. */
12952 /* Then, as bit 4 is always set, we can mask it off, leaving
12953 the mantissa in the range [0, 15]. */
12957 /* GCC internally does not use IEEE754-like encoding (where normalized
12958 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12959 Our mantissa values are shifted 4 places to the left relative to
12960 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12961 by 5 places to correct for GCC's representation. */
12965 }
12969 machine_mode mode,
12971 {
12981 /* This will return true to show const_vector is legal for use as either
12982 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12983 also update INFO to show how the immediate should be generated. */
12992 {
12994 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12995 move immediate path. */
12998 else
12999 {
13008 else
13012 }
13013 }
13026 else
13030 }
13034 {
13036 /* If a floating point number was passed and we desire to use it in an
13037 integer mode do the conversion to integer. */
13039 {
13044 }
13046 machine_mode vmode;
13047 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13048 a 128 bit vector mode. */
13055 }
13057 /* Split operands into moves from op[1] + op[2] into op[0]. */
13059 void
13061 {
13072 {
13073 /* No-op move. Can't split to nothing; emit something. */
13076 }
13078 /* Preserve register attributes for variable tracking. */
13083 /* Special case of reversed high/low parts. */
13086 {
13090 }
13092 {
13093 /* Try to avoid unnecessary moves if part of the result
13094 is in the right place already. */
13099 }
13100 else
13101 {
13106 }
13107 }
13109 /* vec_perm support. */
13111 #define MAX_VECT_LEN 16
13113 struct expand_vec_perm_d
13114 {
13117 machine_mode vmode;
13121 };
13123 /* Generate a variable permutation. */
13125 static void
13127 {
13138 {
13140 {
13141 /* Expand the argument to a V16QI mode by duplicating it. */
13145 }
13146 else
13147 {
13149 }
13150 }
13151 else
13152 {
13153 rtx pair;
13156 {
13160 }
13161 else
13162 {
13166 }
13167 }
13168 }
13170 void
13172 {
13176 rtx mask;
13178 /* The TBL instruction does not use a modulo index, so we must take care
13179 of that ourselves. */
13184 /* For big-endian, we also need to reverse the index within the vector
13185 (but not which vector). */
13187 {
13188 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13193 }
13195 }
13197 /* Recognize patterns suitable for the TRN instructions. */
13198 static bool
13200 {
13209 /* Note that these are little-endian tests.
13210 We correct for big-endian later. */
13215 else
13220 {
13225 }
13227 /* Success! */
13234 {
13237 }
13241 {
13243 {
13258 }
13259 }
13260 else
13261 {
13263 {
13278 }
13279 }
13283 }
13285 /* Recognize patterns suitable for the UZP instructions. */
13286 static bool
13288 {
13297 /* Note that these are little-endian tests.
13298 We correct for big-endian later. */
13303 else
13308 {
13312 }
13314 /* Success! */
13321 {
13324 }
13328 {
13330 {
13345 }
13346 }
13347 else
13348 {
13350 {
13365 }
13366 }
13370 }
13372 /* Recognize patterns suitable for the ZIP instructions. */
13373 static bool
13375 {
13384 /* Note that these are little-endian tests.
13385 We correct for big-endian later. */
13388 /* Do Nothing. */
13389 ;
13392 else
13397 {
13404 }
13406 /* Success! */
13413 {
13416 }
13420 {
13422 {
13437 }
13438 }
13439 else
13440 {
13442 {
13457 }
13458 }
13462 }
13464 /* Recognize patterns for the EXT insn. */
13466 static bool
13468 {
13471 rtx offset;
13475 /* Check if the extracted indices are increasing by one. */
13477 {
13480 {
13481 /* We'll pass the same vector in twice, so allow indices to wrap. */
13483 }
13486 }
13489 {
13504 }
13506 /* Success! */
13510 /* The case where (location == 0) is a no-op for both big- and little-endian,
13511 and is removed by the mid-end at optimization levels -O1 and higher. */
13514 {
13515 /* After setup, we want the high elements of the first vector (stored
13516 at the LSB end of the register), and the low elements of the second
13517 vector (stored at the MSB end of the register). So swap. */
13519 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13521 }
13526 }
13528 /* Recognize patterns for the REV insns. */
13530 static bool
13532 {
13541 {
13544 {
13549 }
13553 {
13560 }
13564 {
13577 }
13581 }
13585 {
13586 /* This is guaranteed to be true as the value of diff
13587 is 7, 3, 1 and we should have enough elements in the
13588 queue to generate this. Getting a vector mask with a
13589 value of diff other than these values implies that
13590 something is wrong by the time we get here. */
13594 }
13596 /* Success! */
13602 }
13604 static bool
13606 {
13609 rtx in0;
13612 rtx lane;
13616 {
13619 }
13621 /* The generic preparation in aarch64_expand_vec_perm_const_1
13622 swaps the operand order and the permute indices if it finds
13623 d->perm[0] to be in the second operand. Thus, we can always
13624 use d->op0 and need not do any extra arithmetic to get the
13625 correct lane number. */
13630 {
13645 }
13649 }
13651 static bool
13653 {
13661 /* Generic code will try constant permutation twice. Once with the
13662 original mode and again with the elements lowered to QImode.
13663 So wait and don't do the selector expansion ourselves. */
13668 {
13671 /* If big-endian and two vectors we end up with a weird mixed-endian
13672 mode on NEON. Reverse the index within each word but not the word
13673 itself. */
13676 }
13682 }
13684 static bool
13686 {
13687 /* The pattern matching functions above are written to look for a small
13688 number to begin the sequence (0, 1, N/2). If we begin with an index
13689 from the second operand, we can swap the operands. */
13691 {
13699 }
13702 {
13716 }
13718 }
13720 /* Expand a vec_perm_const pattern. */
13722 bool
13724 {
13738 {
13743 }
13746 {
13755 /* The elements of PERM do not suggest that only the first operand
13756 is used, but both operands are identical. Allow easier matching
13757 of the permutation by folding the permutation into the single
13758 input vector. */
13759 /* Fall Through. */
13771 }
13774 }
13776 static bool
13779 {
13789 /* Calculate whether all elements are in one vector. */
13791 {
13795 }
13797 /* If all elements are from the second vector, reindex as if from the
13798 first vector. */
13803 /* Check whether the mask can be applied to a single vector. */
13816 }
13818 rtx
13820 {
13821 /* We have to reverse each vector because we dont have
13822 a permuted load that can reverse-load according to ABI rules. */
13823 rtx mask;
13837 }
13839 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13840 However due to issues with register allocation it is preferable to avoid
13841 tieing integer scalar and FP scalar modes. Executing integer operations
13842 in general registers is better than treating them as scalar vector
13843 operations. This reduces latency and avoids redundant int<->FP moves.
13844 So tie modes if they are either the same class, or vector modes with
13845 other vector modes, vector structs or any scalar mode.
13846 */
13848 bool
13850 {
13854 /* We specifically want to allow elements of "structure" modes to
13855 be tieable to the structure. This more general condition allows
13856 other rarer situations too. */
13860 /* Also allow any scalar modes with vectors. */
13866 }
13868 /* Return a new RTX holding the result of moving POINTER forward by
13869 AMOUNT bytes. */
13871 static rtx
13873 {
13878 }
13880 /* Return a new RTX holding the result of moving POINTER forward by the
13881 size of the mode it points to. */
13883 static rtx
13885 {
13889 }
13891 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13892 MODE bytes. */
13894 static void
13896 machine_mode mode)
13897 {
13900 /* "Cast" the pointers to the correct mode. */
13903 /* Emit the memcpy. */
13906 /* Move the pointers forward. */
13909 }
13911 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13912 we succeed, otherwise return false. */
13914 bool
13916 {
13920 rtx base;
13923 /* When optimizing for size, give a better estimate of the length of a
13924 memcpy call, but use the default otherwise. */
13927 /* We can't do anything smart if the amount to copy is not constant. */
13933 /* Try to keep the number of instructions low. For cases below 16 bytes we
13934 need to make at most two moves. For cases above 16 bytes it will be one
13935 move for each 16 byte chunk, then at most two additional moves. */
13945 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13946 1-byte chunk. */
13948 {
13950 {
13953 }
13959 }
13961 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13962 4-byte chunk, partially overlapping with the previously copied chunk. */
13964 {
13968 {
13974 }
13976 }
13978 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13979 them, then (if applicable) an 8-byte chunk. */
13981 {
13983 {
13986 }
13987 else
13988 {
13991 }
13992 }
13994 /* Finish the final bytes of the copy. We can always do this in one
13995 instruction. We either copy the exact amount we need, or partially
13996 overlap with the previous chunk we copied and copy 8-bytes. */
14005 else
14006 {
14008 {
14012 }
14013 else
14014 {
14020 }
14021 }
14024 }
14026 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14027 SImode stores. Handle the case when the constant has identical
14028 bottom and top halves. This is beneficial when the two stores can be
14029 merged into an STP and we avoid synthesising potentially expensive
14030 immediates twice. Return true if such a split is possible. */
14032 bool
14034 {
14043 unsigned int orig_cost
14045 unsigned int lo_cost
14048 /* We want to transform:
14049 MOV x1, 49370
14050 MOVK x1, 0x140, lsl 16
14051 MOVK x1, 0xc0da, lsl 32
14052 MOVK x1, 0x140, lsl 48
14053 STR x1, [x0]
14054 into:
14055 MOV w1, 49370
14056 MOVK w1, 0x140, lsl 16
14057 STP w1, w1, [x0]
14058 So we want to perform this only when we save two instructions
14059 or more. When optimizing for size, however, accept any code size
14060 savings we can. */
14075 /* Don't emit an explicit store pair as this may not be always profitable.
14076 Let the sched-fusion logic decide whether to merge them. */
14081 }
14083 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14085 static unsigned HOST_WIDE_INT
14087 {
14089 }
14091 static bool
14096 {
14097 /* STORE_BY_PIECES can be used when copying a constant string, but
14098 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14099 For now we always fail this and let the move_by_pieces code copy
14100 the string from read-only memory. */
14105 }
14107 static rtx
14110 {
14114 insn_code icode;
14125 {
14153 }
14158 {
14161 }
14170 {
14173 }
14179 }
14181 static rtx
14184 {
14188 insn_code icode;
14200 {
14228 }
14233 {
14236 }
14244 {
14249 }
14260 {
14263 }
14269 }
14271 #undef TARGET_GEN_CCMP_FIRST
14272 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14274 #undef TARGET_GEN_CCMP_NEXT
14275 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14277 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14278 instruction fusion of some sort. */
14280 static bool
14282 {
14284 }
14287 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14288 should be kept together during scheduling. */
14290 static bool
14292 {
14293 rtx set_dest;
14296 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14303 {
14304 /* We are trying to match:
14305 prev (mov) == (set (reg r0) (const_int imm16))
14306 curr (movk) == (set (zero_extract (reg r0)
14307 (const_int 16)
14308 (const_int 16))
14309 (const_int imm16_1)) */
14321 {
14323 }
14324 }
14327 {
14329 /* We're trying to match:
14330 prev (adrp) == (set (reg r1)
14331 (high (symbol_ref ("SYM"))))
14332 curr (add) == (set (reg r0)
14333 (lo_sum (reg r1)
14334 (symbol_ref ("SYM"))))
14335 Note that r0 need not necessarily be the same as r1, especially
14336 during pre-regalloc scheduling. */
14340 {
14348 }
14349 }
14352 {
14354 /* We're trying to match:
14355 prev (movk) == (set (zero_extract (reg r0)
14356 (const_int 16)
14357 (const_int 32))
14358 (const_int imm16_1))
14359 curr (movk) == (set (zero_extract (reg r0)
14360 (const_int 16)
14361 (const_int 48))
14362 (const_int imm16_2)) */
14378 }
14380 {
14381 /* We're trying to match:
14382 prev (adrp) == (set (reg r0)
14383 (high (symbol_ref ("SYM"))))
14384 curr (ldr) == (set (reg r1)
14385 (mem (lo_sum (reg r0)
14386 (symbol_ref ("SYM")))))
14387 or
14388 curr (ldr) == (set (reg r1)
14389 (zero_extend (mem
14390 (lo_sum (reg r0)
14391 (symbol_ref ("SYM")))))) */
14394 {
14407 }
14408 }
14416 {
14420 rtx cc_reg_1;
14425 && prev
14427 {
14428 /* FIXME: this misses some which is considered simple arthematic
14429 instructions for ThunderX. Simple shifts are missed here. */
14435 }
14436 }
14439 && curr_set
14442 {
14443 /* We're trying to match:
14444 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14445 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14446 (const_int 0))
14447 (label_ref ("SYM"))
14448 (pc)) */
14455 {
14456 /* Fuse ALU operations followed by conditional branch instruction. */
14458 {
14479 }
14480 }
14481 }
14484 }
14486 /* Return true iff the instruction fusion described by OP is enabled. */
14488 bool
14490 {
14492 }
14494 /* If MEM is in the form of [base+offset], extract the two parts
14495 of address and set to BASE and OFFSET, otherwise return false
14496 after clearing BASE and OFFSET. */
14498 bool
14500 {
14501 rtx addr;
14508 {
14512 }
14516 {
14520 }
14526 }
14528 /* Types for scheduling fusion. */
14529 enum sched_fusion_type
14530 {
14532 SCHED_FUSION_LD_SIGN_EXTEND,
14533 SCHED_FUSION_LD_ZERO_EXTEND,
14534 SCHED_FUSION_LD,
14535 SCHED_FUSION_ST,
14536 SCHED_FUSION_NUM
14537 };
14539 /* If INSN is a load or store of address in the form of [base+offset],
14540 extract the two parts and set to BASE and OFFSET. Return scheduling
14541 fusion type this INSN is. */
14543 static enum sched_fusion_type
14545 {
14563 {
14568 }
14570 {
14575 }
14580 {
14583 }
14584 else
14591 }
14593 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14595 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14596 and PRI are only calculated for these instructions. For other instruction,
14597 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14598 type instruction fusion can be added by returning different priorities.
14600 It's important that irrelevant instructions get the largest FUSION_PRI. */
14602 static void
14605 {
14615 {
14619 }
14621 /* Set FUSION_PRI according to fusion type and base register. */
14624 /* Calculate PRI. */
14627 /* INSN with smaller offset goes first. */
14631 else
14636 }
14638 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14639 Adjust priority of sha1h instructions so they are scheduled before
14640 other SHA1 instructions. */
14642 static int
14644 {
14648 {
14653 }
14656 }
14658 /* Given OPERANDS of consecutive load/store, check if we can merge
14659 them into ldp/stp. LOAD is true if they are load instructions.
14660 MODE is the mode of memory operands. */
14662 bool
14664 machine_mode mode)
14665 {
14671 {
14679 }
14680 else
14681 {
14686 }
14688 /* The mems cannot be volatile. */
14692 /* If we have SImode and slow unaligned ldp,
14693 check the alignment to be at least 8 byte. */
14697 && !optimize_size
14701 /* Check if the addresses are in the form of [base+offset]. */
14709 /* Check if the bases are same. */
14716 /* Check if the offsets are consecutive. */
14720 /* Check if the addresses are clobbered by load. */
14722 {
14726 /* In increasing order, the last load can clobber the address. */
14729 }
14733 else
14738 else
14741 /* Check if the registers are of same class. */
14746 }
14748 /* Given OPERANDS of consecutive load/store, check if we can merge
14749 them into ldp/stp by adjusting the offset. LOAD is true if they
14750 are load instructions. MODE is the mode of memory operands.
14752 Given below consecutive stores:
14754 str w1, [xb, 0x100]
14755 str w1, [xb, 0x104]
14756 str w1, [xb, 0x108]
14757 str w1, [xb, 0x10c]
14759 Though the offsets are out of the range supported by stp, we can
14760 still pair them after adjusting the offset, like:
14762 add scratch, xb, 0x100
14763 stp w1, w1, [scratch]
14764 stp w1, w1, [scratch, 0x8]
14766 The peephole patterns detecting this opportunity should guarantee
14767 the scratch register is avaliable. */
14769 bool
14771 machine_mode mode)
14772 {
14779 {
14792 }
14793 else
14794 {
14803 }
14804 /* Skip if memory operand is by itslef valid for ldp/stp. */
14808 /* The mems cannot be volatile. */
14813 /* Check if the addresses are in the form of [base+offset]. */
14827 /* Check if the bases are same. */
14838 /* Check if the offsets are consecutive. */
14847 /* Check if the addresses are clobbered by load. */
14849 {
14855 /* In increasing order, the last load can clobber the address. */
14858 }
14860 /* If we have SImode and slow unaligned ldp,
14861 check the alignment to be at least 8 byte. */
14865 && !optimize_size
14871 else
14876 else
14881 else
14886 else
14889 /* Check if the registers are of same class. */
14894 }
14896 /* Given OPERANDS of consecutive load/store, this function pairs them
14897 into ldp/stp after adjusting the offset. It depends on the fact
14898 that addresses of load/store instructions are in increasing order.
14899 MODE is the mode of memory operands. CODE is the rtl operator
14900 which should be applied to all memory operands, it's SIGN_EXTEND,
14901 ZERO_EXTEND or UNKNOWN. */
14903 bool
14906 {
14912 {
14917 }
14918 else
14919 {
14925 }
14930 /* Adjust offset thus it can fit in ldp/stp instruction. */
14938 /* Further adjust to make sure all offsets are OK. */
14940 {
14943 }
14945 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14950 {
14953 }
14955 /* Create new memory references. */
14959 /* Check if the adjusted address is OK for ldp/stp. */
14978 {
14983 }
14985 {
14990 }
14993 {
14998 }
14999 else
15000 {
15005 }
15007 /* Emit adjusting instruction. */
15009 /* Emit ldp/stp instructions. */
15017 }
15019 /* Return 1 if pseudo register should be created and used to hold
15020 GOT address for PIC code. */
15022 bool
15024 {
15026 }
15028 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15030 static int
15032 {
15034 {
15041 }
15044 }
15047 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15048 return the log2 of that value. Otherwise return -1. */
15050 int
15052 {
15067 }
15069 /* If X is a vector of equal CONST_DOUBLE values and that value is
15070 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15072 int
15074 {
15090 }
15092 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15093 to float.
15095 __fp16 always promotes through this hook.
15096 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15097 through the generic excess precision logic rather than here. */
15099 static tree
15101 {
15107 }
15109 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15111 static bool
15113 optimization_type opt_type)
15114 {
15116 {
15122 }
15123 }
15125 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15126 if MODE is HFmode, and punt to the generic implementation otherwise. */
15128 static bool
15130 {
15134 }
15136 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15137 if MODE is HFmode, and punt to the generic implementation otherwise. */
15139 static bool
15141 {
15145 }
15147 /* Set the value of FLT_EVAL_METHOD.
15148 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15150 0: evaluate all operations and constants, whose semantic type has at
15151 most the range and precision of type float, to the range and
15152 precision of float; evaluate all other operations and constants to
15153 the range and precision of the semantic type;
15155 N, where _FloatN is a supported interchange floating type
15156 evaluate all operations and constants, whose semantic type has at
15157 most the range and precision of _FloatN type, to the range and
15158 precision of the _FloatN type; evaluate all other operations and
15159 constants to the range and precision of the semantic type;
15161 If we have the ARMv8.2-A extensions then we support _Float16 in native
15162 precision, so we should set this to 16. Otherwise, we support the type,
15163 but want to evaluate expressions in float precision, so set this to
15164 0. */
15166 static enum flt_eval_method
15168 {
15170 {
15173 /* We can calculate either in 16-bit range and precision or
15174 32-bit range and precision. Make that decision based on whether
15175 we have native support for the ARMv8.2-A 16-bit floating-point
15176 instructions or not. */
15178 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15184 }
15186 }
15188 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15189 scheduled for speculative execution. Reject the long-running division
15190 and square-root instructions. */
15192 static bool
15194 {
15196 {
15214 }
15215 }
15217 /* Target-specific selftests. */
15219 #if CHECKING_P
15223 /* Selftest for the RTL loader.
15224 Verify that the RTL loader copes with a dump from
15225 print_rtx_function. This is essentially just a test that class
15226 function_reader can handle a real dump, but it also verifies
15227 that lookup_reg_by_dump_name correctly handles hard regs.
15228 The presence of hard reg names in the dump means that the test is
15229 target-specific, hence it is in this file. */
15231 static void
15233 {
15245 /* Verify crtl->return_rtx. */
15249 }
15251 /* Run all target-specific selftests. */
15253 static void
15255 {
15257 }
15263 #undef TARGET_ADDRESS_COST
15264 #define TARGET_ADDRESS_COST aarch64_address_cost
15266 /* This hook will determines whether unnamed bitfields affect the alignment
15267 of the containing structure. The hook returns true if the structure
15268 should inherit the alignment requirements of an unnamed bitfield's
15269 type. */
15270 #undef TARGET_ALIGN_ANON_BITFIELD
15271 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15273 #undef TARGET_ASM_ALIGNED_DI_OP
15276 #undef TARGET_ASM_ALIGNED_HI_OP
15279 #undef TARGET_ASM_ALIGNED_SI_OP
15282 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15283 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15284 hook_bool_const_tree_hwi_hwi_const_tree_true
15286 #undef TARGET_ASM_FILE_START
15287 #define TARGET_ASM_FILE_START aarch64_start_file
15289 #undef TARGET_ASM_OUTPUT_MI_THUNK
15290 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15292 #undef TARGET_ASM_SELECT_RTX_SECTION
15293 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15295 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15296 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15298 #undef TARGET_BUILD_BUILTIN_VA_LIST
15299 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15301 #undef TARGET_CALLEE_COPIES
15302 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15304 #undef TARGET_CAN_ELIMINATE
15305 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15307 #undef TARGET_CAN_INLINE_P
15308 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15310 #undef TARGET_CANNOT_FORCE_CONST_MEM
15311 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15313 #undef TARGET_CASE_VALUES_THRESHOLD
15314 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15316 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15317 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15319 /* Only the least significant bit is used for initialization guard
15320 variables. */
15321 #undef TARGET_CXX_GUARD_MASK_BIT
15322 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15324 #undef TARGET_C_MODE_FOR_SUFFIX
15325 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15327 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15328 #undef TARGET_DEFAULT_TARGET_FLAGS
15329 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15330 #endif
15332 #undef TARGET_CLASS_MAX_NREGS
15333 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15335 #undef TARGET_BUILTIN_DECL
15336 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15338 #undef TARGET_BUILTIN_RECIPROCAL
15339 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15341 #undef TARGET_C_EXCESS_PRECISION
15342 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15344 #undef TARGET_EXPAND_BUILTIN
15345 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15347 #undef TARGET_EXPAND_BUILTIN_VA_START
15348 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15350 #undef TARGET_FOLD_BUILTIN
15351 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15353 #undef TARGET_FUNCTION_ARG
15354 #define TARGET_FUNCTION_ARG aarch64_function_arg
15356 #undef TARGET_FUNCTION_ARG_ADVANCE
15357 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15359 #undef TARGET_FUNCTION_ARG_BOUNDARY
15360 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15362 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15363 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15365 #undef TARGET_FUNCTION_VALUE
15366 #define TARGET_FUNCTION_VALUE aarch64_function_value
15368 #undef TARGET_FUNCTION_VALUE_REGNO_P
15369 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15371 #undef TARGET_FRAME_POINTER_REQUIRED
15372 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15374 #undef TARGET_GIMPLE_FOLD_BUILTIN
15375 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15377 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15378 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15380 #undef TARGET_INIT_BUILTINS
15381 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15383 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15384 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15385 aarch64_ira_change_pseudo_allocno_class
15387 #undef TARGET_LEGITIMATE_ADDRESS_P
15388 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15390 #undef TARGET_LEGITIMATE_CONSTANT_P
15391 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15393 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15394 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15395 aarch64_legitimize_address_displacement
15397 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15398 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15400 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15401 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15402 aarch64_libgcc_floating_mode_supported_p
15404 #undef TARGET_MANGLE_TYPE
15405 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15407 #undef TARGET_MEMORY_MOVE_COST
15408 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15410 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15411 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15413 #undef TARGET_MUST_PASS_IN_STACK
15414 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15416 /* This target hook should return true if accesses to volatile bitfields
15417 should use the narrowest mode possible. It should return false if these
15418 accesses should use the bitfield container type. */
15419 #undef TARGET_NARROW_VOLATILE_BITFIELD
15420 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15422 #undef TARGET_OPTION_OVERRIDE
15423 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15425 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15426 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15427 aarch64_override_options_after_change
15429 #undef TARGET_OPTION_SAVE
15430 #define TARGET_OPTION_SAVE aarch64_option_save
15432 #undef TARGET_OPTION_RESTORE
15433 #define TARGET_OPTION_RESTORE aarch64_option_restore
15435 #undef TARGET_OPTION_PRINT
15436 #define TARGET_OPTION_PRINT aarch64_option_print
15438 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15439 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15441 #undef TARGET_SET_CURRENT_FUNCTION
15442 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15444 #undef TARGET_PASS_BY_REFERENCE
15445 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15447 #undef TARGET_PREFERRED_RELOAD_CLASS
15448 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15450 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15451 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15453 #undef TARGET_PROMOTED_TYPE
15454 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15456 #undef TARGET_SECONDARY_RELOAD
15457 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15459 #undef TARGET_SHIFT_TRUNCATION_MASK
15460 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15462 #undef TARGET_SETUP_INCOMING_VARARGS
15463 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15465 #undef TARGET_STRUCT_VALUE_RTX
15466 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15468 #undef TARGET_REGISTER_MOVE_COST
15469 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15471 #undef TARGET_RETURN_IN_MEMORY
15472 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15474 #undef TARGET_RETURN_IN_MSB
15475 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15477 #undef TARGET_RTX_COSTS
15478 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15480 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15481 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15483 #undef TARGET_SCHED_ISSUE_RATE
15484 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15486 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15487 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15488 aarch64_sched_first_cycle_multipass_dfa_lookahead
15490 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15491 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15492 aarch64_first_cycle_multipass_dfa_lookahead_guard
15494 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15495 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15496 aarch64_get_separate_components
15498 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15499 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15500 aarch64_components_for_bb
15502 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15503 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15504 aarch64_disqualify_components
15506 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15507 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15508 aarch64_emit_prologue_components
15510 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15511 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15512 aarch64_emit_epilogue_components
15514 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15515 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15516 aarch64_set_handled_components
15518 #undef TARGET_TRAMPOLINE_INIT
15519 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15521 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15522 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15524 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15525 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15527 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15528 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15529 aarch64_builtin_support_vector_misalignment
15531 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15532 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15534 #undef TARGET_VECTORIZE_ADD_STMT_COST
15535 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15537 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15538 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15539 aarch64_builtin_vectorization_cost
15541 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15542 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15544 #undef TARGET_VECTORIZE_BUILTINS
15545 #define TARGET_VECTORIZE_BUILTINS
15547 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15548 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15549 aarch64_builtin_vectorized_function
15551 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15552 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15553 aarch64_autovectorize_vector_sizes
15555 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15556 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15557 aarch64_atomic_assign_expand_fenv
15559 /* Section anchor support. */
15561 #undef TARGET_MIN_ANCHOR_OFFSET
15562 #define TARGET_MIN_ANCHOR_OFFSET -256
15564 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15565 byte offset; we can do much more for larger data types, but have no way
15566 to determine the size of the access. We assume accesses are aligned. */
15567 #undef TARGET_MAX_ANCHOR_OFFSET
15568 #define TARGET_MAX_ANCHOR_OFFSET 4095
15570 #undef TARGET_VECTOR_ALIGNMENT
15571 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15573 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15574 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15575 aarch64_simd_vector_alignment_reachable
15577 /* vec_perm support. */
15579 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15580 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15581 aarch64_vectorize_vec_perm_const_ok
15583 #undef TARGET_INIT_LIBFUNCS
15584 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15586 #undef TARGET_FIXED_CONDITION_CODE_REGS
15587 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15589 #undef TARGET_FLAGS_REGNUM
15590 #define TARGET_FLAGS_REGNUM CC_REGNUM
15592 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15593 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15595 #undef TARGET_ASAN_SHADOW_OFFSET
15596 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15598 #undef TARGET_LEGITIMIZE_ADDRESS
15599 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15601 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15602 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15603 aarch64_use_by_pieces_infrastructure_p
15605 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15606 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15608 #undef TARGET_CAN_USE_DOLOOP_P
15609 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15611 #undef TARGET_SCHED_ADJUST_PRIORITY
15612 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15614 #undef TARGET_SCHED_MACRO_FUSION_P
15615 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15617 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15618 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15620 #undef TARGET_SCHED_FUSION_PRIORITY
15621 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15623 #undef TARGET_UNSPEC_MAY_TRAP_P
15624 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15626 #undef TARGET_USE_PSEUDO_PIC_REG
15627 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15629 #undef TARGET_PRINT_OPERAND
15630 #define TARGET_PRINT_OPERAND aarch64_print_operand
15632 #undef TARGET_PRINT_OPERAND_ADDRESS
15633 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15635 #undef TARGET_OPTAB_SUPPORTED_P
15636 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15638 #undef TARGET_OMIT_STRUCT_RETURN_REG
15639 #define TARGET_OMIT_STRUCT_RETURN_REG true
15641 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15642 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15643 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15645 #if CHECKING_P
15646 #undef TARGET_RUN_TARGET_SELFTESTS
15647 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests