| blob | e7f87b1ff8854743d06b3602eeec7807e3ff52a2 |
1 /* Target macros for the FRV port of GCC.
2 Copyright (C) 1999-2016 Free Software Foundation, Inc.
3 Contributed by Red Hat Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #ifndef __FRV_H__
22 #define __FRV_H__
24 /* Frv general purpose macros. */
25 /* Align an address. */
26 #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
27 \f
28 /* Driver configuration. */
30 /* -fpic and -fPIC used to imply the -mlibrary-pic multilib, but with
31 FDPIC which multilib to use depends on whether FDPIC is in use or
32 not. The trick we use is to introduce -multilib-library-pic as a
33 pseudo-flag that selects the library-pic multilib, and map fpic
34 and fPIC to it only if fdpic is not selected. Also, if fdpic is
35 selected and no PIC/PIE options are present, we imply -fPIE.
36 Otherwise, if -fpic or -fPIC are enabled and we're optimizing for
37 speed, or if we have -On with n>=3, enable inlining of PLTs. As
38 for -mgprel-ro, we want to enable it by default, but not for -fpic or
39 -fpie. */
41 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS \
42 "%{mno-pack:\
43 %{!mhard-float:-msoft-float}\
44 %{!mmedia:-mno-media}}\
46 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
47 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fPIE}}}}}}}} \
51 "
52 #ifndef SUBTARGET_DRIVER_SELF_SPECS
53 # define SUBTARGET_DRIVER_SELF_SPECS
54 #endif
56 #undef ASM_SPEC
58 %{G*} \
59 %{mtomcat-stats} \
60 %{!mno-eflags: \
61 %{mcpu=*} \
62 %{mgpr-*} %{mfpr-*} \
63 %{msoft-float} %{mhard-float} \
64 %{mdword} %{mno-dword} \
65 %{mdouble} %{mno-double} \
66 %{mmedia} %{mno-media} \
67 %{mmuladd} %{mno-muladd} \
68 %{mpack} %{mno-pack} \
69 %{mno-fdpic:-mnopic} %{mfdpic} \
72 #undef STARTFILE_SPEC
75 #undef ENDFILE_SPEC
79 #define MASK_DEFAULT_FRV \
80 (MASK_MEDIA \
81 | MASK_DOUBLE \
82 | MASK_MULADD \
83 | MASK_DWORD \
84 | MASK_PACK)
86 #define MASK_DEFAULT_FR500 \
87 (MASK_MEDIA | MASK_DWORD | MASK_PACK)
89 #define MASK_DEFAULT_FR550 \
90 (MASK_MEDIA | MASK_DWORD | MASK_PACK)
92 #define MASK_DEFAULT_FR450 \
93 (MASK_GPR_32 \
94 | MASK_FPR_32 \
95 | MASK_MEDIA \
96 | MASK_SOFT_FLOAT \
97 | MASK_DWORD \
98 | MASK_PACK)
100 #define MASK_DEFAULT_FR400 \
101 (MASK_GPR_32 \
102 | MASK_FPR_32 \
103 | MASK_MEDIA \
104 | MASK_ACC_4 \
105 | MASK_SOFT_FLOAT \
106 | MASK_DWORD \
107 | MASK_PACK)
109 #define MASK_DEFAULT_SIMPLE \
110 (MASK_GPR_32 | MASK_SOFT_FLOAT)
112 /* A C string constant that tells the GCC driver program options to pass to
113 `cc1'. It can also specify how to translate options you give to GCC into
114 options for GCC to pass to the `cc1'.
116 Do not define this macro if it does not need to do anything. */
117 /* For ABI compliance, we need to put bss data into the normal data section. */
120 #undef LINK_SPEC
122 %{h*} %{v:-V} \
123 %{mfdpic:-melf32frvfd -z text} \
124 %{static:-dn -Bstatic} \
125 %{shared:-Bdynamic} \
126 %{symbolic:-Bsymbolic} \
127 %{G*}"
129 #undef LIB_SPEC
132 #ifndef CPU_TYPE
133 #define CPU_TYPE FRV_CPU_FR500
134 #endif
136 /* Run-time target specifications */
138 #define TARGET_CPU_CPP_BUILTINS() \
139 do \
140 { \
141 int issue_rate; \
142 \
145 \
146 issue_rate = frv_issue_rate (); \
147 if (issue_rate > 1) \
152 \
153 switch (frv_cpu_type) \
154 { \
155 case FRV_CPU_GENERIC: \
157 break; \
158 case FRV_CPU_FR550: \
160 break; \
161 case FRV_CPU_FR500: \
162 case FRV_CPU_TOMCAT: \
164 break; \
165 case FRV_CPU_FR450: \
167 break; \
168 case FRV_CPU_FR405: \
170 break; \
171 case FRV_CPU_FR400: \
173 break; \
174 case FRV_CPU_FR300: \
175 case FRV_CPU_SIMPLE: \
177 break; \
178 } \
179 \
180 if (TARGET_HARD_FLOAT) \
182 if (TARGET_DWORD) \
184 if (TARGET_FDPIC) \
186 if (flag_leading_underscore > 0) \
188 } \
189 while (0)
191 \f
192 #define TARGET_HAS_FPRS (TARGET_HARD_FLOAT || TARGET_MEDIA)
194 #define NUM_GPRS (TARGET_GPR_32? 32 : 64)
195 #define NUM_FPRS (!TARGET_HAS_FPRS? 0 : TARGET_FPR_32? 32 : 64)
196 #define NUM_ACCS (!TARGET_MEDIA? 0 : TARGET_ACC_4? 4 : 8)
198 /* X is a valid accumulator number if (X & ACC_MASK) == X. */
199 #define ACC_MASK \
200 (!TARGET_MEDIA ? 0 \
201 : TARGET_ACC_4 ? 3 \
202 : frv_cpu_type == FRV_CPU_FR450 ? 11 \
203 : 7)
205 /* Macros to identify the blend of media instructions available. Revision 1
206 is the one found on the FR500. Revision 2 includes the changes made for
207 the FR400.
209 Treat the generic processor as a revision 1 machine for now, for
210 compatibility with earlier releases. */
212 #define TARGET_MEDIA_REV1 \
213 (TARGET_MEDIA \
214 && (frv_cpu_type == FRV_CPU_GENERIC \
215 || frv_cpu_type == FRV_CPU_FR500))
217 #define TARGET_MEDIA_REV2 \
218 (TARGET_MEDIA \
219 && (frv_cpu_type == FRV_CPU_FR400 \
220 || frv_cpu_type == FRV_CPU_FR405 \
221 || frv_cpu_type == FRV_CPU_FR450 \
222 || frv_cpu_type == FRV_CPU_FR550))
224 #define TARGET_MEDIA_FR450 \
225 (frv_cpu_type == FRV_CPU_FR450)
227 #define TARGET_FR500_FR550_BUILTINS \
228 (frv_cpu_type == FRV_CPU_FR500 \
229 || frv_cpu_type == FRV_CPU_FR550)
231 #define TARGET_FR405_BUILTINS \
232 (frv_cpu_type == FRV_CPU_FR405 \
233 || frv_cpu_type == FRV_CPU_FR450)
235 #ifndef HAVE_AS_TLS
236 #define HAVE_AS_TLS 0
237 #endif
239 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_ALIGN_LABELS ? 3 : 0)
240 \f
241 /* Small Data Area Support. */
242 /* Maximum size of variables that go in .sdata/.sbss.
243 The -msdata=foo switch also controls how small variables are handled. */
244 #ifndef SDATA_DEFAULT_SIZE
245 #define SDATA_DEFAULT_SIZE 8
246 #endif
249 /* Storage Layout */
251 /* Define this macro to have the value 1 if the most significant bit in a byte
252 has the lowest number; otherwise define it to have the value zero. This
253 means that bit-field instructions count from the most significant bit. If
254 the machine has no bit-field instructions, then this must still be defined,
255 but it doesn't matter which value it is defined to. This macro need not be
256 a constant.
258 This macro does not affect the way structure fields are packed into bytes or
259 words; that is controlled by `BYTES_BIG_ENDIAN'. */
260 #define BITS_BIG_ENDIAN 1
262 /* Define this macro to have the value 1 if the most significant byte in a word
263 has the lowest number. This macro need not be a constant. */
264 #define BYTES_BIG_ENDIAN 1
266 /* Define this macro to have the value 1 if, in a multiword object, the most
267 significant word has the lowest number. This applies to both memory
268 locations and registers; GCC fundamentally assumes that the order of
269 words in memory is the same as the order in registers. This macro need not
270 be a constant. */
271 #define WORDS_BIG_ENDIAN 1
273 /* Number of storage units in a word; normally 4. */
274 #define UNITS_PER_WORD 4
276 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
277 which has the specified mode and signedness is to be stored in a register.
278 This macro is only called when TYPE is a scalar type.
280 On most RISC machines, which only have operations that operate on a full
281 register, define this macro to set M to `word_mode' if M is an integer mode
282 narrower than `BITS_PER_WORD'. In most cases, only integer modes should be
283 widened because wider-precision floating-point operations are usually more
284 expensive than their narrower counterparts.
286 For most machines, the macro definition does not change UNSIGNEDP. However,
287 some machines, have instructions that preferentially handle either signed or
288 unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit
289 loads from memory and 32-bit add instructions sign-extend the result to 64
290 bits. On such machines, set UNSIGNEDP according to which kind of extension
291 is more efficient.
293 Do not define this macro if it would never modify MODE. */
294 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
295 do \
296 { \
297 if (GET_MODE_CLASS (MODE) == MODE_INT \
298 && GET_MODE_SIZE (MODE) < 4) \
299 (MODE) = SImode; \
300 } \
301 while (0)
303 /* Normal alignment required for function parameters on the stack, in bits.
304 All stack parameters receive at least this much alignment regardless of data
305 type. On most machines, this is the same as the size of an integer. */
306 #define PARM_BOUNDARY 32
308 /* Define this macro if you wish to preserve a certain alignment for the stack
309 pointer. The definition is a C expression for the desired alignment
310 (measured in bits).
312 If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the
313 specified boundary. If `PUSH_ROUNDING' is defined and specifies a less
314 strict alignment than `STACK_BOUNDARY', the stack may be momentarily
315 unaligned while pushing arguments. */
316 #define STACK_BOUNDARY 64
318 /* Alignment required for a function entry point, in bits. */
319 #define FUNCTION_BOUNDARY 128
321 /* Biggest alignment that any data type can require on this machine,
322 in bits. */
323 #define BIGGEST_ALIGNMENT 64
325 /* @@@ A hack, needed because libobjc wants to use ADJUST_FIELD_ALIGN for
326 some reason. */
327 #ifdef IN_TARGET_LIBS
328 #define BIGGEST_FIELD_ALIGNMENT 64
329 #else
330 /* An expression for the alignment of a structure field FIELD if the
331 alignment computed in the usual way is COMPUTED. GCC uses this
332 value instead of the value in `BIGGEST_ALIGNMENT' or
333 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
334 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
335 frv_adjust_field_align (FIELD, COMPUTED)
336 #endif
338 /* If defined, a C expression to compute the alignment for a static variable.
339 TYPE is the data type, and ALIGN is the alignment that the object
340 would ordinarily have. The value of this macro is used instead of that
341 alignment to align the object.
343 If this macro is not defined, then ALIGN is used.
345 One use of this macro is to increase alignment of medium-size data to make
346 it all fit in fewer cache lines. Another is to cause character arrays to be
347 word-aligned so that `strcpy' calls that copy constants to character arrays
348 can be done inline. */
349 #define DATA_ALIGNMENT(TYPE, ALIGN) \
350 (TREE_CODE (TYPE) == ARRAY_TYPE \
351 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
352 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
354 /* If defined, a C expression to compute the alignment given to a constant that
355 is being placed in memory. CONSTANT is the constant and ALIGN is the
356 alignment that the object would ordinarily have. The value of this macro is
357 used instead of that alignment to align the object.
359 If this macro is not defined, then ALIGN is used.
361 The typical use of this macro is to increase alignment for string constants
362 to be word aligned so that `strcpy' calls that copy constants can be done
363 inline. */
364 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
365 (TREE_CODE (EXP) == STRING_CST \
366 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
368 /* Define this macro to be the value 1 if instructions will fail to work if
369 given data not on the nominal alignment. If instructions will merely go
370 slower in that case, define this macro as 0. */
371 #define STRICT_ALIGNMENT 1
373 #define PCC_BITFIELD_TYPE_MATTERS 1
375 \f
376 /* Layout of Source Language Data Types. */
378 #define CHAR_TYPE_SIZE 8
379 #define SHORT_TYPE_SIZE 16
380 #define INT_TYPE_SIZE 32
381 #define LONG_TYPE_SIZE 32
382 #define LONG_LONG_TYPE_SIZE 64
383 #define FLOAT_TYPE_SIZE 32
384 #define DOUBLE_TYPE_SIZE 64
385 #define LONG_DOUBLE_TYPE_SIZE 64
387 /* An expression whose value is 1 or 0, according to whether the type `char'
388 should be signed or unsigned by default. The user can always override this
389 default with the options `-fsigned-char' and `-funsigned-char'. */
390 #define DEFAULT_SIGNED_CHAR 1
392 #undef SIZE_TYPE
395 #undef PTRDIFF_TYPE
398 #undef WCHAR_TYPE
401 #undef WCHAR_TYPE_SIZE
402 #define WCHAR_TYPE_SIZE BITS_PER_WORD
404 \f
405 /* General purpose registers. */
411 /* small data register */
412 #define SDA_BASE_REG ((unsigned)(TARGET_FDPIC ? -1 : flag_pic ? PIC_REGNO : (GPR_FIRST + 16)))
417 #define HARD_REGNO_RENAME_OK(from,to) (TARGET_FDPIC ? ((to) != FDPIC_REG) : 1)
419 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
426 /* We reserve the last CR and CCR in each category to be used as a reload
427 register to reload the CR/CCR registers. This is a kludge. */
436 /* Amount to shift a value to locate a ICC or FCC register in the CCR
437 register and shift it to the bottom 4 bits. */
438 #define CC_SHIFT_RIGHT(REGNO) (((REGNO) - CC_FIRST) << 2)
440 /* Mask to isolate a single ICC/FCC value. */
441 #define CC_MASK 0xf
443 /* Masks to isolate the various bits in an ICC field. */
449 /* Mask to isolate the N/Z flags in an ICC. */
450 #define ICC_MASK_NZ (ICC_MASK_N | ICC_MASK_Z)
452 /* Mask to isolate the Z/C flags in an ICC. */
453 #define ICC_MASK_ZC (ICC_MASK_Z | ICC_MASK_C)
455 /* Masks to isolate the various bits in a FCC field. */
461 /* For CCR registers, the machine wants CR4..CR7 to be used for integer
462 code and CR0..CR3 to be used for floating point. */
472 /* Amount to shift a value to locate a CR register in the CCCR special purpose
473 register and shift it to the bottom 2 bits. */
474 #define CR_SHIFT_RIGHT(REGNO) (((REGNO) - CR_FIRST) << 1)
476 /* Mask to isolate a single CR value. */
477 #define CR_MASK 0x3
487 #define SPR_FIRST 169
488 #define SPR_LAST 172
489 #define LR_REGNO (SPR_FIRST)
490 #define LCR_REGNO (SPR_FIRST + 1)
491 #define IACC_FIRST (SPR_FIRST + 2)
492 #define IACC_LAST (SPR_FIRST + 3)
494 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST)
495 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM)
496 #define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST)
497 #define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST)
498 #define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST)
499 #define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST)
500 #define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST)
501 #define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST)
502 #define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST)
503 #define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST)
504 #define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST)
505 #define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST)
507 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
508 #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
509 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
510 #define CC_OR_PSEUDO_P(R) (CC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
511 #define ICC_OR_PSEUDO_P(R) (ICC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
512 #define FCC_OR_PSEUDO_P(R) (FCC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
513 #define CR_OR_PSEUDO_P(R) (CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
514 #define ICR_OR_PSEUDO_P(R) (ICR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
515 #define FCR_OR_PSEUDO_P(R) (FCR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
516 #define ACC_OR_PSEUDO_P(R) (ACC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
517 #define ACCG_OR_PSEUDO_P(R) (ACCG_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
519 #define MAX_STACK_IMMEDIATE_OFFSET 2047
521 \f
522 /* Register Basics. */
524 /* Number of hardware registers known to the compiler. They receive numbers 0
525 through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number
526 really is assigned the number `FIRST_PSEUDO_REGISTER'. */
527 #define FIRST_PSEUDO_REGISTER (SPR_LAST + 1)
529 /* The first/last register that can contain the arguments to a function. */
530 #define FIRST_ARG_REGNUM (GPR_FIRST + 8)
531 #define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1)
533 /* Registers used by the exception handling functions. These should be
534 registers that are not otherwise used by the calling sequence. */
535 #define FIRST_EH_REGNUM 14
536 #define LAST_EH_REGNUM 15
538 /* Scratch registers used in the prologue, epilogue and thunks.
539 OFFSET_REGNO is for loading constant addends that are too big for a
540 single instruction. TEMP_REGNO is used for transferring SPRs to and from
541 the stack, and various other activities. */
542 #define OFFSET_REGNO 4
543 #define TEMP_REGNO 5
545 /* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer,
546 which is sometimes used to set up the frame pointer. */
547 #define OLD_SP_REGNO 6
549 /* Registers used in the epilogue. STACKADJ_REGNO stores the exception
550 handler's stack adjustment. */
551 #define STACKADJ_REGNO 6
553 /* Registers used in thunks. JMP_REGNO is used for loading the target
554 address. */
555 #define JUMP_REGNO 6
557 #define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \
558 (N) + FIRST_EH_REGNUM : INVALID_REGNUM)
559 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO)
560 #define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx)
562 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNO)
564 /* An initializer that says which registers are used for fixed purposes all
565 throughout the compiled code and are therefore not available for general
566 allocation. These would include the stack pointer, the frame pointer
567 (except on machines where that can be used as a general register when no
568 frame pointer is needed), the program counter on machines where that is
569 considered one of the addressable registers, and any other numbered register
570 with a standard use.
572 This information is expressed as a sequence of numbers, separated by commas
573 and surrounded by braces. The Nth number is 1 if register N is fixed, 0
574 otherwise.
576 The table initialized from this macro, and the table initialized by the
577 following one, may be overridden at run time either automatically, by the
578 actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the
579 command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */
581 /* gr0 -- Hard Zero
582 gr1 -- Stack Pointer
583 gr2 -- Frame Pointer
584 gr3 -- Hidden Parameter
585 gr16 -- Small Data reserved
586 gr17 -- Pic reserved
587 gr28 -- OS reserved
588 gr29 -- OS reserved
589 gr30 -- OS reserved
590 gr31 -- OS reserved
591 cr3 -- reserved to reload FCC registers.
592 cr7 -- reserved to reload ICC registers. */
593 #define FIXED_REGISTERS \
627 }
629 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
630 general) by function calls as well as for fixed registers. This macro
631 therefore identifies the registers that are not available for general
632 allocation of values that must live across function calls.
634 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
635 saves it on function entry and restores it on function exit, if the register
636 is used within the function. */
637 #define CALL_USED_REGISTERS \
671 }
673 \f
674 /* Order of allocation of registers. */
676 /* If defined, an initializer for a vector of integers, containing the numbers
677 of hard registers in the order in which GCC should prefer to use them
678 (from most preferred to least).
680 If this macro is not defined, registers are used lowest numbered first (all
681 else being equal).
683 One use of this macro is on machines where the highest numbered registers
684 must always be saved and the save-multiple-registers instruction supports
685 only sequences of consecutive registers. On such machines, define
686 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
687 allocatable register first. */
689 /* On the FRV, allocate GR16 and GR17 after other saved registers so that we
690 have a better chance of allocating 2 registers at a time and can use the
691 double word load/store instructions in the prologue. */
692 #define REG_ALLOC_ORDER \
693 { \
695 GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \
696 GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \
697 GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \
698 GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \
699 GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \
700 GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \
701 GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \
702 \
703 FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \
704 FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \
705 FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \
706 FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \
707 FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \
708 FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \
709 FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \
710 FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \
711 \
712 ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \
713 FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \
714 CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \
715 CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \
716 \
718 GPR_FIRST + 18, GPR_FIRST + 19, \
719 GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \
720 GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \
721 GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \
722 GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \
723 GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \
724 GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \
725 GPR_FIRST + 16, GPR_FIRST + 17, \
726 \
727 FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \
728 FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \
729 FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \
730 FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \
731 FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \
732 FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \
733 FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \
734 FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \
735 \
737 GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \
738 GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \
739 ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \
740 ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \
741 ACC_FIRST + 8, ACC_FIRST + 9, ACC_FIRST + 10, ACC_FIRST + 11, \
742 ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \
743 ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \
744 ACCG_FIRST + 8, ACCG_FIRST + 9, ACCG_FIRST + 10, ACCG_FIRST + 11, \
745 AP_FIRST, LR_REGNO, LCR_REGNO, \
746 IACC_FIRST + 0, IACC_FIRST + 1 \
747 }
749 \f
750 /* How Values Fit in Registers. */
752 /* A C expression for the number of consecutive hard registers, starting at
753 register number REGNO, required to hold a value of mode MODE.
755 On a machine where all registers are exactly one word, a suitable definition
756 of this macro is
758 #define HARD_REGNO_NREGS(REGNO, MODE) \
759 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
760 / UNITS_PER_WORD)) */
762 /* On the FRV, make the CC modes take 3 words in the integer registers, so that
763 we can build the appropriate instructions to properly reload the values. */
764 #define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)
766 /* A C expression that is nonzero if it is permissible to store a value of mode
767 MODE in hard register number REGNO (or in several registers starting with
768 that one). For a machine where all registers are equivalent, a suitable
769 definition is
771 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
773 It is not necessary for this macro to check for the numbers of fixed
774 registers, because the allocation mechanism considers them to be always
775 occupied.
777 On some machines, double-precision values must be kept in even/odd register
778 pairs. The way to implement that is to define this macro to reject odd
779 register numbers for such modes.
781 The minimum requirement for a mode to be OK in a register is that the
782 `movMODE' instruction pattern support moves between the register and any
783 other hard register for which the mode is OK; and that moving a value into
784 the register and back out not alter it.
786 Since the same instruction used to move `SImode' will work for all narrower
787 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
788 to distinguish between these modes, provided you define patterns `movhi',
789 etc., to take advantage of this. This is useful because of the interaction
790 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
791 all integer modes to be tieable.
793 Many machines have special registers for floating point arithmetic. Often
794 people assume that floating point machine modes are allowed only in floating
795 point registers. This is not true. Any registers that can hold integers
796 can safely *hold* a floating point machine mode, whether or not floating
797 arithmetic can be done on it in those registers. Integer move instructions
798 can be used to move the values.
800 On some machines, though, the converse is true: fixed-point machine modes
801 may not go in floating registers. This is true if the floating registers
802 normalize any value stored in them, because storing a non-floating value
803 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
804 fixed-point machine modes in floating registers. But if the floating
805 registers do not automatically normalize, if you can store any bit pattern
806 in one and retrieve it unchanged without a trap, then any machine mode may
807 go in a floating register, so you can define this macro to say so.
809 The primary significance of special floating registers is rather that they
810 are the registers acceptable in floating point arithmetic instructions.
811 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
812 writing the proper constraints for those instructions.
814 On some machines, the floating registers are especially slow to access, so
815 that it is better to store a value in a stack frame than in such a register
816 if floating point arithmetic is not being done. As long as the floating
817 registers are not in class `GENERAL_REGS', they will not be used unless some
818 pattern's constraint asks for one. */
819 #define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)
821 /* A C expression that is nonzero if it is desirable to choose register
822 allocation so as to avoid move instructions between a value of mode MODE1
823 and a value of mode MODE2.
825 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
826 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
827 zero. */
828 #define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2)
830 /* Define this macro if the compiler should avoid copies to/from CCmode
831 registers. You should only define this macro if support fo copying to/from
832 CCmode is incomplete. */
833 #define AVOID_CCMODE_COPIES
835 \f
836 /* Register Classes. */
838 /* An enumeral type that must be defined with all the register class names as
839 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
840 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
841 which is not a register class but rather tells how many classes there are.
843 Each register class has a number, which is the value of casting the class
844 name to type `int'. The number serves as an index in many of the tables
845 described below. */
846 enum reg_class
847 {
848 NO_REGS,
849 ICC_REGS,
850 FCC_REGS,
851 CC_REGS,
852 ICR_REGS,
853 FCR_REGS,
854 CR_REGS,
855 LCR_REG,
856 LR_REG,
857 GR8_REGS,
858 GR9_REGS,
859 GR89_REGS,
860 FDPIC_REGS,
861 FDPIC_FPTR_REGS,
862 FDPIC_CALL_REGS,
863 SPR_REGS,
864 QUAD_ACC_REGS,
865 ACCG_REGS,
866 QUAD_FPR_REGS,
867 QUAD_REGS,
868 GPR_REGS,
869 ALL_REGS,
870 LIM_REG_CLASSES
871 };
873 #define GENERAL_REGS GPR_REGS
875 /* The number of distinct register classes, defined as follows:
877 #define N_REG_CLASSES (int) LIM_REG_CLASSES */
878 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
880 /* An initializer containing the names of the register classes as C string
881 constants. These names are used in writing some of the debugging dumps. */
882 #define REG_CLASS_NAMES { \
905 }
907 /* An initializer containing the contents of the register classes, as integers
908 which are bit masks. The Nth integer specifies the contents of class N.
909 The way the integer MASK is interpreted is that register R is in the class
910 if `MASK & (1 << R)' is 1.
912 When the machine has more than 32 registers, an integer does not suffice.
913 Then the integers are replaced by sub-initializers, braced groupings
914 containing several integers. Each sub-initializer must be suitable as an
915 initializer for the type `HARD_REG_SET' which is defined in
916 `hard-reg-set.h'. */
917 #define REG_CLASS_CONTENTS \
941 }
943 #define EVEN_ACC_REGS QUAD_ACC_REGS
944 #define ACC_REGS QUAD_ACC_REGS
945 #define FEVEN_REGS QUAD_FPR_REGS
946 #define FPR_REGS QUAD_FPR_REGS
947 #define EVEN_REGS QUAD_REGS
949 /* A C expression whose value is a register class containing hard register
950 REGNO. In general there is more than one such class; choose a class which
951 is "minimal", meaning that no smaller class also contains the register. */
954 #define REGNO_REG_CLASS(REGNO) regno_reg_class [REGNO]
956 /* A macro whose definition is the name of the class to which a valid base
957 register must belong. A base register is one used in an address which is
958 the register value plus a displacement. */
959 #define BASE_REG_CLASS GPR_REGS
961 /* A macro whose definition is the name of the class to which a valid index
962 register must belong. An index register is one used in an address where its
963 value is either multiplied by a scale factor or added to another register
964 (as well as added to a displacement). */
965 #define INDEX_REG_CLASS GPR_REGS
967 /* A C expression which is nonzero if register number NUM is suitable for use
968 as a base register in operand addresses. It may be either a suitable hard
969 register or a pseudo register that has been allocated such a hard register. */
970 #define REGNO_OK_FOR_BASE_P(NUM) \
971 ((NUM) < FIRST_PSEUDO_REGISTER \
972 ? GPR_P (NUM) \
973 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
975 /* A C expression which is nonzero if register number NUM is suitable for use
976 as an index register in operand addresses. It may be either a suitable hard
977 register or a pseudo register that has been allocated such a hard register.
979 The difference between an index register and a base register is that the
980 index register may be scaled. If an address involves the sum of two
981 registers, neither one of them scaled, then either one may be labeled the
982 "base" and the other the "index"; but whichever labeling is used must fit
983 the machine's constraints of which registers may serve in each capacity.
984 The compiler will try both labelings, looking for one that is valid, and
985 will reload one or both registers only if neither labeling works. */
986 #define REGNO_OK_FOR_INDEX_P(NUM) \
987 ((NUM) < FIRST_PSEUDO_REGISTER \
988 ? GPR_P (NUM) \
989 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
991 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
992 frv_secondary_reload_class (CLASS, MODE, X)
994 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
995 frv_secondary_reload_class (CLASS, MODE, X)
997 /* A C expression for the maximum number of consecutive registers of
998 class CLASS needed to hold a value of mode MODE.
1000 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
1001 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
1002 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
1004 This macro helps control the handling of multiple-word values in
1005 the reload pass.
1007 This declaration is required. */
1008 #define CLASS_MAX_NREGS(CLASS, MODE) frv_class_max_nregs (CLASS, MODE)
1010 #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x)))
1012 \f
1013 /* Basic Stack Layout. */
1015 /* Structure to describe information about a saved range of registers */
1028 /* Register ranges to look into saving. */
1039 /* Values for save_p field. */
1044 /* Structure used to define the frv stack. */
1058 /* register range information */
1060 /* offset to store each register */
1062 /* whether to save register (& reg+1) */
1066 /* Define this macro if pushing a word onto the stack moves the stack pointer
1067 to a smaller address. */
1068 #define STACK_GROWS_DOWNWARD 1
1070 /* Define this macro to nonzero if the addresses of local variable slots
1071 are at negative offsets from the frame pointer. */
1072 #define FRAME_GROWS_DOWNWARD 1
1074 /* Offset from the frame pointer to the first local variable slot to be
1075 allocated.
1077 If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the
1078 first slot's length from `STARTING_FRAME_OFFSET'. Otherwise, it is found by
1079 adding the length of the first slot to the value `STARTING_FRAME_OFFSET'. */
1080 #define STARTING_FRAME_OFFSET 0
1082 /* Offset from the stack pointer register to the first location at which
1083 outgoing arguments are placed. If not specified, the default value of zero
1084 is used. This is the proper value for most machines.
1086 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
1087 location at which outgoing arguments are placed. */
1088 #define STACK_POINTER_OFFSET 0
1090 /* Offset from the argument pointer register to the first argument's address.
1091 On some machines it may depend on the data type of the function.
1093 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
1094 argument's address. */
1095 #define FIRST_PARM_OFFSET(FUNDECL) 0
1097 /* A C expression whose value is RTL representing the address in a stack frame
1098 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
1099 an RTL expression for the address of the stack frame itself.
1101 If you don't define this macro, the default is to return the value of
1102 FRAMEADDR--that is, the stack frame address is also the address of the stack
1103 word that points to the previous frame. */
1104 #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) frv_dynamic_chain_address (FRAMEADDR)
1106 /* A C expression whose value is RTL representing the value of the return
1107 address for the frame COUNT steps up from the current frame, after the
1108 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
1109 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
1110 defined.
1112 The value of the expression must always be the correct address when COUNT is
1113 zero, but may be `NULL_RTX' if there is not way to determine the return
1114 address of other frames. */
1115 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) frv_return_addr_rtx (COUNT, FRAMEADDR)
1117 #define RETURN_POINTER_REGNUM LR_REGNO
1119 /* A C expression whose value is RTL representing the location of the incoming
1120 return address at the beginning of any function, before the prologue. This
1121 RTL is either a `REG', indicating that the return value is saved in `REG',
1122 or a `MEM' representing a location in the stack.
1124 You only need to define this macro if you want to support call frame
1125 debugging information like that provided by DWARF 2. */
1126 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM)
1128 \f
1129 /* Register That Address the Stack Frame. */
1131 /* The register number of the stack pointer register, which must also be a
1132 fixed register according to `FIXED_REGISTERS'. On most machines, the
1133 hardware determines which register this is. */
1134 #define STACK_POINTER_REGNUM (GPR_FIRST + 1)
1136 /* The register number of the frame pointer register, which is used to access
1137 automatic variables in the stack frame. On some machines, the hardware
1138 determines which register this is. On other machines, you can choose any
1139 register you wish for this purpose. */
1140 #define FRAME_POINTER_REGNUM (GPR_FIRST + 2)
1142 /* The register number of the arg pointer register, which is used to access the
1143 function's argument list. On some machines, this is the same as the frame
1144 pointer register. On some machines, the hardware determines which register
1145 this is. On other machines, you can choose any register you wish for this
1146 purpose. If this is not the same register as the frame pointer register,
1147 then you must mark it as a fixed register according to `FIXED_REGISTERS', or
1148 arrange to be able to eliminate it. */
1150 /* On frv this is a fake register that is eliminated in
1151 terms of either the frame pointer or stack pointer. */
1152 #define ARG_POINTER_REGNUM AP_FIRST
1154 /* Register numbers used for passing a function's static chain pointer. If
1155 register windows are used, the register number as seen by the called
1156 function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as
1157 seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers
1158 are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined.
1160 The static chain register need not be a fixed register.
1162 If the static chain is passed in memory, these macros should not be defined;
1163 instead, the next two macros should be defined. */
1164 #define STATIC_CHAIN_REGNUM (GPR_FIRST + 7)
1165 #define STATIC_CHAIN_INCOMING_REGNUM (GPR_FIRST + 7)
1167 \f
1168 /* Eliminating the Frame Pointer and the Arg Pointer. */
1170 /* If defined, this macro specifies a table of register pairs used to eliminate
1171 unneeded registers that point into the stack frame. If it is not defined,
1172 the only elimination attempted by the compiler is to replace references to
1173 the frame pointer with references to the stack pointer.
1175 The definition of this macro is a list of structure initializations, each of
1176 which specifies an original and replacement register.
1178 On some machines, the position of the argument pointer is not known until
1179 the compilation is completed. In such a case, a separate hard register must
1180 be used for the argument pointer. This register can be eliminated by
1181 replacing it with either the frame pointer or the argument pointer,
1182 depending on whether or not the frame pointer has been eliminated.
1184 In this case, you might specify:
1185 #define ELIMINABLE_REGS \
1186 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1187 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1188 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1190 Note that the elimination of the argument pointer with the stack pointer is
1191 specified first since that is the preferred elimination. */
1193 #define ELIMINABLE_REGS \
1194 { \
1195 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1196 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1197 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
1198 }
1200 /* This macro returns the initial difference between the specified pair
1201 of registers. */
1203 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1204 (OFFSET) = frv_initial_elimination_offset (FROM, TO)
1206 \f
1207 /* Passing Function Arguments on the Stack. */
1209 /* If defined, the maximum amount of space required for outgoing arguments will
1210 be computed and placed into the variable
1211 `crtl->outgoing_args_size'. No space will be pushed onto the
1212 stack for each call; instead, the function prologue should increase the
1213 stack frame size by this amount.
1215 Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not
1216 proper. */
1217 #define ACCUMULATE_OUTGOING_ARGS 1
1219 \f
1220 /* The number of register assigned to holding function arguments. */
1222 #define FRV_NUM_ARG_REGS 6
1224 /* A C type for declaring a variable that is used as the first argument of
1225 `FUNCTION_ARG' and other related values. For some target machines, the type
1226 `int' suffices and can hold the number of bytes of argument so far.
1228 There is no need to record in `CUMULATIVE_ARGS' anything about the arguments
1229 that have been passed on the stack. The compiler has other variables to
1230 keep track of that. For target machines on which all arguments are passed
1231 on the stack, there is no need to store anything in `CUMULATIVE_ARGS';
1232 however, the data structure must exist and should not be empty, so use
1233 `int'. */
1234 #define CUMULATIVE_ARGS int
1236 /* A C statement (sans semicolon) for initializing the variable CUM for the
1237 state at the beginning of the argument list. The variable has type
1238 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1239 of the function which will receive the args, or 0 if the args are to a
1240 compiler support library function. The value of INDIRECT is nonzero when
1241 processing an indirect call, for example a call through a function pointer.
1242 The value of INDIRECT is zero for a call to an explicitly named function, a
1243 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1244 arguments for the function being compiled.
1246 When processing a call to a compiler support library function, LIBNAME
1247 identifies which one. It is a `symbol_ref' rtx which contains the name of
1248 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1249 being processed. Thus, each time this macro is called, either LIBNAME or
1250 FNTYPE is nonzero, but never both of them at once. */
1252 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1253 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FNDECL, FALSE)
1255 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1256 arguments for the function being compiled. If this macro is undefined,
1257 `INIT_CUMULATIVE_ARGS' is used instead.
1259 The value passed for LIBNAME is always 0, since library routines with
1260 special calling conventions are never compiled with GCC. The argument
1261 LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'. */
1263 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1264 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, NULL, TRUE)
1266 /* A C expression that is nonzero if REGNO is the number of a hard register in
1267 which function arguments are sometimes passed. This does *not* include
1268 implicit arguments such as the static chain and the structure-value address.
1269 On many machines, no registers can be used for this purpose since all
1270 function arguments are pushed on the stack. */
1271 #define FUNCTION_ARG_REGNO_P(REGNO) \
1272 ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) <= LAST_ARG_REGNUM))
1274 \f
1275 /* How Scalar Function Values are Returned. */
1277 /* The number of the hard register that is used to return a scalar value from a
1278 function call. */
1279 #define RETURN_VALUE_REGNUM (GPR_FIRST + 8)
1281 #define FUNCTION_VALUE_REGNO_P(REGNO) frv_function_value_regno_p (REGNO)
1283 \f
1284 /* How Large Values are Returned. */
1286 /* The number of the register that is used to pass the structure
1287 value address. */
1288 #define FRV_STRUCT_VALUE_REGNUM (GPR_FIRST + 3)
1290 \f
1291 /* Function Entry and Exit. */
1293 /* Define this macro as a C expression that is nonzero if the return
1294 instruction or the function epilogue ignores the value of the stack pointer;
1295 in other words, if it is safe to delete an instruction to adjust the stack
1296 pointer before a return from the function.
1298 Note that this macro's value is relevant only for functions for which frame
1299 pointers are maintained. It is never safe to delete a final stack
1300 adjustment in a function that has no frame pointer, and the compiler knows
1301 this regardless of `EXIT_IGNORE_STACK'. */
1302 #define EXIT_IGNORE_STACK 1
1303 \f
1304 /* Generating Code for Profiling. */
1306 /* A C statement or compound statement to output to FILE some assembler code to
1307 call the profiling subroutine `mcount'. Before calling, the assembler code
1308 must load the address of a counter variable into a register where `mcount'
1309 expects to find the address. The name of this variable is `LP' followed by
1310 the number LABELNO, so you would generate the name using `LP%d' in a
1311 `fprintf'.
1313 The details of how the address should be passed to `mcount' are determined
1314 by your operating system environment, not by GCC. To figure them out,
1315 compile a small program for profiling using the system's installed C
1316 compiler and look at the assembler code that results.
1318 This declaration must be present, but it can be an abort if profiling is
1319 not implemented. */
1321 #define FUNCTION_PROFILER(FILE, LABELNO)
1323 /* Trampolines for Nested Functions. */
1325 /* A C expression for the size in bytes of the trampoline, as an integer. */
1326 #define TRAMPOLINE_SIZE frv_trampoline_size ()
1328 /* Alignment required for trampolines, in bits.
1330 If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for
1331 aligning trampolines. */
1332 #define TRAMPOLINE_ALIGNMENT (TARGET_FDPIC ? 64 : 32)
1334 /* Define this macro if trampolines need a special subroutine to do their work.
1335 The macro should expand to a series of `asm' statements which will be
1336 compiled with GCC. They go in a library function named
1337 `__transfer_from_trampoline'.
1339 If you need to avoid executing the ordinary prologue code of a compiled C
1340 function when you jump to the subroutine, you can do so by placing a special
1341 label of your own in the assembler code. Use one `asm' statement to
1342 generate an assembler label, and another to make the label global. Then
1343 trampolines can use that label to jump directly to your special assembler
1344 code. */
1346 #ifdef __FRV_UNDERSCORE__
1348 #else
1350 #endif
1352 #define Twrite _write
1354 #if ! __FRV_FDPIC__
1355 #define TRANSFER_FROM_TRAMPOLINE \
1356 extern int Twrite (int, const void *, unsigned); \
1357 \
1358 void \
1359 __trampoline_setup (short * addr, int size, int fnaddr, int sc) \
1360 { \
1361 extern short __trampoline_template[]; \
1362 short * to = addr; \
1363 short * from = &__trampoline_template[0]; \
1364 int i; \
1365 \
1366 if (size < 20) \
1367 { \
1370 exit (-1); \
1371 } \
1372 \
1373 to[0] = from[0]; \
1374 to[1] = (short)(fnaddr); \
1375 to[2] = from[2]; \
1376 to[3] = (short)(sc); \
1377 to[4] = from[4]; \
1378 to[5] = (short)(fnaddr >> 16); \
1379 to[6] = from[6]; \
1380 to[7] = (short)(sc >> 16); \
1381 to[8] = from[8]; \
1382 to[9] = from[9]; \
1383 \
1384 for (i = 0; i < 20; i++) \
1386 } \
1387 \
1397 #else
1398 #define TRANSFER_FROM_TRAMPOLINE \
1399 extern int Twrite (int, const void *, unsigned); \
1400 \
1401 void \
1402 __trampoline_setup (addr, size, fnaddr, sc) \
1403 short * addr; \
1404 int size; \
1405 int fnaddr; \
1406 int sc; \
1407 { \
1408 extern short __trampoline_template[]; \
1409 short * from = &__trampoline_template[0]; \
1410 int i; \
1411 short **desc = (short **)addr; \
1412 short * to = addr + 4; \
1413 \
1414 if (size != 32) \
1415 { \
1418 exit (-1); \
1419 } \
1420 \
1421 /* Create a function descriptor with the address of the code below \
1422 and NULL as the FDPIC value. We don't need the real GOT value \
1423 here, since we don't use it, so we use NULL, that is just as \
1425 desc[0] = to; \
1426 desc[1] = NULL; \
1427 size -= 8; \
1428 \
1429 to[0] = from[0]; \
1430 to[1] = (short)(fnaddr); \
1431 to[2] = from[2]; \
1432 to[3] = (short)(sc); \
1433 to[4] = from[4]; \
1434 to[5] = (short)(fnaddr >> 16); \
1435 to[6] = from[6]; \
1436 to[7] = (short)(sc >> 16); \
1437 to[8] = from[8]; \
1438 to[9] = from[9]; \
1439 to[10] = from[10]; \
1440 to[11] = from[11]; \
1441 \
1442 for (i = 0; i < size; i++) \
1444 } \
1445 \
1456 );
1457 #endif
1459 \f
1460 /* Addressing Modes. */
1462 /* A number, the maximum number of registers that can appear in a valid memory
1463 address. Note that it is up to you to specify a value equal to the maximum
1464 number that `TARGET_LEGITIMATE_ADDRESS_P' would ever accept. */
1465 #define MAX_REGS_PER_ADDRESS 2
1467 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1468 use as a base register. For hard registers, it should always accept those
1469 which the hardware permits and reject the others. Whether the macro accepts
1470 or rejects pseudo registers must be controlled by `REG_OK_STRICT' as
1471 described above. This usually requires two variant definitions, of which
1472 `REG_OK_STRICT' controls the one actually used. */
1473 #ifdef REG_OK_STRICT
1474 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1475 #else
1476 #define REG_OK_FOR_BASE_P(X) GPR_AP_OR_PSEUDO_P (REGNO (X))
1477 #endif
1479 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1480 use as an index register.
1482 The difference between an index register and a base register is that the
1483 index register may be scaled. If an address involves the sum of two
1484 registers, neither one of them scaled, then either one may be labeled the
1485 "base" and the other the "index"; but whichever labeling is used must fit
1486 the machine's constraints of which registers may serve in each capacity.
1487 The compiler will try both labelings, looking for one that is valid, and
1488 will reload one or both registers only if neither labeling works. */
1489 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1491 #define FIND_BASE_TERM frv_find_base_term
1493 /* The load-and-update commands allow pre-modification in addresses.
1494 The index has to be in a register. */
1495 #define HAVE_PRE_MODIFY_REG 1
1497 \f
1498 /* We define extra CC modes in frv-modes.def so we need a selector. */
1500 #define SELECT_CC_MODE frv_select_cc_mode
1502 /* A C expression whose value is one if it is always safe to reverse a
1503 comparison whose mode is MODE. If `SELECT_CC_MODE' can ever return MODE for
1504 a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)'
1505 must be zero.
1507 You need not define this macro if it would always returns zero or if the
1508 floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
1509 example, here is the definition used on the SPARC, where floating-point
1510 inequality comparisons are always given `CCFPEmode':
1512 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */
1514 /* On frv, don't consider floating point comparisons to be reversible. In
1515 theory, fp equality comparisons can be reversible. */
1516 #define REVERSIBLE_CC_MODE(MODE) \
1517 ((MODE) == CCmode || (MODE) == CC_UNSmode || (MODE) == CC_NZmode)
1519 \f
1520 /* Describing Relative Costs of Operations. */
1522 /* A C expression for the cost of a branch instruction. A value of 1 is the
1523 default; other values are interpreted relative to that. */
1524 #define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int
1526 /* Define this macro as a C expression which is nonzero if accessing less than
1527 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1528 word of memory, i.e., if such access require more than one instruction or if
1529 there is no difference in cost between byte and (aligned) word loads.
1531 When this macro is not defined, the compiler will access a field by finding
1532 the smallest containing object; when it is defined, a fullword load will be
1533 used if alignment permits. Unless bytes accesses are faster than word
1534 accesses, using word accesses is preferable since it may eliminate
1535 subsequent memory access if subsequent accesses occur to other fields in the
1536 same word of the structure, but to different bytes. */
1537 #define SLOW_BYTE_ACCESS 1
1539 /* Define this macro if it is as good or better to call a constant function
1540 address than to call an address kept in a register. */
1541 #define NO_FUNCTION_CSE 1
1543 \f
1544 /* Dividing the output into sections. */
1546 /* A C expression whose value is a string containing the assembler operation
1547 that should precede instructions and read-only data. Normally `".text"' is
1548 right. */
1551 /* A C expression whose value is a string containing the assembler operation to
1552 identify the following data as writable initialized data. Normally
1553 `".data"' is right. */
1558 /* Short Data Support */
1561 #undef INIT_SECTION_ASM_OP
1562 #undef FINI_SECTION_ASM_OP
1566 #undef CTORS_SECTION_ASM_OP
1567 #undef DTORS_SECTION_ASM_OP
1571 /* A C expression whose value is a string containing the assembler operation to
1572 switch to the fixup section that records all initialized pointers in a -fpic
1573 program so they can be changed program startup time if the program is loaded
1574 at a different address than linked for. */
1576 \f
1577 /* Position Independent Code. */
1579 /* A C expression that is nonzero if X is a legitimate immediate operand on the
1580 target machine when generating position independent code. You can assume
1581 that X satisfies `CONSTANT_P', so you need not check this. You can also
1582 assume FLAG_PIC is true, so you need not check it either. You need not
1583 define this macro if all constants (including `SYMBOL_REF') can be immediate
1584 operands when generating position independent code. */
1585 #define LEGITIMATE_PIC_OPERAND_P(X) \
1586 ( GET_CODE (X) == CONST_INT \
1587 || GET_CODE (X) == CONST_DOUBLE \
1588 || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \
1589 || got12_operand (X, VOIDmode)) \
1591 \f
1592 /* The Overall Framework of an Assembler File. */
1594 /* A C string constant describing how to begin a comment in the target
1595 assembler language. The compiler assumes that the comment will end at the
1596 end of the line. */
1599 /* A C string constant for text to be output before each `asm' statement or
1600 group of consecutive ones. Normally this is `"#APP"', which is a comment
1601 that has no effect on most assemblers but tells the GNU assembler that it
1602 must check the lines that follow for all valid assembler constructs. */
1605 /* A C string constant for text to be output after each `asm' statement or
1606 group of consecutive ones. Normally this is `"#NO_APP"', which tells the
1607 GNU assembler to resume making the time-saving assumptions that are valid
1608 for ordinary compiler output. */
1611 \f
1612 /* Output of Data. */
1614 /* This is how to output a label to dwarf/dwarf2. */
1615 #define ASM_OUTPUT_DWARF_ADDR(STREAM, LABEL) \
1616 do { \
1618 assemble_name (STREAM, LABEL); \
1619 } while (0)
1621 /* Whether to emit the gas specific dwarf2 line number support. */
1622 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DEBUG_LOC)
1623 \f
1624 /* Output of Uninitialized Variables. */
1626 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1627 assembler definition of a local-common-label named NAME whose size is SIZE
1628 bytes. The variable ROUNDED is the size rounded up to whatever alignment
1629 the caller wants.
1631 Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
1632 before and after that, output the additional assembler syntax for defining
1633 the name, and a newline.
1635 This macro controls how the assembler definitions of uninitialized static
1636 variables are output. */
1637 #undef ASM_OUTPUT_LOCAL
1639 #undef ASM_OUTPUT_ALIGNED_LOCAL
1641 /* This is for final.c, because it is used by ASM_DECLARE_OBJECT_NAME. */
1644 /* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional
1645 parameter - the DECL of variable to be output, if there is one.
1646 This macro can be called with DECL == NULL_TREE. If you define
1647 this macro, it is used in place of `ASM_OUTPUT_LOCAL' and
1648 `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in
1649 handling the destination of the variable. */
1650 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
1651 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \
1652 do { \
1653 if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1655 else \
1656 switch_to_section (bss_section); \
1657 ASM_OUTPUT_ALIGN (STREAM, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \
1658 ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL); \
1659 ASM_OUTPUT_SKIP (STREAM, (SIZE) ? (SIZE) : 1); \
1660 } while (0)
1662 \f
1663 /* Output and Generation of Labels. */
1665 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1666 assembler definition of a label named NAME. Use the expression
1667 `assemble_name (STREAM, NAME)' to output the name itself; before and after
1668 that, output the additional assembler syntax for defining the name, and a
1669 newline. */
1670 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1671 do { \
1672 assemble_name (STREAM, NAME); \
1674 } while (0)
1676 /* Globalizing directive for a label. */
1679 #undef ASM_GENERATE_INTERNAL_LABEL
1680 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1681 do { \
1683 } while (0)
1685 \f
1686 /* Macros Controlling Initialization Routines. */
1688 #undef INIT_SECTION_ASM_OP
1690 /* If defined, `main' will call `__main' despite the presence of
1691 `INIT_SECTION_ASM_OP'. This macro should be defined for systems where the
1692 init section is not actually run automatically, but is still useful for
1693 collecting the lists of constructors and destructors. */
1694 #define INVOKE__main
1695 \f
1696 /* Output of Assembler Instructions. */
1698 /* A C initializer containing the assembler's names for the machine registers,
1699 each one as a C string constant. This is what translates register numbers
1700 in the compiler into assembler language. */
1701 #define REGISTER_NAMES \
1702 { \
1711 \
1720 \
1728 }
1730 /* Define this macro if you are using an unusual assembler that
1731 requires different names for the machine instructions.
1733 The definition is a C statement or statements which output an
1734 assembler instruction opcode to the stdio stream STREAM. The
1735 macro-operand PTR is a variable of type `char *' which points to
1736 the opcode name in its "internal" form--the form that is written
1737 in the machine description. The definition should output the
1738 opcode name to STREAM, performing any translation you desire, and
1739 increment the variable PTR to point at the end of the opcode so
1740 that it will not be output twice.
1742 In fact, your macro definition may process less than the entire
1743 opcode name, or more than the opcode name; but if you want to
1744 process text that includes `%'-sequences to substitute operands,
1745 you must take care of the substitution yourself. Just be sure to
1746 increment PTR over whatever text should not be output normally.
1748 If you need to look at the operand values, they can be found as the
1749 elements of `recog_operand'.
1751 If the macro definition does nothing, the instruction is output in
1752 the usual way. */
1754 #define ASM_OUTPUT_OPCODE(STREAM, PTR)\
1755 (PTR) = frv_asm_output_opcode (STREAM, PTR)
1757 /* If defined, a C statement to be executed just prior to the output
1758 of assembler code for INSN, to modify the extracted operands so
1759 they will be output differently.
1761 Here the argument OPVEC is the vector containing the operands
1762 extracted from INSN, and NOPERANDS is the number of elements of
1763 the vector which contain meaningful data for this insn. The
1764 contents of this vector are what will be used to convert the insn
1765 template into assembler code, so you can change the assembler
1766 output by changing the contents of the vector.
1768 This macro is useful when various assembler syntaxes share a single
1769 file of instruction patterns; by defining this macro differently,
1770 you can cause a large class of instructions to be output
1771 differently (such as with rearranged operands). Naturally,
1772 variations in assembler syntax affecting individual insn patterns
1773 ought to be handled by writing conditional output routines in
1774 those patterns.
1776 If this macro is not defined, it is equivalent to a null statement. */
1778 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)\
1779 frv_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1781 #undef USER_LABEL_PREFIX
1787 \f
1788 /* Output of dispatch tables. */
1790 /* This macro should be provided on machines where the addresses in a dispatch
1791 table are relative to the table's own address.
1793 The definition should be a C statement to output to the stdio stream STREAM
1794 an assembler pseudo-instruction to generate a difference between two labels.
1795 VALUE and REL are the numbers of two internal labels. The definitions of
1796 these labels are output using `(*targetm.asm_out.internal_label)', and they must be
1797 printed in the same way here. For example,
1799 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */
1800 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1803 /* This macro should be provided on machines where the addresses in a dispatch
1804 table are absolute.
1806 The definition should be a C statement to output to the stdio stream STREAM
1807 an assembler pseudo-instruction to generate a reference to a label. VALUE
1808 is the number of an internal label whose definition is output using
1809 `(*targetm.asm_out.internal_label)'. For example,
1811 fprintf (STREAM, "\t.word L%d\n", VALUE) */
1812 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1815 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1816 \f
1817 /* Assembler Commands for Exception Regions. */
1819 /* Define this macro to 0 if your target supports DWARF 2 frame unwind
1820 information, but it does not yet work with exception handling. Otherwise,
1821 if your target supports this information (if it defines
1822 `INCOMING_RETURN_ADDR_RTX' and `OBJECT_FORMAT_ELF'), GCC will provide
1823 a default definition of 1.
1825 If this macro is defined to 1, the DWARF 2 unwinder will be the default
1826 exception handling mechanism; otherwise, setjmp/longjmp will be used by
1827 default.
1829 If this macro is defined to anything, the DWARF 2 unwinder will be used
1830 instead of inline unwinders and __unwind_function in the non-setjmp case. */
1831 #define DWARF2_UNWIND_INFO 1
1833 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
1834 \f
1835 /* Assembler Commands for Alignment. */
1837 #undef ASM_OUTPUT_SKIP
1838 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1841 /* A C statement to output to the stdio stream STREAM an assembler command to
1842 advance the location counter to a multiple of 2 to the POWER bytes. POWER
1843 will be a C expression of type `int'. */
1844 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1847 /* Inside the text section, align with unpacked nops rather than zeros. */
1848 #define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \
1850 \f
1851 /* Macros Affecting all Debug Formats. */
1853 /* A C expression that returns the DBX register number for the compiler
1854 register number REGNO. In simple cases, the value of this expression may be
1855 REGNO itself. But sometimes there are some registers that the compiler
1856 knows about and DBX does not, or vice versa. In such cases, some register
1857 may need to have one number in the compiler and another for DBX.
1859 If two registers have consecutive numbers inside GCC, and they can be
1860 used as a pair to hold a multiword value, then they *must* have consecutive
1861 numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers
1862 will be unable to access such a pair, because they expect register pairs to
1863 be consecutive in their own numbering scheme.
1865 If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not
1866 preserve register pairs, then what you must do instead is redefine the
1867 actual register numbering scheme.
1869 This declaration is required. */
1870 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1872 #undef PREFERRED_DEBUGGING_TYPE
1873 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1874 \f
1875 /* Miscellaneous Parameters. */
1877 /* An alias for a machine mode name. This is the machine mode that elements of
1878 a jump-table should have. */
1879 #define CASE_VECTOR_MODE SImode
1881 /* Define this macro if operations between registers with integral mode smaller
1882 than a word are always performed on the entire register. Most RISC machines
1883 have this property and most CISC machines do not. */
1884 #define WORD_REGISTER_OPERATIONS 1
1886 /* Define this macro to be a C expression indicating when insns that read
1887 memory in MODE, an integral mode narrower than a word, set the bits outside
1888 of MODE to be either the sign-extension or the zero-extension of the data
1889 read. Return `SIGN_EXTEND' for values of MODE for which the insn
1890 sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other
1891 modes.
1893 This macro is not called with MODE non-integral or with a width greater than
1894 or equal to `BITS_PER_WORD', so you may return any value in this case. Do
1895 not define this macro if it would always return `UNKNOWN'. On machines where
1896 this macro is defined, you will normally define it as the constant
1897 `SIGN_EXTEND' or `ZERO_EXTEND'. */
1898 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1900 /* Define if loading short immediate values into registers sign extends. */
1901 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1903 /* The maximum number of bytes that a single instruction can move quickly from
1904 memory to memory. */
1905 #define MOVE_MAX 8
1907 /* A C expression which is nonzero if on this machine it is safe to "convert"
1908 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1909 than INPREC) by merely operating on it as if it had only OUTPREC bits.
1911 On many machines, this expression can be 1.
1913 When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for
1914 which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the
1915 case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve
1916 things. */
1917 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1919 /* An alias for the machine mode for pointers. On most machines, define this
1920 to be the integer mode corresponding to the width of a hardware pointer;
1921 `SImode' on 32-bit machine or `DImode' on 64-bit machines. On some machines
1922 you must define this to be one of the partial integer modes, such as
1923 `PSImode'.
1925 The width of `Pmode' must be at least as large as the value of
1926 `POINTER_SIZE'. If it is not equal, you must define the macro
1927 `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'. */
1928 #define Pmode SImode
1930 /* An alias for the machine mode used for memory references to functions being
1931 called, in `call' RTL expressions. On most machines this should be
1932 `QImode'. */
1933 #define FUNCTION_MODE QImode
1935 /* A C expression for the maximum number of instructions to execute via
1936 conditional execution instructions instead of a branch. A value of
1937 BRANCH_COST+1 is the default if the machine does not use
1938 cc0, and 1 if it does use cc0. */
1939 #define MAX_CONDITIONAL_EXECUTE frv_condexec_insns
1941 /* A C expression to modify the code described by the conditional if
1942 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
1943 FALSE_EXPR for converting if-then and if-then-else code to conditional
1944 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
1945 tests cannot be converted. */
1946 #define IFCVT_MODIFY_TESTS(CE_INFO, TRUE_EXPR, FALSE_EXPR) \
1947 frv_ifcvt_modify_tests (CE_INFO, &TRUE_EXPR, &FALSE_EXPR)
1949 /* A C expression to modify the code described by the conditional if
1950 information CE_INFO, for the basic block BB, possibly updating the tests in
1951 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
1952 if-then-else code to conditional instructions. OLD_TRUE and OLD_FALSE are
1953 the previous tests. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if
1954 the tests cannot be converted. */
1955 #define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \
1956 frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR)
1958 /* A C expression to modify the code described by the conditional if
1959 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
1960 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
1961 insn cannot be converted to be executed conditionally. */
1962 #define IFCVT_MODIFY_INSN(CE_INFO, PATTERN, INSN) \
1963 (PATTERN) = frv_ifcvt_modify_insn (CE_INFO, PATTERN, INSN)
1965 /* A C expression to perform any final machine dependent modifications in
1966 converting code to conditional execution in the code described by the
1967 conditional if information CE_INFO. */
1968 #define IFCVT_MODIFY_FINAL(CE_INFO) frv_ifcvt_modify_final (CE_INFO)
1970 /* A C expression to cancel any machine dependent modifications in converting
1971 code to conditional execution in the code described by the conditional if
1972 information CE_INFO. */
1973 #define IFCVT_MODIFY_CANCEL(CE_INFO) frv_ifcvt_modify_cancel (CE_INFO)
1975 /* Initialize the machine-specific static data for if-conversion. */
1976 #define IFCVT_MACHDEP_INIT(CE_INFO) frv_ifcvt_machdep_init (CE_INFO)
1978 /* The definition of the following macro results in that the 2nd jump
1979 optimization (after the 2nd insn scheduling) is minimal. It is
1980 necessary to define when start cycle marks of insns (TImode is used
1981 for this) is used for VLIW insn packing. Some jump optimizations
1982 make such marks invalid. These marks are corrected for some
1983 (minimal) optimizations. ??? Probably the macro is temporary.
1984 Final solution could making the 2nd jump optimizations before the
1985 2nd instruction scheduling or corrections of the marks for all jump
1986 optimizations. Although some jump optimizations are actually
1987 deoptimizations for VLIW (super-scalar) processors. */
1989 #define MINIMAL_SECOND_JUMP_OPTIMIZATION
1992 /* If the following macro is defined and nonzero and deterministic
1993 finite state automata are used for pipeline hazard recognition, we
1994 will try to exchange insns in queue ready to improve the schedule.
1995 The more macro value, the more tries will be made. */
1996 #define FIRST_CYCLE_MULTIPASS_SCHEDULING 1
1998 /* The following macro is used only when value of
1999 FIRST_CYCLE_MULTIPASS_SCHEDULING is nonzero. The more macro value,
2000 the more tries will be made to choose better schedule. If the
2001 macro value is zero or negative there will be no multi-pass
2002 scheduling. */
2003 #define FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD frv_sched_lookahead
2005 enum frv_builtins
2006 {
2007 FRV_BUILTIN_MAND,
2008 FRV_BUILTIN_MOR,
2009 FRV_BUILTIN_MXOR,
2010 FRV_BUILTIN_MNOT,
2011 FRV_BUILTIN_MAVEH,
2012 FRV_BUILTIN_MSATHS,
2013 FRV_BUILTIN_MSATHU,
2014 FRV_BUILTIN_MADDHSS,
2015 FRV_BUILTIN_MADDHUS,
2016 FRV_BUILTIN_MSUBHSS,
2017 FRV_BUILTIN_MSUBHUS,
2018 FRV_BUILTIN_MPACKH,
2019 FRV_BUILTIN_MQADDHSS,
2020 FRV_BUILTIN_MQADDHUS,
2021 FRV_BUILTIN_MQSUBHSS,
2022 FRV_BUILTIN_MQSUBHUS,
2023 FRV_BUILTIN_MUNPACKH,
2024 FRV_BUILTIN_MDPACKH,
2025 FRV_BUILTIN_MBTOH,
2026 FRV_BUILTIN_MHTOB,
2027 FRV_BUILTIN_MCOP1,
2028 FRV_BUILTIN_MCOP2,
2029 FRV_BUILTIN_MROTLI,
2030 FRV_BUILTIN_MROTRI,
2031 FRV_BUILTIN_MWCUT,
2032 FRV_BUILTIN_MSLLHI,
2033 FRV_BUILTIN_MSRLHI,
2034 FRV_BUILTIN_MSRAHI,
2035 FRV_BUILTIN_MEXPDHW,
2036 FRV_BUILTIN_MEXPDHD,
2037 FRV_BUILTIN_MMULHS,
2038 FRV_BUILTIN_MMULHU,
2039 FRV_BUILTIN_MMULXHS,
2040 FRV_BUILTIN_MMULXHU,
2041 FRV_BUILTIN_MMACHS,
2042 FRV_BUILTIN_MMACHU,
2043 FRV_BUILTIN_MMRDHS,
2044 FRV_BUILTIN_MMRDHU,
2045 FRV_BUILTIN_MQMULHS,
2046 FRV_BUILTIN_MQMULHU,
2047 FRV_BUILTIN_MQMULXHU,
2048 FRV_BUILTIN_MQMULXHS,
2049 FRV_BUILTIN_MQMACHS,
2050 FRV_BUILTIN_MQMACHU,
2051 FRV_BUILTIN_MCPXRS,
2052 FRV_BUILTIN_MCPXRU,
2053 FRV_BUILTIN_MCPXIS,
2054 FRV_BUILTIN_MCPXIU,
2055 FRV_BUILTIN_MQCPXRS,
2056 FRV_BUILTIN_MQCPXRU,
2057 FRV_BUILTIN_MQCPXIS,
2058 FRV_BUILTIN_MQCPXIU,
2059 FRV_BUILTIN_MCUT,
2060 FRV_BUILTIN_MCUTSS,
2061 FRV_BUILTIN_MWTACC,
2062 FRV_BUILTIN_MWTACCG,
2063 FRV_BUILTIN_MRDACC,
2064 FRV_BUILTIN_MRDACCG,
2065 FRV_BUILTIN_MTRAP,
2066 FRV_BUILTIN_MCLRACC,
2067 FRV_BUILTIN_MCLRACCA,
2068 FRV_BUILTIN_MDUNPACKH,
2069 FRV_BUILTIN_MBTOHE,
2070 FRV_BUILTIN_MQXMACHS,
2071 FRV_BUILTIN_MQXMACXHS,
2072 FRV_BUILTIN_MQMACXHS,
2073 FRV_BUILTIN_MADDACCS,
2074 FRV_BUILTIN_MSUBACCS,
2075 FRV_BUILTIN_MASACCS,
2076 FRV_BUILTIN_MDADDACCS,
2077 FRV_BUILTIN_MDSUBACCS,
2078 FRV_BUILTIN_MDASACCS,
2079 FRV_BUILTIN_MABSHS,
2080 FRV_BUILTIN_MDROTLI,
2081 FRV_BUILTIN_MCPLHI,
2082 FRV_BUILTIN_MCPLI,
2083 FRV_BUILTIN_MDCUTSSI,
2084 FRV_BUILTIN_MQSATHS,
2085 FRV_BUILTIN_MQLCLRHS,
2086 FRV_BUILTIN_MQLMTHS,
2087 FRV_BUILTIN_MQSLLHI,
2088 FRV_BUILTIN_MQSRAHI,
2089 FRV_BUILTIN_MHSETLOS,
2090 FRV_BUILTIN_MHSETLOH,
2091 FRV_BUILTIN_MHSETHIS,
2092 FRV_BUILTIN_MHSETHIH,
2093 FRV_BUILTIN_MHDSETS,
2094 FRV_BUILTIN_MHDSETH,
2095 FRV_BUILTIN_SMUL,
2096 FRV_BUILTIN_UMUL,
2097 FRV_BUILTIN_PREFETCH0,
2098 FRV_BUILTIN_PREFETCH,
2099 FRV_BUILTIN_SMASS,
2100 FRV_BUILTIN_SMSSS,
2101 FRV_BUILTIN_SMU,
2102 FRV_BUILTIN_SCUTSS,
2103 FRV_BUILTIN_ADDSS,
2104 FRV_BUILTIN_SUBSS,
2105 FRV_BUILTIN_SLASS,
2106 FRV_BUILTIN_IACCreadll,
2107 FRV_BUILTIN_IACCreadl,
2108 FRV_BUILTIN_IACCsetll,
2109 FRV_BUILTIN_IACCsetl,
2110 FRV_BUILTIN_SCAN,
2111 FRV_BUILTIN_READ8,
2112 FRV_BUILTIN_READ16,
2113 FRV_BUILTIN_READ32,
2114 FRV_BUILTIN_READ64,
2115 FRV_BUILTIN_WRITE8,
2116 FRV_BUILTIN_WRITE16,
2117 FRV_BUILTIN_WRITE32,
2118 FRV_BUILTIN_WRITE64
2119 };
2120 #define FRV_BUILTIN_FIRST_NONMEDIA FRV_BUILTIN_SMUL
2122 /* Enable prototypes on the call rtl functions. */
2123 #define MD_CALL_PROTOTYPES 1
2125 #define CPU_UNITS_QUERY 1