gcc/config/sh/crt1.asm

   1 /* Copyright (C) 2000, 2001, 2003, 2004, 2005, 2006
   2    Free Software Foundation, Inc.
   3    This file was pretty much copied from newlib.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it
   8 under the terms of the GNU General Public License as published by the
   9 Free Software Foundation; either version 2, or (at your option) any
  10 later version.
  11
  12 In addition to the permissions in the GNU General Public License, the
  13 Free Software Foundation gives you unlimited permission to link the
  14 compiled version of this file into combinations with other programs,
  15 and to distribute those combinations without any restriction coming
  16 from the use of this file.  (The General Public License restrictions
  17 do apply in other respects; for example, they cover modification of
  18 the file, and distribution when not linked into a combine
  19 executable.)
  20
  21 GCC is distributed in the hope that it will be useful,
  22 but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  24 General Public License for more details.
  25
  26 You should have received a copy of the GNU General Public License
  27 along with this program; see the file COPYING.  If not, write to
  28 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  29 Boston, MA 02110-1301, USA.  */
  30
  31 #ifdef MMU_SUPPORT
  32         /* Section used for exception/timer interrupt stack area */
  33         .section .data.vbr.stack,"aw"
  34         .align 4
  35         .global __ST_VBR
  36 __ST_VBR:
  37         .zero 1024 * 2          /* ; 2k for VBR handlers */
  38 /* Label at the highest stack address where the stack grows from */
  39 __timer_stack:
  40 #endif /* MMU_SUPPORT */
  41
  42         /* ;----------------------------------------
  43         Normal newlib crt1.asm */
  44
  45 #ifdef __SH5__
  46         .section .data,"aw"
  47         .global ___data
  48 ___data:
  49
  50         .section .rodata,"a"
  51         .global ___rodata
  52 ___rodata:
  53
  54 #define ICCR_BASE  0x01600000
  55 #define OCCR_BASE  0x01e00000
  56 #define MMUIR_BASE 0x00000000
  57 #define MMUDR_BASE 0x00800000
  58
  59 #define PTE_ENABLED     1
  60 #define PTE_DISABLED    0
  61
  62 #define PTE_SHARED (1 << 1)
  63 #define PTE_NOT_SHARED  0
  64
  65 #define PTE_CB_UNCACHEABLE  0
  66 #define PTE_CB_DEVICE       1
  67 #define PTE_CB_CACHEABLE_WB 2
  68 #define PTE_CB_CACHEABLE_WT 3
  69
  70 #define PTE_SZ_4KB   (0 << 3)
  71 #define PTE_SZ_64KB  (1 << 3)
  72 #define PTE_SZ_1MB   (2 << 3)
  73 #define PTE_SZ_512MB (3 << 3)
  74
  75 #define PTE_PRR      (1 << 6)
  76 #define PTE_PRX      (1 << 7)
  77 #define PTE_PRW      (1 << 8)
  78 #define PTE_PRU      (1 << 9)
  79
  80 #define SR_MMU_BIT          31
  81 #define SR_BL_BIT           28
  82
  83 #define ALIGN_4KB  (0xfff)
  84 #define ALIGN_1MB  (0xfffff)
  85 #define ALIGN_512MB (0x1fffffff)
  86
  87 #define DYNACON_BASE               0x0f000000
  88 #define DM_CB_DLINK_BASE           0x0c000000
  89 #define DM_DB_DLINK_BASE           0x0b000000
  90
  91 #define FEMI_AREA_0                0x00000000
  92 #define FEMI_AREA_1                0x04000000
  93 #define FEMI_AREA_2                0x05000000
  94 #define FEMI_AREA_3                0x06000000
  95 #define FEMI_AREA_4                0x07000000
  96 #define FEMI_CB                    0x08000000
  97
  98 #define EMI_BASE                   0X80000000
  99
 100 #define DMA_BASE                   0X0e000000
 101
 102 #define CPU_BASE                   0X0d000000
 103
 104 #define PERIPH_BASE                0X09000000
 105 #define DMAC_BASE                  0x0e000000
 106 #define INTC_BASE                  0x0a000000
 107 #define CPRC_BASE                  0x0a010000
 108 #define TMU_BASE                   0x0a020000
 109 #define SCIF_BASE                  0x0a030000
 110 #define RTC_BASE                   0x0a040000
 111
 112
 113
 114 #define LOAD_CONST32(val, reg) \
 115         movi    ((val) >> 16) & 65535, reg; \
 116         shori   (val) & 65535, reg
 117
 118 #define LOAD_PTEH_VAL(sym, align, bits, scratch_reg, reg) \
 119         LOAD_ADDR (sym, reg); \
 120         LOAD_CONST32 ((align), scratch_reg); \
 121         andc    reg, scratch_reg, reg; \
 122         LOAD_CONST32 ((bits), scratch_reg); \
 123         or      reg, scratch_reg, reg
 124
 125 #define LOAD_PTEL_VAL(sym, align, bits, scratch_reg, reg) \
 126         LOAD_ADDR (sym, reg); \
 127         LOAD_CONST32 ((align), scratch_reg); \
 128         andc    reg, scratch_reg, reg; \
 129         LOAD_CONST32 ((bits), scratch_reg); \
 130         or      reg, scratch_reg, reg
 131
 132 #define SET_PTE(pte_addr_reg, pteh_val_reg, ptel_val_reg) \
 133         putcfg  pte_addr_reg, 0, r63; \
 134         putcfg  pte_addr_reg, 1, ptel_val_reg; \
 135         putcfg  pte_addr_reg, 0, pteh_val_reg
 136
 137 #if __SH5__ == 64
 138         .section .text,"ax"
 139 #define LOAD_ADDR(sym, reg) \
 140         movi    (sym >> 48) & 65535, reg; \
 141         shori   (sym >> 32) & 65535, reg; \
 142         shori   (sym >> 16) & 65535, reg; \
 143         shori   sym & 65535, reg
 144 #else
 145         .mode   SHmedia
 146         .section .text..SHmedia32,"ax"
 147 #define LOAD_ADDR(sym, reg) \
 148         movi    (sym >> 16) & 65535, reg; \
 149         shori   sym & 65535, reg
 150 #endif
 151         .global start
 152 start:
 153         LOAD_ADDR (_stack, r15)
 154
 155 #ifdef MMU_SUPPORT
 156         ! Set up the VM using the MMU and caches
 157
 158         ! .vm_ep is first instruction to execute
 159         ! after VM initialization
 160         pt/l    .vm_ep, tr1
 161
 162         ! Configure instruction cache (ICCR)
 163         movi    3, r2
 164         movi    0, r3
 165         LOAD_ADDR (ICCR_BASE, r1)
 166         putcfg  r1, 0, r2
 167         putcfg  r1, 1, r3
 168
 169         ! movi  7, r2 ! write through
 170         ! Configure operand cache (OCCR)
 171         LOAD_ADDR (OCCR_BASE, r1)
 172         putcfg  r1, 0, r2
 173         putcfg  r1, 1, r3
 174
 175         ! Disable all PTE translations
 176         LOAD_ADDR (MMUIR_BASE, r1)
 177         LOAD_ADDR (MMUDR_BASE, r2)
 178         movi    64, r3
 179         pt/l    .disable_ptes_loop, tr0
 180 .disable_ptes_loop:
 181         putcfg  r1, 0, r63
 182         putcfg  r2, 0, r63
 183         addi    r1, 16, r1
 184         addi    r2, 16, r2
 185         addi    r3, -1, r3
 186         bgt     r3, r63, tr0
 187
 188         LOAD_ADDR (MMUIR_BASE, r1)
 189
 190         ! FEMI instruction mappings
 191         !   Area 0 - 1Mb cacheable at 0x00000000
 192         !   Area 1 - None
 193         !   Area 2 - 1Mb cacheable at 0x05000000
 194         !          - 1Mb cacheable at 0x05100000
 195         !   Area 3 - None
 196         !   Area 4 - None
 197
 198         ! Map a 1Mb page for instructions at 0x00000000
 199         LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 200         LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
 201         SET_PTE (r1, r2, r3)
 202
 203         ! Map a 1Mb page for instructions at 0x05000000
 204         addi    r1, 16, r1
 205         LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 206         LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
 207         SET_PTE (r1, r2, r3)
 208
 209         ! Map a 1Mb page for instructions at 0x05100000
 210         addi    r1, 16, r1
 211         LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 212         LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRX | PTE_PRU, r25, r3)
 213         SET_PTE (r1, r2, r3)
 214
 215         ! Map a 512M page for instructions at EMI base
 216         addi    r1, 16, r1
 217         LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 218         LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRX | PTE_PRU, r25, r3)
 219         SET_PTE (r1, r2, r3)
 220
 221         ! Map a 4K page for instructions at DM_DB_DLINK_BASE
 222         addi    r1, 16, r1
 223         LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 224         LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRX | PTE_PRU, r25, r3)
 225         SET_PTE (r1, r2, r3)
 226
 227         LOAD_ADDR (MMUDR_BASE, r1)
 228
 229         ! FEMI data mappings
 230         !   Area 0 - 1Mb cacheable at 0x00000000
 231         !   Area 1 - 1Mb device at 0x04000000
 232         !   Area 2 - 1Mb cacheable at 0x05000000
 233         !          - 1Mb cacheable at 0x05100000
 234         !   Area 3 - None
 235         !   Area 4 - None
 236         !   CB     - 1Mb device at 0x08000000
 237
 238         ! Map a 1Mb page for data at 0x00000000
 239         LOAD_PTEH_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 240         LOAD_PTEL_VAL (FEMI_AREA_0, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 241         SET_PTE (r1, r2, r3)
 242
 243         ! Map a 1Mb page for data at 0x04000000
 244         addi    r1, 16, r1
 245         LOAD_PTEH_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 246         LOAD_PTEL_VAL (FEMI_AREA_1, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 247         SET_PTE (r1, r2, r3)
 248
 249         ! Map a 1Mb page for data at 0x05000000
 250         addi    r1, 16, r1
 251         LOAD_PTEH_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 252         LOAD_PTEL_VAL (FEMI_AREA_2, ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 253         SET_PTE (r1, r2, r3)
 254
 255         ! Map a 1Mb page for data at 0x05100000
 256         addi    r1, 16, r1
 257         LOAD_PTEH_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 258         LOAD_PTEL_VAL ((FEMI_AREA_2+0x100000), ALIGN_1MB, PTE_CB_CACHEABLE_WB | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 259         SET_PTE (r1, r2, r3)
 260
 261         ! Map a 4K page for registers at 0x08000000
 262         addi    r1, 16, r1
 263         LOAD_PTEH_VAL (FEMI_CB, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 264         LOAD_PTEL_VAL (FEMI_CB, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 265         SET_PTE (r1, r2, r3)
 266
 267         ! Map a 512M page for data at EMI
 268         addi    r1, 16, r1
 269         LOAD_PTEH_VAL (EMI_BASE, ALIGN_512MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 270         LOAD_PTEL_VAL (EMI_BASE, ALIGN_512MB, PTE_CB_CACHEABLE_WB | PTE_SZ_512MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 271         SET_PTE (r1, r2, r3)
 272
 273         ! Map a 4K page for DYNACON at DYNACON_BASE
 274         addi    r1, 16, r1
 275         LOAD_PTEH_VAL (DYNACON_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 276         LOAD_PTEL_VAL (DYNACON_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 277         SET_PTE (r1, r2, r3)
 278
 279         ! Map a 4K page for instructions at DM_DB_DLINK_BASE
 280         addi    r1, 16, r1
 281         LOAD_PTEH_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 282         LOAD_PTEL_VAL (DM_DB_DLINK_BASE, ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 283         SET_PTE (r1, r2, r3)
 284
 285         ! Map a 4K page for data at DM_DB_DLINK_BASE+0x1000
 286         addi    r1, 16, r1
 287         LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 288         LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x1000), ALIGN_4KB, PTE_CB_UNCACHEABLE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 289         SET_PTE (r1, r2, r3)
 290
 291         ! Map a 4K page for stack DM_DB_DLINK_BASE+0x2000
 292         addi    r1, 16, r1
 293         LOAD_PTEH_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 294         LOAD_PTEL_VAL ((DM_DB_DLINK_BASE+0x2000), ALIGN_4KB, PTE_CB_CACHEABLE_WB | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 295         SET_PTE (r1, r2, r3)
 296
 297         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 298         ! 0x0c000000 - 0x0c0fffff
 299         addi    r1, 16, r1
 300         LOAD_PTEH_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 301         LOAD_PTEL_VAL (DM_CB_DLINK_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 302         SET_PTE (r1, r2, r3)
 303
 304         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 305         ! 0x0c100000 - 0x0c1fffff
 306         addi    r1, 16, r1
 307         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 308         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 309         SET_PTE (r1, r2, r3)
 310
 311         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 312         ! 0x0c200000 - 0x0c2fffff
 313         addi    r1, 16, r1
 314         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 315         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 316         SET_PTE (r1, r2, r3)
 317
 318         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 319         ! 0x0c400000 - 0x0c4fffff
 320         addi    r1, 16, r1
 321         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 322         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 323         SET_PTE (r1, r2, r3)
 324
 325         ! Map a 1M page for DM_CB_BASE2 at DM_CB_DLINK
 326         ! 0x0c800000 - 0x0c8fffff
 327         addi    r1, 16, r1
 328         LOAD_PTEH_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 329         LOAD_PTEL_VAL ((DM_CB_DLINK_BASE+0x800000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 330         SET_PTE (r1, r2, r3)
 331
 332         ! Map a 4K page for DMA control registers
 333         addi    r1, 16, r1
 334         LOAD_PTEH_VAL (DMA_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 335         LOAD_PTEL_VAL (DMA_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 336         SET_PTE (r1, r2, r3)
 337
 338         ! Map lots of 4K pages for peripherals
 339
 340         ! /* peripheral */
 341         addi    r1, 16, r1
 342         LOAD_PTEH_VAL (PERIPH_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 343         LOAD_PTEL_VAL (PERIPH_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 344         SET_PTE (r1, r2, r3)
 345         ! /* dmac */
 346         addi    r1, 16, r1
 347         LOAD_PTEH_VAL (DMAC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 348         LOAD_PTEL_VAL (DMAC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 349         SET_PTE (r1, r2, r3)
 350         ! /* intc */
 351         addi    r1, 16, r1
 352         LOAD_PTEH_VAL (INTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 353         LOAD_PTEL_VAL (INTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 354         SET_PTE (r1, r2, r3)
 355         ! /* rtc */
 356         addi    r1, 16, r1
 357         LOAD_PTEH_VAL (RTC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 358         LOAD_PTEL_VAL (RTC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 359         SET_PTE (r1, r2, r3)
 360         ! /* dmac */
 361         addi    r1, 16, r1
 362         LOAD_PTEH_VAL (TMU_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 363         LOAD_PTEL_VAL (TMU_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 364         SET_PTE (r1, r2, r3)
 365         ! /* scif */
 366         addi    r1, 16, r1
 367         LOAD_PTEH_VAL (SCIF_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 368         LOAD_PTEL_VAL (SCIF_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 369         SET_PTE (r1, r2, r3)
 370         ! /* cprc */
 371         addi    r1, 16, r1
 372         LOAD_PTEH_VAL (CPRC_BASE, ALIGN_4KB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 373         LOAD_PTEL_VAL (CPRC_BASE, ALIGN_4KB, PTE_CB_DEVICE | PTE_SZ_4KB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 374         SET_PTE (r1, r2, r3)
 375
 376         ! Map CPU WPC registers
 377         addi    r1, 16, r1
 378         LOAD_PTEH_VAL (CPU_BASE, ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 379         LOAD_PTEL_VAL (CPU_BASE, ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 380         SET_PTE (r1, r2, r3)
 381         addi    r1, 16, r1
 382
 383         LOAD_PTEH_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 384         LOAD_PTEL_VAL ((CPU_BASE+0x100000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 385         SET_PTE (r1, r2, r3)
 386
 387         addi    r1, 16, r1
 388         LOAD_PTEH_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 389         LOAD_PTEL_VAL ((CPU_BASE+0x200000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 390         SET_PTE (r1, r2, r3)
 391
 392         addi    r1, 16, r1
 393         LOAD_PTEH_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_ENABLED | PTE_NOT_SHARED, r25, r2)
 394         LOAD_PTEL_VAL ((CPU_BASE+0x400000), ALIGN_1MB, PTE_CB_DEVICE | PTE_SZ_1MB | PTE_PRR | PTE_PRW | PTE_PRU, r25, r3)
 395         SET_PTE (r1, r2, r3)
 396
 397         ! Switch over to virtual addressing and enabled cache
 398         getcon  sr, r1
 399         movi    1, r2
 400         shlli   r2, SR_BL_BIT, r2
 401         or      r1, r2, r1
 402         putcon  r1, ssr
 403         getcon  sr, r1
 404         movi    1, r2
 405         shlli   r2, SR_MMU_BIT, r2
 406         or      r1, r2, r1
 407         putcon  r1, ssr
 408         gettr   tr1, r1
 409         putcon  r1, spc
 410         synco
 411         rte
 412
 413         ! VM entry point.  From now on, we are in VM mode.
 414 .vm_ep:
 415
 416         ! Install the trap handler, by seeding vbr with the
 417         ! correct value, and by assigning sr.bl = 0.
 418
 419         LOAD_ADDR (vbr_start, r1)
 420         putcon  r1, vbr
 421         movi    ~(1<<28), r1
 422         getcon  sr, r2
 423         and     r1, r2, r2
 424         putcon  r2, sr
 425 #endif /* MMU_SUPPORT */
 426
 427         pt/l    .Lzero_bss_loop, tr0
 428         pt/l    _init, tr5
 429         pt/l    ___setup_argv_and_call_main, tr6
 430         pt/l    _exit, tr7
 431
 432         ! zero out bss
 433         LOAD_ADDR (_edata, r0)
 434         LOAD_ADDR (_end, r1)
 435 .Lzero_bss_loop:
 436         stx.q   r0, r63, r63
 437         addi    r0, 8, r0
 438         bgt/l   r1, r0, tr0
 439
 440         LOAD_ADDR (___data, r26)
 441         LOAD_ADDR (___rodata, r27)
 442
 443 #ifdef __SH_FPU_ANY__
 444         getcon  sr, r0
 445         ! enable the FP unit, by resetting SR.FD
 446         ! also zero out SR.FR, SR.SZ and SR.PR, as mandated by the ABI
 447         movi    0, r1
 448         shori   0xf000, r1
 449         andc    r0, r1, r0
 450         putcon  r0, sr
 451 #if __SH5__ == 32
 452         pt/l ___set_fpscr, tr0
 453         movi    0, r4
 454         blink   tr0, r18
 455 #endif
 456 #endif
 457
 458         ! arrange for exit to call fini
 459         pt/l    _atexit, tr1
 460         LOAD_ADDR (_fini, r2)
 461         blink   tr1, r18
 462
 463         ! call init
 464         blink   tr5, r18
 465
 466         ! call the mainline
 467         blink   tr6, r18
 468
 469         ! call exit
 470         blink   tr7, r18
 471         ! We should never return from _exit but in case we do we would enter the
 472         ! the following tight loop. This avoids executing any data that might follow.
 473 limbo:
 474         pt/l limbo, tr0
 475         blink tr0, r63
 476
 477 #ifdef MMU_SUPPORT
 478         ! All these traps are handled in the same place.
 479         .balign 256
 480 vbr_start:
 481         pt/l handler, tr0       ! tr0 trashed.
 482         blink tr0, r63
 483         .balign 256
 484 vbr_100:
 485         pt/l handler, tr0       ! tr0 trashed.
 486         blink tr0, r63
 487 vbr_100_end:
 488         .balign 256
 489 vbr_200:
 490         pt/l handler, tr0       ! tr0 trashed.
 491         blink tr0, r63
 492         .balign 256
 493 vbr_300:
 494         pt/l handler, tr0       ! tr0 trashed.
 495         blink tr0, r63
 496         .balign 256
 497 vbr_400:        ! Should be at vbr+0x400
 498 handler:
 499         /* If the trap handler is there call it */
 500         LOAD_ADDR (__superh_trap_handler, r2)
 501         pta chandler,tr2
 502         beq r2, r63, tr2 /* If zero, ie not present branch around to chandler */
 503         /* Now call the trap handler with as much of the context unchanged as possible.
 504            Move trapping address into R18 to make it look like the trap point */
 505         getcon spc, r18
 506         pt/l __superh_trap_handler, tr0
 507         blink tr0, r7
 508 chandler:
 509         getcon  spc, r62
 510         getcon expevt, r2
 511         pt/l    _exit, tr0
 512         blink   tr0, r63
 513
 514         /* Simulated trap handler */
 515         .section        .text..SHmedia32,"ax"
 516 gcc2_compiled.:
 517         .section        .debug_abbrev
 518 .Ldebug_abbrev0:
 519         .section        .text..SHmedia32
 520 .Ltext0:
 521         .section        .debug_info
 522 .Ldebug_info0:
 523         .section        .debug_line
 524 .Ldebug_line0:
 525         .section        .text..SHmedia32,"ax"
 526         .align 5
 527         .global __superh_trap_handler
 528         .type   __superh_trap_handler,@function
 529 __superh_trap_handler:
 530 .LFB1:
 531         ptabs   r18, tr0
 532         addi.l  r15, -8, r15
 533         st.l    r15, 4, r14
 534         addi.l  r15, -8, r15
 535         add.l   r15, r63, r14
 536         st.l    r14, 0, r2
 537          ptabs r7, tr0
 538         addi.l  r14, 8, r14
 539         add.l   r14, r63, r15
 540         ld.l    r15, 4, r14
 541         addi.l  r15, 8, r15
 542         blink   tr0, r63
 543 .LFE1:
 544 .Lfe1:
 545         .size   __superh_trap_handler,.Lfe1-__superh_trap_handler
 546
 547         .section        .text..SHmedia32
 548 .Letext0:
 549
 550         .section        .debug_info
 551         .ualong 0xa7
 552         .uaword 0x2
 553         .ualong .Ldebug_abbrev0
 554         .byte   0x4
 555         .byte   0x1
 556         .ualong .Ldebug_line0
 557         .ualong .Letext0
 558         .ualong .Ltext0
 559         .string "trap_handler.c"
 560
 561         .string "xxxxxxxxxxxxxxxxxxxxxxxxxxxx"
 562
 563         .string "GNU C 2.97-sh5-010522"
 564
 565         .byte   0x1
 566         .byte   0x2
 567         .ualong 0x9a
 568         .byte   0x1
 569         .string "_superh_trap_handler"
 570
 571         .byte   0x1
 572         .byte   0x2
 573         .byte   0x1
 574         .ualong .LFB1
 575         .ualong .LFE1
 576         .byte   0x1
 577         .byte   0x5e
 578         .byte   0x3
 579         .string "trap_reason"
 580
 581         .byte   0x1
 582         .byte   0x1
 583         .ualong 0x9a
 584         .byte   0x2
 585         .byte   0x91
 586         .byte   0x0
 587         .byte   0x0
 588         .byte   0x4
 589         .string "unsigned int"
 590
 591         .byte   0x4
 592         .byte   0x7
 593         .byte   0x0
 594
 595         .section        .debug_abbrev
 596         .byte   0x1
 597         .byte   0x11
 598         .byte   0x1
 599         .byte   0x10
 600         .byte   0x6
 601         .byte   0x12
 602         .byte   0x1
 603         .byte   0x11
 604         .byte   0x1
 605         .byte   0x3
 606         .byte   0x8
 607         .byte   0x1b
 608         .byte   0x8
 609         .byte   0x25
 610         .byte   0x8
 611         .byte   0x13
 612         .byte   0xb
 613         .byte   0,0
 614         .byte   0x2
 615         .byte   0x2e
 616         .byte   0x1
 617         .byte   0x1
 618         .byte   0x13
 619         .byte   0x3f
 620         .byte   0xc
 621         .byte   0x3
 622         .byte   0x8
 623         .byte   0x3a
 624         .byte   0xb
 625         .byte   0x3b
 626         .byte   0xb
 627         .byte   0x27
 628         .byte   0xc
 629         .byte   0x11
 630         .byte   0x1
 631         .byte   0x12
 632         .byte   0x1
 633         .byte   0x40
 634         .byte   0xa
 635         .byte   0,0
 636         .byte   0x3
 637         .byte   0x5
 638         .byte   0x0
 639         .byte   0x3
 640         .byte   0x8
 641         .byte   0x3a
 642         .byte   0xb
 643         .byte   0x3b
 644         .byte   0xb
 645         .byte   0x49
 646         .byte   0x13
 647         .byte   0x2
 648         .byte   0xa
 649         .byte   0,0
 650         .byte   0x4
 651         .byte   0x24
 652         .byte   0x0
 653         .byte   0x3
 654         .byte   0x8
 655         .byte   0xb
 656         .byte   0xb
 657         .byte   0x3e
 658         .byte   0xb
 659         .byte   0,0
 660         .byte   0
 661
 662         .section        .debug_pubnames
 663         .ualong 0x27
 664         .uaword 0x2
 665         .ualong .Ldebug_info0
 666         .ualong 0xab
 667         .ualong 0x5b
 668         .string "_superh_trap_handler"
 669
 670         .ualong 0x0
 671
 672         .section        .debug_aranges
 673         .ualong 0x1c
 674         .uaword 0x2
 675         .ualong .Ldebug_info0
 676         .byte   0x4
 677         .byte   0x0
 678         .uaword 0x0,0
 679         .ualong .Ltext0
 680         .ualong .Letext0-.Ltext0
 681         .ualong 0x0
 682         .ualong 0x0
 683         .ident  "GCC: (GNU) 2.97-sh5-010522"
 684 #endif /* MMU_SUPPORT */
 685 #else /* ! __SH5__ */
 686
 687         ! make a place to keep any previous value of the vbr register
 688         ! this will only have a value if it has been set by redboot (for example)
 689         .section .bss
 690 old_vbr:
 691         .long 0
 692 #ifdef PROFILE
 693 profiling_enabled:
 694         .long 0
 695 #endif
 696
 697
 698         .section .text
 699         .global start
 700         .import ___rtos_profiler_start_timer
 701         .weak   ___rtos_profiler_start_timer
 702 start:
 703         mov.l   stack_k,r15
 704
 705 #if defined (__SH3__) || (defined (__SH_FPU_ANY__) && ! defined (__SH2A__)) || defined (__SH4_NOFPU__)
 706 #define VBR_SETUP
 707         ! before zeroing the bss ...
 708         ! if the vbr is already set to vbr_start then the program has been restarted
 709         ! (i.e. it is not the first time the program has been run since reset)
 710         ! reset the vbr to its old value before old_vbr (in bss) is wiped
 711         ! this ensures that the later code does not create a circular vbr chain
 712         stc     vbr, r1
 713         mov.l   vbr_start_k, r2
 714         cmp/eq  r1, r2
 715         bf      0f
 716         ! reset the old vbr value
 717         mov.l   old_vbr_k, r1
 718         mov.l   @r1, r2
 719         ldc     r2, vbr
 720 0:
 721 #endif /* VBR_SETUP */
 722
 723         ! zero out bss
 724         mov.l   edata_k,r0
 725         mov.l   end_k,r1
 726         mov     #0,r2
 727 start_l:
 728         mov.l   r2,@r0
 729         add     #4,r0
 730         cmp/ge  r0,r1
 731         bt      start_l
 732
 733 #if defined (__SH_FPU_ANY__)
 734         mov.l set_fpscr_k, r1
 735         mov #4,r4
 736         jsr @r1
 737         shll16 r4       ! Set DN bit (flush denormal inputs to zero)
 738         lds r3,fpscr    ! Switch to default precision
 739 #endif /* defined (__SH_FPU_ANY__) */
 740
 741 #ifdef VBR_SETUP
 742         ! save the existing contents of the vbr
 743         ! there will only be a prior value when using something like redboot
 744         ! otherwise it will be zero
 745         stc     vbr, r1
 746         mov.l   old_vbr_k, r2
 747         mov.l   r1, @r2
 748         ! setup vbr
 749         mov.l   vbr_start_k, r1
 750         ldc     r1,vbr
 751 #endif /* VBR_SETUP */
 752
 753         ! if an rtos is exporting a timer start fn,
 754         ! then pick up an SR which does not enable ints
 755         ! (the rtos will take care of this)
 756         mov.l rtos_start_fn, r0
 757         mov.l sr_initial_bare, r1
 758         tst     r0, r0
 759         bt      set_sr
 760
 761         mov.l sr_initial_rtos, r1
 762
 763 set_sr:
 764         ! Set status register (sr)
 765         ldc     r1, sr
 766
 767         ! arrange for exit to call fini
 768         mov.l   atexit_k,r0
 769         mov.l   fini_k,r4
 770         jsr     @r0
 771         nop
 772
 773 #ifdef PROFILE
 774         ! arrange for exit to call _mcleanup (via stop_profiling)
 775         mova    stop_profiling,r0
 776         mov.l   atexit_k,r1
 777         jsr     @r1
 778         mov     r0, r4
 779
 780         ! Call profiler startup code
 781         mov.l monstartup_k, r0
 782         mov.l start_k, r4
 783         mov.l etext_k, r5
 784         jsr @r0
 785         nop
 786
 787         ! enable profiling trap
 788         ! until now any trap 33s will have been ignored
 789         ! This means that all library functions called before this point
 790         ! (directly or indirectly) may have the profiling trap at the start.
 791         ! Therefore, only mcount itself may not have the extra header.
 792         mov.l   profiling_enabled_k2, r0
 793         mov     #1, r1
 794         mov.l   r1, @r0
 795 #endif /* PROFILE */
 796
 797         ! call init
 798         mov.l   init_k,r0
 799         jsr     @r0
 800         nop
 801
 802         ! call the mainline
 803         mov.l   main_k,r0
 804         jsr     @r0
 805         nop
 806
 807         ! call exit
 808         mov     r0,r4
 809         mov.l   exit_k,r0
 810         jsr     @r0
 811         nop
 812
 813                 .balign 4
 814 #ifdef PROFILE
 815 stop_profiling:
 816         # stop mcount counting
 817         mov.l   profiling_enabled_k2, r0
 818         mov     #0, r1
 819         mov.l   r1, @r0
 820
 821         # call mcleanup
 822         mov.l   mcleanup_k, r0
 823         jmp     @r0
 824         nop
 825
 826                 .balign 4
 827 mcleanup_k:
 828         .long __mcleanup
 829 monstartup_k:
 830         .long ___monstartup
 831 profiling_enabled_k2:
 832         .long profiling_enabled
 833 start_k:
 834         .long _start
 835 etext_k:
 836         .long __etext
 837 #endif /* PROFILE */
 838
 839         .align 2
 840 #if defined (__SH_FPU_ANY__)
 841 set_fpscr_k:
 842         .long   ___set_fpscr
 843 #endif /*  defined (__SH_FPU_ANY__) */
 844
 845 stack_k:
 846         .long   _stack
 847 edata_k:
 848         .long   _edata
 849 end_k:
 850         .long   _end
 851 main_k:
 852         .long   ___setup_argv_and_call_main
 853 exit_k:
 854         .long   _exit
 855 atexit_k:
 856         .long   _atexit
 857 init_k:
 858         .long   _init
 859 fini_k:
 860         .long   _fini
 861 #ifdef VBR_SETUP
 862 old_vbr_k:
 863         .long   old_vbr
 864 vbr_start_k:
 865         .long   vbr_start
 866 #endif /* VBR_SETUP */
 867
 868 sr_initial_rtos:
 869         ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
 870         ! Whether profiling or not, keep interrupts masked,
 871         ! the RTOS will enable these if required.
 872         .long 0x600000f1
 873
 874 rtos_start_fn:
 875         .long ___rtos_profiler_start_timer
 876
 877 #ifdef PROFILE
 878 sr_initial_bare:
 879         ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
 880         ! For bare machine, we need to enable interrupts to get profiling working
 881         .long 0x60000001
 882 #else
 883
 884 sr_initial_bare:
 885         ! Privileged mode RB 1 BL 0. Keep BL 0 to allow default trap handlers to work.
 886         ! Keep interrupts disabled - the application will enable as required.
 887         .long 0x600000f1
 888 #endif
 889
 890         ! supplied for backward compatibility only, in case of linking
 891         ! code whose main() was compiled with an older version of GCC.
 892         .global ___main
 893 ___main:
 894         rts
 895         nop
 896 #ifdef VBR_SETUP
 897 ! Exception handlers
 898         .section .text.vbr, "ax"
 899 vbr_start:
 900
 901         .org 0x100
 902 vbr_100:
 903 #ifdef PROFILE
 904         ! Note on register usage.
 905         ! we use r0..r3 as scratch in this code. If we are here due to a trapa for profiling
 906         ! then this is OK as we are just before executing any function code.
 907         ! The other r4..r7 we save explicityl on the stack
 908         ! Remaining registers are saved by normal ABI conventions and we assert we do not
 909         ! use floating point registers.
 910         mov.l expevt_k1, r1
 911         mov.l @r1, r1
 912         mov.l event_mask, r0
 913         and r0,r1
 914         mov.l trapcode_k, r2
 915         cmp/eq r1,r2
 916         bt 1f
 917         bra handler_100   ! if not a trapa, go to default handler
 918         nop
 919 1:
 920         mov.l trapa_k, r0
 921         mov.l @r0, r0
 922         shlr2 r0      ! trapa code is shifted by 2.
 923         cmp/eq #33, r0
 924         bt 2f
 925         bra handler_100
 926         nop
 927 2:
 928
 929         ! If here then it looks like we have trap #33
 930         ! Now we need to call mcount with the following convention
 931         ! Save and restore r4..r7
 932         mov.l   r4,@-r15
 933         mov.l   r5,@-r15
 934         mov.l   r6,@-r15
 935         mov.l   r7,@-r15
 936         sts.l   pr,@-r15
 937
 938         ! r4 is frompc.
 939         ! r5 is selfpc
 940         ! r0 is the branch back address.
 941         ! The code sequence emitted by gcc for the profiling trap is
 942         ! .align 2
 943         ! trapa #33
 944         ! .align 2
 945         ! .long lab Where lab is planted by the compiler. This is the address
 946         ! of a datum that needs to be incremented.
 947         sts pr,  r4     ! frompc
 948         stc spc, r5     ! selfpc
 949         mov #2, r2
 950         not r2, r2      ! pattern to align to 4
 951         and r2, r5      ! r5 now has aligned address
 952 !       add #4, r5      ! r5 now has address of address
 953         mov r5, r2      ! Remember it.
 954 !       mov.l @r5, r5   ! r5 has value of lable (lab in above example)
 955         add #8, r2
 956         ldc r2, spc     ! our return address avoiding address word
 957
 958         ! only call mcount if profiling is enabled
 959         mov.l profiling_enabled_k, r0
 960         mov.l @r0, r0
 961         cmp/eq #0, r0
 962         bt 3f
 963         ! call mcount
 964         mov.l mcount_k, r2
 965         jsr @r2
 966         nop
 967 3:
 968         lds.l @r15+,pr
 969         mov.l @r15+,r7
 970         mov.l @r15+,r6
 971         mov.l @r15+,r5
 972         mov.l @r15+,r4
 973         rte
 974         nop
 975         .balign 4
 976 event_mask:
 977         .long 0xfff
 978 trapcode_k:
 979         .long 0x160
 980 expevt_k1:
 981         .long 0xff000024 ! Address of expevt
 982 trapa_k:
 983         .long 0xff000020
 984 mcount_k:
 985         .long __call_mcount
 986 profiling_enabled_k:
 987         .long profiling_enabled
 988 #endif
 989         ! Non profiling case.
 990 handler_100:
 991         mov.l 2f, r0     ! load the old vbr setting (if any)
 992         mov.l @r0, r0
 993         cmp/eq #0, r0
 994         bf 1f
 995         ! no previous vbr - jump to own generic handler
 996         bra handler
 997         nop
 998 1:      ! there was a previous handler - chain them
 999         add #0x7f, r0    ! 0x7f
1000         add #0x7f, r0    ! 0xfe
1001         add #0x2, r0     ! add 0x100 without corrupting another register
1002         jmp @r0
1003         nop
1004         .balign 4
1005 2:
1006         .long old_vbr
1007
1008         .org 0x400
1009 vbr_400:        ! Should be at vbr+0x400
1010         mov.l 2f, r0     ! load the old vbr setting (if any)
1011         mov.l @r0, r0
1012         cmp/eq #0, r0
1013         ! no previous vbr - jump to own generic handler
1014         bt handler
1015         ! there was a previous handler - chain them
1016         rotcr r0
1017         rotcr r0
1018         add #0x7f, r0    ! 0x1fc
1019         add #0x7f, r0    ! 0x3f8
1020         add #0x02, r0    ! 0x400
1021         rotcl r0
1022         rotcl r0         ! Add 0x400 without corrupting another register
1023         jmp @r0
1024         nop
1025         .balign 4
1026 2:
1027         .long old_vbr
1028 handler:
1029         /* If the trap handler is there call it */
1030         mov.l   superh_trap_handler_k, r0
1031         cmp/eq  #0, r0       ! True if zero.
1032         bf 3f
1033         bra   chandler
1034         nop
1035 3:
1036         ! Here handler available, call it.
1037         /* Now call the trap handler with as much of the context unchanged as possible.
1038            Move trapping address into PR to make it look like the trap point */
1039         stc spc, r1
1040         lds r1, pr
1041         mov.l expevt_k, r4
1042         mov.l @r4, r4 ! r4 is value of expevt, first parameter.
1043         mov r1, r5   ! Remember trapping pc.
1044         mov r1, r6   ! Remember trapping pc.
1045         mov.l chandler_k, r1
1046         mov.l superh_trap_handler_k, r2
1047         ! jmp to trap handler to avoid disturbing pr.
1048         jmp @r2
1049         nop
1050
1051         .org 0x600
1052 vbr_600:
1053 #ifdef PROFILE
1054         ! Should be at vbr+0x600
1055         ! Now we are in the land of interrupts so need to save more state.
1056         ! Save register state
1057         mov.l interrupt_stack_k, r15 ! r15 has been saved to sgr.
1058         mov.l   r0,@-r15
1059         mov.l   r1,@-r15
1060         mov.l   r2,@-r15
1061         mov.l   r3,@-r15
1062         mov.l   r4,@-r15
1063         mov.l   r5,@-r15
1064         mov.l   r6,@-r15
1065         mov.l   r7,@-r15
1066         sts.l   pr,@-r15
1067         sts.l   mach,@-r15
1068         sts.l   macl,@-r15
1069 #if defined(__SH_FPU_ANY__)
1070         ! Save fpul and fpscr, save fr0-fr7 in 64 bit mode
1071         ! and set the pervading precision for the timer_handler
1072         mov     #0,r0
1073         sts.l   fpul,@-r15
1074         sts.l   fpscr,@-r15
1075         lds     r0,fpscr        ! Clear fpscr
1076         fmov    fr0,@-r15
1077         fmov    fr1,@-r15
1078         fmov    fr2,@-r15
1079         fmov    fr3,@-r15
1080         mov.l   pervading_precision_k,r0
1081         fmov    fr4,@-r15
1082         fmov    fr5,@-r15
1083         mov.l   @r0,r0
1084         fmov    fr6,@-r15
1085         fmov    fr7,@-r15
1086         lds     r0,fpscr
1087 #endif /* __SH_FPU_ANY__ */
1088         ! Pass interrupted pc to timer_handler as first parameter (r4).
1089         stc    spc, r4
1090         mov.l timer_handler_k, r0
1091         jsr @r0
1092         nop
1093 #if defined(__SH_FPU_ANY__)
1094         mov     #0,r0
1095         lds     r0,fpscr        ! Clear the fpscr
1096         fmov    @r15+,fr7
1097         fmov    @r15+,fr6
1098         fmov    @r15+,fr5
1099         fmov    @r15+,fr4
1100         fmov    @r15+,fr3
1101         fmov    @r15+,fr2
1102         fmov    @r15+,fr1
1103         fmov    @r15+,fr0
1104         lds.l   @r15+,fpscr
1105         lds.l   @r15+,fpul
1106 #endif /* __SH_FPU_ANY__ */
1107         lds.l @r15+,macl
1108         lds.l @r15+,mach
1109         lds.l @r15+,pr
1110         mov.l @r15+,r7
1111         mov.l @r15+,r6
1112         mov.l @r15+,r5
1113         mov.l @r15+,r4
1114         mov.l @r15+,r3
1115         mov.l @r15+,r2
1116         mov.l @r15+,r1
1117         mov.l @r15+,r0
1118         stc sgr, r15    ! Restore r15, destroyed by this sequence.
1119         rte
1120         nop
1121 #if defined(__SH_FPU_ANY__)
1122         .balign 4
1123 pervading_precision_k:
1124 #define CONCAT1(A,B) A##B
1125 #define CONCAT(A,B) CONCAT1(A,B)
1126         .long CONCAT(__USER_LABEL_PREFIX__,__fpscr_values)+4
1127 #endif
1128 #else
1129         mov.l 2f, r0     ! Load the old vbr setting (if any).
1130         mov.l @r0, r0
1131         cmp/eq #0, r0
1132         ! no previous vbr - jump to own handler
1133         bt chandler
1134         ! there was a previous handler - chain them
1135         rotcr r0
1136         rotcr r0
1137         add #0x7f, r0    ! 0x1fc
1138         add #0x7f, r0    ! 0x3f8
1139         add #0x7f, r0    ! 0x5f4
1140         add #0x03, r0    ! 0x600
1141         rotcl r0
1142         rotcl r0         ! Add 0x600 without corrupting another register
1143         jmp @r0
1144         nop
1145         .balign 4
1146 2:
1147         .long old_vbr
1148 #endif   /* PROFILE code */
1149 chandler:
1150         mov.l expevt_k, r4
1151         mov.l @r4, r4 ! r4 is value of expevt hence making this the return code
1152         mov.l handler_exit_k,r0
1153         jsr   @r0
1154         nop
1155         ! We should never return from _exit but in case we do we would enter the
1156         ! the following tight loop
1157 limbo:
1158         bra limbo
1159         nop
1160         .balign 4
1161 #ifdef PROFILE
1162 interrupt_stack_k:
1163         .long __timer_stack     ! The high end of the stack
1164 timer_handler_k:
1165         .long __profil_counter
1166 #endif
1167 expevt_k:
1168         .long 0xff000024 ! Address of expevt
1169 chandler_k:
1170         .long chandler
1171 superh_trap_handler_k:
1172         .long   __superh_trap_handler
1173 handler_exit_k:
1174         .long _exit
1175         .align 2
1176 ! Simulated compile of trap handler.
1177         .section        .debug_abbrev,"",@progbits
1178 .Ldebug_abbrev0:
1179         .section        .debug_info,"",@progbits
1180 .Ldebug_info0:
1181         .section        .debug_line,"",@progbits
1182 .Ldebug_line0:
1183         .text
1184 .Ltext0:
1185         .align 5
1186         .type   __superh_trap_handler,@function
1187 __superh_trap_handler:
1188 .LFB1:
1189         mov.l   r14,@-r15
1190 .LCFI0:
1191         add     #-4,r15
1192 .LCFI1:
1193         mov     r15,r14
1194 .LCFI2:
1195         mov.l   r4,@r14
1196         lds     r1, pr
1197         add     #4,r14
1198         mov     r14,r15
1199         mov.l   @r15+,r14
1200         rts
1201         nop
1202 .LFE1:
1203 .Lfe1:
1204         .size   __superh_trap_handler,.Lfe1-__superh_trap_handler
1205         .section        .debug_frame,"",@progbits
1206 .Lframe0:
1207         .ualong .LECIE0-.LSCIE0
1208 .LSCIE0:
1209         .ualong 0xffffffff
1210         .byte   0x1
1211         .string ""
1212         .uleb128 0x1
1213         .sleb128 -4
1214         .byte   0x11
1215         .byte   0xc
1216         .uleb128 0xf
1217         .uleb128 0x0
1218         .align 2
1219 .LECIE0:
1220 .LSFDE0:
1221         .ualong .LEFDE0-.LASFDE0
1222 .LASFDE0:
1223         .ualong .Lframe0
1224         .ualong .LFB1
1225         .ualong .LFE1-.LFB1
1226         .byte   0x4
1227         .ualong .LCFI0-.LFB1
1228         .byte   0xe
1229         .uleb128 0x4
1230         .byte   0x4
1231         .ualong .LCFI1-.LCFI0
1232         .byte   0xe
1233         .uleb128 0x8
1234         .byte   0x8e
1235         .uleb128 0x1
1236         .byte   0x4
1237         .ualong .LCFI2-.LCFI1
1238         .byte   0xd
1239         .uleb128 0xe
1240         .align 2
1241 .LEFDE0:
1242         .text
1243 .Letext0:
1244         .section        .debug_info
1245         .ualong 0xb3
1246         .uaword 0x2
1247         .ualong .Ldebug_abbrev0
1248         .byte   0x4
1249         .uleb128 0x1
1250         .ualong .Ldebug_line0
1251         .ualong .Letext0
1252         .ualong .Ltext0
1253         .string "trap_handler.c"
1254         .string "xxxxxxxxxxxxxxxxxxxxxxxxxxxx"
1255         .string "GNU C 3.2 20020529 (experimental)"
1256         .byte   0x1
1257         .uleb128 0x2
1258         .ualong 0xa6
1259         .byte   0x1
1260         .string "_superh_trap_handler"
1261         .byte   0x1
1262         .byte   0x2
1263         .byte   0x1
1264         .ualong .LFB1
1265         .ualong .LFE1
1266         .byte   0x1
1267         .byte   0x5e
1268         .uleb128 0x3
1269         .string "trap_reason"
1270         .byte   0x1
1271         .byte   0x1
1272         .ualong 0xa6
1273         .byte   0x2
1274         .byte   0x91
1275         .sleb128 0
1276         .byte   0x0
1277         .uleb128 0x4
1278         .string "unsigned int"
1279         .byte   0x4
1280         .byte   0x7
1281         .byte   0x0
1282         .section        .debug_abbrev
1283         .uleb128 0x1
1284         .uleb128 0x11
1285         .byte   0x1
1286         .uleb128 0x10
1287         .uleb128 0x6
1288         .uleb128 0x12
1289         .uleb128 0x1
1290         .uleb128 0x11
1291         .uleb128 0x1
1292         .uleb128 0x3
1293         .uleb128 0x8
1294         .uleb128 0x1b
1295         .uleb128 0x8
1296         .uleb128 0x25
1297         .uleb128 0x8
1298         .uleb128 0x13
1299         .uleb128 0xb
1300         .byte   0x0
1301         .byte   0x0
1302         .uleb128 0x2
1303         .uleb128 0x2e
1304         .byte   0x1
1305         .uleb128 0x1
1306         .uleb128 0x13
1307         .uleb128 0x3f
1308         .uleb128 0xc
1309         .uleb128 0x3
1310         .uleb128 0x8
1311         .uleb128 0x3a
1312         .uleb128 0xb
1313         .uleb128 0x3b
1314         .uleb128 0xb
1315         .uleb128 0x27
1316         .uleb128 0xc
1317         .uleb128 0x11
1318         .uleb128 0x1
1319         .uleb128 0x12
1320         .uleb128 0x1
1321         .uleb128 0x40
1322         .uleb128 0xa
1323         .byte   0x0
1324         .byte   0x0
1325         .uleb128 0x3
1326         .uleb128 0x5
1327         .byte   0x0
1328         .uleb128 0x3
1329         .uleb128 0x8
1330         .uleb128 0x3a
1331         .uleb128 0xb
1332         .uleb128 0x3b
1333         .uleb128 0xb
1334         .uleb128 0x49
1335         .uleb128 0x13
1336         .uleb128 0x2
1337         .uleb128 0xa
1338         .byte   0x0
1339         .byte   0x0
1340         .uleb128 0x4
1341         .uleb128 0x24
1342         .byte   0x0
1343         .uleb128 0x3
1344         .uleb128 0x8
1345         .uleb128 0xb
1346         .uleb128 0xb
1347         .uleb128 0x3e
1348         .uleb128 0xb
1349         .byte   0x0
1350         .byte   0x0
1351         .byte   0x0
1352         .section        .debug_pubnames,"",@progbits
1353         .ualong 0x27
1354         .uaword 0x2
1355         .ualong .Ldebug_info0
1356         .ualong 0xb7
1357         .ualong 0x67
1358         .string "_superh_trap_handler"
1359         .ualong 0x0
1360         .section        .debug_aranges,"",@progbits
1361         .ualong 0x1c
1362         .uaword 0x2
1363         .ualong .Ldebug_info0
1364         .byte   0x4
1365         .byte   0x0
1366         .uaword 0x0
1367         .uaword 0x0
1368         .ualong .Ltext0
1369         .ualong .Letext0-.Ltext0
1370         .ualong 0x0
1371         .ualong 0x0
1372 #endif /* VBR_SETUP */
1373 #endif /* ! __SH5__ */