gcc/ChangeLog

   1 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
   2
   3         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
   4         Add web-link to the avr-gcc wiki.
   5
   6 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
   7
   8         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
   9         documentation for a version without argument, which is not supported.
  10
  11 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  12
  13         * config/arm/arm_neon.h
  14         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
  15         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
  16         (vld1_f16_x4, vld1_f32_x4): New.
  17         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
  18         (vld1_bf16_x4): New.
  19         (vld1q_types_x4): Updated to use vld1q_x4
  20         from arm_neon_builtins.def
  21         * config/arm/arm_neon_builtins.def
  22         (vld1_x4): Updated entries.
  23         (vld1q_x4): New entries, but comes from the old vld1_x4
  24         * config/arm/neon.md
  25         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
  26
  27 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  28
  29         * config/arm/arm_neon.h
  30         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
  31         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
  32         (vld1_f16_x3, vld1_f32_x3): New.
  33         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
  34         (vld1_bf16_x3): New.
  35         (vld1q_types_x3): Updated to use vld1q_x3 from
  36         arm_neon_builtins.def
  37         * config/arm/arm_neon_builtins.def
  38         (vld1_x3): Updated entries.
  39         (vld1q_x3): New entries, but comes from the old vld1_x2
  40         * config/arm/neon.md
  41         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
  42
  43 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  44
  45         * config/arm/arm_neon.h
  46         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
  47         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
  48         (vld1_f16_x2, vld1_f32_x2): New.
  49         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
  50         (vld1_bf16_x2): New.
  51         (vld1q_types_x2): Updated to use vld1q_x2 from
  52         arm_neon_builtins.def
  53         * config/arm/arm_neon_builtins.def
  54         (vld1_x2): Updated entries.
  55         (vld1q_x2): New entries, but comes from the old vld1_x2
  56         * config/arm/neon.md
  57         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
  58         neon_vld1_x2<mode>.
  59
  60 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  61
  62         * config/arm/arm_neon.h
  63         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
  64         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
  65         (vst1q_f16_x4, vst1q_f32_x4): New.
  66         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
  67         (vst1q_bf16_x4): New.
  68         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
  69         * config/arm/neon.md
  70         (neon_vst1q_x4<mode>): New.
  71         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
  72         * config/arm/unspecs.md
  73         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
  74
  75 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  76
  77         * config/arm/arm_neon.h
  78         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
  79         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
  80         (vst1q_f16_x3, vst1q_f32_x3): New.
  81         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
  82         (vst1q_bf16_x3): New.
  83         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
  84         * config/arm/neon.md
  85         (neon_vst1q_x3<mode>): New.
  86         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
  87         * config/arm/unspecs.md
  88         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
  89
  90 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
  91
  92         * config/arm/arm_neon.h
  93         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
  94         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
  95         (vst1q_f16_x2, vst1q_f32_x2): New.
  96         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
  97         (vst1q_bf16_x2): New.
  98         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
  99         * config/arm/neon.md
 100         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 101         neon_vst1_x2<mode>.
 102         * config/arm/iterators.md
 103         (VMEMX2): New mode iterator.
 104         (VMEMX2_q): New mode attribute.
 105
 106 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 107
 108         * config/arm/arm_neon.h
 109         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
 110         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
 111         (vst1_f16_x4, vst1_f32_x4): New.
 112         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
 113         (vst1_bf16_x4): New.
 114         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
 115         * config/arm/neon.md (vst1_x4<mode>): New.
 116
 117 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 118
 119         * config/arm/arm_neon.h
 120         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
 121         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
 122         (vst1_f16_x3, vst1_f32_x3): New.
 123         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
 124         (vst1_bf16_x3): New.
 125         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
 126         * config/arm/neon.md (vst1_x3<mode>): New.
 127
 128 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 129
 130         * config/arm/arm_neon.h
 131         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
 132         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
 133         (vst1_f16_x2, vst1_f32_x2): New.
 134         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
 135         (vst1_bf16_x2): New.
 136         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
 137         * config/arm/neon.md (vst1_x2<mode>): New.
 138
 139 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 140
 141         * config/arm/arm_neon.h
 142         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
 143         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
 144         (vld1q_f16_x4, vld1q_f32_x4): New.
 145         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
 146         (vld1q_bf16_x4): New.
 147         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
 148         * config/arm/neon.md
 149         (neon_vld1_x4<mode>): New.
 150         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
 151         * config/arm/unspecs.md
 152         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
 153
 154 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 155
 156         * config/arm/arm_neon.h
 157         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
 158         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
 159         (vld1q_f16_x3, vld1q_f32_x3): New.
 160         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
 161         (vld1q_bf16_x3): New.
 162         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
 163         * config/arm/neon.md
 164         (neon_vld1_x3<mode>): New.
 165         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
 166         * config/arm/unspecs.md
 167         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
 168
 169 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 170
 171         * config/arm/arm_neon.h
 172         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
 173         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
 174         (vld1q_f16_x2, vld1q_f32_x2): New.
 175         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
 176         (vld1q_bf16_x2): New.
 177         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
 178         * config/arm/neon.md (vld1_x2<mode>): New.
 179
 180 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 181
 182         PR tree-optimization/113287
 183         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
 184
 185 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 186
 187         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
 188         * tree-vect-loop.cc (vect_transform_loop): Likewise.
 189
 190 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 191
 192         PR tree-optimization/113178
 193         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
 194         alternate exits.
 195
 196 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 197
 198         PR tree-optimization/113237
 199         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
 200         existing LCSSA variable for exit when all exits are early break.
 201
 202 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 203
 204         PR tree-optimization/113137
 205         PR tree-optimization/113136
 206         PR tree-optimization/113172
 207         PR tree-optimization/113178
 208         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 209         Maintain PHIs on inverted loops.
 210         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
 211         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
 212         latch.
 213         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
 214
 215 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 216
 217         PR tree-optimization/113135
 218         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
 219         dependency analysis.
 220
 221 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
 222
 223         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
 224         diagnostics class member name for abort of error.
 225
 226 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 227
 228         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
 229         format string to %s argument.
 230
 231 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
 232             Jakub Jelinek  <jakub@redhat.com>
 233
 234         PR middle-end/113182
 235         * varasm.cc (process_pending_assemble_externals,
 236         assemble_external_libcall): Use targetm.strip_name_encoding
 237         before calling get_identifier.
 238
 239 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 240
 241         PR target/113196
 242         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
 243         New member variable.
 244         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
 245         Declare.
 246         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
 247         * config/aarch64/aarch64-simd.md
 248         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
 249         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
 250         zip2 for zero-extends to...
 251         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
 252         instruction.  Fix big-endian handling.
 253         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
 254         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
 255         zip1 for zero-extends to...
 256         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
 257         Fix big-endian handling.
 258         (*aarch64_zip1_uxtl): New pattern.
 259         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
 260         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
 261         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
 262         (aarch64_gen_shareable_zero): Use it.
 263         (aarch64_split_simd_shift_p): New function.
 264
 265 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 266
 267         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
 268         (function_beg_insn): New macro.
 269         * function.cc (expand_function_start): Initialize function_beg_insn.
 270
 271 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 272
 273         PR target/112989
 274         * config/aarch64/aarch64-sve-builtins.h
 275         (function_builder::m_overload_names): Replace with...
 276         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
 277         new global.
 278         (add_overloaded_function): Update accordingly, using get_identifier
 279         to get a GGC-friendly record of the name.
 280
 281 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 282
 283         PR target/112989
 284         * config/aarch64/aarch64-sve-builtins.def: Don't include
 285         aarch64-sve-builtins-sme.def.
 286         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
 287         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
 288         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
 289         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
 290         requires AARCH64_FL_SME2.
 291         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
 292         AARCH64_FL_SME adjustment here.
 293         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
 294         include SME intrinsics.
 295         (sme_function_groups): New array.
 296         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
 297         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
 298
 299 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 300
 301         PR target/113281
 302         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
 303         (struct cpu_vector_cost): Add regmove struct.
 304         (get_vector_costs): Export as global.
 305         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
 306         (costs::add_stmt_cost): Ditto.
 307         * config/riscv/riscv.cc (get_common_costs): Export global function.
 308
 309 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 310
 311         PR tree-optimization/113334
 312         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
 313         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
 314         to determine if number should be extended by all ones rather than zero
 315         extended.
 316
 317 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 318
 319         PR tree-optimization/113330
 320         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
 321         too large size.
 322
 323 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 324
 325         PR tree-optimization/113323
 326         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
 327         check for lhs being large/huge _BitInt not in m_names.
 328
 329 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 330
 331         PR tree-optimization/113316
 332         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
 333         uninitialized large/huge _BitInt arguments to calls.
 334
 335 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 336
 337         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
 338         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
 339         CEIL (TYPE_PRECISION (t), limb_prec).
 340         (bitint_large_huge::handle_cast): Likewise.
 341
 342 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
 343
 344         PR sanitizer/113284
 345         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
 346         Use assemble_function_label_final () for Power ELF V1 ABI.
 347         * output.h (assemble_function_label_final): New function.
 348         * varasm.cc (assemble_function_label_raw): Use
 349         assemble_function_label_final ().
 350         (assemble_function_label_final): New function.
 351
 352 2024-01-12  Richard Biener  <rguenther@suse.de>
 353
 354         PR middle-end/113344
 355         * match.pd ((double)float CMP (double)float -> float CMP float):
 356         Perform result type check only for vectors.
 357         * fold-const.cc (fold_binary_loc): Likewise.
 358
 359 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
 360
 361         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
 362         (usdot_prod<mode>): Ditto.
 363         (sdot_prod<mode>): Ditto.
 364         (udot_prod<mode>): Ditto.
 365
 366 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
 367
 368         PR target/113288
 369         * config/i386/i386-c.cc (ix86_target_macros_internal):
 370         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
 371
 372 2024-01-12  Richard Biener  <rguenther@suse.de>
 373
 374         PR target/112280
 375         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
 376         Do not generate code when d.testing_p.
 377
 378 2024-01-12  liuhongt  <hongtao.liu@intel.com>
 379
 380         PR target/113039
 381         * doc/invoke.texi (fcf-protection=): Update documents.
 382
 383 2024-01-12  Pan Li  <pan2.li@intel.com>
 384
 385         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
 386         comments of predicate func riscv_v_ext_mode_p.
 387
 388 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
 389
 390         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
 391                         Modify ABI-name length of vfloat16m8_t
 392
 393 2024-01-12  Li Wei  <liwei@loongson.cn>
 394
 395         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
 396         Adjust.
 397
 398 2024-01-12  Li Wei  <liwei@loongson.cn>
 399
 400         * config/loongarch/loongarch.md (add<mode>3): Removed.
 401         (*addsi3): New.
 402         (addsi3): Ditto.
 403         (adddi3): Ditto.
 404         (*addsi3_extended): Removed.
 405         (addsi3_extended): New.
 406
 407 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
 408
 409         * config/riscv/thead.md: Add limits for splits.
 410
 411 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
 412
 413         PR middle-end/113322
 414         * expr.cc (do_store_flag): Don't try single bit tests with
 415         comparison on vector types.
 416
 417 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
 418
 419         PR tree-optimization/113301
 420         * match.pd (`1/x`): Delay signed case until late.
 421
 422 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
 423
 424         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
 425         and -msp8 to...
 426         (AVR Internal Options): ...this new @subsubsection.
 427
 428 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
 429
 430         PR rtl-optimization/112918
 431         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
 432         (in_class_p): Restrict condition for narrowing class in case of
 433         allow_all_reload_class_changes_p.
 434         (process_alt_operands): Try to match operand without and with
 435         narrowing reg class.  Discourage narrowing the class.  Finish insn
 436         matching only if there is no class narrowing.
 437         (curr_insn_transform): Pass true to in_class_p for reg operand win.
 438
 439 2024-01-11  Richard Biener  <rguenther@suse.de>
 440
 441         PR tree-optimization/112505
 442         * tree-vect-loop.cc (vectorizable_induction): Reject
 443         bit-precision induction.
 444
 445 2024-01-11  Richard Biener  <rguenther@suse.de>
 446
 447         PR tree-optimization/113126
 448         * match.pd ((double)float CMP (double)float -> float CMP float):
 449         Make sure the boolean type is the same.
 450         * fold-const.cc (fold_binary_loc): Likewise.
 451
 452 2024-01-11  Richard Biener  <rguenther@suse.de>
 453
 454         PR tree-optimization/112636
 455         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
 456         estimate_numbers_of_iterations before querying
 457         get_max_loop_iterations_int.
 458         (pass_ch::execute): Initialize SCEV and loops appropriately.
 459
 460 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
 461
 462         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
 463         Reduced Tiny.
 464         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
 465         * doc/extend.texi (AVR Variable Attributes): Improve documentation
 466         of io, io_low and address attributes.
 467         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
 468         * doc/avr-mmcu.texi: Rebuild.
 469
 470 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
 471
 472         PR target/113233
 473         * config/loongarch/genopts/loongarch.opt.in: Mark options with
 474         the "Save" property.
 475         * config/loongarch/loongarch.opt: Same.
 476         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
 477         according to la_target.
 478         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
 479         RESTORE} for the la_target structure; Rename option conditions
 480         to have the same "la_" prefix.
 481         * config/loongarch/loongarch.h: Same.
 482
 483 2024-01-11  Pan Li  <pan2.li@intel.com>
 484
 485         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
 486         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
 487
 488 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
 489
 490         PR target/113077
 491         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
 492         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
 493         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
 494         synthesize these if needed.  Update caller ...
 495         (ldp_bb_info::fuse_pair): ... here.
 496         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
 497         and either insn is frame-related.
 498         (find_trailing_add): Punt on frame-related insns.
 499         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
 500         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
 501
 502 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
 503
 504         * config/mips/mips.cc (mips_start_function_definition):
 505         Add ATTRIBUTE_UNUSED.
 506
 507 2024-01-11  Richard Biener  <rguenther@suse.de>
 508
 509         PR middle-end/112740
 510         * expr.cc (store_constructor): Check the integer vector
 511         mask has a single bit per element before using sign-extension
 512         to expand an uniform vector.
 513
 514 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 515
 516         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
 517         preempt VLS on unknown NITERS loop.
 518
 519 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
 520
 521         * doc/invoke.texi: Add -mevex512.
 522
 523 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
 524
 525         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
 526         (*nor<mode>3): Likewise.
 527         (nor<mode>3): Likewise.
 528         (*negsi2_extended): New template.
 529         (*<optab>si3_internal): Likewise.
 530         (*one_cmplsi2_internal): Likewise.
 531         (*norsi3_internal): Likewise.
 532         (*<optab>nsi_internal): Likewise.
 533         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
 534         modified bit operation to make the optimization work.
 535
 536 2024-01-11  liuhongt  <hongtao.liu@intel.com>
 537
 538         PR target/104401
 539         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
 540
 541 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 542
 543         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
 544         (get_vector_costs): Ditto.
 545         (riscv_builtin_vectorization_cost): Ditto.
 546
 547 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 548
 549         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
 550
 551 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
 552
 553         PR jit/111396
 554         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
 555         ipa_free_size_summary.
 556         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
 557         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
 558         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
 559         * ipa-prop.h (ipa_prop_cc_finalize): New function.
 560         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
 561         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
 562         ipa_sra_cc_finalize): New functions.
 563         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
 564         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
 565         ipa_sra_cc_finalize
 566         Include ipa-utils.h.
 567
 568 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
 569
 570         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
 571         (th_int_get_save_adjustment): Likewise.
 572         (th_int_adjust_cfi_prologue): Likewise.
 573         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
 574         (TH_INT_INTERRUPT): New macro.
 575         (riscv_expand_prologue): Add the processing of XTheadInt.
 576         (riscv_expand_epilogue): Likewise.
 577         * config/riscv/riscv.h (BITSET_P): Moved to here.
 578         * config/riscv/riscv.md: New unspec.
 579         * config/riscv/thead.cc (th_int_get_mask): New function.
 580         (th_int_get_save_adjustment): Likewise.
 581         (th_int_adjust_cfi_prologue): Likewise.
 582         * config/riscv/thead.md (th_int_push): New pattern.
 583         (th_int_pop): new pattern.
 584
 585 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
 586
 587         PR tree-optimization/112468
 588         * doc/sourcebuild.texi: Document ifn_copysign.
 589         * match.pd: Only apply transformation if target supports the IFN.
 590
 591 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
 592
 593         PR tree-optimization/112581
 594         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
 595         mark_ssa_maybe_undefs.
 596         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
 597         variables can not be reassociated.
 598         (init_range_entry): Check for uninitialized variables too.
 599         (init_reassoc): Call mark_ssa_maybe_undefs.
 600
 601 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
 602
 603         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
 604         Also handle sign extension.
 605
 606 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
 607
 608         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
 609         to 0.
 610         (-mlate-ldp-fusion): Likewise.
 611
 612 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
 613
 614         PR tree-optimization/113287
 615         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
 616         instead of using BRANCH_EDGE to determine true edge.
 617
 618 2024-01-10  Richard Biener  <rguenther@suse.de>
 619
 620         PR tree-optimization/113078
 621         * tree-vect-loop.cc (check_reduction_path): Canonicalize
 622         .COND_SUB to .COND_ADD.
 623
 624 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
 625
 626         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
 627         Handle prefix mappings before calling find_opt.
 628         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
 629         "-fno-"-prefixed command-line option.
 630         * opts-common.cc (get_option_prefix_remapping): New.
 631         * opts.h (get_option_prefix_remapping): New decl.
 632
 633 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
 634
 635         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
 636         m_urlifier to pp_output_formatted_text.
 637         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
 638         (obstack_append_string): New overload, taking a length.
 639         (urlify_quoted_string): Pass in an obstack ptr, rather than using
 640         that of the pp's buffer.  Generalize to handle trailing text in
 641         the buffer beyond the run of quoted text.
 642         (class quoting_info): New.
 643         (on_begin_quote): New.
 644         (on_end_quote): New.
 645         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
 646         it to calls to on_begin_quote and on_end_quote.
 647         (struct auto_obstack): New.
 648         (quoting_info::handle_phase_3): New.
 649         (pp_output_formatted_text): Add urlifier param.  Use it if there
 650         is deferred urlification.  Delete m_quotes.
 651         (selftest::pp_printf_with_urlifier): Pass urlifier to
 652         pp_output_formatted_text.
 653         (selftest::test_urlification): Update results for the existing
 654         case of quoted text stradding chunks; add more such test cases.
 655         * pretty-print.h (class quoting_info): New forward decl.
 656         (chunk_info::m_quotes): New field.
 657         (pp_output_formatted_text): Add optional urlifier param.
 658
 659 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
 660
 661         * pretty-print.cc (selftest::test_pp_format): Add selftest
 662         coverage for numbered args.
 663
 664 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
 665
 666         PR tree-optimization/113144
 667         PR tree-optimization/113145
 668         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 669         Update all BB that the original exits dominated.
 670
 671 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
 672
 673         * dwarf2out.cc (modified_type_die): Extend the support of reverse
 674         storage order to enumeration types if -gstrict-dwarf is not passed.
 675         (gen_enumeration_type_die): Add REVERSE parameter and generate the
 676         DIE immediately after the existing one if it is true.
 677         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
 678         call to gen_enumeration_type_die.
 679         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
 680         first recursive call as well as the call to gen_tagged_type_die.
 681         (gen_type_die): Add REVERSE parameter and pass it in the call to
 682         gen_type_die_with_usage.
 683
 684 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
 685
 686         PR tree-optimization/113120
 687         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
 688         with root->size TYPE_PRECISION don't build anything new.
 689         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
 690         rather than build_nonstandard_integer_type.
 691
 692 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
 693
 694         * config/i386/i386.opt: Adjust document.
 695         * doc/invoke.texi: Add description for
 696         -mapx-inline-asm-use-gpr32.
 697
 698 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 699
 700         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
 701         (avg<v_double_trunc>3_floor): New pattern.
 702         (<u>avg<v_double_trunc>3_ceil): Remove.
 703         (avg<v_double_trunc>3_ceil): New pattern.
 704         (uavg<mode>3_floor): Ditto.
 705         (uavg<mode>3_ceil): Ditto.
 706         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
 707         (enum insn_type): Ditto.
 708         * config/riscv/riscv-v.cc: Ditto.
 709         * config/riscv/vector-iterators.md (ashiftrt): Remove.
 710         (ASHIFTRT): Ditto.
 711         * config/riscv/vector.md: Add VLS modes.
 712
 713 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
 714
 715         PR target/111480
 716         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
 717         (vczlsbb_char): New int attribute.
 718         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
 719         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
 720         (*vctzlsbb_zext_<mode>): Rename to ...
 721         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
 722         cover vclzlsbb.
 723
 724 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
 725
 726         PR target/112606
 727         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
 728         of the last argument from altivec_register_operand to any_operand.  If
 729         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
 730         otherwise if it doesn't satisfy altivec_register_operand, force it to
 731         REG using copy_to_mode_reg.
 732
 733 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
 734
 735         PR middle-end/113100
 736         * builtins.cc (expand_builtin_stack_address): Guard stack point
 737         adjustment with SPARC_STACK_BOUNDARY_HACK.
 738
 739 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 740
 741         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
 742         argument string definitions.
 743         * config/loongarch/loongarch-str.h: Same.
 744         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
 745         as aliases to -mexplicit-relocs={always,none}
 746         * config/loongarch/loongarch.opt: Regenerate.
 747         * config/loongarch/loongarch.cc: Same.
 748
 749 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 750
 751         * config/loongarch/loongarch-def.h: Define constants with
 752         enums instead of Macros.
 753
 754 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 755
 756         * config/loongarch/genopts/loongarch-strings: Rename.
 757         * config/loongarch/genopts/loongarch.opt.in: Same.
 758         * config/loongarch/loongarch-cpu.cc: Same.
 759         * config/loongarch/loongarch-def.cc: Same.
 760         * config/loongarch/loongarch-def.h: Same.
 761         * config/loongarch/loongarch-opts.cc: Same.
 762         * config/loongarch/loongarch-opts.h: Same.
 763         * config/loongarch/loongarch-str.h: Same.
 764         * config/loongarch/loongarch.opt: Same.
 765
 766 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
 767
 768         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
 769         variable with the common la_ prefix.
 770         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
 771         flags as saved using TargetVariable.
 772         * config/loongarch/loongarch.opt: Same.
 773         * config/loongarch/loongarch-def.h: Define evolution_set to
 774         mark changes to the -march default.
 775         * config/loongarch/loongarch-driver.cc: Same.
 776         * config/loongarch/loongarch-opts.cc: Same.
 777         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
 778         conditions around the la_target structure.
 779         * config/loongarch/loongarch.cc: Same.
 780         * config/loongarch/loongarch.md: Same.
 781         * config/loongarch/loongarch-builtins.cc: Same.
 782         * config/loongarch/loongarch-c.cc: Same.
 783         * config/loongarch/lasx.md: Same.
 784         * config/loongarch/lsx.md: Same.
 785         * config/loongarch/sync.md: Same.
 786
 787 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
 788
 789         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
 790         no less.
 791
 792 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
 793
 794         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
 795
 796 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
 797
 798         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
 799         restart_loop.
 800         (vectorizable_live_operation): Likewise.
 801
 802 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
 803
 804         PR tree-optimization/113199
 805         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
 806         BIT_FIELD_REF.
 807
 808 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
 809
 810         PR target/113270
 811         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
 812         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
 813         GTY(()) declaration before the definition, drop GTY(()) drom the
 814         definition.
 815
 816 2024-01-09  Richard Biener  <rguenther@suse.de>
 817
 818         PR tree-optimization/113026
 819         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
 820         redundant and wrong niter bound setting.  Move niter
 821         bound adjustment down.
 822
 823 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
 824
 825         PR middle-end/113163
 826         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
 827         Reject non-linear inductions that aren't supported.
 828
 829 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
 830
 831         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
 832         left shift implementation strategies.
 833         (arc_shift_info): Type for each entry of the shift strategy table.
 834         (arc_shift_context_idx): Return a integer value for each code
 835         generation context, used as an index
 836         (arc_ashl_alg): Table indexed by context and shifted bit count.
 837         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
 838         left shift implementation.
 839         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
 840         provide accurate costs, when optimizing for speed or size.
 841
 842 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 843
 844         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
 845
 846 2024-01-09  Julian Brown  <julian@codesourcery.com>
 847
 848         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
 849         processed out before gimplification.
 850         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
 851         * tree.def (OMP_ARRAY_SECTION): New tree code.
 852
 853 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
 854
 855         PR tree-optimization/113210
 856         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
 857         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
 858         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
 859         minus 1.
 860
 861 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
 862
 863         PR rtl-optimization/113140
 864         * reorg.cc (fill_slots_from_thread): If we are to branch after the
 865         last instruction of the function, create an end label.
 866
 867 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
 868             Hongtao Liu  <hongtao.liu@intel.com>
 869
 870         PR target/112992
 871         * config/i386/i386-expand.cc
 872         (ix86_convert_const_wide_int_to_broadcast): Allow call to
 873         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
 874         (ix86_broadcast_from_constant): Revert recent change; Return a
 875         suitable MEMREF independently of mode/target combinations.
 876         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
 877         to decide whether expansion is possible/preferrable.  Only try
 878         forcing DImode constants to memory (and trying again) if calling
 879         ix86_expand_vector_init_duplicate fails with an DImode immediate
 880         constant.
 881         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
 882         V4SImode for suitable immediate constants.
 883         <case E_V4DImode>: Try using V8SImode for suitable constants.
 884         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
 885         <case E_V2HImode>: Likewise.
 886         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
 887         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
 888         <label widen>: Handle CONT_INTs via simplify_binary_operation.
 889         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
 890         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
 891         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
 892         (ix86_expand_vector_init): Move try using a broadcast for all_same
 893         with ix86_expand_vector_init_duplicate before using constant pool.
 894
 895 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
 896
 897         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
 898
 899 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
 900
 901         * config/arm/arm-cpus.in (cortex-m52): New cpu.
 902         * config/arm/arm-tables.opt: Regenerate.
 903         * config/arm/arm-tune.md: Regenerate.
 904
 905 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
 906
 907         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
 908         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
 909         (@vec_concatz<mode>): New insn pattern.
 910         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
 911         Handle VALS containing two vectors.
 912
 913 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 914
 915         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
 916         (vundefined): Ditto.
 917
 918 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
 919
 920         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
 921                                 Add new function_base for crypto vector.
 922         (class bitmanip): Ditto.
 923         (class b_reverse):Ditto.
 924         (class vwsll):   Ditto.
 925         (class clmul):   Ditto.
 926         (class vg_nhab):  Ditto.
 927         (class crypto_vv):Ditto.
 928         (class crypto_vi):Ditto.
 929         (class vaeskf2_vsm3c):Ditto.
 930         (class vsm3me): Ditto.
 931         (BASE): Add BASE declaration for crypto vector.
 932         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
 933         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
 934                                 Add crypto vector intrinsic definition.
 935         (vbrev): Ditto.
 936         (vclz): Ditto.
 937         (vctz): Ditto.
 938         (vwsll): Ditto.
 939         (vandn): Ditto.
 940         (vbrev8): Ditto.
 941         (vrev8): Ditto.
 942         (vrol): Ditto.
 943         (vror): Ditto.
 944         (vclmul): Ditto.
 945         (vclmulh): Ditto.
 946         (vghsh): Ditto.
 947         (vgmul): Ditto.
 948         (vaesef): Ditto.
 949         (vaesem): Ditto.
 950         (vaesdf): Ditto.
 951         (vaesdm): Ditto.
 952         (vaesz): Ditto.
 953         (vaeskf1): Ditto.
 954         (vaeskf2): Ditto.
 955         (vsha2ms): Ditto.
 956         (vsha2ch): Ditto.
 957         (vsha2cl): Ditto.
 958         (vsm4k): Ditto.
 959         (vsm4r): Ditto.
 960         (vsm3me): Ditto.
 961         (vsm3c): Ditto.
 962         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
 963                                 Add new function_shape for crypto vector.
 964         (struct crypto_vi_def): Ditto.
 965         (struct crypto_vv_no_op_type_def): Ditto.
 966         (SHAPE): Add SHAPE declaration of crypto vector.
 967         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
 968         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
 969                                 Add new data type for crypto vector.
 970         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 971         (vuint32mf2_t): Ditto.
 972         (vuint32m1_t): Ditto.
 973         (vuint32m2_t): Ditto.
 974         (vuint32m4_t): Ditto.
 975         (vuint32m8_t): Ditto.
 976         (vuint64m1_t): Ditto.
 977         (vuint64m2_t): Ditto.
 978         (vuint64m4_t): Ditto.
 979         (vuint64m8_t): Ditto.
 980         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
 981                                 Add new data struct for crypto vector.
 982         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 983         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
 984         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
 985
 986 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
 987
 988         PR sanitizer/113251
 989         * varasm.cc (assemble_function_label_raw): Do not call
 990         asan_function_start () without the current function.
 991
 992 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
 993
 994         PR target/113225
 995         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
 996         extern and kernel_helper attributed function decls.
 997
 998 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
 999
1000         * btfout.cc (output_btf_strs): Changed.
1001
1002 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1003
1004         * config/gcn/mkoffload.cc (main): Handle gfx1100
1005         when setting the default XNACK.
1006
1007 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1008
1009         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
1010         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
1011         (ASM_SPEC): Handle gfx1100.
1012         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
1013         (enum gcn_isa): Add ISA_RDNA3.
1014         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
1015         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1016         * config/gcn/gcn.cc (gcn_option_override,
1017         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
1018         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
1019         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1020         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
1021         with gfx1100.
1022         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
1023         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
1024         __gfx1100__.
1025         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1026         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
1027         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
1028         (isa_has_combined_avgprs, main): Handle gfx1100.
1029         * config/gcn/t-omp-device (isa): Add gfx1100.
1030
1031 2024-01-08  Richard Biener  <rguenther@suse.de>
1032
1033         * doc/invoke.texi (-mmovbe): Clarify.
1034
1035 2024-01-08  Richard Biener  <rguenther@suse.de>
1036
1037         PR tree-optimization/113026
1038         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
1039         Avoid an epilog in more cases.
1040         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
1041         epilogues niter upper bounds and estimates.
1042
1043 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1044
1045         PR tree-optimization/113228
1046         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
1047
1048 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1049
1050         PR tree-optimization/113120
1051         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
1052         large _BitInt zero INTEGER_CST PHI argument.
1053
1054 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1055
1056         PR tree-optimization/113119
1057         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
1058         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
1059         is before REALPART_EXPR.
1060
1061 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
1062
1063         PR target/112952
1064         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
1065         range when diagnosing attribute "io" and "io_low" are out of range.
1066         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
1067         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
1068         in contexts other than static storage.
1069         (avr_asm_output_aligned_decl_common): Move output of decls with
1070         attribute "address", "io", and "io_low" to...
1071         (avr_output_addr_attrib): ...this new function.
1072         (avr_asm_asm_output_aligned_bss): Remove output for decls with
1073         attribute "address", "io", and "io_low".
1074         (avr_encode_section_info): Rectify handling of decls with attribute
1075         "address", "io", and "io_low".
1076
1077 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1078
1079         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
1080         (elf_flags): Remove XNACK from the default value.
1081         (main): Set a default XNACK according to the arch.
1082
1083 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1084
1085         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
1086         (process_asm): Don't count avgprs.
1087
1088 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
1089
1090         * config/i386/i386.opt: Add supported sub-features.
1091         * doc/extend.texi: Add description for target attribute.
1092
1093 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
1094
1095         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
1096
1097 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
1098             Uros Bizjak  <ubizjak@gmail.com>
1099
1100         PR target/113231
1101         * config/i386/i386-features.cc (compute_convert_gain): Include
1102         the overhead of explicit load and store (movd) instructions when
1103         converting non-store scalar operations with memory destinations.
1104         Various indentation whitespace fixes.
1105
1106 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
1107
1108         * config/arm/neon.md (cbranch<mode>4): New.
1109
1110 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1111
1112         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
1113
1114 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
1115
1116         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
1117
1118 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1119
1120         PR target/113248
1121         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
1122         Update the MAX_SEW.
1123
1124 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1125
1126         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
1127         (variable_vectorized_p): Teach loop invariant.
1128         (has_unexpected_spills_p): Ditto.
1129
1130 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1131
1132         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
1133         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
1134         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
1135
1136 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
1137
1138         PR target/113104
1139         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
1140         (aarch64-vect-compare-costs): ...this.
1141         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
1142         Replace with...
1143         (-param=aarch64-vect-compare-costs=): ...this new param.
1144         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
1145         Don't disable it when vectorizing for Advanced SIMD only.
1146         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
1147         whenever aarch64_vect_compare_costs is true.
1148
1149 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
1150
1151         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
1152         Modify the method of determining the memory offset of [x]vld/[x]vst.
1153         (lasx_mxst_<lasxfmt_f>): Likewise.
1154         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
1155         (loongarch_address_insns): Likewise.
1156         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
1157         (lsx_st_<lsxfmt_f>): Likewise.
1158         * config/loongarch/predicates.md (aq10b_operand): Likewise.
1159         (aq10h_operand): Likewise.
1160         (aq10w_operand): Likewise.
1161         (aq10d_operand): Likewise.
1162
1163 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
1164
1165         PR target/113217
1166         * config/aarch64/aarch64-ldp-fusion.cc
1167         (ldp_bb_info::try_fuse_pair): If the second access can throw,
1168         narrow the move range to exactly that insn.
1169
1170 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
1171
1172         * asan.cc (asan_function_start): Drop switch_to_section ().
1173         (asan_emit_stack_protection): Set .LASANPC alignment.
1174         * config/i386/i386.cc: Use assemble_function_label_raw ()
1175         instead of ASM_OUTPUT_LABEL ().
1176         * config/s390/s390.cc (s390_asm_output_function_label):
1177         Likewise.
1178         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
1179         * final.cc (final_start_function_1): Drop
1180         asan_function_start ().
1181         * output.h (assemble_function_label_raw): New function.
1182         * varasm.cc (assemble_function_label_raw): Likewise.
1183
1184 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
1185
1186         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
1187         Use ASM_OUTPUT_FUNCTION_LABEL ().
1188         * config/alpha/alpha.cc (alpha_start_function): Likewise.
1189         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1190         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
1191         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1192         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1193         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
1194         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1195         * config/ia64/ia64.cc (ia64_start_function): Likewise.
1196         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
1197         Likewise.
1198         * config/microblaze/microblaze.cc (microblaze_function_prologue):
1199         Likewise.
1200         * config/mips/mips.cc (mips_start_unique_function): Return the
1201         tree.
1202         (mips_start_function_definition): Use
1203         ASM_OUTPUT_FUNCTION_LABEL ().
1204         (mips_finish_stub): Pass the tree to
1205         mips_start_function_definition ().
1206         (mips16_build_function_stub): Likewise.
1207         (mips16_build_call_stub): Likewise.
1208         (mips_output_function_prologue): Likewise.
1209         * config/pa/pa.cc (pa_output_function_label): Use
1210         ASM_OUTPUT_FUNCTION_LABEL ().
1211         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
1212         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1213         Likewise.
1214         (rs6000_xcoff_declare_function_name): Likewise.
1215
1216 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
1217
1218         PR tree-optimization/113201
1219         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
1220         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
1221
1222 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
1223
1224         PR tree-optimization/90693
1225         * tree-ssa-math-opts.cc (match_single_bit_test): If
1226         tree_expr_nonzero_p (arg), remember it in the second argument to
1227         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
1228         arg ^ (arg - 1) > arg - 1.
1229         * internal-fn.cc (expand_POPCOUNT): If second argument to
1230         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
1231         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
1232
1233 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
1234
1235         * config/riscv/riscv-v.cc (expand_load_store):
1236         Remove `value`.
1237         (expand_cond_len_op): Ditto.
1238         (expand_gather_scatter): Ditto.
1239         (expand_lanes_load_store): Ditto.
1240         (expand_fold_extract_last): Ditto.
1241
1242 2024-01-05  Pan Li  <pan2.li@intel.com>
1243
1244         Revert:
1245         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
1246
1247         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1248                                 Add new function_base for crypto vector.
1249         (class bitmanip): Ditto.
1250         (class b_reverse):Ditto.
1251         (class vwsll):   Ditto.
1252         (class clmul):   Ditto.
1253         (class vg_nhab):  Ditto.
1254         (class crypto_vv):Ditto.
1255         (class crypto_vi):Ditto.
1256         (class vaeskf2_vsm3c):Ditto.
1257         (class vsm3me): Ditto.
1258         (BASE): Add BASE declaration for crypto vector.
1259         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1260         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1261                                 Add crypto vector intrinsic definition.
1262         (vbrev): Ditto.
1263         (vclz): Ditto.
1264         (vctz): Ditto.
1265         (vwsll): Ditto.
1266         (vandn): Ditto.
1267         (vbrev8): Ditto.
1268         (vrev8): Ditto.
1269         (vrol): Ditto.
1270         (vror): Ditto.
1271         (vclmul): Ditto.
1272         (vclmulh): Ditto.
1273         (vghsh): Ditto.
1274         (vgmul): Ditto.
1275         (vaesef): Ditto.
1276         (vaesem): Ditto.
1277         (vaesdf): Ditto.
1278         (vaesdm): Ditto.
1279         (vaesz): Ditto.
1280         (vaeskf1): Ditto.
1281         (vaeskf2): Ditto.
1282         (vsha2ms): Ditto.
1283         (vsha2ch): Ditto.
1284         (vsha2cl): Ditto.
1285         (vsm4k): Ditto.
1286         (vsm4r): Ditto.
1287         (vsm3me): Ditto.
1288         (vsm3c): Ditto.
1289         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1290                                 Add new function_shape for crypto vector.
1291         (struct crypto_vi_def): Ditto.
1292         (struct crypto_vv_no_op_type_def): Ditto.
1293         (SHAPE): Add SHAPE declaration of crypto vector.
1294         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1295         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1296                                 Add new data type for crypto vector.
1297         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1298         (vuint32mf2_t): Ditto.
1299         (vuint32m1_t): Ditto.
1300         (vuint32m2_t): Ditto.
1301         (vuint32m4_t): Ditto.
1302         (vuint32m8_t): Ditto.
1303         (vuint64m1_t): Ditto.
1304         (vuint64m2_t): Ditto.
1305         (vuint64m4_t): Ditto.
1306         (vuint64m8_t): Ditto.
1307         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1308                                 Add new data struct for crypto vector.
1309         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1310         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1311         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1312
1313 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
1314
1315         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1316                                 Add new function_base for crypto vector.
1317         (class bitmanip): Ditto.
1318         (class b_reverse):Ditto.
1319         (class vwsll):   Ditto.
1320         (class clmul):   Ditto.
1321         (class vg_nhab):  Ditto.
1322         (class crypto_vv):Ditto.
1323         (class crypto_vi):Ditto.
1324         (class vaeskf2_vsm3c):Ditto.
1325         (class vsm3me): Ditto.
1326         (BASE): Add BASE declaration for crypto vector.
1327         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1328         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1329                                 Add crypto vector intrinsic definition.
1330         (vbrev): Ditto.
1331         (vclz): Ditto.
1332         (vctz): Ditto.
1333         (vwsll): Ditto.
1334         (vandn): Ditto.
1335         (vbrev8): Ditto.
1336         (vrev8): Ditto.
1337         (vrol): Ditto.
1338         (vror): Ditto.
1339         (vclmul): Ditto.
1340         (vclmulh): Ditto.
1341         (vghsh): Ditto.
1342         (vgmul): Ditto.
1343         (vaesef): Ditto.
1344         (vaesem): Ditto.
1345         (vaesdf): Ditto.
1346         (vaesdm): Ditto.
1347         (vaesz): Ditto.
1348         (vaeskf1): Ditto.
1349         (vaeskf2): Ditto.
1350         (vsha2ms): Ditto.
1351         (vsha2ch): Ditto.
1352         (vsha2cl): Ditto.
1353         (vsm4k): Ditto.
1354         (vsm4r): Ditto.
1355         (vsm3me): Ditto.
1356         (vsm3c): Ditto.
1357         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1358                                 Add new function_shape for crypto vector.
1359         (struct crypto_vi_def): Ditto.
1360         (struct crypto_vv_no_op_type_def): Ditto.
1361         (SHAPE): Add SHAPE declaration of crypto vector.
1362         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1363         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1364                                 Add new data type for crypto vector.
1365         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1366         (vuint32mf2_t): Ditto.
1367         (vuint32m1_t): Ditto.
1368         (vuint32m2_t): Ditto.
1369         (vuint32m4_t): Ditto.
1370         (vuint32m8_t): Ditto.
1371         (vuint64m1_t): Ditto.
1372         (vuint64m2_t): Ditto.
1373         (vuint64m4_t): Ditto.
1374         (vuint64m8_t): Ditto.
1375         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1376                                 Add new data struct for crypto vector.
1377         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1378         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1379         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1380
1381 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1382
1383         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
1384
1385 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
1386
1387         PR tree-optimization/113186
1388         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
1389         Match `^` with the `==` for 1bit integral types.
1390         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
1391         integral types.
1392
1393 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1394
1395         * toplev.cc (general_init): Pass lang_mask to urlifier.
1396
1397 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1398
1399         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
1400         param.
1401         (diagnostic_context::make_option_url): Update for lang_mask param.
1402         * gcc-urlifier.cc: Include "opts.h" and "options.h".
1403         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
1404         (gcc_urlifier::m_lang_mask): New field.
1405         (doc_urls): Make static.
1406         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
1407         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
1408         Look for an option by name before trying a binary search in
1409         doc_urls.
1410         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
1411         (gcc_urlifier::get_url_suffix_for_option): New.
1412         (make_gcc_urlifier): Add lang_mask param.
1413         (selftest::gcc_urlifier_cc_tests): Update for above changes.
1414         Verify that a URL is found for "-fpack-struct".
1415         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
1416         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
1417         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
1418         to make_gcc_urlifier.
1419         * opts-diagnostic.h (get_option_url): Add lang_mask param.
1420         * opts.cc (get_option_html_page): Remove special-casing for
1421         analyzer and LTO.
1422         (get_option_url_suffix): New.
1423         (get_option_url): Reimplement.
1424         (selftest::test_get_option_html_page): Rename to...
1425         (selftest::test_get_option_url_suffix): ...this and update for
1426         above changes.
1427         (selftest::opts_cc_tests): Update for renaming.
1428         * opts.h: Include "rich-location.h".
1429         (get_option_url_suffix): New decl.
1430
1431 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1432
1433         * Makefile.in (ALL_OPT_URL_FILES): New.
1434         (GCC_OBJS): Add options-urls.o.
1435         (OBJS): Likewise.
1436         (OBJS-libcommon): Likewise.
1437         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
1438         inputs to opt-gather.awk.
1439         (options-urls.cc): New Makefile target.
1440         * opt-functions.awk (url_suffix): New function.
1441         (lang_url_suffix): New function.
1442         * options-urls-cc-gen.awk: New file.
1443         * opts.h (get_opt_url_suffix): New decl.
1444
1445 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1446
1447         * params.opt.urls: New file, autogenerated by
1448         regenerate-opt-urls.py.
1449
1450 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1451
1452         * common.opt.urls: New file, autogenerated by
1453         regenerate-opt-urls.py.
1454         * config/aarch64/aarch64.opt.urls: Likewise.
1455         * config/alpha/alpha.opt.urls: Likewise.
1456         * config/alpha/elf.opt.urls: Likewise.
1457         * config/arc/arc-tables.opt.urls: Likewise.
1458         * config/arc/arc.opt.urls: Likewise.
1459         * config/arm/arm-tables.opt.urls: Likewise.
1460         * config/arm/arm.opt.urls: Likewise.
1461         * config/arm/vxworks.opt.urls: Likewise.
1462         * config/avr/avr.opt.urls: Likewise.
1463         * config/bpf/bpf.opt.urls: Likewise.
1464         * config/c6x/c6x-tables.opt.urls: Likewise.
1465         * config/c6x/c6x.opt.urls: Likewise.
1466         * config/cris/cris.opt.urls: Likewise.
1467         * config/cris/elf.opt.urls: Likewise.
1468         * config/csky/csky.opt.urls: Likewise.
1469         * config/csky/csky_tables.opt.urls: Likewise.
1470         * config/darwin.opt.urls: Likewise.
1471         * config/dragonfly.opt.urls: Likewise.
1472         * config/epiphany/epiphany.opt.urls: Likewise.
1473         * config/fr30/fr30.opt.urls: Likewise.
1474         * config/freebsd.opt.urls: Likewise.
1475         * config/frv/frv.opt.urls: Likewise.
1476         * config/ft32/ft32.opt.urls: Likewise.
1477         * config/fused-madd.opt.urls: Likewise.
1478         * config/g.opt.urls: Likewise.
1479         * config/gcn/gcn.opt.urls: Likewise.
1480         * config/gnu-user.opt.urls: Likewise.
1481         * config/h8300/h8300.opt.urls: Likewise.
1482         * config/hpux11.opt.urls: Likewise.
1483         * config/i386/cygming.opt.urls: Likewise.
1484         * config/i386/cygwin.opt.urls: Likewise.
1485         * config/i386/djgpp.opt.urls: Likewise.
1486         * config/i386/i386.opt.urls: Likewise.
1487         * config/i386/mingw-w64.opt.urls: Likewise.
1488         * config/i386/mingw.opt.urls: Likewise.
1489         * config/i386/nto.opt.urls: Likewise.
1490         * config/ia64/ia64.opt.urls: Likewise.
1491         * config/ia64/ilp32.opt.urls: Likewise.
1492         * config/ia64/vms.opt.urls: Likewise.
1493         * config/iq2000/iq2000.opt.urls: Likewise.
1494         * config/linux-android.opt.urls: Likewise.
1495         * config/linux.opt.urls: Likewise.
1496         * config/lm32/lm32.opt.urls: Likewise.
1497         * config/loongarch/loongarch.opt.urls: Likewise.
1498         * config/lynx.opt.urls: Likewise.
1499         * config/m32c/m32c.opt.urls: Likewise.
1500         * config/m32r/m32r.opt.urls: Likewise.
1501         * config/m68k/ieee.opt.urls: Likewise.
1502         * config/m68k/m68k-tables.opt.urls: Likewise.
1503         * config/m68k/m68k.opt.urls: Likewise.
1504         * config/m68k/uclinux.opt.urls: Likewise.
1505         * config/mcore/mcore.opt.urls: Likewise.
1506         * config/microblaze/microblaze.opt.urls: Likewise.
1507         * config/mips/mips-tables.opt.urls: Likewise.
1508         * config/mips/mips.opt.urls: Likewise.
1509         * config/mips/sde.opt.urls: Likewise.
1510         * config/mmix/mmix.opt.urls: Likewise.
1511         * config/mn10300/mn10300.opt.urls: Likewise.
1512         * config/moxie/moxie.opt.urls: Likewise.
1513         * config/msp430/msp430.opt.urls: Likewise.
1514         * config/nds32/nds32-elf.opt.urls: Likewise.
1515         * config/nds32/nds32-linux.opt.urls: Likewise.
1516         * config/nds32/nds32.opt.urls: Likewise.
1517         * config/netbsd-elf.opt.urls: Likewise.
1518         * config/netbsd.opt.urls: Likewise.
1519         * config/nios2/elf.opt.urls: Likewise.
1520         * config/nios2/nios2.opt.urls: Likewise.
1521         * config/nvptx/nvptx-gen.opt.urls: Likewise.
1522         * config/nvptx/nvptx.opt.urls: Likewise.
1523         * config/openbsd.opt.urls: Likewise.
1524         * config/or1k/elf.opt.urls: Likewise.
1525         * config/or1k/or1k.opt.urls: Likewise.
1526         * config/pa/pa-hpux.opt.urls: Likewise.
1527         * config/pa/pa-hpux1010.opt.urls: Likewise.
1528         * config/pa/pa-hpux1111.opt.urls: Likewise.
1529         * config/pa/pa-hpux1131.opt.urls: Likewise.
1530         * config/pa/pa.opt.urls: Likewise.
1531         * config/pa/pa64-hpux.opt.urls: Likewise.
1532         * config/pdp11/pdp11.opt.urls: Likewise.
1533         * config/pru/pru.opt.urls: Likewise.
1534         * config/riscv/riscv.opt.urls: Likewise.
1535         * config/rl78/rl78.opt.urls: Likewise.
1536         * config/rpath.opt.urls: Likewise.
1537         * config/rs6000/476.opt.urls: Likewise.
1538         * config/rs6000/aix64.opt.urls: Likewise.
1539         * config/rs6000/darwin.opt.urls: Likewise.
1540         * config/rs6000/linux64.opt.urls: Likewise.
1541         * config/rs6000/rs6000-tables.opt.urls: Likewise.
1542         * config/rs6000/rs6000.opt.urls: Likewise.
1543         * config/rs6000/sysv4.opt.urls: Likewise.
1544         * config/rtems.opt.urls: Likewise.
1545         * config/rx/elf.opt.urls: Likewise.
1546         * config/rx/rx.opt.urls: Likewise.
1547         * config/s390/s390.opt.urls: Likewise.
1548         * config/s390/tpf.opt.urls: Likewise.
1549         * config/sh/sh.opt.urls: Likewise.
1550         * config/sh/superh.opt.urls: Likewise.
1551         * config/sol2.opt.urls: Likewise.
1552         * config/sparc/long-double-switch.opt.urls: Likewise.
1553         * config/sparc/sparc.opt.urls: Likewise.
1554         * config/stormy16/stormy16.opt.urls: Likewise.
1555         * config/v850/v850.opt.urls: Likewise.
1556         * config/vax/elf.opt.urls: Likewise.
1557         * config/vax/vax.opt.urls: Likewise.
1558         * config/visium/visium.opt.urls: Likewise.
1559         * config/vms/vms.opt.urls: Likewise.
1560         * config/vxworks-smp.opt.urls: Likewise.
1561         * config/vxworks.opt.urls: Likewise.
1562         * config/xtensa/elf.opt.urls: Likewise.
1563         * config/xtensa/uclinux.opt.urls: Likewise.
1564         * config/xtensa/xtensa.opt.urls: Likewise.
1565         * config/bfin/bfin.opt.urls: New file.
1566
1567 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1568
1569         * Makefile.in (OPT_URLS_HTML_DEPS): New.
1570         (regenerate-opt-urls): New target.
1571         (regenerate-opt-urls-unit-test): New target.
1572         * doc/options.texi (Option properties): Add UrlSuffix and
1573         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
1574         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
1575         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
1576         and Makefile.in's OPT_URLS_HTML_DEPS.
1577         (Anatomy of a Target Back End): Add
1578         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
1579         * regenerate-opt-urls.py: New file.
1580
1581 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
1582
1583         * diagnostic-format-sarif.cc
1584         (sarif_builder::make_logical_location_object): Convert to...
1585         (make_sarif_logical_location_object): ...this.
1586         (sarif_builder::set_any_logical_locs_arr): Update for above
1587         change.
1588         (sarif_builder::make_thread_flow_location_object): Call
1589         maybe_add_sarif_properties on each diagnostic_event.
1590         * diagnostic-format-sarif.h (class logical_location): New forward
1591         decl.
1592         (make_sarif_logical_location_object): New decl.
1593         * diagnostic-path.h (class sarif_object): New forward decl.
1594         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
1595
1596 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
1597             Patrick Lin  <patrick@andestech.com>
1598             Rufus Chen  <rufus@andestech.com>
1599             Monk Chiang  <monk.chiang@sifive.com>
1600
1601         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
1602         with Nan-boxing value.
1603         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
1604
1605 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
1606             Jeff Law  <jlaw@ventanamicro.com>
1607
1608         PR rtl-optimization/104914
1609         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
1610         a sign or zero extension is only required if the modified field
1611         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
1612         targets, don't refer to the temporarily incorrectly extended value
1613         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
1614
1615 2024-01-04  Pan Li  <pan2.li@intel.com>
1616
1617         Revert:
1618         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1619
1620         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
1621
1622 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1623
1624         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
1625
1626 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
1627
1628         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
1629         offset of fcsr.
1630
1631 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1632
1633         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
1634         (compute_nregs_for_mode): Refine LMUL.
1635         (max_number_of_live_regs): Ditto.
1636         (compute_estimated_lmul): Ditto.
1637         (has_unexpected_spills_p): Ditto.
1638
1639 2024-01-04  Li Wei  <liwei@loongson.cn>
1640
1641         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
1642         Remove useless forward declaration.
1643         (loongarch_is_even_extraction): Remove useless forward declaration.
1644         (loongarch_try_expand_lsx_vshuf_const): Removed.
1645         (loongarch_expand_vec_perm_const_1): Merged.
1646         (loongarch_is_double_duplicate): Removed.
1647         (loongarch_is_center_extraction): Ditto.
1648         (loongarch_is_reversing_permutation): Ditto.
1649         (loongarch_is_di_misalign_extract): Ditto.
1650         (loongarch_is_si_misalign_extract): Ditto.
1651         (loongarch_is_lasx_lowpart_extract): Ditto.
1652         (loongarch_is_op_reverse_perm): Ditto.
1653         (loongarch_is_single_op_perm): Ditto.
1654         (loongarch_is_divisible_perm): Ditto.
1655         (loongarch_is_triple_stride_extract): Ditto.
1656         (loongarch_expand_vec_perm_const_2): Merged.
1657         (loongarch_expand_vec_perm_const): New.
1658         (loongarch_vectorize_vec_perm_const): Adjust.
1659
1660 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
1661
1662         * omp-general.cc: Fix comment typos and misplaced/confusing
1663         comments.  Delete redundant include of omp-general.h.
1664
1665 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
1666
1667         PR rtl-optimization/104914
1668         * config/mips/mips.md (insqisi_extended): New patterns.
1669         (inshisi_extended): Ditto.
1670
1671 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
1672
1673         * config/mips/mips.cc (mips_insn_cost): New function.
1674
1675 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
1676
1677         * config/mips/mips.md (perf_ratio): New attribute.
1678
1679 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1680
1681         PR target/113206
1682         PR target/113209
1683         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
1684         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
1685         blocks belong to infinite loop.
1686         (pre_vsetvl::emit_vsetvl): Remove fake edges.
1687         * config/riscv/t-riscv: Add a new include file.
1688
1689 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1690
1691         * config/riscv/vector.md: Fix indent.
1692
1693 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
1694
1695         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
1696         OMP_CLAUSE__SIMDUID_.
1697         * tree.cc (omp_clause_num_ops): Update position of entry for
1698         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
1699         (omp_clause_code_name): Likewise.
1700
1701 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
1702
1703         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
1704         printing of FUNC_MAP/IND_FUNC_MAP labels.
1705
1706 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
1707
1708         * gcc.cc (process_command): Update copyright notice dates.
1709         * gcov-dump.cc (print_version): Ditto.
1710         * gcov.cc (print_version): Ditto.
1711         * gcov-tool.cc (print_version): Ditto.
1712         * gengtype.cc (create_file): Ditto.
1713         * doc/cpp.texi: Bump @copying's copyright year.
1714         * doc/cppinternals.texi: Ditto.
1715         * doc/gcc.texi: Ditto.
1716         * doc/gccint.texi: Ditto.
1717         * doc/gcov.texi: Ditto.
1718         * doc/install.texi: Ditto.
1719         * doc/invoke.texi: Ditto.
1720
1721 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
1722
1723         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
1724         (fmin<mode>3): Likewise.
1725         (reduc_fmax_scal_<mode>3): New define_expand.
1726         (reduc_fmin_scal_<mode>3): Likewise.
1727
1728 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1729
1730         PR target/113112
1731         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
1732         (max_number_of_live_regs): Ditto.
1733         (has_unexpected_spills_p): Ditto.
1734
1735 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
1736             Jin Ma  <jinma@linux.alibaba.com>
1737             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
1738             Christoph Müllner  <christoph.muellner@vrull.eu>
1739
1740         * config/riscv/vector.md:
1741         Use vector_length_operand for vsetvl patterns.
1742
1743 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1744
1745         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
1746         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
1747
1748 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
1749
1750         * config/aarch64/aarch64-tuning-flags.def
1751         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
1752         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
1753         * config/aarch64/aarch64.cc
1754         (aarch64_override_options_internal): Set
1755         param_fully_pipelined_fma according to tuning option.
1756         * config/aarch64/tuning_models/ampere1.h: Add
1757         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
1758         * config/aarch64/tuning_models/ampere1a.h: Likewise.
1759         * config/aarch64/tuning_models/ampere1b.h: Likewise.
1760
1761 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
1762
1763         * config/riscv/vector-crypto.md: Modify copyright year.
1764
1765 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1766
1767         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
1768
1769 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
1770
1771         * config.in: Regenerate.
1772         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
1773         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
1774         Added TLS Le Relax support.
1775         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
1776         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
1777         * configure: Regenerate.
1778         * configure.ac: Check if binutils supports TLS le relax.
1779
1780 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
1781
1782         * config/riscv/iterators.md: Add rotate insn name.
1783         * config/riscv/riscv.md: Add new insns name for crypto vector.
1784         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
1785         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
1786         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
1787
1788 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1789
1790         PR target/113112
1791         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
1792         pointer type liveness count.
1793 \f
1794 Copyright (C) 2024 Free Software Foundation, Inc.
1795
1796 Copying and distribution of this file, with or without modification,
1797 are permitted in any medium without royalty provided the copyright
1798 notice and this notice are preserved.