1 ;; e500 SPE description
2 ;; Copyright (C) 2002-2014 Free Software Foundation, Inc.
3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
34 (E500_CR_IOR_COMPARE 1018)
37 ;; Modes using a 64-bit register.
38 (define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
40 ;; Likewise, but allow TFmode (two registers) as well.
41 (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
44 (define_mode_iterator DITI [DI TI])
46 (define_insn "*negsf2_gpr"
47 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
48 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
49 "TARGET_HARD_FLOAT && !TARGET_FPRS"
51 [(set_attr "type" "fpsimple")])
53 (define_insn "*abssf2_gpr"
54 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
55 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
56 "TARGET_HARD_FLOAT && !TARGET_FPRS"
58 [(set_attr "type" "fpsimple")])
60 (define_insn "*nabssf2_gpr"
61 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
62 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
63 "TARGET_HARD_FLOAT && !TARGET_FPRS"
65 [(set_attr "type" "fpsimple")])
67 (define_insn "*addsf3_gpr"
68 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
69 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
70 (match_operand:SF 2 "gpc_reg_operand" "r")))]
71 "TARGET_HARD_FLOAT && !TARGET_FPRS"
73 [(set_attr "type" "fp")])
75 (define_insn "*subsf3_gpr"
76 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
77 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
78 (match_operand:SF 2 "gpc_reg_operand" "r")))]
79 "TARGET_HARD_FLOAT && !TARGET_FPRS"
81 [(set_attr "type" "fp")])
83 (define_insn "*mulsf3_gpr"
84 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
85 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
86 (match_operand:SF 2 "gpc_reg_operand" "r")))]
87 "TARGET_HARD_FLOAT && !TARGET_FPRS"
89 [(set_attr "type" "fp")])
91 (define_insn "*divsf3_gpr"
92 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
93 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
94 (match_operand:SF 2 "gpc_reg_operand" "r")))]
95 "TARGET_HARD_FLOAT && !TARGET_FPRS"
97 [(set_attr "type" "vecfdiv")])
99 ;; Floating point conversion instructions.
101 (define_insn "spe_fixuns_truncdfsi2"
102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
103 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
104 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
106 [(set_attr "type" "fp")])
108 (define_insn "spe_extendsfdf2"
109 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
110 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
111 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
113 [(set_attr "type" "fp")])
115 (define_insn "spe_fixuns_truncsfsi2"
116 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
117 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
118 "TARGET_HARD_FLOAT && !TARGET_FPRS"
120 [(set_attr "type" "fp")])
122 (define_insn "spe_fix_truncsfsi2"
123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
124 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
125 "TARGET_HARD_FLOAT && !TARGET_FPRS"
127 [(set_attr "type" "fp")])
129 (define_insn "spe_fix_truncdfsi2"
130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
131 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
132 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
134 [(set_attr "type" "fp")])
136 (define_insn "spe_floatunssisf2"
137 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
138 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
139 "TARGET_HARD_FLOAT && !TARGET_FPRS"
141 [(set_attr "type" "fp")])
143 (define_insn "spe_floatunssidf2"
144 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
145 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
146 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
148 [(set_attr "type" "fp")])
150 (define_insn "spe_floatsisf2"
151 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
152 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
153 "TARGET_HARD_FLOAT && !TARGET_FPRS"
155 [(set_attr "type" "fp")])
157 (define_insn "spe_floatsidf2"
158 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
159 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
160 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
162 [(set_attr "type" "fp")])
164 ;; SPE SIMD instructions
166 (define_insn "absv2si2"
167 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
168 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
171 [(set_attr "type" "vecsimple")
172 (set_attr "length" "4")])
174 (define_insn "spe_evandc"
175 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
176 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
177 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
180 [(set_attr "type" "vecsimple")
181 (set_attr "length" "4")])
183 (define_insn "andv2si3"
184 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
185 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
186 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
189 [(set_attr "type" "vecsimple")
190 (set_attr "length" "4")])
192 ;; Vector compare instructions
194 (define_insn "spe_evcmpeq"
195 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
196 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
197 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
200 [(set_attr "type" "veccmp")
201 (set_attr "length" "4")])
203 (define_insn "spe_evcmpgts"
204 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
205 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
206 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
209 [(set_attr "type" "veccmp")
210 (set_attr "length" "4")])
212 (define_insn "spe_evcmpgtu"
213 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
214 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
215 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
218 [(set_attr "type" "veccmp")
219 (set_attr "length" "4")])
221 (define_insn "spe_evcmplts"
222 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
223 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
224 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
227 [(set_attr "type" "veccmp")
228 (set_attr "length" "4")])
230 (define_insn "spe_evcmpltu"
231 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
232 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
233 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
236 [(set_attr "type" "veccmp")
237 (set_attr "length" "4")])
239 ;; Floating point vector compare instructions
241 (define_insn "spe_evfscmpeq"
242 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
243 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
244 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
245 (clobber (reg:SI SPEFSCR_REGNO))]
248 [(set_attr "type" "veccmp")
249 (set_attr "length" "4")])
251 (define_insn "spe_evfscmpgt"
252 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
253 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
254 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
255 (clobber (reg:SI SPEFSCR_REGNO))]
258 [(set_attr "type" "veccmp")
259 (set_attr "length" "4")])
261 (define_insn "spe_evfscmplt"
262 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
263 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
264 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
265 (clobber (reg:SI SPEFSCR_REGNO))]
268 [(set_attr "type" "veccmp")
269 (set_attr "length" "4")])
271 (define_insn "spe_evfststeq"
272 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
273 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
274 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
277 [(set_attr "type" "veccmp")
278 (set_attr "length" "4")])
280 (define_insn "spe_evfststgt"
281 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
282 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
283 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
286 [(set_attr "type" "veccmp")
287 (set_attr "length" "4")])
289 (define_insn "spe_evfststlt"
290 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
291 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
292 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
295 [(set_attr "type" "veccmp")
296 (set_attr "length" "4")])
298 ;; End of vector compare instructions
300 (define_insn "spe_evcntlsw"
301 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
302 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
305 [(set_attr "type" "vecsimple")
306 (set_attr "length" "4")])
308 (define_insn "spe_evcntlzw"
309 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
310 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
313 [(set_attr "type" "vecsimple")
314 (set_attr "length" "4")])
316 (define_insn "spe_eveqv"
317 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
318 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
319 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
322 [(set_attr "type" "vecsimple")
323 (set_attr "length" "4")])
325 (define_insn "spe_evextsb"
326 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
327 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
330 [(set_attr "type" "vecsimple")
331 (set_attr "length" "4")])
333 (define_insn "spe_evextsh"
334 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
335 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
338 [(set_attr "type" "vecsimple")
339 (set_attr "length" "4")])
341 (define_insn "spe_evlhhesplat"
342 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
343 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
344 (match_operand:QI 2 "immediate_operand" "i"))))
345 (unspec [(const_int 0)] 509)]
346 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
347 "evlhhesplat %0,%2*2(%1)"
348 [(set_attr "type" "vecload")
349 (set_attr "length" "4")])
351 (define_insn "spe_evlhhesplatx"
352 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
353 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
354 (match_operand:SI 2 "gpc_reg_operand" "r"))))
355 (unspec [(const_int 0)] 510)]
357 "evlhhesplatx %0,%1,%2"
358 [(set_attr "type" "vecload")
359 (set_attr "length" "4")])
361 (define_insn "spe_evlhhossplat"
362 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
363 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
364 (match_operand:QI 2 "immediate_operand" "i"))))
365 (unspec [(const_int 0)] 511)]
366 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
367 "evlhhossplat %0,%2*2(%1)"
368 [(set_attr "type" "vecload")
369 (set_attr "length" "4")])
371 (define_insn "spe_evlhhossplatx"
372 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
373 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
374 (match_operand:SI 2 "gpc_reg_operand" "r"))))
375 (unspec [(const_int 0)] 512)]
377 "evlhhossplatx %0,%1,%2"
378 [(set_attr "type" "vecload")
379 (set_attr "length" "4")])
381 (define_insn "spe_evlhhousplat"
382 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
383 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
384 (match_operand:QI 2 "immediate_operand" "i"))))
385 (unspec [(const_int 0)] 513)]
386 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
387 "evlhhousplat %0,%2*2(%1)"
388 [(set_attr "type" "vecload")
389 (set_attr "length" "4")])
391 (define_insn "spe_evlhhousplatx"
392 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
393 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
394 (match_operand:SI 2 "gpc_reg_operand" "r"))))
395 (unspec [(const_int 0)] 514)]
397 "evlhhousplatx %0,%1,%2"
398 [(set_attr "type" "vecload")
399 (set_attr "length" "4")])
401 (define_insn "spe_evlwhsplat"
402 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
403 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
404 (match_operand:QI 2 "immediate_operand" "i"))))
405 (unspec [(const_int 0)] 515)]
406 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
407 "evlwhsplat %0,%2*4(%1)"
408 [(set_attr "type" "vecload")
409 (set_attr "length" "4")])
411 (define_insn "spe_evlwhsplatx"
412 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
413 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
414 (match_operand:SI 2 "gpc_reg_operand" "r"))))
415 (unspec [(const_int 0)] 516)]
417 "evlwhsplatx %0,%1,%2"
418 [(set_attr "type" "vecload")
419 (set_attr "length" "4")])
421 (define_insn "spe_evlwwsplat"
422 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
423 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
424 (match_operand:QI 2 "immediate_operand" "i"))))
425 (unspec [(const_int 0)] 517)]
426 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
427 "evlwwsplat %0,%2*4(%1)"
428 [(set_attr "type" "vecload")
429 (set_attr "length" "4")])
431 (define_insn "spe_evlwwsplatx"
432 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
433 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
434 (match_operand:SI 2 "gpc_reg_operand" "r"))))
435 (unspec [(const_int 0)] 518)]
437 "evlwwsplatx %0,%1,%2"
438 [(set_attr "type" "vecload")
439 (set_attr "length" "4")])
441 (define_insn "spe_evmergehi"
442 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
445 (match_operand:V2SI 1 "gpc_reg_operand" "r")
446 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
447 (parallel [(const_int 0) (const_int 2)])))]
450 [(set_attr "type" "vecsimple")
451 (set_attr "length" "4")])
453 (define_insn "spe_evmergehilo"
454 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
457 (match_operand:V2SI 1 "gpc_reg_operand" "r")
458 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
459 (parallel [(const_int 0) (const_int 3)])))]
461 "evmergehilo %0,%1,%2"
462 [(set_attr "type" "vecsimple")
463 (set_attr "length" "4")])
465 (define_insn "spe_evmergelo"
466 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
469 (match_operand:V2SI 1 "gpc_reg_operand" "r")
470 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
471 (parallel [(const_int 1) (const_int 3)])))]
474 [(set_attr "type" "vecsimple")
475 (set_attr "length" "4")])
477 (define_insn "spe_evmergelohi"
478 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
481 (match_operand:V2SI 1 "gpc_reg_operand" "r")
482 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
483 (parallel [(const_int 1) (const_int 2)])))]
485 "evmergelohi %0,%1,%2"
486 [(set_attr "type" "vecsimple")
487 (set_attr "length" "4")])
489 (define_expand "vec_perm_constv2si"
490 [(match_operand:V2SI 0 "gpc_reg_operand" "")
491 (match_operand:V2SI 1 "gpc_reg_operand" "")
492 (match_operand:V2SI 2 "gpc_reg_operand" "")
493 (match_operand:V2SI 3 "" "")]
496 if (rs6000_expand_vec_perm_const (operands))
502 (define_insn "spe_evnand"
503 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
504 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
505 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
508 [(set_attr "type" "vecsimple")
509 (set_attr "length" "4")])
511 (define_insn "negv2si2"
512 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
513 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
516 [(set_attr "type" "vecsimple")
517 (set_attr "length" "4")])
519 (define_insn "spe_evnor"
520 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
521 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
522 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
525 [(set_attr "type" "vecsimple")
526 (set_attr "length" "4")])
528 (define_insn "spe_evorc"
529 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
530 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
531 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
534 [(set_attr "type" "vecsimple")
535 (set_attr "length" "4")])
537 (define_insn "spe_evor"
538 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
539 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
540 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
543 [(set_attr "type" "vecsimple")
544 (set_attr "length" "4")])
546 (define_insn "spe_evrlwi"
547 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
548 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
549 (match_operand:QI 2 "immediate_operand" "i")] 519))]
552 [(set_attr "type" "vecsimple")
553 (set_attr "length" "4")])
555 (define_insn "spe_evrlw"
556 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
557 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
558 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
561 [(set_attr "type" "veccomplex")
562 (set_attr "length" "4")])
564 (define_insn "spe_evrndw"
565 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
566 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
569 [(set_attr "type" "vecsimple")
570 (set_attr "length" "4")])
572 (define_insn "spe_evsel"
573 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
574 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
575 (match_operand:V2SI 2 "gpc_reg_operand" "r")
576 (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
579 [(set_attr "type" "veccmp")
580 (set_attr "length" "4")])
582 (define_insn "spe_evsel_fs"
583 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
584 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
585 (match_operand:V2SF 2 "gpc_reg_operand" "r")
586 (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
589 [(set_attr "type" "veccmp")
590 (set_attr "length" "4")])
592 (define_insn "spe_evslwi"
593 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
594 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
595 (match_operand:QI 2 "immediate_operand" "i")]
599 [(set_attr "type" "vecsimple")
600 (set_attr "length" "4")])
602 (define_insn "spe_evslw"
603 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
604 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
605 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
608 [(set_attr "type" "vecsimple")
609 (set_attr "length" "4")])
611 (define_insn "spe_evsrwis"
612 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
613 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
614 (match_operand:QI 2 "immediate_operand" "i")]
618 [(set_attr "type" "vecsimple")
619 (set_attr "length" "4")])
621 (define_insn "spe_evsrwiu"
622 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
623 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
624 (match_operand:QI 2 "immediate_operand" "i")]
628 [(set_attr "type" "vecsimple")
629 (set_attr "length" "4")])
631 (define_insn "spe_evsrws"
632 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
633 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
634 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
637 [(set_attr "type" "vecsimple")
638 (set_attr "length" "4")])
640 (define_insn "spe_evsrwu"
641 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
642 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
643 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
646 [(set_attr "type" "vecsimple")
647 (set_attr "length" "4")])
651 (define_insn "xorv2si3"
652 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
653 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
654 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
657 [(set_attr "type" "vecsimple")
658 (set_attr "length" "4")])
660 (define_insn "xorv4hi3"
661 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
662 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
663 (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
666 [(set_attr "type" "vecsimple")
667 (set_attr "length" "4")])
669 (define_insn "xorv1di3"
670 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
671 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
672 (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
675 [(set_attr "type" "vecsimple")
676 (set_attr "length" "4")])
678 ;; end of vector xors
680 (define_insn "spe_evfsabs"
681 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
682 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
685 [(set_attr "type" "vecsimple")
686 (set_attr "length" "4")])
688 (define_insn "spe_evfsadd"
689 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
690 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
691 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
692 (clobber (reg:SI SPEFSCR_REGNO))]
695 [(set_attr "type" "vecfloat")
696 (set_attr "length" "4")])
698 (define_insn "spe_evfscfsf"
699 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
700 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
703 [(set_attr "type" "vecfloat")
704 (set_attr "length" "4")])
706 (define_insn "spe_evfscfsi"
707 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
708 (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
711 [(set_attr "type" "vecfloat")
712 (set_attr "length" "4")])
714 (define_insn "spe_evfscfuf"
715 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
716 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
719 [(set_attr "type" "vecfloat")
720 (set_attr "length" "4")])
722 (define_insn "spe_evfscfui"
723 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
724 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
727 [(set_attr "type" "vecfloat")
728 (set_attr "length" "4")])
730 (define_insn "spe_evfsctsf"
731 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
732 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
735 [(set_attr "type" "vecfloat")
736 (set_attr "length" "4")])
738 (define_insn "spe_evfsctsi"
739 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
740 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
743 [(set_attr "type" "vecfloat")
744 (set_attr "length" "4")])
746 (define_insn "spe_evfsctsiz"
747 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
748 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
751 [(set_attr "type" "vecfloat")
752 (set_attr "length" "4")])
754 (define_insn "spe_evfsctuf"
755 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
756 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
759 [(set_attr "type" "vecfloat")
760 (set_attr "length" "4")])
762 (define_insn "spe_evfsctui"
763 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
764 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
767 [(set_attr "type" "vecfloat")
768 (set_attr "length" "4")])
770 (define_insn "spe_evfsctuiz"
771 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
772 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
775 [(set_attr "type" "vecfloat")
776 (set_attr "length" "4")])
778 (define_insn "spe_evfsdiv"
779 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
780 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
781 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
782 (clobber (reg:SI SPEFSCR_REGNO))]
785 [(set_attr "type" "vecfdiv")
786 (set_attr "length" "4")])
788 (define_insn "spe_evfsmul"
789 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
790 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
791 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
792 (clobber (reg:SI SPEFSCR_REGNO))]
795 [(set_attr "type" "vecfloat")
796 (set_attr "length" "4")])
798 (define_insn "spe_evfsnabs"
799 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
800 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
803 [(set_attr "type" "vecsimple")
804 (set_attr "length" "4")])
806 (define_insn "spe_evfsneg"
807 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
808 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
811 [(set_attr "type" "vecsimple")
812 (set_attr "length" "4")])
814 (define_insn "spe_evfssub"
815 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
816 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
817 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
818 (clobber (reg:SI SPEFSCR_REGNO))]
821 [(set_attr "type" "vecfloat")
822 (set_attr "length" "4")])
824 ;; SPE SIMD load instructions.
826 ;; Only the hardware engineer who designed the SPE understands the
827 ;; plethora of load and store instructions ;-). We have no way of
828 ;; differentiating between them with RTL so use an unspec of const_int 0
829 ;; to avoid identical RTL.
831 (define_insn "spe_evldd"
832 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
833 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
834 (match_operand:QI 2 "immediate_operand" "i"))))
835 (unspec [(const_int 0)] 544)]
836 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
838 [(set_attr "type" "vecload")
839 (set_attr "length" "4")])
841 (define_insn "spe_evlddx"
842 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
843 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
844 (match_operand:SI 2 "gpc_reg_operand" "r"))))
845 (unspec [(const_int 0)] 545)]
848 [(set_attr "type" "vecload")
849 (set_attr "length" "4")])
851 (define_insn "spe_evldh"
852 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
853 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
854 (match_operand:QI 2 "immediate_operand" "i"))))
855 (unspec [(const_int 0)] 546)]
856 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
858 [(set_attr "type" "vecload")
859 (set_attr "length" "4")])
861 (define_insn "spe_evldhx"
862 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
863 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
864 (match_operand:SI 2 "gpc_reg_operand" "r"))))
865 (unspec [(const_int 0)] 547)]
868 [(set_attr "type" "vecload")
869 (set_attr "length" "4")])
871 (define_insn "spe_evldw"
872 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
873 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
874 (match_operand:QI 2 "immediate_operand" "i"))))
875 (unspec [(const_int 0)] 548)]
876 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
878 [(set_attr "type" "vecload")
879 (set_attr "length" "4")])
881 (define_insn "spe_evldwx"
882 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
883 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
884 (match_operand:SI 2 "gpc_reg_operand" "r"))))
885 (unspec [(const_int 0)] 549)]
888 [(set_attr "type" "vecload")
889 (set_attr "length" "4")])
891 (define_insn "spe_evlwhe"
892 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
893 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
894 (match_operand:QI 2 "immediate_operand" "i"))))
895 (unspec [(const_int 0)] 550)]
896 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
898 [(set_attr "type" "vecload")
899 (set_attr "length" "4")])
901 (define_insn "spe_evlwhex"
902 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
903 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
904 (match_operand:SI 2 "gpc_reg_operand" "r"))))
905 (unspec [(const_int 0)] 551)]
908 [(set_attr "type" "vecload")
909 (set_attr "length" "4")])
911 (define_insn "spe_evlwhos"
912 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
913 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
914 (match_operand:QI 2 "immediate_operand" "i"))))
915 (unspec [(const_int 0)] 552)]
916 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
917 "evlwhos %0,%2*4(%1)"
918 [(set_attr "type" "vecload")
919 (set_attr "length" "4")])
921 (define_insn "spe_evlwhosx"
922 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
923 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
924 (match_operand:SI 2 "gpc_reg_operand" "r"))))
925 (unspec [(const_int 0)] 553)]
928 [(set_attr "type" "vecload")
929 (set_attr "length" "4")])
931 (define_insn "spe_evlwhou"
932 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
933 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
934 (match_operand:QI 2 "immediate_operand" "i"))))
935 (unspec [(const_int 0)] 554)]
936 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
937 "evlwhou %0,%2*4(%1)"
938 [(set_attr "type" "vecload")
939 (set_attr "length" "4")])
941 (define_insn "spe_evlwhoux"
942 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
943 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
944 (match_operand:SI 2 "gpc_reg_operand" "r"))))
945 (unspec [(const_int 0)] 555)]
948 [(set_attr "type" "vecload")
949 (set_attr "length" "4")])
951 (define_insn "spe_brinc"
952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
953 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
954 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
957 [(set_attr "type" "brinc")
958 (set_attr "length" "4")])
960 (define_insn "spe_evmhegsmfaa"
961 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
962 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
963 (match_operand:V2SI 2 "gpc_reg_operand" "r")
964 (reg:V2SI SPE_ACC_REGNO)] 557))
965 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
967 "evmhegsmfaa %0,%1,%2"
968 [(set_attr "type" "veccomplex")
969 (set_attr "length" "4")])
971 (define_insn "spe_evmhegsmfan"
972 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
973 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
974 (match_operand:V2SI 2 "gpc_reg_operand" "r")
975 (reg:V2SI SPE_ACC_REGNO)] 558))
976 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
978 "evmhegsmfan %0,%1,%2"
979 [(set_attr "type" "veccomplex")
980 (set_attr "length" "4")])
982 (define_insn "spe_evmhegsmiaa"
983 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
984 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
985 (match_operand:V2SI 2 "gpc_reg_operand" "r")
986 (reg:V2SI SPE_ACC_REGNO)] 559))
987 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
989 "evmhegsmiaa %0,%1,%2"
990 [(set_attr "type" "veccomplex")
991 (set_attr "length" "4")])
993 (define_insn "spe_evmhegsmian"
994 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
995 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
996 (match_operand:V2SI 2 "gpc_reg_operand" "r")
997 (reg:V2SI SPE_ACC_REGNO)] 560))
998 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1000 "evmhegsmian %0,%1,%2"
1001 [(set_attr "type" "veccomplex")
1002 (set_attr "length" "4")])
1004 (define_insn "spe_evmhegumiaa"
1005 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1006 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1007 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1008 (reg:V2SI SPE_ACC_REGNO)] 561))
1009 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1011 "evmhegumiaa %0,%1,%2"
1012 [(set_attr "type" "veccomplex")
1013 (set_attr "length" "4")])
1015 (define_insn "spe_evmhegumian"
1016 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1017 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1018 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1019 (reg:V2SI SPE_ACC_REGNO)] 562))
1020 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1022 "evmhegumian %0,%1,%2"
1023 [(set_attr "type" "veccomplex")
1024 (set_attr "length" "4")])
1026 (define_insn "spe_evmhesmfaaw"
1027 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1028 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1029 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1030 (reg:V2SI SPE_ACC_REGNO)] 563))
1031 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1033 "evmhesmfaaw %0,%1,%2"
1034 [(set_attr "type" "veccomplex")
1035 (set_attr "length" "4")])
1037 (define_insn "spe_evmhesmfanw"
1038 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1039 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1040 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1041 (reg:V2SI SPE_ACC_REGNO)] 564))
1042 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1044 "evmhesmfanw %0,%1,%2"
1045 [(set_attr "type" "veccomplex")
1046 (set_attr "length" "4")])
1048 (define_insn "spe_evmhesmfa"
1049 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1050 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1051 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
1052 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1054 "evmhesmfa %0,%1,%2"
1055 [(set_attr "type" "veccomplex")
1056 (set_attr "length" "4")])
1058 (define_insn "spe_evmhesmf"
1059 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1060 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1061 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
1064 [(set_attr "type" "veccomplex")
1065 (set_attr "length" "4")])
1067 (define_insn "spe_evmhesmiaaw"
1068 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1069 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1070 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1071 (reg:V2SI SPE_ACC_REGNO)] 567))
1072 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1074 "evmhesmiaaw %0,%1,%2"
1075 [(set_attr "type" "veccomplex")
1076 (set_attr "length" "4")])
1078 (define_insn "spe_evmhesmianw"
1079 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1080 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1081 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1082 (reg:V2SI SPE_ACC_REGNO)] 568))
1083 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1085 "evmhesmianw %0,%1,%2"
1086 [(set_attr "type" "veccomplex")
1087 (set_attr "length" "4")])
1089 (define_insn "spe_evmhesmia"
1090 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1091 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1092 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
1093 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1095 "evmhesmia %0,%1,%2"
1096 [(set_attr "type" "veccomplex")
1097 (set_attr "length" "4")])
1099 (define_insn "spe_evmhesmi"
1100 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1101 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1102 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1105 [(set_attr "type" "veccomplex")
1106 (set_attr "length" "4")])
1108 (define_insn "spe_evmhessfaaw"
1109 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1110 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1111 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1112 (reg:V2SI SPE_ACC_REGNO)] 571))
1113 (clobber (reg:SI SPEFSCR_REGNO))
1114 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1116 "evmhessfaaw %0,%1,%2"
1117 [(set_attr "type" "veccomplex")
1118 (set_attr "length" "4")])
1120 (define_insn "spe_evmhessfanw"
1121 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1122 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1123 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1124 (reg:V2SI SPE_ACC_REGNO)] 572))
1125 (clobber (reg:SI SPEFSCR_REGNO))
1126 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1128 "evmhessfanw %0,%1,%2"
1129 [(set_attr "type" "veccomplex")
1130 (set_attr "length" "4")])
1132 (define_insn "spe_evmhessfa"
1133 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1134 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1135 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1136 (clobber (reg:SI SPEFSCR_REGNO))
1137 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1139 "evmhessfa %0,%1,%2"
1140 [(set_attr "type" "veccomplex")
1141 (set_attr "length" "4")])
1143 (define_insn "spe_evmhessf"
1144 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1145 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1146 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1147 (clobber (reg:SI SPEFSCR_REGNO))]
1150 [(set_attr "type" "veccomplex")
1151 (set_attr "length" "4")])
1153 (define_insn "spe_evmhessiaaw"
1154 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1155 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1156 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1157 (reg:V2SI SPE_ACC_REGNO)] 575))
1158 (clobber (reg:SI SPEFSCR_REGNO))
1159 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1161 "evmhessiaaw %0,%1,%2"
1162 [(set_attr "type" "veccomplex")
1163 (set_attr "length" "4")])
1165 (define_insn "spe_evmhessianw"
1166 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1167 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1168 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1169 (reg:V2SI SPE_ACC_REGNO)] 576))
1170 (clobber (reg:SI SPEFSCR_REGNO))
1171 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1173 "evmhessianw %0,%1,%2"
1174 [(set_attr "type" "veccomplex")
1175 (set_attr "length" "4")])
1177 (define_insn "spe_evmheumiaaw"
1178 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1179 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1180 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1181 (reg:V2SI SPE_ACC_REGNO)] 577))
1182 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1184 "evmheumiaaw %0,%1,%2"
1185 [(set_attr "type" "veccomplex")
1186 (set_attr "length" "4")])
1188 (define_insn "spe_evmheumianw"
1189 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1190 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1191 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1192 (reg:V2SI SPE_ACC_REGNO)] 578))
1193 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1195 "evmheumianw %0,%1,%2"
1196 [(set_attr "type" "veccomplex")
1197 (set_attr "length" "4")])
1199 (define_insn "spe_evmheumia"
1200 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1201 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1202 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
1203 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1205 "evmheumia %0,%1,%2"
1206 [(set_attr "type" "veccomplex")
1207 (set_attr "length" "4")])
1209 (define_insn "spe_evmheumi"
1210 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1211 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1212 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1215 [(set_attr "type" "veccomplex")
1216 (set_attr "length" "4")])
1218 (define_insn "spe_evmheusiaaw"
1219 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1220 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1221 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1222 (reg:V2SI SPE_ACC_REGNO)] 581))
1223 (clobber (reg:SI SPEFSCR_REGNO))
1224 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1226 "evmheusiaaw %0,%1,%2"
1227 [(set_attr "type" "veccomplex")
1228 (set_attr "length" "4")])
1230 (define_insn "spe_evmheusianw"
1231 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1232 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1233 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1234 (reg:V2SI SPE_ACC_REGNO)] 582))
1235 (clobber (reg:SI SPEFSCR_REGNO))
1236 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1238 "evmheusianw %0,%1,%2"
1239 [(set_attr "type" "veccomplex")
1240 (set_attr "length" "4")])
1242 (define_insn "spe_evmhogsmfaa"
1243 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1244 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1245 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1246 (reg:V2SI SPE_ACC_REGNO)] 583))
1247 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1249 "evmhogsmfaa %0,%1,%2"
1250 [(set_attr "type" "veccomplex")
1251 (set_attr "length" "4")])
1253 (define_insn "spe_evmhogsmfan"
1254 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1255 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1256 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1257 (reg:V2SI SPE_ACC_REGNO)] 584))
1258 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1260 "evmhogsmfan %0,%1,%2"
1261 [(set_attr "type" "veccomplex")
1262 (set_attr "length" "4")])
1264 (define_insn "spe_evmhogsmiaa"
1265 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1266 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1267 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1268 (reg:V2SI SPE_ACC_REGNO)] 585))
1269 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1271 "evmhogsmiaa %0,%1,%2"
1272 [(set_attr "type" "veccomplex")
1273 (set_attr "length" "4")])
1275 (define_insn "spe_evmhogsmian"
1276 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1277 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1278 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1279 (reg:V2SI SPE_ACC_REGNO)] 586))
1280 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1282 "evmhogsmian %0,%1,%2"
1283 [(set_attr "type" "veccomplex")
1284 (set_attr "length" "4")])
1286 (define_insn "spe_evmhogumiaa"
1287 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1288 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1289 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1290 (reg:V2SI SPE_ACC_REGNO)] 587))
1291 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1293 "evmhogumiaa %0,%1,%2"
1294 [(set_attr "type" "veccomplex")
1295 (set_attr "length" "4")])
1297 (define_insn "spe_evmhogumian"
1298 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1299 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1300 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1301 (reg:V2SI SPE_ACC_REGNO)] 588))
1302 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1304 "evmhogumian %0,%1,%2"
1305 [(set_attr "type" "veccomplex")
1306 (set_attr "length" "4")])
1308 (define_insn "spe_evmhosmfaaw"
1309 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1310 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1311 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1312 (reg:V2SI SPE_ACC_REGNO)] 589))
1313 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1315 "evmhosmfaaw %0,%1,%2"
1316 [(set_attr "type" "veccomplex")
1317 (set_attr "length" "4")])
1319 (define_insn "spe_evmhosmfanw"
1320 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1321 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1322 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1323 (reg:V2SI SPE_ACC_REGNO)] 590))
1324 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1326 "evmhosmfanw %0,%1,%2"
1327 [(set_attr "type" "veccomplex")
1328 (set_attr "length" "4")])
1330 (define_insn "spe_evmhosmfa"
1331 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1332 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1333 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1335 "evmhosmfa %0,%1,%2"
1336 [(set_attr "type" "veccomplex")
1337 (set_attr "length" "4")])
1339 (define_insn "spe_evmhosmf"
1340 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1341 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1342 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
1343 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1346 [(set_attr "type" "veccomplex")
1347 (set_attr "length" "4")])
1349 (define_insn "spe_evmhosmiaaw"
1350 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1351 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1352 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1353 (reg:V2SI SPE_ACC_REGNO)] 593))
1354 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1356 "evmhosmiaaw %0,%1,%2"
1357 [(set_attr "type" "veccomplex")
1358 (set_attr "length" "4")])
1360 (define_insn "spe_evmhosmianw"
1361 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1362 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1363 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1364 (reg:V2SI SPE_ACC_REGNO)] 594))
1365 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1367 "evmhosmianw %0,%1,%2"
1368 [(set_attr "type" "veccomplex")
1369 (set_attr "length" "4")])
1371 (define_insn "spe_evmhosmia"
1372 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1373 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1374 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
1375 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1377 "evmhosmia %0,%1,%2"
1378 [(set_attr "type" "veccomplex")
1379 (set_attr "length" "4")])
1381 (define_insn "spe_evmhosmi"
1382 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1383 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1384 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1387 [(set_attr "type" "veccomplex")
1388 (set_attr "length" "4")])
1390 (define_insn "spe_evmhossfaaw"
1391 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1392 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1393 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1394 (reg:V2SI SPE_ACC_REGNO)] 597))
1395 (clobber (reg:SI SPEFSCR_REGNO))
1396 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1398 "evmhossfaaw %0,%1,%2"
1399 [(set_attr "type" "veccomplex")
1400 (set_attr "length" "4")])
1402 (define_insn "spe_evmhossfanw"
1403 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1404 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1405 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1406 (reg:V2SI SPE_ACC_REGNO)] 598))
1407 (clobber (reg:SI SPEFSCR_REGNO))
1408 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1410 "evmhossfanw %0,%1,%2"
1411 [(set_attr "type" "veccomplex")
1412 (set_attr "length" "4")])
1414 (define_insn "spe_evmhossfa"
1415 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1416 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1417 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1418 (reg:V2SI SPE_ACC_REGNO)] 599))
1419 (clobber (reg:SI SPEFSCR_REGNO))
1420 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1422 "evmhossfa %0,%1,%2"
1423 [(set_attr "type" "veccomplex")
1424 (set_attr "length" "4")])
1426 (define_insn "spe_evmhossf"
1427 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1428 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1429 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1430 (clobber (reg:SI SPEFSCR_REGNO))]
1433 [(set_attr "type" "veccomplex")
1434 (set_attr "length" "4")])
1436 (define_insn "spe_evmhossiaaw"
1437 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1438 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1439 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1440 (reg:V2SI SPE_ACC_REGNO)] 601))
1441 (clobber (reg:SI SPEFSCR_REGNO))
1442 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1444 "evmhossiaaw %0,%1,%2"
1445 [(set_attr "type" "veccomplex")
1446 (set_attr "length" "4")])
1448 (define_insn "spe_evmhossianw"
1449 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1450 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1451 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1452 (reg:V2SI SPE_ACC_REGNO)] 602))
1453 (clobber (reg:SI SPEFSCR_REGNO))
1454 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1456 "evmhossianw %0,%1,%2"
1457 [(set_attr "type" "veccomplex")
1458 (set_attr "length" "4")])
1460 (define_insn "spe_evmhoumiaaw"
1461 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1462 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1463 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1464 (reg:V2SI SPE_ACC_REGNO)] 603))
1465 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1467 "evmhoumiaaw %0,%1,%2"
1468 [(set_attr "type" "veccomplex")
1469 (set_attr "length" "4")])
1471 (define_insn "spe_evmhoumianw"
1472 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1473 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1474 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1475 (reg:V2SI SPE_ACC_REGNO)] 604))
1476 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1478 "evmhoumianw %0,%1,%2"
1479 [(set_attr "type" "veccomplex")
1480 (set_attr "length" "4")])
1482 (define_insn "spe_evmhoumia"
1483 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1484 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1485 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
1486 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1488 "evmhoumia %0,%1,%2"
1489 [(set_attr "type" "veccomplex")
1490 (set_attr "length" "4")])
1492 (define_insn "spe_evmhoumi"
1493 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1494 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1495 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1498 [(set_attr "type" "veccomplex")
1499 (set_attr "length" "4")])
1501 (define_insn "spe_evmhousiaaw"
1502 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1503 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1504 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1505 (reg:V2SI SPE_ACC_REGNO)] 607))
1506 (clobber (reg:SI SPEFSCR_REGNO))
1507 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1509 "evmhousiaaw %0,%1,%2"
1510 [(set_attr "type" "veccomplex")
1511 (set_attr "length" "4")])
1513 (define_insn "spe_evmhousianw"
1514 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1515 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1516 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1517 (reg:V2SI SPE_ACC_REGNO)] 608))
1518 (clobber (reg:SI SPEFSCR_REGNO))
1519 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1521 "evmhousianw %0,%1,%2"
1522 [(set_attr "type" "veccomplex")
1523 (set_attr "length" "4")])
1525 (define_insn "spe_evmmlssfa"
1526 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1527 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1528 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1530 "evmmlssfa %0,%1,%2"
1531 [(set_attr "type" "veccomplex")
1532 (set_attr "length" "4")])
1534 (define_insn "spe_evmmlssf"
1535 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1536 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1537 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1540 [(set_attr "type" "veccomplex")
1541 (set_attr "length" "4")])
1543 (define_insn "spe_evmwhsmfa"
1544 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1545 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1546 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
1547 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1549 "evmwhsmfa %0,%1,%2"
1550 [(set_attr "type" "veccomplex")
1551 (set_attr "length" "4")])
1553 (define_insn "spe_evmwhsmf"
1554 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1555 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1556 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1559 [(set_attr "type" "veccomplex")
1560 (set_attr "length" "4")])
1562 (define_insn "spe_evmwhsmia"
1563 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1564 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1565 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
1566 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1568 "evmwhsmia %0,%1,%2"
1569 [(set_attr "type" "veccomplex")
1570 (set_attr "length" "4")])
1572 (define_insn "spe_evmwhsmi"
1573 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1574 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1575 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1578 [(set_attr "type" "veccomplex")
1579 (set_attr "length" "4")])
1581 (define_insn "spe_evmwhssfa"
1582 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1583 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1584 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1585 (clobber (reg:SI SPEFSCR_REGNO))
1586 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1588 "evmwhssfa %0,%1,%2"
1589 [(set_attr "type" "veccomplex")
1590 (set_attr "length" "4")])
1592 (define_insn "spe_evmwhusian"
1593 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1594 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1595 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1597 "evmwhusian %0,%1,%2"
1598 [(set_attr "type" "veccomplex")
1599 (set_attr "length" "4")])
1601 (define_insn "spe_evmwhssf"
1602 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1603 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1604 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1605 (clobber (reg:SI SPEFSCR_REGNO))]
1608 [(set_attr "type" "veccomplex")
1609 (set_attr "length" "4")])
1611 (define_insn "spe_evmwhumia"
1612 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1613 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1614 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
1615 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1617 "evmwhumia %0,%1,%2"
1618 [(set_attr "type" "veccomplex")
1619 (set_attr "length" "4")])
1621 (define_insn "spe_evmwhumi"
1622 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1623 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1624 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1627 [(set_attr "type" "veccomplex")
1628 (set_attr "length" "4")])
1630 (define_insn "spe_evmwlsmiaaw"
1631 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1632 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1633 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1634 (reg:V2SI SPE_ACC_REGNO)] 635))
1635 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1637 "evmwlsmiaaw %0,%1,%2"
1638 [(set_attr "type" "veccomplex")
1639 (set_attr "length" "4")])
1641 (define_insn "spe_evmwlsmianw"
1642 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1643 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1644 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1645 (reg:V2SI SPE_ACC_REGNO)] 636))
1646 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1648 "evmwlsmianw %0,%1,%2"
1649 [(set_attr "type" "veccomplex")
1650 (set_attr "length" "4")])
1652 (define_insn "spe_evmwlssiaaw"
1653 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1654 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1655 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1656 (reg:V2SI SPE_ACC_REGNO)] 641))
1657 (clobber (reg:SI SPEFSCR_REGNO))
1658 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1660 "evmwlssiaaw %0,%1,%2"
1661 [(set_attr "type" "veccomplex")
1662 (set_attr "length" "4")])
1664 (define_insn "spe_evmwlssianw"
1665 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1666 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1667 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1668 (reg:V2SI SPE_ACC_REGNO)] 642))
1669 (clobber (reg:SI SPEFSCR_REGNO))
1670 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1672 "evmwlssianw %0,%1,%2"
1673 [(set_attr "type" "veccomplex")
1674 (set_attr "length" "4")])
1676 (define_insn "spe_evmwlumiaaw"
1677 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1678 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1679 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1680 (reg:V2SI SPE_ACC_REGNO)] 643))
1681 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1683 "evmwlumiaaw %0,%1,%2"
1684 [(set_attr "type" "veccomplex")
1685 (set_attr "length" "4")])
1687 (define_insn "spe_evmwlumianw"
1688 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1689 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1690 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1691 (reg:V2SI SPE_ACC_REGNO)] 644))
1692 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1694 "evmwlumianw %0,%1,%2"
1695 [(set_attr "type" "veccomplex")
1696 (set_attr "length" "4")])
1698 (define_insn "spe_evmwlumia"
1699 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1700 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1701 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
1702 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1704 "evmwlumia %0,%1,%2"
1705 [(set_attr "type" "veccomplex")
1706 (set_attr "length" "4")])
1708 (define_insn "spe_evmwlumi"
1709 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1710 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1711 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1714 [(set_attr "type" "veccomplex")
1715 (set_attr "length" "4")])
1717 (define_insn "spe_evmwlusiaaw"
1718 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1719 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1720 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1721 (reg:V2SI SPE_ACC_REGNO)] 647))
1722 (clobber (reg:SI SPEFSCR_REGNO))
1723 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1725 "evmwlusiaaw %0,%1,%2"
1726 [(set_attr "type" "veccomplex")
1727 (set_attr "length" "4")])
1729 (define_insn "spe_evmwlusianw"
1730 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1731 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1732 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1733 (reg:V2SI SPE_ACC_REGNO)] 648))
1734 (clobber (reg:SI SPEFSCR_REGNO))
1735 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1737 "evmwlusianw %0,%1,%2"
1738 [(set_attr "type" "veccomplex")
1739 (set_attr "length" "4")])
1741 (define_insn "spe_evmwsmfaa"
1742 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1743 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1744 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1745 (reg:V2SI SPE_ACC_REGNO)] 649))
1746 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1748 "evmwsmfaa %0,%1,%2"
1749 [(set_attr "type" "veccomplex")
1750 (set_attr "length" "4")])
1752 (define_insn "spe_evmwsmfan"
1753 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1754 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1755 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1756 (reg:V2SI SPE_ACC_REGNO)] 650))
1757 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1759 "evmwsmfan %0,%1,%2"
1760 [(set_attr "type" "veccomplex")
1761 (set_attr "length" "4")])
1763 (define_insn "spe_evmwsmfa"
1764 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1765 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1766 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
1767 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1770 [(set_attr "type" "veccomplex")
1771 (set_attr "length" "4")])
1773 (define_insn "spe_evmwsmf"
1774 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1775 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1776 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1779 [(set_attr "type" "veccomplex")
1780 (set_attr "length" "4")])
1782 (define_insn "spe_evmwsmiaa"
1783 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1784 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1785 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1786 (reg:V2SI SPE_ACC_REGNO)] 653))
1787 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1789 "evmwsmiaa %0,%1,%2"
1790 [(set_attr "type" "veccomplex")
1791 (set_attr "length" "4")])
1793 (define_insn "spe_evmwsmian"
1794 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1795 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1796 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1797 (reg:V2SI SPE_ACC_REGNO)] 654))
1798 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1800 "evmwsmian %0,%1,%2"
1801 [(set_attr "type" "veccomplex")
1802 (set_attr "length" "4")])
1804 (define_insn "spe_evmwsmia"
1805 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1806 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1807 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
1808 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1811 [(set_attr "type" "veccomplex")
1812 (set_attr "length" "4")])
1814 (define_insn "spe_evmwsmi"
1815 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1816 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1817 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1820 [(set_attr "type" "veccomplex")
1821 (set_attr "length" "4")])
1823 (define_insn "spe_evmwssfaa"
1824 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1825 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1826 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1827 (reg:V2SI SPE_ACC_REGNO)] 657))
1828 (clobber (reg:SI SPEFSCR_REGNO))
1829 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1831 "evmwssfaa %0,%1,%2"
1832 [(set_attr "type" "veccomplex")
1833 (set_attr "length" "4")])
1835 (define_insn "spe_evmwssfan"
1836 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1837 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1838 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1839 (reg:V2SI SPE_ACC_REGNO)] 658))
1840 (clobber (reg:SI SPEFSCR_REGNO))
1841 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1843 "evmwssfan %0,%1,%2"
1844 [(set_attr "type" "veccomplex")
1845 (set_attr "length" "4")])
1847 (define_insn "spe_evmwssfa"
1848 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1849 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1850 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1851 (clobber (reg:SI SPEFSCR_REGNO))
1852 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1855 [(set_attr "type" "veccomplex")
1856 (set_attr "length" "4")])
1858 (define_insn "spe_evmwssf"
1859 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1860 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1861 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1862 (clobber (reg:SI SPEFSCR_REGNO))]
1865 [(set_attr "type" "veccomplex")
1866 (set_attr "length" "4")])
1868 (define_insn "spe_evmwumiaa"
1869 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1870 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1871 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1872 (reg:V2SI SPE_ACC_REGNO)] 661))
1873 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1875 "evmwumiaa %0,%1,%2"
1876 [(set_attr "type" "veccomplex")
1877 (set_attr "length" "4")])
1879 (define_insn "spe_evmwumian"
1880 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1881 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1882 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1883 (reg:V2SI SPE_ACC_REGNO)] 662))
1884 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1886 "evmwumian %0,%1,%2"
1887 [(set_attr "type" "veccomplex")
1888 (set_attr "length" "4")])
1890 (define_insn "spe_evmwumia"
1891 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1892 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1893 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
1894 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1897 [(set_attr "type" "veccomplex")
1898 (set_attr "length" "4")])
1900 (define_insn "spe_evmwumi"
1901 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1902 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1903 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1906 [(set_attr "type" "veccomplex")
1907 (set_attr "length" "4")])
1909 (define_insn "addv2si3"
1910 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1911 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1912 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1915 [(set_attr "type" "vecsimple")
1916 (set_attr "length" "4")])
1918 (define_insn "spe_evaddusiaaw"
1919 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1920 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1921 (reg:V2SI SPE_ACC_REGNO)] 673))
1922 (clobber (reg:SI SPEFSCR_REGNO))
1923 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1926 [(set_attr "type" "veccomplex")
1927 (set_attr "length" "4")])
1929 (define_insn "spe_evaddumiaaw"
1930 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1931 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1932 (reg:V2SI SPE_ACC_REGNO)] 674))
1933 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1936 [(set_attr "type" "veccomplex")
1937 (set_attr "length" "4")])
1939 (define_insn "spe_evaddssiaaw"
1940 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1941 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1942 (reg:V2SI SPE_ACC_REGNO)] 675))
1943 (clobber (reg:SI SPEFSCR_REGNO))
1944 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1947 [(set_attr "type" "veccomplex")
1948 (set_attr "length" "4")])
1950 (define_insn "spe_evaddsmiaaw"
1951 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1952 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1953 (reg:V2SI SPE_ACC_REGNO)] 676))
1954 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1957 [(set_attr "type" "veccomplex")
1958 (set_attr "length" "4")])
1960 (define_insn "spe_evaddiw"
1961 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1962 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1963 (match_operand:QI 2 "immediate_operand" "i")] 677))]
1966 [(set_attr "type" "vecsimple")
1967 (set_attr "length" "4")])
1969 (define_insn "spe_evsubifw"
1970 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1971 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1972 (match_operand:QI 2 "immediate_operand" "i")] 678))]
1975 [(set_attr "type" "veccomplex")
1976 (set_attr "length" "4")])
1978 (define_insn "subv2si3"
1979 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1980 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1981 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1984 [(set_attr "type" "veccomplex")
1985 (set_attr "length" "4")])
1987 (define_insn "spe_evsubfusiaaw"
1988 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1989 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1990 (reg:V2SI SPE_ACC_REGNO)] 679))
1991 (clobber (reg:SI SPEFSCR_REGNO))
1992 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1994 "evsubfusiaaw %0,%1"
1995 [(set_attr "type" "veccomplex")
1996 (set_attr "length" "4")])
1998 (define_insn "spe_evsubfumiaaw"
1999 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2000 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2001 (reg:V2SI SPE_ACC_REGNO)] 680))
2002 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2004 "evsubfumiaaw %0,%1"
2005 [(set_attr "type" "veccomplex")
2006 (set_attr "length" "4")])
2008 (define_insn "spe_evsubfssiaaw"
2009 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2010 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2011 (reg:V2SI SPE_ACC_REGNO)] 681))
2012 (clobber (reg:SI SPEFSCR_REGNO))
2013 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2015 "evsubfssiaaw %0,%1"
2016 [(set_attr "type" "veccomplex")
2017 (set_attr "length" "4")])
2019 (define_insn "spe_evsubfsmiaaw"
2020 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2021 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2022 (reg:V2SI SPE_ACC_REGNO)] 682))
2023 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2025 "evsubfsmiaaw %0,%1"
2026 [(set_attr "type" "veccomplex")
2027 (set_attr "length" "4")])
2029 (define_insn "spe_evmra"
2030 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2031 (match_operand:V2SI 1 "gpc_reg_operand" "r"))
2032 (set (reg:V2SI SPE_ACC_REGNO)
2033 (unspec:V2SI [(match_dup 1)] 726))]
2036 [(set_attr "type" "veccomplex")
2037 (set_attr "length" "4")])
2039 (define_insn "divv2si3"
2040 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2041 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2042 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2043 (clobber (reg:SI SPEFSCR_REGNO))]
2046 [(set_attr "type" "vecdiv")
2047 (set_attr "length" "4")])
2049 (define_insn "spe_evdivwu"
2050 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2051 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2052 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2053 (clobber (reg:SI SPEFSCR_REGNO))]
2056 [(set_attr "type" "vecdiv")
2057 (set_attr "length" "4")])
2059 (define_insn "spe_evsplatfi"
2060 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2061 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2064 [(set_attr "type" "vecperm")
2065 (set_attr "length" "4")])
2067 (define_insn "spe_evsplati"
2068 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2069 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2072 [(set_attr "type" "vecperm")
2073 (set_attr "length" "4")])
2075 (define_insn "spe_evstdd"
2076 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2077 (match_operand:QI 1 "immediate_operand" "i")))
2078 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2079 (unspec [(const_int 0)] 686)]
2080 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2081 "evstdd %2,%1*8(%0)"
2082 [(set_attr "type" "vecstore")
2083 (set_attr "length" "4")])
2085 (define_insn "spe_evstddx"
2086 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2087 (match_operand:SI 1 "gpc_reg_operand" "r")))
2088 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2089 (unspec [(const_int 0)] 687)]
2092 [(set_attr "type" "vecstore")
2093 (set_attr "length" "4")])
2095 (define_insn "spe_evstdh"
2096 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2097 (match_operand:QI 1 "immediate_operand" "i")))
2098 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2099 (unspec [(const_int 0)] 688)]
2100 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2101 "evstdh %2,%1*8(%0)"
2102 [(set_attr "type" "vecstore")
2103 (set_attr "length" "4")])
2105 (define_insn "spe_evstdhx"
2106 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2107 (match_operand:SI 1 "gpc_reg_operand" "r")))
2108 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2109 (unspec [(const_int 0)] 689)]
2112 [(set_attr "type" "vecstore")
2113 (set_attr "length" "4")])
2115 (define_insn "spe_evstdw"
2116 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2117 (match_operand:QI 1 "immediate_operand" "i")))
2118 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2119 (unspec [(const_int 0)] 690)]
2120 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2121 "evstdw %2,%1*8(%0)"
2122 [(set_attr "type" "vecstore")
2123 (set_attr "length" "4")])
2125 (define_insn "spe_evstdwx"
2126 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2127 (match_operand:SI 1 "gpc_reg_operand" "r")))
2128 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2129 (unspec [(const_int 0)] 691)]
2132 [(set_attr "type" "vecstore")
2133 (set_attr "length" "4")])
2135 (define_insn "spe_evstwhe"
2136 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2137 (match_operand:QI 1 "immediate_operand" "i")))
2138 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2139 (unspec [(const_int 0)] 692)]
2140 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2141 "evstwhe %2,%1*4(%0)"
2142 [(set_attr "type" "vecstore")
2143 (set_attr "length" "4")])
2145 (define_insn "spe_evstwhex"
2146 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2147 (match_operand:SI 1 "gpc_reg_operand" "r")))
2148 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2149 (unspec [(const_int 0)] 693)]
2152 [(set_attr "type" "vecstore")
2153 (set_attr "length" "4")])
2155 (define_insn "spe_evstwho"
2156 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2157 (match_operand:QI 1 "immediate_operand" "i")))
2158 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2159 (unspec [(const_int 0)] 694)]
2160 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2161 "evstwho %2,%1*4(%0)"
2162 [(set_attr "type" "vecstore")
2163 (set_attr "length" "4")])
2165 (define_insn "spe_evstwhox"
2166 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2167 (match_operand:SI 1 "gpc_reg_operand" "r")))
2168 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2169 (unspec [(const_int 0)] 695)]
2172 [(set_attr "type" "vecstore")
2173 (set_attr "length" "4")])
2175 (define_insn "spe_evstwwe"
2176 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2177 (match_operand:QI 1 "immediate_operand" "i")))
2178 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2179 (unspec [(const_int 0)] 696)]
2180 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2181 "evstwwe %2,%1*4(%0)"
2182 [(set_attr "type" "vecstore")
2183 (set_attr "length" "4")])
2185 (define_insn "spe_evstwwex"
2186 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2187 (match_operand:SI 1 "gpc_reg_operand" "r")))
2188 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2189 (unspec [(const_int 0)] 697)]
2192 [(set_attr "type" "vecstore")
2193 (set_attr "length" "4")])
2195 (define_insn "spe_evstwwo"
2196 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2197 (match_operand:QI 1 "immediate_operand" "i")))
2198 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2199 (unspec [(const_int 0)] 698)]
2200 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2201 "evstwwo %2,%1*4(%0)"
2202 [(set_attr "type" "vecstore")
2203 (set_attr "length" "4")])
2205 (define_insn "spe_evstwwox"
2206 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2207 (match_operand:SI 1 "gpc_reg_operand" "r")))
2208 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2209 (unspec [(const_int 0)] 699)]
2212 [(set_attr "type" "vecstore")
2213 (set_attr "length" "4")])
2215 ;; Double-precision floating point instructions.
2217 ;; FIXME: Add o=r option.
2218 (define_insn "*frob_<SPE64:mode>_<DITI:mode>"
2219 [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
2220 (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
2221 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
2222 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
2227 (define_insn "*frob_tf_ti"
2228 [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2229 (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))]
2230 "TARGET_E500_DOUBLE"
2231 "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1"
2232 [(set_attr "length" "8")])
2234 (define_insn "*frob_<mode>_di_2"
2235 [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
2236 (match_operand:DI 1 "input_operand" "r,m"))]
2237 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2238 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2243 (define_insn "*frob_tf_di_8_2"
2244 [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8)
2245 (match_operand:DI 1 "input_operand" "r,m"))]
2246 "TARGET_E500_DOUBLE"
2248 evmergelo %L0,%1,%L1
2251 (define_insn "*frob_di_<mode>"
2252 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
2253 (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
2254 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2255 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2256 "evmergehi %0,%1,%1\;mr %L0,%1"
2257 [(set_attr "length" "8")])
2259 (define_insn "*frob_ti_tf"
2260 [(set (match_operand:TI 0 "nonimmediate_operand" "=&r")
2261 (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))]
2262 "TARGET_E500_DOUBLE"
2263 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2264 [(set_attr "length" "16")])
2266 (define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
2267 [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
2268 (match_operand:SPE64 1 "input_operand" "r,m"))]
2269 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
2270 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
2273 switch (which_alternative)
2278 return \"evmergehi %0,%1,%1\;mr %L0,%1\";
2280 /* If the address is not offsettable we need to load the whole
2281 doubleword into a 64-bit register and then copy the high word
2282 to form the correct output layout. */
2283 if (!offsettable_nonstrict_memref_p (operands[1]))
2284 return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
2285 /* If the low-address word is used in the address, we must load
2286 it last. Otherwise, load it first. Note that we cannot have
2287 auto-increment in that case since the address register is
2288 known to be dead. */
2289 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2291 return \"lwz %L0,%L1\;lwz %0,%1\";
2293 return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\";
2296 [(set_attr "length" "8,8")])
2298 ; As the above, but TImode at offset 8.
2299 (define_insn "*frob_ti_<mode>_8_2"
2300 [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
2301 (match_operand:SPE64 1 "input_operand" "r,m"))]
2302 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode)
2303 || (TARGET_SPE && <MODE>mode != DFmode)"
2306 switch (which_alternative)
2311 return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\";
2313 if (!offsettable_nonstrict_memref_p (operands[1]))
2314 return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\";
2315 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2317 return \"lwz %Z0,%L1\;lwz %Y0,%1\";
2319 return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\";
2322 [(set_attr "length" "8,8")])
2324 (define_insn "*frob_ti_tf_2"
2325 [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0)
2326 (match_operand:TF 1 "input_operand" "r"))]
2327 "TARGET_E500_DOUBLE"
2328 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2329 [(set_attr "length" "16")])
2331 (define_insn "mov_si<mode>_e500_subreg0"
2332 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
2333 (match_operand:SI 1 "input_operand" "r,m"))]
2334 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2335 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2338 evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
2339 [(set_attr "length" "4,12")])
2341 (define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low"
2342 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
2343 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2344 (match_operand 2 "" "")))]
2345 "((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2346 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
2347 && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
2352 rtx tmp = gen_reg_rtx (SImode);
2353 emit_insn (gen_elf_low (tmp, operands[1], operands[2]));
2354 emit_insn (gen_mov_si<mode>_e500_subreg0 (operands[0], tmp));
2357 [(set_attr "length" "8")])
2359 ;; ??? Could use evstwwe for memory stores in some cases, depending on
2361 (define_insn "*mov_si<mode>_e500_subreg0_2"
2362 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2363 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
2364 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2365 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2368 evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
2369 [(set_attr "length" "4,8")])
2371 (define_insn "*mov_si<mode>_e500_subreg4"
2372 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
2373 (match_operand:SI 1 "input_operand" "r,m"))]
2374 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2375 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2380 (define_insn "*mov_si<mode>_e500_subreg4_elf_low"
2381 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
2382 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2383 (match_operand 2 "" "")))]
2384 "((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2385 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
2386 && TARGET_ELF && !TARGET_64BIT"
2389 (define_insn "*mov_si<mode>_e500_subreg4_2"
2390 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2391 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
2392 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2393 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2398 (define_insn "*mov_sitf_e500_subreg8"
2399 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
2400 (match_operand:SI 1 "input_operand" "r,m"))]
2401 "TARGET_E500_DOUBLE"
2403 evmergelo %L0,%1,%L0
2404 evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
2405 [(set_attr "length" "4,12")])
2407 (define_insn "*mov_sitf_e500_subreg8_2"
2408 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2409 (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
2410 "TARGET_E500_DOUBLE"
2413 evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
2414 [(set_attr "length" "4,8")])
2416 (define_insn "*mov_sitf_e500_subreg12"
2417 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12)
2418 (match_operand:SI 1 "input_operand" "r,m"))]
2419 "TARGET_E500_DOUBLE"
2424 (define_insn "*mov_sitf_e500_subreg12_2"
2425 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2426 (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
2427 "TARGET_E500_DOUBLE"
2432 ;; FIXME: Allow r=CONST0.
2433 (define_insn "*movdf_e500_double"
2434 [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
2435 (match_operand:DF 1 "input_operand" "r,m,r"))]
2436 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
2437 && (gpc_reg_operand (operands[0], DFmode)
2438 || gpc_reg_operand (operands[1], DFmode))"
2441 switch (which_alternative)
2444 return \"evor %0,%1,%1\";
2446 return \"evldd%X1 %0,%y1\";
2448 return \"evstdd%X0 %1,%y0\";
2453 [(set_attr "type" "*,vecload,vecstore")
2454 (set_attr "length" "*,*,*")])
2456 (define_insn "spe_truncdfsf2"
2457 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2458 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2459 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2462 (define_insn "spe_absdf2"
2463 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2464 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2465 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2468 (define_insn "spe_nabsdf2"
2469 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2470 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
2471 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2474 (define_insn "spe_negdf2"
2475 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2476 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2477 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2480 (define_insn "spe_adddf3"
2481 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2482 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2483 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2484 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2487 (define_insn "spe_subdf3"
2488 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2489 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2490 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2491 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2494 (define_insn "spe_muldf3"
2495 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2496 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2497 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2498 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2501 (define_insn "spe_divdf3"
2502 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2503 (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2504 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2505 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2508 ;; Double-precision floating point instructions for IBM long double.
2510 (define_insn_and_split "spe_trunctfdf2_internal1"
2511 [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r")
2512 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))]
2514 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2518 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
2521 emit_note (NOTE_INSN_DELETED);
2525 (define_insn_and_split "spe_trunctfsf2"
2526 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2527 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r")))
2528 (clobber (match_scratch:DF 2 "=r"))]
2530 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2532 "&& reload_completed"
2534 (float_truncate:DF (match_dup 1)))
2536 (float_truncate:SF (match_dup 2)))]
2539 (define_insn "spe_extenddftf2"
2540 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o")
2541 (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r")))
2542 (clobber (match_scratch:DF 2 "=X,X,X,&r"))]
2544 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2547 evor %0,%1,%1\;evxor %L0,%L0,%L0
2548 evldd%X1 %0,%y1\;evxor %L0,%L0,%L0
2549 evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0"
2550 [(set_attr "length" "4,8,8,12")])
2552 (define_expand "spe_fix_trunctfsi2"
2553 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2554 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
2555 (clobber (match_dup 2))
2556 (clobber (match_dup 3))
2557 (clobber (match_dup 4))])]
2559 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2561 operands[2] = gen_reg_rtx (DFmode);
2562 operands[3] = gen_reg_rtx (SImode);
2563 operands[4] = gen_reg_rtx (SImode);
2566 ; Like fix_trunc_helper, add with rounding towards 0.
2567 (define_insn "spe_fix_trunctfsi2_internal"
2568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2569 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r")))
2570 (clobber (match_operand:DF 2 "gpc_reg_operand" "=r"))
2571 (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r"))
2572 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))]
2574 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2575 "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2"
2576 [(set_attr "length" "24")])
2578 (define_insn "spe_negtf2_internal"
2579 [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2580 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))]
2582 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2585 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2586 return \"efdneg %L0,%L1\;efdneg %0,%1\";
2588 return \"efdneg %0,%1\;efdneg %L0,%L1\";
2590 [(set_attr "length" "8")])
2592 (define_expand "spe_abstf2_cmp"
2593 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2594 (match_operand:TF 1 "gpc_reg_operand" "f"))
2595 (set (match_dup 3) (match_dup 5))
2596 (set (match_dup 5) (abs:DF (match_dup 5)))
2597 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2598 (match_dup 5))] CMPDFEQ_GPR))
2599 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2600 (label_ref (match_operand 2 "" ""))
2602 (set (match_dup 6) (neg:DF (match_dup 6)))]
2604 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2607 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
2608 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
2609 operands[3] = gen_reg_rtx (DFmode);
2610 operands[4] = gen_reg_rtx (CCFPmode);
2611 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2612 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2615 (define_expand "spe_abstf2_tst"
2616 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2617 (match_operand:TF 1 "gpc_reg_operand" "f"))
2618 (set (match_dup 3) (match_dup 5))
2619 (set (match_dup 5) (abs:DF (match_dup 5)))
2620 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2621 (match_dup 5))] TSTDFEQ_GPR))
2622 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2623 (label_ref (match_operand 2 "" ""))
2625 (set (match_dup 6) (neg:DF (match_dup 6)))]
2627 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2630 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
2631 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
2632 operands[3] = gen_reg_rtx (DFmode);
2633 operands[4] = gen_reg_rtx (CCFPmode);
2634 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2635 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2638 ;; Vector move instructions.
2640 (define_expand "movv2si"
2641 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2642 (match_operand:V2SI 1 "any_operand" ""))]
2644 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2646 (define_insn "*movv2si_internal"
2647 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2648 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
2650 && (gpc_reg_operand (operands[0], V2SImode)
2651 || gpc_reg_operand (operands[1], V2SImode))"
2654 switch (which_alternative)
2656 case 0: return \"evstdd%X0 %1,%y0\";
2657 case 1: return \"evldd%X1 %0,%y1\";
2658 case 2: return \"evor %0,%1,%1\";
2659 case 3: return output_vec_const_move (operands);
2660 default: gcc_unreachable ();
2663 [(set_attr "type" "vecload,vecstore,*,*")
2664 (set_attr "length" "*,*,*,12")])
2667 [(set (match_operand:V2SI 0 "register_operand" "")
2668 (match_operand:V2SI 1 "zero_constant" ""))]
2669 "TARGET_SPE && reload_completed"
2671 (xor:V2SI (match_dup 0) (match_dup 0)))]
2674 (define_expand "movv1di"
2675 [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2676 (match_operand:V1DI 1 "any_operand" ""))]
2678 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2680 (define_insn "*movv1di_internal"
2681 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2682 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
2684 && (gpc_reg_operand (operands[0], V1DImode)
2685 || gpc_reg_operand (operands[1], V1DImode))"
2691 [(set_attr "type" "vecload,vecstore,*,*")
2692 (set_attr "length" "*,*,*,*")])
2694 (define_expand "movv4hi"
2695 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2696 (match_operand:V4HI 1 "any_operand" ""))]
2698 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2700 (define_insn "*movv4hi_internal"
2701 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
2702 (match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
2704 && (gpc_reg_operand (operands[0], V4HImode)
2705 || gpc_reg_operand (operands[1], V4HImode))"
2711 [(set_attr "type" "vecload")])
2713 (define_expand "movv2sf"
2714 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2715 (match_operand:V2SF 1 "any_operand" ""))]
2716 "TARGET_SPE || TARGET_PAIRED_FLOAT"
2717 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2719 (define_insn "*movv2sf_internal"
2720 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2721 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
2723 && (gpc_reg_operand (operands[0], V2SFmode)
2724 || gpc_reg_operand (operands[1], V2SFmode))"
2730 [(set_attr "type" "vecload,vecstore,*,*")
2731 (set_attr "length" "*,*,*,*")])
2733 ;; End of vector move instructions.
2735 (define_insn "spe_evmwhssfaa"
2736 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2737 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2738 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2739 (clobber (reg:SI SPEFSCR_REGNO))
2740 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2742 "evmwhssfaa %0,%1,%2"
2743 [(set_attr "type" "veccomplex")
2744 (set_attr "length" "4")])
2746 (define_insn "spe_evmwhssmaa"
2747 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2748 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2749 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2750 (clobber (reg:SI SPEFSCR_REGNO))
2751 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2753 "evmwhssmaa %0,%1,%2"
2754 [(set_attr "type" "veccomplex")
2755 (set_attr "length" "4")])
2757 (define_insn "spe_evmwhsmfaa"
2758 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2759 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2760 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
2761 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2763 "evmwhsmfaa %0,%1,%2"
2764 [(set_attr "type" "veccomplex")
2765 (set_attr "length" "4")])
2767 (define_insn "spe_evmwhsmiaa"
2768 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2769 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2770 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
2771 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2773 "evmwhsmiaa %0,%1,%2"
2774 [(set_attr "type" "veccomplex")
2775 (set_attr "length" "4")])
2777 (define_insn "spe_evmwhusiaa"
2778 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2779 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2780 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2781 (clobber (reg:SI SPEFSCR_REGNO))
2782 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2784 "evmwhusiaa %0,%1,%2"
2785 [(set_attr "type" "veccomplex")
2786 (set_attr "length" "4")])
2788 (define_insn "spe_evmwhumiaa"
2789 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2790 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2791 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
2792 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2794 "evmwhumiaa %0,%1,%2"
2795 [(set_attr "type" "veccomplex")
2796 (set_attr "length" "4")])
2798 (define_insn "spe_evmwhssfan"
2799 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2800 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2801 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2802 (clobber (reg:SI SPEFSCR_REGNO))
2803 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2805 "evmwhssfan %0,%1,%2"
2806 [(set_attr "type" "veccomplex")
2807 (set_attr "length" "4")])
2809 (define_insn "spe_evmwhssian"
2810 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2811 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2812 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2813 (clobber (reg:SI SPEFSCR_REGNO))
2814 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2816 "evmwhssian %0,%1,%2"
2817 [(set_attr "type" "veccomplex")
2818 (set_attr "length" "4")])
2820 (define_insn "spe_evmwhsmfan"
2821 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2822 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2823 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
2824 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2826 "evmwhsmfan %0,%1,%2"
2827 [(set_attr "type" "veccomplex")
2828 (set_attr "length" "4")])
2830 (define_insn "spe_evmwhsmian"
2831 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2832 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2833 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
2834 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2836 "evmwhsmian %0,%1,%2"
2837 [(set_attr "type" "veccomplex")
2838 (set_attr "length" "4")])
2840 (define_insn "spe_evmwhumian"
2841 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2842 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2843 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
2844 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2846 "evmwhumian %0,%1,%2"
2847 [(set_attr "type" "veccomplex")
2848 (set_attr "length" "4")])
2850 (define_insn "spe_evmwhgssfaa"
2851 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2852 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2853 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2854 (clobber (reg:SI SPEFSCR_REGNO))
2855 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2857 "evmwhgssfaa %0,%1,%2"
2858 [(set_attr "type" "veccomplex")
2859 (set_attr "length" "4")])
2861 (define_insn "spe_evmwhgsmfaa"
2862 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2863 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2864 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
2865 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2867 "evmwhgsmfaa %0,%1,%2"
2868 [(set_attr "type" "veccomplex")
2869 (set_attr "length" "4")])
2871 (define_insn "spe_evmwhgsmiaa"
2872 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2873 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2874 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
2875 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2877 "evmwhgsmiaa %0,%1,%2"
2878 [(set_attr "type" "veccomplex")
2879 (set_attr "length" "4")])
2881 (define_insn "spe_evmwhgumiaa"
2882 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2883 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2884 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
2885 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2887 "evmwhgumiaa %0,%1,%2"
2888 [(set_attr "type" "veccomplex")
2889 (set_attr "length" "4")])
2891 (define_insn "spe_evmwhgssfan"
2892 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2893 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2894 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2895 (clobber (reg:SI SPEFSCR_REGNO))
2896 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2898 "evmwhgssfan %0,%1,%2"
2899 [(set_attr "type" "veccomplex")
2900 (set_attr "length" "4")])
2902 (define_insn "spe_evmwhgsmfan"
2903 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2904 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2905 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
2906 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2908 "evmwhgsmfan %0,%1,%2"
2909 [(set_attr "type" "veccomplex")
2910 (set_attr "length" "4")])
2912 (define_insn "spe_evmwhgsmian"
2913 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2914 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2915 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
2916 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2918 "evmwhgsmian %0,%1,%2"
2919 [(set_attr "type" "veccomplex")
2920 (set_attr "length" "4")])
2922 (define_insn "spe_evmwhgumian"
2923 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2924 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2925 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
2926 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2928 "evmwhgumian %0,%1,%2"
2929 [(set_attr "type" "veccomplex")
2930 (set_attr "length" "4")])
2932 (define_insn "spe_mtspefscr"
2933 [(set (reg:SI SPEFSCR_REGNO)
2934 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2938 [(set_attr "type" "vecsimple")])
2940 (define_insn "spe_mfspefscr"
2941 [(set (match_operand:SI 0 "register_operand" "=r")
2942 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2945 [(set_attr "type" "vecsimple")])
2948 (define_insn "e500_flip_gt_bit"
2949 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2951 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
2952 "!TARGET_FPRS && TARGET_HARD_FLOAT"
2955 return output_e500_flip_gt_bit (operands[0], operands[1]);
2957 [(set_attr "type" "cr_logical")])
2959 ;; MPC8540 single-precision FP instructions on GPRs.
2960 ;; We have 2 variants for each. One for IEEE compliant math and one
2961 ;; for non IEEE compliant math.
2963 (define_insn "cmpsfeq_gpr"
2964 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2966 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2967 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2969 "TARGET_HARD_FLOAT && !TARGET_FPRS
2970 && !(flag_finite_math_only && !flag_trapping_math)"
2972 [(set_attr "type" "veccmp")])
2974 (define_insn "tstsfeq_gpr"
2975 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2977 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2978 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2980 "TARGET_HARD_FLOAT && !TARGET_FPRS
2981 && flag_finite_math_only && !flag_trapping_math"
2983 [(set_attr "type" "veccmpsimple")])
2985 (define_insn "cmpsfgt_gpr"
2986 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2988 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2989 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2991 "TARGET_HARD_FLOAT && !TARGET_FPRS
2992 && !(flag_finite_math_only && !flag_trapping_math)"
2994 [(set_attr "type" "veccmp")])
2996 (define_insn "tstsfgt_gpr"
2997 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2999 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
3000 (match_operand:SF 2 "gpc_reg_operand" "r"))]
3002 "TARGET_HARD_FLOAT && !TARGET_FPRS
3003 && flag_finite_math_only && !flag_trapping_math"
3005 [(set_attr "type" "veccmpsimple")])
3007 (define_insn "cmpsflt_gpr"
3008 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3010 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
3011 (match_operand:SF 2 "gpc_reg_operand" "r"))]
3013 "TARGET_HARD_FLOAT && !TARGET_FPRS
3014 && !(flag_finite_math_only && !flag_trapping_math)"
3016 [(set_attr "type" "veccmp")])
3018 (define_insn "tstsflt_gpr"
3019 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3021 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
3022 (match_operand:SF 2 "gpc_reg_operand" "r"))]
3024 "TARGET_HARD_FLOAT && !TARGET_FPRS
3025 && flag_finite_math_only && !flag_trapping_math"
3027 [(set_attr "type" "veccmpsimple")])
3029 ;; Same thing, but for double-precision.
3031 (define_insn "cmpdfeq_gpr"
3032 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3034 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3035 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3037 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3038 && !(flag_finite_math_only && !flag_trapping_math)"
3040 [(set_attr "type" "veccmp")])
3042 (define_insn "tstdfeq_gpr"
3043 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3045 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3046 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3048 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3049 && flag_finite_math_only && !flag_trapping_math"
3051 [(set_attr "type" "veccmpsimple")])
3053 (define_insn "cmpdfgt_gpr"
3054 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3056 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3057 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3059 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3060 && !(flag_finite_math_only && !flag_trapping_math)"
3062 [(set_attr "type" "veccmp")])
3064 (define_insn "tstdfgt_gpr"
3065 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3067 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3068 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3070 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3071 && flag_finite_math_only && !flag_trapping_math"
3073 [(set_attr "type" "veccmpsimple")])
3075 (define_insn "cmpdflt_gpr"
3076 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3078 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3079 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3081 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3082 && !(flag_finite_math_only && !flag_trapping_math)"
3084 [(set_attr "type" "veccmp")])
3086 (define_insn "tstdflt_gpr"
3087 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3089 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3090 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3092 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3093 && flag_finite_math_only && !flag_trapping_math"
3095 [(set_attr "type" "veccmpsimple")])
3097 ;; Same thing, but for IBM long double.
3099 (define_insn "cmptfeq_gpr"
3100 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3102 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3103 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3106 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3107 && !(flag_finite_math_only && !flag_trapping_math)"
3108 "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2"
3109 [(set_attr "type" "veccmp")
3110 (set_attr "length" "12")])
3112 (define_insn "tsttfeq_gpr"
3113 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3115 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3116 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3119 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3120 && flag_finite_math_only && !flag_trapping_math"
3121 "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2"
3122 [(set_attr "type" "veccmpsimple")
3123 (set_attr "length" "12")])
3125 (define_insn "cmptfgt_gpr"
3126 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3128 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3129 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3132 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3133 && !(flag_finite_math_only && !flag_trapping_math)"
3134 "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2"
3135 [(set_attr "type" "veccmp")
3136 (set_attr "length" "20")])
3138 (define_insn "tsttfgt_gpr"
3139 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3141 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3142 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3145 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3146 && flag_finite_math_only && !flag_trapping_math"
3147 "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2"
3148 [(set_attr "type" "veccmpsimple")
3149 (set_attr "length" "20")])
3151 (define_insn "cmptflt_gpr"
3152 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3154 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3155 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3158 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3159 && !(flag_finite_math_only && !flag_trapping_math)"
3160 "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2"
3161 [(set_attr "type" "veccmp")
3162 (set_attr "length" "20")])
3164 (define_insn "tsttflt_gpr"
3165 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3167 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3168 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3171 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3172 && flag_finite_math_only && !flag_trapping_math"
3173 "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2"
3174 [(set_attr "type" "veccmpsimple")
3175 (set_attr "length" "20")])
3177 ;; Like cceq_ior_compare, but compare the GT bits.
3178 (define_insn "e500_cr_ior_compare"
3179 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3180 (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
3181 (match_operand 2 "cc_reg_operand" "y")]
3182 E500_CR_IOR_COMPARE))]
3183 "TARGET_HARD_FLOAT && !TARGET_FPRS"
3184 "cror 4*%0+gt,4*%1+gt,4*%2+gt"
3185 [(set_attr "type" "cr_logical")])
3187 ;; Out-of-line prologues and epilogues.
3188 (define_insn "*save_gpregs_spe"
3189 [(match_parallel 0 "any_parallel_operand"
3190 [(clobber (reg:P 65))
3191 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3193 (set (match_operand:V2SI 2 "memory_operand" "=m")
3194 (match_operand:V2SI 3 "gpc_reg_operand" "r"))])]
3197 [(set_attr "type" "branch")
3198 (set_attr "length" "4")])
3200 (define_insn "*restore_gpregs_spe"
3201 [(match_parallel 0 "any_parallel_operand"
3202 [(clobber (reg:P 65))
3203 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3205 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3206 (match_operand:V2SI 3 "memory_operand" "m"))])]
3209 [(set_attr "type" "branch")
3210 (set_attr "length" "4")])
3212 (define_insn "*return_and_restore_gpregs_spe"
3213 [(match_parallel 0 "any_parallel_operand"
3215 (clobber (reg:P 65))
3216 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3218 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3219 (match_operand:V2SI 3 "memory_operand" "m"))])]
3222 [(set_attr "type" "branch")
3223 (set_attr "length" "4")])