1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (and (match_code "reg")
120 (match_test "CA_REGNO_P (REGNO (op))")))
122 ;; Return 1 if op is a signed 5-bit constant integer.
123 (define_predicate "s5bit_cint_operand"
124 (and (match_code "const_int")
125 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
127 ;; Return 1 if op is a unsigned 3-bit constant integer.
128 (define_predicate "u3bit_cint_operand"
129 (and (match_code "const_int")
130 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
132 ;; Return 1 if op is a unsigned 5-bit constant integer.
133 (define_predicate "u5bit_cint_operand"
134 (and (match_code "const_int")
135 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
137 ;; Return 1 if op is a signed 8-bit constant integer.
138 ;; Integer multiplication complete more quickly
139 (define_predicate "s8bit_cint_operand"
140 (and (match_code "const_int")
141 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
143 ;; Return 1 if op is a unsigned 10-bit constant integer.
144 (define_predicate "u10bit_cint_operand"
145 (and (match_code "const_int")
146 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
148 ;; Return 1 if op is a constant integer that can fit in a D field.
149 (define_predicate "short_cint_operand"
150 (and (match_code "const_int")
151 (match_test "satisfies_constraint_I (op)")))
153 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
154 (define_predicate "u_short_cint_operand"
155 (and (match_code "const_int")
156 (match_test "satisfies_constraint_K (op)")))
158 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
159 (define_predicate "non_short_cint_operand"
160 (and (match_code "const_int")
161 (match_test "(unsigned HOST_WIDE_INT)
162 (INTVAL (op) + 0x8000) >= 0x10000")))
164 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
165 (define_predicate "exact_log2_cint_operand"
166 (and (match_code "const_int")
167 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
169 ;; Match op = 0 or op = 1.
170 (define_predicate "const_0_to_1_operand"
171 (and (match_code "const_int")
172 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
175 (define_predicate "const_0_to_3_operand"
176 (and (match_code "const_int")
177 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
179 ;; Match op = 2 or op = 3.
180 (define_predicate "const_2_to_3_operand"
181 (and (match_code "const_int")
182 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
185 (define_predicate "const_0_to_15_operand"
186 (and (match_code "const_int")
187 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
189 ;; Return 1 if op is a register that is not special.
190 (define_predicate "gpc_reg_operand"
191 (match_operand 0 "register_operand")
193 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
196 if (GET_CODE (op) == SUBREG)
197 op = SUBREG_REG (op);
202 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
205 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
208 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
211 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
212 ;; allow floating point or vector registers.
213 (define_predicate "int_reg_operand"
214 (match_operand 0 "register_operand")
216 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
219 if (GET_CODE (op) == SUBREG)
220 op = SUBREG_REG (op);
225 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
228 return INT_REGNO_P (REGNO (op));
231 ;; Like int_reg_operand, but only return true for base registers
232 (define_predicate "base_reg_operand"
233 (match_operand 0 "int_reg_operand")
235 if (GET_CODE (op) == SUBREG)
236 op = SUBREG_REG (op);
241 return (REGNO (op) != FIRST_GPR_REGNO);
244 ;; Return 1 if op is a HTM specific SPR register.
245 (define_predicate "htm_spr_reg_operand"
246 (match_operand 0 "register_operand")
251 if (GET_CODE (op) == SUBREG)
252 op = SUBREG_REG (op);
271 ;; Return 1 if op is a general purpose register that is an even register
272 ;; which suitable for a load/store quad operation
273 (define_predicate "quad_int_reg_operand"
274 (match_operand 0 "register_operand")
278 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
281 if (GET_CODE (op) == SUBREG)
282 op = SUBREG_REG (op);
288 if (r >= FIRST_PSEUDO_REGISTER)
291 return (INT_REGNO_P (r) && ((r & 1) == 0));
294 ;; Return 1 if op is a register that is a condition register field.
295 (define_predicate "cc_reg_operand"
296 (match_operand 0 "register_operand")
298 if (GET_CODE (op) == SUBREG)
299 op = SUBREG_REG (op);
304 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
307 return CR_REGNO_P (REGNO (op));
310 ;; Return 1 if op is a register that is a condition register field not cr0.
311 (define_predicate "cc_reg_not_cr0_operand"
312 (match_operand 0 "register_operand")
314 if (GET_CODE (op) == SUBREG)
315 op = SUBREG_REG (op);
320 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
323 return CR_REGNO_NOT_CR0_P (REGNO (op));
326 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
327 (define_predicate "cc_reg_not_micro_cr0_operand"
328 (match_operand 0 "register_operand")
330 if (GET_CODE (op) == SUBREG)
331 op = SUBREG_REG (op);
336 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
339 if (rs6000_gen_cell_microcode)
340 return CR_REGNO_NOT_CR0_P (REGNO (op));
342 return CR_REGNO_P (REGNO (op));
345 ;; Return 1 if op is a constant integer valid for D field
346 ;; or non-special register register.
347 (define_predicate "reg_or_short_operand"
348 (if_then_else (match_code "const_int")
349 (match_operand 0 "short_cint_operand")
350 (match_operand 0 "gpc_reg_operand")))
352 ;; Return 1 if op is a constant integer valid whose negation is valid for
353 ;; D field or non-special register register.
354 ;; Do not allow a constant zero because all patterns that call this
355 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
356 ;; or equal to const, which does not work for zero.
357 (define_predicate "reg_or_neg_short_operand"
358 (if_then_else (match_code "const_int")
359 (match_test "satisfies_constraint_P (op)
360 && INTVAL (op) != 0")
361 (match_operand 0 "gpc_reg_operand")))
363 ;; Return 1 if op is a constant integer valid for DS field
364 ;; or non-special register.
365 (define_predicate "reg_or_aligned_short_operand"
366 (if_then_else (match_code "const_int")
367 (and (match_operand 0 "short_cint_operand")
368 (match_test "!(INTVAL (op) & 3)"))
369 (match_operand 0 "gpc_reg_operand")))
371 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
372 ;; or non-special register.
373 (define_predicate "reg_or_u_short_operand"
374 (if_then_else (match_code "const_int")
375 (match_operand 0 "u_short_cint_operand")
376 (match_operand 0 "gpc_reg_operand")))
378 ;; Return 1 if op is any constant integer
379 ;; or non-special register.
380 (define_predicate "reg_or_cint_operand"
381 (ior (match_code "const_int")
382 (match_operand 0 "gpc_reg_operand")))
384 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
385 (define_predicate "add_cint_operand"
386 (and (match_code "const_int")
387 (match_test "(unsigned HOST_WIDE_INT)
388 (INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
389 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
391 ;; Return 1 if op is a constant integer valid for addition
392 ;; or non-special register.
393 (define_predicate "reg_or_add_cint_operand"
394 (if_then_else (match_code "const_int")
395 (match_operand 0 "add_cint_operand")
396 (match_operand 0 "gpc_reg_operand")))
398 ;; Return 1 if op is a constant integer valid for subtraction
399 ;; or non-special register.
400 (define_predicate "reg_or_sub_cint_operand"
401 (if_then_else (match_code "const_int")
402 (match_test "(unsigned HOST_WIDE_INT)
403 (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
404 < (unsigned HOST_WIDE_INT) 0x100000000ll")
405 (match_operand 0 "gpc_reg_operand")))
407 ;; Return 1 if op is any 32-bit unsigned constant integer
408 ;; or non-special register.
409 (define_predicate "reg_or_logical_cint_operand"
410 (if_then_else (match_code "const_int")
411 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
413 || ((INTVAL (op) & GET_MODE_MASK (mode)
414 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
415 (match_operand 0 "gpc_reg_operand")))
417 ;; Like reg_or_logical_cint_operand, but allow vsx registers
418 (define_predicate "vsx_reg_or_cint_operand"
419 (ior (match_operand 0 "vsx_register_operand")
420 (match_operand 0 "reg_or_logical_cint_operand")))
422 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
423 ;; with no more than one instruction per word.
424 (define_predicate "easy_fp_constant"
425 (match_code "const_double")
430 if (GET_MODE (op) != mode
431 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
434 /* Consider all constants with -msoft-float to be easy. */
435 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
436 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
440 /* The constant 0.0 is easy under VSX. */
441 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
442 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
445 if (DECIMAL_FLOAT_MODE_P (mode))
448 /* If we are using V.4 style PIC, consider all constants to be hard. */
449 if (flag_pic && DEFAULT_ABI == ABI_V4)
452 #ifdef TARGET_RELOCATABLE
453 /* Similarly if we are using -mrelocatable, consider all constants
455 if (TARGET_RELOCATABLE)
462 if (TARGET_E500_DOUBLE)
465 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
466 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
468 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
469 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
470 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
471 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
474 /* The constant 0.f is easy under VSX. */
475 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
478 /* Force constants to memory before reload to utilize
479 compress_float_constant.
480 Avoid this when flag_unsafe_math_optimizations is enabled
481 because RDIV division to reciprocal optimization is not able
482 to regenerate the division. */
483 if (TARGET_E500_DOUBLE
484 || (!reload_in_progress && !reload_completed
485 && !flag_unsafe_math_optimizations))
488 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
489 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
491 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
492 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
495 /* The constant 0.f is easy. */
496 if (op == CONST0_RTX (SFmode))
499 /* Force constants to memory before reload to utilize
500 compress_float_constant.
501 Avoid this when flag_unsafe_math_optimizations is enabled
502 because RDIV division to reciprocal optimization is not able
503 to regenerate the division. */
504 if (!reload_in_progress && !reload_completed
505 && !flag_unsafe_math_optimizations)
508 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
509 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
511 return num_insns_constant_wide (k[0]) == 1;
514 return (num_insns_constant (op, DImode) <= 2);
524 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
525 ;; vector register without using memory.
526 (define_predicate "easy_vector_constant"
527 (match_code "const_vector")
529 /* As the paired vectors are actually FPRs it seems that there is
530 no easy way to load a CONST_VECTOR without using memory. */
531 if (TARGET_PAIRED_FLOAT)
534 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
536 if (zero_constant (op, mode))
539 return easy_altivec_constant (op, mode);
542 if (SPE_VECTOR_MODE (mode))
545 if (zero_constant (op, mode))
547 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
550 /* Limit SPE vectors to 15 bits signed. These we can generate with:
555 I don't know how efficient it would be to allow bigger constants,
556 considering we'll have an extra 'ori' for every 'li'. I doubt 5
557 instructions is better than a 64-bit memory load, but I don't
558 have the e500 timing specs. */
559 if (mode == V2SImode)
561 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
562 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
563 return cst >= -0x7fff && cst <= 0x7fff
564 && cst2 >= -0x7fff && cst2 <= 0x7fff;
571 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
572 (define_predicate "easy_vector_constant_add_self"
573 (and (match_code "const_vector")
574 (and (match_test "TARGET_ALTIVEC")
575 (match_test "easy_altivec_constant (op, mode)")))
579 if (mode == V2DImode || mode == V2DFmode)
581 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
582 val = const_vector_elt_as_int (op, elt);
583 val = ((val & 0xff) ^ 0x80) - 0x80;
584 return EASY_VECTOR_15_ADD_SELF (val);
587 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
588 (define_predicate "easy_vector_constant_msb"
589 (and (match_code "const_vector")
590 (and (match_test "TARGET_ALTIVEC")
591 (match_test "easy_altivec_constant (op, mode)")))
595 if (mode == V2DImode || mode == V2DFmode)
597 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
598 val = const_vector_elt_as_int (op, elt);
599 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
602 ;; Return 1 if operand is constant zero (scalars and vectors).
603 (define_predicate "zero_constant"
604 (and (match_code "const_int,const_double,const_vector")
605 (match_test "op == CONST0_RTX (mode)")))
607 ;; Return 1 if operand is 0.0.
608 (define_predicate "zero_fp_constant"
609 (and (match_code "const_double")
610 (match_test "SCALAR_FLOAT_MODE_P (mode)
611 && op == CONST0_RTX (mode)")))
613 ;; Return 1 if the operand is in volatile memory. Note that during the
614 ;; RTL generation phase, memory_operand does not return TRUE for volatile
615 ;; memory references. So this function allows us to recognize volatile
616 ;; references where it's safe.
617 (define_predicate "volatile_mem_operand"
618 (and (and (match_code "mem")
619 (match_test "MEM_VOLATILE_P (op)"))
620 (if_then_else (match_test "reload_completed")
621 (match_operand 0 "memory_operand")
622 (if_then_else (match_test "reload_in_progress")
623 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
624 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
626 ;; Return 1 if the operand is an offsettable memory operand.
627 (define_predicate "offsettable_mem_operand"
628 (and (match_operand 0 "memory_operand")
629 (match_test "offsettable_nonstrict_memref_p (op)")))
631 ;; Return 1 if the operand is suitable for load/store quad memory.
632 ;; This predicate only checks for non-atomic loads/stores.
633 (define_predicate "quad_memory_operand"
639 if (!TARGET_QUAD_MEMORY)
642 else if (!memory_operand (op, mode))
645 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
648 else if (MEM_ALIGN (op) < 128)
654 if (int_reg_operand (addr, Pmode))
657 else if (GET_CODE (addr) != PLUS)
662 op0 = XEXP (addr, 0);
663 op1 = XEXP (addr, 1);
664 ret = (int_reg_operand (op0, Pmode)
665 && GET_CODE (op1) == CONST_INT
666 && IN_RANGE (INTVAL (op1), -32768, 32767)
667 && (INTVAL (op1) & 15) == 0);
671 if (TARGET_DEBUG_ADDR)
673 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
680 ;; Return 1 if the operand is an indexed or indirect memory operand.
681 (define_predicate "indexed_or_indirect_operand"
685 if (VECTOR_MEM_ALTIVEC_P (mode)
686 && GET_CODE (op) == AND
687 && GET_CODE (XEXP (op, 1)) == CONST_INT
688 && INTVAL (XEXP (op, 1)) == -16)
691 return indexed_or_indirect_address (op, mode);
694 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
695 ;; moves are supported.
696 (define_predicate "reg_or_indexed_operand"
697 (match_code "mem,reg")
700 return indexed_or_indirect_operand (op, mode);
701 else if (TARGET_DIRECT_MOVE)
702 return register_operand (op, mode);
707 ;; Return 1 if the operand is an indexed or indirect memory operand with an
708 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
709 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
710 ;; while VSX uses the full address and traps)
711 (define_predicate "altivec_indexed_or_indirect_operand"
715 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
716 && GET_CODE (op) == AND
717 && GET_CODE (XEXP (op, 1)) == CONST_INT
718 && INTVAL (XEXP (op, 1)) == -16)
719 return indexed_or_indirect_address (XEXP (op, 0), mode);
724 ;; Return 1 if the operand is an indexed or indirect address.
725 (define_special_predicate "indexed_or_indirect_address"
726 (and (match_test "REG_P (op)
727 || (GET_CODE (op) == PLUS
728 /* Omit testing REG_P (XEXP (op, 0)). */
729 && REG_P (XEXP (op, 1)))")
730 (match_operand 0 "address_operand")))
732 ;; Return 1 if the operand is an index-form address.
733 (define_special_predicate "indexed_address"
734 (match_test "(GET_CODE (op) == PLUS
735 && REG_P (XEXP (op, 0))
736 && REG_P (XEXP (op, 1)))"))
738 ;; Return 1 if the operand is a MEM with an update-form address. This may
739 ;; also include update-indexed form.
740 (define_special_predicate "update_address_mem"
741 (match_test "(MEM_P (op)
742 && (GET_CODE (XEXP (op, 0)) == PRE_INC
743 || GET_CODE (XEXP (op, 0)) == PRE_DEC
744 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
746 ;; Return 1 if the operand is a MEM with an update-indexed-form address. Note
747 ;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the
748 ;; increment is based on the mode size and will therefor always be a const.
749 (define_special_predicate "update_indexed_address_mem"
750 (match_test "(MEM_P (op)
751 && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
752 && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
754 ;; Used for the destination of the fix_truncdfsi2 expander.
755 ;; If stfiwx will be used, the result goes to memory; otherwise,
756 ;; we're going to emit a store and a load of a subreg, so the dest is a
758 (define_predicate "fix_trunc_dest_operand"
759 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
760 (match_operand 0 "memory_operand")
761 (match_operand 0 "gpc_reg_operand")))
763 ;; Return 1 if the operand is either a non-special register or can be used
764 ;; as the operand of a `mode' add insn.
765 (define_predicate "add_operand"
766 (if_then_else (match_code "const_int")
767 (match_test "satisfies_constraint_I (op)
768 || satisfies_constraint_L (op)")
769 (match_operand 0 "gpc_reg_operand")))
771 ;; Return 1 if OP is a constant but not a valid add_operand.
772 (define_predicate "non_add_cint_operand"
773 (and (match_code "const_int")
774 (match_test "!satisfies_constraint_I (op)
775 && !satisfies_constraint_L (op)")))
777 ;; Return 1 if the operand is a constant that can be used as the operand
779 (define_predicate "logical_const_operand"
780 (match_code "const_int")
784 opl = INTVAL (op) & GET_MODE_MASK (mode);
786 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
787 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
790 ;; Return 1 if the operand is a non-special register or a constant that
791 ;; can be used as the operand of an OR or XOR.
792 (define_predicate "logical_operand"
793 (ior (match_operand 0 "gpc_reg_operand")
794 (match_operand 0 "logical_const_operand")))
796 ;; Return 1 if op is a constant that is not a logical operand, but could
797 ;; be split into one.
798 (define_predicate "non_logical_cint_operand"
799 (and (match_code "const_int,const_double")
800 (and (not (match_operand 0 "logical_operand"))
801 (match_operand 0 "reg_or_logical_cint_operand"))))
803 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
804 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
805 ;; transitions). Reject all ones and all zeros, since these should have
806 ;; been optimized away and confuse the making of MB and ME.
807 (define_predicate "mask_operand"
808 (match_code "const_int")
810 HOST_WIDE_INT c, lsb;
814 if (TARGET_POWERPC64)
816 /* Fail if the mask is not 32-bit. */
817 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
820 /* Fail if the mask wraps around because the upper 32-bits of the
821 mask will all be 1s, contrary to GCC's internal view. */
822 if ((c & 0x80000001) == 0x80000001)
826 /* We don't change the number of transitions by inverting,
827 so make sure we start with the LS bit zero. */
831 /* Reject all zeros or all ones. */
835 /* Find the first transition. */
838 /* Invert to look for a second transition. */
841 /* Erase first transition. */
844 /* Find the second transition (if any). */
847 /* Match if all the bits above are 1's (or c is zero). */
851 ;; Return 1 for the PowerPC64 rlwinm corner case.
852 (define_predicate "mask_operand_wrap"
853 (match_code "const_int")
855 HOST_WIDE_INT c, lsb;
859 if ((c & 0x80000001) != 0x80000001)
873 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
874 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
875 ;; transition). Reject all zeros, since zero should have been
876 ;; optimized away and confuses the making of MB and ME.
877 (define_predicate "mask64_operand"
878 (match_code "const_int")
880 HOST_WIDE_INT c, lsb;
884 /* Reject all zeros. */
888 /* We don't change the number of transitions by inverting,
889 so make sure we start with the LS bit zero. */
893 /* Find the first transition. */
896 /* Match if all the bits above are 1's (or c is zero). */
900 ;; Like mask64_operand, but allow up to three transitions. This
901 ;; predicate is used by insn patterns that generate two rldicl or
902 ;; rldicr machine insns.
903 (define_predicate "mask64_2_operand"
904 (match_code "const_int")
906 HOST_WIDE_INT c, lsb;
910 /* Disallow all zeros. */
914 /* We don't change the number of transitions by inverting,
915 so make sure we start with the LS bit zero. */
919 /* Find the first transition. */
922 /* Invert to look for a second transition. */
925 /* Erase first transition. */
928 /* Find the second transition. */
931 /* Invert to look for a third transition. */
934 /* Erase second transition. */
937 /* Find the third transition (if any). */
940 /* Match if all the bits above are 1's (or c is zero). */
944 ;; Like and_operand, but also match constants that can be implemented
945 ;; with two rldicl or rldicr insns.
946 (define_predicate "and64_2_operand"
947 (ior (match_operand 0 "mask64_2_operand")
948 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
949 (match_operand 0 "gpc_reg_operand")
950 (match_operand 0 "logical_operand"))))
952 ;; Return 1 if the operand is either a non-special register or a
953 ;; constant that can be used as the operand of a logical AND.
954 (define_predicate "and_operand"
955 (ior (match_operand 0 "mask_operand")
956 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
957 (match_operand 0 "mask64_operand"))
958 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
959 (match_operand 0 "gpc_reg_operand")
960 (match_operand 0 "logical_operand")))))
962 ;; Return 1 if the operand is either a logical operand or a short cint operand.
963 (define_predicate "scc_eq_operand"
964 (ior (match_operand 0 "logical_operand")
965 (match_operand 0 "short_cint_operand")))
967 ;; Return 1 if the operand is a general non-special register or memory operand.
968 (define_predicate "reg_or_mem_operand"
969 (ior (match_operand 0 "memory_operand")
970 (ior (and (match_code "mem")
971 (match_test "macho_lo_sum_memory_operand (op, mode)"))
972 (ior (match_operand 0 "volatile_mem_operand")
973 (match_operand 0 "gpc_reg_operand")))))
975 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
976 (define_predicate "reg_or_none500mem_operand"
977 (if_then_else (match_code "mem")
978 (and (match_test "!TARGET_E500_DOUBLE")
979 (ior (match_operand 0 "memory_operand")
980 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
981 (match_operand 0 "volatile_mem_operand"))))
982 (match_operand 0 "gpc_reg_operand")))
984 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
985 (define_predicate "zero_reg_mem_operand"
986 (ior (match_operand 0 "zero_fp_constant")
987 (match_operand 0 "reg_or_mem_operand")))
989 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
990 ;; data types inside of a vector that scalar instructions operate on
991 (define_predicate "vsx_scalar_64bit"
992 (match_code "const_int")
994 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
997 ;; Return 1 if the operand is a general register or memory operand without
998 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
1000 (define_predicate "lwa_operand"
1001 (match_code "reg,subreg,mem")
1003 rtx inner, addr, offset;
1006 if (reload_completed && GET_CODE (inner) == SUBREG)
1007 inner = SUBREG_REG (inner);
1009 if (gpc_reg_operand (inner, mode))
1011 if (!memory_operand (inner, mode))
1013 addr = XEXP (inner, 0);
1014 if (GET_CODE (addr) == PRE_INC
1015 || GET_CODE (addr) == PRE_DEC
1016 || (GET_CODE (addr) == PRE_MODIFY
1017 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1019 if (GET_CODE (addr) == LO_SUM
1020 && GET_CODE (XEXP (addr, 0)) == REG
1021 && GET_CODE (XEXP (addr, 1)) == CONST)
1022 addr = XEXP (XEXP (addr, 1), 0);
1023 if (GET_CODE (addr) != PLUS)
1025 offset = XEXP (addr, 1);
1026 if (GET_CODE (offset) != CONST_INT)
1028 return INTVAL (offset) % 4 == 0;
1031 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1032 (define_predicate "symbol_ref_operand"
1033 (and (match_code "symbol_ref")
1034 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1035 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1037 ;; Return 1 if op is an operand that can be loaded via the GOT.
1038 ;; or non-special register register field no cr0
1039 (define_predicate "got_operand"
1040 (match_code "symbol_ref,const,label_ref"))
1042 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1043 ;; excluding labels involving addition.
1044 (define_predicate "got_no_const_operand"
1045 (match_code "symbol_ref,label_ref"))
1047 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1048 (define_predicate "rs6000_tls_symbol_ref"
1049 (and (match_code "symbol_ref")
1050 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1052 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1053 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1054 (define_predicate "call_operand"
1055 (if_then_else (match_code "reg")
1056 (match_test "REGNO (op) == LR_REGNO
1057 || REGNO (op) == CTR_REGNO
1058 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1059 (match_code "symbol_ref")))
1061 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1063 (define_predicate "current_file_function_operand"
1064 (and (match_code "symbol_ref")
1065 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1066 && ((SYMBOL_REF_LOCAL_P (op)
1067 && ((DEFAULT_ABI != ABI_AIX
1068 && DEFAULT_ABI != ABI_ELFv2)
1069 || !SYMBOL_REF_EXTERNAL_P (op)))
1070 || (op == XEXP (DECL_RTL (current_function_decl),
1073 ;; Return 1 if this operand is a valid input for a move insn.
1074 (define_predicate "input_operand"
1075 (match_code "symbol_ref,const,reg,subreg,mem,
1076 const_double,const_vector,const_int")
1078 /* Memory is always valid. */
1079 if (memory_operand (op, mode))
1082 /* For floating-point, easy constants are valid. */
1083 if (SCALAR_FLOAT_MODE_P (mode)
1084 && easy_fp_constant (op, mode))
1087 /* Allow any integer constant. */
1088 if (GET_MODE_CLASS (mode) == MODE_INT
1089 && (GET_CODE (op) == CONST_INT
1090 || GET_CODE (op) == CONST_DOUBLE))
1093 /* Allow easy vector constants. */
1094 if (GET_CODE (op) == CONST_VECTOR
1095 && easy_vector_constant (op, mode))
1098 /* Do not allow invalid E500 subregs. */
1099 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1100 && GET_CODE (op) == SUBREG
1101 && invalid_e500_subreg (op, mode))
1104 /* For floating-point or multi-word mode, the only remaining valid type
1106 if (SCALAR_FLOAT_MODE_P (mode)
1107 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1108 return register_operand (op, mode);
1110 /* The only cases left are integral modes one word or smaller (we
1111 do not get called for MODE_CC values). These can be in any
1113 if (register_operand (op, mode))
1116 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1118 if (DEFAULT_ABI == ABI_V4
1119 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1120 && small_data_operand (op, Pmode))
1126 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1127 (define_predicate "splat_input_operand"
1128 (match_code "symbol_ref,const,reg,subreg,mem,
1129 const_double,const_vector,const_int")
1133 if (! volatile_ok && MEM_VOLATILE_P (op))
1137 else if (mode == DImode)
1141 return memory_address_addr_space_p (mode, XEXP (op, 0),
1142 MEM_ADDR_SPACE (op));
1144 return input_operand (op, mode);
1147 ;; Return true if OP is a non-immediate operand and not an invalid
1148 ;; SUBREG operation on the e500.
1149 (define_predicate "rs6000_nonimmediate_operand"
1150 (match_code "reg,subreg,mem")
1152 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1153 && GET_CODE (op) == SUBREG
1154 && invalid_e500_subreg (op, mode))
1157 return nonimmediate_operand (op, mode);
1160 ;; Return true if operand is boolean operator.
1161 (define_predicate "boolean_operator"
1162 (match_code "and,ior,xor"))
1164 ;; Return true if operand is OR-form of boolean operator.
1165 (define_predicate "boolean_or_operator"
1166 (match_code "ior,xor"))
1168 ;; Return true if operand is an equality operator.
1169 (define_special_predicate "equality_operator"
1170 (match_code "eq,ne"))
1172 ;; Return true if operand is MIN or MAX operator.
1173 (define_predicate "min_max_operator"
1174 (match_code "smin,smax,umin,umax"))
1176 ;; Return 1 if OP is a comparison operation that is valid for a branch
1177 ;; instruction. We check the opcode against the mode of the CC value.
1178 ;; validate_condition_mode is an assertion.
1179 (define_predicate "branch_comparison_operator"
1180 (and (match_operand 0 "comparison_operator")
1181 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1182 (match_test "validate_condition_mode (GET_CODE (op),
1183 GET_MODE (XEXP (op, 0))),
1186 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1187 ;; If we're assuming that FP operations cannot generate user-visible traps,
1188 ;; then on e500 we can use the ordered-signaling instructions to implement
1189 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1190 (define_predicate "rs6000_cbranch_operator"
1191 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1192 (if_then_else (match_test "flag_trapping_math")
1193 (match_operand 0 "ordered_comparison_operator")
1194 (ior (match_operand 0 "ordered_comparison_operator")
1195 (match_code ("unlt,unle,ungt,unge"))))
1196 (match_operand 0 "comparison_operator")))
1198 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1199 ;; it must be a positive comparison.
1200 (define_predicate "scc_comparison_operator"
1201 (and (match_operand 0 "branch_comparison_operator")
1202 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1204 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1206 (define_predicate "scc_rev_comparison_operator"
1207 (and (match_operand 0 "branch_comparison_operator")
1208 (match_code "ne,le,ge,leu,geu,ordered")))
1210 ;; Return 1 if OP is a comparison operation that is valid for a branch
1211 ;; insn, which is true if the corresponding bit in the CC register is set.
1212 (define_predicate "branch_positive_comparison_operator"
1213 (and (match_operand 0 "branch_comparison_operator")
1214 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1216 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1217 (define_predicate "load_multiple_operation"
1218 (match_code "parallel")
1220 int count = XVECLEN (op, 0);
1221 unsigned int dest_regno;
1225 /* Perform a quick check so we don't blow up below. */
1227 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1228 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1229 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1232 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1233 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1235 for (i = 1; i < count; i++)
1237 rtx elt = XVECEXP (op, 0, i);
1239 if (GET_CODE (elt) != SET
1240 || GET_CODE (SET_DEST (elt)) != REG
1241 || GET_MODE (SET_DEST (elt)) != SImode
1242 || REGNO (SET_DEST (elt)) != dest_regno + i
1243 || GET_CODE (SET_SRC (elt)) != MEM
1244 || GET_MODE (SET_SRC (elt)) != SImode
1245 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1246 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1247 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1248 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1255 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1256 ;; The second vector element is a CLOBBER.
1257 (define_predicate "store_multiple_operation"
1258 (match_code "parallel")
1260 int count = XVECLEN (op, 0) - 1;
1261 unsigned int src_regno;
1265 /* Perform a quick check so we don't blow up below. */
1267 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1268 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1269 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1272 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1273 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1275 for (i = 1; i < count; i++)
1277 rtx elt = XVECEXP (op, 0, i + 1);
1279 if (GET_CODE (elt) != SET
1280 || GET_CODE (SET_SRC (elt)) != REG
1281 || GET_MODE (SET_SRC (elt)) != SImode
1282 || REGNO (SET_SRC (elt)) != src_regno + i
1283 || GET_CODE (SET_DEST (elt)) != MEM
1284 || GET_MODE (SET_DEST (elt)) != SImode
1285 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1286 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1287 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1288 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1295 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1297 (define_predicate "save_world_operation"
1298 (match_code "parallel")
1303 int count = XVECLEN (op, 0);
1309 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1310 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1313 for (i=1; i <= 18; i++)
1315 elt = XVECEXP (op, 0, index++);
1316 if (GET_CODE (elt) != SET
1317 || GET_CODE (SET_DEST (elt)) != MEM
1318 || ! memory_operand (SET_DEST (elt), DFmode)
1319 || GET_CODE (SET_SRC (elt)) != REG
1320 || GET_MODE (SET_SRC (elt)) != DFmode)
1324 for (i=1; i <= 12; i++)
1326 elt = XVECEXP (op, 0, index++);
1327 if (GET_CODE (elt) != SET
1328 || GET_CODE (SET_DEST (elt)) != MEM
1329 || GET_CODE (SET_SRC (elt)) != REG
1330 || GET_MODE (SET_SRC (elt)) != V4SImode)
1334 for (i=1; i <= 19; i++)
1336 elt = XVECEXP (op, 0, index++);
1337 if (GET_CODE (elt) != SET
1338 || GET_CODE (SET_DEST (elt)) != MEM
1339 || ! memory_operand (SET_DEST (elt), Pmode)
1340 || GET_CODE (SET_SRC (elt)) != REG
1341 || GET_MODE (SET_SRC (elt)) != Pmode)
1345 elt = XVECEXP (op, 0, index++);
1346 if (GET_CODE (elt) != SET
1347 || GET_CODE (SET_DEST (elt)) != MEM
1348 || ! memory_operand (SET_DEST (elt), Pmode)
1349 || GET_CODE (SET_SRC (elt)) != REG
1350 || REGNO (SET_SRC (elt)) != CR2_REGNO
1351 || GET_MODE (SET_SRC (elt)) != Pmode)
1354 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1355 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1360 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1362 (define_predicate "restore_world_operation"
1363 (match_code "parallel")
1368 int count = XVECLEN (op, 0);
1374 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1375 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1376 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1377 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1380 elt = XVECEXP (op, 0, index++);
1381 if (GET_CODE (elt) != SET
1382 || GET_CODE (SET_SRC (elt)) != MEM
1383 || ! memory_operand (SET_SRC (elt), Pmode)
1384 || GET_CODE (SET_DEST (elt)) != REG
1385 || REGNO (SET_DEST (elt)) != CR2_REGNO
1386 || GET_MODE (SET_DEST (elt)) != Pmode)
1389 for (i=1; i <= 19; i++)
1391 elt = XVECEXP (op, 0, index++);
1392 if (GET_CODE (elt) != SET
1393 || GET_CODE (SET_SRC (elt)) != MEM
1394 || ! memory_operand (SET_SRC (elt), Pmode)
1395 || GET_CODE (SET_DEST (elt)) != REG
1396 || GET_MODE (SET_DEST (elt)) != Pmode)
1400 for (i=1; i <= 12; i++)
1402 elt = XVECEXP (op, 0, index++);
1403 if (GET_CODE (elt) != SET
1404 || GET_CODE (SET_SRC (elt)) != MEM
1405 || GET_CODE (SET_DEST (elt)) != REG
1406 || GET_MODE (SET_DEST (elt)) != V4SImode)
1410 for (i=1; i <= 18; i++)
1412 elt = XVECEXP (op, 0, index++);
1413 if (GET_CODE (elt) != SET
1414 || GET_CODE (SET_SRC (elt)) != MEM
1415 || ! memory_operand (SET_SRC (elt), DFmode)
1416 || GET_CODE (SET_DEST (elt)) != REG
1417 || GET_MODE (SET_DEST (elt)) != DFmode)
1421 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1422 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1423 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1424 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1425 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1430 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1431 (define_predicate "vrsave_operation"
1432 (match_code "parallel")
1434 int count = XVECLEN (op, 0);
1435 unsigned int dest_regno, src_regno;
1439 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1440 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1441 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1442 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1445 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1446 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1448 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1451 for (i = 1; i < count; i++)
1453 rtx elt = XVECEXP (op, 0, i);
1455 if (GET_CODE (elt) != CLOBBER
1456 && GET_CODE (elt) != SET)
1463 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1464 (define_predicate "mfcr_operation"
1465 (match_code "parallel")
1467 int count = XVECLEN (op, 0);
1470 /* Perform a quick check so we don't blow up below. */
1472 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1473 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1474 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1477 for (i = 0; i < count; i++)
1479 rtx exp = XVECEXP (op, 0, i);
1484 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1486 if (GET_CODE (src_reg) != REG
1487 || GET_MODE (src_reg) != CCmode
1488 || ! CR_REGNO_P (REGNO (src_reg)))
1491 if (GET_CODE (exp) != SET
1492 || GET_CODE (SET_DEST (exp)) != REG
1493 || GET_MODE (SET_DEST (exp)) != SImode
1494 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1496 unspec = SET_SRC (exp);
1497 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1499 if (GET_CODE (unspec) != UNSPEC
1500 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1501 || XVECLEN (unspec, 0) != 2
1502 || XVECEXP (unspec, 0, 0) != src_reg
1503 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1504 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1510 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1511 (define_predicate "mtcrf_operation"
1512 (match_code "parallel")
1514 int count = XVECLEN (op, 0);
1518 /* Perform a quick check so we don't blow up below. */
1520 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1521 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1522 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1524 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1526 if (GET_CODE (src_reg) != REG
1527 || GET_MODE (src_reg) != SImode
1528 || ! INT_REGNO_P (REGNO (src_reg)))
1531 for (i = 0; i < count; i++)
1533 rtx exp = XVECEXP (op, 0, i);
1537 if (GET_CODE (exp) != SET
1538 || GET_CODE (SET_DEST (exp)) != REG
1539 || GET_MODE (SET_DEST (exp)) != CCmode
1540 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1542 unspec = SET_SRC (exp);
1543 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1545 if (GET_CODE (unspec) != UNSPEC
1546 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1547 || XVECLEN (unspec, 0) != 2
1548 || XVECEXP (unspec, 0, 0) != src_reg
1549 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1550 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1556 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1557 (define_predicate "crsave_operation"
1558 (match_code "parallel")
1560 int count = XVECLEN (op, 0);
1563 for (i = 1; i < count; i++)
1565 rtx exp = XVECEXP (op, 0, i);
1567 if (GET_CODE (exp) != USE
1568 || GET_CODE (XEXP (exp, 0)) != REG
1569 || GET_MODE (XEXP (exp, 0)) != CCmode
1570 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1576 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1577 (define_predicate "lmw_operation"
1578 (match_code "parallel")
1580 int count = XVECLEN (op, 0);
1581 unsigned int dest_regno;
1583 unsigned int base_regno;
1584 HOST_WIDE_INT offset;
1587 /* Perform a quick check so we don't blow up below. */
1589 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1590 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1591 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1594 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1595 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1598 || count != 32 - (int) dest_regno)
1601 if (legitimate_indirect_address_p (src_addr, 0))
1604 base_regno = REGNO (src_addr);
1605 if (base_regno == 0)
1608 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1610 offset = INTVAL (XEXP (src_addr, 1));
1611 base_regno = REGNO (XEXP (src_addr, 0));
1616 for (i = 0; i < count; i++)
1618 rtx elt = XVECEXP (op, 0, i);
1621 HOST_WIDE_INT newoffset;
1623 if (GET_CODE (elt) != SET
1624 || GET_CODE (SET_DEST (elt)) != REG
1625 || GET_MODE (SET_DEST (elt)) != SImode
1626 || REGNO (SET_DEST (elt)) != dest_regno + i
1627 || GET_CODE (SET_SRC (elt)) != MEM
1628 || GET_MODE (SET_SRC (elt)) != SImode)
1630 newaddr = XEXP (SET_SRC (elt), 0);
1631 if (legitimate_indirect_address_p (newaddr, 0))
1636 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1638 addr_reg = XEXP (newaddr, 0);
1639 newoffset = INTVAL (XEXP (newaddr, 1));
1643 if (REGNO (addr_reg) != base_regno
1644 || newoffset != offset + 4 * i)
1651 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1652 (define_predicate "stmw_operation"
1653 (match_code "parallel")
1655 int count = XVECLEN (op, 0);
1656 unsigned int src_regno;
1658 unsigned int base_regno;
1659 HOST_WIDE_INT offset;
1662 /* Perform a quick check so we don't blow up below. */
1664 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1665 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1666 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1669 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1670 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1673 || count != 32 - (int) src_regno)
1676 if (legitimate_indirect_address_p (dest_addr, 0))
1679 base_regno = REGNO (dest_addr);
1680 if (base_regno == 0)
1683 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1685 offset = INTVAL (XEXP (dest_addr, 1));
1686 base_regno = REGNO (XEXP (dest_addr, 0));
1691 for (i = 0; i < count; i++)
1693 rtx elt = XVECEXP (op, 0, i);
1696 HOST_WIDE_INT newoffset;
1698 if (GET_CODE (elt) != SET
1699 || GET_CODE (SET_SRC (elt)) != REG
1700 || GET_MODE (SET_SRC (elt)) != SImode
1701 || REGNO (SET_SRC (elt)) != src_regno + i
1702 || GET_CODE (SET_DEST (elt)) != MEM
1703 || GET_MODE (SET_DEST (elt)) != SImode)
1705 newaddr = XEXP (SET_DEST (elt), 0);
1706 if (legitimate_indirect_address_p (newaddr, 0))
1711 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1713 addr_reg = XEXP (newaddr, 0);
1714 newoffset = INTVAL (XEXP (newaddr, 1));
1718 if (REGNO (addr_reg) != base_regno
1719 || newoffset != offset + 4 * i)
1726 ;; Return 1 if OP is a stack tie operand.
1727 (define_predicate "tie_operand"
1728 (match_code "parallel")
1730 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1731 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1732 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1733 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1736 ;; Match a small code model toc reference (or medium and large
1737 ;; model toc references before reload).
1738 (define_predicate "small_toc_ref"
1739 (match_code "unspec,plus")
1741 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1744 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1747 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1748 ;; GPR registers on power8.
1749 (define_predicate "fusion_gpr_addis"
1750 (match_code "const_int,high,plus")
1752 HOST_WIDE_INT value;
1755 if (GET_CODE (op) == HIGH)
1758 if (CONST_INT_P (op))
1761 else if (GET_CODE (op) == PLUS
1762 && base_reg_operand (XEXP (op, 0), Pmode)
1763 && CONST_INT_P (XEXP (op, 1)))
1764 int_const = XEXP (op, 1);
1769 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1770 value are all 1's or 0's. */
1771 value = INTVAL (int_const);
1772 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1775 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1778 return (IN_RANGE (value >> 16, -32, 31));
1781 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1782 ;; and loads to GPR registers on power8.
1783 (define_predicate "fusion_gpr_mem_load"
1784 (match_code "mem,sign_extend,zero_extend")
1788 /* Handle sign/zero extend. */
1789 if (GET_CODE (op) == ZERO_EXTEND
1790 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1793 mode = GET_MODE (op);
1807 if (!TARGET_POWERPC64)
1815 addr = XEXP (op, 0);
1816 if (GET_CODE (addr) == PLUS)
1818 rtx base = XEXP (addr, 0);
1819 rtx offset = XEXP (addr, 1);
1821 return (base_reg_operand (base, GET_MODE (base))
1822 && satisfies_constraint_I (offset));
1825 else if (GET_CODE (addr) == LO_SUM)
1827 rtx base = XEXP (addr, 0);
1828 rtx offset = XEXP (addr, 1);
1830 if (!base_reg_operand (base, GET_MODE (base)))
1833 else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1834 return small_toc_ref (offset, GET_MODE (offset));
1836 else if (TARGET_ELF && !TARGET_POWERPC64)
1837 return CONSTANT_P (offset);