gcc/config/rs6000/power6.md

   1 ;; Scheduling description for IBM POWER6 processor.
   2 ;;   Copyright (C) 2006-2014 Free Software Foundation, Inc.
   3 ;;   Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Sources:
  22
  23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
  24 ;; (2 engines per chip).  The chip can issue up to 5 internal ops
  25 ;; per cycle.
  26
  27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu")
  28
  29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
  30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
  31 (define_cpu_unit "bpu_power6" "power6bu")
  32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
  33
  34 (define_reservation "LS2_power6"
  35                     "lsu1_power6+lsu2_power6")
  36
  37 (define_reservation "FPU_power6"
  38                     "fpu1_power6|fpu2_power6")
  39
  40 (define_reservation "BRU_power6"
  41                     "bpu_power6")
  42
  43 (define_reservation "LSU_power6"
  44                     "lsu1_power6|lsu2_power6")
  45
  46 (define_reservation "LSF_power6"
  47                     "(lsu1_power6+fpu1_power6)\
  48                     |(lsu1_power6+fpu2_power6)\
  49                     |(lsu2_power6+fpu1_power6)\
  50                     |(lsu2_power6+fpu2_power6)")
  51
  52 (define_reservation "LX2_power6"
  53                     "(iu1_power6+iu2_power6+lsu1_power6)\
  54                     |(iu1_power6+iu2_power6+lsu2_power6)")
  55
  56 (define_reservation "FX2_power6"
  57                     "iu1_power6+iu2_power6")
  58
  59 (define_reservation "X2F_power6"
  60                     "(iu1_power6+iu2_power6+fpu1_power6)\
  61                     |(iu1_power6+iu2_power6+fpu2_power6)")
  62
  63 (define_reservation "BX2_power6"
  64                     "iu1_power6+iu2_power6+bpu_power6")
  65
  66 (define_reservation "LSX_power6"
  67                     "(iu1_power6+lsu1_power6)\
  68                     |(iu1_power6+lsu2_power6)\
  69                     |(iu2_power6+lsu1_power6)\
  70                     |(iu2_power6+lsu2_power6)")
  71
  72 (define_reservation "FXU_power6"
  73                     "iu1_power6|iu2_power6")
  74
  75 (define_reservation "XLF_power6"
  76                     "(iu1_power6+lsu1_power6+fpu1_power6)\
  77                     |(iu1_power6+lsu1_power6+fpu2_power6)\
  78                     |(iu1_power6+lsu2_power6+fpu1_power6)\
  79                     |(iu1_power6+lsu2_power6+fpu2_power6)\
  80                     |(iu2_power6+lsu1_power6+fpu1_power6)\
  81                     |(iu2_power6+lsu1_power6+fpu2_power6)\
  82                     |(iu2_power6+lsu2_power6+fpu1_power6)\
  83                     |(iu2_power6+lsu2_power6+fpu2_power6)")
  84
  85 (define_reservation "BRX_power6"
  86                     "(bpu_power6+iu1_power6)\
  87                     |(bpu_power6+iu2_power6)")
  88
  89 ; Load/store
  90
  91 ; The default for a value written by a fixed point load
  92 ; that is read/written by a subsequent fixed point op.
  93 (define_insn_reservation "power6-load" 2 ; fx
  94   (and (eq_attr "type" "load")
  95        (eq_attr "cpu" "power6"))
  96   "LSU_power6")
  97
  98 ; define the bypass for the case where the value written
  99 ; by a fixed point load is used as the source value on
 100 ; a store.
 101 (define_bypass 1 "power6-load,\
 102                   power6-load-update,\
 103                   power6-load-update-indexed"
 104                  "power6-store,\
 105                   power6-store-update,\
 106                   power6-store-update-indexed,\
 107                   power6-fpstore,\
 108                   power6-fpstore-update"
 109   "store_data_bypass_p")
 110
 111 (define_insn_reservation "power6-load-ext" 4 ; fx
 112   (and (eq_attr "type" "load_ext")
 113        (eq_attr "cpu" "power6"))
 114   "LSU_power6")
 115
 116 ; define the bypass for the case where the value written
 117 ; by a fixed point load ext is used as the source value on
 118 ; a store.
 119 (define_bypass 1 "power6-load-ext,\
 120                   power6-load-ext-update,\
 121                   power6-load-ext-update-indexed"
 122                  "power6-store,\
 123                   power6-store-update,\
 124                   power6-store-update-indexed,\
 125                   power6-fpstore,\
 126                   power6-fpstore-update"
 127   "store_data_bypass_p")
 128
 129 (define_insn_reservation "power6-load-update" 2 ; fx
 130   (and (eq_attr "type" "load_u")
 131        (eq_attr "cpu" "power6"))
 132   "LSX_power6")
 133
 134 (define_insn_reservation "power6-load-update-indexed" 2 ; fx
 135   (and (eq_attr "type" "load_ux")
 136        (eq_attr "cpu" "power6"))
 137   "LSX_power6")
 138
 139 (define_insn_reservation "power6-load-ext-update" 4 ; fx
 140   (and (eq_attr "type" "load_ext_u")
 141        (eq_attr "cpu" "power6"))
 142   "LSX_power6")
 143
 144 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
 145   (and (eq_attr "type" "load_ext_ux")
 146        (eq_attr "cpu" "power6"))
 147   "LSX_power6")
 148
 149 (define_insn_reservation "power6-fpload" 1
 150   (and (eq_attr "type" "fpload")
 151        (eq_attr "cpu" "power6"))
 152   "LSU_power6")
 153
 154 (define_insn_reservation "power6-fpload-update" 1
 155   (and (eq_attr "type" "fpload_u,fpload_ux")
 156        (eq_attr "cpu" "power6"))
 157   "LSX_power6")
 158
 159 (define_insn_reservation "power6-store" 14
 160   (and (eq_attr "type" "store")
 161        (eq_attr "cpu" "power6"))
 162   "LSU_power6")
 163
 164 (define_insn_reservation "power6-store-update" 14
 165   (and (eq_attr "type" "store_u")
 166        (eq_attr "cpu" "power6"))
 167   "LSX_power6")
 168
 169 (define_insn_reservation "power6-store-update-indexed" 14
 170   (and (eq_attr "type" "store_ux")
 171        (eq_attr "cpu" "power6"))
 172   "LX2_power6")
 173
 174 (define_insn_reservation "power6-fpstore" 14
 175   (and (eq_attr "type" "fpstore")
 176        (eq_attr "cpu" "power6"))
 177   "LSF_power6")
 178
 179 (define_insn_reservation "power6-fpstore-update" 14
 180   (and (eq_attr "type" "fpstore_u,fpstore_ux")
 181        (eq_attr "cpu" "power6"))
 182   "XLF_power6")
 183
 184 (define_insn_reservation "power6-larx" 3
 185   (and (eq_attr "type" "load_l")
 186        (eq_attr "cpu" "power6"))
 187   "LS2_power6")
 188
 189 (define_insn_reservation "power6-stcx" 10 ; best case
 190   (and (eq_attr "type" "store_c")
 191        (eq_attr "cpu" "power6"))
 192   "LSX_power6")
 193
 194 (define_insn_reservation "power6-sync" 11 ; N/A
 195   (and (eq_attr "type" "sync")
 196        (eq_attr "cpu" "power6"))
 197   "LSU_power6")
 198
 199 (define_insn_reservation "power6-integer" 1
 200   (and (eq_attr "type" "integer")
 201        (eq_attr "cpu" "power6"))
 202   "FXU_power6")
 203
 204 (define_insn_reservation "power6-isel" 1
 205   (and (eq_attr "type" "isel")
 206        (eq_attr "cpu" "power6"))
 207   "FXU_power6")
 208
 209 (define_insn_reservation "power6-exts" 1
 210   (and (eq_attr "type" "exts")
 211        (eq_attr "cpu" "power6"))
 212   "FXU_power6")
 213
 214 (define_insn_reservation "power6-shift" 1
 215   (and (eq_attr "type" "shift")
 216        (eq_attr "cpu" "power6"))
 217   "FXU_power6")
 218
 219 (define_insn_reservation "power6-popcnt" 1
 220   (and (eq_attr "type" "popcnt")
 221        (eq_attr "cpu" "power6"))
 222   "FXU_power6")
 223
 224 (define_insn_reservation "power6-insert" 1
 225   (and (eq_attr "type" "insert_word")
 226        (eq_attr "cpu" "power6"))
 227   "FX2_power6")
 228
 229 (define_insn_reservation "power6-insert-dword" 1
 230   (and (eq_attr "type" "insert_dword")
 231        (eq_attr "cpu" "power6"))
 232   "FX2_power6")
 233
 234 ; define the bypass for the case where the value written
 235 ; by a fixed point op is used as the source value on a
 236 ; store.
 237 (define_bypass 1 "power6-integer,\
 238                   power6-exts,\
 239                   power6-shift,\
 240                   power6-insert,\
 241                   power6-insert-dword"
 242                  "power6-store,\
 243                   power6-store-update,\
 244                   power6-store-update-indexed,\
 245                   power6-fpstore,\
 246                   power6-fpstore-update"
 247   "store_data_bypass_p")
 248
 249 (define_insn_reservation "power6-cntlz" 2
 250   (and (eq_attr "type" "cntlz")
 251        (eq_attr "cpu" "power6"))
 252   "FXU_power6")
 253
 254 (define_bypass 1 "power6-cntlz"
 255                  "power6-store,\
 256                   power6-store-update,\
 257                   power6-store-update-indexed,\
 258                   power6-fpstore,\
 259                   power6-fpstore-update"
 260   "store_data_bypass_p")
 261
 262 (define_insn_reservation "power6-var-rotate" 4
 263   (and (eq_attr "type" "var_shift_rotate")
 264        (eq_attr "cpu" "power6"))
 265   "FXU_power6")
 266
 267 (define_insn_reservation "power6-trap" 1 ; N/A
 268   (and (eq_attr "type" "trap")
 269        (eq_attr "cpu" "power6"))
 270   "BRX_power6")
 271
 272 (define_insn_reservation "power6-two" 1
 273   (and (eq_attr "type" "two")
 274        (eq_attr "cpu" "power6"))
 275   "(iu1_power6,iu1_power6)\
 276   |(iu1_power6+iu2_power6,nothing)\
 277   |(iu1_power6,iu2_power6)\
 278   |(iu2_power6,iu1_power6)\
 279   |(iu2_power6,iu2_power6)")
 280
 281 (define_insn_reservation "power6-three" 1
 282   (and (eq_attr "type" "three")
 283        (eq_attr "cpu" "power6"))
 284   "(iu1_power6,iu1_power6,iu1_power6)\
 285   |(iu1_power6,iu1_power6,iu2_power6)\
 286   |(iu1_power6,iu2_power6,iu1_power6)\
 287   |(iu1_power6,iu2_power6,iu2_power6)\
 288   |(iu2_power6,iu1_power6,iu1_power6)\
 289   |(iu2_power6,iu1_power6,iu2_power6)\
 290   |(iu2_power6,iu2_power6,iu1_power6)\
 291   |(iu2_power6,iu2_power6,iu2_power6)\
 292   |(iu1_power6+iu2_power6,iu1_power6)\
 293   |(iu1_power6+iu2_power6,iu2_power6)\
 294   |(iu1_power6,iu1_power6+iu2_power6)\
 295   |(iu2_power6,iu1_power6+iu2_power6)")
 296
 297 (define_insn_reservation "power6-cmp" 1
 298   (and (eq_attr "type" "cmp")
 299        (eq_attr "cpu" "power6"))
 300   "FXU_power6")
 301
 302 (define_insn_reservation "power6-compare" 1
 303   (and (eq_attr "type" "compare")
 304        (eq_attr "cpu" "power6"))
 305   "FXU_power6")
 306
 307 (define_insn_reservation "power6-fast-compare" 1
 308   (and (eq_attr "type" "fast_compare")
 309        (eq_attr "cpu" "power6"))
 310   "FXU_power6")
 311
 312 ; define the bypass for the case where the value written
 313 ; by a fixed point rec form op is used as the source value
 314 ; on a store.
 315 (define_bypass 1 "power6-compare,\
 316                   power6-fast-compare"
 317                  "power6-store,\
 318                   power6-store-update,\
 319                   power6-store-update-indexed,\
 320                   power6-fpstore,\
 321                   power6-fpstore-update"
 322   "store_data_bypass_p")
 323
 324 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
 325   (and (eq_attr "type" "delayed_compare")
 326        (eq_attr "cpu" "power6"))
 327   "FXU_power6")
 328
 329 (define_insn_reservation "power6-var-delayed-compare" 4
 330   (and (eq_attr "type" "var_delayed_compare")
 331        (eq_attr "cpu" "power6"))
 332   "FXU_power6")
 333
 334 (define_insn_reservation "power6-lmul-cmp" 16
 335   (and (eq_attr "type" "lmul_compare")
 336        (eq_attr "cpu" "power6"))
 337   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 338   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 339
 340 (define_insn_reservation "power6-imul-cmp" 16
 341   (and (eq_attr "type" "imul_compare")
 342        (eq_attr "cpu" "power6"))
 343   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 344   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 345
 346 (define_insn_reservation "power6-lmul" 16
 347   (and (eq_attr "type" "lmul")
 348        (eq_attr "cpu" "power6"))
 349   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 350   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 351
 352 (define_insn_reservation "power6-imul" 16
 353   (and (eq_attr "type" "imul")
 354        (eq_attr "cpu" "power6"))
 355   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 356   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 357
 358 (define_insn_reservation "power6-imul3" 16
 359   (and (eq_attr "type" "imul2,imul3")
 360        (eq_attr "cpu" "power6"))
 361   "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
 362   |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
 363
 364 (define_bypass 9 "power6-imul,\
 365                   power6-lmul,\
 366                   power6-imul-cmp,\
 367                   power6-lmul-cmp,\
 368                   power6-imul3"
 369                  "power6-store,\
 370                   power6-store-update,\
 371                   power6-store-update-indexed,\
 372                   power6-fpstore,\
 373                   power6-fpstore-update"
 374   "store_data_bypass_p")
 375
 376 (define_insn_reservation "power6-idiv" 44
 377   (and (eq_attr "type" "idiv")
 378        (eq_attr "cpu" "power6"))
 379   "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
 380   |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
 381
 382 ; The latency for this bypass is yet to be defined
 383 ;(define_bypass ? "power6-idiv"
 384 ;                 "power6-store,\
 385 ;                  power6-store-update,\
 386 ;                  power6-store-update-indexed,\
 387 ;                  power6-fpstore,\
 388 ;                  power6-fpstore-update"
 389 ;  "store_data_bypass_p")
 390
 391 (define_insn_reservation "power6-ldiv" 56
 392   (and (eq_attr "type" "ldiv")
 393        (eq_attr "cpu" "power6"))
 394   "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
 395   |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
 396
 397 ; The latency for this bypass is yet to be defined
 398 ;(define_bypass ? "power6-ldiv"
 399 ;                 "power6-store,\
 400 ;                  power6-store-update,\
 401 ;                  power6-store-update-indexed,\
 402 ;                  power6-fpstore,\
 403 ;                  power6-fpstore-update"
 404 ;  "store_data_bypass_p")
 405
 406 (define_insn_reservation "power6-mtjmpr" 2
 407   (and (eq_attr "type" "mtjmpr,mfjmpr")
 408        (eq_attr "cpu" "power6"))
 409   "BX2_power6")
 410
 411 (define_bypass 5 "power6-mtjmpr" "power6-branch")
 412
 413 (define_insn_reservation "power6-branch" 2
 414   (and (eq_attr "type" "jmpreg,branch")
 415        (eq_attr "cpu" "power6"))
 416   "BRU_power6")
 417
 418 (define_bypass 5 "power6-branch" "power6-mtjmpr")
 419
 420 (define_insn_reservation "power6-crlogical" 3
 421   (and (eq_attr "type" "cr_logical")
 422        (eq_attr "cpu" "power6"))
 423   "BRU_power6")
 424
 425 (define_bypass 3 "power6-crlogical" "power6-branch")
 426
 427 (define_insn_reservation "power6-delayedcr" 3
 428   (and (eq_attr "type" "delayed_cr")
 429        (eq_attr "cpu" "power6"))
 430   "BRU_power6")
 431
 432 (define_insn_reservation "power6-mfcr" 6 ; N/A
 433   (and (eq_attr "type" "mfcr")
 434        (eq_attr "cpu" "power6"))
 435   "BX2_power6")
 436
 437 ; mfcrf (1 field)
 438 (define_insn_reservation "power6-mfcrf" 3 ; N/A
 439   (and (eq_attr "type" "mfcrf")
 440        (eq_attr "cpu" "power6"))
 441   "BX2_power6") ;
 442
 443 ; mtcrf (1 field)
 444 (define_insn_reservation "power6-mtcr" 4 ; N/A
 445   (and (eq_attr "type" "mtcr")
 446        (eq_attr "cpu" "power6"))
 447   "BX2_power6")
 448
 449 (define_bypass 9 "power6-mtcr" "power6-branch")
 450
 451 (define_insn_reservation "power6-fp" 6
 452   (and (eq_attr "type" "fp,dmul")
 453        (eq_attr "cpu" "power6"))
 454   "FPU_power6")
 455
 456 ; Any fp instruction that updates a CR has a latency
 457 ; of 6 to a dependent branch
 458 (define_bypass 6 "power6-fp" "power6-branch")
 459
 460 (define_bypass 1 "power6-fp"
 461                  "power6-fpstore,power6-fpstore-update"
 462   "store_data_bypass_p")
 463
 464 (define_insn_reservation "power6-fpcompare" 8
 465   (and (eq_attr "type" "fpcompare")
 466        (eq_attr "cpu" "power6"))
 467   "FPU_power6")
 468
 469 (define_bypass 12 "power6-fpcompare"
 470                   "power6-branch,power6-crlogical")
 471
 472 (define_insn_reservation "power6-sdiv" 26
 473   (and (eq_attr "type" "sdiv")
 474        (eq_attr "cpu" "power6"))
 475   "FPU_power6")
 476
 477 (define_insn_reservation "power6-ddiv" 32
 478   (and (eq_attr "type" "ddiv")
 479        (eq_attr "cpu" "power6"))
 480   "FPU_power6")
 481
 482 (define_insn_reservation "power6-sqrt" 30
 483   (and (eq_attr "type" "ssqrt")
 484        (eq_attr "cpu" "power6"))
 485   "FPU_power6")
 486
 487 (define_insn_reservation "power6-dsqrt" 42
 488   (and (eq_attr "type" "dsqrt")
 489        (eq_attr "cpu" "power6"))
 490   "FPU_power6")
 491
 492 (define_insn_reservation "power6-isync" 2 ; N/A
 493   (and (eq_attr "type" "isync")
 494        (eq_attr "cpu" "power6"))
 495   "FXU_power6")
 496
 497 (define_insn_reservation "power6-vecload" 1
 498   (and (eq_attr "type" "vecload")
 499        (eq_attr "cpu" "power6"))
 500   "LSU_power6")
 501
 502 (define_insn_reservation "power6-vecstore" 1
 503   (and (eq_attr "type" "vecstore")
 504        (eq_attr "cpu" "power6"))
 505   "LSF_power6")
 506
 507 (define_insn_reservation "power6-vecsimple" 3
 508   (and (eq_attr "type" "vecsimple")
 509        (eq_attr "cpu" "power6"))
 510   "FPU_power6")
 511
 512 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
 513                                      power6-vecperm")
 514
 515 (define_bypass 5 "power6-vecsimple" "power6-vecfloat")
 516
 517 (define_bypass 4 "power6-vecsimple" "power6-vecstore" )
 518
 519 (define_insn_reservation "power6-veccmp" 1
 520   (and (eq_attr "type" "veccmp")
 521        (eq_attr "cpu" "power6"))
 522   "FPU_power6")
 523
 524 (define_bypass 10 "power6-veccmp" "power6-branch")
 525
 526 (define_insn_reservation "power6-vecfloat" 7
 527   (and (eq_attr "type" "vecfloat")
 528        (eq_attr "cpu" "power6"))
 529   "FPU_power6")
 530
 531 (define_bypass 10 "power6-vecfloat" "power6-vecsimple")
 532
 533 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
 534                                      power6-vecperm")
 535
 536 (define_bypass 9 "power6-vecfloat" "power6-vecstore" )
 537
 538 (define_insn_reservation "power6-veccomplex" 7
 539   (and (eq_attr "type" "vecsimple")
 540        (eq_attr "cpu" "power6"))
 541   "FPU_power6")
 542
 543 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
 544                                        power6-vecfloat" )
 545
 546 (define_bypass 9 "power6-veccomplex" "power6-vecperm" )
 547
 548 (define_bypass 8 "power6-veccomplex" "power6-vecstore" )
 549
 550 (define_insn_reservation "power6-vecperm" 4
 551   (and (eq_attr "type" "vecperm")
 552        (eq_attr "cpu" "power6"))
 553   "FPU_power6")
 554
 555 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\
 556                                    power6-vecfloat" )
 557
 558 (define_bypass 6 "power6-vecperm" "power6-veccomplex" )
 559
 560 (define_bypass 5 "power6-vecperm" "power6-vecstore" )
 561
 562 (define_insn_reservation "power6-mftgpr" 8
 563   (and (eq_attr "type" "mftgpr")
 564        (eq_attr "cpu" "power6"))
 565   "X2F_power6")
 566
 567 (define_insn_reservation "power6-mffgpr" 14
 568   (and (eq_attr "type" "mffgpr")
 569        (eq_attr "cpu" "power6"))
 570   "LX2_power6")
 571
 572 (define_bypass 4 "power6-mftgpr" "power6-imul,\
 573                                   power6-lmul,\
 574                                   power6-imul-cmp,\
 575                                   power6-lmul-cmp,\
 576                                   power6-imul3,\
 577                                   power6-idiv,\
 578                                   power6-ldiv" )