| blob | 4e965487d7ea25ecf3228e22ae2075c095496961 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 ])
55 ;;
56 ;; UNSPEC_VOLATILE usage
57 ;;
59 (define_constants
60 [(UNSPECV_BLOCK 0)
61 (UNSPECV_EH_RR 9) ; eh_reg_restore
62 ])
63 \f
64 ;; Define an insn type attribute. This is used in function unit delay
65 ;; computations.
66 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
67 (const_string "integer"))
69 ;; Length (in bytes).
70 ; '(pc)' in the following doesn't include the instruction itself; it is
71 ; calculated as if the instruction had zero size.
72 (define_attr "length" ""
73 (if_then_else (eq_attr "type" "branch")
74 (if_then_else (and (ge (minus (match_dup 0) (pc))
75 (const_int -32768))
76 (lt (minus (match_dup 0) (pc))
77 (const_int 32764)))
78 (const_int 4)
79 (const_int 8))
80 (const_int 4)))
82 ;; Processor type -- this attribute must exactly match the processor_type
83 ;; enumeration in rs6000.h.
85 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
86 (const (symbol_ref "rs6000_cpu_attr")))
88 (automata_option "ndfa")
90 (include "rios1.md")
91 (include "rios2.md")
92 (include "rs64.md")
93 (include "mpc.md")
94 (include "40x.md")
95 (include "440.md")
96 (include "603.md")
97 (include "6xx.md")
98 (include "7xx.md")
99 (include "7450.md")
100 (include "8540.md")
101 (include "power4.md")
102 (include "power5.md")
104 \f
105 ;; Start with fixed-point load and store insns. Here we put only the more
106 ;; complex forms. Basic data transfer is done later.
108 (define_expand "zero_extendqidi2"
109 [(set (match_operand:DI 0 "gpc_reg_operand" "")
110 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
111 "TARGET_POWERPC64"
112 "")
114 (define_insn ""
115 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
116 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
117 "TARGET_POWERPC64"
118 "@
119 lbz%U1%X1 %0,%1
120 rldicl %0,%1,0,56"
121 [(set_attr "type" "load,*")])
123 (define_insn ""
124 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
125 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
126 (const_int 0)))
127 (clobber (match_scratch:DI 2 "=r,r"))]
128 "TARGET_64BIT"
129 "@
130 rldicl. %2,%1,0,56
131 #"
132 [(set_attr "type" "compare")
133 (set_attr "length" "4,8")])
135 (define_split
136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
137 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
138 (const_int 0)))
139 (clobber (match_scratch:DI 2 ""))]
140 "TARGET_POWERPC64 && reload_completed"
141 [(set (match_dup 2)
142 (zero_extend:DI (match_dup 1)))
143 (set (match_dup 0)
144 (compare:CC (match_dup 2)
145 (const_int 0)))]
146 "")
148 (define_insn ""
149 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
150 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
151 (const_int 0)))
152 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
153 (zero_extend:DI (match_dup 1)))]
154 "TARGET_64BIT"
155 "@
156 rldicl. %0,%1,0,56
157 #"
158 [(set_attr "type" "compare")
159 (set_attr "length" "4,8")])
161 (define_split
162 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
163 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
164 (const_int 0)))
165 (set (match_operand:DI 0 "gpc_reg_operand" "")
166 (zero_extend:DI (match_dup 1)))]
167 "TARGET_POWERPC64 && reload_completed"
168 [(set (match_dup 0)
169 (zero_extend:DI (match_dup 1)))
170 (set (match_dup 2)
171 (compare:CC (match_dup 0)
172 (const_int 0)))]
173 "")
175 (define_insn "extendqidi2"
176 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
177 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
178 "TARGET_POWERPC64"
179 "extsb %0,%1")
181 (define_insn ""
182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
183 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
184 (const_int 0)))
185 (clobber (match_scratch:DI 2 "=r,r"))]
186 "TARGET_64BIT"
187 "@
188 extsb. %2,%1
189 #"
190 [(set_attr "type" "compare")
191 (set_attr "length" "4,8")])
193 (define_split
194 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
195 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
196 (const_int 0)))
197 (clobber (match_scratch:DI 2 ""))]
198 "TARGET_POWERPC64 && reload_completed"
199 [(set (match_dup 2)
200 (sign_extend:DI (match_dup 1)))
201 (set (match_dup 0)
202 (compare:CC (match_dup 2)
203 (const_int 0)))]
204 "")
206 (define_insn ""
207 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
208 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
209 (const_int 0)))
210 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
211 (sign_extend:DI (match_dup 1)))]
212 "TARGET_64BIT"
213 "@
214 extsb. %0,%1
215 #"
216 [(set_attr "type" "compare")
217 (set_attr "length" "4,8")])
219 (define_split
220 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
221 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
222 (const_int 0)))
223 (set (match_operand:DI 0 "gpc_reg_operand" "")
224 (sign_extend:DI (match_dup 1)))]
225 "TARGET_POWERPC64 && reload_completed"
226 [(set (match_dup 0)
227 (sign_extend:DI (match_dup 1)))
228 (set (match_dup 2)
229 (compare:CC (match_dup 0)
230 (const_int 0)))]
231 "")
233 (define_expand "zero_extendhidi2"
234 [(set (match_operand:DI 0 "gpc_reg_operand" "")
235 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
236 "TARGET_POWERPC64"
237 "")
239 (define_insn ""
240 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
241 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
242 "TARGET_POWERPC64"
243 "@
244 lhz%U1%X1 %0,%1
245 rldicl %0,%1,0,48"
246 [(set_attr "type" "load,*")])
248 (define_insn ""
249 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
250 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
251 (const_int 0)))
252 (clobber (match_scratch:DI 2 "=r,r"))]
253 "TARGET_64BIT"
254 "@
255 rldicl. %2,%1,0,48
256 #"
257 [(set_attr "type" "compare")
258 (set_attr "length" "4,8")])
260 (define_split
261 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
262 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
263 (const_int 0)))
264 (clobber (match_scratch:DI 2 ""))]
265 "TARGET_POWERPC64 && reload_completed"
266 [(set (match_dup 2)
267 (zero_extend:DI (match_dup 1)))
268 (set (match_dup 0)
269 (compare:CC (match_dup 2)
270 (const_int 0)))]
271 "")
273 (define_insn ""
274 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
275 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
276 (const_int 0)))
277 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
278 (zero_extend:DI (match_dup 1)))]
279 "TARGET_64BIT"
280 "@
281 rldicl. %0,%1,0,48
282 #"
283 [(set_attr "type" "compare")
284 (set_attr "length" "4,8")])
286 (define_split
287 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
288 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
289 (const_int 0)))
290 (set (match_operand:DI 0 "gpc_reg_operand" "")
291 (zero_extend:DI (match_dup 1)))]
292 "TARGET_POWERPC64 && reload_completed"
293 [(set (match_dup 0)
294 (zero_extend:DI (match_dup 1)))
295 (set (match_dup 2)
296 (compare:CC (match_dup 0)
297 (const_int 0)))]
298 "")
300 (define_expand "extendhidi2"
301 [(set (match_operand:DI 0 "gpc_reg_operand" "")
302 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
303 "TARGET_POWERPC64"
304 "")
306 (define_insn ""
307 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
308 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
309 "TARGET_POWERPC64"
310 "@
311 lha%U1%X1 %0,%1
312 extsh %0,%1"
313 [(set_attr "type" "load_ext,*")])
315 (define_insn ""
316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
317 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
318 (const_int 0)))
319 (clobber (match_scratch:DI 2 "=r,r"))]
320 "TARGET_64BIT"
321 "@
322 extsh. %2,%1
323 #"
324 [(set_attr "type" "compare")
325 (set_attr "length" "4,8")])
327 (define_split
328 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
329 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
330 (const_int 0)))
331 (clobber (match_scratch:DI 2 ""))]
332 "TARGET_POWERPC64 && reload_completed"
333 [(set (match_dup 2)
334 (sign_extend:DI (match_dup 1)))
335 (set (match_dup 0)
336 (compare:CC (match_dup 2)
337 (const_int 0)))]
338 "")
340 (define_insn ""
341 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
342 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
343 (const_int 0)))
344 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
345 (sign_extend:DI (match_dup 1)))]
346 "TARGET_64BIT"
347 "@
348 extsh. %0,%1
349 #"
350 [(set_attr "type" "compare")
351 (set_attr "length" "4,8")])
353 (define_split
354 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
355 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
356 (const_int 0)))
357 (set (match_operand:DI 0 "gpc_reg_operand" "")
358 (sign_extend:DI (match_dup 1)))]
359 "TARGET_POWERPC64 && reload_completed"
360 [(set (match_dup 0)
361 (sign_extend:DI (match_dup 1)))
362 (set (match_dup 2)
363 (compare:CC (match_dup 0)
364 (const_int 0)))]
365 "")
367 (define_expand "zero_extendsidi2"
368 [(set (match_operand:DI 0 "gpc_reg_operand" "")
369 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
370 "TARGET_POWERPC64"
371 "")
373 (define_insn ""
374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
375 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
376 "TARGET_POWERPC64"
377 "@
378 lwz%U1%X1 %0,%1
379 rldicl %0,%1,0,32"
380 [(set_attr "type" "load,*")])
382 (define_insn ""
383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
384 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
385 (const_int 0)))
386 (clobber (match_scratch:DI 2 "=r,r"))]
387 "TARGET_64BIT"
388 "@
389 rldicl. %2,%1,0,32
390 #"
391 [(set_attr "type" "compare")
392 (set_attr "length" "4,8")])
394 (define_split
395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
396 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
397 (const_int 0)))
398 (clobber (match_scratch:DI 2 ""))]
399 "TARGET_POWERPC64 && reload_completed"
400 [(set (match_dup 2)
401 (zero_extend:DI (match_dup 1)))
402 (set (match_dup 0)
403 (compare:CC (match_dup 2)
404 (const_int 0)))]
405 "")
407 (define_insn ""
408 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
409 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
410 (const_int 0)))
411 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
412 (zero_extend:DI (match_dup 1)))]
413 "TARGET_64BIT"
414 "@
415 rldicl. %0,%1,0,32
416 #"
417 [(set_attr "type" "compare")
418 (set_attr "length" "4,8")])
420 (define_split
421 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
422 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
423 (const_int 0)))
424 (set (match_operand:DI 0 "gpc_reg_operand" "")
425 (zero_extend:DI (match_dup 1)))]
426 "TARGET_POWERPC64 && reload_completed"
427 [(set (match_dup 0)
428 (zero_extend:DI (match_dup 1)))
429 (set (match_dup 2)
430 (compare:CC (match_dup 0)
431 (const_int 0)))]
432 "")
434 (define_expand "extendsidi2"
435 [(set (match_operand:DI 0 "gpc_reg_operand" "")
436 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
437 "TARGET_POWERPC64"
438 "")
440 (define_insn ""
441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
442 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
443 "TARGET_POWERPC64"
444 "@
445 lwa%U1%X1 %0,%1
446 extsw %0,%1"
447 [(set_attr "type" "load_ext,*")])
449 (define_insn ""
450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
451 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
452 (const_int 0)))
453 (clobber (match_scratch:DI 2 "=r,r"))]
454 "TARGET_64BIT"
455 "@
456 extsw. %2,%1
457 #"
458 [(set_attr "type" "compare")
459 (set_attr "length" "4,8")])
461 (define_split
462 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
463 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
464 (const_int 0)))
465 (clobber (match_scratch:DI 2 ""))]
466 "TARGET_POWERPC64 && reload_completed"
467 [(set (match_dup 2)
468 (sign_extend:DI (match_dup 1)))
469 (set (match_dup 0)
470 (compare:CC (match_dup 2)
471 (const_int 0)))]
472 "")
474 (define_insn ""
475 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
476 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
477 (const_int 0)))
478 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
479 (sign_extend:DI (match_dup 1)))]
480 "TARGET_64BIT"
481 "@
482 extsw. %0,%1
483 #"
484 [(set_attr "type" "compare")
485 (set_attr "length" "4,8")])
487 (define_split
488 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
489 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
490 (const_int 0)))
491 (set (match_operand:DI 0 "gpc_reg_operand" "")
492 (sign_extend:DI (match_dup 1)))]
493 "TARGET_POWERPC64 && reload_completed"
494 [(set (match_dup 0)
495 (sign_extend:DI (match_dup 1)))
496 (set (match_dup 2)
497 (compare:CC (match_dup 0)
498 (const_int 0)))]
499 "")
501 (define_expand "zero_extendqisi2"
502 [(set (match_operand:SI 0 "gpc_reg_operand" "")
503 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
504 ""
505 "")
507 (define_insn ""
508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
509 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
510 ""
511 "@
512 lbz%U1%X1 %0,%1
513 {rlinm|rlwinm} %0,%1,0,0xff"
514 [(set_attr "type" "load,*")])
516 (define_insn ""
517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
518 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
519 (const_int 0)))
520 (clobber (match_scratch:SI 2 "=r,r"))]
521 ""
522 "@
523 {andil.|andi.} %2,%1,0xff
524 #"
525 [(set_attr "type" "compare")
526 (set_attr "length" "4,8")])
528 (define_split
529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
530 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
531 (const_int 0)))
532 (clobber (match_scratch:SI 2 ""))]
533 "reload_completed"
534 [(set (match_dup 2)
535 (zero_extend:SI (match_dup 1)))
536 (set (match_dup 0)
537 (compare:CC (match_dup 2)
538 (const_int 0)))]
539 "")
541 (define_insn ""
542 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
543 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
544 (const_int 0)))
545 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
546 (zero_extend:SI (match_dup 1)))]
547 ""
548 "@
549 {andil.|andi.} %0,%1,0xff
550 #"
551 [(set_attr "type" "compare")
552 (set_attr "length" "4,8")])
554 (define_split
555 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
556 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
557 (const_int 0)))
558 (set (match_operand:SI 0 "gpc_reg_operand" "")
559 (zero_extend:SI (match_dup 1)))]
560 "reload_completed"
561 [(set (match_dup 0)
562 (zero_extend:SI (match_dup 1)))
563 (set (match_dup 2)
564 (compare:CC (match_dup 0)
565 (const_int 0)))]
566 "")
568 (define_expand "extendqisi2"
569 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
570 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
571 ""
572 "
573 {
574 if (TARGET_POWERPC)
575 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
576 else if (TARGET_POWER)
577 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
578 else
579 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
580 DONE;
581 }")
583 (define_insn "extendqisi2_ppc"
584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
585 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
586 "TARGET_POWERPC"
587 "extsb %0,%1")
589 (define_insn ""
590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
591 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
592 (const_int 0)))
593 (clobber (match_scratch:SI 2 "=r,r"))]
594 "TARGET_POWERPC"
595 "@
596 extsb. %2,%1
597 #"
598 [(set_attr "type" "compare")
599 (set_attr "length" "4,8")])
601 (define_split
602 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
603 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
604 (const_int 0)))
605 (clobber (match_scratch:SI 2 ""))]
606 "TARGET_POWERPC && reload_completed"
607 [(set (match_dup 2)
608 (sign_extend:SI (match_dup 1)))
609 (set (match_dup 0)
610 (compare:CC (match_dup 2)
611 (const_int 0)))]
612 "")
614 (define_insn ""
615 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
616 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
617 (const_int 0)))
618 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
619 (sign_extend:SI (match_dup 1)))]
620 "TARGET_POWERPC"
621 "@
622 extsb. %0,%1
623 #"
624 [(set_attr "type" "compare")
625 (set_attr "length" "4,8")])
627 (define_split
628 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
629 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
630 (const_int 0)))
631 (set (match_operand:SI 0 "gpc_reg_operand" "")
632 (sign_extend:SI (match_dup 1)))]
633 "TARGET_POWERPC && reload_completed"
634 [(set (match_dup 0)
635 (sign_extend:SI (match_dup 1)))
636 (set (match_dup 2)
637 (compare:CC (match_dup 0)
638 (const_int 0)))]
639 "")
641 (define_expand "extendqisi2_power"
642 [(parallel [(set (match_dup 2)
643 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
644 (const_int 24)))
645 (clobber (scratch:SI))])
646 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
647 (ashiftrt:SI (match_dup 2)
648 (const_int 24)))
649 (clobber (scratch:SI))])]
650 "TARGET_POWER"
651 "
652 { operands[1] = gen_lowpart (SImode, operands[1]);
653 operands[2] = gen_reg_rtx (SImode); }")
655 (define_expand "extendqisi2_no_power"
656 [(set (match_dup 2)
657 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
658 (const_int 24)))
659 (set (match_operand:SI 0 "gpc_reg_operand" "")
660 (ashiftrt:SI (match_dup 2)
661 (const_int 24)))]
662 "! TARGET_POWER && ! TARGET_POWERPC"
663 "
664 { operands[1] = gen_lowpart (SImode, operands[1]);
665 operands[2] = gen_reg_rtx (SImode); }")
667 (define_expand "zero_extendqihi2"
668 [(set (match_operand:HI 0 "gpc_reg_operand" "")
669 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
670 ""
671 "")
673 (define_insn ""
674 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
675 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
676 ""
677 "@
678 lbz%U1%X1 %0,%1
679 {rlinm|rlwinm} %0,%1,0,0xff"
680 [(set_attr "type" "load,*")])
682 (define_insn ""
683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
684 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
685 (const_int 0)))
686 (clobber (match_scratch:HI 2 "=r,r"))]
687 ""
688 "@
689 {andil.|andi.} %2,%1,0xff
690 #"
691 [(set_attr "type" "compare")
692 (set_attr "length" "4,8")])
694 (define_split
695 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
696 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
697 (const_int 0)))
698 (clobber (match_scratch:HI 2 ""))]
699 "reload_completed"
700 [(set (match_dup 2)
701 (zero_extend:HI (match_dup 1)))
702 (set (match_dup 0)
703 (compare:CC (match_dup 2)
704 (const_int 0)))]
705 "")
707 (define_insn ""
708 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
709 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
710 (const_int 0)))
711 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
712 (zero_extend:HI (match_dup 1)))]
713 ""
714 "@
715 {andil.|andi.} %0,%1,0xff
716 #"
717 [(set_attr "type" "compare")
718 (set_attr "length" "4,8")])
720 (define_split
721 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
722 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
723 (const_int 0)))
724 (set (match_operand:HI 0 "gpc_reg_operand" "")
725 (zero_extend:HI (match_dup 1)))]
726 "reload_completed"
727 [(set (match_dup 0)
728 (zero_extend:HI (match_dup 1)))
729 (set (match_dup 2)
730 (compare:CC (match_dup 0)
731 (const_int 0)))]
732 "")
734 (define_expand "extendqihi2"
735 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
736 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
737 ""
738 "
739 {
740 if (TARGET_POWERPC)
741 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
742 else if (TARGET_POWER)
743 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
744 else
745 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
746 DONE;
747 }")
749 (define_insn "extendqihi2_ppc"
750 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
751 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
752 "TARGET_POWERPC"
753 "extsb %0,%1")
755 (define_insn ""
756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
757 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
758 (const_int 0)))
759 (clobber (match_scratch:HI 2 "=r,r"))]
760 "TARGET_POWERPC"
761 "@
762 extsb. %2,%1
763 #"
764 [(set_attr "type" "compare")
765 (set_attr "length" "4,8")])
767 (define_split
768 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
769 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
770 (const_int 0)))
771 (clobber (match_scratch:HI 2 ""))]
772 "TARGET_POWERPC && reload_completed"
773 [(set (match_dup 2)
774 (sign_extend:HI (match_dup 1)))
775 (set (match_dup 0)
776 (compare:CC (match_dup 2)
777 (const_int 0)))]
778 "")
780 (define_insn ""
781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
783 (const_int 0)))
784 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
785 (sign_extend:HI (match_dup 1)))]
786 "TARGET_POWERPC"
787 "@
788 extsb. %0,%1
789 #"
790 [(set_attr "type" "compare")
791 (set_attr "length" "4,8")])
793 (define_split
794 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
796 (const_int 0)))
797 (set (match_operand:HI 0 "gpc_reg_operand" "")
798 (sign_extend:HI (match_dup 1)))]
799 "TARGET_POWERPC && reload_completed"
800 [(set (match_dup 0)
801 (sign_extend:HI (match_dup 1)))
802 (set (match_dup 2)
803 (compare:CC (match_dup 0)
804 (const_int 0)))]
805 "")
807 (define_expand "extendqihi2_power"
808 [(parallel [(set (match_dup 2)
809 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
810 (const_int 24)))
811 (clobber (scratch:SI))])
812 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
813 (ashiftrt:SI (match_dup 2)
814 (const_int 24)))
815 (clobber (scratch:SI))])]
816 "TARGET_POWER"
817 "
818 { operands[0] = gen_lowpart (SImode, operands[0]);
819 operands[1] = gen_lowpart (SImode, operands[1]);
820 operands[2] = gen_reg_rtx (SImode); }")
822 (define_expand "extendqihi2_no_power"
823 [(set (match_dup 2)
824 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
825 (const_int 24)))
826 (set (match_operand:HI 0 "gpc_reg_operand" "")
827 (ashiftrt:SI (match_dup 2)
828 (const_int 24)))]
829 "! TARGET_POWER && ! TARGET_POWERPC"
830 "
831 { operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
838 ""
839 "")
841 (define_insn ""
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
847 {rlinm|rlwinm} %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
850 (define_insn ""
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (clobber (match_scratch:SI 2 "=r,r"))]
855 ""
856 "@
857 {andil.|andi.} %2,%1,0xffff
858 #"
859 [(set_attr "type" "compare")
860 (set_attr "length" "4,8")])
862 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
875 (define_insn ""
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
881 ""
882 "@
883 {andil.|andi.} %0,%1,0xffff
884 #"
885 [(set_attr "type" "compare")
886 (set_attr "length" "4,8")])
888 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
905 ""
906 "")
908 (define_insn ""
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 ""
912 "@
913 lha%U1%X1 %0,%1
914 {exts|extsh} %0,%1"
915 [(set_attr "type" "load_ext,*")])
917 (define_insn ""
918 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
919 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
920 (const_int 0)))
921 (clobber (match_scratch:SI 2 "=r,r"))]
922 ""
923 "@
924 {exts.|extsh.} %2,%1
925 #"
926 [(set_attr "type" "compare")
927 (set_attr "length" "4,8")])
929 (define_split
930 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
931 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
932 (const_int 0)))
933 (clobber (match_scratch:SI 2 ""))]
934 "reload_completed"
935 [(set (match_dup 2)
936 (sign_extend:SI (match_dup 1)))
937 (set (match_dup 0)
938 (compare:CC (match_dup 2)
939 (const_int 0)))]
940 "")
942 (define_insn ""
943 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
944 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
945 (const_int 0)))
946 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
947 (sign_extend:SI (match_dup 1)))]
948 ""
949 "@
950 {exts.|extsh.} %0,%1
951 #"
952 [(set_attr "type" "compare")
953 (set_attr "length" "4,8")])
954 \f
955 (define_split
956 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
957 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
958 (const_int 0)))
959 (set (match_operand:SI 0 "gpc_reg_operand" "")
960 (sign_extend:SI (match_dup 1)))]
961 "reload_completed"
962 [(set (match_dup 0)
963 (sign_extend:SI (match_dup 1)))
964 (set (match_dup 2)
965 (compare:CC (match_dup 0)
966 (const_int 0)))]
967 "")
969 ;; Fixed-point arithmetic insns.
971 ;; Discourage ai/addic because of carry but provide it in an alternative
972 ;; allowing register zero as source.
973 (define_expand "addsi3"
974 [(set (match_operand:SI 0 "gpc_reg_operand" "")
975 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
976 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
977 ""
978 "
979 {
980 if (GET_CODE (operands[2]) == CONST_INT
981 && ! add_operand (operands[2], SImode))
982 {
983 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
984 ? operands[0] : gen_reg_rtx (SImode));
986 HOST_WIDE_INT val = INTVAL (operands[2]);
987 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
988 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
990 /* The ordering here is important for the prolog expander.
991 When space is allocated from the stack, adding 'low' first may
992 produce a temporary deallocation (which would be bad). */
993 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
994 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
995 DONE;
996 }
997 }")
999 (define_insn "*addsi3_internal1"
1000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1001 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1002 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1003 ""
1004 "@
1005 {cax|add} %0,%1,%2
1006 {cal %0,%2(%1)|addi %0,%1,%2}
1007 {ai|addic} %0,%1,%2
1008 {cau|addis} %0,%1,%v2"
1009 [(set_attr "length" "4,4,4,4")])
1011 (define_insn "addsi3_high"
1012 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1013 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1014 (high:SI (match_operand 2 "" ""))))]
1015 "TARGET_MACHO && !TARGET_64BIT"
1016 "{cau|addis} %0,%1,ha16(%2)"
1017 [(set_attr "length" "4")])
1019 (define_insn "*addsi3_internal2"
1020 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1021 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1022 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1023 (const_int 0)))
1024 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1025 "TARGET_32BIT"
1026 "@
1027 {cax.|add.} %3,%1,%2
1028 {ai.|addic.} %3,%1,%2
1029 #
1030 #"
1031 [(set_attr "type" "fast_compare,compare,compare,compare")
1032 (set_attr "length" "4,4,8,8")])
1034 (define_split
1035 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1036 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1037 (match_operand:SI 2 "reg_or_short_operand" ""))
1038 (const_int 0)))
1039 (clobber (match_scratch:SI 3 ""))]
1040 "TARGET_32BIT && reload_completed"
1041 [(set (match_dup 3)
1042 (plus:SI (match_dup 1)
1043 (match_dup 2)))
1044 (set (match_dup 0)
1045 (compare:CC (match_dup 3)
1046 (const_int 0)))]
1047 "")
1049 (define_insn "*addsi3_internal3"
1050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1051 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1052 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1053 (const_int 0)))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1055 (plus:SI (match_dup 1)
1056 (match_dup 2)))]
1057 "TARGET_32BIT"
1058 "@
1059 {cax.|add.} %0,%1,%2
1060 {ai.|addic.} %0,%1,%2
1061 #
1062 #"
1063 [(set_attr "type" "fast_compare,compare,compare,compare")
1064 (set_attr "length" "4,4,8,8")])
1066 (define_split
1067 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1068 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1069 (match_operand:SI 2 "reg_or_short_operand" ""))
1070 (const_int 0)))
1071 (set (match_operand:SI 0 "gpc_reg_operand" "")
1072 (plus:SI (match_dup 1) (match_dup 2)))]
1073 "TARGET_32BIT && reload_completed"
1074 [(set (match_dup 0)
1075 (plus:SI (match_dup 1)
1076 (match_dup 2)))
1077 (set (match_dup 3)
1078 (compare:CC (match_dup 0)
1079 (const_int 0)))]
1080 "")
1082 ;; Split an add that we can't do in one insn into two insns, each of which
1083 ;; does one 16-bit part. This is used by combine. Note that the low-order
1084 ;; add should be last in case the result gets used in an address.
1086 (define_split
1087 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1088 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1089 (match_operand:SI 2 "non_add_cint_operand" "")))]
1090 ""
1091 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1092 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1093 "
1094 {
1095 HOST_WIDE_INT val = INTVAL (operands[2]);
1096 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1097 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1099 operands[3] = GEN_INT (rest);
1100 operands[4] = GEN_INT (low);
1101 }")
1103 (define_insn "one_cmplsi2"
1104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1105 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1106 ""
1107 "nor %0,%1,%1")
1109 (define_insn ""
1110 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1111 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1112 (const_int 0)))
1113 (clobber (match_scratch:SI 2 "=r,r"))]
1114 "TARGET_32BIT"
1115 "@
1116 nor. %2,%1,%1
1117 #"
1118 [(set_attr "type" "compare")
1119 (set_attr "length" "4,8")])
1121 (define_split
1122 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1123 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1124 (const_int 0)))
1125 (clobber (match_scratch:SI 2 ""))]
1126 "TARGET_32BIT && reload_completed"
1127 [(set (match_dup 2)
1128 (not:SI (match_dup 1)))
1129 (set (match_dup 0)
1130 (compare:CC (match_dup 2)
1131 (const_int 0)))]
1132 "")
1134 (define_insn ""
1135 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1136 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1137 (const_int 0)))
1138 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1139 (not:SI (match_dup 1)))]
1140 "TARGET_32BIT"
1141 "@
1142 nor. %0,%1,%1
1143 #"
1144 [(set_attr "type" "compare")
1145 (set_attr "length" "4,8")])
1147 (define_split
1148 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1149 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1150 (const_int 0)))
1151 (set (match_operand:SI 0 "gpc_reg_operand" "")
1152 (not:SI (match_dup 1)))]
1153 "TARGET_32BIT && reload_completed"
1154 [(set (match_dup 0)
1155 (not:SI (match_dup 1)))
1156 (set (match_dup 2)
1157 (compare:CC (match_dup 0)
1158 (const_int 0)))]
1159 "")
1161 (define_insn ""
1162 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1163 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1164 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1165 "! TARGET_POWERPC"
1166 "{sf%I1|subf%I1c} %0,%2,%1")
1168 (define_insn ""
1169 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1170 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1171 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1172 "TARGET_POWERPC"
1173 "@
1174 subf %0,%2,%1
1175 subfic %0,%2,%1")
1177 (define_insn ""
1178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1179 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1180 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1181 (const_int 0)))
1182 (clobber (match_scratch:SI 3 "=r,r"))]
1183 "! TARGET_POWERPC"
1184 "@
1185 {sf.|subfc.} %3,%2,%1
1186 #"
1187 [(set_attr "type" "compare")
1188 (set_attr "length" "4,8")])
1190 (define_insn ""
1191 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1192 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1193 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1194 (const_int 0)))
1195 (clobber (match_scratch:SI 3 "=r,r"))]
1196 "TARGET_POWERPC && TARGET_32BIT"
1197 "@
1198 subf. %3,%2,%1
1199 #"
1200 [(set_attr "type" "fast_compare")
1201 (set_attr "length" "4,8")])
1203 (define_split
1204 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1205 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1206 (match_operand:SI 2 "gpc_reg_operand" ""))
1207 (const_int 0)))
1208 (clobber (match_scratch:SI 3 ""))]
1209 "TARGET_32BIT && reload_completed"
1210 [(set (match_dup 3)
1211 (minus:SI (match_dup 1)
1212 (match_dup 2)))
1213 (set (match_dup 0)
1214 (compare:CC (match_dup 3)
1215 (const_int 0)))]
1216 "")
1218 (define_insn ""
1219 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1220 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1221 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1222 (const_int 0)))
1223 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1224 (minus:SI (match_dup 1) (match_dup 2)))]
1225 "! TARGET_POWERPC"
1226 "@
1227 {sf.|subfc.} %0,%2,%1
1228 #"
1229 [(set_attr "type" "compare")
1230 (set_attr "length" "4,8")])
1232 (define_insn ""
1233 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1234 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1235 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1236 (const_int 0)))
1237 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1238 (minus:SI (match_dup 1)
1239 (match_dup 2)))]
1240 "TARGET_POWERPC && TARGET_32BIT"
1241 "@
1242 subf. %0,%2,%1
1243 #"
1244 [(set_attr "type" "fast_compare")
1245 (set_attr "length" "4,8")])
1247 (define_split
1248 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1249 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1250 (match_operand:SI 2 "gpc_reg_operand" ""))
1251 (const_int 0)))
1252 (set (match_operand:SI 0 "gpc_reg_operand" "")
1253 (minus:SI (match_dup 1)
1254 (match_dup 2)))]
1255 "TARGET_32BIT && reload_completed"
1256 [(set (match_dup 0)
1257 (minus:SI (match_dup 1)
1258 (match_dup 2)))
1259 (set (match_dup 3)
1260 (compare:CC (match_dup 0)
1261 (const_int 0)))]
1262 "")
1264 (define_expand "subsi3"
1265 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1266 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1267 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1268 ""
1269 "
1270 {
1271 if (GET_CODE (operands[2]) == CONST_INT)
1272 {
1273 emit_insn (gen_addsi3 (operands[0], operands[1],
1274 negate_rtx (SImode, operands[2])));
1275 DONE;
1276 }
1277 }")
1279 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1280 ;; instruction and some auxiliary computations. Then we just have a single
1281 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1282 ;; combine.
1284 (define_expand "sminsi3"
1285 [(set (match_dup 3)
1286 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1287 (match_operand:SI 2 "reg_or_short_operand" ""))
1288 (const_int 0)
1289 (minus:SI (match_dup 2) (match_dup 1))))
1290 (set (match_operand:SI 0 "gpc_reg_operand" "")
1291 (minus:SI (match_dup 2) (match_dup 3)))]
1292 "TARGET_POWER || TARGET_ISEL"
1293 "
1294 {
1295 if (TARGET_ISEL)
1296 {
1297 operands[2] = force_reg (SImode, operands[2]);
1298 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1299 DONE;
1300 }
1302 operands[3] = gen_reg_rtx (SImode);
1303 }")
1305 (define_split
1306 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1307 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1308 (match_operand:SI 2 "reg_or_short_operand" "")))
1309 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1310 "TARGET_POWER"
1311 [(set (match_dup 3)
1312 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1313 (const_int 0)
1314 (minus:SI (match_dup 2) (match_dup 1))))
1315 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1316 "")
1318 (define_expand "smaxsi3"
1319 [(set (match_dup 3)
1320 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1321 (match_operand:SI 2 "reg_or_short_operand" ""))
1322 (const_int 0)
1323 (minus:SI (match_dup 2) (match_dup 1))))
1324 (set (match_operand:SI 0 "gpc_reg_operand" "")
1325 (plus:SI (match_dup 3) (match_dup 1)))]
1326 "TARGET_POWER || TARGET_ISEL"
1327 "
1328 {
1329 if (TARGET_ISEL)
1330 {
1331 operands[2] = force_reg (SImode, operands[2]);
1332 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1333 DONE;
1334 }
1335 operands[3] = gen_reg_rtx (SImode);
1336 }")
1338 (define_split
1339 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1340 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1341 (match_operand:SI 2 "reg_or_short_operand" "")))
1342 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1343 "TARGET_POWER"
1344 [(set (match_dup 3)
1345 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1346 (const_int 0)
1347 (minus:SI (match_dup 2) (match_dup 1))))
1348 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1349 "")
1351 (define_expand "uminsi3"
1352 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1353 (match_dup 5)))
1354 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1355 (match_dup 5)))
1356 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1357 (const_int 0)
1358 (minus:SI (match_dup 4) (match_dup 3))))
1359 (set (match_operand:SI 0 "gpc_reg_operand" "")
1360 (minus:SI (match_dup 2) (match_dup 3)))]
1361 "TARGET_POWER || TARGET_ISEL"
1362 "
1363 {
1364 if (TARGET_ISEL)
1365 {
1366 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1367 DONE;
1368 }
1369 operands[3] = gen_reg_rtx (SImode);
1370 operands[4] = gen_reg_rtx (SImode);
1371 operands[5] = GEN_INT (-2147483647 - 1);
1372 }")
1374 (define_expand "umaxsi3"
1375 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1376 (match_dup 5)))
1377 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1378 (match_dup 5)))
1379 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1380 (const_int 0)
1381 (minus:SI (match_dup 4) (match_dup 3))))
1382 (set (match_operand:SI 0 "gpc_reg_operand" "")
1383 (plus:SI (match_dup 3) (match_dup 1)))]
1384 "TARGET_POWER || TARGET_ISEL"
1385 "
1386 {
1387 if (TARGET_ISEL)
1388 {
1389 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1390 DONE;
1391 }
1392 operands[3] = gen_reg_rtx (SImode);
1393 operands[4] = gen_reg_rtx (SImode);
1394 operands[5] = GEN_INT (-2147483647 - 1);
1395 }")
1397 (define_insn ""
1398 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1399 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1400 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1401 (const_int 0)
1402 (minus:SI (match_dup 2) (match_dup 1))))]
1403 "TARGET_POWER"
1404 "doz%I2 %0,%1,%2")
1406 (define_insn ""
1407 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1408 (compare:CC
1409 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1410 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1411 (const_int 0)
1412 (minus:SI (match_dup 2) (match_dup 1)))
1413 (const_int 0)))
1414 (clobber (match_scratch:SI 3 "=r,r"))]
1415 "TARGET_POWER"
1416 "@
1417 doz%I2. %3,%1,%2
1418 #"
1419 [(set_attr "type" "delayed_compare")
1420 (set_attr "length" "4,8")])
1422 (define_split
1423 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1424 (compare:CC
1425 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1426 (match_operand:SI 2 "reg_or_short_operand" ""))
1427 (const_int 0)
1428 (minus:SI (match_dup 2) (match_dup 1)))
1429 (const_int 0)))
1430 (clobber (match_scratch:SI 3 ""))]
1431 "TARGET_POWER && reload_completed"
1432 [(set (match_dup 3)
1433 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1434 (const_int 0)
1435 (minus:SI (match_dup 2) (match_dup 1))))
1436 (set (match_dup 0)
1437 (compare:CC (match_dup 3)
1438 (const_int 0)))]
1439 "")
1441 (define_insn ""
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1443 (compare:CC
1444 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1445 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1446 (const_int 0)
1447 (minus:SI (match_dup 2) (match_dup 1)))
1448 (const_int 0)))
1449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1450 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1451 (const_int 0)
1452 (minus:SI (match_dup 2) (match_dup 1))))]
1453 "TARGET_POWER"
1454 "@
1455 doz%I2. %0,%1,%2
1456 #"
1457 [(set_attr "type" "delayed_compare")
1458 (set_attr "length" "4,8")])
1460 (define_split
1461 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1462 (compare:CC
1463 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1464 (match_operand:SI 2 "reg_or_short_operand" ""))
1465 (const_int 0)
1466 (minus:SI (match_dup 2) (match_dup 1)))
1467 (const_int 0)))
1468 (set (match_operand:SI 0 "gpc_reg_operand" "")
1469 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1470 (const_int 0)
1471 (minus:SI (match_dup 2) (match_dup 1))))]
1472 "TARGET_POWER && reload_completed"
1473 [(set (match_dup 0)
1474 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1475 (const_int 0)
1476 (minus:SI (match_dup 2) (match_dup 1))))
1477 (set (match_dup 3)
1478 (compare:CC (match_dup 0)
1479 (const_int 0)))]
1480 "")
1482 ;; We don't need abs with condition code because such comparisons should
1483 ;; never be done.
1484 (define_expand "abssi2"
1485 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1486 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1487 ""
1488 "
1489 {
1490 if (TARGET_ISEL)
1491 {
1492 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1493 DONE;
1494 }
1495 else if (! TARGET_POWER)
1496 {
1497 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1498 DONE;
1499 }
1500 }")
1502 (define_insn "*abssi2_power"
1503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1504 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1505 "TARGET_POWER"
1506 "abs %0,%1")
1508 (define_insn_and_split "abssi2_isel"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1510 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1511 (clobber (match_scratch:SI 2 "=&b"))
1512 (clobber (match_scratch:CC 3 "=y"))]
1513 "TARGET_ISEL"
1514 "#"
1515 "&& reload_completed"
1516 [(set (match_dup 2) (neg:SI (match_dup 1)))
1517 (set (match_dup 3)
1518 (compare:CC (match_dup 1)
1519 (const_int 0)))
1520 (set (match_dup 0)
1521 (if_then_else:SI (ge (match_dup 3)
1522 (const_int 0))
1523 (match_dup 1)
1524 (match_dup 2)))]
1525 "")
1527 (define_insn_and_split "abssi2_nopower"
1528 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1529 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1530 (clobber (match_scratch:SI 2 "=&r,&r"))]
1531 "! TARGET_POWER && ! TARGET_ISEL"
1532 "#"
1533 "&& reload_completed"
1534 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1535 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1536 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1537 "")
1539 (define_insn "*nabs_power"
1540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1541 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1542 "TARGET_POWER"
1543 "nabs %0,%1")
1545 (define_insn_and_split "*nabs_nopower"
1546 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1547 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1548 (clobber (match_scratch:SI 2 "=&r,&r"))]
1549 "! TARGET_POWER"
1550 "#"
1551 "&& reload_completed"
1552 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1553 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1554 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1555 "")
1557 (define_insn "negsi2"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1559 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1560 ""
1561 "neg %0,%1")
1563 (define_insn ""
1564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1565 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1566 (const_int 0)))
1567 (clobber (match_scratch:SI 2 "=r,r"))]
1568 "TARGET_32BIT"
1569 "@
1570 neg. %2,%1
1571 #"
1572 [(set_attr "type" "fast_compare")
1573 (set_attr "length" "4,8")])
1575 (define_split
1576 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1577 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1578 (const_int 0)))
1579 (clobber (match_scratch:SI 2 ""))]
1580 "TARGET_32BIT && reload_completed"
1581 [(set (match_dup 2)
1582 (neg:SI (match_dup 1)))
1583 (set (match_dup 0)
1584 (compare:CC (match_dup 2)
1585 (const_int 0)))]
1586 "")
1588 (define_insn ""
1589 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1590 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1591 (const_int 0)))
1592 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1593 (neg:SI (match_dup 1)))]
1594 "TARGET_32BIT"
1595 "@
1596 neg. %0,%1
1597 #"
1598 [(set_attr "type" "fast_compare")
1599 (set_attr "length" "4,8")])
1601 (define_split
1602 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1603 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1604 (const_int 0)))
1605 (set (match_operand:SI 0 "gpc_reg_operand" "")
1606 (neg:SI (match_dup 1)))]
1607 "TARGET_32BIT && reload_completed"
1608 [(set (match_dup 0)
1609 (neg:SI (match_dup 1)))
1610 (set (match_dup 2)
1611 (compare:CC (match_dup 0)
1612 (const_int 0)))]
1613 "")
1615 (define_insn "clzsi2"
1616 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1617 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1618 ""
1619 "{cntlz|cntlzw} %0,%1")
1621 (define_expand "ctzsi2"
1622 [(set (match_dup 2)
1623 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1624 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1625 (match_dup 2)))
1626 (clobber (scratch:CC))])
1627 (set (match_dup 4) (clz:SI (match_dup 3)))
1628 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1629 (minus:SI (const_int 31) (match_dup 4)))]
1630 ""
1631 {
1632 operands[2] = gen_reg_rtx (SImode);
1633 operands[3] = gen_reg_rtx (SImode);
1634 operands[4] = gen_reg_rtx (SImode);
1635 })
1637 (define_expand "ffssi2"
1638 [(set (match_dup 2)
1639 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1640 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1641 (match_dup 2)))
1642 (clobber (scratch:CC))])
1643 (set (match_dup 4) (clz:SI (match_dup 3)))
1644 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1645 (minus:SI (const_int 32) (match_dup 4)))]
1646 ""
1647 {
1648 operands[2] = gen_reg_rtx (SImode);
1649 operands[3] = gen_reg_rtx (SImode);
1650 operands[4] = gen_reg_rtx (SImode);
1651 })
1653 (define_expand "mulsi3"
1654 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1655 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1656 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1657 ""
1658 "
1659 {
1660 if (TARGET_POWER)
1661 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1662 else
1663 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1664 DONE;
1665 }")
1667 (define_insn "mulsi3_mq"
1668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1669 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1670 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1671 (clobber (match_scratch:SI 3 "=q,q"))]
1672 "TARGET_POWER"
1673 "@
1674 {muls|mullw} %0,%1,%2
1675 {muli|mulli} %0,%1,%2"
1676 [(set (attr "type")
1677 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1678 (const_string "imul3")
1679 (match_operand:SI 2 "short_cint_operand" "")
1680 (const_string "imul2")]
1681 (const_string "imul")))])
1683 (define_insn "mulsi3_no_mq"
1684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1685 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1686 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1687 "! TARGET_POWER"
1688 "@
1689 {muls|mullw} %0,%1,%2
1690 {muli|mulli} %0,%1,%2"
1691 [(set (attr "type")
1692 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1693 (const_string "imul3")
1694 (match_operand:SI 2 "short_cint_operand" "")
1695 (const_string "imul2")]
1696 (const_string "imul")))])
1698 (define_insn "*mulsi3_mq_internal1"
1699 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1700 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1701 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1702 (const_int 0)))
1703 (clobber (match_scratch:SI 3 "=r,r"))
1704 (clobber (match_scratch:SI 4 "=q,q"))]
1705 "TARGET_POWER"
1706 "@
1707 {muls.|mullw.} %3,%1,%2
1708 #"
1709 [(set_attr "type" "imul_compare")
1710 (set_attr "length" "4,8")])
1712 (define_split
1713 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1714 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1715 (match_operand:SI 2 "gpc_reg_operand" ""))
1716 (const_int 0)))
1717 (clobber (match_scratch:SI 3 ""))
1718 (clobber (match_scratch:SI 4 ""))]
1719 "TARGET_POWER && reload_completed"
1720 [(parallel [(set (match_dup 3)
1721 (mult:SI (match_dup 1) (match_dup 2)))
1722 (clobber (match_dup 4))])
1723 (set (match_dup 0)
1724 (compare:CC (match_dup 3)
1725 (const_int 0)))]
1726 "")
1728 (define_insn "*mulsi3_no_mq_internal1"
1729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1730 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1731 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1732 (const_int 0)))
1733 (clobber (match_scratch:SI 3 "=r,r"))]
1734 "! TARGET_POWER"
1735 "@
1736 {muls.|mullw.} %3,%1,%2
1737 #"
1738 [(set_attr "type" "imul_compare")
1739 (set_attr "length" "4,8")])
1741 (define_split
1742 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1743 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1744 (match_operand:SI 2 "gpc_reg_operand" ""))
1745 (const_int 0)))
1746 (clobber (match_scratch:SI 3 ""))]
1747 "! TARGET_POWER && reload_completed"
1748 [(set (match_dup 3)
1749 (mult:SI (match_dup 1) (match_dup 2)))
1750 (set (match_dup 0)
1751 (compare:CC (match_dup 3)
1752 (const_int 0)))]
1753 "")
1755 (define_insn "*mulsi3_mq_internal2"
1756 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1757 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1758 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1759 (const_int 0)))
1760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1761 (mult:SI (match_dup 1) (match_dup 2)))
1762 (clobber (match_scratch:SI 4 "=q,q"))]
1763 "TARGET_POWER"
1764 "@
1765 {muls.|mullw.} %0,%1,%2
1766 #"
1767 [(set_attr "type" "imul_compare")
1768 (set_attr "length" "4,8")])
1770 (define_split
1771 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1772 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1773 (match_operand:SI 2 "gpc_reg_operand" ""))
1774 (const_int 0)))
1775 (set (match_operand:SI 0 "gpc_reg_operand" "")
1776 (mult:SI (match_dup 1) (match_dup 2)))
1777 (clobber (match_scratch:SI 4 ""))]
1778 "TARGET_POWER && reload_completed"
1779 [(parallel [(set (match_dup 0)
1780 (mult:SI (match_dup 1) (match_dup 2)))
1781 (clobber (match_dup 4))])
1782 (set (match_dup 3)
1783 (compare:CC (match_dup 0)
1784 (const_int 0)))]
1785 "")
1787 (define_insn "*mulsi3_no_mq_internal2"
1788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1789 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1790 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1791 (const_int 0)))
1792 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1793 (mult:SI (match_dup 1) (match_dup 2)))]
1794 "! TARGET_POWER"
1795 "@
1796 {muls.|mullw.} %0,%1,%2
1797 #"
1798 [(set_attr "type" "imul_compare")
1799 (set_attr "length" "4,8")])
1801 (define_split
1802 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1803 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1804 (match_operand:SI 2 "gpc_reg_operand" ""))
1805 (const_int 0)))
1806 (set (match_operand:SI 0 "gpc_reg_operand" "")
1807 (mult:SI (match_dup 1) (match_dup 2)))]
1808 "! TARGET_POWER && reload_completed"
1809 [(set (match_dup 0)
1810 (mult:SI (match_dup 1) (match_dup 2)))
1811 (set (match_dup 3)
1812 (compare:CC (match_dup 0)
1813 (const_int 0)))]
1814 "")
1816 ;; Operand 1 is divided by operand 2; quotient goes to operand
1817 ;; 0 and remainder to operand 3.
1818 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1820 (define_expand "divmodsi4"
1821 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1822 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1823 (match_operand:SI 2 "gpc_reg_operand" "")))
1824 (set (match_operand:SI 3 "register_operand" "")
1825 (mod:SI (match_dup 1) (match_dup 2)))])]
1826 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1827 "
1828 {
1829 if (! TARGET_POWER && ! TARGET_POWERPC)
1830 {
1831 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1832 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1833 emit_insn (gen_divss_call ());
1834 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1835 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1836 DONE;
1837 }
1838 }")
1840 (define_insn "*divmodsi4_internal"
1841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1842 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1843 (match_operand:SI 2 "gpc_reg_operand" "r")))
1844 (set (match_operand:SI 3 "register_operand" "=q")
1845 (mod:SI (match_dup 1) (match_dup 2)))]
1846 "TARGET_POWER"
1847 "divs %0,%1,%2"
1848 [(set_attr "type" "idiv")])
1850 (define_expand "udivsi3"
1851 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1852 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1853 (match_operand:SI 2 "gpc_reg_operand" "")))]
1854 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1855 "
1856 {
1857 if (! TARGET_POWER && ! TARGET_POWERPC)
1858 {
1859 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1860 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1861 emit_insn (gen_quous_call ());
1862 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1863 DONE;
1864 }
1865 else if (TARGET_POWER)
1866 {
1867 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1868 DONE;
1869 }
1870 }")
1872 (define_insn "udivsi3_mq"
1873 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1874 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1875 (match_operand:SI 2 "gpc_reg_operand" "r")))
1876 (clobber (match_scratch:SI 3 "=q"))]
1877 "TARGET_POWERPC && TARGET_POWER"
1878 "divwu %0,%1,%2"
1879 [(set_attr "type" "idiv")])
1881 (define_insn "*udivsi3_no_mq"
1882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1883 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1884 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1885 "TARGET_POWERPC && ! TARGET_POWER"
1886 "divwu %0,%1,%2"
1887 [(set_attr "type" "idiv")])
1889 ;; For powers of two we can do srai/aze for divide and then adjust for
1890 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1891 ;; used; for PowerPC, force operands into register and do a normal divide;
1892 ;; for AIX common-mode, use quoss call on register operands.
1893 (define_expand "divsi3"
1894 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1895 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1896 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1897 ""
1898 "
1899 {
1900 if (GET_CODE (operands[2]) == CONST_INT
1901 && INTVAL (operands[2]) > 0
1902 && exact_log2 (INTVAL (operands[2])) >= 0)
1903 ;
1904 else if (TARGET_POWERPC)
1905 {
1906 operands[2] = force_reg (SImode, operands[2]);
1907 if (TARGET_POWER)
1908 {
1909 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1910 DONE;
1911 }
1912 }
1913 else if (TARGET_POWER)
1914 FAIL;
1915 else
1916 {
1917 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1918 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1919 emit_insn (gen_quoss_call ());
1920 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1921 DONE;
1922 }
1923 }")
1925 (define_insn "divsi3_mq"
1926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1927 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1928 (match_operand:SI 2 "gpc_reg_operand" "r")))
1929 (clobber (match_scratch:SI 3 "=q"))]
1930 "TARGET_POWERPC && TARGET_POWER"
1931 "divw %0,%1,%2"
1932 [(set_attr "type" "idiv")])
1934 (define_insn "*divsi3_no_mq"
1935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1936 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1937 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1938 "TARGET_POWERPC && ! TARGET_POWER"
1939 "divw %0,%1,%2"
1940 [(set_attr "type" "idiv")])
1942 (define_expand "modsi3"
1943 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1944 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1945 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1946 ""
1947 "
1948 {
1949 int i;
1950 rtx temp1;
1951 rtx temp2;
1953 if (GET_CODE (operands[2]) != CONST_INT
1954 || INTVAL (operands[2]) <= 0
1955 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1956 FAIL;
1958 temp1 = gen_reg_rtx (SImode);
1959 temp2 = gen_reg_rtx (SImode);
1961 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1962 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1963 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1964 DONE;
1965 }")
1967 (define_insn ""
1968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1969 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1970 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1971 ""
1972 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1973 [(set_attr "length" "8")])
1975 (define_insn ""
1976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1977 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1979 (const_int 0)))
1980 (clobber (match_scratch:SI 3 "=r,r"))]
1981 ""
1982 "@
1983 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1984 #"
1985 [(set_attr "type" "compare")
1986 (set_attr "length" "8,12")])
1988 (define_split
1989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1990 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1991 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1992 (const_int 0)))
1993 (clobber (match_scratch:SI 3 ""))]
1994 "reload_completed"
1995 [(set (match_dup 3)
1996 (div:SI (match_dup 1) (match_dup 2)))
1997 (set (match_dup 0)
1998 (compare:CC (match_dup 3)
1999 (const_int 0)))]
2000 "")
2002 (define_insn ""
2003 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2004 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2005 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2006 (const_int 0)))
2007 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2008 (div:SI (match_dup 1) (match_dup 2)))]
2009 ""
2010 "@
2011 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2012 #"
2013 [(set_attr "type" "compare")
2014 (set_attr "length" "8,12")])
2016 (define_split
2017 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2018 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2019 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2020 (const_int 0)))
2021 (set (match_operand:SI 0 "gpc_reg_operand" "")
2022 (div:SI (match_dup 1) (match_dup 2)))]
2023 "reload_completed"
2024 [(set (match_dup 0)
2025 (div:SI (match_dup 1) (match_dup 2)))
2026 (set (match_dup 3)
2027 (compare:CC (match_dup 0)
2028 (const_int 0)))]
2029 "")
2031 (define_insn ""
2032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2033 (udiv:SI
2034 (plus:DI (ashift:DI
2035 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2036 (const_int 32))
2037 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2038 (match_operand:SI 3 "gpc_reg_operand" "r")))
2039 (set (match_operand:SI 2 "register_operand" "=*q")
2040 (umod:SI
2041 (plus:DI (ashift:DI
2042 (zero_extend:DI (match_dup 1)) (const_int 32))
2043 (zero_extend:DI (match_dup 4)))
2044 (match_dup 3)))]
2045 "TARGET_POWER"
2046 "div %0,%1,%3"
2047 [(set_attr "type" "idiv")])
2049 ;; To do unsigned divide we handle the cases of the divisor looking like a
2050 ;; negative number. If it is a constant that is less than 2**31, we don't
2051 ;; have to worry about the branches. So make a few subroutines here.
2052 ;;
2053 ;; First comes the normal case.
2054 (define_expand "udivmodsi4_normal"
2055 [(set (match_dup 4) (const_int 0))
2056 (parallel [(set (match_operand:SI 0 "" "")
2057 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2058 (const_int 32))
2059 (zero_extend:DI (match_operand:SI 1 "" "")))
2060 (match_operand:SI 2 "" "")))
2061 (set (match_operand:SI 3 "" "")
2062 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2063 (const_int 32))
2064 (zero_extend:DI (match_dup 1)))
2065 (match_dup 2)))])]
2066 "TARGET_POWER"
2067 "
2068 { operands[4] = gen_reg_rtx (SImode); }")
2070 ;; This handles the branches.
2071 (define_expand "udivmodsi4_tests"
2072 [(set (match_operand:SI 0 "" "") (const_int 0))
2073 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2074 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2075 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2076 (label_ref (match_operand:SI 4 "" "")) (pc)))
2077 (set (match_dup 0) (const_int 1))
2078 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2079 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2080 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2081 (label_ref (match_dup 4)) (pc)))]
2082 "TARGET_POWER"
2083 "
2084 { operands[5] = gen_reg_rtx (CCUNSmode);
2085 operands[6] = gen_reg_rtx (CCmode);
2086 }")
2088 (define_expand "udivmodsi4"
2089 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2090 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2091 (match_operand:SI 2 "reg_or_cint_operand" "")))
2092 (set (match_operand:SI 3 "gpc_reg_operand" "")
2093 (umod:SI (match_dup 1) (match_dup 2)))])]
2094 ""
2095 "
2096 {
2097 rtx label = 0;
2099 if (! TARGET_POWER)
2100 {
2101 if (! TARGET_POWERPC)
2102 {
2103 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2104 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2105 emit_insn (gen_divus_call ());
2106 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2107 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2108 DONE;
2109 }
2110 else
2111 FAIL;
2112 }
2114 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2115 {
2116 operands[2] = force_reg (SImode, operands[2]);
2117 label = gen_label_rtx ();
2118 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2119 operands[3], label));
2120 }
2121 else
2122 operands[2] = force_reg (SImode, operands[2]);
2124 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2125 operands[3]));
2126 if (label)
2127 emit_label (label);
2129 DONE;
2130 }")
2132 ;; AIX architecture-independent common-mode multiply (DImode),
2133 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2134 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2135 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2136 ;; assumed unused if generating common-mode, so ignore.
2137 (define_insn "mulh_call"
2138 [(set (reg:SI 3)
2139 (truncate:SI
2140 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2141 (sign_extend:DI (reg:SI 4)))
2142 (const_int 32))))
2143 (clobber (match_scratch:SI 0 "=l"))]
2144 "! TARGET_POWER && ! TARGET_POWERPC"
2145 "bla __mulh"
2146 [(set_attr "type" "imul")])
2148 (define_insn "mull_call"
2149 [(set (reg:DI 3)
2150 (mult:DI (sign_extend:DI (reg:SI 3))
2151 (sign_extend:DI (reg:SI 4))))
2152 (clobber (match_scratch:SI 0 "=l"))
2153 (clobber (reg:SI 0))]
2154 "! TARGET_POWER && ! TARGET_POWERPC"
2155 "bla __mull"
2156 [(set_attr "type" "imul")])
2158 (define_insn "divss_call"
2159 [(set (reg:SI 3)
2160 (div:SI (reg:SI 3) (reg:SI 4)))
2161 (set (reg:SI 4)
2162 (mod:SI (reg:SI 3) (reg:SI 4)))
2163 (clobber (match_scratch:SI 0 "=l"))
2164 (clobber (reg:SI 0))]
2165 "! TARGET_POWER && ! TARGET_POWERPC"
2166 "bla __divss"
2167 [(set_attr "type" "idiv")])
2169 (define_insn "divus_call"
2170 [(set (reg:SI 3)
2171 (udiv:SI (reg:SI 3) (reg:SI 4)))
2172 (set (reg:SI 4)
2173 (umod:SI (reg:SI 3) (reg:SI 4)))
2174 (clobber (match_scratch:SI 0 "=l"))
2175 (clobber (reg:SI 0))
2176 (clobber (match_scratch:CC 1 "=x"))
2177 (clobber (reg:CC 69))]
2178 "! TARGET_POWER && ! TARGET_POWERPC"
2179 "bla __divus"
2180 [(set_attr "type" "idiv")])
2182 (define_insn "quoss_call"
2183 [(set (reg:SI 3)
2184 (div:SI (reg:SI 3) (reg:SI 4)))
2185 (clobber (match_scratch:SI 0 "=l"))]
2186 "! TARGET_POWER && ! TARGET_POWERPC"
2187 "bla __quoss"
2188 [(set_attr "type" "idiv")])
2190 (define_insn "quous_call"
2191 [(set (reg:SI 3)
2192 (udiv:SI (reg:SI 3) (reg:SI 4)))
2193 (clobber (match_scratch:SI 0 "=l"))
2194 (clobber (reg:SI 0))
2195 (clobber (match_scratch:CC 1 "=x"))
2196 (clobber (reg:CC 69))]
2197 "! TARGET_POWER && ! TARGET_POWERPC"
2198 "bla __quous"
2199 [(set_attr "type" "idiv")])
2200 \f
2201 ;; Logical instructions
2202 ;; The logical instructions are mostly combined by using match_operator,
2203 ;; but the plain AND insns are somewhat different because there is no
2204 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2205 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2207 (define_insn "andsi3"
2208 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2209 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2210 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2211 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2212 ""
2213 "@
2214 and %0,%1,%2
2215 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2216 {andil.|andi.} %0,%1,%b2
2217 {andiu.|andis.} %0,%1,%u2")
2219 ;; Note to set cr's other than cr0 we do the and immediate and then
2220 ;; the test again -- this avoids a mfcr which on the higher end
2221 ;; machines causes an execution serialization
2223 (define_insn "*andsi3_internal2"
2224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2225 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2226 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2227 (const_int 0)))
2228 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2229 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2230 "TARGET_32BIT"
2231 "@
2232 and. %3,%1,%2
2233 {andil.|andi.} %3,%1,%b2
2234 {andiu.|andis.} %3,%1,%u2
2235 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2236 #
2237 #
2238 #
2239 #"
2240 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2241 (set_attr "length" "4,4,4,4,8,8,8,8")])
2243 (define_insn "*andsi3_internal3"
2244 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2245 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2246 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2247 (const_int 0)))
2248 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2249 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2250 "TARGET_64BIT"
2251 "@
2252 #
2253 {andil.|andi.} %3,%1,%b2
2254 {andiu.|andis.} %3,%1,%u2
2255 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2256 #
2257 #
2258 #
2259 #"
2260 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2261 (set_attr "length" "8,4,4,4,8,8,8,8")])
2263 (define_split
2264 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2265 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2266 (match_operand:SI 2 "and_operand" ""))
2267 (const_int 0)))
2268 (clobber (match_scratch:SI 3 ""))
2269 (clobber (match_scratch:CC 4 ""))]
2270 "reload_completed"
2271 [(parallel [(set (match_dup 3)
2272 (and:SI (match_dup 1)
2273 (match_dup 2)))
2274 (clobber (match_dup 4))])
2275 (set (match_dup 0)
2276 (compare:CC (match_dup 3)
2277 (const_int 0)))]
2278 "")
2280 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2281 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2283 (define_split
2284 [(set (match_operand:CC 0 "cc_reg_operand" "")
2285 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2286 (match_operand:SI 2 "gpc_reg_operand" ""))
2287 (const_int 0)))
2288 (clobber (match_scratch:SI 3 ""))
2289 (clobber (match_scratch:CC 4 ""))]
2290 "TARGET_POWERPC64 && reload_completed"
2291 [(parallel [(set (match_dup 3)
2292 (and:SI (match_dup 1)
2293 (match_dup 2)))
2294 (clobber (match_dup 4))])
2295 (set (match_dup 0)
2296 (compare:CC (match_dup 3)
2297 (const_int 0)))]
2298 "")
2300 (define_insn "*andsi3_internal4"
2301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2302 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2303 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2304 (const_int 0)))
2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2306 (and:SI (match_dup 1)
2307 (match_dup 2)))
2308 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2309 "TARGET_32BIT"
2310 "@
2311 and. %0,%1,%2
2312 {andil.|andi.} %0,%1,%b2
2313 {andiu.|andis.} %0,%1,%u2
2314 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2315 #
2316 #
2317 #
2318 #"
2319 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2320 (set_attr "length" "4,4,4,4,8,8,8,8")])
2322 (define_insn "*andsi3_internal5"
2323 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2324 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2325 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2326 (const_int 0)))
2327 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2328 (and:SI (match_dup 1)
2329 (match_dup 2)))
2330 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2331 "TARGET_64BIT"
2332 "@
2333 #
2334 {andil.|andi.} %0,%1,%b2
2335 {andiu.|andis.} %0,%1,%u2
2336 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2337 #
2338 #
2339 #
2340 #"
2341 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2342 (set_attr "length" "8,4,4,4,8,8,8,8")])
2344 (define_split
2345 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2346 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2347 (match_operand:SI 2 "and_operand" ""))
2348 (const_int 0)))
2349 (set (match_operand:SI 0 "gpc_reg_operand" "")
2350 (and:SI (match_dup 1)
2351 (match_dup 2)))
2352 (clobber (match_scratch:CC 4 ""))]
2353 "reload_completed"
2354 [(parallel [(set (match_dup 0)
2355 (and:SI (match_dup 1)
2356 (match_dup 2)))
2357 (clobber (match_dup 4))])
2358 (set (match_dup 3)
2359 (compare:CC (match_dup 0)
2360 (const_int 0)))]
2361 "")
2363 (define_split
2364 [(set (match_operand:CC 3 "cc_reg_operand" "")
2365 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2366 (match_operand:SI 2 "gpc_reg_operand" ""))
2367 (const_int 0)))
2368 (set (match_operand:SI 0 "gpc_reg_operand" "")
2369 (and:SI (match_dup 1)
2370 (match_dup 2)))
2371 (clobber (match_scratch:CC 4 ""))]
2372 "TARGET_POWERPC64 && reload_completed"
2373 [(parallel [(set (match_dup 0)
2374 (and:SI (match_dup 1)
2375 (match_dup 2)))
2376 (clobber (match_dup 4))])
2377 (set (match_dup 3)
2378 (compare:CC (match_dup 0)
2379 (const_int 0)))]
2380 "")
2382 ;; Handle the PowerPC64 rlwinm corner case
2384 (define_insn_and_split "*andsi3_internal6"
2385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2386 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2387 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2388 "TARGET_POWERPC64"
2389 "#"
2390 "TARGET_POWERPC64"
2391 [(set (match_dup 0)
2392 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2393 (match_dup 4)))
2394 (set (match_dup 0)
2395 (rotate:SI (match_dup 0) (match_dup 5)))]
2396 "
2397 {
2398 int mb = extract_MB (operands[2]);
2399 int me = extract_ME (operands[2]);
2400 operands[3] = GEN_INT (me + 1);
2401 operands[5] = GEN_INT (32 - (me + 1));
2402 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2403 }"
2404 [(set_attr "length" "8")])
2406 (define_insn_and_split "*andsi3_internal7"
2407 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2408 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2409 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2410 (const_int 0)))
2411 (clobber (match_scratch:SI 3 "=r,r"))]
2412 "TARGET_POWERPC64"
2413 "#"
2414 "TARGET_POWERPC64"
2415 [(parallel [(set (match_dup 2)
2416 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2417 (match_dup 5))
2418 (const_int 0)))
2419 (clobber (match_dup 3))])]
2420 "
2421 {
2422 int mb = extract_MB (operands[1]);
2423 int me = extract_ME (operands[1]);
2424 operands[4] = GEN_INT (me + 1);
2425 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2426 }"
2427 [(set_attr "type" "delayed_compare,compare")
2428 (set_attr "length" "4,8")])
2430 (define_insn_and_split "*andsi3_internal8"
2431 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2432 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2433 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2434 (const_int 0)))
2435 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2436 (and:SI (match_dup 1)
2437 (match_dup 2)))]
2438 "TARGET_POWERPC64"
2439 "#"
2440 "TARGET_POWERPC64"
2441 [(parallel [(set (match_dup 3)
2442 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2443 (match_dup 5))
2444 (const_int 0)))
2445 (set (match_dup 0)
2446 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2447 (match_dup 5)))])
2448 (set (match_dup 0)
2449 (rotate:SI (match_dup 0) (match_dup 6)))]
2450 "
2451 {
2452 int mb = extract_MB (operands[2]);
2453 int me = extract_ME (operands[2]);
2454 operands[4] = GEN_INT (me + 1);
2455 operands[6] = GEN_INT (32 - (me + 1));
2456 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2457 }"
2458 [(set_attr "type" "delayed_compare,compare")
2459 (set_attr "length" "8,12")])
2461 (define_expand "iorsi3"
2462 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2463 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2464 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2465 ""
2466 "
2467 {
2468 if (GET_CODE (operands[2]) == CONST_INT
2469 && ! logical_operand (operands[2], SImode))
2470 {
2471 HOST_WIDE_INT value = INTVAL (operands[2]);
2472 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2473 ? operands[0] : gen_reg_rtx (SImode));
2475 emit_insn (gen_iorsi3 (tmp, operands[1],
2476 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2477 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2478 DONE;
2479 }
2480 }")
2482 (define_expand "xorsi3"
2483 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2484 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2486 ""
2487 "
2488 {
2489 if (GET_CODE (operands[2]) == CONST_INT
2490 && ! logical_operand (operands[2], SImode))
2491 {
2492 HOST_WIDE_INT value = INTVAL (operands[2]);
2493 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2494 ? operands[0] : gen_reg_rtx (SImode));
2496 emit_insn (gen_xorsi3 (tmp, operands[1],
2497 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2498 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2499 DONE;
2500 }
2501 }")
2503 (define_insn "*boolsi3_internal1"
2504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2505 (match_operator:SI 3 "boolean_or_operator"
2506 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2507 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2508 ""
2509 "@
2510 %q3 %0,%1,%2
2511 {%q3il|%q3i} %0,%1,%b2
2512 {%q3iu|%q3is} %0,%1,%u2")
2514 (define_insn "*boolsi3_internal2"
2515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2516 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2517 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2518 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2519 (const_int 0)))
2520 (clobber (match_scratch:SI 3 "=r,r"))]
2521 "TARGET_32BIT"
2522 "@
2523 %q4. %3,%1,%2
2524 #"
2525 [(set_attr "type" "compare")
2526 (set_attr "length" "4,8")])
2528 (define_split
2529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2530 (compare:CC (match_operator:SI 4 "boolean_operator"
2531 [(match_operand:SI 1 "gpc_reg_operand" "")
2532 (match_operand:SI 2 "gpc_reg_operand" "")])
2533 (const_int 0)))
2534 (clobber (match_scratch:SI 3 ""))]
2535 "TARGET_32BIT && reload_completed"
2536 [(set (match_dup 3) (match_dup 4))
2537 (set (match_dup 0)
2538 (compare:CC (match_dup 3)
2539 (const_int 0)))]
2540 "")
2542 (define_insn "*boolsi3_internal3"
2543 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2544 (compare:CC (match_operator:SI 4 "boolean_operator"
2545 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2546 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2547 (const_int 0)))
2548 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2549 (match_dup 4))]
2550 "TARGET_32BIT"
2551 "@
2552 %q4. %0,%1,%2
2553 #"
2554 [(set_attr "type" "compare")
2555 (set_attr "length" "4,8")])
2557 (define_split
2558 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2559 (compare:CC (match_operator:SI 4 "boolean_operator"
2560 [(match_operand:SI 1 "gpc_reg_operand" "")
2561 (match_operand:SI 2 "gpc_reg_operand" "")])
2562 (const_int 0)))
2563 (set (match_operand:SI 0 "gpc_reg_operand" "")
2564 (match_dup 4))]
2565 "TARGET_32BIT && reload_completed"
2566 [(set (match_dup 0) (match_dup 4))
2567 (set (match_dup 3)
2568 (compare:CC (match_dup 0)
2569 (const_int 0)))]
2570 "")
2572 ;; Split a logical operation that we can't do in one insn into two insns,
2573 ;; each of which does one 16-bit part. This is used by combine.
2575 (define_split
2576 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2577 (match_operator:SI 3 "boolean_or_operator"
2578 [(match_operand:SI 1 "gpc_reg_operand" "")
2579 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2580 ""
2581 [(set (match_dup 0) (match_dup 4))
2582 (set (match_dup 0) (match_dup 5))]
2583 "
2584 {
2585 rtx i;
2586 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2587 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2588 operands[1], i);
2589 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2590 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2591 operands[0], i);
2592 }")
2594 (define_insn "*boolcsi3_internal1"
2595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2596 (match_operator:SI 3 "boolean_operator"
2597 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2598 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2599 ""
2600 "%q3 %0,%2,%1")
2602 (define_insn "*boolcsi3_internal2"
2603 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2604 (compare:CC (match_operator:SI 4 "boolean_operator"
2605 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2606 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2607 (const_int 0)))
2608 (clobber (match_scratch:SI 3 "=r,r"))]
2609 "TARGET_32BIT"
2610 "@
2611 %q4. %3,%2,%1
2612 #"
2613 [(set_attr "type" "compare")
2614 (set_attr "length" "4,8")])
2616 (define_split
2617 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2618 (compare:CC (match_operator:SI 4 "boolean_operator"
2619 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2620 (match_operand:SI 2 "gpc_reg_operand" "")])
2621 (const_int 0)))
2622 (clobber (match_scratch:SI 3 ""))]
2623 "TARGET_32BIT && reload_completed"
2624 [(set (match_dup 3) (match_dup 4))
2625 (set (match_dup 0)
2626 (compare:CC (match_dup 3)
2627 (const_int 0)))]
2628 "")
2630 (define_insn "*boolcsi3_internal3"
2631 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2632 (compare:CC (match_operator:SI 4 "boolean_operator"
2633 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2634 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2635 (const_int 0)))
2636 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2637 (match_dup 4))]
2638 "TARGET_32BIT"
2639 "@
2640 %q4. %0,%2,%1
2641 #"
2642 [(set_attr "type" "compare")
2643 (set_attr "length" "4,8")])
2645 (define_split
2646 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2647 (compare:CC (match_operator:SI 4 "boolean_operator"
2648 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2649 (match_operand:SI 2 "gpc_reg_operand" "")])
2650 (const_int 0)))
2651 (set (match_operand:SI 0 "gpc_reg_operand" "")
2652 (match_dup 4))]
2653 "TARGET_32BIT && reload_completed"
2654 [(set (match_dup 0) (match_dup 4))
2655 (set (match_dup 3)
2656 (compare:CC (match_dup 0)
2657 (const_int 0)))]
2658 "")
2660 (define_insn "*boolccsi3_internal1"
2661 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2662 (match_operator:SI 3 "boolean_operator"
2663 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2664 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2665 ""
2666 "%q3 %0,%1,%2")
2668 (define_insn "*boolccsi3_internal2"
2669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2670 (compare:CC (match_operator:SI 4 "boolean_operator"
2671 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2672 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2673 (const_int 0)))
2674 (clobber (match_scratch:SI 3 "=r,r"))]
2675 "TARGET_32BIT"
2676 "@
2677 %q4. %3,%1,%2
2678 #"
2679 [(set_attr "type" "compare")
2680 (set_attr "length" "4,8")])
2682 (define_split
2683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2684 (compare:CC (match_operator:SI 4 "boolean_operator"
2685 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2686 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2687 (const_int 0)))
2688 (clobber (match_scratch:SI 3 ""))]
2689 "TARGET_32BIT && reload_completed"
2690 [(set (match_dup 3) (match_dup 4))
2691 (set (match_dup 0)
2692 (compare:CC (match_dup 3)
2693 (const_int 0)))]
2694 "")
2696 (define_insn "*boolccsi3_internal3"
2697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2698 (compare:CC (match_operator:SI 4 "boolean_operator"
2699 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2700 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2701 (const_int 0)))
2702 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2703 (match_dup 4))]
2704 "TARGET_32BIT"
2705 "@
2706 %q4. %0,%1,%2
2707 #"
2708 [(set_attr "type" "compare")
2709 (set_attr "length" "4,8")])
2711 (define_split
2712 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2713 (compare:CC (match_operator:SI 4 "boolean_operator"
2714 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2715 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2716 (const_int 0)))
2717 (set (match_operand:SI 0 "gpc_reg_operand" "")
2718 (match_dup 4))]
2719 "TARGET_32BIT && reload_completed"
2720 [(set (match_dup 0) (match_dup 4))
2721 (set (match_dup 3)
2722 (compare:CC (match_dup 0)
2723 (const_int 0)))]
2724 "")
2726 ;; maskir insn. We need four forms because things might be in arbitrary
2727 ;; orders. Don't define forms that only set CR fields because these
2728 ;; would modify an input register.
2730 (define_insn "*maskir_internal1"
2731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2732 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2733 (match_operand:SI 1 "gpc_reg_operand" "0"))
2734 (and:SI (match_dup 2)
2735 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2736 "TARGET_POWER"
2737 "maskir %0,%3,%2")
2739 (define_insn "*maskir_internal2"
2740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2741 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2742 (match_operand:SI 1 "gpc_reg_operand" "0"))
2743 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2744 (match_dup 2))))]
2745 "TARGET_POWER"
2746 "maskir %0,%3,%2")
2748 (define_insn "*maskir_internal3"
2749 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2750 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2751 (match_operand:SI 3 "gpc_reg_operand" "r"))
2752 (and:SI (not:SI (match_dup 2))
2753 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2754 "TARGET_POWER"
2755 "maskir %0,%3,%2")
2757 (define_insn "*maskir_internal4"
2758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2759 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2760 (match_operand:SI 2 "gpc_reg_operand" "r"))
2761 (and:SI (not:SI (match_dup 2))
2762 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2763 "TARGET_POWER"
2764 "maskir %0,%3,%2")
2766 (define_insn "*maskir_internal5"
2767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2768 (compare:CC
2769 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2770 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2771 (and:SI (match_dup 2)
2772 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2773 (const_int 0)))
2774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2775 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2776 (and:SI (match_dup 2) (match_dup 3))))]
2777 "TARGET_POWER"
2778 "@
2779 maskir. %0,%3,%2
2780 #"
2781 [(set_attr "type" "compare")
2782 (set_attr "length" "4,8")])
2784 (define_split
2785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2786 (compare:CC
2787 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2788 (match_operand:SI 1 "gpc_reg_operand" ""))
2789 (and:SI (match_dup 2)
2790 (match_operand:SI 3 "gpc_reg_operand" "")))
2791 (const_int 0)))
2792 (set (match_operand:SI 0 "gpc_reg_operand" "")
2793 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2794 (and:SI (match_dup 2) (match_dup 3))))]
2795 "TARGET_POWER && reload_completed"
2796 [(set (match_dup 0)
2797 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2798 (and:SI (match_dup 2) (match_dup 3))))
2799 (set (match_dup 4)
2800 (compare:CC (match_dup 0)
2801 (const_int 0)))]
2802 "")
2804 (define_insn "*maskir_internal6"
2805 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2806 (compare:CC
2807 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2808 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2809 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2810 (match_dup 2)))
2811 (const_int 0)))
2812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2813 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2814 (and:SI (match_dup 3) (match_dup 2))))]
2815 "TARGET_POWER"
2816 "@
2817 maskir. %0,%3,%2
2818 #"
2819 [(set_attr "type" "compare")
2820 (set_attr "length" "4,8")])
2822 (define_split
2823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2824 (compare:CC
2825 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2826 (match_operand:SI 1 "gpc_reg_operand" ""))
2827 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2828 (match_dup 2)))
2829 (const_int 0)))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "")
2831 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2832 (and:SI (match_dup 3) (match_dup 2))))]
2833 "TARGET_POWER && reload_completed"
2834 [(set (match_dup 0)
2835 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2836 (and:SI (match_dup 3) (match_dup 2))))
2837 (set (match_dup 4)
2838 (compare:CC (match_dup 0)
2839 (const_int 0)))]
2840 "")
2842 (define_insn "*maskir_internal7"
2843 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2844 (compare:CC
2845 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2846 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2847 (and:SI (not:SI (match_dup 2))
2848 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2849 (const_int 0)))
2850 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2851 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2852 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2853 "TARGET_POWER"
2854 "@
2855 maskir. %0,%3,%2
2856 #"
2857 [(set_attr "type" "compare")
2858 (set_attr "length" "4,8")])
2860 (define_split
2861 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2862 (compare:CC
2863 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2864 (match_operand:SI 3 "gpc_reg_operand" ""))
2865 (and:SI (not:SI (match_dup 2))
2866 (match_operand:SI 1 "gpc_reg_operand" "")))
2867 (const_int 0)))
2868 (set (match_operand:SI 0 "gpc_reg_operand" "")
2869 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2870 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2871 "TARGET_POWER && reload_completed"
2872 [(set (match_dup 0)
2873 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2874 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2875 (set (match_dup 4)
2876 (compare:CC (match_dup 0)
2877 (const_int 0)))]
2878 "")
2880 (define_insn "*maskir_internal8"
2881 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2882 (compare:CC
2883 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2884 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2885 (and:SI (not:SI (match_dup 2))
2886 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2887 (const_int 0)))
2888 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2889 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2890 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2891 "TARGET_POWER"
2892 "@
2893 maskir. %0,%3,%2
2894 #"
2895 [(set_attr "type" "compare")
2896 (set_attr "length" "4,8")])
2898 (define_split
2899 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2900 (compare:CC
2901 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2902 (match_operand:SI 2 "gpc_reg_operand" ""))
2903 (and:SI (not:SI (match_dup 2))
2904 (match_operand:SI 1 "gpc_reg_operand" "")))
2905 (const_int 0)))
2906 (set (match_operand:SI 0 "gpc_reg_operand" "")
2907 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2908 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2909 "TARGET_POWER && reload_completed"
2910 [(set (match_dup 0)
2911 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2912 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2913 (set (match_dup 4)
2914 (compare:CC (match_dup 0)
2915 (const_int 0)))]
2916 "")
2917 \f
2918 ;; Rotate and shift insns, in all their variants. These support shifts,
2919 ;; field inserts and extracts, and various combinations thereof.
2920 (define_expand "insv"
2921 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2922 (match_operand:SI 1 "const_int_operand" "")
2923 (match_operand:SI 2 "const_int_operand" ""))
2924 (match_operand 3 "gpc_reg_operand" ""))]
2925 ""
2926 "
2927 {
2928 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2929 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2930 compiler if the address of the structure is taken later. */
2931 if (GET_CODE (operands[0]) == SUBREG
2932 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2933 FAIL;
2935 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2936 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2937 else
2938 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2939 DONE;
2940 }")
2942 (define_insn "insvsi"
2943 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2944 (match_operand:SI 1 "const_int_operand" "i")
2945 (match_operand:SI 2 "const_int_operand" "i"))
2946 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2947 ""
2948 "*
2949 {
2950 int start = INTVAL (operands[2]) & 31;
2951 int size = INTVAL (operands[1]) & 31;
2953 operands[4] = GEN_INT (32 - start - size);
2954 operands[1] = GEN_INT (start + size - 1);
2955 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2956 }"
2957 [(set_attr "type" "insert_word")])
2959 (define_insn "*insvsi_internal1"
2960 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2961 (match_operand:SI 1 "const_int_operand" "i")
2962 (match_operand:SI 2 "const_int_operand" "i"))
2963 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2964 (match_operand:SI 4 "const_int_operand" "i")))]
2965 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2966 "*
2967 {
2968 int shift = INTVAL (operands[4]) & 31;
2969 int start = INTVAL (operands[2]) & 31;
2970 int size = INTVAL (operands[1]) & 31;
2972 operands[4] = GEN_INT (shift - start - size);
2973 operands[1] = GEN_INT (start + size - 1);
2974 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2975 }"
2976 [(set_attr "type" "insert_word")])
2978 (define_insn "*insvsi_internal2"
2979 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2980 (match_operand:SI 1 "const_int_operand" "i")
2981 (match_operand:SI 2 "const_int_operand" "i"))
2982 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2983 (match_operand:SI 4 "const_int_operand" "i")))]
2984 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2985 "*
2986 {
2987 int shift = INTVAL (operands[4]) & 31;
2988 int start = INTVAL (operands[2]) & 31;
2989 int size = INTVAL (operands[1]) & 31;
2991 operands[4] = GEN_INT (32 - shift - start - size);
2992 operands[1] = GEN_INT (start + size - 1);
2993 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2994 }"
2995 [(set_attr "type" "insert_word")])
2997 (define_insn "*insvsi_internal3"
2998 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2999 (match_operand:SI 1 "const_int_operand" "i")
3000 (match_operand:SI 2 "const_int_operand" "i"))
3001 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3002 (match_operand:SI 4 "const_int_operand" "i")))]
3003 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3004 "*
3005 {
3006 int shift = INTVAL (operands[4]) & 31;
3007 int start = INTVAL (operands[2]) & 31;
3008 int size = INTVAL (operands[1]) & 31;
3010 operands[4] = GEN_INT (32 - shift - start - size);
3011 operands[1] = GEN_INT (start + size - 1);
3012 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3013 }"
3014 [(set_attr "type" "insert_word")])
3016 (define_insn "*insvsi_internal4"
3017 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3018 (match_operand:SI 1 "const_int_operand" "i")
3019 (match_operand:SI 2 "const_int_operand" "i"))
3020 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3021 (match_operand:SI 4 "const_int_operand" "i")
3022 (match_operand:SI 5 "const_int_operand" "i")))]
3023 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3024 "*
3025 {
3026 int extract_start = INTVAL (operands[5]) & 31;
3027 int extract_size = INTVAL (operands[4]) & 31;
3028 int insert_start = INTVAL (operands[2]) & 31;
3029 int insert_size = INTVAL (operands[1]) & 31;
3031 /* Align extract field with insert field */
3032 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3033 operands[1] = GEN_INT (insert_start + insert_size - 1);
3034 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3035 }"
3036 [(set_attr "type" "insert_word")])
3038 (define_insn "insvdi"
3039 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3040 (match_operand:SI 1 "const_int_operand" "i")
3041 (match_operand:SI 2 "const_int_operand" "i"))
3042 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3043 "TARGET_POWERPC64"
3044 "*
3045 {
3046 int start = INTVAL (operands[2]) & 63;
3047 int size = INTVAL (operands[1]) & 63;
3049 operands[1] = GEN_INT (64 - start - size);
3050 return \"rldimi %0,%3,%H1,%H2\";
3051 }")
3053 (define_expand "extzv"
3054 [(set (match_operand 0 "gpc_reg_operand" "")
3055 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3056 (match_operand:SI 2 "const_int_operand" "")
3057 (match_operand:SI 3 "const_int_operand" "")))]
3058 ""
3059 "
3060 {
3061 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3062 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3063 compiler if the address of the structure is taken later. */
3064 if (GET_CODE (operands[0]) == SUBREG
3065 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3066 FAIL;
3068 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3069 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3070 else
3071 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3072 DONE;
3073 }")
3075 (define_insn "extzvsi"
3076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3077 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3078 (match_operand:SI 2 "const_int_operand" "i")
3079 (match_operand:SI 3 "const_int_operand" "i")))]
3080 ""
3081 "*
3082 {
3083 int start = INTVAL (operands[3]) & 31;
3084 int size = INTVAL (operands[2]) & 31;
3086 if (start + size >= 32)
3087 operands[3] = const0_rtx;
3088 else
3089 operands[3] = GEN_INT (start + size);
3090 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3091 }")
3093 (define_insn "*extzvsi_internal1"
3094 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3095 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3096 (match_operand:SI 2 "const_int_operand" "i,i")
3097 (match_operand:SI 3 "const_int_operand" "i,i"))
3098 (const_int 0)))
3099 (clobber (match_scratch:SI 4 "=r,r"))]
3100 ""
3101 "*
3102 {
3103 int start = INTVAL (operands[3]) & 31;
3104 int size = INTVAL (operands[2]) & 31;
3106 /* Force split for non-cc0 compare. */
3107 if (which_alternative == 1)
3108 return \"#\";
3110 /* If the bit-field being tested fits in the upper or lower half of a
3111 word, it is possible to use andiu. or andil. to test it. This is
3112 useful because the condition register set-use delay is smaller for
3113 andi[ul]. than for rlinm. This doesn't work when the starting bit
3114 position is 0 because the LT and GT bits may be set wrong. */
3116 if ((start > 0 && start + size <= 16) || start >= 16)
3117 {
3118 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3119 - (1 << (16 - (start & 15) - size))));
3120 if (start < 16)
3121 return \"{andiu.|andis.} %4,%1,%3\";
3122 else
3123 return \"{andil.|andi.} %4,%1,%3\";
3124 }
3126 if (start + size >= 32)
3127 operands[3] = const0_rtx;
3128 else
3129 operands[3] = GEN_INT (start + size);
3130 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3131 }"
3132 [(set_attr "type" "compare")
3133 (set_attr "length" "4,8")])
3135 (define_split
3136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3137 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3138 (match_operand:SI 2 "const_int_operand" "")
3139 (match_operand:SI 3 "const_int_operand" ""))
3140 (const_int 0)))
3141 (clobber (match_scratch:SI 4 ""))]
3142 "reload_completed"
3143 [(set (match_dup 4)
3144 (zero_extract:SI (match_dup 1) (match_dup 2)
3145 (match_dup 3)))
3146 (set (match_dup 0)
3147 (compare:CC (match_dup 4)
3148 (const_int 0)))]
3149 "")
3151 (define_insn "*extzvsi_internal2"
3152 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3153 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3154 (match_operand:SI 2 "const_int_operand" "i,i")
3155 (match_operand:SI 3 "const_int_operand" "i,i"))
3156 (const_int 0)))
3157 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3158 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3159 ""
3160 "*
3161 {
3162 int start = INTVAL (operands[3]) & 31;
3163 int size = INTVAL (operands[2]) & 31;
3165 /* Force split for non-cc0 compare. */
3166 if (which_alternative == 1)
3167 return \"#\";
3169 /* Since we are using the output value, we can't ignore any need for
3170 a shift. The bit-field must end at the LSB. */
3171 if (start >= 16 && start + size == 32)
3172 {
3173 operands[3] = GEN_INT ((1 << size) - 1);
3174 return \"{andil.|andi.} %0,%1,%3\";
3175 }
3177 if (start + size >= 32)
3178 operands[3] = const0_rtx;
3179 else
3180 operands[3] = GEN_INT (start + size);
3181 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3182 }"
3183 [(set_attr "type" "compare")
3184 (set_attr "length" "4,8")])
3186 (define_split
3187 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3188 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3189 (match_operand:SI 2 "const_int_operand" "")
3190 (match_operand:SI 3 "const_int_operand" ""))
3191 (const_int 0)))
3192 (set (match_operand:SI 0 "gpc_reg_operand" "")
3193 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3194 "reload_completed"
3195 [(set (match_dup 0)
3196 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3197 (set (match_dup 4)
3198 (compare:CC (match_dup 0)
3199 (const_int 0)))]
3200 "")
3202 (define_insn "extzvdi"
3203 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3204 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3205 (match_operand:SI 2 "const_int_operand" "i")
3206 (match_operand:SI 3 "const_int_operand" "i")))]
3207 "TARGET_POWERPC64"
3208 "*
3209 {
3210 int start = INTVAL (operands[3]) & 63;
3211 int size = INTVAL (operands[2]) & 63;
3213 if (start + size >= 64)
3214 operands[3] = const0_rtx;
3215 else
3216 operands[3] = GEN_INT (start + size);
3217 operands[2] = GEN_INT (64 - size);
3218 return \"rldicl %0,%1,%3,%2\";
3219 }")
3221 (define_insn "*extzvdi_internal1"
3222 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3223 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3224 (match_operand:SI 2 "const_int_operand" "i")
3225 (match_operand:SI 3 "const_int_operand" "i"))
3226 (const_int 0)))
3227 (clobber (match_scratch:DI 4 "=r"))]
3228 "TARGET_64BIT"
3229 "*
3230 {
3231 int start = INTVAL (operands[3]) & 63;
3232 int size = INTVAL (operands[2]) & 63;
3234 if (start + size >= 64)
3235 operands[3] = const0_rtx;
3236 else
3237 operands[3] = GEN_INT (start + size);
3238 operands[2] = GEN_INT (64 - size);
3239 return \"rldicl. %4,%1,%3,%2\";
3240 }")
3242 (define_insn "*extzvdi_internal2"
3243 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3244 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3245 (match_operand:SI 2 "const_int_operand" "i")
3246 (match_operand:SI 3 "const_int_operand" "i"))
3247 (const_int 0)))
3248 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3249 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3250 "TARGET_64BIT"
3251 "*
3252 {
3253 int start = INTVAL (operands[3]) & 63;
3254 int size = INTVAL (operands[2]) & 63;
3256 if (start + size >= 64)
3257 operands[3] = const0_rtx;
3258 else
3259 operands[3] = GEN_INT (start + size);
3260 operands[2] = GEN_INT (64 - size);
3261 return \"rldicl. %0,%1,%3,%2\";
3262 }")
3264 (define_insn "rotlsi3"
3265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3266 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3267 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3268 ""
3269 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3271 (define_insn "*rotlsi3_internal2"
3272 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3273 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3274 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3275 (const_int 0)))
3276 (clobber (match_scratch:SI 3 "=r,r"))]
3277 ""
3278 "@
3279 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3280 #"
3281 [(set_attr "type" "delayed_compare")
3282 (set_attr "length" "4,8")])
3284 (define_split
3285 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3286 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3287 (match_operand:SI 2 "reg_or_cint_operand" ""))
3288 (const_int 0)))
3289 (clobber (match_scratch:SI 3 ""))]
3290 "reload_completed"
3291 [(set (match_dup 3)
3292 (rotate:SI (match_dup 1) (match_dup 2)))
3293 (set (match_dup 0)
3294 (compare:CC (match_dup 3)
3295 (const_int 0)))]
3296 "")
3298 (define_insn "*rotlsi3_internal3"
3299 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3300 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3301 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3302 (const_int 0)))
3303 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3304 (rotate:SI (match_dup 1) (match_dup 2)))]
3305 ""
3306 "@
3307 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3308 #"
3309 [(set_attr "type" "delayed_compare")
3310 (set_attr "length" "4,8")])
3312 (define_split
3313 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3314 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3315 (match_operand:SI 2 "reg_or_cint_operand" ""))
3316 (const_int 0)))
3317 (set (match_operand:SI 0 "gpc_reg_operand" "")
3318 (rotate:SI (match_dup 1) (match_dup 2)))]
3319 "reload_completed"
3320 [(set (match_dup 0)
3321 (rotate:SI (match_dup 1) (match_dup 2)))
3322 (set (match_dup 3)
3323 (compare:CC (match_dup 0)
3324 (const_int 0)))]
3325 "")
3327 (define_insn "*rotlsi3_internal4"
3328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3329 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3330 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3331 (match_operand:SI 3 "mask_operand" "n")))]
3332 ""
3333 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3335 (define_insn "*rotlsi3_internal5"
3336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3337 (compare:CC (and:SI
3338 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3339 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3340 (match_operand:SI 3 "mask_operand" "n,n"))
3341 (const_int 0)))
3342 (clobber (match_scratch:SI 4 "=r,r"))]
3343 ""
3344 "@
3345 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3346 #"
3347 [(set_attr "type" "delayed_compare")
3348 (set_attr "length" "4,8")])
3350 (define_split
3351 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3352 (compare:CC (and:SI
3353 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3354 (match_operand:SI 2 "reg_or_cint_operand" ""))
3355 (match_operand:SI 3 "mask_operand" ""))
3356 (const_int 0)))
3357 (clobber (match_scratch:SI 4 ""))]
3358 "reload_completed"
3359 [(set (match_dup 4)
3360 (and:SI (rotate:SI (match_dup 1)
3361 (match_dup 2))
3362 (match_dup 3)))
3363 (set (match_dup 0)
3364 (compare:CC (match_dup 4)
3365 (const_int 0)))]
3366 "")
3368 (define_insn "*rotlsi3_internal6"
3369 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3370 (compare:CC (and:SI
3371 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3372 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3373 (match_operand:SI 3 "mask_operand" "n,n"))
3374 (const_int 0)))
3375 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3376 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3377 ""
3378 "@
3379 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3380 #"
3381 [(set_attr "type" "delayed_compare")
3382 (set_attr "length" "4,8")])
3384 (define_split
3385 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3386 (compare:CC (and:SI
3387 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3388 (match_operand:SI 2 "reg_or_cint_operand" ""))
3389 (match_operand:SI 3 "mask_operand" ""))
3390 (const_int 0)))
3391 (set (match_operand:SI 0 "gpc_reg_operand" "")
3392 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3393 "reload_completed"
3394 [(set (match_dup 0)
3395 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3396 (set (match_dup 4)
3397 (compare:CC (match_dup 0)
3398 (const_int 0)))]
3399 "")
3401 (define_insn "*rotlsi3_internal7"
3402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3403 (zero_extend:SI
3404 (subreg:QI
3405 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3406 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3407 ""
3408 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3410 (define_insn "*rotlsi3_internal8"
3411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3412 (compare:CC (zero_extend:SI
3413 (subreg:QI
3414 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3415 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3416 (const_int 0)))
3417 (clobber (match_scratch:SI 3 "=r,r"))]
3418 ""
3419 "@
3420 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3421 #"
3422 [(set_attr "type" "delayed_compare")
3423 (set_attr "length" "4,8")])
3425 (define_split
3426 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3427 (compare:CC (zero_extend:SI
3428 (subreg:QI
3429 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3430 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3431 (const_int 0)))
3432 (clobber (match_scratch:SI 3 ""))]
3433 "reload_completed"
3434 [(set (match_dup 3)
3435 (zero_extend:SI (subreg:QI
3436 (rotate:SI (match_dup 1)
3437 (match_dup 2)) 0)))
3438 (set (match_dup 0)
3439 (compare:CC (match_dup 3)
3440 (const_int 0)))]
3441 "")
3443 (define_insn "*rotlsi3_internal9"
3444 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3445 (compare:CC (zero_extend:SI
3446 (subreg:QI
3447 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3448 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3449 (const_int 0)))
3450 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3451 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3452 ""
3453 "@
3454 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3455 #"
3456 [(set_attr "type" "delayed_compare")
3457 (set_attr "length" "4,8")])
3459 (define_split
3460 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3461 (compare:CC (zero_extend:SI
3462 (subreg:QI
3463 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3464 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3465 (const_int 0)))
3466 (set (match_operand:SI 0 "gpc_reg_operand" "")
3467 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3468 "reload_completed"
3469 [(set (match_dup 0)
3470 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3471 (set (match_dup 3)
3472 (compare:CC (match_dup 0)
3473 (const_int 0)))]
3474 "")
3476 (define_insn "*rotlsi3_internal10"
3477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3478 (zero_extend:SI
3479 (subreg:HI
3480 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3481 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3482 ""
3483 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3485 (define_insn "*rotlsi3_internal11"
3486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3487 (compare:CC (zero_extend:SI
3488 (subreg:HI
3489 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3490 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3491 (const_int 0)))
3492 (clobber (match_scratch:SI 3 "=r,r"))]
3493 ""
3494 "@
3495 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3496 #"
3497 [(set_attr "type" "delayed_compare")
3498 (set_attr "length" "4,8")])
3500 (define_split
3501 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3502 (compare:CC (zero_extend:SI
3503 (subreg:HI
3504 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3505 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3506 (const_int 0)))
3507 (clobber (match_scratch:SI 3 ""))]
3508 "reload_completed"
3509 [(set (match_dup 3)
3510 (zero_extend:SI (subreg:HI
3511 (rotate:SI (match_dup 1)
3512 (match_dup 2)) 0)))
3513 (set (match_dup 0)
3514 (compare:CC (match_dup 3)
3515 (const_int 0)))]
3516 "")
3518 (define_insn "*rotlsi3_internal12"
3519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3520 (compare:CC (zero_extend:SI
3521 (subreg:HI
3522 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3523 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3524 (const_int 0)))
3525 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3526 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3527 ""
3528 "@
3529 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3530 #"
3531 [(set_attr "type" "delayed_compare")
3532 (set_attr "length" "4,8")])
3534 (define_split
3535 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3536 (compare:CC (zero_extend:SI
3537 (subreg:HI
3538 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3539 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3540 (const_int 0)))
3541 (set (match_operand:SI 0 "gpc_reg_operand" "")
3542 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3543 "reload_completed"
3544 [(set (match_dup 0)
3545 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3546 (set (match_dup 3)
3547 (compare:CC (match_dup 0)
3548 (const_int 0)))]
3549 "")
3551 ;; Note that we use "sle." instead of "sl." so that we can set
3552 ;; SHIFT_COUNT_TRUNCATED.
3554 (define_expand "ashlsi3"
3555 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3556 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3557 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3558 ""
3559 "
3560 {
3561 if (TARGET_POWER)
3562 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3563 else
3564 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3565 DONE;
3566 }")
3568 (define_insn "ashlsi3_power"
3569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3570 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3571 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3572 (clobber (match_scratch:SI 3 "=q,X"))]
3573 "TARGET_POWER"
3574 "@
3575 sle %0,%1,%2
3576 {sli|slwi} %0,%1,%h2")
3578 (define_insn "ashlsi3_no_power"
3579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3580 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3581 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3582 "! TARGET_POWER"
3583 "{sl|slw}%I2 %0,%1,%h2")
3585 (define_insn ""
3586 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3587 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3588 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3589 (const_int 0)))
3590 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3591 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3592 "TARGET_POWER"
3593 "@
3594 sle. %3,%1,%2
3595 {sli.|slwi.} %3,%1,%h2
3596 #
3597 #"
3598 [(set_attr "type" "delayed_compare")
3599 (set_attr "length" "4,4,8,8")])
3601 (define_split
3602 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3603 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3604 (match_operand:SI 2 "reg_or_cint_operand" ""))
3605 (const_int 0)))
3606 (clobber (match_scratch:SI 3 ""))
3607 (clobber (match_scratch:SI 4 ""))]
3608 "TARGET_POWER && reload_completed"
3609 [(parallel [(set (match_dup 3)
3610 (ashift:SI (match_dup 1) (match_dup 2)))
3611 (clobber (match_dup 4))])
3612 (set (match_dup 0)
3613 (compare:CC (match_dup 3)
3614 (const_int 0)))]
3615 "")
3617 (define_insn ""
3618 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3619 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3620 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3621 (const_int 0)))
3622 (clobber (match_scratch:SI 3 "=r,r"))]
3623 "! TARGET_POWER && TARGET_32BIT"
3624 "@
3625 {sl|slw}%I2. %3,%1,%h2
3626 #"
3627 [(set_attr "type" "delayed_compare")
3628 (set_attr "length" "4,8")])
3630 (define_split
3631 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3632 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3633 (match_operand:SI 2 "reg_or_cint_operand" ""))
3634 (const_int 0)))
3635 (clobber (match_scratch:SI 3 ""))]
3636 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3637 [(set (match_dup 3)
3638 (ashift:SI (match_dup 1) (match_dup 2)))
3639 (set (match_dup 0)
3640 (compare:CC (match_dup 3)
3641 (const_int 0)))]
3642 "")
3644 (define_insn ""
3645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3646 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3647 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3648 (const_int 0)))
3649 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3650 (ashift:SI (match_dup 1) (match_dup 2)))
3651 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3652 "TARGET_POWER"
3653 "@
3654 sle. %0,%1,%2
3655 {sli.|slwi.} %0,%1,%h2
3656 #
3657 #"
3658 [(set_attr "type" "delayed_compare")
3659 (set_attr "length" "4,4,8,8")])
3661 (define_split
3662 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3663 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3664 (match_operand:SI 2 "reg_or_cint_operand" ""))
3665 (const_int 0)))
3666 (set (match_operand:SI 0 "gpc_reg_operand" "")
3667 (ashift:SI (match_dup 1) (match_dup 2)))
3668 (clobber (match_scratch:SI 4 ""))]
3669 "TARGET_POWER && reload_completed"
3670 [(parallel [(set (match_dup 0)
3671 (ashift:SI (match_dup 1) (match_dup 2)))
3672 (clobber (match_dup 4))])
3673 (set (match_dup 3)
3674 (compare:CC (match_dup 0)
3675 (const_int 0)))]
3676 "")
3678 (define_insn ""
3679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3680 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3681 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3682 (const_int 0)))
3683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3684 (ashift:SI (match_dup 1) (match_dup 2)))]
3685 "! TARGET_POWER && TARGET_32BIT"
3686 "@
3687 {sl|slw}%I2. %0,%1,%h2
3688 #"
3689 [(set_attr "type" "delayed_compare")
3690 (set_attr "length" "4,8")])
3692 (define_split
3693 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3694 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3695 (match_operand:SI 2 "reg_or_cint_operand" ""))
3696 (const_int 0)))
3697 (set (match_operand:SI 0 "gpc_reg_operand" "")
3698 (ashift:SI (match_dup 1) (match_dup 2)))]
3699 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3700 [(set (match_dup 0)
3701 (ashift:SI (match_dup 1) (match_dup 2)))
3702 (set (match_dup 3)
3703 (compare:CC (match_dup 0)
3704 (const_int 0)))]
3705 "")
3707 (define_insn ""
3708 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3709 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3710 (match_operand:SI 2 "const_int_operand" "i"))
3711 (match_operand:SI 3 "mask_operand" "n")))]
3712 "includes_lshift_p (operands[2], operands[3])"
3713 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3715 (define_insn ""
3716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3717 (compare:CC
3718 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3719 (match_operand:SI 2 "const_int_operand" "i,i"))
3720 (match_operand:SI 3 "mask_operand" "n,n"))
3721 (const_int 0)))
3722 (clobber (match_scratch:SI 4 "=r,r"))]
3723 "includes_lshift_p (operands[2], operands[3])"
3724 "@
3725 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3726 #"
3727 [(set_attr "type" "delayed_compare")
3728 (set_attr "length" "4,8")])
3730 (define_split
3731 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3732 (compare:CC
3733 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3734 (match_operand:SI 2 "const_int_operand" ""))
3735 (match_operand:SI 3 "mask_operand" ""))
3736 (const_int 0)))
3737 (clobber (match_scratch:SI 4 ""))]
3738 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3739 [(set (match_dup 4)
3740 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3741 (match_dup 3)))
3742 (set (match_dup 0)
3743 (compare:CC (match_dup 4)
3744 (const_int 0)))]
3745 "")
3747 (define_insn ""
3748 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3749 (compare:CC
3750 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3751 (match_operand:SI 2 "const_int_operand" "i,i"))
3752 (match_operand:SI 3 "mask_operand" "n,n"))
3753 (const_int 0)))
3754 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3755 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3756 "includes_lshift_p (operands[2], operands[3])"
3757 "@
3758 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3759 #"
3760 [(set_attr "type" "delayed_compare")
3761 (set_attr "length" "4,8")])
3763 (define_split
3764 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3765 (compare:CC
3766 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3767 (match_operand:SI 2 "const_int_operand" ""))
3768 (match_operand:SI 3 "mask_operand" ""))
3769 (const_int 0)))
3770 (set (match_operand:SI 0 "gpc_reg_operand" "")
3771 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3772 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3773 [(set (match_dup 0)
3774 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3775 (set (match_dup 4)
3776 (compare:CC (match_dup 0)
3777 (const_int 0)))]
3778 "")
3780 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3781 ;; "sli x,x,0".
3782 (define_expand "lshrsi3"
3783 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3784 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3785 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3786 ""
3787 "
3788 {
3789 if (TARGET_POWER)
3790 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3791 else
3792 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3793 DONE;
3794 }")
3796 (define_insn "lshrsi3_power"
3797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3798 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3799 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3800 (clobber (match_scratch:SI 3 "=q,X,X"))]
3801 "TARGET_POWER"
3802 "@
3803 sre %0,%1,%2
3804 mr %0,%1
3805 {s%A2i|s%A2wi} %0,%1,%h2")
3807 (define_insn "lshrsi3_no_power"
3808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3809 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3810 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3811 "! TARGET_POWER"
3812 "@
3813 mr %0,%1
3814 {sr|srw}%I2 %0,%1,%h2")
3816 (define_insn ""
3817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3818 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3819 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3820 (const_int 0)))
3821 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3822 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3823 "TARGET_POWER"
3824 "@
3825 sre. %3,%1,%2
3826 mr. %1,%1
3827 {s%A2i.|s%A2wi.} %3,%1,%h2
3828 #
3829 #
3830 #"
3831 [(set_attr "type" "delayed_compare")
3832 (set_attr "length" "4,4,4,8,8,8")])
3834 (define_split
3835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3836 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3837 (match_operand:SI 2 "reg_or_cint_operand" ""))
3838 (const_int 0)))
3839 (clobber (match_scratch:SI 3 ""))
3840 (clobber (match_scratch:SI 4 ""))]
3841 "TARGET_POWER && reload_completed"
3842 [(parallel [(set (match_dup 3)
3843 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3844 (clobber (match_dup 4))])
3845 (set (match_dup 0)
3846 (compare:CC (match_dup 3)
3847 (const_int 0)))]
3848 "")
3850 (define_insn ""
3851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3852 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3853 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3854 (const_int 0)))
3855 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3856 "! TARGET_POWER && TARGET_32BIT"
3857 "@
3858 mr. %1,%1
3859 {sr|srw}%I2. %3,%1,%h2
3860 #
3861 #"
3862 [(set_attr "type" "delayed_compare")
3863 (set_attr "length" "4,4,8,8")])
3865 (define_split
3866 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3867 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3868 (match_operand:SI 2 "reg_or_cint_operand" ""))
3869 (const_int 0)))
3870 (clobber (match_scratch:SI 3 ""))]
3871 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3872 [(set (match_dup 3)
3873 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3874 (set (match_dup 0)
3875 (compare:CC (match_dup 3)
3876 (const_int 0)))]
3877 "")
3879 (define_insn ""
3880 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3881 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3882 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3883 (const_int 0)))
3884 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3885 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3886 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3887 "TARGET_POWER"
3888 "@
3889 sre. %0,%1,%2
3890 mr. %0,%1
3891 {s%A2i.|s%A2wi.} %0,%1,%h2
3892 #
3893 #
3894 #"
3895 [(set_attr "type" "delayed_compare")
3896 (set_attr "length" "4,4,4,8,8,8")])
3898 (define_split
3899 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3900 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3901 (match_operand:SI 2 "reg_or_cint_operand" ""))
3902 (const_int 0)))
3903 (set (match_operand:SI 0 "gpc_reg_operand" "")
3904 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3905 (clobber (match_scratch:SI 4 ""))]
3906 "TARGET_POWER && reload_completed"
3907 [(parallel [(set (match_dup 0)
3908 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3909 (clobber (match_dup 4))])
3910 (set (match_dup 3)
3911 (compare:CC (match_dup 0)
3912 (const_int 0)))]
3913 "")
3915 (define_insn ""
3916 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3917 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3918 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3919 (const_int 0)))
3920 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3921 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3922 "! TARGET_POWER && TARGET_32BIT"
3923 "@
3924 mr. %0,%1
3925 {sr|srw}%I2. %0,%1,%h2
3926 #
3927 #"
3928 [(set_attr "type" "delayed_compare")
3929 (set_attr "length" "4,4,8,8")])
3931 (define_split
3932 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3933 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3934 (match_operand:SI 2 "reg_or_cint_operand" ""))
3935 (const_int 0)))
3936 (set (match_operand:SI 0 "gpc_reg_operand" "")
3937 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3938 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3939 [(set (match_dup 0)
3940 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3941 (set (match_dup 3)
3942 (compare:CC (match_dup 0)
3943 (const_int 0)))]
3944 "")
3946 (define_insn ""
3947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3948 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3949 (match_operand:SI 2 "const_int_operand" "i"))
3950 (match_operand:SI 3 "mask_operand" "n")))]
3951 "includes_rshift_p (operands[2], operands[3])"
3952 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3954 (define_insn ""
3955 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3956 (compare:CC
3957 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "const_int_operand" "i,i"))
3959 (match_operand:SI 3 "mask_operand" "n,n"))
3960 (const_int 0)))
3961 (clobber (match_scratch:SI 4 "=r,r"))]
3962 "includes_rshift_p (operands[2], operands[3])"
3963 "@
3964 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3965 #"
3966 [(set_attr "type" "delayed_compare")
3967 (set_attr "length" "4,8")])
3969 (define_split
3970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3971 (compare:CC
3972 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3973 (match_operand:SI 2 "const_int_operand" ""))
3974 (match_operand:SI 3 "mask_operand" ""))
3975 (const_int 0)))
3976 (clobber (match_scratch:SI 4 ""))]
3977 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3978 [(set (match_dup 4)
3979 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3980 (match_dup 3)))
3981 (set (match_dup 0)
3982 (compare:CC (match_dup 4)
3983 (const_int 0)))]
3984 "")
3986 (define_insn ""
3987 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3988 (compare:CC
3989 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3990 (match_operand:SI 2 "const_int_operand" "i,i"))
3991 (match_operand:SI 3 "mask_operand" "n,n"))
3992 (const_int 0)))
3993 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3994 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3995 "includes_rshift_p (operands[2], operands[3])"
3996 "@
3997 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3998 #"
3999 [(set_attr "type" "delayed_compare")
4000 (set_attr "length" "4,8")])
4002 (define_split
4003 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4004 (compare:CC
4005 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4006 (match_operand:SI 2 "const_int_operand" ""))
4007 (match_operand:SI 3 "mask_operand" ""))
4008 (const_int 0)))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "")
4010 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4011 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4012 [(set (match_dup 0)
4013 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4014 (set (match_dup 4)
4015 (compare:CC (match_dup 0)
4016 (const_int 0)))]
4017 "")
4019 (define_insn ""
4020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4021 (zero_extend:SI
4022 (subreg:QI
4023 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4024 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4025 "includes_rshift_p (operands[2], GEN_INT (255))"
4026 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4028 (define_insn ""
4029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4030 (compare:CC
4031 (zero_extend:SI
4032 (subreg:QI
4033 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4034 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4035 (const_int 0)))
4036 (clobber (match_scratch:SI 3 "=r,r"))]
4037 "includes_rshift_p (operands[2], GEN_INT (255))"
4038 "@
4039 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4040 #"
4041 [(set_attr "type" "delayed_compare")
4042 (set_attr "length" "4,8")])
4044 (define_split
4045 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4046 (compare:CC
4047 (zero_extend:SI
4048 (subreg:QI
4049 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4050 (match_operand:SI 2 "const_int_operand" "")) 0))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 ""))]
4053 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4054 [(set (match_dup 3)
4055 (zero_extend:SI (subreg:QI
4056 (lshiftrt:SI (match_dup 1)
4057 (match_dup 2)) 0)))
4058 (set (match_dup 0)
4059 (compare:CC (match_dup 3)
4060 (const_int 0)))]
4061 "")
4063 (define_insn ""
4064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4065 (compare:CC
4066 (zero_extend:SI
4067 (subreg:QI
4068 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4069 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4070 (const_int 0)))
4071 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4072 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4073 "includes_rshift_p (operands[2], GEN_INT (255))"
4074 "@
4075 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4076 #"
4077 [(set_attr "type" "delayed_compare")
4078 (set_attr "length" "4,8")])
4080 (define_split
4081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4082 (compare:CC
4083 (zero_extend:SI
4084 (subreg:QI
4085 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4086 (match_operand:SI 2 "const_int_operand" "")) 0))
4087 (const_int 0)))
4088 (set (match_operand:SI 0 "gpc_reg_operand" "")
4089 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4090 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4091 [(set (match_dup 0)
4092 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4093 (set (match_dup 3)
4094 (compare:CC (match_dup 0)
4095 (const_int 0)))]
4096 "")
4098 (define_insn ""
4099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4100 (zero_extend:SI
4101 (subreg:HI
4102 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4103 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4104 "includes_rshift_p (operands[2], GEN_INT (65535))"
4105 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4107 (define_insn ""
4108 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4109 (compare:CC
4110 (zero_extend:SI
4111 (subreg:HI
4112 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4113 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4114 (const_int 0)))
4115 (clobber (match_scratch:SI 3 "=r,r"))]
4116 "includes_rshift_p (operands[2], GEN_INT (65535))"
4117 "@
4118 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4119 #"
4120 [(set_attr "type" "delayed_compare")
4121 (set_attr "length" "4,8")])
4123 (define_split
4124 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4125 (compare:CC
4126 (zero_extend:SI
4127 (subreg:HI
4128 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4129 (match_operand:SI 2 "const_int_operand" "")) 0))
4130 (const_int 0)))
4131 (clobber (match_scratch:SI 3 ""))]
4132 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4133 [(set (match_dup 3)
4134 (zero_extend:SI (subreg:HI
4135 (lshiftrt:SI (match_dup 1)
4136 (match_dup 2)) 0)))
4137 (set (match_dup 0)
4138 (compare:CC (match_dup 3)
4139 (const_int 0)))]
4140 "")
4142 (define_insn ""
4143 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4144 (compare:CC
4145 (zero_extend:SI
4146 (subreg:HI
4147 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4148 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4149 (const_int 0)))
4150 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4151 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4152 "includes_rshift_p (operands[2], GEN_INT (65535))"
4153 "@
4154 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4155 #"
4156 [(set_attr "type" "delayed_compare")
4157 (set_attr "length" "4,8")])
4159 (define_split
4160 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4161 (compare:CC
4162 (zero_extend:SI
4163 (subreg:HI
4164 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4165 (match_operand:SI 2 "const_int_operand" "")) 0))
4166 (const_int 0)))
4167 (set (match_operand:SI 0 "gpc_reg_operand" "")
4168 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4169 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4170 [(set (match_dup 0)
4171 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4172 (set (match_dup 3)
4173 (compare:CC (match_dup 0)
4174 (const_int 0)))]
4175 "")
4177 (define_insn ""
4178 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4179 (const_int 1)
4180 (match_operand:SI 1 "gpc_reg_operand" "r"))
4181 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4182 (const_int 31)))]
4183 "TARGET_POWER"
4184 "rrib %0,%1,%2")
4186 (define_insn ""
4187 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4188 (const_int 1)
4189 (match_operand:SI 1 "gpc_reg_operand" "r"))
4190 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4191 (const_int 31)))]
4192 "TARGET_POWER"
4193 "rrib %0,%1,%2")
4195 (define_insn ""
4196 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4197 (const_int 1)
4198 (match_operand:SI 1 "gpc_reg_operand" "r"))
4199 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4200 (const_int 1)
4201 (const_int 0)))]
4202 "TARGET_POWER"
4203 "rrib %0,%1,%2")
4205 (define_expand "ashrsi3"
4206 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4207 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4208 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4209 ""
4210 "
4211 {
4212 if (TARGET_POWER)
4213 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4214 else
4215 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4216 DONE;
4217 }")
4219 (define_insn "ashrsi3_power"
4220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4221 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4222 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4223 (clobber (match_scratch:SI 3 "=q,X"))]
4224 "TARGET_POWER"
4225 "@
4226 srea %0,%1,%2
4227 {srai|srawi} %0,%1,%h2")
4229 (define_insn "ashrsi3_no_power"
4230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4231 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4232 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4233 "! TARGET_POWER"
4234 "{sra|sraw}%I2 %0,%1,%h2")
4236 (define_insn ""
4237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4238 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4239 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4240 (const_int 0)))
4241 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4242 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4243 "TARGET_POWER"
4244 "@
4245 srea. %3,%1,%2
4246 {srai.|srawi.} %3,%1,%h2
4247 #
4248 #"
4249 [(set_attr "type" "delayed_compare")
4250 (set_attr "length" "4,4,8,8")])
4252 (define_split
4253 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4254 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4255 (match_operand:SI 2 "reg_or_cint_operand" ""))
4256 (const_int 0)))
4257 (clobber (match_scratch:SI 3 ""))
4258 (clobber (match_scratch:SI 4 ""))]
4259 "TARGET_POWER && reload_completed"
4260 [(parallel [(set (match_dup 3)
4261 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4262 (clobber (match_dup 4))])
4263 (set (match_dup 0)
4264 (compare:CC (match_dup 3)
4265 (const_int 0)))]
4266 "")
4268 (define_insn ""
4269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4270 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4271 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4272 (const_int 0)))
4273 (clobber (match_scratch:SI 3 "=r,r"))]
4274 "! TARGET_POWER"
4275 "@
4276 {sra|sraw}%I2. %3,%1,%h2
4277 #"
4278 [(set_attr "type" "delayed_compare")
4279 (set_attr "length" "4,8")])
4281 (define_split
4282 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4283 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4284 (match_operand:SI 2 "reg_or_cint_operand" ""))
4285 (const_int 0)))
4286 (clobber (match_scratch:SI 3 ""))]
4287 "! TARGET_POWER && reload_completed"
4288 [(set (match_dup 3)
4289 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4290 (set (match_dup 0)
4291 (compare:CC (match_dup 3)
4292 (const_int 0)))]
4293 "")
4295 (define_insn ""
4296 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4297 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4298 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4299 (const_int 0)))
4300 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4301 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4302 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4303 "TARGET_POWER"
4304 "@
4305 srea. %0,%1,%2
4306 {srai.|srawi.} %0,%1,%h2
4307 #
4308 #"
4309 [(set_attr "type" "delayed_compare")
4310 (set_attr "length" "4,4,8,8")])
4312 (define_split
4313 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4314 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4315 (match_operand:SI 2 "reg_or_cint_operand" ""))
4316 (const_int 0)))
4317 (set (match_operand:SI 0 "gpc_reg_operand" "")
4318 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4319 (clobber (match_scratch:SI 4 ""))]
4320 "TARGET_POWER && reload_completed"
4321 [(parallel [(set (match_dup 0)
4322 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4323 (clobber (match_dup 4))])
4324 (set (match_dup 3)
4325 (compare:CC (match_dup 0)
4326 (const_int 0)))]
4327 "")
4329 (define_insn ""
4330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4331 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4332 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4333 (const_int 0)))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4335 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4336 "! TARGET_POWER"
4337 "@
4338 {sra|sraw}%I2. %0,%1,%h2
4339 #"
4340 [(set_attr "type" "delayed_compare")
4341 (set_attr "length" "4,8")])
4342 \f
4343 (define_split
4344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4345 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4346 (match_operand:SI 2 "reg_or_cint_operand" ""))
4347 (const_int 0)))
4348 (set (match_operand:SI 0 "gpc_reg_operand" "")
4349 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4350 "! TARGET_POWER && reload_completed"
4351 [(set (match_dup 0)
4352 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4353 (set (match_dup 3)
4354 (compare:CC (match_dup 0)
4355 (const_int 0)))]
4356 "")
4358 ;; Floating-point insns, excluding normal data motion.
4359 ;;
4360 ;; PowerPC has a full set of single-precision floating point instructions.
4361 ;;
4362 ;; For the POWER architecture, we pretend that we have both SFmode and
4363 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4364 ;; The only conversions we will do will be when storing to memory. In that
4365 ;; case, we will use the "frsp" instruction before storing.
4366 ;;
4367 ;; Note that when we store into a single-precision memory location, we need to
4368 ;; use the frsp insn first. If the register being stored isn't dead, we
4369 ;; need a scratch register for the frsp. But this is difficult when the store
4370 ;; is done by reload. It is not incorrect to do the frsp on the register in
4371 ;; this case, we just lose precision that we would have otherwise gotten but
4372 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4374 (define_insn "extendsfdf2"
4375 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4376 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4377 "TARGET_HARD_FLOAT && TARGET_FPRS"
4378 "*
4379 {
4380 if (REGNO (operands[0]) == REGNO (operands[1]))
4381 return \"\";
4382 else
4383 return \"fmr %0,%1\";
4384 }"
4385 [(set_attr "type" "fp")])
4387 (define_insn "truncdfsf2"
4388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4389 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4390 "TARGET_HARD_FLOAT && TARGET_FPRS"
4391 "frsp %0,%1"
4392 [(set_attr "type" "fp")])
4394 (define_insn "aux_truncdfsf2"
4395 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4396 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4397 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4398 "frsp %0,%1"
4399 [(set_attr "type" "fp")])
4401 (define_expand "negsf2"
4402 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4403 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4404 "TARGET_HARD_FLOAT"
4405 "")
4407 (define_insn "*negsf2"
4408 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4409 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4410 "TARGET_HARD_FLOAT && TARGET_FPRS"
4411 "fneg %0,%1"
4412 [(set_attr "type" "fp")])
4414 (define_expand "abssf2"
4415 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4416 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4417 "TARGET_HARD_FLOAT"
4418 "")
4420 (define_insn "*abssf2"
4421 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4422 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4423 "TARGET_HARD_FLOAT && TARGET_FPRS"
4424 "fabs %0,%1"
4425 [(set_attr "type" "fp")])
4427 (define_insn ""
4428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4429 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4430 "TARGET_HARD_FLOAT && TARGET_FPRS"
4431 "fnabs %0,%1"
4432 [(set_attr "type" "fp")])
4434 (define_expand "addsf3"
4435 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4436 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4437 (match_operand:SF 2 "gpc_reg_operand" "")))]
4438 "TARGET_HARD_FLOAT"
4439 "")
4441 (define_insn ""
4442 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4443 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4444 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4445 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4446 "fadds %0,%1,%2"
4447 [(set_attr "type" "fp")])
4449 (define_insn ""
4450 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4451 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4452 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4453 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4454 "{fa|fadd} %0,%1,%2"
4455 [(set_attr "type" "fp")])
4457 (define_expand "subsf3"
4458 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4459 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4460 (match_operand:SF 2 "gpc_reg_operand" "")))]
4461 "TARGET_HARD_FLOAT"
4462 "")
4464 (define_insn ""
4465 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4466 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4467 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4468 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4469 "fsubs %0,%1,%2"
4470 [(set_attr "type" "fp")])
4472 (define_insn ""
4473 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4474 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4475 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4476 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4477 "{fs|fsub} %0,%1,%2"
4478 [(set_attr "type" "fp")])
4480 (define_expand "mulsf3"
4481 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4482 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4483 (match_operand:SF 2 "gpc_reg_operand" "")))]
4484 "TARGET_HARD_FLOAT"
4485 "")
4487 (define_insn ""
4488 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4489 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4490 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4491 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4492 "fmuls %0,%1,%2"
4493 [(set_attr "type" "fp")])
4495 (define_insn ""
4496 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4497 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4498 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4499 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4500 "{fm|fmul} %0,%1,%2"
4501 [(set_attr "type" "dmul")])
4503 (define_expand "divsf3"
4504 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4505 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4506 (match_operand:SF 2 "gpc_reg_operand" "")))]
4507 "TARGET_HARD_FLOAT"
4508 "")
4510 (define_insn ""
4511 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4512 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4513 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4514 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4515 "fdivs %0,%1,%2"
4516 [(set_attr "type" "sdiv")])
4518 (define_insn ""
4519 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4520 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4521 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4522 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4523 "{fd|fdiv} %0,%1,%2"
4524 [(set_attr "type" "ddiv")])
4526 (define_insn ""
4527 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4528 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4529 (match_operand:SF 2 "gpc_reg_operand" "f"))
4530 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4531 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4532 "fmadds %0,%1,%2,%3"
4533 [(set_attr "type" "fp")])
4535 (define_insn ""
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4538 (match_operand:SF 2 "gpc_reg_operand" "f"))
4539 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4540 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4541 "{fma|fmadd} %0,%1,%2,%3"
4542 [(set_attr "type" "dmul")])
4544 (define_insn ""
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4547 (match_operand:SF 2 "gpc_reg_operand" "f"))
4548 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4549 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4550 "fmsubs %0,%1,%2,%3"
4551 [(set_attr "type" "fp")])
4553 (define_insn ""
4554 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4555 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4556 (match_operand:SF 2 "gpc_reg_operand" "f"))
4557 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4558 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4559 "{fms|fmsub} %0,%1,%2,%3"
4560 [(set_attr "type" "dmul")])
4562 (define_insn ""
4563 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4564 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4565 (match_operand:SF 2 "gpc_reg_operand" "f"))
4566 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4567 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4568 && HONOR_SIGNED_ZEROS (SFmode)"
4569 "fnmadds %0,%1,%2,%3"
4570 [(set_attr "type" "fp")])
4572 (define_insn ""
4573 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4574 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4575 (match_operand:SF 2 "gpc_reg_operand" "f"))
4576 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4577 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4578 && ! HONOR_SIGNED_ZEROS (SFmode)"
4579 "fnmadds %0,%1,%2,%3"
4580 [(set_attr "type" "fp")])
4582 (define_insn ""
4583 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4584 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4585 (match_operand:SF 2 "gpc_reg_operand" "f"))
4586 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4587 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4588 "{fnma|fnmadd} %0,%1,%2,%3"
4589 [(set_attr "type" "dmul")])
4591 (define_insn ""
4592 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4593 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4594 (match_operand:SF 2 "gpc_reg_operand" "f"))
4595 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4596 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4597 && ! HONOR_SIGNED_ZEROS (SFmode)"
4598 "{fnma|fnmadd} %0,%1,%2,%3"
4599 [(set_attr "type" "dmul")])
4601 (define_insn ""
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f"))
4605 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4606 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4607 && HONOR_SIGNED_ZEROS (SFmode)"
4608 "fnmsubs %0,%1,%2,%3"
4609 [(set_attr "type" "fp")])
4611 (define_insn ""
4612 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4613 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4614 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4615 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4616 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4617 && ! HONOR_SIGNED_ZEROS (SFmode)"
4618 "fnmsubs %0,%1,%2,%3"
4619 [(set_attr "type" "fp")])
4621 (define_insn ""
4622 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4623 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4624 (match_operand:SF 2 "gpc_reg_operand" "f"))
4625 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4626 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4627 "{fnms|fnmsub} %0,%1,%2,%3"
4628 [(set_attr "type" "dmul")])
4630 (define_insn ""
4631 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4632 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4633 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4634 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4635 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4636 && ! HONOR_SIGNED_ZEROS (SFmode)"
4637 "{fnms|fnmsub} %0,%1,%2,%3"
4638 [(set_attr "type" "fp")])
4640 (define_expand "sqrtsf2"
4641 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4642 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4643 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4644 "")
4646 (define_insn ""
4647 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4648 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4649 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4650 "fsqrts %0,%1"
4651 [(set_attr "type" "ssqrt")])
4653 (define_insn ""
4654 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4655 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4656 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4657 "fsqrt %0,%1"
4658 [(set_attr "type" "dsqrt")])
4660 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4661 ;; fsel instruction and some auxiliary computations. Then we just have a
4662 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4663 ;; combine.
4664 (define_expand "maxsf3"
4665 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4666 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4667 (match_operand:SF 2 "gpc_reg_operand" ""))
4668 (match_dup 1)
4669 (match_dup 2)))]
4670 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4671 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4673 (define_expand "minsf3"
4674 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4675 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4676 (match_operand:SF 2 "gpc_reg_operand" ""))
4677 (match_dup 2)
4678 (match_dup 1)))]
4679 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4680 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4682 (define_split
4683 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4684 (match_operator:SF 3 "min_max_operator"
4685 [(match_operand:SF 1 "gpc_reg_operand" "")
4686 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4687 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4688 [(const_int 0)]
4689 "
4690 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4691 operands[1], operands[2]);
4692 DONE;
4693 }")
4695 (define_expand "movsicc"
4696 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4697 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4698 (match_operand:SI 2 "gpc_reg_operand" "")
4699 (match_operand:SI 3 "gpc_reg_operand" "")))]
4700 "TARGET_ISEL"
4701 "
4702 {
4703 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4704 DONE;
4705 else
4706 FAIL;
4707 }")
4709 ;; We use the BASE_REGS for the isel input operands because, if rA is
4710 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4711 ;; because we may switch the operands and rB may end up being rA.
4712 ;;
4713 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4714 ;; leave out the mode in operand 4 and use one pattern, but reload can
4715 ;; change the mode underneath our feet and then gets confused trying
4716 ;; to reload the value.
4717 (define_insn "isel_signed"
4718 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4719 (if_then_else:SI
4720 (match_operator 1 "comparison_operator"
4721 [(match_operand:CC 4 "cc_reg_operand" "y")
4722 (const_int 0)])
4723 (match_operand:SI 2 "gpc_reg_operand" "b")
4724 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4725 "TARGET_ISEL"
4726 "*
4727 { return output_isel (operands); }"
4728 [(set_attr "length" "4")])
4730 (define_insn "isel_unsigned"
4731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4732 (if_then_else:SI
4733 (match_operator 1 "comparison_operator"
4734 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4735 (const_int 0)])
4736 (match_operand:SI 2 "gpc_reg_operand" "b")
4737 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4738 "TARGET_ISEL"
4739 "*
4740 { return output_isel (operands); }"
4741 [(set_attr "length" "4")])
4743 (define_expand "movsfcc"
4744 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4745 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4746 (match_operand:SF 2 "gpc_reg_operand" "")
4747 (match_operand:SF 3 "gpc_reg_operand" "")))]
4748 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4749 "
4750 {
4751 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4752 DONE;
4753 else
4754 FAIL;
4755 }")
4757 (define_insn "*fselsfsf4"
4758 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4759 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4760 (match_operand:SF 4 "zero_fp_constant" "F"))
4761 (match_operand:SF 2 "gpc_reg_operand" "f")
4762 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4763 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4764 "fsel %0,%1,%2,%3"
4765 [(set_attr "type" "fp")])
4767 (define_insn "*fseldfsf4"
4768 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4769 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4770 (match_operand:DF 4 "zero_fp_constant" "F"))
4771 (match_operand:SF 2 "gpc_reg_operand" "f")
4772 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4773 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4774 "fsel %0,%1,%2,%3"
4775 [(set_attr "type" "fp")])
4777 (define_insn "negdf2"
4778 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4779 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4780 "TARGET_HARD_FLOAT && TARGET_FPRS"
4781 "fneg %0,%1"
4782 [(set_attr "type" "fp")])
4784 (define_insn "absdf2"
4785 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4786 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4787 "TARGET_HARD_FLOAT && TARGET_FPRS"
4788 "fabs %0,%1"
4789 [(set_attr "type" "fp")])
4791 (define_insn ""
4792 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4793 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4794 "TARGET_HARD_FLOAT && TARGET_FPRS"
4795 "fnabs %0,%1"
4796 [(set_attr "type" "fp")])
4798 (define_insn "adddf3"
4799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4800 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4801 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4802 "TARGET_HARD_FLOAT && TARGET_FPRS"
4803 "{fa|fadd} %0,%1,%2"
4804 [(set_attr "type" "fp")])
4806 (define_insn "subdf3"
4807 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4808 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4809 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4810 "TARGET_HARD_FLOAT && TARGET_FPRS"
4811 "{fs|fsub} %0,%1,%2"
4812 [(set_attr "type" "fp")])
4814 (define_insn "muldf3"
4815 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4816 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4817 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4818 "TARGET_HARD_FLOAT && TARGET_FPRS"
4819 "{fm|fmul} %0,%1,%2"
4820 [(set_attr "type" "dmul")])
4822 (define_insn "divdf3"
4823 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4824 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4825 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4826 "TARGET_HARD_FLOAT && TARGET_FPRS"
4827 "{fd|fdiv} %0,%1,%2"
4828 [(set_attr "type" "ddiv")])
4830 (define_insn ""
4831 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4832 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4833 (match_operand:DF 2 "gpc_reg_operand" "f"))
4834 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4835 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4836 "{fma|fmadd} %0,%1,%2,%3"
4837 [(set_attr "type" "dmul")])
4839 (define_insn ""
4840 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4841 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4842 (match_operand:DF 2 "gpc_reg_operand" "f"))
4843 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4844 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4845 "{fms|fmsub} %0,%1,%2,%3"
4846 [(set_attr "type" "dmul")])
4848 (define_insn ""
4849 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4850 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4851 (match_operand:DF 2 "gpc_reg_operand" "f"))
4852 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4853 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4854 && HONOR_SIGNED_ZEROS (DFmode)"
4855 "{fnma|fnmadd} %0,%1,%2,%3"
4856 [(set_attr "type" "dmul")])
4858 (define_insn ""
4859 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4860 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4861 (match_operand:DF 2 "gpc_reg_operand" "f"))
4862 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4863 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4864 && ! HONOR_SIGNED_ZEROS (DFmode)"
4865 "{fnma|fnmadd} %0,%1,%2,%3"
4866 [(set_attr "type" "dmul")])
4868 (define_insn ""
4869 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4870 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4871 (match_operand:DF 2 "gpc_reg_operand" "f"))
4872 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4873 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4874 && HONOR_SIGNED_ZEROS (DFmode)"
4875 "{fnms|fnmsub} %0,%1,%2,%3"
4876 [(set_attr "type" "dmul")])
4878 (define_insn ""
4879 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4880 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4881 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4882 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4883 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4884 && ! HONOR_SIGNED_ZEROS (DFmode)"
4885 "{fnms|fnmsub} %0,%1,%2,%3"
4886 [(set_attr "type" "dmul")])
4888 (define_insn "sqrtdf2"
4889 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4890 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4891 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4892 "fsqrt %0,%1"
4893 [(set_attr "type" "dsqrt")])
4895 ;; The conditional move instructions allow us to perform max and min
4896 ;; operations even when
4898 (define_expand "maxdf3"
4899 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4900 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4901 (match_operand:DF 2 "gpc_reg_operand" ""))
4902 (match_dup 1)
4903 (match_dup 2)))]
4904 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4905 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4907 (define_expand "mindf3"
4908 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4909 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4910 (match_operand:DF 2 "gpc_reg_operand" ""))
4911 (match_dup 2)
4912 (match_dup 1)))]
4913 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4914 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4916 (define_split
4917 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4918 (match_operator:DF 3 "min_max_operator"
4919 [(match_operand:DF 1 "gpc_reg_operand" "")
4920 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4921 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4922 [(const_int 0)]
4923 "
4924 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4925 operands[1], operands[2]);
4926 DONE;
4927 }")
4929 (define_expand "movdfcc"
4930 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4931 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4932 (match_operand:DF 2 "gpc_reg_operand" "")
4933 (match_operand:DF 3 "gpc_reg_operand" "")))]
4934 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4935 "
4936 {
4937 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4938 DONE;
4939 else
4940 FAIL;
4941 }")
4943 (define_insn "*fseldfdf4"
4944 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4945 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4946 (match_operand:DF 4 "zero_fp_constant" "F"))
4947 (match_operand:DF 2 "gpc_reg_operand" "f")
4948 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4949 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4950 "fsel %0,%1,%2,%3"
4951 [(set_attr "type" "fp")])
4953 (define_insn "*fselsfdf4"
4954 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4955 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4956 (match_operand:SF 4 "zero_fp_constant" "F"))
4957 (match_operand:DF 2 "gpc_reg_operand" "f")
4958 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4959 "TARGET_PPC_GFXOPT"
4960 "fsel %0,%1,%2,%3"
4961 [(set_attr "type" "fp")])
4962 \f
4963 ;; Conversions to and from floating-point.
4965 (define_expand "fixuns_truncsfsi2"
4966 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4967 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4968 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4969 "")
4971 (define_expand "fix_truncsfsi2"
4972 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4973 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4974 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4975 "")
4977 ; For each of these conversions, there is a define_expand, a define_insn
4978 ; with a '#' template, and a define_split (with C code). The idea is
4979 ; to allow constant folding with the template of the define_insn,
4980 ; then to have the insns split later (between sched1 and final).
4982 (define_expand "floatsidf2"
4983 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4984 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4985 (use (match_dup 2))
4986 (use (match_dup 3))
4987 (clobber (match_dup 4))
4988 (clobber (match_dup 5))
4989 (clobber (match_dup 6))])]
4990 "TARGET_HARD_FLOAT && TARGET_FPRS"
4991 "
4992 {
4993 if (TARGET_POWERPC64)
4994 {
4995 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4996 rtx t1 = gen_reg_rtx (DImode);
4997 rtx t2 = gen_reg_rtx (DImode);
4998 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4999 DONE;
5000 }
5002 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5003 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5004 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5005 operands[5] = gen_reg_rtx (DFmode);
5006 operands[6] = gen_reg_rtx (SImode);
5007 }")
5009 (define_insn "*floatsidf2_internal"
5010 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5011 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5012 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5013 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5014 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5015 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5016 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5017 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5018 "#"
5019 [(set_attr "length" "24")])
5021 (define_split
5022 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5023 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5024 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5025 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5026 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5027 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5028 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5029 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5030 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5031 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5032 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5033 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5034 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5035 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5036 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5037 "
5038 {
5039 rtx lowword, highword;
5040 if (GET_CODE (operands[4]) != MEM)
5041 abort();
5042 highword = XEXP (operands[4], 0);
5043 lowword = plus_constant (highword, 4);
5044 if (! WORDS_BIG_ENDIAN)
5045 {
5046 rtx tmp;
5047 tmp = highword; highword = lowword; lowword = tmp;
5048 }
5050 emit_insn (gen_xorsi3 (operands[6], operands[1],
5051 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5052 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5053 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5054 emit_move_insn (operands[5], operands[4]);
5055 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5056 DONE;
5057 }")
5059 (define_expand "floatunssisf2"
5060 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5061 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5062 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5063 "")
5065 (define_expand "floatunssidf2"
5066 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5067 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5068 (use (match_dup 2))
5069 (use (match_dup 3))
5070 (clobber (match_dup 4))
5071 (clobber (match_dup 5))])]
5072 "TARGET_HARD_FLOAT && TARGET_FPRS"
5073 "
5074 {
5075 if (TARGET_POWERPC64)
5076 {
5077 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5078 rtx t1 = gen_reg_rtx (DImode);
5079 rtx t2 = gen_reg_rtx (DImode);
5080 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5081 t1, t2));
5082 DONE;
5083 }
5085 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5086 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5087 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5088 operands[5] = gen_reg_rtx (DFmode);
5089 }")
5091 (define_insn "*floatunssidf2_internal"
5092 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5093 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5094 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5095 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5096 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5097 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5098 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5099 "#"
5100 [(set_attr "length" "20")])
5102 (define_split
5103 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5104 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5105 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5106 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5107 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5108 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5109 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5110 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5111 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5112 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5113 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5114 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5115 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5116 "
5117 {
5118 rtx lowword, highword;
5119 if (GET_CODE (operands[4]) != MEM)
5120 abort();
5121 highword = XEXP (operands[4], 0);
5122 lowword = plus_constant (highword, 4);
5123 if (! WORDS_BIG_ENDIAN)
5124 {
5125 rtx tmp;
5126 tmp = highword; highword = lowword; lowword = tmp;
5127 }
5129 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5130 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5131 emit_move_insn (operands[5], operands[4]);
5132 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5133 DONE;
5134 }")
5136 (define_expand "fix_truncdfsi2"
5137 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5138 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5139 (clobber (match_dup 2))
5140 (clobber (match_dup 3))])]
5141 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5142 "
5143 {
5144 operands[2] = gen_reg_rtx (DImode);
5145 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5146 }")
5148 (define_insn "*fix_truncdfsi2_internal"
5149 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5150 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5151 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5152 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5153 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5154 "#"
5155 [(set_attr "length" "16")])
5157 (define_split
5158 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5159 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5160 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5161 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5162 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5163 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5164 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5165 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5166 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5167 "
5168 {
5169 rtx lowword;
5170 if (GET_CODE (operands[3]) != MEM)
5171 abort();
5172 lowword = XEXP (operands[3], 0);
5173 if (WORDS_BIG_ENDIAN)
5174 lowword = plus_constant (lowword, 4);
5176 emit_insn (gen_fctiwz (operands[2], operands[1]));
5177 emit_move_insn (operands[3], operands[2]);
5178 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5179 DONE;
5180 }")
5182 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5183 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5184 ; because the first makes it clear that operand 0 is not live
5185 ; before the instruction.
5186 (define_insn "fctiwz"
5187 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5188 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5189 UNSPEC_FCTIWZ))]
5190 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5191 "{fcirz|fctiwz} %0,%1"
5192 [(set_attr "type" "fp")])
5194 (define_expand "floatsisf2"
5195 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5196 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5197 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5198 "")
5200 (define_insn "floatdidf2"
5201 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5202 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5203 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5204 "fcfid %0,%1"
5205 [(set_attr "type" "fp")])
5207 (define_insn_and_split "floatsidf_ppc64"
5208 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5209 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5210 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5211 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5212 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5213 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5214 "#"
5215 "&& 1"
5216 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5217 (set (match_dup 2) (match_dup 3))
5218 (set (match_dup 4) (match_dup 2))
5219 (set (match_dup 0) (float:DF (match_dup 4)))]
5220 "")
5222 (define_insn_and_split "floatunssidf_ppc64"
5223 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5224 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5225 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5226 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5227 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5228 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5229 "#"
5230 "&& 1"
5231 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5232 (set (match_dup 2) (match_dup 3))
5233 (set (match_dup 4) (match_dup 2))
5234 (set (match_dup 0) (float:DF (match_dup 4)))]
5235 "")
5237 (define_insn "fix_truncdfdi2"
5238 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5239 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5240 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5241 "fctidz %0,%1"
5242 [(set_attr "type" "fp")])
5244 (define_expand "floatdisf2"
5245 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5246 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5247 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5248 "
5249 {
5250 if (!flag_unsafe_math_optimizations)
5251 {
5252 rtx label = gen_label_rtx ();
5253 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5254 emit_label (label);
5255 }
5256 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5257 DONE;
5258 }")
5260 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5261 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5262 ;; from double rounding.
5263 (define_insn_and_split "floatdisf2_internal1"
5264 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5265 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5266 (clobber (match_scratch:DF 2 "=f"))]
5267 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5268 "#"
5269 "&& reload_completed"
5270 [(set (match_dup 2)
5271 (float:DF (match_dup 1)))
5272 (set (match_dup 0)
5273 (float_truncate:SF (match_dup 2)))]
5274 "")
5276 ;; Twiddles bits to avoid double rounding.
5277 ;; Bits that might be truncated when converting to DFmode are replaced
5278 ;; by a bit that won't be lost at that stage, but is below the SFmode
5279 ;; rounding position.
5280 (define_expand "floatdisf2_internal2"
5281 [(parallel [(set (match_dup 4)
5282 (compare:CC (and:DI (match_operand:DI 0 "" "")
5283 (const_int 2047))
5284 (const_int 0)))
5285 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5286 (clobber (match_scratch:CC 7 ""))])
5287 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5288 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5289 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5290 (label_ref (match_operand:DI 1 "" ""))
5291 (pc)))
5292 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5293 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5294 (label_ref (match_dup 1))
5295 (pc)))
5296 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5297 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5298 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5299 "
5300 {
5301 operands[2] = gen_reg_rtx (DImode);
5302 operands[3] = gen_reg_rtx (DImode);
5303 operands[4] = gen_reg_rtx (CCmode);
5304 operands[5] = gen_reg_rtx (CCUNSmode);
5305 }")
5306 \f
5307 ;; Define the DImode operations that can be done in a small number
5308 ;; of instructions. The & constraints are to prevent the register
5309 ;; allocator from allocating registers that overlap with the inputs
5310 ;; (for example, having an input in 7,8 and an output in 6,7). We
5311 ;; also allow for the output being the same as one of the inputs.
5313 (define_insn "*adddi3_noppc64"
5314 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5315 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5316 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5317 "! TARGET_POWERPC64"
5318 "*
5319 {
5320 if (WORDS_BIG_ENDIAN)
5321 return (GET_CODE (operands[2])) != CONST_INT
5322 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5323 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5324 else
5325 return (GET_CODE (operands[2])) != CONST_INT
5326 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5327 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5328 }"
5329 [(set_attr "length" "8")])
5331 (define_insn "*subdi3_noppc64"
5332 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5333 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5334 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5335 "! TARGET_POWERPC64"
5336 "*
5337 {
5338 if (WORDS_BIG_ENDIAN)
5339 return (GET_CODE (operands[1]) != CONST_INT)
5340 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5341 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5342 else
5343 return (GET_CODE (operands[1]) != CONST_INT)
5344 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5345 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5346 }"
5347 [(set_attr "length" "8")])
5349 (define_insn "*negdi2_noppc64"
5350 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5351 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5352 "! TARGET_POWERPC64"
5353 "*
5354 {
5355 return (WORDS_BIG_ENDIAN)
5356 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5357 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5358 }"
5359 [(set_attr "length" "8")])
5361 (define_expand "mulsidi3"
5362 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5363 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5364 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5365 "! TARGET_POWERPC64"
5366 "
5367 {
5368 if (! TARGET_POWER && ! TARGET_POWERPC)
5369 {
5370 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5371 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5372 emit_insn (gen_mull_call ());
5373 if (WORDS_BIG_ENDIAN)
5374 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5375 else
5376 {
5377 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5378 gen_rtx_REG (SImode, 3));
5379 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5380 gen_rtx_REG (SImode, 4));
5381 }
5382 DONE;
5383 }
5384 else if (TARGET_POWER)
5385 {
5386 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5387 DONE;
5388 }
5389 }")
5391 (define_insn "mulsidi3_mq"
5392 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5393 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5394 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5395 (clobber (match_scratch:SI 3 "=q"))]
5396 "TARGET_POWER"
5397 "mul %0,%1,%2\;mfmq %L0"
5398 [(set_attr "type" "imul")
5399 (set_attr "length" "8")])
5401 (define_insn "*mulsidi3_no_mq"
5402 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5403 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5404 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5405 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5406 "*
5407 {
5408 return (WORDS_BIG_ENDIAN)
5409 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5410 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5411 }"
5412 [(set_attr "type" "imul")
5413 (set_attr "length" "8")])
5415 (define_split
5416 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5417 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5418 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5419 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5420 [(set (match_dup 3)
5421 (truncate:SI
5422 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5423 (sign_extend:DI (match_dup 2)))
5424 (const_int 32))))
5425 (set (match_dup 4)
5426 (mult:SI (match_dup 1)
5427 (match_dup 2)))]
5428 "
5429 {
5430 int endian = (WORDS_BIG_ENDIAN == 0);
5431 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5432 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5433 }")
5435 (define_expand "umulsidi3"
5436 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5437 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5438 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5439 "TARGET_POWERPC && ! TARGET_POWERPC64"
5440 "
5441 {
5442 if (TARGET_POWER)
5443 {
5444 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5445 DONE;
5446 }
5447 }")
5449 (define_insn "umulsidi3_mq"
5450 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5451 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5452 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5453 (clobber (match_scratch:SI 3 "=q"))]
5454 "TARGET_POWERPC && TARGET_POWER"
5455 "*
5456 {
5457 return (WORDS_BIG_ENDIAN)
5458 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5459 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5460 }"
5461 [(set_attr "type" "imul")
5462 (set_attr "length" "8")])
5464 (define_insn "*umulsidi3_no_mq"
5465 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5466 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5467 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5468 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5469 "*
5470 {
5471 return (WORDS_BIG_ENDIAN)
5472 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5473 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5474 }"
5475 [(set_attr "type" "imul")
5476 (set_attr "length" "8")])
5478 (define_split
5479 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5480 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5481 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5482 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5483 [(set (match_dup 3)
5484 (truncate:SI
5485 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5486 (zero_extend:DI (match_dup 2)))
5487 (const_int 32))))
5488 (set (match_dup 4)
5489 (mult:SI (match_dup 1)
5490 (match_dup 2)))]
5491 "
5492 {
5493 int endian = (WORDS_BIG_ENDIAN == 0);
5494 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5495 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5496 }")
5498 (define_expand "smulsi3_highpart"
5499 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5500 (truncate:SI
5501 (lshiftrt:DI (mult:DI (sign_extend:DI
5502 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5503 (sign_extend:DI
5504 (match_operand:SI 2 "gpc_reg_operand" "r")))
5505 (const_int 32))))]
5506 ""
5507 "
5508 {
5509 if (! TARGET_POWER && ! TARGET_POWERPC)
5510 {
5511 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5512 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5513 emit_insn (gen_mulh_call ());
5514 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5515 DONE;
5516 }
5517 else if (TARGET_POWER)
5518 {
5519 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5520 DONE;
5521 }
5522 }")
5524 (define_insn "smulsi3_highpart_mq"
5525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5526 (truncate:SI
5527 (lshiftrt:DI (mult:DI (sign_extend:DI
5528 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5529 (sign_extend:DI
5530 (match_operand:SI 2 "gpc_reg_operand" "r")))
5531 (const_int 32))))
5532 (clobber (match_scratch:SI 3 "=q"))]
5533 "TARGET_POWER"
5534 "mul %0,%1,%2"
5535 [(set_attr "type" "imul")])
5537 (define_insn "*smulsi3_highpart_no_mq"
5538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5539 (truncate:SI
5540 (lshiftrt:DI (mult:DI (sign_extend:DI
5541 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5542 (sign_extend:DI
5543 (match_operand:SI 2 "gpc_reg_operand" "r")))
5544 (const_int 32))))]
5545 "TARGET_POWERPC && ! TARGET_POWER"
5546 "mulhw %0,%1,%2"
5547 [(set_attr "type" "imul")])
5549 (define_expand "umulsi3_highpart"
5550 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5551 (truncate:SI
5552 (lshiftrt:DI (mult:DI (zero_extend:DI
5553 (match_operand:SI 1 "gpc_reg_operand" ""))
5554 (zero_extend:DI
5555 (match_operand:SI 2 "gpc_reg_operand" "")))
5556 (const_int 32))))]
5557 "TARGET_POWERPC"
5558 "
5559 {
5560 if (TARGET_POWER)
5561 {
5562 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5563 DONE;
5564 }
5565 }")
5567 (define_insn "umulsi3_highpart_mq"
5568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5569 (truncate:SI
5570 (lshiftrt:DI (mult:DI (zero_extend:DI
5571 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5572 (zero_extend:DI
5573 (match_operand:SI 2 "gpc_reg_operand" "r")))
5574 (const_int 32))))
5575 (clobber (match_scratch:SI 3 "=q"))]
5576 "TARGET_POWERPC && TARGET_POWER"
5577 "mulhwu %0,%1,%2"
5578 [(set_attr "type" "imul")])
5580 (define_insn "*umulsi3_highpart_no_mq"
5581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5582 (truncate:SI
5583 (lshiftrt:DI (mult:DI (zero_extend:DI
5584 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5585 (zero_extend:DI
5586 (match_operand:SI 2 "gpc_reg_operand" "r")))
5587 (const_int 32))))]
5588 "TARGET_POWERPC && ! TARGET_POWER"
5589 "mulhwu %0,%1,%2"
5590 [(set_attr "type" "imul")])
5592 ;; If operands 0 and 2 are in the same register, we have a problem. But
5593 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5594 ;; why we have the strange constraints below.
5595 (define_insn "ashldi3_power"
5596 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5597 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5598 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5599 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5600 "TARGET_POWER"
5601 "@
5602 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5603 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5604 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5605 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5606 [(set_attr "length" "8")])
5608 (define_insn "lshrdi3_power"
5609 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5610 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5611 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5612 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5613 "TARGET_POWER"
5614 "@
5615 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5616 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5617 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5618 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5619 [(set_attr "length" "8")])
5621 ;; Shift by a variable amount is too complex to be worth open-coding. We
5622 ;; just handle shifts by constants.
5623 (define_insn "ashrdi3_power"
5624 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5625 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5626 (match_operand:SI 2 "const_int_operand" "M,i")))
5627 (clobber (match_scratch:SI 3 "=X,q"))]
5628 "TARGET_POWER"
5629 "@
5630 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5631 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5632 [(set_attr "length" "8")])
5634 (define_insn "ashrdi3_no_power"
5635 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5636 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5637 (match_operand:SI 2 "const_int_operand" "M,i")))]
5638 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5639 "@
5640 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5641 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5642 [(set_attr "length" "8,12")])
5644 (define_insn "*ashrdisi3_noppc64"
5645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5646 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5647 (const_int 32)) 4))]
5648 "TARGET_32BIT && !TARGET_POWERPC64"
5649 "*
5650 {
5651 if (REGNO (operands[0]) == REGNO (operands[1]))
5652 return \"\";
5653 else
5654 return \"mr %0,%1\";
5655 }"
5656 [(set_attr "length" "4")])
5658 \f
5659 ;; PowerPC64 DImode operations.
5661 (define_expand "adddi3"
5662 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5663 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5664 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5665 ""
5666 "
5667 {
5668 if (! TARGET_POWERPC64)
5669 {
5670 if (non_short_cint_operand (operands[2], DImode))
5671 FAIL;
5672 }
5673 else
5674 if (GET_CODE (operands[2]) == CONST_INT
5675 && ! add_operand (operands[2], DImode))
5676 {
5677 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5678 ? operands[0] : gen_reg_rtx (DImode));
5680 HOST_WIDE_INT val = INTVAL (operands[2]);
5681 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5682 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5684 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5685 FAIL;
5687 /* The ordering here is important for the prolog expander.
5688 When space is allocated from the stack, adding 'low' first may
5689 produce a temporary deallocation (which would be bad). */
5690 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5691 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5692 DONE;
5693 }
5694 }")
5696 ;; Discourage ai/addic because of carry but provide it in an alternative
5697 ;; allowing register zero as source.
5699 (define_insn "*adddi3_internal1"
5700 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5701 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5702 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5703 "TARGET_POWERPC64"
5704 "@
5705 add %0,%1,%2
5706 addi %0,%1,%2
5707 addic %0,%1,%2
5708 addis %0,%1,%v2")
5710 (define_insn "*adddi3_internal2"
5711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5712 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5713 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5714 (const_int 0)))
5715 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5716 "TARGET_64BIT"
5717 "@
5718 add. %3,%1,%2
5719 addic. %3,%1,%2
5720 #
5721 #"
5722 [(set_attr "type" "fast_compare,compare,compare,compare")
5723 (set_attr "length" "4,4,8,8")])
5725 (define_split
5726 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5727 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5728 (match_operand:DI 2 "reg_or_short_operand" ""))
5729 (const_int 0)))
5730 (clobber (match_scratch:DI 3 ""))]
5731 "TARGET_POWERPC64 && reload_completed"
5732 [(set (match_dup 3)
5733 (plus:DI (match_dup 1) (match_dup 2)))
5734 (set (match_dup 0)
5735 (compare:CC (match_dup 3)
5736 (const_int 0)))]
5737 "")
5739 (define_insn "*adddi3_internal3"
5740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5741 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5742 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5743 (const_int 0)))
5744 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5745 (plus:DI (match_dup 1) (match_dup 2)))]
5746 "TARGET_64BIT"
5747 "@
5748 add. %0,%1,%2
5749 addic. %0,%1,%2
5750 #
5751 #"
5752 [(set_attr "type" "fast_compare,compare,compare,compare")
5753 (set_attr "length" "4,4,8,8")])
5755 (define_split
5756 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5757 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5758 (match_operand:DI 2 "reg_or_short_operand" ""))
5759 (const_int 0)))
5760 (set (match_operand:DI 0 "gpc_reg_operand" "")
5761 (plus:DI (match_dup 1) (match_dup 2)))]
5762 "TARGET_POWERPC64 && reload_completed"
5763 [(set (match_dup 0)
5764 (plus:DI (match_dup 1) (match_dup 2)))
5765 (set (match_dup 3)
5766 (compare:CC (match_dup 0)
5767 (const_int 0)))]
5768 "")
5770 ;; Split an add that we can't do in one insn into two insns, each of which
5771 ;; does one 16-bit part. This is used by combine. Note that the low-order
5772 ;; add should be last in case the result gets used in an address.
5774 (define_split
5775 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5776 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5777 (match_operand:DI 2 "non_add_cint_operand" "")))]
5778 "TARGET_POWERPC64"
5779 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5780 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5781 "
5782 {
5783 HOST_WIDE_INT val = INTVAL (operands[2]);
5784 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5785 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5787 operands[4] = GEN_INT (low);
5788 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5789 operands[3] = GEN_INT (rest);
5790 else if (! no_new_pseudos)
5791 {
5792 operands[3] = gen_reg_rtx (DImode);
5793 emit_move_insn (operands[3], operands[2]);
5794 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5795 DONE;
5796 }
5797 else
5798 FAIL;
5799 }")
5801 (define_insn "one_cmpldi2"
5802 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5803 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5804 "TARGET_POWERPC64"
5805 "nor %0,%1,%1")
5807 (define_insn ""
5808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5809 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5810 (const_int 0)))
5811 (clobber (match_scratch:DI 2 "=r,r"))]
5812 "TARGET_64BIT"
5813 "@
5814 nor. %2,%1,%1
5815 #"
5816 [(set_attr "type" "compare")
5817 (set_attr "length" "4,8")])
5819 (define_split
5820 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5821 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5822 (const_int 0)))
5823 (clobber (match_scratch:DI 2 ""))]
5824 "TARGET_POWERPC64 && reload_completed"
5825 [(set (match_dup 2)
5826 (not:DI (match_dup 1)))
5827 (set (match_dup 0)
5828 (compare:CC (match_dup 2)
5829 (const_int 0)))]
5830 "")
5832 (define_insn ""
5833 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5834 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5835 (const_int 0)))
5836 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5837 (not:DI (match_dup 1)))]
5838 "TARGET_64BIT"
5839 "@
5840 nor. %0,%1,%1
5841 #"
5842 [(set_attr "type" "compare")
5843 (set_attr "length" "4,8")])
5845 (define_split
5846 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5847 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5848 (const_int 0)))
5849 (set (match_operand:DI 0 "gpc_reg_operand" "")
5850 (not:DI (match_dup 1)))]
5851 "TARGET_POWERPC64 && reload_completed"
5852 [(set (match_dup 0)
5853 (not:DI (match_dup 1)))
5854 (set (match_dup 2)
5855 (compare:CC (match_dup 0)
5856 (const_int 0)))]
5857 "")
5859 (define_insn ""
5860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5861 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5862 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5863 "TARGET_POWERPC64"
5864 "@
5865 subf %0,%2,%1
5866 subfic %0,%2,%1")
5868 (define_insn ""
5869 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5870 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5871 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5872 (const_int 0)))
5873 (clobber (match_scratch:DI 3 "=r,r"))]
5874 "TARGET_64BIT"
5875 "@
5876 subf. %3,%2,%1
5877 #"
5878 [(set_attr "type" "fast_compare")
5879 (set_attr "length" "4,8")])
5881 (define_split
5882 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5883 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5884 (match_operand:DI 2 "gpc_reg_operand" ""))
5885 (const_int 0)))
5886 (clobber (match_scratch:DI 3 ""))]
5887 "TARGET_POWERPC64 && reload_completed"
5888 [(set (match_dup 3)
5889 (minus:DI (match_dup 1) (match_dup 2)))
5890 (set (match_dup 0)
5891 (compare:CC (match_dup 3)
5892 (const_int 0)))]
5893 "")
5895 (define_insn ""
5896 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5897 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5898 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5899 (const_int 0)))
5900 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5901 (minus:DI (match_dup 1) (match_dup 2)))]
5902 "TARGET_64BIT"
5903 "@
5904 subf. %0,%2,%1
5905 #"
5906 [(set_attr "type" "fast_compare")
5907 (set_attr "length" "4,8")])
5909 (define_split
5910 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5911 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5912 (match_operand:DI 2 "gpc_reg_operand" ""))
5913 (const_int 0)))
5914 (set (match_operand:DI 0 "gpc_reg_operand" "")
5915 (minus:DI (match_dup 1) (match_dup 2)))]
5916 "TARGET_POWERPC64 && reload_completed"
5917 [(set (match_dup 0)
5918 (minus:DI (match_dup 1) (match_dup 2)))
5919 (set (match_dup 3)
5920 (compare:CC (match_dup 0)
5921 (const_int 0)))]
5922 "")
5924 (define_expand "subdi3"
5925 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5926 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5927 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5928 ""
5929 "
5930 {
5931 if (GET_CODE (operands[2]) == CONST_INT)
5932 {
5933 emit_insn (gen_adddi3 (operands[0], operands[1],
5934 negate_rtx (DImode, operands[2])));
5935 DONE;
5936 }
5937 }")
5939 (define_insn_and_split "absdi2"
5940 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5941 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5942 (clobber (match_scratch:DI 2 "=&r,&r"))]
5943 "TARGET_POWERPC64"
5944 "#"
5945 "&& reload_completed"
5946 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5947 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5948 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5949 "")
5951 (define_insn_and_split "*nabsdi2"
5952 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5953 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5954 (clobber (match_scratch:DI 2 "=&r,&r"))]
5955 "TARGET_POWERPC64"
5956 "#"
5957 "&& reload_completed"
5958 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5959 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5960 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5961 "")
5963 (define_expand "negdi2"
5964 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5965 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5966 ""
5967 "")
5969 (define_insn ""
5970 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5971 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5972 "TARGET_POWERPC64"
5973 "neg %0,%1")
5975 (define_insn ""
5976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5977 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5978 (const_int 0)))
5979 (clobber (match_scratch:DI 2 "=r,r"))]
5980 "TARGET_64BIT"
5981 "@
5982 neg. %2,%1
5983 #"
5984 [(set_attr "type" "fast_compare")
5985 (set_attr "length" "4,8")])
5987 (define_split
5988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5989 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5990 (const_int 0)))
5991 (clobber (match_scratch:DI 2 ""))]
5992 "TARGET_POWERPC64 && reload_completed"
5993 [(set (match_dup 2)
5994 (neg:DI (match_dup 1)))
5995 (set (match_dup 0)
5996 (compare:CC (match_dup 2)
5997 (const_int 0)))]
5998 "")
6000 (define_insn ""
6001 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6002 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6003 (const_int 0)))
6004 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6005 (neg:DI (match_dup 1)))]
6006 "TARGET_64BIT"
6007 "@
6008 neg. %0,%1
6009 #"
6010 [(set_attr "type" "fast_compare")
6011 (set_attr "length" "4,8")])
6013 (define_split
6014 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6015 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6016 (const_int 0)))
6017 (set (match_operand:DI 0 "gpc_reg_operand" "")
6018 (neg:DI (match_dup 1)))]
6019 "TARGET_POWERPC64 && reload_completed"
6020 [(set (match_dup 0)
6021 (neg:DI (match_dup 1)))
6022 (set (match_dup 2)
6023 (compare:CC (match_dup 0)
6024 (const_int 0)))]
6025 "")
6027 (define_insn "clzdi2"
6028 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6029 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6030 "TARGET_POWERPC64"
6031 "cntlzd %0,%1")
6033 (define_expand "ctzdi2"
6034 [(set (match_dup 2)
6035 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6036 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6037 (match_dup 2)))
6038 (clobber (scratch:CC))])
6039 (set (match_dup 4) (clz:DI (match_dup 3)))
6040 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6041 (minus:DI (const_int 63) (match_dup 4)))]
6042 "TARGET_POWERPC64"
6043 {
6044 operands[2] = gen_reg_rtx (DImode);
6045 operands[3] = gen_reg_rtx (DImode);
6046 operands[4] = gen_reg_rtx (DImode);
6047 })
6049 (define_expand "ffsdi2"
6050 [(set (match_dup 2)
6051 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6052 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6053 (match_dup 2)))
6054 (clobber (scratch:CC))])
6055 (set (match_dup 4) (clz:DI (match_dup 3)))
6056 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6057 (minus:DI (const_int 64) (match_dup 4)))]
6058 "TARGET_POWERPC64"
6059 {
6060 operands[2] = gen_reg_rtx (DImode);
6061 operands[3] = gen_reg_rtx (DImode);
6062 operands[4] = gen_reg_rtx (DImode);
6063 })
6065 (define_insn "muldi3"
6066 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6067 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6068 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6069 "TARGET_POWERPC64"
6070 "mulld %0,%1,%2"
6071 [(set_attr "type" "lmul")])
6073 (define_insn "*muldi3_internal1"
6074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6075 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6076 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6077 (const_int 0)))
6078 (clobber (match_scratch:DI 3 "=r,r"))]
6079 "TARGET_POWERPC64"
6080 "@
6081 mulld. %3,%1,%2
6082 #"
6083 [(set_attr "type" "lmul_compare")
6084 (set_attr "length" "4,8")])
6086 (define_split
6087 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6088 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6089 (match_operand:DI 2 "gpc_reg_operand" ""))
6090 (const_int 0)))
6091 (clobber (match_scratch:DI 3 ""))]
6092 "TARGET_POWERPC64 && reload_completed"
6093 [(set (match_dup 3)
6094 (mult:DI (match_dup 1) (match_dup 2)))
6095 (set (match_dup 0)
6096 (compare:CC (match_dup 3)
6097 (const_int 0)))]
6098 "")
6100 (define_insn "*muldi3_internal2"
6101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6102 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6103 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6104 (const_int 0)))
6105 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6106 (mult:DI (match_dup 1) (match_dup 2)))]
6107 "TARGET_POWERPC64"
6108 "@
6109 mulld. %0,%1,%2
6110 #"
6111 [(set_attr "type" "lmul_compare")
6112 (set_attr "length" "4,8")])
6114 (define_split
6115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6116 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6117 (match_operand:DI 2 "gpc_reg_operand" ""))
6118 (const_int 0)))
6119 (set (match_operand:DI 0 "gpc_reg_operand" "")
6120 (mult:DI (match_dup 1) (match_dup 2)))]
6121 "TARGET_POWERPC64 && reload_completed"
6122 [(set (match_dup 0)
6123 (mult:DI (match_dup 1) (match_dup 2)))
6124 (set (match_dup 3)
6125 (compare:CC (match_dup 0)
6126 (const_int 0)))]
6127 "")
6129 (define_insn "smuldi3_highpart"
6130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6131 (truncate:DI
6132 (lshiftrt:TI (mult:TI (sign_extend:TI
6133 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6134 (sign_extend:TI
6135 (match_operand:DI 2 "gpc_reg_operand" "r")))
6136 (const_int 64))))]
6137 "TARGET_POWERPC64"
6138 "mulhd %0,%1,%2"
6139 [(set_attr "type" "lmul")])
6141 (define_insn "umuldi3_highpart"
6142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6143 (truncate:DI
6144 (lshiftrt:TI (mult:TI (zero_extend:TI
6145 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6146 (zero_extend:TI
6147 (match_operand:DI 2 "gpc_reg_operand" "r")))
6148 (const_int 64))))]
6149 "TARGET_POWERPC64"
6150 "mulhdu %0,%1,%2"
6151 [(set_attr "type" "lmul")])
6153 (define_expand "divdi3"
6154 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6155 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6156 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6157 "TARGET_POWERPC64"
6158 "
6159 {
6160 if (GET_CODE (operands[2]) == CONST_INT
6161 && INTVAL (operands[2]) > 0
6162 && exact_log2 (INTVAL (operands[2])) >= 0)
6163 ;
6164 else
6165 operands[2] = force_reg (DImode, operands[2]);
6166 }")
6168 (define_expand "moddi3"
6169 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6170 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6171 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6172 "TARGET_POWERPC64"
6173 "
6174 {
6175 int i;
6176 rtx temp1;
6177 rtx temp2;
6179 if (GET_CODE (operands[2]) != CONST_INT
6180 || INTVAL (operands[2]) <= 0
6181 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6182 FAIL;
6184 temp1 = gen_reg_rtx (DImode);
6185 temp2 = gen_reg_rtx (DImode);
6187 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6188 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6189 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6190 DONE;
6191 }")
6193 (define_insn ""
6194 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6195 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6196 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6197 "TARGET_POWERPC64"
6198 "sradi %0,%1,%p2\;addze %0,%0"
6199 [(set_attr "length" "8")])
6201 (define_insn ""
6202 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6203 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6204 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6205 (const_int 0)))
6206 (clobber (match_scratch:DI 3 "=r,r"))]
6207 "TARGET_64BIT"
6208 "@
6209 sradi %3,%1,%p2\;addze. %3,%3
6210 #"
6211 [(set_attr "type" "compare")
6212 (set_attr "length" "8,12")])
6214 (define_split
6215 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6216 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6217 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6218 (const_int 0)))
6219 (clobber (match_scratch:DI 3 ""))]
6220 "TARGET_POWERPC64 && reload_completed"
6221 [(set (match_dup 3)
6222 (div:DI (match_dup 1) (match_dup 2)))
6223 (set (match_dup 0)
6224 (compare:CC (match_dup 3)
6225 (const_int 0)))]
6226 "")
6228 (define_insn ""
6229 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6230 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6231 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6232 (const_int 0)))
6233 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6234 (div:DI (match_dup 1) (match_dup 2)))]
6235 "TARGET_64BIT"
6236 "@
6237 sradi %0,%1,%p2\;addze. %0,%0
6238 #"
6239 [(set_attr "type" "compare")
6240 (set_attr "length" "8,12")])
6242 (define_split
6243 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6244 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6245 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6246 (const_int 0)))
6247 (set (match_operand:DI 0 "gpc_reg_operand" "")
6248 (div:DI (match_dup 1) (match_dup 2)))]
6249 "TARGET_POWERPC64 && reload_completed"
6250 [(set (match_dup 0)
6251 (div:DI (match_dup 1) (match_dup 2)))
6252 (set (match_dup 3)
6253 (compare:CC (match_dup 0)
6254 (const_int 0)))]
6255 "")
6257 (define_insn ""
6258 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6259 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6260 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6261 "TARGET_POWERPC64"
6262 "divd %0,%1,%2"
6263 [(set_attr "type" "ldiv")])
6265 (define_insn "udivdi3"
6266 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6267 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6268 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6269 "TARGET_POWERPC64"
6270 "divdu %0,%1,%2"
6271 [(set_attr "type" "ldiv")])
6273 (define_insn "rotldi3"
6274 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6275 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6276 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6277 "TARGET_POWERPC64"
6278 "rld%I2cl %0,%1,%H2,0")
6280 (define_insn "*rotldi3_internal2"
6281 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6282 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6283 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6284 (const_int 0)))
6285 (clobber (match_scratch:DI 3 "=r,r"))]
6286 "TARGET_64BIT"
6287 "@
6288 rld%I2cl. %3,%1,%H2,0
6289 #"
6290 [(set_attr "type" "delayed_compare")
6291 (set_attr "length" "4,8")])
6293 (define_split
6294 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6295 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6296 (match_operand:DI 2 "reg_or_cint_operand" ""))
6297 (const_int 0)))
6298 (clobber (match_scratch:DI 3 ""))]
6299 "TARGET_POWERPC64 && reload_completed"
6300 [(set (match_dup 3)
6301 (rotate:DI (match_dup 1) (match_dup 2)))
6302 (set (match_dup 0)
6303 (compare:CC (match_dup 3)
6304 (const_int 0)))]
6305 "")
6307 (define_insn "*rotldi3_internal3"
6308 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6309 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6310 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6311 (const_int 0)))
6312 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6313 (rotate:DI (match_dup 1) (match_dup 2)))]
6314 "TARGET_64BIT"
6315 "@
6316 rld%I2cl. %0,%1,%H2,0
6317 #"
6318 [(set_attr "type" "delayed_compare")
6319 (set_attr "length" "4,8")])
6321 (define_split
6322 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6323 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6324 (match_operand:DI 2 "reg_or_cint_operand" ""))
6325 (const_int 0)))
6326 (set (match_operand:DI 0 "gpc_reg_operand" "")
6327 (rotate:DI (match_dup 1) (match_dup 2)))]
6328 "TARGET_POWERPC64 && reload_completed"
6329 [(set (match_dup 0)
6330 (rotate:DI (match_dup 1) (match_dup 2)))
6331 (set (match_dup 3)
6332 (compare:CC (match_dup 0)
6333 (const_int 0)))]
6334 "")
6336 (define_insn "*rotldi3_internal4"
6337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6338 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6339 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6340 (match_operand:DI 3 "mask64_operand" "n")))]
6341 "TARGET_POWERPC64"
6342 "rld%I2c%B3 %0,%1,%H2,%S3")
6344 (define_insn "*rotldi3_internal5"
6345 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6346 (compare:CC (and:DI
6347 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6348 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6349 (match_operand:DI 3 "mask64_operand" "n,n"))
6350 (const_int 0)))
6351 (clobber (match_scratch:DI 4 "=r,r"))]
6352 "TARGET_64BIT"
6353 "@
6354 rld%I2c%B3. %4,%1,%H2,%S3
6355 #"
6356 [(set_attr "type" "delayed_compare")
6357 (set_attr "length" "4,8")])
6359 (define_split
6360 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6361 (compare:CC (and:DI
6362 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6363 (match_operand:DI 2 "reg_or_cint_operand" ""))
6364 (match_operand:DI 3 "mask64_operand" ""))
6365 (const_int 0)))
6366 (clobber (match_scratch:DI 4 ""))]
6367 "TARGET_POWERPC64 && reload_completed"
6368 [(set (match_dup 4)
6369 (and:DI (rotate:DI (match_dup 1)
6370 (match_dup 2))
6371 (match_dup 3)))
6372 (set (match_dup 0)
6373 (compare:CC (match_dup 4)
6374 (const_int 0)))]
6375 "")
6377 (define_insn "*rotldi3_internal6"
6378 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6379 (compare:CC (and:DI
6380 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6381 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6382 (match_operand:DI 3 "mask64_operand" "n,n"))
6383 (const_int 0)))
6384 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6385 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6386 "TARGET_64BIT"
6387 "@
6388 rld%I2c%B3. %0,%1,%H2,%S3
6389 #"
6390 [(set_attr "type" "delayed_compare")
6391 (set_attr "length" "4,8")])
6393 (define_split
6394 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6395 (compare:CC (and:DI
6396 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6397 (match_operand:DI 2 "reg_or_cint_operand" ""))
6398 (match_operand:DI 3 "mask64_operand" ""))
6399 (const_int 0)))
6400 (set (match_operand:DI 0 "gpc_reg_operand" "")
6401 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6402 "TARGET_POWERPC64 && reload_completed"
6403 [(set (match_dup 0)
6404 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6405 (set (match_dup 4)
6406 (compare:CC (match_dup 0)
6407 (const_int 0)))]
6408 "")
6410 (define_insn "*rotldi3_internal7"
6411 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6412 (zero_extend:DI
6413 (subreg:QI
6414 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6415 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6416 "TARGET_POWERPC64"
6417 "rld%I2cl %0,%1,%H2,56")
6419 (define_insn "*rotldi3_internal8"
6420 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6421 (compare:CC (zero_extend:DI
6422 (subreg:QI
6423 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6424 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6425 (const_int 0)))
6426 (clobber (match_scratch:DI 3 "=r,r"))]
6427 "TARGET_64BIT"
6428 "@
6429 rld%I2cl. %3,%1,%H2,56
6430 #"
6431 [(set_attr "type" "delayed_compare")
6432 (set_attr "length" "4,8")])
6434 (define_split
6435 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6436 (compare:CC (zero_extend:DI
6437 (subreg:QI
6438 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6439 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6440 (const_int 0)))
6441 (clobber (match_scratch:DI 3 ""))]
6442 "TARGET_POWERPC64 && reload_completed"
6443 [(set (match_dup 3)
6444 (zero_extend:DI (subreg:QI
6445 (rotate:DI (match_dup 1)
6446 (match_dup 2)) 0)))
6447 (set (match_dup 0)
6448 (compare:CC (match_dup 3)
6449 (const_int 0)))]
6450 "")
6452 (define_insn "*rotldi3_internal9"
6453 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6454 (compare:CC (zero_extend:DI
6455 (subreg:QI
6456 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6457 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6458 (const_int 0)))
6459 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6460 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6461 "TARGET_64BIT"
6462 "@
6463 rld%I2cl. %0,%1,%H2,56
6464 #"
6465 [(set_attr "type" "delayed_compare")
6466 (set_attr "length" "4,8")])
6468 (define_split
6469 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6470 (compare:CC (zero_extend:DI
6471 (subreg:QI
6472 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6473 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6474 (const_int 0)))
6475 (set (match_operand:DI 0 "gpc_reg_operand" "")
6476 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6477 "TARGET_POWERPC64 && reload_completed"
6478 [(set (match_dup 0)
6479 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6480 (set (match_dup 3)
6481 (compare:CC (match_dup 0)
6482 (const_int 0)))]
6483 "")
6485 (define_insn "*rotldi3_internal10"
6486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6487 (zero_extend:DI
6488 (subreg:HI
6489 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6490 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6491 "TARGET_POWERPC64"
6492 "rld%I2cl %0,%1,%H2,48")
6494 (define_insn "*rotldi3_internal11"
6495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6496 (compare:CC (zero_extend:DI
6497 (subreg:HI
6498 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6499 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6500 (const_int 0)))
6501 (clobber (match_scratch:DI 3 "=r,r"))]
6502 "TARGET_64BIT"
6503 "@
6504 rld%I2cl. %3,%1,%H2,48
6505 #"
6506 [(set_attr "type" "delayed_compare")
6507 (set_attr "length" "4,8")])
6509 (define_split
6510 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6511 (compare:CC (zero_extend:DI
6512 (subreg:HI
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6514 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6515 (const_int 0)))
6516 (clobber (match_scratch:DI 3 ""))]
6517 "TARGET_POWERPC64 && reload_completed"
6518 [(set (match_dup 3)
6519 (zero_extend:DI (subreg:HI
6520 (rotate:DI (match_dup 1)
6521 (match_dup 2)) 0)))
6522 (set (match_dup 0)
6523 (compare:CC (match_dup 3)
6524 (const_int 0)))]
6525 "")
6527 (define_insn "*rotldi3_internal12"
6528 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6529 (compare:CC (zero_extend:DI
6530 (subreg:HI
6531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6532 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6533 (const_int 0)))
6534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6535 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6536 "TARGET_64BIT"
6537 "@
6538 rld%I2cl. %0,%1,%H2,48
6539 #"
6540 [(set_attr "type" "delayed_compare")
6541 (set_attr "length" "4,8")])
6543 (define_split
6544 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6545 (compare:CC (zero_extend:DI
6546 (subreg:HI
6547 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6548 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6549 (const_int 0)))
6550 (set (match_operand:DI 0 "gpc_reg_operand" "")
6551 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6552 "TARGET_POWERPC64 && reload_completed"
6553 [(set (match_dup 0)
6554 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6555 (set (match_dup 3)
6556 (compare:CC (match_dup 0)
6557 (const_int 0)))]
6558 "")
6560 (define_insn "*rotldi3_internal13"
6561 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6562 (zero_extend:DI
6563 (subreg:SI
6564 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6565 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6566 "TARGET_POWERPC64"
6567 "rld%I2cl %0,%1,%H2,32")
6569 (define_insn "*rotldi3_internal14"
6570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6571 (compare:CC (zero_extend:DI
6572 (subreg:SI
6573 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6574 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6575 (const_int 0)))
6576 (clobber (match_scratch:DI 3 "=r,r"))]
6577 "TARGET_64BIT"
6578 "@
6579 rld%I2cl. %3,%1,%H2,32
6580 #"
6581 [(set_attr "type" "delayed_compare")
6582 (set_attr "length" "4,8")])
6584 (define_split
6585 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6586 (compare:CC (zero_extend:DI
6587 (subreg:SI
6588 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6589 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6590 (const_int 0)))
6591 (clobber (match_scratch:DI 3 ""))]
6592 "TARGET_POWERPC64 && reload_completed"
6593 [(set (match_dup 3)
6594 (zero_extend:DI (subreg:SI
6595 (rotate:DI (match_dup 1)
6596 (match_dup 2)) 0)))
6597 (set (match_dup 0)
6598 (compare:CC (match_dup 3)
6599 (const_int 0)))]
6600 "")
6602 (define_insn "*rotldi3_internal15"
6603 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6604 (compare:CC (zero_extend:DI
6605 (subreg:SI
6606 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6607 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6608 (const_int 0)))
6609 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6610 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6611 "TARGET_64BIT"
6612 "@
6613 rld%I2cl. %0,%1,%H2,32
6614 #"
6615 [(set_attr "type" "delayed_compare")
6616 (set_attr "length" "4,8")])
6618 (define_split
6619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6620 (compare:CC (zero_extend:DI
6621 (subreg:SI
6622 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6623 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6624 (const_int 0)))
6625 (set (match_operand:DI 0 "gpc_reg_operand" "")
6626 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6627 "TARGET_POWERPC64 && reload_completed"
6628 [(set (match_dup 0)
6629 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6630 (set (match_dup 3)
6631 (compare:CC (match_dup 0)
6632 (const_int 0)))]
6633 "")
6635 (define_expand "ashldi3"
6636 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6637 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6638 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6639 "TARGET_POWERPC64 || TARGET_POWER"
6640 "
6641 {
6642 if (TARGET_POWERPC64)
6643 ;
6644 else if (TARGET_POWER)
6645 {
6646 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6647 DONE;
6648 }
6649 else
6650 FAIL;
6651 }")
6653 (define_insn "*ashldi3_internal1"
6654 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6655 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6656 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6657 "TARGET_POWERPC64"
6658 "sld%I2 %0,%1,%H2"
6659 [(set_attr "length" "8")])
6661 (define_insn "*ashldi3_internal2"
6662 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6663 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6664 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6665 (const_int 0)))
6666 (clobber (match_scratch:DI 3 "=r,r"))]
6667 "TARGET_64BIT"
6668 "@
6669 sld%I2. %3,%1,%H2
6670 #"
6671 [(set_attr "type" "delayed_compare")
6672 (set_attr "length" "4,8")])
6674 (define_split
6675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6676 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6677 (match_operand:SI 2 "reg_or_cint_operand" ""))
6678 (const_int 0)))
6679 (clobber (match_scratch:DI 3 ""))]
6680 "TARGET_POWERPC64 && reload_completed"
6681 [(set (match_dup 3)
6682 (ashift:DI (match_dup 1) (match_dup 2)))
6683 (set (match_dup 0)
6684 (compare:CC (match_dup 3)
6685 (const_int 0)))]
6686 "")
6688 (define_insn "*ashldi3_internal3"
6689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6690 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6691 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6692 (const_int 0)))
6693 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6694 (ashift:DI (match_dup 1) (match_dup 2)))]
6695 "TARGET_64BIT"
6696 "@
6697 sld%I2. %0,%1,%H2
6698 #"
6699 [(set_attr "type" "delayed_compare")
6700 (set_attr "length" "4,8")])
6702 (define_split
6703 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6704 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6705 (match_operand:SI 2 "reg_or_cint_operand" ""))
6706 (const_int 0)))
6707 (set (match_operand:DI 0 "gpc_reg_operand" "")
6708 (ashift:DI (match_dup 1) (match_dup 2)))]
6709 "TARGET_POWERPC64 && reload_completed"
6710 [(set (match_dup 0)
6711 (ashift:DI (match_dup 1) (match_dup 2)))
6712 (set (match_dup 3)
6713 (compare:CC (match_dup 0)
6714 (const_int 0)))]
6715 "")
6717 (define_insn "*ashldi3_internal4"
6718 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6719 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6720 (match_operand:SI 2 "const_int_operand" "i"))
6721 (match_operand:DI 3 "const_int_operand" "n")))]
6722 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6723 "rldic %0,%1,%H2,%W3")
6725 (define_insn "ashldi3_internal5"
6726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6727 (compare:CC
6728 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6729 (match_operand:SI 2 "const_int_operand" "i,i"))
6730 (match_operand:DI 3 "const_int_operand" "n,n"))
6731 (const_int 0)))
6732 (clobber (match_scratch:DI 4 "=r,r"))]
6733 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6734 "@
6735 rldic. %4,%1,%H2,%W3
6736 #"
6737 [(set_attr "type" "delayed_compare")
6738 (set_attr "length" "4,8")])
6740 (define_split
6741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6742 (compare:CC
6743 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6744 (match_operand:SI 2 "const_int_operand" ""))
6745 (match_operand:DI 3 "const_int_operand" ""))
6746 (const_int 0)))
6747 (clobber (match_scratch:DI 4 ""))]
6748 "TARGET_POWERPC64 && reload_completed
6749 && includes_rldic_lshift_p (operands[2], operands[3])"
6750 [(set (match_dup 4)
6751 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6752 (match_dup 3)))
6753 (set (match_dup 0)
6754 (compare:CC (match_dup 4)
6755 (const_int 0)))]
6756 "")
6758 (define_insn "*ashldi3_internal6"
6759 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6760 (compare:CC
6761 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6762 (match_operand:SI 2 "const_int_operand" "i,i"))
6763 (match_operand:DI 3 "const_int_operand" "n,n"))
6764 (const_int 0)))
6765 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6766 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6767 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6768 "@
6769 rldic. %0,%1,%H2,%W3
6770 #"
6771 [(set_attr "type" "delayed_compare")
6772 (set_attr "length" "4,8")])
6774 (define_split
6775 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6776 (compare:CC
6777 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6778 (match_operand:SI 2 "const_int_operand" ""))
6779 (match_operand:DI 3 "const_int_operand" ""))
6780 (const_int 0)))
6781 (set (match_operand:DI 0 "gpc_reg_operand" "")
6782 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6783 "TARGET_POWERPC64 && reload_completed
6784 && includes_rldic_lshift_p (operands[2], operands[3])"
6785 [(set (match_dup 0)
6786 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6787 (match_dup 3)))
6788 (set (match_dup 4)
6789 (compare:CC (match_dup 0)
6790 (const_int 0)))]
6791 "")
6793 (define_insn "*ashldi3_internal7"
6794 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6795 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6796 (match_operand:SI 2 "const_int_operand" "i"))
6797 (match_operand:DI 3 "mask64_operand" "n")))]
6798 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6799 "rldicr %0,%1,%H2,%S3")
6801 (define_insn "ashldi3_internal8"
6802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6803 (compare:CC
6804 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6805 (match_operand:SI 2 "const_int_operand" "i,i"))
6806 (match_operand:DI 3 "mask64_operand" "n,n"))
6807 (const_int 0)))
6808 (clobber (match_scratch:DI 4 "=r,r"))]
6809 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6810 "@
6811 rldicr. %4,%1,%H2,%S3
6812 #"
6813 [(set_attr "type" "delayed_compare")
6814 (set_attr "length" "4,8")])
6816 (define_split
6817 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6818 (compare:CC
6819 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6820 (match_operand:SI 2 "const_int_operand" ""))
6821 (match_operand:DI 3 "mask64_operand" ""))
6822 (const_int 0)))
6823 (clobber (match_scratch:DI 4 ""))]
6824 "TARGET_POWERPC64 && reload_completed
6825 && includes_rldicr_lshift_p (operands[2], operands[3])"
6826 [(set (match_dup 4)
6827 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6828 (match_dup 3)))
6829 (set (match_dup 0)
6830 (compare:CC (match_dup 4)
6831 (const_int 0)))]
6832 "")
6834 (define_insn "*ashldi3_internal9"
6835 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6836 (compare:CC
6837 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6838 (match_operand:SI 2 "const_int_operand" "i,i"))
6839 (match_operand:DI 3 "mask64_operand" "n,n"))
6840 (const_int 0)))
6841 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6842 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6843 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6844 "@
6845 rldicr. %0,%1,%H2,%S3
6846 #"
6847 [(set_attr "type" "delayed_compare")
6848 (set_attr "length" "4,8")])
6850 (define_split
6851 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6852 (compare:CC
6853 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6854 (match_operand:SI 2 "const_int_operand" ""))
6855 (match_operand:DI 3 "mask64_operand" ""))
6856 (const_int 0)))
6857 (set (match_operand:DI 0 "gpc_reg_operand" "")
6858 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6859 "TARGET_POWERPC64 && reload_completed
6860 && includes_rldicr_lshift_p (operands[2], operands[3])"
6861 [(set (match_dup 0)
6862 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6863 (match_dup 3)))
6864 (set (match_dup 4)
6865 (compare:CC (match_dup 0)
6866 (const_int 0)))]
6867 "")
6869 (define_expand "lshrdi3"
6870 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6871 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6872 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6873 "TARGET_POWERPC64 || TARGET_POWER"
6874 "
6875 {
6876 if (TARGET_POWERPC64)
6877 ;
6878 else if (TARGET_POWER)
6879 {
6880 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6881 DONE;
6882 }
6883 else
6884 FAIL;
6885 }")
6887 (define_insn "*lshrdi3_internal1"
6888 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6889 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6890 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6891 "TARGET_POWERPC64"
6892 "srd%I2 %0,%1,%H2")
6894 (define_insn "*lshrdi3_internal2"
6895 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6896 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6897 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6898 (const_int 0)))
6899 (clobber (match_scratch:DI 3 "=r,r"))]
6900 "TARGET_64BIT "
6901 "@
6902 srd%I2. %3,%1,%H2
6903 #"
6904 [(set_attr "type" "delayed_compare")
6905 (set_attr "length" "4,8")])
6907 (define_split
6908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6909 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6910 (match_operand:SI 2 "reg_or_cint_operand" ""))
6911 (const_int 0)))
6912 (clobber (match_scratch:DI 3 ""))]
6913 "TARGET_POWERPC64 && reload_completed"
6914 [(set (match_dup 3)
6915 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6916 (set (match_dup 0)
6917 (compare:CC (match_dup 3)
6918 (const_int 0)))]
6919 "")
6921 (define_insn "*lshrdi3_internal3"
6922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6923 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6924 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6925 (const_int 0)))
6926 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6927 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6928 "TARGET_64BIT"
6929 "@
6930 srd%I2. %0,%1,%H2
6931 #"
6932 [(set_attr "type" "delayed_compare")
6933 (set_attr "length" "4,8")])
6935 (define_split
6936 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6937 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6938 (match_operand:SI 2 "reg_or_cint_operand" ""))
6939 (const_int 0)))
6940 (set (match_operand:DI 0 "gpc_reg_operand" "")
6941 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6942 "TARGET_POWERPC64 && reload_completed"
6943 [(set (match_dup 0)
6944 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6945 (set (match_dup 3)
6946 (compare:CC (match_dup 0)
6947 (const_int 0)))]
6948 "")
6950 (define_expand "ashrdi3"
6951 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6952 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6953 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6954 "WORDS_BIG_ENDIAN"
6955 "
6956 {
6957 if (TARGET_POWERPC64)
6958 ;
6959 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6960 {
6961 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6962 DONE;
6963 }
6964 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6965 && WORDS_BIG_ENDIAN)
6966 {
6967 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6968 DONE;
6969 }
6970 else
6971 FAIL;
6972 }")
6974 (define_insn "*ashrdi3_internal1"
6975 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6976 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6977 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6978 "TARGET_POWERPC64"
6979 "srad%I2 %0,%1,%H2")
6981 (define_insn "*ashrdi3_internal2"
6982 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6983 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6984 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6985 (const_int 0)))
6986 (clobber (match_scratch:DI 3 "=r,r"))]
6987 "TARGET_64BIT"
6988 "@
6989 srad%I2. %3,%1,%H2
6990 #"
6991 [(set_attr "type" "delayed_compare")
6992 (set_attr "length" "4,8")])
6994 (define_split
6995 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6996 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6997 (match_operand:SI 2 "reg_or_cint_operand" ""))
6998 (const_int 0)))
6999 (clobber (match_scratch:DI 3 ""))]
7000 "TARGET_POWERPC64 && reload_completed"
7001 [(set (match_dup 3)
7002 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7003 (set (match_dup 0)
7004 (compare:CC (match_dup 3)
7005 (const_int 0)))]
7006 "")
7008 (define_insn "*ashrdi3_internal3"
7009 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7010 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7011 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7012 (const_int 0)))
7013 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7014 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7015 "TARGET_64BIT"
7016 "@
7017 srad%I2. %0,%1,%H2
7018 #"
7019 [(set_attr "type" "delayed_compare")
7020 (set_attr "length" "4,8")])
7022 (define_split
7023 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7024 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7025 (match_operand:SI 2 "reg_or_cint_operand" ""))
7026 (const_int 0)))
7027 (set (match_operand:DI 0 "gpc_reg_operand" "")
7028 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7029 "TARGET_POWERPC64 && reload_completed"
7030 [(set (match_dup 0)
7031 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7032 (set (match_dup 3)
7033 (compare:CC (match_dup 0)
7034 (const_int 0)))]
7035 "")
7037 (define_insn "anddi3"
7038 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7039 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7040 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7041 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
7042 "TARGET_POWERPC64"
7043 "@
7044 and %0,%1,%2
7045 rldic%B2 %0,%1,0,%S2
7046 andi. %0,%1,%b2
7047 andis. %0,%1,%u2
7048 #"
7049 [(set_attr "length" "4,4,4,4,8")])
7051 (define_split
7052 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7053 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7054 (match_operand:DI 2 "mask64_2_operand" "")))
7055 (clobber (match_scratch:CC 3 ""))]
7056 "TARGET_POWERPC64
7057 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7058 && !mask64_operand (operands[2], DImode)"
7059 [(set (match_dup 0)
7060 (and:DI (rotate:DI (match_dup 1)
7061 (match_dup 4))
7062 (match_dup 5)))
7063 (set (match_dup 0)
7064 (and:DI (rotate:DI (match_dup 0)
7065 (match_dup 6))
7066 (match_dup 7)))]
7067 "
7068 {
7069 build_mask64_2_operands (operands[2], &operands[4]);
7070 }")
7072 (define_insn "*anddi3_internal2"
7073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7074 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7075 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7076 (const_int 0)))
7077 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7078 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7079 "TARGET_64BIT"
7080 "@
7081 and. %3,%1,%2
7082 rldic%B2. %3,%1,0,%S2
7083 andi. %3,%1,%b2
7084 andis. %3,%1,%u2
7085 #
7086 #
7087 #
7088 #
7089 #
7090 #"
7091 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7092 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7094 (define_split
7095 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7096 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7097 (match_operand:DI 2 "and64_operand" ""))
7098 (const_int 0)))
7099 (clobber (match_scratch:DI 3 ""))
7100 (clobber (match_scratch:CC 4 ""))]
7101 "TARGET_POWERPC64 && reload_completed"
7102 [(parallel [(set (match_dup 3)
7103 (and:DI (match_dup 1)
7104 (match_dup 2)))
7105 (clobber (match_dup 4))])
7106 (set (match_dup 0)
7107 (compare:CC (match_dup 3)
7108 (const_int 0)))]
7109 "")
7111 (define_split
7112 [(set (match_operand:CC 0 "cc_reg_operand" "")
7113 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7114 (match_operand:DI 2 "mask64_2_operand" ""))
7115 (const_int 0)))
7116 (clobber (match_scratch:DI 3 ""))
7117 (clobber (match_scratch:CC 4 ""))]
7118 "TARGET_POWERPC64 && reload_completed
7119 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7120 && !mask64_operand (operands[2], DImode)"
7121 [(set (match_dup 3)
7122 (and:DI (rotate:DI (match_dup 1)
7123 (match_dup 5))
7124 (match_dup 6)))
7125 (parallel [(set (match_dup 0)
7126 (compare:CC (and:DI (rotate:DI (match_dup 3)
7127 (match_dup 7))
7128 (match_dup 8))
7129 (const_int 0)))
7130 (clobber (match_dup 3))])]
7131 "
7132 {
7133 build_mask64_2_operands (operands[2], &operands[5]);
7134 }")
7136 (define_insn "*anddi3_internal3"
7137 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7138 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7139 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7140 (const_int 0)))
7141 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7142 (and:DI (match_dup 1) (match_dup 2)))
7143 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7144 "TARGET_64BIT"
7145 "@
7146 and. %0,%1,%2
7147 rldic%B2. %0,%1,0,%S2
7148 andi. %0,%1,%b2
7149 andis. %0,%1,%u2
7150 #
7151 #
7152 #
7153 #
7154 #
7155 #"
7156 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7157 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7159 (define_split
7160 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7161 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7162 (match_operand:DI 2 "and64_operand" ""))
7163 (const_int 0)))
7164 (set (match_operand:DI 0 "gpc_reg_operand" "")
7165 (and:DI (match_dup 1) (match_dup 2)))
7166 (clobber (match_scratch:CC 4 ""))]
7167 "TARGET_POWERPC64 && reload_completed"
7168 [(parallel [(set (match_dup 0)
7169 (and:DI (match_dup 1) (match_dup 2)))
7170 (clobber (match_dup 4))])
7171 (set (match_dup 3)
7172 (compare:CC (match_dup 0)
7173 (const_int 0)))]
7174 "")
7176 (define_split
7177 [(set (match_operand:CC 3 "cc_reg_operand" "")
7178 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7179 (match_operand:DI 2 "mask64_2_operand" ""))
7180 (const_int 0)))
7181 (set (match_operand:DI 0 "gpc_reg_operand" "")
7182 (and:DI (match_dup 1) (match_dup 2)))
7183 (clobber (match_scratch:CC 4 ""))]
7184 "TARGET_POWERPC64 && reload_completed
7185 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7186 && !mask64_operand (operands[2], DImode)"
7187 [(set (match_dup 0)
7188 (and:DI (rotate:DI (match_dup 1)
7189 (match_dup 5))
7190 (match_dup 6)))
7191 (parallel [(set (match_dup 3)
7192 (compare:CC (and:DI (rotate:DI (match_dup 0)
7193 (match_dup 7))
7194 (match_dup 8))
7195 (const_int 0)))
7196 (set (match_dup 0)
7197 (and:DI (rotate:DI (match_dup 0)
7198 (match_dup 7))
7199 (match_dup 8)))])]
7200 "
7201 {
7202 build_mask64_2_operands (operands[2], &operands[5]);
7203 }")
7205 (define_expand "iordi3"
7206 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7207 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7208 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7209 "TARGET_POWERPC64"
7210 "
7211 {
7212 if (non_logical_cint_operand (operands[2], DImode))
7213 {
7214 HOST_WIDE_INT value;
7215 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7216 ? operands[0] : gen_reg_rtx (DImode));
7218 if (GET_CODE (operands[2]) == CONST_INT)
7219 {
7220 value = INTVAL (operands[2]);
7221 emit_insn (gen_iordi3 (tmp, operands[1],
7222 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7223 }
7224 else
7225 {
7226 value = CONST_DOUBLE_LOW (operands[2]);
7227 emit_insn (gen_iordi3 (tmp, operands[1],
7228 immed_double_const (value
7229 & (~ (HOST_WIDE_INT) 0xffff),
7230 0, DImode)));
7231 }
7233 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7234 DONE;
7235 }
7236 }")
7238 (define_expand "xordi3"
7239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7240 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7241 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7242 "TARGET_POWERPC64"
7243 "
7244 {
7245 if (non_logical_cint_operand (operands[2], DImode))
7246 {
7247 HOST_WIDE_INT value;
7248 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7249 ? operands[0] : gen_reg_rtx (DImode));
7251 if (GET_CODE (operands[2]) == CONST_INT)
7252 {
7253 value = INTVAL (operands[2]);
7254 emit_insn (gen_xordi3 (tmp, operands[1],
7255 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7256 }
7257 else
7258 {
7259 value = CONST_DOUBLE_LOW (operands[2]);
7260 emit_insn (gen_xordi3 (tmp, operands[1],
7261 immed_double_const (value
7262 & (~ (HOST_WIDE_INT) 0xffff),
7263 0, DImode)));
7264 }
7266 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7267 DONE;
7268 }
7269 }")
7271 (define_insn "*booldi3_internal1"
7272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7273 (match_operator:DI 3 "boolean_or_operator"
7274 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7275 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7276 "TARGET_POWERPC64"
7277 "@
7278 %q3 %0,%1,%2
7279 %q3i %0,%1,%b2
7280 %q3is %0,%1,%u2")
7282 (define_insn "*booldi3_internal2"
7283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7284 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7285 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7286 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7287 (const_int 0)))
7288 (clobber (match_scratch:DI 3 "=r,r"))]
7289 "TARGET_64BIT"
7290 "@
7291 %q4. %3,%1,%2
7292 #"
7293 [(set_attr "type" "compare")
7294 (set_attr "length" "4,8")])
7296 (define_split
7297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7298 (compare:CC (match_operator:DI 4 "boolean_operator"
7299 [(match_operand:DI 1 "gpc_reg_operand" "")
7300 (match_operand:DI 2 "gpc_reg_operand" "")])
7301 (const_int 0)))
7302 (clobber (match_scratch:DI 3 ""))]
7303 "TARGET_POWERPC64 && reload_completed"
7304 [(set (match_dup 3) (match_dup 4))
7305 (set (match_dup 0)
7306 (compare:CC (match_dup 3)
7307 (const_int 0)))]
7308 "")
7310 (define_insn "*booldi3_internal3"
7311 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7312 (compare:CC (match_operator:DI 4 "boolean_operator"
7313 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7314 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7315 (const_int 0)))
7316 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7317 (match_dup 4))]
7318 "TARGET_64BIT"
7319 "@
7320 %q4. %0,%1,%2
7321 #"
7322 [(set_attr "type" "compare")
7323 (set_attr "length" "4,8")])
7325 (define_split
7326 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7327 (compare:CC (match_operator:DI 4 "boolean_operator"
7328 [(match_operand:DI 1 "gpc_reg_operand" "")
7329 (match_operand:DI 2 "gpc_reg_operand" "")])
7330 (const_int 0)))
7331 (set (match_operand:DI 0 "gpc_reg_operand" "")
7332 (match_dup 4))]
7333 "TARGET_POWERPC64 && reload_completed"
7334 [(set (match_dup 0) (match_dup 4))
7335 (set (match_dup 3)
7336 (compare:CC (match_dup 0)
7337 (const_int 0)))]
7338 "")
7340 ;; Split a logical operation that we can't do in one insn into two insns,
7341 ;; each of which does one 16-bit part. This is used by combine.
7343 (define_split
7344 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7345 (match_operator:DI 3 "boolean_or_operator"
7346 [(match_operand:DI 1 "gpc_reg_operand" "")
7347 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7348 "TARGET_POWERPC64"
7349 [(set (match_dup 0) (match_dup 4))
7350 (set (match_dup 0) (match_dup 5))]
7351 "
7352 {
7353 rtx i3,i4;
7355 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7356 {
7357 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7358 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7359 0, DImode);
7360 i4 = GEN_INT (value & 0xffff);
7361 }
7362 else
7363 {
7364 i3 = GEN_INT (INTVAL (operands[2])
7365 & (~ (HOST_WIDE_INT) 0xffff));
7366 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7367 }
7368 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7369 operands[1], i3);
7370 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7371 operands[0], i4);
7372 }")
7374 (define_insn "*boolcdi3_internal1"
7375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7376 (match_operator:DI 3 "boolean_operator"
7377 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7378 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7379 "TARGET_POWERPC64"
7380 "%q3 %0,%2,%1")
7382 (define_insn "*boolcdi3_internal2"
7383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7384 (compare:CC (match_operator:DI 4 "boolean_operator"
7385 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7386 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7387 (const_int 0)))
7388 (clobber (match_scratch:DI 3 "=r,r"))]
7389 "TARGET_64BIT"
7390 "@
7391 %q4. %3,%2,%1
7392 #"
7393 [(set_attr "type" "compare")
7394 (set_attr "length" "4,8")])
7396 (define_split
7397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7398 (compare:CC (match_operator:DI 4 "boolean_operator"
7399 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7400 (match_operand:DI 2 "gpc_reg_operand" "")])
7401 (const_int 0)))
7402 (clobber (match_scratch:DI 3 ""))]
7403 "TARGET_POWERPC64 && reload_completed"
7404 [(set (match_dup 3) (match_dup 4))
7405 (set (match_dup 0)
7406 (compare:CC (match_dup 3)
7407 (const_int 0)))]
7408 "")
7410 (define_insn "*boolcdi3_internal3"
7411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7412 (compare:CC (match_operator:DI 4 "boolean_operator"
7413 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7414 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7415 (const_int 0)))
7416 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7417 (match_dup 4))]
7418 "TARGET_64BIT"
7419 "@
7420 %q4. %0,%2,%1
7421 #"
7422 [(set_attr "type" "compare")
7423 (set_attr "length" "4,8")])
7425 (define_split
7426 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7427 (compare:CC (match_operator:DI 4 "boolean_operator"
7428 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7429 (match_operand:DI 2 "gpc_reg_operand" "")])
7430 (const_int 0)))
7431 (set (match_operand:DI 0 "gpc_reg_operand" "")
7432 (match_dup 4))]
7433 "TARGET_POWERPC64 && reload_completed"
7434 [(set (match_dup 0) (match_dup 4))
7435 (set (match_dup 3)
7436 (compare:CC (match_dup 0)
7437 (const_int 0)))]
7438 "")
7440 (define_insn "*boolccdi3_internal1"
7441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7442 (match_operator:DI 3 "boolean_operator"
7443 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7444 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7445 "TARGET_POWERPC64"
7446 "%q3 %0,%1,%2")
7448 (define_insn "*boolccdi3_internal2"
7449 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7450 (compare:CC (match_operator:DI 4 "boolean_operator"
7451 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7452 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7453 (const_int 0)))
7454 (clobber (match_scratch:DI 3 "=r,r"))]
7455 "TARGET_64BIT"
7456 "@
7457 %q4. %3,%1,%2
7458 #"
7459 [(set_attr "type" "compare")
7460 (set_attr "length" "4,8")])
7462 (define_split
7463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7464 (compare:CC (match_operator:DI 4 "boolean_operator"
7465 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7466 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7467 (const_int 0)))
7468 (clobber (match_scratch:DI 3 ""))]
7469 "TARGET_POWERPC64 && reload_completed"
7470 [(set (match_dup 3) (match_dup 4))
7471 (set (match_dup 0)
7472 (compare:CC (match_dup 3)
7473 (const_int 0)))]
7474 "")
7476 (define_insn "*boolccdi3_internal3"
7477 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7478 (compare:CC (match_operator:DI 4 "boolean_operator"
7479 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7480 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7481 (const_int 0)))
7482 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7483 (match_dup 4))]
7484 "TARGET_64BIT"
7485 "@
7486 %q4. %0,%1,%2
7487 #"
7488 [(set_attr "type" "compare")
7489 (set_attr "length" "4,8")])
7491 (define_split
7492 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7493 (compare:CC (match_operator:DI 4 "boolean_operator"
7494 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7495 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7496 (const_int 0)))
7497 (set (match_operand:DI 0 "gpc_reg_operand" "")
7498 (match_dup 4))]
7499 "TARGET_POWERPC64 && reload_completed"
7500 [(set (match_dup 0) (match_dup 4))
7501 (set (match_dup 3)
7502 (compare:CC (match_dup 0)
7503 (const_int 0)))]
7504 "")
7505 \f
7506 ;; Now define ways of moving data around.
7508 ;; Elf specific ways of loading addresses for non-PIC code.
7509 ;; The output of this could be r0, but we make a very strong
7510 ;; preference for a base register because it will usually
7511 ;; be needed there.
7512 (define_insn "elf_high"
7513 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7514 (high:SI (match_operand 1 "" "")))]
7515 "TARGET_ELF && ! TARGET_64BIT"
7516 "{liu|lis} %0,%1@ha")
7518 (define_insn "elf_low"
7519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7520 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7521 (match_operand 2 "" "")))]
7522 "TARGET_ELF && ! TARGET_64BIT"
7523 "@
7524 {cal|la} %0,%2@l(%1)
7525 {ai|addic} %0,%1,%K2")
7527 ;; Mach-O PIC trickery.
7528 (define_insn "macho_high"
7529 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7530 (high:SI (match_operand 1 "" "")))]
7531 "TARGET_MACHO && ! TARGET_64BIT"
7532 "{liu|lis} %0,ha16(%1)")
7534 (define_insn "macho_low"
7535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7536 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7537 (match_operand 2 "" "")))]
7538 "TARGET_MACHO && ! TARGET_64BIT"
7539 "@
7540 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7541 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7543 ;; Set up a register with a value from the GOT table
7545 (define_expand "movsi_got"
7546 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7547 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7548 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7549 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7550 "
7551 {
7552 if (GET_CODE (operands[1]) == CONST)
7553 {
7554 rtx offset = const0_rtx;
7555 HOST_WIDE_INT value;
7557 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7558 value = INTVAL (offset);
7559 if (value != 0)
7560 {
7561 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7562 emit_insn (gen_movsi_got (tmp, operands[1]));
7563 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7564 DONE;
7565 }
7566 }
7568 operands[2] = rs6000_got_register (operands[1]);
7569 }")
7571 (define_insn "*movsi_got_internal"
7572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7573 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7574 (match_operand:SI 2 "gpc_reg_operand" "b")]
7575 UNSPEC_MOVSI_GOT))]
7576 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7577 "{l|lwz} %0,%a1@got(%2)"
7578 [(set_attr "type" "load")])
7580 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7581 ;; didn't get allocated to a hard register.
7582 (define_split
7583 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7584 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7585 (match_operand:SI 2 "memory_operand" "")]
7586 UNSPEC_MOVSI_GOT))]
7587 "DEFAULT_ABI == ABI_V4
7588 && flag_pic == 1
7589 && (reload_in_progress || reload_completed)"
7590 [(set (match_dup 0) (match_dup 2))
7591 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7592 UNSPEC_MOVSI_GOT))]
7593 "")
7595 ;; For SI, we special-case integers that can't be loaded in one insn. We
7596 ;; do the load 16-bits at a time. We could do this by loading from memory,
7597 ;; and this is even supposed to be faster, but it is simpler not to get
7598 ;; integers in the TOC.
7599 (define_expand "movsi"
7600 [(set (match_operand:SI 0 "general_operand" "")
7601 (match_operand:SI 1 "any_operand" ""))]
7602 ""
7603 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7605 (define_insn "movsi_low"
7606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7607 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7608 (match_operand 2 "" ""))))]
7609 "TARGET_MACHO && ! TARGET_64BIT"
7610 "{l|lwz} %0,lo16(%2)(%1)"
7611 [(set_attr "type" "load")
7612 (set_attr "length" "4")])
7614 (define_insn "movsi_low_st"
7615 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7616 (match_operand 2 "" "")))
7617 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7618 "TARGET_MACHO && ! TARGET_64BIT"
7619 "{st|stw} %0,lo16(%2)(%1)"
7620 [(set_attr "type" "store")
7621 (set_attr "length" "4")])
7623 (define_insn "movdf_low"
7624 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7625 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7626 (match_operand 2 "" ""))))]
7627 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7628 "*
7629 {
7630 switch (which_alternative)
7631 {
7632 case 0:
7633 return \"lfd %0,lo16(%2)(%1)\";
7634 case 1:
7635 {
7636 rtx operands2[4];
7637 operands2[0] = operands[0];
7638 operands2[1] = operands[1];
7639 operands2[2] = operands[2];
7640 if (TARGET_POWERPC64 && TARGET_32BIT)
7641 /* Note, old assemblers didn't support relocation here. */
7642 return \"ld %0,lo16(%2)(%1)\";
7643 else
7644 {
7645 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7646 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7647 #if TARGET_MACHO
7648 if (MACHO_DYNAMIC_NO_PIC_P)
7649 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7650 else
7651 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7652 although in practice it almost always is. */
7653 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7654 #endif
7655 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7656 }
7657 }
7658 default:
7659 abort();
7660 }
7661 }"
7662 [(set_attr "type" "load")
7663 (set_attr "length" "4,12")])
7665 (define_insn "movdf_low_st"
7666 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7667 (match_operand 2 "" "")))
7668 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7669 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7670 "stfd %0,lo16(%2)(%1)"
7671 [(set_attr "type" "store")
7672 (set_attr "length" "4")])
7674 (define_insn "movsf_low"
7675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7676 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7677 (match_operand 2 "" ""))))]
7678 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7679 "@
7680 lfs %0,lo16(%2)(%1)
7681 {l|lwz} %0,lo16(%2)(%1)"
7682 [(set_attr "type" "load")
7683 (set_attr "length" "4")])
7685 (define_insn "movsf_low_st"
7686 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7687 (match_operand 2 "" "")))
7688 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7689 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7690 "@
7691 stfs %0,lo16(%2)(%1)
7692 {st|stw} %0,lo16(%2)(%1)"
7693 [(set_attr "type" "store")
7694 (set_attr "length" "4")])
7696 (define_insn "*movsi_internal1"
7697 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7698 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7699 "gpc_reg_operand (operands[0], SImode)
7700 || gpc_reg_operand (operands[1], SImode)"
7701 "@
7702 mr %0,%1
7703 {cal|la} %0,%a1
7704 {l%U1%X1|lwz%U1%X1} %0,%1
7705 {st%U0%X0|stw%U0%X0} %1,%0
7706 {lil|li} %0,%1
7707 {liu|lis} %0,%v1
7708 #
7709 {cal|la} %0,%a1
7710 mf%1 %0
7711 mt%0 %1
7712 mt%0 %1
7713 mt%0 %1
7714 {cror 0,0,0|nop}"
7715 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7716 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7718 ;; Split a load of a large constant into the appropriate two-insn
7719 ;; sequence.
7721 (define_split
7722 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7723 (match_operand:SI 1 "const_int_operand" ""))]
7724 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7725 && (INTVAL (operands[1]) & 0xffff) != 0"
7726 [(set (match_dup 0)
7727 (match_dup 2))
7728 (set (match_dup 0)
7729 (ior:SI (match_dup 0)
7730 (match_dup 3)))]
7731 "
7732 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7734 if (tem == operands[0])
7735 DONE;
7736 else
7737 FAIL;
7738 }")
7740 (define_insn "*movsi_internal2"
7741 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7742 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7743 (const_int 0)))
7744 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7745 "TARGET_32BIT"
7746 "@
7747 {cmpi|cmpwi} %2,%0,0
7748 mr. %0,%1
7749 #"
7750 [(set_attr "type" "cmp,compare,cmp")
7751 (set_attr "length" "4,4,8")])
7753 (define_split
7754 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7755 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7756 (const_int 0)))
7757 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7758 "TARGET_32BIT && reload_completed"
7759 [(set (match_dup 0) (match_dup 1))
7760 (set (match_dup 2)
7761 (compare:CC (match_dup 0)
7762 (const_int 0)))]
7763 "")
7764 \f
7765 (define_expand "movhi"
7766 [(set (match_operand:HI 0 "general_operand" "")
7767 (match_operand:HI 1 "any_operand" ""))]
7768 ""
7769 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7771 (define_insn "*movhi_internal"
7772 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7773 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7774 "gpc_reg_operand (operands[0], HImode)
7775 || gpc_reg_operand (operands[1], HImode)"
7776 "@
7777 mr %0,%1
7778 lhz%U1%X1 %0,%1
7779 sth%U0%X0 %1,%0
7780 {lil|li} %0,%w1
7781 mf%1 %0
7782 mt%0 %1
7783 mt%0 %1
7784 {cror 0,0,0|nop}"
7785 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7787 (define_expand "movqi"
7788 [(set (match_operand:QI 0 "general_operand" "")
7789 (match_operand:QI 1 "any_operand" ""))]
7790 ""
7791 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7793 (define_insn "*movqi_internal"
7794 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7795 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7796 "gpc_reg_operand (operands[0], QImode)
7797 || gpc_reg_operand (operands[1], QImode)"
7798 "@
7799 mr %0,%1
7800 lbz%U1%X1 %0,%1
7801 stb%U0%X0 %1,%0
7802 {lil|li} %0,%1
7803 mf%1 %0
7804 mt%0 %1
7805 mt%0 %1
7806 {cror 0,0,0|nop}"
7807 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7808 \f
7809 ;; Here is how to move condition codes around. When we store CC data in
7810 ;; an integer register or memory, we store just the high-order 4 bits.
7811 ;; This lets us not shift in the most common case of CR0.
7812 (define_expand "movcc"
7813 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7814 (match_operand:CC 1 "nonimmediate_operand" ""))]
7815 ""
7816 "")
7818 (define_insn "*movcc_internal1"
7819 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7820 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7821 "register_operand (operands[0], CCmode)
7822 || register_operand (operands[1], CCmode)"
7823 "@
7824 mcrf %0,%1
7825 mtcrf 128,%1
7826 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7827 mfcr %0%Q1
7828 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7829 mr %0,%1
7830 mf%1 %0
7831 mt%0 %1
7832 mt%0 %1
7833 {l%U1%X1|lwz%U1%X1} %0,%1
7834 {st%U0%U1|stw%U0%U1} %1,%0"
7835 [(set (attr "type")
7836 (cond [(eq_attr "alternative" "0")
7837 (const_string "cr_logical")
7838 (eq_attr "alternative" "1,2")
7839 (const_string "mtcr")
7840 (eq_attr "alternative" "5,7")
7841 (const_string "integer")
7842 (eq_attr "alternative" "6")
7843 (const_string "mfjmpr")
7844 (eq_attr "alternative" "8")
7845 (const_string "mtjmpr")
7846 (eq_attr "alternative" "9")
7847 (const_string "load")
7848 (eq_attr "alternative" "10")
7849 (const_string "store")
7850 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7851 (const_string "mfcrf")
7852 ]
7853 (const_string "mfcr")))
7854 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7855 \f
7856 ;; For floating-point, we normally deal with the floating-point registers
7857 ;; unless -msoft-float is used. The sole exception is that parameter passing
7858 ;; can produce floating-point values in fixed-point registers. Unless the
7859 ;; value is a simple constant or already in memory, we deal with this by
7860 ;; allocating memory and copying the value explicitly via that memory location.
7861 (define_expand "movsf"
7862 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7863 (match_operand:SF 1 "any_operand" ""))]
7864 ""
7865 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7867 (define_split
7868 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7869 (match_operand:SF 1 "const_double_operand" ""))]
7870 "reload_completed
7871 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7872 || (GET_CODE (operands[0]) == SUBREG
7873 && GET_CODE (SUBREG_REG (operands[0])) == REG
7874 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7875 [(set (match_dup 2) (match_dup 3))]
7876 "
7877 {
7878 long l;
7879 REAL_VALUE_TYPE rv;
7881 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7882 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7884 if (! TARGET_POWERPC64)
7885 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7886 else
7887 operands[2] = gen_lowpart (SImode, operands[0]);
7889 operands[3] = gen_int_mode (l, SImode);
7890 }")
7892 (define_insn "*movsf_hardfloat"
7893 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7894 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7895 "(gpc_reg_operand (operands[0], SFmode)
7896 || gpc_reg_operand (operands[1], SFmode))
7897 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7898 "@
7899 mr %0,%1
7900 {l%U1%X1|lwz%U1%X1} %0,%1
7901 {st%U0%X0|stw%U0%X0} %1,%0
7902 fmr %0,%1
7903 lfs%U1%X1 %0,%1
7904 stfs%U0%X0 %1,%0
7905 mt%0 %1
7906 mt%0 %1
7907 mf%1 %0
7908 {cror 0,0,0|nop}
7909 #
7910 #"
7911 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7912 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7914 (define_insn "*movsf_softfloat"
7915 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7916 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7917 "(gpc_reg_operand (operands[0], SFmode)
7918 || gpc_reg_operand (operands[1], SFmode))
7919 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7920 "@
7921 mr %0,%1
7922 mt%0 %1
7923 mt%0 %1
7924 mf%1 %0
7925 {l%U1%X1|lwz%U1%X1} %0,%1
7926 {st%U0%X0|stw%U0%X0} %1,%0
7927 {lil|li} %0,%1
7928 {liu|lis} %0,%v1
7929 {cal|la} %0,%a1
7930 #
7931 #
7932 {cror 0,0,0|nop}"
7933 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7934 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7936 \f
7937 (define_expand "movdf"
7938 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7939 (match_operand:DF 1 "any_operand" ""))]
7940 ""
7941 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7943 (define_split
7944 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7945 (match_operand:DF 1 "const_int_operand" ""))]
7946 "! TARGET_POWERPC64 && reload_completed
7947 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7948 || (GET_CODE (operands[0]) == SUBREG
7949 && GET_CODE (SUBREG_REG (operands[0])) == REG
7950 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7951 [(set (match_dup 2) (match_dup 4))
7952 (set (match_dup 3) (match_dup 1))]
7953 "
7954 {
7955 int endian = (WORDS_BIG_ENDIAN == 0);
7956 HOST_WIDE_INT value = INTVAL (operands[1]);
7958 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7959 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7960 #if HOST_BITS_PER_WIDE_INT == 32
7961 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7962 #else
7963 operands[4] = GEN_INT (value >> 32);
7964 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7965 #endif
7966 }")
7968 (define_split
7969 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7970 (match_operand:DF 1 "const_double_operand" ""))]
7971 "! TARGET_POWERPC64 && reload_completed
7972 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7973 || (GET_CODE (operands[0]) == SUBREG
7974 && GET_CODE (SUBREG_REG (operands[0])) == REG
7975 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7976 [(set (match_dup 2) (match_dup 4))
7977 (set (match_dup 3) (match_dup 5))]
7978 "
7979 {
7980 int endian = (WORDS_BIG_ENDIAN == 0);
7981 long l[2];
7982 REAL_VALUE_TYPE rv;
7984 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7985 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7987 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7988 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7989 operands[4] = gen_int_mode (l[endian], SImode);
7990 operands[5] = gen_int_mode (l[1 - endian], SImode);
7991 }")
7993 (define_split
7994 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7995 (match_operand:DF 1 "easy_fp_constant" ""))]
7996 "TARGET_POWERPC64 && reload_completed
7997 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7998 || (GET_CODE (operands[0]) == SUBREG
7999 && GET_CODE (SUBREG_REG (operands[0])) == REG
8000 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8001 [(set (match_dup 2) (match_dup 3))]
8002 "
8003 {
8004 int endian = (WORDS_BIG_ENDIAN == 0);
8005 long l[2];
8006 REAL_VALUE_TYPE rv;
8007 #if HOST_BITS_PER_WIDE_INT >= 64
8008 HOST_WIDE_INT val;
8009 #endif
8011 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8012 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8014 operands[2] = gen_lowpart (DImode, operands[0]);
8015 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8016 #if HOST_BITS_PER_WIDE_INT >= 64
8017 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8018 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8020 operands[3] = gen_int_mode (val, DImode);
8021 #else
8022 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8023 #endif
8024 }")
8026 ;; Don't have reload use general registers to load a constant. First,
8027 ;; it might not work if the output operand is the equivalent of
8028 ;; a non-offsettable memref, but also it is less efficient than loading
8029 ;; the constant into an FP register, since it will probably be used there.
8030 ;; The "??" is a kludge until we can figure out a more reasonable way
8031 ;; of handling these non-offsettable values.
8032 (define_insn "*movdf_hardfloat32"
8033 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8034 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8035 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8036 && (gpc_reg_operand (operands[0], DFmode)
8037 || gpc_reg_operand (operands[1], DFmode))"
8038 "*
8039 {
8040 switch (which_alternative)
8041 {
8042 default:
8043 abort ();
8044 case 0:
8045 /* We normally copy the low-numbered register first. However, if
8046 the first register operand 0 is the same as the second register
8047 of operand 1, we must copy in the opposite order. */
8048 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8049 return \"mr %L0,%L1\;mr %0,%1\";
8050 else
8051 return \"mr %0,%1\;mr %L0,%L1\";
8052 case 1:
8053 if (offsettable_memref_p (operands[1])
8054 || (GET_CODE (operands[1]) == MEM
8055 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8056 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8057 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8058 {
8059 /* If the low-address word is used in the address, we must load
8060 it last. Otherwise, load it first. Note that we cannot have
8061 auto-increment in that case since the address register is
8062 known to be dead. */
8063 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8064 operands[1], 0))
8065 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8066 else
8067 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8068 }
8069 else
8070 {
8071 rtx addreg;
8073 addreg = find_addr_reg (XEXP (operands[1], 0));
8074 if (refers_to_regno_p (REGNO (operands[0]),
8075 REGNO (operands[0]) + 1,
8076 operands[1], 0))
8077 {
8078 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8079 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8080 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8081 return \"{lx|lwzx} %0,%1\";
8082 }
8083 else
8084 {
8085 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8086 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8087 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8088 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8089 return \"\";
8090 }
8091 }
8092 case 2:
8093 if (offsettable_memref_p (operands[0])
8094 || (GET_CODE (operands[0]) == MEM
8095 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8096 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8097 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8098 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8099 else
8100 {
8101 rtx addreg;
8103 addreg = find_addr_reg (XEXP (operands[0], 0));
8104 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8105 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8106 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8107 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8108 return \"\";
8109 }
8110 case 3:
8111 return \"fmr %0,%1\";
8112 case 4:
8113 return \"lfd%U1%X1 %0,%1\";
8114 case 5:
8115 return \"stfd%U0%X0 %1,%0\";
8116 case 6:
8117 case 7:
8118 case 8:
8119 return \"#\";
8120 }
8121 }"
8122 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8123 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8125 (define_insn "*movdf_softfloat32"
8126 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8127 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8128 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8129 && (gpc_reg_operand (operands[0], DFmode)
8130 || gpc_reg_operand (operands[1], DFmode))"
8131 "*
8132 {
8133 switch (which_alternative)
8134 {
8135 default:
8136 abort ();
8137 case 0:
8138 /* We normally copy the low-numbered register first. However, if
8139 the first register operand 0 is the same as the second register of
8140 operand 1, we must copy in the opposite order. */
8141 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8142 return \"mr %L0,%L1\;mr %0,%1\";
8143 else
8144 return \"mr %0,%1\;mr %L0,%L1\";
8145 case 1:
8146 /* If the low-address word is used in the address, we must load
8147 it last. Otherwise, load it first. Note that we cannot have
8148 auto-increment in that case since the address register is
8149 known to be dead. */
8150 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8151 operands[1], 0))
8152 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8153 else
8154 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8155 case 2:
8156 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8157 case 3:
8158 case 4:
8159 case 5:
8160 return \"#\";
8161 }
8162 }"
8163 [(set_attr "type" "*,load,store,*,*,*")
8164 (set_attr "length" "8,8,8,8,12,16")])
8166 ; ld/std require word-aligned displacements -> 'Y' constraint.
8167 ; List Y->r and r->Y before r->r for reload.
8168 (define_insn "*movdf_hardfloat64"
8169 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8170 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8171 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8172 && (gpc_reg_operand (operands[0], DFmode)
8173 || gpc_reg_operand (operands[1], DFmode))"
8174 "@
8175 std%U0%X0 %1,%0
8176 ld%U1%X1 %0,%1
8177 mr %0,%1
8178 fmr %0,%1
8179 lfd%U1%X1 %0,%1
8180 stfd%U0%X0 %1,%0
8181 mt%0 %1
8182 mf%1 %0
8183 {cror 0,0,0|nop}
8184 #
8185 #
8186 #"
8187 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8188 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8190 (define_insn "*movdf_softfloat64"
8191 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8192 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8193 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8194 && (gpc_reg_operand (operands[0], DFmode)
8195 || gpc_reg_operand (operands[1], DFmode))"
8196 "@
8197 ld%U1%X1 %0,%1
8198 std%U0%X0 %1,%0
8199 mr %0,%1
8200 mt%0 %1
8201 mf%1 %0
8202 #
8203 #
8204 #
8205 {cror 0,0,0|nop}"
8206 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8207 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8208 \f
8209 (define_expand "movtf"
8210 [(set (match_operand:TF 0 "general_operand" "")
8211 (match_operand:TF 1 "any_operand" ""))]
8212 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8213 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8214 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8216 ; It's important to list the o->f and f->o moves before f->f because
8217 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8218 ; which doesn't make progress.
8219 (define_insn_and_split "*movtf_internal"
8220 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8221 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
8222 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8223 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8224 && (gpc_reg_operand (operands[0], TFmode)
8225 || gpc_reg_operand (operands[1], TFmode))"
8226 "#"
8227 "&& reload_completed"
8228 [(pc)]
8229 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8230 [(set_attr "length" "8,8,8,20,20")])
8232 (define_expand "extenddftf2"
8233 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8234 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8235 (use (match_dup 2))])]
8236 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8237 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8238 {
8239 operands[2] = CONST0_RTX (DFmode);
8240 })
8242 (define_insn_and_split "*extenddftf2_internal"
8243 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8244 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8245 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8246 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8247 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8248 "#"
8249 "&& reload_completed"
8250 [(pc)]
8251 {
8252 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8253 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8254 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8255 operands[1]);
8256 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8257 operands[2]);
8258 DONE;
8259 })
8261 (define_expand "extendsftf2"
8262 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8263 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8264 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8265 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8266 {
8267 rtx tmp = gen_reg_rtx (DFmode);
8268 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8269 emit_insn (gen_extenddftf2 (operands[0], tmp));
8270 DONE;
8271 })
8273 (define_insn "trunctfdf2"
8274 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8275 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8276 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8277 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8278 "fadd %0,%1,%L1"
8279 [(set_attr "type" "fp")
8280 (set_attr "length" "4")])
8282 (define_insn_and_split "trunctfsf2"
8283 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8284 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8285 (clobber (match_scratch:DF 2 "=f"))]
8286 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8287 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8288 "#"
8289 "&& reload_completed"
8290 [(set (match_dup 2)
8291 (float_truncate:DF (match_dup 1)))
8292 (set (match_dup 0)
8293 (float_truncate:SF (match_dup 2)))]
8294 "")
8296 (define_expand "floatsitf2"
8297 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8298 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8299 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8300 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8301 {
8302 rtx tmp = gen_reg_rtx (DFmode);
8303 expand_float (tmp, operands[1], false);
8304 emit_insn (gen_extenddftf2 (operands[0], tmp));
8305 DONE;
8306 })
8308 ; fadd, but rounding towards zero.
8309 ; This is probably not the optimal code sequence.
8310 (define_insn "fix_trunc_helper"
8311 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8312 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8313 UNSPEC_FIX_TRUNC_TF))
8314 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8315 "TARGET_HARD_FLOAT && TARGET_FPRS"
8316 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8317 [(set_attr "type" "fp")
8318 (set_attr "length" "20")])
8320 (define_expand "fix_trunctfsi2"
8321 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8322 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8323 (clobber (match_dup 2))
8324 (clobber (match_dup 3))
8325 (clobber (match_dup 4))
8326 (clobber (match_dup 5))])]
8327 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8328 && (TARGET_POWER2 || TARGET_POWERPC)
8329 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8330 {
8331 operands[2] = gen_reg_rtx (DFmode);
8332 operands[3] = gen_reg_rtx (DFmode);
8333 operands[4] = gen_reg_rtx (DImode);
8334 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8335 })
8337 (define_insn_and_split "*fix_trunctfsi2_internal"
8338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8339 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8340 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8341 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8342 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8343 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8344 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8345 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8346 "#"
8347 "&& reload_completed"
8348 [(pc)]
8349 {
8350 rtx lowword;
8351 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8353 if (GET_CODE (operands[5]) != MEM)
8354 abort();
8355 lowword = XEXP (operands[5], 0);
8356 if (WORDS_BIG_ENDIAN)
8357 lowword = plus_constant (lowword, 4);
8359 emit_insn (gen_fctiwz (operands[4], operands[2]));
8360 emit_move_insn (operands[5], operands[4]);
8361 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8362 DONE;
8363 })
8365 (define_insn "negtf2"
8366 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8367 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8368 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8369 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8370 "*
8371 {
8372 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8373 return \"fneg %L0,%L1\;fneg %0,%1\";
8374 else
8375 return \"fneg %0,%1\;fneg %L0,%L1\";
8376 }"
8377 [(set_attr "type" "fp")
8378 (set_attr "length" "8")])
8380 (define_expand "abstf2"
8381 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8382 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8383 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8384 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8385 "
8386 {
8387 rtx label = gen_label_rtx ();
8388 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8389 emit_label (label);
8390 DONE;
8391 }")
8393 (define_expand "abstf2_internal"
8394 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8395 (match_operand:TF 1 "gpc_reg_operand" "f"))
8396 (set (match_dup 3) (match_dup 5))
8397 (set (match_dup 5) (abs:DF (match_dup 5)))
8398 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8399 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8400 (label_ref (match_operand 2 "" ""))
8401 (pc)))
8402 (set (match_dup 6) (neg:DF (match_dup 6)))]
8403 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8404 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8405 "
8406 {
8407 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8408 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8409 operands[3] = gen_reg_rtx (DFmode);
8410 operands[4] = gen_reg_rtx (CCFPmode);
8411 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8412 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8413 }")
8414 \f
8415 ;; Next come the multi-word integer load and store and the load and store
8416 ;; multiple insns.
8417 (define_expand "movdi"
8418 [(set (match_operand:DI 0 "general_operand" "")
8419 (match_operand:DI 1 "any_operand" ""))]
8420 ""
8421 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8423 (define_insn "*movdi_internal32"
8424 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8425 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8426 "! TARGET_POWERPC64
8427 && (gpc_reg_operand (operands[0], DImode)
8428 || gpc_reg_operand (operands[1], DImode))"
8429 "*
8430 {
8431 switch (which_alternative)
8432 {
8433 default:
8434 abort ();
8435 case 0:
8436 case 1:
8437 case 2:
8438 return \"#\";
8439 case 3:
8440 return \"fmr %0,%1\";
8441 case 4:
8442 return \"lfd%U1%X1 %0,%1\";
8443 case 5:
8444 return \"stfd%U0%X0 %1,%0\";
8445 case 6:
8446 case 7:
8447 case 8:
8448 case 9:
8449 case 10:
8450 return \"#\";
8451 }
8452 }"
8453 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
8455 (define_split
8456 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8457 (match_operand:DI 1 "const_int_operand" ""))]
8458 "! TARGET_POWERPC64 && reload_completed"
8459 [(set (match_dup 2) (match_dup 4))
8460 (set (match_dup 3) (match_dup 1))]
8461 "
8462 {
8463 HOST_WIDE_INT value = INTVAL (operands[1]);
8464 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8465 DImode);
8466 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8467 DImode);
8468 #if HOST_BITS_PER_WIDE_INT == 32
8469 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8470 #else
8471 operands[4] = GEN_INT (value >> 32);
8472 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8473 #endif
8474 }")
8476 (define_split
8477 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8478 (match_operand:DI 1 "input_operand" ""))]
8479 "reload_completed && !TARGET_POWERPC64
8480 && gpr_or_gpr_p (operands[0], operands[1])"
8481 [(pc)]
8482 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8484 (define_split
8485 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8486 (match_operand:TI 1 "const_double_operand" ""))]
8487 "TARGET_POWERPC64"
8488 [(set (match_dup 2) (match_dup 4))
8489 (set (match_dup 3) (match_dup 5))]
8490 "
8491 {
8492 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8493 TImode);
8494 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8495 TImode);
8496 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8497 {
8498 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8499 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8500 }
8501 else if (GET_CODE (operands[1]) == CONST_INT)
8502 {
8503 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8504 operands[5] = operands[1];
8505 }
8506 else
8507 FAIL;
8508 }")
8510 (define_insn "*movdi_internal64"
8511 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
8512 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8513 "TARGET_POWERPC64
8514 && (gpc_reg_operand (operands[0], DImode)
8515 || gpc_reg_operand (operands[1], DImode))"
8516 "@
8517 mr %0,%1
8518 ld%U1%X1 %0,%1
8519 std%U0%X0 %1,%0
8520 li %0,%1
8521 lis %0,%v1
8522 #
8523 {cal|la} %0,%a1
8524 fmr %0,%1
8525 lfd%U1%X1 %0,%1
8526 stfd%U0%X0 %1,%0
8527 mf%1 %0
8528 mt%0 %1
8529 {cror 0,0,0|nop}"
8530 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8531 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8533 ;; immediate value valid for a single instruction hiding in a const_double
8534 (define_insn ""
8535 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8536 (match_operand:DI 1 "const_double_operand" "F"))]
8537 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8538 && GET_CODE (operands[1]) == CONST_DOUBLE
8539 && num_insns_constant (operands[1], DImode) == 1"
8540 "*
8541 {
8542 return ((unsigned HOST_WIDE_INT)
8543 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8544 ? \"li %0,%1\" : \"lis %0,%v1\";
8545 }")
8547 ;; Generate all one-bits and clear left or right.
8548 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8549 (define_split
8550 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8551 (match_operand:DI 1 "mask64_operand" ""))]
8552 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8553 [(set (match_dup 0) (const_int -1))
8554 (set (match_dup 0)
8555 (and:DI (rotate:DI (match_dup 0)
8556 (const_int 0))
8557 (match_dup 1)))]
8558 "")
8560 ;; Split a load of a large constant into the appropriate five-instruction
8561 ;; sequence. Handle anything in a constant number of insns.
8562 ;; When non-easy constants can go in the TOC, this should use
8563 ;; easy_fp_constant predicate.
8564 (define_split
8565 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8566 (match_operand:DI 1 "const_int_operand" ""))]
8567 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8568 [(set (match_dup 0) (match_dup 2))
8569 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8570 "
8571 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8573 if (tem == operands[0])
8574 DONE;
8575 else
8576 FAIL;
8577 }")
8579 (define_split
8580 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8581 (match_operand:DI 1 "const_double_operand" ""))]
8582 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8583 [(set (match_dup 0) (match_dup 2))
8584 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8585 "
8586 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8588 if (tem == operands[0])
8589 DONE;
8590 else
8591 FAIL;
8592 }")
8594 (define_insn "*movdi_internal2"
8595 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8596 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8597 (const_int 0)))
8598 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8599 "TARGET_64BIT"
8600 "@
8601 cmpdi %2,%0,0
8602 mr. %0,%1
8603 #"
8604 [(set_attr "type" "cmp,compare,cmp")
8605 (set_attr "length" "4,4,8")])
8607 (define_split
8608 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8609 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8610 (const_int 0)))
8611 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8612 "TARGET_POWERPC64 && reload_completed"
8613 [(set (match_dup 0) (match_dup 1))
8614 (set (match_dup 2)
8615 (compare:CC (match_dup 0)
8616 (const_int 0)))]
8617 "")
8618 \f
8619 ;; TImode is similar, except that we usually want to compute the address into
8620 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8621 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8622 (define_expand "movti"
8623 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8624 (match_operand:TI 1 "general_operand" ""))
8625 (clobber (scratch:SI))])]
8626 ""
8627 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8629 ;; We say that MQ is clobbered in the last alternative because the first
8630 ;; alternative would never get used otherwise since it would need a reload
8631 ;; while the 2nd alternative would not. We put memory cases first so they
8632 ;; are preferred. Otherwise, we'd try to reload the output instead of
8633 ;; giving the SCRATCH mq.
8635 (define_insn "*movti_power"
8636 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8637 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8638 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8639 "TARGET_POWER && ! TARGET_POWERPC64
8640 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8641 "*
8642 {
8643 switch (which_alternative)
8644 {
8645 default:
8646 abort ();
8648 case 0:
8649 if (TARGET_STRING)
8650 return \"{stsi|stswi} %1,%P0,16\";
8651 case 1:
8652 case 2:
8653 return \"#\";
8654 case 3:
8655 /* If the address is not used in the output, we can use lsi. Otherwise,
8656 fall through to generating four loads. */
8657 if (TARGET_STRING
8658 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8659 return \"{lsi|lswi} %0,%P1,16\";
8660 /* ... fall through ... */
8661 case 4:
8662 return \"#\";
8663 }
8664 }"
8665 [(set_attr "type" "store,store,*,load,load")])
8667 (define_insn "*movti_string"
8668 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8669 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8670 "! TARGET_POWER && ! TARGET_POWERPC64
8671 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8672 "*
8673 {
8674 switch (which_alternative)
8675 {
8676 default:
8677 abort ();
8678 case 0:
8679 if (TARGET_STRING)
8680 return \"{stsi|stswi} %1,%P0,16\";
8681 case 1:
8682 case 2:
8683 return \"#\";
8684 case 3:
8685 /* If the address is not used in the output, we can use lsi. Otherwise,
8686 fall through to generating four loads. */
8687 if (TARGET_STRING
8688 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8689 return \"{lsi|lswi} %0,%P1,16\";
8690 /* ... fall through ... */
8691 case 4:
8692 return \"#\";
8693 }
8694 }"
8695 [(set_attr "type" "store,store,*,load,load")])
8697 (define_insn "*movti_ppc64"
8698 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8699 (match_operand:TI 1 "input_operand" "r,r,o"))]
8700 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8701 || gpc_reg_operand (operands[1], TImode))"
8702 "@
8703 #
8704 #
8705 #"
8706 [(set_attr "type" "*,load,store")])
8708 (define_split
8709 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8710 (match_operand:TI 1 "input_operand" ""))]
8711 "reload_completed
8712 && gpr_or_gpr_p (operands[0], operands[1])"
8713 [(pc)]
8714 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8715 \f
8716 (define_expand "load_multiple"
8717 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8718 (match_operand:SI 1 "" ""))
8719 (use (match_operand:SI 2 "" ""))])]
8720 "TARGET_STRING && !TARGET_POWERPC64"
8721 "
8722 {
8723 int regno;
8724 int count;
8725 rtx op1;
8726 int i;
8728 /* Support only loading a constant number of fixed-point registers from
8729 memory and only bother with this if more than two; the machine
8730 doesn't support more than eight. */
8731 if (GET_CODE (operands[2]) != CONST_INT
8732 || INTVAL (operands[2]) <= 2
8733 || INTVAL (operands[2]) > 8
8734 || GET_CODE (operands[1]) != MEM
8735 || GET_CODE (operands[0]) != REG
8736 || REGNO (operands[0]) >= 32)
8737 FAIL;
8739 count = INTVAL (operands[2]);
8740 regno = REGNO (operands[0]);
8742 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8743 op1 = replace_equiv_address (operands[1],
8744 force_reg (SImode, XEXP (operands[1], 0)));
8746 for (i = 0; i < count; i++)
8747 XVECEXP (operands[3], 0, i)
8748 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8749 adjust_address_nv (op1, SImode, i * 4));
8750 }")
8752 (define_insn "*ldmsi8"
8753 [(match_parallel 0 "load_multiple_operation"
8754 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8755 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8756 (set (match_operand:SI 3 "gpc_reg_operand" "")
8757 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8758 (set (match_operand:SI 4 "gpc_reg_operand" "")
8759 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8760 (set (match_operand:SI 5 "gpc_reg_operand" "")
8761 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8762 (set (match_operand:SI 6 "gpc_reg_operand" "")
8763 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8764 (set (match_operand:SI 7 "gpc_reg_operand" "")
8765 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8766 (set (match_operand:SI 8 "gpc_reg_operand" "")
8767 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8768 (set (match_operand:SI 9 "gpc_reg_operand" "")
8769 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8770 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8771 "*
8772 { return rs6000_output_load_multiple (operands); }"
8773 [(set_attr "type" "load")
8774 (set_attr "length" "32")])
8776 (define_insn "*ldmsi7"
8777 [(match_parallel 0 "load_multiple_operation"
8778 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8779 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8780 (set (match_operand:SI 3 "gpc_reg_operand" "")
8781 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8782 (set (match_operand:SI 4 "gpc_reg_operand" "")
8783 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8784 (set (match_operand:SI 5 "gpc_reg_operand" "")
8785 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8786 (set (match_operand:SI 6 "gpc_reg_operand" "")
8787 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8788 (set (match_operand:SI 7 "gpc_reg_operand" "")
8789 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8790 (set (match_operand:SI 8 "gpc_reg_operand" "")
8791 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8792 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8793 "*
8794 { return rs6000_output_load_multiple (operands); }"
8795 [(set_attr "type" "load")
8796 (set_attr "length" "32")])
8798 (define_insn "*ldmsi6"
8799 [(match_parallel 0 "load_multiple_operation"
8800 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8801 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8802 (set (match_operand:SI 3 "gpc_reg_operand" "")
8803 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8804 (set (match_operand:SI 4 "gpc_reg_operand" "")
8805 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8806 (set (match_operand:SI 5 "gpc_reg_operand" "")
8807 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8808 (set (match_operand:SI 6 "gpc_reg_operand" "")
8809 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8810 (set (match_operand:SI 7 "gpc_reg_operand" "")
8811 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8812 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8813 "*
8814 { return rs6000_output_load_multiple (operands); }"
8815 [(set_attr "type" "load")
8816 (set_attr "length" "32")])
8818 (define_insn "*ldmsi5"
8819 [(match_parallel 0 "load_multiple_operation"
8820 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8821 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8822 (set (match_operand:SI 3 "gpc_reg_operand" "")
8823 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8824 (set (match_operand:SI 4 "gpc_reg_operand" "")
8825 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8826 (set (match_operand:SI 5 "gpc_reg_operand" "")
8827 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8828 (set (match_operand:SI 6 "gpc_reg_operand" "")
8829 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8830 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8831 "*
8832 { return rs6000_output_load_multiple (operands); }"
8833 [(set_attr "type" "load")
8834 (set_attr "length" "32")])
8836 (define_insn "*ldmsi4"
8837 [(match_parallel 0 "load_multiple_operation"
8838 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8839 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8840 (set (match_operand:SI 3 "gpc_reg_operand" "")
8841 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8842 (set (match_operand:SI 4 "gpc_reg_operand" "")
8843 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8844 (set (match_operand:SI 5 "gpc_reg_operand" "")
8845 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8846 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8847 "*
8848 { return rs6000_output_load_multiple (operands); }"
8849 [(set_attr "type" "load")
8850 (set_attr "length" "32")])
8852 (define_insn "*ldmsi3"
8853 [(match_parallel 0 "load_multiple_operation"
8854 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8855 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8856 (set (match_operand:SI 3 "gpc_reg_operand" "")
8857 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8858 (set (match_operand:SI 4 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8860 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8861 "*
8862 { return rs6000_output_load_multiple (operands); }"
8863 [(set_attr "type" "load")
8864 (set_attr "length" "32")])
8866 (define_expand "store_multiple"
8867 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8868 (match_operand:SI 1 "" ""))
8869 (clobber (scratch:SI))
8870 (use (match_operand:SI 2 "" ""))])]
8871 "TARGET_STRING && !TARGET_POWERPC64"
8872 "
8873 {
8874 int regno;
8875 int count;
8876 rtx to;
8877 rtx op0;
8878 int i;
8880 /* Support only storing a constant number of fixed-point registers to
8881 memory and only bother with this if more than two; the machine
8882 doesn't support more than eight. */
8883 if (GET_CODE (operands[2]) != CONST_INT
8884 || INTVAL (operands[2]) <= 2
8885 || INTVAL (operands[2]) > 8
8886 || GET_CODE (operands[0]) != MEM
8887 || GET_CODE (operands[1]) != REG
8888 || REGNO (operands[1]) >= 32)
8889 FAIL;
8891 count = INTVAL (operands[2]);
8892 regno = REGNO (operands[1]);
8894 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8895 to = force_reg (SImode, XEXP (operands[0], 0));
8896 op0 = replace_equiv_address (operands[0], to);
8898 XVECEXP (operands[3], 0, 0)
8899 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8900 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8901 gen_rtx_SCRATCH (SImode));
8903 for (i = 1; i < count; i++)
8904 XVECEXP (operands[3], 0, i + 1)
8905 = gen_rtx_SET (VOIDmode,
8906 adjust_address_nv (op0, SImode, i * 4),
8907 gen_rtx_REG (SImode, regno + i));
8908 }")
8910 (define_insn "*store_multiple_power"
8911 [(match_parallel 0 "store_multiple_operation"
8912 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8913 (match_operand:SI 2 "gpc_reg_operand" "r"))
8914 (clobber (match_scratch:SI 3 "=q"))])]
8915 "TARGET_STRING && TARGET_POWER"
8916 "{stsi|stswi} %2,%P1,%O0"
8917 [(set_attr "type" "store")])
8919 (define_insn "*stmsi8"
8920 [(match_parallel 0 "store_multiple_operation"
8921 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8922 (match_operand:SI 2 "gpc_reg_operand" "r"))
8923 (clobber (match_scratch:SI 3 "X"))
8924 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8925 (match_operand:SI 4 "gpc_reg_operand" "r"))
8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8927 (match_operand:SI 5 "gpc_reg_operand" "r"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8929 (match_operand:SI 6 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8931 (match_operand:SI 7 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8933 (match_operand:SI 8 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8935 (match_operand:SI 9 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8937 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8938 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8939 "{stsi|stswi} %2,%1,%O0"
8940 [(set_attr "type" "store")])
8942 (define_insn "*stmsi7"
8943 [(match_parallel 0 "store_multiple_operation"
8944 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8945 (match_operand:SI 2 "gpc_reg_operand" "r"))
8946 (clobber (match_scratch:SI 3 "X"))
8947 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8948 (match_operand:SI 4 "gpc_reg_operand" "r"))
8949 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8950 (match_operand:SI 5 "gpc_reg_operand" "r"))
8951 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8952 (match_operand:SI 6 "gpc_reg_operand" "r"))
8953 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8954 (match_operand:SI 7 "gpc_reg_operand" "r"))
8955 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8956 (match_operand:SI 8 "gpc_reg_operand" "r"))
8957 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8958 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8959 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8960 "{stsi|stswi} %2,%1,%O0"
8961 [(set_attr "type" "store")])
8963 (define_insn "*stmsi6"
8964 [(match_parallel 0 "store_multiple_operation"
8965 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8966 (match_operand:SI 2 "gpc_reg_operand" "r"))
8967 (clobber (match_scratch:SI 3 "X"))
8968 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8969 (match_operand:SI 4 "gpc_reg_operand" "r"))
8970 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8971 (match_operand:SI 5 "gpc_reg_operand" "r"))
8972 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8973 (match_operand:SI 6 "gpc_reg_operand" "r"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8975 (match_operand:SI 7 "gpc_reg_operand" "r"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8977 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8978 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8979 "{stsi|stswi} %2,%1,%O0"
8980 [(set_attr "type" "store")])
8982 (define_insn "*stmsi5"
8983 [(match_parallel 0 "store_multiple_operation"
8984 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8985 (match_operand:SI 2 "gpc_reg_operand" "r"))
8986 (clobber (match_scratch:SI 3 "X"))
8987 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8988 (match_operand:SI 4 "gpc_reg_operand" "r"))
8989 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8990 (match_operand:SI 5 "gpc_reg_operand" "r"))
8991 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8992 (match_operand:SI 6 "gpc_reg_operand" "r"))
8993 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8994 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8995 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8996 "{stsi|stswi} %2,%1,%O0"
8997 [(set_attr "type" "store")])
8999 (define_insn "*stmsi4"
9000 [(match_parallel 0 "store_multiple_operation"
9001 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9002 (match_operand:SI 2 "gpc_reg_operand" "r"))
9003 (clobber (match_scratch:SI 3 "X"))
9004 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9005 (match_operand:SI 4 "gpc_reg_operand" "r"))
9006 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9007 (match_operand:SI 5 "gpc_reg_operand" "r"))
9008 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9009 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9010 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9011 "{stsi|stswi} %2,%1,%O0"
9012 [(set_attr "type" "store")])
9014 (define_insn "*stmsi3"
9015 [(match_parallel 0 "store_multiple_operation"
9016 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9017 (match_operand:SI 2 "gpc_reg_operand" "r"))
9018 (clobber (match_scratch:SI 3 "X"))
9019 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9020 (match_operand:SI 4 "gpc_reg_operand" "r"))
9021 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9022 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9023 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9024 "{stsi|stswi} %2,%1,%O0"
9025 [(set_attr "type" "store")])
9026 \f
9027 ;; String/block move insn.
9028 ;; Argument 0 is the destination
9029 ;; Argument 1 is the source
9030 ;; Argument 2 is the length
9031 ;; Argument 3 is the alignment
9033 (define_expand "movstrsi"
9034 [(parallel [(set (match_operand:BLK 0 "" "")
9035 (match_operand:BLK 1 "" ""))
9036 (use (match_operand:SI 2 "" ""))
9037 (use (match_operand:SI 3 "" ""))])]
9038 ""
9039 "
9040 {
9041 if (expand_block_move (operands))
9042 DONE;
9043 else
9044 FAIL;
9045 }")
9047 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9048 ;; register allocator doesn't have a clue about allocating 8 word registers.
9049 ;; rD/rS = r5 is preferred, efficient form.
9050 (define_expand "movstrsi_8reg"
9051 [(parallel [(set (match_operand 0 "" "")
9052 (match_operand 1 "" ""))
9053 (use (match_operand 2 "" ""))
9054 (use (match_operand 3 "" ""))
9055 (clobber (reg:SI 5))
9056 (clobber (reg:SI 6))
9057 (clobber (reg:SI 7))
9058 (clobber (reg:SI 8))
9059 (clobber (reg:SI 9))
9060 (clobber (reg:SI 10))
9061 (clobber (reg:SI 11))
9062 (clobber (reg:SI 12))
9063 (clobber (match_scratch:SI 4 ""))])]
9064 "TARGET_STRING"
9065 "")
9067 (define_insn ""
9068 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9069 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9070 (use (match_operand:SI 2 "immediate_operand" "i"))
9071 (use (match_operand:SI 3 "immediate_operand" "i"))
9072 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9073 (clobber (reg:SI 6))
9074 (clobber (reg:SI 7))
9075 (clobber (reg:SI 8))
9076 (clobber (reg:SI 9))
9077 (clobber (reg:SI 10))
9078 (clobber (reg:SI 11))
9079 (clobber (reg:SI 12))
9080 (clobber (match_scratch:SI 5 "=q"))]
9081 "TARGET_STRING && TARGET_POWER
9082 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9083 || INTVAL (operands[2]) == 0)
9084 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9085 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9086 && REGNO (operands[4]) == 5"
9087 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9088 [(set_attr "type" "load")
9089 (set_attr "length" "8")])
9091 (define_insn ""
9092 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9093 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9094 (use (match_operand:SI 2 "immediate_operand" "i"))
9095 (use (match_operand:SI 3 "immediate_operand" "i"))
9096 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9097 (clobber (reg:SI 6))
9098 (clobber (reg:SI 7))
9099 (clobber (reg:SI 8))
9100 (clobber (reg:SI 9))
9101 (clobber (reg:SI 10))
9102 (clobber (reg:SI 11))
9103 (clobber (reg:SI 12))
9104 (clobber (match_scratch:SI 5 "X"))]
9105 "TARGET_STRING && ! TARGET_POWER
9106 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9107 || INTVAL (operands[2]) == 0)
9108 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9109 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9110 && REGNO (operands[4]) == 5"
9111 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9112 [(set_attr "type" "load")
9113 (set_attr "length" "8")])
9115 (define_insn ""
9116 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9117 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9118 (use (match_operand:SI 2 "immediate_operand" "i"))
9119 (use (match_operand:SI 3 "immediate_operand" "i"))
9120 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9121 (clobber (reg:SI 6))
9122 (clobber (reg:SI 7))
9123 (clobber (reg:SI 8))
9124 (clobber (reg:SI 9))
9125 (clobber (reg:SI 10))
9126 (clobber (reg:SI 11))
9127 (clobber (reg:SI 12))
9128 (clobber (match_scratch:SI 5 "X"))]
9129 "TARGET_STRING && TARGET_POWERPC64
9130 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9131 || INTVAL (operands[2]) == 0)
9132 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9133 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9134 && REGNO (operands[4]) == 5"
9135 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9136 [(set_attr "type" "load")
9137 (set_attr "length" "8")])
9139 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9140 ;; register allocator doesn't have a clue about allocating 6 word registers.
9141 ;; rD/rS = r5 is preferred, efficient form.
9142 (define_expand "movstrsi_6reg"
9143 [(parallel [(set (match_operand 0 "" "")
9144 (match_operand 1 "" ""))
9145 (use (match_operand 2 "" ""))
9146 (use (match_operand 3 "" ""))
9147 (clobber (reg:SI 5))
9148 (clobber (reg:SI 6))
9149 (clobber (reg:SI 7))
9150 (clobber (reg:SI 8))
9151 (clobber (reg:SI 9))
9152 (clobber (reg:SI 10))
9153 (clobber (match_scratch:SI 4 ""))])]
9154 "TARGET_STRING"
9155 "")
9157 (define_insn ""
9158 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9159 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9160 (use (match_operand:SI 2 "immediate_operand" "i"))
9161 (use (match_operand:SI 3 "immediate_operand" "i"))
9162 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9163 (clobber (reg:SI 6))
9164 (clobber (reg:SI 7))
9165 (clobber (reg:SI 8))
9166 (clobber (reg:SI 9))
9167 (clobber (reg:SI 10))
9168 (clobber (match_scratch:SI 5 "=q"))]
9169 "TARGET_STRING && TARGET_POWER
9170 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9171 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9172 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9173 && REGNO (operands[4]) == 5"
9174 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9175 [(set_attr "type" "load")
9176 (set_attr "length" "8")])
9178 (define_insn ""
9179 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9180 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9181 (use (match_operand:SI 2 "immediate_operand" "i"))
9182 (use (match_operand:SI 3 "immediate_operand" "i"))
9183 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9184 (clobber (reg:SI 6))
9185 (clobber (reg:SI 7))
9186 (clobber (reg:SI 8))
9187 (clobber (reg:SI 9))
9188 (clobber (reg:SI 10))
9189 (clobber (match_scratch:SI 5 "X"))]
9190 "TARGET_STRING && ! TARGET_POWER
9191 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9192 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9193 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9194 && REGNO (operands[4]) == 5"
9195 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9196 [(set_attr "type" "load")
9197 (set_attr "length" "8")])
9199 (define_insn ""
9200 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9201 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9202 (use (match_operand:SI 2 "immediate_operand" "i"))
9203 (use (match_operand:SI 3 "immediate_operand" "i"))
9204 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9205 (clobber (reg:SI 6))
9206 (clobber (reg:SI 7))
9207 (clobber (reg:SI 8))
9208 (clobber (reg:SI 9))
9209 (clobber (reg:SI 10))
9210 (clobber (match_scratch:SI 5 "X"))]
9211 "TARGET_STRING && TARGET_POWERPC64
9212 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9213 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9214 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9215 && REGNO (operands[4]) == 5"
9216 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9217 [(set_attr "type" "load")
9218 (set_attr "length" "8")])
9220 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9221 ;; problems with TImode.
9222 ;; rD/rS = r5 is preferred, efficient form.
9223 (define_expand "movstrsi_4reg"
9224 [(parallel [(set (match_operand 0 "" "")
9225 (match_operand 1 "" ""))
9226 (use (match_operand 2 "" ""))
9227 (use (match_operand 3 "" ""))
9228 (clobber (reg:SI 5))
9229 (clobber (reg:SI 6))
9230 (clobber (reg:SI 7))
9231 (clobber (reg:SI 8))
9232 (clobber (match_scratch:SI 4 ""))])]
9233 "TARGET_STRING"
9234 "")
9236 (define_insn ""
9237 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9238 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9239 (use (match_operand:SI 2 "immediate_operand" "i"))
9240 (use (match_operand:SI 3 "immediate_operand" "i"))
9241 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9242 (clobber (reg:SI 6))
9243 (clobber (reg:SI 7))
9244 (clobber (reg:SI 8))
9245 (clobber (match_scratch:SI 5 "=q"))]
9246 "TARGET_STRING && TARGET_POWER
9247 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9248 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9249 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9250 && REGNO (operands[4]) == 5"
9251 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9252 [(set_attr "type" "load")
9253 (set_attr "length" "8")])
9255 (define_insn ""
9256 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9257 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9258 (use (match_operand:SI 2 "immediate_operand" "i"))
9259 (use (match_operand:SI 3 "immediate_operand" "i"))
9260 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9261 (clobber (reg:SI 6))
9262 (clobber (reg:SI 7))
9263 (clobber (reg:SI 8))
9264 (clobber (match_scratch:SI 5 "X"))]
9265 "TARGET_STRING && ! TARGET_POWER
9266 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9267 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9268 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9269 && REGNO (operands[4]) == 5"
9270 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9271 [(set_attr "type" "load")
9272 (set_attr "length" "8")])
9274 (define_insn ""
9275 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9276 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9277 (use (match_operand:SI 2 "immediate_operand" "i"))
9278 (use (match_operand:SI 3 "immediate_operand" "i"))
9279 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9280 (clobber (reg:SI 6))
9281 (clobber (reg:SI 7))
9282 (clobber (reg:SI 8))
9283 (clobber (match_scratch:SI 5 "X"))]
9284 "TARGET_STRING && TARGET_POWERPC64
9285 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9286 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9287 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9288 && REGNO (operands[4]) == 5"
9289 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9290 [(set_attr "type" "load")
9291 (set_attr "length" "8")])
9293 ;; Move up to 8 bytes at a time.
9294 (define_expand "movstrsi_2reg"
9295 [(parallel [(set (match_operand 0 "" "")
9296 (match_operand 1 "" ""))
9297 (use (match_operand 2 "" ""))
9298 (use (match_operand 3 "" ""))
9299 (clobber (match_scratch:DI 4 ""))
9300 (clobber (match_scratch:SI 5 ""))])]
9301 "TARGET_STRING && ! TARGET_POWERPC64"
9302 "")
9304 (define_insn ""
9305 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9306 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9307 (use (match_operand:SI 2 "immediate_operand" "i"))
9308 (use (match_operand:SI 3 "immediate_operand" "i"))
9309 (clobber (match_scratch:DI 4 "=&r"))
9310 (clobber (match_scratch:SI 5 "=q"))]
9311 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9312 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9313 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9314 [(set_attr "type" "load")
9315 (set_attr "length" "8")])
9317 (define_insn ""
9318 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9319 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9320 (use (match_operand:SI 2 "immediate_operand" "i"))
9321 (use (match_operand:SI 3 "immediate_operand" "i"))
9322 (clobber (match_scratch:DI 4 "=&r"))
9323 (clobber (match_scratch:SI 5 "X"))]
9324 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9325 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9326 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9327 [(set_attr "type" "load")
9328 (set_attr "length" "8")])
9330 ;; Move up to 4 bytes at a time.
9331 (define_expand "movstrsi_1reg"
9332 [(parallel [(set (match_operand 0 "" "")
9333 (match_operand 1 "" ""))
9334 (use (match_operand 2 "" ""))
9335 (use (match_operand 3 "" ""))
9336 (clobber (match_scratch:SI 4 ""))
9337 (clobber (match_scratch:SI 5 ""))])]
9338 "TARGET_STRING"
9339 "")
9341 (define_insn ""
9342 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9343 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9344 (use (match_operand:SI 2 "immediate_operand" "i"))
9345 (use (match_operand:SI 3 "immediate_operand" "i"))
9346 (clobber (match_scratch:SI 4 "=&r"))
9347 (clobber (match_scratch:SI 5 "=q"))]
9348 "TARGET_STRING && TARGET_POWER
9349 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9350 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9351 [(set_attr "type" "load")
9352 (set_attr "length" "8")])
9354 (define_insn ""
9355 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9356 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9357 (use (match_operand:SI 2 "immediate_operand" "i"))
9358 (use (match_operand:SI 3 "immediate_operand" "i"))
9359 (clobber (match_scratch:SI 4 "=&r"))
9360 (clobber (match_scratch:SI 5 "X"))]
9361 "TARGET_STRING && ! TARGET_POWER
9362 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9363 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9364 [(set_attr "type" "load")
9365 (set_attr "length" "8")])
9367 (define_insn ""
9368 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9369 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9370 (use (match_operand:SI 2 "immediate_operand" "i"))
9371 (use (match_operand:SI 3 "immediate_operand" "i"))
9372 (clobber (match_scratch:SI 4 "=&r"))
9373 (clobber (match_scratch:SI 5 "X"))]
9374 "TARGET_STRING && TARGET_POWERPC64
9375 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9376 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9377 [(set_attr "type" "load")
9378 (set_attr "length" "8")])
9380 \f
9381 ;; Define insns that do load or store with update. Some of these we can
9382 ;; get by using pre-decrement or pre-increment, but the hardware can also
9383 ;; do cases where the increment is not the size of the object.
9384 ;;
9385 ;; In all these cases, we use operands 0 and 1 for the register being
9386 ;; incremented because those are the operands that local-alloc will
9387 ;; tie and these are the pair most likely to be tieable (and the ones
9388 ;; that will benefit the most).
9390 (define_insn "*movdi_update1"
9391 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9392 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9393 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9394 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9395 (plus:DI (match_dup 1) (match_dup 2)))]
9396 "TARGET_POWERPC64 && TARGET_UPDATE"
9397 "@
9398 ldux %3,%0,%2
9399 ldu %3,%2(%0)"
9400 [(set_attr "type" "load_ux,load_u")])
9402 (define_insn "movdi_update"
9403 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9404 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9405 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9406 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9407 (plus:DI (match_dup 1) (match_dup 2)))]
9408 "TARGET_POWERPC64 && TARGET_UPDATE"
9409 "@
9410 stdux %3,%0,%2
9411 stdu %3,%2(%0)"
9412 [(set_attr "type" "store_ux,store_u")])
9414 (define_insn "*movsi_update1"
9415 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9416 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9417 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9418 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9419 (plus:SI (match_dup 1) (match_dup 2)))]
9420 "TARGET_UPDATE"
9421 "@
9422 {lux|lwzux} %3,%0,%2
9423 {lu|lwzu} %3,%2(%0)"
9424 [(set_attr "type" "load_ux,load_u")])
9426 (define_insn "*movsi_update2"
9427 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9428 (sign_extend:DI
9429 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9430 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9431 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9432 (plus:DI (match_dup 1) (match_dup 2)))]
9433 "TARGET_POWERPC64"
9434 "lwaux %3,%0,%2"
9435 [(set_attr "type" "load_ext_ux")])
9437 (define_insn "movsi_update"
9438 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9439 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9440 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9441 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9442 (plus:SI (match_dup 1) (match_dup 2)))]
9443 "TARGET_UPDATE"
9444 "@
9445 {stux|stwux} %3,%0,%2
9446 {stu|stwu} %3,%2(%0)"
9447 [(set_attr "type" "store_ux,store_u")])
9449 (define_insn "*movhi_update1"
9450 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9451 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9452 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9453 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9454 (plus:SI (match_dup 1) (match_dup 2)))]
9455 "TARGET_UPDATE"
9456 "@
9457 lhzux %3,%0,%2
9458 lhzu %3,%2(%0)"
9459 [(set_attr "type" "load_ux,load_u")])
9461 (define_insn "*movhi_update2"
9462 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9463 (zero_extend:SI
9464 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9465 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9466 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9467 (plus:SI (match_dup 1) (match_dup 2)))]
9468 "TARGET_UPDATE"
9469 "@
9470 lhzux %3,%0,%2
9471 lhzu %3,%2(%0)"
9472 [(set_attr "type" "load_ux,load_u")])
9474 (define_insn "*movhi_update3"
9475 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9476 (sign_extend:SI
9477 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9478 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9479 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9480 (plus:SI (match_dup 1) (match_dup 2)))]
9481 "TARGET_UPDATE"
9482 "@
9483 lhaux %3,%0,%2
9484 lhau %3,%2(%0)"
9485 [(set_attr "type" "load_ext_ux,load_ext_u")])
9487 (define_insn "*movhi_update4"
9488 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9489 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9490 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9491 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9492 (plus:SI (match_dup 1) (match_dup 2)))]
9493 "TARGET_UPDATE"
9494 "@
9495 sthux %3,%0,%2
9496 sthu %3,%2(%0)"
9497 [(set_attr "type" "store_ux,store_u")])
9499 (define_insn "*movqi_update1"
9500 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9501 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9502 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9503 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9504 (plus:SI (match_dup 1) (match_dup 2)))]
9505 "TARGET_UPDATE"
9506 "@
9507 lbzux %3,%0,%2
9508 lbzu %3,%2(%0)"
9509 [(set_attr "type" "load_ux,load_u")])
9511 (define_insn "*movqi_update2"
9512 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9513 (zero_extend:SI
9514 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9515 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9516 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9517 (plus:SI (match_dup 1) (match_dup 2)))]
9518 "TARGET_UPDATE"
9519 "@
9520 lbzux %3,%0,%2
9521 lbzu %3,%2(%0)"
9522 [(set_attr "type" "load_ux,load_u")])
9524 (define_insn "*movqi_update3"
9525 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9526 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9527 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9528 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9529 (plus:SI (match_dup 1) (match_dup 2)))]
9530 "TARGET_UPDATE"
9531 "@
9532 stbux %3,%0,%2
9533 stbu %3,%2(%0)"
9534 [(set_attr "type" "store_ux,store_u")])
9536 (define_insn "*movsf_update1"
9537 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9538 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9539 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9540 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9541 (plus:SI (match_dup 1) (match_dup 2)))]
9542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9543 "@
9544 lfsux %3,%0,%2
9545 lfsu %3,%2(%0)"
9546 [(set_attr "type" "fpload_ux,fpload_u")])
9548 (define_insn "*movsf_update2"
9549 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9550 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9551 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9552 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9553 (plus:SI (match_dup 1) (match_dup 2)))]
9554 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9555 "@
9556 stfsux %3,%0,%2
9557 stfsu %3,%2(%0)"
9558 [(set_attr "type" "fpstore_ux,fpstore_u")])
9560 (define_insn "*movsf_update3"
9561 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9562 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9563 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9564 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9565 (plus:SI (match_dup 1) (match_dup 2)))]
9566 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9567 "@
9568 {lux|lwzux} %3,%0,%2
9569 {lu|lwzu} %3,%2(%0)"
9570 [(set_attr "type" "load_ux,load_u")])
9572 (define_insn "*movsf_update4"
9573 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9574 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9575 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9576 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9577 (plus:SI (match_dup 1) (match_dup 2)))]
9578 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9579 "@
9580 {stux|stwux} %3,%0,%2
9581 {stu|stwu} %3,%2(%0)"
9582 [(set_attr "type" "store_ux,store_u")])
9584 (define_insn "*movdf_update1"
9585 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9586 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9587 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9588 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9589 (plus:SI (match_dup 1) (match_dup 2)))]
9590 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9591 "@
9592 lfdux %3,%0,%2
9593 lfdu %3,%2(%0)"
9594 [(set_attr "type" "fpload_ux,fpload_u")])
9596 (define_insn "*movdf_update2"
9597 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9598 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9599 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9600 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9601 (plus:SI (match_dup 1) (match_dup 2)))]
9602 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9603 "@
9604 stfdux %3,%0,%2
9605 stfdu %3,%2(%0)"
9606 [(set_attr "type" "fpstore_ux,fpstore_u")])
9608 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9610 (define_peephole
9611 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9612 (match_operand:DF 1 "memory_operand" ""))
9613 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9614 (match_operand:DF 3 "memory_operand" ""))]
9615 "TARGET_POWER2
9616 && TARGET_HARD_FLOAT && TARGET_FPRS
9617 && registers_ok_for_quad_peep (operands[0], operands[2])
9618 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9619 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9620 "lfq%U1%X1 %0,%1")
9622 (define_peephole
9623 [(set (match_operand:DF 0 "memory_operand" "")
9624 (match_operand:DF 1 "gpc_reg_operand" "f"))
9625 (set (match_operand:DF 2 "memory_operand" "")
9626 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9627 "TARGET_POWER2
9628 && TARGET_HARD_FLOAT && TARGET_FPRS
9629 && registers_ok_for_quad_peep (operands[1], operands[3])
9630 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9631 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9632 "stfq%U0%X0 %1,%0")
9633 \f
9634 ;; TLS support.
9636 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9637 (define_insn "tls_gd_32"
9638 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9639 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9640 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9641 UNSPEC_TLSGD))]
9642 "HAVE_AS_TLS && !TARGET_64BIT"
9643 "addi %0,%1,%2@got@tlsgd")
9645 (define_insn "tls_gd_64"
9646 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9647 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9648 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9649 UNSPEC_TLSGD))]
9650 "HAVE_AS_TLS && TARGET_64BIT"
9651 "addi %0,%1,%2@got@tlsgd")
9653 (define_insn "tls_ld_32"
9654 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9655 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9656 UNSPEC_TLSLD))]
9657 "HAVE_AS_TLS && !TARGET_64BIT"
9658 "addi %0,%1,%&@got@tlsld")
9660 (define_insn "tls_ld_64"
9661 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9662 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9663 UNSPEC_TLSLD))]
9664 "HAVE_AS_TLS && TARGET_64BIT"
9665 "addi %0,%1,%&@got@tlsld")
9667 (define_insn "tls_dtprel_32"
9668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9669 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9670 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9671 UNSPEC_TLSDTPREL))]
9672 "HAVE_AS_TLS && !TARGET_64BIT"
9673 "addi %0,%1,%2@dtprel")
9675 (define_insn "tls_dtprel_64"
9676 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9677 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9678 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9679 UNSPEC_TLSDTPREL))]
9680 "HAVE_AS_TLS && TARGET_64BIT"
9681 "addi %0,%1,%2@dtprel")
9683 (define_insn "tls_dtprel_ha_32"
9684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9685 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9686 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9687 UNSPEC_TLSDTPRELHA))]
9688 "HAVE_AS_TLS && !TARGET_64BIT"
9689 "addis %0,%1,%2@dtprel@ha")
9691 (define_insn "tls_dtprel_ha_64"
9692 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9693 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9694 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9695 UNSPEC_TLSDTPRELHA))]
9696 "HAVE_AS_TLS && TARGET_64BIT"
9697 "addis %0,%1,%2@dtprel@ha")
9699 (define_insn "tls_dtprel_lo_32"
9700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9701 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9702 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9703 UNSPEC_TLSDTPRELLO))]
9704 "HAVE_AS_TLS && !TARGET_64BIT"
9705 "addi %0,%1,%2@dtprel@l")
9707 (define_insn "tls_dtprel_lo_64"
9708 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9709 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9710 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9711 UNSPEC_TLSDTPRELLO))]
9712 "HAVE_AS_TLS && TARGET_64BIT"
9713 "addi %0,%1,%2@dtprel@l")
9715 (define_insn "tls_got_dtprel_32"
9716 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9717 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9718 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9719 UNSPEC_TLSGOTDTPREL))]
9720 "HAVE_AS_TLS && !TARGET_64BIT"
9721 "lwz %0,%2@got@dtprel(%1)")
9723 (define_insn "tls_got_dtprel_64"
9724 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9725 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9726 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9727 UNSPEC_TLSGOTDTPREL))]
9728 "HAVE_AS_TLS && TARGET_64BIT"
9729 "ld %0,%2@got@dtprel(%1)")
9731 (define_insn "tls_tprel_32"
9732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9733 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9734 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9735 UNSPEC_TLSTPREL))]
9736 "HAVE_AS_TLS && !TARGET_64BIT"
9737 "addi %0,%1,%2@tprel")
9739 (define_insn "tls_tprel_64"
9740 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9741 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9742 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9743 UNSPEC_TLSTPREL))]
9744 "HAVE_AS_TLS && TARGET_64BIT"
9745 "addi %0,%1,%2@tprel")
9747 (define_insn "tls_tprel_ha_32"
9748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9749 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9750 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9751 UNSPEC_TLSTPRELHA))]
9752 "HAVE_AS_TLS && !TARGET_64BIT"
9753 "addis %0,%1,%2@tprel@ha")
9755 (define_insn "tls_tprel_ha_64"
9756 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9757 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9758 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9759 UNSPEC_TLSTPRELHA))]
9760 "HAVE_AS_TLS && TARGET_64BIT"
9761 "addis %0,%1,%2@tprel@ha")
9763 (define_insn "tls_tprel_lo_32"
9764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9765 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9766 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9767 UNSPEC_TLSTPRELLO))]
9768 "HAVE_AS_TLS && !TARGET_64BIT"
9769 "addi %0,%1,%2@tprel@l")
9771 (define_insn "tls_tprel_lo_64"
9772 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9773 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9774 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9775 UNSPEC_TLSTPRELLO))]
9776 "HAVE_AS_TLS && TARGET_64BIT"
9777 "addi %0,%1,%2@tprel@l")
9779 ;; "b" output constraint here and on tls_tls input to support linker tls
9780 ;; optimization. The linker may edit the instructions emitted by a
9781 ;; tls_got_tprel/tls_tls pair to addis,addi.
9782 (define_insn "tls_got_tprel_32"
9783 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9784 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9785 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9786 UNSPEC_TLSGOTTPREL))]
9787 "HAVE_AS_TLS && !TARGET_64BIT"
9788 "lwz %0,%2@got@tprel(%1)")
9790 (define_insn "tls_got_tprel_64"
9791 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9792 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9793 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9794 UNSPEC_TLSGOTTPREL))]
9795 "HAVE_AS_TLS && TARGET_64BIT"
9796 "ld %0,%2@got@tprel(%1)")
9798 (define_insn "tls_tls_32"
9799 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9800 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9801 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9802 UNSPEC_TLSTLS))]
9803 "HAVE_AS_TLS && !TARGET_64BIT"
9804 "add %0,%1,%2@tls")
9806 (define_insn "tls_tls_64"
9807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9808 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9809 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9810 UNSPEC_TLSTLS))]
9811 "HAVE_AS_TLS && TARGET_64BIT"
9812 "add %0,%1,%2@tls")
9813 \f
9814 ;; Next come insns related to the calling sequence.
9815 ;;
9816 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9817 ;; We move the back-chain and decrement the stack pointer.
9819 (define_expand "allocate_stack"
9820 [(set (match_operand 0 "gpc_reg_operand" "=r")
9821 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9822 (set (reg 1)
9823 (minus (reg 1) (match_dup 1)))]
9824 ""
9825 "
9826 { rtx chain = gen_reg_rtx (Pmode);
9827 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9828 rtx neg_op0;
9830 emit_move_insn (chain, stack_bot);
9832 /* Check stack bounds if necessary. */
9833 if (current_function_limit_stack)
9834 {
9835 rtx available;
9836 available = expand_binop (Pmode, sub_optab,
9837 stack_pointer_rtx, stack_limit_rtx,
9838 NULL_RTX, 1, OPTAB_WIDEN);
9839 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9840 }
9842 if (GET_CODE (operands[1]) != CONST_INT
9843 || INTVAL (operands[1]) < -32767
9844 || INTVAL (operands[1]) > 32768)
9845 {
9846 neg_op0 = gen_reg_rtx (Pmode);
9847 if (TARGET_32BIT)
9848 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9849 else
9850 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9851 }
9852 else
9853 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9855 if (TARGET_UPDATE)
9856 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9857 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9859 else
9860 {
9861 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9862 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9863 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9864 }
9866 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9867 DONE;
9868 }")
9870 ;; These patterns say how to save and restore the stack pointer. We need not
9871 ;; save the stack pointer at function level since we are careful to
9872 ;; preserve the backchain. At block level, we have to restore the backchain
9873 ;; when we restore the stack pointer.
9874 ;;
9875 ;; For nonlocal gotos, we must save both the stack pointer and its
9876 ;; backchain and restore both. Note that in the nonlocal case, the
9877 ;; save area is a memory location.
9879 (define_expand "save_stack_function"
9880 [(match_operand 0 "any_operand" "")
9881 (match_operand 1 "any_operand" "")]
9882 ""
9883 "DONE;")
9885 (define_expand "restore_stack_function"
9886 [(match_operand 0 "any_operand" "")
9887 (match_operand 1 "any_operand" "")]
9888 ""
9889 "DONE;")
9891 (define_expand "restore_stack_block"
9892 [(use (match_operand 0 "register_operand" ""))
9893 (set (match_dup 2) (match_dup 3))
9894 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9895 (set (match_dup 3) (match_dup 2))]
9896 ""
9897 "
9898 {
9899 operands[2] = gen_reg_rtx (Pmode);
9900 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9901 }")
9903 (define_expand "save_stack_nonlocal"
9904 [(match_operand 0 "memory_operand" "")
9905 (match_operand 1 "register_operand" "")]
9906 ""
9907 "
9908 {
9909 rtx temp = gen_reg_rtx (Pmode);
9910 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9912 /* Copy the backchain to the first word, sp to the second. */
9913 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9914 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9915 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9916 operands[1]);
9917 DONE;
9918 }")
9920 (define_expand "restore_stack_nonlocal"
9921 [(match_operand 0 "register_operand" "")
9922 (match_operand 1 "memory_operand" "")]
9923 ""
9924 "
9925 {
9926 rtx temp = gen_reg_rtx (Pmode);
9927 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9929 /* Restore the backchain from the first word, sp from the second. */
9930 emit_move_insn (temp,
9931 adjust_address_nv (operands[1], Pmode, 0));
9932 emit_move_insn (operands[0],
9933 adjust_address_nv (operands[1], Pmode, units_per_word));
9934 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9935 DONE;
9936 }")
9937 \f
9938 ;; TOC register handling.
9940 ;; Code to initialize the TOC register...
9942 (define_insn "load_toc_aix_si"
9943 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9944 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9945 (use (reg:SI 2))])]
9946 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9947 "*
9948 {
9949 char buf[30];
9950 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9951 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9952 operands[2] = gen_rtx_REG (Pmode, 2);
9953 return \"{l|lwz} %0,%1(%2)\";
9954 }"
9955 [(set_attr "type" "load")])
9957 (define_insn "load_toc_aix_di"
9958 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9959 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9960 (use (reg:DI 2))])]
9961 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9962 "*
9963 {
9964 char buf[30];
9965 #ifdef TARGET_RELOCATABLE
9966 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9967 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9968 #else
9969 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9970 #endif
9971 if (TARGET_ELF)
9972 strcat (buf, \"@toc\");
9973 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9974 operands[2] = gen_rtx_REG (Pmode, 2);
9975 return \"ld %0,%1(%2)\";
9976 }"
9977 [(set_attr "type" "load")])
9979 (define_insn "load_toc_v4_pic_si"
9980 [(set (match_operand:SI 0 "register_operand" "=l")
9981 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9982 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9983 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9984 [(set_attr "type" "branch")
9985 (set_attr "length" "4")])
9987 (define_insn "load_toc_v4_PIC_1"
9988 [(set (match_operand:SI 0 "register_operand" "=l")
9989 (match_operand:SI 1 "immediate_operand" "s"))
9990 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9991 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9992 "bcl 20,31,%1\\n%1:"
9993 [(set_attr "type" "branch")
9994 (set_attr "length" "4")])
9996 (define_insn "load_toc_v4_PIC_1b"
9997 [(set (match_operand:SI 0 "register_operand" "=l")
9998 (match_operand:SI 1 "immediate_operand" "s"))
9999 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10000 UNSPEC_TOCPTR))]
10001 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10002 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10003 [(set_attr "type" "branch")
10004 (set_attr "length" "8")])
10006 (define_insn "load_toc_v4_PIC_2"
10007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10008 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10009 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10010 (match_operand:SI 3 "immediate_operand" "s")))))]
10011 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10012 "{l|lwz} %0,%2-%3(%1)"
10013 [(set_attr "type" "load")])
10015 (define_insn "load_macho_picbase"
10016 [(set (match_operand:SI 0 "register_operand" "=l")
10017 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10018 UNSPEC_LD_MPIC))]
10019 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
10020 "bcl 20,31,%1\\n%1:"
10021 [(set_attr "type" "branch")
10022 (set_attr "length" "4")])
10024 (define_insn "macho_correct_pic"
10025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10026 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10027 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10028 (match_operand:SI 3 "immediate_operand" "s")]
10029 UNSPEC_MPIC_CORRECT)))]
10030 "DEFAULT_ABI == ABI_DARWIN"
10031 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
10032 [(set_attr "length" "8")])
10034 ;; If the TOC is shared over a translation unit, as happens with all
10035 ;; the kinds of PIC that we support, we need to restore the TOC
10036 ;; pointer only when jumping over units of translation.
10037 ;; On Darwin, we need to reload the picbase.
10039 (define_expand "builtin_setjmp_receiver"
10040 [(use (label_ref (match_operand 0 "" "")))]
10041 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10042 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10043 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10044 "
10045 {
10046 #if TARGET_MACHO
10047 if (DEFAULT_ABI == ABI_DARWIN)
10048 {
10049 const char *picbase = machopic_function_base_name ();
10050 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10051 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10052 rtx tmplabrtx;
10053 char tmplab[20];
10055 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10056 CODE_LABEL_NUMBER (operands[0]));
10057 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10059 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10060 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10061 }
10062 else
10063 #endif
10064 rs6000_emit_load_toc_table (FALSE);
10065 DONE;
10066 }")
10067 \f
10068 ;; A function pointer under AIX is a pointer to a data area whose first word
10069 ;; contains the actual address of the function, whose second word contains a
10070 ;; pointer to its TOC, and whose third word contains a value to place in the
10071 ;; static chain register (r11). Note that if we load the static chain, our
10072 ;; "trampoline" need not have any executable code.
10074 (define_expand "call_indirect_aix32"
10075 [(set (match_dup 2)
10076 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10077 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10078 (reg:SI 2))
10079 (set (reg:SI 2)
10080 (mem:SI (plus:SI (match_dup 0)
10081 (const_int 4))))
10082 (set (reg:SI 11)
10083 (mem:SI (plus:SI (match_dup 0)
10084 (const_int 8))))
10085 (parallel [(call (mem:SI (match_dup 2))
10086 (match_operand 1 "" ""))
10087 (use (reg:SI 2))
10088 (use (reg:SI 11))
10089 (set (reg:SI 2)
10090 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10091 (clobber (scratch:SI))])]
10092 "TARGET_32BIT"
10093 "
10094 { operands[2] = gen_reg_rtx (SImode); }")
10096 (define_expand "call_indirect_aix64"
10097 [(set (match_dup 2)
10098 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10099 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10100 (reg:DI 2))
10101 (set (reg:DI 2)
10102 (mem:DI (plus:DI (match_dup 0)
10103 (const_int 8))))
10104 (set (reg:DI 11)
10105 (mem:DI (plus:DI (match_dup 0)
10106 (const_int 16))))
10107 (parallel [(call (mem:SI (match_dup 2))
10108 (match_operand 1 "" ""))
10109 (use (reg:DI 2))
10110 (use (reg:DI 11))
10111 (set (reg:DI 2)
10112 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10113 (clobber (scratch:SI))])]
10114 "TARGET_64BIT"
10115 "
10116 { operands[2] = gen_reg_rtx (DImode); }")
10118 (define_expand "call_value_indirect_aix32"
10119 [(set (match_dup 3)
10120 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10121 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10122 (reg:SI 2))
10123 (set (reg:SI 2)
10124 (mem:SI (plus:SI (match_dup 1)
10125 (const_int 4))))
10126 (set (reg:SI 11)
10127 (mem:SI (plus:SI (match_dup 1)
10128 (const_int 8))))
10129 (parallel [(set (match_operand 0 "" "")
10130 (call (mem:SI (match_dup 3))
10131 (match_operand 2 "" "")))
10132 (use (reg:SI 2))
10133 (use (reg:SI 11))
10134 (set (reg:SI 2)
10135 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10136 (clobber (scratch:SI))])]
10137 "TARGET_32BIT"
10138 "
10139 { operands[3] = gen_reg_rtx (SImode); }")
10141 (define_expand "call_value_indirect_aix64"
10142 [(set (match_dup 3)
10143 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10144 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10145 (reg:DI 2))
10146 (set (reg:DI 2)
10147 (mem:DI (plus:DI (match_dup 1)
10148 (const_int 8))))
10149 (set (reg:DI 11)
10150 (mem:DI (plus:DI (match_dup 1)
10151 (const_int 16))))
10152 (parallel [(set (match_operand 0 "" "")
10153 (call (mem:SI (match_dup 3))
10154 (match_operand 2 "" "")))
10155 (use (reg:DI 2))
10156 (use (reg:DI 11))
10157 (set (reg:DI 2)
10158 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10159 (clobber (scratch:SI))])]
10160 "TARGET_64BIT"
10161 "
10162 { operands[3] = gen_reg_rtx (DImode); }")
10164 ;; Now the definitions for the call and call_value insns
10165 (define_expand "call"
10166 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10167 (match_operand 1 "" ""))
10168 (use (match_operand 2 "" ""))
10169 (clobber (scratch:SI))])]
10170 ""
10171 "
10172 {
10173 #if TARGET_MACHO
10174 if (MACHOPIC_INDIRECT)
10175 operands[0] = machopic_indirect_call_target (operands[0]);
10176 #endif
10178 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10179 abort ();
10181 operands[0] = XEXP (operands[0], 0);
10183 if (GET_CODE (operands[0]) != SYMBOL_REF
10184 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10185 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10186 {
10187 if (INTVAL (operands[2]) & CALL_LONG)
10188 operands[0] = rs6000_longcall_ref (operands[0]);
10190 if (DEFAULT_ABI == ABI_V4
10191 || DEFAULT_ABI == ABI_DARWIN)
10192 operands[0] = force_reg (Pmode, operands[0]);
10194 else if (DEFAULT_ABI == ABI_AIX)
10195 {
10196 /* AIX function pointers are really pointers to a three word
10197 area. */
10198 emit_call_insn (TARGET_32BIT
10199 ? gen_call_indirect_aix32 (force_reg (SImode,
10200 operands[0]),
10201 operands[1])
10202 : gen_call_indirect_aix64 (force_reg (DImode,
10203 operands[0]),
10204 operands[1]));
10205 DONE;
10206 }
10207 else
10208 abort ();
10209 }
10210 }")
10212 (define_expand "call_value"
10213 [(parallel [(set (match_operand 0 "" "")
10214 (call (mem:SI (match_operand 1 "address_operand" ""))
10215 (match_operand 2 "" "")))
10216 (use (match_operand 3 "" ""))
10217 (clobber (scratch:SI))])]
10218 ""
10219 "
10220 {
10221 #if TARGET_MACHO
10222 if (MACHOPIC_INDIRECT)
10223 operands[1] = machopic_indirect_call_target (operands[1]);
10224 #endif
10226 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10227 abort ();
10229 operands[1] = XEXP (operands[1], 0);
10231 if (GET_CODE (operands[1]) != SYMBOL_REF
10232 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10233 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10234 {
10235 if (INTVAL (operands[3]) & CALL_LONG)
10236 operands[1] = rs6000_longcall_ref (operands[1]);
10238 if (DEFAULT_ABI == ABI_V4
10239 || DEFAULT_ABI == ABI_DARWIN)
10240 operands[1] = force_reg (Pmode, operands[1]);
10242 else if (DEFAULT_ABI == ABI_AIX)
10243 {
10244 /* AIX function pointers are really pointers to a three word
10245 area. */
10246 emit_call_insn (TARGET_32BIT
10247 ? gen_call_value_indirect_aix32 (operands[0],
10248 force_reg (SImode,
10249 operands[1]),
10250 operands[2])
10251 : gen_call_value_indirect_aix64 (operands[0],
10252 force_reg (DImode,
10253 operands[1]),
10254 operands[2]));
10255 DONE;
10256 }
10257 else
10258 abort ();
10259 }
10260 }")
10262 ;; Call to function in current module. No TOC pointer reload needed.
10263 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10264 ;; either the function was not prototyped, or it was prototyped as a
10265 ;; variable argument function. It is > 0 if FP registers were passed
10266 ;; and < 0 if they were not.
10268 (define_insn "*call_local32"
10269 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10270 (match_operand 1 "" "g,g"))
10271 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10272 (clobber (match_scratch:SI 3 "=l,l"))]
10273 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10274 "*
10275 {
10276 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10277 output_asm_insn (\"crxor 6,6,6\", operands);
10279 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10280 output_asm_insn (\"creqv 6,6,6\", operands);
10282 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10283 }"
10284 [(set_attr "type" "branch")
10285 (set_attr "length" "4,8")])
10287 (define_insn "*call_local64"
10288 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10289 (match_operand 1 "" "g,g"))
10290 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10291 (clobber (match_scratch:SI 3 "=l,l"))]
10292 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10293 "*
10294 {
10295 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10296 output_asm_insn (\"crxor 6,6,6\", operands);
10298 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10299 output_asm_insn (\"creqv 6,6,6\", operands);
10301 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10302 }"
10303 [(set_attr "type" "branch")
10304 (set_attr "length" "4,8")])
10306 (define_insn "*call_value_local32"
10307 [(set (match_operand 0 "" "")
10308 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10309 (match_operand 2 "" "g,g")))
10310 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10311 (clobber (match_scratch:SI 4 "=l,l"))]
10312 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10313 "*
10314 {
10315 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10316 output_asm_insn (\"crxor 6,6,6\", operands);
10318 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10319 output_asm_insn (\"creqv 6,6,6\", operands);
10321 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10322 }"
10323 [(set_attr "type" "branch")
10324 (set_attr "length" "4,8")])
10327 (define_insn "*call_value_local64"
10328 [(set (match_operand 0 "" "")
10329 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10330 (match_operand 2 "" "g,g")))
10331 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10332 (clobber (match_scratch:SI 4 "=l,l"))]
10333 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10334 "*
10335 {
10336 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10337 output_asm_insn (\"crxor 6,6,6\", operands);
10339 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10340 output_asm_insn (\"creqv 6,6,6\", operands);
10342 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10343 }"
10344 [(set_attr "type" "branch")
10345 (set_attr "length" "4,8")])
10347 ;; Call to function which may be in another module. Restore the TOC
10348 ;; pointer (r2) after the call unless this is System V.
10349 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10350 ;; either the function was not prototyped, or it was prototyped as a
10351 ;; variable argument function. It is > 0 if FP registers were passed
10352 ;; and < 0 if they were not.
10354 (define_insn "*call_indirect_nonlocal_aix32"
10355 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10356 (match_operand 1 "" "g"))
10357 (use (reg:SI 2))
10358 (use (reg:SI 11))
10359 (set (reg:SI 2)
10360 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10361 (clobber (match_scratch:SI 2 "=l"))]
10362 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10363 "b%T0l\;{l|lwz} 2,20(1)"
10364 [(set_attr "type" "jmpreg")
10365 (set_attr "length" "8")])
10367 (define_insn "*call_nonlocal_aix32"
10368 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10369 (match_operand 1 "" "g"))
10370 (use (match_operand:SI 2 "immediate_operand" "O"))
10371 (clobber (match_scratch:SI 3 "=l"))]
10372 "TARGET_32BIT
10373 && DEFAULT_ABI == ABI_AIX
10374 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10375 "bl %z0\;%."
10376 [(set_attr "type" "branch")
10377 (set_attr "length" "8")])
10379 (define_insn "*call_indirect_nonlocal_aix64"
10380 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10381 (match_operand 1 "" "g"))
10382 (use (reg:DI 2))
10383 (use (reg:DI 11))
10384 (set (reg:DI 2)
10385 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10386 (clobber (match_scratch:SI 2 "=l"))]
10387 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10388 "b%T0l\;ld 2,40(1)"
10389 [(set_attr "type" "jmpreg")
10390 (set_attr "length" "8")])
10392 (define_insn "*call_nonlocal_aix64"
10393 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10394 (match_operand 1 "" "g"))
10395 (use (match_operand:SI 2 "immediate_operand" "O"))
10396 (clobber (match_scratch:SI 3 "=l"))]
10397 "TARGET_64BIT
10398 && DEFAULT_ABI == ABI_AIX
10399 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10400 "bl %z0\;%."
10401 [(set_attr "type" "branch")
10402 (set_attr "length" "8")])
10404 (define_insn "*call_value_indirect_nonlocal_aix32"
10405 [(set (match_operand 0 "" "")
10406 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10407 (match_operand 2 "" "g")))
10408 (use (reg:SI 2))
10409 (use (reg:SI 11))
10410 (set (reg:SI 2)
10411 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10412 (clobber (match_scratch:SI 3 "=l"))]
10413 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10414 "b%T1l\;{l|lwz} 2,20(1)"
10415 [(set_attr "type" "jmpreg")
10416 (set_attr "length" "8")])
10418 (define_insn "*call_value_nonlocal_aix32"
10419 [(set (match_operand 0 "" "")
10420 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10421 (match_operand 2 "" "g")))
10422 (use (match_operand:SI 3 "immediate_operand" "O"))
10423 (clobber (match_scratch:SI 4 "=l"))]
10424 "TARGET_32BIT
10425 && DEFAULT_ABI == ABI_AIX
10426 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10427 "bl %z1\;%."
10428 [(set_attr "type" "branch")
10429 (set_attr "length" "8")])
10431 (define_insn "*call_value_indirect_nonlocal_aix64"
10432 [(set (match_operand 0 "" "")
10433 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10434 (match_operand 2 "" "g")))
10435 (use (reg:DI 2))
10436 (use (reg:DI 11))
10437 (set (reg:DI 2)
10438 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10439 (clobber (match_scratch:SI 3 "=l"))]
10440 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10441 "b%T1l\;ld 2,40(1)"
10442 [(set_attr "type" "jmpreg")
10443 (set_attr "length" "8")])
10445 (define_insn "*call_value_nonlocal_aix64"
10446 [(set (match_operand 0 "" "")
10447 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10448 (match_operand 2 "" "g")))
10449 (use (match_operand:SI 3 "immediate_operand" "O"))
10450 (clobber (match_scratch:SI 4 "=l"))]
10451 "TARGET_64BIT
10452 && DEFAULT_ABI == ABI_AIX
10453 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10454 "bl %z1\;%."
10455 [(set_attr "type" "branch")
10456 (set_attr "length" "8")])
10458 ;; A function pointer under System V is just a normal pointer
10459 ;; operands[0] is the function pointer
10460 ;; operands[1] is the stack size to clean up
10461 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10462 ;; which indicates how to set cr1
10464 (define_insn "*call_indirect_nonlocal_sysv"
10465 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10466 (match_operand 1 "" "g,g"))
10467 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10468 (clobber (match_scratch:SI 3 "=l,l"))]
10469 "DEFAULT_ABI == ABI_V4
10470 || DEFAULT_ABI == ABI_DARWIN"
10471 {
10472 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10473 output_asm_insn ("crxor 6,6,6", operands);
10475 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10476 output_asm_insn ("creqv 6,6,6", operands);
10478 return "b%T0l";
10479 }
10480 [(set_attr "type" "jmpreg,jmpreg")
10481 (set_attr "length" "4,8")])
10483 (define_insn "*call_nonlocal_sysv"
10484 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10485 (match_operand 1 "" "g,g"))
10486 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10487 (clobber (match_scratch:SI 3 "=l,l"))]
10488 "(DEFAULT_ABI == ABI_DARWIN
10489 || (DEFAULT_ABI == ABI_V4
10490 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10491 {
10492 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10493 output_asm_insn ("crxor 6,6,6", operands);
10495 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10496 output_asm_insn ("creqv 6,6,6", operands);
10498 #if TARGET_MACHO
10499 return output_call(insn, operands, 0, 2);
10500 #else
10501 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10502 #endif
10503 }
10504 [(set_attr "type" "branch,branch")
10505 (set_attr "length" "4,8")])
10507 (define_insn "*call_value_indirect_nonlocal_sysv"
10508 [(set (match_operand 0 "" "")
10509 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10510 (match_operand 2 "" "g,g")))
10511 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10512 (clobber (match_scratch:SI 4 "=l,l"))]
10513 "DEFAULT_ABI == ABI_V4
10514 || DEFAULT_ABI == ABI_DARWIN"
10515 {
10516 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10517 output_asm_insn ("crxor 6,6,6", operands);
10519 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10520 output_asm_insn ("creqv 6,6,6", operands);
10522 return "b%T1l";
10523 }
10524 [(set_attr "type" "jmpreg,jmpreg")
10525 (set_attr "length" "4,8")])
10527 (define_insn "*call_value_nonlocal_sysv"
10528 [(set (match_operand 0 "" "")
10529 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10530 (match_operand 2 "" "g,g")))
10531 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10532 (clobber (match_scratch:SI 4 "=l,l"))]
10533 "(DEFAULT_ABI == ABI_DARWIN
10534 || (DEFAULT_ABI == ABI_V4
10535 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10536 {
10537 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10538 output_asm_insn ("crxor 6,6,6", operands);
10540 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10541 output_asm_insn ("creqv 6,6,6", operands);
10543 #if TARGET_MACHO
10544 return output_call(insn, operands, 1, 3);
10545 #else
10546 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10547 #endif
10548 }
10549 [(set_attr "type" "branch,branch")
10550 (set_attr "length" "4,8")])
10552 ;; Call subroutine returning any type.
10553 (define_expand "untyped_call"
10554 [(parallel [(call (match_operand 0 "" "")
10555 (const_int 0))
10556 (match_operand 1 "" "")
10557 (match_operand 2 "" "")])]
10558 ""
10559 "
10560 {
10561 int i;
10563 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10565 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10566 {
10567 rtx set = XVECEXP (operands[2], 0, i);
10568 emit_move_insn (SET_DEST (set), SET_SRC (set));
10569 }
10571 /* The optimizer does not know that the call sets the function value
10572 registers we stored in the result block. We avoid problems by
10573 claiming that all hard registers are used and clobbered at this
10574 point. */
10575 emit_insn (gen_blockage ());
10577 DONE;
10578 }")
10580 ;; sibling call patterns
10581 (define_expand "sibcall"
10582 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10583 (match_operand 1 "" ""))
10584 (use (match_operand 2 "" ""))
10585 (use (match_operand 3 "" ""))
10586 (return)])]
10587 ""
10588 "
10589 {
10590 #if TARGET_MACHO
10591 if (MACHOPIC_INDIRECT)
10592 operands[0] = machopic_indirect_call_target (operands[0]);
10593 #endif
10595 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10596 abort ();
10598 operands[0] = XEXP (operands[0], 0);
10599 operands[3] = gen_reg_rtx (SImode);
10601 }")
10603 ;; this and similar patterns must be marked as using LR, otherwise
10604 ;; dataflow will try to delete the store into it. This is true
10605 ;; even when the actual reg to jump to is in CTR, when LR was
10606 ;; saved and restored around the PIC-setting BCL.
10607 (define_insn "*sibcall_local32"
10608 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10609 (match_operand 1 "" "g,g"))
10610 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10611 (use (match_operand:SI 3 "register_operand" "l,l"))
10612 (return)]
10613 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10614 "*
10615 {
10616 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10617 output_asm_insn (\"crxor 6,6,6\", operands);
10619 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10620 output_asm_insn (\"creqv 6,6,6\", operands);
10622 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10623 }"
10624 [(set_attr "type" "branch")
10625 (set_attr "length" "4,8")])
10627 (define_insn "*sibcall_local64"
10628 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10629 (match_operand 1 "" "g,g"))
10630 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10631 (use (match_operand:SI 3 "register_operand" "l,l"))
10632 (return)]
10633 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10634 "*
10635 {
10636 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10637 output_asm_insn (\"crxor 6,6,6\", operands);
10639 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10640 output_asm_insn (\"creqv 6,6,6\", operands);
10642 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10643 }"
10644 [(set_attr "type" "branch")
10645 (set_attr "length" "4,8")])
10647 (define_insn "*sibcall_value_local32"
10648 [(set (match_operand 0 "" "")
10649 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10650 (match_operand 2 "" "g,g")))
10651 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10652 (use (match_operand:SI 4 "register_operand" "l,l"))
10653 (return)]
10654 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10655 "*
10656 {
10657 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10658 output_asm_insn (\"crxor 6,6,6\", operands);
10660 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10661 output_asm_insn (\"creqv 6,6,6\", operands);
10663 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10664 }"
10665 [(set_attr "type" "branch")
10666 (set_attr "length" "4,8")])
10669 (define_insn "*sibcall_value_local64"
10670 [(set (match_operand 0 "" "")
10671 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10672 (match_operand 2 "" "g,g")))
10673 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10674 (use (match_operand:SI 4 "register_operand" "l,l"))
10675 (return)]
10676 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10677 "*
10678 {
10679 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10680 output_asm_insn (\"crxor 6,6,6\", operands);
10682 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10683 output_asm_insn (\"creqv 6,6,6\", operands);
10685 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10686 }"
10687 [(set_attr "type" "branch")
10688 (set_attr "length" "4,8")])
10690 (define_insn "*sibcall_nonlocal_aix32"
10691 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10692 (match_operand 1 "" "g"))
10693 (use (match_operand:SI 2 "immediate_operand" "O"))
10694 (use (match_operand:SI 3 "register_operand" "l"))
10695 (return)]
10696 "TARGET_32BIT
10697 && DEFAULT_ABI == ABI_AIX
10698 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10699 "b %z0"
10700 [(set_attr "type" "branch")
10701 (set_attr "length" "4")])
10703 (define_insn "*sibcall_nonlocal_aix64"
10704 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10705 (match_operand 1 "" "g"))
10706 (use (match_operand:SI 2 "immediate_operand" "O"))
10707 (use (match_operand:SI 3 "register_operand" "l"))
10708 (return)]
10709 "TARGET_64BIT
10710 && DEFAULT_ABI == ABI_AIX
10711 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10712 "b %z0"
10713 [(set_attr "type" "branch")
10714 (set_attr "length" "4")])
10716 (define_insn "*sibcall_value_nonlocal_aix32"
10717 [(set (match_operand 0 "" "")
10718 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10719 (match_operand 2 "" "g")))
10720 (use (match_operand:SI 3 "immediate_operand" "O"))
10721 (use (match_operand:SI 4 "register_operand" "l"))
10722 (return)]
10723 "TARGET_32BIT
10724 && DEFAULT_ABI == ABI_AIX
10725 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10726 "b %z1"
10727 [(set_attr "type" "branch")
10728 (set_attr "length" "4")])
10730 (define_insn "*sibcall_value_nonlocal_aix64"
10731 [(set (match_operand 0 "" "")
10732 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10733 (match_operand 2 "" "g")))
10734 (use (match_operand:SI 3 "immediate_operand" "O"))
10735 (use (match_operand:SI 4 "register_operand" "l"))
10736 (return)]
10737 "TARGET_64BIT
10738 && DEFAULT_ABI == ABI_AIX
10739 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10740 "b %z1"
10741 [(set_attr "type" "branch")
10742 (set_attr "length" "4")])
10744 (define_insn "*sibcall_nonlocal_sysv"
10745 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10746 (match_operand 1 "" ""))
10747 (use (match_operand 2 "immediate_operand" "O,n"))
10748 (use (match_operand:SI 3 "register_operand" "l,l"))
10749 (return)]
10750 "(DEFAULT_ABI == ABI_DARWIN
10751 || DEFAULT_ABI == ABI_V4)
10752 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10753 "*
10754 {
10755 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10756 output_asm_insn (\"crxor 6,6,6\", operands);
10758 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10759 output_asm_insn (\"creqv 6,6,6\", operands);
10761 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10762 }"
10763 [(set_attr "type" "branch,branch")
10764 (set_attr "length" "4,8")])
10766 (define_expand "sibcall_value"
10767 [(parallel [(set (match_operand 0 "register_operand" "")
10768 (call (mem:SI (match_operand 1 "address_operand" ""))
10769 (match_operand 2 "" "")))
10770 (use (match_operand 3 "" ""))
10771 (use (match_operand 4 "" ""))
10772 (return)])]
10773 ""
10774 "
10775 {
10776 #if TARGET_MACHO
10777 if (MACHOPIC_INDIRECT)
10778 operands[1] = machopic_indirect_call_target (operands[1]);
10779 #endif
10781 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10782 abort ();
10784 operands[1] = XEXP (operands[1], 0);
10785 operands[4] = gen_reg_rtx (SImode);
10787 }")
10789 (define_insn "*sibcall_value_nonlocal_sysv"
10790 [(set (match_operand 0 "" "")
10791 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10792 (match_operand 2 "" "")))
10793 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10794 (use (match_operand:SI 4 "register_operand" "l,l"))
10795 (return)]
10796 "(DEFAULT_ABI == ABI_DARWIN
10797 || DEFAULT_ABI == ABI_V4)
10798 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10799 "*
10800 {
10801 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10802 output_asm_insn (\"crxor 6,6,6\", operands);
10804 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10805 output_asm_insn (\"creqv 6,6,6\", operands);
10807 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10808 }"
10809 [(set_attr "type" "branch,branch")
10810 (set_attr "length" "4,8")])
10812 (define_expand "sibcall_epilogue"
10813 [(use (const_int 0))]
10814 "TARGET_SCHED_PROLOG"
10815 "
10816 {
10817 rs6000_emit_epilogue (TRUE);
10818 DONE;
10819 }")
10821 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10822 ;; all of memory. This blocks insns from being moved across this point.
10824 (define_insn "blockage"
10825 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10826 ""
10827 "")
10828 \f
10829 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10830 ;; signed & unsigned, and one type of branch.
10831 ;;
10832 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10833 ;; insns, and branches. We store the operands of compares until we see
10834 ;; how it is used.
10835 (define_expand "cmpsi"
10836 [(set (cc0)
10837 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10838 (match_operand:SI 1 "reg_or_short_operand" "")))]
10839 ""
10840 "
10841 {
10842 /* Take care of the possibility that operands[1] might be negative but
10843 this might be a logical operation. That insn doesn't exist. */
10844 if (GET_CODE (operands[1]) == CONST_INT
10845 && INTVAL (operands[1]) < 0)
10846 operands[1] = force_reg (SImode, operands[1]);
10848 rs6000_compare_op0 = operands[0];
10849 rs6000_compare_op1 = operands[1];
10850 rs6000_compare_fp_p = 0;
10851 DONE;
10852 }")
10854 (define_expand "cmpdi"
10855 [(set (cc0)
10856 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10857 (match_operand:DI 1 "reg_or_short_operand" "")))]
10858 "TARGET_POWERPC64"
10859 "
10860 {
10861 /* Take care of the possibility that operands[1] might be negative but
10862 this might be a logical operation. That insn doesn't exist. */
10863 if (GET_CODE (operands[1]) == CONST_INT
10864 && INTVAL (operands[1]) < 0)
10865 operands[1] = force_reg (DImode, operands[1]);
10867 rs6000_compare_op0 = operands[0];
10868 rs6000_compare_op1 = operands[1];
10869 rs6000_compare_fp_p = 0;
10870 DONE;
10871 }")
10873 (define_expand "cmpsf"
10874 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10875 (match_operand:SF 1 "gpc_reg_operand" "")))]
10876 "TARGET_HARD_FLOAT"
10877 "
10878 {
10879 rs6000_compare_op0 = operands[0];
10880 rs6000_compare_op1 = operands[1];
10881 rs6000_compare_fp_p = 1;
10882 DONE;
10883 }")
10885 (define_expand "cmpdf"
10886 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10887 (match_operand:DF 1 "gpc_reg_operand" "")))]
10888 "TARGET_HARD_FLOAT && TARGET_FPRS"
10889 "
10890 {
10891 rs6000_compare_op0 = operands[0];
10892 rs6000_compare_op1 = operands[1];
10893 rs6000_compare_fp_p = 1;
10894 DONE;
10895 }")
10897 (define_expand "cmptf"
10898 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10899 (match_operand:TF 1 "gpc_reg_operand" "")))]
10900 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10901 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10902 "
10903 {
10904 rs6000_compare_op0 = operands[0];
10905 rs6000_compare_op1 = operands[1];
10906 rs6000_compare_fp_p = 1;
10907 DONE;
10908 }")
10910 (define_expand "beq"
10911 [(use (match_operand 0 "" ""))]
10912 ""
10913 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10915 (define_expand "bne"
10916 [(use (match_operand 0 "" ""))]
10917 ""
10918 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10920 (define_expand "bge"
10921 [(use (match_operand 0 "" ""))]
10922 ""
10923 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10925 (define_expand "bgt"
10926 [(use (match_operand 0 "" ""))]
10927 ""
10928 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10930 (define_expand "ble"
10931 [(use (match_operand 0 "" ""))]
10932 ""
10933 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10935 (define_expand "blt"
10936 [(use (match_operand 0 "" ""))]
10937 ""
10938 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10940 (define_expand "bgeu"
10941 [(use (match_operand 0 "" ""))]
10942 ""
10943 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10945 (define_expand "bgtu"
10946 [(use (match_operand 0 "" ""))]
10947 ""
10948 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10950 (define_expand "bleu"
10951 [(use (match_operand 0 "" ""))]
10952 ""
10953 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10955 (define_expand "bltu"
10956 [(use (match_operand 0 "" ""))]
10957 ""
10958 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10960 (define_expand "bunordered"
10961 [(use (match_operand 0 "" ""))]
10962 ""
10963 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10965 (define_expand "bordered"
10966 [(use (match_operand 0 "" ""))]
10967 ""
10968 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10970 (define_expand "buneq"
10971 [(use (match_operand 0 "" ""))]
10972 ""
10973 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10975 (define_expand "bunge"
10976 [(use (match_operand 0 "" ""))]
10977 ""
10978 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10980 (define_expand "bungt"
10981 [(use (match_operand 0 "" ""))]
10982 ""
10983 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10985 (define_expand "bunle"
10986 [(use (match_operand 0 "" ""))]
10987 ""
10988 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10990 (define_expand "bunlt"
10991 [(use (match_operand 0 "" ""))]
10992 ""
10993 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10995 (define_expand "bltgt"
10996 [(use (match_operand 0 "" ""))]
10997 ""
10998 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11000 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11001 ;; For SEQ, likewise, except that comparisons with zero should be done
11002 ;; with an scc insns. However, due to the order that combine see the
11003 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11004 ;; the cases we don't want to handle.
11005 (define_expand "seq"
11006 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11007 ""
11008 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11010 (define_expand "sne"
11011 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11012 ""
11013 "
11014 {
11015 if (! rs6000_compare_fp_p)
11016 FAIL;
11018 rs6000_emit_sCOND (NE, operands[0]);
11019 DONE;
11020 }")
11022 ;; A >= 0 is best done the portable way for A an integer.
11023 (define_expand "sge"
11024 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11025 ""
11026 "
11027 {
11028 if (! rs6000_compare_fp_p
11029 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11030 FAIL;
11032 rs6000_emit_sCOND (GE, operands[0]);
11033 DONE;
11034 }")
11036 ;; A > 0 is best done using the portable sequence, so fail in that case.
11037 (define_expand "sgt"
11038 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11039 ""
11040 "
11041 {
11042 if (! rs6000_compare_fp_p
11043 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11044 FAIL;
11046 rs6000_emit_sCOND (GT, operands[0]);
11047 DONE;
11048 }")
11050 ;; A <= 0 is best done the portable way for A an integer.
11051 (define_expand "sle"
11052 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11053 ""
11054 "
11055 {
11056 if (! rs6000_compare_fp_p
11057 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11058 FAIL;
11060 rs6000_emit_sCOND (LE, operands[0]);
11061 DONE;
11062 }")
11064 ;; A < 0 is best done in the portable way for A an integer.
11065 (define_expand "slt"
11066 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11067 ""
11068 "
11069 {
11070 if (! rs6000_compare_fp_p
11071 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11072 FAIL;
11074 rs6000_emit_sCOND (LT, operands[0]);
11075 DONE;
11076 }")
11078 (define_expand "sgeu"
11079 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11080 ""
11081 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11083 (define_expand "sgtu"
11084 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11085 ""
11086 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11088 (define_expand "sleu"
11089 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11090 ""
11091 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11093 (define_expand "sltu"
11094 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11095 ""
11096 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11098 (define_expand "sunordered"
11099 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11100 ""
11101 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11103 (define_expand "sordered"
11104 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11105 ""
11106 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11108 (define_expand "suneq"
11109 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11110 ""
11111 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11113 (define_expand "sunge"
11114 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11115 ""
11116 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11118 (define_expand "sungt"
11119 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11120 ""
11121 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11123 (define_expand "sunle"
11124 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11125 ""
11126 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11128 (define_expand "sunlt"
11129 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11130 ""
11131 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11133 (define_expand "sltgt"
11134 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11135 ""
11136 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11138 \f
11139 ;; Here are the actual compare insns.
11140 (define_insn "*cmpsi_internal1"
11141 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11142 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11143 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11144 ""
11145 "{cmp%I2|cmpw%I2} %0,%1,%2"
11146 [(set_attr "type" "cmp")])
11148 (define_insn "*cmpdi_internal1"
11149 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11150 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11151 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11152 "TARGET_POWERPC64"
11153 "cmpd%I2 %0,%1,%2"
11154 [(set_attr "type" "cmp")])
11156 ;; If we are comparing a register for equality with a large constant,
11157 ;; we can do this with an XOR followed by a compare. But we need a scratch
11158 ;; register for the result of the XOR.
11160 (define_split
11161 [(set (match_operand:CC 0 "cc_reg_operand" "")
11162 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11163 (match_operand:SI 2 "non_short_cint_operand" "")))
11164 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11165 "find_single_use (operands[0], insn, 0)
11166 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11167 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11168 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11169 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11170 "
11171 {
11172 /* Get the constant we are comparing against, C, and see what it looks like
11173 sign-extended to 16 bits. Then see what constant could be XOR'ed
11174 with C to get the sign-extended value. */
11176 HOST_WIDE_INT c = INTVAL (operands[2]);
11177 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11178 HOST_WIDE_INT xorv = c ^ sextc;
11180 operands[4] = GEN_INT (xorv);
11181 operands[5] = GEN_INT (sextc);
11182 }")
11184 (define_insn "*cmpsi_internal2"
11185 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11186 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11187 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11188 ""
11189 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11190 [(set_attr "type" "cmp")])
11192 (define_insn "*cmpdi_internal2"
11193 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11194 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11195 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11196 ""
11197 "cmpld%I2 %0,%1,%b2"
11198 [(set_attr "type" "cmp")])
11200 ;; The following two insns don't exist as single insns, but if we provide
11201 ;; them, we can swap an add and compare, which will enable us to overlap more
11202 ;; of the required delay between a compare and branch. We generate code for
11203 ;; them by splitting.
11205 (define_insn ""
11206 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11207 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11208 (match_operand:SI 2 "short_cint_operand" "i")))
11209 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11210 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11211 ""
11212 "#"
11213 [(set_attr "length" "8")])
11215 (define_insn ""
11216 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11217 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11218 (match_operand:SI 2 "u_short_cint_operand" "i")))
11219 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11220 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11221 ""
11222 "#"
11223 [(set_attr "length" "8")])
11225 (define_split
11226 [(set (match_operand:CC 3 "cc_reg_operand" "")
11227 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11228 (match_operand:SI 2 "short_cint_operand" "")))
11229 (set (match_operand:SI 0 "gpc_reg_operand" "")
11230 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11231 ""
11232 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11233 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11235 (define_split
11236 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11237 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11238 (match_operand:SI 2 "u_short_cint_operand" "")))
11239 (set (match_operand:SI 0 "gpc_reg_operand" "")
11240 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11241 ""
11242 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11243 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11245 (define_insn "*cmpsf_internal1"
11246 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11247 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11248 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11249 "TARGET_HARD_FLOAT && TARGET_FPRS"
11250 "fcmpu %0,%1,%2"
11251 [(set_attr "type" "fpcompare")])
11253 (define_insn "*cmpdf_internal1"
11254 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11255 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11256 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11257 "TARGET_HARD_FLOAT && TARGET_FPRS"
11258 "fcmpu %0,%1,%2"
11259 [(set_attr "type" "fpcompare")])
11261 ;; Only need to compare second words if first words equal
11262 (define_insn "*cmptf_internal1"
11263 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11264 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11265 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11266 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11267 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11268 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11269 [(set_attr "type" "fpcompare")
11270 (set_attr "length" "12")])
11271 \f
11272 ;; Now we have the scc insns. We can do some combinations because of the
11273 ;; way the machine works.
11274 ;;
11275 ;; Note that this is probably faster if we can put an insn between the
11276 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11277 ;; cases the insns below which don't use an intermediate CR field will
11278 ;; be used instead.
11279 (define_insn ""
11280 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11281 (match_operator:SI 1 "scc_comparison_operator"
11282 [(match_operand 2 "cc_reg_operand" "y")
11283 (const_int 0)]))]
11284 ""
11285 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11286 [(set (attr "type")
11287 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11288 (const_string "mfcrf")
11289 ]
11290 (const_string "mfcr")))
11291 (set_attr "length" "12")])
11293 ;; Same as above, but get the OV/ORDERED bit.
11294 (define_insn "move_from_CR_ov_bit"
11295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11296 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11297 "TARGET_ISEL"
11298 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11299 [(set_attr "type" "mfcr")
11300 (set_attr "length" "12")])
11302 (define_insn ""
11303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11304 (match_operator:DI 1 "scc_comparison_operator"
11305 [(match_operand 2 "cc_reg_operand" "y")
11306 (const_int 0)]))]
11307 "TARGET_POWERPC64"
11308 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11309 [(set (attr "type")
11310 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11311 (const_string "mfcrf")
11312 ]
11313 (const_string "mfcr")))
11314 (set_attr "length" "12")])
11316 (define_insn ""
11317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11318 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11319 [(match_operand 2 "cc_reg_operand" "y,y")
11320 (const_int 0)])
11321 (const_int 0)))
11322 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11323 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11324 "TARGET_32BIT"
11325 "@
11326 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11327 #"
11328 [(set_attr "type" "delayed_compare")
11329 (set_attr "length" "12,16")])
11331 (define_split
11332 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11333 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11334 [(match_operand 2 "cc_reg_operand" "")
11335 (const_int 0)])
11336 (const_int 0)))
11337 (set (match_operand:SI 3 "gpc_reg_operand" "")
11338 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11339 "TARGET_32BIT && reload_completed"
11340 [(set (match_dup 3)
11341 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11342 (set (match_dup 0)
11343 (compare:CC (match_dup 3)
11344 (const_int 0)))]
11345 "")
11347 (define_insn ""
11348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11349 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11350 [(match_operand 2 "cc_reg_operand" "y")
11351 (const_int 0)])
11352 (match_operand:SI 3 "const_int_operand" "n")))]
11353 ""
11354 "*
11355 {
11356 int is_bit = ccr_bit (operands[1], 1);
11357 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11358 int count;
11360 if (is_bit >= put_bit)
11361 count = is_bit - put_bit;
11362 else
11363 count = 32 - (put_bit - is_bit);
11365 operands[4] = GEN_INT (count);
11366 operands[5] = GEN_INT (put_bit);
11368 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11369 }"
11370 [(set (attr "type")
11371 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11372 (const_string "mfcrf")
11373 ]
11374 (const_string "mfcr")))
11375 (set_attr "length" "12")])
11377 (define_insn ""
11378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11379 (compare:CC
11380 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11381 [(match_operand 2 "cc_reg_operand" "y,y")
11382 (const_int 0)])
11383 (match_operand:SI 3 "const_int_operand" "n,n"))
11384 (const_int 0)))
11385 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11386 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11387 (match_dup 3)))]
11388 ""
11389 "*
11390 {
11391 int is_bit = ccr_bit (operands[1], 1);
11392 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11393 int count;
11395 /* Force split for non-cc0 compare. */
11396 if (which_alternative == 1)
11397 return \"#\";
11399 if (is_bit >= put_bit)
11400 count = is_bit - put_bit;
11401 else
11402 count = 32 - (put_bit - is_bit);
11404 operands[5] = GEN_INT (count);
11405 operands[6] = GEN_INT (put_bit);
11407 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11408 }"
11409 [(set_attr "type" "delayed_compare")
11410 (set_attr "length" "12,16")])
11412 (define_split
11413 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11414 (compare:CC
11415 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11416 [(match_operand 2 "cc_reg_operand" "")
11417 (const_int 0)])
11418 (match_operand:SI 3 "const_int_operand" ""))
11419 (const_int 0)))
11420 (set (match_operand:SI 4 "gpc_reg_operand" "")
11421 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11422 (match_dup 3)))]
11423 "reload_completed"
11424 [(set (match_dup 4)
11425 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11426 (match_dup 3)))
11427 (set (match_dup 0)
11428 (compare:CC (match_dup 4)
11429 (const_int 0)))]
11430 "")
11432 ;; There is a 3 cycle delay between consecutive mfcr instructions
11433 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11435 (define_peephole
11436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11437 (match_operator:SI 1 "scc_comparison_operator"
11438 [(match_operand 2 "cc_reg_operand" "y")
11439 (const_int 0)]))
11440 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11441 (match_operator:SI 4 "scc_comparison_operator"
11442 [(match_operand 5 "cc_reg_operand" "y")
11443 (const_int 0)]))]
11444 "REGNO (operands[2]) != REGNO (operands[5])"
11445 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11446 [(set_attr "type" "mfcr")
11447 (set_attr "length" "20")])
11449 (define_peephole
11450 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11451 (match_operator:DI 1 "scc_comparison_operator"
11452 [(match_operand 2 "cc_reg_operand" "y")
11453 (const_int 0)]))
11454 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11455 (match_operator:DI 4 "scc_comparison_operator"
11456 [(match_operand 5 "cc_reg_operand" "y")
11457 (const_int 0)]))]
11458 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11459 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11460 [(set_attr "type" "mfcr")
11461 (set_attr "length" "20")])
11463 ;; There are some scc insns that can be done directly, without a compare.
11464 ;; These are faster because they don't involve the communications between
11465 ;; the FXU and branch units. In fact, we will be replacing all of the
11466 ;; integer scc insns here or in the portable methods in emit_store_flag.
11467 ;;
11468 ;; Also support (neg (scc ..)) since that construct is used to replace
11469 ;; branches, (plus (scc ..) ..) since that construct is common and
11470 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11471 ;; cases where it is no more expensive than (neg (scc ..)).
11473 ;; Have reload force a constant into a register for the simple insns that
11474 ;; otherwise won't accept constants. We do this because it is faster than
11475 ;; the cmp/mfcr sequence we would otherwise generate.
11477 (define_insn ""
11478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11479 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11480 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11481 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11482 "TARGET_32BIT"
11483 "@
11484 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11485 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11486 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11487 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11488 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11489 [(set_attr "length" "12,8,12,12,12")])
11491 (define_insn ""
11492 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11493 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11494 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11495 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11496 "TARGET_64BIT"
11497 "@
11498 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11499 subfic %3,%1,0\;adde %0,%3,%1
11500 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11501 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11502 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11503 [(set_attr "length" "12,8,12,12,12")])
11505 (define_insn ""
11506 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11507 (compare:CC
11508 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11509 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11510 (const_int 0)))
11511 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11512 (eq:SI (match_dup 1) (match_dup 2)))
11513 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11514 "TARGET_32BIT"
11515 "@
11516 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11517 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11518 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11519 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11520 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11521 #
11522 #
11523 #
11524 #
11525 #"
11526 [(set_attr "type" "compare")
11527 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11529 (define_split
11530 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11531 (compare:CC
11532 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11533 (match_operand:SI 2 "reg_or_cint_operand" ""))
11534 (const_int 0)))
11535 (set (match_operand:SI 0 "gpc_reg_operand" "")
11536 (eq:SI (match_dup 1) (match_dup 2)))
11537 (clobber (match_scratch:SI 3 ""))]
11538 "TARGET_32BIT && reload_completed"
11539 [(parallel [(set (match_dup 0)
11540 (eq:SI (match_dup 1) (match_dup 2)))
11541 (clobber (match_dup 3))])
11542 (set (match_dup 4)
11543 (compare:CC (match_dup 0)
11544 (const_int 0)))]
11545 "")
11547 (define_insn ""
11548 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11549 (compare:CC
11550 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11551 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11552 (const_int 0)))
11553 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11554 (eq:DI (match_dup 1) (match_dup 2)))
11555 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11556 "TARGET_64BIT"
11557 "@
11558 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11559 subfic %3,%1,0\;adde. %0,%3,%1
11560 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11561 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11562 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11563 #
11564 #
11565 #
11566 #
11567 #"
11568 [(set_attr "type" "compare")
11569 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11571 (define_split
11572 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11573 (compare:CC
11574 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11575 (match_operand:DI 2 "reg_or_cint_operand" ""))
11576 (const_int 0)))
11577 (set (match_operand:DI 0 "gpc_reg_operand" "")
11578 (eq:DI (match_dup 1) (match_dup 2)))
11579 (clobber (match_scratch:DI 3 ""))]
11580 "TARGET_64BIT && reload_completed"
11581 [(parallel [(set (match_dup 0)
11582 (eq:DI (match_dup 1) (match_dup 2)))
11583 (clobber (match_dup 3))])
11584 (set (match_dup 4)
11585 (compare:CC (match_dup 0)
11586 (const_int 0)))]
11587 "")
11589 ;; We have insns of the form shown by the first define_insn below. If
11590 ;; there is something inside the comparison operation, we must split it.
11591 (define_split
11592 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11593 (plus:SI (match_operator 1 "comparison_operator"
11594 [(match_operand:SI 2 "" "")
11595 (match_operand:SI 3
11596 "reg_or_cint_operand" "")])
11597 (match_operand:SI 4 "gpc_reg_operand" "")))
11598 (clobber (match_operand:SI 5 "register_operand" ""))]
11599 "! gpc_reg_operand (operands[2], SImode)"
11600 [(set (match_dup 5) (match_dup 2))
11601 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11602 (match_dup 4)))])
11604 (define_insn ""
11605 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11606 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11607 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11608 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11609 "TARGET_32BIT"
11610 "@
11611 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11612 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11613 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11614 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11615 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11616 [(set_attr "length" "12,8,12,12,12")])
11618 (define_insn ""
11619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11620 (compare:CC
11621 (plus:SI
11622 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11623 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11624 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11625 (const_int 0)))
11626 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11627 "TARGET_32BIT"
11628 "@
11629 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11630 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11631 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11632 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11633 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11634 #
11635 #
11636 #
11637 #
11638 #"
11639 [(set_attr "type" "compare")
11640 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11642 (define_split
11643 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11644 (compare:CC
11645 (plus:SI
11646 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11647 (match_operand:SI 2 "reg_or_cint_operand" ""))
11648 (match_operand:SI 3 "gpc_reg_operand" ""))
11649 (const_int 0)))
11650 (clobber (match_scratch:SI 4 ""))]
11651 "TARGET_32BIT && reload_completed"
11652 [(set (match_dup 4)
11653 (plus:SI (eq:SI (match_dup 1)
11654 (match_dup 2))
11655 (match_dup 3)))
11656 (set (match_dup 0)
11657 (compare:CC (match_dup 4)
11658 (const_int 0)))]
11659 "")
11661 (define_insn ""
11662 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11663 (compare:CC
11664 (plus:SI
11665 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11666 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11667 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11668 (const_int 0)))
11669 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11670 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11671 "TARGET_32BIT"
11672 "@
11673 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11674 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11675 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11676 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11677 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11678 #
11679 #
11680 #
11681 #
11682 #"
11683 [(set_attr "type" "compare")
11684 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11686 (define_split
11687 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11688 (compare:CC
11689 (plus:SI
11690 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11691 (match_operand:SI 2 "reg_or_cint_operand" ""))
11692 (match_operand:SI 3 "gpc_reg_operand" ""))
11693 (const_int 0)))
11694 (set (match_operand:SI 0 "gpc_reg_operand" "")
11695 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11696 "TARGET_32BIT && reload_completed"
11697 [(set (match_dup 0)
11698 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11699 (set (match_dup 4)
11700 (compare:CC (match_dup 0)
11701 (const_int 0)))]
11702 "")
11704 (define_insn ""
11705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11706 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11707 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11708 "TARGET_32BIT"
11709 "@
11710 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11711 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11712 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11713 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11714 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11715 [(set_attr "length" "12,8,12,12,12")])
11717 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11718 ;; since it nabs/sr is just as fast.
11719 (define_insn "*ne0"
11720 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11721 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11722 (const_int 31)))
11723 (clobber (match_scratch:SI 2 "=&r"))]
11724 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11725 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11726 [(set_attr "length" "8")])
11728 (define_insn ""
11729 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11730 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11731 (const_int 63)))
11732 (clobber (match_scratch:DI 2 "=&r"))]
11733 "TARGET_64BIT"
11734 "addic %2,%1,-1\;subfe %0,%2,%1"
11735 [(set_attr "length" "8")])
11737 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11738 (define_insn ""
11739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11740 (plus:SI (lshiftrt:SI
11741 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11742 (const_int 31))
11743 (match_operand:SI 2 "gpc_reg_operand" "r")))
11744 (clobber (match_scratch:SI 3 "=&r"))]
11745 "TARGET_32BIT"
11746 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11747 [(set_attr "length" "8")])
11749 (define_insn ""
11750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11751 (plus:DI (lshiftrt:DI
11752 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11753 (const_int 63))
11754 (match_operand:DI 2 "gpc_reg_operand" "r")))
11755 (clobber (match_scratch:DI 3 "=&r"))]
11756 "TARGET_64BIT"
11757 "addic %3,%1,-1\;addze %0,%2"
11758 [(set_attr "length" "8")])
11760 (define_insn ""
11761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11762 (compare:CC
11763 (plus:SI (lshiftrt:SI
11764 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11765 (const_int 31))
11766 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11767 (const_int 0)))
11768 (clobber (match_scratch:SI 3 "=&r,&r"))
11769 (clobber (match_scratch:SI 4 "=X,&r"))]
11770 "TARGET_32BIT"
11771 "@
11772 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11773 #"
11774 [(set_attr "type" "compare")
11775 (set_attr "length" "8,12")])
11777 (define_split
11778 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11779 (compare:CC
11780 (plus:SI (lshiftrt:SI
11781 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11782 (const_int 31))
11783 (match_operand:SI 2 "gpc_reg_operand" ""))
11784 (const_int 0)))
11785 (clobber (match_scratch:SI 3 ""))
11786 (clobber (match_scratch:SI 4 ""))]
11787 "TARGET_32BIT && reload_completed"
11788 [(parallel [(set (match_dup 3)
11789 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11790 (const_int 31))
11791 (match_dup 2)))
11792 (clobber (match_dup 4))])
11793 (set (match_dup 0)
11794 (compare:CC (match_dup 3)
11795 (const_int 0)))]
11796 "")
11798 (define_insn ""
11799 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11800 (compare:CC
11801 (plus:DI (lshiftrt:DI
11802 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11803 (const_int 63))
11804 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11805 (const_int 0)))
11806 (clobber (match_scratch:DI 3 "=&r,&r"))]
11807 "TARGET_64BIT"
11808 "@
11809 addic %3,%1,-1\;addze. %3,%2
11810 #"
11811 [(set_attr "type" "compare")
11812 (set_attr "length" "8,12")])
11814 (define_split
11815 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11816 (compare:CC
11817 (plus:DI (lshiftrt:DI
11818 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11819 (const_int 63))
11820 (match_operand:DI 2 "gpc_reg_operand" ""))
11821 (const_int 0)))
11822 (clobber (match_scratch:DI 3 ""))]
11823 "TARGET_64BIT && reload_completed"
11824 [(set (match_dup 3)
11825 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11826 (const_int 63))
11827 (match_dup 2)))
11828 (set (match_dup 0)
11829 (compare:CC (match_dup 3)
11830 (const_int 0)))]
11831 "")
11833 (define_insn ""
11834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11835 (compare:CC
11836 (plus:SI (lshiftrt:SI
11837 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11838 (const_int 31))
11839 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11840 (const_int 0)))
11841 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11842 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11843 (match_dup 2)))
11844 (clobber (match_scratch:SI 3 "=&r,&r"))]
11845 "TARGET_32BIT"
11846 "@
11847 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11848 #"
11849 [(set_attr "type" "compare")
11850 (set_attr "length" "8,12")])
11852 (define_split
11853 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11854 (compare:CC
11855 (plus:SI (lshiftrt:SI
11856 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11857 (const_int 31))
11858 (match_operand:SI 2 "gpc_reg_operand" ""))
11859 (const_int 0)))
11860 (set (match_operand:SI 0 "gpc_reg_operand" "")
11861 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11862 (match_dup 2)))
11863 (clobber (match_scratch:SI 3 ""))]
11864 "TARGET_32BIT && reload_completed"
11865 [(parallel [(set (match_dup 0)
11866 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11867 (match_dup 2)))
11868 (clobber (match_dup 3))])
11869 (set (match_dup 4)
11870 (compare:CC (match_dup 0)
11871 (const_int 0)))]
11872 "")
11874 (define_insn ""
11875 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11876 (compare:CC
11877 (plus:DI (lshiftrt:DI
11878 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11879 (const_int 63))
11880 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11881 (const_int 0)))
11882 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11883 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11884 (match_dup 2)))
11885 (clobber (match_scratch:DI 3 "=&r,&r"))]
11886 "TARGET_64BIT"
11887 "@
11888 addic %3,%1,-1\;addze. %0,%2
11889 #"
11890 [(set_attr "type" "compare")
11891 (set_attr "length" "8,12")])
11893 (define_split
11894 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11895 (compare:CC
11896 (plus:DI (lshiftrt:DI
11897 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11898 (const_int 63))
11899 (match_operand:DI 2 "gpc_reg_operand" ""))
11900 (const_int 0)))
11901 (set (match_operand:DI 0 "gpc_reg_operand" "")
11902 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11903 (match_dup 2)))
11904 (clobber (match_scratch:DI 3 ""))]
11905 "TARGET_64BIT && reload_completed"
11906 [(parallel [(set (match_dup 0)
11907 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11908 (match_dup 2)))
11909 (clobber (match_dup 3))])
11910 (set (match_dup 4)
11911 (compare:CC (match_dup 0)
11912 (const_int 0)))]
11913 "")
11915 (define_insn ""
11916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11917 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11918 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11919 (clobber (match_scratch:SI 3 "=r,X"))]
11920 "TARGET_POWER"
11921 "@
11922 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11923 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11924 [(set_attr "length" "12")])
11926 (define_insn ""
11927 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11928 (compare:CC
11929 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11930 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11931 (const_int 0)))
11932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11933 (le:SI (match_dup 1) (match_dup 2)))
11934 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11935 "TARGET_POWER"
11936 "@
11937 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11938 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11939 #
11940 #"
11941 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11942 (set_attr "length" "12,12,16,16")])
11944 (define_split
11945 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11946 (compare:CC
11947 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11948 (match_operand:SI 2 "reg_or_short_operand" ""))
11949 (const_int 0)))
11950 (set (match_operand:SI 0 "gpc_reg_operand" "")
11951 (le:SI (match_dup 1) (match_dup 2)))
11952 (clobber (match_scratch:SI 3 ""))]
11953 "TARGET_POWER && reload_completed"
11954 [(parallel [(set (match_dup 0)
11955 (le:SI (match_dup 1) (match_dup 2)))
11956 (clobber (match_dup 3))])
11957 (set (match_dup 4)
11958 (compare:CC (match_dup 0)
11959 (const_int 0)))]
11960 "")
11962 (define_insn ""
11963 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11964 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11965 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11966 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11967 "TARGET_POWER"
11968 "@
11969 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11970 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11971 [(set_attr "length" "12")])
11973 (define_insn ""
11974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11975 (compare:CC
11976 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11977 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11978 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11979 (const_int 0)))
11980 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11981 "TARGET_POWER"
11982 "@
11983 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11984 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11985 #
11986 #"
11987 [(set_attr "type" "compare")
11988 (set_attr "length" "12,12,16,16")])
11990 (define_split
11991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11992 (compare:CC
11993 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11994 (match_operand:SI 2 "reg_or_short_operand" ""))
11995 (match_operand:SI 3 "gpc_reg_operand" ""))
11996 (const_int 0)))
11997 (clobber (match_scratch:SI 4 ""))]
11998 "TARGET_POWER && reload_completed"
11999 [(set (match_dup 4)
12000 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12001 (match_dup 3)))
12002 (set (match_dup 0)
12003 (compare:CC (match_dup 4)
12004 (const_int 0)))]
12005 "")
12007 (define_insn ""
12008 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12009 (compare:CC
12010 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12011 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12012 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12013 (const_int 0)))
12014 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12015 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12016 "TARGET_POWER"
12017 "@
12018 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12019 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12020 #
12021 #"
12022 [(set_attr "type" "compare")
12023 (set_attr "length" "12,12,16,16")])
12025 (define_split
12026 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12027 (compare:CC
12028 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12029 (match_operand:SI 2 "reg_or_short_operand" ""))
12030 (match_operand:SI 3 "gpc_reg_operand" ""))
12031 (const_int 0)))
12032 (set (match_operand:SI 0 "gpc_reg_operand" "")
12033 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12034 "TARGET_POWER && reload_completed"
12035 [(set (match_dup 0)
12036 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12037 (set (match_dup 4)
12038 (compare:CC (match_dup 0)
12039 (const_int 0)))]
12040 "")
12042 (define_insn ""
12043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12044 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12045 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12046 "TARGET_POWER"
12047 "@
12048 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12049 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12050 [(set_attr "length" "12")])
12052 (define_insn ""
12053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12054 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12055 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12056 "TARGET_32BIT"
12057 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12058 [(set_attr "length" "12")])
12060 (define_insn ""
12061 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12062 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12063 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12064 "TARGET_64BIT"
12065 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12066 [(set_attr "length" "12")])
12068 (define_insn ""
12069 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12070 (compare:CC
12071 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12072 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12073 (const_int 0)))
12074 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12075 (leu:DI (match_dup 1) (match_dup 2)))]
12076 "TARGET_64BIT"
12077 "@
12078 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12079 #"
12080 [(set_attr "type" "compare")
12081 (set_attr "length" "12,16")])
12083 (define_split
12084 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12085 (compare:CC
12086 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12087 (match_operand:DI 2 "reg_or_short_operand" ""))
12088 (const_int 0)))
12089 (set (match_operand:DI 0 "gpc_reg_operand" "")
12090 (leu:DI (match_dup 1) (match_dup 2)))]
12091 "TARGET_64BIT && reload_completed"
12092 [(set (match_dup 0)
12093 (leu:DI (match_dup 1) (match_dup 2)))
12094 (set (match_dup 3)
12095 (compare:CC (match_dup 0)
12096 (const_int 0)))]
12097 "")
12099 (define_insn ""
12100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12101 (compare:CC
12102 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12103 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12104 (const_int 0)))
12105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12106 (leu:SI (match_dup 1) (match_dup 2)))]
12107 "TARGET_32BIT"
12108 "@
12109 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12110 #"
12111 [(set_attr "type" "compare")
12112 (set_attr "length" "12,16")])
12114 (define_split
12115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12116 (compare:CC
12117 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12118 (match_operand:SI 2 "reg_or_short_operand" ""))
12119 (const_int 0)))
12120 (set (match_operand:SI 0 "gpc_reg_operand" "")
12121 (leu:SI (match_dup 1) (match_dup 2)))]
12122 "TARGET_32BIT && reload_completed"
12123 [(set (match_dup 0)
12124 (leu:SI (match_dup 1) (match_dup 2)))
12125 (set (match_dup 3)
12126 (compare:CC (match_dup 0)
12127 (const_int 0)))]
12128 "")
12130 (define_insn ""
12131 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12132 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12133 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12134 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12135 "TARGET_32BIT"
12136 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12137 [(set_attr "length" "8")])
12139 (define_insn ""
12140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12141 (compare:CC
12142 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12143 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12144 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12145 (const_int 0)))
12146 (clobber (match_scratch:SI 4 "=&r,&r"))]
12147 "TARGET_32BIT"
12148 "@
12149 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12150 #"
12151 [(set_attr "type" "compare")
12152 (set_attr "length" "8,12")])
12154 (define_split
12155 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12156 (compare:CC
12157 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12158 (match_operand:SI 2 "reg_or_short_operand" ""))
12159 (match_operand:SI 3 "gpc_reg_operand" ""))
12160 (const_int 0)))
12161 (clobber (match_scratch:SI 4 ""))]
12162 "TARGET_32BIT && reload_completed"
12163 [(set (match_dup 4)
12164 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12165 (match_dup 3)))
12166 (set (match_dup 0)
12167 (compare:CC (match_dup 4)
12168 (const_int 0)))]
12169 "")
12171 (define_insn ""
12172 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12173 (compare:CC
12174 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12175 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12176 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12177 (const_int 0)))
12178 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12179 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12180 "TARGET_32BIT"
12181 "@
12182 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12183 #"
12184 [(set_attr "type" "compare")
12185 (set_attr "length" "8,12")])
12187 (define_split
12188 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12189 (compare:CC
12190 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12191 (match_operand:SI 2 "reg_or_short_operand" ""))
12192 (match_operand:SI 3 "gpc_reg_operand" ""))
12193 (const_int 0)))
12194 (set (match_operand:SI 0 "gpc_reg_operand" "")
12195 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12196 "TARGET_32BIT && reload_completed"
12197 [(set (match_dup 0)
12198 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12199 (set (match_dup 4)
12200 (compare:CC (match_dup 0)
12201 (const_int 0)))]
12202 "")
12204 (define_insn ""
12205 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12206 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12207 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12208 "TARGET_32BIT"
12209 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12210 [(set_attr "length" "12")])
12212 (define_insn ""
12213 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12214 (and:SI (neg:SI
12215 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12216 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12217 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12218 "TARGET_32BIT"
12219 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12220 [(set_attr "length" "12")])
12222 (define_insn ""
12223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12224 (compare:CC
12225 (and:SI (neg:SI
12226 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12227 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12228 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12229 (const_int 0)))
12230 (clobber (match_scratch:SI 4 "=&r,&r"))]
12231 "TARGET_32BIT"
12232 "@
12233 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12234 #"
12235 [(set_attr "type" "compare")
12236 (set_attr "length" "12,16")])
12238 (define_split
12239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12240 (compare:CC
12241 (and:SI (neg:SI
12242 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12243 (match_operand:SI 2 "reg_or_short_operand" "")))
12244 (match_operand:SI 3 "gpc_reg_operand" ""))
12245 (const_int 0)))
12246 (clobber (match_scratch:SI 4 ""))]
12247 "TARGET_32BIT && reload_completed"
12248 [(set (match_dup 4)
12249 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12250 (match_dup 3)))
12251 (set (match_dup 0)
12252 (compare:CC (match_dup 4)
12253 (const_int 0)))]
12254 "")
12256 (define_insn ""
12257 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12258 (compare:CC
12259 (and:SI (neg:SI
12260 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12261 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12262 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12263 (const_int 0)))
12264 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12265 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12266 "TARGET_32BIT"
12267 "@
12268 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12269 #"
12270 [(set_attr "type" "compare")
12271 (set_attr "length" "12,16")])
12273 (define_split
12274 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12275 (compare:CC
12276 (and:SI (neg:SI
12277 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12278 (match_operand:SI 2 "reg_or_short_operand" "")))
12279 (match_operand:SI 3 "gpc_reg_operand" ""))
12280 (const_int 0)))
12281 (set (match_operand:SI 0 "gpc_reg_operand" "")
12282 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12283 "TARGET_32BIT && reload_completed"
12284 [(set (match_dup 0)
12285 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12286 (match_dup 3)))
12287 (set (match_dup 4)
12288 (compare:CC (match_dup 0)
12289 (const_int 0)))]
12290 "")
12292 (define_insn ""
12293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12294 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12295 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12296 "TARGET_POWER"
12297 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12298 [(set_attr "length" "12")])
12300 (define_insn ""
12301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12302 (compare:CC
12303 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12304 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12305 (const_int 0)))
12306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12307 (lt:SI (match_dup 1) (match_dup 2)))]
12308 "TARGET_POWER"
12309 "@
12310 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12311 #"
12312 [(set_attr "type" "delayed_compare")
12313 (set_attr "length" "12,16")])
12315 (define_split
12316 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12317 (compare:CC
12318 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12319 (match_operand:SI 2 "reg_or_short_operand" ""))
12320 (const_int 0)))
12321 (set (match_operand:SI 0 "gpc_reg_operand" "")
12322 (lt:SI (match_dup 1) (match_dup 2)))]
12323 "TARGET_POWER && reload_completed"
12324 [(set (match_dup 0)
12325 (lt:SI (match_dup 1) (match_dup 2)))
12326 (set (match_dup 3)
12327 (compare:CC (match_dup 0)
12328 (const_int 0)))]
12329 "")
12331 (define_insn ""
12332 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12333 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12334 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12335 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12336 "TARGET_POWER"
12337 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12338 [(set_attr "length" "12")])
12340 (define_insn ""
12341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12342 (compare:CC
12343 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12344 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12345 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12346 (const_int 0)))
12347 (clobber (match_scratch:SI 4 "=&r,&r"))]
12348 "TARGET_POWER"
12349 "@
12350 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12351 #"
12352 [(set_attr "type" "compare")
12353 (set_attr "length" "12,16")])
12355 (define_split
12356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12357 (compare:CC
12358 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12359 (match_operand:SI 2 "reg_or_short_operand" ""))
12360 (match_operand:SI 3 "gpc_reg_operand" ""))
12361 (const_int 0)))
12362 (clobber (match_scratch:SI 4 ""))]
12363 "TARGET_POWER && reload_completed"
12364 [(set (match_dup 4)
12365 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12366 (match_dup 3)))
12367 (set (match_dup 0)
12368 (compare:CC (match_dup 4)
12369 (const_int 0)))]
12370 "")
12372 (define_insn ""
12373 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12374 (compare:CC
12375 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12376 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12377 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12378 (const_int 0)))
12379 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12380 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12381 "TARGET_POWER"
12382 "@
12383 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12384 #"
12385 [(set_attr "type" "compare")
12386 (set_attr "length" "12,16")])
12388 (define_split
12389 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12390 (compare:CC
12391 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12392 (match_operand:SI 2 "reg_or_short_operand" ""))
12393 (match_operand:SI 3 "gpc_reg_operand" ""))
12394 (const_int 0)))
12395 (set (match_operand:SI 0 "gpc_reg_operand" "")
12396 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12397 "TARGET_POWER && reload_completed"
12398 [(set (match_dup 0)
12399 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12400 (set (match_dup 4)
12401 (compare:CC (match_dup 0)
12402 (const_int 0)))]
12403 "")
12405 (define_insn ""
12406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12407 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12408 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12409 "TARGET_POWER"
12410 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12411 [(set_attr "length" "12")])
12413 (define_insn ""
12414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12415 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12416 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12417 "TARGET_32BIT"
12418 "@
12419 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12420 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12421 [(set_attr "length" "12")])
12423 (define_insn ""
12424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12425 (compare:CC
12426 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12427 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12428 (const_int 0)))
12429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12430 (ltu:SI (match_dup 1) (match_dup 2)))]
12431 "TARGET_32BIT"
12432 "@
12433 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12434 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12435 #
12436 #"
12437 [(set_attr "type" "compare")
12438 (set_attr "length" "12,12,16,16")])
12440 (define_split
12441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12442 (compare:CC
12443 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12444 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12445 (const_int 0)))
12446 (set (match_operand:SI 0 "gpc_reg_operand" "")
12447 (ltu:SI (match_dup 1) (match_dup 2)))]
12448 "TARGET_32BIT && reload_completed"
12449 [(set (match_dup 0)
12450 (ltu:SI (match_dup 1) (match_dup 2)))
12451 (set (match_dup 3)
12452 (compare:CC (match_dup 0)
12453 (const_int 0)))]
12454 "")
12456 (define_insn ""
12457 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12458 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12459 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12460 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12461 "TARGET_32BIT"
12462 "@
12463 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12464 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12465 [(set_attr "length" "12")])
12467 (define_insn ""
12468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12469 (compare:CC
12470 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12471 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12472 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12473 (const_int 0)))
12474 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12475 "TARGET_32BIT"
12476 "@
12477 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12478 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12479 #
12480 #"
12481 [(set_attr "type" "compare")
12482 (set_attr "length" "12,12,16,16")])
12484 (define_split
12485 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12486 (compare:CC
12487 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12488 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12489 (match_operand:SI 3 "gpc_reg_operand" ""))
12490 (const_int 0)))
12491 (clobber (match_scratch:SI 4 ""))]
12492 "TARGET_32BIT && reload_completed"
12493 [(set (match_dup 4)
12494 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12495 (match_dup 3)))
12496 (set (match_dup 0)
12497 (compare:CC (match_dup 4)
12498 (const_int 0)))]
12499 "")
12501 (define_insn ""
12502 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12503 (compare:CC
12504 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12505 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12506 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12507 (const_int 0)))
12508 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12509 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12510 "TARGET_32BIT"
12511 "@
12512 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12513 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12514 #
12515 #"
12516 [(set_attr "type" "compare")
12517 (set_attr "length" "12,12,16,16")])
12519 (define_split
12520 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12521 (compare:CC
12522 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12523 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12524 (match_operand:SI 3 "gpc_reg_operand" ""))
12525 (const_int 0)))
12526 (set (match_operand:SI 0 "gpc_reg_operand" "")
12527 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12528 "TARGET_32BIT && reload_completed"
12529 [(set (match_dup 0)
12530 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12531 (set (match_dup 4)
12532 (compare:CC (match_dup 0)
12533 (const_int 0)))]
12534 "")
12536 (define_insn ""
12537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12538 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12539 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12540 "TARGET_32BIT"
12541 "@
12542 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12543 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12544 [(set_attr "length" "8")])
12546 (define_insn ""
12547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12548 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12549 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12550 (clobber (match_scratch:SI 3 "=r"))]
12551 "TARGET_POWER"
12552 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12553 [(set_attr "length" "12")])
12555 (define_insn ""
12556 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12557 (compare:CC
12558 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12559 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12560 (const_int 0)))
12561 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12562 (ge:SI (match_dup 1) (match_dup 2)))
12563 (clobber (match_scratch:SI 3 "=r,r"))]
12564 "TARGET_POWER"
12565 "@
12566 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12567 #"
12568 [(set_attr "type" "compare")
12569 (set_attr "length" "12,16")])
12571 (define_split
12572 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12573 (compare:CC
12574 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12575 (match_operand:SI 2 "reg_or_short_operand" ""))
12576 (const_int 0)))
12577 (set (match_operand:SI 0 "gpc_reg_operand" "")
12578 (ge:SI (match_dup 1) (match_dup 2)))
12579 (clobber (match_scratch:SI 3 ""))]
12580 "TARGET_POWER && reload_completed"
12581 [(parallel [(set (match_dup 0)
12582 (ge:SI (match_dup 1) (match_dup 2)))
12583 (clobber (match_dup 3))])
12584 (set (match_dup 4)
12585 (compare:CC (match_dup 0)
12586 (const_int 0)))]
12587 "")
12589 (define_insn ""
12590 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12591 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12592 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12593 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12594 "TARGET_POWER"
12595 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12596 [(set_attr "length" "12")])
12598 (define_insn ""
12599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12600 (compare:CC
12601 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12602 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12603 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12604 (const_int 0)))
12605 (clobber (match_scratch:SI 4 "=&r,&r"))]
12606 "TARGET_POWER"
12607 "@
12608 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12609 #"
12610 [(set_attr "type" "compare")
12611 (set_attr "length" "12,16")])
12613 (define_split
12614 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12615 (compare:CC
12616 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12617 (match_operand:SI 2 "reg_or_short_operand" ""))
12618 (match_operand:SI 3 "gpc_reg_operand" ""))
12619 (const_int 0)))
12620 (clobber (match_scratch:SI 4 ""))]
12621 "TARGET_POWER && reload_completed"
12622 [(set (match_dup 4)
12623 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12624 (match_dup 3)))
12625 (set (match_dup 0)
12626 (compare:CC (match_dup 4)
12627 (const_int 0)))]
12628 "")
12630 (define_insn ""
12631 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12632 (compare:CC
12633 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12634 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12635 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12636 (const_int 0)))
12637 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12638 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12639 "TARGET_POWER"
12640 "@
12641 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12642 #"
12643 [(set_attr "type" "compare")
12644 (set_attr "length" "12,16")])
12646 (define_split
12647 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12648 (compare:CC
12649 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12650 (match_operand:SI 2 "reg_or_short_operand" ""))
12651 (match_operand:SI 3 "gpc_reg_operand" ""))
12652 (const_int 0)))
12653 (set (match_operand:SI 0 "gpc_reg_operand" "")
12654 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12655 "TARGET_POWER && reload_completed"
12656 [(set (match_dup 0)
12657 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12658 (set (match_dup 4)
12659 (compare:CC (match_dup 0)
12660 (const_int 0)))]
12661 "")
12663 (define_insn ""
12664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12665 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12666 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12667 "TARGET_POWER"
12668 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12669 [(set_attr "length" "12")])
12671 (define_insn ""
12672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12673 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12674 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12675 "TARGET_32BIT"
12676 "@
12677 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12678 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12679 [(set_attr "length" "12")])
12681 (define_insn ""
12682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12683 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12684 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12685 "TARGET_64BIT"
12686 "@
12687 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12688 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12689 [(set_attr "length" "12")])
12691 (define_insn ""
12692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12693 (compare:CC
12694 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12695 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12696 (const_int 0)))
12697 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12698 (geu:SI (match_dup 1) (match_dup 2)))]
12699 "TARGET_32BIT"
12700 "@
12701 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12702 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12703 #
12704 #"
12705 [(set_attr "type" "compare")
12706 (set_attr "length" "12,12,16,16")])
12708 (define_split
12709 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12710 (compare:CC
12711 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12712 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12713 (const_int 0)))
12714 (set (match_operand:SI 0 "gpc_reg_operand" "")
12715 (geu:SI (match_dup 1) (match_dup 2)))]
12716 "TARGET_32BIT && reload_completed"
12717 [(set (match_dup 0)
12718 (geu:SI (match_dup 1) (match_dup 2)))
12719 (set (match_dup 3)
12720 (compare:CC (match_dup 0)
12721 (const_int 0)))]
12722 "")
12724 (define_insn ""
12725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12726 (compare:CC
12727 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12728 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12729 (const_int 0)))
12730 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12731 (geu:DI (match_dup 1) (match_dup 2)))]
12732 "TARGET_64BIT"
12733 "@
12734 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12735 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12736 #
12737 #"
12738 [(set_attr "type" "compare")
12739 (set_attr "length" "12,12,16,16")])
12741 (define_split
12742 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12743 (compare:CC
12744 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12745 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12746 (const_int 0)))
12747 (set (match_operand:DI 0 "gpc_reg_operand" "")
12748 (geu:DI (match_dup 1) (match_dup 2)))]
12749 "TARGET_64BIT && reload_completed"
12750 [(set (match_dup 0)
12751 (geu:DI (match_dup 1) (match_dup 2)))
12752 (set (match_dup 3)
12753 (compare:CC (match_dup 0)
12754 (const_int 0)))]
12755 "")
12757 (define_insn ""
12758 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12759 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12760 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12761 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12762 "TARGET_32BIT"
12763 "@
12764 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12765 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12766 [(set_attr "length" "8")])
12768 (define_insn ""
12769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12770 (compare:CC
12771 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12772 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12773 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12774 (const_int 0)))
12775 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12776 "TARGET_32BIT"
12777 "@
12778 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12779 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12780 #
12781 #"
12782 [(set_attr "type" "compare")
12783 (set_attr "length" "8,8,12,12")])
12785 (define_split
12786 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12787 (compare:CC
12788 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12789 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12790 (match_operand:SI 3 "gpc_reg_operand" ""))
12791 (const_int 0)))
12792 (clobber (match_scratch:SI 4 ""))]
12793 "TARGET_32BIT && reload_completed"
12794 [(set (match_dup 4)
12795 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12796 (match_dup 3)))
12797 (set (match_dup 0)
12798 (compare:CC (match_dup 4)
12799 (const_int 0)))]
12800 "")
12802 (define_insn ""
12803 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12804 (compare:CC
12805 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12806 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12807 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12808 (const_int 0)))
12809 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12810 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12811 "TARGET_32BIT"
12812 "@
12813 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12814 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12815 #
12816 #"
12817 [(set_attr "type" "compare")
12818 (set_attr "length" "8,8,12,12")])
12820 (define_split
12821 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12822 (compare:CC
12823 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12824 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12825 (match_operand:SI 3 "gpc_reg_operand" ""))
12826 (const_int 0)))
12827 (set (match_operand:SI 0 "gpc_reg_operand" "")
12828 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12829 "TARGET_32BIT && reload_completed"
12830 [(set (match_dup 0)
12831 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12832 (set (match_dup 4)
12833 (compare:CC (match_dup 0)
12834 (const_int 0)))]
12835 "")
12837 (define_insn ""
12838 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12839 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12840 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12841 "TARGET_32BIT"
12842 "@
12843 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12844 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12845 [(set_attr "length" "12")])
12847 (define_insn ""
12848 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12849 (and:SI (neg:SI
12850 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12851 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12852 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12853 "TARGET_32BIT"
12854 "@
12855 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12856 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12857 [(set_attr "length" "12")])
12859 (define_insn ""
12860 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12861 (compare:CC
12862 (and:SI (neg:SI
12863 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12864 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12865 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12866 (const_int 0)))
12867 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12868 "TARGET_32BIT"
12869 "@
12870 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12871 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12872 #
12873 #"
12874 [(set_attr "type" "compare")
12875 (set_attr "length" "12,12,16,16")])
12877 (define_split
12878 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12879 (compare:CC
12880 (and:SI (neg:SI
12881 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12882 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12883 (match_operand:SI 3 "gpc_reg_operand" ""))
12884 (const_int 0)))
12885 (clobber (match_scratch:SI 4 ""))]
12886 "TARGET_32BIT && reload_completed"
12887 [(set (match_dup 4)
12888 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12889 (match_dup 3)))
12890 (set (match_dup 0)
12891 (compare:CC (match_dup 4)
12892 (const_int 0)))]
12893 "")
12895 (define_insn ""
12896 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12897 (compare:CC
12898 (and:SI (neg:SI
12899 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12900 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12901 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12902 (const_int 0)))
12903 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12904 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12905 "TARGET_32BIT"
12906 "@
12907 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12908 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12909 #
12910 #"
12911 [(set_attr "type" "compare")
12912 (set_attr "length" "12,12,16,16")])
12914 (define_split
12915 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12916 (compare:CC
12917 (and:SI (neg:SI
12918 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12919 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12920 (match_operand:SI 3 "gpc_reg_operand" ""))
12921 (const_int 0)))
12922 (set (match_operand:SI 0 "gpc_reg_operand" "")
12923 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12924 "TARGET_32BIT && reload_completed"
12925 [(set (match_dup 0)
12926 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12927 (set (match_dup 4)
12928 (compare:CC (match_dup 0)
12929 (const_int 0)))]
12930 "")
12932 (define_insn ""
12933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12934 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12935 (const_int 0)))]
12936 "TARGET_32BIT"
12937 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12938 [(set_attr "length" "12")])
12940 (define_insn ""
12941 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12942 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12943 (const_int 0)))]
12944 "TARGET_64BIT"
12945 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12946 [(set_attr "length" "12")])
12948 (define_insn ""
12949 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12950 (compare:CC
12951 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12952 (const_int 0))
12953 (const_int 0)))
12954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12955 (gt:SI (match_dup 1) (const_int 0)))]
12956 "TARGET_32BIT"
12957 "@
12958 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12959 #"
12960 [(set_attr "type" "delayed_compare")
12961 (set_attr "length" "12,16")])
12963 (define_split
12964 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12965 (compare:CC
12966 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12967 (const_int 0))
12968 (const_int 0)))
12969 (set (match_operand:SI 0 "gpc_reg_operand" "")
12970 (gt:SI (match_dup 1) (const_int 0)))]
12971 "TARGET_32BIT && reload_completed"
12972 [(set (match_dup 0)
12973 (gt:SI (match_dup 1) (const_int 0)))
12974 (set (match_dup 2)
12975 (compare:CC (match_dup 0)
12976 (const_int 0)))]
12977 "")
12979 (define_insn ""
12980 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12981 (compare:CC
12982 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12983 (const_int 0))
12984 (const_int 0)))
12985 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12986 (gt:DI (match_dup 1) (const_int 0)))]
12987 "TARGET_64BIT"
12988 "@
12989 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12990 #"
12991 [(set_attr "type" "delayed_compare")
12992 (set_attr "length" "12,16")])
12994 (define_split
12995 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12996 (compare:CC
12997 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12998 (const_int 0))
12999 (const_int 0)))
13000 (set (match_operand:DI 0 "gpc_reg_operand" "")
13001 (gt:DI (match_dup 1) (const_int 0)))]
13002 "TARGET_64BIT && reload_completed"
13003 [(set (match_dup 0)
13004 (gt:DI (match_dup 1) (const_int 0)))
13005 (set (match_dup 2)
13006 (compare:CC (match_dup 0)
13007 (const_int 0)))]
13008 "")
13010 (define_insn ""
13011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13012 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13013 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13014 "TARGET_POWER"
13015 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13016 [(set_attr "length" "12")])
13018 (define_insn ""
13019 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13020 (compare:CC
13021 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13022 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13023 (const_int 0)))
13024 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13025 (gt:SI (match_dup 1) (match_dup 2)))]
13026 "TARGET_POWER"
13027 "@
13028 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13029 #"
13030 [(set_attr "type" "delayed_compare")
13031 (set_attr "length" "12,16")])
13033 (define_split
13034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13035 (compare:CC
13036 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13037 (match_operand:SI 2 "reg_or_short_operand" ""))
13038 (const_int 0)))
13039 (set (match_operand:SI 0 "gpc_reg_operand" "")
13040 (gt:SI (match_dup 1) (match_dup 2)))]
13041 "TARGET_POWER && reload_completed"
13042 [(set (match_dup 0)
13043 (gt:SI (match_dup 1) (match_dup 2)))
13044 (set (match_dup 3)
13045 (compare:CC (match_dup 0)
13046 (const_int 0)))]
13047 "")
13049 (define_insn ""
13050 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13051 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13052 (const_int 0))
13053 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13054 "TARGET_32BIT"
13055 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13056 [(set_attr "length" "12")])
13058 (define_insn ""
13059 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13060 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13061 (const_int 0))
13062 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13063 "TARGET_64BIT"
13064 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13065 [(set_attr "length" "12")])
13067 (define_insn ""
13068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13069 (compare:CC
13070 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13071 (const_int 0))
13072 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13073 (const_int 0)))
13074 (clobber (match_scratch:SI 3 "=&r,&r"))]
13075 "TARGET_32BIT"
13076 "@
13077 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13078 #"
13079 [(set_attr "type" "compare")
13080 (set_attr "length" "12,16")])
13082 (define_split
13083 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13084 (compare:CC
13085 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13086 (const_int 0))
13087 (match_operand:SI 2 "gpc_reg_operand" ""))
13088 (const_int 0)))
13089 (clobber (match_scratch:SI 3 ""))]
13090 "TARGET_32BIT && reload_completed"
13091 [(set (match_dup 3)
13092 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13093 (match_dup 2)))
13094 (set (match_dup 0)
13095 (compare:CC (match_dup 3)
13096 (const_int 0)))]
13097 "")
13099 (define_insn ""
13100 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13101 (compare:CC
13102 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13103 (const_int 0))
13104 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13105 (const_int 0)))
13106 (clobber (match_scratch:DI 3 "=&r,&r"))]
13107 "TARGET_64BIT"
13108 "@
13109 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13110 #"
13111 [(set_attr "type" "compare")
13112 (set_attr "length" "12,16")])
13114 (define_split
13115 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13116 (compare:CC
13117 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13118 (const_int 0))
13119 (match_operand:DI 2 "gpc_reg_operand" ""))
13120 (const_int 0)))
13121 (clobber (match_scratch:DI 3 ""))]
13122 "TARGET_64BIT && reload_completed"
13123 [(set (match_dup 3)
13124 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13125 (match_dup 2)))
13126 (set (match_dup 0)
13127 (compare:CC (match_dup 3)
13128 (const_int 0)))]
13129 "")
13131 (define_insn ""
13132 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13133 (compare:CC
13134 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13135 (const_int 0))
13136 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13137 (const_int 0)))
13138 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13139 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13140 "TARGET_32BIT"
13141 "@
13142 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13143 #"
13144 [(set_attr "type" "compare")
13145 (set_attr "length" "12,16")])
13147 (define_split
13148 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13149 (compare:CC
13150 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13151 (const_int 0))
13152 (match_operand:SI 2 "gpc_reg_operand" ""))
13153 (const_int 0)))
13154 (set (match_operand:SI 0 "gpc_reg_operand" "")
13155 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13156 "TARGET_32BIT && reload_completed"
13157 [(set (match_dup 0)
13158 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13159 (set (match_dup 3)
13160 (compare:CC (match_dup 0)
13161 (const_int 0)))]
13162 "")
13164 (define_insn ""
13165 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13166 (compare:CC
13167 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13168 (const_int 0))
13169 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13170 (const_int 0)))
13171 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13172 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13173 "TARGET_64BIT"
13174 "@
13175 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13176 #"
13177 [(set_attr "type" "compare")
13178 (set_attr "length" "12,16")])
13180 (define_split
13181 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13182 (compare:CC
13183 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13184 (const_int 0))
13185 (match_operand:DI 2 "gpc_reg_operand" ""))
13186 (const_int 0)))
13187 (set (match_operand:DI 0 "gpc_reg_operand" "")
13188 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13189 "TARGET_64BIT && reload_completed"
13190 [(set (match_dup 0)
13191 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13192 (set (match_dup 3)
13193 (compare:CC (match_dup 0)
13194 (const_int 0)))]
13195 "")
13197 (define_insn ""
13198 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13199 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13200 (match_operand:SI 2 "reg_or_short_operand" "r"))
13201 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13202 "TARGET_POWER"
13203 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13204 [(set_attr "length" "12")])
13206 (define_insn ""
13207 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13208 (compare:CC
13209 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13210 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13211 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13212 (const_int 0)))
13213 (clobber (match_scratch:SI 4 "=&r,&r"))]
13214 "TARGET_POWER"
13215 "@
13216 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13217 #"
13218 [(set_attr "type" "compare")
13219 (set_attr "length" "12,16")])
13221 (define_split
13222 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13223 (compare:CC
13224 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13225 (match_operand:SI 2 "reg_or_short_operand" ""))
13226 (match_operand:SI 3 "gpc_reg_operand" ""))
13227 (const_int 0)))
13228 (clobber (match_scratch:SI 4 ""))]
13229 "TARGET_POWER && reload_completed"
13230 [(set (match_dup 4)
13231 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13232 (set (match_dup 0)
13233 (compare:CC (match_dup 4)
13234 (const_int 0)))]
13235 "")
13237 (define_insn ""
13238 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13239 (compare:CC
13240 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13241 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13242 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13243 (const_int 0)))
13244 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13245 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13246 "TARGET_POWER"
13247 "@
13248 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13249 #"
13250 [(set_attr "type" "compare")
13251 (set_attr "length" "12,16")])
13253 (define_split
13254 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13255 (compare:CC
13256 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13257 (match_operand:SI 2 "reg_or_short_operand" ""))
13258 (match_operand:SI 3 "gpc_reg_operand" ""))
13259 (const_int 0)))
13260 (set (match_operand:SI 0 "gpc_reg_operand" "")
13261 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13262 "TARGET_POWER && reload_completed"
13263 [(set (match_dup 0)
13264 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13265 (set (match_dup 4)
13266 (compare:CC (match_dup 0)
13267 (const_int 0)))]
13268 "")
13270 (define_insn ""
13271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13272 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13273 (const_int 0))))]
13274 "TARGET_32BIT"
13275 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13276 [(set_attr "length" "12")])
13278 (define_insn ""
13279 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13280 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13281 (const_int 0))))]
13282 "TARGET_64BIT"
13283 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13284 [(set_attr "length" "12")])
13286 (define_insn ""
13287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13288 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13289 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13290 "TARGET_POWER"
13291 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13292 [(set_attr "length" "12")])
13294 (define_insn ""
13295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13296 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13297 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13298 "TARGET_32BIT"
13299 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13300 [(set_attr "length" "12")])
13302 (define_insn ""
13303 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13304 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13305 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13306 "TARGET_64BIT"
13307 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13308 [(set_attr "length" "12")])
13310 (define_insn ""
13311 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13312 (compare:CC
13313 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13314 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13315 (const_int 0)))
13316 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13317 (gtu:SI (match_dup 1) (match_dup 2)))]
13318 "TARGET_32BIT"
13319 "@
13320 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13321 #"
13322 [(set_attr "type" "compare")
13323 (set_attr "length" "12,16")])
13325 (define_split
13326 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13327 (compare:CC
13328 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13329 (match_operand:SI 2 "reg_or_short_operand" ""))
13330 (const_int 0)))
13331 (set (match_operand:SI 0 "gpc_reg_operand" "")
13332 (gtu:SI (match_dup 1) (match_dup 2)))]
13333 "TARGET_32BIT && reload_completed"
13334 [(set (match_dup 0)
13335 (gtu:SI (match_dup 1) (match_dup 2)))
13336 (set (match_dup 3)
13337 (compare:CC (match_dup 0)
13338 (const_int 0)))]
13339 "")
13341 (define_insn ""
13342 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13343 (compare:CC
13344 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13345 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13346 (const_int 0)))
13347 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13348 (gtu:DI (match_dup 1) (match_dup 2)))]
13349 "TARGET_64BIT"
13350 "@
13351 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13352 #"
13353 [(set_attr "type" "compare")
13354 (set_attr "length" "12,16")])
13356 (define_split
13357 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13358 (compare:CC
13359 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13360 (match_operand:DI 2 "reg_or_short_operand" ""))
13361 (const_int 0)))
13362 (set (match_operand:DI 0 "gpc_reg_operand" "")
13363 (gtu:DI (match_dup 1) (match_dup 2)))]
13364 "TARGET_64BIT && reload_completed"
13365 [(set (match_dup 0)
13366 (gtu:DI (match_dup 1) (match_dup 2)))
13367 (set (match_dup 3)
13368 (compare:CC (match_dup 0)
13369 (const_int 0)))]
13370 "")
13372 (define_insn ""
13373 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13374 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13375 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13376 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13377 "TARGET_32BIT"
13378 "@
13379 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13380 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13381 [(set_attr "length" "8,12")])
13383 (define_insn ""
13384 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13385 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13386 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13387 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13388 "TARGET_64BIT"
13389 "@
13390 addic %0,%1,%k2\;addze %0,%3
13391 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13392 [(set_attr "length" "8,12")])
13394 (define_insn ""
13395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13396 (compare:CC
13397 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13398 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13399 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13400 (const_int 0)))
13401 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13402 "TARGET_32BIT"
13403 "@
13404 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13405 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13406 #
13407 #"
13408 [(set_attr "type" "compare")
13409 (set_attr "length" "8,12,12,16")])
13411 (define_split
13412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13413 (compare:CC
13414 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13415 (match_operand:SI 2 "reg_or_short_operand" ""))
13416 (match_operand:SI 3 "gpc_reg_operand" ""))
13417 (const_int 0)))
13418 (clobber (match_scratch:SI 4 ""))]
13419 "TARGET_32BIT && reload_completed"
13420 [(set (match_dup 4)
13421 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13422 (match_dup 3)))
13423 (set (match_dup 0)
13424 (compare:CC (match_dup 4)
13425 (const_int 0)))]
13426 "")
13428 (define_insn ""
13429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13430 (compare:CC
13431 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13432 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13433 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13434 (const_int 0)))
13435 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13436 "TARGET_64BIT"
13437 "@
13438 addic %4,%1,%k2\;addze. %4,%3
13439 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13440 #
13441 #"
13442 [(set_attr "type" "compare")
13443 (set_attr "length" "8,12,12,16")])
13445 (define_split
13446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13447 (compare:CC
13448 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13449 (match_operand:DI 2 "reg_or_short_operand" ""))
13450 (match_operand:DI 3 "gpc_reg_operand" ""))
13451 (const_int 0)))
13452 (clobber (match_scratch:DI 4 ""))]
13453 "TARGET_64BIT && reload_completed"
13454 [(set (match_dup 4)
13455 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13456 (match_dup 3)))
13457 (set (match_dup 0)
13458 (compare:CC (match_dup 4)
13459 (const_int 0)))]
13460 "")
13462 (define_insn ""
13463 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13464 (compare:CC
13465 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13466 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13467 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13468 (const_int 0)))
13469 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13470 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13471 "TARGET_32BIT"
13472 "@
13473 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13474 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13475 #
13476 #"
13477 [(set_attr "type" "compare")
13478 (set_attr "length" "8,12,12,16")])
13480 (define_split
13481 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13482 (compare:CC
13483 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13484 (match_operand:SI 2 "reg_or_short_operand" ""))
13485 (match_operand:SI 3 "gpc_reg_operand" ""))
13486 (const_int 0)))
13487 (set (match_operand:SI 0 "gpc_reg_operand" "")
13488 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13489 "TARGET_32BIT && reload_completed"
13490 [(set (match_dup 0)
13491 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13492 (set (match_dup 4)
13493 (compare:CC (match_dup 0)
13494 (const_int 0)))]
13495 "")
13497 (define_insn ""
13498 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13499 (compare:CC
13500 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13501 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13502 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13503 (const_int 0)))
13504 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13505 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13506 "TARGET_64BIT"
13507 "@
13508 addic %0,%1,%k2\;addze. %0,%3
13509 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13510 #
13511 #"
13512 [(set_attr "type" "compare")
13513 (set_attr "length" "8,12,12,16")])
13515 (define_split
13516 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13517 (compare:CC
13518 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13519 (match_operand:DI 2 "reg_or_short_operand" ""))
13520 (match_operand:DI 3 "gpc_reg_operand" ""))
13521 (const_int 0)))
13522 (set (match_operand:DI 0 "gpc_reg_operand" "")
13523 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13524 "TARGET_64BIT && reload_completed"
13525 [(set (match_dup 0)
13526 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13527 (set (match_dup 4)
13528 (compare:CC (match_dup 0)
13529 (const_int 0)))]
13530 "")
13532 (define_insn ""
13533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13534 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13535 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13536 "TARGET_32BIT"
13537 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13538 [(set_attr "length" "8")])
13540 (define_insn ""
13541 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13542 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13543 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13544 "TARGET_64BIT"
13545 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13546 [(set_attr "length" "8")])
13547 \f
13548 ;; Define both directions of branch and return. If we need a reload
13549 ;; register, we'd rather use CR0 since it is much easier to copy a
13550 ;; register CC value to there.
13552 (define_insn ""
13553 [(set (pc)
13554 (if_then_else (match_operator 1 "branch_comparison_operator"
13555 [(match_operand 2
13556 "cc_reg_operand" "y")
13557 (const_int 0)])
13558 (label_ref (match_operand 0 "" ""))
13559 (pc)))]
13560 ""
13561 "*
13562 {
13563 return output_cbranch (operands[1], \"%l0\", 0, insn);
13564 }"
13565 [(set_attr "type" "branch")])
13567 (define_insn ""
13568 [(set (pc)
13569 (if_then_else (match_operator 0 "branch_comparison_operator"
13570 [(match_operand 1
13571 "cc_reg_operand" "y")
13572 (const_int 0)])
13573 (return)
13574 (pc)))]
13575 "direct_return ()"
13576 "*
13577 {
13578 return output_cbranch (operands[0], NULL, 0, insn);
13579 }"
13580 [(set_attr "type" "branch")
13581 (set_attr "length" "4")])
13583 (define_insn ""
13584 [(set (pc)
13585 (if_then_else (match_operator 1 "branch_comparison_operator"
13586 [(match_operand 2
13587 "cc_reg_operand" "y")
13588 (const_int 0)])
13589 (pc)
13590 (label_ref (match_operand 0 "" ""))))]
13591 ""
13592 "*
13593 {
13594 return output_cbranch (operands[1], \"%l0\", 1, insn);
13595 }"
13596 [(set_attr "type" "branch")])
13598 (define_insn ""
13599 [(set (pc)
13600 (if_then_else (match_operator 0 "branch_comparison_operator"
13601 [(match_operand 1
13602 "cc_reg_operand" "y")
13603 (const_int 0)])
13604 (pc)
13605 (return)))]
13606 "direct_return ()"
13607 "*
13608 {
13609 return output_cbranch (operands[0], NULL, 1, insn);
13610 }"
13611 [(set_attr "type" "branch")
13612 (set_attr "length" "4")])
13614 ;; Logic on condition register values.
13616 ; This pattern matches things like
13617 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13618 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13619 ; (const_int 1)))
13620 ; which are generated by the branch logic.
13621 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13623 (define_insn ""
13624 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13625 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13626 [(match_operator:SI 2
13627 "branch_positive_comparison_operator"
13628 [(match_operand 3
13629 "cc_reg_operand" "y,y")
13630 (const_int 0)])
13631 (match_operator:SI 4
13632 "branch_positive_comparison_operator"
13633 [(match_operand 5
13634 "cc_reg_operand" "0,y")
13635 (const_int 0)])])
13636 (const_int 1)))]
13637 ""
13638 "cr%q1 %E0,%j2,%j4"
13639 [(set_attr "type" "cr_logical,delayed_cr")])
13641 ; Why is the constant -1 here, but 1 in the previous pattern?
13642 ; Because ~1 has all but the low bit set.
13643 (define_insn ""
13644 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13645 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13646 [(not:SI (match_operator:SI 2
13647 "branch_positive_comparison_operator"
13648 [(match_operand 3
13649 "cc_reg_operand" "y,y")
13650 (const_int 0)]))
13651 (match_operator:SI 4
13652 "branch_positive_comparison_operator"
13653 [(match_operand 5
13654 "cc_reg_operand" "0,y")
13655 (const_int 0)])])
13656 (const_int -1)))]
13657 ""
13658 "cr%q1 %E0,%j2,%j4"
13659 [(set_attr "type" "cr_logical,delayed_cr")])
13661 (define_insn ""
13662 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13663 (compare:CCEQ (match_operator:SI 1
13664 "branch_positive_comparison_operator"
13665 [(match_operand 2
13666 "cc_reg_operand" "0,y")
13667 (const_int 0)])
13668 (const_int 0)))]
13669 ;; This pattern is not available to SPE because the CR bits on an FP
13670 ;; compare are different than traditional PPC.
13671 "!TARGET_SPE"
13672 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13673 [(set_attr "type" "cr_logical,delayed_cr")])
13675 ;; If we are comparing the result of two comparisons, this can be done
13676 ;; using creqv or crxor.
13678 (define_insn_and_split ""
13679 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13680 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13681 [(match_operand 2 "cc_reg_operand" "y")
13682 (const_int 0)])
13683 (match_operator 3 "branch_comparison_operator"
13684 [(match_operand 4 "cc_reg_operand" "y")
13685 (const_int 0)])))]
13686 ""
13687 "#"
13688 ""
13689 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13690 (match_dup 5)))]
13691 "
13692 {
13693 int positive_1, positive_2;
13695 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13696 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13698 if (! positive_1)
13699 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13700 GET_CODE (operands[1])),
13701 SImode,
13702 operands[2], const0_rtx);
13703 else if (GET_MODE (operands[1]) != SImode)
13704 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13705 operands[2], const0_rtx);
13707 if (! positive_2)
13708 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13709 GET_CODE (operands[3])),
13710 SImode,
13711 operands[4], const0_rtx);
13712 else if (GET_MODE (operands[3]) != SImode)
13713 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13714 operands[4], const0_rtx);
13716 if (positive_1 == positive_2)
13717 {
13718 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13719 operands[5] = constm1_rtx;
13720 }
13721 else
13722 {
13723 operands[5] = const1_rtx;
13724 }
13725 }")
13727 ;; Unconditional branch and return.
13729 (define_insn "jump"
13730 [(set (pc)
13731 (label_ref (match_operand 0 "" "")))]
13732 ""
13733 "b %l0"
13734 [(set_attr "type" "branch")])
13736 (define_insn "return"
13737 [(return)]
13738 "direct_return ()"
13739 "{br|blr}"
13740 [(set_attr "type" "jmpreg")])
13742 (define_expand "indirect_jump"
13743 [(set (pc) (match_operand 0 "register_operand" ""))]
13744 ""
13745 "
13746 {
13747 if (TARGET_32BIT)
13748 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13749 else
13750 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13751 DONE;
13752 }")
13754 (define_insn "indirect_jumpsi"
13755 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13756 "TARGET_32BIT"
13757 "@
13758 bctr
13759 {br|blr}"
13760 [(set_attr "type" "jmpreg")])
13762 (define_insn "indirect_jumpdi"
13763 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13764 "TARGET_64BIT"
13765 "@
13766 bctr
13767 blr"
13768 [(set_attr "type" "jmpreg")])
13770 ;; Table jump for switch statements:
13771 (define_expand "tablejump"
13772 [(use (match_operand 0 "" ""))
13773 (use (label_ref (match_operand 1 "" "")))]
13774 ""
13775 "
13776 {
13777 if (TARGET_32BIT)
13778 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13779 else
13780 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13781 DONE;
13782 }")
13784 (define_expand "tablejumpsi"
13785 [(set (match_dup 3)
13786 (plus:SI (match_operand:SI 0 "" "")
13787 (match_dup 2)))
13788 (parallel [(set (pc) (match_dup 3))
13789 (use (label_ref (match_operand 1 "" "")))])]
13790 "TARGET_32BIT"
13791 "
13792 { operands[0] = force_reg (SImode, operands[0]);
13793 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13794 operands[3] = gen_reg_rtx (SImode);
13795 }")
13797 (define_expand "tablejumpdi"
13798 [(set (match_dup 4)
13799 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13800 (set (match_dup 3)
13801 (plus:DI (match_dup 4)
13802 (match_dup 2)))
13803 (parallel [(set (pc) (match_dup 3))
13804 (use (label_ref (match_operand 1 "" "")))])]
13805 "TARGET_64BIT"
13806 "
13807 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13808 operands[3] = gen_reg_rtx (DImode);
13809 operands[4] = gen_reg_rtx (DImode);
13810 }")
13812 (define_insn ""
13813 [(set (pc)
13814 (match_operand:SI 0 "register_operand" "c,*l"))
13815 (use (label_ref (match_operand 1 "" "")))]
13816 "TARGET_32BIT"
13817 "@
13818 bctr
13819 {br|blr}"
13820 [(set_attr "type" "jmpreg")])
13822 (define_insn ""
13823 [(set (pc)
13824 (match_operand:DI 0 "register_operand" "c,*l"))
13825 (use (label_ref (match_operand 1 "" "")))]
13826 "TARGET_64BIT"
13827 "@
13828 bctr
13829 blr"
13830 [(set_attr "type" "jmpreg")])
13832 (define_insn "nop"
13833 [(const_int 0)]
13834 ""
13835 "{cror 0,0,0|nop}")
13836 \f
13837 ;; Define the subtract-one-and-jump insns, starting with the template
13838 ;; so loop.c knows what to generate.
13840 (define_expand "doloop_end"
13841 [(use (match_operand 0 "" "")) ; loop pseudo
13842 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13843 (use (match_operand 2 "" "")) ; max iterations
13844 (use (match_operand 3 "" "")) ; loop level
13845 (use (match_operand 4 "" ""))] ; label
13846 ""
13847 "
13848 {
13849 /* Only use this on innermost loops. */
13850 if (INTVAL (operands[3]) > 1)
13851 FAIL;
13852 if (TARGET_64BIT)
13853 {
13854 if (GET_MODE (operands[0]) != DImode)
13855 FAIL;
13856 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13857 }
13858 else
13859 {
13860 if (GET_MODE (operands[0]) != SImode)
13861 FAIL;
13862 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13863 }
13864 DONE;
13865 }")
13867 (define_expand "ctrsi"
13868 [(parallel [(set (pc)
13869 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13870 (const_int 1))
13871 (label_ref (match_operand 1 "" ""))
13872 (pc)))
13873 (set (match_dup 0)
13874 (plus:SI (match_dup 0)
13875 (const_int -1)))
13876 (clobber (match_scratch:CC 2 ""))
13877 (clobber (match_scratch:SI 3 ""))])]
13878 "TARGET_32BIT"
13879 "")
13881 (define_expand "ctrdi"
13882 [(parallel [(set (pc)
13883 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13884 (const_int 1))
13885 (label_ref (match_operand 1 "" ""))
13886 (pc)))
13887 (set (match_dup 0)
13888 (plus:DI (match_dup 0)
13889 (const_int -1)))
13890 (clobber (match_scratch:CC 2 ""))
13891 (clobber (match_scratch:DI 3 ""))])]
13892 "TARGET_64BIT"
13893 "")
13895 ;; We need to be able to do this for any operand, including MEM, or we
13896 ;; will cause reload to blow up since we don't allow output reloads on
13897 ;; JUMP_INSNs.
13898 ;; For the length attribute to be calculated correctly, the
13899 ;; label MUST be operand 0.
13901 (define_insn "*ctrsi_internal1"
13902 [(set (pc)
13903 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13904 (const_int 1))
13905 (label_ref (match_operand 0 "" ""))
13906 (pc)))
13907 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13908 (plus:SI (match_dup 1)
13909 (const_int -1)))
13910 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13911 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13912 "TARGET_32BIT"
13913 "*
13914 {
13915 if (which_alternative != 0)
13916 return \"#\";
13917 else if (get_attr_length (insn) == 4)
13918 return \"{bdn|bdnz} %l0\";
13919 else
13920 return \"bdz $+8\;b %l0\";
13921 }"
13922 [(set_attr "type" "branch")
13923 (set_attr "length" "*,12,16,16")])
13925 (define_insn "*ctrsi_internal2"
13926 [(set (pc)
13927 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13928 (const_int 1))
13929 (pc)
13930 (label_ref (match_operand 0 "" ""))))
13931 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13932 (plus:SI (match_dup 1)
13933 (const_int -1)))
13934 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13935 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13936 "TARGET_32BIT"
13937 "*
13938 {
13939 if (which_alternative != 0)
13940 return \"#\";
13941 else if (get_attr_length (insn) == 4)
13942 return \"bdz %l0\";
13943 else
13944 return \"{bdn|bdnz} $+8\;b %l0\";
13945 }"
13946 [(set_attr "type" "branch")
13947 (set_attr "length" "*,12,16,16")])
13949 (define_insn "*ctrdi_internal1"
13950 [(set (pc)
13951 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13952 (const_int 1))
13953 (label_ref (match_operand 0 "" ""))
13954 (pc)))
13955 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13956 (plus:DI (match_dup 1)
13957 (const_int -1)))
13958 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13959 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13960 "TARGET_64BIT"
13961 "*
13962 {
13963 if (which_alternative != 0)
13964 return \"#\";
13965 else if (get_attr_length (insn) == 4)
13966 return \"{bdn|bdnz} %l0\";
13967 else
13968 return \"bdz $+8\;b %l0\";
13969 }"
13970 [(set_attr "type" "branch")
13971 (set_attr "length" "*,12,16,16")])
13973 (define_insn "*ctrdi_internal2"
13974 [(set (pc)
13975 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13976 (const_int 1))
13977 (pc)
13978 (label_ref (match_operand 0 "" ""))))
13979 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13980 (plus:DI (match_dup 1)
13981 (const_int -1)))
13982 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13983 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13984 "TARGET_64BIT"
13985 "*
13986 {
13987 if (which_alternative != 0)
13988 return \"#\";
13989 else if (get_attr_length (insn) == 4)
13990 return \"bdz %l0\";
13991 else
13992 return \"{bdn|bdnz} $+8\;b %l0\";
13993 }"
13994 [(set_attr "type" "branch")
13995 (set_attr "length" "*,12,16,16")])
13997 ;; Similar, but we can use GE since we have a REG_NONNEG.
13999 (define_insn "*ctrsi_internal3"
14000 [(set (pc)
14001 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14002 (const_int 0))
14003 (label_ref (match_operand 0 "" ""))
14004 (pc)))
14005 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14006 (plus:SI (match_dup 1)
14007 (const_int -1)))
14008 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14009 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14010 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14011 "*
14012 {
14013 if (which_alternative != 0)
14014 return \"#\";
14015 else if (get_attr_length (insn) == 4)
14016 return \"{bdn|bdnz} %l0\";
14017 else
14018 return \"bdz $+8\;b %l0\";
14019 }"
14020 [(set_attr "type" "branch")
14021 (set_attr "length" "*,12,16,16")])
14023 (define_insn "*ctrsi_internal4"
14024 [(set (pc)
14025 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14026 (const_int 0))
14027 (pc)
14028 (label_ref (match_operand 0 "" ""))))
14029 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14030 (plus:SI (match_dup 1)
14031 (const_int -1)))
14032 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14033 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14034 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14035 "*
14036 {
14037 if (which_alternative != 0)
14038 return \"#\";
14039 else if (get_attr_length (insn) == 4)
14040 return \"bdz %l0\";
14041 else
14042 return \"{bdn|bdnz} $+8\;b %l0\";
14043 }"
14044 [(set_attr "type" "branch")
14045 (set_attr "length" "*,12,16,16")])
14047 (define_insn "*ctrdi_internal3"
14048 [(set (pc)
14049 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14050 (const_int 0))
14051 (label_ref (match_operand 0 "" ""))
14052 (pc)))
14053 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14054 (plus:DI (match_dup 1)
14055 (const_int -1)))
14056 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14057 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14058 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14059 "*
14060 {
14061 if (which_alternative != 0)
14062 return \"#\";
14063 else if (get_attr_length (insn) == 4)
14064 return \"{bdn|bdnz} %l0\";
14065 else
14066 return \"bdz $+8\;b %l0\";
14067 }"
14068 [(set_attr "type" "branch")
14069 (set_attr "length" "*,12,16,16")])
14071 (define_insn "*ctrdi_internal4"
14072 [(set (pc)
14073 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14074 (const_int 0))
14075 (pc)
14076 (label_ref (match_operand 0 "" ""))))
14077 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14078 (plus:DI (match_dup 1)
14079 (const_int -1)))
14080 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14081 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14082 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14083 "*
14084 {
14085 if (which_alternative != 0)
14086 return \"#\";
14087 else if (get_attr_length (insn) == 4)
14088 return \"bdz %l0\";
14089 else
14090 return \"{bdn|bdnz} $+8\;b %l0\";
14091 }"
14092 [(set_attr "type" "branch")
14093 (set_attr "length" "*,12,16,16")])
14095 ;; Similar but use EQ
14097 (define_insn "*ctrsi_internal5"
14098 [(set (pc)
14099 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14100 (const_int 1))
14101 (label_ref (match_operand 0 "" ""))
14102 (pc)))
14103 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14104 (plus:SI (match_dup 1)
14105 (const_int -1)))
14106 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14107 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14108 "TARGET_32BIT"
14109 "*
14110 {
14111 if (which_alternative != 0)
14112 return \"#\";
14113 else if (get_attr_length (insn) == 4)
14114 return \"bdz %l0\";
14115 else
14116 return \"{bdn|bdnz} $+8\;b %l0\";
14117 }"
14118 [(set_attr "type" "branch")
14119 (set_attr "length" "*,12,16,16")])
14121 (define_insn "*ctrsi_internal6"
14122 [(set (pc)
14123 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14124 (const_int 1))
14125 (pc)
14126 (label_ref (match_operand 0 "" ""))))
14127 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14128 (plus:SI (match_dup 1)
14129 (const_int -1)))
14130 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14131 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14132 "TARGET_32BIT"
14133 "*
14134 {
14135 if (which_alternative != 0)
14136 return \"#\";
14137 else if (get_attr_length (insn) == 4)
14138 return \"{bdn|bdnz} %l0\";
14139 else
14140 return \"bdz $+8\;b %l0\";
14141 }"
14142 [(set_attr "type" "branch")
14143 (set_attr "length" "*,12,16,16")])
14145 (define_insn "*ctrdi_internal5"
14146 [(set (pc)
14147 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14148 (const_int 1))
14149 (label_ref (match_operand 0 "" ""))
14150 (pc)))
14151 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14152 (plus:DI (match_dup 1)
14153 (const_int -1)))
14154 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14155 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14156 "TARGET_64BIT"
14157 "*
14158 {
14159 if (which_alternative != 0)
14160 return \"#\";
14161 else if (get_attr_length (insn) == 4)
14162 return \"bdz %l0\";
14163 else
14164 return \"{bdn|bdnz} $+8\;b %l0\";
14165 }"
14166 [(set_attr "type" "branch")
14167 (set_attr "length" "*,12,16,16")])
14169 (define_insn "*ctrdi_internal6"
14170 [(set (pc)
14171 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14172 (const_int 1))
14173 (pc)
14174 (label_ref (match_operand 0 "" ""))))
14175 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14176 (plus:DI (match_dup 1)
14177 (const_int -1)))
14178 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14179 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14180 "TARGET_64BIT"
14181 "*
14182 {
14183 if (which_alternative != 0)
14184 return \"#\";
14185 else if (get_attr_length (insn) == 4)
14186 return \"{bdn|bdnz} %l0\";
14187 else
14188 return \"bdz $+8\;b %l0\";
14189 }"
14190 [(set_attr "type" "branch")
14191 (set_attr "length" "*,12,16,16")])
14193 ;; Now the splitters if we could not allocate the CTR register
14195 (define_split
14196 [(set (pc)
14197 (if_then_else (match_operator 2 "comparison_operator"
14198 [(match_operand:SI 1 "gpc_reg_operand" "")
14199 (const_int 1)])
14200 (match_operand 5 "" "")
14201 (match_operand 6 "" "")))
14202 (set (match_operand:SI 0 "gpc_reg_operand" "")
14203 (plus:SI (match_dup 1)
14204 (const_int -1)))
14205 (clobber (match_scratch:CC 3 ""))
14206 (clobber (match_scratch:SI 4 ""))]
14207 "TARGET_32BIT && reload_completed"
14208 [(parallel [(set (match_dup 3)
14209 (compare:CC (plus:SI (match_dup 1)
14210 (const_int -1))
14211 (const_int 0)))
14212 (set (match_dup 0)
14213 (plus:SI (match_dup 1)
14214 (const_int -1)))])
14215 (set (pc) (if_then_else (match_dup 7)
14216 (match_dup 5)
14217 (match_dup 6)))]
14218 "
14219 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14220 operands[3], const0_rtx); }")
14222 (define_split
14223 [(set (pc)
14224 (if_then_else (match_operator 2 "comparison_operator"
14225 [(match_operand:SI 1 "gpc_reg_operand" "")
14226 (const_int 1)])
14227 (match_operand 5 "" "")
14228 (match_operand 6 "" "")))
14229 (set (match_operand:SI 0 "nonimmediate_operand" "")
14230 (plus:SI (match_dup 1) (const_int -1)))
14231 (clobber (match_scratch:CC 3 ""))
14232 (clobber (match_scratch:SI 4 ""))]
14233 "TARGET_32BIT && reload_completed
14234 && ! gpc_reg_operand (operands[0], SImode)"
14235 [(parallel [(set (match_dup 3)
14236 (compare:CC (plus:SI (match_dup 1)
14237 (const_int -1))
14238 (const_int 0)))
14239 (set (match_dup 4)
14240 (plus:SI (match_dup 1)
14241 (const_int -1)))])
14242 (set (match_dup 0)
14243 (match_dup 4))
14244 (set (pc) (if_then_else (match_dup 7)
14245 (match_dup 5)
14246 (match_dup 6)))]
14247 "
14248 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14249 operands[3], const0_rtx); }")
14250 (define_split
14251 [(set (pc)
14252 (if_then_else (match_operator 2 "comparison_operator"
14253 [(match_operand:DI 1 "gpc_reg_operand" "")
14254 (const_int 1)])
14255 (match_operand 5 "" "")
14256 (match_operand 6 "" "")))
14257 (set (match_operand:DI 0 "gpc_reg_operand" "")
14258 (plus:DI (match_dup 1)
14259 (const_int -1)))
14260 (clobber (match_scratch:CC 3 ""))
14261 (clobber (match_scratch:DI 4 ""))]
14262 "TARGET_64BIT && reload_completed"
14263 [(parallel [(set (match_dup 3)
14264 (compare:CC (plus:DI (match_dup 1)
14265 (const_int -1))
14266 (const_int 0)))
14267 (set (match_dup 0)
14268 (plus:DI (match_dup 1)
14269 (const_int -1)))])
14270 (set (pc) (if_then_else (match_dup 7)
14271 (match_dup 5)
14272 (match_dup 6)))]
14273 "
14274 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14275 operands[3], const0_rtx); }")
14277 (define_split
14278 [(set (pc)
14279 (if_then_else (match_operator 2 "comparison_operator"
14280 [(match_operand:DI 1 "gpc_reg_operand" "")
14281 (const_int 1)])
14282 (match_operand 5 "" "")
14283 (match_operand 6 "" "")))
14284 (set (match_operand:DI 0 "nonimmediate_operand" "")
14285 (plus:DI (match_dup 1) (const_int -1)))
14286 (clobber (match_scratch:CC 3 ""))
14287 (clobber (match_scratch:DI 4 ""))]
14288 "TARGET_64BIT && reload_completed
14289 && ! gpc_reg_operand (operands[0], DImode)"
14290 [(parallel [(set (match_dup 3)
14291 (compare:CC (plus:DI (match_dup 1)
14292 (const_int -1))
14293 (const_int 0)))
14294 (set (match_dup 4)
14295 (plus:DI (match_dup 1)
14296 (const_int -1)))])
14297 (set (match_dup 0)
14298 (match_dup 4))
14299 (set (pc) (if_then_else (match_dup 7)
14300 (match_dup 5)
14301 (match_dup 6)))]
14302 "
14303 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14304 operands[3], const0_rtx); }")
14305 \f
14306 (define_insn "trap"
14307 [(trap_if (const_int 1) (const_int 0))]
14308 ""
14309 "{t 31,0,0|trap}")
14311 (define_expand "conditional_trap"
14312 [(trap_if (match_operator 0 "trap_comparison_operator"
14313 [(match_dup 2) (match_dup 3)])
14314 (match_operand 1 "const_int_operand" ""))]
14315 ""
14316 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14317 operands[2] = rs6000_compare_op0;
14318 operands[3] = rs6000_compare_op1;")
14320 (define_insn ""
14321 [(trap_if (match_operator 0 "trap_comparison_operator"
14322 [(match_operand:SI 1 "register_operand" "r")
14323 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14324 (const_int 0))]
14325 ""
14326 "{t|tw}%V0%I2 %1,%2")
14328 (define_insn ""
14329 [(trap_if (match_operator 0 "trap_comparison_operator"
14330 [(match_operand:DI 1 "register_operand" "r")
14331 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14332 (const_int 0))]
14333 "TARGET_POWERPC64"
14334 "td%V0%I2 %1,%2")
14335 \f
14336 ;; Insns related to generating the function prologue and epilogue.
14338 (define_expand "prologue"
14339 [(use (const_int 0))]
14340 "TARGET_SCHED_PROLOG"
14341 "
14342 {
14343 rs6000_emit_prologue ();
14344 DONE;
14345 }")
14347 (define_insn "*movesi_from_cr_one"
14348 [(match_parallel 0 "mfcr_operation"
14349 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14350 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14351 (match_operand 3 "immediate_operand" "n")]
14352 UNSPEC_MOVESI_FROM_CR))])]
14353 "TARGET_MFCRF"
14354 "*
14355 {
14356 int mask = 0;
14357 int i;
14358 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14359 {
14360 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14361 operands[4] = GEN_INT (mask);
14362 output_asm_insn (\"mfcr %1,%4\", operands);
14363 }
14364 return \"\";
14365 }"
14366 [(set_attr "type" "mfcrf")])
14368 (define_insn "movesi_from_cr"
14369 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14370 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14371 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14372 UNSPEC_MOVESI_FROM_CR))]
14373 ""
14374 "mfcr %0"
14375 [(set_attr "type" "mfcr")])
14377 (define_insn "*stmw"
14378 [(match_parallel 0 "stmw_operation"
14379 [(set (match_operand:SI 1 "memory_operand" "=m")
14380 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14381 "TARGET_MULTIPLE"
14382 "{stm|stmw} %2,%1")
14384 (define_insn "*save_fpregs_si"
14385 [(match_parallel 0 "any_operand"
14386 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14387 (use (match_operand:SI 2 "call_operand" "s"))
14388 (set (match_operand:DF 3 "memory_operand" "=m")
14389 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14390 "TARGET_32BIT"
14391 "bl %z2"
14392 [(set_attr "type" "branch")
14393 (set_attr "length" "4")])
14395 (define_insn "*save_fpregs_di"
14396 [(match_parallel 0 "any_operand"
14397 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14398 (use (match_operand:DI 2 "call_operand" "s"))
14399 (set (match_operand:DF 3 "memory_operand" "=m")
14400 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14401 "TARGET_64BIT"
14402 "bl %z2"
14403 [(set_attr "type" "branch")
14404 (set_attr "length" "4")])
14406 ; These are to explain that changes to the stack pointer should
14407 ; not be moved over stores to stack memory.
14408 (define_insn "stack_tie"
14409 [(set (match_operand:BLK 0 "memory_operand" "+m")
14410 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14411 ""
14412 ""
14413 [(set_attr "length" "0")])
14416 (define_expand "epilogue"
14417 [(use (const_int 0))]
14418 "TARGET_SCHED_PROLOG"
14419 "
14420 {
14421 rs6000_emit_epilogue (FALSE);
14422 DONE;
14423 }")
14425 ; On some processors, doing the mtcrf one CC register at a time is
14426 ; faster (like on the 604e). On others, doing them all at once is
14427 ; faster; for instance, on the 601 and 750.
14429 (define_expand "movsi_to_cr_one"
14430 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14431 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14432 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14433 ""
14434 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14436 (define_insn "*movsi_to_cr"
14437 [(match_parallel 0 "mtcrf_operation"
14438 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14439 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14440 (match_operand 3 "immediate_operand" "n")]
14441 UNSPEC_MOVESI_TO_CR))])]
14442 ""
14443 "*
14444 {
14445 int mask = 0;
14446 int i;
14447 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14448 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14449 operands[4] = GEN_INT (mask);
14450 return \"mtcrf %4,%2\";
14451 }"
14452 [(set_attr "type" "mtcr")])
14454 (define_insn "*mtcrfsi"
14455 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14456 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14457 (match_operand 2 "immediate_operand" "n")]
14458 UNSPEC_MOVESI_TO_CR))]
14459 "GET_CODE (operands[0]) == REG
14460 && CR_REGNO_P (REGNO (operands[0]))
14461 && GET_CODE (operands[2]) == CONST_INT
14462 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14463 "mtcrf %R0,%1"
14464 [(set_attr "type" "mtcr")])
14466 ; The load-multiple instructions have similar properties.
14467 ; Note that "load_multiple" is a name known to the machine-independent
14468 ; code that actually corresponds to the powerpc load-string.
14470 (define_insn "*lmw"
14471 [(match_parallel 0 "lmw_operation"
14472 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14473 (match_operand:SI 2 "memory_operand" "m"))])]
14474 "TARGET_MULTIPLE"
14475 "{lm|lmw} %1,%2")
14477 (define_insn "*return_internal_si"
14478 [(return)
14479 (use (match_operand:SI 0 "register_operand" "lc"))]
14480 "TARGET_32BIT"
14481 "b%T0"
14482 [(set_attr "type" "jmpreg")])
14484 (define_insn "*return_internal_di"
14485 [(return)
14486 (use (match_operand:DI 0 "register_operand" "lc"))]
14487 "TARGET_64BIT"
14488 "b%T0"
14489 [(set_attr "type" "jmpreg")])
14491 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14492 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14494 (define_insn "*return_and_restore_fpregs_si"
14495 [(match_parallel 0 "any_operand"
14496 [(return)
14497 (use (match_operand:SI 1 "register_operand" "l"))
14498 (use (match_operand:SI 2 "call_operand" "s"))
14499 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14500 (match_operand:DF 4 "memory_operand" "m"))])]
14501 "TARGET_32BIT"
14502 "b %z2")
14504 (define_insn "*return_and_restore_fpregs_di"
14505 [(match_parallel 0 "any_operand"
14506 [(return)
14507 (use (match_operand:DI 1 "register_operand" "l"))
14508 (use (match_operand:DI 2 "call_operand" "s"))
14509 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14510 (match_operand:DF 4 "memory_operand" "m"))])]
14511 "TARGET_64BIT"
14512 "b %z2")
14514 ; This is used in compiling the unwind routines.
14515 (define_expand "eh_return"
14516 [(use (match_operand 0 "general_operand" ""))]
14517 ""
14518 "
14519 {
14520 if (TARGET_32BIT)
14521 emit_insn (gen_eh_set_lr_si (operands[0]));
14522 else
14523 emit_insn (gen_eh_set_lr_di (operands[0]));
14524 DONE;
14525 }")
14527 ; We can't expand this before we know where the link register is stored.
14528 (define_insn "eh_set_lr_si"
14529 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14530 UNSPECV_EH_RR)
14531 (clobber (match_scratch:SI 1 "=&b"))]
14532 "TARGET_32BIT"
14533 "#")
14535 (define_insn "eh_set_lr_di"
14536 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14537 UNSPECV_EH_RR)
14538 (clobber (match_scratch:DI 1 "=&b"))]
14539 "TARGET_64BIT"
14540 "#")
14542 (define_split
14543 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14544 (clobber (match_scratch 1 ""))]
14545 "reload_completed"
14546 [(const_int 0)]
14547 "
14548 {
14549 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14550 DONE;
14551 }")
14553 (define_insn "prefetch"
14554 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14555 (match_operand:SI 1 "const_int_operand" "n")
14556 (match_operand:SI 2 "const_int_operand" "n"))]
14557 "TARGET_POWERPC"
14558 "*
14559 {
14560 if (GET_CODE (operands[0]) == REG)
14561 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14562 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14563 }"
14564 [(set_attr "type" "load")])
14566 (include "altivec.md")
14567 (include "spe.md")