gcc/config/rs6000/rs6000.c

   1 /* Subroutines used for code generation on IBM RS/6000.
   2    Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
   4    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 2, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  21    MA 02111-1307, USA.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "tm.h"
  27 #include "rtl.h"
  28 #include "regs.h"
  29 #include "hard-reg-set.h"
  30 #include "real.h"
  31 #include "insn-config.h"
  32 #include "conditions.h"
  33 #include "insn-attr.h"
  34 #include "flags.h"
  35 #include "recog.h"
  36 #include "obstack.h"
  37 #include "tree.h"
  38 #include "expr.h"
  39 #include "optabs.h"
  40 #include "except.h"
  41 #include "function.h"
  42 #include "output.h"
  43 #include "basic-block.h"
  44 #include "integrate.h"
  45 #include "toplev.h"
  46 #include "ggc.h"
  47 #include "hashtab.h"
  48 #include "tm_p.h"
  49 #include "target.h"
  50 #include "target-def.h"
  51 #include "langhooks.h"
  52 #include "reload.h"
  53 #include "cfglayout.h"
  54 #include "sched-int.h"
  55 #if TARGET_XCOFF
  56 #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
  57 #endif
  58
  59 #ifndef TARGET_NO_PROTOTYPE
  60 #define TARGET_NO_PROTOTYPE 0
  61 #endif
  62
  63 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
  64 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \
  65                                           && !((n) & 1))
  66
  67 #define min(A,B)        ((A) < (B) ? (A) : (B))
  68 #define max(A,B)        ((A) > (B) ? (A) : (B))
  69
  70 /* Structure used to define the rs6000 stack */
  71 typedef struct rs6000_stack {
  72   int first_gp_reg_save;        /* first callee saved GP register used */
  73   int first_fp_reg_save;        /* first callee saved FP register used */
  74   int first_altivec_reg_save;   /* first callee saved AltiVec register used */
  75   int lr_save_p;                /* true if the link reg needs to be saved */
  76   int cr_save_p;                /* true if the CR reg needs to be saved */
  77   unsigned int vrsave_mask;     /* mask of vec registers to save */
  78   int toc_save_p;               /* true if the TOC needs to be saved */
  79   int push_p;                   /* true if we need to allocate stack space */
  80   int calls_p;                  /* true if the function makes any calls */
  81   enum rs6000_abi abi;          /* which ABI to use */
  82   int gp_save_offset;           /* offset to save GP regs from initial SP */
  83   int fp_save_offset;           /* offset to save FP regs from initial SP */
  84   int altivec_save_offset;      /* offset to save AltiVec regs from initial SP */
  85   int lr_save_offset;           /* offset to save LR from initial SP */
  86   int cr_save_offset;           /* offset to save CR from initial SP */
  87   int vrsave_save_offset;       /* offset to save VRSAVE from initial SP */
  88   int spe_gp_save_offset;       /* offset to save spe 64-bit gprs  */
  89   int toc_save_offset;          /* offset to save the TOC pointer */
  90   int varargs_save_offset;      /* offset to save the varargs registers */
  91   int ehrd_offset;              /* offset to EH return data */
  92   int reg_size;                 /* register size (4 or 8) */
  93   int varargs_size;             /* size to hold V.4 args passed in regs */
  94   HOST_WIDE_INT vars_size;      /* variable save area size */
  95   int parm_size;                /* outgoing parameter size */
  96   int save_size;                /* save area size */
  97   int fixed_size;               /* fixed size of stack frame */
  98   int gp_size;                  /* size of saved GP registers */
  99   int fp_size;                  /* size of saved FP registers */
 100   int altivec_size;             /* size of saved AltiVec registers */
 101   int cr_size;                  /* size to hold CR if not in save_size */
 102   int lr_size;                  /* size to hold LR if not in save_size */
 103   int vrsave_size;              /* size to hold VRSAVE if not in save_size */
 104   int altivec_padding_size;     /* size of altivec alignment padding if
 105                                    not in save_size */
 106   int spe_gp_size;              /* size of 64-bit GPR save size for SPE */
 107   int spe_padding_size;
 108   int toc_size;                 /* size to hold TOC if not in save_size */
 109   HOST_WIDE_INT total_size;     /* total bytes allocated for stack */
 110   int spe_64bit_regs_used;
 111 } rs6000_stack_t;
 112
 113 /* Target cpu type */
 114
 115 enum processor_type rs6000_cpu;
 116 struct rs6000_cpu_select rs6000_select[3] =
 117 {
 118   /* switch             name,                   tune    arch */
 119   { (const char *)0,    "--with-cpu=",          1,      1 },
 120   { (const char *)0,    "-mcpu=",               1,      1 },
 121   { (const char *)0,    "-mtune=",              1,      0 },
 122 };
 123
 124 /* Always emit branch hint bits.  */
 125 static GTY(()) bool rs6000_always_hint;
 126
 127 /* Schedule instructions for group formation.  */
 128 static GTY(()) bool rs6000_sched_groups;
 129
 130 /* Support adjust_priority scheduler hook
 131    and -mprioritize-restricted-insns= option.  */
 132 const char *rs6000_sched_restricted_insns_priority_str;
 133 int rs6000_sched_restricted_insns_priority;
 134
 135 /* Support for -msched-costly-dep option.  */
 136 const char *rs6000_sched_costly_dep_str;
 137 enum rs6000_dependence_cost rs6000_sched_costly_dep;
 138
 139 /* Support for -minsert-sched-nops option.  */
 140 const char *rs6000_sched_insert_nops_str;
 141 enum rs6000_nop_insertion rs6000_sched_insert_nops;
 142
 143 /* Size of long double */
 144 const char *rs6000_long_double_size_string;
 145 int rs6000_long_double_type_size;
 146
 147 /* Whether -mabi=altivec has appeared */
 148 int rs6000_altivec_abi;
 149
 150 /* Whether VRSAVE instructions should be generated.  */
 151 int rs6000_altivec_vrsave;
 152
 153 /* String from -mvrsave= option.  */
 154 const char *rs6000_altivec_vrsave_string;
 155
 156 /* Nonzero if we want SPE ABI extensions.  */
 157 int rs6000_spe_abi;
 158
 159 /* Whether isel instructions should be generated.  */
 160 int rs6000_isel;
 161
 162 /* Whether SPE simd instructions should be generated.  */
 163 int rs6000_spe;
 164
 165 /* Nonzero if floating point operations are done in the GPRs.  */
 166 int rs6000_float_gprs = 0;
 167
 168 /* String from -mfloat-gprs=.  */
 169 const char *rs6000_float_gprs_string;
 170
 171 /* String from -misel=.  */
 172 const char *rs6000_isel_string;
 173
 174 /* String from -mspe=.  */
 175 const char *rs6000_spe_string;
 176
 177 /* Set to nonzero once AIX common-mode calls have been defined.  */
 178 static GTY(()) int common_mode_defined;
 179
 180 /* Save information from a "cmpxx" operation until the branch or scc is
 181    emitted.  */
 182 rtx rs6000_compare_op0, rs6000_compare_op1;
 183 int rs6000_compare_fp_p;
 184
 185 /* Label number of label created for -mrelocatable, to call to so we can
 186    get the address of the GOT section */
 187 int rs6000_pic_labelno;
 188
 189 #ifdef USING_ELFOS_H
 190 /* Which abi to adhere to */
 191 const char *rs6000_abi_name;
 192
 193 /* Semantics of the small data area */
 194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
 195
 196 /* Which small data model to use */
 197 const char *rs6000_sdata_name = (char *)0;
 198
 199 /* Counter for labels which are to be placed in .fixup.  */
 200 int fixuplabelno = 0;
 201 #endif
 202
 203 /* Bit size of immediate TLS offsets and string from which it is decoded.  */
 204 int rs6000_tls_size = 32;
 205 const char *rs6000_tls_size_string;
 206
 207 /* ABI enumeration available for subtarget to use.  */
 208 enum rs6000_abi rs6000_current_abi;
 209
 210 /* ABI string from -mabi= option.  */
 211 const char *rs6000_abi_string;
 212
 213 /* Debug flags */
 214 const char *rs6000_debug_name;
 215 int rs6000_debug_stack;         /* debug stack applications */
 216 int rs6000_debug_arg;           /* debug argument handling */
 217
 218 /* Opaque types.  */
 219 static GTY(()) tree opaque_V2SI_type_node;
 220 static GTY(()) tree opaque_V2SF_type_node;
 221 static GTY(()) tree opaque_p_V2SI_type_node;
 222 static GTY(()) tree V16QI_type_node;
 223 static GTY(()) tree V2SI_type_node;
 224 static GTY(()) tree V2SF_type_node;
 225 static GTY(()) tree V4HI_type_node;
 226 static GTY(()) tree V4SI_type_node;
 227 static GTY(()) tree V4SF_type_node;
 228 static GTY(()) tree V8HI_type_node;
 229 static GTY(()) tree unsigned_V16QI_type_node;
 230 static GTY(()) tree unsigned_V8HI_type_node;
 231 static GTY(()) tree unsigned_V4SI_type_node;
 232 static GTY(()) tree bool_char_type_node;        /* __bool char */
 233 static GTY(()) tree bool_short_type_node;       /* __bool short */
 234 static GTY(()) tree bool_int_type_node;         /* __bool int */
 235 static GTY(()) tree pixel_type_node;            /* __pixel */
 236 static GTY(()) tree bool_V16QI_type_node;       /* __vector __bool char */
 237 static GTY(()) tree bool_V8HI_type_node;        /* __vector __bool short */
 238 static GTY(()) tree bool_V4SI_type_node;        /* __vector __bool int */
 239 static GTY(()) tree pixel_V8HI_type_node;       /* __vector __pixel */
 240
 241 int rs6000_warn_altivec_long = 1;               /* On by default. */
 242 const char *rs6000_warn_altivec_long_switch;
 243
 244 const char *rs6000_traceback_name;
 245 static enum {
 246   traceback_default = 0,
 247   traceback_none,
 248   traceback_part,
 249   traceback_full
 250 } rs6000_traceback;
 251
 252 /* Flag to say the TOC is initialized */
 253 int toc_initialized;
 254 char toc_label_name[10];
 255
 256 /* Alias set for saves and restores from the rs6000 stack.  */
 257 static GTY(()) int rs6000_sr_alias_set;
 258
 259 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
 260    The only place that looks at this is rs6000_set_default_type_attributes;
 261    everywhere else should rely on the presence or absence of a longcall
 262    attribute on the function declaration.  */
 263 int rs6000_default_long_calls;
 264 const char *rs6000_longcall_switch;
 265
 266 /* Control alignment for fields within structures.  */
 267 /* String from -malign-XXXXX.  */
 268 const char *rs6000_alignment_string;
 269 int rs6000_alignment_flags;
 270
 271 struct builtin_description
 272 {
 273   /* mask is not const because we're going to alter it below.  This
 274      nonsense will go away when we rewrite the -march infrastructure
 275      to give us more target flag bits.  */
 276   unsigned int mask;
 277   const enum insn_code icode;
 278   const char *const name;
 279   const enum rs6000_builtins code;
 280 };
 281
 282 static bool rs6000_function_ok_for_sibcall (tree, tree);
 283 static int num_insns_constant_wide (HOST_WIDE_INT);
 284 static void validate_condition_mode (enum rtx_code, enum machine_mode);
 285 static rtx rs6000_generate_compare (enum rtx_code);
 286 static void rs6000_maybe_dead (rtx);
 287 static void rs6000_emit_stack_tie (void);
 288 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
 289 static rtx spe_synthesize_frame_save (rtx);
 290 static bool spe_func_has_64bit_regs_p (void);
 291 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
 292                              int, HOST_WIDE_INT);
 293 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
 294 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
 295 static unsigned rs6000_hash_constant (rtx);
 296 static unsigned toc_hash_function (const void *);
 297 static int toc_hash_eq (const void *, const void *);
 298 static int constant_pool_expr_1 (rtx, int *, int *);
 299 static bool constant_pool_expr_p (rtx);
 300 static bool toc_relative_expr_p (rtx);
 301 static bool legitimate_small_data_p (enum machine_mode, rtx);
 302 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
 303 static bool legitimate_indexed_address_p (rtx, int);
 304 static bool legitimate_indirect_address_p (rtx, int);
 305 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
 306 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
 307 static struct machine_function * rs6000_init_machine_status (void);
 308 static bool rs6000_assemble_integer (rtx, unsigned int, int);
 309 #ifdef HAVE_GAS_HIDDEN
 310 static void rs6000_assemble_visibility (tree, int);
 311 #endif
 312 static int rs6000_ra_ever_killed (void);
 313 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
 314 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
 315 static const char *rs6000_mangle_fundamental_type (tree);
 316 extern const struct attribute_spec rs6000_attribute_table[];
 317 static void rs6000_set_default_type_attributes (tree);
 318 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
 319 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
 320 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
 321                                     tree);
 322 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 323 static bool rs6000_return_in_memory (tree, tree);
 324 static void rs6000_file_start (void);
 325 #if TARGET_ELF
 326 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
 327 static void rs6000_elf_asm_out_constructor (rtx, int);
 328 static void rs6000_elf_asm_out_destructor (rtx, int);
 329 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
 330 static void rs6000_elf_unique_section (tree, int);
 331 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
 332                                            unsigned HOST_WIDE_INT);
 333 static void rs6000_elf_encode_section_info (tree, rtx, int)
 334      ATTRIBUTE_UNUSED;
 335 static bool rs6000_elf_in_small_data_p (tree);
 336 #endif
 337 #if TARGET_XCOFF
 338 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
 339 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
 340 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
 341 static void rs6000_xcoff_unique_section (tree, int);
 342 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
 343                                              unsigned HOST_WIDE_INT);
 344 static const char * rs6000_xcoff_strip_name_encoding (const char *);
 345 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
 346 static void rs6000_xcoff_file_start (void);
 347 static void rs6000_xcoff_file_end (void);
 348 #endif
 349 #if TARGET_MACHO
 350 static bool rs6000_binds_local_p (tree);
 351 #endif
 352 static int rs6000_use_dfa_pipeline_interface (void);
 353 static int rs6000_variable_issue (FILE *, int, rtx, int);
 354 static bool rs6000_rtx_costs (rtx, int, int, int *);
 355 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
 356 static bool is_microcoded_insn (rtx);
 357 static int is_dispatch_slot_restricted (rtx);
 358 static bool is_cracked_insn (rtx);
 359 static bool is_branch_slot_insn (rtx);
 360 static int rs6000_adjust_priority (rtx, int);
 361 static int rs6000_issue_rate (void);
 362 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
 363 static rtx get_next_active_insn (rtx, rtx);
 364 static bool insn_terminates_group_p (rtx , enum group_termination);
 365 static bool is_costly_group (rtx *, rtx);
 366 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
 367 static int redefine_groups (FILE *, int, rtx, rtx);
 368 static int pad_groups (FILE *, int, rtx, rtx);
 369 static void rs6000_sched_finish (FILE *, int);
 370 static int rs6000_use_sched_lookahead (void);
 371
 372 static void rs6000_init_builtins (void);
 373 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
 374 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
 375 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
 376 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
 377 static void altivec_init_builtins (void);
 378 static void rs6000_common_init_builtins (void);
 379 static void rs6000_init_libfuncs (void);
 380
 381 static void enable_mask_for_builtins (struct builtin_description *, int,
 382                                       enum rs6000_builtins,
 383                                       enum rs6000_builtins);
 384 static void spe_init_builtins (void);
 385 static rtx spe_expand_builtin (tree, rtx, bool *);
 386 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
 387 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
 388 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
 389 static rs6000_stack_t *rs6000_stack_info (void);
 390 static void debug_stack_info (rs6000_stack_t *);
 391
 392 static rtx altivec_expand_builtin (tree, rtx, bool *);
 393 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
 394 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
 395 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
 396 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
 397 static rtx altivec_expand_predicate_builtin (enum insn_code,
 398                                             const char *, tree, rtx);
 399 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
 400 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
 401 static void rs6000_parse_abi_options (void);
 402 static void rs6000_parse_alignment_option (void);
 403 static void rs6000_parse_tls_size_option (void);
 404 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
 405 static int first_altivec_reg_to_save (void);
 406 static unsigned int compute_vrsave_mask (void);
 407 static void is_altivec_return_reg (rtx, void *);
 408 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
 409 int easy_vector_constant (rtx, enum machine_mode);
 410 static int easy_vector_same (rtx, enum machine_mode);
 411 static int easy_vector_splat_const (int, enum machine_mode);
 412 static bool is_ev64_opaque_type (tree);
 413 static rtx rs6000_dwarf_register_span (rtx);
 414 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
 415 static rtx rs6000_tls_get_addr (void);
 416 static rtx rs6000_got_sym (void);
 417 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
 418 static const char *rs6000_get_some_local_dynamic_name (void);
 419 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
 420 static rtx rs6000_complex_function_value (enum machine_mode);
 421 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
 422                                     enum machine_mode, tree);
 423 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
 424                                       enum machine_mode, tree, int);
 425 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
 426 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
 427                                     enum machine_mode, tree,
 428                                     int *, int);
 429 #if TARGET_MACHO
 430 static void macho_branch_islands (void);
 431 static void add_compiler_branch_island (tree, tree, int);
 432 static int no_previous_def (tree function_name);
 433 static tree get_prev_label (tree function_name);
 434 #endif
 435
 436 static tree rs6000_build_builtin_va_list (void);
 437
 438 /* Hash table stuff for keeping track of TOC entries.  */
 439
 440 struct toc_hash_struct GTY(())
 441 {
 442   /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
 443      ASM_OUTPUT_SPECIAL_POOL_ENTRY_P.  */
 444   rtx key;
 445   enum machine_mode key_mode;
 446   int labelno;
 447 };
 448
 449 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
 450 \f
 451 /* Default register names.  */
 452 char rs6000_reg_names[][8] =
 453 {
 454       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 455       "8",  "9", "10", "11", "12", "13", "14", "15",
 456      "16", "17", "18", "19", "20", "21", "22", "23",
 457      "24", "25", "26", "27", "28", "29", "30", "31",
 458       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 459       "8",  "9", "10", "11", "12", "13", "14", "15",
 460      "16", "17", "18", "19", "20", "21", "22", "23",
 461      "24", "25", "26", "27", "28", "29", "30", "31",
 462      "mq", "lr", "ctr","ap",
 463       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
 464       "xer",
 465       /* AltiVec registers.  */
 466       "0",  "1",  "2",  "3",  "4",  "5",  "6", "7",
 467       "8",  "9",  "10", "11", "12", "13", "14", "15",
 468       "16", "17", "18", "19", "20", "21", "22", "23",
 469       "24", "25", "26", "27", "28", "29", "30", "31",
 470       "vrsave", "vscr",
 471       /* SPE registers.  */
 472       "spe_acc", "spefscr"
 473 };
 474
 475 #ifdef TARGET_REGNAMES
 476 static const char alt_reg_names[][8] =
 477 {
 478    "%r0",   "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
 479    "%r8",   "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
 480   "%r16",  "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
 481   "%r24",  "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
 482    "%f0",   "%f1",  "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
 483    "%f8",   "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
 484   "%f16",  "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
 485   "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
 486     "mq",    "lr",  "ctr",   "ap",
 487   "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
 488    "xer",
 489   /* AltiVec registers.  */
 490    "%v0",  "%v1",  "%v2",  "%v3",  "%v4",  "%v5",  "%v6", "%v7",
 491    "%v8",  "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
 492   "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
 493   "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
 494   "vrsave", "vscr",
 495   /* SPE registers.  */
 496   "spe_acc", "spefscr"
 497 };
 498 #endif
 499 \f
 500 #ifndef MASK_STRICT_ALIGN
 501 #define MASK_STRICT_ALIGN 0
 502 #endif
 503 #ifndef TARGET_PROFILE_KERNEL
 504 #define TARGET_PROFILE_KERNEL 0
 505 #endif
 506
 507 /* The VRSAVE bitmask puts bit %v0 as the most significant bit.  */
 508 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
 509
 510 /* Return 1 for a symbol ref for a thread-local storage symbol.  */
 511 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
 512   (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
 513 \f
 514 /* Initialize the GCC target structure.  */
 515 #undef TARGET_ATTRIBUTE_TABLE
 516 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
 517 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
 518 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
 519
 520 #undef TARGET_ASM_ALIGNED_DI_OP
 521 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
 522
 523 /* Default unaligned ops are only provided for ELF.  Find the ops needed
 524    for non-ELF systems.  */
 525 #ifndef OBJECT_FORMAT_ELF
 526 #if TARGET_XCOFF
 527 /* For XCOFF.  rs6000_assemble_integer will handle unaligned DIs on
 528    64-bit targets.  */
 529 #undef TARGET_ASM_UNALIGNED_HI_OP
 530 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
 531 #undef TARGET_ASM_UNALIGNED_SI_OP
 532 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
 533 #undef TARGET_ASM_UNALIGNED_DI_OP
 534 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
 535 #else
 536 /* For Darwin.  */
 537 #undef TARGET_ASM_UNALIGNED_HI_OP
 538 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
 539 #undef TARGET_ASM_UNALIGNED_SI_OP
 540 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
 541 #endif
 542 #endif
 543
 544 /* This hook deals with fixups for relocatable code and DI-mode objects
 545    in 64-bit code.  */
 546 #undef TARGET_ASM_INTEGER
 547 #define TARGET_ASM_INTEGER rs6000_assemble_integer
 548
 549 #ifdef HAVE_GAS_HIDDEN
 550 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
 551 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
 552 #endif
 553
 554 #undef TARGET_HAVE_TLS
 555 #define TARGET_HAVE_TLS HAVE_AS_TLS
 556
 557 #undef TARGET_CANNOT_FORCE_CONST_MEM
 558 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
 559
 560 #undef TARGET_ASM_FUNCTION_PROLOGUE
 561 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
 562 #undef TARGET_ASM_FUNCTION_EPILOGUE
 563 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
 564
 565 #undef  TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
 566 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
 567 #undef  TARGET_SCHED_VARIABLE_ISSUE
 568 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
 569
 570 #undef TARGET_SCHED_ISSUE_RATE
 571 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
 572 #undef TARGET_SCHED_ADJUST_COST
 573 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
 574 #undef TARGET_SCHED_ADJUST_PRIORITY
 575 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
 576 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
 577 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
 578 #undef TARGET_SCHED_FINISH
 579 #define TARGET_SCHED_FINISH rs6000_sched_finish
 580
 581 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
 582 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
 583
 584 #undef TARGET_INIT_BUILTINS
 585 #define TARGET_INIT_BUILTINS rs6000_init_builtins
 586
 587 #undef TARGET_EXPAND_BUILTIN
 588 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
 589
 590 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
 591 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
 592
 593 #undef TARGET_INIT_LIBFUNCS
 594 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
 595
 596 #if TARGET_MACHO
 597 #undef TARGET_BINDS_LOCAL_P
 598 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
 599 #endif
 600
 601 #undef TARGET_ASM_OUTPUT_MI_THUNK
 602 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
 603
 604 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
 605 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
 606
 607 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 608 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
 609
 610 #undef TARGET_RTX_COSTS
 611 #define TARGET_RTX_COSTS rs6000_rtx_costs
 612 #undef TARGET_ADDRESS_COST
 613 #define TARGET_ADDRESS_COST hook_int_rtx_0
 614
 615 #undef TARGET_VECTOR_OPAQUE_P
 616 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
 617
 618 #undef TARGET_DWARF_REGISTER_SPAN
 619 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
 620
 621 /* On rs6000, function arguments are promoted, as are function return
 622    values.  */
 623 #undef TARGET_PROMOTE_FUNCTION_ARGS
 624 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
 625 #undef TARGET_PROMOTE_FUNCTION_RETURN
 626 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
 627
 628 #undef TARGET_RETURN_IN_MEMORY
 629 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
 630
 631 #undef TARGET_SETUP_INCOMING_VARARGS
 632 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
 633
 634 /* Always strict argument naming on rs6000.  */
 635 #undef TARGET_STRICT_ARGUMENT_NAMING
 636 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
 637 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
 638 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
 639 #undef TARGET_SPLIT_COMPLEX_ARG
 640 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
 641
 642 #undef TARGET_BUILD_BUILTIN_VA_LIST
 643 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
 644
 645 struct gcc_target targetm = TARGET_INITIALIZER;
 646 \f
 647 /* Override command line options.  Mostly we process the processor
 648    type and sometimes adjust other TARGET_ options.  */
 649
 650 void
 651 rs6000_override_options (const char *default_cpu)
 652 {
 653   size_t i, j;
 654   struct rs6000_cpu_select *ptr;
 655   int set_masks;
 656
 657   /* Simplifications for entries below.  */
 658
 659   enum {
 660     POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
 661     POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
 662   };
 663
 664   /* This table occasionally claims that a processor does not support
 665      a particular feature even though it does, but the feature is slower
 666      than the alternative.  Thus, it shouldn't be relied on as a
 667      complete description of the processor's support.
 668
 669      Please keep this list in order, and don't forget to update the
 670      documentation in invoke.texi when adding a new processor or
 671      flag.  */
 672   static struct ptt
 673     {
 674       const char *const name;           /* Canonical processor name.  */
 675       const enum processor_type processor; /* Processor type enum value.  */
 676       const int target_enable;  /* Target flags to enable.  */
 677     } const processor_target_table[]
 678       = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 679          {"403", PROCESSOR_PPC403,
 680           POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
 681          {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 682          {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
 683          {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 684          {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
 685          {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
 686          {"601", PROCESSOR_PPC601,
 687           MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
 688          {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 689          {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 690          {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 691          {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 692          {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 693          {"620", PROCESSOR_PPC620,
 694           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 695          {"630", PROCESSOR_PPC630,
 696           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 697          {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 698          {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
 699          {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
 700          {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 701          {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 702          {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 703          {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 704          {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 705          {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 706          {"970", PROCESSOR_POWER4,
 707           POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
 708          {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
 709          {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
 710          {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
 711          {"G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK},
 712          {"G5", PROCESSOR_POWER4,
 713           POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
 714          {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 715          {"power2", PROCESSOR_POWER,
 716           MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
 717          {"power3", PROCESSOR_PPC630,
 718           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
 719          {"power4", PROCESSOR_POWER4,
 720           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
 721          {"power5", PROCESSOR_POWER5,
 722           POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
 723          {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
 724          {"powerpc64", PROCESSOR_POWERPC64,
 725           POWERPC_BASE_MASK | MASK_POWERPC64},
 726          {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 727          {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 728          {"rios2", PROCESSOR_RIOS2,
 729           MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
 730          {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 731          {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
 732          {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
 733       };
 734
 735   const size_t ptt_size = ARRAY_SIZE (processor_target_table);
 736
 737   /* Some OSs don't support saving the high part of 64-bit registers on
 738      context switch.  Other OSs don't support saving Altivec registers.
 739      On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
 740      settings; if the user wants either, the user must explicitly specify
 741      them and we won't interfere with the user's specification.  */
 742
 743   enum {
 744     POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
 745     POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
 746                      | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
 747                      | MASK_MFCRF)
 748   };
 749  set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
 750 #ifdef OS_MISSING_POWERPC64
 751   if (OS_MISSING_POWERPC64)
 752     set_masks &= ~MASK_POWERPC64;
 753 #endif
 754 #ifdef OS_MISSING_ALTIVEC
 755   if (OS_MISSING_ALTIVEC)
 756     set_masks &= ~MASK_ALTIVEC;
 757 #endif
 758
 759   /* Don't override these by the processor default if given explicitly.  */
 760   set_masks &= ~(target_flags_explicit
 761                  & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
 762
 763   /* Identify the processor type.  */
 764   rs6000_select[0].string = default_cpu;
 765   rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
 766
 767   for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
 768     {
 769       ptr = &rs6000_select[i];
 770       if (ptr->string != (char *)0 && ptr->string[0] != '\0')
 771         {
 772           for (j = 0; j < ptt_size; j++)
 773             if (! strcmp (ptr->string, processor_target_table[j].name))
 774               {
 775                 if (ptr->set_tune_p)
 776                   rs6000_cpu = processor_target_table[j].processor;
 777
 778                 if (ptr->set_arch_p)
 779                   {
 780                     target_flags &= ~set_masks;
 781                     target_flags |= (processor_target_table[j].target_enable
 782                                      & set_masks);
 783                   }
 784                 break;
 785               }
 786
 787           if (j == ptt_size)
 788             error ("bad value (%s) for %s switch", ptr->string, ptr->name);
 789         }
 790     }
 791
 792   if (TARGET_E500)
 793     rs6000_isel = 1;
 794
 795   /* If we are optimizing big endian systems for space, use the load/store
 796      multiple and string instructions.  */
 797   if (BYTES_BIG_ENDIAN && optimize_size)
 798     target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
 799
 800   /* Don't allow -mmultiple or -mstring on little endian systems
 801      unless the cpu is a 750, because the hardware doesn't support the
 802      instructions used in little endian mode, and causes an alignment
 803      trap.  The 750 does not cause an alignment trap (except when the
 804      target is unaligned).  */
 805
 806   if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
 807     {
 808       if (TARGET_MULTIPLE)
 809         {
 810           target_flags &= ~MASK_MULTIPLE;
 811           if ((target_flags_explicit & MASK_MULTIPLE) != 0)
 812             warning ("-mmultiple is not supported on little endian systems");
 813         }
 814
 815       if (TARGET_STRING)
 816         {
 817           target_flags &= ~MASK_STRING;
 818           if ((target_flags_explicit & MASK_STRING) != 0)
 819             warning ("-mstring is not supported on little endian systems");
 820         }
 821     }
 822
 823   /* Set debug flags */
 824   if (rs6000_debug_name)
 825     {
 826       if (! strcmp (rs6000_debug_name, "all"))
 827         rs6000_debug_stack = rs6000_debug_arg = 1;
 828       else if (! strcmp (rs6000_debug_name, "stack"))
 829         rs6000_debug_stack = 1;
 830       else if (! strcmp (rs6000_debug_name, "arg"))
 831         rs6000_debug_arg = 1;
 832       else
 833         error ("unknown -mdebug-%s switch", rs6000_debug_name);
 834     }
 835
 836   if (rs6000_traceback_name)
 837     {
 838       if (! strncmp (rs6000_traceback_name, "full", 4))
 839         rs6000_traceback = traceback_full;
 840       else if (! strncmp (rs6000_traceback_name, "part", 4))
 841         rs6000_traceback = traceback_part;
 842       else if (! strncmp (rs6000_traceback_name, "no", 2))
 843         rs6000_traceback = traceback_none;
 844       else
 845         error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
 846                rs6000_traceback_name);
 847     }
 848
 849   /* Set size of long double */
 850   rs6000_long_double_type_size = 64;
 851   if (rs6000_long_double_size_string)
 852     {
 853       char *tail;
 854       int size = strtol (rs6000_long_double_size_string, &tail, 10);
 855       if (*tail != '\0' || (size != 64 && size != 128))
 856         error ("Unknown switch -mlong-double-%s",
 857                rs6000_long_double_size_string);
 858       else
 859         rs6000_long_double_type_size = size;
 860     }
 861
 862   /* Set Altivec ABI as default for powerpc64 linux.  */
 863   if (TARGET_ELF && TARGET_64BIT)
 864     {
 865       rs6000_altivec_abi = 1;
 866       rs6000_altivec_vrsave = 1;
 867     }
 868
 869   /* Handle -mabi= options.  */
 870   rs6000_parse_abi_options ();
 871
 872   /* Handle -malign-XXXXX option.  */
 873   rs6000_parse_alignment_option ();
 874
 875   /* Handle generic -mFOO=YES/NO options.  */
 876   rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
 877                               &rs6000_altivec_vrsave);
 878   rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
 879                               &rs6000_isel);
 880   rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
 881   rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
 882                               &rs6000_float_gprs);
 883
 884   /* Handle -mtls-size option.  */
 885   rs6000_parse_tls_size_option ();
 886
 887 #ifdef SUBTARGET_OVERRIDE_OPTIONS
 888   SUBTARGET_OVERRIDE_OPTIONS;
 889 #endif
 890 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
 891   SUBSUBTARGET_OVERRIDE_OPTIONS;
 892 #endif
 893
 894   if (TARGET_E500)
 895     {
 896       /* The e500 does not have string instructions, and we set
 897          MASK_STRING above when optimizing for size.  */
 898       if ((target_flags & MASK_STRING) != 0)
 899         target_flags = target_flags & ~MASK_STRING;
 900
 901       /* No SPE means 64-bit long doubles, even if an E500.  */
 902       if (rs6000_spe_string != 0
 903           && !strcmp (rs6000_spe_string, "no"))
 904         rs6000_long_double_type_size = 64;
 905     }
 906   else if (rs6000_select[1].string != NULL)
 907     {
 908       /* For the powerpc-eabispe configuration, we set all these by
 909          default, so let's unset them if we manually set another
 910          CPU that is not the E500.  */
 911       if (rs6000_abi_string == 0)
 912         rs6000_spe_abi = 0;
 913       if (rs6000_spe_string == 0)
 914         rs6000_spe = 0;
 915       if (rs6000_float_gprs_string == 0)
 916         rs6000_float_gprs = 0;
 917       if (rs6000_isel_string == 0)
 918         rs6000_isel = 0;
 919       if (rs6000_long_double_size_string == 0)
 920         rs6000_long_double_type_size = 64;
 921     }
 922
 923   rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
 924                         && rs6000_cpu != PROCESSOR_POWER5);
 925   rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
 926                          || rs6000_cpu == PROCESSOR_POWER5);
 927
 928   /* Handle -m(no-)longcall option.  This is a bit of a cheap hack,
 929      using TARGET_OPTIONS to handle a toggle switch, but we're out of
 930      bits in target_flags so TARGET_SWITCHES cannot be used.
 931      Assumption here is that rs6000_longcall_switch points into the
 932      text of the complete option, rather than being a copy, so we can
 933      scan back for the presence or absence of the no- modifier.  */
 934   if (rs6000_longcall_switch)
 935     {
 936       const char *base = rs6000_longcall_switch;
 937       while (base[-1] != 'm') base--;
 938
 939       if (*rs6000_longcall_switch != '\0')
 940         error ("invalid option `%s'", base);
 941       rs6000_default_long_calls = (base[0] != 'n');
 942     }
 943
 944   /* Handle -m(no-)warn-altivec-long similarly.  */
 945   if (rs6000_warn_altivec_long_switch)
 946     {
 947       const char *base = rs6000_warn_altivec_long_switch;
 948       while (base[-1] != 'm') base--;
 949
 950       if (*rs6000_warn_altivec_long_switch != '\0')
 951         error ("invalid option `%s'", base);
 952       rs6000_warn_altivec_long = (base[0] != 'n');
 953     }
 954
 955   /* Handle -mprioritize-restricted-insns option.  */
 956   rs6000_sched_restricted_insns_priority
 957     = (rs6000_sched_groups ? 1 : 0);
 958   if (rs6000_sched_restricted_insns_priority_str)
 959     rs6000_sched_restricted_insns_priority =
 960       atoi (rs6000_sched_restricted_insns_priority_str);
 961
 962   /* Handle -msched-costly-dep option.  */
 963   rs6000_sched_costly_dep
 964     = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
 965   if (rs6000_sched_costly_dep_str)
 966     {
 967       if (! strcmp (rs6000_sched_costly_dep_str, "no"))
 968         rs6000_sched_costly_dep = no_dep_costly;
 969       else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
 970         rs6000_sched_costly_dep = all_deps_costly;
 971       else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
 972         rs6000_sched_costly_dep = true_store_to_load_dep_costly;
 973       else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
 974         rs6000_sched_costly_dep = store_to_load_dep_costly;
 975       else
 976         rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
 977     }
 978
 979   /* Handle -minsert-sched-nops option.  */
 980   rs6000_sched_insert_nops
 981     = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
 982   if (rs6000_sched_insert_nops_str)
 983     {
 984       if (! strcmp (rs6000_sched_insert_nops_str, "no"))
 985         rs6000_sched_insert_nops = sched_finish_none;
 986       else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
 987         rs6000_sched_insert_nops = sched_finish_pad_groups;
 988       else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
 989         rs6000_sched_insert_nops = sched_finish_regroup_exact;
 990       else
 991         rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
 992     }
 993
 994 #ifdef TARGET_REGNAMES
 995   /* If the user desires alternate register names, copy in the
 996      alternate names now.  */
 997   if (TARGET_REGNAMES)
 998     memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
 999 #endif
1000
1001   /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1002      If -maix-struct-return or -msvr4-struct-return was explicitly
1003      used, don't override with the ABI default.  */
1004   if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1005     {
1006       if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1007         target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1008       else
1009         target_flags |= MASK_AIX_STRUCT_RET;
1010     }
1011
1012   if (TARGET_LONG_DOUBLE_128
1013       && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1014     REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1015
1016   /* Allocate an alias set for register saves & restores from stack.  */
1017   rs6000_sr_alias_set = new_alias_set ();
1018
1019   if (TARGET_TOC)
1020     ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1021
1022   /* We can only guarantee the availability of DI pseudo-ops when
1023      assembling for 64-bit targets.  */
1024   if (!TARGET_64BIT)
1025     {
1026       targetm.asm_out.aligned_op.di = NULL;
1027       targetm.asm_out.unaligned_op.di = NULL;
1028     }
1029
1030   /* Set maximum branch target alignment at two instructions, eight bytes.  */
1031   align_jumps_max_skip = 8;
1032   align_loops_max_skip = 8;
1033
1034   /* Arrange to save and restore machine status around nested functions.  */
1035   init_machine_status = rs6000_init_machine_status;
1036
1037   /* We should always be splitting complex arguments, but we can't break
1038      Linux and Darwin ABIs at the moment.  For now, only AIX is fixed.  */
1039   if (DEFAULT_ABI != ABI_AIX)
1040     targetm.calls.split_complex_arg = NULL;
1041 }
1042
1043 /* Handle generic options of the form -mfoo=yes/no.
1044    NAME is the option name.
1045    VALUE is the option value.
1046    FLAG is the pointer to the flag where to store a 1 or 0, depending on
1047    whether the option value is 'yes' or 'no' respectively.  */
1048 static void
1049 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1050 {
1051   if (value == 0)
1052     return;
1053   else if (!strcmp (value, "yes"))
1054     *flag = 1;
1055   else if (!strcmp (value, "no"))
1056     *flag = 0;
1057   else
1058     error ("unknown -m%s= option specified: '%s'", name, value);
1059 }
1060
1061 /* Handle -mabi= options.  */
1062 static void
1063 rs6000_parse_abi_options (void)
1064 {
1065   if (rs6000_abi_string == 0)
1066     return;
1067   else if (! strcmp (rs6000_abi_string, "altivec"))
1068     {
1069       rs6000_altivec_abi = 1;
1070       rs6000_spe_abi = 0;
1071     }
1072   else if (! strcmp (rs6000_abi_string, "no-altivec"))
1073     rs6000_altivec_abi = 0;
1074   else if (! strcmp (rs6000_abi_string, "spe"))
1075     {
1076       rs6000_spe_abi = 1;
1077       rs6000_altivec_abi = 0;
1078       if (!TARGET_SPE_ABI)
1079         error ("not configured for ABI: '%s'", rs6000_abi_string);
1080     }
1081
1082   else if (! strcmp (rs6000_abi_string, "no-spe"))
1083     rs6000_spe_abi = 0;
1084   else
1085     error ("unknown ABI specified: '%s'", rs6000_abi_string);
1086 }
1087
1088 /* Handle -malign-XXXXXX options.  */
1089 static void
1090 rs6000_parse_alignment_option (void)
1091 {
1092   if (rs6000_alignment_string == 0)
1093     return;
1094   else if (! strcmp (rs6000_alignment_string, "power"))
1095     rs6000_alignment_flags = MASK_ALIGN_POWER;
1096   else if (! strcmp (rs6000_alignment_string, "natural"))
1097     rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1098   else
1099     error ("unknown -malign-XXXXX option specified: '%s'",
1100            rs6000_alignment_string);
1101 }
1102
1103 /* Validate and record the size specified with the -mtls-size option.  */
1104
1105 static void
1106 rs6000_parse_tls_size_option (void)
1107 {
1108   if (rs6000_tls_size_string == 0)
1109     return;
1110   else if (strcmp (rs6000_tls_size_string, "16") == 0)
1111     rs6000_tls_size = 16;
1112   else if (strcmp (rs6000_tls_size_string, "32") == 0)
1113     rs6000_tls_size = 32;
1114   else if (strcmp (rs6000_tls_size_string, "64") == 0)
1115     rs6000_tls_size = 64;
1116   else
1117     error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1118 }
1119
1120 void
1121 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1122 {
1123 }
1124 \f
1125 /* Do anything needed at the start of the asm file.  */
1126
1127 static void
1128 rs6000_file_start (void)
1129 {
1130   size_t i;
1131   char buffer[80];
1132   const char *start = buffer;
1133   struct rs6000_cpu_select *ptr;
1134   const char *default_cpu = TARGET_CPU_DEFAULT;
1135   FILE *file = asm_out_file;
1136
1137   default_file_start ();
1138
1139 #ifdef TARGET_BI_ARCH
1140   if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1141     default_cpu = 0;
1142 #endif
1143
1144   if (flag_verbose_asm)
1145     {
1146       sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1147       rs6000_select[0].string = default_cpu;
1148
1149       for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1150         {
1151           ptr = &rs6000_select[i];
1152           if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1153             {
1154               fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1155               start = "";
1156             }
1157         }
1158
1159 #ifdef USING_ELFOS_H
1160       switch (rs6000_sdata)
1161         {
1162         case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1163         case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1164         case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1165         case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1166         }
1167
1168       if (rs6000_sdata && g_switch_value)
1169         {
1170           fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1171                    g_switch_value);
1172           start = "";
1173         }
1174 #endif
1175
1176       if (*start == '\0')
1177         putc ('\n', file);
1178     }
1179 }
1180 \f
1181 /* Return nonzero if this function is known to have a null epilogue.  */
1182
1183 int
1184 direct_return (void)
1185 {
1186   if (reload_completed)
1187     {
1188       rs6000_stack_t *info = rs6000_stack_info ();
1189
1190       if (info->first_gp_reg_save == 32
1191           && info->first_fp_reg_save == 64
1192           && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1193           && ! info->lr_save_p
1194           && ! info->cr_save_p
1195           && info->vrsave_mask == 0
1196           && ! info->push_p)
1197         return 1;
1198     }
1199
1200   return 0;
1201 }
1202
1203 /* Returns 1 always.  */
1204
1205 int
1206 any_operand (rtx op ATTRIBUTE_UNUSED,
1207              enum machine_mode mode ATTRIBUTE_UNUSED)
1208 {
1209   return 1;
1210 }
1211
1212 /* Returns 1 if op is the count register.  */
1213 int
1214 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1215 {
1216   if (GET_CODE (op) != REG)
1217     return 0;
1218
1219   if (REGNO (op) == COUNT_REGISTER_REGNUM)
1220     return 1;
1221
1222   if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1223     return 1;
1224
1225   return 0;
1226 }
1227
1228 /* Returns 1 if op is an altivec register.  */
1229 int
1230 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1231 {
1232
1233   return (register_operand (op, mode)
1234           && (GET_CODE (op) != REG
1235               || REGNO (op) > FIRST_PSEUDO_REGISTER
1236               || ALTIVEC_REGNO_P (REGNO (op))));
1237 }
1238
1239 int
1240 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1241 {
1242   if (GET_CODE (op) != REG)
1243     return 0;
1244
1245   if (XER_REGNO_P (REGNO (op)))
1246     return 1;
1247
1248   return 0;
1249 }
1250
1251 /* Return 1 if OP is a signed 8-bit constant.  Int multiplication
1252    by such constants completes more quickly.  */
1253
1254 int
1255 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1256 {
1257   return ( GET_CODE (op) == CONST_INT
1258           && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1259 }
1260
1261 /* Return 1 if OP is a constant that can fit in a D field.  */
1262
1263 int
1264 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1265 {
1266   return (GET_CODE (op) == CONST_INT
1267           && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1268 }
1269
1270 /* Similar for an unsigned D field.  */
1271
1272 int
1273 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1274 {
1275   return (GET_CODE (op) == CONST_INT
1276           && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1277 }
1278
1279 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
1280
1281 int
1282 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1283 {
1284   return (GET_CODE (op) == CONST_INT
1285           && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1286 }
1287
1288 /* Returns 1 if OP is a CONST_INT that is a positive value
1289    and an exact power of 2.  */
1290
1291 int
1292 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1293 {
1294   return (GET_CODE (op) == CONST_INT
1295           && INTVAL (op) > 0
1296           && exact_log2 (INTVAL (op)) >= 0);
1297 }
1298
1299 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1300    ctr, or lr).  */
1301
1302 int
1303 gpc_reg_operand (rtx op, enum machine_mode mode)
1304 {
1305   return (register_operand (op, mode)
1306           && (GET_CODE (op) != REG
1307               || (REGNO (op) >= ARG_POINTER_REGNUM
1308                   && !XER_REGNO_P (REGNO (op)))
1309               || REGNO (op) < MQ_REGNO));
1310 }
1311
1312 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1313    CR field.  */
1314
1315 int
1316 cc_reg_operand (rtx op, enum machine_mode mode)
1317 {
1318   return (register_operand (op, mode)
1319           && (GET_CODE (op) != REG
1320               || REGNO (op) >= FIRST_PSEUDO_REGISTER
1321               || CR_REGNO_P (REGNO (op))));
1322 }
1323
1324 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1325    CR field that isn't CR0.  */
1326
1327 int
1328 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1329 {
1330   return (register_operand (op, mode)
1331           && (GET_CODE (op) != REG
1332               || REGNO (op) >= FIRST_PSEUDO_REGISTER
1333               || CR_REGNO_NOT_CR0_P (REGNO (op))));
1334 }
1335
1336 /* Returns 1 if OP is either a constant integer valid for a D-field or
1337    a non-special register.  If a register, it must be in the proper
1338    mode unless MODE is VOIDmode.  */
1339
1340 int
1341 reg_or_short_operand (rtx op, enum machine_mode mode)
1342 {
1343   return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1344 }
1345
1346 /* Similar, except check if the negation of the constant would be
1347    valid for a D-field.  */
1348
1349 int
1350 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1351 {
1352   if (GET_CODE (op) == CONST_INT)
1353     return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1354
1355   return gpc_reg_operand (op, mode);
1356 }
1357
1358 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1359    a non-special register.  If a register, it must be in the proper
1360    mode unless MODE is VOIDmode.  */
1361
1362 int
1363 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1364 {
1365   if (gpc_reg_operand (op, mode))
1366     return 1;
1367   else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1368     return 1;
1369
1370   return 0;
1371 }
1372
1373
1374 /* Return 1 if the operand is either a register or an integer whose
1375    high-order 16 bits are zero.  */
1376
1377 int
1378 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1379 {
1380   return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1381 }
1382
1383 /* Return 1 is the operand is either a non-special register or ANY
1384    constant integer.  */
1385
1386 int
1387 reg_or_cint_operand (rtx op, enum machine_mode mode)
1388 {
1389   return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1390 }
1391
1392 /* Return 1 is the operand is either a non-special register or ANY
1393    32-bit signed constant integer.  */
1394
1395 int
1396 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1397 {
1398   return (gpc_reg_operand (op, mode)
1399           || (GET_CODE (op) == CONST_INT
1400 #if HOST_BITS_PER_WIDE_INT != 32
1401               && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1402                   < (unsigned HOST_WIDE_INT) 0x100000000ll)
1403 #endif
1404               ));
1405 }
1406
1407 /* Return 1 is the operand is either a non-special register or a 32-bit
1408    signed constant integer valid for 64-bit addition.  */
1409
1410 int
1411 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1412 {
1413   return (gpc_reg_operand (op, mode)
1414           || (GET_CODE (op) == CONST_INT
1415 #if HOST_BITS_PER_WIDE_INT == 32
1416               && INTVAL (op) < 0x7fff8000
1417 #else
1418               && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1419                   < 0x100000000ll)
1420 #endif
1421               ));
1422 }
1423
1424 /* Return 1 is the operand is either a non-special register or a 32-bit
1425    signed constant integer valid for 64-bit subtraction.  */
1426
1427 int
1428 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1429 {
1430   return (gpc_reg_operand (op, mode)
1431           || (GET_CODE (op) == CONST_INT
1432 #if HOST_BITS_PER_WIDE_INT == 32
1433               && (- INTVAL (op)) < 0x7fff8000
1434 #else
1435               && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1436                   < 0x100000000ll)
1437 #endif
1438               ));
1439 }
1440
1441 /* Return 1 is the operand is either a non-special register or ANY
1442    32-bit unsigned constant integer.  */
1443
1444 int
1445 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1446 {
1447   if (GET_CODE (op) == CONST_INT)
1448     {
1449       if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1450         {
1451           if (GET_MODE_BITSIZE (mode) <= 32)
1452             abort ();
1453
1454           if (INTVAL (op) < 0)
1455             return 0;
1456         }
1457
1458       return ((INTVAL (op) & GET_MODE_MASK (mode)
1459                & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1460     }
1461   else if (GET_CODE (op) == CONST_DOUBLE)
1462     {
1463       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1464           || mode != DImode)
1465         abort ();
1466
1467       return CONST_DOUBLE_HIGH (op) == 0;
1468     }
1469   else
1470     return gpc_reg_operand (op, mode);
1471 }
1472
1473 /* Return 1 if the operand is an operand that can be loaded via the GOT.  */
1474
1475 int
1476 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1477 {
1478   return (GET_CODE (op) == SYMBOL_REF
1479           || GET_CODE (op) == CONST
1480           || GET_CODE (op) == LABEL_REF);
1481 }
1482
1483 /* Return 1 if the operand is a simple references that can be loaded via
1484    the GOT (labels involving addition aren't allowed).  */
1485
1486 int
1487 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1488 {
1489   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1490 }
1491
1492 /* Return the number of instructions it takes to form a constant in an
1493    integer register.  */
1494
1495 static int
1496 num_insns_constant_wide (HOST_WIDE_INT value)
1497 {
1498   /* signed constant loadable with {cal|addi} */
1499   if (CONST_OK_FOR_LETTER_P (value, 'I'))
1500     return 1;
1501
1502   /* constant loadable with {cau|addis} */
1503   else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1504     return 1;
1505
1506 #if HOST_BITS_PER_WIDE_INT == 64
1507   else if (TARGET_POWERPC64)
1508     {
1509       HOST_WIDE_INT low  = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1510       HOST_WIDE_INT high = value >> 31;
1511
1512       if (high == 0 || high == -1)
1513         return 2;
1514
1515       high >>= 1;
1516
1517       if (low == 0)
1518         return num_insns_constant_wide (high) + 1;
1519       else
1520         return (num_insns_constant_wide (high)
1521                 + num_insns_constant_wide (low) + 1);
1522     }
1523 #endif
1524
1525   else
1526     return 2;
1527 }
1528
1529 int
1530 num_insns_constant (rtx op, enum machine_mode mode)
1531 {
1532   if (GET_CODE (op) == CONST_INT)
1533     {
1534 #if HOST_BITS_PER_WIDE_INT == 64
1535       if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1536           && mask64_operand (op, mode))
1537             return 2;
1538       else
1539 #endif
1540         return num_insns_constant_wide (INTVAL (op));
1541     }
1542
1543   else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1544     {
1545       long l;
1546       REAL_VALUE_TYPE rv;
1547
1548       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1549       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1550       return num_insns_constant_wide ((HOST_WIDE_INT) l);
1551     }
1552
1553   else if (GET_CODE (op) == CONST_DOUBLE)
1554     {
1555       HOST_WIDE_INT low;
1556       HOST_WIDE_INT high;
1557       long l[2];
1558       REAL_VALUE_TYPE rv;
1559       int endian = (WORDS_BIG_ENDIAN == 0);
1560
1561       if (mode == VOIDmode || mode == DImode)
1562         {
1563           high = CONST_DOUBLE_HIGH (op);
1564           low  = CONST_DOUBLE_LOW (op);
1565         }
1566       else
1567         {
1568           REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1569           REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1570           high = l[endian];
1571           low  = l[1 - endian];
1572         }
1573
1574       if (TARGET_32BIT)
1575         return (num_insns_constant_wide (low)
1576                 + num_insns_constant_wide (high));
1577
1578       else
1579         {
1580           if (high == 0 && low >= 0)
1581             return num_insns_constant_wide (low);
1582
1583           else if (high == -1 && low < 0)
1584             return num_insns_constant_wide (low);
1585
1586           else if (mask64_operand (op, mode))
1587             return 2;
1588
1589           else if (low == 0)
1590             return num_insns_constant_wide (high) + 1;
1591
1592           else
1593             return (num_insns_constant_wide (high)
1594                     + num_insns_constant_wide (low) + 1);
1595         }
1596     }
1597
1598   else
1599     abort ();
1600 }
1601
1602 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1603    register with one instruction per word.  We only do this if we can
1604    safely read CONST_DOUBLE_{LOW,HIGH}.  */
1605
1606 int
1607 easy_fp_constant (rtx op, enum machine_mode mode)
1608 {
1609   if (GET_CODE (op) != CONST_DOUBLE
1610       || GET_MODE (op) != mode
1611       || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1612     return 0;
1613
1614   /* Consider all constants with -msoft-float to be easy.  */
1615   if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1616       && mode != DImode)
1617     return 1;
1618
1619   /* If we are using V.4 style PIC, consider all constants to be hard.  */
1620   if (flag_pic && DEFAULT_ABI == ABI_V4)
1621     return 0;
1622
1623 #ifdef TARGET_RELOCATABLE
1624   /* Similarly if we are using -mrelocatable, consider all constants
1625      to be hard.  */
1626   if (TARGET_RELOCATABLE)
1627     return 0;
1628 #endif
1629
1630   if (mode == TFmode)
1631     {
1632       long k[4];
1633       REAL_VALUE_TYPE rv;
1634
1635       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1636       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1637
1638       return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1639               && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1640               && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1641               && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1642     }
1643
1644   else if (mode == DFmode)
1645     {
1646       long k[2];
1647       REAL_VALUE_TYPE rv;
1648
1649       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1650       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1651
1652       return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1653               && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1654     }
1655
1656   else if (mode == SFmode)
1657     {
1658       long l;
1659       REAL_VALUE_TYPE rv;
1660
1661       REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1662       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1663
1664       return num_insns_constant_wide (l) == 1;
1665     }
1666
1667   else if (mode == DImode)
1668     return ((TARGET_POWERPC64
1669              && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1670             || (num_insns_constant (op, DImode) <= 2));
1671
1672   else if (mode == SImode)
1673     return 1;
1674   else
1675     abort ();
1676 }
1677
1678 /* Returns the constant for the splat instrunction, if exists.  */
1679
1680 static int
1681 easy_vector_splat_const (int cst, enum machine_mode mode)
1682 {
1683   switch (mode)
1684     {
1685     case V4SImode:
1686       if (EASY_VECTOR_15 (cst)
1687           || EASY_VECTOR_15_ADD_SELF (cst))
1688         return cst;
1689       if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1690         break;
1691       cst = cst >> 16;
1692     case V8HImode:
1693       if (EASY_VECTOR_15 (cst)
1694           || EASY_VECTOR_15_ADD_SELF (cst))
1695         return cst;
1696       if ((cst & 0xff) != ((cst >> 8) & 0xff))
1697         break;
1698       cst = cst >> 8;
1699     case V16QImode:
1700           if (EASY_VECTOR_15 (cst)
1701               || EASY_VECTOR_15_ADD_SELF (cst))
1702             return cst;
1703     default:
1704       break;
1705     }
1706   return 0;
1707 }
1708
1709
1710 /* Return nonzero if all elements of a vector have the same value.  */
1711
1712 static int
1713 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1714 {
1715   int units, i, cst;
1716
1717   units = CONST_VECTOR_NUNITS (op);
1718
1719   cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1720   for (i = 1; i < units; ++i)
1721     if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1722       break;
1723   if (i == units && easy_vector_splat_const (cst, mode))
1724     return 1;
1725   return 0;
1726 }
1727
1728 /* Return 1 if the operand is a CONST_INT and can be put into a
1729    register without using memory.  */
1730
1731 int
1732 easy_vector_constant (rtx op, enum machine_mode mode)
1733 {
1734   int cst, cst2;
1735
1736   if (GET_CODE (op) != CONST_VECTOR
1737       || (!TARGET_ALTIVEC
1738           && !TARGET_SPE))
1739     return 0;
1740
1741   if (zero_constant (op, mode)
1742       && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1743           || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1744     return 1;
1745
1746   if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1747     return 0;
1748
1749   if (TARGET_SPE && mode == V1DImode)
1750     return 0;
1751
1752   cst  = INTVAL (CONST_VECTOR_ELT (op, 0));
1753   cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1754
1755   /* Limit SPE vectors to 15 bits signed.  These we can generate with:
1756        li r0, CONSTANT1
1757        evmergelo r0, r0, r0
1758        li r0, CONSTANT2
1759
1760      I don't know how efficient it would be to allow bigger constants,
1761      considering we'll have an extra 'ori' for every 'li'.  I doubt 5
1762      instructions is better than a 64-bit memory load, but I don't
1763      have the e500 timing specs.  */
1764   if (TARGET_SPE && mode == V2SImode
1765       && cst  >= -0x7fff && cst <= 0x7fff
1766       && cst2 >= -0x7fff && cst2 <= 0x7fff)
1767     return 1;
1768
1769   if (TARGET_ALTIVEC
1770       && easy_vector_same (op, mode))
1771     {
1772       cst = easy_vector_splat_const (cst, mode);
1773       if (EASY_VECTOR_15_ADD_SELF (cst)
1774           || EASY_VECTOR_15 (cst))
1775         return 1;
1776     }
1777   return 0;
1778 }
1779
1780 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.  */
1781
1782 int
1783 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1784 {
1785   int cst;
1786   if (TARGET_ALTIVEC
1787       && GET_CODE (op) == CONST_VECTOR
1788       && easy_vector_same (op, mode))
1789     {
1790       cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
1791       if (EASY_VECTOR_15_ADD_SELF (cst))
1792         return 1;
1793     }
1794   return 0;
1795 }
1796
1797 /* Generate easy_vector_constant out of a easy_vector_constant_add_self.  */
1798
1799 rtx
1800 gen_easy_vector_constant_add_self (rtx op)
1801 {
1802   int i, units;
1803   rtvec v;
1804   units = GET_MODE_NUNITS (GET_MODE (op));
1805   v = rtvec_alloc (units);
1806
1807   for (i = 0; i < units; i++)
1808     RTVEC_ELT (v, i) =
1809       GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1810   return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1811 }
1812
1813 const char *
1814 output_vec_const_move (rtx *operands)
1815 {
1816   int cst, cst2;
1817   enum machine_mode mode;
1818   rtx dest, vec;
1819
1820   dest = operands[0];
1821   vec = operands[1];
1822
1823   cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1824   cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1825   mode = GET_MODE (dest);
1826
1827   if (TARGET_ALTIVEC)
1828     {
1829       if (zero_constant (vec, mode))
1830         return "vxor %0,%0,%0";
1831       else if (easy_vector_constant (vec, mode))
1832         {
1833           operands[1] = GEN_INT (cst);
1834           switch (mode)
1835             {
1836             case V4SImode:
1837               if (EASY_VECTOR_15 (cst))
1838                 {
1839                   operands[1] = GEN_INT (cst);
1840                   return "vspltisw %0,%1";
1841                 }
1842               else if (EASY_VECTOR_15_ADD_SELF (cst))
1843                 return "#";
1844               cst = cst >> 16;
1845             case V8HImode:
1846               if (EASY_VECTOR_15 (cst))
1847                 {
1848                   operands[1] = GEN_INT (cst);
1849                   return "vspltish %0,%1";
1850                 }
1851               else if (EASY_VECTOR_15_ADD_SELF (cst))
1852                 return "#";
1853               cst = cst >> 8;
1854             case V16QImode:
1855               if (EASY_VECTOR_15 (cst))
1856                 {
1857                   operands[1] = GEN_INT (cst);
1858                   return "vspltisb %0,%1";
1859                 }
1860               else if (EASY_VECTOR_15_ADD_SELF (cst))
1861                 return "#";
1862             default:
1863               abort ();
1864             }
1865         }
1866       else
1867         abort ();
1868     }
1869
1870   if (TARGET_SPE)
1871     {
1872       /* Vector constant 0 is handled as a splitter of V2SI, and in the
1873          pattern of V1DI, V4HI, and V2SF.
1874
1875          FIXME: We should probably return # and add post reload
1876          splitters for these, but this way is so easy ;-).
1877       */
1878       operands[1] = GEN_INT (cst);
1879       operands[2] = GEN_INT (cst2);
1880       if (cst == cst2)
1881         return "li %0,%1\n\tevmergelo %0,%0,%0";
1882       else
1883         return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1884     }
1885
1886   abort ();
1887 }
1888
1889 /* Return 1 if the operand is the constant 0.  This works for scalars
1890    as well as vectors.  */
1891 int
1892 zero_constant (rtx op, enum machine_mode mode)
1893 {
1894   return op == CONST0_RTX (mode);
1895 }
1896
1897 /* Return 1 if the operand is 0.0.  */
1898 int
1899 zero_fp_constant (rtx op, enum machine_mode mode)
1900 {
1901   return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1902 }
1903
1904 /* Return 1 if the operand is in volatile memory.  Note that during
1905    the RTL generation phase, memory_operand does not return TRUE for
1906    volatile memory references.  So this function allows us to
1907    recognize volatile references where its safe.  */
1908
1909 int
1910 volatile_mem_operand (rtx op, enum machine_mode mode)
1911 {
1912   if (GET_CODE (op) != MEM)
1913     return 0;
1914
1915   if (!MEM_VOLATILE_P (op))
1916     return 0;
1917
1918   if (mode != GET_MODE (op))
1919     return 0;
1920
1921   if (reload_completed)
1922     return memory_operand (op, mode);
1923
1924   if (reload_in_progress)
1925     return strict_memory_address_p (mode, XEXP (op, 0));
1926
1927   return memory_address_p (mode, XEXP (op, 0));
1928 }
1929
1930 /* Return 1 if the operand is an offsettable memory operand.  */
1931
1932 int
1933 offsettable_mem_operand (rtx op, enum machine_mode mode)
1934 {
1935   return ((GET_CODE (op) == MEM)
1936           && offsettable_address_p (reload_completed || reload_in_progress,
1937                                     mode, XEXP (op, 0)));
1938 }
1939
1940 /* Return 1 if the operand is either an easy FP constant (see above) or
1941    memory.  */
1942
1943 int
1944 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1945 {
1946   return memory_operand (op, mode) || easy_fp_constant (op, mode);
1947 }
1948
1949 /* Return 1 if the operand is either a non-special register or an item
1950    that can be used as the operand of a `mode' add insn.  */
1951
1952 int
1953 add_operand (rtx op, enum machine_mode mode)
1954 {
1955   if (GET_CODE (op) == CONST_INT)
1956     return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1957             || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1958
1959   return gpc_reg_operand (op, mode);
1960 }
1961
1962 /* Return 1 if OP is a constant but not a valid add_operand.  */
1963
1964 int
1965 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1966 {
1967   return (GET_CODE (op) == CONST_INT
1968           && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1969           && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1970 }
1971
1972 /* Return 1 if the operand is a non-special register or a constant that
1973    can be used as the operand of an OR or XOR insn on the RS/6000.  */
1974
1975 int
1976 logical_operand (rtx op, enum machine_mode mode)
1977 {
1978   HOST_WIDE_INT opl, oph;
1979
1980   if (gpc_reg_operand (op, mode))
1981     return 1;
1982
1983   if (GET_CODE (op) == CONST_INT)
1984     {
1985       opl = INTVAL (op) & GET_MODE_MASK (mode);
1986
1987 #if HOST_BITS_PER_WIDE_INT <= 32
1988       if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1989         return 0;
1990 #endif
1991     }
1992   else if (GET_CODE (op) == CONST_DOUBLE)
1993     {
1994       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1995         abort ();
1996
1997       opl = CONST_DOUBLE_LOW (op);
1998       oph = CONST_DOUBLE_HIGH (op);
1999       if (oph != 0)
2000         return 0;
2001     }
2002   else
2003     return 0;
2004
2005   return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2006           || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2007 }
2008
2009 /* Return 1 if C is a constant that is not a logical operand (as
2010    above), but could be split into one.  */
2011
2012 int
2013 non_logical_cint_operand (rtx op, enum machine_mode mode)
2014 {
2015   return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2016           && ! logical_operand (op, mode)
2017           && reg_or_logical_cint_operand (op, mode));
2018 }
2019
2020 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2021    RS/6000.  It is if there are no more than two 1->0 or 0->1 transitions.
2022    Reject all ones and all zeros, since these should have been optimized
2023    away and confuse the making of MB and ME.  */
2024
2025 int
2026 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2027 {
2028   HOST_WIDE_INT c, lsb;
2029
2030   if (GET_CODE (op) != CONST_INT)
2031     return 0;
2032
2033   c = INTVAL (op);
2034
2035   /* Fail in 64-bit mode if the mask wraps around because the upper
2036      32-bits of the mask will all be 1s, contrary to GCC's internal view.  */
2037   if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2038     return 0;
2039
2040   /* We don't change the number of transitions by inverting,
2041      so make sure we start with the LS bit zero.  */
2042   if (c & 1)
2043     c = ~c;
2044
2045   /* Reject all zeros or all ones.  */
2046   if (c == 0)
2047     return 0;
2048
2049   /* Find the first transition.  */
2050   lsb = c & -c;
2051
2052   /* Invert to look for a second transition.  */
2053   c = ~c;
2054
2055   /* Erase first transition.  */
2056   c &= -lsb;
2057
2058   /* Find the second transition (if any).  */
2059   lsb = c & -c;
2060
2061   /* Match if all the bits above are 1's (or c is zero).  */
2062   return c == -lsb;
2063 }
2064
2065 /* Return 1 for the PowerPC64 rlwinm corner case.  */
2066
2067 int
2068 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2069 {
2070   HOST_WIDE_INT c, lsb;
2071
2072   if (GET_CODE (op) != CONST_INT)
2073     return 0;
2074
2075   c = INTVAL (op);
2076
2077   if ((c & 0x80000001) != 0x80000001)
2078     return 0;
2079
2080   c = ~c;
2081   if (c == 0)
2082     return 0;
2083
2084   lsb = c & -c;
2085   c = ~c;
2086   c &= -lsb;
2087   lsb = c & -c;
2088   return c == -lsb;
2089 }
2090
2091 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2092    It is if there are no more than one 1->0 or 0->1 transitions.
2093    Reject all zeros, since zero should have been optimized away and
2094    confuses the making of MB and ME.  */
2095
2096 int
2097 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2098 {
2099   if (GET_CODE (op) == CONST_INT)
2100     {
2101       HOST_WIDE_INT c, lsb;
2102
2103       c = INTVAL (op);
2104
2105       /* Reject all zeros.  */
2106       if (c == 0)
2107         return 0;
2108
2109       /* We don't change the number of transitions by inverting,
2110          so make sure we start with the LS bit zero.  */
2111       if (c & 1)
2112         c = ~c;
2113
2114       /* Find the transition, and check that all bits above are 1's.  */
2115       lsb = c & -c;
2116
2117       /* Match if all the bits above are 1's (or c is zero).  */
2118       return c == -lsb;
2119     }
2120   return 0;
2121 }
2122
2123 /* Like mask64_operand, but allow up to three transitions.  This
2124    predicate is used by insn patterns that generate two rldicl or
2125    rldicr machine insns.  */
2126
2127 int
2128 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2129 {
2130   if (GET_CODE (op) == CONST_INT)
2131     {
2132       HOST_WIDE_INT c, lsb;
2133
2134       c = INTVAL (op);
2135
2136       /* Disallow all zeros.  */
2137       if (c == 0)
2138         return 0;
2139
2140       /* We don't change the number of transitions by inverting,
2141          so make sure we start with the LS bit zero.  */
2142       if (c & 1)
2143         c = ~c;
2144
2145       /* Find the first transition.  */
2146       lsb = c & -c;
2147
2148       /* Invert to look for a second transition.  */
2149       c = ~c;
2150
2151       /* Erase first transition.  */
2152       c &= -lsb;
2153
2154       /* Find the second transition.  */
2155       lsb = c & -c;
2156
2157       /* Invert to look for a third transition.  */
2158       c = ~c;
2159
2160       /* Erase second transition.  */
2161       c &= -lsb;
2162
2163       /* Find the third transition (if any).  */
2164       lsb = c & -c;
2165
2166       /* Match if all the bits above are 1's (or c is zero).  */
2167       return c == -lsb;
2168     }
2169   return 0;
2170 }
2171
2172 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2173    implement ANDing by the mask IN.  */
2174 void
2175 build_mask64_2_operands (rtx in, rtx *out)
2176 {
2177 #if HOST_BITS_PER_WIDE_INT >= 64
2178   unsigned HOST_WIDE_INT c, lsb, m1, m2;
2179   int shift;
2180
2181   if (GET_CODE (in) != CONST_INT)
2182     abort ();
2183
2184   c = INTVAL (in);
2185   if (c & 1)
2186     {
2187       /* Assume c initially something like 0x00fff000000fffff.  The idea
2188          is to rotate the word so that the middle ^^^^^^ group of zeros
2189          is at the MS end and can be cleared with an rldicl mask.  We then
2190          rotate back and clear off the MS    ^^ group of zeros with a
2191          second rldicl.  */
2192       c = ~c;                   /*   c == 0xff000ffffff00000 */
2193       lsb = c & -c;             /* lsb == 0x0000000000100000 */
2194       m1 = -lsb;                /*  m1 == 0xfffffffffff00000 */
2195       c = ~c;                   /*   c == 0x00fff000000fffff */
2196       c &= -lsb;                /*   c == 0x00fff00000000000 */
2197       lsb = c & -c;             /* lsb == 0x0000100000000000 */
2198       c = ~c;                   /*   c == 0xff000fffffffffff */
2199       c &= -lsb;                /*   c == 0xff00000000000000 */
2200       shift = 0;
2201       while ((lsb >>= 1) != 0)
2202         shift++;                /* shift == 44 on exit from loop */
2203       m1 <<= 64 - shift;        /*  m1 == 0xffffff0000000000 */
2204       m1 = ~m1;                 /*  m1 == 0x000000ffffffffff */
2205       m2 = ~c;                  /*  m2 == 0x00ffffffffffffff */
2206     }
2207   else
2208     {
2209       /* Assume c initially something like 0xff000f0000000000.  The idea
2210          is to rotate the word so that the     ^^^  middle group of zeros
2211          is at the LS end and can be cleared with an rldicr mask.  We then
2212          rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2213          a second rldicr.  */
2214       lsb = c & -c;             /* lsb == 0x0000010000000000 */
2215       m2 = -lsb;                /*  m2 == 0xffffff0000000000 */
2216       c = ~c;                   /*   c == 0x00fff0ffffffffff */
2217       c &= -lsb;                /*   c == 0x00fff00000000000 */
2218       lsb = c & -c;             /* lsb == 0x0000100000000000 */
2219       c = ~c;                   /*   c == 0xff000fffffffffff */
2220       c &= -lsb;                /*   c == 0xff00000000000000 */
2221       shift = 0;
2222       while ((lsb >>= 1) != 0)
2223         shift++;                /* shift == 44 on exit from loop */
2224       m1 = ~c;                  /*  m1 == 0x00ffffffffffffff */
2225       m1 >>= shift;             /*  m1 == 0x0000000000000fff */
2226       m1 = ~m1;                 /*  m1 == 0xfffffffffffff000 */
2227     }
2228
2229   /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2230      masks will be all 1's.  We are guaranteed more than one transition.  */
2231   out[0] = GEN_INT (64 - shift);
2232   out[1] = GEN_INT (m1);
2233   out[2] = GEN_INT (shift);
2234   out[3] = GEN_INT (m2);
2235 #else
2236   (void)in;
2237   (void)out;
2238   abort ();
2239 #endif
2240 }
2241
2242 /* Return 1 if the operand is either a non-special register or a constant
2243    that can be used as the operand of a PowerPC64 logical AND insn.  */
2244
2245 int
2246 and64_operand (rtx op, enum machine_mode mode)
2247 {
2248   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2249     return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2250
2251   return (logical_operand (op, mode) || mask64_operand (op, mode));
2252 }
2253
2254 /* Like the above, but also match constants that can be implemented
2255    with two rldicl or rldicr insns.  */
2256
2257 int
2258 and64_2_operand (rtx op, enum machine_mode mode)
2259 {
2260   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2261     return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2262
2263   return logical_operand (op, mode) || mask64_2_operand (op, mode);
2264 }
2265
2266 /* Return 1 if the operand is either a non-special register or a
2267    constant that can be used as the operand of an RS/6000 logical AND insn.  */
2268
2269 int
2270 and_operand (rtx op, enum machine_mode mode)
2271 {
2272   if (fixed_regs[CR0_REGNO])    /* CR0 not available, don't do andi./andis.  */
2273     return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2274
2275   return (logical_operand (op, mode) || mask_operand (op, mode));
2276 }
2277
2278 /* Return 1 if the operand is a general register or memory operand.  */
2279
2280 int
2281 reg_or_mem_operand (rtx op, enum machine_mode mode)
2282 {
2283   return (gpc_reg_operand (op, mode)
2284           || memory_operand (op, mode)
2285           || macho_lo_sum_memory_operand (op, mode)
2286           || volatile_mem_operand (op, mode));
2287 }
2288
2289 /* Return 1 if the operand is a general register or memory operand without
2290    pre_inc or pre_dec which produces invalid form of PowerPC lwa
2291    instruction.  */
2292
2293 int
2294 lwa_operand (rtx op, enum machine_mode mode)
2295 {
2296   rtx inner = op;
2297
2298   if (reload_completed && GET_CODE (inner) == SUBREG)
2299     inner = SUBREG_REG (inner);
2300
2301   return gpc_reg_operand (inner, mode)
2302     || (memory_operand (inner, mode)
2303         && GET_CODE (XEXP (inner, 0)) != PRE_INC
2304         && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2305         && (GET_CODE (XEXP (inner, 0)) != PLUS
2306             || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2307             || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2308 }
2309
2310 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.  */
2311
2312 int
2313 symbol_ref_operand (rtx op, enum machine_mode mode)
2314 {
2315   if (mode != VOIDmode && GET_MODE (op) != mode)
2316     return 0;
2317
2318 #if TARGET_MACHO
2319   if (GET_CODE (op) == SYMBOL_REF && TARGET_MACHO && MACHOPIC_INDIRECT)
2320     {
2321       /* Macho says it has to go through a stub or be local
2322          when indirect mode.  Stubs are considered local.  */
2323       const char *t = XSTR (op, 0);
2324       /* "&" means that it is it a local defined symbol
2325           so it is okay to call to.  */
2326       if (t[0] == '&')
2327         return true;
2328
2329       /* "!T" means that the function is local defined.  */
2330       return (t[0] == '!' && t[1] == 'T');
2331     }
2332 #endif
2333
2334
2335   return (GET_CODE (op) == SYMBOL_REF
2336           && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2337 }
2338
2339 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2340    to CALL.  This is a SYMBOL_REF, a pseudo-register, LR or CTR.  */
2341
2342 int
2343 call_operand (rtx op, enum machine_mode mode)
2344 {
2345   if (mode != VOIDmode && GET_MODE (op) != mode)
2346     return 0;
2347
2348   return (GET_CODE (op) == SYMBOL_REF
2349           || (GET_CODE (op) == REG
2350               && (REGNO (op) == LINK_REGISTER_REGNUM
2351                   || REGNO (op) == COUNT_REGISTER_REGNUM
2352                   || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2353 }
2354
2355 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2356    this file.  */
2357
2358 int
2359 current_file_function_operand (rtx op,
2360                               enum machine_mode mode ATTRIBUTE_UNUSED)
2361 {
2362   return (GET_CODE (op) == SYMBOL_REF
2363           && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2364           && (SYMBOL_REF_LOCAL_P (op)
2365               || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2366 }
2367
2368 /* Return 1 if this operand is a valid input for a move insn.  */
2369
2370 int
2371 input_operand (rtx op, enum machine_mode mode)
2372 {
2373   /* Memory is always valid.  */
2374   if (memory_operand (op, mode))
2375     return 1;
2376
2377   /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary.  */
2378   if (GET_CODE (op) == CONSTANT_P_RTX)
2379     return 1;
2380
2381   /* For floating-point, easy constants are valid.  */
2382   if (GET_MODE_CLASS (mode) == MODE_FLOAT
2383       && CONSTANT_P (op)
2384       && easy_fp_constant (op, mode))
2385     return 1;
2386
2387   /* Allow any integer constant.  */
2388   if (GET_MODE_CLASS (mode) == MODE_INT
2389       && (GET_CODE (op) == CONST_INT
2390           || GET_CODE (op) == CONST_DOUBLE))
2391     return 1;
2392
2393   /* Allow easy vector constants.  */
2394   if (GET_CODE (op) == CONST_VECTOR
2395       && easy_vector_constant (op, mode))
2396     return 1;
2397
2398   /* For floating-point or multi-word mode, the only remaining valid type
2399      is a register.  */
2400   if (GET_MODE_CLASS (mode) == MODE_FLOAT
2401       || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2402     return register_operand (op, mode);
2403
2404   /* The only cases left are integral modes one word or smaller (we
2405      do not get called for MODE_CC values).  These can be in any
2406      register.  */
2407   if (register_operand (op, mode))
2408     return 1;
2409
2410   /* A SYMBOL_REF referring to the TOC is valid.  */
2411   if (legitimate_constant_pool_address_p (op))
2412     return 1;
2413
2414   /* A constant pool expression (relative to the TOC) is valid */
2415   if (toc_relative_expr_p (op))
2416     return 1;
2417
2418   /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2419      to be valid.  */
2420   if (DEFAULT_ABI == ABI_V4
2421       && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2422       && small_data_operand (op, Pmode))
2423     return 1;
2424
2425   return 0;
2426 }
2427
2428
2429 /* Darwin, AIX increases natural record alignment to doubleword if the first
2430    field is an FP double while the FP fields remain word aligned.  */
2431
2432 unsigned int
2433 rs6000_special_round_type_align (tree type, int computed, int specified)
2434 {
2435   tree field = TYPE_FIELDS (type);
2436
2437   /* Skip all the static variables only if ABI is greater than
2438      1 or equal to 0.  */
2439   while (field != NULL && TREE_CODE (field) == VAR_DECL)
2440     field = TREE_CHAIN (field);
2441
2442   if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2443     return MAX (computed, specified);
2444
2445   return MAX (MAX (computed, specified), 64);
2446 }
2447
2448 /* Return 1 for an operand in small memory on V.4/eabi.  */
2449
2450 int
2451 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2452                     enum machine_mode mode ATTRIBUTE_UNUSED)
2453 {
2454 #if TARGET_ELF
2455   rtx sym_ref;
2456
2457   if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2458     return 0;
2459
2460   if (DEFAULT_ABI != ABI_V4)
2461     return 0;
2462
2463   if (GET_CODE (op) == SYMBOL_REF)
2464     sym_ref = op;
2465
2466   else if (GET_CODE (op) != CONST
2467            || GET_CODE (XEXP (op, 0)) != PLUS
2468            || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2469            || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2470     return 0;
2471
2472   else
2473     {
2474       rtx sum = XEXP (op, 0);
2475       HOST_WIDE_INT summand;
2476
2477       /* We have to be careful here, because it is the referenced address
2478         that must be 32k from _SDA_BASE_, not just the symbol.  */
2479       summand = INTVAL (XEXP (sum, 1));
2480       if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2481        return 0;
2482
2483       sym_ref = XEXP (sum, 0);
2484     }
2485
2486   return SYMBOL_REF_SMALL_P (sym_ref);
2487 #else
2488   return 0;
2489 #endif
2490 }
2491
2492 /* Return true, if operand is a memory operand and has a
2493    displacement divisible by 4.  */
2494
2495 int
2496 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2497 {
2498   rtx addr;
2499   int off = 0;
2500
2501   if (!memory_operand (op, mode))
2502     return 0;
2503
2504   addr = XEXP (op, 0);
2505   if (GET_CODE (addr) == PLUS
2506       && GET_CODE (XEXP (addr, 0)) == REG
2507       && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2508     off = INTVAL (XEXP (addr, 1));
2509
2510   return (off % 4) == 0;
2511 }
2512
2513 /* Return true if either operand is a general purpose register.  */
2514
2515 bool
2516 gpr_or_gpr_p (rtx op0, rtx op1)
2517 {
2518   return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2519           || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2520 }
2521
2522 \f
2523 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address.  */
2524
2525 static int
2526 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2527 {
2528   switch (GET_CODE(op))
2529     {
2530     case SYMBOL_REF:
2531       if (RS6000_SYMBOL_REF_TLS_P (op))
2532         return 0;
2533       else if (CONSTANT_POOL_ADDRESS_P (op))
2534         {
2535           if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2536             {
2537               *have_sym = 1;
2538               return 1;
2539             }
2540           else
2541             return 0;
2542         }
2543       else if (! strcmp (XSTR (op, 0), toc_label_name))
2544         {
2545           *have_toc = 1;
2546           return 1;
2547         }
2548       else
2549         return 0;
2550     case PLUS:
2551     case MINUS:
2552       return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2553               && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2554     case CONST:
2555       return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2556     case CONST_INT:
2557       return 1;
2558     default:
2559       return 0;
2560     }
2561 }
2562
2563 static bool
2564 constant_pool_expr_p (rtx op)
2565 {
2566   int have_sym = 0;
2567   int have_toc = 0;
2568   return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2569 }
2570
2571 static bool
2572 toc_relative_expr_p (rtx op)
2573 {
2574   int have_sym = 0;
2575   int have_toc = 0;
2576   return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2577 }
2578
2579 /* SPE offset addressing is limited to 5-bits worth of double words.  */
2580 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2581
2582 bool
2583 legitimate_constant_pool_address_p (rtx x)
2584 {
2585   return (TARGET_TOC
2586           && GET_CODE (x) == PLUS
2587           && GET_CODE (XEXP (x, 0)) == REG
2588           && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2589           && constant_pool_expr_p (XEXP (x, 1)));
2590 }
2591
2592 static bool
2593 legitimate_small_data_p (enum machine_mode mode, rtx x)
2594 {
2595   return (DEFAULT_ABI == ABI_V4
2596           && !flag_pic && !TARGET_TOC
2597           && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2598           && small_data_operand (x, mode));
2599 }
2600
2601 static bool
2602 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2603 {
2604   unsigned HOST_WIDE_INT offset, extra;
2605
2606   if (GET_CODE (x) != PLUS)
2607     return false;
2608   if (GET_CODE (XEXP (x, 0)) != REG)
2609     return false;
2610   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2611     return false;
2612   if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2613     return false;
2614
2615   offset = INTVAL (XEXP (x, 1));
2616   extra = 0;
2617   switch (mode)
2618     {
2619     case V16QImode:
2620     case V8HImode:
2621     case V4SFmode:
2622     case V4SImode:
2623       /* AltiVec vector modes.  Only reg+reg addressing is valid here,
2624          which leaves the only valid constant offset of zero, which by
2625          canonicalization rules is also invalid.  */
2626       return false;
2627
2628     case V4HImode:
2629     case V2SImode:
2630     case V1DImode:
2631     case V2SFmode:
2632       /* SPE vector modes.  */
2633       return SPE_CONST_OFFSET_OK (offset);
2634
2635     case DFmode:
2636     case DImode:
2637       if (mode == DFmode || !TARGET_POWERPC64)
2638         extra = 4;
2639       else if (offset & 3)
2640         return false;
2641       break;
2642
2643     case TFmode:
2644     case TImode:
2645       if (mode == TFmode || !TARGET_POWERPC64)
2646         extra = 12;
2647       else if (offset & 3)
2648         return false;
2649       else
2650         extra = 8;
2651       break;
2652
2653     default:
2654       break;
2655     }
2656
2657   offset += 0x8000;
2658   return (offset < 0x10000) && (offset + extra < 0x10000);
2659 }
2660
2661 static bool
2662 legitimate_indexed_address_p (rtx x, int strict)
2663 {
2664   rtx op0, op1;
2665
2666   if (GET_CODE (x) != PLUS)
2667     return false;
2668   op0 = XEXP (x, 0);
2669   op1 = XEXP (x, 1);
2670
2671   if (!REG_P (op0) || !REG_P (op1))
2672     return false;
2673
2674   return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2675            && INT_REG_OK_FOR_INDEX_P (op1, strict))
2676           || (INT_REG_OK_FOR_BASE_P (op1, strict)
2677               && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2678 }
2679
2680 static inline bool
2681 legitimate_indirect_address_p (rtx x, int strict)
2682 {
2683   return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2684 }
2685
2686 static bool
2687 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2688 {
2689     if (!TARGET_MACHO || !flag_pic
2690         || mode != SImode || GET_CODE(x) != MEM)
2691       return false;
2692     x = XEXP (x, 0);
2693
2694   if (GET_CODE (x) != LO_SUM)
2695     return false;
2696   if (GET_CODE (XEXP (x, 0)) != REG)
2697     return false;
2698   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2699     return false;
2700   x = XEXP (x, 1);
2701
2702   return CONSTANT_P (x);
2703 }
2704
2705 static bool
2706 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2707 {
2708   if (GET_CODE (x) != LO_SUM)
2709     return false;
2710   if (GET_CODE (XEXP (x, 0)) != REG)
2711     return false;
2712   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2713     return false;
2714   x = XEXP (x, 1);
2715
2716   if (TARGET_ELF || TARGET_MACHO)
2717     {
2718       if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2719         return false;
2720       if (TARGET_TOC)
2721         return false;
2722       if (GET_MODE_NUNITS (mode) != 1)
2723         return false;
2724       if (GET_MODE_BITSIZE (mode) > 32
2725           && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2726         return false;
2727
2728       return CONSTANT_P (x);
2729     }
2730
2731   return false;
2732 }
2733
2734
2735 /* Try machine-dependent ways of modifying an illegitimate address
2736    to be legitimate.  If we find one, return the new, valid address.
2737    This is used from only one place: `memory_address' in explow.c.
2738
2739    OLDX is the address as it was before break_out_memory_refs was
2740    called.  In some cases it is useful to look at this to decide what
2741    needs to be done.
2742
2743    MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2744
2745    It is always safe for this function to do nothing.  It exists to
2746    recognize opportunities to optimize the output.
2747
2748    On RS/6000, first check for the sum of a register with a constant
2749    integer that is out of range.  If so, generate code to add the
2750    constant with the low-order 16 bits masked to the register and force
2751    this result into another register (this can be done with `cau').
2752    Then generate an address of REG+(CONST&0xffff), allowing for the
2753    possibility of bit 16 being a one.
2754
2755    Then check for the sum of a register and something not constant, try to
2756    load the other things into a register and return the sum.  */
2757
2758 rtx
2759 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2760                            enum machine_mode mode)
2761 {
2762   if (GET_CODE (x) == SYMBOL_REF)
2763     {
2764       enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2765       if (model != 0)
2766         return rs6000_legitimize_tls_address (x, model);
2767     }
2768
2769   if (GET_CODE (x) == PLUS
2770       && GET_CODE (XEXP (x, 0)) == REG
2771       && GET_CODE (XEXP (x, 1)) == CONST_INT
2772       && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2773     {
2774       HOST_WIDE_INT high_int, low_int;
2775       rtx sum;
2776       low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2777       high_int = INTVAL (XEXP (x, 1)) - low_int;
2778       sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2779                                          GEN_INT (high_int)), 0);
2780       return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2781     }
2782   else if (GET_CODE (x) == PLUS
2783            && GET_CODE (XEXP (x, 0)) == REG
2784            && GET_CODE (XEXP (x, 1)) != CONST_INT
2785            && GET_MODE_NUNITS (mode) == 1
2786            && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2787                || TARGET_POWERPC64
2788                || (mode != DFmode && mode != TFmode))
2789            && (TARGET_POWERPC64 || mode != DImode)
2790            && mode != TImode)
2791     {
2792       return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2793                            force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2794     }
2795   else if (ALTIVEC_VECTOR_MODE (mode))
2796     {
2797       rtx reg;
2798
2799       /* Make sure both operands are registers.  */
2800       if (GET_CODE (x) == PLUS)
2801         return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2802                              force_reg (Pmode, XEXP (x, 1)));
2803
2804       reg = force_reg (Pmode, x);
2805       return reg;
2806     }
2807   else if (SPE_VECTOR_MODE (mode))
2808     {
2809       /* We accept [reg + reg] and [reg + OFFSET].  */
2810
2811       if (GET_CODE (x) == PLUS)
2812       {
2813         rtx op1 = XEXP (x, 0);
2814         rtx op2 = XEXP (x, 1);
2815
2816         op1 = force_reg (Pmode, op1);
2817
2818         if (GET_CODE (op2) != REG
2819             && (GET_CODE (op2) != CONST_INT
2820                 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2821           op2 = force_reg (Pmode, op2);
2822
2823         return gen_rtx_PLUS (Pmode, op1, op2);
2824       }
2825
2826       return force_reg (Pmode, x);
2827     }
2828   else if (TARGET_ELF
2829            && TARGET_32BIT
2830            && TARGET_NO_TOC
2831            && ! flag_pic
2832            && GET_CODE (x) != CONST_INT
2833            && GET_CODE (x) != CONST_DOUBLE
2834            && CONSTANT_P (x)
2835            && GET_MODE_NUNITS (mode) == 1
2836            && (GET_MODE_BITSIZE (mode) <= 32
2837                || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2838     {
2839       rtx reg = gen_reg_rtx (Pmode);
2840       emit_insn (gen_elf_high (reg, x));
2841       return gen_rtx_LO_SUM (Pmode, reg, x);
2842     }
2843   else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2844            && ! flag_pic
2845 #if TARGET_MACHO
2846            && ! MACHO_DYNAMIC_NO_PIC_P
2847 #endif
2848            && GET_CODE (x) != CONST_INT
2849            && GET_CODE (x) != CONST_DOUBLE
2850            && CONSTANT_P (x)
2851            && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2852            && mode != DImode
2853            && mode != TImode)
2854     {
2855       rtx reg = gen_reg_rtx (Pmode);
2856       emit_insn (gen_macho_high (reg, x));
2857       return gen_rtx_LO_SUM (Pmode, reg, x);
2858     }
2859   else if (TARGET_TOC
2860            && constant_pool_expr_p (x)
2861            && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2862     {
2863       return create_TOC_reference (x);
2864     }
2865   else
2866     return NULL_RTX;
2867 }
2868
2869 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2870    We need to emit DTP-relative relocations.  */
2871
2872 void
2873 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2874 {
2875   switch (size)
2876     {
2877     case 4:
2878       fputs ("\t.long\t", file);
2879       break;
2880     case 8:
2881       fputs (DOUBLE_INT_ASM_OP, file);
2882       break;
2883     default:
2884       abort ();
2885     }
2886   output_addr_const (file, x);
2887   fputs ("@dtprel+0x8000", file);
2888 }
2889
2890 /* Construct the SYMBOL_REF for the tls_get_addr function.  */
2891
2892 static GTY(()) rtx rs6000_tls_symbol;
2893 static rtx
2894 rs6000_tls_get_addr (void)
2895 {
2896   if (!rs6000_tls_symbol)
2897     rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2898
2899   return rs6000_tls_symbol;
2900 }
2901
2902 /* Construct the SYMBOL_REF for TLS GOT references.  */
2903
2904 static GTY(()) rtx rs6000_got_symbol;
2905 static rtx
2906 rs6000_got_sym (void)
2907 {
2908   if (!rs6000_got_symbol)
2909     {
2910       rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2911       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2912       SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2913     }
2914
2915   return rs6000_got_symbol;
2916 }
2917
2918 /* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
2919    this (thread-local) address.  */
2920
2921 static rtx
2922 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2923 {
2924   rtx dest, insn;
2925
2926   dest = gen_reg_rtx (Pmode);
2927   if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2928     {
2929       rtx tlsreg;
2930
2931       if (TARGET_64BIT)
2932         {
2933           tlsreg = gen_rtx_REG (Pmode, 13);
2934           insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2935         }
2936       else
2937         {
2938           tlsreg = gen_rtx_REG (Pmode, 2);
2939           insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2940         }
2941       emit_insn (insn);
2942     }
2943   else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2944     {
2945       rtx tlsreg, tmp;
2946
2947       tmp = gen_reg_rtx (Pmode);
2948       if (TARGET_64BIT)
2949         {
2950           tlsreg = gen_rtx_REG (Pmode, 13);
2951           insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2952         }
2953       else
2954         {
2955           tlsreg = gen_rtx_REG (Pmode, 2);
2956           insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2957         }
2958       emit_insn (insn);
2959       if (TARGET_64BIT)
2960         insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2961       else
2962         insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2963       emit_insn (insn);
2964     }
2965   else
2966     {
2967       rtx r3, got, tga, tmp1, tmp2, eqv;
2968
2969       if (TARGET_64BIT)
2970         got = gen_rtx_REG (Pmode, TOC_REGISTER);
2971       else
2972         {
2973           if (flag_pic == 1)
2974             got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2975           else
2976             {
2977               rtx gsym = rs6000_got_sym ();
2978               got = gen_reg_rtx (Pmode);
2979               if (flag_pic == 0)
2980                 rs6000_emit_move (got, gsym, Pmode);
2981               else
2982                 {
2983                   char buf[30];
2984                   static int tls_got_labelno = 0;
2985                   rtx tempLR, lab, tmp3, mem;
2986                   rtx first, last;
2987
2988                   ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2989                   lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2990                   tempLR = gen_reg_rtx (Pmode);
2991                   tmp1 = gen_reg_rtx (Pmode);
2992                   tmp2 = gen_reg_rtx (Pmode);
2993                   tmp3 = gen_reg_rtx (Pmode);
2994                   mem = gen_rtx_MEM (Pmode, tmp1);
2995                   RTX_UNCHANGING_P (mem) = 1;
2996
2997                   first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2998                                                              gsym));
2999                   emit_move_insn (tmp1, tempLR);
3000                   emit_move_insn (tmp2, mem);
3001                   emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3002                   last = emit_move_insn (got, tmp3);
3003                   REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3004                                                         REG_NOTES (last));
3005                   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3006                                                          REG_NOTES (first));
3007                   REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3008                                                         REG_NOTES (last));
3009                 }
3010             }
3011         }
3012
3013       if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3014         {
3015           r3 = gen_rtx_REG (Pmode, 3);
3016           if (TARGET_64BIT)
3017             insn = gen_tls_gd_64 (r3, got, addr);
3018           else
3019             insn = gen_tls_gd_32 (r3, got, addr);
3020           start_sequence ();
3021           emit_insn (insn);
3022           tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3023           insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3024           insn = emit_call_insn (insn);
3025           CONST_OR_PURE_CALL_P (insn) = 1;
3026           use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3027           insn = get_insns ();
3028           end_sequence ();
3029           emit_libcall_block (insn, dest, r3, addr);
3030         }
3031       else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3032         {
3033           r3 = gen_rtx_REG (Pmode, 3);
3034           if (TARGET_64BIT)
3035             insn = gen_tls_ld_64 (r3, got);
3036           else
3037             insn = gen_tls_ld_32 (r3, got);
3038           start_sequence ();
3039           emit_insn (insn);
3040           tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3041           insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3042           insn = emit_call_insn (insn);
3043           CONST_OR_PURE_CALL_P (insn) = 1;
3044           use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3045           insn = get_insns ();
3046           end_sequence ();
3047           tmp1 = gen_reg_rtx (Pmode);
3048           eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3049                                 UNSPEC_TLSLD);
3050           emit_libcall_block (insn, tmp1, r3, eqv);
3051           if (rs6000_tls_size == 16)
3052             {
3053               if (TARGET_64BIT)
3054                 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3055               else
3056                 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3057             }
3058           else if (rs6000_tls_size == 32)
3059             {
3060               tmp2 = gen_reg_rtx (Pmode);
3061               if (TARGET_64BIT)
3062                 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3063               else
3064                 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3065               emit_insn (insn);
3066               if (TARGET_64BIT)
3067                 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3068               else
3069                 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3070             }
3071           else
3072             {
3073               tmp2 = gen_reg_rtx (Pmode);
3074               if (TARGET_64BIT)
3075                 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3076               else
3077                 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3078               emit_insn (insn);
3079               insn = gen_rtx_SET (Pmode, dest,
3080                                   gen_rtx_PLUS (Pmode, tmp2, tmp1));
3081             }
3082           emit_insn (insn);
3083         }
3084       else
3085         {
3086           /* IE, or 64 bit offset LE.  */
3087           tmp2 = gen_reg_rtx (Pmode);
3088           if (TARGET_64BIT)
3089             insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3090           else
3091             insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3092           emit_insn (insn);
3093           if (TARGET_64BIT)
3094             insn = gen_tls_tls_64 (dest, tmp2, addr);
3095           else
3096             insn = gen_tls_tls_32 (dest, tmp2, addr);
3097           emit_insn (insn);
3098         }
3099     }
3100
3101   return dest;
3102 }
3103
3104 /* Return 1 if X is a SYMBOL_REF for a TLS symbol.  This is used in
3105    instruction definitions.  */
3106
3107 int
3108 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3109 {
3110   return RS6000_SYMBOL_REF_TLS_P (x);
3111 }
3112
3113 /* Return 1 if X contains a thread-local symbol.  */
3114
3115 bool
3116 rs6000_tls_referenced_p (rtx x)
3117 {
3118   if (! TARGET_HAVE_TLS)
3119     return false;
3120
3121   return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3122 }
3123
3124 /* Return 1 if *X is a thread-local symbol.  This is the same as
3125    rs6000_tls_symbol_ref except for the type of the unused argument.  */
3126
3127 static inline int
3128 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3129 {
3130   return RS6000_SYMBOL_REF_TLS_P (*x);
3131 }
3132
3133 /* The convention appears to be to define this wherever it is used.
3134    With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3135    is now used here.  */
3136 #ifndef REG_MODE_OK_FOR_BASE_P
3137 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3138 #endif
3139
3140 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS.  Returns a value to
3141    replace the input X, or the original X if no replacement is called for.
3142    The output parameter *WIN is 1 if the calling macro should goto WIN,
3143    0 if it should not.
3144
3145    For RS/6000, we wish to handle large displacements off a base
3146    register by splitting the addend across an addiu/addis and the mem insn.
3147    This cuts number of extra insns needed from 3 to 1.
3148
3149    On Darwin, we use this to generate code for floating point constants.
3150    A movsf_low is generated so we wind up with 2 instructions rather than 3.
3151    The Darwin code is inside #if TARGET_MACHO because only then is
3152    machopic_function_base_name() defined.  */
3153 rtx
3154 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3155         int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
3156 {
3157   /* We must recognize output that we have already generated ourselves.  */
3158   if (GET_CODE (x) == PLUS
3159       && GET_CODE (XEXP (x, 0)) == PLUS
3160       && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3161       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3162       && GET_CODE (XEXP (x, 1)) == CONST_INT)
3163     {
3164       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3165                    BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3166                    opnum, (enum reload_type)type);
3167       *win = 1;
3168       return x;
3169     }
3170
3171 #if TARGET_MACHO
3172   if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3173       && GET_CODE (x) == LO_SUM
3174       && GET_CODE (XEXP (x, 0)) == PLUS
3175       && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3176       && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3177       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3178       && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3179       && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3180       && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3181       && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3182     {
3183       /* Result of previous invocation of this function on Darwin
3184          floating point constant.  */
3185       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3186                 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3187                 opnum, (enum reload_type)type);
3188       *win = 1;
3189       return x;
3190     }
3191 #endif
3192   if (GET_CODE (x) == PLUS
3193       && GET_CODE (XEXP (x, 0)) == REG
3194       && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3195       && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3196       && GET_CODE (XEXP (x, 1)) == CONST_INT
3197       && !SPE_VECTOR_MODE (mode)
3198       && !ALTIVEC_VECTOR_MODE (mode))
3199     {
3200       HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3201       HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3202       HOST_WIDE_INT high
3203         = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3204
3205       /* Check for 32-bit overflow.  */
3206       if (high + low != val)
3207         {
3208           *win = 0;
3209           return x;
3210         }
3211
3212       /* Reload the high part into a base reg; leave the low part
3213          in the mem directly.  */
3214
3215       x = gen_rtx_PLUS (GET_MODE (x),
3216                         gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3217                                       GEN_INT (high)),
3218                         GEN_INT (low));
3219
3220       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3221                    BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3222                    opnum, (enum reload_type)type);
3223       *win = 1;
3224       return x;
3225     }
3226 #if TARGET_MACHO
3227   if (GET_CODE (x) == SYMBOL_REF
3228       && DEFAULT_ABI == ABI_DARWIN
3229       && !ALTIVEC_VECTOR_MODE (mode)
3230       && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3231       /* Don't do this for TFmode, since the result isn't offsettable.  */
3232       && mode != TFmode)
3233     {
3234       if (flag_pic)
3235         {
3236           rtx offset = gen_rtx_CONST (Pmode,
3237                          gen_rtx_MINUS (Pmode, x,
3238                            gen_rtx_SYMBOL_REF (Pmode,
3239                              machopic_function_base_name ())));
3240           x = gen_rtx_LO_SUM (GET_MODE (x),
3241                 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3242                   gen_rtx_HIGH (Pmode, offset)), offset);
3243         }
3244       else
3245         x = gen_rtx_LO_SUM (GET_MODE (x),
3246               gen_rtx_HIGH (Pmode, x), x);
3247
3248       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3249                    BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3250                    opnum, (enum reload_type)type);
3251       *win = 1;
3252       return x;
3253     }
3254 #endif
3255   if (TARGET_TOC
3256       && constant_pool_expr_p (x)
3257       && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3258     {
3259       (x) = create_TOC_reference (x);
3260       *win = 1;
3261       return x;
3262     }
3263   *win = 0;
3264   return x;
3265 }
3266
3267 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3268    that is a valid memory address for an instruction.
3269    The MODE argument is the machine mode for the MEM expression
3270    that wants to use this address.
3271
3272    On the RS/6000, there are four valid address: a SYMBOL_REF that
3273    refers to a constant pool entry of an address (or the sum of it
3274    plus a constant), a short (16-bit signed) constant plus a register,
3275    the sum of two registers, or a register indirect, possibly with an
3276    auto-increment.  For DFmode and DImode with a constant plus register,
3277    we must ensure that both words are addressable or PowerPC64 with offset
3278    word aligned.
3279
3280    For modes spanning multiple registers (DFmode in 32-bit GPRs,
3281    32-bit DImode, TImode), indexed addressing cannot be used because
3282    adjacent memory cells are accessed by adding word-sized offsets
3283    during assembly output.  */
3284 int
3285 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3286 {
3287   if (RS6000_SYMBOL_REF_TLS_P (x))
3288     return 0;
3289   if (legitimate_indirect_address_p (x, reg_ok_strict))
3290     return 1;
3291   if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3292       && !ALTIVEC_VECTOR_MODE (mode)
3293       && !SPE_VECTOR_MODE (mode)
3294       && TARGET_UPDATE
3295       && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3296     return 1;
3297   if (legitimate_small_data_p (mode, x))
3298     return 1;
3299   if (legitimate_constant_pool_address_p (x))
3300     return 1;
3301   /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
3302   if (! reg_ok_strict
3303       && GET_CODE (x) == PLUS
3304       && GET_CODE (XEXP (x, 0)) == REG
3305       && (XEXP (x, 0) == virtual_stack_vars_rtx
3306          || XEXP (x, 0) == arg_pointer_rtx)
3307       && GET_CODE (XEXP (x, 1)) == CONST_INT)
3308     return 1;
3309   if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3310     return 1;
3311   if (mode != TImode
3312       && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3313           || TARGET_POWERPC64
3314           || (mode != DFmode && mode != TFmode))
3315       && (TARGET_POWERPC64 || mode != DImode)
3316       && legitimate_indexed_address_p (x, reg_ok_strict))
3317     return 1;
3318   if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3319     return 1;
3320   return 0;
3321 }
3322
3323 /* Go to LABEL if ADDR (a legitimate address expression)
3324    has an effect that depends on the machine mode it is used for.
3325
3326    On the RS/6000 this is true of all integral offsets (since AltiVec
3327    modes don't allow them) or is a pre-increment or decrement.
3328
3329    ??? Except that due to conceptual problems in offsettable_address_p
3330    we can't really report the problems of integral offsets.  So leave
3331    this assuming that the adjustable offset must be valid for the
3332    sub-words of a TFmode operand, which is what we had before.  */
3333
3334 bool
3335 rs6000_mode_dependent_address (rtx addr)
3336 {
3337   switch (GET_CODE (addr))
3338     {
3339     case PLUS:
3340       if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3341         {
3342           unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3343           return val + 12 + 0x8000 >= 0x10000;
3344         }
3345       break;
3346
3347     case LO_SUM:
3348       return true;
3349
3350     case PRE_INC:
3351     case PRE_DEC:
3352       return TARGET_UPDATE;
3353
3354     default:
3355       break;
3356     }
3357
3358   return false;
3359 }
3360 \f
3361 /* Try to output insns to set TARGET equal to the constant C if it can
3362    be done in less than N insns.  Do all computations in MODE.
3363    Returns the place where the output has been placed if it can be
3364    done and the insns have been emitted.  If it would take more than N
3365    insns, zero is returned and no insns and emitted.  */
3366
3367 rtx
3368 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3369                        rtx source, int n ATTRIBUTE_UNUSED)
3370 {
3371   rtx result, insn, set;
3372   HOST_WIDE_INT c0, c1;
3373
3374   if (mode == QImode || mode == HImode)
3375     {
3376       if (dest == NULL)
3377         dest = gen_reg_rtx (mode);
3378       emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3379       return dest;
3380     }
3381   else if (mode == SImode)
3382     {
3383       result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3384
3385       emit_insn (gen_rtx_SET (VOIDmode, result,
3386                               GEN_INT (INTVAL (source)
3387                                        & (~ (HOST_WIDE_INT) 0xffff))));
3388       emit_insn (gen_rtx_SET (VOIDmode, dest,
3389                               gen_rtx_IOR (SImode, result,
3390                                            GEN_INT (INTVAL (source) & 0xffff))));
3391       result = dest;
3392     }
3393   else if (mode == DImode)
3394     {
3395       if (GET_CODE (source) == CONST_INT)
3396         {
3397           c0 = INTVAL (source);
3398           c1 = -(c0 < 0);
3399         }
3400       else if (GET_CODE (source) == CONST_DOUBLE)
3401         {
3402 #if HOST_BITS_PER_WIDE_INT >= 64
3403           c0 = CONST_DOUBLE_LOW (source);
3404           c1 = -(c0 < 0);
3405 #else
3406           c0 = CONST_DOUBLE_LOW (source);
3407           c1 = CONST_DOUBLE_HIGH (source);
3408 #endif
3409         }
3410       else
3411         abort ();
3412
3413       result = rs6000_emit_set_long_const (dest, c0, c1);
3414     }
3415   else
3416     abort ();
3417
3418   insn = get_last_insn ();
3419   set = single_set (insn);
3420   if (! CONSTANT_P (SET_SRC (set)))
3421     set_unique_reg_note (insn, REG_EQUAL, source);
3422
3423   return result;
3424 }
3425
3426 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3427    fall back to a straight forward decomposition.  We do this to avoid
3428    exponential run times encountered when looking for longer sequences
3429    with rs6000_emit_set_const.  */
3430 static rtx
3431 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3432 {
3433   if (!TARGET_POWERPC64)
3434     {
3435       rtx operand1, operand2;
3436
3437       operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3438                                         DImode);
3439       operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3440                                         DImode);
3441       emit_move_insn (operand1, GEN_INT (c1));
3442       emit_move_insn (operand2, GEN_INT (c2));
3443     }
3444   else
3445     {
3446       HOST_WIDE_INT ud1, ud2, ud3, ud4;
3447
3448       ud1 = c1 & 0xffff;
3449       ud2 = (c1 & 0xffff0000) >> 16;
3450 #if HOST_BITS_PER_WIDE_INT >= 64
3451       c2 = c1 >> 32;
3452 #endif
3453       ud3 = c2 & 0xffff;
3454       ud4 = (c2 & 0xffff0000) >> 16;
3455
3456       if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3457           || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3458         {
3459           if (ud1 & 0x8000)
3460             emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) -  0x8000)));
3461           else
3462             emit_move_insn (dest, GEN_INT (ud1));
3463         }
3464
3465       else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3466                || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3467         {
3468           if (ud2 & 0x8000)
3469             emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3470                                            - 0x80000000));
3471           else
3472             emit_move_insn (dest, GEN_INT (ud2 << 16));
3473           if (ud1 != 0)
3474             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3475         }
3476       else if ((ud4 == 0xffff && (ud3 & 0x8000))
3477                || (ud4 == 0 && ! (ud3 & 0x8000)))
3478         {
3479           if (ud3 & 0x8000)
3480             emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3481                                            - 0x80000000));
3482           else
3483             emit_move_insn (dest, GEN_INT (ud3 << 16));
3484
3485           if (ud2 != 0)
3486             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3487           emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3488           if (ud1 != 0)
3489             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3490         }
3491       else
3492         {
3493           if (ud4 & 0x8000)
3494             emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3495                                            - 0x80000000));
3496           else
3497             emit_move_insn (dest, GEN_INT (ud4 << 16));
3498
3499           if (ud3 != 0)
3500             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3501
3502           emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3503           if (ud2 != 0)
3504             emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3505                                                GEN_INT (ud2 << 16)));
3506           if (ud1 != 0)
3507             emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3508         }
3509     }
3510   return dest;
3511 }
3512
3513 /* Emit a move from SOURCE to DEST in mode MODE.  */
3514 void
3515 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3516 {
3517   rtx operands[2];
3518   operands[0] = dest;
3519   operands[1] = source;
3520
3521   /* Sanity checks.  Check that we get CONST_DOUBLE only when we should.  */
3522   if (GET_CODE (operands[1]) == CONST_DOUBLE
3523       && ! FLOAT_MODE_P (mode)
3524       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3525     {
3526       /* FIXME.  This should never happen.  */
3527       /* Since it seems that it does, do the safe thing and convert
3528          to a CONST_INT.  */
3529       operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3530     }
3531   if (GET_CODE (operands[1]) == CONST_DOUBLE
3532       && ! FLOAT_MODE_P (mode)
3533       && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3534            && CONST_DOUBLE_LOW (operands[1]) >= 0)
3535           || (CONST_DOUBLE_HIGH (operands[1]) == -1
3536               && CONST_DOUBLE_LOW (operands[1]) < 0)))
3537     abort ();
3538
3539   /* Check if GCC is setting up a block move that will end up using FP
3540      registers as temporaries.  We must make sure this is acceptable.  */
3541   if (GET_CODE (operands[0]) == MEM
3542       && GET_CODE (operands[1]) == MEM
3543       && mode == DImode
3544       && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3545           || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3546       && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3547                                             ? 32 : MEM_ALIGN (operands[0])))
3548             || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3549                                                ? 32
3550                                                : MEM_ALIGN (operands[1]))))
3551       && ! MEM_VOLATILE_P (operands [0])
3552       && ! MEM_VOLATILE_P (operands [1]))
3553     {
3554       emit_move_insn (adjust_address (operands[0], SImode, 0),
3555                       adjust_address (operands[1], SImode, 0));
3556       emit_move_insn (adjust_address (operands[0], SImode, 4),
3557                       adjust_address (operands[1], SImode, 4));
3558       return;
3559     }
3560
3561   if (!no_new_pseudos)
3562     {
3563       if (GET_CODE (operands[1]) == MEM && optimize > 0
3564           && (mode == QImode || mode == HImode || mode == SImode)
3565           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3566         {
3567           rtx reg = gen_reg_rtx (word_mode);
3568
3569           emit_insn (gen_rtx_SET (word_mode, reg,
3570                                   gen_rtx_ZERO_EXTEND (word_mode,
3571                                                        operands[1])));
3572           operands[1] = gen_lowpart (mode, reg);
3573         }
3574       if (GET_CODE (operands[0]) != REG)
3575         operands[1] = force_reg (mode, operands[1]);
3576     }
3577
3578   if (mode == SFmode && ! TARGET_POWERPC
3579       && TARGET_HARD_FLOAT && TARGET_FPRS
3580       && GET_CODE (operands[0]) == MEM)
3581     {
3582       int regnum;
3583
3584       if (reload_in_progress || reload_completed)
3585         regnum = true_regnum (operands[1]);
3586       else if (GET_CODE (operands[1]) == REG)
3587         regnum = REGNO (operands[1]);
3588       else
3589         regnum = -1;
3590
3591       /* If operands[1] is a register, on POWER it may have
3592          double-precision data in it, so truncate it to single
3593          precision.  */
3594       if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3595         {
3596           rtx newreg;
3597           newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3598           emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3599           operands[1] = newreg;
3600         }
3601     }
3602
3603   /* Recognize the case where operand[1] is a reference to thread-local
3604      data and load its address to a register.  */
3605   if (GET_CODE (operands[1]) == SYMBOL_REF)
3606     {
3607       enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3608       if (model != 0)
3609         operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3610     }
3611
3612   /* Handle the case where reload calls us with an invalid address.  */
3613   if (reload_in_progress && mode == Pmode
3614       && (! general_operand (operands[1], mode)
3615           || ! nonimmediate_operand (operands[0], mode)))
3616     goto emit_set;
3617
3618   /* Handle the case of CONSTANT_P_RTX.  */
3619   if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3620     goto emit_set;
3621
3622   /* 128-bit constant floating-point values on Darwin should really be
3623      loaded as two parts.  */
3624   if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3625       && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3626       && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3627     {
3628       /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3629          know how to get a DFmode SUBREG of a TFmode.  */
3630       rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3631                         simplify_gen_subreg (DImode, operands[1], mode, 0),
3632                         DImode);
3633       rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3634                                              GET_MODE_SIZE (DImode)),
3635                         simplify_gen_subreg (DImode, operands[1], mode,
3636                                              GET_MODE_SIZE (DImode)),
3637                         DImode);
3638       return;
3639     }
3640
3641   /* FIXME:  In the long term, this switch statement should go away
3642      and be replaced by a sequence of tests based on things like
3643      mode == Pmode.  */
3644   switch (mode)
3645     {
3646     case HImode:
3647     case QImode:
3648       if (CONSTANT_P (operands[1])
3649           && GET_CODE (operands[1]) != CONST_INT)
3650         operands[1] = force_const_mem (mode, operands[1]);
3651       break;
3652
3653     case TFmode:
3654     case DFmode:
3655     case SFmode:
3656       if (CONSTANT_P (operands[1])
3657           && ! easy_fp_constant (operands[1], mode))
3658         operands[1] = force_const_mem (mode, operands[1]);
3659       break;
3660
3661     case V16QImode:
3662     case V8HImode:
3663     case V4SFmode:
3664     case V4SImode:
3665     case V4HImode:
3666     case V2SFmode:
3667     case V2SImode:
3668     case V1DImode:
3669       if (CONSTANT_P (operands[1])
3670           && !easy_vector_constant (operands[1], mode))
3671         operands[1] = force_const_mem (mode, operands[1]);
3672       break;
3673
3674     case SImode:
3675     case DImode:
3676       /* Use default pattern for address of ELF small data */
3677       if (TARGET_ELF
3678           && mode == Pmode
3679           && DEFAULT_ABI == ABI_V4
3680           && (GET_CODE (operands[1]) == SYMBOL_REF
3681               || GET_CODE (operands[1]) == CONST)
3682           && small_data_operand (operands[1], mode))
3683         {
3684           emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3685           return;
3686         }
3687
3688       if (DEFAULT_ABI == ABI_V4
3689           && mode == Pmode && mode == SImode
3690           && flag_pic == 1 && got_operand (operands[1], mode))
3691         {
3692           emit_insn (gen_movsi_got (operands[0], operands[1]));
3693           return;
3694         }
3695
3696       if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3697           && TARGET_NO_TOC
3698           && ! flag_pic
3699           && mode == Pmode
3700           && CONSTANT_P (operands[1])
3701           && GET_CODE (operands[1]) != HIGH
3702           && GET_CODE (operands[1]) != CONST_INT)
3703         {
3704           rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3705
3706           /* If this is a function address on -mcall-aixdesc,
3707              convert it to the address of the descriptor.  */
3708           if (DEFAULT_ABI == ABI_AIX
3709               && GET_CODE (operands[1]) == SYMBOL_REF
3710               && XSTR (operands[1], 0)[0] == '.')
3711             {
3712               const char *name = XSTR (operands[1], 0);
3713               rtx new_ref;
3714               while (*name == '.')
3715                 name++;
3716               new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3717               CONSTANT_POOL_ADDRESS_P (new_ref)
3718                 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3719               SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3720               SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3721               SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3722               operands[1] = new_ref;
3723             }
3724
3725           if (DEFAULT_ABI == ABI_DARWIN)
3726             {
3727 #if TARGET_MACHO
3728               if (MACHO_DYNAMIC_NO_PIC_P)
3729                 {
3730                   /* Take care of any required data indirection.  */
3731                   operands[1] = rs6000_machopic_legitimize_pic_address (
3732                                   operands[1], mode, operands[0]);
3733                   if (operands[0] != operands[1])
3734                     emit_insn (gen_rtx_SET (VOIDmode,
3735                                             operands[0], operands[1]));
3736                   return;
3737                 }
3738 #endif
3739               emit_insn (gen_macho_high (target, operands[1]));
3740               emit_insn (gen_macho_low (operands[0], target, operands[1]));
3741               return;
3742             }
3743
3744           emit_insn (gen_elf_high (target, operands[1]));
3745           emit_insn (gen_elf_low (operands[0], target, operands[1]));
3746           return;
3747         }
3748
3749       /* If this is a SYMBOL_REF that refers to a constant pool entry,
3750          and we have put it in the TOC, we just need to make a TOC-relative
3751          reference to it.  */
3752       if (TARGET_TOC
3753           && GET_CODE (operands[1]) == SYMBOL_REF
3754           && constant_pool_expr_p (operands[1])
3755           && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3756                                               get_pool_mode (operands[1])))
3757         {
3758           operands[1] = create_TOC_reference (operands[1]);
3759         }
3760       else if (mode == Pmode
3761                && CONSTANT_P (operands[1])
3762                && ((GET_CODE (operands[1]) != CONST_INT
3763                     && ! easy_fp_constant (operands[1], mode))
3764                    || (GET_CODE (operands[1]) == CONST_INT
3765                        && num_insns_constant (operands[1], mode) > 2)
3766                    || (GET_CODE (operands[0]) == REG
3767                        && FP_REGNO_P (REGNO (operands[0]))))
3768                && GET_CODE (operands[1]) != HIGH
3769                && ! legitimate_constant_pool_address_p (operands[1])
3770                && ! toc_relative_expr_p (operands[1]))
3771         {
3772           /* Emit a USE operation so that the constant isn't deleted if
3773              expensive optimizations are turned on because nobody
3774              references it.  This should only be done for operands that
3775              contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3776              This should not be done for operands that contain LABEL_REFs.
3777              For now, we just handle the obvious case.  */
3778           if (GET_CODE (operands[1]) != LABEL_REF)
3779             emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3780
3781 #if TARGET_MACHO
3782           /* Darwin uses a special PIC legitimizer.  */
3783           if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3784             {
3785               operands[1] =
3786                 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3787                                                         operands[0]);
3788               if (operands[0] != operands[1])
3789                 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3790               return;
3791             }
3792 #endif
3793
3794           /* If we are to limit the number of things we put in the TOC and
3795              this is a symbol plus a constant we can add in one insn,
3796              just put the symbol in the TOC and add the constant.  Don't do
3797              this if reload is in progress.  */
3798           if (GET_CODE (operands[1]) == CONST
3799               && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3800               && GET_CODE (XEXP (operands[1], 0)) == PLUS
3801               && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3802               && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3803                   || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3804               && ! side_effects_p (operands[0]))
3805             {
3806               rtx sym =
3807                 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3808               rtx other = XEXP (XEXP (operands[1], 0), 1);
3809
3810               sym = force_reg (mode, sym);
3811               if (mode == SImode)
3812                 emit_insn (gen_addsi3 (operands[0], sym, other));
3813               else
3814                 emit_insn (gen_adddi3 (operands[0], sym, other));
3815               return;
3816             }
3817
3818           operands[1] = force_const_mem (mode, operands[1]);
3819
3820           if (TARGET_TOC
3821               && constant_pool_expr_p (XEXP (operands[1], 0))
3822               && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3823                         get_pool_constant (XEXP (operands[1], 0)),
3824                         get_pool_mode (XEXP (operands[1], 0))))
3825             {
3826               operands[1]
3827                 = gen_rtx_MEM (mode,
3828                                create_TOC_reference (XEXP (operands[1], 0)));
3829               set_mem_alias_set (operands[1], get_TOC_alias_set ());
3830               RTX_UNCHANGING_P (operands[1]) = 1;
3831             }
3832         }
3833       break;
3834
3835     case TImode:
3836       if (GET_CODE (operands[0]) == MEM
3837           && GET_CODE (XEXP (operands[0], 0)) != REG
3838           && ! reload_in_progress)
3839         operands[0]
3840           = replace_equiv_address (operands[0],
3841                                    copy_addr_to_reg (XEXP (operands[0], 0)));
3842
3843       if (GET_CODE (operands[1]) == MEM
3844           && GET_CODE (XEXP (operands[1], 0)) != REG
3845           && ! reload_in_progress)
3846         operands[1]
3847           = replace_equiv_address (operands[1],
3848                                    copy_addr_to_reg (XEXP (operands[1], 0)));
3849       if (TARGET_POWER)
3850         {
3851           emit_insn (gen_rtx_PARALLEL (VOIDmode,
3852                        gen_rtvec (2,
3853                                   gen_rtx_SET (VOIDmode,
3854                                                operands[0], operands[1]),
3855                                   gen_rtx_CLOBBER (VOIDmode,
3856                                                    gen_rtx_SCRATCH (SImode)))));
3857           return;
3858         }
3859       break;
3860
3861     default:
3862       abort ();
3863     }
3864
3865   /* Above, we may have called force_const_mem which may have returned
3866      an invalid address.  If we can, fix this up; otherwise, reload will
3867      have to deal with it.  */
3868   if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3869     operands[1] = validize_mem (operands[1]);
3870
3871  emit_set:
3872   emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3873 }
3874 \f
3875 /* Nonzero if we can use a floating-point register to pass this arg.  */
3876 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE)         \
3877   (GET_MODE_CLASS (MODE) == MODE_FLOAT          \
3878    && (CUM)->fregno <= FP_ARG_MAX_REG           \
3879    && TARGET_HARD_FLOAT && TARGET_FPRS)
3880
3881 /* Nonzero if we can use an AltiVec register to pass this arg.  */
3882 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED)      \
3883   (ALTIVEC_VECTOR_MODE (MODE)                           \
3884    && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG              \
3885    && TARGET_ALTIVEC_ABI                                \
3886    && (NAMED))
3887
3888 /* Return a nonzero value to say to return the function value in
3889    memory, just as large structures are always returned.  TYPE will be
3890    the data type of the value, and FNTYPE will be the type of the
3891    function doing the returning, or @code{NULL} for libcalls.
3892
3893    The AIX ABI for the RS/6000 specifies that all structures are
3894    returned in memory.  The Darwin ABI does the same.  The SVR4 ABI
3895    specifies that structures <= 8 bytes are returned in r3/r4, but a
3896    draft put them in memory, and GCC used to implement the draft
3897    instead of the final standard.  Therefore, TARGET_AIX_STRUCT_RET
3898    controls this instead of DEFAULT_ABI; V.4 targets needing backward
3899    compatibility can change DRAFT_V4_STRUCT_RET to override the
3900    default, and -m switches get the final word.  See
3901    rs6000_override_options for more details.
3902
3903    The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3904    long double support is enabled.  These values are returned in memory.
3905
3906    int_size_in_bytes returns -1 for variable size objects, which go in
3907    memory always.  The cast to unsigned makes -1 > 8.  */
3908
3909 static bool
3910 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3911 {
3912   if (AGGREGATE_TYPE_P (type)
3913       && (TARGET_AIX_STRUCT_RET
3914           || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3915     return true;
3916   if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3917     return true;
3918   return false;
3919 }
3920
3921 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3922    for a call to a function whose data type is FNTYPE.
3923    For a library call, FNTYPE is 0.
3924
3925    For incoming args we set the number of arguments in the prototype large
3926    so we never return a PARALLEL.  */
3927
3928 void
3929 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3930                       rtx libname ATTRIBUTE_UNUSED, int incoming,
3931                       int libcall, int n_named_args)
3932 {
3933   static CUMULATIVE_ARGS zero_cumulative;
3934
3935   *cum = zero_cumulative;
3936   cum->words = 0;
3937   cum->fregno = FP_ARG_MIN_REG;
3938   cum->vregno = ALTIVEC_ARG_MIN_REG;
3939   cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3940   cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3941                       ? CALL_LIBCALL : CALL_NORMAL);
3942   cum->sysv_gregno = GP_ARG_MIN_REG;
3943   cum->stdarg = fntype
3944     && (TYPE_ARG_TYPES (fntype) != 0
3945         && (TREE_VALUE (tree_last  (TYPE_ARG_TYPES (fntype)))
3946             != void_type_node));
3947
3948   cum->nargs_prototype = 0;
3949   if (incoming || cum->prototype)
3950     cum->nargs_prototype = n_named_args;
3951
3952   /* Check for a longcall attribute.  */
3953   if (fntype
3954       && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3955       && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3956     cum->call_cookie = CALL_LONG;
3957
3958   if (TARGET_DEBUG_ARG)
3959     {
3960       fprintf (stderr, "\ninit_cumulative_args:");
3961       if (fntype)
3962         {
3963           tree ret_type = TREE_TYPE (fntype);
3964           fprintf (stderr, " ret code = %s,",
3965                    tree_code_name[ (int)TREE_CODE (ret_type) ]);
3966         }
3967
3968       if (cum->call_cookie & CALL_LONG)
3969         fprintf (stderr, " longcall,");
3970
3971       fprintf (stderr, " proto = %d, nargs = %d\n",
3972                cum->prototype, cum->nargs_prototype);
3973     }
3974
3975     if (fntype
3976         && !TARGET_ALTIVEC
3977         && TARGET_ALTIVEC_ABI
3978         && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3979       {
3980         error ("Cannot return value in vector register because"
3981                " altivec instructions are disabled, use -maltivec"
3982                " to enable them.");
3983       }
3984 }
3985 \f
3986 /* If defined, a C expression which determines whether, and in which
3987    direction, to pad out an argument with extra space.  The value
3988    should be of type `enum direction': either `upward' to pad above
3989    the argument, `downward' to pad below, or `none' to inhibit
3990    padding.
3991
3992    For the AIX ABI structs are always stored left shifted in their
3993    argument slot.  */
3994
3995 enum direction
3996 function_arg_padding (enum machine_mode mode, tree type)
3997 {
3998 #ifndef AGGREGATE_PADDING_FIXED
3999 #define AGGREGATE_PADDING_FIXED 0
4000 #endif
4001 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4002 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4003 #endif
4004
4005   if (!AGGREGATE_PADDING_FIXED)
4006     {
4007       /* GCC used to pass structures of the same size as integer types as
4008          if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4009          ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4010          passed padded downward, except that -mstrict-align further
4011          muddied the water in that multi-component structures of 2 and 4
4012          bytes in size were passed padded upward.
4013
4014          The following arranges for best compatibility with previous
4015          versions of gcc, but removes the -mstrict-align dependency.  */
4016       if (BYTES_BIG_ENDIAN)
4017         {
4018           HOST_WIDE_INT size = 0;
4019
4020           if (mode == BLKmode)
4021             {
4022               if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4023                 size = int_size_in_bytes (type);
4024             }
4025           else
4026             size = GET_MODE_SIZE (mode);
4027
4028           if (size == 1 || size == 2 || size == 4)
4029             return downward;
4030         }
4031       return upward;
4032     }
4033
4034   if (AGGREGATES_PAD_UPWARD_ALWAYS)
4035     {
4036       if (type != 0 && AGGREGATE_TYPE_P (type))
4037         return upward;
4038     }
4039
4040   /* Fall back to the default.  */
4041   return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4042 }
4043
4044 /* If defined, a C expression that gives the alignment boundary, in bits,
4045    of an argument with the specified mode and type.  If it is not defined,
4046    PARM_BOUNDARY is used for all arguments.
4047
4048    V.4 wants long longs to be double word aligned.  */
4049
4050 int
4051 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
4052 {
4053   if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
4054     return 64;
4055    else if (SPE_VECTOR_MODE (mode))
4056      return 64;
4057   else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4058     return 128;
4059   else
4060     return PARM_BOUNDARY;
4061 }
4062
4063 /* Compute the size (in words) of a function argument.  */
4064
4065 static unsigned long
4066 rs6000_arg_size (enum machine_mode mode, tree type)
4067 {
4068   unsigned long size;
4069
4070   if (mode != BLKmode)
4071     size = GET_MODE_SIZE (mode);
4072   else
4073     size = int_size_in_bytes (type);
4074
4075   if (TARGET_32BIT)
4076     return (size + 3) >> 2;
4077   else
4078     return (size + 7) >> 3;
4079 }
4080 \f
4081 /* Update the data in CUM to advance over an argument
4082    of mode MODE and data type TYPE.
4083    (TYPE is null for libcalls where that information may not be available.)  */
4084
4085 void
4086 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4087                       tree type, int named)
4088 {
4089   cum->nargs_prototype--;
4090
4091   if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4092     {
4093       if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4094         {
4095           cum->vregno++;
4096           if (!TARGET_ALTIVEC)
4097             error ("Cannot pass argument in vector register because"
4098                    " altivec instructions are disabled, use -maltivec"
4099                    " to enable them.");
4100         }
4101       /* PowerPC64 Linux and AIX allocates GPRs for a vector argument
4102          even if it is going to be passed in a vector register.
4103          Darwin does the same for variable-argument functions.  */
4104       if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4105                    || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4106         {
4107           int align;
4108
4109           /* Vector parameters must be 16-byte aligned.  This places
4110              them at 2 mod 4 in terms of words in 32-bit mode, since
4111              the parameter save area starts at offset 24 from the
4112              stack.  In 64-bit mode, they just have to start on an
4113              even word, since the parameter save area is 16-byte
4114              aligned.  Space for GPRs is reserved even if the argument
4115              will be passed in memory.  */
4116           if (TARGET_32BIT)
4117             align = ((6 - (cum->words & 3)) & 3);
4118           else
4119             align = cum->words & 1;
4120           cum->words += align + rs6000_arg_size (mode, type);
4121
4122           if (TARGET_DEBUG_ARG)
4123             {
4124               fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4125                        cum->words, align);
4126               fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4127                        cum->nargs_prototype, cum->prototype,
4128                        GET_MODE_NAME (mode));
4129             }
4130         }
4131     }
4132   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4133            && !cum->stdarg
4134            && cum->sysv_gregno <= GP_ARG_MAX_REG)
4135     cum->sysv_gregno++;
4136   else if (DEFAULT_ABI == ABI_V4)
4137     {
4138       if (TARGET_HARD_FLOAT && TARGET_FPRS
4139           && (mode == SFmode || mode == DFmode))
4140         {
4141           if (cum->fregno <= FP_ARG_V4_MAX_REG)
4142             cum->fregno++;
4143           else
4144             {
4145               if (mode == DFmode)
4146                 cum->words += cum->words & 1;
4147               cum->words += rs6000_arg_size (mode, type);
4148             }
4149         }
4150       else
4151         {
4152           int n_words;
4153           int gregno = cum->sysv_gregno;
4154
4155           /* Aggregates and IEEE quad get passed by reference.  */
4156           if ((type && AGGREGATE_TYPE_P (type))
4157               || mode == TFmode)
4158             n_words = 1;
4159           else
4160             n_words = rs6000_arg_size (mode, type);
4161
4162           /* Long long and SPE vectors are put in odd registers.  */
4163           if (n_words == 2 && (gregno & 1) == 0)
4164             gregno += 1;
4165
4166           /* Long long and SPE vectors are not split between registers
4167              and stack.  */
4168           if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4169             {
4170               /* Long long is aligned on the stack.  */
4171               if (n_words == 2)
4172                 cum->words += cum->words & 1;
4173               cum->words += n_words;
4174             }
4175
4176           /* Note: continuing to accumulate gregno past when we've started
4177              spilling to the stack indicates the fact that we've started
4178              spilling to the stack to expand_builtin_saveregs.  */
4179           cum->sysv_gregno = gregno + n_words;
4180         }
4181
4182       if (TARGET_DEBUG_ARG)
4183         {
4184           fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4185                    cum->words, cum->fregno);
4186           fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4187                    cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4188           fprintf (stderr, "mode = %4s, named = %d\n",
4189                    GET_MODE_NAME (mode), named);
4190         }
4191     }
4192   else
4193     {
4194       int align = (TARGET_32BIT && (cum->words & 1) != 0
4195                    && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4196
4197       cum->words += align + rs6000_arg_size (mode, type);
4198
4199       if (GET_MODE_CLASS (mode) == MODE_FLOAT
4200           && TARGET_HARD_FLOAT && TARGET_FPRS)
4201         cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4202
4203       if (TARGET_DEBUG_ARG)
4204         {
4205           fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4206                    cum->words, cum->fregno);
4207           fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4208                    cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4209           fprintf (stderr, "named = %d, align = %d\n", named, align);
4210         }
4211     }
4212 }
4213
4214 /* Determine where to put a SIMD argument on the SPE.  */
4215
4216 static rtx
4217 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4218                          tree type)
4219 {
4220   if (cum->stdarg)
4221     {
4222       int gregno = cum->sysv_gregno;
4223       int n_words = rs6000_arg_size (mode, type);
4224
4225       /* SPE vectors are put in odd registers.  */
4226       if (n_words == 2 && (gregno & 1) == 0)
4227         gregno += 1;
4228
4229       if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4230         {
4231           rtx r1, r2;
4232           enum machine_mode m = SImode;
4233
4234           r1 = gen_rtx_REG (m, gregno);
4235           r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4236           r2 = gen_rtx_REG (m, gregno + 1);
4237           r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4238           return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4239         }
4240       else
4241         return NULL_RTX;
4242     }
4243   else
4244     {
4245       if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4246         return gen_rtx_REG (mode, cum->sysv_gregno);
4247       else
4248         return NULL_RTX;
4249     }
4250 }
4251
4252 /* Determine where to place an argument in 64-bit mode with 32-bit ABI.  */
4253
4254 static rtx
4255 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4256                            tree type, int align_words)
4257 {
4258   if (mode == DFmode)
4259     {
4260       /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4261          in vararg list into zero, one or two GPRs */
4262       if (align_words >= GP_ARG_NUM_REG)
4263         return gen_rtx_PARALLEL (DFmode,
4264                  gen_rtvec (2,
4265                             gen_rtx_EXPR_LIST (VOIDmode,
4266                                                NULL_RTX, const0_rtx),
4267                             gen_rtx_EXPR_LIST (VOIDmode,
4268                                                gen_rtx_REG (mode,
4269                                                             cum->fregno),
4270                                                const0_rtx)));
4271       else if (align_words + rs6000_arg_size (mode, type)
4272                > GP_ARG_NUM_REG)
4273         /* If this is partially on the stack, then we only
4274            include the portion actually in registers here.  */
4275         return gen_rtx_PARALLEL (DFmode,
4276                  gen_rtvec (2,
4277                             gen_rtx_EXPR_LIST (VOIDmode,
4278                                                gen_rtx_REG (SImode,
4279                                                             GP_ARG_MIN_REG
4280                                                             + align_words),
4281                                                const0_rtx),
4282                             gen_rtx_EXPR_LIST (VOIDmode,
4283                                                gen_rtx_REG (mode,
4284                                                             cum->fregno),
4285                                                const0_rtx)));
4286
4287       /* split a DFmode arg into two GPRs */
4288       return gen_rtx_PARALLEL (DFmode,
4289                gen_rtvec (3,
4290                           gen_rtx_EXPR_LIST (VOIDmode,
4291                                              gen_rtx_REG (SImode,
4292                                                           GP_ARG_MIN_REG
4293                                                           + align_words),
4294                                              const0_rtx),
4295                           gen_rtx_EXPR_LIST (VOIDmode,
4296                                              gen_rtx_REG (SImode,
4297                                                           GP_ARG_MIN_REG
4298                                                           + align_words + 1),
4299                                              GEN_INT (4)),
4300                           gen_rtx_EXPR_LIST (VOIDmode,
4301                                              gen_rtx_REG (mode, cum->fregno),
4302                                              const0_rtx)));
4303     }
4304   /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4305      or two GPRs */
4306   else if (mode == DImode)
4307     {
4308       if (align_words < GP_ARG_NUM_REG - 1)
4309         return gen_rtx_PARALLEL (DImode,
4310                  gen_rtvec (2,
4311                             gen_rtx_EXPR_LIST (VOIDmode,
4312                                                gen_rtx_REG (SImode,
4313                                                             GP_ARG_MIN_REG
4314                                                             + align_words),
4315                                                const0_rtx),
4316                             gen_rtx_EXPR_LIST (VOIDmode,
4317                                                gen_rtx_REG (SImode,
4318                                                             GP_ARG_MIN_REG
4319                                                             + align_words + 1),
4320                                                GEN_INT (4))));
4321       else if (align_words == GP_ARG_NUM_REG - 1)
4322           return gen_rtx_PARALLEL (DImode,
4323                    gen_rtvec (2,
4324                               gen_rtx_EXPR_LIST (VOIDmode,
4325                                                  NULL_RTX, const0_rtx),
4326                               gen_rtx_EXPR_LIST (VOIDmode,
4327                                                  gen_rtx_REG (SImode,
4328                                                               GP_ARG_MIN_REG
4329                                                               + align_words),
4330                                                  const0_rtx)));
4331     }
4332   else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1))
4333     {
4334       int k;
4335       int size = int_size_in_bytes (type);
4336       int no_units = ((size - 1) / 4) + 1;
4337       int max_no_words = GP_ARG_NUM_REG - align_words;
4338       int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4339       rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4340
4341       memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4342
4343       for (k=0; k < rtlvec_len; k++)
4344         rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4345                                        gen_rtx_REG (SImode,
4346                                                     GP_ARG_MIN_REG
4347                                                     + align_words + k),
4348                                        k == 0 ? const0_rtx : GEN_INT (k*4));
4349
4350       return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec));
4351   }
4352
4353   return NULL_RTX;
4354 }
4355
4356 /* Determine where to put an argument to a function.
4357    Value is zero to push the argument on the stack,
4358    or a hard register in which to store the argument.
4359
4360    MODE is the argument's machine mode.
4361    TYPE is the data type of the argument (as a tree).
4362     This is null for libcalls where that information may
4363     not be available.
4364    CUM is a variable of type CUMULATIVE_ARGS which gives info about
4365     the preceding args and about the function being called.
4366    NAMED is nonzero if this argument is a named parameter
4367     (otherwise it is an extra parameter matching an ellipsis).
4368
4369    On RS/6000 the first eight words of non-FP are normally in registers
4370    and the rest are pushed.  Under AIX, the first 13 FP args are in registers.
4371    Under V.4, the first 8 FP args are in registers.
4372
4373    If this is floating-point and no prototype is specified, we use
4374    both an FP and integer register (or possibly FP reg and stack).  Library
4375    functions (when CALL_LIBCALL is set) always have the proper types for args,
4376    so we can pass the FP value just in one register.  emit_library_function
4377    doesn't support PARALLEL anyway.  */
4378
4379 struct rtx_def *
4380 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4381               tree type, int named)
4382 {
4383   enum rs6000_abi abi = DEFAULT_ABI;
4384
4385   /* Return a marker to indicate whether CR1 needs to set or clear the
4386      bit that V.4 uses to say fp args were passed in registers.
4387      Assume that we don't need the marker for software floating point,
4388      or compiler generated library calls.  */
4389   if (mode == VOIDmode)
4390     {
4391       if (abi == ABI_V4
4392           && cum->nargs_prototype < 0
4393           && (cum->call_cookie & CALL_LIBCALL) == 0
4394           && (cum->prototype || TARGET_NO_PROTOTYPE))
4395         {
4396           /* For the SPE, we need to crxor CR6 always.  */
4397           if (TARGET_SPE_ABI)
4398             return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4399           else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4400             return GEN_INT (cum->call_cookie
4401                             | ((cum->fregno == FP_ARG_MIN_REG)
4402                                ? CALL_V4_SET_FP_ARGS
4403                                : CALL_V4_CLEAR_FP_ARGS));
4404         }
4405
4406       return GEN_INT (cum->call_cookie);
4407     }
4408
4409   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4410     if (TARGET_64BIT && ! cum->prototype)
4411       {
4412        /* Vector parameters get passed in vector register
4413           and also in GPRs or memory, in absence of prototype.  */
4414        int align_words;
4415        rtx slot;
4416        align_words = (cum->words + 1) & ~1;
4417
4418        if (align_words >= GP_ARG_NUM_REG)
4419          {
4420            slot = NULL_RTX;
4421          }
4422        else
4423          {
4424            slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4425          }
4426        return gen_rtx_PARALLEL (mode,
4427                 gen_rtvec (2,
4428                            gen_rtx_EXPR_LIST (VOIDmode,
4429                                               slot, const0_rtx),
4430                            gen_rtx_EXPR_LIST (VOIDmode,
4431                                               gen_rtx_REG (mode, cum->vregno),
4432                                               const0_rtx)));
4433       }
4434     else
4435       return gen_rtx_REG (mode, cum->vregno);
4436   else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4437     {
4438       if (named || abi == ABI_V4)
4439         return NULL_RTX;
4440       else
4441         {
4442           /* Vector parameters to varargs functions under AIX or Darwin
4443              get passed in memory and possibly also in GPRs.  */
4444           int align, align_words;
4445           enum machine_mode part_mode = mode;
4446
4447           /* Vector parameters must be 16-byte aligned.  This places them at
4448              2 mod 4 in terms of words in 32-bit mode, since the parameter
4449              save area starts at offset 24 from the stack.  In 64-bit mode,
4450              they just have to start on an even word, since the parameter
4451              save area is 16-byte aligned.  */
4452           if (TARGET_32BIT)
4453             align = ((6 - (cum->words & 3)) & 3);
4454           else
4455             align = cum->words & 1;
4456           align_words = cum->words + align;
4457
4458           /* Out of registers?  Memory, then.  */
4459           if (align_words >= GP_ARG_NUM_REG)
4460             return NULL_RTX;
4461
4462           /* The vector value goes in GPRs.  Only the part of the
4463              value in GPRs is reported here.  */
4464           if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4465               > GP_ARG_NUM_REG)
4466             /* Fortunately, there are only two possibilities, the value
4467                is either wholly in GPRs or half in GPRs and half not.  */
4468             part_mode = DImode;
4469
4470           return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4471         }
4472     }
4473   else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4474     return rs6000_spe_function_arg (cum, mode, type);
4475   else if (abi == ABI_V4)
4476     {
4477       if (TARGET_HARD_FLOAT && TARGET_FPRS
4478           && (mode == SFmode || mode == DFmode))
4479         {
4480           if (cum->fregno <= FP_ARG_V4_MAX_REG)
4481             return gen_rtx_REG (mode, cum->fregno);
4482           else
4483             return NULL_RTX;
4484         }
4485       else
4486         {
4487           int n_words;
4488           int gregno = cum->sysv_gregno;
4489
4490           /* Aggregates and IEEE quad get passed by reference.  */
4491           if ((type && AGGREGATE_TYPE_P (type))
4492               || mode == TFmode)
4493             n_words = 1;
4494           else
4495             n_words = rs6000_arg_size (mode, type);
4496
4497           /* Long long and SPE vectors are put in odd registers.  */
4498           if (n_words == 2 && (gregno & 1) == 0)
4499             gregno += 1;
4500
4501           /* Long long does not split between registers and stack.  */
4502           if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4503             return gen_rtx_REG (mode, gregno);
4504           else
4505             return NULL_RTX;
4506         }
4507     }
4508   else
4509     {
4510       int align = (TARGET_32BIT && (cum->words & 1) != 0
4511                    && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4512       int align_words = cum->words + align;
4513
4514       if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4515         return NULL_RTX;
4516
4517       if (TARGET_32BIT && TARGET_POWERPC64
4518           && (mode == DImode || mode == BLKmode))
4519         return rs6000_mixed_function_arg (cum, mode, type, align_words);
4520
4521       if (USE_FP_FOR_ARG_P (cum, mode, type))
4522         {
4523           rtx fpr[2];
4524           rtx *r;
4525           bool needs_psave;
4526           enum machine_mode fmode = mode;
4527           int n;
4528           unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4529
4530           if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4531             {
4532               /* Long double split over regs and memory.  */
4533               if (fmode == TFmode)
4534                 fmode = DFmode;
4535
4536               /* Currently, we only ever need one reg here because complex
4537                  doubles are split.  */
4538               if (cum->fregno != FP_ARG_MAX_REG - 1)
4539                 abort ();
4540             }
4541           fpr[1] = gen_rtx_REG (fmode, cum->fregno);
4542
4543           /* Do we also need to pass this arg in the parameter save
4544              area?  */
4545           needs_psave = (type
4546                          && (cum->nargs_prototype <= 0
4547                              || (DEFAULT_ABI == ABI_AIX
4548                                  && TARGET_XL_CALL
4549                                  && align_words >= GP_ARG_NUM_REG)));
4550
4551           if (!needs_psave && mode == fmode)
4552             return fpr[1];
4553
4554           if (TARGET_32BIT && TARGET_POWERPC64
4555               && mode == DFmode && cum->stdarg)
4556             return rs6000_mixed_function_arg (cum, mode, type, align_words);
4557
4558           /* Describe where this piece goes.  */
4559           r = fpr + 1;
4560           *r = gen_rtx_EXPR_LIST (VOIDmode, *r, const0_rtx);
4561           n = 1;
4562
4563           if (needs_psave)
4564             {
4565               /* Now describe the part that goes in gprs or the stack.
4566                  This piece must come first, before the fprs.  */
4567               rtx reg = NULL_RTX;
4568               if (align_words < GP_ARG_NUM_REG)
4569                 {
4570                   unsigned long n_words = rs6000_arg_size (mode, type);
4571                   enum machine_mode rmode = mode;
4572
4573                   if (align_words + n_words > GP_ARG_NUM_REG)
4574                     /* If this is partially on the stack, then we only
4575                        include the portion actually in registers here.
4576                        We know this can only be one register because
4577                        complex doubles are splt.  */
4578                     rmode = Pmode;
4579                   reg = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
4580                 }
4581               *--r = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
4582               ++n;
4583             }
4584
4585           return gen_rtx_PARALLEL (mode, gen_rtvec_v (n, r));
4586         }
4587       else if (align_words < GP_ARG_NUM_REG)
4588         return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4589       else
4590         return NULL_RTX;
4591     }
4592 }
4593 \f
4594 /* For an arg passed partly in registers and partly in memory,
4595    this is the number of registers used.
4596    For args passed entirely in registers or entirely in memory, zero.  */
4597
4598 int
4599 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4600                             tree type, int named)
4601 {
4602   int ret = 0;
4603
4604   if (DEFAULT_ABI == ABI_V4)
4605     return 0;
4606
4607   if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4608       && cum->nargs_prototype >= 0)
4609     return 0;
4610
4611   if (USE_FP_FOR_ARG_P (cum, mode, type))
4612     {
4613       if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4614         ret = FP_ARG_MAX_REG - cum->fregno;
4615       else if (cum->nargs_prototype >= 0)
4616         return 0;
4617     }
4618
4619   if (cum->words < GP_ARG_NUM_REG
4620       && GP_ARG_NUM_REG < cum->words + rs6000_arg_size (mode, type))
4621     ret = GP_ARG_NUM_REG - cum->words;
4622
4623   if (ret != 0 && TARGET_DEBUG_ARG)
4624     fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4625
4626   return ret;
4627 }
4628 \f
4629 /* A C expression that indicates when an argument must be passed by
4630    reference.  If nonzero for an argument, a copy of that argument is
4631    made in memory and a pointer to the argument is passed instead of
4632    the argument itself.  The pointer is passed in whatever way is
4633    appropriate for passing a pointer to that type.
4634
4635    Under V.4, structures and unions are passed by reference.
4636
4637    As an extension to all ABIs, variable sized types are passed by
4638    reference.  */
4639
4640 int
4641 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4642                                 enum machine_mode mode ATTRIBUTE_UNUSED,
4643                                 tree type, int named ATTRIBUTE_UNUSED)
4644 {
4645   if (DEFAULT_ABI == ABI_V4
4646       && ((type && AGGREGATE_TYPE_P (type))
4647           || mode == TFmode))
4648     {
4649       if (TARGET_DEBUG_ARG)
4650         fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4651
4652       return 1;
4653     }
4654   return type && int_size_in_bytes (type) < 0;
4655 }
4656
4657 static void
4658 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
4659 {
4660   int i;
4661   enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4662
4663   if (nregs == 0)
4664     return;
4665
4666     for (i = 0; i < nregs; i++)
4667     {
4668       rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4669       if (reload_completed)
4670       {
4671         if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4672           tem = NULL_RTX;
4673         else
4674           tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4675                                      i * GET_MODE_SIZE(reg_mode));
4676       }
4677       else
4678         tem = replace_equiv_address (tem, XEXP (tem, 0));
4679
4680       if (tem == NULL_RTX)
4681         abort ();
4682
4683       emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4684     }
4685 }
4686
4687 \f
4688 /* Perform any needed actions needed for a function that is receiving a
4689    variable number of arguments.
4690
4691    CUM is as above.
4692
4693    MODE and TYPE are the mode and type of the current parameter.
4694
4695    PRETEND_SIZE is a variable that should be set to the amount of stack
4696    that must be pushed by the prolog to pretend that our caller pushed
4697    it.
4698
4699    Normally, this macro will push all remaining incoming registers on the
4700    stack and set PRETEND_SIZE to the length of the registers pushed.  */
4701
4702 static void
4703 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4704                 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4705 {
4706   CUMULATIVE_ARGS next_cum;
4707   int reg_size = TARGET_32BIT ? 4 : 8;
4708   rtx save_area = NULL_RTX, mem;
4709   int first_reg_offset, set;
4710
4711   /* Skip the last named argument.  */
4712   next_cum = *cum;
4713   function_arg_advance (&next_cum, mode, type, 1);
4714
4715   if (DEFAULT_ABI == ABI_V4)
4716     {
4717       /* Indicate to allocate space on the stack for varargs save area.  */
4718       cfun->machine->sysv_varargs_p = 1;
4719       if (! no_rtl)
4720         save_area = plus_constant (virtual_stack_vars_rtx,
4721                                    - RS6000_VARARGS_SIZE);
4722
4723       first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4724     }
4725   else
4726     {
4727       first_reg_offset = next_cum.words;
4728       save_area = virtual_incoming_args_rtx;
4729       cfun->machine->sysv_varargs_p = 0;
4730
4731       if (MUST_PASS_IN_STACK (mode, type))
4732         first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4733     }
4734
4735   set = get_varargs_alias_set ();
4736   if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4737     {
4738       mem = gen_rtx_MEM (BLKmode,
4739                          plus_constant (save_area,
4740                                         first_reg_offset * reg_size)),
4741       set_mem_alias_set (mem, set);
4742       set_mem_align (mem, BITS_PER_WORD);
4743
4744       rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4745                                   GP_ARG_NUM_REG - first_reg_offset);
4746     }
4747
4748   /* Save FP registers if needed.  */
4749   if (DEFAULT_ABI == ABI_V4
4750       && TARGET_HARD_FLOAT && TARGET_FPRS
4751       && ! no_rtl
4752       && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4753     {
4754       int fregno = next_cum.fregno;
4755       rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4756       rtx lab = gen_label_rtx ();
4757       int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4758
4759       emit_jump_insn (gen_rtx_SET (VOIDmode,
4760                                    pc_rtx,
4761                                    gen_rtx_IF_THEN_ELSE (VOIDmode,
4762                                             gen_rtx_NE (VOIDmode, cr1,
4763                                                         const0_rtx),
4764                                             gen_rtx_LABEL_REF (VOIDmode, lab),
4765                                             pc_rtx)));
4766
4767       while (fregno <= FP_ARG_V4_MAX_REG)
4768         {
4769           mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4770           set_mem_alias_set (mem, set);
4771           emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4772           fregno++;
4773           off += 8;
4774         }
4775
4776       emit_label (lab);
4777     }
4778 }
4779
4780 /* Create the va_list data type.  */
4781
4782 static tree
4783 rs6000_build_builtin_va_list (void)
4784 {
4785   tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4786
4787   /* For AIX, prefer 'char *' because that's what the system
4788      header files like.  */
4789   if (DEFAULT_ABI != ABI_V4)
4790     return build_pointer_type (char_type_node);
4791
4792   record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4793   type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4794
4795   f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4796                       unsigned_char_type_node);
4797   f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4798                       unsigned_char_type_node);
4799   /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4800      every user file.  */
4801   f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4802                       short_unsigned_type_node);
4803   f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4804                       ptr_type_node);
4805   f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4806                       ptr_type_node);
4807
4808   DECL_FIELD_CONTEXT (f_gpr) = record;
4809   DECL_FIELD_CONTEXT (f_fpr) = record;
4810   DECL_FIELD_CONTEXT (f_res) = record;
4811   DECL_FIELD_CONTEXT (f_ovf) = record;
4812   DECL_FIELD_CONTEXT (f_sav) = record;
4813
4814   TREE_CHAIN (record) = type_decl;
4815   TYPE_NAME (record) = type_decl;
4816   TYPE_FIELDS (record) = f_gpr;
4817   TREE_CHAIN (f_gpr) = f_fpr;
4818   TREE_CHAIN (f_fpr) = f_res;
4819   TREE_CHAIN (f_res) = f_ovf;
4820   TREE_CHAIN (f_ovf) = f_sav;
4821
4822   layout_type (record);
4823
4824   /* The correct type is an array type of one element.  */
4825   return build_array_type (record, build_index_type (size_zero_node));
4826 }
4827
4828 /* Implement va_start.  */
4829
4830 void
4831 rs6000_va_start (tree valist, rtx nextarg)
4832 {
4833   HOST_WIDE_INT words, n_gpr, n_fpr;
4834   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4835   tree gpr, fpr, ovf, sav, t;
4836
4837   /* Only SVR4 needs something special.  */
4838   if (DEFAULT_ABI != ABI_V4)
4839     {
4840       std_expand_builtin_va_start (valist, nextarg);
4841       return;
4842     }
4843
4844   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4845   f_fpr = TREE_CHAIN (f_gpr);
4846   f_res = TREE_CHAIN (f_fpr);
4847   f_ovf = TREE_CHAIN (f_res);
4848   f_sav = TREE_CHAIN (f_ovf);
4849
4850   valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4851   gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4852   fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4853   ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4854   sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4855
4856   /* Count number of gp and fp argument registers used.  */
4857   words = current_function_args_info.words;
4858   n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4859   n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4860
4861   if (TARGET_DEBUG_ARG)
4862     fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4863              HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4864              words, n_gpr, n_fpr);
4865
4866   t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4867   TREE_SIDE_EFFECTS (t) = 1;
4868   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4869
4870   t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4871   TREE_SIDE_EFFECTS (t) = 1;
4872   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4873
4874   /* Find the overflow area.  */
4875   t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4876   if (words != 0)
4877     t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4878                build_int_2 (words * UNITS_PER_WORD, 0));
4879   t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4880   TREE_SIDE_EFFECTS (t) = 1;
4881   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4882
4883   /* Find the register save area.  */
4884   t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4885   t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4886              build_int_2 (-RS6000_VARARGS_SIZE, -1));
4887   t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4888   TREE_SIDE_EFFECTS (t) = 1;
4889   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4890 }
4891
4892 /* Implement va_arg.  */
4893
4894 rtx
4895 rs6000_va_arg (tree valist, tree type)
4896 {
4897   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4898   tree gpr, fpr, ovf, sav, reg, t, u;
4899   int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4900   rtx lab_false, lab_over, addr_rtx, r;
4901
4902   if (DEFAULT_ABI != ABI_V4)
4903     {
4904       /* Variable sized types are passed by reference.  */
4905       if (int_size_in_bytes (type) < 0)
4906         {
4907           u = build_pointer_type (type);
4908
4909           /* Args grow upward.  */
4910           t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4911                      build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4912           TREE_SIDE_EFFECTS (t) = 1;
4913
4914           t = build1 (NOP_EXPR, build_pointer_type (u), t);
4915           TREE_SIDE_EFFECTS (t) = 1;
4916
4917           t = build1 (INDIRECT_REF, u, t);
4918           TREE_SIDE_EFFECTS (t) = 1;
4919
4920           return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4921         }
4922       if (targetm.calls.split_complex_arg
4923           && TREE_CODE (type) == COMPLEX_TYPE)
4924         {
4925           tree elem_type = TREE_TYPE (type);
4926           enum machine_mode elem_mode = TYPE_MODE (elem_type);
4927           int elem_size = GET_MODE_SIZE (elem_mode);
4928
4929           if (elem_size < UNITS_PER_WORD)
4930             {
4931               rtx real_part, imag_part, dest_real, rr;
4932
4933               real_part = rs6000_va_arg (valist, elem_type);
4934               imag_part = rs6000_va_arg (valist, elem_type);
4935
4936               /* We're not returning the value here, but the address.
4937                  real_part and imag_part are not contiguous, and we know
4938                  there is space available to pack real_part next to
4939                  imag_part.  float _Complex is not promoted to
4940                  double _Complex by the default promotion rules that
4941                  promote float to double.  */
4942               if (2 * elem_size > UNITS_PER_WORD)
4943                 abort ();
4944
4945               real_part = gen_rtx_MEM (elem_mode, real_part);
4946               imag_part = gen_rtx_MEM (elem_mode, imag_part);
4947
4948               dest_real = adjust_address (imag_part, elem_mode, -elem_size);
4949               rr = gen_reg_rtx (elem_mode);
4950               emit_move_insn (rr, real_part);
4951               emit_move_insn (dest_real, rr);
4952
4953               return XEXP (dest_real, 0);
4954             }
4955         }
4956
4957       return std_expand_builtin_va_arg (valist, type);
4958     }
4959
4960   f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4961   f_fpr = TREE_CHAIN (f_gpr);
4962   f_res = TREE_CHAIN (f_fpr);
4963   f_ovf = TREE_CHAIN (f_res);
4964   f_sav = TREE_CHAIN (f_ovf);
4965
4966   valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4967   gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4968   fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4969   ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4970   sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4971
4972   size = int_size_in_bytes (type);
4973   rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4974
4975   if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4976     {
4977       /* Aggregates and long doubles are passed by reference.  */
4978       indirect_p = 1;
4979       reg = gpr;
4980       n_reg = 1;
4981       sav_ofs = 0;
4982       sav_scale = 4;
4983       size = UNITS_PER_WORD;
4984       rsize = 1;
4985     }
4986   else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
4987     {
4988       /* FP args go in FP registers, if present.  */
4989       indirect_p = 0;
4990       reg = fpr;
4991       n_reg = 1;
4992       sav_ofs = 8*4;
4993       sav_scale = 8;
4994     }
4995   else
4996     {
4997       /* Otherwise into GP registers.  */
4998       indirect_p = 0;
4999       reg = gpr;
5000       n_reg = rsize;
5001       sav_ofs = 0;
5002       sav_scale = 4;
5003     }
5004
5005   /* Pull the value out of the saved registers....  */
5006
5007   lab_false = gen_label_rtx ();
5008   lab_over = gen_label_rtx ();
5009   addr_rtx = gen_reg_rtx (Pmode);
5010
5011   /*  AltiVec vectors never go in registers.  */
5012   if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
5013     {
5014       TREE_THIS_VOLATILE (reg) = 1;
5015       emit_cmp_and_jump_insns
5016         (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
5017          GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
5018          lab_false);
5019
5020       /* Long long is aligned in the registers.  */
5021       if (n_reg > 1)
5022         {
5023           u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5024                      build_int_2 (n_reg - 1, 0));
5025           u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
5026           u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
5027           TREE_SIDE_EFFECTS (u) = 1;
5028           expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
5029         }
5030
5031       if (sav_ofs)
5032         t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
5033       else
5034         t = sav;
5035
5036       u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
5037                  build_int_2 (n_reg, 0));
5038       TREE_SIDE_EFFECTS (u) = 1;
5039
5040       u = build1 (CONVERT_EXPR, integer_type_node, u);
5041       TREE_SIDE_EFFECTS (u) = 1;
5042
5043       u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
5044       TREE_SIDE_EFFECTS (u) = 1;
5045
5046       t = build (PLUS_EXPR, ptr_type_node, t, u);
5047       TREE_SIDE_EFFECTS (t) = 1;
5048
5049       r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5050       if (r != addr_rtx)
5051         emit_move_insn (addr_rtx, r);
5052
5053       emit_jump_insn (gen_jump (lab_over));
5054       emit_barrier ();
5055     }
5056
5057   emit_label (lab_false);
5058
5059   /* ... otherwise out of the overflow area.  */
5060
5061   /* Make sure we don't find reg 7 for the next int arg.
5062
5063      All AltiVec vectors go in the overflow area.  So in the AltiVec
5064      case we need to get the vectors from the overflow area, but
5065      remember where the GPRs and FPRs are.  */
5066   if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
5067                     || !TARGET_ALTIVEC))
5068     {
5069       t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
5070       TREE_SIDE_EFFECTS (t) = 1;
5071       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5072     }
5073
5074   /* Care for on-stack alignment if needed.  */
5075   if (rsize <= 1)
5076     t = ovf;
5077   else
5078     {
5079       int align;
5080
5081       /* AltiVec vectors are 16 byte aligned.  */
5082       if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
5083         align = 15;
5084       else
5085         align = 7;
5086
5087       t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
5088       t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
5089     }
5090   t = save_expr (t);
5091
5092   r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
5093   if (r != addr_rtx)
5094     emit_move_insn (addr_rtx, r);
5095
5096   t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
5097   t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5098   TREE_SIDE_EFFECTS (t) = 1;
5099   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5100
5101   emit_label (lab_over);
5102
5103   if (indirect_p)
5104     {
5105       r = gen_rtx_MEM (Pmode, addr_rtx);
5106       set_mem_alias_set (r, get_varargs_alias_set ());
5107       emit_move_insn (addr_rtx, r);
5108     }
5109
5110   return addr_rtx;
5111 }
5112
5113 /* Builtins.  */
5114
5115 #define def_builtin(MASK, NAME, TYPE, CODE)                     \
5116 do {                                                            \
5117   if ((MASK) & target_flags)                                    \
5118     builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD,      \
5119                       NULL, NULL_TREE);                         \
5120 } while (0)
5121
5122 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc).  */
5123
5124 static const struct builtin_description bdesc_3arg[] =
5125 {
5126   { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5127   { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5128   { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5129   { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5130   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5131   { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5132   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5133   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5134   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5135   { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5136   { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5137   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5138   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5139   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5140   { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5141   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5142   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5143   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5144   { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5145   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5146   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5147   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5148   { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5149 };
5150
5151 /* DST operations: void foo (void *, const int, const char).  */
5152
5153 static const struct builtin_description bdesc_dst[] =
5154 {
5155   { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5156   { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5157   { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5158   { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5159 };
5160
5161 /* Simple binary operations: VECc = foo (VECa, VECb).  */
5162
5163 static struct builtin_description bdesc_2arg[] =
5164 {
5165   { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5166   { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5167   { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5168   { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5169   { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5170   { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5171   { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5172   { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5173   { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5174   { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5175   { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5176   { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5177   { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5178   { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5179   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5180   { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5181   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5182   { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5183   { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5184   { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5185   { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5186   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5187   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5188   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5189   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5190   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5191   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5192   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5193   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5194   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5195   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5196   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5197   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5198   { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5199   { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5200   { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5201   { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5202   { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5203   { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5204   { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5205   { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5206   { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5207   { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5208   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5209   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5210   { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5211   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5212   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5213   { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5214   { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5215   { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5216   { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5217   { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5218   { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5219   { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5220   { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5221   { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5222   { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5223   { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5224   { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5225   { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5226   { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5227   { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5228   { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5229   { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5230   { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5231   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5232   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5233   { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5234   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5235   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5236   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5237   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5238   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5239   { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5240   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5241   { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5242   { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5243   { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5244   { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5245   { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5246   { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5247   { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5248   { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5249   { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5250   { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5251   { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5252   { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5253   { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5254   { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5255   { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5256   { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5257   { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5258   { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5259   { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5260   { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5261   { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5262   { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5263   { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5264   { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5265   { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5266   { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5267   { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5268   { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5269   { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5270   { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5271   { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5272   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5273   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5274   { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5275   { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5276   { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5277   { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5278
5279   /* Place holder, leave as first spe builtin.  */
5280   { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5281   { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5282   { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5283   { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5284   { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5285   { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5286   { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5287   { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5288   { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5289   { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5290   { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5291   { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5292   { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5293   { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5294   { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5295   { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5296   { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5297   { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5298   { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5299   { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5300   { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5301   { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5302   { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5303   { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5304   { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5305   { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5306   { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5307   { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5308   { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5309   { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5310   { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5311   { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5312   { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5313   { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5314   { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5315   { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5316   { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5317   { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5318   { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5319   { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5320   { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5321   { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5322   { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5323   { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5324   { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5325   { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5326   { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5327   { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5328   { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5329   { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5330   { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5331   { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5332   { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5333   { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5334   { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5335   { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5336   { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5337   { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5338   { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5339   { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5340   { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5341   { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5342   { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5343   { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5344   { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5345   { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5346   { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5347   { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5348   { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5349   { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5350   { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5351   { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5352   { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5353   { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5354   { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5355   { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5356   { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5357   { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5358   { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5359   { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5360   { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5361   { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5362   { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5363   { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5364   { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5365   { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5366   { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5367   { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5368   { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5369   { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5370   { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5371   { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5372   { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5373   { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5374   { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5375   { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5376   { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5377   { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5378   { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5379   { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5380   { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5381   { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5382   { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5383   { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5384   { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5385   { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5386   { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5387   { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5388   { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5389
5390   /* SPE binary operations expecting a 5-bit unsigned literal.  */
5391   { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5392
5393   { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5394   { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5395   { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5396   { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5397   { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5398   { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5399   { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5400   { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5401   { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5402   { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5403   { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5404   { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5405   { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5406   { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5407   { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5408   { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5409   { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5410   { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5411   { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5412   { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5413   { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5414   { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5415   { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5416   { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5417   { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5418   { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5419
5420   /* Place-holder.  Leave as last binary SPE builtin.  */
5421   { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5422 };
5423
5424 /* AltiVec predicates.  */
5425
5426 struct builtin_description_predicates
5427 {
5428   const unsigned int mask;
5429   const enum insn_code icode;
5430   const char *opcode;
5431   const char *const name;
5432   const enum rs6000_builtins code;
5433 };
5434
5435 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5436 {
5437   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5438   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5439   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5440   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5441   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5442   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5443   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5444   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5445   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5446   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5447   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5448   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5449   { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5450 };
5451
5452 /* SPE predicates.  */
5453 static struct builtin_description bdesc_spe_predicates[] =
5454 {
5455   /* Place-holder.  Leave as first.  */
5456   { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5457   { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5458   { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5459   { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5460   { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5461   { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5462   { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5463   { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5464   { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5465   { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5466   /* Place-holder.  Leave as last.  */
5467   { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5468 };
5469
5470 /* SPE evsel predicates.  */
5471 static struct builtin_description bdesc_spe_evsel[] =
5472 {
5473   /* Place-holder.  Leave as first.  */
5474   { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5475   { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5476   { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5477   { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5478   { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5479   { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5480   { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5481   { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5482   { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5483   { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5484   /* Place-holder.  Leave as last.  */
5485   { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5486 };
5487
5488 /* ABS* operations.  */
5489
5490 static const struct builtin_description bdesc_abs[] =
5491 {
5492   { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5493   { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5494   { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5495   { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5496   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5497   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5498   { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5499 };
5500
5501 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5502    foo (VECa).  */
5503
5504 static struct builtin_description bdesc_1arg[] =
5505 {
5506   { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5507   { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5508   { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5509   { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5510   { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5511   { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5512   { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5513   { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5514   { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5515   { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5516   { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5517   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5518   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5519   { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5520   { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5521   { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5522   { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5523
5524   /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5525      end with SPE_BUILTIN_EVSUBFUSIAAW.  */
5526   { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5527   { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5528   { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5529   { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5530   { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5531   { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5532   { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5533   { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5534   { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5535   { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5536   { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5537   { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5538   { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5539   { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5540   { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5541   { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5542   { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5543   { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5544   { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5545   { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5546   { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5547   { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5548   { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5549   { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5550   { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5551   { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5552   { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5553   { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5554
5555   /* Place-holder.  Leave as last unary SPE builtin.  */
5556   { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5557 };
5558
5559 static rtx
5560 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5561 {
5562   rtx pat;
5563   tree arg0 = TREE_VALUE (arglist);
5564   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5565   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5566   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5567
5568   if (icode == CODE_FOR_nothing)
5569     /* Builtin not supported on this processor.  */
5570     return 0;
5571
5572   /* If we got invalid arguments bail out before generating bad rtl.  */
5573   if (arg0 == error_mark_node)
5574     return const0_rtx;
5575
5576   if (icode == CODE_FOR_altivec_vspltisb
5577       || icode == CODE_FOR_altivec_vspltish
5578       || icode == CODE_FOR_altivec_vspltisw
5579       || icode == CODE_FOR_spe_evsplatfi
5580       || icode == CODE_FOR_spe_evsplati)
5581     {
5582       /* Only allow 5-bit *signed* literals.  */
5583       if (GET_CODE (op0) != CONST_INT
5584           || INTVAL (op0) > 0x1f
5585           || INTVAL (op0) < -0x1f)
5586         {
5587           error ("argument 1 must be a 5-bit signed literal");
5588           return const0_rtx;
5589         }
5590     }
5591
5592   if (target == 0
5593       || GET_MODE (target) != tmode
5594       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5595     target = gen_reg_rtx (tmode);
5596
5597   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5598     op0 = copy_to_mode_reg (mode0, op0);
5599
5600   pat = GEN_FCN (icode) (target, op0);
5601   if (! pat)
5602     return 0;
5603   emit_insn (pat);
5604
5605   return target;
5606 }
5607
5608 static rtx
5609 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5610 {
5611   rtx pat, scratch1, scratch2;
5612   tree arg0 = TREE_VALUE (arglist);
5613   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5614   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5615   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5616
5617   /* If we have invalid arguments, bail out before generating bad rtl.  */
5618   if (arg0 == error_mark_node)
5619     return const0_rtx;
5620
5621   if (target == 0
5622       || GET_MODE (target) != tmode
5623       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5624     target = gen_reg_rtx (tmode);
5625
5626   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5627     op0 = copy_to_mode_reg (mode0, op0);
5628
5629   scratch1 = gen_reg_rtx (mode0);
5630   scratch2 = gen_reg_rtx (mode0);
5631
5632   pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5633   if (! pat)
5634     return 0;
5635   emit_insn (pat);
5636
5637   return target;
5638 }
5639
5640 static rtx
5641 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5642 {
5643   rtx pat;
5644   tree arg0 = TREE_VALUE (arglist);
5645   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5646   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5647   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5648   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5649   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5650   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5651
5652   if (icode == CODE_FOR_nothing)
5653     /* Builtin not supported on this processor.  */
5654     return 0;
5655
5656   /* If we got invalid arguments bail out before generating bad rtl.  */
5657   if (arg0 == error_mark_node || arg1 == error_mark_node)
5658     return const0_rtx;
5659
5660   if (icode == CODE_FOR_altivec_vcfux
5661       || icode == CODE_FOR_altivec_vcfsx
5662       || icode == CODE_FOR_altivec_vctsxs
5663       || icode == CODE_FOR_altivec_vctuxs
5664       || icode == CODE_FOR_altivec_vspltb
5665       || icode == CODE_FOR_altivec_vsplth
5666       || icode == CODE_FOR_altivec_vspltw
5667       || icode == CODE_FOR_spe_evaddiw
5668       || icode == CODE_FOR_spe_evldd
5669       || icode == CODE_FOR_spe_evldh
5670       || icode == CODE_FOR_spe_evldw
5671       || icode == CODE_FOR_spe_evlhhesplat
5672       || icode == CODE_FOR_spe_evlhhossplat
5673       || icode == CODE_FOR_spe_evlhhousplat
5674       || icode == CODE_FOR_spe_evlwhe
5675       || icode == CODE_FOR_spe_evlwhos
5676       || icode == CODE_FOR_spe_evlwhou
5677       || icode == CODE_FOR_spe_evlwhsplat
5678       || icode == CODE_FOR_spe_evlwwsplat
5679       || icode == CODE_FOR_spe_evrlwi
5680       || icode == CODE_FOR_spe_evslwi
5681       || icode == CODE_FOR_spe_evsrwis
5682       || icode == CODE_FOR_spe_evsubifw
5683       || icode == CODE_FOR_spe_evsrwiu)
5684     {
5685       /* Only allow 5-bit unsigned literals.  */
5686       STRIP_NOPS (arg1);
5687       if (TREE_CODE (arg1) != INTEGER_CST
5688           || TREE_INT_CST_LOW (arg1) & ~0x1f)
5689         {
5690           error ("argument 2 must be a 5-bit unsigned literal");
5691           return const0_rtx;
5692         }
5693     }
5694
5695   if (target == 0
5696       || GET_MODE (target) != tmode
5697       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5698     target = gen_reg_rtx (tmode);
5699
5700   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5701     op0 = copy_to_mode_reg (mode0, op0);
5702   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5703     op1 = copy_to_mode_reg (mode1, op1);
5704
5705   pat = GEN_FCN (icode) (target, op0, op1);
5706   if (! pat)
5707     return 0;
5708   emit_insn (pat);
5709
5710   return target;
5711 }
5712
5713 static rtx
5714 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5715                                   tree arglist, rtx target)
5716 {
5717   rtx pat, scratch;
5718   tree cr6_form = TREE_VALUE (arglist);
5719   tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5720   tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5721   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5722   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5723   enum machine_mode tmode = SImode;
5724   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5725   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5726   int cr6_form_int;
5727
5728   if (TREE_CODE (cr6_form) != INTEGER_CST)
5729     {
5730       error ("argument 1 of __builtin_altivec_predicate must be a constant");
5731       return const0_rtx;
5732     }
5733   else
5734     cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5735
5736   if (mode0 != mode1)
5737     abort ();
5738
5739   /* If we have invalid arguments, bail out before generating bad rtl.  */
5740   if (arg0 == error_mark_node || arg1 == error_mark_node)
5741     return const0_rtx;
5742
5743   if (target == 0
5744       || GET_MODE (target) != tmode
5745       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5746     target = gen_reg_rtx (tmode);
5747
5748   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5749     op0 = copy_to_mode_reg (mode0, op0);
5750   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5751     op1 = copy_to_mode_reg (mode1, op1);
5752
5753   scratch = gen_reg_rtx (mode0);
5754
5755   pat = GEN_FCN (icode) (scratch, op0, op1,
5756                          gen_rtx_SYMBOL_REF (Pmode, opcode));
5757   if (! pat)
5758     return 0;
5759   emit_insn (pat);
5760
5761   /* The vec_any* and vec_all* predicates use the same opcodes for two
5762      different operations, but the bits in CR6 will be different
5763      depending on what information we want.  So we have to play tricks
5764      with CR6 to get the right bits out.
5765
5766      If you think this is disgusting, look at the specs for the
5767      AltiVec predicates.  */
5768
5769      switch (cr6_form_int)
5770        {
5771        case 0:
5772          emit_insn (gen_cr6_test_for_zero (target));
5773          break;
5774        case 1:
5775          emit_insn (gen_cr6_test_for_zero_reverse (target));
5776          break;
5777        case 2:
5778          emit_insn (gen_cr6_test_for_lt (target));
5779          break;
5780        case 3:
5781          emit_insn (gen_cr6_test_for_lt_reverse (target));
5782          break;
5783        default:
5784          error ("argument 1 of __builtin_altivec_predicate is out of range");
5785          break;
5786        }
5787
5788   return target;
5789 }
5790
5791 static rtx
5792 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5793 {
5794   rtx pat, addr;
5795   tree arg0 = TREE_VALUE (arglist);
5796   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5797   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5798   enum machine_mode mode0 = Pmode;
5799   enum machine_mode mode1 = Pmode;
5800   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5801   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5802
5803   if (icode == CODE_FOR_nothing)
5804     /* Builtin not supported on this processor.  */
5805     return 0;
5806
5807   /* If we got invalid arguments bail out before generating bad rtl.  */
5808   if (arg0 == error_mark_node || arg1 == error_mark_node)
5809     return const0_rtx;
5810
5811   if (target == 0
5812       || GET_MODE (target) != tmode
5813       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5814     target = gen_reg_rtx (tmode);
5815
5816   op1 = copy_to_mode_reg (mode1, op1);
5817
5818   if (op0 == const0_rtx)
5819     {
5820       addr = gen_rtx_MEM (tmode, op1);
5821     }
5822   else
5823     {
5824       op0 = copy_to_mode_reg (mode0, op0);
5825       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5826     }
5827
5828   pat = GEN_FCN (icode) (target, addr);
5829
5830   if (! pat)
5831     return 0;
5832   emit_insn (pat);
5833
5834   return target;
5835 }
5836
5837 static rtx
5838 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5839 {
5840   tree arg0 = TREE_VALUE (arglist);
5841   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5842   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5843   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5844   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5845   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5846   rtx pat, addr;
5847   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5848   enum machine_mode mode1 = Pmode;
5849   enum machine_mode mode2 = Pmode;
5850
5851   /* Invalid arguments.  Bail before doing anything stoopid!  */
5852   if (arg0 == error_mark_node
5853       || arg1 == error_mark_node
5854       || arg2 == error_mark_node)
5855     return const0_rtx;
5856
5857   if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5858     op0 = copy_to_mode_reg (tmode, op0);
5859
5860   op2 = copy_to_mode_reg (mode2, op2);
5861
5862   if (op1 == const0_rtx)
5863     {
5864       addr = gen_rtx_MEM (tmode, op2);
5865     }
5866   else
5867     {
5868       op1 = copy_to_mode_reg (mode1, op1);
5869       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5870     }
5871
5872   pat = GEN_FCN (icode) (addr, op0);
5873   if (pat)
5874     emit_insn (pat);
5875   return NULL_RTX;
5876 }
5877
5878 static rtx
5879 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5880 {
5881   rtx pat;
5882   tree arg0 = TREE_VALUE (arglist);
5883   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5884   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5885   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5886   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5887   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5888   enum machine_mode tmode = insn_data[icode].operand[0].mode;
5889   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5890   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5891   enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5892
5893   if (icode == CODE_FOR_nothing)
5894     /* Builtin not supported on this processor.  */
5895     return 0;
5896
5897   /* If we got invalid arguments bail out before generating bad rtl.  */
5898   if (arg0 == error_mark_node
5899       || arg1 == error_mark_node
5900       || arg2 == error_mark_node)
5901     return const0_rtx;
5902
5903   if (icode == CODE_FOR_altivec_vsldoi_4sf
5904       || icode == CODE_FOR_altivec_vsldoi_4si
5905       || icode == CODE_FOR_altivec_vsldoi_8hi
5906       || icode == CODE_FOR_altivec_vsldoi_16qi)
5907     {
5908       /* Only allow 4-bit unsigned literals.  */
5909       STRIP_NOPS (arg2);
5910       if (TREE_CODE (arg2) != INTEGER_CST
5911           || TREE_INT_CST_LOW (arg2) & ~0xf)
5912         {
5913           error ("argument 3 must be a 4-bit unsigned literal");
5914           return const0_rtx;
5915         }
5916     }
5917
5918   if (target == 0
5919       || GET_MODE (target) != tmode
5920       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5921     target = gen_reg_rtx (tmode);
5922
5923   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5924     op0 = copy_to_mode_reg (mode0, op0);
5925   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5926     op1 = copy_to_mode_reg (mode1, op1);
5927   if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5928     op2 = copy_to_mode_reg (mode2, op2);
5929
5930   pat = GEN_FCN (icode) (target, op0, op1, op2);
5931   if (! pat)
5932     return 0;
5933   emit_insn (pat);
5934
5935   return target;
5936 }
5937
5938 /* Expand the lvx builtins.  */
5939 static rtx
5940 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5941 {
5942   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5943   tree arglist = TREE_OPERAND (exp, 1);
5944   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5945   tree arg0;
5946   enum machine_mode tmode, mode0;
5947   rtx pat, op0;
5948   enum insn_code icode;
5949
5950   switch (fcode)
5951     {
5952     case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5953       icode = CODE_FOR_altivec_lvx_16qi;
5954       break;
5955     case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5956       icode = CODE_FOR_altivec_lvx_8hi;
5957       break;
5958     case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5959       icode = CODE_FOR_altivec_lvx_4si;
5960       break;
5961     case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
5962       icode = CODE_FOR_altivec_lvx_4sf;
5963       break;
5964     default:
5965       *expandedp = false;
5966       return NULL_RTX;
5967     }
5968
5969   *expandedp = true;
5970
5971   arg0 = TREE_VALUE (arglist);
5972   op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5973   tmode = insn_data[icode].operand[0].mode;
5974   mode0 = insn_data[icode].operand[1].mode;
5975
5976   if (target == 0
5977       || GET_MODE (target) != tmode
5978       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5979     target = gen_reg_rtx (tmode);
5980
5981   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5982     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5983
5984   pat = GEN_FCN (icode) (target, op0);
5985   if (! pat)
5986     return 0;
5987   emit_insn (pat);
5988   return target;
5989 }
5990
5991 /* Expand the stvx builtins.  */
5992 static rtx
5993 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5994                            bool *expandedp)
5995 {
5996   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5997   tree arglist = TREE_OPERAND (exp, 1);
5998   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5999   tree arg0, arg1;
6000   enum machine_mode mode0, mode1;
6001   rtx pat, op0, op1;
6002   enum insn_code icode;
6003
6004   switch (fcode)
6005     {
6006     case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6007       icode = CODE_FOR_altivec_stvx_16qi;
6008       break;
6009     case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6010       icode = CODE_FOR_altivec_stvx_8hi;
6011       break;
6012     case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6013       icode = CODE_FOR_altivec_stvx_4si;
6014       break;
6015     case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6016       icode = CODE_FOR_altivec_stvx_4sf;
6017       break;
6018     default:
6019       *expandedp = false;
6020       return NULL_RTX;
6021     }
6022
6023   arg0 = TREE_VALUE (arglist);
6024   arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6025   op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6026   op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6027   mode0 = insn_data[icode].operand[0].mode;
6028   mode1 = insn_data[icode].operand[1].mode;
6029
6030   if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6031     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6032   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6033     op1 = copy_to_mode_reg (mode1, op1);
6034
6035   pat = GEN_FCN (icode) (op0, op1);
6036   if (pat)
6037     emit_insn (pat);
6038
6039   *expandedp = true;
6040   return NULL_RTX;
6041 }
6042
6043 /* Expand the dst builtins.  */
6044 static rtx
6045 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6046                             bool *expandedp)
6047 {
6048   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6049   tree arglist = TREE_OPERAND (exp, 1);
6050   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6051   tree arg0, arg1, arg2;
6052   enum machine_mode mode0, mode1, mode2;
6053   rtx pat, op0, op1, op2;
6054   struct builtin_description *d;
6055   size_t i;
6056
6057   *expandedp = false;
6058
6059   /* Handle DST variants.  */
6060   d = (struct builtin_description *) bdesc_dst;
6061   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6062     if (d->code == fcode)
6063       {
6064         arg0 = TREE_VALUE (arglist);
6065         arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6066         arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6067         op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6068         op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6069         op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6070         mode0 = insn_data[d->icode].operand[0].mode;
6071         mode1 = insn_data[d->icode].operand[1].mode;
6072         mode2 = insn_data[d->icode].operand[2].mode;
6073
6074         /* Invalid arguments, bail out before generating bad rtl.  */
6075         if (arg0 == error_mark_node
6076             || arg1 == error_mark_node
6077             || arg2 == error_mark_node)
6078           return const0_rtx;
6079
6080         *expandedp = true;
6081         STRIP_NOPS (arg2);
6082         if (TREE_CODE (arg2) != INTEGER_CST
6083             || TREE_INT_CST_LOW (arg2) & ~0x3)
6084           {
6085             error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
6086             return const0_rtx;
6087           }
6088
6089         if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6090           op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6091         if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6092           op1 = copy_to_mode_reg (mode1, op1);
6093
6094         pat = GEN_FCN (d->icode) (op0, op1, op2);
6095         if (pat != 0)
6096           emit_insn (pat);
6097
6098         return NULL_RTX;
6099       }
6100
6101   return NULL_RTX;
6102 }
6103
6104 /* Expand the builtin in EXP and store the result in TARGET.  Store
6105    true in *EXPANDEDP if we found a builtin to expand.  */
6106 static rtx
6107 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6108 {
6109   struct builtin_description *d;
6110   struct builtin_description_predicates *dp;
6111   size_t i;
6112   enum insn_code icode;
6113   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6114   tree arglist = TREE_OPERAND (exp, 1);
6115   tree arg0;
6116   rtx op0, pat;
6117   enum machine_mode tmode, mode0;
6118   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6119
6120   target = altivec_expand_ld_builtin (exp, target, expandedp);
6121   if (*expandedp)
6122     return target;
6123
6124   target = altivec_expand_st_builtin (exp, target, expandedp);
6125   if (*expandedp)
6126     return target;
6127
6128   target = altivec_expand_dst_builtin (exp, target, expandedp);
6129   if (*expandedp)
6130     return target;
6131
6132   *expandedp = true;
6133
6134   switch (fcode)
6135     {
6136     case ALTIVEC_BUILTIN_STVX:
6137       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6138     case ALTIVEC_BUILTIN_STVEBX:
6139       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6140     case ALTIVEC_BUILTIN_STVEHX:
6141       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6142     case ALTIVEC_BUILTIN_STVEWX:
6143       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6144     case ALTIVEC_BUILTIN_STVXL:
6145       return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6146
6147     case ALTIVEC_BUILTIN_MFVSCR:
6148       icode = CODE_FOR_altivec_mfvscr;
6149       tmode = insn_data[icode].operand[0].mode;
6150
6151       if (target == 0
6152           || GET_MODE (target) != tmode
6153           || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6154         target = gen_reg_rtx (tmode);
6155
6156       pat = GEN_FCN (icode) (target);
6157       if (! pat)
6158         return 0;
6159       emit_insn (pat);
6160       return target;
6161
6162     case ALTIVEC_BUILTIN_MTVSCR:
6163       icode = CODE_FOR_altivec_mtvscr;
6164       arg0 = TREE_VALUE (arglist);
6165       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6166       mode0 = insn_data[icode].operand[0].mode;
6167
6168       /* If we got invalid arguments bail out before generating bad rtl.  */
6169       if (arg0 == error_mark_node)
6170         return const0_rtx;
6171
6172       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6173         op0 = copy_to_mode_reg (mode0, op0);
6174
6175       pat = GEN_FCN (icode) (op0);
6176       if (pat)
6177         emit_insn (pat);
6178       return NULL_RTX;
6179
6180     case ALTIVEC_BUILTIN_DSSALL:
6181       emit_insn (gen_altivec_dssall ());
6182       return NULL_RTX;
6183
6184     case ALTIVEC_BUILTIN_DSS:
6185       icode = CODE_FOR_altivec_dss;
6186       arg0 = TREE_VALUE (arglist);
6187       STRIP_NOPS (arg0);
6188       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6189       mode0 = insn_data[icode].operand[0].mode;
6190
6191       /* If we got invalid arguments bail out before generating bad rtl.  */
6192       if (arg0 == error_mark_node)
6193         return const0_rtx;
6194
6195       if (TREE_CODE (arg0) != INTEGER_CST
6196           || TREE_INT_CST_LOW (arg0) & ~0x3)
6197         {
6198           error ("argument to dss must be a 2-bit unsigned literal");
6199           return const0_rtx;
6200         }
6201
6202       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6203         op0 = copy_to_mode_reg (mode0, op0);
6204
6205       emit_insn (gen_altivec_dss (op0));
6206       return NULL_RTX;
6207
6208     case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6209       arg0 = TREE_VALUE (arglist);
6210       while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR)
6211         arg0 = TREE_OPERAND (arg0, 0);
6212       error ("invalid parameter combination for `%s' AltiVec intrinsic",
6213              TREE_STRING_POINTER (arg0));
6214
6215       return const0_rtx;
6216     }
6217
6218   /* Expand abs* operations.  */
6219   d = (struct builtin_description *) bdesc_abs;
6220   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6221     if (d->code == fcode)
6222       return altivec_expand_abs_builtin (d->icode, arglist, target);
6223
6224   /* Expand the AltiVec predicates.  */
6225   dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6226   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6227     if (dp->code == fcode)
6228       return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
6229
6230   /* LV* are funky.  We initialized them differently.  */
6231   switch (fcode)
6232     {
6233     case ALTIVEC_BUILTIN_LVSL:
6234       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6235                                            arglist, target);
6236     case ALTIVEC_BUILTIN_LVSR:
6237       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6238                                           arglist, target);
6239     case ALTIVEC_BUILTIN_LVEBX:
6240       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6241                                           arglist, target);
6242     case ALTIVEC_BUILTIN_LVEHX:
6243       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6244                                           arglist, target);
6245     case ALTIVEC_BUILTIN_LVEWX:
6246       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6247                                           arglist, target);
6248     case ALTIVEC_BUILTIN_LVXL:
6249       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6250                                           arglist, target);
6251     case ALTIVEC_BUILTIN_LVX:
6252       return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6253                                           arglist, target);
6254     default:
6255       break;
6256       /* Fall through.  */
6257     }
6258
6259   *expandedp = false;
6260   return NULL_RTX;
6261 }
6262
6263 /* Binops that need to be initialized manually, but can be expanded
6264    automagically by rs6000_expand_binop_builtin.  */
6265 static struct builtin_description bdesc_2arg_spe[] =
6266 {
6267   { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6268   { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6269   { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6270   { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6271   { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6272   { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6273   { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6274   { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6275   { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6276   { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6277   { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6278   { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6279   { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6280   { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6281   { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6282   { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6283   { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6284   { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6285   { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6286   { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6287   { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6288   { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6289 };
6290
6291 /* Expand the builtin in EXP and store the result in TARGET.  Store
6292    true in *EXPANDEDP if we found a builtin to expand.
6293
6294    This expands the SPE builtins that are not simple unary and binary
6295    operations.  */
6296 static rtx
6297 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6298 {
6299   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6300   tree arglist = TREE_OPERAND (exp, 1);
6301   tree arg1, arg0;
6302   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6303   enum insn_code icode;
6304   enum machine_mode tmode, mode0;
6305   rtx pat, op0;
6306   struct builtin_description *d;
6307   size_t i;
6308
6309   *expandedp = true;
6310
6311   /* Syntax check for a 5-bit unsigned immediate.  */
6312   switch (fcode)
6313     {
6314     case SPE_BUILTIN_EVSTDD:
6315     case SPE_BUILTIN_EVSTDH:
6316     case SPE_BUILTIN_EVSTDW:
6317     case SPE_BUILTIN_EVSTWHE:
6318     case SPE_BUILTIN_EVSTWHO:
6319     case SPE_BUILTIN_EVSTWWE:
6320     case SPE_BUILTIN_EVSTWWO:
6321       arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6322       if (TREE_CODE (arg1) != INTEGER_CST
6323           || TREE_INT_CST_LOW (arg1) & ~0x1f)
6324         {
6325           error ("argument 2 must be a 5-bit unsigned literal");
6326           return const0_rtx;
6327         }
6328       break;
6329     default:
6330       break;
6331     }
6332
6333   /* The evsplat*i instructions are not quite generic.  */
6334   switch (fcode)
6335     {
6336     case SPE_BUILTIN_EVSPLATFI:
6337       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6338                                          arglist, target);
6339     case SPE_BUILTIN_EVSPLATI:
6340       return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6341                                          arglist, target);
6342     default:
6343       break;
6344     }
6345
6346   d = (struct builtin_description *) bdesc_2arg_spe;
6347   for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6348     if (d->code == fcode)
6349       return rs6000_expand_binop_builtin (d->icode, arglist, target);
6350
6351   d = (struct builtin_description *) bdesc_spe_predicates;
6352   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6353     if (d->code == fcode)
6354       return spe_expand_predicate_builtin (d->icode, arglist, target);
6355
6356   d = (struct builtin_description *) bdesc_spe_evsel;
6357   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6358     if (d->code == fcode)
6359       return spe_expand_evsel_builtin (d->icode, arglist, target);
6360
6361   switch (fcode)
6362     {
6363     case SPE_BUILTIN_EVSTDDX:
6364       return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6365     case SPE_BUILTIN_EVSTDHX:
6366       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6367     case SPE_BUILTIN_EVSTDWX:
6368       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6369     case SPE_BUILTIN_EVSTWHEX:
6370       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6371     case SPE_BUILTIN_EVSTWHOX:
6372       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6373     case SPE_BUILTIN_EVSTWWEX:
6374       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6375     case SPE_BUILTIN_EVSTWWOX:
6376       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6377     case SPE_BUILTIN_EVSTDD:
6378       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6379     case SPE_BUILTIN_EVSTDH:
6380       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6381     case SPE_BUILTIN_EVSTDW:
6382       return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6383     case SPE_BUILTIN_EVSTWHE:
6384       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6385     case SPE_BUILTIN_EVSTWHO:
6386       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6387     case SPE_BUILTIN_EVSTWWE:
6388       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6389     case SPE_BUILTIN_EVSTWWO:
6390       return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6391     case SPE_BUILTIN_MFSPEFSCR:
6392       icode = CODE_FOR_spe_mfspefscr;
6393       tmode = insn_data[icode].operand[0].mode;
6394
6395       if (target == 0
6396           || GET_MODE (target) != tmode
6397           || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6398         target = gen_reg_rtx (tmode);
6399
6400       pat = GEN_FCN (icode) (target);
6401       if (! pat)
6402         return 0;
6403       emit_insn (pat);
6404       return target;
6405     case SPE_BUILTIN_MTSPEFSCR:
6406       icode = CODE_FOR_spe_mtspefscr;
6407       arg0 = TREE_VALUE (arglist);
6408       op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6409       mode0 = insn_data[icode].operand[0].mode;
6410
6411       if (arg0 == error_mark_node)
6412         return const0_rtx;
6413
6414       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6415         op0 = copy_to_mode_reg (mode0, op0);
6416
6417       pat = GEN_FCN (icode) (op0);
6418       if (pat)
6419         emit_insn (pat);
6420       return NULL_RTX;
6421     default:
6422       break;
6423     }
6424
6425   *expandedp = false;
6426   return NULL_RTX;
6427 }
6428
6429 static rtx
6430 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6431 {
6432   rtx pat, scratch, tmp;
6433   tree form = TREE_VALUE (arglist);
6434   tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6435   tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6436   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6437   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6438   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6439   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6440   int form_int;
6441   enum rtx_code code;
6442
6443   if (TREE_CODE (form) != INTEGER_CST)
6444     {
6445       error ("argument 1 of __builtin_spe_predicate must be a constant");
6446       return const0_rtx;
6447     }
6448   else
6449     form_int = TREE_INT_CST_LOW (form);
6450
6451   if (mode0 != mode1)
6452     abort ();
6453
6454   if (arg0 == error_mark_node || arg1 == error_mark_node)
6455     return const0_rtx;
6456
6457   if (target == 0
6458       || GET_MODE (target) != SImode
6459       || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6460     target = gen_reg_rtx (SImode);
6461
6462   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6463     op0 = copy_to_mode_reg (mode0, op0);
6464   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6465     op1 = copy_to_mode_reg (mode1, op1);
6466
6467   scratch = gen_reg_rtx (CCmode);
6468
6469   pat = GEN_FCN (icode) (scratch, op0, op1);
6470   if (! pat)
6471     return const0_rtx;
6472   emit_insn (pat);
6473
6474   /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6475      _lower_.  We use one compare, but look in different bits of the
6476      CR for each variant.
6477
6478      There are 2 elements in each SPE simd type (upper/lower).  The CR
6479      bits are set as follows:
6480
6481      BIT0  | BIT 1  | BIT 2   | BIT 3
6482      U     |   L    | (U | L) | (U & L)
6483
6484      So, for an "all" relationship, BIT 3 would be set.
6485      For an "any" relationship, BIT 2 would be set.  Etc.
6486
6487      Following traditional nomenclature, these bits map to:
6488
6489      BIT0  | BIT 1  | BIT 2   | BIT 3
6490      LT    | GT     | EQ      | OV
6491
6492      Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6493   */
6494
6495   switch (form_int)
6496     {
6497       /* All variant.  OV bit.  */
6498     case 0:
6499       /* We need to get to the OV bit, which is the ORDERED bit.  We
6500          could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6501          that's ugly and will trigger a validate_condition_mode abort.
6502          So let's just use another pattern.  */
6503       emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6504       return target;
6505       /* Any variant.  EQ bit.  */
6506     case 1:
6507       code = EQ;
6508       break;
6509       /* Upper variant.  LT bit.  */
6510     case 2:
6511       code = LT;
6512       break;
6513       /* Lower variant.  GT bit.  */
6514     case 3:
6515       code = GT;
6516       break;
6517     default:
6518       error ("argument 1 of __builtin_spe_predicate is out of range");
6519       return const0_rtx;
6520     }
6521
6522   tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6523   emit_move_insn (target, tmp);
6524
6525   return target;
6526 }
6527
6528 /* The evsel builtins look like this:
6529
6530      e = __builtin_spe_evsel_OP (a, b, c, d);
6531
6532    and work like this:
6533
6534      e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6535      e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6536 */
6537
6538 static rtx
6539 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6540 {
6541   rtx pat, scratch;
6542   tree arg0 = TREE_VALUE (arglist);
6543   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6544   tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6545   tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6546   rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6547   rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6548   rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6549   rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6550   enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6551   enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6552
6553   if (mode0 != mode1)
6554     abort ();
6555
6556   if (arg0 == error_mark_node || arg1 == error_mark_node
6557       || arg2 == error_mark_node || arg3 == error_mark_node)
6558     return const0_rtx;
6559
6560   if (target == 0
6561       || GET_MODE (target) != mode0
6562       || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6563     target = gen_reg_rtx (mode0);
6564
6565   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6566     op0 = copy_to_mode_reg (mode0, op0);
6567   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6568     op1 = copy_to_mode_reg (mode0, op1);
6569   if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6570     op2 = copy_to_mode_reg (mode0, op2);
6571   if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6572     op3 = copy_to_mode_reg (mode0, op3);
6573
6574   /* Generate the compare.  */
6575   scratch = gen_reg_rtx (CCmode);
6576   pat = GEN_FCN (icode) (scratch, op0, op1);
6577   if (! pat)
6578     return const0_rtx;
6579   emit_insn (pat);
6580
6581   if (mode0 == V2SImode)
6582     emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6583   else
6584     emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6585
6586   return target;
6587 }
6588
6589 /* Expand an expression EXP that calls a built-in function,
6590    with result going to TARGET if that's convenient
6591    (and in mode MODE if that's convenient).
6592    SUBTARGET may be used as the target for computing one of EXP's operands.
6593    IGNORE is nonzero if the value is to be ignored.  */
6594
6595 static rtx
6596 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6597                       enum machine_mode mode ATTRIBUTE_UNUSED,
6598                       int ignore ATTRIBUTE_UNUSED)
6599 {
6600   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6601   tree arglist = TREE_OPERAND (exp, 1);
6602   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6603   struct builtin_description *d;
6604   size_t i;
6605   rtx ret;
6606   bool success;
6607
6608   if (TARGET_ALTIVEC)
6609     {
6610       ret = altivec_expand_builtin (exp, target, &success);
6611
6612       if (success)
6613         return ret;
6614     }
6615   if (TARGET_SPE)
6616     {
6617       ret = spe_expand_builtin (exp, target, &success);
6618
6619       if (success)
6620         return ret;
6621     }
6622
6623   if (TARGET_ALTIVEC || TARGET_SPE)
6624     {
6625       /* Handle simple unary operations.  */
6626       d = (struct builtin_description *) bdesc_1arg;
6627       for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6628         if (d->code == fcode)
6629           return rs6000_expand_unop_builtin (d->icode, arglist, target);
6630
6631       /* Handle simple binary operations.  */
6632       d = (struct builtin_description *) bdesc_2arg;
6633       for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6634         if (d->code == fcode)
6635           return rs6000_expand_binop_builtin (d->icode, arglist, target);
6636
6637       /* Handle simple ternary operations.  */
6638       d = (struct builtin_description *) bdesc_3arg;
6639       for (i = 0; i < ARRAY_SIZE  (bdesc_3arg); i++, d++)
6640         if (d->code == fcode)
6641           return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6642     }
6643
6644   abort ();
6645   return NULL_RTX;
6646 }
6647
6648 static void
6649 rs6000_init_builtins (void)
6650 {
6651   V2SI_type_node = build_vector_type (intSI_type_node, 2);
6652   V2SF_type_node = build_vector_type (float_type_node, 2);
6653   V4HI_type_node = build_vector_type (intHI_type_node, 4);
6654   V4SI_type_node = build_vector_type (intSI_type_node, 4);
6655   V4SF_type_node = build_vector_type (float_type_node, 4);
6656   V8HI_type_node = build_vector_type (intHI_type_node, 8);
6657   V16QI_type_node = build_vector_type (intQI_type_node, 16);
6658
6659   unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
6660   unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
6661   unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
6662
6663   opaque_V2SI_type_node = copy_node (V2SI_type_node);
6664   opaque_V2SF_type_node = copy_node (V2SF_type_node);
6665   opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6666
6667   /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
6668      types, especially in C++ land.  Similarly, 'vector pixel' is distinct from
6669      'vector unsigned short'.  */
6670
6671   bool_char_type_node = copy_node (unsigned_intQI_type_node);
6672   TYPE_MAIN_VARIANT (bool_char_type_node) = bool_char_type_node;
6673   bool_short_type_node = copy_node (unsigned_intHI_type_node);
6674   TYPE_MAIN_VARIANT (bool_short_type_node) = bool_short_type_node;
6675   bool_int_type_node = copy_node (unsigned_intSI_type_node);
6676   TYPE_MAIN_VARIANT (bool_int_type_node) = bool_int_type_node;
6677   pixel_type_node = copy_node (unsigned_intHI_type_node);
6678   TYPE_MAIN_VARIANT (pixel_type_node) = pixel_type_node;
6679
6680   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6681                                             get_identifier ("__bool char"),
6682                                             bool_char_type_node));
6683   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6684                                             get_identifier ("__bool short"),
6685                                             bool_short_type_node));
6686   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6687                                             get_identifier ("__bool int"),
6688                                             bool_int_type_node));
6689   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6690                                             get_identifier ("__pixel"),
6691                                             pixel_type_node));
6692
6693   bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
6694   bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
6695   bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
6696   pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
6697
6698   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6699                                             get_identifier ("__vector unsigned char"),
6700                                             unsigned_V16QI_type_node));
6701   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6702                                             get_identifier ("__vector signed char"),
6703                                             V16QI_type_node));
6704   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6705                                             get_identifier ("__vector __bool char"),
6706                                             bool_V16QI_type_node));
6707
6708   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6709                                             get_identifier ("__vector unsigned short"),
6710                                             unsigned_V8HI_type_node));
6711   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6712                                             get_identifier ("__vector signed short"),
6713                                             V8HI_type_node));
6714   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6715                                             get_identifier ("__vector __bool short"),
6716                                             bool_V8HI_type_node));
6717
6718   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6719                                             get_identifier ("__vector unsigned int"),
6720                                             unsigned_V4SI_type_node));
6721   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6722                                             get_identifier ("__vector signed int"),
6723                                             V4SI_type_node));
6724   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6725                                             get_identifier ("__vector __bool int"),
6726                                             bool_V4SI_type_node));
6727
6728   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6729                                             get_identifier ("__vector float"),
6730                                             V4SF_type_node));
6731   (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
6732                                             get_identifier ("__vector __pixel"),
6733                                             pixel_V8HI_type_node));
6734
6735   if (TARGET_SPE)
6736     spe_init_builtins ();
6737   if (TARGET_ALTIVEC)
6738     altivec_init_builtins ();
6739   if (TARGET_ALTIVEC || TARGET_SPE)
6740     rs6000_common_init_builtins ();
6741 }
6742
6743 /* Search through a set of builtins and enable the mask bits.
6744    DESC is an array of builtins.
6745    SIZE is the total number of builtins.
6746    START is the builtin enum at which to start.
6747    END is the builtin enum at which to end.  */
6748 static void
6749 enable_mask_for_builtins (struct builtin_description *desc, int size,
6750                           enum rs6000_builtins start,
6751                           enum rs6000_builtins end)
6752 {
6753   int i;
6754
6755   for (i = 0; i < size; ++i)
6756     if (desc[i].code == start)
6757       break;
6758
6759   if (i == size)
6760     return;
6761
6762   for (; i < size; ++i)
6763     {
6764       /* Flip all the bits on.  */
6765       desc[i].mask = target_flags;
6766       if (desc[i].code == end)
6767         break;
6768     }
6769 }
6770
6771 static void
6772 spe_init_builtins (void)
6773 {
6774   tree endlink = void_list_node;
6775   tree puint_type_node = build_pointer_type (unsigned_type_node);
6776   tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6777   struct builtin_description *d;
6778   size_t i;
6779
6780   tree v2si_ftype_4_v2si
6781     = build_function_type
6782     (opaque_V2SI_type_node,
6783      tree_cons (NULL_TREE, opaque_V2SI_type_node,
6784                 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6785                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6786                                       tree_cons (NULL_TREE, opaque_V2SI_type_node,
6787                                                  endlink)))));
6788
6789   tree v2sf_ftype_4_v2sf
6790     = build_function_type
6791     (opaque_V2SF_type_node,
6792      tree_cons (NULL_TREE, opaque_V2SF_type_node,
6793                 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6794                            tree_cons (NULL_TREE, opaque_V2SF_type_node,
6795                                       tree_cons (NULL_TREE, opaque_V2SF_type_node,
6796                                                  endlink)))));
6797
6798   tree int_ftype_int_v2si_v2si
6799     = build_function_type
6800     (integer_type_node,
6801      tree_cons (NULL_TREE, integer_type_node,
6802                 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6803                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6804                                       endlink))));
6805
6806   tree int_ftype_int_v2sf_v2sf
6807     = build_function_type
6808     (integer_type_node,
6809      tree_cons (NULL_TREE, integer_type_node,
6810                 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6811                            tree_cons (NULL_TREE, opaque_V2SF_type_node,
6812                                       endlink))));
6813
6814   tree void_ftype_v2si_puint_int
6815     = build_function_type (void_type_node,
6816                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6817                                       tree_cons (NULL_TREE, puint_type_node,
6818                                                  tree_cons (NULL_TREE,
6819                                                             integer_type_node,
6820                                                             endlink))));
6821
6822   tree void_ftype_v2si_puint_char
6823     = build_function_type (void_type_node,
6824                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6825                                       tree_cons (NULL_TREE, puint_type_node,
6826                                                  tree_cons (NULL_TREE,
6827                                                             char_type_node,
6828                                                             endlink))));
6829
6830   tree void_ftype_v2si_pv2si_int
6831     = build_function_type (void_type_node,
6832                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6833                                       tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6834                                                  tree_cons (NULL_TREE,
6835                                                             integer_type_node,
6836                                                             endlink))));
6837
6838   tree void_ftype_v2si_pv2si_char
6839     = build_function_type (void_type_node,
6840                            tree_cons (NULL_TREE, opaque_V2SI_type_node,
6841                                       tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6842                                                  tree_cons (NULL_TREE,
6843                                                             char_type_node,
6844                                                             endlink))));
6845
6846   tree void_ftype_int
6847     = build_function_type (void_type_node,
6848                            tree_cons (NULL_TREE, integer_type_node, endlink));
6849
6850   tree int_ftype_void
6851     = build_function_type (integer_type_node, endlink);
6852
6853   tree v2si_ftype_pv2si_int
6854     = build_function_type (opaque_V2SI_type_node,
6855                            tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6856                                       tree_cons (NULL_TREE, integer_type_node,
6857                                                  endlink)));
6858
6859   tree v2si_ftype_puint_int
6860     = build_function_type (opaque_V2SI_type_node,
6861                            tree_cons (NULL_TREE, puint_type_node,
6862                                       tree_cons (NULL_TREE, integer_type_node,
6863                                                  endlink)));
6864
6865   tree v2si_ftype_pushort_int
6866     = build_function_type (opaque_V2SI_type_node,
6867                            tree_cons (NULL_TREE, pushort_type_node,
6868                                       tree_cons (NULL_TREE, integer_type_node,
6869                                                  endlink)));
6870
6871   tree v2si_ftype_signed_char
6872     = build_function_type (opaque_V2SI_type_node,
6873                            tree_cons (NULL_TREE, signed_char_type_node,
6874                                       endlink));
6875
6876   /* The initialization of the simple binary and unary builtins is
6877      done in rs6000_common_init_builtins, but we have to enable the
6878      mask bits here manually because we have run out of `target_flags'
6879      bits.  We really need to redesign this mask business.  */
6880
6881   enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6882                             ARRAY_SIZE (bdesc_2arg),
6883                             SPE_BUILTIN_EVADDW,
6884                             SPE_BUILTIN_EVXOR);
6885   enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6886                             ARRAY_SIZE (bdesc_1arg),
6887                             SPE_BUILTIN_EVABS,
6888                             SPE_BUILTIN_EVSUBFUSIAAW);
6889   enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6890                             ARRAY_SIZE (bdesc_spe_predicates),
6891                             SPE_BUILTIN_EVCMPEQ,
6892                             SPE_BUILTIN_EVFSTSTLT);
6893   enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6894                             ARRAY_SIZE (bdesc_spe_evsel),
6895                             SPE_BUILTIN_EVSEL_CMPGTS,
6896                             SPE_BUILTIN_EVSEL_FSTSTEQ);
6897
6898   (*lang_hooks.decls.pushdecl)
6899     (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6900                  opaque_V2SI_type_node));
6901
6902   /* Initialize irregular SPE builtins.  */
6903
6904   def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6905   def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6906   def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6907   def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6908   def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6909   def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6910   def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6911   def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6912   def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6913   def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6914   def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6915   def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6916   def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6917   def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6918   def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6919   def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6920   def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6921   def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6922
6923   /* Loads.  */
6924   def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6925   def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6926   def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6927   def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6928   def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6929   def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6930   def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6931   def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6932   def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6933   def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6934   def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6935   def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6936   def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6937   def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6938   def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6939   def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6940   def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6941   def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6942   def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6943   def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6944   def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6945   def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6946
6947   /* Predicates.  */
6948   d = (struct builtin_description *) bdesc_spe_predicates;
6949   for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6950     {
6951       tree type;
6952
6953       switch (insn_data[d->icode].operand[1].mode)
6954         {
6955         case V2SImode:
6956           type = int_ftype_int_v2si_v2si;
6957           break;
6958         case V2SFmode:
6959           type = int_ftype_int_v2sf_v2sf;
6960           break;
6961         default:
6962           abort ();
6963         }
6964
6965       def_builtin (d->mask, d->name, type, d->code);
6966     }
6967
6968   /* Evsel predicates.  */
6969   d = (struct builtin_description *) bdesc_spe_evsel;
6970   for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
6971     {
6972       tree type;
6973
6974       switch (insn_data[d->icode].operand[1].mode)
6975         {
6976         case V2SImode:
6977           type = v2si_ftype_4_v2si;
6978           break;
6979         case V2SFmode:
6980           type = v2sf_ftype_4_v2sf;
6981           break;
6982         default:
6983           abort ();
6984         }
6985
6986       def_builtin (d->mask, d->name, type, d->code);
6987     }
6988 }
6989
6990 static void
6991 altivec_init_builtins (void)
6992 {
6993   struct builtin_description *d;
6994   struct builtin_description_predicates *dp;
6995   size_t i;
6996   tree pfloat_type_node = build_pointer_type (float_type_node);
6997   tree pint_type_node = build_pointer_type (integer_type_node);
6998   tree pshort_type_node = build_pointer_type (short_integer_type_node);
6999   tree pchar_type_node = build_pointer_type (char_type_node);
7000
7001   tree pvoid_type_node = build_pointer_type (void_type_node);
7002
7003   tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7004   tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7005   tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7006   tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7007
7008   tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7009
7010   tree int_ftype_int_v4si_v4si
7011     = build_function_type_list (integer_type_node,
7012                                 integer_type_node, V4SI_type_node,
7013                                 V4SI_type_node, NULL_TREE);
7014   tree v4sf_ftype_pcfloat
7015     = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7016   tree void_ftype_pfloat_v4sf
7017     = build_function_type_list (void_type_node,
7018                                 pfloat_type_node, V4SF_type_node, NULL_TREE);
7019   tree v4si_ftype_pcint
7020     = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7021   tree void_ftype_pint_v4si
7022     = build_function_type_list (void_type_node,
7023                                 pint_type_node, V4SI_type_node, NULL_TREE);
7024   tree v8hi_ftype_pcshort
7025     = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7026   tree void_ftype_pshort_v8hi
7027     = build_function_type_list (void_type_node,
7028                                 pshort_type_node, V8HI_type_node, NULL_TREE);
7029   tree v16qi_ftype_pcchar
7030     = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7031   tree void_ftype_pchar_v16qi
7032     = build_function_type_list (void_type_node,
7033                                 pchar_type_node, V16QI_type_node, NULL_TREE);
7034   tree void_ftype_v4si
7035     = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7036   tree v8hi_ftype_void
7037     = build_function_type (V8HI_type_node, void_list_node);
7038   tree void_ftype_void
7039     = build_function_type (void_type_node, void_list_node);
7040   tree void_ftype_qi
7041     = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
7042
7043   tree v16qi_ftype_long_pcvoid
7044     = build_function_type_list (V16QI_type_node,
7045                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7046   tree v8hi_ftype_long_pcvoid
7047     = build_function_type_list (V8HI_type_node,
7048                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7049   tree v4si_ftype_long_pcvoid
7050     = build_function_type_list (V4SI_type_node,
7051                                 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7052
7053   tree void_ftype_v4si_long_pvoid
7054     = build_function_type_list (void_type_node,
7055                                 V4SI_type_node, long_integer_type_node,
7056                                 pvoid_type_node, NULL_TREE);
7057   tree void_ftype_v16qi_long_pvoid
7058     = build_function_type_list (void_type_node,
7059                                 V16QI_type_node, long_integer_type_node,
7060                                 pvoid_type_node, NULL_TREE);
7061   tree void_ftype_v8hi_long_pvoid
7062     = build_function_type_list (void_type_node,
7063                                 V8HI_type_node, long_integer_type_node,
7064                                 pvoid_type_node, NULL_TREE);
7065   tree int_ftype_int_v8hi_v8hi
7066     = build_function_type_list (integer_type_node,
7067                                 integer_type_node, V8HI_type_node,
7068                                 V8HI_type_node, NULL_TREE);
7069   tree int_ftype_int_v16qi_v16qi
7070     = build_function_type_list (integer_type_node,
7071                                 integer_type_node, V16QI_type_node,
7072                                 V16QI_type_node, NULL_TREE);
7073   tree int_ftype_int_v4sf_v4sf
7074     = build_function_type_list (integer_type_node,
7075                                 integer_type_node, V4SF_type_node,
7076                                 V4SF_type_node, NULL_TREE);
7077   tree v4si_ftype_v4si
7078     = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7079   tree v8hi_ftype_v8hi
7080     = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7081   tree v16qi_ftype_v16qi
7082     = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7083   tree v4sf_ftype_v4sf
7084     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7085   tree void_ftype_pcvoid_int_int
7086     = build_function_type_list (void_type_node,
7087                                 pcvoid_type_node, integer_type_node,
7088                                 integer_type_node, NULL_TREE);
7089   tree int_ftype_pcchar
7090     = build_function_type_list (integer_type_node,
7091                                 pcchar_type_node, NULL_TREE);
7092
7093   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7094                ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7095   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7096                ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7097   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7098                ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7099   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7100                ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7101   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7102                ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7103   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7104                ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7105   def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7106                ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7107   def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7108                ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7109   def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7110   def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7111   def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7112   def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
7113   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7114   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7115   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7116   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7117   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7118   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7119   def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7120   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7121   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7122   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7123   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7124   def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7125
7126   /* See altivec.h for usage of "__builtin_altivec_compiletime_error".  */
7127   def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7128                ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7129
7130   /* Add the DST variants.  */
7131   d = (struct builtin_description *) bdesc_dst;
7132   for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7133     def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7134
7135   /* Initialize the predicates.  */
7136   dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7137   for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7138     {
7139       enum machine_mode mode1;
7140       tree type;
7141
7142       mode1 = insn_data[dp->icode].operand[1].mode;
7143
7144       switch (mode1)
7145         {
7146         case V4SImode:
7147           type = int_ftype_int_v4si_v4si;
7148           break;
7149         case V8HImode:
7150           type = int_ftype_int_v8hi_v8hi;
7151           break;
7152         case V16QImode:
7153           type = int_ftype_int_v16qi_v16qi;
7154           break;
7155         case V4SFmode:
7156           type = int_ftype_int_v4sf_v4sf;
7157           break;
7158         default:
7159           abort ();
7160         }
7161
7162       def_builtin (dp->mask, dp->name, type, dp->code);
7163     }
7164
7165   /* Initialize the abs* operators.  */
7166   d = (struct builtin_description *) bdesc_abs;
7167   for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7168     {
7169       enum machine_mode mode0;
7170       tree type;
7171
7172       mode0 = insn_data[d->icode].operand[0].mode;
7173
7174       switch (mode0)
7175         {
7176         case V4SImode:
7177           type = v4si_ftype_v4si;
7178           break;
7179         case V8HImode:
7180           type = v8hi_ftype_v8hi;
7181           break;
7182         case V16QImode:
7183           type = v16qi_ftype_v16qi;
7184           break;
7185         case V4SFmode:
7186           type = v4sf_ftype_v4sf;
7187           break;
7188         default:
7189           abort ();
7190         }
7191
7192       def_builtin (d->mask, d->name, type, d->code);
7193     }
7194 }
7195
7196 static void
7197 rs6000_common_init_builtins (void)
7198 {
7199   struct builtin_description *d;
7200   size_t i;
7201
7202   tree v4sf_ftype_v4sf_v4sf_v16qi
7203     = build_function_type_list (V4SF_type_node,
7204                                 V4SF_type_node, V4SF_type_node,
7205                                 V16QI_type_node, NULL_TREE);
7206   tree v4si_ftype_v4si_v4si_v16qi
7207     = build_function_type_list (V4SI_type_node,
7208                                 V4SI_type_node, V4SI_type_node,
7209                                 V16QI_type_node, NULL_TREE);
7210   tree v8hi_ftype_v8hi_v8hi_v16qi
7211     = build_function_type_list (V8HI_type_node,
7212                                 V8HI_type_node, V8HI_type_node,
7213                                 V16QI_type_node, NULL_TREE);
7214   tree v16qi_ftype_v16qi_v16qi_v16qi
7215     = build_function_type_list (V16QI_type_node,
7216                                 V16QI_type_node, V16QI_type_node,
7217                                 V16QI_type_node, NULL_TREE);
7218   tree v4si_ftype_int
7219     = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7220   tree v8hi_ftype_int
7221     = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7222   tree v16qi_ftype_int
7223     = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7224   tree v8hi_ftype_v16qi
7225     = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7226   tree v4sf_ftype_v4sf
7227     = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7228
7229   tree v2si_ftype_v2si_v2si
7230     = build_function_type_list (opaque_V2SI_type_node,
7231                                 opaque_V2SI_type_node,
7232                                 opaque_V2SI_type_node, NULL_TREE);
7233
7234   tree v2sf_ftype_v2sf_v2sf
7235     = build_function_type_list (opaque_V2SF_type_node,
7236                                 opaque_V2SF_type_node,
7237                                 opaque_V2SF_type_node, NULL_TREE);
7238
7239   tree v2si_ftype_int_int
7240     = build_function_type_list (opaque_V2SI_type_node,
7241                                 integer_type_node, integer_type_node,
7242                                 NULL_TREE);
7243
7244   tree v2si_ftype_v2si
7245     = build_function_type_list (opaque_V2SI_type_node,
7246                                 opaque_V2SI_type_node, NULL_TREE);
7247
7248   tree v2sf_ftype_v2sf
7249     = build_function_type_list (opaque_V2SF_type_node,
7250                                 opaque_V2SF_type_node, NULL_TREE);
7251
7252   tree v2sf_ftype_v2si
7253     = build_function_type_list (opaque_V2SF_type_node,
7254                                 opaque_V2SI_type_node, NULL_TREE);
7255
7256   tree v2si_ftype_v2sf
7257     = build_function_type_list (opaque_V2SI_type_node,
7258                                 opaque_V2SF_type_node, NULL_TREE);
7259
7260   tree v2si_ftype_v2si_char
7261     = build_function_type_list (opaque_V2SI_type_node,
7262                                 opaque_V2SI_type_node,
7263                                 char_type_node, NULL_TREE);
7264
7265   tree v2si_ftype_int_char
7266     = build_function_type_list (opaque_V2SI_type_node,
7267                                 integer_type_node, char_type_node, NULL_TREE);
7268
7269   tree v2si_ftype_char
7270     = build_function_type_list (opaque_V2SI_type_node,
7271                                 char_type_node, NULL_TREE);
7272
7273   tree int_ftype_int_int
7274     = build_function_type_list (integer_type_node,
7275                                 integer_type_node, integer_type_node,
7276                                 NULL_TREE);
7277
7278   tree v4si_ftype_v4si_v4si
7279     = build_function_type_list (V4SI_type_node,
7280                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7281   tree v4sf_ftype_v4si_int
7282     = build_function_type_list (V4SF_type_node,
7283                                 V4SI_type_node, integer_type_node, NULL_TREE);
7284   tree v4si_ftype_v4sf_int
7285     = build_function_type_list (V4SI_type_node,
7286                                 V4SF_type_node, integer_type_node, NULL_TREE);
7287   tree v4si_ftype_v4si_int
7288     = build_function_type_list (V4SI_type_node,
7289                                 V4SI_type_node, integer_type_node, NULL_TREE);
7290   tree v8hi_ftype_v8hi_int
7291     = build_function_type_list (V8HI_type_node,
7292                                 V8HI_type_node, integer_type_node, NULL_TREE);
7293   tree v16qi_ftype_v16qi_int
7294     = build_function_type_list (V16QI_type_node,
7295                                 V16QI_type_node, integer_type_node, NULL_TREE);
7296   tree v16qi_ftype_v16qi_v16qi_int
7297     = build_function_type_list (V16QI_type_node,
7298                                 V16QI_type_node, V16QI_type_node,
7299                                 integer_type_node, NULL_TREE);
7300   tree v8hi_ftype_v8hi_v8hi_int
7301     = build_function_type_list (V8HI_type_node,
7302                                 V8HI_type_node, V8HI_type_node,
7303                                 integer_type_node, NULL_TREE);
7304   tree v4si_ftype_v4si_v4si_int
7305     = build_function_type_list (V4SI_type_node,
7306                                 V4SI_type_node, V4SI_type_node,
7307                                 integer_type_node, NULL_TREE);
7308   tree v4sf_ftype_v4sf_v4sf_int
7309     = build_function_type_list (V4SF_type_node,
7310                                 V4SF_type_node, V4SF_type_node,
7311                                 integer_type_node, NULL_TREE);
7312   tree v4sf_ftype_v4sf_v4sf
7313     = build_function_type_list (V4SF_type_node,
7314                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7315   tree v4sf_ftype_v4sf_v4sf_v4si
7316     = build_function_type_list (V4SF_type_node,
7317                                 V4SF_type_node, V4SF_type_node,
7318                                 V4SI_type_node, NULL_TREE);
7319   tree v4sf_ftype_v4sf_v4sf_v4sf
7320     = build_function_type_list (V4SF_type_node,
7321                                 V4SF_type_node, V4SF_type_node,
7322                                 V4SF_type_node, NULL_TREE);
7323   tree v4si_ftype_v4si_v4si_v4si
7324     = build_function_type_list (V4SI_type_node,
7325                                 V4SI_type_node, V4SI_type_node,
7326                                 V4SI_type_node, NULL_TREE);
7327   tree v8hi_ftype_v8hi_v8hi
7328     = build_function_type_list (V8HI_type_node,
7329                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7330   tree v8hi_ftype_v8hi_v8hi_v8hi
7331     = build_function_type_list (V8HI_type_node,
7332                                 V8HI_type_node, V8HI_type_node,
7333                                 V8HI_type_node, NULL_TREE);
7334  tree v4si_ftype_v8hi_v8hi_v4si
7335     = build_function_type_list (V4SI_type_node,
7336                                 V8HI_type_node, V8HI_type_node,
7337                                 V4SI_type_node, NULL_TREE);
7338  tree v4si_ftype_v16qi_v16qi_v4si
7339     = build_function_type_list (V4SI_type_node,
7340                                 V16QI_type_node, V16QI_type_node,
7341                                 V4SI_type_node, NULL_TREE);
7342   tree v16qi_ftype_v16qi_v16qi
7343     = build_function_type_list (V16QI_type_node,
7344                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7345   tree v4si_ftype_v4sf_v4sf
7346     = build_function_type_list (V4SI_type_node,
7347                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7348   tree v8hi_ftype_v16qi_v16qi
7349     = build_function_type_list (V8HI_type_node,
7350                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7351   tree v4si_ftype_v8hi_v8hi
7352     = build_function_type_list (V4SI_type_node,
7353                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7354   tree v8hi_ftype_v4si_v4si
7355     = build_function_type_list (V8HI_type_node,
7356                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7357   tree v16qi_ftype_v8hi_v8hi
7358     = build_function_type_list (V16QI_type_node,
7359                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7360   tree v4si_ftype_v16qi_v4si
7361     = build_function_type_list (V4SI_type_node,
7362                                 V16QI_type_node, V4SI_type_node, NULL_TREE);
7363   tree v4si_ftype_v16qi_v16qi
7364     = build_function_type_list (V4SI_type_node,
7365                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7366   tree v4si_ftype_v8hi_v4si
7367     = build_function_type_list (V4SI_type_node,
7368                                 V8HI_type_node, V4SI_type_node, NULL_TREE);
7369   tree v4si_ftype_v8hi
7370     = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7371   tree int_ftype_v4si_v4si
7372     = build_function_type_list (integer_type_node,
7373                                 V4SI_type_node, V4SI_type_node, NULL_TREE);
7374   tree int_ftype_v4sf_v4sf
7375     = build_function_type_list (integer_type_node,
7376                                 V4SF_type_node, V4SF_type_node, NULL_TREE);
7377   tree int_ftype_v16qi_v16qi
7378     = build_function_type_list (integer_type_node,
7379                                 V16QI_type_node, V16QI_type_node, NULL_TREE);
7380   tree int_ftype_v8hi_v8hi
7381     = build_function_type_list (integer_type_node,
7382                                 V8HI_type_node, V8HI_type_node, NULL_TREE);
7383
7384   /* Add the simple ternary operators.  */
7385   d = (struct builtin_description *) bdesc_3arg;
7386   for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7387     {
7388
7389       enum machine_mode mode0, mode1, mode2, mode3;
7390       tree type;
7391
7392       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7393         continue;
7394
7395       mode0 = insn_data[d->icode].operand[0].mode;
7396       mode1 = insn_data[d->icode].operand[1].mode;
7397       mode2 = insn_data[d->icode].operand[2].mode;
7398       mode3 = insn_data[d->icode].operand[3].mode;
7399
7400       /* When all four are of the same mode.  */
7401       if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7402         {
7403           switch (mode0)
7404             {
7405             case V4SImode:
7406               type = v4si_ftype_v4si_v4si_v4si;
7407               break;
7408             case V4SFmode:
7409               type = v4sf_ftype_v4sf_v4sf_v4sf;
7410               break;
7411             case V8HImode:
7412               type = v8hi_ftype_v8hi_v8hi_v8hi;
7413               break;
7414             case V16QImode:
7415               type = v16qi_ftype_v16qi_v16qi_v16qi;
7416               break;
7417             default:
7418               abort();
7419             }
7420         }
7421       else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7422         {
7423           switch (mode0)
7424             {
7425             case V4SImode:
7426               type = v4si_ftype_v4si_v4si_v16qi;
7427               break;
7428             case V4SFmode:
7429               type = v4sf_ftype_v4sf_v4sf_v16qi;
7430               break;
7431             case V8HImode:
7432               type = v8hi_ftype_v8hi_v8hi_v16qi;
7433               break;
7434             case V16QImode:
7435               type = v16qi_ftype_v16qi_v16qi_v16qi;
7436               break;
7437             default:
7438               abort();
7439             }
7440         }
7441       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7442                && mode3 == V4SImode)
7443         type = v4si_ftype_v16qi_v16qi_v4si;
7444       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7445                && mode3 == V4SImode)
7446         type = v4si_ftype_v8hi_v8hi_v4si;
7447       else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7448                && mode3 == V4SImode)
7449         type = v4sf_ftype_v4sf_v4sf_v4si;
7450
7451       /* vchar, vchar, vchar, 4 bit literal.  */
7452       else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7453                && mode3 == QImode)
7454         type = v16qi_ftype_v16qi_v16qi_int;
7455
7456       /* vshort, vshort, vshort, 4 bit literal.  */
7457       else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7458                && mode3 == QImode)
7459         type = v8hi_ftype_v8hi_v8hi_int;
7460
7461       /* vint, vint, vint, 4 bit literal.  */
7462       else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7463                && mode3 == QImode)
7464         type = v4si_ftype_v4si_v4si_int;
7465
7466       /* vfloat, vfloat, vfloat, 4 bit literal.  */
7467       else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7468                && mode3 == QImode)
7469         type = v4sf_ftype_v4sf_v4sf_int;
7470
7471       else
7472         abort ();
7473
7474       def_builtin (d->mask, d->name, type, d->code);
7475     }
7476
7477   /* Add the simple binary operators.  */
7478   d = (struct builtin_description *) bdesc_2arg;
7479   for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7480     {
7481       enum machine_mode mode0, mode1, mode2;
7482       tree type;
7483
7484       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7485         continue;
7486
7487       mode0 = insn_data[d->icode].operand[0].mode;
7488       mode1 = insn_data[d->icode].operand[1].mode;
7489       mode2 = insn_data[d->icode].operand[2].mode;
7490
7491       /* When all three operands are of the same mode.  */
7492       if (mode0 == mode1 && mode1 == mode2)
7493         {
7494           switch (mode0)
7495             {
7496             case V4SFmode:
7497               type = v4sf_ftype_v4sf_v4sf;
7498               break;
7499             case V4SImode:
7500               type = v4si_ftype_v4si_v4si;
7501               break;
7502             case V16QImode:
7503               type = v16qi_ftype_v16qi_v16qi;
7504               break;
7505             case V8HImode:
7506               type = v8hi_ftype_v8hi_v8hi;
7507               break;
7508             case V2SImode:
7509               type = v2si_ftype_v2si_v2si;
7510               break;
7511             case V2SFmode:
7512               type = v2sf_ftype_v2sf_v2sf;
7513               break;
7514             case SImode:
7515               type = int_ftype_int_int;
7516               break;
7517             default:
7518               abort ();
7519             }
7520         }
7521
7522       /* A few other combos we really don't want to do manually.  */
7523
7524       /* vint, vfloat, vfloat.  */
7525       else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7526         type = v4si_ftype_v4sf_v4sf;
7527
7528       /* vshort, vchar, vchar.  */
7529       else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7530         type = v8hi_ftype_v16qi_v16qi;
7531
7532       /* vint, vshort, vshort.  */
7533       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7534         type = v4si_ftype_v8hi_v8hi;
7535
7536       /* vshort, vint, vint.  */
7537       else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7538         type = v8hi_ftype_v4si_v4si;
7539
7540       /* vchar, vshort, vshort.  */
7541       else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7542         type = v16qi_ftype_v8hi_v8hi;
7543
7544       /* vint, vchar, vint.  */
7545       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7546         type = v4si_ftype_v16qi_v4si;
7547
7548       /* vint, vchar, vchar.  */
7549       else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7550         type = v4si_ftype_v16qi_v16qi;
7551
7552       /* vint, vshort, vint.  */
7553       else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7554         type = v4si_ftype_v8hi_v4si;
7555
7556       /* vint, vint, 5 bit literal.  */
7557       else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7558         type = v4si_ftype_v4si_int;
7559
7560       /* vshort, vshort, 5 bit literal.  */
7561       else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7562         type = v8hi_ftype_v8hi_int;
7563
7564       /* vchar, vchar, 5 bit literal.  */
7565       else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7566         type = v16qi_ftype_v16qi_int;
7567
7568       /* vfloat, vint, 5 bit literal.  */
7569       else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7570         type = v4sf_ftype_v4si_int;
7571
7572       /* vint, vfloat, 5 bit literal.  */
7573       else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7574         type = v4si_ftype_v4sf_int;
7575
7576       else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7577         type = v2si_ftype_int_int;
7578
7579       else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7580         type = v2si_ftype_v2si_char;
7581
7582       else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7583         type = v2si_ftype_int_char;
7584
7585       /* int, x, x.  */
7586       else if (mode0 == SImode)
7587         {
7588           switch (mode1)
7589             {
7590             case V4SImode:
7591               type = int_ftype_v4si_v4si;
7592               break;
7593             case V4SFmode:
7594               type = int_ftype_v4sf_v4sf;
7595               break;
7596             case V16QImode:
7597               type = int_ftype_v16qi_v16qi;
7598               break;
7599             case V8HImode:
7600               type = int_ftype_v8hi_v8hi;
7601               break;
7602             default:
7603               abort ();
7604             }
7605         }
7606
7607       else
7608         abort ();
7609
7610       def_builtin (d->mask, d->name, type, d->code);
7611     }
7612
7613   /* Add the simple unary operators.  */
7614   d = (struct builtin_description *) bdesc_1arg;
7615   for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7616     {
7617       enum machine_mode mode0, mode1;
7618       tree type;
7619
7620       if (d->name == 0 || d->icode == CODE_FOR_nothing)
7621         continue;
7622
7623       mode0 = insn_data[d->icode].operand[0].mode;
7624       mode1 = insn_data[d->icode].operand[1].mode;
7625
7626       if (mode0 == V4SImode && mode1 == QImode)
7627         type = v4si_ftype_int;
7628       else if (mode0 == V8HImode && mode1 == QImode)
7629         type = v8hi_ftype_int;
7630       else if (mode0 == V16QImode && mode1 == QImode)
7631         type = v16qi_ftype_int;
7632       else if (mode0 == V4SFmode && mode1 == V4SFmode)
7633         type = v4sf_ftype_v4sf;
7634       else if (mode0 == V8HImode && mode1 == V16QImode)
7635         type = v8hi_ftype_v16qi;
7636       else if (mode0 == V4SImode && mode1 == V8HImode)
7637         type = v4si_ftype_v8hi;
7638       else if (mode0 == V2SImode && mode1 == V2SImode)
7639         type = v2si_ftype_v2si;
7640       else if (mode0 == V2SFmode && mode1 == V2SFmode)
7641         type = v2sf_ftype_v2sf;
7642       else if (mode0 == V2SFmode && mode1 == V2SImode)
7643         type = v2sf_ftype_v2si;
7644       else if (mode0 == V2SImode && mode1 == V2SFmode)
7645         type = v2si_ftype_v2sf;
7646       else if (mode0 == V2SImode && mode1 == QImode)
7647         type = v2si_ftype_char;
7648       else
7649         abort ();
7650
7651       def_builtin (d->mask, d->name, type, d->code);
7652     }
7653 }
7654
7655 static void
7656 rs6000_init_libfuncs (void)
7657 {
7658   if (!TARGET_HARD_FLOAT)
7659     return;
7660
7661   if (DEFAULT_ABI != ABI_V4)
7662     {
7663       if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7664         {
7665           /* AIX library routines for float->int conversion.  */
7666           set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7667           set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7668           set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
7669           set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
7670         }
7671
7672       /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines.  */
7673       set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7674       set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7675       set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7676       set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7677     }
7678   else
7679     {
7680       /* 32-bit SVR4 quad floating point routines.  */
7681
7682       set_optab_libfunc (add_optab, TFmode, "_q_add");
7683       set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7684       set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7685       set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7686       set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7687       if (TARGET_PPC_GPOPT || TARGET_POWER2)
7688         set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7689
7690       set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7691       set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7692       set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7693       set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7694       set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7695       set_optab_libfunc (le_optab, TFmode, "_q_fle");
7696
7697       set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7698       set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7699       set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7700       set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7701       set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7702       set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7703       set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7704     }
7705 }
7706 \f
7707 /* Expand a block move operation, and return 1 if successful.  Return 0
7708    if we should let the compiler generate normal code.
7709
7710    operands[0] is the destination
7711    operands[1] is the source
7712    operands[2] is the length
7713    operands[3] is the alignment */
7714
7715 #define MAX_MOVE_REG 4
7716
7717 int
7718 expand_block_move (rtx operands[])
7719 {
7720   rtx orig_dest = operands[0];
7721   rtx orig_src  = operands[1];
7722   rtx bytes_rtx = operands[2];
7723   rtx align_rtx = operands[3];
7724   int constp    = (GET_CODE (bytes_rtx) == CONST_INT);
7725   int align;
7726   int bytes;
7727   int offset;
7728   int move_bytes;
7729   rtx stores[MAX_MOVE_REG];
7730   int num_reg = 0;
7731
7732   /* If this is not a fixed size move, just call memcpy */
7733   if (! constp)
7734     return 0;
7735
7736   /* If this is not a fixed size alignment, abort */
7737   if (GET_CODE (align_rtx) != CONST_INT)
7738     abort ();
7739   align = INTVAL (align_rtx);
7740
7741   /* Anything to move? */
7742   bytes = INTVAL (bytes_rtx);
7743   if (bytes <= 0)
7744     return 1;
7745
7746   /* store_one_arg depends on expand_block_move to handle at least the size of
7747      reg_parm_stack_space.  */
7748   if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7749     return 0;
7750
7751   for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7752     {
7753       union {
7754         rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7755         rtx (*mov) (rtx, rtx);
7756       } gen_func;
7757       enum machine_mode mode = BLKmode;
7758       rtx src, dest;
7759
7760       if (TARGET_STRING
7761           && bytes > 24         /* move up to 32 bytes at a time */
7762           && ! fixed_regs[5]
7763           && ! fixed_regs[6]
7764           && ! fixed_regs[7]
7765           && ! fixed_regs[8]
7766           && ! fixed_regs[9]
7767           && ! fixed_regs[10]
7768           && ! fixed_regs[11]
7769           && ! fixed_regs[12])
7770         {
7771           move_bytes = (bytes > 32) ? 32 : bytes;
7772           gen_func.movstrsi = gen_movstrsi_8reg;
7773         }
7774       else if (TARGET_STRING
7775                && bytes > 16    /* move up to 24 bytes at a time */
7776                && ! fixed_regs[5]
7777                && ! fixed_regs[6]
7778                && ! fixed_regs[7]
7779                && ! fixed_regs[8]
7780                && ! fixed_regs[9]
7781                && ! fixed_regs[10])
7782         {
7783           move_bytes = (bytes > 24) ? 24 : bytes;
7784           gen_func.movstrsi = gen_movstrsi_6reg;
7785         }
7786       else if (TARGET_STRING
7787                && bytes > 8     /* move up to 16 bytes at a time */
7788                && ! fixed_regs[5]
7789                && ! fixed_regs[6]
7790                && ! fixed_regs[7]
7791                && ! fixed_regs[8])
7792         {
7793           move_bytes = (bytes > 16) ? 16 : bytes;
7794           gen_func.movstrsi = gen_movstrsi_4reg;
7795         }
7796       else if (bytes >= 8 && TARGET_POWERPC64
7797                /* 64-bit loads and stores require word-aligned
7798                   displacements.  */
7799                && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7800         {
7801           move_bytes = 8;
7802           mode = DImode;
7803           gen_func.mov = gen_movdi;
7804         }
7805       else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7806         {                       /* move up to 8 bytes at a time */
7807           move_bytes = (bytes > 8) ? 8 : bytes;
7808           gen_func.movstrsi = gen_movstrsi_2reg;
7809         }
7810       else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7811         {                       /* move 4 bytes */
7812           move_bytes = 4;
7813           mode = SImode;
7814           gen_func.mov = gen_movsi;
7815         }
7816       else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7817         {                       /* move 2 bytes */
7818           move_bytes = 2;
7819           mode = HImode;
7820           gen_func.mov = gen_movhi;
7821         }
7822       else if (TARGET_STRING && bytes > 1)
7823         {                       /* move up to 4 bytes at a time */
7824           move_bytes = (bytes > 4) ? 4 : bytes;
7825           gen_func.movstrsi = gen_movstrsi_1reg;
7826         }
7827       else /* move 1 byte at a time */
7828         {
7829           move_bytes = 1;
7830           mode = QImode;
7831           gen_func.mov = gen_movqi;
7832         }
7833
7834       src = adjust_address (orig_src, mode, offset);
7835       dest = adjust_address (orig_dest, mode, offset);
7836
7837       if (mode != BLKmode)
7838         {
7839           rtx tmp_reg = gen_reg_rtx (mode);
7840
7841           emit_insn ((*gen_func.mov) (tmp_reg, src));
7842           stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7843         }
7844
7845       if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7846         {
7847           int i;
7848           for (i = 0; i < num_reg; i++)
7849             emit_insn (stores[i]);
7850           num_reg = 0;
7851         }
7852
7853       if (mode == BLKmode)
7854         {
7855           /* Move the address into scratch registers.  The movstrsi
7856              patterns require zero offset.  */
7857           if (!REG_P (XEXP (src, 0)))
7858             {
7859               rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7860               src = replace_equiv_address (src, src_reg);
7861             }
7862           set_mem_size (src, GEN_INT (move_bytes));
7863
7864           if (!REG_P (XEXP (dest, 0)))
7865             {
7866               rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7867               dest = replace_equiv_address (dest, dest_reg);
7868             }
7869           set_mem_size (dest, GEN_INT (move_bytes));
7870
7871           emit_insn ((*gen_func.movstrsi) (dest, src,
7872                                            GEN_INT (move_bytes & 31),
7873                                            align_rtx));
7874         }
7875     }
7876
7877   return 1;
7878 }
7879
7880 \f
7881 /* Return 1 if OP is a load multiple operation.  It is known to be a
7882    PARALLEL and the first section will be tested.  */
7883
7884 int
7885 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7886 {
7887   int count = XVECLEN (op, 0);
7888   unsigned int dest_regno;
7889   rtx src_addr;
7890   int i;
7891
7892   /* Perform a quick check so we don't blow up below.  */
7893   if (count <= 1
7894       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7895       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7896       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7897     return 0;
7898
7899   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7900   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7901
7902   for (i = 1; i < count; i++)
7903     {
7904       rtx elt = XVECEXP (op, 0, i);
7905
7906       if (GET_CODE (elt) != SET
7907           || GET_CODE (SET_DEST (elt)) != REG
7908           || GET_MODE (SET_DEST (elt)) != SImode
7909           || REGNO (SET_DEST (elt)) != dest_regno + i
7910           || GET_CODE (SET_SRC (elt)) != MEM
7911           || GET_MODE (SET_SRC (elt)) != SImode
7912           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7913           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7914           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7915           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7916         return 0;
7917     }
7918
7919   return 1;
7920 }
7921
7922 /* Similar, but tests for store multiple.  Here, the second vector element
7923    is a CLOBBER.  It will be tested later.  */
7924
7925 int
7926 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7927 {
7928   int count = XVECLEN (op, 0) - 1;
7929   unsigned int src_regno;
7930   rtx dest_addr;
7931   int i;
7932
7933   /* Perform a quick check so we don't blow up below.  */
7934   if (count <= 1
7935       || GET_CODE (XVECEXP (op, 0, 0)) != SET
7936       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7937       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7938     return 0;
7939
7940   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7941   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7942
7943   for (i = 1; i < count; i++)
7944     {
7945       rtx elt = XVECEXP (op, 0, i + 1);
7946
7947       if (GET_CODE (elt) != SET
7948           || GET_CODE (SET_SRC (elt)) != REG
7949           || GET_MODE (SET_SRC (elt)) != SImode
7950           || REGNO (SET_SRC (elt)) != src_regno + i
7951           || GET_CODE (SET_DEST (elt)) != MEM
7952           || GET_MODE (SET_DEST (elt)) != SImode
7953           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
7954           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
7955           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
7956           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
7957         return 0;
7958     }
7959
7960   return 1;
7961 }
7962
7963 /* Return a string to perform a load_multiple operation.
7964    operands[0] is the vector.
7965    operands[1] is the source address.
7966    operands[2] is the first destination register.  */
7967
7968 const char *
7969 rs6000_output_load_multiple (rtx operands[3])
7970 {
7971   /* We have to handle the case where the pseudo used to contain the address
7972      is assigned to one of the output registers.  */
7973   int i, j;
7974   int words = XVECLEN (operands[0], 0);
7975   rtx xop[10];
7976
7977   if (XVECLEN (operands[0], 0) == 1)
7978     return "{l|lwz} %2,0(%1)";
7979
7980   for (i = 0; i < words; i++)
7981     if (refers_to_regno_p (REGNO (operands[2]) + i,
7982                            REGNO (operands[2]) + i + 1, operands[1], 0))
7983       {
7984         if (i == words-1)
7985           {
7986             xop[0] = GEN_INT (4 * (words-1));
7987             xop[1] = operands[1];
7988             xop[2] = operands[2];
7989             output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
7990             return "";
7991           }
7992         else if (i == 0)
7993           {
7994             xop[0] = GEN_INT (4 * (words-1));
7995             xop[1] = operands[1];
7996             xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7997             output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
7998             return "";
7999           }
8000         else
8001           {
8002             for (j = 0; j < words; j++)
8003               if (j != i)
8004                 {
8005                   xop[0] = GEN_INT (j * 4);
8006                   xop[1] = operands[1];
8007                   xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8008                   output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8009                 }
8010             xop[0] = GEN_INT (i * 4);
8011             xop[1] = operands[1];
8012             output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8013             return "";
8014           }
8015       }
8016
8017   return "{lsi|lswi} %2,%1,%N0";
8018 }
8019
8020 /* Return 1 for a parallel vrsave operation.  */
8021
8022 int
8023 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8024 {
8025   int count = XVECLEN (op, 0);
8026   unsigned int dest_regno, src_regno;
8027   int i;
8028
8029   if (count <= 1
8030       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8031       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8032       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
8033     return 0;
8034
8035   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8036   src_regno  = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8037
8038   if (dest_regno != VRSAVE_REGNO
8039       && src_regno != VRSAVE_REGNO)
8040     return 0;
8041
8042   for (i = 1; i < count; i++)
8043     {
8044       rtx elt = XVECEXP (op, 0, i);
8045
8046       if (GET_CODE (elt) != CLOBBER
8047           && GET_CODE (elt) != SET)
8048         return 0;
8049     }
8050
8051   return 1;
8052 }
8053
8054 /* Return 1 for an PARALLEL suitable for mfcr.  */
8055
8056 int
8057 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8058 {
8059   int count = XVECLEN (op, 0);
8060   int i;
8061
8062   /* Perform a quick check so we don't blow up below.  */
8063   if (count < 1
8064       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8065       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8066       || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8067     return 0;
8068
8069   for (i = 0; i < count; i++)
8070     {
8071       rtx exp = XVECEXP (op, 0, i);
8072       rtx unspec;
8073       int maskval;
8074       rtx src_reg;
8075
8076       src_reg = XVECEXP (SET_SRC (exp), 0, 0);
8077
8078       if (GET_CODE (src_reg) != REG
8079           || GET_MODE (src_reg) != CCmode
8080           || ! CR_REGNO_P (REGNO (src_reg)))
8081         return 0;
8082
8083       if (GET_CODE (exp) != SET
8084           || GET_CODE (SET_DEST (exp)) != REG
8085           || GET_MODE (SET_DEST (exp)) != SImode
8086           || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
8087         return 0;
8088       unspec = SET_SRC (exp);
8089       maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
8090
8091       if (GET_CODE (unspec) != UNSPEC
8092           || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
8093           || XVECLEN (unspec, 0) != 2
8094           || XVECEXP (unspec, 0, 0) != src_reg
8095           || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8096           || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8097         return 0;
8098     }
8099   return 1;
8100 }
8101
8102 /* Return 1 for an PARALLEL suitable for mtcrf.  */
8103
8104 int
8105 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8106 {
8107   int count = XVECLEN (op, 0);
8108   int i;
8109   rtx src_reg;
8110
8111   /* Perform a quick check so we don't blow up below.  */
8112   if (count < 1
8113       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8114       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8115       || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8116     return 0;
8117   src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
8118
8119   if (GET_CODE (src_reg) != REG
8120       || GET_MODE (src_reg) != SImode
8121       || ! INT_REGNO_P (REGNO (src_reg)))
8122     return 0;
8123
8124   for (i = 0; i < count; i++)
8125     {
8126       rtx exp = XVECEXP (op, 0, i);
8127       rtx unspec;
8128       int maskval;
8129
8130       if (GET_CODE (exp) != SET
8131           || GET_CODE (SET_DEST (exp)) != REG
8132           || GET_MODE (SET_DEST (exp)) != CCmode
8133           || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
8134         return 0;
8135       unspec = SET_SRC (exp);
8136       maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
8137
8138       if (GET_CODE (unspec) != UNSPEC
8139           || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
8140           || XVECLEN (unspec, 0) != 2
8141           || XVECEXP (unspec, 0, 0) != src_reg
8142           || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8143           || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8144         return 0;
8145     }
8146   return 1;
8147 }
8148
8149 /* Return 1 for an PARALLEL suitable for lmw.  */
8150
8151 int
8152 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8153 {
8154   int count = XVECLEN (op, 0);
8155   unsigned int dest_regno;
8156   rtx src_addr;
8157   unsigned int base_regno;
8158   HOST_WIDE_INT offset;
8159   int i;
8160
8161   /* Perform a quick check so we don't blow up below.  */
8162   if (count <= 1
8163       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8164       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8165       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8166     return 0;
8167
8168   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8169   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8170
8171   if (dest_regno > 31
8172       || count != 32 - (int) dest_regno)
8173     return 0;
8174
8175   if (legitimate_indirect_address_p (src_addr, 0))
8176     {
8177       offset = 0;
8178       base_regno = REGNO (src_addr);
8179       if (base_regno == 0)
8180         return 0;
8181     }
8182   else if (legitimate_offset_address_p (SImode, src_addr, 0))
8183     {
8184       offset = INTVAL (XEXP (src_addr, 1));
8185       base_regno = REGNO (XEXP (src_addr, 0));
8186     }
8187   else
8188     return 0;
8189
8190   for (i = 0; i < count; i++)
8191     {
8192       rtx elt = XVECEXP (op, 0, i);
8193       rtx newaddr;
8194       rtx addr_reg;
8195       HOST_WIDE_INT newoffset;
8196
8197       if (GET_CODE (elt) != SET
8198           || GET_CODE (SET_DEST (elt)) != REG
8199           || GET_MODE (SET_DEST (elt)) != SImode
8200           || REGNO (SET_DEST (elt)) != dest_regno + i
8201           || GET_CODE (SET_SRC (elt)) != MEM
8202           || GET_MODE (SET_SRC (elt)) != SImode)
8203         return 0;
8204       newaddr = XEXP (SET_SRC (elt), 0);
8205       if (legitimate_indirect_address_p (newaddr, 0))
8206         {
8207           newoffset = 0;
8208           addr_reg = newaddr;
8209         }
8210       else if (legitimate_offset_address_p (SImode, newaddr, 0))
8211         {
8212           addr_reg = XEXP (newaddr, 0);
8213           newoffset = INTVAL (XEXP (newaddr, 1));
8214         }
8215       else
8216         return 0;
8217       if (REGNO (addr_reg) != base_regno
8218           || newoffset != offset + 4 * i)
8219         return 0;
8220     }
8221
8222   return 1;
8223 }
8224
8225 /* Return 1 for an PARALLEL suitable for stmw.  */
8226
8227 int
8228 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8229 {
8230   int count = XVECLEN (op, 0);
8231   unsigned int src_regno;
8232   rtx dest_addr;
8233   unsigned int base_regno;
8234   HOST_WIDE_INT offset;
8235   int i;
8236
8237   /* Perform a quick check so we don't blow up below.  */
8238   if (count <= 1
8239       || GET_CODE (XVECEXP (op, 0, 0)) != SET
8240       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
8241       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
8242     return 0;
8243
8244   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8245   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
8246
8247   if (src_regno > 31
8248       || count != 32 - (int) src_regno)
8249     return 0;
8250
8251   if (legitimate_indirect_address_p (dest_addr, 0))
8252     {
8253       offset = 0;
8254       base_regno = REGNO (dest_addr);
8255       if (base_regno == 0)
8256         return 0;
8257     }
8258   else if (legitimate_offset_address_p (SImode, dest_addr, 0))
8259     {
8260       offset = INTVAL (XEXP (dest_addr, 1));
8261       base_regno = REGNO (XEXP (dest_addr, 0));
8262     }
8263   else
8264     return 0;
8265
8266   for (i = 0; i < count; i++)
8267     {
8268       rtx elt = XVECEXP (op, 0, i);
8269       rtx newaddr;
8270       rtx addr_reg;
8271       HOST_WIDE_INT newoffset;
8272
8273       if (GET_CODE (elt) != SET
8274           || GET_CODE (SET_SRC (elt)) != REG
8275           || GET_MODE (SET_SRC (elt)) != SImode
8276           || REGNO (SET_SRC (elt)) != src_regno + i
8277           || GET_CODE (SET_DEST (elt)) != MEM
8278           || GET_MODE (SET_DEST (elt)) != SImode)
8279         return 0;
8280       newaddr = XEXP (SET_DEST (elt), 0);
8281       if (legitimate_indirect_address_p (newaddr, 0))
8282         {
8283           newoffset = 0;
8284           addr_reg = newaddr;
8285         }
8286       else if (legitimate_offset_address_p (SImode, newaddr, 0))
8287         {
8288           addr_reg = XEXP (newaddr, 0);
8289           newoffset = INTVAL (XEXP (newaddr, 1));
8290         }
8291       else
8292         return 0;
8293       if (REGNO (addr_reg) != base_regno
8294           || newoffset != offset + 4 * i)
8295         return 0;
8296     }
8297
8298   return 1;
8299 }
8300 \f
8301 /* A validation routine: say whether CODE, a condition code, and MODE
8302    match.  The other alternatives either don't make sense or should
8303    never be generated.  */
8304
8305 static void
8306 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8307 {
8308   if ((GET_RTX_CLASS (code) != RTX_COMPARE
8309        && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8310       || GET_MODE_CLASS (mode) != MODE_CC)
8311     abort ();
8312
8313   /* These don't make sense.  */
8314   if ((code == GT || code == LT || code == GE || code == LE)
8315       && mode == CCUNSmode)
8316     abort ();
8317
8318   if ((code == GTU || code == LTU || code == GEU || code == LEU)
8319       && mode != CCUNSmode)
8320     abort ();
8321
8322   if (mode != CCFPmode
8323       && (code == ORDERED || code == UNORDERED
8324           || code == UNEQ || code == LTGT
8325           || code == UNGT || code == UNLT
8326           || code == UNGE || code == UNLE))
8327     abort ();
8328
8329   /* These should never be generated except for
8330      flag_finite_math_only.  */
8331   if (mode == CCFPmode
8332       && ! flag_finite_math_only
8333       && (code == LE || code == GE
8334           || code == UNEQ || code == LTGT
8335           || code == UNGT || code == UNLT))
8336     abort ();
8337
8338   /* These are invalid; the information is not there.  */
8339   if (mode == CCEQmode
8340       && code != EQ && code != NE)
8341     abort ();
8342 }
8343
8344 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
8345    We only check the opcode against the mode of the CC value here.  */
8346
8347 int
8348 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8349 {
8350   enum rtx_code code = GET_CODE (op);
8351   enum machine_mode cc_mode;
8352
8353   if (!COMPARISON_P (op))
8354     return 0;
8355
8356   cc_mode = GET_MODE (XEXP (op, 0));
8357   if (GET_MODE_CLASS (cc_mode) != MODE_CC)
8358     return 0;
8359
8360   validate_condition_mode (code, cc_mode);
8361
8362   return 1;
8363 }
8364
8365 /* Return 1 if OP is a comparison operation that is valid for a branch
8366    insn and which is true if the corresponding bit in the CC register
8367    is set.  */
8368
8369 int
8370 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
8371 {
8372   enum rtx_code code;
8373
8374   if (! branch_comparison_operator (op, mode))
8375     return 0;
8376
8377   code = GET_CODE (op);
8378   return (code == EQ || code == LT || code == GT
8379           || code == LTU || code == GTU
8380           || code == UNORDERED);
8381 }
8382
8383 /* Return 1 if OP is a comparison operation that is valid for an scc
8384    insn: it must be a positive comparison.  */
8385
8386 int
8387 scc_comparison_operator (rtx op, enum machine_mode mode)
8388 {
8389   return branch_positive_comparison_operator (op, mode);
8390 }
8391
8392 int
8393 trap_comparison_operator (rtx op, enum machine_mode mode)
8394 {
8395   if (mode != VOIDmode && mode != GET_MODE (op))
8396     return 0;
8397   return COMPARISON_P (op);
8398 }
8399
8400 int
8401 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8402 {
8403   enum rtx_code code = GET_CODE (op);
8404   return (code == AND || code == IOR || code == XOR);
8405 }
8406
8407 int
8408 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8409 {
8410   enum rtx_code code = GET_CODE (op);
8411   return (code == IOR || code == XOR);
8412 }
8413
8414 int
8415 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8416 {
8417   enum rtx_code code = GET_CODE (op);
8418   return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8419 }
8420 \f
8421 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8422    mask required to convert the result of a rotate insn into a shift
8423    left insn of SHIFTOP bits.  Both are known to be SImode CONST_INT.  */
8424
8425 int
8426 includes_lshift_p (rtx shiftop, rtx andop)
8427 {
8428   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8429
8430   shift_mask <<= INTVAL (shiftop);
8431
8432   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8433 }
8434
8435 /* Similar, but for right shift.  */
8436
8437 int
8438 includes_rshift_p (rtx shiftop, rtx andop)
8439 {
8440   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8441
8442   shift_mask >>= INTVAL (shiftop);
8443
8444   return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8445 }
8446
8447 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8448    to perform a left shift.  It must have exactly SHIFTOP least
8449    significant 0's, then one or more 1's, then zero or more 0's.  */
8450
8451 int
8452 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8453 {
8454   if (GET_CODE (andop) == CONST_INT)
8455     {
8456       HOST_WIDE_INT c, lsb, shift_mask;
8457
8458       c = INTVAL (andop);
8459       if (c == 0 || c == ~0)
8460         return 0;
8461
8462       shift_mask = ~0;
8463       shift_mask <<= INTVAL (shiftop);
8464
8465       /* Find the least significant one bit.  */
8466       lsb = c & -c;
8467
8468       /* It must coincide with the LSB of the shift mask.  */
8469       if (-lsb != shift_mask)
8470         return 0;
8471
8472       /* Invert to look for the next transition (if any).  */
8473       c = ~c;
8474
8475       /* Remove the low group of ones (originally low group of zeros).  */
8476       c &= -lsb;
8477
8478       /* Again find the lsb, and check we have all 1's above.  */
8479       lsb = c & -c;
8480       return c == -lsb;
8481     }
8482   else if (GET_CODE (andop) == CONST_DOUBLE
8483            && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8484     {
8485       HOST_WIDE_INT low, high, lsb;
8486       HOST_WIDE_INT shift_mask_low, shift_mask_high;
8487
8488       low = CONST_DOUBLE_LOW (andop);
8489       if (HOST_BITS_PER_WIDE_INT < 64)
8490         high = CONST_DOUBLE_HIGH (andop);
8491
8492       if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8493           || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8494         return 0;
8495
8496       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8497         {
8498           shift_mask_high = ~0;
8499           if (INTVAL (shiftop) > 32)
8500             shift_mask_high <<= INTVAL (shiftop) - 32;
8501
8502           lsb = high & -high;
8503
8504           if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8505             return 0;
8506
8507           high = ~high;
8508           high &= -lsb;
8509
8510           lsb = high & -high;
8511           return high == -lsb;
8512         }
8513
8514       shift_mask_low = ~0;
8515       shift_mask_low <<= INTVAL (shiftop);
8516
8517       lsb = low & -low;
8518
8519       if (-lsb != shift_mask_low)
8520         return 0;
8521
8522       if (HOST_BITS_PER_WIDE_INT < 64)
8523         high = ~high;
8524       low = ~low;
8525       low &= -lsb;
8526
8527       if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8528         {
8529           lsb = high & -high;
8530           return high == -lsb;
8531         }
8532
8533       lsb = low & -low;
8534       return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8535     }
8536   else
8537     return 0;
8538 }
8539
8540 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8541    to perform a left shift.  It must have SHIFTOP or more least
8542    significant 0's, with the remainder of the word 1's.  */
8543
8544 int
8545 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8546 {
8547   if (GET_CODE (andop) == CONST_INT)
8548     {
8549       HOST_WIDE_INT c, lsb, shift_mask;
8550
8551       shift_mask = ~0;
8552       shift_mask <<= INTVAL (shiftop);
8553       c = INTVAL (andop);
8554
8555       /* Find the least significant one bit.  */
8556       lsb = c & -c;
8557
8558       /* It must be covered by the shift mask.
8559          This test also rejects c == 0.  */
8560       if ((lsb & shift_mask) == 0)
8561         return 0;
8562
8563       /* Check we have all 1's above the transition, and reject all 1's.  */
8564       return c == -lsb && lsb != 1;
8565     }
8566   else if (GET_CODE (andop) == CONST_DOUBLE
8567            && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8568     {
8569       HOST_WIDE_INT low, lsb, shift_mask_low;
8570
8571       low = CONST_DOUBLE_LOW (andop);
8572
8573       if (HOST_BITS_PER_WIDE_INT < 64)
8574         {
8575           HOST_WIDE_INT high, shift_mask_high;
8576
8577           high = CONST_DOUBLE_HIGH (andop);
8578
8579           if (low == 0)
8580             {
8581               shift_mask_high = ~0;
8582               if (INTVAL (shiftop) > 32)
8583                 shift_mask_high <<= INTVAL (shiftop) - 32;
8584
8585               lsb = high & -high;
8586
8587               if ((lsb & shift_mask_high) == 0)
8588                 return 0;
8589
8590               return high == -lsb;
8591             }
8592           if (high != ~0)
8593             return 0;
8594         }
8595
8596       shift_mask_low = ~0;
8597       shift_mask_low <<= INTVAL (shiftop);
8598
8599       lsb = low & -low;
8600
8601       if ((lsb & shift_mask_low) == 0)
8602         return 0;
8603
8604       return low == -lsb && lsb != 1;
8605     }
8606   else
8607     return 0;
8608 }
8609
8610 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8611    for lfq and stfq insns.
8612
8613    Note reg1 and reg2 *must* be hard registers.  To be sure we will
8614    abort if we are passed pseudo registers.  */
8615
8616 int
8617 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8618 {
8619   /* We might have been passed a SUBREG.  */
8620   if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8621     return 0;
8622
8623   return (REGNO (reg1) == REGNO (reg2) - 1);
8624 }
8625
8626 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8627    addr1 and addr2 must be in consecutive memory locations
8628    (addr2 == addr1 + 8).  */
8629
8630 int
8631 addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
8632 {
8633   unsigned int reg1;
8634   int offset1;
8635
8636   /* Extract an offset (if used) from the first addr.  */
8637   if (GET_CODE (addr1) == PLUS)
8638     {
8639       /* If not a REG, return zero.  */
8640       if (GET_CODE (XEXP (addr1, 0)) != REG)
8641         return 0;
8642       else
8643         {
8644           reg1 = REGNO (XEXP (addr1, 0));
8645           /* The offset must be constant!  */
8646           if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8647             return 0;
8648           offset1 = INTVAL (XEXP (addr1, 1));
8649         }
8650     }
8651   else if (GET_CODE (addr1) != REG)
8652     return 0;
8653   else
8654     {
8655       reg1 = REGNO (addr1);
8656       /* This was a simple (mem (reg)) expression.  Offset is 0.  */
8657       offset1 = 0;
8658     }
8659
8660   /* Make sure the second address is a (mem (plus (reg) (const_int)))
8661      or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8662      register as addr1.  */
8663   if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8664     return 1;
8665   if (GET_CODE (addr2) != PLUS)
8666     return 0;
8667
8668   if (GET_CODE (XEXP (addr2, 0)) != REG
8669       || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8670     return 0;
8671
8672   if (reg1 != REGNO (XEXP (addr2, 0)))
8673     return 0;
8674
8675   /* The offset for the second addr must be 8 more than the first addr.  */
8676   if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8677     return 0;
8678
8679   /* All the tests passed.  addr1 and addr2 are valid for lfq or stfq
8680      instructions.  */
8681   return 1;
8682 }
8683 \f
8684 /* Return the register class of a scratch register needed to copy IN into
8685    or out of a register in CLASS in MODE.  If it can be done directly,
8686    NO_REGS is returned.  */
8687
8688 enum reg_class
8689 secondary_reload_class (enum reg_class class,
8690                         enum machine_mode mode ATTRIBUTE_UNUSED,
8691                         rtx in)
8692 {
8693   int regno;
8694
8695   if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8696 #if TARGET_MACHO
8697                     && MACHOPIC_INDIRECT
8698 #endif
8699                     ))
8700     {
8701       /* We cannot copy a symbolic operand directly into anything
8702          other than BASE_REGS for TARGET_ELF.  So indicate that a
8703          register from BASE_REGS is needed as an intermediate
8704          register.
8705
8706          On Darwin, pic addresses require a load from memory, which
8707          needs a base register.  */
8708       if (class != BASE_REGS
8709           && (GET_CODE (in) == SYMBOL_REF
8710               || GET_CODE (in) == HIGH
8711               || GET_CODE (in) == LABEL_REF
8712               || GET_CODE (in) == CONST))
8713         return BASE_REGS;
8714     }
8715
8716   if (GET_CODE (in) == REG)
8717     {
8718       regno = REGNO (in);
8719       if (regno >= FIRST_PSEUDO_REGISTER)
8720         {
8721           regno = true_regnum (in);
8722           if (regno >= FIRST_PSEUDO_REGISTER)
8723             regno = -1;
8724         }
8725     }
8726   else if (GET_CODE (in) == SUBREG)
8727     {
8728       regno = true_regnum (in);
8729       if (regno >= FIRST_PSEUDO_REGISTER)
8730         regno = -1;
8731     }
8732   else
8733     regno = -1;
8734
8735   /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8736      into anything.  */
8737   if (class == GENERAL_REGS || class == BASE_REGS
8738       || (regno >= 0 && INT_REGNO_P (regno)))
8739     return NO_REGS;
8740
8741   /* Constants, memory, and FP registers can go into FP registers.  */
8742   if ((regno == -1 || FP_REGNO_P (regno))
8743       && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8744     return NO_REGS;
8745
8746   /* Memory, and AltiVec registers can go into AltiVec registers.  */
8747   if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8748       && class == ALTIVEC_REGS)
8749     return NO_REGS;
8750
8751   /* We can copy among the CR registers.  */
8752   if ((class == CR_REGS || class == CR0_REGS)
8753       && regno >= 0 && CR_REGNO_P (regno))
8754     return NO_REGS;
8755
8756   /* Otherwise, we need GENERAL_REGS.  */
8757   return GENERAL_REGS;
8758 }
8759 \f
8760 /* Given a comparison operation, return the bit number in CCR to test.  We
8761    know this is a valid comparison.
8762
8763    SCC_P is 1 if this is for an scc.  That means that %D will have been
8764    used instead of %C, so the bits will be in different places.
8765
8766    Return -1 if OP isn't a valid comparison for some reason.  */
8767
8768 int
8769 ccr_bit (rtx op, int scc_p)
8770 {
8771   enum rtx_code code = GET_CODE (op);
8772   enum machine_mode cc_mode;
8773   int cc_regnum;
8774   int base_bit;
8775   rtx reg;
8776
8777   if (!COMPARISON_P (op))
8778     return -1;
8779
8780   reg = XEXP (op, 0);
8781
8782   if (GET_CODE (reg) != REG
8783       || ! CR_REGNO_P (REGNO (reg)))
8784     abort ();
8785
8786   cc_mode = GET_MODE (reg);
8787   cc_regnum = REGNO (reg);
8788   base_bit = 4 * (cc_regnum - CR0_REGNO);
8789
8790   validate_condition_mode (code, cc_mode);
8791
8792   /* When generating a sCOND operation, only positive conditions are
8793      allowed.  */
8794   if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8795       && code != GTU && code != LTU)
8796     abort ();
8797
8798   switch (code)
8799     {
8800     case NE:
8801       if (TARGET_E500 && !TARGET_FPRS
8802           && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8803         return base_bit + 1;
8804       return scc_p ? base_bit + 3 : base_bit + 2;
8805     case EQ:
8806       if (TARGET_E500 && !TARGET_FPRS
8807           && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8808         return base_bit + 1;
8809       return base_bit + 2;
8810     case GT:  case GTU:  case UNLE:
8811       return base_bit + 1;
8812     case LT:  case LTU:  case UNGE:
8813       return base_bit;
8814     case ORDERED:  case UNORDERED:
8815       return base_bit + 3;
8816
8817     case GE:  case GEU:
8818       /* If scc, we will have done a cror to put the bit in the
8819          unordered position.  So test that bit.  For integer, this is ! LT
8820          unless this is an scc insn.  */
8821       return scc_p ? base_bit + 3 : base_bit;
8822
8823     case LE:  case LEU:
8824       return scc_p ? base_bit + 3 : base_bit + 1;
8825
8826     default:
8827       abort ();
8828     }
8829 }
8830 \f
8831 /* Return the GOT register.  */
8832
8833 struct rtx_def *
8834 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8835 {
8836   /* The second flow pass currently (June 1999) can't update
8837      regs_ever_live without disturbing other parts of the compiler, so
8838      update it here to make the prolog/epilogue code happy.  */
8839   if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8840     regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8841
8842   current_function_uses_pic_offset_table = 1;
8843
8844   return pic_offset_table_rtx;
8845 }
8846 \f
8847 /* Function to init struct machine_function.
8848    This will be called, via a pointer variable,
8849    from push_function_context.  */
8850
8851 static struct machine_function *
8852 rs6000_init_machine_status (void)
8853 {
8854   return ggc_alloc_cleared (sizeof (machine_function));
8855 }
8856 \f
8857 /* These macros test for integers and extract the low-order bits.  */
8858 #define INT_P(X)  \
8859 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)    \
8860  && GET_MODE (X) == VOIDmode)
8861
8862 #define INT_LOWPART(X) \
8863   (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8864
8865 int
8866 extract_MB (rtx op)
8867 {
8868   int i;
8869   unsigned long val = INT_LOWPART (op);
8870
8871   /* If the high bit is zero, the value is the first 1 bit we find
8872      from the left.  */
8873   if ((val & 0x80000000) == 0)
8874     {
8875       if ((val & 0xffffffff) == 0)
8876         abort ();
8877
8878       i = 1;
8879       while (((val <<= 1) & 0x80000000) == 0)
8880         ++i;
8881       return i;
8882     }
8883
8884   /* If the high bit is set and the low bit is not, or the mask is all
8885      1's, the value is zero.  */
8886   if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8887     return 0;
8888
8889   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
8890      from the right.  */
8891   i = 31;
8892   while (((val >>= 1) & 1) != 0)
8893     --i;
8894
8895   return i;
8896 }
8897
8898 int
8899 extract_ME (rtx op)
8900 {
8901   int i;
8902   unsigned long val = INT_LOWPART (op);
8903
8904   /* If the low bit is zero, the value is the first 1 bit we find from
8905      the right.  */
8906   if ((val & 1) == 0)
8907     {
8908       if ((val & 0xffffffff) == 0)
8909         abort ();
8910
8911       i = 30;
8912       while (((val >>= 1) & 1) == 0)
8913         --i;
8914
8915       return i;
8916     }
8917
8918   /* If the low bit is set and the high bit is not, or the mask is all
8919      1's, the value is 31.  */
8920   if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8921     return 31;
8922
8923   /* Otherwise we have a wrap-around mask.  Look for the first 0 bit
8924      from the left.  */
8925   i = 0;
8926   while (((val <<= 1) & 0x80000000) != 0)
8927     ++i;
8928
8929   return i;
8930 }
8931
8932 /* Locate some local-dynamic symbol still in use by this function
8933    so that we can print its name in some tls_ld pattern.  */
8934
8935 static const char *
8936 rs6000_get_some_local_dynamic_name (void)
8937 {
8938   rtx insn;
8939
8940   if (cfun->machine->some_ld_name)
8941     return cfun->machine->some_ld_name;
8942
8943   for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8944     if (INSN_P (insn)
8945         && for_each_rtx (&PATTERN (insn),
8946                          rs6000_get_some_local_dynamic_name_1, 0))
8947       return cfun->machine->some_ld_name;
8948
8949   abort ();
8950 }
8951
8952 /* Helper function for rs6000_get_some_local_dynamic_name.  */
8953
8954 static int
8955 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8956 {
8957   rtx x = *px;
8958
8959   if (GET_CODE (x) == SYMBOL_REF)
8960     {
8961       const char *str = XSTR (x, 0);
8962       if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8963         {
8964           cfun->machine->some_ld_name = str;
8965           return 1;
8966         }
8967     }
8968
8969   return 0;
8970 }
8971
8972 /* Print an operand.  Recognize special options, documented below.  */
8973
8974 #if TARGET_ELF
8975 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8976 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
8977 #else
8978 #define SMALL_DATA_RELOC "sda21"
8979 #define SMALL_DATA_REG 0
8980 #endif
8981
8982 void
8983 print_operand (FILE *file, rtx x, int code)
8984 {
8985   int i;
8986   HOST_WIDE_INT val;
8987   unsigned HOST_WIDE_INT uval;
8988
8989   switch (code)
8990     {
8991     case '.':
8992       /* Write out an instruction after the call which may be replaced
8993          with glue code by the loader.  This depends on the AIX version.  */
8994       asm_fprintf (file, RS6000_CALL_GLUE);
8995       return;
8996
8997       /* %a is output_address.  */
8998
8999     case 'A':
9000       /* If X is a constant integer whose low-order 5 bits are zero,
9001          write 'l'.  Otherwise, write 'r'.  This is a kludge to fix a bug
9002          in the AIX assembler where "sri" with a zero shift count
9003          writes a trash instruction.  */
9004       if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9005         putc ('l', file);
9006       else
9007         putc ('r', file);
9008       return;
9009
9010     case 'b':
9011       /* If constant, low-order 16 bits of constant, unsigned.
9012          Otherwise, write normally.  */
9013       if (INT_P (x))
9014         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9015       else
9016         print_operand (file, x, 0);
9017       return;
9018
9019     case 'B':
9020       /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9021          for 64-bit mask direction.  */
9022       putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
9023       return;
9024
9025       /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9026          output_operand.  */
9027
9028     case 'E':
9029       /* X is a CR register.  Print the number of the EQ bit of the CR */
9030       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9031         output_operand_lossage ("invalid %%E value");
9032       else
9033         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9034       return;
9035
9036     case 'f':
9037       /* X is a CR register.  Print the shift count needed to move it
9038          to the high-order four bits.  */
9039       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9040         output_operand_lossage ("invalid %%f value");
9041       else
9042         fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9043       return;
9044
9045     case 'F':
9046       /* Similar, but print the count for the rotate in the opposite
9047          direction.  */
9048       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9049         output_operand_lossage ("invalid %%F value");
9050       else
9051         fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9052       return;
9053
9054     case 'G':
9055       /* X is a constant integer.  If it is negative, print "m",
9056          otherwise print "z".  This is to make an aze or ame insn.  */
9057       if (GET_CODE (x) != CONST_INT)
9058         output_operand_lossage ("invalid %%G value");
9059       else if (INTVAL (x) >= 0)
9060         putc ('z', file);
9061       else
9062         putc ('m', file);
9063       return;
9064
9065     case 'h':
9066       /* If constant, output low-order five bits.  Otherwise, write
9067          normally.  */
9068       if (INT_P (x))
9069         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9070       else
9071         print_operand (file, x, 0);
9072       return;
9073
9074     case 'H':
9075       /* If constant, output low-order six bits.  Otherwise, write
9076          normally.  */
9077       if (INT_P (x))
9078         fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9079       else
9080         print_operand (file, x, 0);
9081       return;
9082
9083     case 'I':
9084       /* Print `i' if this is a constant, else nothing.  */
9085       if (INT_P (x))
9086         putc ('i', file);
9087       return;
9088
9089     case 'j':
9090       /* Write the bit number in CCR for jump.  */
9091       i = ccr_bit (x, 0);
9092       if (i == -1)
9093         output_operand_lossage ("invalid %%j code");
9094       else
9095         fprintf (file, "%d", i);
9096       return;
9097
9098     case 'J':
9099       /* Similar, but add one for shift count in rlinm for scc and pass
9100          scc flag to `ccr_bit'.  */
9101       i = ccr_bit (x, 1);
9102       if (i == -1)
9103         output_operand_lossage ("invalid %%J code");
9104       else
9105         /* If we want bit 31, write a shift count of zero, not 32.  */
9106         fprintf (file, "%d", i == 31 ? 0 : i + 1);
9107       return;
9108
9109     case 'k':
9110       /* X must be a constant.  Write the 1's complement of the
9111          constant.  */
9112       if (! INT_P (x))
9113         output_operand_lossage ("invalid %%k value");
9114       else
9115         fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9116       return;
9117
9118     case 'K':
9119       /* X must be a symbolic constant on ELF.  Write an
9120          expression suitable for an 'addi' that adds in the low 16
9121          bits of the MEM.  */
9122       if (GET_CODE (x) != CONST)
9123         {
9124           print_operand_address (file, x);
9125           fputs ("@l", file);
9126         }
9127       else
9128         {
9129           if (GET_CODE (XEXP (x, 0)) != PLUS
9130               || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9131                   && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9132               || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9133             output_operand_lossage ("invalid %%K value");
9134           print_operand_address (file, XEXP (XEXP (x, 0), 0));
9135           fputs ("@l", file);
9136           /* For GNU as, there must be a non-alphanumeric character
9137              between 'l' and the number.  The '-' is added by
9138              print_operand() already.  */
9139           if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9140             fputs ("+", file);
9141           print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9142         }
9143       return;
9144
9145       /* %l is output_asm_label.  */
9146
9147     case 'L':
9148       /* Write second word of DImode or DFmode reference.  Works on register
9149          or non-indexed memory only.  */
9150       if (GET_CODE (x) == REG)
9151         fprintf (file, "%s", reg_names[REGNO (x) + 1]);
9152       else if (GET_CODE (x) == MEM)
9153         {
9154           /* Handle possible auto-increment.  Since it is pre-increment and
9155              we have already done it, we can just use an offset of word.  */
9156           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9157               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9158             output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9159                                            UNITS_PER_WORD));
9160           else
9161             output_address (XEXP (adjust_address_nv (x, SImode,
9162                                                      UNITS_PER_WORD),
9163                                   0));
9164
9165           if (small_data_operand (x, GET_MODE (x)))
9166             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9167                      reg_names[SMALL_DATA_REG]);
9168         }
9169       return;
9170
9171     case 'm':
9172       /* MB value for a mask operand.  */
9173       if (! mask_operand (x, SImode))
9174         output_operand_lossage ("invalid %%m value");
9175
9176       fprintf (file, "%d", extract_MB (x));
9177       return;
9178
9179     case 'M':
9180       /* ME value for a mask operand.  */
9181       if (! mask_operand (x, SImode))
9182         output_operand_lossage ("invalid %%M value");
9183
9184       fprintf (file, "%d", extract_ME (x));
9185       return;
9186
9187       /* %n outputs the negative of its operand.  */
9188
9189     case 'N':
9190       /* Write the number of elements in the vector times 4.  */
9191       if (GET_CODE (x) != PARALLEL)
9192         output_operand_lossage ("invalid %%N value");
9193       else
9194         fprintf (file, "%d", XVECLEN (x, 0) * 4);
9195       return;
9196
9197     case 'O':
9198       /* Similar, but subtract 1 first.  */
9199       if (GET_CODE (x) != PARALLEL)
9200         output_operand_lossage ("invalid %%O value");
9201       else
9202         fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9203       return;
9204
9205     case 'p':
9206       /* X is a CONST_INT that is a power of two.  Output the logarithm.  */
9207       if (! INT_P (x)
9208           || INT_LOWPART (x) < 0
9209           || (i = exact_log2 (INT_LOWPART (x))) < 0)
9210         output_operand_lossage ("invalid %%p value");
9211       else
9212         fprintf (file, "%d", i);
9213       return;
9214
9215     case 'P':
9216       /* The operand must be an indirect memory reference.  The result
9217          is the register name.  */
9218       if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9219           || REGNO (XEXP (x, 0)) >= 32)
9220         output_operand_lossage ("invalid %%P value");
9221       else
9222         fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
9223       return;
9224
9225     case 'q':
9226       /* This outputs the logical code corresponding to a boolean
9227          expression.  The expression may have one or both operands
9228          negated (if one, only the first one).  For condition register
9229          logical operations, it will also treat the negated
9230          CR codes as NOTs, but not handle NOTs of them.  */
9231       {
9232         const char *const *t = 0;
9233         const char *s;
9234         enum rtx_code code = GET_CODE (x);
9235         static const char * const tbl[3][3] = {
9236           { "and", "andc", "nor" },
9237           { "or", "orc", "nand" },
9238           { "xor", "eqv", "xor" } };
9239
9240         if (code == AND)
9241           t = tbl[0];
9242         else if (code == IOR)
9243           t = tbl[1];
9244         else if (code == XOR)
9245           t = tbl[2];
9246         else
9247           output_operand_lossage ("invalid %%q value");
9248
9249         if (GET_CODE (XEXP (x, 0)) != NOT)
9250           s = t[0];
9251         else
9252           {
9253             if (GET_CODE (XEXP (x, 1)) == NOT)
9254               s = t[2];
9255             else
9256               s = t[1];
9257           }
9258
9259         fputs (s, file);
9260       }
9261       return;
9262
9263     case 'Q':
9264       if (TARGET_MFCRF)
9265         fputc (',', file);
9266         /* FALLTHRU */
9267       else
9268         return;
9269
9270     case 'R':
9271       /* X is a CR register.  Print the mask for `mtcrf'.  */
9272       if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9273         output_operand_lossage ("invalid %%R value");
9274       else
9275         fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9276       return;
9277
9278     case 's':
9279       /* Low 5 bits of 32 - value */
9280       if (! INT_P (x))
9281         output_operand_lossage ("invalid %%s value");
9282       else
9283         fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9284       return;
9285
9286     case 'S':
9287       /* PowerPC64 mask position.  All 0's is excluded.
9288          CONST_INT 32-bit mask is considered sign-extended so any
9289          transition must occur within the CONST_INT, not on the boundary.  */
9290       if (! mask64_operand (x, DImode))
9291         output_operand_lossage ("invalid %%S value");
9292
9293       uval = INT_LOWPART (x);
9294
9295       if (uval & 1)     /* Clear Left */
9296         {
9297 #if HOST_BITS_PER_WIDE_INT > 64
9298           uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9299 #endif
9300           i = 64;
9301         }
9302       else              /* Clear Right */
9303         {
9304           uval = ~uval;
9305 #if HOST_BITS_PER_WIDE_INT > 64
9306           uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9307 #endif
9308           i = 63;
9309         }
9310       while (uval != 0)
9311         --i, uval >>= 1;
9312       if (i < 0)
9313         abort ();
9314       fprintf (file, "%d", i);
9315       return;
9316
9317     case 't':
9318       /* Like 'J' but get to the OVERFLOW/UNORDERED bit.  */
9319       if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9320         abort ();
9321
9322       /* Bit 3 is OV bit.  */
9323       i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9324
9325       /* If we want bit 31, write a shift count of zero, not 32.  */
9326       fprintf (file, "%d", i == 31 ? 0 : i + 1);
9327       return;
9328
9329     case 'T':
9330       /* Print the symbolic name of a branch target register.  */
9331       if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9332                                   && REGNO (x) != COUNT_REGISTER_REGNUM))
9333         output_operand_lossage ("invalid %%T value");
9334       else if (REGNO (x) == LINK_REGISTER_REGNUM)
9335         fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9336       else
9337         fputs ("ctr", file);
9338       return;
9339
9340     case 'u':
9341       /* High-order 16 bits of constant for use in unsigned operand.  */
9342       if (! INT_P (x))
9343         output_operand_lossage ("invalid %%u value");
9344       else
9345         fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9346                  (INT_LOWPART (x) >> 16) & 0xffff);
9347       return;
9348
9349     case 'v':
9350       /* High-order 16 bits of constant for use in signed operand.  */
9351       if (! INT_P (x))
9352         output_operand_lossage ("invalid %%v value");
9353       else
9354         fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9355                  (INT_LOWPART (x) >> 16) & 0xffff);
9356       return;
9357
9358     case 'U':
9359       /* Print `u' if this has an auto-increment or auto-decrement.  */
9360       if (GET_CODE (x) == MEM
9361           && (GET_CODE (XEXP (x, 0)) == PRE_INC
9362               || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9363         putc ('u', file);
9364       return;
9365
9366     case 'V':
9367       /* Print the trap code for this operand.  */
9368       switch (GET_CODE (x))
9369         {
9370         case EQ:
9371           fputs ("eq", file);   /* 4 */
9372           break;
9373         case NE:
9374           fputs ("ne", file);   /* 24 */
9375           break;
9376         case LT:
9377           fputs ("lt", file);   /* 16 */
9378           break;
9379         case LE:
9380           fputs ("le", file);   /* 20 */
9381           break;
9382         case GT:
9383           fputs ("gt", file);   /* 8 */
9384           break;
9385         case GE:
9386           fputs ("ge", file);   /* 12 */
9387           break;
9388         case LTU:
9389           fputs ("llt", file);  /* 2 */
9390           break;
9391         case LEU:
9392           fputs ("lle", file);  /* 6 */
9393           break;
9394         case GTU:
9395           fputs ("lgt", file);  /* 1 */
9396           break;
9397         case GEU:
9398           fputs ("lge", file);  /* 5 */
9399           break;
9400         default:
9401           abort ();
9402         }
9403       break;
9404
9405     case 'w':
9406       /* If constant, low-order 16 bits of constant, signed.  Otherwise, write
9407          normally.  */
9408       if (INT_P (x))
9409         fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9410                  ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9411       else
9412         print_operand (file, x, 0);
9413       return;
9414
9415     case 'W':
9416       /* MB value for a PowerPC64 rldic operand.  */
9417       val = (GET_CODE (x) == CONST_INT
9418              ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9419
9420       if (val < 0)
9421         i = -1;
9422       else
9423         for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9424           if ((val <<= 1) < 0)
9425             break;
9426
9427 #if HOST_BITS_PER_WIDE_INT == 32
9428       if (GET_CODE (x) == CONST_INT && i >= 0)
9429         i += 32;  /* zero-extend high-part was all 0's */
9430       else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9431         {
9432           val = CONST_DOUBLE_LOW (x);
9433
9434           if (val == 0)
9435             abort ();
9436           else if (val < 0)
9437             --i;
9438           else
9439             for ( ; i < 64; i++)
9440               if ((val <<= 1) < 0)
9441                 break;
9442         }
9443 #endif
9444
9445       fprintf (file, "%d", i + 1);
9446       return;
9447
9448     case 'X':
9449       if (GET_CODE (x) == MEM
9450           && legitimate_indexed_address_p (XEXP (x, 0), 0))
9451         putc ('x', file);
9452       return;
9453
9454     case 'Y':
9455       /* Like 'L', for third word of TImode  */
9456       if (GET_CODE (x) == REG)
9457         fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9458       else if (GET_CODE (x) == MEM)
9459         {
9460           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9461               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9462             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9463           else
9464             output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9465           if (small_data_operand (x, GET_MODE (x)))
9466             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9467                      reg_names[SMALL_DATA_REG]);
9468         }
9469       return;
9470
9471     case 'z':
9472       /* X is a SYMBOL_REF.  Write out the name preceded by a
9473          period and without any trailing data in brackets.  Used for function
9474          names.  If we are configured for System V (or the embedded ABI) on
9475          the PowerPC, do not emit the period, since those systems do not use
9476          TOCs and the like.  */
9477       if (GET_CODE (x) != SYMBOL_REF)
9478         abort ();
9479
9480       if (XSTR (x, 0)[0] != '.')
9481         {
9482           switch (DEFAULT_ABI)
9483             {
9484             default:
9485               abort ();
9486
9487             case ABI_AIX:
9488               putc ('.', file);
9489               break;
9490
9491             case ABI_V4:
9492             case ABI_DARWIN:
9493               break;
9494             }
9495         }
9496       if (TARGET_AIX)
9497         RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9498       else
9499         assemble_name (file, XSTR (x, 0));
9500       return;
9501
9502     case 'Z':
9503       /* Like 'L', for last word of TImode.  */
9504       if (GET_CODE (x) == REG)
9505         fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9506       else if (GET_CODE (x) == MEM)
9507         {
9508           if (GET_CODE (XEXP (x, 0)) == PRE_INC
9509               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9510             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9511           else
9512             output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9513           if (small_data_operand (x, GET_MODE (x)))
9514             fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9515                      reg_names[SMALL_DATA_REG]);
9516         }
9517       return;
9518
9519       /* Print AltiVec or SPE memory operand.  */
9520     case 'y':
9521       {
9522         rtx tmp;
9523
9524         if (GET_CODE (x) != MEM)
9525           abort ();
9526
9527         tmp = XEXP (x, 0);
9528
9529         if (TARGET_E500)
9530           {
9531             /* Handle [reg].  */
9532             if (GET_CODE (tmp) == REG)
9533               {
9534                 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9535                 break;
9536               }
9537             /* Handle [reg+UIMM].  */
9538             else if (GET_CODE (tmp) == PLUS &&
9539                      GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9540               {
9541                 int x;
9542
9543                 if (GET_CODE (XEXP (tmp, 0)) != REG)
9544                   abort ();
9545
9546                 x = INTVAL (XEXP (tmp, 1));
9547                 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9548                 break;
9549               }
9550
9551             /* Fall through.  Must be [reg+reg].  */
9552           }
9553         if (GET_CODE (tmp) == REG)
9554           fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9555         else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9556           {
9557             if (REGNO (XEXP (tmp, 0)) == 0)
9558               fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9559                        reg_names[ REGNO (XEXP (tmp, 0)) ]);
9560             else
9561               fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9562                        reg_names[ REGNO (XEXP (tmp, 1)) ]);
9563           }
9564         else
9565           abort ();
9566         break;
9567       }
9568
9569     case 0:
9570       if (GET_CODE (x) == REG)
9571         fprintf (file, "%s", reg_names[REGNO (x)]);
9572       else if (GET_CODE (x) == MEM)
9573         {
9574           /* We need to handle PRE_INC and PRE_DEC here, since we need to
9575              know the width from the mode.  */
9576           if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9577             fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9578                      reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9579           else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9580             fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9581                      reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9582           else
9583             output_address (XEXP (x, 0));
9584         }
9585       else
9586         output_addr_const (file, x);
9587       return;
9588
9589     case '&':
9590       assemble_name (file, rs6000_get_some_local_dynamic_name ());
9591       return;
9592
9593     default:
9594       output_operand_lossage ("invalid %%xn code");
9595     }
9596 }
9597 \f
9598 /* Print the address of an operand.  */
9599
9600 void
9601 print_operand_address (FILE *file, rtx x)
9602 {
9603   if (GET_CODE (x) == REG)
9604     fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9605   else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9606            || GET_CODE (x) == LABEL_REF)
9607     {
9608       output_addr_const (file, x);
9609       if (small_data_operand (x, GET_MODE (x)))
9610         fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9611                  reg_names[SMALL_DATA_REG]);
9612       else if (TARGET_TOC)
9613         abort ();
9614     }
9615   else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9616     {
9617       if (REGNO (XEXP (x, 0)) == 0)
9618         fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9619                  reg_names[ REGNO (XEXP (x, 0)) ]);
9620       else
9621         fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9622                  reg_names[ REGNO (XEXP (x, 1)) ]);
9623     }
9624   else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9625     fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9626              INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9627 #if TARGET_ELF
9628   else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9629            && CONSTANT_P (XEXP (x, 1)))
9630     {
9631       output_addr_const (file, XEXP (x, 1));
9632       fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9633     }
9634 #endif
9635 #if TARGET_MACHO
9636   else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9637            && CONSTANT_P (XEXP (x, 1)))
9638     {
9639       fprintf (file, "lo16(");
9640       output_addr_const (file, XEXP (x, 1));
9641       fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9642     }
9643 #endif
9644   else if (legitimate_constant_pool_address_p (x))
9645     {
9646       if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9647         {
9648           rtx contains_minus = XEXP (x, 1);
9649           rtx minus, symref;
9650           const char *name;
9651
9652           /* Find the (minus (sym) (toc)) buried in X, and temporarily
9653              turn it into (sym) for output_addr_const.  */
9654           while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9655             contains_minus = XEXP (contains_minus, 0);
9656
9657           minus = XEXP (contains_minus, 0);
9658           symref = XEXP (minus, 0);
9659           XEXP (contains_minus, 0) = symref;
9660           if (TARGET_ELF)
9661             {
9662               char *newname;
9663
9664               name = XSTR (symref, 0);
9665               newname = alloca (strlen (name) + sizeof ("@toc"));
9666               strcpy (newname, name);
9667               strcat (newname, "@toc");
9668               XSTR (symref, 0) = newname;
9669             }
9670           output_addr_const (file, XEXP (x, 1));
9671           if (TARGET_ELF)
9672             XSTR (symref, 0) = name;
9673           XEXP (contains_minus, 0) = minus;
9674         }
9675       else
9676         output_addr_const (file, XEXP (x, 1));
9677
9678       fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9679     }
9680   else
9681     abort ();
9682 }
9683 \f
9684 /* Target hook for assembling integer objects.  The PowerPC version has
9685    to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9686    is defined.  It also needs to handle DI-mode objects on 64-bit
9687    targets.  */
9688
9689 static bool
9690 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9691 {
9692 #ifdef RELOCATABLE_NEEDS_FIXUP
9693   /* Special handling for SI values.  */
9694   if (size == 4 && aligned_p)
9695     {
9696       extern int in_toc_section (void);
9697       static int recurse = 0;
9698
9699       /* For -mrelocatable, we mark all addresses that need to be fixed up
9700          in the .fixup section.  */
9701       if (TARGET_RELOCATABLE
9702           && !in_toc_section ()
9703           && !in_text_section ()
9704           && !in_unlikely_text_section ()
9705           && !recurse
9706           && GET_CODE (x) != CONST_INT
9707           && GET_CODE (x) != CONST_DOUBLE
9708           && CONSTANT_P (x))
9709         {
9710           char buf[256];
9711
9712           recurse = 1;
9713           ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9714           fixuplabelno++;
9715           ASM_OUTPUT_LABEL (asm_out_file, buf);
9716           fprintf (asm_out_file, "\t.long\t(");
9717           output_addr_const (asm_out_file, x);
9718           fprintf (asm_out_file, ")@fixup\n");
9719           fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9720           ASM_OUTPUT_ALIGN (asm_out_file, 2);
9721           fprintf (asm_out_file, "\t.long\t");
9722           assemble_name (asm_out_file, buf);
9723           fprintf (asm_out_file, "\n\t.previous\n");
9724           recurse = 0;
9725           return true;
9726         }
9727       /* Remove initial .'s to turn a -mcall-aixdesc function
9728          address into the address of the descriptor, not the function
9729          itself.  */
9730       else if (GET_CODE (x) == SYMBOL_REF
9731                && XSTR (x, 0)[0] == '.'
9732                && DEFAULT_ABI == ABI_AIX)
9733         {
9734           const char *name = XSTR (x, 0);
9735           while (*name == '.')
9736             name++;
9737
9738           fprintf (asm_out_file, "\t.long\t%s\n", name);
9739           return true;
9740         }
9741     }
9742 #endif /* RELOCATABLE_NEEDS_FIXUP */
9743   return default_assemble_integer (x, size, aligned_p);
9744 }
9745
9746 #ifdef HAVE_GAS_HIDDEN
9747 /* Emit an assembler directive to set symbol visibility for DECL to
9748    VISIBILITY_TYPE.  */
9749
9750 static void
9751 rs6000_assemble_visibility (tree decl, int vis)
9752 {
9753   /* Functions need to have their entry point symbol visibility set as
9754      well as their descriptor symbol visibility.  */
9755   if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9756     {
9757       static const char * const visibility_types[] = {
9758         NULL, "internal", "hidden", "protected"
9759       };
9760
9761       const char *name, *type;
9762
9763       name = ((* targetm.strip_name_encoding)
9764               (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9765       type = visibility_types[vis];
9766
9767       fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9768       fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9769     }
9770   else
9771     default_assemble_visibility (decl, vis);
9772 }
9773 #endif
9774 \f
9775 enum rtx_code
9776 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9777 {
9778   /* Reversal of FP compares takes care -- an ordered compare
9779      becomes an unordered compare and vice versa.  */
9780   if (mode == CCFPmode
9781       && (!flag_finite_math_only
9782           || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9783           || code == UNEQ || code == LTGT))
9784     return reverse_condition_maybe_unordered (code);
9785   else
9786     return reverse_condition (code);
9787 }
9788
9789 /* Generate a compare for CODE.  Return a brand-new rtx that
9790    represents the result of the compare.  */
9791
9792 static rtx
9793 rs6000_generate_compare (enum rtx_code code)
9794 {
9795   enum machine_mode comp_mode;
9796   rtx compare_result;
9797
9798   if (rs6000_compare_fp_p)
9799     comp_mode = CCFPmode;
9800   else if (code == GTU || code == LTU
9801           || code == GEU || code == LEU)
9802     comp_mode = CCUNSmode;
9803   else
9804     comp_mode = CCmode;
9805
9806   /* First, the compare.  */
9807   compare_result = gen_reg_rtx (comp_mode);
9808
9809   /* SPE FP compare instructions on the GPRs.  Yuck!  */
9810   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9811       && rs6000_compare_fp_p)
9812     {
9813       rtx cmp, or1, or2, or_result, compare_result2;
9814
9815       switch (code)
9816         {
9817         case EQ:
9818         case UNEQ:
9819         case NE:
9820         case LTGT:
9821           cmp = flag_finite_math_only
9822             ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9823                                rs6000_compare_op1)
9824             : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9825                                rs6000_compare_op1);
9826           break;
9827         case GT:
9828         case GTU:
9829         case UNGT:
9830         case UNGE:
9831         case GE:
9832         case GEU:
9833           cmp = flag_finite_math_only
9834             ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9835                                rs6000_compare_op1)
9836             : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9837                                rs6000_compare_op1);
9838           break;
9839         case LT:
9840         case LTU:
9841         case UNLT:
9842         case UNLE:
9843         case LE:
9844         case LEU:
9845           cmp = flag_finite_math_only
9846             ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9847                                rs6000_compare_op1)
9848             : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9849                                rs6000_compare_op1);
9850           break;
9851         default:
9852           abort ();
9853         }
9854
9855       /* Synthesize LE and GE from LT/GT || EQ.  */
9856       if (code == LE || code == GE || code == LEU || code == GEU)
9857         {
9858           /* Synthesize GE/LE frome GT/LT || EQ.  */
9859
9860           emit_insn (cmp);
9861
9862           switch (code)
9863             {
9864             case LE: code = LT; break;
9865             case GE: code = GT; break;
9866             case LEU: code = LT; break;
9867             case GEU: code = GT; break;
9868             default: abort ();
9869             }
9870
9871           or1 = gen_reg_rtx (SImode);
9872           or2 = gen_reg_rtx (SImode);
9873           or_result = gen_reg_rtx (CCEQmode);
9874           compare_result2 = gen_reg_rtx (CCFPmode);
9875
9876           /* Do the EQ.  */
9877           cmp = flag_finite_math_only
9878             ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9879                                rs6000_compare_op1)
9880             : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9881                                rs6000_compare_op1);
9882           emit_insn (cmp);
9883
9884           /* The MC8540 FP compare instructions set the CR bits
9885              differently than other PPC compare instructions.  For
9886              that matter, there is no generic test instruction, but a
9887              testgt, testlt, and testeq.  For a true condition, bit 2
9888              is set (x1xx) in the CR.  Following the traditional CR
9889              values:
9890
9891              LT    GT    EQ    OV
9892              bit3  bit2  bit1  bit0
9893
9894              ... bit 2 would be a GT CR alias, so later on we
9895              look in the GT bits for the branch instructions.
9896              However, we must be careful to emit correct RTL in
9897              the meantime, so optimizations don't get confused.  */
9898
9899           or1 = gen_rtx_NE (SImode, compare_result, const0_rtx);
9900           or2 = gen_rtx_NE (SImode, compare_result2, const0_rtx);
9901
9902           /* OR them together.  */
9903           cmp = gen_rtx_SET (VOIDmode, or_result,
9904                              gen_rtx_COMPARE (CCEQmode,
9905                                               gen_rtx_IOR (SImode, or1, or2),
9906                                               const_true_rtx));
9907           compare_result = or_result;
9908           code = EQ;
9909         }
9910       else
9911         {
9912           /* We only care about 1 bit (x1xx), so map everything to NE to
9913              maintain rtl sanity.  We'll get to the right bit (x1xx) at
9914              code output time.  */
9915           if (code == NE || code == LTGT)
9916             /* Do the inverse here because we have no cmpne
9917                instruction.  We use the cmpeq instruction and expect
9918                to get a 0 instead.  */
9919             code = EQ;
9920           else
9921             code = NE;
9922         }
9923
9924       emit_insn (cmp);
9925     }
9926   else
9927     emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9928                             gen_rtx_COMPARE (comp_mode,
9929                                              rs6000_compare_op0,
9930                                              rs6000_compare_op1)));
9931
9932   /* Some kinds of FP comparisons need an OR operation;
9933      under flag_finite_math_only we don't bother.  */
9934   if (rs6000_compare_fp_p
9935       && ! flag_finite_math_only
9936       && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9937       && (code == LE || code == GE
9938           || code == UNEQ || code == LTGT
9939           || code == UNGT || code == UNLT))
9940     {
9941       enum rtx_code or1, or2;
9942       rtx or1_rtx, or2_rtx, compare2_rtx;
9943       rtx or_result = gen_reg_rtx (CCEQmode);
9944
9945       switch (code)
9946         {
9947         case LE: or1 = LT;  or2 = EQ;  break;
9948         case GE: or1 = GT;  or2 = EQ;  break;
9949         case UNEQ: or1 = UNORDERED;  or2 = EQ;  break;
9950         case LTGT: or1 = LT;  or2 = GT;  break;
9951         case UNGT: or1 = UNORDERED;  or2 = GT;  break;
9952         case UNLT: or1 = UNORDERED;  or2 = LT;  break;
9953         default:  abort ();
9954         }
9955       validate_condition_mode (or1, comp_mode);
9956       validate_condition_mode (or2, comp_mode);
9957       or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
9958       or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
9959       compare2_rtx = gen_rtx_COMPARE (CCEQmode,
9960                                       gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
9961                                       const_true_rtx);
9962       emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
9963
9964       compare_result = or_result;
9965       code = EQ;
9966     }
9967
9968   validate_condition_mode (code, GET_MODE (compare_result));
9969
9970   return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
9971 }
9972
9973
9974 /* Emit the RTL for an sCOND pattern.  */
9975
9976 void
9977 rs6000_emit_sCOND (enum rtx_code code, rtx result)
9978 {
9979   rtx condition_rtx;
9980   enum machine_mode op_mode;
9981   enum rtx_code cond_code;
9982
9983   condition_rtx = rs6000_generate_compare (code);
9984   cond_code = GET_CODE (condition_rtx);
9985
9986   if (cond_code == NE
9987       || cond_code == GE || cond_code == LE
9988       || cond_code == GEU || cond_code == LEU
9989       || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
9990     {
9991       rtx not_result = gen_reg_rtx (CCEQmode);
9992       rtx not_op, rev_cond_rtx;
9993       enum machine_mode cc_mode;
9994
9995       cc_mode = GET_MODE (XEXP (condition_rtx, 0));
9996
9997       rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
9998                                      SImode, XEXP (condition_rtx, 0), const0_rtx);
9999       not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10000       emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10001       condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10002     }
10003
10004   op_mode = GET_MODE (rs6000_compare_op0);
10005   if (op_mode == VOIDmode)
10006     op_mode = GET_MODE (rs6000_compare_op1);
10007
10008   if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10009     {
10010       PUT_MODE (condition_rtx, DImode);
10011       convert_move (result, condition_rtx, 0);
10012     }
10013   else
10014     {
10015       PUT_MODE (condition_rtx, SImode);
10016       emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10017     }
10018 }
10019
10020 /* Emit a branch of kind CODE to location LOC.  */
10021
10022 void
10023 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10024 {
10025   rtx condition_rtx, loc_ref;
10026
10027   condition_rtx = rs6000_generate_compare (code);
10028   loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10029   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10030                                gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10031                                                      loc_ref, pc_rtx)));
10032 }
10033
10034 /* Return the string to output a conditional branch to LABEL, which is
10035    the operand number of the label, or -1 if the branch is really a
10036    conditional return.
10037
10038    OP is the conditional expression.  XEXP (OP, 0) is assumed to be a
10039    condition code register and its mode specifies what kind of
10040    comparison we made.
10041
10042    REVERSED is nonzero if we should reverse the sense of the comparison.
10043
10044    INSN is the insn.  */
10045
10046 char *
10047 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10048 {
10049   static char string[64];
10050   enum rtx_code code = GET_CODE (op);
10051   rtx cc_reg = XEXP (op, 0);
10052   enum machine_mode mode = GET_MODE (cc_reg);
10053   int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10054   int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10055   int really_reversed = reversed ^ need_longbranch;
10056   char *s = string;
10057   const char *ccode;
10058   const char *pred;
10059   rtx note;
10060
10061   validate_condition_mode (code, mode);
10062
10063   /* Work out which way this really branches.  We could use
10064      reverse_condition_maybe_unordered here always but this
10065      makes the resulting assembler clearer.  */
10066   if (really_reversed)
10067     {
10068       /* Reversal of FP compares takes care -- an ordered compare
10069          becomes an unordered compare and vice versa.  */
10070       if (mode == CCFPmode)
10071         code = reverse_condition_maybe_unordered (code);
10072       else
10073         code = reverse_condition (code);
10074     }
10075
10076   if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10077     {
10078       /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10079          to the GT bit.  */
10080       if (code == EQ)
10081         /* Opposite of GT.  */
10082         code = UNLE;
10083       else if (code == NE)
10084         code = GT;
10085       else
10086         abort ();
10087     }
10088
10089   switch (code)
10090     {
10091       /* Not all of these are actually distinct opcodes, but
10092          we distinguish them for clarity of the resulting assembler.  */
10093     case NE: case LTGT:
10094       ccode = "ne"; break;
10095     case EQ: case UNEQ:
10096       ccode = "eq"; break;
10097     case GE: case GEU:
10098       ccode = "ge"; break;
10099     case GT: case GTU: case UNGT:
10100       ccode = "gt"; break;
10101     case LE: case LEU:
10102       ccode = "le"; break;
10103     case LT: case LTU: case UNLT:
10104       ccode = "lt"; break;
10105     case UNORDERED: ccode = "un"; break;
10106     case ORDERED: ccode = "nu"; break;
10107     case UNGE: ccode = "nl"; break;
10108     case UNLE: ccode = "ng"; break;
10109     default:
10110       abort ();
10111     }
10112
10113   /* Maybe we have a guess as to how likely the branch is.
10114      The old mnemonics don't have a way to specify this information.  */
10115   pred = "";
10116   note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10117   if (note != NULL_RTX)
10118     {
10119       /* PROB is the difference from 50%.  */
10120       int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10121
10122       /* Only hint for highly probable/improbable branches on newer
10123          cpus as static prediction overrides processor dynamic
10124          prediction.  For older cpus we may as well always hint, but
10125          assume not taken for branches that are very close to 50% as a
10126          mispredicted taken branch is more expensive than a
10127          mispredicted not-taken branch.  */
10128       if (rs6000_always_hint
10129           || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10130         {
10131           if (abs (prob) > REG_BR_PROB_BASE / 20
10132               && ((prob > 0) ^ need_longbranch))
10133               pred = "+";
10134           else
10135             pred = "-";
10136         }
10137     }
10138
10139   if (label == NULL)
10140     s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10141   else
10142     s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10143
10144   /* We need to escape any '%' characters in the reg_names string.
10145      Assume they'd only be the first character....  */
10146   if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10147     *s++ = '%';
10148   s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10149
10150   if (label != NULL)
10151     {
10152       /* If the branch distance was too far, we may have to use an
10153          unconditional branch to go the distance.  */
10154       if (need_longbranch)
10155         s += sprintf (s, ",$+8\n\tb %s", label);
10156       else
10157         s += sprintf (s, ",%s", label);
10158     }
10159
10160   return string;
10161 }
10162
10163 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10164    operands of the last comparison is nonzero/true, FALSE_COND if it
10165    is zero/false.  Return 0 if the hardware has no such operation.  */
10166
10167 int
10168 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10169 {
10170   enum rtx_code code = GET_CODE (op);
10171   rtx op0 = rs6000_compare_op0;
10172   rtx op1 = rs6000_compare_op1;
10173   REAL_VALUE_TYPE c1;
10174   enum machine_mode compare_mode = GET_MODE (op0);
10175   enum machine_mode result_mode = GET_MODE (dest);
10176   rtx temp;
10177
10178   /* These modes should always match.  */
10179   if (GET_MODE (op1) != compare_mode
10180       /* In the isel case however, we can use a compare immediate, so
10181          op1 may be a small constant.  */
10182       && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10183     return 0;
10184   if (GET_MODE (true_cond) != result_mode)
10185     return 0;
10186   if (GET_MODE (false_cond) != result_mode)
10187     return 0;
10188
10189   /* First, work out if the hardware can do this at all, or
10190      if it's too slow....  */
10191   if (! rs6000_compare_fp_p)
10192     {
10193       if (TARGET_ISEL)
10194         return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10195       return 0;
10196     }
10197   else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10198            && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10199     return 0;
10200
10201   /* Eliminate half of the comparisons by switching operands, this
10202      makes the remaining code simpler.  */
10203   if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10204       || code == LTGT || code == LT || code == UNLE)
10205     {
10206       code = reverse_condition_maybe_unordered (code);
10207       temp = true_cond;
10208       true_cond = false_cond;
10209       false_cond = temp;
10210     }
10211
10212   /* UNEQ and LTGT take four instructions for a comparison with zero,
10213      it'll probably be faster to use a branch here too.  */
10214   if (code == UNEQ && HONOR_NANS (compare_mode))
10215     return 0;
10216
10217   if (GET_CODE (op1) == CONST_DOUBLE)
10218     REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10219
10220   /* We're going to try to implement comparisons by performing
10221      a subtract, then comparing against zero.  Unfortunately,
10222      Inf - Inf is NaN which is not zero, and so if we don't
10223      know that the operand is finite and the comparison
10224      would treat EQ different to UNORDERED, we can't do it.  */
10225   if (HONOR_INFINITIES (compare_mode)
10226       && code != GT && code != UNGE
10227       && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10228       /* Constructs of the form (a OP b ? a : b) are safe.  */
10229       && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10230           || (! rtx_equal_p (op0, true_cond)
10231               && ! rtx_equal_p (op1, true_cond))))
10232     return 0;
10233   /* At this point we know we can use fsel.  */
10234
10235   /* Reduce the comparison to a comparison against zero.  */
10236   temp = gen_reg_rtx (compare_mode);
10237   emit_insn (gen_rtx_SET (VOIDmode, temp,
10238                           gen_rtx_MINUS (compare_mode, op0, op1)));
10239   op0 = temp;
10240   op1 = CONST0_RTX (compare_mode);
10241
10242   /* If we don't care about NaNs we can reduce some of the comparisons
10243      down to faster ones.  */
10244   if (! HONOR_NANS (compare_mode))
10245     switch (code)
10246       {
10247       case GT:
10248         code = LE;
10249         temp = true_cond;
10250         true_cond = false_cond;
10251         false_cond = temp;
10252         break;
10253       case UNGE:
10254         code = GE;
10255         break;
10256       case UNEQ:
10257         code = EQ;
10258         break;
10259       default:
10260         break;
10261       }
10262
10263   /* Now, reduce everything down to a GE.  */
10264   switch (code)
10265     {
10266     case GE:
10267       break;
10268
10269     case LE:
10270       temp = gen_reg_rtx (compare_mode);
10271       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10272       op0 = temp;
10273       break;
10274
10275     case ORDERED:
10276       temp = gen_reg_rtx (compare_mode);
10277       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10278       op0 = temp;
10279       break;
10280
10281     case EQ:
10282       temp = gen_reg_rtx (compare_mode);
10283       emit_insn (gen_rtx_SET (VOIDmode, temp,
10284                               gen_rtx_NEG (compare_mode,
10285                                            gen_rtx_ABS (compare_mode, op0))));
10286       op0 = temp;
10287       break;
10288
10289     case UNGE:
10290       /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10291       temp = gen_reg_rtx (result_mode);
10292       emit_insn (gen_rtx_SET (VOIDmode, temp,
10293                               gen_rtx_IF_THEN_ELSE (result_mode,
10294                                                     gen_rtx_GE (VOIDmode,
10295                                                                 op0, op1),
10296                                                     true_cond, false_cond)));
10297       false_cond = true_cond;
10298       true_cond = temp;
10299
10300       temp = gen_reg_rtx (compare_mode);
10301       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10302       op0 = temp;
10303       break;
10304
10305     case GT:
10306       /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10307       temp = gen_reg_rtx (result_mode);
10308       emit_insn (gen_rtx_SET (VOIDmode, temp,
10309                               gen_rtx_IF_THEN_ELSE (result_mode,
10310                                                     gen_rtx_GE (VOIDmode,
10311                                                                 op0, op1),
10312                                                     true_cond, false_cond)));
10313       true_cond = false_cond;
10314       false_cond = temp;
10315
10316       temp = gen_reg_rtx (compare_mode);
10317       emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10318       op0 = temp;
10319       break;
10320
10321     default:
10322       abort ();
10323     }
10324
10325   emit_insn (gen_rtx_SET (VOIDmode, dest,
10326                           gen_rtx_IF_THEN_ELSE (result_mode,
10327                                                 gen_rtx_GE (VOIDmode,
10328                                                             op0, op1),
10329                                                 true_cond, false_cond)));
10330   return 1;
10331 }
10332
10333 /* Same as above, but for ints (isel).  */
10334
10335 static int
10336 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10337 {
10338   rtx condition_rtx, cr;
10339
10340   /* All isel implementations thus far are 32-bits.  */
10341   if (GET_MODE (rs6000_compare_op0) != SImode)
10342     return 0;
10343
10344   /* We still have to do the compare, because isel doesn't do a
10345      compare, it just looks at the CRx bits set by a previous compare
10346      instruction.  */
10347   condition_rtx = rs6000_generate_compare (GET_CODE (op));
10348   cr = XEXP (condition_rtx, 0);
10349
10350   if (GET_MODE (cr) == CCmode)
10351     emit_insn (gen_isel_signed (dest, condition_rtx,
10352                                 true_cond, false_cond, cr));
10353   else
10354     emit_insn (gen_isel_unsigned (dest, condition_rtx,
10355                                   true_cond, false_cond, cr));
10356
10357   return 1;
10358 }
10359
10360 const char *
10361 output_isel (rtx *operands)
10362 {
10363   enum rtx_code code;
10364
10365   code = GET_CODE (operands[1]);
10366   if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10367     {
10368       PUT_CODE (operands[1], reverse_condition (code));
10369       return "isel %0,%3,%2,%j1";
10370     }
10371   else
10372     return "isel %0,%2,%3,%j1";
10373 }
10374
10375 void
10376 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10377 {
10378   enum machine_mode mode = GET_MODE (op0);
10379   enum rtx_code c;
10380   rtx target;
10381
10382   if (code == SMAX || code == SMIN)
10383     c = GE;
10384   else
10385     c = GEU;
10386
10387   if (code == SMAX || code == UMAX)
10388     target = emit_conditional_move (dest, c, op0, op1, mode,
10389                                     op0, op1, mode, 0);
10390   else
10391     target = emit_conditional_move (dest, c, op0, op1, mode,
10392                                     op1, op0, mode, 0);
10393   if (target == NULL_RTX)
10394     abort ();
10395   if (target != dest)
10396     emit_move_insn (dest, target);
10397 }
10398
10399 /* Emit instructions to move SRC to DST.  Called by splitters for
10400    multi-register moves.  It will emit at most one instruction for
10401    each register that is accessed; that is, it won't emit li/lis pairs
10402    (or equivalent for 64-bit code).  One of SRC or DST must be a hard
10403    register.  */
10404
10405 void
10406 rs6000_split_multireg_move (rtx dst, rtx src)
10407 {
10408   /* The register number of the first register being moved.  */
10409   int reg;
10410   /* The mode that is to be moved.  */
10411   enum machine_mode mode;
10412   /* The mode that the move is being done in, and its size.  */
10413   enum machine_mode reg_mode;
10414   int reg_mode_size;
10415   /* The number of registers that will be moved.  */
10416   int nregs;
10417
10418   reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10419   mode = GET_MODE (dst);
10420   nregs = HARD_REGNO_NREGS (reg, mode);
10421   if (FP_REGNO_P (reg))
10422     reg_mode = DFmode;
10423   else if (ALTIVEC_REGNO_P (reg))
10424     reg_mode = V16QImode;
10425   else
10426     reg_mode = word_mode;
10427   reg_mode_size = GET_MODE_SIZE (reg_mode);
10428
10429   if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10430     abort ();
10431
10432   if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10433     {
10434       /* Move register range backwards, if we might have destructive
10435          overlap.  */
10436       int i;
10437       for (i = nregs - 1; i >= 0; i--)
10438         emit_insn (gen_rtx_SET (VOIDmode,
10439                                 simplify_gen_subreg (reg_mode, dst, mode,
10440                                                      i * reg_mode_size),
10441                                 simplify_gen_subreg (reg_mode, src, mode,
10442                                                      i * reg_mode_size)));
10443     }
10444   else
10445     {
10446       int i;
10447       int j = -1;
10448       bool used_update = false;
10449
10450       if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10451         {
10452           rtx breg;
10453
10454           if (GET_CODE (XEXP (src, 0)) == PRE_INC
10455               || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10456             {
10457               rtx delta_rtx;
10458               breg = XEXP (XEXP (src, 0), 0);
10459               delta_rtx =  GET_CODE (XEXP (src, 0)) == PRE_INC
10460                   ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10461                   : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10462               emit_insn (TARGET_32BIT
10463                          ? gen_addsi3 (breg, breg, delta_rtx)
10464                          : gen_adddi3 (breg, breg, delta_rtx));
10465               src = gen_rtx_MEM (mode, breg);
10466             }
10467
10468           /* We have now address involving an base register only.
10469              If we use one of the registers to address memory,
10470              we have change that register last.  */
10471
10472           breg = (GET_CODE (XEXP (src, 0)) == PLUS
10473                   ? XEXP (XEXP (src, 0), 0)
10474                   : XEXP (src, 0));
10475
10476           if (!REG_P (breg))
10477               abort();
10478
10479           if (REGNO (breg) >= REGNO (dst)
10480               && REGNO (breg) < REGNO (dst) + nregs)
10481             j = REGNO (breg) - REGNO (dst);
10482         }
10483
10484       if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10485         {
10486           rtx breg;
10487
10488           if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10489               || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10490             {
10491               rtx delta_rtx;
10492               breg = XEXP (XEXP (dst, 0), 0);
10493               delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10494                 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10495                 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10496
10497               /* We have to update the breg before doing the store.
10498                  Use store with update, if available.  */
10499
10500               if (TARGET_UPDATE)
10501                 {
10502                   rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10503                   emit_insn (TARGET_32BIT
10504                              ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10505                              : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10506                   used_update = true;
10507                 }
10508               else
10509                 emit_insn (TARGET_32BIT
10510                            ? gen_addsi3 (breg, breg, delta_rtx)
10511                            : gen_adddi3 (breg, breg, delta_rtx));
10512               dst = gen_rtx_MEM (mode, breg);
10513             }
10514         }
10515
10516       for (i = 0; i < nregs; i++)
10517         {
10518           /* Calculate index to next subword.  */
10519           ++j;
10520           if (j == nregs)
10521             j = 0;
10522
10523           /* If compiler already emited move of first word by
10524              store with update, no need to do anything.  */
10525           if (j == 0 && used_update)
10526             continue;
10527
10528           emit_insn (gen_rtx_SET (VOIDmode,
10529                                   simplify_gen_subreg (reg_mode, dst, mode,
10530                                                        j * reg_mode_size),
10531                                   simplify_gen_subreg (reg_mode, src, mode,
10532                                                        j * reg_mode_size)));
10533         }
10534     }
10535 }
10536
10537 \f
10538 /* This page contains routines that are used to determine what the
10539    function prologue and epilogue code will do and write them out.  */
10540
10541 /* Return the first fixed-point register that is required to be
10542    saved. 32 if none.  */
10543
10544 int
10545 first_reg_to_save (void)
10546 {
10547   int first_reg;
10548
10549   /* Find lowest numbered live register.  */
10550   for (first_reg = 13; first_reg <= 31; first_reg++)
10551     if (regs_ever_live[first_reg]
10552         && (! call_used_regs[first_reg]
10553             || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10554                 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10555                     || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10556       break;
10557
10558 #if TARGET_MACHO
10559   if (flag_pic
10560       && current_function_uses_pic_offset_table
10561       && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10562     return RS6000_PIC_OFFSET_TABLE_REGNUM;
10563 #endif
10564
10565   return first_reg;
10566 }
10567
10568 /* Similar, for FP regs.  */
10569
10570 int
10571 first_fp_reg_to_save (void)
10572 {
10573   int first_reg;
10574
10575   /* Find lowest numbered live register.  */
10576   for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10577     if (regs_ever_live[first_reg])
10578       break;
10579
10580   return first_reg;
10581 }
10582
10583 /* Similar, for AltiVec regs.  */
10584
10585 static int
10586 first_altivec_reg_to_save (void)
10587 {
10588   int i;
10589
10590   /* Stack frame remains as is unless we are in AltiVec ABI.  */
10591   if (! TARGET_ALTIVEC_ABI)
10592     return LAST_ALTIVEC_REGNO + 1;
10593
10594   /* Find lowest numbered live register.  */
10595   for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10596     if (regs_ever_live[i])
10597       break;
10598
10599   return i;
10600 }
10601
10602 /* Return a 32-bit mask of the AltiVec registers we need to set in
10603    VRSAVE.  Bit n of the return value is 1 if Vn is live.  The MSB in
10604    the 32-bit word is 0.  */
10605
10606 static unsigned int
10607 compute_vrsave_mask (void)
10608 {
10609   unsigned int i, mask = 0;
10610
10611   /* First, find out if we use _any_ altivec registers.  */
10612   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10613     if (regs_ever_live[i])
10614       mask |= ALTIVEC_REG_BIT (i);
10615
10616   if (mask == 0)
10617     return mask;
10618
10619   /* Next, remove the argument registers from the set.  These must
10620      be in the VRSAVE mask set by the caller, so we don't need to add
10621      them in again.  More importantly, the mask we compute here is
10622      used to generate CLOBBERs in the set_vrsave insn, and we do not
10623      wish the argument registers to die.  */
10624   for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10625     mask &= ~ALTIVEC_REG_BIT (i);
10626
10627   /* Similarly, remove the return value from the set.  */
10628   {
10629     bool yes = false;
10630     diddle_return_value (is_altivec_return_reg, &yes);
10631     if (yes)
10632       mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10633   }
10634
10635   return mask;
10636 }
10637
10638 static void
10639 is_altivec_return_reg (rtx reg, void *xyes)
10640 {
10641   bool *yes = (bool *) xyes;
10642   if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10643     *yes = true;
10644 }
10645
10646 \f
10647 /* Calculate the stack information for the current function.  This is
10648    complicated by having two separate calling sequences, the AIX calling
10649    sequence and the V.4 calling sequence.
10650
10651    AIX (and Darwin/Mac OS X) stack frames look like:
10652                                                           32-bit  64-bit
10653         SP----> +---------------------------------------+
10654                 | back chain to caller                  | 0       0
10655                 +---------------------------------------+
10656                 | saved CR                              | 4       8 (8-11)
10657                 +---------------------------------------+
10658                 | saved LR                              | 8       16
10659                 +---------------------------------------+
10660                 | reserved for compilers                | 12      24
10661                 +---------------------------------------+
10662                 | reserved for binders                  | 16      32
10663                 +---------------------------------------+
10664                 | saved TOC pointer                     | 20      40
10665                 +---------------------------------------+
10666                 | Parameter save area (P)               | 24      48
10667                 +---------------------------------------+
10668                 | Alloca space (A)                      | 24+P    etc.
10669                 +---------------------------------------+
10670                 | Local variable space (L)              | 24+P+A
10671                 +---------------------------------------+
10672                 | Float/int conversion temporary (X)    | 24+P+A+L
10673                 +---------------------------------------+
10674                 | Save area for AltiVec registers (W)   | 24+P+A+L+X
10675                 +---------------------------------------+
10676                 | AltiVec alignment padding (Y)         | 24+P+A+L+X+W
10677                 +---------------------------------------+
10678                 | Save area for VRSAVE register (Z)     | 24+P+A+L+X+W+Y
10679                 +---------------------------------------+
10680                 | Save area for GP registers (G)        | 24+P+A+X+L+X+W+Y+Z
10681                 +---------------------------------------+
10682                 | Save area for FP registers (F)        | 24+P+A+X+L+X+W+Y+Z+G
10683                 +---------------------------------------+
10684         old SP->| back chain to caller's caller         |
10685                 +---------------------------------------+
10686
10687    The required alignment for AIX configurations is two words (i.e., 8
10688    or 16 bytes).
10689
10690
10691    V.4 stack frames look like:
10692
10693         SP----> +---------------------------------------+
10694                 | back chain to caller                  | 0
10695                 +---------------------------------------+
10696                 | caller's saved LR                     | 4
10697                 +---------------------------------------+
10698                 | Parameter save area (P)               | 8
10699                 +---------------------------------------+
10700                 | Alloca space (A)                      | 8+P
10701                 +---------------------------------------+
10702                 | Varargs save area (V)                 | 8+P+A
10703                 +---------------------------------------+
10704                 | Local variable space (L)              | 8+P+A+V
10705                 +---------------------------------------+
10706                 | Float/int conversion temporary (X)    | 8+P+A+V+L
10707                 +---------------------------------------+
10708                 | Save area for AltiVec registers (W)   | 8+P+A+V+L+X
10709                 +---------------------------------------+
10710                 | AltiVec alignment padding (Y)         | 8+P+A+V+L+X+W
10711                 +---------------------------------------+
10712                 | Save area for VRSAVE register (Z)     | 8+P+A+V+L+X+W+Y
10713                 +---------------------------------------+
10714                 | SPE: area for 64-bit GP registers     |
10715                 +---------------------------------------+
10716                 | SPE alignment padding                 |
10717                 +---------------------------------------+
10718                 | saved CR (C)                          | 8+P+A+V+L+X+W+Y+Z
10719                 +---------------------------------------+
10720                 | Save area for GP registers (G)        | 8+P+A+V+L+X+W+Y+Z+C
10721                 +---------------------------------------+
10722                 | Save area for FP registers (F)        | 8+P+A+V+L+X+W+Y+Z+C+G
10723                 +---------------------------------------+
10724         old SP->| back chain to caller's caller         |
10725                 +---------------------------------------+
10726
10727    The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10728    given.  (But note below and in sysv4.h that we require only 8 and
10729    may round up the size of our stack frame anyways.  The historical
10730    reason is early versions of powerpc-linux which didn't properly
10731    align the stack at program startup.  A happy side-effect is that
10732    -mno-eabi libraries can be used with -meabi programs.)
10733
10734    The EABI configuration defaults to the V.4 layout.  However,
10735    the stack alignment requirements may differ.  If -mno-eabi is not
10736    given, the required stack alignment is 8 bytes; if -mno-eabi is
10737    given, the required alignment is 16 bytes.  (But see V.4 comment
10738    above.)  */
10739
10740 #ifndef ABI_STACK_BOUNDARY
10741 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10742 #endif
10743
10744 static rs6000_stack_t *
10745 rs6000_stack_info (void)
10746 {
10747   static rs6000_stack_t info, zero_info;
10748   rs6000_stack_t *info_ptr = &info;
10749   int reg_size = TARGET_32BIT ? 4 : 8;
10750   int ehrd_size;
10751   HOST_WIDE_INT total_raw_size;
10752
10753   /* Zero all fields portably.  */
10754   info = zero_info;
10755
10756   if (TARGET_SPE)
10757     {
10758       /* Cache value so we don't rescan instruction chain over and over.  */
10759       if (cfun->machine->insn_chain_scanned_p == 0)
10760         {
10761           cfun->machine->insn_chain_scanned_p = 1;
10762           info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10763         }
10764     }
10765
10766   /* Select which calling sequence.  */
10767   info_ptr->abi = DEFAULT_ABI;
10768
10769   /* Calculate which registers need to be saved & save area size.  */
10770   info_ptr->first_gp_reg_save = first_reg_to_save ();
10771   /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10772      even if it currently looks like we won't.  */
10773   if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10774        || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10775        || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10776       && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10777     info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10778   else
10779     info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10780
10781   /* For the SPE, we have an additional upper 32-bits on each GPR.
10782      Ideally we should save the entire 64-bits only when the upper
10783      half is used in SIMD instructions.  Since we only record
10784      registers live (not the size they are used in), this proves
10785      difficult because we'd have to traverse the instruction chain at
10786      the right time, taking reload into account.  This is a real pain,
10787      so we opt to save the GPRs in 64-bits always if but one register
10788      gets used in 64-bits.  Otherwise, all the registers in the frame
10789      get saved in 32-bits.
10790
10791      So... since when we save all GPRs (except the SP) in 64-bits, the
10792      traditional GP save area will be empty.  */
10793   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10794     info_ptr->gp_size = 0;
10795
10796   info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10797   info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10798
10799   info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10800   info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10801                                  - info_ptr->first_altivec_reg_save);
10802
10803   /* Does this function call anything?  */
10804   info_ptr->calls_p = (! current_function_is_leaf
10805                        || cfun->machine->ra_needs_full_frame);
10806
10807   /* Determine if we need to save the link register.  */
10808   if (rs6000_ra_ever_killed ()
10809       || (DEFAULT_ABI == ABI_AIX
10810           && current_function_profile
10811           && !TARGET_PROFILE_KERNEL)
10812 #ifdef TARGET_RELOCATABLE
10813       || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10814 #endif
10815       || (info_ptr->first_fp_reg_save != 64
10816           && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10817       || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10818       || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10819       || (DEFAULT_ABI == ABI_DARWIN
10820           && flag_pic
10821           && current_function_uses_pic_offset_table)
10822       || info_ptr->calls_p)
10823     {
10824       info_ptr->lr_save_p = 1;
10825       regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10826     }
10827
10828   /* Determine if we need to save the condition code registers.  */
10829   if (regs_ever_live[CR2_REGNO]
10830       || regs_ever_live[CR3_REGNO]
10831       || regs_ever_live[CR4_REGNO])
10832     {
10833       info_ptr->cr_save_p = 1;
10834       if (DEFAULT_ABI == ABI_V4)
10835         info_ptr->cr_size = reg_size;
10836     }
10837
10838   /* If the current function calls __builtin_eh_return, then we need
10839      to allocate stack space for registers that will hold data for
10840      the exception handler.  */
10841   if (current_function_calls_eh_return)
10842     {
10843       unsigned int i;
10844       for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10845         continue;
10846
10847       /* SPE saves EH registers in 64-bits.  */
10848       ehrd_size = i * (TARGET_SPE_ABI
10849                        && info_ptr->spe_64bit_regs_used != 0
10850                        ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10851     }
10852   else
10853     ehrd_size = 0;
10854
10855   /* Determine various sizes.  */
10856   info_ptr->reg_size     = reg_size;
10857   info_ptr->fixed_size   = RS6000_SAVE_AREA;
10858   info_ptr->varargs_size = RS6000_VARARGS_AREA;
10859   info_ptr->vars_size    = RS6000_ALIGN (get_frame_size (), 8);
10860   info_ptr->parm_size    = RS6000_ALIGN (current_function_outgoing_args_size,
10861                                          8);
10862
10863   if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10864     info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10865   else
10866     info_ptr->spe_gp_size = 0;
10867
10868   if (TARGET_ALTIVEC_ABI)
10869     info_ptr->vrsave_mask = compute_vrsave_mask ();
10870   else
10871     info_ptr->vrsave_mask = 0;
10872
10873   if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
10874     info_ptr->vrsave_size  = 4;
10875   else
10876     info_ptr->vrsave_size  = 0;
10877
10878   /* Calculate the offsets.  */
10879   switch (DEFAULT_ABI)
10880     {
10881     case ABI_NONE:
10882     default:
10883       abort ();
10884
10885     case ABI_AIX:
10886     case ABI_DARWIN:
10887       info_ptr->fp_save_offset   = - info_ptr->fp_size;
10888       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
10889
10890       if (TARGET_ALTIVEC_ABI)
10891         {
10892           info_ptr->vrsave_save_offset
10893             = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10894
10895           /* Align stack so vector save area is on a quadword boundary.  */
10896           if (info_ptr->altivec_size != 0)
10897             info_ptr->altivec_padding_size
10898               = 16 - (-info_ptr->vrsave_save_offset % 16);
10899           else
10900             info_ptr->altivec_padding_size = 0;
10901
10902           info_ptr->altivec_save_offset
10903             = info_ptr->vrsave_save_offset
10904             - info_ptr->altivec_padding_size
10905             - info_ptr->altivec_size;
10906
10907           /* Adjust for AltiVec case.  */
10908           info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10909         }
10910       else
10911         info_ptr->ehrd_offset      = info_ptr->gp_save_offset - ehrd_size;
10912       info_ptr->cr_save_offset   = reg_size; /* first word when 64-bit.  */
10913       info_ptr->lr_save_offset   = 2*reg_size;
10914       break;
10915
10916     case ABI_V4:
10917       info_ptr->fp_save_offset   = - info_ptr->fp_size;
10918       info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
10919       info_ptr->cr_save_offset   = info_ptr->gp_save_offset - info_ptr->cr_size;
10920
10921       if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10922       {
10923         /* Align stack so SPE GPR save area is aligned on a
10924            double-word boundary.  */
10925         if (info_ptr->spe_gp_size != 0)
10926           info_ptr->spe_padding_size
10927             = 8 - (-info_ptr->cr_save_offset % 8);
10928         else
10929           info_ptr->spe_padding_size = 0;
10930
10931         info_ptr->spe_gp_save_offset
10932           = info_ptr->cr_save_offset
10933           - info_ptr->spe_padding_size
10934           - info_ptr->spe_gp_size;
10935
10936         /* Adjust for SPE case.  */
10937         info_ptr->toc_save_offset
10938           = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
10939       }
10940       else if (TARGET_ALTIVEC_ABI)
10941         {
10942           info_ptr->vrsave_save_offset
10943             = info_ptr->cr_save_offset - info_ptr->vrsave_size;
10944
10945           /* Align stack so vector save area is on a quadword boundary.  */
10946           if (info_ptr->altivec_size != 0)
10947             info_ptr->altivec_padding_size
10948               = 16 - (-info_ptr->vrsave_save_offset % 16);
10949           else
10950             info_ptr->altivec_padding_size = 0;
10951
10952           info_ptr->altivec_save_offset
10953             = info_ptr->vrsave_save_offset
10954             - info_ptr->altivec_padding_size
10955             - info_ptr->altivec_size;
10956
10957           /* Adjust for AltiVec case.  */
10958           info_ptr->toc_save_offset
10959             = info_ptr->altivec_save_offset - info_ptr->toc_size;
10960         }
10961       else
10962         info_ptr->toc_save_offset  = info_ptr->cr_save_offset - info_ptr->toc_size;
10963       info_ptr->ehrd_offset      = info_ptr->toc_save_offset - ehrd_size;
10964       info_ptr->lr_save_offset   = reg_size;
10965       break;
10966     }
10967
10968   info_ptr->save_size    = RS6000_ALIGN (info_ptr->fp_size
10969                                          + info_ptr->gp_size
10970                                          + info_ptr->altivec_size
10971                                          + info_ptr->altivec_padding_size
10972                                          + info_ptr->spe_gp_size
10973                                          + info_ptr->spe_padding_size
10974                                          + ehrd_size
10975                                          + info_ptr->cr_size
10976                                          + info_ptr->lr_size
10977                                          + info_ptr->vrsave_size
10978                                          + info_ptr->toc_size,
10979                                          (TARGET_ALTIVEC_ABI || ABI_DARWIN)
10980                                          ? 16 : 8);
10981
10982   total_raw_size         = (info_ptr->vars_size
10983                             + info_ptr->parm_size
10984                             + info_ptr->save_size
10985                             + info_ptr->varargs_size
10986                             + info_ptr->fixed_size);
10987
10988   info_ptr->total_size =
10989     RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
10990
10991   /* Determine if we need to allocate any stack frame:
10992
10993      For AIX we need to push the stack if a frame pointer is needed
10994      (because the stack might be dynamically adjusted), if we are
10995      debugging, if we make calls, or if the sum of fp_save, gp_save,
10996      and local variables are more than the space needed to save all
10997      non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
10998      + 18*8 = 288 (GPR13 reserved).
10999
11000      For V.4 we don't have the stack cushion that AIX uses, but assume
11001      that the debugger can handle stackless frames.  */
11002
11003   if (info_ptr->calls_p)
11004     info_ptr->push_p = 1;
11005
11006   else if (DEFAULT_ABI == ABI_V4)
11007     info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
11008
11009   else if (frame_pointer_needed)
11010     info_ptr->push_p = 1;
11011
11012   else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11013     info_ptr->push_p = 1;
11014
11015   else
11016     info_ptr->push_p
11017       = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288);
11018
11019   /* Zero offsets if we're not saving those registers.  */
11020   if (info_ptr->fp_size == 0)
11021     info_ptr->fp_save_offset = 0;
11022
11023   if (info_ptr->gp_size == 0)
11024     info_ptr->gp_save_offset = 0;
11025
11026   if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11027     info_ptr->altivec_save_offset = 0;
11028
11029   if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11030     info_ptr->vrsave_save_offset = 0;
11031
11032   if (! TARGET_SPE_ABI
11033       || info_ptr->spe_64bit_regs_used == 0
11034       || info_ptr->spe_gp_size == 0)
11035     info_ptr->spe_gp_save_offset = 0;
11036
11037   if (! info_ptr->lr_save_p)
11038     info_ptr->lr_save_offset = 0;
11039
11040   if (! info_ptr->cr_save_p)
11041     info_ptr->cr_save_offset = 0;
11042
11043   if (! info_ptr->toc_save_p)
11044     info_ptr->toc_save_offset = 0;
11045
11046   return info_ptr;
11047 }
11048
11049 /* Return true if the current function uses any GPRs in 64-bit SIMD
11050    mode.  */
11051
11052 static bool
11053 spe_func_has_64bit_regs_p (void)
11054 {
11055   rtx insns, insn;
11056
11057   /* Functions that save and restore all the call-saved registers will
11058      need to save/restore the registers in 64-bits.  */
11059   if (current_function_calls_eh_return
11060       || current_function_calls_setjmp
11061       || current_function_has_nonlocal_goto)
11062     return true;
11063
11064   insns = get_insns ();
11065
11066   for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11067     {
11068       if (INSN_P (insn))
11069         {
11070           rtx i;
11071
11072           i = PATTERN (insn);
11073           if (GET_CODE (i) == SET
11074               && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
11075             return true;
11076         }
11077     }
11078
11079   return false;
11080 }
11081
11082 static void
11083 debug_stack_info (rs6000_stack_t *info)
11084 {
11085   const char *abi_string;
11086
11087   if (! info)
11088     info = rs6000_stack_info ();
11089
11090   fprintf (stderr, "\nStack information for function %s:\n",
11091            ((current_function_decl && DECL_NAME (current_function_decl))
11092             ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11093             : "<unknown>"));
11094
11095   switch (info->abi)
11096     {
11097     default:             abi_string = "Unknown";        break;
11098     case ABI_NONE:       abi_string = "NONE";           break;
11099     case ABI_AIX:        abi_string = "AIX";            break;
11100     case ABI_DARWIN:     abi_string = "Darwin";         break;
11101     case ABI_V4:         abi_string = "V.4";            break;
11102     }
11103
11104   fprintf (stderr, "\tABI                 = %5s\n", abi_string);
11105
11106   if (TARGET_ALTIVEC_ABI)
11107     fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11108
11109   if (TARGET_SPE_ABI)
11110     fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11111
11112   if (info->first_gp_reg_save != 32)
11113     fprintf (stderr, "\tfirst_gp_reg_save   = %5d\n", info->first_gp_reg_save);
11114
11115   if (info->first_fp_reg_save != 64)
11116     fprintf (stderr, "\tfirst_fp_reg_save   = %5d\n", info->first_fp_reg_save);
11117
11118   if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11119     fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11120              info->first_altivec_reg_save);
11121
11122   if (info->lr_save_p)
11123     fprintf (stderr, "\tlr_save_p           = %5d\n", info->lr_save_p);
11124
11125   if (info->cr_save_p)
11126     fprintf (stderr, "\tcr_save_p           = %5d\n", info->cr_save_p);
11127
11128   if (info->toc_save_p)
11129     fprintf (stderr, "\ttoc_save_p          = %5d\n", info->toc_save_p);
11130
11131   if (info->vrsave_mask)
11132     fprintf (stderr, "\tvrsave_mask         = 0x%x\n", info->vrsave_mask);
11133
11134   if (info->push_p)
11135     fprintf (stderr, "\tpush_p              = %5d\n", info->push_p);
11136
11137   if (info->calls_p)
11138     fprintf (stderr, "\tcalls_p             = %5d\n", info->calls_p);
11139
11140   if (info->gp_save_offset)
11141     fprintf (stderr, "\tgp_save_offset      = %5d\n", info->gp_save_offset);
11142
11143   if (info->fp_save_offset)
11144     fprintf (stderr, "\tfp_save_offset      = %5d\n", info->fp_save_offset);
11145
11146   if (info->altivec_save_offset)
11147     fprintf (stderr, "\taltivec_save_offset = %5d\n",
11148              info->altivec_save_offset);
11149
11150   if (info->spe_gp_save_offset)
11151     fprintf (stderr, "\tspe_gp_save_offset  = %5d\n",
11152              info->spe_gp_save_offset);
11153
11154   if (info->vrsave_save_offset)
11155     fprintf (stderr, "\tvrsave_save_offset  = %5d\n",
11156              info->vrsave_save_offset);
11157
11158   if (info->lr_save_offset)
11159     fprintf (stderr, "\tlr_save_offset      = %5d\n", info->lr_save_offset);
11160
11161   if (info->cr_save_offset)
11162     fprintf (stderr, "\tcr_save_offset      = %5d\n", info->cr_save_offset);
11163
11164   if (info->toc_save_offset)
11165     fprintf (stderr, "\ttoc_save_offset     = %5d\n", info->toc_save_offset);
11166
11167   if (info->varargs_save_offset)
11168     fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11169
11170   if (info->total_size)
11171     fprintf (stderr, "\ttotal_size          = "HOST_WIDE_INT_PRINT_DEC"\n",
11172              info->total_size);
11173
11174   if (info->varargs_size)
11175     fprintf (stderr, "\tvarargs_size        = %5d\n", info->varargs_size);
11176
11177   if (info->vars_size)
11178     fprintf (stderr, "\tvars_size           = "HOST_WIDE_INT_PRINT_DEC"\n",
11179              info->vars_size);
11180
11181   if (info->parm_size)
11182     fprintf (stderr, "\tparm_size           = %5d\n", info->parm_size);
11183
11184   if (info->fixed_size)
11185     fprintf (stderr, "\tfixed_size          = %5d\n", info->fixed_size);
11186
11187   if (info->gp_size)
11188     fprintf (stderr, "\tgp_size             = %5d\n", info->gp_size);
11189
11190   if (info->spe_gp_size)
11191     fprintf (stderr, "\tspe_gp_size         = %5d\n", info->spe_gp_size);
11192
11193   if (info->fp_size)
11194     fprintf (stderr, "\tfp_size             = %5d\n", info->fp_size);
11195
11196   if (info->altivec_size)
11197     fprintf (stderr, "\taltivec_size        = %5d\n", info->altivec_size);
11198
11199   if (info->vrsave_size)
11200     fprintf (stderr, "\tvrsave_size         = %5d\n", info->vrsave_size);
11201
11202   if (info->altivec_padding_size)
11203     fprintf (stderr, "\taltivec_padding_size= %5d\n",
11204              info->altivec_padding_size);
11205
11206   if (info->spe_padding_size)
11207     fprintf (stderr, "\tspe_padding_size    = %5d\n",
11208              info->spe_padding_size);
11209
11210   if (info->lr_size)
11211     fprintf (stderr, "\tlr_size             = %5d\n", info->lr_size);
11212
11213   if (info->cr_size)
11214     fprintf (stderr, "\tcr_size             = %5d\n", info->cr_size);
11215
11216   if (info->toc_size)
11217     fprintf (stderr, "\ttoc_size            = %5d\n", info->toc_size);
11218
11219   if (info->save_size)
11220     fprintf (stderr, "\tsave_size           = %5d\n", info->save_size);
11221
11222   if (info->reg_size != 4)
11223     fprintf (stderr, "\treg_size            = %5d\n", info->reg_size);
11224
11225   fprintf (stderr, "\n");
11226 }
11227
11228 rtx
11229 rs6000_return_addr (int count, rtx frame)
11230 {
11231   /* Currently we don't optimize very well between prolog and body
11232      code and for PIC code the code can be actually quite bad, so
11233      don't try to be too clever here.  */
11234   if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11235     {
11236       cfun->machine->ra_needs_full_frame = 1;
11237
11238       return
11239         gen_rtx_MEM
11240           (Pmode,
11241            memory_address
11242            (Pmode,
11243             plus_constant (copy_to_reg
11244                            (gen_rtx_MEM (Pmode,
11245                                          memory_address (Pmode, frame))),
11246                            RETURN_ADDRESS_OFFSET)));
11247     }
11248
11249   cfun->machine->ra_need_lr = 1;
11250   return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11251 }
11252
11253 /* Say whether a function is a candidate for sibcall handling or not.
11254    We do not allow indirect calls to be optimized into sibling calls.
11255    Also, we can't do it if there are any vector parameters; there's
11256    nowhere to put the VRsave code so it works; note that functions with
11257    vector parameters are required to have a prototype, so the argument
11258    type info must be available here.  (The tail recursion case can work
11259    with vector parameters, but there's no way to distinguish here.) */
11260 static bool
11261 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11262 {
11263   tree type;
11264   if (decl)
11265     {
11266       if (TARGET_ALTIVEC_VRSAVE)
11267         {
11268           for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11269                type; type = TREE_CHAIN (type))
11270             {
11271               if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11272                 return false;
11273             }
11274         }
11275       if (DEFAULT_ABI == ABI_DARWIN
11276           || (*targetm.binds_local_p) (decl))
11277         {
11278           tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11279
11280           if (!lookup_attribute ("longcall", attr_list)
11281               || lookup_attribute ("shortcall", attr_list))
11282             return true;
11283         }
11284     }
11285   return false;
11286 }
11287
11288 static int
11289 rs6000_ra_ever_killed (void)
11290 {
11291   rtx top;
11292   rtx reg;
11293   rtx insn;
11294
11295   if (current_function_is_thunk)
11296     return 0;
11297
11298   /* regs_ever_live has LR marked as used if any sibcalls are present,
11299      but this should not force saving and restoring in the
11300      pro/epilogue.  Likewise, reg_set_between_p thinks a sibcall
11301      clobbers LR, so that is inappropriate.  */
11302
11303   /* Also, the prologue can generate a store into LR that
11304      doesn't really count, like this:
11305
11306         move LR->R0
11307         bcl to set PIC register
11308         move LR->R31
11309         move R0->LR
11310
11311      When we're called from the epilogue, we need to avoid counting
11312      this as a store.  */
11313
11314   push_topmost_sequence ();
11315   top = get_insns ();
11316   pop_topmost_sequence ();
11317   reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11318
11319   for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11320     {
11321       if (INSN_P (insn))
11322         {
11323           if (FIND_REG_INC_NOTE (insn, reg))
11324             return 1;
11325           else if (GET_CODE (insn) == CALL_INSN
11326                    && !SIBLING_CALL_P (insn))
11327             return 1;
11328           else if (set_of (reg, insn) != NULL_RTX
11329                    && !prologue_epilogue_contains (insn))
11330             return 1;
11331         }
11332     }
11333   return 0;
11334 }
11335 \f
11336 /* Add a REG_MAYBE_DEAD note to the insn.  */
11337 static void
11338 rs6000_maybe_dead (rtx insn)
11339 {
11340   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11341                                         const0_rtx,
11342                                         REG_NOTES (insn));
11343 }
11344
11345 /* Emit instructions needed to load the TOC register.
11346    This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11347    a constant pool; or for SVR4 -fpic.  */
11348
11349 void
11350 rs6000_emit_load_toc_table (int fromprolog)
11351 {
11352   rtx dest, insn;
11353   dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11354
11355   if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11356     {
11357       rtx temp = (fromprolog
11358                   ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11359                   : gen_reg_rtx (Pmode));
11360       insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11361       if (fromprolog)
11362         rs6000_maybe_dead (insn);
11363       insn = emit_move_insn (dest, temp);
11364       if (fromprolog)
11365         rs6000_maybe_dead (insn);
11366     }
11367   else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11368     {
11369       char buf[30];
11370       rtx tempLR = (fromprolog
11371                     ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11372                     : gen_reg_rtx (Pmode));
11373       rtx temp0 = (fromprolog
11374                    ? gen_rtx_REG (Pmode, 0)
11375                    : gen_reg_rtx (Pmode));
11376       rtx symF;
11377
11378       /* possibly create the toc section */
11379       if (! toc_initialized)
11380         {
11381           toc_section ();
11382           function_section (current_function_decl);
11383         }
11384
11385       if (fromprolog)
11386         {
11387           rtx symL;
11388
11389           ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
11390           symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11391
11392           ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
11393           symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11394
11395           rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
11396                                                                symF)));
11397           rs6000_maybe_dead (emit_move_insn (dest, tempLR));
11398           rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
11399                                                                symL,
11400                                                                symF)));
11401         }
11402       else
11403         {
11404           rtx tocsym;
11405           static int reload_toc_labelno = 0;
11406
11407           tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11408
11409           ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11410           symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11411
11412           emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11413           emit_move_insn (dest, tempLR);
11414           emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11415         }
11416       insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11417       if (fromprolog)
11418         rs6000_maybe_dead (insn);
11419     }
11420   else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11421     {
11422       /* This is for AIX code running in non-PIC ELF32.  */
11423       char buf[30];
11424       rtx realsym;
11425       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11426       realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11427
11428       insn = emit_insn (gen_elf_high (dest, realsym));
11429       if (fromprolog)
11430         rs6000_maybe_dead (insn);
11431       insn = emit_insn (gen_elf_low (dest, dest, realsym));
11432       if (fromprolog)
11433         rs6000_maybe_dead (insn);
11434     }
11435   else if (DEFAULT_ABI == ABI_AIX)
11436     {
11437       if (TARGET_32BIT)
11438         insn = emit_insn (gen_load_toc_aix_si (dest));
11439       else
11440         insn = emit_insn (gen_load_toc_aix_di (dest));
11441       if (fromprolog)
11442         rs6000_maybe_dead (insn);
11443     }
11444   else
11445     abort ();
11446 }
11447
11448 /* Emit instructions to restore the link register after determining where
11449    its value has been stored.  */
11450
11451 void
11452 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11453 {
11454   rs6000_stack_t *info = rs6000_stack_info ();
11455   rtx operands[2];
11456
11457   operands[0] = source;
11458   operands[1] = scratch;
11459
11460   if (info->lr_save_p)
11461     {
11462       rtx frame_rtx = stack_pointer_rtx;
11463       HOST_WIDE_INT sp_offset = 0;
11464       rtx tmp;
11465
11466       if (frame_pointer_needed
11467           || current_function_calls_alloca
11468           || info->total_size > 32767)
11469         {
11470           emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11471           frame_rtx = operands[1];
11472         }
11473       else if (info->push_p)
11474         sp_offset = info->total_size;
11475
11476       tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11477       tmp = gen_rtx_MEM (Pmode, tmp);
11478       emit_move_insn (tmp, operands[0]);
11479     }
11480   else
11481     emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11482 }
11483
11484 static GTY(()) int set = -1;
11485
11486 int
11487 get_TOC_alias_set (void)
11488 {
11489   if (set == -1)
11490     set = new_alias_set ();
11491   return set;
11492 }
11493
11494 /* This returns nonzero if the current function uses the TOC.  This is
11495    determined by the presence of (use (unspec ... UNSPEC_TOC)), which
11496    is generated by the ABI_V4 load_toc_* patterns.  */
11497 #if TARGET_ELF
11498 static int
11499 uses_TOC (void)
11500 {
11501   rtx insn;
11502
11503   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11504     if (INSN_P (insn))
11505       {
11506         rtx pat = PATTERN (insn);
11507         int i;
11508
11509         if (GET_CODE (pat) == PARALLEL)
11510           for (i = 0; i < XVECLEN (pat, 0); i++)
11511             {
11512               rtx sub = XVECEXP (pat, 0, i);
11513               if (GET_CODE (sub) == USE)
11514                 {
11515                   sub = XEXP (sub, 0);
11516                   if (GET_CODE (sub) == UNSPEC
11517                       && XINT (sub, 1) == UNSPEC_TOC)
11518                     return 1;
11519                 }
11520             }
11521       }
11522   return 0;
11523 }
11524 #endif
11525
11526 rtx
11527 create_TOC_reference (rtx symbol)
11528 {
11529   return gen_rtx_PLUS (Pmode,
11530            gen_rtx_REG (Pmode, TOC_REGISTER),
11531              gen_rtx_CONST (Pmode,
11532                gen_rtx_MINUS (Pmode, symbol,
11533                  gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11534 }
11535
11536 /* If _Unwind_* has been called from within the same module,
11537    toc register is not guaranteed to be saved to 40(1) on function
11538    entry.  Save it there in that case.  */
11539
11540 void
11541 rs6000_aix_emit_builtin_unwind_init (void)
11542 {
11543   rtx mem;
11544   rtx stack_top = gen_reg_rtx (Pmode);
11545   rtx opcode_addr = gen_reg_rtx (Pmode);
11546   rtx opcode = gen_reg_rtx (SImode);
11547   rtx tocompare = gen_reg_rtx (SImode);
11548   rtx no_toc_save_needed = gen_label_rtx ();
11549
11550   mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11551   emit_move_insn (stack_top, mem);
11552
11553   mem = gen_rtx_MEM (Pmode,
11554                      gen_rtx_PLUS (Pmode, stack_top,
11555                                    GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11556   emit_move_insn (opcode_addr, mem);
11557   emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11558   emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11559                                            : 0xE8410028, SImode));
11560
11561   do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11562                            SImode, NULL_RTX, NULL_RTX,
11563                            no_toc_save_needed);
11564
11565   mem = gen_rtx_MEM (Pmode,
11566                      gen_rtx_PLUS (Pmode, stack_top,
11567                                    GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11568   emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11569   emit_label (no_toc_save_needed);
11570 }
11571 \f
11572 /* This ties together stack memory (MEM with an alias set of
11573    rs6000_sr_alias_set) and the change to the stack pointer.  */
11574
11575 static void
11576 rs6000_emit_stack_tie (void)
11577 {
11578   rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11579
11580   set_mem_alias_set (mem, rs6000_sr_alias_set);
11581   emit_insn (gen_stack_tie (mem));
11582 }
11583
11584 /* Emit the correct code for allocating stack space, as insns.
11585    If COPY_R12, make sure a copy of the old frame is left in r12.
11586    The generated code may use hard register 0 as a temporary.  */
11587
11588 static void
11589 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11590 {
11591   rtx insn;
11592   rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11593   rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11594   rtx todec = GEN_INT (-size);
11595
11596   if (current_function_limit_stack)
11597     {
11598       if (REG_P (stack_limit_rtx)
11599           && REGNO (stack_limit_rtx) > 1
11600           && REGNO (stack_limit_rtx) <= 31)
11601         {
11602           emit_insn (TARGET_32BIT
11603                      ? gen_addsi3 (tmp_reg,
11604                                    stack_limit_rtx,
11605                                    GEN_INT (size))
11606                      : gen_adddi3 (tmp_reg,
11607                                    stack_limit_rtx,
11608                                    GEN_INT (size)));
11609
11610           emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11611                                     const0_rtx));
11612         }
11613       else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11614                && TARGET_32BIT
11615                && DEFAULT_ABI == ABI_V4)
11616         {
11617           rtx toload = gen_rtx_CONST (VOIDmode,
11618                                       gen_rtx_PLUS (Pmode,
11619                                                     stack_limit_rtx,
11620                                                     GEN_INT (size)));
11621
11622           emit_insn (gen_elf_high (tmp_reg, toload));
11623           emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11624           emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11625                                     const0_rtx));
11626         }
11627       else
11628         warning ("stack limit expression is not supported");
11629     }
11630
11631   if (copy_r12 || ! TARGET_UPDATE)
11632     emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11633
11634   if (TARGET_UPDATE)
11635     {
11636       if (size > 32767)
11637         {
11638           /* Need a note here so that try_split doesn't get confused.  */
11639           if (get_last_insn() == NULL_RTX)
11640             emit_note (NOTE_INSN_DELETED);
11641           insn = emit_move_insn (tmp_reg, todec);
11642           try_split (PATTERN (insn), insn, 0);
11643           todec = tmp_reg;
11644         }
11645
11646       insn = emit_insn (TARGET_32BIT
11647                         ? gen_movsi_update (stack_reg, stack_reg,
11648                                             todec, stack_reg)
11649                         : gen_movdi_update (stack_reg, stack_reg,
11650                                             todec, stack_reg));
11651     }
11652   else
11653     {
11654       insn = emit_insn (TARGET_32BIT
11655                         ? gen_addsi3 (stack_reg, stack_reg, todec)
11656                         : gen_adddi3 (stack_reg, stack_reg, todec));
11657       emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11658                       gen_rtx_REG (Pmode, 12));
11659     }
11660
11661   RTX_FRAME_RELATED_P (insn) = 1;
11662   REG_NOTES (insn) =
11663     gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11664                        gen_rtx_SET (VOIDmode, stack_reg,
11665                                     gen_rtx_PLUS (Pmode, stack_reg,
11666                                                   GEN_INT (-size))),
11667                        REG_NOTES (insn));
11668 }
11669
11670 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11671    with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11672    is not NULL.  It would be nice if dwarf2out_frame_debug_expr could
11673    deduce these equivalences by itself so it wasn't necessary to hold
11674    its hand so much.  */
11675
11676 static void
11677 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11678                       rtx reg2, rtx rreg)
11679 {
11680   rtx real, temp;
11681
11682   /* copy_rtx will not make unique copies of registers, so we need to
11683      ensure we don't have unwanted sharing here.  */
11684   if (reg == reg2)
11685     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11686
11687   if (reg == rreg)
11688     reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11689
11690   real = copy_rtx (PATTERN (insn));
11691
11692   if (reg2 != NULL_RTX)
11693     real = replace_rtx (real, reg2, rreg);
11694
11695   real = replace_rtx (real, reg,
11696                       gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11697                                                         STACK_POINTER_REGNUM),
11698                                     GEN_INT (val)));
11699
11700   /* We expect that 'real' is either a SET or a PARALLEL containing
11701      SETs (and possibly other stuff).  In a PARALLEL, all the SETs
11702      are important so they all have to be marked RTX_FRAME_RELATED_P.  */
11703
11704   if (GET_CODE (real) == SET)
11705     {
11706       rtx set = real;
11707
11708       temp = simplify_rtx (SET_SRC (set));
11709       if (temp)
11710         SET_SRC (set) = temp;
11711       temp = simplify_rtx (SET_DEST (set));
11712       if (temp)
11713         SET_DEST (set) = temp;
11714       if (GET_CODE (SET_DEST (set)) == MEM)
11715         {
11716           temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11717           if (temp)
11718             XEXP (SET_DEST (set), 0) = temp;
11719         }
11720     }
11721   else if (GET_CODE (real) == PARALLEL)
11722     {
11723       int i;
11724       for (i = 0; i < XVECLEN (real, 0); i++)
11725         if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11726           {
11727             rtx set = XVECEXP (real, 0, i);
11728
11729             temp = simplify_rtx (SET_SRC (set));
11730             if (temp)
11731               SET_SRC (set) = temp;
11732             temp = simplify_rtx (SET_DEST (set));
11733             if (temp)
11734               SET_DEST (set) = temp;
11735             if (GET_CODE (SET_DEST (set)) == MEM)
11736               {
11737                 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11738                 if (temp)
11739                   XEXP (SET_DEST (set), 0) = temp;
11740               }
11741             RTX_FRAME_RELATED_P (set) = 1;
11742           }
11743     }
11744   else
11745     abort ();
11746
11747   if (TARGET_SPE)
11748     real = spe_synthesize_frame_save (real);
11749
11750   RTX_FRAME_RELATED_P (insn) = 1;
11751   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11752                                         real,
11753                                         REG_NOTES (insn));
11754 }
11755
11756 /* Given an SPE frame note, return a PARALLEL of SETs with the
11757    original note, plus a synthetic register save.  */
11758
11759 static rtx
11760 spe_synthesize_frame_save (rtx real)
11761 {
11762   rtx synth, offset, reg, real2;
11763
11764   if (GET_CODE (real) != SET
11765       || GET_MODE (SET_SRC (real)) != V2SImode)
11766     return real;
11767
11768   /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11769      frame related note.  The parallel contains a set of the register
11770      being saved, and another set to a synthetic register (n+1200).
11771      This is so we can differentiate between 64-bit and 32-bit saves.
11772      Words cannot describe this nastiness.  */
11773
11774   if (GET_CODE (SET_DEST (real)) != MEM
11775       || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11776       || GET_CODE (SET_SRC (real)) != REG)
11777     abort ();
11778
11779   /* Transform:
11780        (set (mem (plus (reg x) (const y)))
11781             (reg z))
11782      into:
11783        (set (mem (plus (reg x) (const y+4)))
11784             (reg z+1200))
11785   */
11786
11787   real2 = copy_rtx (real);
11788   PUT_MODE (SET_DEST (real2), SImode);
11789   reg = SET_SRC (real2);
11790   real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11791   synth = copy_rtx (real2);
11792
11793   if (BYTES_BIG_ENDIAN)
11794     {
11795       offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11796       real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11797     }
11798
11799   reg = SET_SRC (synth);
11800
11801   synth = replace_rtx (synth, reg,
11802                        gen_rtx_REG (SImode, REGNO (reg) + 1200));
11803
11804   offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11805   synth = replace_rtx (synth, offset,
11806                        GEN_INT (INTVAL (offset)
11807                                 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11808
11809   RTX_FRAME_RELATED_P (synth) = 1;
11810   RTX_FRAME_RELATED_P (real2) = 1;
11811   if (BYTES_BIG_ENDIAN)
11812     real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11813   else
11814     real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11815
11816   return real;
11817 }
11818
11819 /* Returns an insn that has a vrsave set operation with the
11820    appropriate CLOBBERs.  */
11821
11822 static rtx
11823 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11824 {
11825   int nclobs, i;
11826   rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11827   rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11828
11829   clobs[0]
11830     = gen_rtx_SET (VOIDmode,
11831                    vrsave,
11832                    gen_rtx_UNSPEC_VOLATILE (SImode,
11833                                             gen_rtvec (2, reg, vrsave),
11834                                             30));
11835
11836   nclobs = 1;
11837
11838   /* We need to clobber the registers in the mask so the scheduler
11839      does not move sets to VRSAVE before sets of AltiVec registers.
11840
11841      However, if the function receives nonlocal gotos, reload will set
11842      all call saved registers live.  We will end up with:
11843
11844         (set (reg 999) (mem))
11845         (parallel [ (set (reg vrsave) (unspec blah))
11846                     (clobber (reg 999))])
11847
11848      The clobber will cause the store into reg 999 to be dead, and
11849      flow will attempt to delete an epilogue insn.  In this case, we
11850      need an unspec use/set of the register.  */
11851
11852   for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11853     if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
11854       {
11855         if (!epiloguep || call_used_regs [i])
11856           clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11857                                              gen_rtx_REG (V4SImode, i));
11858         else
11859           {
11860             rtx reg = gen_rtx_REG (V4SImode, i);
11861
11862             clobs[nclobs++]
11863               = gen_rtx_SET (VOIDmode,
11864                              reg,
11865                              gen_rtx_UNSPEC (V4SImode,
11866                                              gen_rtvec (1, reg), 27));
11867           }
11868       }
11869
11870   insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11871
11872   for (i = 0; i < nclobs; ++i)
11873     XVECEXP (insn, 0, i) = clobs[i];
11874
11875   return insn;
11876 }
11877
11878 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11879    Save REGNO into [FRAME_REG + OFFSET] in mode MODE.  */
11880
11881 static void
11882 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11883                  unsigned int regno, int offset, HOST_WIDE_INT total_size)
11884 {
11885   rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11886   rtx replacea, replaceb;
11887
11888   int_rtx = GEN_INT (offset);
11889
11890   /* Some cases that need register indexed addressing.  */
11891   if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11892       || (TARGET_SPE_ABI
11893           && SPE_VECTOR_MODE (mode)
11894           && !SPE_CONST_OFFSET_OK (offset)))
11895     {
11896       /* Whomever calls us must make sure r11 is available in the
11897          flow path of instructions in the prologue.  */
11898       offset_rtx = gen_rtx_REG (Pmode, 11);
11899       emit_move_insn (offset_rtx, int_rtx);
11900
11901       replacea = offset_rtx;
11902       replaceb = int_rtx;
11903     }
11904   else
11905     {
11906       offset_rtx = int_rtx;
11907       replacea = NULL_RTX;
11908       replaceb = NULL_RTX;
11909     }
11910
11911   reg = gen_rtx_REG (mode, regno);
11912   addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11913   mem = gen_rtx_MEM (mode, addr);
11914   set_mem_alias_set (mem, rs6000_sr_alias_set);
11915
11916   insn = emit_move_insn (mem, reg);
11917
11918   rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
11919 }
11920
11921 /* Emit an offset memory reference suitable for a frame store, while
11922    converting to a valid addressing mode.  */
11923
11924 static rtx
11925 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
11926 {
11927   rtx int_rtx, offset_rtx;
11928
11929   int_rtx = GEN_INT (offset);
11930
11931   if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
11932     {
11933       offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11934       emit_move_insn (offset_rtx, int_rtx);
11935     }
11936   else
11937     offset_rtx = int_rtx;
11938
11939   return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
11940 }
11941
11942 /* Emit function prologue as insns.  */
11943
11944 void
11945 rs6000_emit_prologue (void)
11946 {
11947   rs6000_stack_t *info = rs6000_stack_info ();
11948   enum machine_mode reg_mode = Pmode;
11949   int reg_size = TARGET_32BIT ? 4 : 8;
11950   rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11951   rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
11952   rtx frame_reg_rtx = sp_reg_rtx;
11953   rtx cr_save_rtx = NULL_RTX;
11954   rtx insn;
11955   int saving_FPRs_inline;
11956   int using_store_multiple;
11957   HOST_WIDE_INT sp_offset = 0;
11958
11959    if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11960      {
11961        reg_mode = V2SImode;
11962        reg_size = 8;
11963      }
11964
11965   using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
11966                           && (!TARGET_SPE_ABI
11967                               || info->spe_64bit_regs_used == 0)
11968                           && info->first_gp_reg_save < 31);
11969   saving_FPRs_inline = (info->first_fp_reg_save == 64
11970                         || FP_SAVE_INLINE (info->first_fp_reg_save)
11971                         || current_function_calls_eh_return
11972                         || cfun->machine->ra_need_lr);
11973
11974   /* For V.4, update stack before we do any saving and set back pointer.  */
11975   if (info->push_p
11976       && (DEFAULT_ABI == ABI_V4
11977           || current_function_calls_eh_return))
11978     {
11979       if (info->total_size < 32767)
11980         sp_offset = info->total_size;
11981       else
11982         frame_reg_rtx = frame_ptr_rtx;
11983       rs6000_emit_allocate_stack (info->total_size,
11984                                   (frame_reg_rtx != sp_reg_rtx
11985                                    && (info->cr_save_p
11986                                        || info->lr_save_p
11987                                        || info->first_fp_reg_save < 64
11988                                        || info->first_gp_reg_save < 32
11989                                        )));
11990       if (frame_reg_rtx != sp_reg_rtx)
11991         rs6000_emit_stack_tie ();
11992     }
11993
11994   /* Save AltiVec registers if needed.  */
11995   if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
11996     {
11997       int i;
11998
11999       /* There should be a non inline version of this, for when we
12000          are saving lots of vector registers.  */
12001       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12002         if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12003           {
12004             rtx areg, savereg, mem;
12005             int offset;
12006
12007             offset = info->altivec_save_offset + sp_offset
12008               + 16 * (i - info->first_altivec_reg_save);
12009
12010             savereg = gen_rtx_REG (V4SImode, i);
12011
12012             areg = gen_rtx_REG (Pmode, 0);
12013             emit_move_insn (areg, GEN_INT (offset));
12014
12015             /* AltiVec addressing mode is [reg+reg].  */
12016             mem = gen_rtx_MEM (V4SImode,
12017                                gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12018
12019             set_mem_alias_set (mem, rs6000_sr_alias_set);
12020
12021             insn = emit_move_insn (mem, savereg);
12022
12023             rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12024                                   areg, GEN_INT (offset));
12025           }
12026     }
12027
12028   /* VRSAVE is a bit vector representing which AltiVec registers
12029      are used.  The OS uses this to determine which vector
12030      registers to save on a context switch.  We need to save
12031      VRSAVE on the stack frame, add whatever AltiVec registers we
12032      used in this function, and do the corresponding magic in the
12033      epilogue.  */
12034
12035   if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12036       && info->vrsave_mask != 0)
12037     {
12038       rtx reg, mem, vrsave;
12039       int offset;
12040
12041       /* Get VRSAVE onto a GPR.  */
12042       reg = gen_rtx_REG (SImode, 12);
12043       vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12044       if (TARGET_MACHO)
12045         emit_insn (gen_get_vrsave_internal (reg));
12046       else
12047         emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12048
12049       /* Save VRSAVE.  */
12050       offset = info->vrsave_save_offset + sp_offset;
12051       mem
12052         = gen_rtx_MEM (SImode,
12053                        gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12054       set_mem_alias_set (mem, rs6000_sr_alias_set);
12055       insn = emit_move_insn (mem, reg);
12056
12057       /* Include the registers in the mask.  */
12058       emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12059
12060       insn = emit_insn (generate_set_vrsave (reg, info, 0));
12061     }
12062
12063   /* If we use the link register, get it into r0.  */
12064   if (info->lr_save_p)
12065     emit_move_insn (gen_rtx_REG (Pmode, 0),
12066                     gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12067
12068   /* If we need to save CR, put it into r12.  */
12069   if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12070     {
12071       cr_save_rtx = gen_rtx_REG (SImode, 12);
12072       emit_insn (gen_movesi_from_cr (cr_save_rtx));
12073     }
12074
12075   /* Do any required saving of fpr's.  If only one or two to save, do
12076      it ourselves.  Otherwise, call function.  */
12077   if (saving_FPRs_inline)
12078     {
12079       int i;
12080       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12081         if ((regs_ever_live[info->first_fp_reg_save+i]
12082              && ! call_used_regs[info->first_fp_reg_save+i]))
12083           emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12084                            info->first_fp_reg_save + i,
12085                            info->fp_save_offset + sp_offset + 8 * i,
12086                            info->total_size);
12087     }
12088   else if (info->first_fp_reg_save != 64)
12089     {
12090       int i;
12091       char rname[30];
12092       const char *alloc_rname;
12093       rtvec p;
12094       p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12095
12096       RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12097                                           gen_rtx_REG (Pmode,
12098                                                        LINK_REGISTER_REGNUM));
12099       sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12100                info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12101       alloc_rname = ggc_strdup (rname);
12102       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12103                                       gen_rtx_SYMBOL_REF (Pmode,
12104                                                           alloc_rname));
12105       for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12106         {
12107           rtx addr, reg, mem;
12108           reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12109           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12110                                GEN_INT (info->fp_save_offset
12111                                         + sp_offset + 8*i));
12112           mem = gen_rtx_MEM (DFmode, addr);
12113           set_mem_alias_set (mem, rs6000_sr_alias_set);
12114
12115           RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12116         }
12117       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12118       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12119                             NULL_RTX, NULL_RTX);
12120     }
12121
12122   /* Save GPRs.  This is done as a PARALLEL if we are using
12123      the store-multiple instructions.  */
12124   if (using_store_multiple)
12125     {
12126       rtvec p;
12127       int i;
12128       p = rtvec_alloc (32 - info->first_gp_reg_save);
12129       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12130         {
12131           rtx addr, reg, mem;
12132           reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12133           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12134                                GEN_INT (info->gp_save_offset
12135                                         + sp_offset
12136                                         + reg_size * i));
12137           mem = gen_rtx_MEM (reg_mode, addr);
12138           set_mem_alias_set (mem, rs6000_sr_alias_set);
12139
12140           RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12141         }
12142       insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12143       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12144                             NULL_RTX, NULL_RTX);
12145     }
12146   else
12147     {
12148       int i;
12149       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12150         if ((regs_ever_live[info->first_gp_reg_save+i]
12151              && ! call_used_regs[info->first_gp_reg_save+i])
12152             || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12153                 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12154                     || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12155           {
12156             rtx addr, reg, mem;
12157             reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12158
12159             if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12160               {
12161                 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12162                 rtx b;
12163
12164                 if (!SPE_CONST_OFFSET_OK (offset))
12165                   {
12166                     b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12167                     emit_move_insn (b, GEN_INT (offset));
12168                   }
12169                 else
12170                   b = GEN_INT (offset);
12171
12172                 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12173                 mem = gen_rtx_MEM (V2SImode, addr);
12174                 set_mem_alias_set (mem, rs6000_sr_alias_set);
12175                 insn = emit_move_insn (mem, reg);
12176
12177                 if (GET_CODE (b) == CONST_INT)
12178                   rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12179                                         NULL_RTX, NULL_RTX);
12180                 else
12181                   rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12182                                         b, GEN_INT (offset));
12183               }
12184             else
12185               {
12186                 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12187                                      GEN_INT (info->gp_save_offset
12188                                               + sp_offset
12189                                               + reg_size * i));
12190                 mem = gen_rtx_MEM (reg_mode, addr);
12191                 set_mem_alias_set (mem, rs6000_sr_alias_set);
12192
12193                 insn = emit_move_insn (mem, reg);
12194                 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12195                                       NULL_RTX, NULL_RTX);
12196               }
12197           }
12198     }
12199
12200   /* ??? There's no need to emit actual instructions here, but it's the
12201      easiest way to get the frame unwind information emitted.  */
12202   if (current_function_calls_eh_return)
12203     {
12204       unsigned int i, regno;
12205
12206       /* In AIX ABI we need to pretend we save r2 here.  */
12207       if (TARGET_AIX)
12208         {
12209           rtx addr, reg, mem;
12210
12211           reg = gen_rtx_REG (reg_mode, 2);
12212           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12213                                GEN_INT (sp_offset + 5 * reg_size));
12214           mem = gen_rtx_MEM (reg_mode, addr);
12215           set_mem_alias_set (mem, rs6000_sr_alias_set);
12216
12217           insn = emit_move_insn (mem, reg);
12218           rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12219                                 NULL_RTX, NULL_RTX);
12220           PATTERN (insn) = gen_blockage ();
12221         }
12222
12223       for (i = 0; ; ++i)
12224         {
12225           regno = EH_RETURN_DATA_REGNO (i);
12226           if (regno == INVALID_REGNUM)
12227             break;
12228
12229           emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12230                            info->ehrd_offset + sp_offset
12231                            + reg_size * (int) i,
12232                            info->total_size);
12233         }
12234     }
12235
12236   /* Save lr if we used it.  */
12237   if (info->lr_save_p)
12238     {
12239       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12240                                GEN_INT (info->lr_save_offset + sp_offset));
12241       rtx reg = gen_rtx_REG (Pmode, 0);
12242       rtx mem = gen_rtx_MEM (Pmode, addr);
12243       /* This should not be of rs6000_sr_alias_set, because of
12244          __builtin_return_address.  */
12245
12246       insn = emit_move_insn (mem, reg);
12247       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12248                             reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12249     }
12250
12251   /* Save CR if we use any that must be preserved.  */
12252   if (info->cr_save_p)
12253     {
12254       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12255                                GEN_INT (info->cr_save_offset + sp_offset));
12256       rtx mem = gen_rtx_MEM (SImode, addr);
12257
12258       set_mem_alias_set (mem, rs6000_sr_alias_set);
12259
12260       /* If r12 was used to hold the original sp, copy cr into r0 now
12261          that it's free.  */
12262       if (REGNO (frame_reg_rtx) == 12)
12263         {
12264           cr_save_rtx = gen_rtx_REG (SImode, 0);
12265           emit_insn (gen_movesi_from_cr (cr_save_rtx));
12266         }
12267       insn = emit_move_insn (mem, cr_save_rtx);
12268
12269       /* Now, there's no way that dwarf2out_frame_debug_expr is going
12270          to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12271          But that's OK.  All we have to do is specify that _one_ condition
12272          code register is saved in this stack slot.  The thrower's epilogue
12273          will then restore all the call-saved registers.
12274          We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux.  */
12275       rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12276                             cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
12277     }
12278
12279   /* Update stack and set back pointer unless this is V.4,
12280      for which it was done previously.  */
12281   if (info->push_p
12282       && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
12283     rs6000_emit_allocate_stack (info->total_size, FALSE);
12284
12285   /* Set frame pointer, if needed.  */
12286   if (frame_pointer_needed)
12287     {
12288       insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
12289                              sp_reg_rtx);
12290       RTX_FRAME_RELATED_P (insn) = 1;
12291     }
12292
12293   /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up.  */
12294   if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
12295       || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
12296           && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
12297   {
12298     /* If emit_load_toc_table will use the link register, we need to save
12299        it.  We use R12 for this purpose because emit_load_toc_table
12300        can use register 0.  This allows us to use a plain 'blr' to return
12301        from the procedure more often.  */
12302     int save_LR_around_toc_setup = (TARGET_ELF
12303                                     && DEFAULT_ABI != ABI_AIX
12304                                     && flag_pic
12305                                     && ! info->lr_save_p
12306                                     && EXIT_BLOCK_PTR->pred != NULL);
12307     if (save_LR_around_toc_setup)
12308       {
12309         rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12310         rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
12311         rs6000_emit_load_toc_table (TRUE);
12312         rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
12313       }
12314     else
12315       rs6000_emit_load_toc_table (TRUE);
12316   }
12317
12318 #if TARGET_MACHO
12319   if (DEFAULT_ABI == ABI_DARWIN
12320       && flag_pic && current_function_uses_pic_offset_table)
12321     {
12322       rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12323       const char *picbase = machopic_function_base_name ();
12324       rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
12325
12326       rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
12327
12328       rs6000_maybe_dead (
12329         emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
12330                         gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
12331     }
12332 #endif
12333 }
12334
12335 /* Write function prologue.  */
12336
12337 static void
12338 rs6000_output_function_prologue (FILE *file,
12339                                  HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12340 {
12341   rs6000_stack_t *info = rs6000_stack_info ();
12342
12343   if (TARGET_DEBUG_STACK)
12344     debug_stack_info (info);
12345
12346   /* Write .extern for any function we will call to save and restore
12347      fp values.  */
12348   if (info->first_fp_reg_save < 64
12349       && !FP_SAVE_INLINE (info->first_fp_reg_save))
12350     fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
12351              SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
12352              RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
12353              RESTORE_FP_SUFFIX);
12354
12355   /* Write .extern for AIX common mode routines, if needed.  */
12356   if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
12357     {
12358       fputs ("\t.extern __mulh\n", file);
12359       fputs ("\t.extern __mull\n", file);
12360       fputs ("\t.extern __divss\n", file);
12361       fputs ("\t.extern __divus\n", file);
12362       fputs ("\t.extern __quoss\n", file);
12363       fputs ("\t.extern __quous\n", file);
12364       common_mode_defined = 1;
12365     }
12366
12367   if (! HAVE_prologue)
12368     {
12369       start_sequence ();
12370
12371       /* A NOTE_INSN_DELETED is supposed to be at the start and end of
12372          the "toplevel" insn chain.  */
12373       emit_note (NOTE_INSN_DELETED);
12374       rs6000_emit_prologue ();
12375       emit_note (NOTE_INSN_DELETED);
12376
12377       /* Expand INSN_ADDRESSES so final() doesn't crash.  */
12378       {
12379         rtx insn;
12380         unsigned addr = 0;
12381         for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12382           {
12383             INSN_ADDRESSES_NEW (insn, addr);
12384             addr += 4;
12385           }
12386       }
12387
12388       if (TARGET_DEBUG_STACK)
12389         debug_rtx_list (get_insns (), 100);
12390       final (get_insns (), file, FALSE, FALSE);
12391       end_sequence ();
12392     }
12393
12394   rs6000_pic_labelno++;
12395 }
12396
12397 /* Emit function epilogue as insns.
12398
12399    At present, dwarf2out_frame_debug_expr doesn't understand
12400    register restores, so we don't bother setting RTX_FRAME_RELATED_P
12401    anywhere in the epilogue.  Most of the insns below would in any case
12402    need special notes to explain where r11 is in relation to the stack.  */
12403
12404 void
12405 rs6000_emit_epilogue (int sibcall)
12406 {
12407   rs6000_stack_t *info;
12408   int restoring_FPRs_inline;
12409   int using_load_multiple;
12410   int using_mfcr_multiple;
12411   int use_backchain_to_restore_sp;
12412   int sp_offset = 0;
12413   rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12414   rtx frame_reg_rtx = sp_reg_rtx;
12415   enum machine_mode reg_mode = Pmode;
12416   int reg_size = TARGET_32BIT ? 4 : 8;
12417   int i;
12418
12419   info = rs6000_stack_info ();
12420
12421   if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12422     {
12423       reg_mode = V2SImode;
12424       reg_size = 8;
12425     }
12426
12427   using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12428                          && (!TARGET_SPE_ABI
12429                              || info->spe_64bit_regs_used == 0)
12430                          && info->first_gp_reg_save < 31);
12431   restoring_FPRs_inline = (sibcall
12432                            || current_function_calls_eh_return
12433                            || info->first_fp_reg_save == 64
12434                            || FP_SAVE_INLINE (info->first_fp_reg_save));
12435   use_backchain_to_restore_sp = (frame_pointer_needed
12436                                  || current_function_calls_alloca
12437                                  || info->total_size > 32767);
12438   using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12439                          || rs6000_cpu == PROCESSOR_PPC603
12440                          || rs6000_cpu == PROCESSOR_PPC750
12441                          || optimize_size);
12442
12443   /* If we have a frame pointer, a call to alloca,  or a large stack
12444      frame, restore the old stack pointer using the backchain.  Otherwise,
12445      we know what size to update it with.  */
12446   if (use_backchain_to_restore_sp)
12447     {
12448       /* Under V.4, don't reset the stack pointer until after we're done
12449          loading the saved registers.  */
12450       if (DEFAULT_ABI == ABI_V4)
12451         frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12452
12453       emit_move_insn (frame_reg_rtx,
12454                       gen_rtx_MEM (Pmode, sp_reg_rtx));
12455
12456     }
12457   else if (info->push_p)
12458     {
12459       if (DEFAULT_ABI == ABI_V4
12460           || current_function_calls_eh_return)
12461         sp_offset = info->total_size;
12462       else
12463         {
12464           emit_insn (TARGET_32BIT
12465                      ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12466                                    GEN_INT (info->total_size))
12467                      : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12468                                    GEN_INT (info->total_size)));
12469         }
12470     }
12471
12472   /* Restore AltiVec registers if needed.  */
12473   if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12474     {
12475       int i;
12476
12477       for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12478         if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12479           {
12480             rtx addr, areg, mem;
12481
12482             areg = gen_rtx_REG (Pmode, 0);
12483             emit_move_insn
12484               (areg, GEN_INT (info->altivec_save_offset
12485                               + sp_offset
12486                               + 16 * (i - info->first_altivec_reg_save)));
12487
12488             /* AltiVec addressing mode is [reg+reg].  */
12489             addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12490             mem = gen_rtx_MEM (V4SImode, addr);
12491             set_mem_alias_set (mem, rs6000_sr_alias_set);
12492
12493             emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12494           }
12495     }
12496
12497   /* Restore VRSAVE if needed.  */
12498   if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE
12499       && info->vrsave_mask != 0)
12500     {
12501       rtx addr, mem, reg;
12502
12503       addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12504                            GEN_INT (info->vrsave_save_offset + sp_offset));
12505       mem = gen_rtx_MEM (SImode, addr);
12506       set_mem_alias_set (mem, rs6000_sr_alias_set);
12507       reg = gen_rtx_REG (SImode, 12);
12508       emit_move_insn (reg, mem);
12509
12510       emit_insn (generate_set_vrsave (reg, info, 1));
12511     }
12512
12513   /* Get the old lr if we saved it.  */
12514   if (info->lr_save_p)
12515     {
12516       rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12517                                       info->lr_save_offset + sp_offset);
12518
12519       set_mem_alias_set (mem, rs6000_sr_alias_set);
12520
12521       emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12522     }
12523
12524   /* Get the old cr if we saved it.  */
12525   if (info->cr_save_p)
12526     {
12527       rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12528                                GEN_INT (info->cr_save_offset + sp_offset));
12529       rtx mem = gen_rtx_MEM (SImode, addr);
12530
12531       set_mem_alias_set (mem, rs6000_sr_alias_set);
12532
12533       emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12534     }
12535
12536   /* Set LR here to try to overlap restores below.  */
12537   if (info->lr_save_p)
12538     emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12539                     gen_rtx_REG (Pmode, 0));
12540
12541   /* Load exception handler data registers, if needed.  */
12542   if (current_function_calls_eh_return)
12543     {
12544       unsigned int i, regno;
12545
12546       if (TARGET_AIX)
12547         {
12548           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12549                                    GEN_INT (sp_offset + 5 * reg_size));
12550           rtx mem = gen_rtx_MEM (reg_mode, addr);
12551
12552           set_mem_alias_set (mem, rs6000_sr_alias_set);
12553
12554           emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12555         }
12556
12557       for (i = 0; ; ++i)
12558         {
12559           rtx mem;
12560
12561           regno = EH_RETURN_DATA_REGNO (i);
12562           if (regno == INVALID_REGNUM)
12563             break;
12564
12565           mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12566                                       info->ehrd_offset + sp_offset
12567                                       + reg_size * (int) i);
12568           set_mem_alias_set (mem, rs6000_sr_alias_set);
12569
12570           emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12571         }
12572     }
12573
12574   /* Restore GPRs.  This is done as a PARALLEL if we are using
12575      the load-multiple instructions.  */
12576   if (using_load_multiple)
12577     {
12578       rtvec p;
12579       p = rtvec_alloc (32 - info->first_gp_reg_save);
12580       for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12581         {
12582           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12583                                    GEN_INT (info->gp_save_offset
12584                                             + sp_offset
12585                                             + reg_size * i));
12586           rtx mem = gen_rtx_MEM (reg_mode, addr);
12587
12588           set_mem_alias_set (mem, rs6000_sr_alias_set);
12589
12590           RTVEC_ELT (p, i) =
12591             gen_rtx_SET (VOIDmode,
12592                          gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12593                          mem);
12594         }
12595       emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12596     }
12597   else
12598     for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12599       if ((regs_ever_live[info->first_gp_reg_save+i]
12600            && ! call_used_regs[info->first_gp_reg_save+i])
12601           || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12602               && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12603                   || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12604         {
12605           rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12606                                    GEN_INT (info->gp_save_offset
12607                                             + sp_offset
12608                                             + reg_size * i));
12609           rtx mem = gen_rtx_MEM (reg_mode, addr);
12610
12611           /* Restore 64-bit quantities for SPE.  */
12612           if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12613             {
12614               int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12615               rtx b;
12616
12617               if (!SPE_CONST_OFFSET_OK (offset))
12618                 {
12619                   b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12620                   emit_move_insn (b, GEN_INT (offset));
12621                 }
12622               else
12623                 b = GEN_INT (offset);
12624
12625               addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12626               mem = gen_rtx_MEM (V2SImode, addr);
12627             }
12628
12629           set_mem_alias_set (mem, rs6000_sr_alias_set);
12630
12631           emit_move_insn (gen_rtx_REG (reg_mode,
12632                                        info->first_gp_reg_save + i), mem);
12633         }
12634
12635   /* Restore fpr's if we need to do it without calling a function.  */
12636   if (restoring_FPRs_inline)
12637     for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12638       if ((regs_ever_live[info->first_fp_reg_save+i]
12639            && ! call_used_regs[info->first_fp_reg_save+i]))
12640         {
12641           rtx addr, mem;
12642           addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12643                                GEN_INT (info->fp_save_offset
12644                                         + sp_offset
12645                                         + 8 * i));
12646           mem = gen_rtx_MEM (DFmode, addr);
12647           set_mem_alias_set (mem, rs6000_sr_alias_set);
12648
12649           emit_move_insn (gen_rtx_REG (DFmode,
12650                                        info->first_fp_reg_save + i),
12651                           mem);
12652         }
12653
12654   /* If we saved cr, restore it here.  Just those that were used.  */
12655   if (info->cr_save_p)
12656     {
12657       rtx r12_rtx = gen_rtx_REG (SImode, 12);
12658       int count = 0;
12659
12660       if (using_mfcr_multiple)
12661         {
12662           for (i = 0; i < 8; i++)
12663             if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12664               count++;
12665           if (count == 0)
12666             abort ();
12667         }
12668
12669       if (using_mfcr_multiple && count > 1)
12670         {
12671           rtvec p;
12672           int ndx;
12673
12674           p = rtvec_alloc (count);
12675
12676           ndx = 0;
12677           for (i = 0; i < 8; i++)
12678             if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12679               {
12680                 rtvec r = rtvec_alloc (2);
12681                 RTVEC_ELT (r, 0) = r12_rtx;
12682                 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12683                 RTVEC_ELT (p, ndx) =
12684                   gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12685                                gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12686                 ndx++;
12687               }
12688           emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12689           if (ndx != count)
12690             abort ();
12691         }
12692       else
12693         for (i = 0; i < 8; i++)
12694           if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12695             {
12696               emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12697                                                            CR0_REGNO+i),
12698                                               r12_rtx));
12699             }
12700     }
12701
12702   /* If this is V.4, unwind the stack pointer after all of the loads
12703      have been done.  We need to emit a block here so that sched
12704      doesn't decide to move the sp change before the register restores
12705      (which may not have any obvious dependency on the stack).  This
12706      doesn't hurt performance, because there is no scheduling that can
12707      be done after this point.  */
12708   if (DEFAULT_ABI == ABI_V4
12709       || current_function_calls_eh_return)
12710     {
12711       if (frame_reg_rtx != sp_reg_rtx)
12712           rs6000_emit_stack_tie ();
12713
12714       if (use_backchain_to_restore_sp)
12715         {
12716           emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12717         }
12718       else if (sp_offset != 0)
12719         {
12720           emit_insn (TARGET_32BIT
12721                      ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12722                                    GEN_INT (sp_offset))
12723                      : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12724                                    GEN_INT (sp_offset)));
12725         }
12726     }
12727
12728   if (current_function_calls_eh_return)
12729     {
12730       rtx sa = EH_RETURN_STACKADJ_RTX;
12731       emit_insn (TARGET_32BIT
12732                  ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12733                  : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12734     }
12735
12736   if (!sibcall)
12737     {
12738       rtvec p;
12739       if (! restoring_FPRs_inline)
12740         p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12741       else
12742         p = rtvec_alloc (2);
12743
12744       RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12745       RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12746                                       gen_rtx_REG (Pmode,
12747                                                    LINK_REGISTER_REGNUM));
12748
12749       /* If we have to restore more than two FP registers, branch to the
12750          restore function.  It will return to our caller.  */
12751       if (! restoring_FPRs_inline)
12752         {
12753           int i;
12754           char rname[30];
12755           const char *alloc_rname;
12756
12757           sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12758                    info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12759           alloc_rname = ggc_strdup (rname);
12760           RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12761                                           gen_rtx_SYMBOL_REF (Pmode,
12762                                                               alloc_rname));
12763
12764           for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12765             {
12766               rtx addr, mem;
12767               addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12768                                    GEN_INT (info->fp_save_offset + 8*i));
12769               mem = gen_rtx_MEM (DFmode, addr);
12770               set_mem_alias_set (mem, rs6000_sr_alias_set);
12771
12772               RTVEC_ELT (p, i+3) =
12773                 gen_rtx_SET (VOIDmode,
12774                              gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12775                              mem);
12776             }
12777         }
12778
12779       emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12780     }
12781 }
12782
12783 /* Write function epilogue.  */
12784
12785 static void
12786 rs6000_output_function_epilogue (FILE *file,
12787                                  HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12788 {
12789   rs6000_stack_t *info = rs6000_stack_info ();
12790
12791   if (! HAVE_epilogue)
12792     {
12793       rtx insn = get_last_insn ();
12794       /* If the last insn was a BARRIER, we don't have to write anything except
12795          the trace table.  */
12796       if (GET_CODE (insn) == NOTE)
12797         insn = prev_nonnote_insn (insn);
12798       if (insn == 0 ||  GET_CODE (insn) != BARRIER)
12799         {
12800           /* This is slightly ugly, but at least we don't have two
12801              copies of the epilogue-emitting code.  */
12802           start_sequence ();
12803
12804           /* A NOTE_INSN_DELETED is supposed to be at the start
12805              and end of the "toplevel" insn chain.  */
12806           emit_note (NOTE_INSN_DELETED);
12807           rs6000_emit_epilogue (FALSE);
12808           emit_note (NOTE_INSN_DELETED);
12809
12810           /* Expand INSN_ADDRESSES so final() doesn't crash.  */
12811           {
12812             rtx insn;
12813             unsigned addr = 0;
12814             for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12815               {
12816                 INSN_ADDRESSES_NEW (insn, addr);
12817                 addr += 4;
12818               }
12819           }
12820
12821           if (TARGET_DEBUG_STACK)
12822             debug_rtx_list (get_insns (), 100);
12823           final (get_insns (), file, FALSE, FALSE);
12824           end_sequence ();
12825         }
12826     }
12827
12828 #if TARGET_MACHO
12829   macho_branch_islands ();
12830   /* Mach-O doesn't support labels at the end of objects, so if
12831      it looks like we might want one, insert a NOP.  */
12832   {
12833     rtx insn = get_last_insn ();
12834     while (insn
12835            && NOTE_P (insn)
12836            && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12837       insn = PREV_INSN (insn);
12838     if (insn
12839         && (LABEL_P (insn)
12840             || (NOTE_P (insn)
12841                 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12842       fputs ("\tnop\n", file);
12843   }
12844 #endif
12845
12846   /* Output a traceback table here.  See /usr/include/sys/debug.h for info
12847      on its format.
12848
12849      We don't output a traceback table if -finhibit-size-directive was
12850      used.  The documentation for -finhibit-size-directive reads
12851      ``don't output a @code{.size} assembler directive, or anything
12852      else that would cause trouble if the function is split in the
12853      middle, and the two halves are placed at locations far apart in
12854      memory.''  The traceback table has this property, since it
12855      includes the offset from the start of the function to the
12856      traceback table itself.
12857
12858      System V.4 Powerpc's (and the embedded ABI derived from it) use a
12859      different traceback table.  */
12860   if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12861       && rs6000_traceback != traceback_none)
12862     {
12863       const char *fname = NULL;
12864       const char *language_string = lang_hooks.name;
12865       int fixed_parms = 0, float_parms = 0, parm_info = 0;
12866       int i;
12867       int optional_tbtab;
12868
12869       if (rs6000_traceback == traceback_full)
12870         optional_tbtab = 1;
12871       else if (rs6000_traceback == traceback_part)
12872         optional_tbtab = 0;
12873       else
12874         optional_tbtab = !optimize_size && !TARGET_ELF;
12875
12876       if (optional_tbtab)
12877         {
12878           fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12879           while (*fname == '.') /* V.4 encodes . in the name */
12880             fname++;
12881
12882           /* Need label immediately before tbtab, so we can compute
12883              its offset from the function start.  */
12884           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12885           ASM_OUTPUT_LABEL (file, fname);
12886         }
12887
12888       /* The .tbtab pseudo-op can only be used for the first eight
12889          expressions, since it can't handle the possibly variable
12890          length fields that follow.  However, if you omit the optional
12891          fields, the assembler outputs zeros for all optional fields
12892          anyways, giving each variable length field is minimum length
12893          (as defined in sys/debug.h).  Thus we can not use the .tbtab
12894          pseudo-op at all.  */
12895
12896       /* An all-zero word flags the start of the tbtab, for debuggers
12897          that have to find it by searching forward from the entry
12898          point or from the current pc.  */
12899       fputs ("\t.long 0\n", file);
12900
12901       /* Tbtab format type.  Use format type 0.  */
12902       fputs ("\t.byte 0,", file);
12903
12904       /* Language type.  Unfortunately, there does not seem to be any
12905          official way to discover the language being compiled, so we
12906          use language_string.
12907          C is 0.  Fortran is 1.  Pascal is 2.  Ada is 3.  C++ is 9.
12908          Java is 13.  Objective-C is 14.  */
12909       if (! strcmp (language_string, "GNU C"))
12910         i = 0;
12911       else if (! strcmp (language_string, "GNU F77"))
12912         i = 1;
12913       else if (! strcmp (language_string, "GNU Pascal"))
12914         i = 2;
12915       else if (! strcmp (language_string, "GNU Ada"))
12916         i = 3;
12917       else if (! strcmp (language_string, "GNU C++"))
12918         i = 9;
12919       else if (! strcmp (language_string, "GNU Java"))
12920         i = 13;
12921       else if (! strcmp (language_string, "GNU Objective-C"))
12922         i = 14;
12923       else
12924         abort ();
12925       fprintf (file, "%d,", i);
12926
12927       /* 8 single bit fields: global linkage (not set for C extern linkage,
12928          apparently a PL/I convention?), out-of-line epilogue/prologue, offset
12929          from start of procedure stored in tbtab, internal function, function
12930          has controlled storage, function has no toc, function uses fp,
12931          function logs/aborts fp operations.  */
12932       /* Assume that fp operations are used if any fp reg must be saved.  */
12933       fprintf (file, "%d,",
12934                (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
12935
12936       /* 6 bitfields: function is interrupt handler, name present in
12937          proc table, function calls alloca, on condition directives
12938          (controls stack walks, 3 bits), saves condition reg, saves
12939          link reg.  */
12940       /* The `function calls alloca' bit seems to be set whenever reg 31 is
12941          set up as a frame pointer, even when there is no alloca call.  */
12942       fprintf (file, "%d,",
12943                ((optional_tbtab << 6)
12944                 | ((optional_tbtab & frame_pointer_needed) << 5)
12945                 | (info->cr_save_p << 1)
12946                 | (info->lr_save_p)));
12947
12948       /* 3 bitfields: saves backchain, fixup code, number of fpr saved
12949          (6 bits).  */
12950       fprintf (file, "%d,",
12951                (info->push_p << 7) | (64 - info->first_fp_reg_save));
12952
12953       /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits).  */
12954       fprintf (file, "%d,", (32 - first_reg_to_save ()));
12955
12956       if (optional_tbtab)
12957         {
12958           /* Compute the parameter info from the function decl argument
12959              list.  */
12960           tree decl;
12961           int next_parm_info_bit = 31;
12962
12963           for (decl = DECL_ARGUMENTS (current_function_decl);
12964                decl; decl = TREE_CHAIN (decl))
12965             {
12966               rtx parameter = DECL_INCOMING_RTL (decl);
12967               enum machine_mode mode = GET_MODE (parameter);
12968
12969               if (GET_CODE (parameter) == REG)
12970                 {
12971                   if (GET_MODE_CLASS (mode) == MODE_FLOAT)
12972                     {
12973                       int bits;
12974
12975                       float_parms++;
12976
12977                       if (mode == SFmode)
12978                         bits = 0x2;
12979                       else if (mode == DFmode || mode == TFmode)
12980                         bits = 0x3;
12981                       else
12982                         abort ();
12983
12984                       /* If only one bit will fit, don't or in this entry.  */
12985                       if (next_parm_info_bit > 0)
12986                         parm_info |= (bits << (next_parm_info_bit - 1));
12987                       next_parm_info_bit -= 2;
12988                     }
12989                   else
12990                     {
12991                       fixed_parms += ((GET_MODE_SIZE (mode)
12992                                        + (UNITS_PER_WORD - 1))
12993                                       / UNITS_PER_WORD);
12994                       next_parm_info_bit -= 1;
12995                     }
12996                 }
12997             }
12998         }
12999
13000       /* Number of fixed point parameters.  */
13001       /* This is actually the number of words of fixed point parameters; thus
13002          an 8 byte struct counts as 2; and thus the maximum value is 8.  */
13003       fprintf (file, "%d,", fixed_parms);
13004
13005       /* 2 bitfields: number of floating point parameters (7 bits), parameters
13006          all on stack.  */
13007       /* This is actually the number of fp registers that hold parameters;
13008          and thus the maximum value is 13.  */
13009       /* Set parameters on stack bit if parameters are not in their original
13010          registers, regardless of whether they are on the stack?  Xlc
13011          seems to set the bit when not optimizing.  */
13012       fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13013
13014       if (! optional_tbtab)
13015         return;
13016
13017       /* Optional fields follow.  Some are variable length.  */
13018
13019       /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13020          11 double float.  */
13021       /* There is an entry for each parameter in a register, in the order that
13022          they occur in the parameter list.  Any intervening arguments on the
13023          stack are ignored.  If the list overflows a long (max possible length
13024          34 bits) then completely leave off all elements that don't fit.  */
13025       /* Only emit this long if there was at least one parameter.  */
13026       if (fixed_parms || float_parms)
13027         fprintf (file, "\t.long %d\n", parm_info);
13028
13029       /* Offset from start of code to tb table.  */
13030       fputs ("\t.long ", file);
13031       ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13032 #if TARGET_AIX
13033       RS6000_OUTPUT_BASENAME (file, fname);
13034 #else
13035       assemble_name (file, fname);
13036 #endif
13037       fputs ("-.", file);
13038 #if TARGET_AIX
13039       RS6000_OUTPUT_BASENAME (file, fname);
13040 #else
13041       assemble_name (file, fname);
13042 #endif
13043       putc ('\n', file);
13044
13045       /* Interrupt handler mask.  */
13046       /* Omit this long, since we never set the interrupt handler bit
13047          above.  */
13048
13049       /* Number of CTL (controlled storage) anchors.  */
13050       /* Omit this long, since the has_ctl bit is never set above.  */
13051
13052       /* Displacement into stack of each CTL anchor.  */
13053       /* Omit this list of longs, because there are no CTL anchors.  */
13054
13055       /* Length of function name.  */
13056       if (*fname == '*')
13057         ++fname;
13058       fprintf (file, "\t.short %d\n", (int) strlen (fname));
13059
13060       /* Function name.  */
13061       assemble_string (fname, strlen (fname));
13062
13063       /* Register for alloca automatic storage; this is always reg 31.
13064          Only emit this if the alloca bit was set above.  */
13065       if (frame_pointer_needed)
13066         fputs ("\t.byte 31\n", file);
13067
13068       fputs ("\t.align 2\n", file);
13069     }
13070 }
13071 \f
13072 /* A C compound statement that outputs the assembler code for a thunk
13073    function, used to implement C++ virtual function calls with
13074    multiple inheritance.  The thunk acts as a wrapper around a virtual
13075    function, adjusting the implicit object parameter before handing
13076    control off to the real function.
13077
13078    First, emit code to add the integer DELTA to the location that
13079    contains the incoming first argument.  Assume that this argument
13080    contains a pointer, and is the one used to pass the `this' pointer
13081    in C++.  This is the incoming argument *before* the function
13082    prologue, e.g. `%o0' on a sparc.  The addition must preserve the
13083    values of all other incoming arguments.
13084
13085    After the addition, emit code to jump to FUNCTION, which is a
13086    `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does
13087    not touch the return address.  Hence returning from FUNCTION will
13088    return to whoever called the current `thunk'.
13089
13090    The effect must be as if FUNCTION had been called directly with the
13091    adjusted first argument.  This macro is responsible for emitting
13092    all of the code for a thunk function; output_function_prologue()
13093    and output_function_epilogue() are not invoked.
13094
13095    The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already
13096    been extracted from it.)  It might possibly be useful on some
13097    targets, but probably not.
13098
13099    If you do not define this macro, the target-independent code in the
13100    C++ frontend will generate a less efficient heavyweight thunk that
13101    calls FUNCTION instead of jumping to it.  The generic approach does
13102    not support varargs.  */
13103
13104 static void
13105 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13106                         HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13107                         tree function)
13108 {
13109   rtx this, insn, funexp;
13110
13111   reload_completed = 1;
13112   epilogue_completed = 1;
13113   no_new_pseudos = 1;
13114
13115   /* Mark the end of the (empty) prologue.  */
13116   emit_note (NOTE_INSN_PROLOGUE_END);
13117
13118   /* Find the "this" pointer.  If the function returns a structure,
13119      the structure return pointer is in r3.  */
13120   if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13121     this = gen_rtx_REG (Pmode, 4);
13122   else
13123     this = gen_rtx_REG (Pmode, 3);
13124
13125   /* Apply the constant offset, if required.  */
13126   if (delta)
13127     {
13128       rtx delta_rtx = GEN_INT (delta);
13129       emit_insn (TARGET_32BIT
13130                  ? gen_addsi3 (this, this, delta_rtx)
13131                  : gen_adddi3 (this, this, delta_rtx));
13132     }
13133
13134   /* Apply the offset from the vtable, if required.  */
13135   if (vcall_offset)
13136     {
13137       rtx vcall_offset_rtx = GEN_INT (vcall_offset);
13138       rtx tmp = gen_rtx_REG (Pmode, 12);
13139
13140       emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
13141       if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
13142         {
13143           emit_insn (TARGET_32BIT
13144                      ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
13145                      : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
13146           emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
13147         }
13148       else
13149         {
13150           rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
13151
13152           emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
13153         }
13154       emit_insn (TARGET_32BIT
13155                  ? gen_addsi3 (this, this, tmp)
13156                  : gen_adddi3 (this, this, tmp));
13157     }
13158
13159   /* Generate a tail call to the target function.  */
13160   if (!TREE_USED (function))
13161     {
13162       assemble_external (function);
13163       TREE_USED (function) = 1;
13164     }
13165   funexp = XEXP (DECL_RTL (function), 0);
13166   funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
13167
13168 #if TARGET_MACHO
13169   if (MACHOPIC_INDIRECT)
13170     funexp = machopic_indirect_call_target (funexp);
13171 #endif
13172
13173   /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
13174      generate sibcall RTL explicitly to avoid constraint abort.  */
13175   insn = emit_call_insn (
13176            gen_rtx_PARALLEL (VOIDmode,
13177              gen_rtvec (4,
13178                         gen_rtx_CALL (VOIDmode,
13179                                       funexp, const0_rtx),
13180                         gen_rtx_USE (VOIDmode, const0_rtx),
13181                         gen_rtx_USE (VOIDmode,
13182                                      gen_rtx_REG (SImode,
13183                                                   LINK_REGISTER_REGNUM)),
13184                         gen_rtx_RETURN (VOIDmode))));
13185   SIBLING_CALL_P (insn) = 1;
13186   emit_barrier ();
13187
13188   /* Run just enough of rest_of_compilation to get the insns emitted.
13189      There's not really enough bulk here to make other passes such as
13190      instruction scheduling worth while.  Note that use_thunk calls
13191      assemble_start_function and assemble_end_function.  */
13192   insn = get_insns ();
13193   insn_locators_initialize ();
13194   shorten_branches (insn);
13195   final_start_function (insn, file, 1);
13196   final (insn, file, 1, 0);
13197   final_end_function ();
13198
13199   reload_completed = 0;
13200   epilogue_completed = 0;
13201   no_new_pseudos = 0;
13202 }
13203 \f
13204 /* A quick summary of the various types of 'constant-pool tables'
13205    under PowerPC:
13206
13207    Target       Flags           Name            One table per
13208    AIX          (none)          AIX TOC         object file
13209    AIX          -mfull-toc      AIX TOC         object file
13210    AIX          -mminimal-toc   AIX minimal TOC translation unit
13211    SVR4/EABI    (none)          SVR4 SDATA      object file
13212    SVR4/EABI    -fpic           SVR4 pic        object file
13213    SVR4/EABI    -fPIC           SVR4 PIC        translation unit
13214    SVR4/EABI    -mrelocatable   EABI TOC        function
13215    SVR4/EABI    -maix           AIX TOC         object file
13216    SVR4/EABI    -maix -mminimal-toc
13217                                 AIX minimal TOC translation unit
13218
13219    Name                 Reg.    Set by  entries       contains:
13220                                         made by  addrs? fp?     sum?
13221
13222    AIX TOC              2       crt0    as       Y      option  option
13223    AIX minimal TOC      30      prolog  gcc      Y      Y       option
13224    SVR4 SDATA           13      crt0    gcc      N      Y       N
13225    SVR4 pic             30      prolog  ld       Y      not yet N
13226    SVR4 PIC             30      prolog  gcc      Y      option  option
13227    EABI TOC             30      prolog  gcc      Y      option  option
13228
13229 */
13230
13231 /* Hash functions for the hash table.  */
13232
13233 static unsigned
13234 rs6000_hash_constant (rtx k)
13235 {
13236   enum rtx_code code = GET_CODE (k);
13237   enum machine_mode mode = GET_MODE (k);
13238   unsigned result = (code << 3) ^ mode;
13239   const char *format;
13240   int flen, fidx;
13241
13242   format = GET_RTX_FORMAT (code);
13243   flen = strlen (format);
13244   fidx = 0;
13245
13246   switch (code)
13247     {
13248     case LABEL_REF:
13249       return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
13250
13251     case CONST_DOUBLE:
13252       if (mode != VOIDmode)
13253         return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
13254       flen = 2;
13255       break;
13256
13257     case CODE_LABEL:
13258       fidx = 3;
13259       break;
13260
13261     default:
13262       break;
13263     }
13264
13265   for (; fidx < flen; fidx++)
13266     switch (format[fidx])
13267       {
13268       case 's':
13269         {
13270           unsigned i, len;
13271           const char *str = XSTR (k, fidx);
13272           len = strlen (str);
13273           result = result * 613 + len;
13274           for (i = 0; i < len; i++)
13275             result = result * 613 + (unsigned) str[i];
13276           break;
13277         }
13278       case 'u':
13279       case 'e':
13280         result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
13281         break;
13282       case 'i':
13283       case 'n':
13284         result = result * 613 + (unsigned) XINT (k, fidx);
13285         break;
13286       case 'w':
13287         if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
13288           result = result * 613 + (unsigned) XWINT (k, fidx);
13289         else
13290           {
13291             size_t i;
13292             for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
13293               result = result * 613 + (unsigned) (XWINT (k, fidx)
13294                                                   >> CHAR_BIT * i);
13295           }
13296         break;
13297       case '0':
13298         break;
13299       default:
13300         abort ();
13301       }
13302
13303   return result;
13304 }
13305
13306 static unsigned
13307 toc_hash_function (const void *hash_entry)
13308 {
13309   const struct toc_hash_struct *thc =
13310     (const struct toc_hash_struct *) hash_entry;
13311   return rs6000_hash_constant (thc->key) ^ thc->key_mode;
13312 }
13313
13314 /* Compare H1 and H2 for equivalence.  */
13315
13316 static int
13317 toc_hash_eq (const void *h1, const void *h2)
13318 {
13319   rtx r1 = ((const struct toc_hash_struct *) h1)->key;
13320   rtx r2 = ((const struct toc_hash_struct *) h2)->key;
13321
13322   if (((const struct toc_hash_struct *) h1)->key_mode
13323       != ((const struct toc_hash_struct *) h2)->key_mode)
13324     return 0;
13325
13326   return rtx_equal_p (r1, r2);
13327 }
13328
13329 /* These are the names given by the C++ front-end to vtables, and
13330    vtable-like objects.  Ideally, this logic should not be here;
13331    instead, there should be some programmatic way of inquiring as
13332    to whether or not an object is a vtable.  */
13333
13334 #define VTABLE_NAME_P(NAME)                             \
13335   (strncmp ("_vt.", name, strlen("_vt.")) == 0          \
13336   || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0       \
13337   || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0       \
13338   || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0       \
13339   || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
13340
13341 void
13342 rs6000_output_symbol_ref (FILE *file, rtx x)
13343 {
13344   /* Currently C++ toc references to vtables can be emitted before it
13345      is decided whether the vtable is public or private.  If this is
13346      the case, then the linker will eventually complain that there is
13347      a reference to an unknown section.  Thus, for vtables only,
13348      we emit the TOC reference to reference the symbol and not the
13349      section.  */
13350   const char *name = XSTR (x, 0);
13351
13352   if (VTABLE_NAME_P (name))
13353     {
13354       RS6000_OUTPUT_BASENAME (file, name);
13355     }
13356   else
13357     assemble_name (file, name);
13358 }
13359
13360 /* Output a TOC entry.  We derive the entry name from what is being
13361    written.  */
13362
13363 void
13364 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
13365 {
13366   char buf[256];
13367   const char *name = buf;
13368   const char *real_name;
13369   rtx base = x;
13370   int offset = 0;
13371
13372   if (TARGET_NO_TOC)
13373     abort ();
13374
13375   /* When the linker won't eliminate them, don't output duplicate
13376      TOC entries (this happens on AIX if there is any kind of TOC,
13377      and on SVR4 under -fPIC or -mrelocatable).  Don't do this for
13378      CODE_LABELs.  */
13379   if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
13380     {
13381       struct toc_hash_struct *h;
13382       void * * found;
13383
13384       /* Create toc_hash_table.  This can't be done at OVERRIDE_OPTIONS
13385          time because GGC is not initialized at that point.  */
13386       if (toc_hash_table == NULL)
13387         toc_hash_table = htab_create_ggc (1021, toc_hash_function,
13388                                           toc_hash_eq, NULL);
13389
13390       h = ggc_alloc (sizeof (*h));
13391       h->key = x;
13392       h->key_mode = mode;
13393       h->labelno = labelno;
13394
13395       found = htab_find_slot (toc_hash_table, h, 1);
13396       if (*found == NULL)
13397         *found = h;
13398       else  /* This is indeed a duplicate.
13399                Set this label equal to that label.  */
13400         {
13401           fputs ("\t.set ", file);
13402           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13403           fprintf (file, "%d,", labelno);
13404           ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
13405           fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
13406                                               found)->labelno));
13407           return;
13408         }
13409     }
13410
13411   /* If we're going to put a double constant in the TOC, make sure it's
13412      aligned properly when strict alignment is on.  */
13413   if (GET_CODE (x) == CONST_DOUBLE
13414       && STRICT_ALIGNMENT
13415       && GET_MODE_BITSIZE (mode) >= 64
13416       && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13417     ASM_OUTPUT_ALIGN (file, 3);
13418   }
13419
13420   (*targetm.asm_out.internal_label) (file, "LC", labelno);
13421
13422   /* Handle FP constants specially.  Note that if we have a minimal
13423      TOC, things we put here aren't actually in the TOC, so we can allow
13424      FP constants.  */
13425   if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13426     {
13427       REAL_VALUE_TYPE rv;
13428       long k[4];
13429
13430       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13431       REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13432
13433       if (TARGET_64BIT)
13434         {
13435           if (TARGET_MINIMAL_TOC)
13436             fputs (DOUBLE_INT_ASM_OP, file);
13437           else
13438             fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13439                      k[0] & 0xffffffff, k[1] & 0xffffffff,
13440                      k[2] & 0xffffffff, k[3] & 0xffffffff);
13441           fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13442                    k[0] & 0xffffffff, k[1] & 0xffffffff,
13443                    k[2] & 0xffffffff, k[3] & 0xffffffff);
13444           return;
13445         }
13446       else
13447         {
13448           if (TARGET_MINIMAL_TOC)
13449             fputs ("\t.long ", file);
13450           else
13451             fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13452                      k[0] & 0xffffffff, k[1] & 0xffffffff,
13453                      k[2] & 0xffffffff, k[3] & 0xffffffff);
13454           fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13455                    k[0] & 0xffffffff, k[1] & 0xffffffff,
13456                    k[2] & 0xffffffff, k[3] & 0xffffffff);
13457           return;
13458         }
13459     }
13460   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13461     {
13462       REAL_VALUE_TYPE rv;
13463       long k[2];
13464
13465       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13466       REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13467
13468       if (TARGET_64BIT)
13469         {
13470           if (TARGET_MINIMAL_TOC)
13471             fputs (DOUBLE_INT_ASM_OP, file);
13472           else
13473             fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13474                      k[0] & 0xffffffff, k[1] & 0xffffffff);
13475           fprintf (file, "0x%lx%08lx\n",
13476                    k[0] & 0xffffffff, k[1] & 0xffffffff);
13477           return;
13478         }
13479       else
13480         {
13481           if (TARGET_MINIMAL_TOC)
13482             fputs ("\t.long ", file);
13483           else
13484             fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13485                      k[0] & 0xffffffff, k[1] & 0xffffffff);
13486           fprintf (file, "0x%lx,0x%lx\n",
13487                    k[0] & 0xffffffff, k[1] & 0xffffffff);
13488           return;
13489         }
13490     }
13491   else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13492     {
13493       REAL_VALUE_TYPE rv;
13494       long l;
13495
13496       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13497       REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13498
13499       if (TARGET_64BIT)
13500         {
13501           if (TARGET_MINIMAL_TOC)
13502             fputs (DOUBLE_INT_ASM_OP, file);
13503           else
13504             fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13505           fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13506           return;
13507         }
13508       else
13509         {
13510           if (TARGET_MINIMAL_TOC)
13511             fputs ("\t.long ", file);
13512           else
13513             fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13514           fprintf (file, "0x%lx\n", l & 0xffffffff);
13515           return;
13516         }
13517     }
13518   else if (GET_MODE (x) == VOIDmode
13519            && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13520     {
13521       unsigned HOST_WIDE_INT low;
13522       HOST_WIDE_INT high;
13523
13524       if (GET_CODE (x) == CONST_DOUBLE)
13525         {
13526           low = CONST_DOUBLE_LOW (x);
13527           high = CONST_DOUBLE_HIGH (x);
13528         }
13529       else
13530 #if HOST_BITS_PER_WIDE_INT == 32
13531         {
13532           low = INTVAL (x);
13533           high = (low & 0x80000000) ? ~0 : 0;
13534         }
13535 #else
13536         {
13537           low = INTVAL (x) & 0xffffffff;
13538           high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13539         }
13540 #endif
13541
13542       /* TOC entries are always Pmode-sized, but since this
13543          is a bigendian machine then if we're putting smaller
13544          integer constants in the TOC we have to pad them.
13545          (This is still a win over putting the constants in
13546          a separate constant pool, because then we'd have
13547          to have both a TOC entry _and_ the actual constant.)
13548
13549          For a 32-bit target, CONST_INT values are loaded and shifted
13550          entirely within `low' and can be stored in one TOC entry.  */
13551
13552       if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13553         abort ();/* It would be easy to make this work, but it doesn't now.  */
13554
13555       if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13556         {
13557 #if HOST_BITS_PER_WIDE_INT == 32
13558           lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13559                          POINTER_SIZE, &low, &high, 0);
13560 #else
13561           low |= high << 32;
13562           low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13563           high = (HOST_WIDE_INT) low >> 32;
13564           low &= 0xffffffff;
13565 #endif
13566         }
13567
13568       if (TARGET_64BIT)
13569         {
13570           if (TARGET_MINIMAL_TOC)
13571             fputs (DOUBLE_INT_ASM_OP, file);
13572           else
13573             fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13574                      (long) high & 0xffffffff, (long) low & 0xffffffff);
13575           fprintf (file, "0x%lx%08lx\n",
13576                    (long) high & 0xffffffff, (long) low & 0xffffffff);
13577           return;
13578         }
13579       else
13580         {
13581           if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13582             {
13583               if (TARGET_MINIMAL_TOC)
13584                 fputs ("\t.long ", file);
13585               else
13586                 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13587                          (long) high & 0xffffffff, (long) low & 0xffffffff);
13588               fprintf (file, "0x%lx,0x%lx\n",
13589                        (long) high & 0xffffffff, (long) low & 0xffffffff);
13590             }
13591           else
13592             {
13593               if (TARGET_MINIMAL_TOC)
13594                 fputs ("\t.long ", file);
13595               else
13596                 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13597               fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13598             }
13599           return;
13600         }
13601     }
13602
13603   if (GET_CODE (x) == CONST)
13604     {
13605       if (GET_CODE (XEXP (x, 0)) != PLUS)
13606         abort ();
13607
13608       base = XEXP (XEXP (x, 0), 0);
13609       offset = INTVAL (XEXP (XEXP (x, 0), 1));
13610     }
13611
13612   if (GET_CODE (base) == SYMBOL_REF)
13613     name = XSTR (base, 0);
13614   else if (GET_CODE (base) == LABEL_REF)
13615     ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13616   else if (GET_CODE (base) == CODE_LABEL)
13617     ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13618   else
13619     abort ();
13620
13621   real_name = (*targetm.strip_name_encoding) (name);
13622   if (TARGET_MINIMAL_TOC)
13623     fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13624   else
13625     {
13626       fprintf (file, "\t.tc %s", real_name);
13627
13628       if (offset < 0)
13629         fprintf (file, ".N%d", - offset);
13630       else if (offset)
13631         fprintf (file, ".P%d", offset);
13632
13633       fputs ("[TC],", file);
13634     }
13635
13636   /* Currently C++ toc references to vtables can be emitted before it
13637      is decided whether the vtable is public or private.  If this is
13638      the case, then the linker will eventually complain that there is
13639      a TOC reference to an unknown section.  Thus, for vtables only,
13640      we emit the TOC reference to reference the symbol and not the
13641      section.  */
13642   if (VTABLE_NAME_P (name))
13643     {
13644       RS6000_OUTPUT_BASENAME (file, name);
13645       if (offset < 0)
13646         fprintf (file, "%d", offset);
13647       else if (offset > 0)
13648         fprintf (file, "+%d", offset);
13649     }
13650   else
13651     output_addr_const (file, x);
13652   putc ('\n', file);
13653 }
13654 \f
13655 /* Output an assembler pseudo-op to write an ASCII string of N characters
13656    starting at P to FILE.
13657
13658    On the RS/6000, we have to do this using the .byte operation and
13659    write out special characters outside the quoted string.
13660    Also, the assembler is broken; very long strings are truncated,
13661    so we must artificially break them up early.  */
13662
13663 void
13664 output_ascii (FILE *file, const char *p, int n)
13665 {
13666   char c;
13667   int i, count_string;
13668   const char *for_string = "\t.byte \"";
13669   const char *for_decimal = "\t.byte ";
13670   const char *to_close = NULL;
13671
13672   count_string = 0;
13673   for (i = 0; i < n; i++)
13674     {
13675       c = *p++;
13676       if (c >= ' ' && c < 0177)
13677         {
13678           if (for_string)
13679             fputs (for_string, file);
13680           putc (c, file);
13681
13682           /* Write two quotes to get one.  */
13683           if (c == '"')
13684             {
13685               putc (c, file);
13686               ++count_string;
13687             }
13688
13689           for_string = NULL;
13690           for_decimal = "\"\n\t.byte ";
13691           to_close = "\"\n";
13692           ++count_string;
13693
13694           if (count_string >= 512)
13695             {
13696               fputs (to_close, file);
13697
13698               for_string = "\t.byte \"";
13699               for_decimal = "\t.byte ";
13700               to_close = NULL;
13701               count_string = 0;
13702             }
13703         }
13704       else
13705         {
13706           if (for_decimal)
13707             fputs (for_decimal, file);
13708           fprintf (file, "%d", c);
13709
13710           for_string = "\n\t.byte \"";
13711           for_decimal = ", ";
13712           to_close = "\n";
13713           count_string = 0;
13714         }
13715     }
13716
13717   /* Now close the string if we have written one.  Then end the line.  */
13718   if (to_close)
13719     fputs (to_close, file);
13720 }
13721 \f
13722 /* Generate a unique section name for FILENAME for a section type
13723    represented by SECTION_DESC.  Output goes into BUF.
13724
13725    SECTION_DESC can be any string, as long as it is different for each
13726    possible section type.
13727
13728    We name the section in the same manner as xlc.  The name begins with an
13729    underscore followed by the filename (after stripping any leading directory
13730    names) with the last period replaced by the string SECTION_DESC.  If
13731    FILENAME does not contain a period, SECTION_DESC is appended to the end of
13732    the name.  */
13733
13734 void
13735 rs6000_gen_section_name (char **buf, const char *filename,
13736                          const char *section_desc)
13737 {
13738   const char *q, *after_last_slash, *last_period = 0;
13739   char *p;
13740   int len;
13741
13742   after_last_slash = filename;
13743   for (q = filename; *q; q++)
13744     {
13745       if (*q == '/')
13746         after_last_slash = q + 1;
13747       else if (*q == '.')
13748         last_period = q;
13749     }
13750
13751   len = strlen (after_last_slash) + strlen (section_desc) + 2;
13752   *buf = (char *) xmalloc (len);
13753
13754   p = *buf;
13755   *p++ = '_';
13756
13757   for (q = after_last_slash; *q; q++)
13758     {
13759       if (q == last_period)
13760         {
13761           strcpy (p, section_desc);
13762           p += strlen (section_desc);
13763           break;
13764         }
13765
13766       else if (ISALNUM (*q))
13767         *p++ = *q;
13768     }
13769
13770   if (last_period == 0)
13771     strcpy (p, section_desc);
13772   else
13773     *p = '\0';
13774 }
13775 \f
13776 /* Emit profile function.  */
13777
13778 void
13779 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13780 {
13781   if (TARGET_PROFILE_KERNEL)
13782     return;
13783
13784   if (DEFAULT_ABI == ABI_AIX)
13785     {
13786 #ifndef NO_PROFILE_COUNTERS
13787 # define NO_PROFILE_COUNTERS 0
13788 #endif
13789       if (NO_PROFILE_COUNTERS)
13790         emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13791       else
13792         {
13793           char buf[30];
13794           const char *label_name;
13795           rtx fun;
13796
13797           ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13798           label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13799           fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13800
13801           emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13802                              fun, Pmode);
13803         }
13804     }
13805   else if (DEFAULT_ABI == ABI_DARWIN)
13806     {
13807       const char *mcount_name = RS6000_MCOUNT;
13808       int caller_addr_regno = LINK_REGISTER_REGNUM;
13809
13810       /* Be conservative and always set this, at least for now.  */
13811       current_function_uses_pic_offset_table = 1;
13812
13813 #if TARGET_MACHO
13814       /* For PIC code, set up a stub and collect the caller's address
13815          from r0, which is where the prologue puts it.  */
13816       if (MACHOPIC_INDIRECT)
13817         {
13818           mcount_name = machopic_stub_name (mcount_name);
13819           if (current_function_uses_pic_offset_table)
13820             caller_addr_regno = 0;
13821         }
13822 #endif
13823       emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13824                          0, VOIDmode, 1,
13825                          gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13826     }
13827 }
13828
13829 /* Write function profiler code.  */
13830
13831 void
13832 output_function_profiler (FILE *file, int labelno)
13833 {
13834   char buf[100];
13835   int save_lr = 8;
13836
13837   switch (DEFAULT_ABI)
13838     {
13839     default:
13840       abort ();
13841
13842     case ABI_V4:
13843       save_lr = 4;
13844       if (!TARGET_32BIT)
13845         {
13846           warning ("no profiling of 64-bit code for this ABI");
13847           return;
13848         }
13849       ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13850       fprintf (file, "\tmflr %s\n", reg_names[0]);
13851       if (flag_pic == 1)
13852         {
13853           fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13854           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13855                        reg_names[0], save_lr, reg_names[1]);
13856           asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13857           asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13858           assemble_name (file, buf);
13859           asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13860         }
13861       else if (flag_pic > 1)
13862         {
13863           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13864                        reg_names[0], save_lr, reg_names[1]);
13865           /* Now, we need to get the address of the label.  */
13866           fputs ("\tbl 1f\n\t.long ", file);
13867           assemble_name (file, buf);
13868           fputs ("-.\n1:", file);
13869           asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13870           asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13871                        reg_names[0], reg_names[11]);
13872           asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13873                        reg_names[0], reg_names[0], reg_names[11]);
13874         }
13875       else
13876         {
13877           asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13878           assemble_name (file, buf);
13879           fputs ("@ha\n", file);
13880           asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13881                        reg_names[0], save_lr, reg_names[1]);
13882           asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13883           assemble_name (file, buf);
13884           asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13885         }
13886
13887       /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH.  */
13888       fprintf (file, "\tbl %s%s\n",
13889                RS6000_MCOUNT, flag_pic ? "@plt" : "");
13890       break;
13891
13892     case ABI_AIX:
13893     case ABI_DARWIN:
13894       if (!TARGET_PROFILE_KERNEL)
13895         {
13896           /* Don't do anything, done in output_profile_hook ().  */
13897         }
13898       else
13899         {
13900           if (TARGET_32BIT)
13901             abort ();
13902
13903           asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13904           asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13905
13906           if (current_function_needs_context)
13907             {
13908               asm_fprintf (file, "\tstd %s,24(%s)\n",
13909                            reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13910               fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13911               asm_fprintf (file, "\tld %s,24(%s)\n",
13912                            reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13913             }
13914           else
13915             fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13916         }
13917       break;
13918     }
13919 }
13920
13921 \f
13922 static int
13923 rs6000_use_dfa_pipeline_interface (void)
13924 {
13925   return 1;
13926 }
13927
13928 /* Power4 load update and store update instructions are cracked into a
13929    load or store and an integer insn which are executed in the same cycle.
13930    Branches have their own dispatch slot which does not count against the
13931    GCC issue rate, but it changes the program flow so there are no other
13932    instructions to issue in this cycle.  */
13933
13934 static int
13935 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
13936                        int verbose ATTRIBUTE_UNUSED,
13937                        rtx insn, int more)
13938 {
13939   if (GET_CODE (PATTERN (insn)) == USE
13940       || GET_CODE (PATTERN (insn)) == CLOBBER)
13941     return more;
13942
13943   if (rs6000_sched_groups)
13944     {
13945       if (is_microcoded_insn (insn))
13946         return 0;
13947       else if (is_cracked_insn (insn))
13948         return more > 2 ? more - 2 : 0;
13949     }
13950
13951   return more - 1;
13952 }
13953
13954 /* Adjust the cost of a scheduling dependency.  Return the new cost of
13955    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
13956
13957 static int
13958 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
13959                     int cost)
13960 {
13961   if (! recog_memoized (insn))
13962     return 0;
13963
13964   if (REG_NOTE_KIND (link) != 0)
13965     return 0;
13966
13967   if (REG_NOTE_KIND (link) == 0)
13968     {
13969       /* Data dependency; DEP_INSN writes a register that INSN reads
13970          some cycles later.  */
13971       switch (get_attr_type (insn))
13972         {
13973         case TYPE_JMPREG:
13974           /* Tell the first scheduling pass about the latency between
13975              a mtctr and bctr (and mtlr and br/blr).  The first
13976              scheduling pass will not know about this latency since
13977              the mtctr instruction, which has the latency associated
13978              to it, will be generated by reload.  */
13979           return TARGET_POWER ? 5 : 4;
13980         case TYPE_BRANCH:
13981           /* Leave some extra cycles between a compare and its
13982              dependent branch, to inhibit expensive mispredicts.  */
13983           if ((rs6000_cpu_attr == CPU_PPC603
13984                || rs6000_cpu_attr == CPU_PPC604
13985                || rs6000_cpu_attr == CPU_PPC604E
13986                || rs6000_cpu_attr == CPU_PPC620
13987                || rs6000_cpu_attr == CPU_PPC630
13988                || rs6000_cpu_attr == CPU_PPC750
13989                || rs6000_cpu_attr == CPU_PPC7400
13990                || rs6000_cpu_attr == CPU_PPC7450
13991                || rs6000_cpu_attr == CPU_POWER4
13992                || rs6000_cpu_attr == CPU_POWER5)
13993               && recog_memoized (dep_insn)
13994               && (INSN_CODE (dep_insn) >= 0)
13995               && (get_attr_type (dep_insn) == TYPE_CMP
13996                   || get_attr_type (dep_insn) == TYPE_COMPARE
13997                   || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
13998                   || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
13999                   || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
14000                   || get_attr_type (dep_insn) == TYPE_FPCOMPARE
14001                   || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14002                   || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14003             return cost + 2;
14004         default:
14005           break;
14006         }
14007       /* Fall out to return default cost.  */
14008     }
14009
14010   return cost;
14011 }
14012
14013 /* The function returns a true if INSN is microcoded.
14014    Return false otherwise.  */
14015
14016 static bool
14017 is_microcoded_insn (rtx insn)
14018 {
14019   if (!insn || !INSN_P (insn)
14020       || GET_CODE (PATTERN (insn)) == USE
14021       || GET_CODE (PATTERN (insn)) == CLOBBER)
14022     return false;
14023
14024   if (rs6000_sched_groups)
14025     {
14026       enum attr_type type = get_attr_type (insn);
14027       if (type == TYPE_LOAD_EXT_U
14028           || type == TYPE_LOAD_EXT_UX
14029           || type == TYPE_LOAD_UX
14030           || type == TYPE_STORE_UX
14031           || type == TYPE_MFCR)
14032         return true;
14033     }
14034
14035   return false;
14036 }
14037
14038 /* The function returns a nonzero value if INSN can be scheduled only
14039    as the first insn in a dispatch group ("dispatch-slot restricted").
14040    In this case, the returned value indicates how many dispatch slots
14041    the insn occupies (at the beginning of the group).
14042    Return 0 otherwise.  */
14043
14044 static int
14045 is_dispatch_slot_restricted (rtx insn)
14046 {
14047   enum attr_type type;
14048
14049   if (!rs6000_sched_groups)
14050     return 0;
14051
14052   if (!insn
14053       || insn == NULL_RTX
14054       || GET_CODE (insn) == NOTE
14055       || GET_CODE (PATTERN (insn)) == USE
14056       || GET_CODE (PATTERN (insn)) == CLOBBER)
14057     return 0;
14058
14059   type = get_attr_type (insn);
14060
14061   switch (type)
14062     {
14063     case TYPE_MFCR:
14064     case TYPE_MFCRF:
14065     case TYPE_MTCR:
14066     case TYPE_DELAYED_CR:
14067     case TYPE_CR_LOGICAL:
14068     case TYPE_MTJMPR:
14069     case TYPE_MFJMPR:
14070       return 1;
14071     case TYPE_IDIV:
14072     case TYPE_LDIV:
14073       return 2;
14074     default:
14075       if (rs6000_cpu == PROCESSOR_POWER5
14076           && is_cracked_insn (insn))
14077         return 2;
14078       return 0;
14079     }
14080 }
14081
14082 /* The function returns true if INSN is cracked into 2 instructions
14083    by the processor (and therefore occupies 2 issue slots).  */
14084
14085 static bool
14086 is_cracked_insn (rtx insn)
14087 {
14088   if (!insn || !INSN_P (insn)
14089       || GET_CODE (PATTERN (insn)) == USE
14090       || GET_CODE (PATTERN (insn)) == CLOBBER)
14091     return false;
14092
14093   if (rs6000_sched_groups)
14094     {
14095       enum attr_type type = get_attr_type (insn);
14096       if (type == TYPE_LOAD_U || type == TYPE_STORE_U
14097                || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
14098                || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
14099                || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
14100                || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
14101                || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
14102                || type == TYPE_IDIV || type == TYPE_LDIV
14103                || type == TYPE_INSERT_WORD)
14104         return true;
14105     }
14106
14107   return false;
14108 }
14109
14110 /* The function returns true if INSN can be issued only from
14111    the branch slot.  */
14112
14113 static bool
14114 is_branch_slot_insn (rtx insn)
14115 {
14116   if (!insn || !INSN_P (insn)
14117       || GET_CODE (PATTERN (insn)) == USE
14118       || GET_CODE (PATTERN (insn)) == CLOBBER)
14119     return false;
14120
14121   if (rs6000_sched_groups)
14122     {
14123       enum attr_type type = get_attr_type (insn);
14124       if (type == TYPE_BRANCH || type == TYPE_JMPREG)
14125         return true;
14126       return false;
14127     }
14128
14129   return false;
14130 }
14131
14132 /* A C statement (sans semicolon) to update the integer scheduling
14133    priority INSN_PRIORITY (INSN). Increase the priority to execute the
14134    INSN earlier, reduce the priority to execute INSN later.  Do not
14135    define this macro if you do not need to adjust the scheduling
14136    priorities of insns.  */
14137
14138 static int
14139 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
14140 {
14141   /* On machines (like the 750) which have asymmetric integer units,
14142      where one integer unit can do multiply and divides and the other
14143      can't, reduce the priority of multiply/divide so it is scheduled
14144      before other integer operations.  */
14145
14146 #if 0
14147   if (! INSN_P (insn))
14148     return priority;
14149
14150   if (GET_CODE (PATTERN (insn)) == USE)
14151     return priority;
14152
14153   switch (rs6000_cpu_attr) {
14154   case CPU_PPC750:
14155     switch (get_attr_type (insn))
14156       {
14157       default:
14158         break;
14159
14160       case TYPE_IMUL:
14161       case TYPE_IDIV:
14162         fprintf (stderr, "priority was %#x (%d) before adjustment\n",
14163                  priority, priority);
14164         if (priority >= 0 && priority < 0x01000000)
14165           priority >>= 3;
14166         break;
14167       }
14168   }
14169 #endif
14170
14171   if (is_dispatch_slot_restricted (insn)
14172       && reload_completed
14173       && current_sched_info->sched_max_insns_priority
14174       && rs6000_sched_restricted_insns_priority)
14175     {
14176
14177       /* Prioritize insns that can be dispatched only in the first dispatch slot.  */
14178       if (rs6000_sched_restricted_insns_priority == 1)
14179         /* Attach highest priority to insn. This means that in
14180            haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
14181            precede 'priority' (critical path) considerations.  */
14182         return current_sched_info->sched_max_insns_priority;
14183       else if (rs6000_sched_restricted_insns_priority == 2)
14184         /* Increase priority of insn by a minimal amount. This means that in
14185            haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
14186            precede dispatch-slot restriction considerations.  */
14187         return (priority + 1);
14188     }
14189
14190   return priority;
14191 }
14192
14193 /* Return how many instructions the machine can issue per cycle.  */
14194
14195 static int
14196 rs6000_issue_rate (void)
14197 {
14198   /* Use issue rate of 1 for first scheduling pass to decrease degradation.  */
14199   if (!reload_completed)
14200     return 1;
14201
14202   switch (rs6000_cpu_attr) {
14203   case CPU_RIOS1:  /* ? */
14204   case CPU_RS64A:
14205   case CPU_PPC601: /* ? */
14206   case CPU_PPC7450:
14207     return 3;
14208   case CPU_PPC440:
14209   case CPU_PPC603:
14210   case CPU_PPC750:
14211   case CPU_PPC7400:
14212   case CPU_PPC8540:
14213     return 2;
14214   case CPU_RIOS2:
14215   case CPU_PPC604:
14216   case CPU_PPC604E:
14217   case CPU_PPC620:
14218   case CPU_PPC630:
14219     return 4;
14220   case CPU_POWER4:
14221   case CPU_POWER5:
14222     return 5;
14223   default:
14224     return 1;
14225   }
14226 }
14227
14228 /* Return how many instructions to look ahead for better insn
14229    scheduling.  */
14230
14231 static int
14232 rs6000_use_sched_lookahead (void)
14233 {
14234   if (rs6000_cpu_attr == CPU_PPC8540)
14235     return 4;
14236   return 0;
14237 }
14238
14239 /* Determine is PAT refers to memory.  */
14240
14241 static bool
14242 is_mem_ref (rtx pat)
14243 {
14244   const char * fmt;
14245   int i, j;
14246   bool ret = false;
14247
14248   if (GET_CODE (pat) == MEM)
14249     return true;
14250
14251   /* Recursively process the pattern.  */
14252   fmt = GET_RTX_FORMAT (GET_CODE (pat));
14253
14254   for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
14255     {
14256       if (fmt[i] == 'e')
14257         ret |= is_mem_ref (XEXP (pat, i));
14258       else if (fmt[i] == 'E')
14259         for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
14260           ret |= is_mem_ref (XVECEXP (pat, i, j));
14261     }
14262
14263   return ret;
14264 }
14265
14266 /* Determine if PAT is a PATTERN of a load insn.  */
14267
14268 static bool
14269 is_load_insn1 (rtx pat)
14270 {
14271   if (!pat || pat == NULL_RTX)
14272     return false;
14273
14274   if (GET_CODE (pat) == SET)
14275     return is_mem_ref (SET_SRC (pat));
14276
14277   if (GET_CODE (pat) == PARALLEL)
14278     {
14279       int i;
14280
14281       for (i = 0; i < XVECLEN (pat, 0); i++)
14282         if (is_load_insn1 (XVECEXP (pat, 0, i)))
14283           return true;
14284     }
14285
14286   return false;
14287 }
14288
14289 /* Determine if INSN loads from memory.  */
14290
14291 static bool
14292 is_load_insn (rtx insn)
14293 {
14294   if (!insn || !INSN_P (insn))
14295     return false;
14296
14297   if (GET_CODE (insn) == CALL_INSN)
14298     return false;
14299
14300   return is_load_insn1 (PATTERN (insn));
14301 }
14302
14303 /* Determine if PAT is a PATTERN of a store insn.  */
14304
14305 static bool
14306 is_store_insn1 (rtx pat)
14307 {
14308   if (!pat || pat == NULL_RTX)
14309     return false;
14310
14311   if (GET_CODE (pat) == SET)
14312     return is_mem_ref (SET_DEST (pat));
14313
14314   if (GET_CODE (pat) == PARALLEL)
14315     {
14316       int i;
14317
14318       for (i = 0; i < XVECLEN (pat, 0); i++)
14319         if (is_store_insn1 (XVECEXP (pat, 0, i)))
14320           return true;
14321     }
14322
14323   return false;
14324 }
14325
14326 /* Determine if INSN stores to memory.  */
14327
14328 static bool
14329 is_store_insn (rtx insn)
14330 {
14331   if (!insn || !INSN_P (insn))
14332     return false;
14333
14334   return is_store_insn1 (PATTERN (insn));
14335 }
14336
14337 /* Returns whether the dependence between INSN and NEXT is considered
14338    costly by the given target.  */
14339
14340 static bool
14341 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
14342 {
14343   /* If the flag is not enbled - no dependence is considered costly;
14344      allow all dependent insns in the same group.
14345      This is the most aggressive option.  */
14346   if (rs6000_sched_costly_dep == no_dep_costly)
14347     return false;
14348
14349   /* If the flag is set to 1 - a dependence is always considered costly;
14350      do not allow dependent instructions in the same group.
14351      This is the most conservative option.  */
14352   if (rs6000_sched_costly_dep == all_deps_costly)
14353     return true;
14354
14355   if (rs6000_sched_costly_dep == store_to_load_dep_costly
14356       && is_load_insn (next)
14357       && is_store_insn (insn))
14358     /* Prevent load after store in the same group.  */
14359     return true;
14360
14361   if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
14362       && is_load_insn (next)
14363       && is_store_insn (insn)
14364       && (!link || (int) REG_NOTE_KIND (link) == 0))
14365      /* Prevent load after store in the same group if it is a true dependence.  */
14366      return true;
14367
14368   /* The flag is set to X; dependences with latency >= X are considered costly,
14369      and will not be scheduled in the same group.  */
14370   if (rs6000_sched_costly_dep <= max_dep_latency
14371       && ((cost - distance) >= (int)rs6000_sched_costly_dep))
14372     return true;
14373
14374   return false;
14375 }
14376
14377 /* Return the next insn after INSN that is found before TAIL is reached,
14378    skipping any "non-active" insns - insns that will not actually occupy
14379    an issue slot.  Return NULL_RTX if such an insn is not found.  */
14380
14381 static rtx
14382 get_next_active_insn (rtx insn, rtx tail)
14383 {
14384   rtx next_insn;
14385
14386   if (!insn || insn == tail)
14387     return NULL_RTX;
14388
14389   next_insn = NEXT_INSN (insn);
14390
14391   while (next_insn
14392          && next_insn != tail
14393          && (GET_CODE(next_insn) == NOTE
14394              || GET_CODE (PATTERN (next_insn)) == USE
14395              || GET_CODE (PATTERN (next_insn)) == CLOBBER))
14396     {
14397       next_insn = NEXT_INSN (next_insn);
14398     }
14399
14400   if (!next_insn || next_insn == tail)
14401     return NULL_RTX;
14402
14403   return next_insn;
14404 }
14405
14406 /* Return whether the presence of INSN causes a dispatch group termination
14407    of group WHICH_GROUP.
14408
14409    If WHICH_GROUP == current_group, this function will return true if INSN
14410    causes the termination of the current group (i.e, the dispatch group to
14411    which INSN belongs). This means that INSN will be the last insn in the
14412    group it belongs to.
14413
14414    If WHICH_GROUP == previous_group, this function will return true if INSN
14415    causes the termination of the previous group (i.e, the dispatch group that
14416    precedes the group to which INSN belongs).  This means that INSN will be
14417    the first insn in the group it belongs to).  */
14418
14419 static bool
14420 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14421 {
14422   enum attr_type type;
14423
14424   if (! insn)
14425     return false;
14426
14427   type = get_attr_type (insn);
14428
14429   if (is_microcoded_insn (insn))
14430     return true;
14431
14432   if (which_group == current_group)
14433     {
14434       if (is_branch_slot_insn (insn))
14435         return true;
14436       return false;
14437     }
14438   else if (which_group == previous_group)
14439     {
14440       if (is_dispatch_slot_restricted (insn))
14441         return true;
14442       return false;
14443     }
14444
14445   return false;
14446 }
14447
14448 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14449    dispatch group) from the insns in GROUP_INSNS.  Return false otherwise.  */
14450
14451 static bool
14452 is_costly_group (rtx *group_insns, rtx next_insn)
14453 {
14454   int i;
14455   rtx link;
14456   int cost;
14457   int issue_rate = rs6000_issue_rate ();
14458
14459   for (i = 0; i < issue_rate; i++)
14460     {
14461       rtx insn = group_insns[i];
14462       if (!insn)
14463         continue;
14464       for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14465         {
14466           rtx next = XEXP (link, 0);
14467           if (next == next_insn)
14468             {
14469               cost = insn_cost (insn, link, next_insn);
14470               if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14471                 return true;
14472             }
14473         }
14474     }
14475
14476   return false;
14477 }
14478
14479 /* Utility of the function redefine_groups.
14480    Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14481    in the same dispatch group.  If so, insert nops before NEXT_INSN, in order
14482    to keep it "far" (in a separate group) from GROUP_INSNS, following
14483    one of the following schemes, depending on the value of the flag
14484    -minsert_sched_nops = X:
14485    (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14486        in order to force NEXT_INSN into a separate group.
14487    (2) X < sched_finish_regroup_exact: insert exactly X nops.
14488    GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14489    insertion (has a group just ended, how many vacant issue slots remain in the
14490    last group, and how many dispatch groups were encountered so far).  */
14491
14492 static int
14493 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14494                  bool *group_end, int can_issue_more, int *group_count)
14495 {
14496   rtx nop;
14497   bool force;
14498   int issue_rate = rs6000_issue_rate ();
14499   bool end = *group_end;
14500   int i;
14501
14502   if (next_insn == NULL_RTX)
14503     return can_issue_more;
14504
14505   if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14506     return can_issue_more;
14507
14508   force = is_costly_group (group_insns, next_insn);
14509   if (!force)
14510     return can_issue_more;
14511
14512   if (sched_verbose > 6)
14513     fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14514                         *group_count ,can_issue_more);
14515
14516   if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14517     {
14518       if (*group_end)
14519         can_issue_more = 0;
14520
14521       /* Since only a branch can be issued in the last issue_slot, it is
14522          sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14523          a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14524          in this case the last nop will start a new group and the branch will be
14525          forced to the new group.  */
14526       if (can_issue_more && !is_branch_slot_insn (next_insn))
14527         can_issue_more--;
14528
14529       while (can_issue_more > 0)
14530         {
14531           nop = gen_nop();
14532           emit_insn_before (nop, next_insn);
14533           can_issue_more--;
14534         }
14535
14536       *group_end = true;
14537       return 0;
14538     }
14539
14540   if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14541     {
14542       int n_nops = rs6000_sched_insert_nops;
14543
14544       /* Nops can't be issued from the branch slot, so the effective
14545          issue_rate for nops is 'issue_rate - 1'.  */
14546       if (can_issue_more == 0)
14547         can_issue_more = issue_rate;
14548       can_issue_more--;
14549       if (can_issue_more == 0)
14550         {
14551           can_issue_more = issue_rate - 1;
14552           (*group_count)++;
14553           end = true;
14554           for (i = 0; i < issue_rate; i++)
14555             {
14556               group_insns[i] = 0;
14557             }
14558         }
14559
14560       while (n_nops > 0)
14561         {
14562           nop = gen_nop ();
14563           emit_insn_before (nop, next_insn);
14564           if (can_issue_more == issue_rate - 1) /* new group begins */
14565             end = false;
14566           can_issue_more--;
14567           if (can_issue_more == 0)
14568             {
14569               can_issue_more = issue_rate - 1;
14570               (*group_count)++;
14571               end = true;
14572               for (i = 0; i < issue_rate; i++)
14573                 {
14574                   group_insns[i] = 0;
14575                 }
14576             }
14577           n_nops--;
14578         }
14579
14580       /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1').  */
14581       can_issue_more++;
14582
14583       *group_end = /* Is next_insn going to start a new group?  */
14584           (end
14585            || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14586            || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14587            || (can_issue_more < issue_rate &&
14588               insn_terminates_group_p (next_insn, previous_group)));
14589       if (*group_end && end)
14590         (*group_count)--;
14591
14592       if (sched_verbose > 6)
14593         fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14594                         *group_count, can_issue_more);
14595       return can_issue_more;
14596     }
14597
14598   return can_issue_more;
14599 }
14600
14601 /* This function tries to synch the dispatch groups that the compiler "sees"
14602    with the dispatch groups that the processor dispatcher is expected to
14603    form in practice.  It tries to achieve this synchronization by forcing the
14604    estimated processor grouping on the compiler (as opposed to the function
14605    'pad_goups' which tries to force the scheduler's grouping on the processor).
14606
14607    The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14608    examines the (estimated) dispatch groups that will be formed by the processor
14609    dispatcher.  It marks these group boundaries to reflect the estimated
14610    processor grouping, overriding the grouping that the scheduler had marked.
14611    Depending on the value of the flag '-minsert-sched-nops' this function can
14612    force certain insns into separate groups or force a certain distance between
14613    them by inserting nops, for example, if there exists a "costly dependence"
14614    between the insns.
14615
14616    The function estimates the group boundaries that the processor will form as
14617    folllows:  It keeps track of how many vacant issue slots are available after
14618    each insn.  A subsequent insn will start a new group if one of the following
14619    4 cases applies:
14620    - no more vacant issue slots remain in the current dispatch group.
14621    - only the last issue slot, which is the branch slot, is vacant, but the next
14622      insn is not a branch.
14623    - only the last 2 or less issue slots, including the branch slot, are vacant,
14624      which means that a cracked insn (which occupies two issue slots) can't be
14625      issued in this group.
14626    - less than 'issue_rate' slots are vacant, and the next insn always needs to
14627      start a new group.  */
14628
14629 static int
14630 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14631 {
14632   rtx insn, next_insn;
14633   int issue_rate;
14634   int can_issue_more;
14635   int slot, i;
14636   bool group_end;
14637   int group_count = 0;
14638   rtx *group_insns;
14639
14640   /* Initialize.  */
14641   issue_rate = rs6000_issue_rate ();
14642   group_insns = alloca (issue_rate * sizeof (rtx));
14643   for (i = 0; i < issue_rate; i++)
14644     {
14645       group_insns[i] = 0;
14646     }
14647   can_issue_more = issue_rate;
14648   slot = 0;
14649   insn = get_next_active_insn (prev_head_insn, tail);
14650   group_end = false;
14651
14652   while (insn != NULL_RTX)
14653     {
14654       slot = (issue_rate - can_issue_more);
14655       group_insns[slot] = insn;
14656       can_issue_more =
14657         rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14658       if (insn_terminates_group_p (insn, current_group))
14659         can_issue_more = 0;
14660
14661       next_insn = get_next_active_insn (insn, tail);
14662       if (next_insn == NULL_RTX)
14663         return group_count + 1;
14664
14665       group_end = /* Is next_insn going to start a new group?  */
14666         (can_issue_more == 0
14667          || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14668          || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14669          || (can_issue_more < issue_rate &&
14670              insn_terminates_group_p (next_insn, previous_group)));
14671
14672       can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14673                         next_insn, &group_end, can_issue_more, &group_count);
14674
14675       if (group_end)
14676         {
14677           group_count++;
14678           can_issue_more = 0;
14679           for (i = 0; i < issue_rate; i++)
14680             {
14681               group_insns[i] = 0;
14682             }
14683         }
14684
14685       if (GET_MODE (next_insn) == TImode && can_issue_more)
14686         PUT_MODE(next_insn, VOIDmode);
14687       else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14688         PUT_MODE (next_insn, TImode);
14689
14690       insn = next_insn;
14691       if (can_issue_more == 0)
14692         can_issue_more = issue_rate;
14693    } /* while */
14694
14695   return group_count;
14696 }
14697
14698 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14699    dispatch group boundaries that the scheduler had marked.  Pad with nops
14700    any dispatch groups which have vacant issue slots, in order to force the
14701    scheduler's grouping on the processor dispatcher.  The function
14702    returns the number of dispatch groups found.  */
14703
14704 static int
14705 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14706 {
14707   rtx insn, next_insn;
14708   rtx nop;
14709   int issue_rate;
14710   int can_issue_more;
14711   int group_end;
14712   int group_count = 0;
14713
14714   /* Initialize issue_rate.  */
14715   issue_rate = rs6000_issue_rate ();
14716   can_issue_more = issue_rate;
14717
14718   insn = get_next_active_insn (prev_head_insn, tail);
14719   next_insn = get_next_active_insn (insn, tail);
14720
14721   while (insn != NULL_RTX)
14722     {
14723       can_issue_more =
14724         rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14725
14726       group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14727
14728       if (next_insn == NULL_RTX)
14729         break;
14730
14731       if (group_end)
14732         {
14733           /* If the scheduler had marked group termination at this location
14734              (between insn and next_indn), and neither insn nor next_insn will
14735              force group termination, pad the group with nops to force group
14736              termination.  */
14737           if (can_issue_more
14738               && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14739               && !insn_terminates_group_p (insn, current_group)
14740               && !insn_terminates_group_p (next_insn, previous_group))
14741             {
14742               if (!is_branch_slot_insn(next_insn))
14743                 can_issue_more--;
14744
14745               while (can_issue_more)
14746                 {
14747                   nop = gen_nop ();
14748                   emit_insn_before (nop, next_insn);
14749                   can_issue_more--;
14750                 }
14751             }
14752
14753           can_issue_more = issue_rate;
14754           group_count++;
14755         }
14756
14757       insn = next_insn;
14758       next_insn = get_next_active_insn (insn, tail);
14759     }
14760
14761   return group_count;
14762 }
14763
14764 /* The following function is called at the end of scheduling BB.
14765    After reload, it inserts nops at insn group bundling.  */
14766
14767 static void
14768 rs6000_sched_finish (FILE *dump, int sched_verbose)
14769 {
14770   int n_groups;
14771
14772   if (sched_verbose)
14773     fprintf (dump, "=== Finishing schedule.\n");
14774
14775   if (reload_completed && rs6000_sched_groups)
14776     {
14777       if (rs6000_sched_insert_nops == sched_finish_none)
14778         return;
14779
14780       if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14781         n_groups = pad_groups (dump, sched_verbose,
14782                                 current_sched_info->prev_head,
14783                                 current_sched_info->next_tail);
14784       else
14785         n_groups = redefine_groups (dump, sched_verbose,
14786                                 current_sched_info->prev_head,
14787                                 current_sched_info->next_tail);
14788
14789       if (sched_verbose >= 6)
14790         {
14791           fprintf (dump, "ngroups = %d\n", n_groups);
14792           print_rtl (dump, current_sched_info->prev_head);
14793           fprintf (dump, "Done finish_sched\n");
14794         }
14795     }
14796 }
14797 \f
14798 /* Length in units of the trampoline for entering a nested function.  */
14799
14800 int
14801 rs6000_trampoline_size (void)
14802 {
14803   int ret = 0;
14804
14805   switch (DEFAULT_ABI)
14806     {
14807     default:
14808       abort ();
14809
14810     case ABI_AIX:
14811       ret = (TARGET_32BIT) ? 12 : 24;
14812       break;
14813
14814     case ABI_DARWIN:
14815     case ABI_V4:
14816       ret = (TARGET_32BIT) ? 40 : 48;
14817       break;
14818     }
14819
14820   return ret;
14821 }
14822
14823 /* Emit RTL insns to initialize the variable parts of a trampoline.
14824    FNADDR is an RTX for the address of the function's pure code.
14825    CXT is an RTX for the static chain value for the function.  */
14826
14827 void
14828 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14829 {
14830   enum machine_mode pmode = Pmode;
14831   int regsize = (TARGET_32BIT) ? 4 : 8;
14832   rtx ctx_reg = force_reg (pmode, cxt);
14833
14834   switch (DEFAULT_ABI)
14835     {
14836     default:
14837       abort ();
14838
14839 /* Macros to shorten the code expansions below.  */
14840 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14841 #define MEM_PLUS(addr,offset) \
14842   gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14843
14844     /* Under AIX, just build the 3 word function descriptor */
14845     case ABI_AIX:
14846       {
14847         rtx fn_reg = gen_reg_rtx (pmode);
14848         rtx toc_reg = gen_reg_rtx (pmode);
14849         emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14850         emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14851         emit_move_insn (MEM_DEREF (addr), fn_reg);
14852         emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14853         emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14854       }
14855       break;
14856
14857     /* Under V.4/eabi/darwin, __trampoline_setup does the real work.  */
14858     case ABI_DARWIN:
14859     case ABI_V4:
14860       emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14861                          FALSE, VOIDmode, 4,
14862                          addr, pmode,
14863                          GEN_INT (rs6000_trampoline_size ()), SImode,
14864                          fnaddr, pmode,
14865                          ctx_reg, pmode);
14866       break;
14867     }
14868
14869   return;
14870 }
14871
14872 \f
14873 /* Table of valid machine attributes.  */
14874
14875 const struct attribute_spec rs6000_attribute_table[] =
14876 {
14877   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14878   { "altivec",   1, 1, false, true,  false, rs6000_handle_altivec_attribute },
14879   { "longcall",  0, 0, false, true,  true,  rs6000_handle_longcall_attribute },
14880   { "shortcall", 0, 0, false, true,  true,  rs6000_handle_longcall_attribute },
14881   { NULL,        0, 0, false, false, false, NULL }
14882 };
14883
14884 /* Handle the "altivec" attribute.  The attribute may have
14885    arguments as follows:
14886
14887         __attribute__((altivec(vector__)))
14888         __attribute__((altivec(pixel__)))       (always followed by 'unsigned short')
14889         __attribute__((altivec(bool__)))        (always followed by 'unsigned')
14890
14891   and may appear more than once (e.g., 'vector bool char') in a
14892   given declaration.  */
14893
14894 static tree
14895 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
14896                                  int flags ATTRIBUTE_UNUSED,
14897                                  bool *no_add_attrs)
14898 {
14899   tree type = *node, result = NULL_TREE;
14900   enum machine_mode mode;
14901   int unsigned_p;
14902   char altivec_type
14903     = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
14904         && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
14905        ? *IDENTIFIER_POINTER (TREE_VALUE (args))
14906        : '?');
14907
14908   while (POINTER_TYPE_P (type)
14909          || TREE_CODE (type) == FUNCTION_TYPE
14910          || TREE_CODE (type) == METHOD_TYPE
14911          || TREE_CODE (type) == ARRAY_TYPE)
14912     type = TREE_TYPE (type);
14913
14914   mode = TYPE_MODE (type);
14915
14916   if (rs6000_warn_altivec_long
14917       && (type == long_unsigned_type_node || type == long_integer_type_node))
14918     warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
14919
14920   switch (altivec_type)
14921     {
14922     case 'v':
14923       unsigned_p = TYPE_UNSIGNED (type);
14924       switch (mode)
14925         {
14926           case SImode:
14927             result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
14928             break;
14929           case HImode:
14930             result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
14931             break;
14932           case QImode:
14933             result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
14934             break;
14935           case SFmode: result = V4SF_type_node; break;
14936             /* If the user says 'vector int bool', we may be handed the 'bool'
14937                attribute _before_ the 'vector' attribute, and so select the proper
14938                type in the 'b' case below.  */
14939           case V4SImode: case V8HImode: case V16QImode: result = type;
14940           default: break;
14941         }
14942       break;
14943     case 'b':
14944       switch (mode)
14945         {
14946           case SImode: case V4SImode: result = bool_V4SI_type_node; break;
14947           case HImode: case V8HImode: result = bool_V8HI_type_node; break;
14948           case QImode: case V16QImode: result = bool_V16QI_type_node;
14949           default: break;
14950         }
14951       break;
14952     case 'p':
14953       switch (mode)
14954         {
14955           case V8HImode: result = pixel_V8HI_type_node;
14956           default: break;
14957         }
14958     default: break;
14959     }
14960
14961   *no_add_attrs = true;  /* No need to hang on to the attribute.  */
14962
14963   if (!result)
14964     warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
14965   else
14966     *node = reconstruct_complex_type (*node, result);
14967
14968   return NULL_TREE;
14969 }
14970
14971 /* AltiVec defines four built-in scalar types that serve as vector
14972    elements; we must teach the compiler how to mangle them.  */
14973
14974 static const char *
14975 rs6000_mangle_fundamental_type (tree type)
14976 {
14977   if (type == bool_char_type_node) return "U6__boolc";
14978   if (type == bool_short_type_node) return "U6__bools";
14979   if (type == pixel_type_node) return "u7__pixel";
14980   if (type == bool_int_type_node) return "U6__booli";
14981
14982   /* For all other types, use normal C++ mangling.  */
14983   return NULL;
14984 }
14985
14986 /* Handle a "longcall" or "shortcall" attribute; arguments as in
14987    struct attribute_spec.handler.  */
14988
14989 static tree
14990 rs6000_handle_longcall_attribute (tree *node, tree name,
14991                                   tree args ATTRIBUTE_UNUSED,
14992                                   int flags ATTRIBUTE_UNUSED,
14993                                   bool *no_add_attrs)
14994 {
14995   if (TREE_CODE (*node) != FUNCTION_TYPE
14996       && TREE_CODE (*node) != FIELD_DECL
14997       && TREE_CODE (*node) != TYPE_DECL)
14998     {
14999       warning ("`%s' attribute only applies to functions",
15000                IDENTIFIER_POINTER (name));
15001       *no_add_attrs = true;
15002     }
15003
15004   return NULL_TREE;
15005 }
15006
15007 /* Set longcall attributes on all functions declared when
15008    rs6000_default_long_calls is true.  */
15009 static void
15010 rs6000_set_default_type_attributes (tree type)
15011 {
15012   if (rs6000_default_long_calls
15013       && (TREE_CODE (type) == FUNCTION_TYPE
15014           || TREE_CODE (type) == METHOD_TYPE))
15015     TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15016                                         NULL_TREE,
15017                                         TYPE_ATTRIBUTES (type));
15018 }
15019
15020 /* Return a reference suitable for calling a function with the
15021    longcall attribute.  */
15022
15023 struct rtx_def *
15024 rs6000_longcall_ref (rtx call_ref)
15025 {
15026   const char *call_name;
15027   tree node;
15028
15029   if (GET_CODE (call_ref) != SYMBOL_REF)
15030     return call_ref;
15031
15032   /* System V adds '.' to the internal name, so skip them.  */
15033   call_name = XSTR (call_ref, 0);
15034   if (*call_name == '.')
15035     {
15036       while (*call_name == '.')
15037         call_name++;
15038
15039       node = get_identifier (call_name);
15040       call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15041     }
15042
15043   return force_reg (Pmode, call_ref);
15044 }
15045 \f
15046 #ifdef USING_ELFOS_H
15047
15048 /* A C statement or statements to switch to the appropriate section
15049    for output of RTX in mode MODE.  You can assume that RTX is some
15050    kind of constant in RTL.  The argument MODE is redundant except in
15051    the case of a `const_int' rtx.  Select the section by calling
15052    `text_section' or one of the alternatives for other sections.
15053
15054    Do not define this macro if you put all constants in the read-only
15055    data section.  */
15056
15057 static void
15058 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
15059                                unsigned HOST_WIDE_INT align)
15060 {
15061   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15062     toc_section ();
15063   else
15064     default_elf_select_rtx_section (mode, x, align);
15065 }
15066
15067 /* A C statement or statements to switch to the appropriate
15068    section for output of DECL.  DECL is either a `VAR_DECL' node
15069    or a constant of some sort.  RELOC indicates whether forming
15070    the initial value of DECL requires link-time relocations.  */
15071
15072 static void
15073 rs6000_elf_select_section (tree decl, int reloc,
15074                            unsigned HOST_WIDE_INT align)
15075 {
15076   /* Pretend that we're always building for a shared library when
15077      ABI_AIX, because otherwise we end up with dynamic relocations
15078      in read-only sections.  This happens for function pointers,
15079      references to vtables in typeinfo, and probably other cases.  */
15080   default_elf_select_section_1 (decl, reloc, align,
15081                                 flag_pic || DEFAULT_ABI == ABI_AIX);
15082 }
15083
15084 /* A C statement to build up a unique section name, expressed as a
15085    STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
15086    RELOC indicates whether the initial value of EXP requires
15087    link-time relocations.  If you do not define this macro, GCC will use
15088    the symbol name prefixed by `.' as the section name.  Note - this
15089    macro can now be called for uninitialized data items as well as
15090    initialized data and functions.  */
15091
15092 static void
15093 rs6000_elf_unique_section (tree decl, int reloc)
15094 {
15095   /* As above, pretend that we're always building for a shared library
15096      when ABI_AIX, to avoid dynamic relocations in read-only sections.  */
15097   default_unique_section_1 (decl, reloc,
15098                             flag_pic || DEFAULT_ABI == ABI_AIX);
15099 }
15100 \f
15101 /* For a SYMBOL_REF, set generic flags and then perform some
15102    target-specific processing.
15103
15104    When the AIX ABI is requested on a non-AIX system, replace the
15105    function name with the real name (with a leading .) rather than the
15106    function descriptor name.  This saves a lot of overriding code to
15107    read the prefixes.  */
15108
15109 static void
15110 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
15111 {
15112   default_encode_section_info (decl, rtl, first);
15113
15114   if (first
15115       && TREE_CODE (decl) == FUNCTION_DECL
15116       && !TARGET_AIX
15117       && DEFAULT_ABI == ABI_AIX)
15118     {
15119       rtx sym_ref = XEXP (rtl, 0);
15120       size_t len = strlen (XSTR (sym_ref, 0));
15121       char *str = alloca (len + 2);
15122       str[0] = '.';
15123       memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
15124       XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
15125     }
15126 }
15127
15128 static bool
15129 rs6000_elf_in_small_data_p (tree decl)
15130 {
15131   if (rs6000_sdata == SDATA_NONE)
15132     return false;
15133
15134   if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
15135     {
15136       const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
15137       if (strcmp (section, ".sdata") == 0
15138           || strcmp (section, ".sdata2") == 0
15139           || strcmp (section, ".sbss") == 0
15140           || strcmp (section, ".sbss2") == 0
15141           || strcmp (section, ".PPC.EMB.sdata0") == 0
15142           || strcmp (section, ".PPC.EMB.sbss0") == 0)
15143         return true;
15144     }
15145   else
15146     {
15147       HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
15148
15149       if (size > 0
15150           && (unsigned HOST_WIDE_INT) size <= g_switch_value
15151           /* If it's not public, and we're not going to reference it there,
15152              there's no need to put it in the small data section.  */
15153           && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
15154         return true;
15155     }
15156
15157   return false;
15158 }
15159
15160 #endif /* USING_ELFOS_H */
15161
15162 \f
15163 /* Return a REG that occurs in ADDR with coefficient 1.
15164    ADDR can be effectively incremented by incrementing REG.
15165
15166    r0 is special and we must not select it as an address
15167    register by this routine since our caller will try to
15168    increment the returned register via an "la" instruction.  */
15169
15170 struct rtx_def *
15171 find_addr_reg (rtx addr)
15172 {
15173   while (GET_CODE (addr) == PLUS)
15174     {
15175       if (GET_CODE (XEXP (addr, 0)) == REG
15176           && REGNO (XEXP (addr, 0)) != 0)
15177         addr = XEXP (addr, 0);
15178       else if (GET_CODE (XEXP (addr, 1)) == REG
15179                && REGNO (XEXP (addr, 1)) != 0)
15180         addr = XEXP (addr, 1);
15181       else if (CONSTANT_P (XEXP (addr, 0)))
15182         addr = XEXP (addr, 1);
15183       else if (CONSTANT_P (XEXP (addr, 1)))
15184         addr = XEXP (addr, 0);
15185       else
15186         abort ();
15187     }
15188   if (GET_CODE (addr) == REG && REGNO (addr) != 0)
15189     return addr;
15190   abort ();
15191 }
15192
15193 void
15194 rs6000_fatal_bad_address (rtx op)
15195 {
15196   fatal_insn ("bad address", op);
15197 }
15198
15199 #if TARGET_MACHO
15200
15201 #if 0
15202 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
15203    reference and a constant.  */
15204
15205 int
15206 symbolic_operand (rtx op)
15207 {
15208   switch (GET_CODE (op))
15209     {
15210     case SYMBOL_REF:
15211     case LABEL_REF:
15212       return 1;
15213     case CONST:
15214       op = XEXP (op, 0);
15215       return (GET_CODE (op) == SYMBOL_REF ||
15216               (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
15217                || GET_CODE (XEXP (op, 0)) == LABEL_REF)
15218               && GET_CODE (XEXP (op, 1)) == CONST_INT);
15219     default:
15220       return 0;
15221     }
15222 }
15223 #endif
15224
15225 #if TARGET_MACHO
15226
15227 static tree branch_island_list = 0;
15228
15229 /* Remember to generate a branch island for far calls to the given
15230    function.  */
15231
15232 static void
15233 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
15234 {
15235   tree branch_island = build_tree_list (function_name, label_name);
15236   TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
15237   TREE_CHAIN (branch_island) = branch_island_list;
15238   branch_island_list = branch_island;
15239 }
15240
15241 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND)     TREE_VALUE (BRANCH_ISLAND)
15242 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND)  TREE_PURPOSE (BRANCH_ISLAND)
15243 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND)    \
15244                 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
15245
15246 /* Generate far-jump branch islands for everything on the
15247    branch_island_list.  Invoked immediately after the last instruction
15248    of the epilogue has been emitted; the branch-islands must be
15249    appended to, and contiguous with, the function body.  Mach-O stubs
15250    are generated in machopic_output_stub().  */
15251
15252 static void
15253 macho_branch_islands (void)
15254 {
15255   char tmp_buf[512];
15256   tree branch_island;
15257
15258   for (branch_island = branch_island_list;
15259        branch_island;
15260        branch_island = TREE_CHAIN (branch_island))
15261     {
15262       const char *label =
15263         IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
15264       const char *name  =
15265         darwin_strip_name_encoding (
15266           IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
15267       char name_buf[512];
15268       /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF().  */
15269       if (name[0] == '*' || name[0] == '&')
15270         strcpy (name_buf, name+1);
15271       else
15272         {
15273           name_buf[0] = '_';
15274           strcpy (name_buf+1, name);
15275         }
15276       strcpy (tmp_buf, "\n");
15277       strcat (tmp_buf, label);
15278 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
15279       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
15280         fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
15281                  BRANCH_ISLAND_LINE_NUMBER(branch_island));
15282 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
15283       if (flag_pic)
15284         {
15285           strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
15286           strcat (tmp_buf, label);
15287           strcat (tmp_buf, "_pic\n");
15288           strcat (tmp_buf, label);
15289           strcat (tmp_buf, "_pic:\n\tmflr r11\n");
15290
15291           strcat (tmp_buf, "\taddis r11,r11,ha16(");
15292           strcat (tmp_buf, name_buf);
15293           strcat (tmp_buf, " - ");
15294           strcat (tmp_buf, label);
15295           strcat (tmp_buf, "_pic)\n");
15296
15297           strcat (tmp_buf, "\tmtlr r0\n");
15298
15299           strcat (tmp_buf, "\taddi r12,r11,lo16(");
15300           strcat (tmp_buf, name_buf);
15301           strcat (tmp_buf, " - ");
15302           strcat (tmp_buf, label);
15303           strcat (tmp_buf, "_pic)\n");
15304
15305           strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
15306         }
15307       else
15308         {
15309           strcat (tmp_buf, ":\nlis r12,hi16(");
15310           strcat (tmp_buf, name_buf);
15311           strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
15312           strcat (tmp_buf, name_buf);
15313           strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
15314         }
15315       output_asm_insn (tmp_buf, 0);
15316 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
15317       if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
15318         fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
15319                 BRANCH_ISLAND_LINE_NUMBER (branch_island));
15320 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
15321     }
15322
15323   branch_island_list = 0;
15324 }
15325
15326 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
15327    already there or not.  */
15328
15329 static int
15330 no_previous_def (tree function_name)
15331 {
15332   tree branch_island;
15333   for (branch_island = branch_island_list;
15334        branch_island;
15335        branch_island = TREE_CHAIN (branch_island))
15336     if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
15337       return 0;
15338   return 1;
15339 }
15340
15341 /* GET_PREV_LABEL gets the label name from the previous definition of
15342    the function.  */
15343
15344 static tree
15345 get_prev_label (tree function_name)
15346 {
15347   tree branch_island;
15348   for (branch_island = branch_island_list;
15349        branch_island;
15350        branch_island = TREE_CHAIN (branch_island))
15351     if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
15352       return BRANCH_ISLAND_LABEL_NAME (branch_island);
15353   return 0;
15354 }
15355
15356 /* INSN is either a function call or a millicode call.  It may have an
15357    unconditional jump in its delay slot.
15358
15359    CALL_DEST is the routine we are calling.  */
15360
15361 char *
15362 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
15363 {
15364   static char buf[256];
15365   if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
15366       && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
15367     {
15368       tree labelname;
15369       tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
15370
15371       if (no_previous_def (funname))
15372         {
15373           int line_number = 0;
15374           rtx label_rtx = gen_label_rtx ();
15375           char *label_buf, temp_buf[256];
15376           ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
15377                                        CODE_LABEL_NUMBER (label_rtx));
15378           label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
15379           labelname = get_identifier (label_buf);
15380           for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
15381           if (insn)
15382             line_number = NOTE_LINE_NUMBER (insn);
15383           add_compiler_branch_island (labelname, funname, line_number);
15384         }
15385       else
15386         labelname = get_prev_label (funname);
15387
15388       /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
15389          instruction will reach 'foo', otherwise link as 'bl L42'".
15390          "L42" should be a 'branch island', that will do a far jump to
15391          'foo'.  Branch islands are generated in
15392          macho_branch_islands().  */
15393       sprintf (buf, "jbsr %%z%d,%.246s",
15394                dest_operand_number, IDENTIFIER_POINTER (labelname));
15395     }
15396   else
15397     sprintf (buf, "bl %%z%d", dest_operand_number);
15398   return buf;
15399 }
15400
15401 #endif /* TARGET_MACHO */
15402
15403 /* Generate PIC and indirect symbol stubs.  */
15404
15405 void
15406 machopic_output_stub (FILE *file, const char *symb, const char *stub)
15407 {
15408   unsigned int length;
15409   char *symbol_name, *lazy_ptr_name;
15410   char *local_label_0;
15411   static int label = 0;
15412
15413   /* Lose our funky encoding stuff so it doesn't contaminate the stub.  */
15414   symb = (*targetm.strip_name_encoding) (symb);
15415
15416
15417   length = strlen (symb);
15418   symbol_name = alloca (length + 32);
15419   GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
15420
15421   lazy_ptr_name = alloca (length + 32);
15422   GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
15423
15424   if (flag_pic == 2)
15425     machopic_picsymbol_stub1_section ();
15426   else
15427     machopic_symbol_stub1_section ();
15428   fprintf (file, "\t.align 2\n");
15429
15430   fprintf (file, "%s:\n", stub);
15431   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
15432
15433   if (flag_pic == 2)
15434     {
15435       label++;
15436       local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
15437       sprintf (local_label_0, "\"L%011d$spb\"", label);
15438
15439       fprintf (file, "\tmflr r0\n");
15440       fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
15441       fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
15442       fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
15443                lazy_ptr_name, local_label_0);
15444       fprintf (file, "\tmtlr r0\n");
15445       fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
15446                lazy_ptr_name, local_label_0);
15447       fprintf (file, "\tmtctr r12\n");
15448       fprintf (file, "\tbctr\n");
15449     }
15450   else
15451    {
15452      fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
15453      fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
15454      fprintf (file, "\tmtctr r12\n");
15455      fprintf (file, "\tbctr\n");
15456    }
15457
15458   machopic_lazy_symbol_ptr_section ();
15459   fprintf (file, "%s:\n", lazy_ptr_name);
15460   fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
15461   fprintf (file, "\t.long dyld_stub_binding_helper\n");
15462 }
15463
15464 /* Legitimize PIC addresses.  If the address is already
15465    position-independent, we return ORIG.  Newly generated
15466    position-independent addresses go into a reg.  This is REG if non
15467    zero, otherwise we allocate register(s) as necessary.  */
15468
15469 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
15470
15471 rtx
15472 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
15473                                         rtx reg)
15474 {
15475   rtx base, offset;
15476
15477   if (reg == NULL && ! reload_in_progress && ! reload_completed)
15478     reg = gen_reg_rtx (Pmode);
15479
15480   if (GET_CODE (orig) == CONST)
15481     {
15482       if (GET_CODE (XEXP (orig, 0)) == PLUS
15483           && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
15484         return orig;
15485
15486       if (GET_CODE (XEXP (orig, 0)) == PLUS)
15487         {
15488           /* Use a different reg for the intermediate value, as
15489              it will be marked UNCHANGING.  */
15490           rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
15491
15492           base =
15493             rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
15494                                                     Pmode, reg_temp);
15495           offset =
15496             rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
15497                                                     Pmode, reg);
15498         }
15499       else
15500         abort ();
15501
15502       if (GET_CODE (offset) == CONST_INT)
15503         {
15504           if (SMALL_INT (offset))
15505             return plus_constant (base, INTVAL (offset));
15506           else if (! reload_in_progress && ! reload_completed)
15507             offset = force_reg (Pmode, offset);
15508           else
15509             {
15510               rtx mem = force_const_mem (Pmode, orig);
15511               return machopic_legitimize_pic_address (mem, Pmode, reg);
15512             }
15513         }
15514       return gen_rtx_PLUS (Pmode, base, offset);
15515     }
15516
15517   /* Fall back on generic machopic code.  */
15518   return machopic_legitimize_pic_address (orig, mode, reg);
15519 }
15520
15521 /* This is just a placeholder to make linking work without having to
15522    add this to the generic Darwin EXTRA_SECTIONS.  If -mcall-aix is
15523    ever needed for Darwin (not too likely!) this would have to get a
15524    real definition.  */
15525
15526 void
15527 toc_section (void)
15528 {
15529 }
15530
15531 #endif /* TARGET_MACHO */
15532
15533 #if TARGET_ELF
15534 static unsigned int
15535 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15536 {
15537   return default_section_type_flags_1 (decl, name, reloc,
15538                                        flag_pic || DEFAULT_ABI == ABI_AIX);
15539 }
15540
15541 /* Record an element in the table of global constructors.  SYMBOL is
15542    a SYMBOL_REF of the function to be called; PRIORITY is a number
15543    between 0 and MAX_INIT_PRIORITY.
15544
15545    This differs from default_named_section_asm_out_constructor in
15546    that we have special handling for -mrelocatable.  */
15547
15548 static void
15549 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15550 {
15551   const char *section = ".ctors";
15552   char buf[16];
15553
15554   if (priority != DEFAULT_INIT_PRIORITY)
15555     {
15556       sprintf (buf, ".ctors.%.5u",
15557                /* Invert the numbering so the linker puts us in the proper
15558                   order; constructors are run from right to left, and the
15559                   linker sorts in increasing order.  */
15560                MAX_INIT_PRIORITY - priority);
15561       section = buf;
15562     }
15563
15564   named_section_flags (section, SECTION_WRITE);
15565   assemble_align (POINTER_SIZE);
15566
15567   if (TARGET_RELOCATABLE)
15568     {
15569       fputs ("\t.long (", asm_out_file);
15570       output_addr_const (asm_out_file, symbol);
15571       fputs (")@fixup\n", asm_out_file);
15572     }
15573   else
15574     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15575 }
15576
15577 static void
15578 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15579 {
15580   const char *section = ".dtors";
15581   char buf[16];
15582
15583   if (priority != DEFAULT_INIT_PRIORITY)
15584     {
15585       sprintf (buf, ".dtors.%.5u",
15586                /* Invert the numbering so the linker puts us in the proper
15587                   order; constructors are run from right to left, and the
15588                   linker sorts in increasing order.  */
15589                MAX_INIT_PRIORITY - priority);
15590       section = buf;
15591     }
15592
15593   named_section_flags (section, SECTION_WRITE);
15594   assemble_align (POINTER_SIZE);
15595
15596   if (TARGET_RELOCATABLE)
15597     {
15598       fputs ("\t.long (", asm_out_file);
15599       output_addr_const (asm_out_file, symbol);
15600       fputs (")@fixup\n", asm_out_file);
15601     }
15602   else
15603     assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15604 }
15605
15606 void
15607 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15608 {
15609   if (TARGET_64BIT)
15610     {
15611       fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15612       ASM_OUTPUT_LABEL (file, name);
15613       fputs (DOUBLE_INT_ASM_OP, file);
15614       putc ('.', file);
15615       assemble_name (file, name);
15616       fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15617       assemble_name (file, name);
15618       fputs (",24\n\t.type\t.", file);
15619       assemble_name (file, name);
15620       fputs (",@function\n", file);
15621       if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15622         {
15623           fputs ("\t.globl\t.", file);
15624           assemble_name (file, name);
15625           putc ('\n', file);
15626         }
15627       ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15628       putc ('.', file);
15629       ASM_OUTPUT_LABEL (file, name);
15630       return;
15631     }
15632
15633   if (TARGET_RELOCATABLE
15634       && (get_pool_size () != 0 || current_function_profile)
15635       && uses_TOC ())
15636     {
15637       char buf[256];
15638
15639       (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15640
15641       ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15642       fprintf (file, "\t.long ");
15643       assemble_name (file, buf);
15644       putc ('-', file);
15645       ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15646       assemble_name (file, buf);
15647       putc ('\n', file);
15648     }
15649
15650   ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15651   ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15652
15653   if (DEFAULT_ABI == ABI_AIX)
15654     {
15655       const char *desc_name, *orig_name;
15656
15657       orig_name = (*targetm.strip_name_encoding) (name);
15658       desc_name = orig_name;
15659       while (*desc_name == '.')
15660         desc_name++;
15661
15662       if (TREE_PUBLIC (decl))
15663         fprintf (file, "\t.globl %s\n", desc_name);
15664
15665       fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15666       fprintf (file, "%s:\n", desc_name);
15667       fprintf (file, "\t.long %s\n", orig_name);
15668       fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15669       if (DEFAULT_ABI == ABI_AIX)
15670         fputs ("\t.long 0\n", file);
15671       fprintf (file, "\t.previous\n");
15672     }
15673   ASM_OUTPUT_LABEL (file, name);
15674 }
15675 #endif
15676
15677 #if TARGET_XCOFF
15678 static void
15679 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15680 {
15681   fputs (GLOBAL_ASM_OP, stream);
15682   RS6000_OUTPUT_BASENAME (stream, name);
15683   putc ('\n', stream);
15684 }
15685
15686 static void
15687 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15688 {
15689   int smclass;
15690   static const char * const suffix[3] = { "PR", "RO", "RW" };
15691
15692   if (flags & SECTION_CODE)
15693     smclass = 0;
15694   else if (flags & SECTION_WRITE)
15695     smclass = 2;
15696   else
15697     smclass = 1;
15698
15699   fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15700            (flags & SECTION_CODE) ? "." : "",
15701            name, suffix[smclass], flags & SECTION_ENTSIZE);
15702 }
15703
15704 static void
15705 rs6000_xcoff_select_section (tree decl, int reloc,
15706                             unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15707 {
15708   if (decl_readonly_section_1 (decl, reloc, 1))
15709     {
15710       if (TREE_PUBLIC (decl))
15711         read_only_data_section ();
15712       else
15713         read_only_private_data_section ();
15714     }
15715   else
15716     {
15717       if (TREE_PUBLIC (decl))
15718         data_section ();
15719       else
15720         private_data_section ();
15721     }
15722 }
15723
15724 static void
15725 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15726 {
15727   const char *name;
15728
15729   /* Use select_section for private and uninitialized data.  */
15730   if (!TREE_PUBLIC (decl)
15731       || DECL_COMMON (decl)
15732       || DECL_INITIAL (decl) == NULL_TREE
15733       || DECL_INITIAL (decl) == error_mark_node
15734       || (flag_zero_initialized_in_bss
15735           && initializer_zerop (DECL_INITIAL (decl))))
15736     return;
15737
15738   name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15739   name = (*targetm.strip_name_encoding) (name);
15740   DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15741 }
15742
15743 /* Select section for constant in constant pool.
15744
15745    On RS/6000, all constants are in the private read-only data area.
15746    However, if this is being placed in the TOC it must be output as a
15747    toc entry.  */
15748
15749 static void
15750 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15751                                 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15752 {
15753   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15754     toc_section ();
15755   else
15756     read_only_private_data_section ();
15757 }
15758
15759 /* Remove any trailing [DS] or the like from the symbol name.  */
15760
15761 static const char *
15762 rs6000_xcoff_strip_name_encoding (const char *name)
15763 {
15764   size_t len;
15765   if (*name == '*')
15766     name++;
15767   len = strlen (name);
15768   if (name[len - 1] == ']')
15769     return ggc_alloc_string (name, len - 4);
15770   else
15771     return name;
15772 }
15773
15774 /* Section attributes.  AIX is always PIC.  */
15775
15776 static unsigned int
15777 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15778 {
15779   unsigned int align;
15780   unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15781
15782   /* Align to at least UNIT size.  */
15783   if (flags & SECTION_CODE)
15784     align = MIN_UNITS_PER_WORD;
15785   else
15786     /* Increase alignment of large objects if not already stricter.  */
15787     align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15788                  int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15789                  ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15790
15791   return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15792 }
15793
15794 /* Output at beginning of assembler file.
15795
15796    Initialize the section names for the RS/6000 at this point.
15797
15798    Specify filename, including full path, to assembler.
15799
15800    We want to go into the TOC section so at least one .toc will be emitted.
15801    Also, in order to output proper .bs/.es pairs, we need at least one static
15802    [RW] section emitted.
15803
15804    Finally, declare mcount when profiling to make the assembler happy.  */
15805
15806 static void
15807 rs6000_xcoff_file_start (void)
15808 {
15809   rs6000_gen_section_name (&xcoff_bss_section_name,
15810                            main_input_filename, ".bss_");
15811   rs6000_gen_section_name (&xcoff_private_data_section_name,
15812                            main_input_filename, ".rw_");
15813   rs6000_gen_section_name (&xcoff_read_only_section_name,
15814                            main_input_filename, ".ro_");
15815
15816   fputs ("\t.file\t", asm_out_file);
15817   output_quoted_string (asm_out_file, main_input_filename);
15818   fputc ('\n', asm_out_file);
15819   toc_section ();
15820   if (write_symbols != NO_DEBUG)
15821     private_data_section ();
15822   text_section ();
15823   if (profile_flag)
15824     fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15825   rs6000_file_start ();
15826 }
15827
15828 /* Output at end of assembler file.
15829    On the RS/6000, referencing data should automatically pull in text.  */
15830
15831 static void
15832 rs6000_xcoff_file_end (void)
15833 {
15834   text_section ();
15835   fputs ("_section_.text:\n", asm_out_file);
15836   data_section ();
15837   fputs (TARGET_32BIT
15838          ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15839          asm_out_file);
15840 }
15841 #endif /* TARGET_XCOFF */
15842
15843 #if TARGET_MACHO
15844 /* Cross-module name binding.  Darwin does not support overriding
15845    functions at dynamic-link time.  */
15846
15847 static bool
15848 rs6000_binds_local_p (tree decl)
15849 {
15850   return default_binds_local_p_1 (decl, 0);
15851 }
15852 #endif
15853
15854 /* Compute a (partial) cost for rtx X.  Return true if the complete
15855    cost has been computed, and false if subexpressions should be
15856    scanned.  In either case, *TOTAL contains the cost result.  */
15857
15858 static bool
15859 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15860                   int *total)
15861 {
15862   switch (code)
15863     {
15864       /* On the RS/6000, if it is valid in the insn, it is free.
15865          So this always returns 0.  */
15866     case CONST_INT:
15867     case CONST:
15868     case LABEL_REF:
15869     case SYMBOL_REF:
15870     case CONST_DOUBLE:
15871     case HIGH:
15872       *total = 0;
15873       return true;
15874
15875     case PLUS:
15876       *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15877                  && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15878                                                + 0x8000) >= 0x10000)
15879                  && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15880                 ? COSTS_N_INSNS (2)
15881                 : COSTS_N_INSNS (1));
15882       return true;
15883
15884     case AND:
15885     case IOR:
15886     case XOR:
15887       *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15888                  && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15889                  && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15890                 ? COSTS_N_INSNS (2)
15891                 : COSTS_N_INSNS (1));
15892       return true;
15893
15894     case MULT:
15895       if (optimize_size)
15896         {
15897           *total = COSTS_N_INSNS (2);
15898           return true;
15899         }
15900       switch (rs6000_cpu)
15901         {
15902         case PROCESSOR_RIOS1:
15903         case PROCESSOR_PPC405:
15904           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15905                     ? COSTS_N_INSNS (5)
15906                     : (INTVAL (XEXP (x, 1)) >= -256
15907                        && INTVAL (XEXP (x, 1)) <= 255)
15908                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15909           return true;
15910
15911         case PROCESSOR_PPC440:
15912           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15913                     ? COSTS_N_INSNS (3)
15914                     : COSTS_N_INSNS (2));
15915           return true;
15916
15917         case PROCESSOR_RS64A:
15918           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15919                     ? GET_MODE (XEXP (x, 1)) != DImode
15920                     ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
15921                     : (INTVAL (XEXP (x, 1)) >= -256
15922                        && INTVAL (XEXP (x, 1)) <= 255)
15923                     ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
15924           return true;
15925
15926         case PROCESSOR_RIOS2:
15927         case PROCESSOR_MPCCORE:
15928         case PROCESSOR_PPC604e:
15929           *total = COSTS_N_INSNS (2);
15930           return true;
15931
15932         case PROCESSOR_PPC601:
15933           *total = COSTS_N_INSNS (5);
15934           return true;
15935
15936         case PROCESSOR_PPC603:
15937         case PROCESSOR_PPC7400:
15938         case PROCESSOR_PPC750:
15939           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15940                     ? COSTS_N_INSNS (5)
15941                     : (INTVAL (XEXP (x, 1)) >= -256
15942                        && INTVAL (XEXP (x, 1)) <= 255)
15943                     ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
15944           return true;
15945
15946         case PROCESSOR_PPC7450:
15947           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15948                     ? COSTS_N_INSNS (4)
15949                     : COSTS_N_INSNS (3));
15950           return true;
15951
15952         case PROCESSOR_PPC403:
15953         case PROCESSOR_PPC604:
15954         case PROCESSOR_PPC8540:
15955           *total = COSTS_N_INSNS (4);
15956           return true;
15957
15958         case PROCESSOR_PPC620:
15959         case PROCESSOR_PPC630:
15960           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15961                     ? GET_MODE (XEXP (x, 1)) != DImode
15962                     ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
15963                     : (INTVAL (XEXP (x, 1)) >= -256
15964                        && INTVAL (XEXP (x, 1)) <= 255)
15965                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15966           return true;
15967
15968         case PROCESSOR_POWER4:
15969         case PROCESSOR_POWER5:
15970           *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15971                     ? GET_MODE (XEXP (x, 1)) != DImode
15972                     ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
15973                     : COSTS_N_INSNS (2));
15974           return true;
15975
15976         default:
15977           abort ();
15978         }
15979
15980     case DIV:
15981     case MOD:
15982       if (GET_CODE (XEXP (x, 1)) == CONST_INT
15983           && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
15984         {
15985           *total = COSTS_N_INSNS (2);
15986           return true;
15987         }
15988       /* FALLTHRU */
15989
15990     case UDIV:
15991     case UMOD:
15992       switch (rs6000_cpu)
15993         {
15994         case PROCESSOR_RIOS1:
15995           *total = COSTS_N_INSNS (19);
15996           return true;
15997
15998         case PROCESSOR_RIOS2:
15999           *total = COSTS_N_INSNS (13);
16000           return true;
16001
16002         case PROCESSOR_RS64A:
16003           *total = (GET_MODE (XEXP (x, 1)) != DImode
16004                     ? COSTS_N_INSNS (65)
16005                     : COSTS_N_INSNS (67));
16006           return true;
16007
16008         case PROCESSOR_MPCCORE:
16009           *total = COSTS_N_INSNS (6);
16010           return true;
16011
16012         case PROCESSOR_PPC403:
16013           *total = COSTS_N_INSNS (33);
16014           return true;
16015
16016         case PROCESSOR_PPC405:
16017           *total = COSTS_N_INSNS (35);
16018           return true;
16019
16020         case PROCESSOR_PPC440:
16021           *total = COSTS_N_INSNS (34);
16022           return true;
16023
16024         case PROCESSOR_PPC601:
16025           *total = COSTS_N_INSNS (36);
16026           return true;
16027
16028         case PROCESSOR_PPC603:
16029           *total = COSTS_N_INSNS (37);
16030           return true;
16031
16032         case PROCESSOR_PPC604:
16033         case PROCESSOR_PPC604e:
16034           *total = COSTS_N_INSNS (20);
16035           return true;
16036
16037         case PROCESSOR_PPC620:
16038         case PROCESSOR_PPC630:
16039           *total = (GET_MODE (XEXP (x, 1)) != DImode
16040                     ? COSTS_N_INSNS (21)
16041                     : COSTS_N_INSNS (37));
16042           return true;
16043
16044         case PROCESSOR_PPC750:
16045         case PROCESSOR_PPC8540:
16046         case PROCESSOR_PPC7400:
16047           *total = COSTS_N_INSNS (19);
16048           return true;
16049
16050         case PROCESSOR_PPC7450:
16051           *total = COSTS_N_INSNS (23);
16052           return true;
16053
16054         case PROCESSOR_POWER4:
16055         case PROCESSOR_POWER5:
16056           *total = (GET_MODE (XEXP (x, 1)) != DImode
16057                     ? COSTS_N_INSNS (18)
16058                     : COSTS_N_INSNS (34));
16059           return true;
16060
16061         default:
16062           abort ();
16063         }
16064
16065     case FFS:
16066       *total = COSTS_N_INSNS (4);
16067       return true;
16068
16069     case MEM:
16070       /* MEM should be slightly more expensive than (plus (reg) (const)).  */
16071       *total = 5;
16072       return true;
16073
16074     default:
16075       return false;
16076     }
16077 }
16078
16079 /* A C expression returning the cost of moving data from a register of class
16080    CLASS1 to one of CLASS2.  */
16081
16082 int
16083 rs6000_register_move_cost (enum machine_mode mode,
16084                            enum reg_class from, enum reg_class to)
16085 {
16086   /*  Moves from/to GENERAL_REGS.  */
16087   if (reg_classes_intersect_p (to, GENERAL_REGS)
16088       || reg_classes_intersect_p (from, GENERAL_REGS))
16089     {
16090       if (! reg_classes_intersect_p (to, GENERAL_REGS))
16091         from = to;
16092
16093       if (from == FLOAT_REGS || from == ALTIVEC_REGS)
16094         return (rs6000_memory_move_cost (mode, from, 0)
16095                 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
16096
16097 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift....  */
16098       else if (from == CR_REGS)
16099         return 4;
16100
16101       else
16102 /* A move will cost one instruction per GPR moved.  */
16103         return 2 * HARD_REGNO_NREGS (0, mode);
16104     }
16105
16106 /* Moving between two similar registers is just one instruction.  */
16107   else if (reg_classes_intersect_p (to, from))
16108     return mode == TFmode ? 4 : 2;
16109
16110 /* Everything else has to go through GENERAL_REGS.  */
16111   else
16112     return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
16113             + rs6000_register_move_cost (mode, from, GENERAL_REGS));
16114 }
16115
16116 /* A C expressions returning the cost of moving data of MODE from a register to
16117    or from memory.  */
16118
16119 int
16120 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
16121                          int in ATTRIBUTE_UNUSED)
16122 {
16123   if (reg_classes_intersect_p (class, GENERAL_REGS))
16124     return 4 * HARD_REGNO_NREGS (0, mode);
16125   else if (reg_classes_intersect_p (class, FLOAT_REGS))
16126     return 4 * HARD_REGNO_NREGS (32, mode);
16127   else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
16128     return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
16129   else
16130     return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
16131 }
16132
16133 /* Return an RTX representing where to find the function value of a
16134    function returning MODE.  */
16135 static rtx
16136 rs6000_complex_function_value (enum machine_mode mode)
16137 {
16138   unsigned int regno;
16139   rtx r1, r2;
16140   enum machine_mode inner = GET_MODE_INNER (mode);
16141   unsigned int inner_bytes = GET_MODE_SIZE (inner);
16142
16143   if (FLOAT_MODE_P (mode))
16144     regno = FP_ARG_RETURN;
16145   else
16146     {
16147       regno = GP_ARG_RETURN;
16148
16149       /* 32-bit is OK since it'll go in r3/r4.  */
16150       if (TARGET_32BIT && inner_bytes >= 4)
16151         return gen_rtx_REG (mode, regno);
16152     }
16153
16154   if (inner_bytes >= 8)
16155     return gen_rtx_REG (mode, regno);
16156
16157   r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
16158                           const0_rtx);
16159   r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
16160                           GEN_INT (inner_bytes));
16161   return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
16162 }
16163
16164 /* Define how to find the value returned by a function.
16165    VALTYPE is the data type of the value (as a tree).
16166    If the precise function being called is known, FUNC is its FUNCTION_DECL;
16167    otherwise, FUNC is 0.
16168
16169    On the SPE, both FPs and vectors are returned in r3.
16170
16171    On RS/6000 an integer value is in r3 and a floating-point value is in
16172    fp1, unless -msoft-float.  */
16173
16174 rtx
16175 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
16176 {
16177   enum machine_mode mode;
16178   unsigned int regno;
16179
16180   if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
16181     {
16182       /* Long long return value need be split in -mpowerpc64, 32bit ABI.  */
16183       return gen_rtx_PARALLEL (DImode,
16184         gen_rtvec (2,
16185                    gen_rtx_EXPR_LIST (VOIDmode,
16186                                       gen_rtx_REG (SImode, GP_ARG_RETURN),
16187                                       const0_rtx),
16188                    gen_rtx_EXPR_LIST (VOIDmode,
16189                                       gen_rtx_REG (SImode,
16190                                                    GP_ARG_RETURN + 1),
16191                                       GEN_INT (4))));
16192     }
16193
16194   if ((INTEGRAL_TYPE_P (valtype)
16195        && TYPE_PRECISION (valtype) < BITS_PER_WORD)
16196       || POINTER_TYPE_P (valtype))
16197     mode = TARGET_32BIT ? SImode : DImode;
16198   else
16199     mode = TYPE_MODE (valtype);
16200
16201   if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
16202     regno = FP_ARG_RETURN;
16203   else if (TREE_CODE (valtype) == COMPLEX_TYPE
16204            && TARGET_HARD_FLOAT
16205            && targetm.calls.split_complex_arg)
16206     return rs6000_complex_function_value (mode);
16207   else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC)
16208     regno = ALTIVEC_ARG_RETURN;
16209   else
16210     regno = GP_ARG_RETURN;
16211
16212   return gen_rtx_REG (mode, regno);
16213 }
16214
16215 /* Define how to find the value returned by a library function
16216    assuming the value has mode MODE.  */
16217 rtx
16218 rs6000_libcall_value (enum machine_mode mode)
16219 {
16220   unsigned int regno;
16221
16222   if (GET_MODE_CLASS (mode) == MODE_FLOAT
16223            && TARGET_HARD_FLOAT && TARGET_FPRS)
16224     regno = FP_ARG_RETURN;
16225   else if (ALTIVEC_VECTOR_MODE (mode))
16226     regno = ALTIVEC_ARG_RETURN;
16227   else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
16228     return rs6000_complex_function_value (mode);
16229   else
16230     regno = GP_ARG_RETURN;
16231
16232   return gen_rtx_REG (mode, regno);
16233 }
16234
16235 /* Define the offset between two registers, FROM to be eliminated and its
16236    replacement TO, at the start of a routine.  */
16237 HOST_WIDE_INT
16238 rs6000_initial_elimination_offset (int from, int to)
16239 {
16240   rs6000_stack_t *info = rs6000_stack_info ();
16241   HOST_WIDE_INT offset;
16242
16243   if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
16244     offset = info->push_p ? 0 : -info->total_size;
16245   else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
16246     offset = info->total_size;
16247   else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
16248     offset = info->push_p ? info->total_size : 0;
16249   else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
16250     offset = 0;
16251   else
16252     abort ();
16253
16254   return offset;
16255 }
16256
16257 /* Return true if TYPE is of type __ev64_opaque__.  */
16258
16259 static bool
16260 is_ev64_opaque_type (tree type)
16261 {
16262   return (TARGET_SPE
16263           && (type == opaque_V2SI_type_node
16264               || type == opaque_V2SF_type_node
16265               || type == opaque_p_V2SI_type_node));
16266 }
16267
16268 static rtx
16269 rs6000_dwarf_register_span (rtx reg)
16270 {
16271   unsigned regno;
16272
16273   if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
16274     return NULL_RTX;
16275
16276   regno = REGNO (reg);
16277
16278   /* The duality of the SPE register size wreaks all kinds of havoc.
16279      This is a way of distinguishing r0 in 32-bits from r0 in
16280      64-bits.  */
16281   return
16282     gen_rtx_PARALLEL (VOIDmode,
16283                       BYTES_BIG_ENDIAN
16284                       ? gen_rtvec (2,
16285                                    gen_rtx_REG (SImode, regno + 1200),
16286                                    gen_rtx_REG (SImode, regno))
16287                       : gen_rtvec (2,
16288                                    gen_rtx_REG (SImode, regno),
16289                                    gen_rtx_REG (SImode, regno + 1200)));
16290 }
16291
16292 /* Map internal gcc register numbers to DWARF2 register numbers.  */
16293
16294 unsigned int
16295 rs6000_dbx_register_number (unsigned int regno)
16296 {
16297   if (regno <= 63 || write_symbols != DWARF2_DEBUG)
16298     return regno;
16299   if (regno == MQ_REGNO)
16300     return 100;
16301   if (regno == LINK_REGISTER_REGNUM)
16302     return 108;
16303   if (regno == COUNT_REGISTER_REGNUM)
16304     return 109;
16305   if (CR_REGNO_P (regno))
16306     return regno - CR0_REGNO + 86;
16307   if (regno == XER_REGNO)
16308     return 101;
16309   if (ALTIVEC_REGNO_P (regno))
16310     return regno - FIRST_ALTIVEC_REGNO + 1124;
16311   if (regno == VRSAVE_REGNO)
16312     return 356;
16313   if (regno == VSCR_REGNO)
16314     return 67;
16315   if (regno == SPE_ACC_REGNO)
16316     return 99;
16317   if (regno == SPEFSCR_REGNO)
16318     return 612;
16319   /* SPE high reg number.  We get these values of regno from
16320      rs6000_dwarf_register_span.  */
16321   if (regno >= 1200 && regno < 1232)
16322     return regno;
16323
16324   abort ();
16325 }
16326
16327 #include "gt-rs6000.h"