gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2015 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27
  28 /* Computing the Length of an Insn.  */
  29 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  30   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  31
  32 /* Check instruction LS-37-FP-implied form.
  33    Note: actually its immediate range is imm9u
  34          since it is used for lwi37/swi37 instructions.  */
  35 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  36   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  37    && REGNO (ra) == FP_REGNUM               \
  38    && satisfies_constraint_Iu09 (imm))
  39
  40 /* Check instruction LS-37-SP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == SP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48
  49 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  50 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  51
  52 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  53    Note: no need to check ra because Ra5 means it covers all registers.  */
  54 #define NDS32_LS_450_P(rt, ra, imm)                     \
  55   ((imm == const0_rtx)                                  \
  56    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  57        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  58
  59 /* Check instruction RRI-333-form.  */
  60 #define NDS32_RRI_333_P(rt, ra, imm)           \
  61   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  62    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  63    && satisfies_constraint_Iu03 (imm))
  64
  65 /* Check instruction RI-45-form.  */
  66 #define NDS32_RI_45_P(rt, ra, imm)                     \
  67   (REGNO (rt) == REGNO (ra)                            \
  68    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  69        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  70    && satisfies_constraint_Iu05 (imm))
  71
  72
  73 /* Check instruction RR-33-form.  */
  74 #define NDS32_RR_33_P(rt, ra)                   \
  75   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  76    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  77
  78 /* Check instruction RRR-333-form.  */
  79 #define NDS32_RRR_333_P(rt, ra, rb)             \
  80   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  81    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  82    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  83
  84 /* Check instruction RR-45-form.
  85    Note: no need to check rb because Rb5 means it covers all registers.  */
  86 #define NDS32_RR_45_P(rt, ra, rb)               \
  87   (REGNO (rt) == REGNO (ra)                     \
  88    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  89        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  90
  91 /* Classifies address type to distinguish 16-bit/32-bit format.  */
  92 enum nds32_16bit_address_type
  93 {
  94   /* [reg]: 45 format address.  */
  95   ADDRESS_REG,
  96   /* [lo_reg + imm3u]: 333 format address.  */
  97   ADDRESS_LO_REG_IMM3U,
  98   /* post_inc [lo_reg + imm3u]: 333 format address.  */
  99   ADDRESS_POST_INC_LO_REG_IMM3U,
 100   /* [$fp + imm7u]: fp imply address.  */
 101   ADDRESS_FP_IMM7U,
 102   /* [$sp + imm7u]: sp imply address.  */
 103   ADDRESS_SP_IMM7U,
 104   /* Other address format.  */
 105   ADDRESS_NOT_16BIT_FORMAT
 106 };
 107
 108
 109 /* ------------------------------------------------------------------------ */
 110
 111 /* Define maximum numbers of registers for passing arguments.  */
 112 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 113
 114 /* Define the register number for first argument.  */
 115 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 116
 117 /* Define the register number for return value.  */
 118 #define NDS32_GPR_RET_FIRST_REGNUM 0
 119
 120 /* Define the first integer register number.  */
 121 #define NDS32_FIRST_GPR_REGNUM 0
 122 /* Define the last integer register number.  */
 123 #define NDS32_LAST_GPR_REGNUM 31
 124
 125 /* Define double word alignment bits.  */
 126 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 127
 128 /* Define alignment checking macros for convenience.  */
 129 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 130 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 131 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 132
 133 /* Get alignment according to mode or type information.
 134    When 'type' is nonnull, there is no need to look at 'mode'.  */
 135 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 136   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 137
 138 /* Round X up to the nearest double word.  */
 139 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 140
 141
 142 /* This macro is used to calculate the numbers of registers for
 143    containing 'size' bytes of the argument.
 144    The size of a register is a word in nds32 target.
 145    So we use UNITS_PER_WORD to do the calculation.  */
 146 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 147   ((mode == BLKmode)                                                     \
 148    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 149    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 150
 151 /* This macro is used to return the register number for passing argument.
 152    We need to obey the following rules:
 153      1. If it is required MORE THAN one register,
 154         we need to further check if it really needs to be
 155         aligned on double words.
 156           a) If double word alignment is necessary,
 157              the register number must be even value.
 158           b) Otherwise, the register number can be odd or even value.
 159      2. If it is required ONLY one register,
 160         the register number can be odd or even value.  */
 161 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type)  \
 162   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                     \
 163    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)          \
 164       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)      \
 165       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))                \
 166    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 167
 168 /* This macro is to check if there are still available registers
 169    for passing argument, which must be entirely in registers.  */
 170 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 171   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 172     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 173    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 174        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 175
 176 /* This macro is to check if there are still available registers
 177    for passing argument, either entirely in registers or partially
 178    in registers.  */
 179 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 180   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 181    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 182
 183 /* This macro is to check if the register is required to be saved on stack.
 184    If call_used_regs[regno] == 0, regno is the callee-saved register.
 185    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 186    As long as the register satisfies both criteria above,
 187    it is required to be saved.  */
 188 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 189   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 190
 191 /* ------------------------------------------------------------------------ */
 192
 193 /* A C structure for machine-specific, per-function data.
 194    This is added to the cfun structure.  */
 195 struct GTY(()) machine_function
 196 {
 197   /* Number of bytes allocated on the stack for variadic args
 198      if we want to push them into stack as pretend arguments by ourself.  */
 199   int va_args_size;
 200   /* Number of bytes reserved on the stack for
 201      local and temporary variables.  */
 202   int local_size;
 203   /* Number of bytes allocated on the stack for outgoing arguments.  */
 204   int out_args_size;
 205
 206   /* Number of bytes on the stack for saving $fp.  */
 207   int fp_size;
 208   /* Number of bytes on the stack for saving $gp.  */
 209   int gp_size;
 210   /* Number of bytes on the stack for saving $lp.  */
 211   int lp_size;
 212
 213   /* Number of bytes on the stack for saving callee-saved registers.  */
 214   int callee_saved_regs_size;
 215   /* The padding bytes in callee-saved area may be required.  */
 216   int callee_saved_area_padding_bytes;
 217
 218   /* The first required callee-saved register.  */
 219   int callee_saved_regs_first_regno;
 220   /* The last required callee-saved register.  */
 221   int callee_saved_regs_last_regno;
 222
 223   /* The padding bytes in varargs area may be required.  */
 224   int va_args_area_padding_bytes;
 225
 226   /* The first required register that should be saved on stack for va_args.  */
 227   int va_args_first_regno;
 228   /* The last required register that should be saved on stack for va_args.  */
 229   int va_args_last_regno;
 230
 231   /* Indicate that whether this function needs
 232      prologue/epilogue code generation.  */
 233   int naked_p;
 234   /* Indicate that whether this function
 235      uses fp_as_gp optimization.  */
 236   int fp_as_gp_p;
 237 };
 238
 239 /* A C structure that contains the arguments information.  */
 240 typedef struct
 241 {
 242   unsigned int gpr_offset;
 243 } nds32_cumulative_args;
 244
 245 /* ------------------------------------------------------------------------ */
 246
 247 /* The following we define C-ISR related stuff.
 248    In nds32 architecture, we have 73 vectors for interrupt/exception.
 249    For each vector (except for vector 0, which is used for reset behavior),
 250    we allow users to set its register saving scheme and interrupt level.  */
 251
 252 /* There are 73 vectors in nds32 architecture.
 253    0 for reset handler,
 254    1-8 for exception handler,
 255    and 9-72 for interrupt handler.
 256    We use an array, which is defined in nds32.c, to record
 257    essential information for each vector.  */
 258 #define NDS32_N_ISR_VECTORS 73
 259
 260 /* Define possible isr category.  */
 261 enum nds32_isr_category
 262 {
 263   NDS32_ISR_NONE,
 264   NDS32_ISR_INTERRUPT,
 265   NDS32_ISR_EXCEPTION,
 266   NDS32_ISR_RESET
 267 };
 268
 269 /* Define isr register saving scheme.  */
 270 enum nds32_isr_save_reg
 271 {
 272   NDS32_SAVE_ALL,
 273   NDS32_PARTIAL_SAVE
 274 };
 275
 276 /* Define isr nested type.  */
 277 enum nds32_isr_nested_type
 278 {
 279   NDS32_NESTED,
 280   NDS32_NOT_NESTED,
 281   NDS32_NESTED_READY
 282 };
 283
 284 /* Define structure to record isr information.
 285    The isr vector array 'isr_vectors[]' with this structure
 286    is defined in nds32.c.  */
 287 struct nds32_isr_info
 288 {
 289   /* The field to identify isr category.
 290      It should be set to NDS32_ISR_NONE by default.
 291      If user specifies a function as isr by using attribute,
 292      this field will be set accordingly.  */
 293   enum nds32_isr_category category;
 294
 295   /* A string for the applied function name.
 296      It should be set to empty string by default.  */
 297   char func_name[100];
 298
 299   /* The register saving scheme.
 300      It should be set to NDS32_PARTIAL_SAVE by default
 301      unless user specifies attribute to change it.  */
 302   enum nds32_isr_save_reg save_reg;
 303
 304   /* The nested type.
 305      It should be set to NDS32_NOT_NESTED by default
 306      unless user specifies attribute to change it.  */
 307   enum nds32_isr_nested_type nested_type;
 308
 309   /* Total vectors.
 310      The total vectors = interrupt + exception numbers + reset.
 311      It should be set to 0 by default.
 312      This field is ONLY used in NDS32_ISR_RESET category.  */
 313   unsigned int total_n_vectors;
 314
 315   /* A string for nmi handler name.
 316      It should be set to empty string by default.
 317      This field is ONLY used in NDS32_ISR_RESET category.  */
 318   char nmi_name[100];
 319
 320   /* A string for warm handler name.
 321      It should be set to empty string by default.
 322      This field is ONLY used in NDS32_ISR_RESET category.  */
 323   char warm_name[100];
 324 };
 325
 326 /* ------------------------------------------------------------------------ */
 327
 328 /* Define code for all nds32 builtins.  */
 329 enum nds32_builtins
 330 {
 331   NDS32_BUILTIN_ISYNC,
 332   NDS32_BUILTIN_ISB,
 333   NDS32_BUILTIN_MFSR,
 334   NDS32_BUILTIN_MFUSR,
 335   NDS32_BUILTIN_MTSR,
 336   NDS32_BUILTIN_MTUSR,
 337   NDS32_BUILTIN_SETGIE_EN,
 338   NDS32_BUILTIN_SETGIE_DIS
 339 };
 340
 341 /* ------------------------------------------------------------------------ */
 342
 343 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 344 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 345 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 346
 347 #define TARGET_CMODEL_SMALL \
 348    (nds32_cmodel_option == CMODEL_SMALL)
 349 #define TARGET_CMODEL_MEDIUM \
 350    (nds32_cmodel_option == CMODEL_MEDIUM)
 351 #define TARGET_CMODEL_LARGE \
 352    (nds32_cmodel_option == CMODEL_LARGE)
 353
 354 /* When -mcmodel=small or -mcmodel=medium,
 355    compiler may generate gp-base instruction directly.  */
 356 #define TARGET_GP_DIRECT \
 357    (nds32_cmodel_option == CMODEL_SMALL\
 358     || nds32_cmodel_option == CMODEL_MEDIUM)
 359
 360 #define TARGET_SOFT_FLOAT 1
 361 #define TARGET_HARD_FLOAT 0
 362
 363 /* ------------------------------------------------------------------------ */
 364 \f
 365 /* Controlling the Compilation Driver.  */
 366
 367 #define OPTION_DEFAULT_SPECS \
 368   {"arch", "%{!march=*:-march=%(VALUE)}" }
 369
 370 #define CC1_SPEC \
 371   ""
 372
 373 #define ASM_SPEC \
 374   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 375
 376 /* If user issues -mrelax, -mforce-fp-as-gp, or -mex9,
 377    we need to pass '--relax' to linker.
 378    Besides, for -mex9, we need to further pass '--mex9'.  */
 379 #define LINK_SPEC \
 380   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 381   " %{mrelax|mforce-fp-as-gp|mex9:--relax}" \
 382   " %{mex9:--mex9}"
 383
 384 #define LIB_SPEC \
 385   " -lc -lgloss"
 386
 387 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 388    by applying different crt stuff.  In the convention, crt0.o is the
 389    startup file without constructor/destructor;
 390    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 391    startup files with constructor/destructor.
 392    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 393    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 394    currently provided by GCC for nds32 target.
 395
 396    For nds32 target so far:
 397    If -mno-ctor-dtor, we are going to link
 398    "crt0.o [user objects]".
 399    If general cases, we are going to link
 400    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 401 #define STARTFILE_SPEC \
 402   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 403   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 404 #define ENDFILE_SPEC \
 405   " %{!mno-ctor-dtor:crtend1.o%s}"
 406
 407 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 408    configure gcc with --target=nds32be-* setting.
 409    Check gcc/config.gcc for more information.  */
 410 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 411 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 412 #else
 413 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 414 #endif
 415
 416 /* Currently we only have elf toolchain,
 417    where -mcmodel=medium is always the default.  */
 418 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 419
 420 #define MULTILIB_DEFAULTS \
 421   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 422
 423 \f
 424 /* Run-time Target Specification.  */
 425
 426 #define TARGET_CPU_CPP_BUILTINS()                     \
 427   do                                                  \
 428     {                                                 \
 429       builtin_define ("__nds32__");                   \
 430                                                       \
 431       if (TARGET_ISA_V2)                              \
 432         builtin_define ("__NDS32_ISA_V2__");          \
 433       if (TARGET_ISA_V3)                              \
 434         builtin_define ("__NDS32_ISA_V3__");          \
 435       if (TARGET_ISA_V3M)                             \
 436         builtin_define ("__NDS32_ISA_V3M__");         \
 437                                                       \
 438       if (TARGET_BIG_ENDIAN)                          \
 439         builtin_define ("__big_endian__");            \
 440       if (TARGET_REDUCED_REGS)                        \
 441         builtin_define ("__NDS32_REDUCED_REGS__");    \
 442       if (TARGET_CMOV)                                \
 443         builtin_define ("__NDS32_CMOV__");            \
 444       if (TARGET_PERF_EXT)                            \
 445         builtin_define ("__NDS32_PERF_EXT__");        \
 446       if (TARGET_16_BIT)                              \
 447         builtin_define ("__NDS32_16_BIT__");          \
 448       if (TARGET_GP_DIRECT)                           \
 449         builtin_define ("__NDS32_GP_DIRECT__");       \
 450                                                       \
 451       builtin_assert ("cpu=nds32");                   \
 452       builtin_assert ("machine=nds32");               \
 453     } while (0)
 454
 455 \f
 456 /* Defining Data Structures for Per-function Information.  */
 457
 458 /* This macro is called once per function,
 459    before generation of any RTL has begun.  */
 460 #define INIT_EXPANDERS  nds32_init_expanders ()
 461
 462 \f
 463 /* Storage Layout.  */
 464
 465 #define BITS_BIG_ENDIAN 0
 466
 467 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 468
 469 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 470
 471 #define UNITS_PER_WORD 4
 472
 473 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 474   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 475     {                                                                       \
 476       (m) = SImode;                                                         \
 477     }
 478
 479 #define PARM_BOUNDARY 32
 480
 481 #define STACK_BOUNDARY 64
 482
 483 #define FUNCTION_BOUNDARY 32
 484
 485 #define BIGGEST_ALIGNMENT 64
 486
 487 #define EMPTY_FIELD_BOUNDARY 32
 488
 489 #define STRUCTURE_SIZE_BOUNDARY 8
 490
 491 #define STRICT_ALIGNMENT 1
 492
 493 #define PCC_BITFIELD_TYPE_MATTERS 1
 494
 495 \f
 496 /* Layout of Source Language Data Types.  */
 497
 498 #define INT_TYPE_SIZE           32
 499 #define SHORT_TYPE_SIZE         16
 500 #define LONG_TYPE_SIZE          32
 501 #define LONG_LONG_TYPE_SIZE     64
 502
 503 #define FLOAT_TYPE_SIZE         32
 504 #define DOUBLE_TYPE_SIZE        64
 505 #define LONG_DOUBLE_TYPE_SIZE   64
 506
 507 #define DEFAULT_SIGNED_CHAR 1
 508
 509 #define SIZE_TYPE "long unsigned int"
 510 #define PTRDIFF_TYPE "long int"
 511 #define WCHAR_TYPE "short unsigned int"
 512 #define WCHAR_TYPE_SIZE 16
 513
 514 \f
 515 /* Register Usage.  */
 516
 517 /* Number of actual hardware registers.
 518    The hardware registers are assigned numbers for the compiler
 519    from 0 to just below FIRST_PSEUDO_REGISTER.
 520    All registers that the compiler knows about must be given numbers,
 521    even those that are not normally considered general registers.  */
 522 #define FIRST_PSEUDO_REGISTER 34
 523
 524 /* An initializer that says which registers are used for fixed
 525    purposes all throughout the compiled code and are therefore
 526    not available for general allocation.
 527
 528    $r28 : $fp
 529    $r29 : $gp
 530    $r30 : $lp
 531    $r31 : $sp
 532
 533    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 534    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 535
 536    reserved for assembler : $r15
 537    reserved for other use : $r24, $r25, $r26, $r27 */
 538 #define FIXED_REGISTERS                 \
 539 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 540       0,  0,  0,  0,  0,  0,  0,  0,    \
 541   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 542       0,  0,  0,  0,  0,  0,  0,  1,    \
 543   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 544       0,  0,  0,  0,  0,  0,  0,  0,    \
 545   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 546       1,  1,  1,  1,  0,  1,  0,  1,    \
 547   /* ARG_POINTER:32 */                  \
 548       1,                                \
 549   /* FRAME_POINTER:33 */                \
 550       1                                 \
 551 }
 552
 553 /* Identifies the registers that are not available for
 554    general allocation of values that must live across
 555    function calls -- so they are caller-save registers.
 556
 557    0 : callee-save registers
 558    1 : caller-save registers */
 559 #define CALL_USED_REGISTERS             \
 560 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 561       1,  1,  1,  1,  1,  1,  0,  0,    \
 562   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 563       0,  0,  0,  0,  0,  0,  0,  1,    \
 564   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 565       1,  1,  1,  1,  1,  1,  1,  1,    \
 566   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 567       1,  1,  1,  1,  0,  1,  0,  1,    \
 568   /* ARG_POINTER:32 */                  \
 569       1,                                \
 570   /* FRAME_POINTER:33 */                \
 571       1                                 \
 572 }
 573
 574 /* In nds32 target, we have three levels of registers:
 575      LOW_COST_REGS    : $r0 ~ $r7
 576      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 577      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 578 #define REG_ALLOC_ORDER           \
 579 {                                 \
 580    0,  1,  2,  3,  4,  5,  6,  7, \
 581    8,  9, 10, 11, 16, 17, 18, 19, \
 582   12, 13, 14, 15, 20, 21, 22, 23, \
 583   24, 25, 26, 27, 28, 29, 30, 31, \
 584   32,                             \
 585   33                              \
 586 }
 587
 588 /* Tell IRA to use the order we define rather than messing it up with its
 589    own cost calculations.  */
 590 #define HONOR_REG_ALLOC_ORDER optimize_size
 591
 592 /* The number of consecutive hard regs needed starting at
 593    reg "regno" for holding a value of mode "mode".  */
 594 #define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
 595
 596 /* Value is 1 if hard register "regno" can hold a value
 597    of machine-mode "mode".  */
 598 #define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
 599
 600 /* A C expression that is nonzero if a value of mode1
 601    is accessible in mode2 without copying.
 602    Define this macro to return nonzero in as many cases as possible
 603    since doing so will allow GCC to perform better register allocation.
 604    We can use general registers to tie QI/HI/SI modes together.  */
 605 #define MODES_TIEABLE_P(mode1, mode2)          \
 606   (GET_MODE_CLASS (mode1) == MODE_INT          \
 607    && GET_MODE_CLASS (mode2) == MODE_INT       \
 608    && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD  \
 609    && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
 610
 611 \f
 612 /* Register Classes.  */
 613
 614 /* In nds32 target, we have three levels of registers:
 615      Low cost regsiters    : $r0 ~ $r7
 616      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 617      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 618
 619    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 620    so that it provides more chance to use low cost registers.  */
 621 enum reg_class
 622 {
 623   NO_REGS,
 624   R15_TA_REG,
 625   STACK_REG,
 626   LOW_REGS,
 627   MIDDLE_REGS,
 628   HIGH_REGS,
 629   GENERAL_REGS,
 630   FRAME_REGS,
 631   ALL_REGS,
 632   LIM_REG_CLASSES
 633 };
 634
 635 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 636
 637 #define REG_CLASS_NAMES \
 638 {                       \
 639   "NO_REGS",            \
 640   "R15_TA_REG",         \
 641   "STACK_REG",          \
 642   "LOW_REGS",           \
 643   "MIDDLE_REGS",        \
 644   "HIGH_REGS",          \
 645   "GENERAL_REGS",       \
 646   "FRAME_REGS",         \
 647   "ALL_REGS"            \
 648 }
 649
 650 #define REG_CLASS_CONTENTS \
 651 {                                                            \
 652   {0x00000000, 0x00000000}, /* NO_REGS     :              */ \
 653   {0x00008000, 0x00000000}, /* R15_TA_REG  : 15           */ \
 654   {0x80000000, 0x00000000}, /* STACK_REG   : 31           */ \
 655   {0x000000ff, 0x00000000}, /* LOW_REGS    : 0-7          */ \
 656   {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19  */ \
 657   {0xfff07000, 0x00000000}, /* HIGH_REGS   : 12-14, 20-31 */ \
 658   {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31         */ \
 659   {0x00000000, 0x00000003}, /* FRAME_REGS  : 32, 33       */ \
 660   {0xffffffff, 0x00000003}  /* ALL_REGS    : 0-31, 32, 33 */ \
 661 }
 662
 663 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 664
 665 #define BASE_REG_CLASS GENERAL_REGS
 666 #define INDEX_REG_CLASS GENERAL_REGS
 667
 668 /* Return nonzero if it is suitable for use as a
 669    base register in operand addresses.
 670    So far, we return nonzero only if "num" is a hard reg
 671    of the suitable class or a pseudo register which is
 672    allocated to a suitable hard reg.  */
 673 #define REGNO_OK_FOR_BASE_P(num) \
 674   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 675
 676 /* Return nonzero if it is suitable for use as a
 677    index register in operand addresses.
 678    So far, we return nonzero only if "num" is a hard reg
 679    of the suitable class or a pseudo register which is
 680    allocated to a suitable hard reg.
 681    The difference between an index register and a base register is that
 682    the index register may be scaled.  */
 683 #define REGNO_OK_FOR_INDEX_P(num) \
 684   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 685
 686 \f
 687 /* Obsolete Macros for Defining Constraints.  */
 688
 689 \f
 690 /* Stack Layout and Calling Conventions.  */
 691
 692 #define STACK_GROWS_DOWNWARD
 693
 694 #define FRAME_GROWS_DOWNWARD 1
 695
 696 #define STARTING_FRAME_OFFSET 0
 697
 698 #define STACK_POINTER_OFFSET 0
 699
 700 #define FIRST_PARM_OFFSET(fundecl) \
 701   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 702
 703 #define RETURN_ADDR_RTX(count, frameaddr) \
 704   nds32_return_addr_rtx (count, frameaddr)
 705
 706 /* A C expression whose value is RTL representing the location
 707    of the incoming return address at the beginning of any function
 708    before the prologue.
 709    If this RTL is REG, you should also define
 710    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 711 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 712 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 713
 714 #define STACK_POINTER_REGNUM SP_REGNUM
 715
 716 #define FRAME_POINTER_REGNUM 33
 717
 718 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 719
 720 #define ARG_POINTER_REGNUM 32
 721
 722 #define STATIC_CHAIN_REGNUM 16
 723
 724 #define ELIMINABLE_REGS                                \
 725 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 726   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 727   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 728   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 729
 730 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 731   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 732
 733 #define ACCUMULATE_OUTGOING_ARGS 1
 734
 735 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 736
 737 #define CUMULATIVE_ARGS nds32_cumulative_args
 738
 739 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 740   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 741
 742 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 743    We better cast REGNO into signed integer so that we can avoid
 744    'comparison of unsigned expression >= 0 is always true' warning.  */
 745 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 746   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 747    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 748
 749 #define DEFAULT_PCC_STRUCT_RETURN 0
 750
 751 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 752    from a function, the stack pointer does not matter.
 753    The value is tested only in functions that have frame pointers.
 754    In nds32 target, the function epilogue recovers the
 755    stack pointer from the frame.  */
 756 #define EXIT_IGNORE_STACK 1
 757
 758 #define FUNCTION_PROFILER(file, labelno) \
 759   fprintf (file, "/* profiler %d */", (labelno))
 760
 761 \f
 762 /* Implementing the Varargs Macros.  */
 763
 764 \f
 765 /* Trampolines for Nested Functions.  */
 766
 767 /* Giving A-function and B-function,
 768    if B-function wants to call A-function's nested function,
 769    we need to fill trampoline code into A-function's stack
 770    so that B-function can execute the code in stack to indirectly
 771    jump to (like 'trampoline' action) desired nested function.
 772
 773    The trampoline code for nds32 target must contains following parts:
 774
 775      1. instructions (4 * 4 = 16 bytes):
 776           get $pc first
 777           load chain_value to static chain register via $pc
 778           load nested function address to $r15 via $pc
 779           jump to desired nested function via $r15
 780      2. data (4 * 2 = 8 bytes):
 781           chain_value
 782           nested function address
 783
 784    Please check nds32.c implementation for more information.  */
 785 #define TRAMPOLINE_SIZE 24
 786
 787 /* Because all instructions/data in trampoline template are 4-byte size,
 788    we set trampoline alignment 8*4=32 bits.  */
 789 #define TRAMPOLINE_ALIGNMENT 32
 790
 791 \f
 792 /* Implicit Calls to Library Routines.  */
 793
 794 \f
 795 /* Addressing Modes.  */
 796
 797 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 798 #define HAVE_POST_INCREMENT 1
 799 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 800 #define HAVE_POST_DECREMENT 1
 801
 802 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 803 #define HAVE_POST_MODIFY_DISP 1
 804 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 805 #define HAVE_POST_MODIFY_REG  1
 806
 807 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 808
 809 #define MAX_REGS_PER_ADDRESS 2
 810
 811 \f
 812 /* Anchored Addresses.  */
 813
 814 \f
 815 /* Condition Code Status.  */
 816
 817 \f
 818 /* Describing Relative Costs of Operations.  */
 819
 820 /* A C expression for the cost of a branch instruction.
 821    A value of 1 is the default;
 822    other values are interpreted relative to that.  */
 823 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
 824
 825 #define SLOW_BYTE_ACCESS 1
 826
 827 #define NO_FUNCTION_CSE
 828
 829 \f
 830 /* Adjusting the Instruction Scheduler.  */
 831
 832 \f
 833 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 834
 835 #define TEXT_SECTION_ASM_OP     "\t.text"
 836 #define DATA_SECTION_ASM_OP     "\t.data"
 837
 838 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 839    So we use '.section .bss' alternatively.  */
 840 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 841
 842 /* Define this macro to be an expression with a nonzero value if jump tables
 843    (for tablejump insns) should be output in the text section,
 844    along with the assembler instructions.
 845    Otherwise, the readonly data section is used.  */
 846 #define JUMP_TABLES_IN_TEXT_SECTION 1
 847
 848 \f
 849 /* Position Independent Code.  */
 850
 851 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 852
 853 \f
 854 /* Defining the Output Assembler Language.  */
 855
 856 #define ASM_COMMENT_START "!"
 857
 858 #define ASM_APP_ON "! #APP"
 859
 860 #define ASM_APP_OFF "! #NO_APP\n"
 861
 862 #define ASM_OUTPUT_LABELREF(stream, name) \
 863   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 864
 865 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 866   assemble_name (stream, XSTR (sym, 0))
 867
 868 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 869   assemble_name (stream, buf)
 870
 871 #define LOCAL_LABEL_PREFIX "."
 872
 873 #define REGISTER_NAMES                                            \
 874 {                                                                 \
 875   "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 876   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 877   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 878   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 879   "$AP",                                                          \
 880   "$SFP"                                                          \
 881 }
 882
 883 /* Output normal jump table entry.  */
 884 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 885   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 886
 887 /* Output pc relative jump table entry.  */
 888 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 889   do                                                                    \
 890     {                                                                   \
 891       switch (GET_MODE (body))                                          \
 892         {                                                               \
 893         case QImode:                                                    \
 894           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 895           break;                                                        \
 896         case HImode:                                                    \
 897           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 898           break;                                                        \
 899         case SImode:                                                    \
 900           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 901           break;                                                        \
 902         default:                                                        \
 903           gcc_unreachable();                                            \
 904         }                                                               \
 905     } while (0)
 906
 907 /* We have to undef it first because elfos.h formerly define it
 908    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 909 #undef  ASM_OUTPUT_CASE_LABEL
 910 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 911   do                                                               \
 912     {                                                              \
 913       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 914       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 915     } while (0)
 916
 917 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 918   do                                                   \
 919     {                                                  \
 920       /* Because our jump table is in text section,    \
 921          we need to make sure 2-byte alignment after   \
 922          the jump table for instructions fetch.  */    \
 923       if (GET_MODE (PATTERN (table)) == QImode)        \
 924         ASM_OUTPUT_ALIGN (stream, 1);                  \
 925       asm_fprintf (stream, "\t! Jump Table End\n");    \
 926     }  while (0)
 927
 928 /* This macro is not documented yet.
 929    But we do need it to make jump table vector aligned.  */
 930 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 931
 932 #define DWARF2_UNWIND_INFO 1
 933
 934 #define JUMP_ALIGN(x) \
 935   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 936
 937 #define LOOP_ALIGN(x) \
 938   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
 939
 940 #define LABEL_ALIGN(x) \
 941   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
 942
 943 #define ASM_OUTPUT_ALIGN(stream, power) \
 944   fprintf (stream, "\t.align\t%d\n", power)
 945
 946 \f
 947 /* Controlling Debugging Information Format.  */
 948
 949 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 950
 951 #define DWARF2_DEBUGGING_INFO 1
 952
 953 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 954
 955 \f
 956 /* Cross Compilation and Floating Point.  */
 957
 958 \f
 959 /* Mode Switching Instructions.  */
 960
 961 \f
 962 /* Defining target-specific uses of __attribute__.  */
 963
 964 \f
 965 /* Emulating TLS.  */
 966
 967 \f
 968 /* Defining coprocessor specifics for MIPS targets.  */
 969
 970 \f
 971 /* Parameters for Precompiled Header Validity Checking.  */
 972
 973 \f
 974 /* C++ ABI parameters.  */
 975
 976 \f
 977 /* Adding support for named address spaces.  */
 978
 979 \f
 980 /* Miscellaneous Parameters.  */
 981
 982 /* This is the machine mode that elements of a jump-table should have.  */
 983 #define CASE_VECTOR_MODE Pmode
 984
 985 /* Return the preferred mode for and addr_diff_vec when the mininum
 986    and maximum offset are known.  */
 987 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
 988    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
 989    : (max_offset >= 100) ? HImode                               \
 990    : QImode)
 991
 992 /* Generate pc relative jump table when -fpic or -Os.  */
 993 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
 994
 995 /* Define this macro if operations between registers with integral mode
 996    smaller than a word are always performed on the entire register.  */
 997 #define WORD_REGISTER_OPERATIONS
 998
 999 /* A C expression indicating when insns that read memory in mem_mode,
1000    an integral mode narrower than a word, set the bits outside of mem_mode
1001    to be either the sign-extension or the zero-extension of the data read.  */
1002 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1003
1004 /* The maximum number of bytes that a single instruction can move quickly
1005    between memory and registers or between two memory locations.  */
1006 #define MOVE_MAX 4
1007
1008 /* A C expression that is nonzero if on this machine the number of bits
1009    actually used for the count of a shift operation is equal to the number
1010    of bits needed to represent the size of the object being shifted.  */
1011 #define SHIFT_COUNT_TRUNCATED 1
1012
1013 /* A C expression which is nonzero if on this machine it is safe to "convert"
1014    an integer of 'inprec' bits to one of 'outprec' bits by merely operating
1015    on it as if it had only 'outprec' bits.  */
1016 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
1017
1018 /* A C expression describing the value returned by a comparison operator with
1019    an integral mode and stored by a store-flag instruction ('cstoremode4')
1020    when the condition is true.  */
1021 #define STORE_FLAG_VALUE 1
1022
1023 /* An alias for the machine mode for pointers.  */
1024 #define Pmode SImode
1025
1026 /* An alias for the machine mode used for memory references to functions
1027    being called, in call RTL expressions.  */
1028 #define FUNCTION_MODE SImode
1029
1030 /* ------------------------------------------------------------------------ */