| blob | 177c4c5c919101d6f8a67c37f557e0d6edb9b811 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
59 /* Not really meaningful values, but at least something. */
60 #ifndef SIMULTANEOUS_PREFETCHES
61 #define SIMULTANEOUS_PREFETCHES 3
62 #endif
63 #ifndef PREFETCH_BLOCK
64 #define PREFETCH_BLOCK 32
65 #endif
66 #ifndef HAVE_prefetch
67 #define HAVE_prefetch 0
68 #define CODE_FOR_prefetch 0
69 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
70 #endif
72 /* Give up the prefetch optimizations once we exceed a given threshhold.
73 It is unlikely that we would be able to optimize something in a loop
74 with so many detected prefetches. */
75 #define MAX_PREFETCHES 100
76 /* The number of prefetch blocks that are beneficial to fetch at once before
77 a loop with a known (and low) iteration count. */
78 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
79 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
80 since it is likely that the data are already in the cache. */
81 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
83 /* Parameterize some prefetch heuristics so they can be turned on and off
84 easily for performance testing on new architecures. These can be
85 defined in target-dependent files. */
87 /* Prefetch is worthwhile only when loads/stores are dense. */
88 #ifndef PREFETCH_ONLY_DENSE_MEM
89 #define PREFETCH_ONLY_DENSE_MEM 1
90 #endif
92 /* Define what we mean by "dense" loads and stores; This value divided by 256
93 is the minimum percentage of memory references that worth prefetching. */
94 #ifndef PREFETCH_DENSE_MEM
95 #define PREFETCH_DENSE_MEM 220
96 #endif
98 /* Do not prefetch for a loop whose iteration count is known to be low. */
99 #ifndef PREFETCH_NO_LOW_LOOPCNT
100 #define PREFETCH_NO_LOW_LOOPCNT 1
101 #endif
103 /* Define what we mean by a "low" iteration count. */
104 #ifndef PREFETCH_LOW_LOOPCNT
105 #define PREFETCH_LOW_LOOPCNT 32
106 #endif
108 /* Do not prefetch for a loop that contains a function call; such a loop is
109 probably not an internal loop. */
110 #ifndef PREFETCH_NO_CALL
111 #define PREFETCH_NO_CALL 1
112 #endif
114 /* Do not prefetch accesses with an extreme stride. */
115 #ifndef PREFETCH_NO_EXTREME_STRIDE
116 #define PREFETCH_NO_EXTREME_STRIDE 1
117 #endif
119 /* Define what we mean by an "extreme" stride. */
120 #ifndef PREFETCH_EXTREME_STRIDE
121 #define PREFETCH_EXTREME_STRIDE 4096
122 #endif
124 /* Define a limit to how far apart indices can be and still be merged
125 into a single prefetch. */
126 #ifndef PREFETCH_EXTREME_DIFFERENCE
127 #define PREFETCH_EXTREME_DIFFERENCE 4096
128 #endif
130 /* Issue prefetch instructions before the loop to fetch data to be used
131 in the first few loop iterations. */
132 #ifndef PREFETCH_BEFORE_LOOP
133 #define PREFETCH_BEFORE_LOOP 1
134 #endif
136 /* Do not handle reversed order prefetches (negative stride). */
137 #ifndef PREFETCH_NO_REVERSE_ORDER
138 #define PREFETCH_NO_REVERSE_ORDER 1
139 #endif
141 /* Prefetch even if the GIV is in conditional code. */
142 #ifndef PREFETCH_CONDITIONAL
143 #define PREFETCH_CONDITIONAL 1
144 #endif
146 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
147 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
149 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
150 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
151 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
153 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
154 ((REGNO) < FIRST_PSEUDO_REGISTER \
155 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
158 /* Vector mapping INSN_UIDs to luids.
159 The luids are like uids but increase monotonically always.
160 We use them to see whether a jump comes from outside a given loop. */
164 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
165 number the insn is contained in. */
169 /* 1 + largest uid of any insn. */
173 /* 1 + luid of last insn. */
177 /* Number of loops detected in current function. Used as index to the
178 next few tables. */
182 /* Bound on pseudo register number before loop optimization.
183 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
186 /* The value to pass to the next call of reg_scan_update. */
188 \f
189 /* During the analysis of a loop, a chain of `struct movable's
190 is made to record all the movable insns found.
191 Then the entire chain can be scanned to decide which to move. */
193 struct movable
194 {
199 of any registers used within the LIBCALL. */
201 that must be moved with this one. */
204 may be adjusted when matching movables
205 that load the same value are found. */
207 including other movables that force this
208 or match this one. */
212 /* If PARTIAL is 1, GLOBAL means something different:
213 that the reg is live outside the range from where it is set
214 to the following label. */
218 In particular, moving it does not make it
219 invariant. */
221 load SRC, rather than copying INSN. */
223 first insn of a consecutive sets group. */
226 that we should avoid changing when clearing
227 the rest of the reg. */
231 };
236 /* Forward declarations. */
251 #if 0
253 #endif
283 rtx *));
366 {
367 rtx r1;
368 rtx r2;
372 {
373 rtx match;
374 rtx replacement;
375 rtx insn;
378 /* Nonzero iff INSN is between START and END, inclusive. */
379 #define INSN_IN_RANGE_P(INSN, START, END) \
380 (INSN_UID (INSN) < max_uid_for_loop \
381 && INSN_LUID (INSN) >= INSN_LUID (START) \
382 && INSN_LUID (INSN) <= INSN_LUID (END))
384 /* Indirect_jump_in_function is computed once per function. */
392 rtx));
393 \f
394 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
395 copy the value of the strength reduced giv to its original register. */
398 /* Cost of using a register, to normalize the benefits of a giv. */
401 void
403 {
409 }
410 \f
411 /* Compute the mapping from uids to luids.
412 LUIDs are numbers assigned to insns, like uids,
413 except that luids increase monotonically through the code.
414 Start at insn START and stop just before END. Assign LUIDs
415 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
416 static int
420 {
422 rtx insn;
425 {
428 /* Don't assign luids to line-number NOTEs, so that the distance in
429 luids between two insns is not affected by -g. */
433 else
434 /* Give a line number note the same luid as preceding insn. */
436 }
438 }
439 \f
440 /* Entry point of this file. Perform loop optimization
441 on the current function. F is the first insn of the function
442 and DUMPFILE is a stream for output of a trace of actions taken
443 (or 0 if none should be output). */
445 void
447 /* f is the first instruction of a chain of insns for one function */
448 rtx f;
451 {
452 rtx insn;
467 /* Count the number of loops. */
471 {
474 max_loop_num++;
475 }
477 /* Don't waste time if no loops. */
483 /* Get size to use for tables indexed by uids.
484 Leave some space for labels allocated by find_and_verify_loops. */
491 /* Allocate storage for array of loops. */
495 /* Find and process each loop.
496 First, find them, and record them in order of their beginnings. */
499 /* Allocate and initialize auxiliary loop information. */
504 /* Now find all register lifetimes. This must be done after
505 find_and_verify_loops, because it might reorder the insns in the
506 function. */
509 /* This must occur after reg_scan so that registers created by gcse
510 will have entries in the register tables.
512 We could have added a call to reg_scan after gcse_main in toplev.c,
513 but moving this call to init_alias_analysis is more efficient. */
516 /* See if we went too far. Note that get_max_uid already returns
517 one more that the maximum uid of all insn. */
520 /* Now reset it to the actual size we need. See above. */
523 /* find_and_verify_loops has already called compute_luids, but it
524 might have rearranged code afterwards, so we need to recompute
525 the luids now. */
528 /* Don't leave gaps in uid_luid for insns that have been
529 deleted. It is possible that the first or last insn
530 using some register has been deleted by cross-jumping.
531 Make sure that uid_luid for that former insn's uid
532 points to the general area where that insn used to be. */
534 {
538 }
543 /* Determine if the function has indirect jump. On some systems
544 this prevents low overhead loop instructions from being used. */
547 /* Now scan the loops, last ones first, since this means inner ones are done
548 before outer ones. */
550 {
555 }
559 /* Clean up. */
564 }
565 \f
566 /* Returns the next insn, in execution order, after INSN. START and
567 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
568 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
569 insn-stream; it is used with loops that are entered near the
570 bottom. */
572 static rtx
575 rtx insn;
576 {
580 {
582 /* Go to the top of the loop, and continue there. */
584 else
585 /* We're done. */
587 }
590 /* We're done. */
594 }
596 /* Optimize one loop described by LOOP. */
598 /* ??? Could also move memory writes out of loops if the destination address
599 is invariant, the source is invariant, the memory write is not volatile,
600 and if we can prove that no read inside the loop can read this address
601 before the write occurs. If there is a read of this address after the
602 write, then we can also mark the memory read as invariant. */
604 static void
608 {
614 rtx p;
615 /* 1 if we are scanning insns that could be executed zero times. */
617 /* 1 if we are scanning insns that might never be executed
618 due to a subroutine call which might exit before they are reached. */
620 /* Jump insn that enters the loop, or 0 if control drops in. */
622 /* Number of insns in the loop. */
626 /* The SET from an insn, if it is the only SET in the insn. */
628 /* Chain describing insns movable in current loop. */
630 /* Ratio of extra register life span we can justify
631 for saving an instruction. More if loop doesn't call subroutines
632 since in that case saving an insn makes more difference
633 and more registers are available. */
635 /* Nonzero if we are scanning instructions in a sub-loop. */
643 /* Determine whether this loop starts with a jump down to a test at
644 the end. This will occur for a small number of loops with a test
645 that is too complex to duplicate in front of the loop.
647 We search for the first insn or label in the loop, skipping NOTEs.
648 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
649 (because we might have a loop executed only once that contains a
650 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
651 (in case we have a degenerate loop).
653 Note that if we mistakenly think that a loop is entered at the top
654 when, in fact, it is entered at the exit test, the only effect will be
655 slightly poorer optimization. Making the opposite error can generate
656 incorrect code. Since very few loops now start with a jump to the
657 exit test, the code here to detect that case is very conservative. */
660 p != loop_end
666 ;
670 /* If loop end is the end of the current function, then emit a
671 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
672 note insn. This is the position we use when sinking insns out of
673 the loop. */
676 else
679 /* Set up variables describing this loop. */
683 /* If loop has a jump before the first label,
684 the true entry is the target of that jump.
685 Start scan from there.
686 But record in LOOP->TOP the place where the end-test jumps
687 back to so we can scan that after the end of the loop. */
689 {
692 /* Loop entry must be unconditional jump (and not a RETURN) */
695 /* Check to see whether the jump actually
696 jumps out of the loop (meaning it's no loop).
697 This case can happen for things like
698 do {..} while (0). If this label was generated previously
699 by loop, we can't tell anything about it and have to reject
700 the loop. */
702 {
705 }
706 }
708 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
709 as required by loop_reg_used_before_p. So skip such loops. (This
710 test may never be true, but it's best to play it safe.)
712 Also, skip loops where we do not start scanning at a label. This
713 test also rejects loops starting with a JUMP_INSN that failed the
714 test above. */
718 {
723 }
725 /* Allocate extra space for REGs that might be created by load_mems.
726 We allocate a little extra slop as well, in the hopes that we
727 won't have to reallocate the regs array. */
732 {
738 }
740 /* Scan through the loop finding insns that are safe to move.
741 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
742 this reg will be considered invariant for subsequent insns.
743 We consider whether subsequent insns use the reg
744 in deciding whether it is worth actually moving.
746 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
747 and therefore it is possible that the insns we are scanning
748 would never be executed. At such times, we must make sure
749 that it is safe to execute the insn once instead of zero times.
750 When MAYBE_NEVER is 0, all insns will be executed at least once
751 so that is not a problem. */
756 {
760 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
762 #endif
764 {
771 /* Figure out what to use as a source of this insn. If a REG_EQUIV
772 note is given or if a REG_EQUAL note with a constant operand is
773 specified, use it as the source and mark that we should move
774 this insn by calling emit_move_insn rather that duplicating the
775 insn.
777 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
778 is present. */
782 else
783 {
788 {
790 /* A libcall block can use regs that don't appear in
791 the equivalent expression. To move the libcall,
792 we must move those regs too. */
794 }
795 }
797 /* For parallels, add any possible uses to the depencies, as we can't move
798 the insn without resolving them first. */
800 {
802 {
806 }
807 }
809 /* Don't try to optimize a register that was made
810 by loop-optimization for an inner loop.
811 We don't know its life-span, so we can't compute the benefit. */
813 ;
815 than the one where it is set (meaning that
816 something after this point in the loop might
817 depend on its value before the set). */
819 /* And the set is not guaranteed to be executed once
820 the loop starts, or the value before the set is
821 needed before the set occurs...
823 ??? Note we have quadratic behaviour here, mitigated
824 by the fact that the previous test will often fail for
825 large loops. Rather than re-scanning the entire loop
826 each time for register usage, we should build tables
827 of the register usage and use them here instead. */
828 && (maybe_never
830 /* It is unsafe to move the set.
832 This code used to consider it OK to move a set of a variable
833 which was not created by the user and not used in an exit test.
834 That behavior is incorrect and was removed. */
835 ;
840 || (tem1
841 = consec_sets_invariant_p
844 p)))
845 /* If the insn can cause a trap (such as divide by zero),
846 can't move it unless it's guaranteed to be executed
847 once loop is entered. Even a function call might
848 prevent the trap insn from being reached
849 (since it might exit!) */
852 {
856 /* A potential lossage is where we have a case where two insns
857 can be combined as long as they are both in the loop, but
858 we move one of them outside the loop. For large loops,
859 this can lose. The most common case of this is the address
860 of a function being called.
862 Therefore, if this register is marked as being used exactly
863 once if we are in a loop with calls (a "large loop"), see if
864 we can replace the usage of this register with the source
865 of this SET. If we can, delete this insn.
867 Don't do this if P has a REG_RETVAL note or if we have
868 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
880 && (! SMALL_REGISTER_CLASSES
883 /* This test is not redundant; SET_SRC (set) might be
884 a call-clobbered register and the life of REGNO
885 might span a call. */
891 {
892 /* Replace any usage in a REG_EQUAL note. Must copy the
893 new source, so that we don't get rtx sharing between the
894 SET_SOURCE and REG_NOTES of insn p. */
903 }
921 /* Set M->cond if either loop_invariant_p
922 or consec_sets_invariant_p returned 2
923 (only conditionally invariant). */
933 /* Add M to the end of the chain MOVABLES. */
937 {
938 /* It is possible for the first instruction to have a
939 REG_EQUAL note but a non-invariant SET_SRC, so we must
940 remember the status of the first instruction in case
941 the last instruction doesn't have a REG_EQUAL note. */
944 /* Skip this insn, not checking REG_LIBCALL notes. */
946 /* Skip the consecutive insns, if there are any. */
948 /* Back up to the last insn of the consecutive group. */
951 /* We must now reset m->move_insn, m->is_equiv, and possibly
952 m->set_src to correspond to the effects of all the
953 insns. */
957 else
958 {
962 else
965 }
967 }
968 }
969 /* If this register is always set within a STRICT_LOW_PART
970 or set to zero, then its high bytes are constant.
971 So clear them outside the loop and within the loop
972 just load the low bytes.
973 We must check that the machine has an instruction to do so.
974 Also, if the value loaded into the register
975 depends on the same register, this cannot be done. */
985 {
988 {
1002 /* If the insn may not be executed on some cycles,
1003 we can't clear the whole reg; clear just high part.
1004 Not even if the reg is used only within this loop.
1005 Consider this:
1006 while (1)
1007 while (s != t) {
1008 if (foo ()) x = *s;
1009 use (x);
1010 }
1011 Clearing x before the inner loop could clobber a value
1012 being saved from the last time around the outer loop.
1013 However, if the reg is not used outside this loop
1014 and all uses of the register are in the same
1015 basic block as the store, there is no problem.
1017 If this insn was made by loop, we don't know its
1018 INSN_LUID and hence must make a conservative
1019 assumption. */
1022 || (labels_in_range_p
1026 else
1035 /* Add M to the end of the chain MOVABLES. */
1037 }
1038 }
1039 }
1040 /* Past a call insn, we get to insns which might not be executed
1041 because the call might exit. This matters for insns that trap.
1042 Constant and pure call insns always return, so they don't count. */
1045 /* Past a label or a jump, we get to insns for which we
1046 can't count on whether or how many times they will be
1047 executed during each iteration. Therefore, we can
1048 only move out sets of trivial variables
1049 (those not used after the loop). */
1050 /* Similar code appears twice in strength_reduce. */
1052 /* If we enter the loop in the middle, and scan around to the
1053 beginning, don't set maybe_never for that. This must be an
1054 unconditional jump, otherwise the code at the top of the
1055 loop might never be executed. Unconditional jumps are
1056 followed by a barrier then the loop_end. */
1062 {
1063 /* At the virtual top of a converted loop, insns are again known to
1064 be executed: logically, the loop begins here even though the exit
1065 code has been duplicated. */
1069 loop_depth++;
1071 loop_depth--;
1072 }
1073 }
1075 /* If one movable subsumes another, ignore that other. */
1079 /* For each movable insn, see if the reg that it loads
1080 leads when it dies right into another conditionally movable insn.
1081 If so, record that the second insn "forces" the first one,
1082 since the second can be moved only if the first is. */
1086 /* See if there are multiple movable insns that load the same value.
1087 If there are, make all but the first point at the first one
1088 through the `match' field, and add the priorities of them
1089 all together as the priority of the first. */
1093 /* Now consider each movable insn to decide whether it is worth moving.
1094 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1096 Generally this increases code size, so do not move moveables when
1097 optimizing for code size. */
1100 {
1103 /* Recalculate regs->array if move_movables has created new
1104 registers. */
1106 {
1112 ;
1117 }
1118 }
1120 /* Now candidates that still are negative are those not moved.
1121 Change regs->array[I].set_in_loop to indicate that those are not actually
1122 invariant. */
1127 /* Now that we've moved some things out of the loop, we might be able to
1128 hoist even more memory references. */
1131 /* Recalculate regs->array if load_mems has created new registers. */
1139 ;
1146 {
1148 /* Ensure our label doesn't go away. */
1159 }
1162 /* The movable information is required for strength reduction. */
1168 }
1169 \f
1170 /* Add elements to *OUTPUT to record all the pseudo-regs
1171 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1173 void
1177 {
1185 {
1203 }
1207 {
1211 {
1220 }
1221 }
1222 }
1223 \f
1224 /* Check what regs are referred to in the libcall block ending with INSN,
1225 aside from those mentioned in the equivalent value.
1226 If there are none, return 0.
1227 If there are one or more, return an EXPR_LIST containing all of them. */
1229 rtx
1232 {
1237 /* First, find all the regs used in the libcall block
1238 that are not mentioned as inputs to the result. */
1241 {
1246 }
1249 }
1250 \f
1251 /* Return 1 if all uses of REG
1252 are between INSN and the end of the basic block. */
1254 static int
1257 {
1259 rtx p;
1264 /* Search this basic block for the already recorded last use of the reg. */
1266 {
1268 {
1274 /* Ordinary insn: if this is the last use, we win. */
1280 /* Jump insn: if this is the last use, we win. */
1283 /* Otherwise, it's the end of the basic block, so we lose. */
1288 /* It's the end of the basic block, so we lose. */
1293 }
1294 }
1296 /* The "last use" that was recorded can't be found after the first
1297 use. This can happen when the last use was deleted while
1298 processing an inner loop, this inner loop was then completely
1299 unrolled, and the outer loop is always exited after the inner loop,
1300 so that everything after the first use becomes a single basic block. */
1302 }
1303 \f
1304 /* Compute the benefit of eliminating the insns in the block whose
1305 last insn is LAST. This may be a group of insns used to compute a
1306 value directly or can contain a library call. */
1308 static int
1310 rtx last;
1311 {
1312 rtx insn;
1317 {
1320 routine. */
1324 benefit++;
1325 }
1328 }
1329 \f
1330 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1332 static rtx
1334 rtx insn;
1336 {
1338 {
1339 rtx temp;
1341 /* If first insn of libcall sequence, skip to end. */
1342 /* Do this at start of loop, since INSN is guaranteed to
1343 be an insn here. */
1348 do
1351 }
1354 }
1356 /* Ignore any movable whose insn falls within a libcall
1357 which is part of another movable.
1358 We make use of the fact that the movable for the libcall value
1359 was made later and so appears later on the chain. */
1361 static void
1364 {
1368 {
1369 /* Is this a movable for the value of a libcall? */
1372 {
1373 rtx insn;
1374 /* Check for earlier movables inside that range,
1375 and mark them invalid. We cannot use LUIDs here because
1376 insns created by loop.c for prior loops don't have LUIDs.
1377 Rather than reject all such insns from movables, we just
1378 explicitly check each insn in the libcall (since invariant
1379 libcalls aren't that common). */
1384 }
1385 }
1386 }
1388 /* For each movable insn, see if the reg that it loads
1389 leads when it dies right into another conditionally movable insn.
1390 If so, record that the second insn "forces" the first one,
1391 since the second can be moved only if the first is. */
1393 static void
1396 {
1400 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1402 {
1405 /* ??? Could this be a bug? What if CSE caused the
1406 register of M1 to be used after this insn?
1407 Since CSE does not update regno_last_uid,
1408 this insn M->insn might not be where it dies.
1409 But very likely this doesn't matter; what matters is
1410 that M's reg is computed from M1's reg. */
1415 /* If m->consec, m->set_src isn't valid. */
1419 /* Increase the priority of the moving the first insn
1420 since it permits the second to be moved as well. */
1422 {
1426 }
1427 }
1428 }
1429 \f
1430 /* Find invariant expressions that are equal and can be combined into
1431 one register. */
1433 static void
1437 {
1442 /* Regs that are set more than once are not allowed to match
1443 or be matched. I'm no longer sure why not. */
1444 /* Only pseudo registers are allowed to match or be matched,
1445 since move_movables does not validate the change. */
1446 /* Perhaps testing m->consec_sets would be more appropriate here? */
1452 {
1459 /* We want later insns to match the first one. Don't make the first
1460 one match any later ones. So start this loop at m->next. */
1465 /* A reg used outside the loop mustn't be eliminated. */
1467 /* A reg used for zero-extending mustn't be eliminated. */
1470 ||
1471 (
1472 /* Can combine regs with different modes loaded from the
1473 same constant only if the modes are the same or
1474 if both are integer modes with M wider or the same
1475 width as M1. The check for integer is redundant, but
1476 safe, since the only case of differing destination
1477 modes with equal sources is when both sources are
1478 VOIDmode, i.e., CONST_INT. */
1484 /* See if the source of M1 says it matches M. */
1491 {
1497 }
1498 }
1500 /* Now combine the regs used for zero-extension.
1501 This can be done for those not marked `global'
1502 provided their lives don't overlap. */
1506 {
1509 /* Combine all the registers for extension from mode MODE.
1510 Don't combine any that are used outside this loop. */
1514 {
1521 {
1522 /* First one: don't check for overlap, just record it. */
1525 }
1527 /* Make sure they extend to the same mode.
1528 (Almost always true.) */
1532 /* We already have one: check for overlap with those
1533 already combined together. */
1540 /* No overlap: we can combine this with the others. */
1546 overlap:
1547 ;
1548 }
1549 }
1551 /* Clean up. */
1553 }
1555 /* Returns the number of movable instructions in LOOP that were not
1556 moved outside the loop. */
1558 static int
1561 {
1570 }
1572 \f
1573 /* Return 1 if regs X and Y will become the same if moved. */
1575 static int
1579 {
1596 }
1598 /* Return 1 if X and Y are identical-looking rtx's.
1599 This is the Lisp function EQUAL for rtx arguments.
1601 If two registers are matching movables or a movable register and an
1602 equivalent constant, consider them equal. */
1604 static int
1609 {
1623 /* If we have a register and a constant, they may sometimes be
1624 equal. */
1627 {
1632 }
1635 {
1640 }
1642 /* Otherwise, rtx's of different codes cannot be equal. */
1646 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1647 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1652 /* These three types of rtx's can be compared nonrecursively. */
1661 /* Compare the elements. If any pair of corresponding elements
1662 fail to match, return 0 for the whole things. */
1666 {
1668 {
1680 /* Two vectors must have the same length. */
1684 /* And the corresponding elements must match. */
1703 /* These are just backpointers, so they don't matter. */
1709 /* It is believed that rtx's at this level will never
1710 contain anything but integers and other rtx's,
1711 except for within LABEL_REFs and SYMBOL_REFs. */
1714 }
1715 }
1717 }
1718 \f
1719 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1720 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1721 references is incremented once for each added note. */
1723 static void
1725 rtx x;
1726 rtx insns;
1727 {
1731 rtx insn;
1734 {
1735 /* This code used to ignore labels that referred to dispatch tables to
1736 avoid flow generating (slighly) worse code.
1738 We no longer ignore such label references (see LABEL_REF handling in
1739 mark_jump_label for additional information). */
1742 {
1747 }
1748 }
1752 {
1758 }
1759 }
1760 \f
1761 /* Scan MOVABLES, and move the insns that deserve to be moved.
1762 If two matching movables are combined, replace one reg with the
1763 other throughout. */
1765 static void
1771 {
1776 rtx p;
1779 /* Map of pseudo-register replacements to handle combining
1780 when we move several insns that load the same value
1781 into different pseudo-registers. */
1786 {
1787 /* Describe this movable insn. */
1790 {
1811 }
1813 /* Ignore the insn if it's already done (it matched something else).
1814 Otherwise, see if it is now safe to move. */
1826 {
1828 rtx p;
1831 /* We have an insn that is safe to move.
1832 Compute its desirability. */
1843 /* An insn MUST be moved if we already moved something else
1844 which is safe only if this one is moved too: that is,
1845 if already_moved[REGNO] is nonzero. */
1847 /* An insn is desirable to move if the new lifetime of the
1848 register is no more than THRESHOLD times the old lifetime.
1849 If it's not desirable, it means the loop is so big
1850 that moving won't speed things up much,
1851 and it is liable to make register usage worse. */
1853 /* It is also desirable to move if it can be moved at no
1854 extra cost because something else was already moved. */
1857 || flag_move_all_movables
1862 {
1867 /* Now move the insns that set the reg. */
1870 {
1873 /* Find the end of this chain of matching regs.
1874 Thus, we load each reg in the chain from that one reg.
1875 And that reg is loaded with 0 directly,
1876 since it has ->match == 0. */
1882 /* Mark the moved, invariant reg as being allowed to
1883 share a hard reg with the other matching invariant. */
1887 regs_may_share
1890 regs_may_share));
1898 }
1899 /* If we are to re-generate the item being moved with a
1900 new move insn, first delete what we have and then emit
1901 the move insn before the loop. */
1903 {
1907 {
1908 /* If this is the first insn of a library call sequence,
1909 skip to the end. */
1914 /* If this is the last insn of a libcall sequence, then
1915 delete every insn in the sequence except the last.
1916 The last insn is handled in the normal manner. */
1919 {
1923 }
1928 /* simplify_giv_expr expects that it can walk the insns
1929 at m->insn forwards and see this old sequence we are
1930 tossing here. delete_insn does preserve the next
1931 pointers, but when we skip over a NOTE we must fix
1932 it up. Otherwise that code walks into the non-deleted
1933 insn stream. */
1936 }
1954 /* The more regs we move, the less we like moving them. */
1956 }
1957 else
1958 {
1960 {
1963 /* If first insn of libcall sequence, skip to end. */
1964 /* Do this at start of loop, since p is guaranteed to
1965 be an insn here. */
1970 /* If last insn of libcall sequence, move all
1971 insns except the last before the loop. The last
1972 insn is handled in the normal manner. */
1975 {
1983 {
1984 rtx body;
1985 rtx n;
1986 rtx next;
1993 /* Find the next insn after TEMP,
1994 not counting USE or NOTE insns. */
2002 /* If that is the call, this may be the insn
2003 that loads the function address.
2005 Extract the function address from the insn
2006 that loads it into a register.
2007 If this insn was cse'd, we get incorrect code.
2009 So emit a new move insn that copies the
2010 function address into the register that the
2011 call insn will use. flow.c will delete any
2012 redundant stores that we have created. */
2017 NULL_RTX)))
2018 {
2024 }
2025 /* We have the call insn.
2026 If it uses the register we suspect it might,
2027 load it with the correct address directly. */
2032 gen_move_insn
2036 {
2038 /* Because the USAGE information potentially
2039 contains objects other than hard registers
2040 we need to copy it. */
2044 }
2045 else
2054 }
2057 }
2059 {
2060 /* P sets REG to zero; but we should clear only
2061 the bits that are not covered by the mode
2062 m->savemode. */
2064 rtx sequence;
2065 rtx tem;
2068 tem = expand_simple_binop
2081 }
2083 {
2085 /* Because the USAGE information potentially
2086 contains objects other than hard registers
2087 we need to copy it. */
2091 }
2093 {
2094 rtx seq;
2095 /* The SET_SRC might not be invariant, so we must
2096 use the REG_EQUAL note. */
2108 }
2109 else
2113 {
2117 /* If there is a REG_EQUAL note present whose value
2118 is not loop invariant, then delete it, since it
2119 may cause problems with later optimization passes.
2120 It is possible for cse to create such notes
2121 like this as a result of record_jump_cond. */
2126 }
2135 /* If library call, now fix the REG_NOTES that contain
2136 insn pointers, namely REG_LIBCALL on FIRST
2137 and REG_RETVAL on I1. */
2139 {
2143 }
2149 /* simplify_giv_expr expects that it can walk the insns
2150 at m->insn forwards and see this old sequence we are
2151 tossing here. delete_insn does preserve the next
2152 pointers, but when we skip over a NOTE we must fix
2153 it up. Otherwise that code walks into the non-deleted
2154 insn stream. */
2157 }
2159 /* The more regs we move, the less we like moving them. */
2161 }
2163 /* Any other movable that loads the same register
2164 MUST be moved. */
2167 /* This reg has been moved out of one loop. */
2170 /* The reg set here is now invariant. */
2172 {
2176 }
2180 /* Change the length-of-life info for the register
2181 to say it lives at least the full length of this loop.
2182 This will help guide optimizations in outer loops. */
2185 /* This is the old insn before all the moved insns.
2186 We can't use the moved insn because it is out of range
2187 in uid_luid. Only the old insns have luids. */
2192 /* Combine with this moved insn any other matching movables. */
2197 {
2198 rtx temp;
2200 /* Schedule the reg loaded by M1
2201 for replacement so that shares the reg of M.
2202 If the modes differ (only possible in restricted
2203 circumstances, make a SUBREG.
2205 Note this assumes that the target dependent files
2206 treat REG and SUBREG equally, including within
2207 GO_IF_LEGITIMATE_ADDRESS and in all the
2208 predicates since we never verify that replacing the
2209 original register with a SUBREG results in a
2210 recognizable insn. */
2213 else
2218 /* Get rid of the matching insn
2219 and prevent further processing of it. */
2222 /* if library call, delete all insns. */
2224 NULL_RTX)))
2226 else
2229 /* Any other movable that loads the same register
2230 MUST be moved. */
2233 /* The reg merged here is now invariant,
2234 if the reg it matches is invariant. */
2236 {
2240 i++)
2242 }
2243 }
2244 }
2247 }
2253 }
2258 /* Go through all the instructions in the loop, making
2259 all the register substitutions scheduled in REG_MAP. */
2263 {
2267 }
2269 /* Clean up. */
2272 }
2275 static void
2279 {
2282 else
2285 }
2288 static void
2291 {
2296 {
2299 }
2300 }
2301 \f
2302 #if 0
2303 /* Scan X and replace the address of any MEM in it with ADDR.
2304 REG is the address that MEM should have before the replacement. */
2306 static void
2309 {
2318 {
2330 /* Short cut for very common case. */
2335 /* Short cut for very common case. */
2340 /* If this MEM uses a reg other than the one we expected,
2341 something is wrong. */
2349 }
2353 {
2357 {
2361 }
2362 }
2363 }
2364 #endif
2365 \f
2366 /* Return the number of memory refs to addresses that vary
2367 in the rtx X. */
2369 static int
2372 rtx x;
2373 {
2384 {
2401 }
2406 {
2410 {
2414 }
2415 }
2417 }
2418 \f
2419 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2420 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2421 `unknown_address_altered', `unknown_constant_address_altered', and
2422 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2423 list `store_mems' in LOOP. */
2425 static void
2428 {
2430 rtx insn;
2434 /* The label after END. Jumping here is just like falling off the
2435 end of the loop. We use next_nonnote_insn instead of next_label
2436 as a hedge against the (pathological) case where some actual insn
2437 might end up between the two. */
2460 {
2462 {
2465 }
2466 }
2470 {
2472 {
2475 {
2477 /* Count number of loops contained in this one. */
2479 }
2486 {
2489 }
2499 {
2503 {
2508 {
2511 }
2512 else
2513 {
2516 }
2518 do
2519 {
2521 {
2523 {
2524 /* Something tricky. */
2527 }
2530 {
2531 /* A jump outside the current loop. */
2534 }
2535 }
2539 }
2541 }
2542 else
2543 {
2544 /* A return, or something tricky. */
2546 }
2547 }
2548 /* FALLTHRU */
2569 }
2570 }
2572 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2574 anywhere. */
2576 /* We don't want loads for MEMs moved to a location before the
2577 one at which their stack memory becomes allocated. (Note
2578 that this is not a problem for malloc, etc., since those
2579 require actual function calls. */
2580 && ! current_function_calls_alloca
2581 /* There are ways to leave the loop other than falling off the
2582 end. */
2588 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2589 that loop_invariant_p and load_mems can use true_dependence
2590 to determine what is really clobbered. */
2592 {
2595 loop_info->store_mems
2597 }
2599 {
2603 loop_info->store_mems
2605 }
2606 }
2607 \f
2608 /* Invalidate all loops containing LABEL. */
2610 static void
2612 rtx label;
2613 {
2617 }
2619 /* Scan the function looking for loops. Record the start and end of each loop.
2620 Also mark as invalid loops any loops that contain a setjmp or are branched
2621 to from outside the loop. */
2623 static void
2625 rtx f;
2627 {
2628 rtx insn;
2629 rtx label;
2639 /* If there are jumps to undefined labels,
2640 treat them as jumps out of any/all loops.
2641 This also avoids writing past end of tables when there are no loops. */
2644 /* Find boundaries of loops, mark which loops are contained within
2645 loops, and invalidate loops that have setjmp. */
2650 {
2653 {
2657 num_loops++;
2681 }
2685 {
2686 /* In this case, we must invalidate our current loop and any
2687 enclosing loop. */
2689 {
2695 }
2696 }
2698 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2699 enclosing loop, but this doesn't matter. */
2701 }
2703 /* Any loop containing a label used in an initializer must be invalidated,
2704 because it can be jumped into from anywhere. */
2708 /* Any loop containing a label used for an exception handler must be
2709 invalidated, because it can be jumped into from anywhere. */
2712 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2713 loop that it is not contained within, that loop is marked invalid.
2714 If any INSN or CALL_INSN uses a label's address, then the loop containing
2715 that label is marked invalid, because it could be jumped into from
2716 anywhere.
2718 Also look for blocks of code ending in an unconditional branch that
2719 exits the loop. If such a block is surrounded by a conditional
2720 branch around the block, move the block elsewhere (see below) and
2721 invert the jump to point to the code block. This may eliminate a
2722 label in our loop and will simplify processing by both us and a
2723 possible second cse pass. */
2727 {
2731 {
2735 }
2742 /* See if this is an unconditional branch outside the loop. */
2750 {
2751 rtx p;
2757 /* Go backwards until we reach the start of the loop, a label,
2758 or a JUMP_INSN. */
2765 ;
2767 /* Check for the case where we have a jump to an inner nested
2768 loop, and do not perform the optimization in that case. */
2771 {
2774 {
2779 }
2780 }
2782 /* Make sure that the target of P is within the current loop. */
2788 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2789 we have a block of code to try to move.
2791 We look backward and then forward from the target of INSN
2792 to find a BARRIER at the same loop depth as the target.
2793 If we find such a BARRIER, we make a new label for the start
2794 of the block, invert the jump in P and point it to that label,
2795 and move the block of code to the spot we found. */
2800 /* Just ignore jumps to labels that were never emitted.
2801 These always indicate compilation errors. */
2805 /* If it's not safe to move the sequence, then we
2806 mustn't try. */
2809 {
2810 rtx target
2814 rtx tmp;
2816 /* Search for possible garbage past the conditional jumps
2817 and look for the last barrier. */
2825 /* Don't move things inside a tablejump. */
2838 /* Don't move things inside a tablejump. */
2849 {
2853 /* Ensure our label doesn't go away. */
2856 /* Verify that uid_loop is large enough and that
2857 we can invert P. */
2859 {
2862 /* If no suitable BARRIER was found, create a suitable
2863 one before TARGET. Since TARGET is a fall through
2864 path, we'll need to insert an jump around our block
2865 and add a BARRIER before TARGET.
2867 This creates an extra unconditional jump outside
2868 the loop. However, the benefits of removing rarely
2869 executed instructions from inside the loop usually
2870 outweighs the cost of the extra unconditional jump
2871 outside the loop. */
2873 {
2874 rtx temp;
2881 }
2883 /* Include the BARRIER after INSN and copy the
2884 block after LOC. */
2889 /* All those insns are now in TARGET_LOOP. */
2895 /* The label jumped to by INSN is no longer a loop
2896 exit. Unless INSN does not have a label (e.g.,
2897 it is a RETURN insn), search loop->exit_labels
2898 to find its label_ref, and remove it. Also turn
2899 off LABEL_OUTSIDE_LOOP_P bit. */
2901 {
2903 r;
2906 {
2910 else
2913 }
2919 /* If we didn't find it, then something is
2920 wrong. */
2923 }
2925 /* P is now a jump outside the loop, so it must be put
2926 in loop->exit_labels, and marked as such.
2927 The easiest way to do this is to just call
2928 mark_loop_jump again for P. */
2931 /* If INSN now jumps to the insn after it,
2932 delete INSN. */
2937 }
2939 /* Continue the loop after where the conditional
2940 branch used to jump, since the only branch insn
2941 in the block (if it still remains) is an inter-loop
2942 branch and hence needs no processing. */
2948 /* This loop will be continued with NEXT_INSN (insn). */
2950 }
2951 }
2952 }
2953 }
2954 }
2956 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2957 loops it is contained in, mark the target loop invalid.
2959 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2961 static void
2963 rtx x;
2965 {
2971 {
2983 /* There could be a label reference in here. */
2995 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3007 /* Link together all labels that branch outside the loop. This
3008 is used by final_[bg]iv_value and the loop unrolling code. Also
3009 mark this LABEL_REF so we know that this branch should predict
3010 false. */
3012 /* A check to make sure the label is not in an inner nested loop,
3013 since this does not count as a loop exit. */
3015 {
3020 }
3021 else
3025 {
3034 }
3036 /* If this is inside a loop, but not in the current loop or one enclosed
3037 by it, it invalidates at least one loop. */
3042 /* We must invalidate every nested loop containing the target of this
3043 label, except those that also contain the jump insn. */
3046 {
3047 /* Stop when we reach a loop that also contains the jump insn. */
3052 /* If we get here, we know we need to invalidate a loop. */
3059 }
3063 /* If this is not setting pc, ignore. */
3085 /* Strictly speaking this is not a jump into the loop, only a possible
3086 jump out of the loop. However, we have no way to link the destination
3087 of this jump onto the list of exit labels. To be safe we mark this
3088 loop and any containing loops as invalid. */
3090 {
3092 {
3098 }
3099 }
3101 }
3102 }
3103 \f
3104 /* Return nonzero if there is a label in the range from
3105 insn INSN to and including the insn whose luid is END
3106 INSN must have an assigned luid (i.e., it must not have
3107 been previously created by loop.c). */
3109 static int
3111 rtx insn;
3113 {
3115 {
3119 }
3122 }
3124 /* Record that a memory reference X is being set. */
3126 static void
3128 rtx x;
3129 rtx y ATTRIBUTE_UNUSED;
3131 {
3137 /* Count number of memory writes.
3138 This affects heuristics in strength_reduce. */
3141 /* BLKmode MEM means all memory is clobbered. */
3143 {
3146 else
3150 }
3154 }
3156 /* X is a value modified by an INSN that references a biv inside a loop
3157 exit test (ie, X is somehow related to the value of the biv). If X
3158 is a pseudo that is used more than once, then the biv is (effectively)
3159 used more than once. DATA is a pointer to a loop_regs structure. */
3161 static void
3163 rtx x;
3164 rtx y ATTRIBUTE_UNUSED;
3166 {
3181 /* If we do not have usage information, or if we know the register
3182 is used more than once, note that fact for check_dbra_loop. */
3187 }
3188 \f
3189 /* Return nonzero if the rtx X is invariant over the current loop.
3191 The value is 2 if we refer to something only conditionally invariant.
3193 A memory ref is invariant if it is not volatile and does not conflict
3194 with anything stored in `loop_info->store_mems'. */
3196 int
3199 rtx x;
3200 {
3207 rtx mem_list_entry;
3213 {
3221 /* A LABEL_REF is normally invariant, however, if we are unrolling
3222 loops, and this label is inside the loop, then it isn't invariant.
3223 This is because each unrolled copy of the loop body will have
3224 a copy of this label. If this was invariant, then an insn loading
3225 the address of this label into a register might get moved outside
3226 the loop, and then each loop body would end up using the same label.
3228 We don't know the loop bounds here though, so just fail for all
3229 labels. */
3232 else
3241 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3242 since the reg might be set by initialization within the loop. */
3259 /* Volatile memory references must be rejected. Do this before
3260 checking for read-only items, so that volatile read-only items
3261 will be rejected also. */
3265 /* See if there is any dependence between a store and this load. */
3268 {
3274 }
3276 /* It's not invalidated by a store in memory
3277 but we must still verify the address is invariant. */
3281 /* Don't mess with insns declared volatile. */
3288 }
3292 {
3294 {
3300 }
3302 {
3305 {
3311 }
3313 }
3314 }
3317 }
3318 \f
3319 /* Return nonzero if all the insns in the loop that set REG
3320 are INSN and the immediately following insns,
3321 and if each of those insns sets REG in an invariant way
3322 (not counting uses of REG in them).
3324 The value is 2 if some of these insns are only conditionally invariant.
3326 We assume that INSN itself is the first set of REG
3327 and that its source is invariant. */
3329 static int
3334 {
3338 rtx temp;
3339 /* Number of sets we have to insist on finding after INSN. */
3345 /* If N_SETS hit the limit, we can't rely on its value. */
3352 {
3354 rtx set;
3359 /* If library call, skip to end of it. */
3368 {
3373 {
3374 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3375 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3376 notes are OK. */
3382 }
3383 }
3385 count--;
3387 {
3390 }
3391 }
3394 /* If loop_invariant_p ever returned 2, we return 2. */
3396 }
3398 #if 0
3399 /* I don't think this condition is sufficient to allow INSN
3400 to be moved, so we no longer test it. */
3402 /* Return 1 if all insns in the basic block of INSN and following INSN
3403 that set REG are invariant according to TABLE. */
3405 static int
3409 {
3414 {
3423 {
3426 }
3427 }
3428 }
3430 \f
3431 /* Look at all uses (not sets) of registers in X. For each, if it is
3432 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3433 a different insn, set USAGE[REGNO] to const0_rtx. */
3435 static void
3438 rtx insn;
3439 rtx x;
3440 {
3452 {
3453 /* Don't count SET_DEST if it is a REG; otherwise count things
3454 in SET_DEST because if a register is partially modified, it won't
3455 show up as a potential movable so we don't care how USAGE is set
3456 for it. */
3460 }
3461 else
3463 {
3469 }
3470 }
3471 \f
3472 /* Count and record any set in X which is contained in INSN. Update
3473 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3474 in X. */
3476 static void
3481 {
3483 /* Don't move a reg that has an explicit clobber.
3484 It's not worth the pain to try to do it correctly. */
3488 {
3496 {
3500 {
3501 /* If this is the first setting of this reg
3502 in current basic block, and it was set before,
3503 it must be set in two basic blocks, so it cannot
3504 be moved out of the loop. */
3508 /* If this is not first setting in current basic block,
3509 see if reg was used in between previous one and this.
3510 If so, neither one can be moved. */
3517 }
3518 }
3519 }
3520 }
3521 \f
3522 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3523 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3524 contained in insn INSN is used by any insn that precedes INSN in
3525 cyclic order starting from the loop entry point.
3527 We don't want to use INSN_LUID here because if we restrict INSN to those
3528 that have a valid INSN_LUID, it means we cannot move an invariant out
3529 from an inner loop past two loops. */
3531 static int
3535 {
3537 rtx p;
3539 /* Scan forward checking for register usage. If we hit INSN, we
3540 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3542 {
3548 }
3551 }
3552 \f
3554 /* Information we collect about arrays that we might want to prefetch. */
3555 struct prefetch_info
3556 {
3560 index. */
3561 HOST_WIDE_INT index;
3563 iteration. */
3565 prefetch area in one iteration. */
3567 This is set only for loops with known
3568 iteration counts and is 0xffffffff
3569 otherwise. */
3573 };
3575 /* Data used by check_store function. */
3576 struct check_store_data
3577 {
3578 rtx mem_address;
3580 };
3586 /* Set mem_write when mem_address is found. Used as callback to
3587 note_stores. */
3588 static void
3592 {
3597 }
3598 \f
3599 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3600 important to get some addresses combined. Later more sophisticated
3601 transformations can be added when necesary.
3603 ??? Same trick with swapping operand is done at several other places.
3604 It can be nice to develop some common way to handle this. */
3606 static int
3609 {
3623 {
3628 }
3629 /* Compare the elements. If any pair of corresponding elements fails to
3630 match, return 0 for the whole thing. */
3634 {
3636 {
3648 /* Two vectors must have the same length. */
3652 /* And the corresponding elements must match. */
3670 /* These are just backpointers, so they don't matter. */
3676 /* It is believed that rtx's at this level will never
3677 contain anything but integers and other rtx's,
3678 except for within LABEL_REFs and SYMBOL_REFs. */
3681 }
3682 }
3684 }
3685 \f
3686 /* Remove constant addition value from the expression X (when present)
3687 and return it. */
3689 static HOST_WIDE_INT
3692 {
3696 /* Avoid clobbering a shared CONST expression. */
3698 {
3702 {
3705 }
3707 }
3710 {
3713 }
3715 /* For plus expression recurse on ourself. */
3717 {
3721 /* In case our parameter was constant, remove extra zero from the
3722 expression. */
3727 }
3730 }
3732 /* Attempt to identify accesses to arrays that are most likely to cause cache
3733 misses, and emit prefetch instructions a few prefetch blocks forward.
3735 To detect the arrays we use the GIV information that was collected by the
3736 strength reduction pass.
3738 The prefetch instructions are generated after the GIV information is done
3739 and before the strength reduction process. The new GIVs are injected into
3740 the strength reduction tables, so the prefetch addresses are optimized as
3741 well.
3743 GIVs are split into base address, stride, and constant addition values.
3744 GIVs with the same address, stride and close addition values are combined
3745 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3746 for write instructions can be used for the block we write to, on machines
3747 that support write prefetches.
3749 Several heuristics are used to determine when to prefetch. They are
3750 controlled by defined symbols that can be overridden for each target. */
3752 static void
3755 {
3771 /* Consider only loops w/o calls. When a call is done, the loop is probably
3772 slow enough to read the memory. */
3774 {
3779 }
3781 /* Don't prefetch in loops known to have few iterations. */
3785 {
3790 }
3792 /* Search all induction variables and pick those interesting for the prefetch
3793 machinery. */
3795 {
3801 /* Expect all BIVs to be executed in each iteration. This makes our
3802 analysis more conservative. */
3804 {
3805 /* Discard non-constant additions that we can't handle well yet, and
3806 BIVs that are executed multiple times; such BIVs ought to be
3807 handled in the nested loop. We accept not_every_iteration BIVs,
3808 since these only result in larger strides and make our
3809 heuristics more conservative. */
3811 {
3813 {
3819 }
3821 }
3824 {
3826 {
3832 }
3834 }
3838 }
3844 {
3845 rtx address;
3846 rtx temp;
3855 /* See whether an induction variable is interesting to us and if
3856 not, report the reason. */
3860 /* We are interested only in constant stride memory references
3861 in order to be able to compute density easily. */
3865 else
3866 {
3869 {
3872 }
3874 /* On some targets, reversed order prefetches are not
3875 worthwhile. */
3879 /* Prefetch of accesses with an extreme stride might not be
3880 worthwhile, either. */
3885 /* Ignore GIVs with varying add values; we can't predict the
3886 value for the next iteration. */
3890 /* Ignore GIVs in the nested loops; they ought to have been
3891 handled already. */
3894 }
3897 {
3903 }
3905 /* Determine the pointer to the basic array we are examining. It is
3906 the sum of the BIV's initial value and the GIV's add_val. */
3916 /* When the GIV is not always executed, we might be better off by
3917 not dirtying the cache pages. */
3920 else
3921 {
3926 }
3928 /* Attempt to find another prefetch to the same array and see if we
3929 can merge this one. */
3933 {
3934 /* In case both access same array (same location
3935 just with small difference in constant indexes), merge
3936 the prefetches. Just do the later and the earlier will
3937 get prefetched from previous iteration.
3938 The artificial threshold should not be too small,
3939 but also not bigger than small portion of memory usually
3940 traversed by single loop. */
3943 {
3952 }
3956 {
3961 }
3962 }
3964 /* Merging failed. */
3966 {
3974 num_prefetches++;
3976 {
3981 }
3982 }
3983 }
3984 }
3987 {
3990 /* Attempt to calculate the total number of bytes fetched by all
3991 iterations of the loop. Avoid overflow. */
3996 else
4001 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4006 {
4011 }
4012 else
4013 {
4019 }
4020 else
4023 /* Find how many prefetch instructions we'll use within the loop. */
4025 {
4031 }
4032 }
4034 /* Determine how many iterations ahead to prefetch within the loop, based
4035 on how many prefetches we currently expect to do within the loop. */
4037 {
4039 {
4045 }
4046 }
4047 /* We'll also use AHEAD to determine how many prefetch instructions to
4048 emit before a loop, so don't leave it zero. */
4053 {
4054 /* Update if we've decided not to prefetch anything within the loop. */
4058 /* Find how many prefetch instructions we'll use before the loop. */
4060 {
4068 }
4071 {
4093 }
4094 }
4097 {
4098 /* Record that this loop uses prefetch instructions. */
4102 {
4107 }
4108 }
4111 {
4115 {
4117 rtx insn;
4121 rtx seq;
4123 /* We can save some effort by offsetting the address on
4124 architectures with offsettable memory references. */
4127 else
4128 {
4134 }
4137 /* Make sure the address operand is valid for prefetch. */
4147 /* Check all insns emitted and record the new GIV
4148 information. */
4151 {
4156 }
4157 }
4160 {
4161 /* Emit insns before the loop to fetch the first cache lines or,
4162 if we're not prefetching within the loop, everything we expect
4163 to need. */
4165 {
4173 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4174 non-constant INIT_VAL to have the same mode as REG, which
4175 in this case we know to be Pmode. */
4183 loop_start);
4184 }
4185 }
4186 }
4189 }
4190 \f
4191 /* A "basic induction variable" or biv is a pseudo reg that is set
4192 (within this loop) only by incrementing or decrementing it. */
4193 /* A "general induction variable" or giv is a pseudo reg whose
4194 value is a linear function of a biv. */
4196 /* Bivs are recognized by `basic_induction_var';
4197 Givs by `general_induction_var'. */
4199 /* Communication with routines called via `note_stores'. */
4203 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4207 /* ??? Unfinished optimizations, and possible future optimizations,
4208 for the strength reduction code. */
4210 /* ??? The interaction of biv elimination, and recognition of 'constant'
4211 bivs, may cause problems. */
4213 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4214 performance problems.
4216 Perhaps don't eliminate things that can be combined with an addressing
4217 mode. Find all givs that have the same biv, mult_val, and add_val;
4218 then for each giv, check to see if its only use dies in a following
4219 memory address. If so, generate a new memory address and check to see
4220 if it is valid. If it is valid, then store the modified memory address,
4221 otherwise, mark the giv as not done so that it will get its own iv. */
4223 /* ??? Could try to optimize branches when it is known that a biv is always
4224 positive. */
4226 /* ??? When replace a biv in a compare insn, we should replace with closest
4227 giv so that an optimized branch can still be recognized by the combiner,
4228 e.g. the VAX acb insn. */
4230 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4231 was rerun in loop_optimize whenever a register was added or moved.
4232 Also, some of the optimizations could be a little less conservative. */
4233 \f
4234 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4235 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4236 callback.
4238 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4239 least once for every loop iteration except for the last one.
4241 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4242 loop iteration.
4243 */
4244 void
4247 loop_insn_callback fncall;
4248 {
4253 rtx p;
4255 /* If loop_scan_start points to the loop exit test, we have to be wary of
4256 subversive use of gotos inside expression statements. */
4260 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4264 {
4267 /* Past CODE_LABEL, we get to insns that may be executed multiple
4268 times. The only way we can be sure that they can't is if every
4269 jump insn between here and the end of the loop either
4270 returns, exits the loop, is a jump to a location that is still
4271 behind the label, or is a jump to the loop start. */
4274 {
4280 {
4285 {
4288 else
4292 }
4300 {
4303 }
4304 }
4305 }
4307 /* Past a jump, we get to insns for which we can't count
4308 on whether they will be executed during each iteration. */
4309 /* This code appears twice in strength_reduce. There is also similar
4310 code in scan_loop. */
4312 /* If we enter the loop in the middle, and scan around to the
4313 beginning, don't set not_every_iteration for that.
4314 This can be any kind of jump, since we want to know if insns
4315 will be executed if the loop is executed. */
4320 {
4323 /* If this is a jump outside the loop, then it also doesn't
4324 matter. Check to see if the target of this branch is on the
4325 loop->exits_labels list. */
4333 }
4336 {
4337 /* At the virtual top of a converted loop, insns are again known to
4338 be executed each iteration: logically, the loop begins here
4339 even though the exit code has been duplicated.
4341 Insns are also again known to be executed each iteration at
4342 the LOOP_CONT note. */
4348 loop_depth++;
4350 loop_depth--;
4351 }
4353 /* Note if we pass a loop latch. If we do, then we can not clear
4354 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4355 a loop since a jump before the last CODE_LABEL may have started
4356 a new loop iteration.
4358 Note that LOOP_TOP is only set for rotated loops and we need
4359 this check for all loops, so compare against the CODE_LABEL
4360 which immediately follows LOOP_START. */
4365 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4366 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4367 or not an insn is known to be executed each iteration of the
4368 loop, whether or not any iterations are known to occur.
4370 Therefore, if we have just passed a label and have no more labels
4371 between here and the test insn of the loop, and we have not passed
4372 a jump to the top of the loop, then we know these insns will be
4373 executed each iteration. */
4376 && !past_loop_latch
4381 }
4382 }
4383 \f
4384 static void
4387 {
4390 /* Temporary list pointers for traversing ivs->list. */
4397 /* Scan ivs->list to remove all regs that proved not to be bivs.
4398 Make a sanity check against regs->n_times_set. */
4400 {
4402 /* Above happens if register modified by subreg, etc. */
4403 /* Make sure it is not recognized as a basic induction var: */
4405 /* If never incremented, it is invariant that we decided not to
4406 move. So leave it alone. */
4408 {
4419 }
4420 else
4421 {
4426 }
4427 }
4428 }
4431 /* Determine how BIVS are initialised by looking through pre-header
4432 extended basic block. */
4433 static void
4436 {
4438 /* Temporary list pointers for traversing ivs->list. */
4441 rtx p;
4443 /* Find initial value for each biv by searching backwards from loop_start,
4444 halting at first label. Also record any test condition. */
4448 {
4449 rtx test;
4459 /* Record any test of a biv that branches around the loop if no store
4460 between it and the start of loop. We only care about tests with
4461 constants and registers and only certain of those. */
4471 {
4472 /* If an NE test, we have an initial value! */
4474 {
4478 }
4479 else
4481 }
4482 }
4483 }
4486 /* Look at the each biv and see if we can say anything better about its
4487 initial value from any initializing insns set up above. (This is done
4488 in two passes to avoid missing SETs in a PARALLEL.) */
4489 static void
4492 {
4494 /* Temporary list pointers for traversing ivs->list. */
4499 {
4500 rtx src;
4501 rtx note;
4506 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4507 is a constant, use the value of that. */
4513 else
4526 {
4530 {
4533 }
4534 }
4535 /* If we can't make it a giv,
4536 let biv keep initial value of "itself". */
4539 }
4540 }
4543 /* Search the loop for general induction variables. */
4545 static void
4548 {
4550 }
4553 /* For each giv for which we still don't know whether or not it is
4554 replaceable, check to see if it is replaceable because its final value
4555 can be calculated. */
4557 static void
4560 {
4565 {
4571 }
4572 }
4575 /* Return non-zero if it is possible to eliminate the biv BL provided
4576 all givs are reduced. This is possible if either the reg is not
4577 used outside the loop, or we can compute what its final value will
4578 be. */
4580 static int
4586 {
4587 /* For architectures with a decrement_and_branch_until_zero insn,
4588 don't do this if we put a REG_NONNEG note on the endtest for this
4589 biv. */
4591 #ifdef HAVE_decrement_and_branch_until_zero
4593 {
4598 }
4599 #endif
4601 /* Check that biv is used outside loop or if it has a final value.
4602 Compare against bl->init_insn rather than loop->start. We aren't
4603 concerned with any uses of the biv between init_insn and
4604 loop->start since these won't be affected by the value of the biv
4605 elsewhere in the function, so long as init_insn doesn't use the
4606 biv itself. */
4617 {
4625 }
4627 }
4630 /* Reduce each giv of BL that we have decided to reduce. */
4632 static void
4636 {
4640 {
4643 {
4646 /* If the code for derived givs immediately below has already
4647 allocated a new_reg, we must keep it. */
4651 #ifdef AUTO_INC_DEC
4652 /* If the target has auto-increment addressing modes, and
4653 this is an address giv, then try to put the increment
4654 immediately after its use, so that flow can create an
4655 auto-increment addressing mode. */
4658 /* We don't handle reversed biv's because bl->biv->insn
4659 does not have a valid INSN_LUID. */
4663 {
4664 /* If other giv's have been combined with this one, then
4665 this will work only if all uses of the other giv's occur
4666 before this giv's insn. This is difficult to check.
4668 We simplify this by looking for the common case where
4669 there is one DEST_REG giv, and this giv's insn is the
4670 last use of the dest_reg of that DEST_REG giv. If the
4671 increment occurs after the address giv, then we can
4672 perform the optimization. (Otherwise, the increment
4673 would have to go before other_giv, and we would not be
4674 able to combine it with the address giv to get an
4675 auto-inc address.) */
4677 {
4682 {
4685 else
4687 }
4694 }
4695 /* Check for case where increment is before the address
4696 giv. Do this test in "loop order". */
4705 else
4708 #ifdef HAVE_cc0
4709 {
4710 rtx prev;
4712 /* We can't put an insn immediately after one setting
4713 cc0, or immediately before one using cc0. */
4720 }
4721 #endif
4725 }
4726 #endif
4728 /* For each place where the biv is incremented, add an insn
4729 to increment the new, reduced reg for the giv. */
4731 {
4732 rtx insert_before;
4738 else
4746 /* A multiply is acceptable here
4747 since this is presumed to be seldom executed. */
4751 }
4753 /* Add code at loop start to initialize giv's reduced reg. */
4758 }
4759 }
4760 }
4763 /* Check for givs whose first use is their definition and whose
4764 last use is the definition of another giv. If so, it is likely
4765 dead and should not be used to derive another giv nor to
4766 eliminate a biv. */
4768 static void
4772 {
4776 {
4783 {
4789 }
4790 }
4791 }
4794 static void
4799 {
4803 {
4810 /* Update expression if this was combined, in case other giv was
4811 replaced. */
4816 /* See if this register is known to be a pointer to something. If
4817 so, see if we can find the alignment. First see if there is a
4818 destination register that is a pointer. If so, this shares the
4819 alignment too. Next see if we can deduce anything from the
4820 computational information. If not, and this is a DEST_ADDR
4821 giv, at least we know that it's a pointer, though we don't know
4822 the alignment. */
4830 {
4839 }
4843 {
4851 }
4856 /* Store reduced reg as the address in the memref where we found
4857 this giv. */
4860 {
4862 }
4863 else
4864 {
4866 rtx note;
4868 /* Not replaceable; emit an insn to set the original giv reg from
4869 the reduced giv, same as above. */
4874 /* The original insn may have a REG_EQUAL note. This note is
4875 now incorrect and may result in invalid substitutions later.
4876 The original insn is dead, but may be part of a libcall
4877 sequence, which doesn't seem worth the bother of handling. */
4881 }
4883 /* When a loop is reversed, givs which depend on the reversed
4884 biv, and which are live outside the loop, must be set to their
4885 correct final value. This insn is only needed if the giv is
4886 not replaceable. The correct final value is the same as the
4887 value that the giv starts the reversed loop with. */
4898 {
4903 }
4904 }
4905 }
4908 static int
4913 rtx test_reg;
4914 {
4923 /* Reduce benefit if not replaceable, since we will insert a
4924 move-insn to replace the insn that calculates this giv. Don't do
4925 this unless the giv is a user variable, since it will often be
4926 marked non-replaceable because of the duplication of the exit
4927 code outside the loop. In such a case, the copies we insert are
4928 dead and will be deleted. So they don't have a cost. Similar
4929 situations exist. */
4930 /* ??? The new final_[bg]iv_value code does a much better job of
4931 finding replaceable giv's, and hence this code may no longer be
4932 necessary. */
4937 /* Decrease the benefit to count the add-insns that we will insert
4938 to increment the reduced reg for the giv. ??? This can
4939 overestimate the run-time cost of the additional insns, e.g. if
4940 there are multiple basic blocks that increment the biv, but only
4941 one of these blocks is executed during each iteration. There is
4942 no good way to detect cases like this with the current structure
4943 of the loop optimizer. This code is more accurate for
4944 determining code size than run-time benefits. */
4947 /* Decide whether to strength-reduce this giv or to leave the code
4948 unchanged (recompute it from the biv each time it is used). This
4949 decision can be made independently for each giv. */
4951 #ifdef AUTO_INC_DEC
4952 /* Attempt to guess whether autoincrement will handle some of the
4953 new add insns; if so, increase BENEFIT (undo the subtraction of
4954 add_cost that was done above). */
4956 /* Increasing the benefit is risky, since this is only a guess.
4957 Avoid increasing register pressure in cases where there would
4958 be no other benefit from reducing this giv. */
4961 {
4976 }
4977 #endif
4980 }
4983 /* Free IV structures for LOOP. */
4985 static void
4988 {
4995 {
5001 {
5004 }
5006 {
5009 }
5013 }
5014 }
5017 /* Perform strength reduction and induction variable elimination.
5019 Pseudo registers created during this function will be beyond the
5020 last valid index in several tables including
5021 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5022 problem here, because the added registers cannot be givs outside of
5023 their loop, and hence will never be reconsidered. But scan_loop
5024 must check regnos to make sure they are in bounds. */
5026 static void
5030 {
5034 rtx p;
5035 /* Temporary list pointer for traversing ivs->list. */
5037 /* Ratio of extra register life span we can justify
5038 for saving an instruction. More if loop doesn't call subroutines
5039 since in that case saving an insn makes more difference
5040 and more registers are available. */
5041 /* ??? could set this to last value of threshold in move_movables */
5043 /* Map of pseudo-register replacements. */
5055 /* Find all BIVs in loop. */
5058 /* Exit if there are no bivs. */
5060 {
5061 /* Can still unroll the loop anyways, but indicate that there is no
5062 strength reduction info available. */
5068 }
5070 /* Determine how BIVS are initialised by looking through pre-header
5071 extended basic block. */
5074 /* Look at the each biv and see if we can say anything better about its
5075 initial value from any initializing insns set up above. */
5078 /* Search the loop for general induction variables. */
5081 /* Try to calculate and save the number of loop iterations. This is
5082 set to zero if the actual number can not be calculated. This must
5083 be called after all giv's have been identified, since otherwise it may
5084 fail if the iteration variable is a giv. */
5087 #ifdef HAVE_prefetch
5090 #endif
5092 /* Now for each giv for which we still don't know whether or not it is
5093 replaceable, check to see if it is replaceable because its final value
5094 can be calculated. This must be done after loop_iterations is called,
5095 so that final_giv_value will work correctly. */
5098 /* Try to prove that the loop counter variable (if any) is always
5099 nonnegative; if so, record that fact with a REG_NONNEG note
5100 so that "decrement and branch until zero" insn can be used. */
5103 /* Create reg_map to hold substitutions for replaceable giv regs.
5104 Some givs might have been made from biv increments, so look at
5105 ivs->reg_iv_type for a suitable size. */
5109 /* Examine each iv class for feasibility of strength reduction/induction
5110 variable elimination. */
5113 {
5117 /* Test whether it will be possible to eliminate this biv
5118 provided all givs are reduced. */
5121 /* This will be true at the end, if all givs which depend on this
5122 biv have been strength reduced.
5123 We can't (currently) eliminate the biv unless this is so. */
5126 /* Check each extension dependent giv in this class to see if its
5127 root biv is safe from wrapping in the interior mode. */
5130 /* Combine all giv's for this iv_class. */
5134 {
5142 /* If an insn is not to be strength reduced, then set its ignore
5143 flag, and clear bl->all_reduced. */
5145 /* A giv that depends on a reversed biv must be reduced if it is
5146 used after the loop exit, otherwise, it would have the wrong
5147 value after the loop exit. To make it simple, just reduce all
5148 of such giv's whether or not we know they are used after the loop
5149 exit. */
5154 {
5162 }
5163 else
5164 {
5165 /* Check that we can increment the reduced giv without a
5166 multiply insn. If not, reject it. */
5171 {
5179 }
5180 }
5181 }
5183 /* Check for givs whose first use is their definition and whose
5184 last use is the definition of another giv. If so, it is likely
5185 dead and should not be used to derive another giv nor to
5186 eliminate a biv. */
5189 /* Reduce each giv that we decided to reduce. */
5192 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5193 as not reduced.
5195 For each giv register that can be reduced now: if replaceable,
5196 substitute reduced reg wherever the old giv occurs;
5197 else add new move insn "giv_reg = reduced_reg". */
5200 /* All the givs based on the biv bl have been reduced if they
5201 merit it. */
5203 /* For each giv not marked as maybe dead that has been combined with a
5204 second giv, clear any "maybe dead" mark on that second giv.
5205 v->new_reg will either be or refer to the register of the giv it
5206 combined with.
5208 Doing this clearing avoids problems in biv elimination where
5209 a giv's new_reg is a complex value that can't be put in the
5210 insn but the giv combined with (with a reg as new_reg) is
5211 marked maybe_dead. Since the register will be used in either
5212 case, we'd prefer it be used from the simpler giv. */
5218 /* Try to eliminate the biv, if it is a candidate.
5219 This won't work if ! bl->all_reduced,
5220 since the givs we planned to use might not have been reduced.
5222 We have to be careful that we didn't initially think we could
5223 eliminate this biv because of a giv that we now think may be
5224 dead and shouldn't be used as a biv replacement.
5226 Also, there is the possibility that we may have a giv that looks
5227 like it can be used to eliminate a biv, but the resulting insn
5228 isn't valid. This can happen, for example, on the 88k, where a
5229 JUMP_INSN can compare a register only with zero. Attempts to
5230 replace it with a compare with a constant will fail.
5232 Note that in cases where this call fails, we may have replaced some
5233 of the occurrences of the biv with a giv, but no harm was done in
5234 doing so in the rare cases where it can occur. */
5238 {
5239 /* ?? If we created a new test to bypass the loop entirely,
5240 or otherwise drop straight in, based on this test, then
5241 we might want to rewrite it also. This way some later
5242 pass has more hope of removing the initialization of this
5243 biv entirely. */
5245 /* If final_value != 0, then the biv may be used after loop end
5246 and we must emit an insn to set it just in case.
5248 Reversed bivs already have an insn after the loop setting their
5249 value, so we don't need another one. We can't calculate the
5250 proper final value for such a biv here anyways. */
5259 }
5260 /* See above note wrt final_value. But since we couldn't eliminate
5261 the biv, we must set the value after the loop instead of before. */
5265 }
5267 /* Go through all the instructions in the loop, making all the
5268 register substitutions scheduled in REG_MAP. */
5273 {
5277 }
5280 {
5281 /* When we completely unroll a loop we will likely not need the increment
5282 of the loop BIV and we will not need the conditional branch at the
5283 end of the loop. */
5286 #ifdef HAVE_cc0
5287 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5288 need the comparison before the conditional branch at the end of the
5289 loop. */
5291 #endif
5293 /* We'll need one copy for each loop iteration. */
5296 /* A little slop to account for the ability to remove initialization
5297 code, better CSE, and other secondary benefits of completely
5298 unrolling some loops. */
5301 /* Clamp the value. */
5304 }
5306 /* Unroll loops from within strength reduction so that we can use the
5307 induction variable information that strength_reduce has already
5308 collected. Always unroll loops that would be as small or smaller
5309 unrolled than when rolled. */
5316 #ifdef HAVE_doloop_end
5321 /* In case number of iterations is known, drop branch prediction note
5322 in the branch. Do that only in second loop pass, as loop unrolling
5323 may change the number of iterations performed. */
5325 {
5326 unsigned HOST_WIDE_INT n
5331 }
5339 }
5340 \f
5341 /*Record all basic induction variables calculated in the insn. */
5342 static rtx
5345 rtx p;
5348 {
5350 rtx set;
5351 rtx dest_reg;
5352 rtx inc_val;
5353 rtx mult_val;
5359 {
5364 {
5369 {
5370 /* It is a possible basic induction variable.
5371 Create and initialize an induction structure for it. */
5379 }
5382 }
5383 }
5385 }
5386 \f
5387 /* Record all givs calculated in the insn.
5388 A register is a giv if: it is only set once, it is a function of a
5389 biv and a constant (or invariant), and it is not a biv. */
5390 static rtx
5393 rtx p;
5396 {
5399 rtx set;
5400 /* Look for a general induction variable in a register. */
5405 {
5406 rtx src_reg;
5407 rtx dest_reg;
5408 rtx add_val;
5409 rtx mult_val;
5410 rtx ext_val;
5413 rtx last_consec_insn;
5422 /* Equivalent expression is a giv. */
5427 /* Don't try to handle any regs made by loop optimization.
5428 We have nothing on them in regno_first_uid, etc. */
5430 /* Don't recognize a BASIC_INDUCT_VAR here. */
5432 /* This must be the only place where the register is set. */
5434 /* or all sets must be consecutive and make a giv. */
5439 {
5443 /* If this is a library call, increase benefit. */
5447 /* Skip the consecutive insns, if there are any. */
5455 }
5456 }
5458 #ifndef DONT_REDUCE_ADDR
5459 /* Look for givs which are memory addresses. */
5460 /* This resulted in worse code on a VAX 8600. I wonder if it
5461 still does. */
5464 maybe_multiple);
5465 #endif
5467 /* Update the status of whether giv can derive other givs. This can
5468 change when we pass a label or an insn that updates a biv. */
5473 }
5474 \f
5475 /* Return 1 if X is a valid source for an initial value (or as value being
5476 compared against in an initial test).
5478 X must be either a register or constant and must not be clobbered between
5479 the current insn and the start of the loop.
5481 INSN is the insn containing X. */
5483 static int
5485 rtx x;
5486 rtx insn;
5488 rtx loop_start;
5489 {
5493 /* Only consider pseudos we know about initialized in insns whose luids
5494 we know. */
5499 /* Don't use call-clobbered registers across a call which clobbers it. On
5500 some machines, don't use any hard registers at all. */
5502 && (SMALL_REGISTER_CLASSES
5506 /* Don't use registers that have been clobbered before the start of the
5507 loop. */
5512 }
5513 \f
5514 /* Scan X for memory refs and check each memory address
5515 as a possible giv. INSN is the insn whose pattern X comes from.
5516 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5517 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5518 more thanonce in each loop iteration. */
5520 static void
5523 rtx x;
5524 rtx insn;
5526 {
5536 {
5552 {
5553 rtx src_reg;
5554 rtx add_val;
5555 rtx mult_val;
5556 rtx ext_val;
5559 /* This code used to disable creating GIVs with mult_val == 1 and
5560 add_val == 0. However, this leads to lost optimizations when
5561 it comes time to combine a set of related DEST_ADDR GIVs, since
5562 this one would not be seen. */
5567 {
5568 /* Found one; record it. */
5577 }
5578 }
5583 }
5585 /* Recursively scan the subexpressions for other mem refs. */
5591 maybe_multiple);
5595 maybe_multiple);
5596 }
5597 \f
5598 /* Fill in the data about one biv update.
5599 V is the `struct induction' in which we record the biv. (It is
5600 allocated by the caller, with alloca.)
5601 INSN is the insn that sets it.
5602 DEST_REG is the biv's reg.
5604 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5605 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5606 being set to INC_VAL.
5608 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5609 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5610 can be executed more than once per iteration. If MAYBE_MULTIPLE
5611 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5612 executed exactly once per iteration. */
5614 static void
5619 rtx insn;
5620 rtx dest_reg;
5621 rtx inc_val;
5622 rtx mult_val;
5626 {
5642 /* Add this to the reg's iv_class, creating a class
5643 if this is the first incrementation of the reg. */
5647 {
5648 /* Create and initialize new iv_class. */
5658 /* Set initial value to the reg itself. */
5661 /* We haven't seen the initializing insn yet */
5671 /* Add this class to ivs->list. */
5675 /* Put it in the array of biv register classes. */
5677 }
5679 /* Update IV_CLASS entry for this biv. */
5688 }
5689 \f
5690 /* Fill in the data about one giv.
5691 V is the `struct induction' in which we record the giv. (It is
5692 allocated by the caller, with alloca.)
5693 INSN is the insn that sets it.
5694 BENEFIT estimates the savings from deleting this insn.
5695 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5696 into a register or is used as a memory address.
5698 SRC_REG is the biv reg which the giv is computed from.
5699 DEST_REG is the giv's reg (if the giv is stored in a reg).
5700 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5701 LOCATION points to the place where this giv's value appears in INSN. */
5703 static void
5708 rtx insn;
5709 rtx src_reg;
5710 rtx dest_reg;
5716 {
5721 rtx temp;
5723 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5724 undo the MULT canonicalization that we performed earlier. */
5754 /* The v->always_computable field is used in update_giv_derive, to
5755 determine whether a giv can be used to derive another giv. For a
5756 DEST_REG giv, INSN computes a new value for the giv, so its value
5757 isn't computable if INSN insn't executed every iteration.
5758 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5759 it does not compute a new value. Hence the value is always computable
5760 regardless of whether INSN is executed each iteration. */
5764 else
5770 {
5773 }
5775 {
5780 /* If the lifetime is zero, it means that this register is
5781 really a dead store. So mark this as a giv that can be
5782 ignored. This will not prevent the biv from being eliminated. */
5788 }
5790 /* Add the giv to the class of givs computed from one biv. */
5794 {
5797 /* Don't count DEST_ADDR. This is supposed to count the number of
5798 insns that calculate givs. */
5802 }
5803 else
5804 /* Fatal error, biv missing for this giv? */
5809 else
5810 {
5811 /* The giv can be replaced outright by the reduced register only if all
5812 of the following conditions are true:
5813 - the insn that sets the giv is always executed on any iteration
5814 on which the giv is used at all
5815 (there are two ways to deduce this:
5816 either the insn is executed on every iteration,
5817 or all uses follow that insn in the same basic block),
5818 - the giv is not used outside the loop
5819 - no assignments to the biv occur during the giv's lifetime. */
5822 /* Previous line always fails if INSN was moved by loop opt. */
5825 && (! not_every_iteration
5827 {
5828 /* Now check that there are no assignments to the biv within the
5829 giv's lifetime. This requires two separate checks. */
5831 /* Check each biv update, and fail if any are between the first
5832 and last use of the giv.
5834 If this loop contains an inner loop that was unrolled, then
5835 the insn modifying the biv may have been emitted by the loop
5836 unrolling code, and hence does not have a valid luid. Just
5837 mark the biv as not replaceable in this case. It is not very
5838 useful as a biv, because it is used in two different loops.
5839 It is very unlikely that we would be able to optimize the giv
5840 using this biv anyways. */
5844 {
5850 {
5854 }
5855 }
5857 /* If there are any backwards branches that go from after the
5858 biv update to before it, then this giv is not replaceable. */
5862 {
5866 }
5867 }
5868 else
5869 {
5870 /* May still be replaceable, we don't have enough info here to
5871 decide. */
5874 }
5875 }
5877 /* Record whether the add_val contains a const_int, for later use by
5878 combine_givs. */
5879 {
5884 ;
5888 {
5890 {
5895 else
5897 }
5900 }
5901 }
5905 }
5907 /* All this does is determine whether a giv can be made replaceable because
5908 its final value can be calculated. This code can not be part of record_giv
5909 above, because final_giv_value requires that the number of loop iterations
5910 be known, and that can not be accurately calculated until after all givs
5911 have been identified. */
5913 static void
5917 {
5924 /* DEST_ADDR givs will never reach here, because they are always marked
5925 replaceable above in record_giv. */
5927 /* The giv can be replaced outright by the reduced register only if all
5928 of the following conditions are true:
5929 - the insn that sets the giv is always executed on any iteration
5930 on which the giv is used at all
5931 (there are two ways to deduce this:
5932 either the insn is executed on every iteration,
5933 or all uses follow that insn in the same basic block),
5934 - its final value can be calculated (this condition is different
5935 than the one above in record_giv)
5936 - it's not used before the it's set
5937 - no assignments to the biv occur during the giv's lifetime. */
5939 #if 0
5940 /* This is only called now when replaceable is known to be false. */
5941 /* Clear replaceable, so that it won't confuse final_giv_value. */
5943 #endif
5948 {
5951 rtx last_giv_use;
5955 /* When trying to determine whether or not a biv increment occurs
5956 during the lifetime of the giv, we can ignore uses of the variable
5957 outside the loop because final_value is true. Hence we can not
5958 use regno_last_uid and regno_first_uid as above in record_giv. */
5960 /* Search the loop to determine whether any assignments to the
5961 biv occur during the giv's lifetime. Start with the insn
5962 that sets the giv, and search around the loop until we come
5963 back to that insn again.
5965 Also fail if there is a jump within the giv's lifetime that jumps
5966 to somewhere outside the lifetime but still within the loop. This
5967 catches spaghetti code where the execution order is not linear, and
5968 hence the above test fails. Here we assume that the giv lifetime
5969 does not extend from one iteration of the loop to the next, so as
5970 to make the test easier. Since the lifetime isn't known yet,
5971 this requires two loops. See also record_giv above. */
5976 {
5979 {
5982 }
5988 {
5989 /* It is possible for the BIV increment to use the GIV if we
5990 have a cycle. Thus we must be sure to check each insn for
5991 both BIV and GIV uses, and we must check for BIV uses
5992 first. */
5999 {
6001 {
6005 }
6007 }
6008 }
6009 }
6011 /* Now that the lifetime of the giv is known, check for branches
6012 from within the lifetime to outside the lifetime if it is still
6013 replaceable. */
6016 {
6019 {
6032 {
6041 }
6042 }
6043 }
6045 /* If it is replaceable, then save the final value. */
6048 }
6053 }
6054 \f
6055 /* Update the status of whether a giv can derive other givs.
6057 We need to do something special if there is or may be an update to the biv
6058 between the time the giv is defined and the time it is used to derive
6059 another giv.
6061 In addition, a giv that is only conditionally set is not allowed to
6062 derive another giv once a label has been passed.
6064 The cases we look at are when a label or an update to a biv is passed. */
6066 static void
6069 rtx p;
6070 {
6074 rtx tem;
6077 /* Search all IV classes, then all bivs, and finally all givs.
6079 There are three cases we are concerned with. First we have the situation
6080 of a giv that is only updated conditionally. In that case, it may not
6081 derive any givs after a label is passed.
6083 The second case is when a biv update occurs, or may occur, after the
6084 definition of a giv. For certain biv updates (see below) that are
6085 known to occur between the giv definition and use, we can adjust the
6086 giv definition. For others, or when the biv update is conditional,
6087 we must prevent the giv from deriving any other givs. There are two
6088 sub-cases within this case.
6090 If this is a label, we are concerned with any biv update that is done
6091 conditionally, since it may be done after the giv is defined followed by
6092 a branch here (actually, we need to pass both a jump and a label, but
6093 this extra tracking doesn't seem worth it).
6095 If this is a jump, we are concerned about any biv update that may be
6096 executed multiple times. We are actually only concerned about
6097 backward jumps, but it is probably not worth performing the test
6098 on the jump again here.
6100 If this is a biv update, we must adjust the giv status to show that a
6101 subsequent biv update was performed. If this adjustment cannot be done,
6102 the giv cannot derive further givs. */
6108 {
6110 {
6111 /* If cant_derive is already true, there is no point in
6112 checking all of these conditions again. */
6116 /* If this giv is conditionally set and we have passed a label,
6117 it cannot derive anything. */
6121 /* Skip givs that have mult_val == 0, since
6122 they are really invariants. Also skip those that are
6123 replaceable, since we know their lifetime doesn't contain
6124 any biv update. */
6128 /* The only way we can allow this giv to derive another
6129 is if this is a biv increment and we can form the product
6130 of biv->add_val and giv->mult_val. In this case, we will
6131 be able to compute a compensation. */
6133 {
6134 rtx ext_val_dummy;
6145 tem = simplify_giv_expr
6152 else
6154 }
6158 }
6159 }
6160 }
6161 \f
6162 /* Check whether an insn is an increment legitimate for a basic induction var.
6163 X is the source of insn P, or a part of it.
6164 MODE is the mode in which X should be interpreted.
6166 DEST_REG is the putative biv, also the destination of the insn.
6167 We accept patterns of these forms:
6168 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6169 REG = INVARIANT + REG
6171 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6172 store the additive term into *INC_VAL, and store the place where
6173 we found the additive term into *LOCATION.
6175 If X is an assignment of an invariant into DEST_REG, we set
6176 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6178 We also want to detect a BIV when it corresponds to a variable
6179 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6180 of the variable may be a PLUS that adds a SUBREG of that variable to
6181 an invariant and then sign- or zero-extends the result of the PLUS
6182 into the variable.
6184 Most GIVs in such cases will be in the promoted mode, since that is the
6185 probably the natural computation mode (and almost certainly the mode
6186 used for addresses) on the machine. So we view the pseudo-reg containing
6187 the variable as the BIV, as if it were simply incremented.
6189 Note that treating the entire pseudo as a BIV will result in making
6190 simple increments to any GIVs based on it. However, if the variable
6191 overflows in its declared mode but not its promoted mode, the result will
6192 be incorrect. This is acceptable if the variable is signed, since
6193 overflows in such cases are undefined, but not if it is unsigned, since
6194 those overflows are defined. So we only check for SIGN_EXTEND and
6195 not ZERO_EXTEND.
6197 If we cannot find a biv, we return 0. */
6199 static int
6202 rtx x;
6204 rtx dest_reg;
6205 rtx p;
6209 {
6217 {
6223 {
6225 }
6230 {
6232 }
6233 else
6246 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6247 handle addition of promoted variables.
6248 ??? The comment at the start of this function is wrong: promoted
6249 variable increments don't look like it says they do. */
6255 /* If this register is assigned in a previous insn, look at its
6256 source, but don't go outside the loop or past a label. */
6258 /* If this sets a register to itself, we would repeat any previous
6259 biv increment if we applied this strategy blindly. */
6265 {
6266 rtx dest;
6267 do
6268 {
6270 }
6299 }
6300 /* Fall through. */
6302 /* Can accept constant setting of biv only when inside inner most loop.
6303 Otherwise, a biv of an inner loop may be incorrectly recognized
6304 as a biv of the outer loop,
6305 causing code to be moved INTO the inner loop. */
6312 /* convert_modes aborts if we try to convert to or from CCmode, so just
6313 exclude that case. It is very unlikely that a condition code value
6314 would be a useful iterator anyways. convert_modes aborts if we try to
6315 convert a float mode to non-float or vice versa too. */
6319 {
6320 /* Possible bug here? Perhaps we don't know the mode of X. */
6324 }
6325 else
6333 /* Similar, since this can be a sign extension. */
6338 ;
6352 location);
6357 }
6358 }
6359 \f
6360 /* A general induction variable (giv) is any quantity that is a linear
6361 function of a basic induction variable,
6362 i.e. giv = biv * mult_val + add_val.
6363 The coefficients can be any loop invariant quantity.
6364 A giv need not be computed directly from the biv;
6365 it can be computed by way of other givs. */
6367 /* Determine whether X computes a giv.
6368 If it does, return a nonzero value
6369 which is the benefit from eliminating the computation of X;
6370 set *SRC_REG to the register of the biv that it is computed from;
6371 set *ADD_VAL and *MULT_VAL to the coefficients,
6372 such that the value of X is biv * mult + add; */
6374 static int
6378 rtx x;
6386 {
6390 /* If this is an invariant, forget it, it isn't a giv. */
6401 {
6404 /* Since this is now an invariant and wasn't before, it must be a giv
6405 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6406 with. */
6413 /* This is equivalent to a BIV. */
6420 /* Either (plus (biv) (invar)) or
6421 (plus (mult (biv) (invar_1)) (invar_2)). */
6423 {
6426 }
6427 else
6428 {
6431 }
6436 /* ADD_VAL is zero. */
6444 }
6446 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6447 unless they are CONST_INT). */
6455 else
6458 /* Always return true if this is a giv so it will be detected as such,
6459 even if the benefit is zero or negative. This allows elimination
6460 of bivs that might otherwise not be eliminated. */
6462 }
6463 \f
6464 /* Given an expression, X, try to form it as a linear function of a biv.
6465 We will canonicalize it to be of the form
6466 (plus (mult (BIV) (invar_1))
6467 (invar_2))
6468 with possible degeneracies.
6470 The invariant expressions must each be of a form that can be used as a
6471 machine operand. We surround then with a USE rtx (a hack, but localized
6472 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6473 routine; it is the caller's responsibility to strip them.
6475 If no such canonicalization is possible (i.e., two biv's are used or an
6476 expression that is neither invariant nor a biv or giv), this routine
6477 returns 0.
6479 For a non-zero return, the result will have a code of CONST_INT, USE,
6480 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6482 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6487 static rtx
6490 rtx x;
6493 {
6498 rtx tem;
6500 /* If this is not an integer mode, or if we cannot do arithmetic in this
6501 mode, this can't be a giv. */
6508 {
6515 /* Put constant last, CONST_INT last if both constant. */
6523 /* Handle addition of zero, then addition of an invariant. */
6528 {
6531 /* Adding two invariants must result in an invariant, so enclose
6532 addition operation inside a USE and return it. */
6542 else
6551 /* biv + invar or mult + invar. Return sum. */
6555 /* (a + invar_1) + invar_2. Associate. */
6556 return
6562 arg1)),
6567 }
6569 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6570 MULT to reduce cases. */
6576 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6577 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6578 Recurse to associate the second PLUS. */
6583 return
6591 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6607 /* Handle "a - b" as "a + b * (-1)". */
6613 constm1_rtx)),
6622 /* Put constant last, CONST_INT last if both constant. */
6627 /* If second argument is not now constant, not giv. */
6631 /* Handle multiply by 0 or 1. */
6639 {
6641 /* biv * invar. Done. */
6645 /* Product of two constants. */
6649 /* invar * invar is a giv, but attempt to simplify it somehow. */
6655 {
6656 /* (invar_0 * invar_1) * invar_2. Associate. */
6663 arg1)),
6665 }
6666 /* Porpagate the MULT expressions to the intermost nodes. */
6668 {
6669 /* (invar_0 + invar_1) * invar_2. Distribute. */
6675 arg1),
6679 arg1)),
6681 }
6685 /* (a * invar_1) * invar_2. Associate. */
6691 arg1)),
6695 /* (a + invar_1) * invar_2. Distribute. */
6700 arg1),
6703 arg1)),
6708 }
6711 /* Shift by constant is multiply by power of two. */
6715 return
6724 /* "-a" is "a * (-1)" */
6730 /* "~a" is "-a - 1". Silly, but easy. */
6734 const1_rtx),
6738 /* Already in proper form for invariant. */
6744 /* Conditionally recognize extensions of simple IVs. After we've
6745 computed loop traversal counts and verified the range of the
6746 source IV, we'll reevaluate this as a GIV. */
6748 {
6751 {
6754 }
6755 }
6759 /* If this is a new register, we can't deal with it. */
6763 /* Check for biv or giv. */
6765 {
6769 {
6772 /* Form expression from giv and add benefit. Ensure this giv
6773 can derive another and subtract any needed adjustment if so. */
6775 /* Increasing the benefit here is risky. The only case in which it
6776 is arguably correct is if this is the only use of V. In other
6777 cases, this will artificially inflate the benefit of the current
6778 giv, and lead to suboptimal code. Thus, it is disabled, since
6779 potentially not reducing an only marginally beneficial giv is
6780 less harmful than reducing many givs that are not really
6781 beneficial. */
6782 {
6786 }
6799 {
6802 }
6803 else
6804 {
6807 }
6809 }
6812 do_default:
6813 /* If it isn't an induction variable, and it is invariant, we
6814 may be able to simplify things further by looking through
6815 the bits we just moved outside the loop. */
6817 {
6823 {
6824 /* Ok, we found a match. Substitute and simplify. */
6826 /* If we match another movable, we must use that, as
6827 this one is going away. */
6832 /* If consec is non-zero, this is a member of a group of
6833 instructions that were moved together. We handle this
6834 case only to the point of seeking to the last insn and
6835 looking for a REG_EQUAL. Fail if we don't find one. */
6837 {
6840 do
6841 {
6843 }
6849 }
6850 else
6851 {
6855 }
6858 {
6859 /* What we are most interested in is pointer
6860 arithmetic on invariants -- only take
6861 patterns we may be able to do something with. */
6867 {
6869 benefit);
6872 }
6877 {
6882 }
6883 }
6885 }
6886 }
6888 }
6890 /* Fall through to general case. */
6892 /* If invariant, return as USE (unless CONST_INT).
6893 Otherwise, not giv. */
6898 {
6907 }
6908 else
6910 }
6911 }
6913 /* This routine folds invariants such that there is only ever one
6914 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6916 static rtx
6919 {
6925 {
6928 }
6931 {
6934 }
6935 else
6936 {
6939 }
6940 }
6942 static rtx
6946 {
6948 {
6952 else
6955 }
6958 else
6961 }
6962 \f
6963 /* Help detect a giv that is calculated by several consecutive insns;
6964 for example,
6965 giv = biv * M
6966 giv = giv + A
6967 The caller has already identified the first insn P as having a giv as dest;
6968 we check that all other insns that set the same register follow
6969 immediately after P, that they alter nothing else,
6970 and that the result of the last is still a giv.
6972 The value is 0 if the reg set in P is not really a giv.
6973 Otherwise, the value is the amount gained by eliminating
6974 all the consecutive insns that compute the value.
6976 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6977 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6979 The coefficients of the ultimate giv value are stored in
6980 *MULT_VAL and *ADD_VAL. */
6982 static int
6987 rtx p;
6988 rtx src_reg;
6989 rtx dest_reg;
6994 {
7000 rtx temp;
7001 rtx set;
7003 /* Indicate that this is a giv so that we can update the value produced in
7004 each insn of the multi-insn sequence.
7006 This induction structure will be used only by the call to
7007 general_induction_var below, so we can allocate it on our stack.
7008 If this is a giv, our caller will replace the induct var entry with
7009 a new induction structure. */
7030 {
7034 /* If libcall, skip to end of call sequence. */
7045 /* Giv created by equivalent expression. */
7051 {
7055 count--;
7059 }
7061 {
7062 /* Allow insns that set something other than this giv to a
7063 constant. Such insns are needed on machines which cannot
7064 include long constants and should not disqualify a giv. */
7073 }
7074 }
7079 }
7080 \f
7081 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7082 represented by G1. If no such expression can be found, or it is clear that
7083 it cannot possibly be a valid address, 0 is returned.
7085 To perform the computation, we note that
7086 G1 = x * v + a and
7087 G2 = y * v + b
7088 where `v' is the biv.
7090 So G2 = (y/b) * G1 + (b - a*y/x).
7092 Note that MULT = y/x.
7094 Update: A and B are now allowed to be additive expressions such that
7095 B contains all variables in A. That is, computing B-A will not require
7096 subtracting variables. */
7098 static rtx
7101 {
7102 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7107 /* If MULT is not 1, we cannot handle A with non-constants, since we
7108 would then be required to subtract multiples of the registers in A.
7109 This is theoretically possible, and may even apply to some Fortran
7110 constructs, but it is a lot of work and we do not attempt it here. */
7115 /* In general these structures are sorted top to bottom (down the PLUS
7116 chain), but not left to right across the PLUS. If B is a higher
7117 order giv than A, we can strip one level and recurse. If A is higher
7118 order, we'll eventually bail out, but won't know that until the end.
7119 If they are the same, we'll strip one level around this loop. */
7122 {
7134 /* We matched: remove one reg completely. */
7137 /* An alternate match. */
7140 /* An alternate match. */
7142 else
7143 {
7144 /* Indicates an extra register in B. Strip one level from B and
7145 recurse, hoping B was the higher order expression. */
7150 }
7151 }
7153 /* Here we are at the last level of A, go through the cases hoping to
7154 get rid of everything but a constant. */
7157 {
7170 }
7172 {
7174 }
7176 {
7181 }
7183 {
7188 else
7190 }
7195 }
7197 rtx
7200 {
7203 /* The value that G1 will be multiplied by must be a constant integer. Also,
7204 the only chance we have of getting a valid address is if b*c/a (see above
7205 for notation) is also an integer. */
7208 {
7213 }
7216 else
7217 {
7218 /* ??? Find out if the one is a multiple of the other? */
7220 }
7224 {
7225 /* Failed. If we've got a multiplication factor between G1 and G2,
7226 scale G1's addend and try again. */
7228 {
7232 {
7233 HOST_WIDE_INT m;
7237 }
7238 else
7239 {
7241 mult);
7242 }
7245 }
7246 }
7250 /* Form simplified final result. */
7255 else
7260 else
7261 {
7264 {
7268 }
7271 }
7272 }
7273 \f
7274 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7275 represented by G1. This indicates that G2 should be combined with G1 and
7276 that G2 can use (either directly or via an address expression) a register
7277 used to represent G1. */
7279 static rtx
7282 {
7285 /* With the introduction of ext dependent givs, we must care for modes.
7286 G2 must not use a wider mode than G1. */
7296 /* If these givs are identical, they can be combined. We use the results
7297 of express_from because the addends are not in a canonical form, so
7298 rtx_equal_p is a weaker test. */
7299 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7300 combination to be the other way round. */
7303 {
7305 }
7307 /* If G2 can be expressed as a function of G1 and that function is valid
7308 as an address and no more expensive than using a register for G2,
7309 the expression of G2 in terms of G1 can be used. */
7313 /* ??? Looses, especially with -fforce-addr, where *g2->location
7314 will always be a register, and so anything more complicated
7315 gets discarded. */
7316 #if 0
7317 #ifdef ADDRESS_COST
7319 #else
7321 #endif
7322 #endif
7323 )
7324 {
7326 }
7329 }
7330 \f
7331 /* Check each extension dependent giv in this class to see if its
7332 root biv is safe from wrapping in the interior mode, which would
7333 make the giv illegal. */
7335 static void
7339 {
7342 HOST_WIDE_INT start_val;
7348 /* Make sure the iteration data is available. We must have
7349 constants in order to be certain of no overflow. */
7350 /* ??? An unknown iteration count with an increment of +-1
7351 combined with friendly exit tests of against an invariant
7352 value is also ameanable to optimization. Not implemented. */
7358 /* Make sure the host can represent the arithmetic. */
7360 {
7362 HOST_WIDE_INT s_end_val;
7374 /* Check for host arithmatic overflow. */
7376 {
7378 HOST_WIDE_INT s_max;
7385 /* Check zero extension of biv ok. */
7387 /* Check for host arithmatic overflow. */
7388 && (neg_incr
7391 /* Check for target arithmetic overflow. */
7392 && (neg_incr
7395 {
7397 }
7399 /* Check sign extension of biv ok. */
7400 /* ??? While it is true that overflow with signed and pointer
7401 arithmetic is undefined, I fear too many programmers don't
7402 keep this fact in mind -- myself included on occasion.
7403 So leave alone with the signed overflow optimizations. */
7405 /* Check for host arithmatic overflow. */
7406 && (neg_incr
7409 /* Check for target arithmetic overflow. */
7410 && (neg_incr
7413 {
7415 }
7416 }
7417 }
7419 /* Invalidate givs that fail the tests. */
7422 {
7427 {
7436 /* We don't know whether this value is being used as either
7437 signed or unsigned, so to safely truncate we must satisfy
7438 both. The initial check here verifies the BIV itself;
7439 once that is successful we may check its range wrt the
7440 derived GIV. */
7442 {
7446 /* We know from the above that both endpoints are nonnegative,
7447 and that there is no wrapping. Verify that both endpoints
7448 are within the (signed) range of the outer mode. */
7451 }
7456 }
7459 {
7461 {
7465 }
7466 }
7467 else
7468 {
7470 {
7475 else
7476 {
7481 else
7483 }
7488 }
7491 }
7492 }
7493 }
7495 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7497 rtx
7500 rtx value;
7501 {
7507 /* Recall that check_ext_dependent_givs verified that the known bounds
7508 of a biv did not overflow or wrap with respect to the extension for
7509 the giv. Therefore, constants need no additional adjustment. */
7513 /* Otherwise, we must adjust the value to compensate for the
7514 differing modes of the biv and the giv. */
7516 }
7517 \f
7518 struct combine_givs_stats
7519 {
7522 };
7524 static int
7528 {
7535 /* Stabilize the sort. */
7539 }
7541 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7542 any other. If so, point SAME to the giv combined with and set NEW_REG to
7543 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7544 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7546 static void
7550 {
7551 /* Additional benefit to add for being combined multiple times. */
7559 /* Count givs, because bl->giv_count is incorrect here. */
7563 giv_count++;
7565 giv_array
7576 {
7578 rtx single_use;
7583 /* If a DEST_REG GIV is used only once, do not allow it to combine
7584 with anything, for in doing so we will gain nothing that cannot
7585 be had by simply letting the GIV with which we would have combined
7586 to be reduced on its own. The losage shows up in particular with
7587 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7588 be seen elsewhere as well. */
7595 /* Add an additional weight for zero addends. */
7600 {
7601 rtx this_combine;
7606 {
7609 }
7610 }
7612 }
7614 /* Iterate, combining until we can't. */
7615 restart:
7619 {
7622 {
7628 }
7630 }
7633 {
7639 /* If it has already been combined, skip. */
7644 {
7647 /* If it has already been combined, skip. */
7649 {
7654 /* For destination, we now may replace by mem expression instead
7655 of register. This changes the costs considerably, so add the
7656 compensation. */
7666 /* ??? The new final_[bg]iv_value code does a much better job
7667 of finding replaceable giv's, and hence this code may no
7668 longer be necessary. */
7672 /* To help optimize the next set of combinations, remove
7673 this giv from the benefits of other potential mates. */
7675 {
7679 }
7686 }
7687 }
7689 /* To help optimize the next set of combinations, remove
7690 this giv from the benefits of other potential mates. */
7692 {
7694 {
7698 }
7702 /* We've finished with this giv, and everything it touched.
7703 Restart the combination so that proper weights for the
7704 rest of the givs are properly taken into account. */
7705 /* ??? Ideally we would compact the arrays at this point, so
7706 as to not cover old ground. But sanely compacting
7707 can_combine is tricky. */
7709 }
7710 }
7712 /* Clean up. */
7715 }
7716 \f
7717 /* Generate sequence for REG = B * M + A. */
7719 static rtx
7725 {
7726 rtx seq;
7727 rtx result;
7730 /* Use unsigned arithmetic. */
7738 }
7741 /* Update registers created in insn sequence SEQ. */
7743 static void
7746 rtx seq;
7747 {
7748 rtx insn;
7750 /* Update register info for alias analysis. */
7756 {
7759 {
7766 }
7767 }
7771 }
7774 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7776 void
7783 basic_block before_bb;
7784 rtx before_insn;
7785 {
7786 rtx seq;
7789 {
7792 }
7794 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7797 /* Increase the lifetime of any invariants moved further in code. */
7804 /* It is possible that the expansion created lots of new registers.
7805 Iterate over the sequence we just created and record them all. */
7807 }
7810 /* Emit insns in loop pre-header to set REG = B * M + A. */
7812 void
7819 {
7820 rtx seq;
7822 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7825 /* Increase the lifetime of any invariants moved further in code.
7826 ???? Is this really necessary? */
7833 /* It is possible that the expansion created lots of new registers.
7834 Iterate over the sequence we just created and record them all. */
7836 }
7839 /* Emit insns after loop to set REG = B * M + A. */
7841 void
7848 {
7849 rtx seq;
7851 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7856 /* It is possible that the expansion created lots of new registers.
7857 Iterate over the sequence we just created and record them all. */
7859 }
7863 /* Similar to gen_add_mult, but compute cost rather than generating
7864 sequence. */
7866 static int
7872 {
7882 {
7887 }
7890 }
7891 \f
7892 /* Test whether A * B can be computed without
7893 an actual multiply insn. Value is 1 if so.
7895 ??? This function stinks because it generates a ton of wasted RTL
7896 ??? and as a result fragments GC memory to no end. There are other
7897 ??? places in the compiler which are invoked a lot and do the same
7898 ??? thing, generate wasted RTL just to see if something is possible. */
7900 static int
7902 rtx a;
7903 rtx b;
7904 {
7905 rtx tmp;
7908 /* If only one is constant, make it B. */
7912 /* If first constant, both constant, so don't need multiply. */
7916 /* If second not constant, neither is constant, so would need multiply. */
7920 /* One operand is constant, so might not need multiply insn. Generate the
7921 code for the multiply and see if a call or multiply, or long sequence
7922 of insns is generated. */
7931 {
7934 {
7944 {
7947 }
7950 }
7951 }
7961 }
7962 \f
7963 /* Check to see if loop can be terminated by a "decrement and branch until
7964 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7965 Also try reversing an increment loop to a decrement loop
7966 to see if the optimization can be performed.
7967 Value is nonzero if optimization was performed. */
7969 /* This is useful even if the architecture doesn't have such an insn,
7970 because it might change a loops which increments from 0 to n to a loop
7971 which decrements from n to 0. A loop that decrements to zero is usually
7972 faster than one that increments from zero. */
7974 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7975 such as approx_final_value, biv_total_increment, loop_iterations, and
7976 final_[bg]iv_value. */
7978 static int
7982 {
7987 rtx reg;
7988 rtx jump_label;
7989 rtx final_value;
7990 rtx start_value;
7991 rtx new_add_val;
7992 rtx comparison;
7993 rtx before_comparison;
7994 rtx p;
7995 rtx jump;
7996 rtx first_compare;
8001 /* If last insn is a conditional branch, and the insn before tests a
8002 register value, try to optimize it. Otherwise, we can't do anything. */
8011 /* Try to compute whether the compare/branch at the loop end is one or
8012 two instructions. */
8018 else
8021 {
8022 /* If more than one condition is present to control the loop, then
8023 do not proceed, as this function does not know how to rewrite
8024 loop tests with more than one condition.
8026 Look backwards from the first insn in the last comparison
8027 sequence and see if we've got another comparison sequence. */
8029 rtx jump1;
8033 }
8035 /* Check all of the bivs to see if the compare uses one of them.
8036 Skip biv's set more than once because we can't guarantee that
8037 it will be zero on the last iteration. Also skip if the biv is
8038 used between its update and the test insn. */
8041 {
8046 first_compare))
8048 }
8053 /* Look for the case where the basic induction variable is always
8054 nonnegative, and equals zero on the last iteration.
8055 In this case, add a reg_note REG_NONNEG, which allows the
8056 m68k DBRA instruction to be used. */
8064 {
8065 /* Initial value must be greater than 0,
8066 init_val % -dec_value == 0 to ensure that it equals zero on
8067 the last iteration */
8073 {
8074 /* register always nonnegative, add REG_NOTE to branch */
8082 }
8084 /* If the decrement is 1 and the value was tested as >= 0 before
8085 the loop, then we can safely optimize. */
8087 {
8100 {
8108 }
8109 }
8110 }
8113 {
8114 /* Try to change inc to dec, so can apply above optimization. */
8115 /* Can do this if:
8116 all registers modified are induction variables or invariant,
8117 all memory references have non-overlapping addresses
8118 (obviously true if only one write)
8119 allow 2 insns for the compare/jump at the end of the loop. */
8120 /* Also, we must avoid any instructions which use both the reversed
8121 biv and another biv. Such instructions will fail if the loop is
8122 reversed. We meet this condition by requiring that either
8123 no_use_except_counting is true, or else that there is only
8124 one biv. */
8126 /* 1 if the iteration var is used only to count iterations. */
8128 /* 1 if the loop has no memory store, or it has a single memory store
8129 which is reversible. */
8135 {
8139 /* If there are no givs for this biv, and the only exit is the
8140 fall through at the end of the loop, then
8141 see if perhaps there are no uses except to count. */
8145 {
8150 /* An insn that sets the biv is okay. */
8151 ;
8155 {
8156 /* If either of these insns uses the biv and sets a pseudo
8157 that has more than one usage, then the biv has uses
8158 other than counting since it's used to derive a value
8159 that is used more than one time. */
8161 regs);
8163 {
8166 }
8167 }
8169 {
8172 }
8173 }
8175 /* A biv has uses besides counting if it is used to set
8176 another biv. */
8180 {
8183 }
8184 }
8187 /* No need to worry about MEMs. */
8188 ;
8190 {
8195 /* If the loop has a single store, and the destination address is
8196 invariant, then we can't reverse the loop, because this address
8197 might then have the wrong value at loop exit.
8198 This would work if the source was invariant also, however, in that
8199 case, the insn should have been moved out of the loop. */
8202 {
8205 /* If we could prove that each of the memory locations
8206 written to was different, then we could reverse the
8207 store -- but we don't presently have any way of
8208 knowing that. */
8211 /* If the store depends on a register that is set after the
8212 store, it depends on the initial value, and is thus not
8213 reversible. */
8215 {
8222 }
8223 }
8224 }
8225 else
8228 /* This code only acts for innermost loops. Also it simplifies
8229 the memory address check by only reversing loops with
8230 zero or one memory access.
8231 Two memory accesses could involve parts of the same array,
8232 and that can't be reversed.
8233 If the biv is used only for counting, than we don't need to worry
8234 about all these things. */
8240 && reversible_mem_store
8245 {
8246 rtx tem;
8248 /* Loop can be reversed. */
8252 /* Now check other conditions:
8254 The increment must be a constant, as must the initial value,
8255 and the comparison code must be LT.
8257 This test can probably be improved since +/- 1 in the constant
8258 can be obtained by changing LT to LE and vice versa; this is
8259 confusing. */
8262 /* for constants, LE gets turned into LT */
8266 {
8277 comparison_const_width
8279 else
8280 comparison_const_width
8284 comparison_sign_mask
8287 /* If the comparison value is not a loop invariant, then we
8288 can not reverse this loop.
8290 ??? If the insns which initialize the comparison value as
8291 a whole compute an invariant result, then we could move
8292 them out of the loop and proceed with loop reversal. */
8300 /* Normalize the initial value if it is an integer and
8301 has no other use except as a counter. This will allow
8302 a few more loops to be reversed. */
8306 {
8308 /* The code below requires comparison_val to be a multiple
8309 of add_val in order to do the loop reversal, so
8310 round up comparison_val to a multiple of add_val.
8311 Since comparison_value is constant, we know that the
8312 current comparison code is LT. */
8314 comparison_val
8316 /* We postpone overflow checks for COMPARISON_VAL here;
8317 even if there is an overflow, we might still be able to
8318 reverse the loop, if converting the loop exit test to
8319 NE is possible. */
8321 }
8323 /* First check if we can do a vanilla loop reversal. */
8325 /* If we have a decrement_and_branch_on_count,
8326 prefer the NE test, since this will allow that
8327 instruction to be generated. Note that we must
8328 use a vanilla loop reversal if the biv is used to
8329 calculate a giv or has a non-counting use. */
8330 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8331 && defined (HAVE_decrement_and_branch_on_count)
8335 #endif
8337 /* Now do postponed overflow checks on COMPARISON_VAL. */
8340 {
8341 /* Register will always be nonnegative, with value
8342 0 on last iteration */
8346 }
8350 {
8353 }
8354 else
8360 /* If the initial value is not zero, or if the comparison
8361 value is not an exact multiple of the increment, then we
8362 can not reverse this loop. */
8365 {
8368 }
8369 else
8370 {
8373 }
8377 /* Reset these in case we normalized the initial value
8378 and comparison value above. */
8381 {
8383 final_value
8385 }
8388 /* Save some info needed to produce the new insns. */
8393 /* Set start_value; if this is not a CONST_INT, we need
8394 to generate a SUB.
8395 Initialize biv to start_value before loop start.
8396 The old initializing insn will be deleted as a
8397 dead store by flow.c. */
8400 {
8403 }
8405 {
8413 start_value
8419 }
8421 {
8424 initial_value);
8428 start_value
8431 }
8432 else
8433 /* We could handle the other cases too, but it'll be
8434 better to have a testcase first. */
8437 /* We may not have a single insn which can increment a reg, so
8438 create a sequence to hold all the insns from expand_inc. */
8447 /* Update biv info to reflect its new status. */
8452 /* Update loop info. */
8461 /* Inc LABEL_NUSES so that delete_insn will
8462 not delete the label. */
8465 /* Emit an insn after the end of the loop to set the biv's
8466 proper exit value if it is used anywhere outside the loop. */
8472 /* Delete compare/branch at end of loop. */
8477 /* Add new compare/branch insn at end of loop. */
8489 ;
8495 {
8497 {
8498 /* Increment of LABEL_NUSES done above. */
8499 /* Register is now always nonnegative,
8500 so add REG_NONNEG note to the branch. */
8503 }
8505 }
8507 /* No insn may reference both the reversed and another biv or it
8508 will fail (see comment near the top of the loop reversal
8509 code).
8510 Earlier on, we have verified that the biv has no use except
8511 counting, or it is the only biv in this function.
8512 However, the code that computes no_use_except_counting does
8513 not verify reg notes. It's possible to have an insn that
8514 references another biv, and has a REG_EQUAL note with an
8515 expression based on the reversed biv. To avoid this case,
8516 remove all REG_EQUAL notes based on the reversed biv
8517 here. */
8520 {
8523 /* If this is a set of a GIV based on the reversed biv, any
8524 REG_EQUAL notes should still be correct. */
8531 {
8536 else
8538 }
8539 }
8541 /* Mark that this biv has been reversed. Each giv which depends
8542 on this biv, and which is also live past the end of the loop
8543 will have to be fixed up. */
8548 {
8552 else
8554 }
8557 }
8558 }
8559 }
8562 }
8563 \f
8564 /* Verify whether the biv BL appears to be eliminable,
8565 based on the insns in the loop that refer to it.
8567 If ELIMINATE_P is non-zero, actually do the elimination.
8569 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8570 determine whether invariant insns should be placed inside or at the
8571 start of the loop. */
8573 static int
8579 {
8582 rtx p;
8584 /* Scan all insns in the loop, stopping if we find one that uses the
8585 biv in a way that we cannot eliminate. */
8588 {
8593 /* If this is a libcall that sets a giv, skip ahead to its end. */
8595 {
8599 {
8604 {
8611 }
8612 }
8613 }
8618 {
8624 }
8625 }
8628 {
8633 }
8636 }
8637 \f
8638 /* INSN and REFERENCE are instructions in the same insn chain.
8639 Return non-zero if INSN is first. */
8641 int
8644 {
8648 {
8649 /* Start with test for not first so that INSN == REFERENCE yields not
8650 first. */
8656 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8657 previous insn, hence the <= comparison below does not work if
8658 P is a note. */
8669 }
8670 }
8672 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8673 the offset that we have to take into account due to auto-increment /
8674 div derivation is zero. */
8675 static int
8678 rtx insn;
8679 {
8680 /* If the giv V had the auto-inc address optimization applied
8681 to it, and INSN occurs between the giv insn and the biv
8682 insn, then we'd have to adjust the value used here.
8683 This is rare, so we don't bother to make this possible. */
8692 }
8694 /* If BL appears in X (part of the pattern of INSN), see if we can
8695 eliminate its use. If so, return 1. If not, return 0.
8697 If BIV does not appear in X, return 1.
8699 If ELIMINATE_P is non-zero, actually do the elimination.
8700 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8701 Depending on how many items have been moved out of the loop, it
8702 will either be before INSN (when WHERE_INSN is non-zero) or at the
8703 start of the loop (when WHERE_INSN is zero). */
8705 static int
8711 basic_block where_bb;
8712 rtx where_insn;
8713 {
8719 #ifdef HAVE_cc0
8721 #endif
8727 {
8729 /* If we haven't already been able to do something with this BIV,
8730 we can't eliminate it. */
8736 /* If this sets the BIV, it is not a problem. */
8740 /* If this is an insn that defines a giv, it is also ok because
8741 it will go away when the giv is reduced. */
8746 #ifdef HAVE_cc0
8748 {
8749 /* Can replace with any giv that was reduced and
8750 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8751 Require a constant for MULT_VAL, so we know it's nonzero.
8752 ??? We disable this optimization to avoid potential
8753 overflows. */
8761 {
8768 /* If the giv has the opposite direction of change,
8769 then reverse the comparison. */
8773 else
8776 /* We can probably test that giv's reduced reg. */
8779 }
8781 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8782 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8783 Require a constant for MULT_VAL, so we know it's nonzero.
8784 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8785 overflow problem. */
8797 {
8804 /* If the giv has the opposite direction of change,
8805 then reverse the comparison. */
8809 else
8813 /* Replace biv with the giv's reduced register. */
8818 /* Insn doesn't support that constant or invariant. Copy it
8819 into a register (it will be a loop invariant.) */
8826 /* Substitute the new register for its invariant value in
8827 the compare expression. */
8831 }
8832 }
8833 #endif
8840 /* See if either argument is the biv. */
8845 else
8849 {
8850 /* First try to replace with any giv that has constant positive
8851 mult_val and constant add_val. We might be able to support
8852 negative mult_val, but it seems complex to do it in general. */
8864 {
8868 /* Don't eliminate if the linear combination that makes up
8869 the giv overflows when it is applied to ARG. */
8871 {
8872 rtx add_val;
8876 else
8882 }
8887 /* Replace biv with the giv's reduced reg. */
8890 /* If all constants are actually constant integers and
8891 the derived constant can be directly placed in the COMPARE,
8892 do so. */
8895 {
8898 }
8899 else
8900 {
8901 /* Otherwise, load it into a register. */
8906 }
8912 }
8914 /* Look for giv with positive constant mult_val and nonconst add_val.
8915 Insert insns to calculate new compare value.
8916 ??? Turn this off due to possible overflow. */
8924 {
8925 rtx tem;
8935 /* Replace biv with giv's reduced register. */
8939 /* Compute value to compare against. */
8943 /* Use it in this insn. */
8947 }
8948 }
8950 {
8952 {
8953 /* Look for giv with constant positive mult_val and nonconst
8954 add_val. Insert insns to compute new compare value.
8955 ??? Turn this off due to possible overflow. */
8962 {
8963 rtx tem;
8973 /* Replace biv with giv's reduced register. */
8977 /* Compute value to compare against. */
8984 }
8985 }
8987 /* This code has problems. Basically, you can't know when
8988 seeing if we will eliminate BL, whether a particular giv
8989 of ARG will be reduced. If it isn't going to be reduced,
8990 we can't eliminate BL. We can try forcing it to be reduced,
8991 but that can generate poor code.
8993 The problem is that the benefit of reducing TV, below should
8994 be increased if BL can actually be eliminated, but this means
8995 we might have to do a topological sort of the order in which
8996 we try to process biv. It doesn't seem worthwhile to do
8997 this sort of thing now. */
8999 #if 0
9000 /* Otherwise the reg compared with had better be a biv. */
9005 /* Look for a pair of givs, one for each biv,
9006 with identical coefficients. */
9008 {
9020 {
9027 /* Replace biv with its giv's reduced reg. */
9029 /* Replace other operand with the other giv's
9030 reduced reg. */
9033 }
9034 }
9035 #endif
9036 }
9038 /* If we get here, the biv can't be eliminated. */
9042 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9043 biv is used in it, since it will be replaced. */
9051 }
9053 /* See if any subexpression fails elimination. */
9056 {
9058 {
9071 }
9072 }
9075 }
9076 \f
9077 /* Return nonzero if the last use of REG
9078 is in an insn following INSN in the same basic block. */
9080 static int
9082 rtx reg;
9083 rtx insn;
9084 {
9085 rtx n;
9089 {
9092 }
9094 }
9095 \f
9096 /* Called via `note_stores' to record the initial value of a biv. Here we
9097 just record the location of the set and process it later. */
9099 static void
9101 rtx dest;
9102 rtx set;
9104 {
9115 /* If this is the first set found, record it. */
9117 {
9120 }
9121 }
9122 \f
9123 /* If any of the registers in X are "old" and currently have a last use earlier
9124 than INSN, update them to have a last use of INSN. Their actual last use
9125 will be the previous insn but it will not have a valid uid_luid so we can't
9126 use it. X must be a source expression only. */
9128 static void
9130 rtx x;
9131 rtx insn;
9132 {
9133 /* Check for the case where INSN does not have a valid luid. In this case,
9134 there is no need to modify the regno_last_uid, as this can only happen
9135 when code is inserted after the loop_end to set a pseudo's final value,
9136 and hence this insn will never be the last use of x.
9137 ???? This comment is not correct. See for example loop_givs_reduce.
9138 This may insert an insn before another new insn. */
9142 {
9144 }
9145 else
9146 {
9150 {
9156 }
9157 }
9158 }
9159 \f
9160 /* Given an insn INSN and condition COND, return the condition in a
9161 canonical form to simplify testing by callers. Specifically:
9163 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9164 (2) Both operands will be machine operands; (cc0) will have been replaced.
9165 (3) If an operand is a constant, it will be the second operand.
9166 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9167 for GE, GEU, and LEU.
9169 If the condition cannot be understood, or is an inequality floating-point
9170 comparison which needs to be reversed, 0 will be returned.
9172 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9174 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9175 insn used in locating the condition was found. If a replacement test
9176 of the condition is desired, it should be placed in front of that
9177 insn and we will be sure that the inputs are still valid.
9179 If WANT_REG is non-zero, we wish the condition to be relative to that
9180 register, if possible. Therefore, do not canonicalize the condition
9181 further. */
9183 rtx
9185 rtx insn;
9186 rtx cond;
9189 rtx want_reg;
9190 {
9193 rtx set;
9194 rtx tem;
9212 /* If we are comparing a register with zero, see if the register is set
9213 in the previous insn to a COMPARE or a comparison operation. Perform
9214 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9215 in cse.c */
9220 {
9221 /* Set non-zero when we find something of interest. */
9224 #ifdef HAVE_cc0
9225 /* If comparison with cc0, import actual comparison from compare
9226 insn. */
9228 {
9239 }
9240 #endif
9242 /* If this is a COMPARE, pick up the two things being compared. */
9244 {
9248 }
9252 /* Go back to the previous insn. Stop if it is not an INSN. We also
9253 stop if it isn't a single set or if it has a REG_INC note because
9254 we don't want to bother dealing with it. */
9268 /* If this is setting OP0, get what it sets it to if it looks
9269 relevant. */
9271 {
9274 /* ??? We may not combine comparisons done in a CCmode with
9275 comparisons not done in a CCmode. This is to aid targets
9276 like Alpha that have an IEEE compliant EQ instruction, and
9277 a non-IEEE compliant BEQ instruction. The use of CCmode is
9278 actually artificial, simply to prevent the combination, but
9279 should not affect other platforms.
9281 However, we must allow VOIDmode comparisons to match either
9282 CCmode or non-CCmode comparison, because some ports have
9283 modeless comparisons inside branch patterns.
9285 ??? This mode check should perhaps look more like the mode check
9286 in simplify_comparison in combine. */
9294 && (STORE_FLAG_VALUE
9297 #ifdef FLOAT_STORE_FLAG_VALUE
9300 && (REAL_VALUE_NEGATIVE
9302 #endif
9303 ))
9314 && (STORE_FLAG_VALUE
9317 #ifdef FLOAT_STORE_FLAG_VALUE
9320 && (REAL_VALUE_NEGATIVE
9322 #endif
9323 ))
9329 {
9332 }
9333 else
9335 }
9338 /* If this sets OP0, but not directly, we have to give up. */
9342 {
9346 {
9351 }
9356 }
9357 }
9359 /* If constant is first, put it last. */
9363 /* If OP0 is the result of a comparison, we weren't able to find what
9364 was really being compared, so fail. */
9368 /* Canonicalize any ordered comparison with integers involving equality
9369 if we can do computations in the relevant mode and we do not
9370 overflow. */
9375 {
9378 unsigned HOST_WIDE_INT max_val
9382 {
9388 /* When cross-compiling, const_val might be sign-extended from
9389 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9409 }
9410 }
9412 #ifdef HAVE_cc0
9413 /* Never return CC0; return zero instead. */
9416 #endif
9419 }
9421 /* Given a jump insn JUMP, return the condition that will cause it to branch
9422 to its JUMP_LABEL. If the condition cannot be understood, or is an
9423 inequality floating-point comparison which needs to be reversed, 0 will
9424 be returned.
9426 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9427 insn used in locating the condition was found. If a replacement test
9428 of the condition is desired, it should be placed in front of that
9429 insn and we will be sure that the inputs are still valid. */
9431 rtx
9433 rtx jump;
9435 {
9436 rtx cond;
9438 rtx set;
9440 /* If this is not a standard conditional jump, we can't parse it. */
9448 /* If this branches to JUMP_LABEL when the condition is false, reverse
9449 the condition. */
9450 reverse
9455 }
9457 /* Similar to above routine, except that we also put an invariant last
9458 unless both operands are invariants. */
9460 rtx
9463 rtx x;
9464 {
9474 }
9476 /* Scan the function and determine whether it has indirect (computed) jumps.
9478 This is taken mostly from flow.c; similar code exists elsewhere
9479 in the compiler. It may be useful to put this into rtlanal.c. */
9480 static int
9482 rtx start;
9483 {
9484 rtx insn;
9491 }
9493 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9494 documentation for LOOP_MEMS for the definition of `appropriate'.
9495 This function is called from prescan_loop via for_each_rtx. */
9497 static int
9501 {
9510 {
9515 /* We're not interested in MEMs that are only clobbered. */
9519 /* We're not interested in the MEM associated with a
9520 CONST_DOUBLE, so there's no need to traverse into this. */
9524 /* We're not interested in any MEMs that only appear in notes. */
9528 /* This is not a MEM. */
9530 }
9532 /* See if we've already seen this MEM. */
9535 {
9537 /* The modes of the two memory accesses are different. If
9538 this happens, something tricky is going on, and we just
9539 don't optimize accesses to this MEM. */
9543 }
9545 /* Resize the array, if necessary. */
9547 {
9550 else
9556 }
9558 /* Actually insert the MEM. */
9560 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9561 because we can't put it in a register. We still store it in the
9562 table, though, so that if we see the same address later, but in a
9563 non-BLK mode, we'll not think we can optimize it at that point. */
9569 }
9572 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9574 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9575 register that is modified by an insn between FROM and TO. If the
9576 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9577 more, stop incrementing it, to avoid overflow.
9579 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9580 register I is used, if it is only used once. Otherwise, it is set
9581 to 0 (for no uses) or const0_rtx for more than one use. This
9582 parameter may be zero, in which case this processing is not done.
9584 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9585 optimize register I. */
9587 static void
9591 {
9594 /* last_set[n] is nonzero iff reg n has been set in the current
9595 basic block. In that case, it is the insn that last set reg n. */
9597 rtx insn;
9603 /* Grow the regs array if not allocated or too small. */
9605 {
9611 /* Zero the new elements. */
9614 }
9616 /* Clear previously scanned fields but do not clear n_times_set. */
9618 {
9622 }
9626 /* Scan the loop, recording register usage. */
9629 {
9631 {
9632 /* Record registers that have exactly one use. */
9635 /* Include uses in REG_EQUAL notes. */
9643 {
9647 last_set);
9648 }
9649 }
9653 }
9655 /* Invalidate all hard registers clobbered by calls. With one exception:
9656 a call-clobbered PIC register is still function-invariant for our
9657 purposes, since we can hoist any PIC calculations out of the loop.
9658 Thus the call to rtx_varies_p. */
9663 {
9666 }
9668 #ifdef AVOID_CCMODE_COPIES
9669 /* Don't try to move insns which set CC registers if we should not
9670 create CCmode register copies. */
9674 #endif
9676 /* Set regs->array[I].n_times_set for the new registers. */
9681 }
9683 /* Returns the number of real INSNs in the LOOP. */
9685 static int
9688 {
9690 rtx insn;
9698 }
9700 /* Move MEMs into registers for the duration of the loop. */
9702 static void
9705 {
9712 rtx end_label;
9713 /* Nonzero if the next instruction may never be executed. */
9720 /* We cannot use next_label here because it skips over normal insns. */
9725 /* Check to see if it's possible that some instructions in the loop are
9726 never executed. Also check if there is a goto out of the loop other
9727 than right after the end of the loop. */
9731 {
9735 /* If we enter the loop in the middle, and scan
9736 around to the beginning, don't set maybe_never
9737 for that. This must be an unconditional jump,
9738 otherwise the code at the top of the loop might
9739 never be executed. Unconditional jumps are
9740 followed a by barrier then loop end. */
9745 {
9746 /* If this is a jump outside of the loop but not right
9747 after the end of the loop, we would have to emit new fixup
9748 sequences for each such label. */
9750 JUMP_INSN is executed, we must be conservative. */
9759 /* Something complicated. */
9761 else
9762 /* If there are any more instructions in the loop, they
9763 might not be reached. */
9765 }
9768 }
9770 /* Find start of the extended basic block that enters the loop. */
9774 ;
9779 /* Build table of mems that get set to constant values before the
9780 loop. */
9784 /* Actually move the MEMs. */
9786 {
9787 regset_head load_copies;
9788 regset_head store_copies;
9790 rtx reg;
9792 rtx mem_list_entry;
9796 /* There's no telling whether or not MEM is modified. */
9799 /* Go through the MEMs written to in the loop to see if this
9800 one is aliased by one of them. */
9803 {
9808 {
9809 /* MEM is indeed aliased by this store. */
9812 }
9814 }
9820 /* If this MEM is written to, we must be sure that there
9821 are no reads from another MEM that aliases this one. */
9823 {
9827 {
9831 VOIDmode,
9833 rtx_varies_p))
9834 {
9835 /* It's not safe to hoist loop_info->mems[i] out of
9836 the loop because writes to it might not be
9837 seen by reads from loop_info->mems[j]. */
9840 }
9841 }
9842 }
9845 /* We can't access the MEM outside the loop; it might
9846 cause a trap that wouldn't have happened otherwise. */
9850 /* We thought we were going to lift this MEM out of the
9851 loop, but later discovered that we could not. */
9857 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9858 order to keep scan_loop from moving stores to this MEM
9859 out of the loop just because this REG is neither a
9860 user-variable nor used in the loop test. */
9865 /* Now, replace all references to the MEM with the
9866 corresponding pseudos. */
9871 {
9873 {
9874 rtx set;
9878 /* See if this copies the mem into a register that isn't
9879 modified afterwards. We'll try to do copy propagation
9880 a little further on. */
9882 /* @@@ This test is _way_ too conservative. */
9883 && ! maybe_never
9891 /* See if this copies the mem from a register that isn't
9892 modified afterwards. We'll try to remove the
9893 redundant copy later on by doing a little register
9894 renaming and copy propagation. This will help
9895 to untangle things for the BIV detection code. */
9897 && ! maybe_never
9905 /* If this is a call which uses / clobbers this memory
9906 location, we must not change the interface here. */
9910 {
9914 }
9915 else
9916 /* Replace the memory reference with the shadow register. */
9919 }
9924 }
9929 /* We couldn't replace all occurrences of the MEM. */
9931 else
9932 {
9933 /* Load the memory immediately before LOOP->START, which is
9934 the NOTE_LOOP_BEG. */
9936 rtx set;
9942 {
9946 {
9950 /* Extending hard register lifetimes causes crash
9951 on SRC targets. Doing so on non-SRC is
9952 probably also not good idea, since we most
9953 probably have pseudoregister equivalence as
9954 well. */
9957 }
9958 /* Use the constant equivalence if that is cheap enough. */
9964 {
9967 }
9969 /* If best_equiv is nonzero, we know that MEM is set to a
9970 constant or register before the loop. We will use this
9971 knowledge to initialize the shadow register with that
9972 constant or reg rather than by loading from MEM. */
9975 }
9980 {
9983 {
9986 }
9987 }
9993 {
9995 {
9998 }
10000 /* Store the memory immediately after END, which is
10001 the NOTE_LOOP_END. */
10004 }
10007 {
10012 }
10014 /* Attempt a bit of copy propagation. This helps untangle the
10015 data flow, and enables {basic,general}_induction_var to find
10016 more bivs/givs. */
10017 EXECUTE_IF_SET_IN_REG_SET
10019 {
10021 });
10024 EXECUTE_IF_SET_IN_REG_SET
10026 {
10028 });
10030 }
10031 }
10034 {
10035 /* Now, we need to replace all references to the previous exit
10036 label with the new one. */
10037 rtx_pair rr;
10042 {
10045 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10046 field. This is not handled by for_each_rtx because it doesn't
10047 handle unprinted ('0') fields. We need to update JUMP_LABEL
10048 because the immediately following unroll pass will use it.
10049 replace_label would not work anyways, because that only handles
10050 LABEL_REFs. */
10053 }
10054 }
10057 }
10059 /* For communication between note_reg_stored and its caller. */
10060 struct note_reg_stored_arg
10061 {
10063 rtx reg;
10064 };
10066 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10067 is equal to ARG. */
10068 static void
10072 {
10076 }
10078 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10079 There must be exactly one insn that sets this pseudo; it will be
10080 deleted if all replacements succeed and we can prove that the register
10081 is not used after the loop. */
10083 static void
10086 rtx replacement;
10088 {
10089 /* This is the reg that we are copying from. */
10092 rtx insn;
10093 /* These help keep track of whether we replaced all uses of the reg. */
10100 {
10101 rtx set;
10103 /* Only substitute within one extended basic block from the initializing
10104 insn. */
10111 /* Is this the initializing insn? */
10116 {
10123 }
10125 /* Only substitute after seeing the initializing insn. */
10127 {
10134 /* Stop replacing when REPLACEMENT is modified. */
10139 {
10142 /* It is possible that we've turned previously valid REG_EQUAL to
10143 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10144 REPLACEMENT is modified, we get different meaning. */
10148 }
10149 }
10150 }
10154 {
10158 {
10159 rtx first;
10160 rtx retval_note;
10162 /* Assume we're just deleting INIT_INSN. */
10164 /* Look for REG_RETVAL note. If we're deleting the end of
10165 the libcall sequence, the whole sequence can go. */
10167 /* If we found a REG_RETVAL note, find the first instruction
10168 in the sequence. */
10172 /* Delete the instructions. */
10174 }
10177 }
10178 }
10180 /* Replace all the instructions from FIRST up to and including LAST
10181 with NOTE_INSN_DELETED notes. */
10183 static void
10185 rtx first;
10186 rtx last;
10187 {
10189 {
10195 /* If this was the LAST instructions we're supposed to delete,
10196 we're done. */
10201 }
10202 }
10204 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10205 loop LOOP if the order of the sets of these registers can be
10206 swapped. There must be exactly one insn within the loop that sets
10207 this pseudo followed immediately by a move insn that sets
10208 REPLACEMENT with REGNO. */
10209 static void
10212 rtx replacement;
10214 {
10215 rtx insn;
10224 {
10225 /* Search for the insn that copies REGNO to NEW_REGNO? */
10233 }
10236 {
10237 rtx prev_insn;
10238 rtx prev_set;
10240 /* Some DEF-USE info would come in handy here to make this
10241 function more general. For now, just check the previous insn
10242 which is the most likely candidate for setting REGNO. */
10250 {
10251 /* We have:
10252 (set (reg regno) (expr))
10253 (set (reg new_regno) (reg regno))
10255 so try converting this to:
10256 (set (reg new_regno) (expr))
10257 (set (reg regno) (reg new_regno))
10259 The former construct is often generated when a global
10260 variable used for an induction variable is shadowed by a
10261 register (NEW_REGNO). The latter construct improves the
10262 chances of GIV replacement and BIV elimination. */
10272 {
10279 /* Update first use of REGNO. */
10283 /* Now perform copy propagation to hopefully
10284 remove all uses of REGNO within the loop. */
10286 }
10287 }
10288 }
10289 }
10291 /* Replace MEM with its associated pseudo register. This function is
10292 called from load_mems via for_each_rtx. DATA is actually a pointer
10293 to a structure describing the instruction currently being scanned
10294 and the MEM we are currently replacing. */
10296 static int
10300 {
10308 {
10313 /* We're not interested in the MEM associated with a
10314 CONST_DOUBLE, so there's no need to traverse into one. */
10318 /* This is not a MEM. */
10320 }
10323 /* This is not the MEM we are currently replacing. */
10326 /* Actually replace the MEM. */
10330 }
10332 static void
10334 rtx insn;
10335 rtx mem;
10336 rtx reg;
10337 {
10338 loop_replace_args args;
10345 }
10347 /* Replace one register with another. Called through for_each_rtx; PX points
10348 to the rtx being scanned. DATA is actually a pointer to
10349 a structure of arguments. */
10351 static int
10355 {
10366 }
10368 static void
10370 rtx insn;
10371 rtx reg;
10372 rtx replacement;
10373 {
10374 loop_replace_args args;
10381 }
10383 /* Replace occurrences of the old exit label for the loop with the new
10384 one. DATA is an rtx_pair containing the old and new labels,
10385 respectively. */
10387 static int
10391 {
10410 }
10411 \f
10412 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10413 (ignored in the interim). */
10415 static rtx
10418 basic_block where_bb ATTRIBUTE_UNUSED;
10419 rtx where_insn;
10420 rtx pattern;
10421 {
10423 }
10426 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10427 in basic block WHERE_BB (ignored in the interim) within the loop
10428 otherwise hoist PATTERN into the loop pre-header. */
10430 rtx
10433 basic_block where_bb ATTRIBUTE_UNUSED;
10434 rtx where_insn;
10435 rtx pattern;
10436 {
10440 }
10443 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10444 WHERE_BB (ignored in the interim) within the loop. */
10446 static rtx
10449 basic_block where_bb ATTRIBUTE_UNUSED;
10450 rtx where_insn;
10451 rtx pattern;
10452 {
10454 }
10457 /* Hoist insn for PATTERN into the loop pre-header. */
10459 rtx
10462 rtx pattern;
10463 {
10465 }
10468 /* Hoist call insn for PATTERN into the loop pre-header. */
10470 static rtx
10473 rtx pattern;
10474 {
10476 }
10479 /* Sink insn for PATTERN after the loop end. */
10481 rtx
10484 rtx pattern;
10485 {
10487 }
10489 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10490 and constant. Emit sequence of intructions to load it into REG */
10491 static rtx
10494 {
10495 rtx seq;
10503 }
10505 /* If the loop has multiple exits, emit insn for PATTERN before the
10506 loop to ensure that it will always be executed no matter how the
10507 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10508 since this is slightly more efficient. */
10510 static rtx
10513 rtx pattern;
10514 {
10517 else
10519 }
10520 \f
10521 static void
10526 {
10534 iv_num++;
10539 {
10542 }
10543 }
10546 static void
10551 {
10553 rtx incr;
10564 {
10567 }
10569 {
10572 }
10576 {
10580 }
10583 {
10587 }
10589 /* List the increments. */
10591 {
10595 }
10597 /* List the givs. */
10599 {
10604 else
10607 }
10608 }
10611 static void
10616 {
10627 {
10631 }
10634 }
10637 static void
10642 {
10649 else
10665 {
10667 {
10679 }
10680 }
10691 {
10695 }
10698 }
10701 void
10704 {
10706 }
10709 void
10712 {
10714 }
10717 void
10720 {
10722 }
10725 void
10728 {
10730 }
10733 #define LOOP_BLOCK_NUM_1(INSN) \
10734 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10736 /* The notes do not have an assigned block, so look at the next insn. */
10737 #define LOOP_BLOCK_NUM(INSN) \
10738 ((INSN) ? (GET_CODE (INSN) == NOTE \
10739 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10740 : LOOP_BLOCK_NUM_1 (INSN)) \
10741 : -1)
10743 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10745 static void
10750 {
10751 rtx label;
10756 /* Print diagnostics to compare our concept of a loop with
10757 what the loop notes say. */
10772 {
10792 {
10795 {
10798 }
10799 }
10802 /* This can happen when a marked loop appears as two nested loops,
10803 say from while (a || b) {}. The inner loop won't match
10804 the loop markers but the outer one will. */
10807 }
10808 }
10810 /* Call this function from the debugger to dump LOOP. */
10812 void
10815 {
10817 }
10819 /* Call this function from the debugger to dump LOOPS. */
10821 void
10824 {
10826 }