1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 #include "integrate.h"
79 /* Next quantity number available for allocation. */
83 /* Information we maintain about each quantity. */
86 /* The number of refs to quantity Q. */
90 /* The frequency of uses of quantity Q. */
94 /* Insn number (counting from head of basic block)
95 where quantity Q was born. -1 if birth has not been recorded. */
99 /* Insn number (counting from head of basic block)
100 where given quantity died. Due to the way tying is done,
101 and the fact that we consider in this pass only regs that die but once,
102 a quantity can die only once. Each quantity's life span
103 is a set of consecutive insns. -1 if death has not been recorded. */
107 /* Number of words needed to hold the data in given quantity.
108 This depends on its machine mode. It is used for these purposes:
109 1. It is used in computing the relative importances of qtys,
110 which determines the order in which we look for regs for them.
111 2. It is used in rules that prevent tying several registers of
112 different sizes in a way that is geometrically impossible
113 (see combine_regs). */
117 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
121 /* The register number of one pseudo register whose reg_qty value is Q.
122 This register should be the head of the chain
123 maintained in reg_next_in_qty. */
127 /* Reg class contained in (smaller than) the preferred classes of all
128 the pseudo regs that are tied in given quantity.
129 This is the preferred class for allocating that quantity. */
131 enum reg_class min_class
;
133 /* Register class within which we allocate given qty if we can't get
134 its preferred class. */
136 enum reg_class alternate_class
;
138 /* This holds the mode of the registers that are tied to given qty,
139 or VOIDmode if registers with differing modes are tied together. */
141 enum machine_mode mode
;
143 /* the hard reg number chosen for given quantity,
144 or -1 if none was found. */
148 /* Nonzero if this quantity has been used in a SUBREG in some
149 way that is illegal. */
155 static struct qty
*qty
;
157 /* These fields are kept separately to speedup their clearing. */
159 /* We maintain two hard register sets that indicate suggested hard registers
160 for each quantity. The first, phys_copy_sugg, contains hard registers
161 that are tied to the quantity by a simple copy. The second contains all
162 hard registers that are tied to the quantity via an arithmetic operation.
164 The former register set is given priority for allocation. This tends to
165 eliminate copy insns. */
167 /* Element Q is a set of hard registers that are suggested for quantity Q by
170 static HARD_REG_SET
*qty_phys_copy_sugg
;
172 /* Element Q is a set of hard registers that are suggested for quantity Q by
175 static HARD_REG_SET
*qty_phys_sugg
;
177 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
179 static short *qty_phys_num_copy_sugg
;
181 /* Element Q is the number of suggested registers in qty_phys_sugg. */
183 static short *qty_phys_num_sugg
;
185 /* If (REG N) has been assigned a quantity number, is a register number
186 of another register assigned the same quantity number, or -1 for the
187 end of the chain. qty->first_reg point to the head of this chain. */
189 static int *reg_next_in_qty
;
191 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
193 of -1 if this register cannot be allocated by local-alloc,
194 or -2 if not known yet.
196 Note that if we see a use or death of pseudo register N with
197 reg_qty[N] == -2, register N must be local to the current block. If
198 it were used in more than one block, we would have reg_qty[N] == -1.
199 This relies on the fact that if reg_basic_block[N] is >= 0, register N
200 will not appear in any other block. We save a considerable number of
201 tests by exploiting this.
203 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
208 /* The offset (in words) of register N within its quantity.
209 This can be nonzero if register N is SImode, and has been tied
210 to a subreg of a DImode register. */
212 static char *reg_offset
;
214 /* Vector of substitutions of register numbers,
215 used to map pseudo regs into hardware regs.
216 This is set up as a result of register allocation.
217 Element N is the hard reg assigned to pseudo reg N,
218 or is -1 if no hard reg was assigned.
219 If N is a hard reg number, element N is N. */
223 /* Set of hard registers live at the current point in the scan
224 of the instructions in a basic block. */
226 static HARD_REG_SET regs_live
;
228 /* Each set of hard registers indicates registers live at a particular
229 point in the basic block. For N even, regs_live_at[N] says which
230 hard registers are needed *after* insn N/2 (i.e., they may not
231 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
233 If an object is to conflict with the inputs of insn J but not the
234 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
235 if it is to conflict with the outputs of insn J but not the inputs of
236 insn J + 1, it is said to die at index J*2 + 1. */
238 static HARD_REG_SET
*regs_live_at
;
240 /* Communicate local vars `insn_number' and `insn'
241 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
242 static int this_insn_number
;
243 static rtx this_insn
;
247 /* Set when an attempt should be made to replace a register
248 with the associated src entry. */
252 /* Set when a REG_EQUIV note is found or created. Use to
253 keep track of what memory accesses might be created later,
260 /* Loop depth is used to recognize equivalences which appear
261 to be present within the same loop (or in an inner loop). */
265 /* The list of each instruction which initializes this register. */
270 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
271 structure for that register. */
273 static struct equivalence
*reg_equiv
;
275 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
276 static int recorded_label_ref
;
278 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
279 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
280 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
281 static int equiv_init_varies_p
PARAMS ((rtx
));
282 static int equiv_init_movable_p
PARAMS ((rtx
, int));
283 static int contains_replace_regs
PARAMS ((rtx
));
284 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
285 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
286 static void update_equiv_regs
PARAMS ((void));
287 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
288 static void block_alloc
PARAMS ((int));
289 static int qty_sugg_compare
PARAMS ((int, int));
290 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
291 static int qty_compare
PARAMS ((int, int));
292 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
293 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
294 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
295 static void update_qty_class
PARAMS ((int, int));
296 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
297 static void reg_is_born
PARAMS ((rtx
, int));
298 static void wipe_dead_reg
PARAMS ((rtx
, int));
299 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
300 int, int, int, int, int));
301 static void mark_life
PARAMS ((int, enum machine_mode
, int));
302 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
303 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
304 static int requires_inout
PARAMS ((const char *));
306 /* Allocate a new quantity (new within current basic block)
307 for register number REGNO which is born at index BIRTH
308 within the block. MODE and SIZE are info on reg REGNO. */
311 alloc_qty (regno
, mode
, size
, birth
)
313 enum machine_mode mode
;
316 int qtyno
= next_qty
++;
318 reg_qty
[regno
] = qtyno
;
319 reg_offset
[regno
] = 0;
320 reg_next_in_qty
[regno
] = -1;
322 qty
[qtyno
].first_reg
= regno
;
323 qty
[qtyno
].size
= size
;
324 qty
[qtyno
].mode
= mode
;
325 qty
[qtyno
].birth
= birth
;
326 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
327 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
328 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
329 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
330 qty
[qtyno
].freq
= REG_FREQ (regno
);
331 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
334 /* Main entry point of this file. */
342 /* We need to keep track of whether or not we recorded a LABEL_REF so
343 that we know if the jump optimizer needs to be rerun. */
344 recorded_label_ref
= 0;
346 /* Leaf functions and non-leaf functions have different needs.
347 If defined, let the machine say what kind of ordering we
349 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
350 ORDER_REGS_FOR_LOCAL_ALLOC
;
353 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
356 update_equiv_regs ();
358 /* This sets the maximum number of quantities we can have. Quantity
359 numbers start at zero and we can have one for each pseudo. */
360 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
362 /* Allocate vectors of temporary data.
363 See the declarations of these variables, above,
364 for what they mean. */
366 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
368 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
369 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
370 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
371 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
373 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
374 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
375 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
377 /* Determine which pseudo-registers can be allocated by local-alloc.
378 In general, these are the registers used only in a single block and
381 We need not be concerned with which block actually uses the register
382 since we will never see it outside that block. */
384 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
386 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
392 /* Force loop below to initialize entire quantity array. */
395 /* Allocate each block's local registers, block by block. */
397 for (b
= 0; b
< n_basic_blocks
; b
++)
399 /* NEXT_QTY indicates which elements of the `qty_...'
400 vectors might need to be initialized because they were used
401 for the previous block; it is set to the entire array before
402 block 0. Initialize those, with explicit loop if there are few,
403 else with bzero and bcopy. Do not initialize vectors that are
404 explicit set by `alloc_qty'. */
408 for (i
= 0; i
< next_qty
; i
++)
410 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
411 qty_phys_num_copy_sugg
[i
] = 0;
412 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
413 qty_phys_num_sugg
[i
] = 0;
418 #define CLEAR(vector) \
419 memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
421 CLEAR (qty_phys_copy_sugg
);
422 CLEAR (qty_phys_num_copy_sugg
);
423 CLEAR (qty_phys_sugg
);
424 CLEAR (qty_phys_num_sugg
);
433 free (qty_phys_copy_sugg
);
434 free (qty_phys_num_copy_sugg
);
435 free (qty_phys_sugg
);
436 free (qty_phys_num_sugg
);
440 free (reg_next_in_qty
);
442 return recorded_label_ref
;
445 /* Used for communication between the following two functions: contains
446 a MEM that we wish to ensure remains unchanged. */
447 static rtx equiv_mem
;
449 /* Set nonzero if EQUIV_MEM is modified. */
450 static int equiv_mem_modified
;
452 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
453 Called via note_stores. */
456 validate_equiv_mem_from_store (dest
, set
, data
)
458 rtx set ATTRIBUTE_UNUSED
;
459 void *data ATTRIBUTE_UNUSED
;
461 if ((GET_CODE (dest
) == REG
462 && reg_overlap_mentioned_p (dest
, equiv_mem
))
463 || (GET_CODE (dest
) == MEM
464 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
465 equiv_mem_modified
= 1;
468 /* Verify that no store between START and the death of REG invalidates
469 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
470 by storing into an overlapping memory location, or with a non-const
473 Return 1 if MEMREF remains valid. */
476 validate_equiv_mem (start
, reg
, memref
)
485 equiv_mem_modified
= 0;
487 /* If the memory reference has side effects or is volatile, it isn't a
488 valid equivalence. */
489 if (side_effects_p (memref
))
492 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
497 if (find_reg_note (insn
, REG_DEAD
, reg
))
500 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
501 && ! CONST_OR_PURE_CALL_P (insn
))
504 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
506 /* If a register mentioned in MEMREF is modified via an
507 auto-increment, we lose the equivalence. Do the same if one
508 dies; although we could extend the life, it doesn't seem worth
511 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
512 if ((REG_NOTE_KIND (note
) == REG_INC
513 || REG_NOTE_KIND (note
) == REG_DEAD
)
514 && GET_CODE (XEXP (note
, 0)) == REG
515 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
522 /* Returns zero if X is known to be invariant. */
525 equiv_init_varies_p (x
)
528 RTX_CODE code
= GET_CODE (x
);
535 return ! RTX_UNCHANGING_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
549 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
552 if (MEM_VOLATILE_P (x
))
561 fmt
= GET_RTX_FORMAT (code
);
562 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
565 if (equiv_init_varies_p (XEXP (x
, i
)))
568 else if (fmt
[i
] == 'E')
571 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
572 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
579 /* Returns non-zero if X (used to initialize register REGNO) is movable.
580 X is only movable if the registers it uses have equivalent initializations
581 which appear to be within the same loop (or in an inner loop) and movable
582 or if they are not candidates for local_alloc and don't vary. */
585 equiv_init_movable_p (x
, regno
)
591 enum rtx_code code
= GET_CODE (x
);
596 return equiv_init_movable_p (SET_SRC (x
), regno
);
611 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
612 && reg_equiv
[REGNO (x
)].replace
)
613 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
, 0));
615 case UNSPEC_VOLATILE
:
619 if (MEM_VOLATILE_P (x
))
628 fmt
= GET_RTX_FORMAT (code
);
629 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
633 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
637 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
638 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
646 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
649 contains_replace_regs (x
)
654 enum rtx_code code
= GET_CODE (x
);
670 return reg_equiv
[REGNO (x
)].replace
;
676 fmt
= GET_RTX_FORMAT (code
);
677 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
681 if (contains_replace_regs (XEXP (x
, i
)))
685 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
686 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
694 /* TRUE if X references a memory location that would be affected by a store
698 memref_referenced_p (memref
, x
)
704 enum rtx_code code
= GET_CODE (x
);
721 return (reg_equiv
[REGNO (x
)].replacement
722 && memref_referenced_p (memref
,
723 reg_equiv
[REGNO (x
)].replacement
));
726 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
731 /* If we are setting a MEM, it doesn't count (its address does), but any
732 other SET_DEST that has a MEM in it is referencing the MEM. */
733 if (GET_CODE (SET_DEST (x
)) == MEM
)
735 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
738 else if (memref_referenced_p (memref
, SET_DEST (x
)))
741 return memref_referenced_p (memref
, SET_SRC (x
));
747 fmt
= GET_RTX_FORMAT (code
);
748 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
752 if (memref_referenced_p (memref
, XEXP (x
, i
)))
756 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
757 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
765 /* TRUE if some insn in the range (START, END] references a memory location
766 that would be affected by a store to MEMREF. */
769 memref_used_between_p (memref
, start
, end
)
776 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
777 insn
= NEXT_INSN (insn
))
778 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
784 /* Return nonzero if the rtx X is invariant over the current function. */
785 /* ??? Actually, the places this is used in reload expect exactly what
786 is tested here, and not everything that is function invariant. In
787 particular, the frame pointer and arg pointer are special cased;
788 pic_offset_table_rtx is not, and this will cause aborts when we
789 go to spill these things to memory. */
792 function_invariant_p (x
)
797 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
799 if (GET_CODE (x
) == PLUS
800 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
801 && CONSTANT_P (XEXP (x
, 1)))
806 /* Find registers that are equivalent to a single value throughout the
807 compilation (either because they can be referenced in memory or are set once
808 from a single constant). Lower their priority for a register.
810 If such a register is only referenced once, try substituting its value
811 into the using insn. If it succeeds, we can eliminate the register
820 regset_head cleared_regs
;
821 int clear_regnos
= 0;
823 reg_equiv
= (struct equivalence
*) xcalloc (max_regno
, sizeof *reg_equiv
);
824 INIT_REG_SET (&cleared_regs
);
826 init_alias_analysis ();
828 /* Scan the insns and find which registers have equivalences. Do this
829 in a separate scan of the insns because (due to -fcse-follow-jumps)
830 a register can be set below its use. */
831 for (block
= 0; block
< n_basic_blocks
; block
++)
833 basic_block bb
= BASIC_BLOCK (block
);
834 loop_depth
= bb
->loop_depth
;
836 for (insn
= bb
->head
; insn
!= NEXT_INSN (bb
->end
); insn
= NEXT_INSN (insn
))
846 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
847 if (REG_NOTE_KIND (note
) == REG_INC
)
848 no_equiv (XEXP (note
, 0), note
, NULL
);
850 set
= single_set (insn
);
852 /* If this insn contains more (or less) than a single SET,
853 only mark all destinations as having no known equivalence. */
856 note_stores (PATTERN (insn
), no_equiv
, NULL
);
859 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
863 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
865 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
867 note_stores (part
, no_equiv
, NULL
);
871 dest
= SET_DEST (set
);
874 /* If this sets a MEM to the contents of a REG that is only used
875 in a single basic block, see if the register is always equivalent
876 to that memory location and if moving the store from INSN to the
877 insn that set REG is safe. If so, put a REG_EQUIV note on the
880 Don't add a REG_EQUIV note if the insn already has one. The existing
881 REG_EQUIV is likely more useful than the one we are adding.
883 If one of the regs in the address has reg_equiv[REGNO].replace set,
884 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
885 optimization may move the set of this register immediately before
886 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
887 the mention in the REG_EQUIV note would be to an uninitialized
889 /* ????? This test isn't good enough; we might see a MEM with a use of
890 a pseudo register before we see its setting insn that will cause
891 reg_equiv[].replace for that pseudo to be set.
892 Equivalences to MEMs should be made in another pass, after the
893 reg_equiv[].replace information has been gathered. */
895 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
896 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
897 && REG_BASIC_BLOCK (regno
) >= 0
898 && REG_N_SETS (regno
) == 1
899 && reg_equiv
[regno
].init_insns
!= 0
900 && reg_equiv
[regno
].init_insns
!= const0_rtx
901 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
903 && ! contains_replace_regs (XEXP (dest
, 0)))
905 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
906 if (validate_equiv_mem (init_insn
, src
, dest
)
907 && ! memref_used_between_p (dest
, init_insn
, insn
))
908 REG_NOTES (init_insn
)
909 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
912 /* We only handle the case of a pseudo register being set
913 once, or always to the same value. */
914 /* ??? The mn10200 port breaks if we add equivalences for
915 values that need an ADDRESS_REGS register and set them equivalent
916 to a MEM of a pseudo. The actual problem is in the over-conservative
917 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
918 calculate_needs, but we traditionally work around this problem
919 here by rejecting equivalences when the destination is in a register
920 that's likely spilled. This is fragile, of course, since the
921 preferred class of a pseudo depends on all instructions that set
924 if (GET_CODE (dest
) != REG
925 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
926 || reg_equiv
[regno
].init_insns
== const0_rtx
927 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
928 && GET_CODE (src
) == MEM
))
930 /* This might be seting a SUBREG of a pseudo, a pseudo that is
931 also set somewhere else to a constant. */
932 note_stores (set
, no_equiv
, NULL
);
936 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
938 /* cse sometimes generates function invariants, but doesn't put a
939 REG_EQUAL note on the insn. Since this note would be redundant,
940 there's no point creating it earlier than here. */
941 if (! note
&& ! rtx_varies_p (src
, 0))
942 note
= set_unique_reg_note (insn
, REG_EQUAL
, src
);
944 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
945 since it represents a function call */
946 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
949 if (REG_N_SETS (regno
) != 1
951 || rtx_varies_p (XEXP (note
, 0), 0)
952 || (reg_equiv
[regno
].replacement
953 && ! rtx_equal_p (XEXP (note
, 0),
954 reg_equiv
[regno
].replacement
))))
956 no_equiv (dest
, set
, NULL
);
959 /* Record this insn as initializing this register. */
960 reg_equiv
[regno
].init_insns
961 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
963 /* If this register is known to be equal to a constant, record that
964 it is always equivalent to the constant. */
965 if (note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
966 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
968 /* If this insn introduces a "constant" register, decrease the priority
969 of that register. Record this insn if the register is only used once
970 more and the equivalence value is the same as our source.
972 The latter condition is checked for two reasons: First, it is an
973 indication that it may be more efficient to actually emit the insn
974 as written (if no registers are available, reload will substitute
975 the equivalence). Secondly, it avoids problems with any registers
976 dying in this insn whose death notes would be missed.
978 If we don't have a REG_EQUIV note, see if this insn is loading
979 a register used only in one basic block from a MEM. If so, and the
980 MEM remains unchanged for the life of the register, add a REG_EQUIV
983 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
985 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
986 && GET_CODE (SET_SRC (set
)) == MEM
987 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
988 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
993 int regno
= REGNO (dest
);
995 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
996 We might end up substituting the LABEL_REF for uses of the
997 pseudo here or later. That kind of transformation may turn an
998 indirect jump into a direct jump, in which case we must rerun the
999 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
1000 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
1001 || (GET_CODE (XEXP (note
, 0)) == CONST
1002 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
1003 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
1005 recorded_label_ref
= 1;
1007 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
1008 reg_equiv
[regno
].src
= src
;
1009 reg_equiv
[regno
].loop_depth
= loop_depth
;
1011 /* Don't mess with things live during setjmp. */
1012 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
1014 /* Note that the statement below does not affect the priority
1016 REG_LIVE_LENGTH (regno
) *= 2;
1019 /* If the register is referenced exactly twice, meaning it is
1020 set once and used once, indicate that the reference may be
1021 replaced by the equivalence we computed above. Do this
1022 even if the register is only used in one block so that
1023 dependencies can be handled where the last register is
1024 used in a different block (i.e. HIGH / LO_SUM sequences)
1025 and to reduce the number of registers alive across
1028 if (REG_N_REFS (regno
) == 2
1029 && (rtx_equal_p (XEXP (note
, 0), src
)
1030 || ! equiv_init_varies_p (src
))
1031 && GET_CODE (insn
) == INSN
1032 && equiv_init_movable_p (PATTERN (insn
), regno
))
1033 reg_equiv
[regno
].replace
= 1;
1039 /* Now scan all regs killed in an insn to see if any of them are
1040 registers only used that once. If so, see if we can replace the
1041 reference with the equivalent from. If we can, delete the
1042 initializing reference and this register will go away. If we
1043 can't replace the reference, and the initialzing reference is
1044 within the same loop (or in an inner loop), then move the register
1045 initialization just before the use, so that they are in the same
1047 for (block
= n_basic_blocks
- 1; block
>= 0; block
--)
1049 basic_block bb
= BASIC_BLOCK (block
);
1051 loop_depth
= bb
->loop_depth
;
1052 for (insn
= bb
->end
; insn
!= PREV_INSN (bb
->head
); insn
= PREV_INSN (insn
))
1056 if (! INSN_P (insn
))
1059 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1061 if (REG_NOTE_KIND (link
) == REG_DEAD
1062 /* Make sure this insn still refers to the register. */
1063 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1065 int regno
= REGNO (XEXP (link
, 0));
1068 if (! reg_equiv
[regno
].replace
1069 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1072 /* reg_equiv[REGNO].replace gets set only when
1073 REG_N_REFS[REGNO] is 2, i.e. the register is set
1074 once and used once. (If it were only set, but not used,
1075 flow would have deleted the setting insns.) Hence
1076 there can only be one insn in reg_equiv[REGNO].init_insns. */
1077 if (reg_equiv
[regno
].init_insns
== NULL_RTX
1078 || XEXP (reg_equiv
[regno
].init_insns
, 1) != NULL_RTX
)
1080 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1082 /* We may not move instructions that can throw, since
1083 that changes basic block boundaries and we are not
1084 prepared to adjust the CFG to match. */
1085 if (can_throw_internal (equiv_insn
))
1088 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1089 && validate_replace_rtx (regno_reg_rtx
[regno
],
1090 reg_equiv
[regno
].src
, insn
))
1096 /* Find the last note. */
1097 for (last_link
= link
; XEXP (last_link
, 1);
1098 last_link
= XEXP (last_link
, 1))
1101 /* Append the REG_DEAD notes from equiv_insn. */
1102 equiv_link
= REG_NOTES (equiv_insn
);
1106 equiv_link
= XEXP (equiv_link
, 1);
1107 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1109 remove_note (equiv_insn
, note
);
1110 XEXP (last_link
, 1) = note
;
1111 XEXP (note
, 1) = NULL_RTX
;
1116 remove_death (regno
, insn
);
1117 REG_N_REFS (regno
) = 0;
1118 REG_FREQ (regno
) = 0;
1119 delete_insn (equiv_insn
);
1121 reg_equiv
[regno
].init_insns
1122 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1124 /* Move the initialization of the register to just before
1125 INSN. Update the flow information. */
1126 else if (PREV_INSN (insn
) != equiv_insn
)
1130 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1131 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1132 REG_NOTES (equiv_insn
) = 0;
1134 /* Make sure this insn is recognized before reload begins,
1135 otherwise eliminate_regs_in_insn will abort. */
1136 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1138 delete_insn (equiv_insn
);
1140 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1142 REG_BASIC_BLOCK (regno
) = block
>= 0 ? block
: 0;
1143 REG_N_CALLS_CROSSED (regno
) = 0;
1144 REG_LIVE_LENGTH (regno
) = 2;
1146 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
1147 BLOCK_HEAD (block
) = PREV_INSN (insn
);
1149 /* Remember to clear REGNO from all basic block's live
1151 SET_REGNO_REG_SET (&cleared_regs
, regno
);
1159 /* Clear all dead REGNOs from all basic block's live info. */
1163 if (clear_regnos
> 8)
1165 for (l
= 0; l
< n_basic_blocks
; l
++)
1167 AND_COMPL_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
1169 AND_COMPL_REG_SET (BASIC_BLOCK (l
)->global_live_at_end
,
1174 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs
, 0, j
,
1176 for (l
= 0; l
< n_basic_blocks
; l
++)
1178 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
, j
);
1179 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_end
, j
);
1185 end_alias_analysis ();
1186 CLEAR_REG_SET (&cleared_regs
);
1190 /* Mark REG as having no known equivalence.
1191 Some instructions might have been proceessed before and furnished
1192 with REG_EQUIV notes for this register; these notes will have to be
1194 STORE is the piece of RTL that does the non-constant / conflicting
1195 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1196 but needs to be there because this function is called from note_stores. */
1198 no_equiv (reg
, store
, data
)
1199 rtx reg
, store ATTRIBUTE_UNUSED
;
1200 void *data ATTRIBUTE_UNUSED
;
1205 if (GET_CODE (reg
) != REG
)
1207 regno
= REGNO (reg
);
1208 list
= reg_equiv
[regno
].init_insns
;
1209 if (list
== const0_rtx
)
1211 for (; list
; list
= XEXP (list
, 1))
1213 rtx insn
= XEXP (list
, 0);
1214 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1216 reg_equiv
[regno
].init_insns
= const0_rtx
;
1217 reg_equiv
[regno
].replacement
= NULL_RTX
;
1220 /* Allocate hard regs to the pseudo regs used only within block number B.
1221 Only the pseudos that die but once can be handled. */
1230 int insn_number
= 0;
1232 int max_uid
= get_max_uid ();
1234 int no_conflict_combined_regno
= -1;
1236 /* Count the instructions in the basic block. */
1238 insn
= BLOCK_END (b
);
1241 if (GET_CODE (insn
) != NOTE
)
1242 if (++insn_count
> max_uid
)
1244 if (insn
== BLOCK_HEAD (b
))
1246 insn
= PREV_INSN (insn
);
1249 /* +2 to leave room for a post_mark_life at the last insn and for
1250 the birth of a CLOBBER in the first insn. */
1251 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1252 sizeof (HARD_REG_SET
));
1254 /* Initialize table of hardware registers currently live. */
1256 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1258 /* This loop scans the instructions of the basic block
1259 and assigns quantities to registers.
1260 It computes which registers to tie. */
1262 insn
= BLOCK_HEAD (b
);
1265 if (GET_CODE (insn
) != NOTE
)
1272 rtx r0
, r1
= NULL_RTX
;
1273 int combined_regno
= -1;
1276 this_insn_number
= insn_number
;
1279 extract_insn (insn
);
1280 which_alternative
= -1;
1282 /* Is this insn suitable for tying two registers?
1283 If so, try doing that.
1284 Suitable insns are those with at least two operands and where
1285 operand 0 is an output that is a register that is not
1288 We can tie operand 0 with some operand that dies in this insn.
1289 First look for operands that are required to be in the same
1290 register as operand 0. If we find such, only try tying that
1291 operand or one that can be put into that operand if the
1292 operation is commutative. If we don't find an operand
1293 that is required to be in the same register as operand 0,
1294 we can tie with any operand.
1296 Subregs in place of regs are also ok.
1298 If tying is done, WIN is set nonzero. */
1301 && recog_data
.n_operands
> 1
1302 && recog_data
.constraints
[0][0] == '='
1303 && recog_data
.constraints
[0][1] != '&')
1305 /* If non-negative, is an operand that must match operand 0. */
1306 int must_match_0
= -1;
1307 /* Counts number of alternatives that require a match with
1309 int n_matching_alts
= 0;
1311 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1313 const char *p
= recog_data
.constraints
[i
];
1314 int this_match
= requires_inout (p
);
1316 n_matching_alts
+= this_match
;
1317 if (this_match
== recog_data
.n_alternatives
)
1321 r0
= recog_data
.operand
[0];
1322 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1324 /* Skip this operand if we found an operand that
1325 must match operand 0 and this operand isn't it
1326 and can't be made to be it by commutativity. */
1328 if (must_match_0
>= 0 && i
!= must_match_0
1329 && ! (i
== must_match_0
+ 1
1330 && recog_data
.constraints
[i
-1][0] == '%')
1331 && ! (i
== must_match_0
- 1
1332 && recog_data
.constraints
[i
][0] == '%'))
1335 /* Likewise if each alternative has some operand that
1336 must match operand zero. In that case, skip any
1337 operand that doesn't list operand 0 since we know that
1338 the operand always conflicts with operand 0. We
1339 ignore commutatity in this case to keep things simple. */
1340 if (n_matching_alts
== recog_data
.n_alternatives
1341 && 0 == requires_inout (recog_data
.constraints
[i
]))
1344 r1
= recog_data
.operand
[i
];
1346 /* If the operand is an address, find a register in it.
1347 There may be more than one register, but we only try one
1349 if (recog_data
.constraints
[i
][0] == 'p')
1350 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1353 /* Avoid making a call-saved register unnecessarily
1355 hard_reg
= get_hard_reg_initial_reg (cfun
, r1
);
1356 if (hard_reg
!= NULL_RTX
)
1358 if (GET_CODE (hard_reg
) == REG
1359 && IN_RANGE (REGNO (hard_reg
),
1360 0, FIRST_PSEUDO_REGISTER
- 1)
1361 && ! call_used_regs
[REGNO (hard_reg
)])
1365 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1367 /* We have two priorities for hard register preferences.
1368 If we have a move insn or an insn whose first input
1369 can only be in the same register as the output, give
1370 priority to an equivalence found from that insn. */
1372 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1374 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1375 win
= combine_regs (r1
, r0
, may_save_copy
,
1376 insn_number
, insn
, 0);
1383 /* Recognize an insn sequence with an ultimate result
1384 which can safely overlap one of the inputs.
1385 The sequence begins with a CLOBBER of its result,
1386 and ends with an insn that copies the result to itself
1387 and has a REG_EQUAL note for an equivalent formula.
1388 That note indicates what the inputs are.
1389 The result and the input can overlap if each insn in
1390 the sequence either doesn't mention the input
1391 or has a REG_NO_CONFLICT note to inhibit the conflict.
1393 We do the combining test at the CLOBBER so that the
1394 destination register won't have had a quantity number
1395 assigned, since that would prevent combining. */
1398 && GET_CODE (PATTERN (insn
)) == CLOBBER
1399 && (r0
= XEXP (PATTERN (insn
), 0),
1400 GET_CODE (r0
) == REG
)
1401 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1402 && XEXP (link
, 0) != 0
1403 && GET_CODE (XEXP (link
, 0)) == INSN
1404 && (set
= single_set (XEXP (link
, 0))) != 0
1405 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1406 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1409 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1410 /* Check that we have such a sequence. */
1411 && no_conflict_p (insn
, r0
, r1
))
1412 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1413 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1414 && (r1
= XEXP (XEXP (note
, 0), 0),
1415 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1416 && no_conflict_p (insn
, r0
, r1
))
1417 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1419 /* Here we care if the operation to be computed is
1421 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1422 || GET_CODE (XEXP (note
, 0)) == NE
1423 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1424 && (r1
= XEXP (XEXP (note
, 0), 1),
1425 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1426 && no_conflict_p (insn
, r0
, r1
))
1427 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1429 /* If we did combine something, show the register number
1430 in question so that we know to ignore its death. */
1432 no_conflict_combined_regno
= REGNO (r1
);
1435 /* If registers were just tied, set COMBINED_REGNO
1436 to the number of the register used in this insn
1437 that was tied to the register set in this insn.
1438 This register's qty should not be "killed". */
1442 while (GET_CODE (r1
) == SUBREG
)
1443 r1
= SUBREG_REG (r1
);
1444 combined_regno
= REGNO (r1
);
1447 /* Mark the death of everything that dies in this instruction,
1448 except for anything that was just combined. */
1450 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1451 if (REG_NOTE_KIND (link
) == REG_DEAD
1452 && GET_CODE (XEXP (link
, 0)) == REG
1453 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1454 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1455 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1457 wipe_dead_reg (XEXP (link
, 0), 0);
1459 /* Allocate qty numbers for all registers local to this block
1460 that are born (set) in this instruction.
1461 A pseudo that already has a qty is not changed. */
1463 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1465 /* If anything is set in this insn and then unused, mark it as dying
1466 after this insn, so it will conflict with our outputs. This
1467 can't match with something that combined, and it doesn't matter
1468 if it did. Do this after the calls to reg_is_set since these
1469 die after, not during, the current insn. */
1471 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1472 if (REG_NOTE_KIND (link
) == REG_UNUSED
1473 && GET_CODE (XEXP (link
, 0)) == REG
)
1474 wipe_dead_reg (XEXP (link
, 0), 1);
1476 /* If this is an insn that has a REG_RETVAL note pointing at a
1477 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1478 block, so clear any register number that combined within it. */
1479 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1480 && GET_CODE (XEXP (note
, 0)) == INSN
1481 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1482 no_conflict_combined_regno
= -1;
1485 /* Set the registers live after INSN_NUMBER. Note that we never
1486 record the registers live before the block's first insn, since no
1487 pseudos we care about are live before that insn. */
1489 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1490 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1492 if (insn
== BLOCK_END (b
))
1495 insn
= NEXT_INSN (insn
);
1498 /* Now every register that is local to this basic block
1499 should have been given a quantity, or else -1 meaning ignore it.
1500 Every quantity should have a known birth and death.
1502 Order the qtys so we assign them registers in order of the
1503 number of suggested registers they need so we allocate those with
1504 the most restrictive needs first. */
1506 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1507 for (i
= 0; i
< next_qty
; i
++)
1510 #define EXCHANGE(I1, I2) \
1511 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1516 /* Make qty_order[2] be the one to allocate last. */
1517 if (qty_sugg_compare (0, 1) > 0)
1519 if (qty_sugg_compare (1, 2) > 0)
1522 /* ... Fall through ... */
1524 /* Put the best one to allocate in qty_order[0]. */
1525 if (qty_sugg_compare (0, 1) > 0)
1528 /* ... Fall through ... */
1532 /* Nothing to do here. */
1536 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1539 /* Try to put each quantity in a suggested physical register, if it has one.
1540 This may cause registers to be allocated that otherwise wouldn't be, but
1541 this seems acceptable in local allocation (unlike global allocation). */
1542 for (i
= 0; i
< next_qty
; i
++)
1545 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1546 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1547 0, 1, qty
[q
].birth
, qty
[q
].death
);
1549 qty
[q
].phys_reg
= -1;
1552 /* Order the qtys so we assign them registers in order of
1553 decreasing length of life. Normally call qsort, but if we
1554 have only a very small number of quantities, sort them ourselves. */
1556 for (i
= 0; i
< next_qty
; i
++)
1559 #define EXCHANGE(I1, I2) \
1560 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1565 /* Make qty_order[2] be the one to allocate last. */
1566 if (qty_compare (0, 1) > 0)
1568 if (qty_compare (1, 2) > 0)
1571 /* ... Fall through ... */
1573 /* Put the best one to allocate in qty_order[0]. */
1574 if (qty_compare (0, 1) > 0)
1577 /* ... Fall through ... */
1581 /* Nothing to do here. */
1585 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1588 /* Now for each qty that is not a hardware register,
1589 look for a hardware register to put it in.
1590 First try the register class that is cheapest for this qty,
1591 if there is more than one class. */
1593 for (i
= 0; i
< next_qty
; i
++)
1596 if (qty
[q
].phys_reg
< 0)
1598 #ifdef INSN_SCHEDULING
1599 /* These values represent the adjusted lifetime of a qty so
1600 that it conflicts with qtys which appear near the start/end
1601 of this qty's lifetime.
1603 The purpose behind extending the lifetime of this qty is to
1604 discourage the register allocator from creating false
1607 The adjustment value is chosen to indicate that this qty
1608 conflicts with all the qtys in the instructions immediately
1609 before and after the lifetime of this qty.
1611 Experiments have shown that higher values tend to hurt
1612 overall code performance.
1614 If allocation using the extended lifetime fails we will try
1615 again with the qty's unadjusted lifetime. */
1616 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1617 int fake_death
= MIN (insn_number
* 2 + 1,
1618 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1621 if (N_REG_CLASSES
> 1)
1623 #ifdef INSN_SCHEDULING
1624 /* We try to avoid using hard registers allocated to qtys which
1625 are born immediately after this qty or die immediately before
1628 This optimization is only appropriate when we will run
1629 a scheduling pass after reload and we are not optimizing
1631 if (flag_schedule_insns_after_reload
1633 && !SMALL_REGISTER_CLASSES
)
1635 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1636 qty
[q
].mode
, q
, 0, 0,
1637 fake_birth
, fake_death
);
1638 if (qty
[q
].phys_reg
>= 0)
1642 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1643 qty
[q
].mode
, q
, 0, 0,
1644 qty
[q
].birth
, qty
[q
].death
);
1645 if (qty
[q
].phys_reg
>= 0)
1649 #ifdef INSN_SCHEDULING
1650 /* Similarly, avoid false dependencies. */
1651 if (flag_schedule_insns_after_reload
1653 && !SMALL_REGISTER_CLASSES
1654 && qty
[q
].alternate_class
!= NO_REGS
)
1655 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1656 qty
[q
].mode
, q
, 0, 0,
1657 fake_birth
, fake_death
);
1659 if (qty
[q
].alternate_class
!= NO_REGS
)
1660 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1661 qty
[q
].mode
, q
, 0, 0,
1662 qty
[q
].birth
, qty
[q
].death
);
1666 /* Now propagate the register assignments
1667 to the pseudo regs belonging to the qtys. */
1669 for (q
= 0; q
< next_qty
; q
++)
1670 if (qty
[q
].phys_reg
>= 0)
1672 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1673 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1677 free (regs_live_at
);
1681 /* Compare two quantities' priority for getting real registers.
1682 We give shorter-lived quantities higher priority.
1683 Quantities with more references are also preferred, as are quantities that
1684 require multiple registers. This is the identical prioritization as
1685 done by global-alloc.
1687 We used to give preference to registers with *longer* lives, but using
1688 the same algorithm in both local- and global-alloc can speed up execution
1689 of some programs by as much as a factor of three! */
1691 /* Note that the quotient will never be bigger than
1692 the value of floor_log2 times the maximum number of
1693 times a register can occur in one insn (surely less than 100)
1694 weighted by frequency (max REG_FREQ_MAX).
1695 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1696 QTY_CMP_PRI is also used by qty_sugg_compare. */
1698 #define QTY_CMP_PRI(q) \
1699 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1700 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1703 qty_compare (q1
, q2
)
1706 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1710 qty_compare_1 (q1p
, q2p
)
1714 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1715 int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1720 /* If qtys are equally good, sort by qty number,
1721 so that the results of qsort leave nothing to chance. */
1725 /* Compare two quantities' priority for getting real registers. This version
1726 is called for quantities that have suggested hard registers. First priority
1727 goes to quantities that have copy preferences, then to those that have
1728 normal preferences. Within those groups, quantities with the lower
1729 number of preferences have the highest priority. Of those, we use the same
1730 algorithm as above. */
1732 #define QTY_CMP_SUGG(q) \
1733 (qty_phys_num_copy_sugg[q] \
1734 ? qty_phys_num_copy_sugg[q] \
1735 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1738 qty_sugg_compare (q1
, q2
)
1741 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1746 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1750 qty_sugg_compare_1 (q1p
, q2p
)
1754 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1755 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1760 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1764 /* If qtys are equally good, sort by qty number,
1765 so that the results of qsort leave nothing to chance. */
1772 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1773 Returns 1 if have done so, or 0 if cannot.
1775 Combining registers means marking them as having the same quantity
1776 and adjusting the offsets within the quantity if either of
1779 We don't actually combine a hard reg with a pseudo; instead
1780 we just record the hard reg as the suggestion for the pseudo's quantity.
1781 If we really combined them, we could lose if the pseudo lives
1782 across an insn that clobbers the hard reg (eg, movstr).
1784 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1785 there is no REG_DEAD note on INSN. This occurs during the processing
1786 of REG_NO_CONFLICT blocks.
1788 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1789 SETREG or if the input and output must share a register.
1790 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1792 There are elaborate checks for the validity of combining. */
1795 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1796 rtx usedreg
, setreg
;
1807 /* Determine the numbers and sizes of registers being used. If a subreg
1808 is present that does not change the entire register, don't consider
1809 this a copy insn. */
1811 while (GET_CODE (usedreg
) == SUBREG
)
1813 rtx subreg
= SUBREG_REG (usedreg
);
1815 if (GET_CODE (subreg
) == REG
)
1817 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1820 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1821 offset
+= subreg_regno_offset (REGNO (subreg
),
1823 SUBREG_BYTE (usedreg
),
1824 GET_MODE (usedreg
));
1826 offset
+= (SUBREG_BYTE (usedreg
)
1827 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1833 if (GET_CODE (usedreg
) != REG
)
1836 ureg
= REGNO (usedreg
);
1837 if (ureg
< FIRST_PSEUDO_REGISTER
)
1838 usize
= HARD_REGNO_NREGS (ureg
, GET_MODE (usedreg
));
1840 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1841 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1842 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1844 while (GET_CODE (setreg
) == SUBREG
)
1846 rtx subreg
= SUBREG_REG (setreg
);
1848 if (GET_CODE (subreg
) == REG
)
1850 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1853 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1854 offset
-= subreg_regno_offset (REGNO (subreg
),
1856 SUBREG_BYTE (setreg
),
1859 offset
-= (SUBREG_BYTE (setreg
)
1860 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1866 if (GET_CODE (setreg
) != REG
)
1869 sreg
= REGNO (setreg
);
1870 if (sreg
< FIRST_PSEUDO_REGISTER
)
1871 ssize
= HARD_REGNO_NREGS (sreg
, GET_MODE (setreg
));
1873 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1874 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1875 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1877 /* If UREG is a pseudo-register that hasn't already been assigned a
1878 quantity number, it means that it is not local to this block or dies
1879 more than once. In either event, we can't do anything with it. */
1880 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1881 /* Do not combine registers unless one fits within the other. */
1882 || (offset
> 0 && usize
+ offset
> ssize
)
1883 || (offset
< 0 && usize
+ offset
< ssize
)
1884 /* Do not combine with a smaller already-assigned object
1885 if that smaller object is already combined with something bigger. */
1886 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1887 && usize
< qty
[reg_qty
[ureg
]].size
)
1888 /* Can't combine if SREG is not a register we can allocate. */
1889 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1890 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1891 These have already been taken care of. This probably wouldn't
1892 combine anyway, but don't take any chances. */
1893 || (ureg
>= FIRST_PSEUDO_REGISTER
1894 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1895 /* Don't tie something to itself. In most cases it would make no
1896 difference, but it would screw up if the reg being tied to itself
1897 also dies in this insn. */
1899 /* Don't try to connect two different hardware registers. */
1900 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1901 /* Don't connect two different machine modes if they have different
1902 implications as to which registers may be used. */
1903 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1906 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1907 qty_phys_sugg for the pseudo instead of tying them.
1909 Return "failure" so that the lifespan of UREG is terminated here;
1910 that way the two lifespans will be disjoint and nothing will prevent
1911 the pseudo reg from being given this hard reg. */
1913 if (ureg
< FIRST_PSEUDO_REGISTER
)
1915 /* Allocate a quantity number so we have a place to put our
1917 if (reg_qty
[sreg
] == -2)
1918 reg_is_born (setreg
, 2 * insn_number
);
1920 if (reg_qty
[sreg
] >= 0)
1923 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1925 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1926 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1928 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1930 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1931 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1937 /* Similarly for SREG a hard register and UREG a pseudo register. */
1939 if (sreg
< FIRST_PSEUDO_REGISTER
)
1942 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1944 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1945 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1947 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1949 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1950 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1955 /* At this point we know that SREG and UREG are both pseudos.
1956 Do nothing if SREG already has a quantity or is a register that we
1958 if (reg_qty
[sreg
] >= -1
1959 /* If we are not going to let any regs live across calls,
1960 don't tie a call-crossing reg to a non-call-crossing reg. */
1961 || (current_function_has_nonlocal_label
1962 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1963 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1966 /* We don't already know about SREG, so tie it to UREG
1967 if this is the last use of UREG, provided the classes they want
1970 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1971 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1973 /* Add SREG to UREG's quantity. */
1974 sqty
= reg_qty
[ureg
];
1975 reg_qty
[sreg
] = sqty
;
1976 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1977 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1978 qty
[sqty
].first_reg
= sreg
;
1980 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1981 update_qty_class (sqty
, sreg
);
1983 /* Update info about quantity SQTY. */
1984 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1985 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1986 qty
[sqty
].freq
+= REG_FREQ (sreg
);
1991 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1992 reg_offset
[i
] -= offset
;
1994 qty
[sqty
].size
= ssize
;
1995 qty
[sqty
].mode
= GET_MODE (setreg
);
2004 /* Return 1 if the preferred class of REG allows it to be tied
2005 to a quantity or register whose class is CLASS.
2006 True if REG's reg class either contains or is contained in CLASS. */
2009 reg_meets_class_p (reg
, class)
2011 enum reg_class
class;
2013 enum reg_class rclass
= reg_preferred_class (reg
);
2014 return (reg_class_subset_p (rclass
, class)
2015 || reg_class_subset_p (class, rclass
));
2018 /* Update the class of QTYNO assuming that REG is being tied to it. */
2021 update_qty_class (qtyno
, reg
)
2025 enum reg_class rclass
= reg_preferred_class (reg
);
2026 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
2027 qty
[qtyno
].min_class
= rclass
;
2029 rclass
= reg_alternate_class (reg
);
2030 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
2031 qty
[qtyno
].alternate_class
= rclass
;
2033 if (REG_CHANGES_MODE (reg
))
2034 qty
[qtyno
].changes_mode
= 1;
2037 /* Handle something which alters the value of an rtx REG.
2039 REG is whatever is set or clobbered. SETTER is the rtx that
2040 is modifying the register.
2042 If it is not really a register, we do nothing.
2043 The file-global variables `this_insn' and `this_insn_number'
2044 carry info from `block_alloc'. */
2047 reg_is_set (reg
, setter
, data
)
2050 void *data ATTRIBUTE_UNUSED
;
2052 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2053 a hard register. These may actually not exist any more. */
2055 if (GET_CODE (reg
) != SUBREG
2056 && GET_CODE (reg
) != REG
)
2059 /* Mark this register as being born. If it is used in a CLOBBER, mark
2060 it as being born halfway between the previous insn and this insn so that
2061 it conflicts with our inputs but not the outputs of the previous insn. */
2063 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
2066 /* Handle beginning of the life of register REG.
2067 BIRTH is the index at which this is happening. */
2070 reg_is_born (reg
, birth
)
2076 if (GET_CODE (reg
) == SUBREG
)
2078 regno
= REGNO (SUBREG_REG (reg
));
2079 if (regno
< FIRST_PSEUDO_REGISTER
)
2080 regno
= subreg_hard_regno (reg
, 1);
2083 regno
= REGNO (reg
);
2085 if (regno
< FIRST_PSEUDO_REGISTER
)
2087 mark_life (regno
, GET_MODE (reg
), 1);
2089 /* If the register was to have been born earlier that the present
2090 insn, mark it as live where it is actually born. */
2091 if (birth
< 2 * this_insn_number
)
2092 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2096 if (reg_qty
[regno
] == -2)
2097 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2099 /* If this register has a quantity number, show that it isn't dead. */
2100 if (reg_qty
[regno
] >= 0)
2101 qty
[reg_qty
[regno
]].death
= -1;
2105 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2106 REG is an output that is dying (i.e., it is never used), otherwise it
2107 is an input (the normal case).
2108 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2111 wipe_dead_reg (reg
, output_p
)
2115 int regno
= REGNO (reg
);
2117 /* If this insn has multiple results,
2118 and the dead reg is used in one of the results,
2119 extend its life to after this insn,
2120 so it won't get allocated together with any other result of this insn.
2122 It is unsafe to use !single_set here since it will ignore an unused
2123 output. Just because an output is unused does not mean the compiler
2124 can assume the side effect will not occur. Consider if REG appears
2125 in the address of an output and we reload the output. If we allocate
2126 REG to the same hard register as an unused output we could set the hard
2127 register before the output reload insn. */
2128 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2129 && multiple_sets (this_insn
))
2132 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2134 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2135 if (GET_CODE (set
) == SET
2136 && GET_CODE (SET_DEST (set
)) != REG
2137 && !rtx_equal_p (reg
, SET_DEST (set
))
2138 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2143 /* If this register is used in an auto-increment address, then extend its
2144 life to after this insn, so that it won't get allocated together with
2145 the result of this insn. */
2146 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2149 if (regno
< FIRST_PSEUDO_REGISTER
)
2151 mark_life (regno
, GET_MODE (reg
), 0);
2153 /* If a hard register is dying as an output, mark it as in use at
2154 the beginning of this insn (the above statement would cause this
2157 post_mark_life (regno
, GET_MODE (reg
), 1,
2158 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2161 else if (reg_qty
[regno
] >= 0)
2162 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2165 /* Find a block of SIZE words of hard regs in reg_class CLASS
2166 that can hold something of machine-mode MODE
2167 (but actually we test only the first of the block for holding MODE)
2168 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2169 and return the number of the first of them.
2170 Return -1 if such a block cannot be found.
2171 If QTYNO crosses calls, insist on a register preserved by calls,
2172 unless ACCEPT_CALL_CLOBBERED is nonzero.
2174 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2175 register is available. If not, return -1. */
2178 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
2179 born_index
, dead_index
)
2180 enum reg_class
class;
2181 enum machine_mode mode
;
2183 int accept_call_clobbered
;
2184 int just_try_suggested
;
2185 int born_index
, dead_index
;
2189 /* Declare it register if it's a scalar. */
2192 HARD_REG_SET used
, first_used
;
2193 #ifdef ELIMINABLE_REGS
2194 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2197 /* Validate our parameters. */
2198 if (born_index
< 0 || born_index
> dead_index
)
2201 /* Don't let a pseudo live in a reg across a function call
2202 if we might get a nonlocal goto. */
2203 if (current_function_has_nonlocal_label
2204 && qty
[qtyno
].n_calls_crossed
> 0)
2207 if (accept_call_clobbered
)
2208 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2209 else if (qty
[qtyno
].n_calls_crossed
== 0)
2210 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2212 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2214 if (accept_call_clobbered
)
2215 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2217 for (ins
= born_index
; ins
< dead_index
; ins
++)
2218 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2220 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2222 /* Don't use the frame pointer reg in local-alloc even if
2223 we may omit the frame pointer, because if we do that and then we
2224 need a frame pointer, reload won't know how to move the pseudo
2225 to another hard reg. It can move only regs made by global-alloc.
2227 This is true of any register that can be eliminated. */
2228 #ifdef ELIMINABLE_REGS
2229 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2230 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2231 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2232 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2233 that it might be eliminated into. */
2234 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2237 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2240 #ifdef CLASS_CANNOT_CHANGE_MODE
2241 if (qty
[qtyno
].changes_mode
)
2242 IOR_HARD_REG_SET (used
,
2243 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
2246 /* Normally, the registers that can be used for the first register in
2247 a multi-register quantity are the same as those that can be used for
2248 subsequent registers. However, if just trying suggested registers,
2249 restrict our consideration to them. If there are copy-suggested
2250 register, try them. Otherwise, try the arithmetic-suggested
2252 COPY_HARD_REG_SET (first_used
, used
);
2254 if (just_try_suggested
)
2256 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2257 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2259 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2262 /* If all registers are excluded, we can't do anything. */
2263 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2265 /* If at least one would be suitable, test each hard reg. */
2267 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2269 #ifdef REG_ALLOC_ORDER
2270 int regno
= reg_alloc_order
[i
];
2274 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2275 && HARD_REGNO_MODE_OK (regno
, mode
)
2276 && (qty
[qtyno
].n_calls_crossed
== 0
2277 || accept_call_clobbered
2278 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2281 int size1
= HARD_REGNO_NREGS (regno
, mode
);
2282 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2285 /* Mark that this register is in use between its birth and death
2287 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2290 #ifndef REG_ALLOC_ORDER
2291 /* Skip starting points we know will lose. */
2298 /* If we are just trying suggested register, we have just tried copy-
2299 suggested registers, and there are arithmetic-suggested registers,
2302 /* If it would be profitable to allocate a call-clobbered register
2303 and save and restore it around calls, do that. */
2304 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2305 && qty_phys_num_sugg
[qtyno
] != 0)
2307 /* Don't try the copy-suggested regs again. */
2308 qty_phys_num_copy_sugg
[qtyno
] = 0;
2309 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2310 born_index
, dead_index
);
2313 /* We need not check to see if the current function has nonlocal
2314 labels because we don't put any pseudos that are live over calls in
2315 registers in that case. */
2317 if (! accept_call_clobbered
2318 && flag_caller_saves
2319 && ! just_try_suggested
2320 && qty
[qtyno
].n_calls_crossed
!= 0
2321 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2322 qty
[qtyno
].n_calls_crossed
))
2324 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2326 caller_save_needed
= 1;
2332 /* Mark that REGNO with machine-mode MODE is live starting from the current
2333 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2337 mark_life (regno
, mode
, life
)
2339 enum machine_mode mode
;
2342 int j
= HARD_REGNO_NREGS (regno
, mode
);
2345 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2348 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2351 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2352 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2353 to insn number DEATH (exclusive). */
2356 post_mark_life (regno
, mode
, life
, birth
, death
)
2358 enum machine_mode mode
;
2359 int life
, birth
, death
;
2361 int j
= HARD_REGNO_NREGS (regno
, mode
);
2363 /* Declare it register if it's a scalar. */
2366 HARD_REG_SET this_reg
;
2368 CLEAR_HARD_REG_SET (this_reg
);
2370 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2373 while (birth
< death
)
2375 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2379 while (birth
< death
)
2381 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2386 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2387 is the register being clobbered, and R1 is a register being used in
2388 the equivalent expression.
2390 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2391 in which it is used, return 1.
2393 Otherwise, return 0. */
2396 no_conflict_p (insn
, r0
, r1
)
2397 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2400 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2403 /* If R1 is a hard register, return 0 since we handle this case
2404 when we scan the insns that actually use it. */
2407 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2408 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2409 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2412 last
= XEXP (note
, 0);
2414 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2417 if (find_reg_note (p
, REG_DEAD
, r1
))
2420 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2421 some earlier optimization pass has inserted instructions into
2422 the sequence, and it is not safe to perform this optimization.
2423 Note that emit_no_conflict_block always ensures that this is
2424 true when these sequences are created. */
2425 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2432 /* Return the number of alternatives for which the constraint string P
2433 indicates that the operand must be equal to operand 0 and that no register
2442 int reg_allowed
= 0;
2443 int num_matching_alts
= 0;
2448 case '=': case '+': case '?':
2449 case '#': case '&': case '!':
2451 case 'm': case '<': case '>': case 'V': case 'o':
2452 case 'E': case 'F': case 'G': case 'H':
2453 case 's': case 'i': case 'n':
2454 case 'I': case 'J': case 'K': case 'L':
2455 case 'M': case 'N': case 'O': case 'P':
2457 /* These don't say anything we care about. */
2461 if (found_zero
&& ! reg_allowed
)
2462 num_matching_alts
++;
2464 found_zero
= reg_allowed
= 0;
2471 case '1': case '2': case '3': case '4': case '5':
2472 case '6': case '7': case '8': case '9':
2473 /* Skip the balance of the matching constraint. */
2474 while (ISDIGIT (*p
))
2479 if (REG_CLASS_FROM_LETTER (c
) == NO_REGS
)
2488 if (found_zero
&& ! reg_allowed
)
2489 num_matching_alts
++;
2491 return num_matching_alts
;
2495 dump_local_alloc (file
)
2499 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2500 if (reg_renumber
[i
] != -1)
2501 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);