1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
596 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
597 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
601 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
604 dump_value_slim (lra_dump_file
, original
, 1);
606 if (new_class
!= lra_get_allocno_class (regno
))
607 lra_change_class (regno
, new_class
, ", change to", false);
608 if (lra_dump_file
!= NULL
)
609 fprintf (lra_dump_file
, "\n");
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original
)
615 && REG_P (curr_insn_input_reloads
[i
].input
)
616 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
617 && (GET_MODE (original
)
618 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
621 *result_reg
= (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
624 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
625 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
633 /* The page contains code to extract memory address parts. */
635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 ok_for_index_p_nonstrict (rtx reg
)
639 unsigned regno
= REGNO (reg
);
641 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
644 /* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
647 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
648 enum rtx_code outer_code
, enum rtx_code index_code
)
650 unsigned regno
= REGNO (reg
);
652 if (regno
>= FIRST_PSEUDO_REGISTER
)
654 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
659 /* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
662 /* Return the offset from REGNO of the least significant register
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 lra_constraint_offset (int regno
, machine_mode mode
)
673 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
674 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
675 && SCALAR_INT_MODE_P (mode
))
676 return hard_regno_nregs
[regno
][mode
] - 1;
680 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
681 if they are the same hard reg, and has special hacks for
682 auto-increment and auto-decrement. This is specifically intended for
683 process_alt_operands to use in determining whether two operands
684 match. X is the operand whose number is the lower of the two.
686 It is supposed that X is the output operand and Y is the input
687 operand. Y_HARD_REGNO is the final hard regno of register Y or
688 register in subreg Y as we know it now. Otherwise, it is a
691 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
694 RTX_CODE code
= GET_CODE (x
);
699 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
700 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
704 i
= get_hard_regno (x
, false);
708 if ((j
= y_hard_regno
) < 0)
711 i
+= lra_constraint_offset (i
, GET_MODE (x
));
712 j
+= lra_constraint_offset (j
, GET_MODE (y
));
717 /* If two operands must match, because they are really a single
718 operand of an assembler insn, then two post-increments are invalid
719 because the assembler insn would increment only once. On the
720 other hand, a post-increment matches ordinary indexing if the
721 post-increment is the output operand. */
722 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
723 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
725 /* Two pre-increments are invalid because the assembler insn would
726 increment only once. On the other hand, a pre-increment matches
727 ordinary indexing if the pre-increment is the input operand. */
728 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
729 || GET_CODE (y
) == PRE_MODIFY
)
730 return operands_match_p (x
, XEXP (y
, 0), -1);
734 if (code
== REG
&& REG_P (y
))
735 return REGNO (x
) == REGNO (y
);
737 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
738 && x
== SUBREG_REG (y
))
740 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
741 && SUBREG_REG (x
) == y
)
744 /* Now we have disposed of all the cases in which different rtx
746 if (code
!= GET_CODE (y
))
749 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
750 if (GET_MODE (x
) != GET_MODE (y
))
759 return label_ref_label (x
) == label_ref_label (y
);
761 return XSTR (x
, 0) == XSTR (y
, 0);
767 /* Compare the elements. If any pair of corresponding elements fail
768 to match, return false for the whole things. */
770 fmt
= GET_RTX_FORMAT (code
);
771 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
777 if (XWINT (x
, i
) != XWINT (y
, i
))
782 if (XINT (x
, i
) != XINT (y
, i
))
787 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
796 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
798 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
800 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
806 /* It is believed that rtx's at this level will never
807 contain anything but integers and other rtx's, except for
808 within LABEL_REFs and SYMBOL_REFs. */
816 /* True if X is a constant that can be forced into the constant pool.
817 MODE is the mode of the operand, or VOIDmode if not known. */
818 #define CONST_POOL_OK_P(MODE, X) \
819 ((MODE) != VOIDmode \
821 && GET_CODE (X) != HIGH \
822 && !targetm.cannot_force_const_mem (MODE, X))
824 /* True if C is a non-empty register class that has too few registers
825 to be safely used as a reload target class. */
826 #define SMALL_REGISTER_CLASS_P(C) \
827 (ira_class_hard_regs_num [(C)] == 1 \
828 || (ira_class_hard_regs_num [(C)] >= 1 \
829 && targetm.class_likely_spilled_p (C)))
831 /* If REG is a reload pseudo, try to make its class satisfying CL. */
833 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
835 enum reg_class rclass
;
837 /* Do not make more accurate class from reloads generated. They are
838 mostly moves with a lot of constraints. Making more accurate
839 class may results in very narrow class and impossibility of find
840 registers for several reloads of one insn. */
841 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
843 if (GET_CODE (reg
) == SUBREG
)
844 reg
= SUBREG_REG (reg
);
845 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
847 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
848 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
851 /* Searches X for any reference to a reg with the same value as REGNO,
852 returning the rtx of the reference found if any. Otherwise,
855 regno_val_use_in (unsigned int regno
, rtx x
)
861 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
864 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
865 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
869 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
872 else if (fmt
[i
] == 'E')
873 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
874 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
881 /* Return true if all current insn non-output operands except INS (it
882 has a negaitve end marker) do not use pseudos with the same value
885 check_conflict_input_operands (int regno
, signed char *ins
)
888 int n_operands
= curr_static_id
->n_operands
;
890 for (int nop
= 0; nop
< n_operands
; nop
++)
891 if (! curr_static_id
->operand
[nop
].is_operator
892 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
894 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
898 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
904 /* Generate reloads for matching OUT and INS (array of input operand
905 numbers with end marker -1) with reg class GOAL_CLASS, considering
906 output operands OUTS (similar array to INS) needing to be in different
907 registers. Add input and output reloads correspondingly to the lists
908 *BEFORE and *AFTER. OUT might be negative. In this case we generate
909 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
910 that the output operand is early clobbered for chosen alternative. */
912 match_reload (signed char out
, signed char *ins
, signed char *outs
,
913 enum reg_class goal_class
, rtx_insn
**before
,
914 rtx_insn
**after
, bool early_clobber_p
)
918 rtx new_in_reg
, new_out_reg
, reg
;
919 machine_mode inmode
, outmode
;
920 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
921 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
923 inmode
= curr_operand_mode
[ins
[0]];
924 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
925 push_to_sequence (*before
);
926 if (inmode
!= outmode
)
928 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
931 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
933 if (SCALAR_INT_MODE_P (inmode
))
934 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
936 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
937 LRA_SUBREG_P (new_out_reg
) = 1;
938 /* If the input reg is dying here, we can use the same hard
939 register for REG and IN_RTX. We do it only for original
940 pseudos as reload pseudos can die although original
941 pseudos still live where reload pseudos dies. */
942 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
943 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
945 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
946 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
951 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
953 if (SCALAR_INT_MODE_P (outmode
))
954 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
956 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
957 /* NEW_IN_REG is non-paradoxical subreg. We don't want
958 NEW_OUT_REG living above. We add clobber clause for
959 this. This is just a temporary clobber. We can remove
960 it at the end of LRA work. */
961 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
962 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
963 LRA_SUBREG_P (new_in_reg
) = 1;
964 if (GET_CODE (in_rtx
) == SUBREG
)
966 rtx subreg_reg
= SUBREG_REG (in_rtx
);
968 /* If SUBREG_REG is dying here and sub-registers IN_RTX
969 and NEW_IN_REG are similar, we can use the same hard
970 register for REG and SUBREG_REG. */
971 if (REG_P (subreg_reg
)
972 && (int) REGNO (subreg_reg
) < lra_new_regno_start
973 && GET_MODE (subreg_reg
) == outmode
974 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
975 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
976 && (! early_clobber_p
977 || check_conflict_input_operands (REGNO (subreg_reg
),
979 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
985 /* Pseudos have values -- see comments for lra_reg_info.
986 Different pseudos with the same value do not conflict even if
987 they live in the same place. When we create a pseudo we
988 assign value of original pseudo (if any) from which we
989 created the new pseudo. If we create the pseudo from the
990 input pseudo, the new pseudo will have no conflict with the
991 input pseudo which is wrong when the input pseudo lives after
992 the insn and as the new pseudo value is changed by the insn
993 output. Therefore we create the new pseudo from the output
994 except the case when we have single matched dying input
997 We cannot reuse the current output register because we might
998 have a situation like "a <- a op b", where the constraints
999 force the second input operand ("b") to match the output
1000 operand ("a"). "b" must then be copied into a new register
1001 so that it doesn't clobber the current value of "a".
1003 We can not use the same value if the output pseudo is
1004 early clobbered or the input pseudo is mentioned in the
1005 output, e.g. as an address part in memory, because
1006 output reload will actually extend the pseudo liveness.
1007 We don't care about eliminable hard regs here as we are
1008 interesting only in pseudos. */
1010 /* Matching input's register value is the same as one of the other
1011 output operand. Output operands in a parallel insn must be in
1012 different registers. */
1013 out_conflict
= false;
1016 for (i
= 0; outs
[i
] >= 0; i
++)
1018 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1019 if (REG_P (other_out_rtx
)
1020 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1023 out_conflict
= true;
1029 new_in_reg
= new_out_reg
1030 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1031 && (int) REGNO (in_rtx
) < lra_new_regno_start
1032 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1033 && (! early_clobber_p
1034 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1036 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1038 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1039 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1042 /* In operand can be got from transformations before processing insn
1043 constraints. One example of such transformations is subreg
1044 reloading (see function simplify_operand_subreg). The new
1045 pseudos created by the transformations might have inaccurate
1046 class (ALL_REGS) and we should make their classes more
1048 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1049 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1050 *before
= get_insns ();
1052 /* Add the new pseudo to consider values of subsequent input reload
1054 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1055 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1056 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1057 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1058 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1061 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1062 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1063 *curr_id
->operand_loc
[in
] = new_in_reg
;
1065 lra_update_dups (curr_id
, ins
);
1068 /* See a comment for the input operand above. */
1069 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1070 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1073 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1075 *after
= get_insns ();
1078 *curr_id
->operand_loc
[out
] = new_out_reg
;
1079 lra_update_dup (curr_id
, out
);
1082 /* Return register class which is union of all reg classes in insn
1083 constraint alternative string starting with P. */
1084 static enum reg_class
1085 reg_class_from_constraints (const char *p
)
1088 enum reg_class op_class
= NO_REGS
;
1091 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1098 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1102 enum constraint_num cn
= lookup_constraint (p
);
1103 enum reg_class cl
= reg_class_for_constraint (cn
);
1106 if (insn_extra_address_constraint (cn
))
1108 = (reg_class_subunion
1109 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1110 ADDRESS
, SCRATCH
)]);
1114 op_class
= reg_class_subunion
[op_class
][cl
];
1117 while ((p
+= len
), c
);
1121 /* If OP is a register, return the class of the register as per
1122 get_reg_class, otherwise return NO_REGS. */
1123 static inline enum reg_class
1124 get_op_class (rtx op
)
1126 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1129 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1130 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1131 SUBREG for VAL to make them equal. */
1133 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1135 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1137 /* Usually size of mem_pseudo is greater than val size but in
1138 rare cases it can be less as it can be defined by target
1139 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1142 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1143 GET_CODE (val
) == SUBREG
1144 ? SUBREG_REG (val
) : val
);
1145 LRA_SUBREG_P (val
) = 1;
1149 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1150 LRA_SUBREG_P (mem_pseudo
) = 1;
1153 return to_p
? gen_move_insn (mem_pseudo
, val
)
1154 : gen_move_insn (val
, mem_pseudo
);
1157 /* Process a special case insn (register move), return true if we
1158 don't need to process it anymore. INSN should be a single set
1159 insn. Set up that RTL was changed through CHANGE_P and macro
1160 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1163 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1166 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1168 enum reg_class dclass
, sclass
, secondary_class
;
1169 secondary_reload_info sri
;
1171 lra_assert (curr_insn_set
!= NULL_RTX
);
1172 dreg
= dest
= SET_DEST (curr_insn_set
);
1173 sreg
= src
= SET_SRC (curr_insn_set
);
1174 if (GET_CODE (dest
) == SUBREG
)
1175 dreg
= SUBREG_REG (dest
);
1176 if (GET_CODE (src
) == SUBREG
)
1177 sreg
= SUBREG_REG (src
);
1178 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1180 sclass
= dclass
= NO_REGS
;
1182 dclass
= get_reg_class (REGNO (dreg
));
1183 gcc_assert (dclass
< LIM_REG_CLASSES
);
1184 if (dclass
== ALL_REGS
)
1185 /* ALL_REGS is used for new pseudos created by transformations
1186 like reload of SUBREG_REG (see function
1187 simplify_operand_subreg). We don't know their class yet. We
1188 should figure out the class from processing the insn
1189 constraints not in this fast path function. Even if ALL_REGS
1190 were a right class for the pseudo, secondary_... hooks usually
1191 are not define for ALL_REGS. */
1194 sclass
= get_reg_class (REGNO (sreg
));
1195 gcc_assert (sclass
< LIM_REG_CLASSES
);
1196 if (sclass
== ALL_REGS
)
1197 /* See comments above. */
1199 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1201 #ifdef SECONDARY_MEMORY_NEEDED
1202 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1203 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1204 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1205 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1213 if (! REG_P (dreg
) || ! REG_P (sreg
))
1215 sri
.prev_sri
= NULL
;
1216 sri
.icode
= CODE_FOR_nothing
;
1218 secondary_class
= NO_REGS
;
1219 /* Set up hard register for a reload pseudo for hook
1220 secondary_reload because some targets just ignore unassigned
1221 pseudos in the hook. */
1222 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1224 dregno
= REGNO (dreg
);
1225 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1229 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1231 sregno
= REGNO (sreg
);
1232 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1236 if (sclass
!= NO_REGS
)
1238 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1239 (reg_class_t
) sclass
,
1240 GET_MODE (src
), &sri
);
1241 if (sclass
== NO_REGS
1242 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1243 && dclass
!= NO_REGS
))
1245 enum reg_class old_sclass
= secondary_class
;
1246 secondary_reload_info old_sri
= sri
;
1248 sri
.prev_sri
= NULL
;
1249 sri
.icode
= CODE_FOR_nothing
;
1252 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1253 (reg_class_t
) dclass
,
1254 GET_MODE (src
), &sri
);
1255 /* Check the target hook consistency. */
1257 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1258 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1259 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1262 reg_renumber
[sregno
] = -1;
1264 reg_renumber
[dregno
] = -1;
1265 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1269 if (secondary_class
!= NO_REGS
)
1270 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1274 if (sri
.icode
== CODE_FOR_nothing
)
1275 lra_emit_move (new_reg
, src
);
1278 enum reg_class scratch_class
;
1280 scratch_class
= (reg_class_from_constraints
1281 (insn_data
[sri
.icode
].operand
[2].constraint
));
1282 scratch_reg
= (lra_create_new_reg_with_unique_value
1283 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1284 scratch_class
, "scratch"));
1285 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1288 before
= get_insns ();
1290 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1291 if (new_reg
!= NULL_RTX
)
1292 SET_SRC (curr_insn_set
) = new_reg
;
1295 if (lra_dump_file
!= NULL
)
1297 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1298 dump_insn_slim (lra_dump_file
, curr_insn
);
1300 lra_set_insn_deleted (curr_insn
);
1306 /* The following data describe the result of process_alt_operands.
1307 The data are used in curr_insn_transform to generate reloads. */
1309 /* The chosen reg classes which should be used for the corresponding
1311 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1312 /* True if the operand should be the same as another operand and that
1313 other operand does not need a reload. */
1314 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1315 /* True if the operand does not need a reload. */
1316 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1317 /* True if the operand can be offsetable memory. */
1318 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1319 /* The number of an operand to which given operand can be matched to. */
1320 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1321 /* The number of elements in the following array. */
1322 static int goal_alt_dont_inherit_ops_num
;
1323 /* Numbers of operands whose reload pseudos should not be inherited. */
1324 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1325 /* True if the insn commutative operands should be swapped. */
1326 static bool goal_alt_swapped
;
1327 /* The chosen insn alternative. */
1328 static int goal_alt_number
;
1330 /* True if the corresponding operand is the result of an equivalence
1332 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1334 /* The following five variables are used to choose the best insn
1335 alternative. They reflect final characteristics of the best
1338 /* Number of necessary reloads and overall cost reflecting the
1339 previous value and other unpleasantness of the best alternative. */
1340 static int best_losers
, best_overall
;
1341 /* Overall number hard registers used for reloads. For example, on
1342 some targets we need 2 general registers to reload DFmode and only
1343 one floating point register. */
1344 static int best_reload_nregs
;
1345 /* Overall number reflecting distances of previous reloading the same
1346 value. The distances are counted from the current BB start. It is
1347 used to improve inheritance chances. */
1348 static int best_reload_sum
;
1350 /* True if the current insn should have no correspondingly input or
1352 static bool no_input_reloads_p
, no_output_reloads_p
;
1354 /* True if we swapped the commutative operands in the current
1356 static int curr_swapped
;
1358 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1359 register of class CL. Add any input reloads to list BEFORE. AFTER
1360 is nonnull if *LOC is an automodified value; handle that case by
1361 adding the required output reloads to list AFTER. Return true if
1362 the RTL was changed.
1364 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1365 register. Return false if the address register is correct. */
1367 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1371 enum reg_class rclass
, new_class
;
1375 bool subreg_p
, before_p
= false;
1377 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1380 reg
= SUBREG_REG (*loc
);
1381 mode
= GET_MODE (reg
);
1383 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1384 between two registers with different classes, but there normally will
1385 be "mov" which transfers element of vector register into the general
1386 register, and this normally will be a subreg which should be reloaded
1387 as a whole. This is particularly likely to be triggered when
1388 -fno-split-wide-types specified. */
1390 || in_class_p (reg
, cl
, &new_class
)
1391 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1392 loc
= &SUBREG_REG (*loc
);
1396 mode
= GET_MODE (reg
);
1401 /* Always reload memory in an address even if the target supports
1403 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1408 regno
= REGNO (reg
);
1409 rclass
= get_reg_class (regno
);
1411 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1413 if (lra_dump_file
!= NULL
)
1415 fprintf (lra_dump_file
,
1416 "Changing pseudo %d in address of insn %u on equiv ",
1417 REGNO (reg
), INSN_UID (curr_insn
));
1418 dump_value_slim (lra_dump_file
, *loc
, 1);
1419 fprintf (lra_dump_file
, "\n");
1421 *loc
= copy_rtx (*loc
);
1423 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1428 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1429 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1432 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1436 lra_change_class (regno
, new_class
, " Change to", true);
1444 push_to_sequence (*before
);
1445 lra_emit_move (new_reg
, reg
);
1446 *before
= get_insns ();
1453 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1455 *after
= get_insns ();
1461 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1462 the insn to be inserted before curr insn. AFTER returns the
1463 the insn to be inserted after curr insn. ORIGREG and NEWREG
1464 are the original reg and new reg for reload. */
1466 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1471 push_to_sequence (*before
);
1472 lra_emit_move (newreg
, origreg
);
1473 *before
= get_insns ();
1479 lra_emit_move (origreg
, newreg
);
1481 *after
= get_insns ();
1486 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1487 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1489 /* Make reloads for subreg in operand NOP with internal subreg mode
1490 REG_MODE, add new reloads for further processing. Return true if
1491 any change was done. */
1493 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1496 rtx_insn
*before
, *after
;
1497 machine_mode mode
, innermode
;
1499 rtx operand
= *curr_id
->operand_loc
[nop
];
1500 enum reg_class regclass
;
1503 before
= after
= NULL
;
1505 if (GET_CODE (operand
) != SUBREG
)
1508 mode
= GET_MODE (operand
);
1509 reg
= SUBREG_REG (operand
);
1510 innermode
= GET_MODE (reg
);
1511 type
= curr_static_id
->operand
[nop
].type
;
1514 const bool addr_was_valid
1515 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1516 alter_subreg (curr_id
->operand_loc
[nop
], false);
1517 rtx subst
= *curr_id
->operand_loc
[nop
];
1518 lra_assert (MEM_P (subst
));
1521 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1522 MEM_ADDR_SPACE (subst
))
1523 || ((get_constraint_type (lookup_constraint
1524 (curr_static_id
->operand
[nop
].constraint
))
1525 != CT_SPECIAL_MEMORY
)
1526 /* We still can reload address and if the address is
1527 valid, we can remove subreg without reloading its
1529 && valid_address_p (GET_MODE (subst
),
1531 [ira_class_hard_regs
1532 [base_reg_class (GET_MODE (subst
),
1533 MEM_ADDR_SPACE (subst
),
1534 ADDRESS
, SCRATCH
)][0]],
1535 MEM_ADDR_SPACE (subst
))))
1537 /* If we change the address for a paradoxical subreg of memory, the
1538 new address might violate the necessary alignment or the access
1539 might be slow; take this into consideration. We need not worry
1540 about accesses beyond allocated memory for paradoxical memory
1541 subregs as we don't substitute such equiv memory (see processing
1542 equivalences in function lra_constraints) and because for spilled
1543 pseudos we allocate stack memory enough for the biggest
1544 corresponding paradoxical subreg. */
1545 if (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1546 && SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (subst
)))
1547 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1548 && SLOW_UNALIGNED_ACCESS (innermode
, MEM_ALIGN (reg
))))
1551 *curr_id
->operand_loc
[nop
] = operand
;
1553 /* But if the address was not valid, we cannot reload the MEM without
1554 reloading the address first. */
1555 if (!addr_was_valid
)
1556 process_address (nop
, false, &before
, &after
);
1558 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1559 enum reg_class rclass
1560 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1561 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1562 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1564 bool insert_before
, insert_after
;
1565 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1567 insert_before
= (type
!= OP_OUT
1568 || GET_MODE_SIZE (innermode
)
1569 > GET_MODE_SIZE (mode
));
1570 insert_after
= type
!= OP_IN
;
1571 insert_move_for_subreg (insert_before
? &before
: NULL
,
1572 insert_after
? &after
: NULL
,
1575 SUBREG_REG (operand
) = new_reg
;
1577 /* Convert to MODE. */
1580 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1581 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1582 rclass
, TRUE
, "slow mem", &new_reg
))
1584 bool insert_before
, insert_after
;
1585 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1587 insert_before
= type
!= OP_OUT
;
1588 insert_after
= type
!= OP_IN
;
1589 insert_move_for_subreg (insert_before
? &before
: NULL
,
1590 insert_after
? &after
: NULL
,
1593 *curr_id
->operand_loc
[nop
] = new_reg
;
1594 lra_process_new_insns (curr_insn
, before
, after
,
1595 "Inserting slow mem reload");
1599 /* If the address was valid and became invalid, prefer to reload
1600 the memory. Typical case is when the index scale should
1601 correspond the memory. */
1602 *curr_id
->operand_loc
[nop
] = operand
;
1605 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1607 alter_subreg (curr_id
->operand_loc
[nop
], false);
1610 else if (CONSTANT_P (reg
))
1612 /* Try to simplify subreg of constant. It is usually result of
1613 equivalence substitution. */
1614 if (innermode
== VOIDmode
1615 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1616 innermode
= curr_static_id
->operand
[nop
].mode
;
1617 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1618 SUBREG_BYTE (operand
))) != NULL_RTX
)
1620 *curr_id
->operand_loc
[nop
] = new_reg
;
1624 /* Put constant into memory when we have mixed modes. It generates
1625 a better code in most cases as it does not need a secondary
1626 reload memory. It also prevents LRA looping when LRA is using
1627 secondary reload memory again and again. */
1628 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1629 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1631 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1632 alter_subreg (curr_id
->operand_loc
[nop
], false);
1635 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1636 if there may be a problem accessing OPERAND in the outer
1639 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1640 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1641 /* Don't reload paradoxical subregs because we could be looping
1642 having repeatedly final regno out of hard regs range. */
1643 && (hard_regno_nregs
[hard_regno
][innermode
]
1644 >= hard_regno_nregs
[hard_regno
][mode
])
1645 && simplify_subreg_regno (hard_regno
, innermode
,
1646 SUBREG_BYTE (operand
), mode
) < 0
1647 /* Don't reload subreg for matching reload. It is actually
1648 valid subreg in LRA. */
1649 && ! LRA_SUBREG_P (operand
))
1650 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1652 enum reg_class rclass
;
1655 /* There is a big probability that we will get the same class
1656 for the new pseudo and we will get the same insn which
1657 means infinite looping. So spill the new pseudo. */
1660 /* The class will be defined later in curr_insn_transform. */
1662 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1664 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1665 rclass
, TRUE
, "subreg reg", &new_reg
))
1667 bool insert_before
, insert_after
;
1668 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1670 insert_before
= (type
!= OP_OUT
1671 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1672 insert_after
= (type
!= OP_IN
);
1673 insert_move_for_subreg (insert_before
? &before
: NULL
,
1674 insert_after
? &after
: NULL
,
1677 SUBREG_REG (operand
) = new_reg
;
1678 lra_process_new_insns (curr_insn
, before
, after
,
1679 "Inserting subreg reload");
1682 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1683 IRA allocates hardreg to the inner pseudo reg according to its mode
1684 instead of the outermode, so the size of the hardreg may not be enough
1685 to contain the outermode operand, in that case we may need to insert
1686 reload for the reg. For the following two types of paradoxical subreg,
1687 we need to insert reload:
1688 1. If the op_type is OP_IN, and the hardreg could not be paired with
1689 other hardreg to contain the outermode operand
1690 (checked by in_hard_reg_set_p), we need to insert the reload.
1691 2. If the op_type is OP_OUT or OP_INOUT.
1693 Here is a paradoxical subreg example showing how the reload is generated:
1695 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1696 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1698 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1699 here, if reg107 is assigned to hardreg R15, because R15 is the last
1700 hardreg, compiler cannot find another hardreg to pair with R15 to
1701 contain TImode data. So we insert a TImode reload reg180 for it.
1702 After reload is inserted:
1704 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1705 (reg:DI 107 [ __comp ])) -1
1706 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1707 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1709 Two reload hard registers will be allocated to reg180 to save TImode data
1711 else if (REG_P (reg
)
1712 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1713 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1714 && (hard_regno_nregs
[hard_regno
][innermode
]
1715 < hard_regno_nregs
[hard_regno
][mode
])
1716 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1718 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1721 /* The class will be defined later in curr_insn_transform. */
1722 enum reg_class rclass
1723 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1725 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1726 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1729 bool insert_before
, insert_after
;
1731 PUT_MODE (new_reg
, mode
);
1732 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1733 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1735 insert_before
= (type
!= OP_OUT
);
1736 insert_after
= (type
!= OP_IN
);
1737 insert_move_for_subreg (insert_before
? &before
: NULL
,
1738 insert_after
? &after
: NULL
,
1741 SUBREG_REG (operand
) = new_reg
;
1742 lra_process_new_insns (curr_insn
, before
, after
,
1743 "Inserting paradoxical subreg reload");
1749 /* Return TRUE if X refers for a hard register from SET. */
1751 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1753 int i
, j
, x_hard_regno
;
1760 code
= GET_CODE (x
);
1761 mode
= GET_MODE (x
);
1765 code
= GET_CODE (x
);
1766 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1767 mode
= GET_MODE (x
);
1772 x_hard_regno
= get_hard_regno (x
, true);
1773 return (x_hard_regno
>= 0
1774 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1778 struct address_info ad
;
1780 decompose_mem_address (&ad
, x
);
1781 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1783 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1786 fmt
= GET_RTX_FORMAT (code
);
1787 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1791 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1794 else if (fmt
[i
] == 'E')
1796 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1797 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1804 /* Return true if OP is a spilled pseudo. */
1806 spilled_pseudo_p (rtx op
)
1809 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1812 /* Return true if X is a general constant. */
1814 general_constant_p (rtx x
)
1816 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1820 reg_in_class_p (rtx reg
, enum reg_class cl
)
1823 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1824 return in_class_p (reg
, cl
, NULL
);
1827 /* Return true if SET of RCLASS contains no hard regs which can be
1830 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1832 enum machine_mode mode
)
1836 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1837 COPY_HARD_REG_SET (temp
, set
);
1838 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1839 return (hard_reg_set_subset_p
1840 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1843 /* Major function to choose the current insn alternative and what
1844 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1845 negative we should consider only this alternative. Return false if
1846 we can not choose the alternative or find how to reload the
1849 process_alt_operands (int only_alternative
)
1852 int nop
, overall
, nalt
;
1853 int n_alternatives
= curr_static_id
->n_alternatives
;
1854 int n_operands
= curr_static_id
->n_operands
;
1855 /* LOSERS counts the operands that don't fit this alternative and
1856 would require loading. */
1858 /* REJECT is a count of how undesirable this alternative says it is
1859 if any reloading is required. If the alternative matches exactly
1860 then REJECT is ignored, but otherwise it gets this much counted
1861 against it in addition to the reloading needed. */
1864 /* The number of elements in the following array. */
1865 int early_clobbered_regs_num
;
1866 /* Numbers of operands which are early clobber registers. */
1867 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1868 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1869 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1870 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1871 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1872 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1873 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1874 /* The number of elements in the following array. */
1875 int curr_alt_dont_inherit_ops_num
;
1876 /* Numbers of operands whose reload pseudos should not be inherited. */
1877 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1879 /* The register when the operand is a subreg of register, otherwise the
1881 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1882 /* The register if the operand is a register or subreg of register,
1884 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1885 int hard_regno
[MAX_RECOG_OPERANDS
];
1886 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1887 int reload_nregs
, reload_sum
;
1891 /* Calculate some data common for all alternatives to speed up the
1893 for (nop
= 0; nop
< n_operands
; nop
++)
1897 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1898 /* The real hard regno of the operand after the allocation. */
1899 hard_regno
[nop
] = get_hard_regno (op
, true);
1901 operand_reg
[nop
] = reg
= op
;
1902 biggest_mode
[nop
] = GET_MODE (op
);
1903 if (GET_CODE (op
) == SUBREG
)
1905 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1906 if (GET_MODE_SIZE (biggest_mode
[nop
])
1907 < GET_MODE_SIZE (GET_MODE (reg
)))
1908 biggest_mode
[nop
] = GET_MODE (reg
);
1911 operand_reg
[nop
] = NULL_RTX
;
1912 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1913 || ((int) REGNO (reg
)
1914 == lra_get_elimination_hard_regno (REGNO (reg
))))
1915 no_subreg_reg_operand
[nop
] = reg
;
1917 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1918 /* Just use natural mode for elimination result. It should
1919 be enough for extra constraints hooks. */
1920 = regno_reg_rtx
[hard_regno
[nop
]];
1923 /* The constraints are made of several alternatives. Each operand's
1924 constraint looks like foo,bar,... with commas separating the
1925 alternatives. The first alternatives for all operands go
1926 together, the second alternatives go together, etc.
1928 First loop over alternatives. */
1929 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1930 if (only_alternative
>= 0)
1931 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1933 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1935 /* Loop over operands for one constraint alternative. */
1936 if (!TEST_BIT (preferred
, nalt
))
1939 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1940 for (nop
= 0; nop
< n_operands
; nop
++)
1942 int inc
= (curr_static_id
1943 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1944 if (lra_dump_file
!= NULL
&& inc
!= 0)
1945 fprintf (lra_dump_file
,
1946 " Staticly defined alt reject+=%d\n", inc
);
1949 early_clobbered_regs_num
= 0;
1951 for (nop
= 0; nop
< n_operands
; nop
++)
1955 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1956 bool win
, did_match
, offmemok
, early_clobber_p
;
1957 /* false => this operand can be reloaded somehow for this
1960 /* true => this operand can be reloaded if the alternative
1963 /* True if a constant forced into memory would be OK for
1966 enum reg_class this_alternative
, this_costly_alternative
;
1967 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1968 bool this_alternative_match_win
, this_alternative_win
;
1969 bool this_alternative_offmemok
;
1972 enum constraint_num cn
;
1974 opalt_num
= nalt
* n_operands
+ nop
;
1975 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1977 /* Fast track for no constraints at all. */
1978 curr_alt
[nop
] = NO_REGS
;
1979 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1980 curr_alt_win
[nop
] = true;
1981 curr_alt_match_win
[nop
] = false;
1982 curr_alt_offmemok
[nop
] = false;
1983 curr_alt_matches
[nop
] = -1;
1987 op
= no_subreg_reg_operand
[nop
];
1988 mode
= curr_operand_mode
[nop
];
1990 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1993 early_clobber_p
= false;
1994 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1996 this_costly_alternative
= this_alternative
= NO_REGS
;
1997 /* We update set of possible hard regs besides its class
1998 because reg class might be inaccurate. For example,
1999 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2000 is translated in HI_REGS because classes are merged by
2001 pairs and there is no accurate intermediate class. */
2002 CLEAR_HARD_REG_SET (this_alternative_set
);
2003 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2004 this_alternative_win
= false;
2005 this_alternative_match_win
= false;
2006 this_alternative_offmemok
= false;
2007 this_alternative_matches
= -1;
2009 /* An empty constraint should be excluded by the fast
2011 lra_assert (*p
!= 0 && *p
!= ',');
2014 /* Scan this alternative's specs for this operand; set WIN
2015 if the operand fits any letter in this alternative.
2016 Otherwise, clear BADOP if this operand could fit some
2017 letter after reloads, or set WINREG if this operand could
2018 fit after reloads provided the constraint allows some
2023 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2033 early_clobber_p
= true;
2037 op_reject
+= LRA_MAX_REJECT
;
2040 op_reject
+= LRA_LOSER_COST_FACTOR
;
2044 /* Ignore rest of this alternative. */
2048 case '0': case '1': case '2': case '3': case '4':
2049 case '5': case '6': case '7': case '8': case '9':
2054 m
= strtoul (p
, &end
, 10);
2057 lra_assert (nop
> m
);
2059 this_alternative_matches
= m
;
2060 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2061 /* We are supposed to match a previous operand.
2062 If we do, we win if that one did. If we do
2063 not, count both of the operands as losers.
2064 (This is too conservative, since most of the
2065 time only a single reload insn will be needed
2066 to make the two operands win. As a result,
2067 this alternative may be rejected when it is
2068 actually desirable.) */
2070 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2071 *curr_id
->operand_loc
[m
], m_hregno
))
2073 /* We should reject matching of an early
2074 clobber operand if the matching operand is
2075 not dying in the insn. */
2076 if (! curr_static_id
->operand
[m
].early_clobber
2077 || operand_reg
[nop
] == NULL_RTX
2078 || (find_regno_note (curr_insn
, REG_DEAD
,
2080 || REGNO (op
) == REGNO (operand_reg
[m
])))
2085 /* If we are matching a non-offsettable
2086 address where an offsettable address was
2087 expected, then we must reject this
2088 combination, because we can't reload
2090 if (curr_alt_offmemok
[m
]
2091 && MEM_P (*curr_id
->operand_loc
[m
])
2092 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2097 /* Operands don't match. Both operands must
2098 allow a reload register, otherwise we
2099 cannot make them match. */
2100 if (curr_alt
[m
] == NO_REGS
)
2102 /* Retroactively mark the operand we had to
2103 match as a loser, if it wasn't already and
2104 it wasn't matched to a register constraint
2105 (e.g it might be matched by memory). */
2107 && (operand_reg
[m
] == NULL_RTX
2108 || hard_regno
[m
] < 0))
2112 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2113 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2116 /* Prefer matching earlyclobber alternative as
2117 it results in less hard regs required for
2118 the insn than a non-matching earlyclobber
2120 if (curr_static_id
->operand
[m
].early_clobber
)
2122 if (lra_dump_file
!= NULL
)
2125 " %d Matching earlyclobber alt:"
2130 /* Otherwise we prefer no matching
2131 alternatives because it gives more freedom
2133 else if (operand_reg
[nop
] == NULL_RTX
2134 || (find_regno_note (curr_insn
, REG_DEAD
,
2135 REGNO (operand_reg
[nop
]))
2138 if (lra_dump_file
!= NULL
)
2141 " %d Matching alt: reject+=2\n",
2146 /* If we have to reload this operand and some
2147 previous operand also had to match the same
2148 thing as this operand, we don't know how to do
2150 if (!match_p
|| !curr_alt_win
[m
])
2152 for (i
= 0; i
< nop
; i
++)
2153 if (curr_alt_matches
[i
] == m
)
2161 /* This can be fixed with reloads if the operand
2162 we are supposed to match can be fixed with
2165 this_alternative
= curr_alt
[m
];
2166 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2167 winreg
= this_alternative
!= NO_REGS
;
2173 || general_constant_p (op
)
2174 || spilled_pseudo_p (op
))
2180 cn
= lookup_constraint (p
);
2181 switch (get_constraint_type (cn
))
2184 cl
= reg_class_for_constraint (cn
);
2190 if (CONST_INT_P (op
)
2191 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2197 && satisfies_memory_constraint_p (op
, cn
))
2199 else if (spilled_pseudo_p (op
))
2202 /* If we didn't already win, we can reload constants
2203 via force_const_mem or put the pseudo value into
2204 memory, or make other memory by reloading the
2205 address like for 'o'. */
2206 if (CONST_POOL_OK_P (mode
, op
)
2207 || MEM_P (op
) || REG_P (op
)
2208 /* We can restore the equiv insn by a
2210 || equiv_substition_p
[nop
])
2217 /* If we didn't already win, we can reload the address
2218 into a base register. */
2219 if (satisfies_address_constraint_p (op
, cn
))
2221 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2227 if (constraint_satisfied_p (op
, cn
))
2231 case CT_SPECIAL_MEMORY
:
2233 && satisfies_memory_constraint_p (op
, cn
))
2235 else if (spilled_pseudo_p (op
))
2242 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2243 IOR_HARD_REG_SET (this_alternative_set
,
2244 reg_class_contents
[cl
]);
2247 this_costly_alternative
2248 = reg_class_subunion
[this_costly_alternative
][cl
];
2249 IOR_HARD_REG_SET (this_costly_alternative_set
,
2250 reg_class_contents
[cl
]);
2252 if (mode
== BLKmode
)
2257 if (hard_regno
[nop
] >= 0
2258 && in_hard_reg_set_p (this_alternative_set
,
2259 mode
, hard_regno
[nop
]))
2261 else if (hard_regno
[nop
] < 0
2262 && in_class_p (op
, this_alternative
, NULL
))
2267 if (c
!= ' ' && c
!= '\t')
2268 costly_p
= c
== '*';
2270 while ((p
+= len
), c
);
2272 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2273 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2274 /* Record which operands fit this alternative. */
2277 this_alternative_win
= true;
2278 if (operand_reg
[nop
] != NULL_RTX
)
2280 if (hard_regno
[nop
] >= 0)
2282 if (in_hard_reg_set_p (this_costly_alternative_set
,
2283 mode
, hard_regno
[nop
]))
2285 if (lra_dump_file
!= NULL
)
2286 fprintf (lra_dump_file
,
2287 " %d Costly set: reject++\n",
2294 /* Prefer won reg to spilled pseudo under other
2295 equal conditions for possibe inheritance. */
2298 if (lra_dump_file
!= NULL
)
2301 " %d Non pseudo reload: reject++\n",
2305 if (in_class_p (operand_reg
[nop
],
2306 this_costly_alternative
, NULL
))
2308 if (lra_dump_file
!= NULL
)
2311 " %d Non pseudo costly reload:"
2317 /* We simulate the behavior of old reload here.
2318 Although scratches need hard registers and it
2319 might result in spilling other pseudos, no reload
2320 insns are generated for the scratches. So it
2321 might cost something but probably less than old
2322 reload pass believes. */
2325 if (lra_dump_file
!= NULL
)
2326 fprintf (lra_dump_file
,
2327 " %d Scratch win: reject+=2\n",
2334 this_alternative_match_win
= true;
2337 int const_to_mem
= 0;
2340 reject
+= op_reject
;
2341 /* Never do output reload of stack pointer. It makes
2342 impossible to do elimination when SP is changed in
2344 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2345 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2348 /* If this alternative asks for a specific reg class, see if there
2349 is at least one allocatable register in that class. */
2351 = (this_alternative
== NO_REGS
2352 || (hard_reg_set_subset_p
2353 (reg_class_contents
[this_alternative
],
2354 lra_no_alloc_regs
)));
2356 /* For asms, verify that the class for this alternative is possible
2357 for the mode that is specified. */
2358 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2361 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2362 if (HARD_REGNO_MODE_OK (i
, mode
)
2363 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2366 if (i
== FIRST_PSEUDO_REGISTER
)
2370 /* If this operand accepts a register, and if the
2371 register class has at least one allocatable register,
2372 then this operand can be reloaded. */
2373 if (winreg
&& !no_regs_p
)
2378 if (lra_dump_file
!= NULL
)
2379 fprintf (lra_dump_file
,
2380 " alt=%d: Bad operand -- refuse\n",
2385 if (this_alternative
!= NO_REGS
)
2387 HARD_REG_SET available_regs
;
2389 COPY_HARD_REG_SET (available_regs
,
2390 reg_class_contents
[this_alternative
]);
2391 AND_COMPL_HARD_REG_SET
2393 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2394 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2395 if (hard_reg_set_empty_p (available_regs
))
2397 /* There are no hard regs holding a value of given
2401 this_alternative
= NO_REGS
;
2402 if (lra_dump_file
!= NULL
)
2403 fprintf (lra_dump_file
,
2404 " %d Using memory because of"
2405 " a bad mode: reject+=2\n",
2411 if (lra_dump_file
!= NULL
)
2412 fprintf (lra_dump_file
,
2413 " alt=%d: Wrong mode -- refuse\n",
2420 /* If not assigned pseudo has a class which a subset of
2421 required reg class, it is a less costly alternative
2422 as the pseudo still can get a hard reg of necessary
2424 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2425 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2426 && ira_class_subset_p
[this_alternative
][cl
])
2428 if (lra_dump_file
!= NULL
)
2431 " %d Super set class reg: reject-=3\n", nop
);
2435 this_alternative_offmemok
= offmemok
;
2436 if (this_costly_alternative
!= NO_REGS
)
2438 if (lra_dump_file
!= NULL
)
2439 fprintf (lra_dump_file
,
2440 " %d Costly loser: reject++\n", nop
);
2443 /* If the operand is dying, has a matching constraint,
2444 and satisfies constraints of the matched operand
2445 which failed to satisfy the own constraints, most probably
2446 the reload for this operand will be gone. */
2447 if (this_alternative_matches
>= 0
2448 && !curr_alt_win
[this_alternative_matches
]
2450 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2451 && (hard_regno
[nop
] >= 0
2452 ? in_hard_reg_set_p (this_alternative_set
,
2453 mode
, hard_regno
[nop
])
2454 : in_class_p (op
, this_alternative
, NULL
)))
2456 if (lra_dump_file
!= NULL
)
2459 " %d Dying matched operand reload: reject++\n",
2465 /* Strict_low_part requires to reload the register
2466 not the sub-register. In this case we should
2467 check that a final reload hard reg can hold the
2469 if (curr_static_id
->operand
[nop
].strict_low
2471 && hard_regno
[nop
] < 0
2472 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2473 && ira_class_hard_regs_num
[this_alternative
] > 0
2474 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2475 [this_alternative
][0],
2477 (*curr_id
->operand_loc
[nop
])))
2479 if (lra_dump_file
!= NULL
)
2482 " alt=%d: Strict low subreg reload -- refuse\n",
2488 if (operand_reg
[nop
] != NULL_RTX
2489 /* Output operands and matched input operands are
2490 not inherited. The following conditions do not
2491 exactly describe the previous statement but they
2492 are pretty close. */
2493 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2494 && (this_alternative_matches
< 0
2495 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2497 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2501 /* The value of reload_sum has sense only if we
2502 process insns in their order. It happens only on
2503 the first constraints sub-pass when we do most of
2505 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2506 reload_sum
+= last_reload
- bb_reload_num
;
2508 /* If this is a constant that is reloaded into the
2509 desired class by copying it to memory first, count
2510 that as another reload. This is consistent with
2511 other code and is required to avoid choosing another
2512 alternative when the constant is moved into memory.
2513 Note that the test here is precisely the same as in
2514 the code below that calls force_const_mem. */
2515 if (CONST_POOL_OK_P (mode
, op
)
2516 && ((targetm
.preferred_reload_class
2517 (op
, this_alternative
) == NO_REGS
)
2518 || no_input_reloads_p
))
2525 /* Alternative loses if it requires a type of reload not
2526 permitted for this insn. We can always reload
2527 objects with a REG_UNUSED note. */
2528 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2529 && no_output_reloads_p
2530 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2531 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2532 && no_input_reloads_p
&& ! const_to_mem
)
2533 || (this_alternative_matches
>= 0
2534 && (no_input_reloads_p
2535 || (no_output_reloads_p
2536 && (curr_static_id
->operand
2537 [this_alternative_matches
].type
!= OP_IN
)
2538 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2539 no_subreg_reg_operand
2540 [this_alternative_matches
])))))
2542 if (lra_dump_file
!= NULL
)
2545 " alt=%d: No input/otput reload -- refuse\n",
2550 /* Alternative loses if it required class pseudo can not
2551 hold value of required mode. Such insns can be
2552 described by insn definitions with mode iterators. */
2553 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2554 && ! hard_reg_set_empty_p (this_alternative_set
)
2555 /* It is common practice for constraints to use a
2556 class which does not have actually enough regs to
2557 hold the value (e.g. x86 AREG for mode requiring
2558 more one general reg). Therefore we have 2
2559 conditions to check that the reload pseudo can
2560 not hold the mode value. */
2561 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2562 [this_alternative
][0],
2563 GET_MODE (*curr_id
->operand_loc
[nop
]))
2564 /* The above condition is not enough as the first
2565 reg in ira_class_hard_regs can be not aligned for
2566 multi-words mode values. */
2567 && (prohibited_class_reg_set_mode_p
2568 (this_alternative
, this_alternative_set
,
2569 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2571 if (lra_dump_file
!= NULL
)
2572 fprintf (lra_dump_file
,
2573 " alt=%d: reload pseudo for op %d "
2574 " can not hold the mode value -- refuse\n",
2579 /* Check strong discouragement of reload of non-constant
2580 into class THIS_ALTERNATIVE. */
2581 if (! CONSTANT_P (op
) && ! no_regs_p
2582 && (targetm
.preferred_reload_class
2583 (op
, this_alternative
) == NO_REGS
2584 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2585 && (targetm
.preferred_output_reload_class
2586 (op
, this_alternative
) == NO_REGS
))))
2588 if (lra_dump_file
!= NULL
)
2589 fprintf (lra_dump_file
,
2590 " %d Non-prefered reload: reject+=%d\n",
2591 nop
, LRA_MAX_REJECT
);
2592 reject
+= LRA_MAX_REJECT
;
2595 if (! (MEM_P (op
) && offmemok
)
2596 && ! (const_to_mem
&& constmemok
))
2598 /* We prefer to reload pseudos over reloading other
2599 things, since such reloads may be able to be
2600 eliminated later. So bump REJECT in other cases.
2601 Don't do this in the case where we are forcing a
2602 constant into memory and it will then win since
2603 we don't want to have a different alternative
2605 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2607 if (lra_dump_file
!= NULL
)
2610 " %d Non-pseudo reload: reject+=2\n",
2617 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2619 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2621 if (lra_dump_file
!= NULL
)
2624 " %d Small class reload: reject+=%d\n",
2625 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2626 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2630 /* We are trying to spill pseudo into memory. It is
2631 usually more costly than moving to a hard register
2632 although it might takes the same number of
2635 Non-pseudo spill may happen also. Suppose a target allows both
2636 register and memory in the operand constraint alternatives,
2637 then it's typical that an eliminable register has a substition
2638 of "base + offset" which can either be reloaded by a simple
2639 "new_reg <= base + offset" which will match the register
2640 constraint, or a similar reg addition followed by further spill
2641 to and reload from memory which will match the memory
2642 constraint, but this memory spill will be much more costly
2645 Code below increases the reject for both pseudo and non-pseudo
2648 && !(MEM_P (op
) && offmemok
)
2649 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2651 if (lra_dump_file
!= NULL
)
2654 " %d Spill %spseudo into memory: reject+=3\n",
2655 nop
, REG_P (op
) ? "" : "Non-");
2657 if (VECTOR_MODE_P (mode
))
2659 /* Spilling vectors into memory is usually more
2660 costly as they contain big values. */
2661 if (lra_dump_file
!= NULL
)
2664 " %d Spill vector pseudo: reject+=2\n",
2670 #ifdef SECONDARY_MEMORY_NEEDED
2671 /* If reload requires moving value through secondary
2672 memory, it will need one more insn at least. */
2673 if (this_alternative
!= NO_REGS
2674 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2675 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2676 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2678 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2679 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2683 /* Input reloads can be inherited more often than output
2684 reloads can be removed, so penalize output
2686 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2688 if (lra_dump_file
!= NULL
)
2691 " %d Non input pseudo reload: reject++\n",
2697 if (early_clobber_p
&& ! scratch_p
)
2699 if (lra_dump_file
!= NULL
)
2700 fprintf (lra_dump_file
,
2701 " %d Early clobber: reject++\n", nop
);
2704 /* ??? We check early clobbers after processing all operands
2705 (see loop below) and there we update the costs more.
2706 Should we update the cost (may be approximately) here
2707 because of early clobber register reloads or it is a rare
2708 or non-important thing to be worth to do it. */
2709 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2710 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2712 if (lra_dump_file
!= NULL
)
2713 fprintf (lra_dump_file
,
2714 " alt=%d,overall=%d,losers=%d -- refuse\n",
2715 nalt
, overall
, losers
);
2719 curr_alt
[nop
] = this_alternative
;
2720 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2721 curr_alt_win
[nop
] = this_alternative_win
;
2722 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2723 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2724 curr_alt_matches
[nop
] = this_alternative_matches
;
2726 if (this_alternative_matches
>= 0
2727 && !did_match
&& !this_alternative_win
)
2728 curr_alt_win
[this_alternative_matches
] = false;
2730 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2731 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2733 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2734 /* Prevent processing non-move insns. */
2735 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2736 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2737 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2738 && REG_P (no_subreg_reg_operand
[0])
2739 && REG_P (no_subreg_reg_operand
[1])
2740 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2741 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2742 || (! curr_alt_win
[0] && curr_alt_win
[1]
2743 && REG_P (no_subreg_reg_operand
[1])
2744 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2745 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2746 && REG_P (no_subreg_reg_operand
[0])
2747 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2748 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2749 no_subreg_reg_operand
[1])
2750 || (targetm
.preferred_reload_class
2751 (no_subreg_reg_operand
[1],
2752 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2753 /* If it is a result of recent elimination in move
2754 insn we can transform it into an add still by
2755 using this alternative. */
2756 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2758 /* We have a move insn and a new reload insn will be similar
2759 to the current insn. We should avoid such situation as it
2760 results in LRA cycling. */
2761 overall
+= LRA_MAX_REJECT
;
2764 curr_alt_dont_inherit_ops_num
= 0;
2765 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2767 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2768 HARD_REG_SET temp_set
;
2770 i
= early_clobbered_nops
[nop
];
2771 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2772 || hard_regno
[i
] < 0)
2774 lra_assert (operand_reg
[i
] != NULL_RTX
);
2775 clobbered_hard_regno
= hard_regno
[i
];
2776 CLEAR_HARD_REG_SET (temp_set
);
2777 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2778 first_conflict_j
= last_conflict_j
= -1;
2779 for (j
= 0; j
< n_operands
; j
++)
2781 /* We don't want process insides of match_operator and
2782 match_parallel because otherwise we would process
2783 their operands once again generating a wrong
2785 || curr_static_id
->operand
[j
].is_operator
)
2787 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2788 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2790 /* If we don't reload j-th operand, check conflicts. */
2791 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2792 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2794 if (first_conflict_j
< 0)
2795 first_conflict_j
= j
;
2796 last_conflict_j
= j
;
2798 if (last_conflict_j
< 0)
2800 /* If earlyclobber operand conflicts with another
2801 non-matching operand which is actually the same register
2802 as the earlyclobber operand, it is better to reload the
2803 another operand as an operand matching the earlyclobber
2804 operand can be also the same. */
2805 if (first_conflict_j
== last_conflict_j
2806 && operand_reg
[last_conflict_j
] != NULL_RTX
2807 && ! curr_alt_match_win
[last_conflict_j
]
2808 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2810 curr_alt_win
[last_conflict_j
] = false;
2811 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2814 /* Early clobber was already reflected in REJECT. */
2815 lra_assert (reject
> 0);
2816 if (lra_dump_file
!= NULL
)
2819 " %d Conflict early clobber reload: reject--\n",
2822 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2826 /* We need to reload early clobbered register and the
2827 matched registers. */
2828 for (j
= 0; j
< n_operands
; j
++)
2829 if (curr_alt_matches
[j
] == i
)
2831 curr_alt_match_win
[j
] = false;
2833 overall
+= LRA_LOSER_COST_FACTOR
;
2835 if (! curr_alt_match_win
[i
])
2836 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2839 /* Remember pseudos used for match reloads are never
2841 lra_assert (curr_alt_matches
[i
] >= 0);
2842 curr_alt_win
[curr_alt_matches
[i
]] = false;
2844 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2846 /* Early clobber was already reflected in REJECT. */
2847 lra_assert (reject
> 0);
2848 if (lra_dump_file
!= NULL
)
2851 " %d Matched conflict early clobber reloads: "
2855 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2858 if (lra_dump_file
!= NULL
)
2859 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2860 nalt
, overall
, losers
, reload_nregs
);
2862 /* If this alternative can be made to work by reloading, and it
2863 needs less reloading than the others checked so far, record
2864 it as the chosen goal for reloading. */
2865 if ((best_losers
!= 0 && losers
== 0)
2866 || (((best_losers
== 0 && losers
== 0)
2867 || (best_losers
!= 0 && losers
!= 0))
2868 && (best_overall
> overall
2869 || (best_overall
== overall
2870 /* If the cost of the reloads is the same,
2871 prefer alternative which requires minimal
2872 number of reload regs. */
2873 && (reload_nregs
< best_reload_nregs
2874 || (reload_nregs
== best_reload_nregs
2875 && (best_reload_sum
< reload_sum
2876 || (best_reload_sum
== reload_sum
2877 && nalt
< goal_alt_number
))))))))
2879 for (nop
= 0; nop
< n_operands
; nop
++)
2881 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2882 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2883 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2884 goal_alt
[nop
] = curr_alt
[nop
];
2885 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2887 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2888 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2889 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2890 goal_alt_swapped
= curr_swapped
;
2891 best_overall
= overall
;
2892 best_losers
= losers
;
2893 best_reload_nregs
= reload_nregs
;
2894 best_reload_sum
= reload_sum
;
2895 goal_alt_number
= nalt
;
2898 /* Everything is satisfied. Do not process alternatives
2907 /* Make reload base reg from address AD. */
2909 base_to_reg (struct address_info
*ad
)
2913 rtx new_inner
= NULL_RTX
;
2914 rtx new_reg
= NULL_RTX
;
2916 rtx_insn
*last_insn
= get_last_insn();
2918 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2919 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2920 get_index_code (ad
));
2921 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2923 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2924 ad
->disp_term
== NULL
2925 ? gen_int_mode (0, ad
->mode
)
2927 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2929 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base_term
));
2930 code
= recog_memoized (insn
);
2933 delete_insns_since (last_insn
);
2940 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2942 base_plus_disp_to_reg (struct address_info
*ad
)
2947 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2948 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2949 get_index_code (ad
));
2950 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2952 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2956 /* Make reload of index part of address AD. Return the new
2959 index_part_to_reg (struct address_info
*ad
)
2963 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2964 INDEX_REG_CLASS
, "index term");
2965 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2966 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2970 /* Return true if we can add a displacement to address AD, even if that
2971 makes the address invalid. The fix-up code requires any new address
2972 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2974 can_add_disp_p (struct address_info
*ad
)
2976 return (!ad
->autoinc_p
2977 && ad
->segment
== NULL
2978 && ad
->base
== ad
->base_term
2979 && ad
->disp
== ad
->disp_term
);
2982 /* Make equiv substitution in address AD. Return true if a substitution
2985 equiv_address_substitution (struct address_info
*ad
)
2987 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2988 HOST_WIDE_INT disp
, scale
;
2991 base_term
= strip_subreg (ad
->base_term
);
2992 if (base_term
== NULL
)
2993 base_reg
= new_base_reg
= NULL_RTX
;
2996 base_reg
= *base_term
;
2997 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2999 index_term
= strip_subreg (ad
->index_term
);
3000 if (index_term
== NULL
)
3001 index_reg
= new_index_reg
= NULL_RTX
;
3004 index_reg
= *index_term
;
3005 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3007 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3011 if (lra_dump_file
!= NULL
)
3013 fprintf (lra_dump_file
, "Changing address in insn %d ",
3014 INSN_UID (curr_insn
));
3015 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3017 if (base_reg
!= new_base_reg
)
3019 if (REG_P (new_base_reg
))
3021 *base_term
= new_base_reg
;
3024 else if (GET_CODE (new_base_reg
) == PLUS
3025 && REG_P (XEXP (new_base_reg
, 0))
3026 && CONST_INT_P (XEXP (new_base_reg
, 1))
3027 && can_add_disp_p (ad
))
3029 disp
+= INTVAL (XEXP (new_base_reg
, 1));
3030 *base_term
= XEXP (new_base_reg
, 0);
3033 if (ad
->base_term2
!= NULL
)
3034 *ad
->base_term2
= *ad
->base_term
;
3036 if (index_reg
!= new_index_reg
)
3038 if (REG_P (new_index_reg
))
3040 *index_term
= new_index_reg
;
3043 else if (GET_CODE (new_index_reg
) == PLUS
3044 && REG_P (XEXP (new_index_reg
, 0))
3045 && CONST_INT_P (XEXP (new_index_reg
, 1))
3046 && can_add_disp_p (ad
)
3047 && (scale
= get_index_scale (ad
)))
3049 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
3050 *index_term
= XEXP (new_index_reg
, 0);
3056 if (ad
->disp
!= NULL
)
3057 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3060 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3061 update_address (ad
);
3065 if (lra_dump_file
!= NULL
)
3068 fprintf (lra_dump_file
, " -- no change\n");
3071 fprintf (lra_dump_file
, " on equiv ");
3072 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3073 fprintf (lra_dump_file
, "\n");
3079 /* Major function to make reloads for an address in operand NOP or
3080 check its correctness (If CHECK_ONLY_P is true). The supported
3083 1) an address that existed before LRA started, at which point it
3084 must have been valid. These addresses are subject to elimination
3085 and may have become invalid due to the elimination offset being out
3088 2) an address created by forcing a constant to memory
3089 (force_const_to_mem). The initial form of these addresses might
3090 not be valid, and it is this function's job to make them valid.
3092 3) a frame address formed from a register and a (possibly zero)
3093 constant offset. As above, these addresses might not be valid and
3094 this function must make them so.
3096 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3097 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3098 address. Return true for any RTL change.
3100 The function is a helper function which does not produce all
3101 transformations (when CHECK_ONLY_P is false) which can be
3102 necessary. It does just basic steps. To do all necessary
3103 transformations use function process_address. */
3105 process_address_1 (int nop
, bool check_only_p
,
3106 rtx_insn
**before
, rtx_insn
**after
)
3108 struct address_info ad
;
3110 HOST_WIDE_INT scale
;
3111 rtx op
= *curr_id
->operand_loc
[nop
];
3112 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3113 enum constraint_num cn
= lookup_constraint (constraint
);
3114 bool change_p
= false;
3117 && GET_MODE (op
) == BLKmode
3118 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3121 if (insn_extra_address_constraint (cn
))
3122 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3123 /* Do not attempt to decompose arbitrary addresses generated by combine
3124 for asm operands with loose constraints, e.g 'X'. */
3126 && !(get_constraint_type (cn
) == CT_FIXED_FORM
3127 && constraint_satisfied_p (op
, cn
)))
3128 decompose_mem_address (&ad
, op
);
3129 else if (GET_CODE (op
) == SUBREG
3130 && MEM_P (SUBREG_REG (op
)))
3131 decompose_mem_address (&ad
, SUBREG_REG (op
));
3134 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3135 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3136 when INDEX_REG_CLASS is a single register class. */
3137 if (ad
.base_term
!= NULL
3138 && ad
.index_term
!= NULL
3139 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3140 && REG_P (*ad
.base_term
)
3141 && REG_P (*ad
.index_term
)
3142 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3143 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3145 std::swap (ad
.base
, ad
.index
);
3146 std::swap (ad
.base_term
, ad
.index_term
);
3149 change_p
= equiv_address_substitution (&ad
);
3150 if (ad
.base_term
!= NULL
3151 && (process_addr_reg
3152 (ad
.base_term
, check_only_p
, before
,
3154 && !(REG_P (*ad
.base_term
)
3155 && find_regno_note (curr_insn
, REG_DEAD
,
3156 REGNO (*ad
.base_term
)) != NULL_RTX
)
3158 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3159 get_index_code (&ad
)))))
3162 if (ad
.base_term2
!= NULL
)
3163 *ad
.base_term2
= *ad
.base_term
;
3165 if (ad
.index_term
!= NULL
3166 && process_addr_reg (ad
.index_term
, check_only_p
,
3167 before
, NULL
, INDEX_REG_CLASS
))
3170 /* Target hooks sometimes don't treat extra-constraint addresses as
3171 legitimate address_operands, so handle them specially. */
3172 if (insn_extra_address_constraint (cn
)
3173 && satisfies_address_constraint_p (&ad
, cn
))
3179 /* There are three cases where the shape of *AD.INNER may now be invalid:
3181 1) the original address was valid, but either elimination or
3182 equiv_address_substitution was applied and that made
3183 the address invalid.
3185 2) the address is an invalid symbolic address created by
3188 3) the address is a frame address with an invalid offset.
3190 4) the address is a frame address with an invalid base.
3192 All these cases involve a non-autoinc address, so there is no
3193 point revalidating other types. */
3194 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3197 /* Any index existed before LRA started, so we can assume that the
3198 presence and shape of the index is valid. */
3199 push_to_sequence (*before
);
3200 lra_assert (ad
.disp
== ad
.disp_term
);
3201 if (ad
.base
== NULL
)
3203 if (ad
.index
== NULL
)
3206 rtx_insn
*last
= get_last_insn ();
3208 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3210 rtx addr
= *ad
.inner
;
3212 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3215 /* addr => lo_sum (new_base, addr), case (2) above. */
3216 insn
= emit_insn (gen_rtx_SET
3218 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3219 code
= recog_memoized (insn
);
3222 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3223 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3225 /* Try to put lo_sum into register. */
3226 insn
= emit_insn (gen_rtx_SET
3228 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3229 code
= recog_memoized (insn
);
3232 *ad
.inner
= new_reg
;
3233 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3243 delete_insns_since (last
);
3248 /* addr => new_base, case (2) above. */
3249 lra_emit_move (new_reg
, addr
);
3251 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3253 insn
= NEXT_INSN (insn
))
3254 if (recog_memoized (insn
) < 0)
3256 if (insn
!= NULL_RTX
)
3258 /* Do nothing if we cannot generate right insns.
3259 This is analogous to reload pass behavior. */
3260 delete_insns_since (last
);
3264 *ad
.inner
= new_reg
;
3269 /* index * scale + disp => new base + index * scale,
3271 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3272 GET_CODE (*ad
.index
));
3274 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3275 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3276 lra_emit_move (new_reg
, *ad
.disp
);
3277 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3278 new_reg
, *ad
.index
);
3281 else if (ad
.index
== NULL
)
3286 rtx_insn
*insns
, *last_insn
;
3287 /* Try to reload base into register only if the base is invalid
3288 for the address but with valid offset, case (4) above. */
3290 new_reg
= base_to_reg (&ad
);
3292 /* base + disp => new base, cases (1) and (3) above. */
3293 /* Another option would be to reload the displacement into an
3294 index register. However, postreload has code to optimize
3295 address reloads that have the same base and different
3296 displacements, so reloading into an index register would
3297 not necessarily be a win. */
3298 if (new_reg
== NULL_RTX
)
3299 new_reg
= base_plus_disp_to_reg (&ad
);
3300 insns
= get_insns ();
3301 last_insn
= get_last_insn ();
3302 /* If we generated at least two insns, try last insn source as
3303 an address. If we succeed, we generate one less insn. */
3304 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3305 && GET_CODE (SET_SRC (set
)) == PLUS
3306 && REG_P (XEXP (SET_SRC (set
), 0))
3307 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3309 *ad
.inner
= SET_SRC (set
);
3310 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3312 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3313 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3314 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3315 get_index_code (&ad
));
3316 regno
= REGNO (*ad
.base_term
);
3317 if (regno
>= FIRST_PSEUDO_REGISTER
3318 && cl
!= lra_get_allocno_class (regno
))
3319 lra_change_class (regno
, cl
, " Change to", true);
3320 new_reg
= SET_SRC (set
);
3321 delete_insns_since (PREV_INSN (last_insn
));
3324 /* Try if target can split displacement into legitimite new disp
3325 and offset. If it's the case, we replace the last insn with
3326 insns for base + offset => new_reg and set new_reg + new disp
3328 last_insn
= get_last_insn ();
3329 if ((set
= single_set (last_insn
)) != NULL_RTX
3330 && GET_CODE (SET_SRC (set
)) == PLUS
3331 && REG_P (XEXP (SET_SRC (set
), 0))
3332 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3333 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3335 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3336 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3339 rtx_insn
*new_insns
;
3341 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3342 new_insns
= get_insns ();
3344 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3345 delete_insns_since (PREV_INSN (last_insn
));
3346 add_insn (new_insns
);
3347 insns
= get_insns ();
3352 *ad
.inner
= new_reg
;
3354 else if (ad
.disp_term
!= NULL
)
3356 /* base + scale * index + disp => new base + scale * index,
3358 new_reg
= base_plus_disp_to_reg (&ad
);
3359 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3360 new_reg
, *ad
.index
);
3362 else if ((scale
= get_index_scale (&ad
)) == 1)
3364 /* The last transformation to one reg will be made in
3365 curr_insn_transform function. */
3369 else if (scale
!= 0)
3371 /* base + scale * index => base + new_reg,
3373 Index part of address may become invalid. For example, we
3374 changed pseudo on the equivalent memory and a subreg of the
3375 pseudo onto the memory of different mode for which the scale is
3377 new_reg
= index_part_to_reg (&ad
);
3378 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3379 *ad
.base_term
, new_reg
);
3383 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3385 rtx addr
= *ad
.inner
;
3387 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3388 /* addr => new_base. */
3389 lra_emit_move (new_reg
, addr
);
3390 *ad
.inner
= new_reg
;
3392 *before
= get_insns ();
3397 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3398 Use process_address_1 as a helper function. Return true for any
3401 If CHECK_ONLY_P is true, just check address correctness. Return
3402 false if the address correct. */
3404 process_address (int nop
, bool check_only_p
,
3405 rtx_insn
**before
, rtx_insn
**after
)
3409 while (process_address_1 (nop
, check_only_p
, before
, after
))
3418 /* Emit insns to reload VALUE into a new register. VALUE is an
3419 auto-increment or auto-decrement RTX whose operand is a register or
3420 memory location; so reloading involves incrementing that location.
3421 IN is either identical to VALUE, or some cheaper place to reload
3422 value being incremented/decremented from.
3424 INC_AMOUNT is the number to increment or decrement by (always
3425 positive and ignored for POST_MODIFY/PRE_MODIFY).
3427 Return pseudo containing the result. */
3429 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3431 /* REG or MEM to be copied and incremented. */
3432 rtx incloc
= XEXP (value
, 0);
3433 /* Nonzero if increment after copying. */
3434 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3435 || GET_CODE (value
) == POST_MODIFY
);
3440 rtx real_in
= in
== value
? incloc
: in
;
3444 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3446 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3447 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3448 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3449 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3450 inc
= XEXP (XEXP (value
, 1), 1);
3454 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3455 inc_amount
= -inc_amount
;
3457 inc
= GEN_INT (inc_amount
);
3460 if (! post
&& REG_P (incloc
))
3463 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3466 if (real_in
!= result
)
3468 /* First copy the location to the result register. */
3469 lra_assert (REG_P (result
));
3470 emit_insn (gen_move_insn (result
, real_in
));
3473 /* We suppose that there are insns to add/sub with the constant
3474 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3475 old reload worked with this assumption. If the assumption
3476 becomes wrong, we should use approach in function
3477 base_plus_disp_to_reg. */
3480 /* See if we can directly increment INCLOC. */
3481 last
= get_last_insn ();
3482 add_insn
= emit_insn (plus_p
3483 ? gen_add2_insn (incloc
, inc
)
3484 : gen_sub2_insn (incloc
, inc
));
3486 code
= recog_memoized (add_insn
);
3489 if (! post
&& result
!= incloc
)
3490 emit_insn (gen_move_insn (result
, incloc
));
3493 delete_insns_since (last
);
3496 /* If couldn't do the increment directly, must increment in RESULT.
3497 The way we do this depends on whether this is pre- or
3498 post-increment. For pre-increment, copy INCLOC to the reload
3499 register, increment it there, then save back. */
3502 if (real_in
!= result
)
3503 emit_insn (gen_move_insn (result
, real_in
));
3505 emit_insn (gen_add2_insn (result
, inc
));
3507 emit_insn (gen_sub2_insn (result
, inc
));
3508 if (result
!= incloc
)
3509 emit_insn (gen_move_insn (incloc
, result
));
3515 Because this might be a jump insn or a compare, and because
3516 RESULT may not be available after the insn in an input
3517 reload, we must do the incrementing before the insn being
3520 We have already copied IN to RESULT. Increment the copy in
3521 RESULT, save that back, then decrement RESULT so it has
3522 the original value. */
3524 emit_insn (gen_add2_insn (result
, inc
));
3526 emit_insn (gen_sub2_insn (result
, inc
));
3527 emit_insn (gen_move_insn (incloc
, result
));
3528 /* Restore non-modified value for the result. We prefer this
3529 way because it does not require an additional hard
3533 if (CONST_INT_P (inc
))
3534 emit_insn (gen_add2_insn (result
,
3535 gen_int_mode (-INTVAL (inc
),
3536 GET_MODE (result
))));
3538 emit_insn (gen_sub2_insn (result
, inc
));
3541 emit_insn (gen_add2_insn (result
, inc
));
3546 /* Return true if the current move insn does not need processing as we
3547 already know that it satisfies its constraints. */
3549 simple_move_p (void)
3552 enum reg_class dclass
, sclass
;
3554 lra_assert (curr_insn_set
!= NULL_RTX
);
3555 dest
= SET_DEST (curr_insn_set
);
3556 src
= SET_SRC (curr_insn_set
);
3558 /* If the instruction has multiple sets we need to process it even if it
3559 is single_set. This can happen if one or more of the SETs are dead.
3561 if (multiple_sets (curr_insn
))
3564 return ((dclass
= get_op_class (dest
)) != NO_REGS
3565 && (sclass
= get_op_class (src
)) != NO_REGS
3566 /* The backend guarantees that register moves of cost 2
3567 never need reloads. */
3568 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3571 /* Swap operands NOP and NOP + 1. */
3573 swap_operands (int nop
)
3575 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3576 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3577 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3578 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3579 /* Swap the duplicates too. */
3580 lra_update_dup (curr_id
, nop
);
3581 lra_update_dup (curr_id
, nop
+ 1);
3584 /* Main entry point of the constraint code: search the body of the
3585 current insn to choose the best alternative. It is mimicking insn
3586 alternative cost calculation model of former reload pass. That is
3587 because machine descriptions were written to use this model. This
3588 model can be changed in future. Make commutative operand exchange
3591 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3592 constraints. Return true if any change happened during function
3595 If CHECK_ONLY_P is true then don't do any transformation. Just
3596 check that the insn satisfies all constraints. If the insn does
3597 not satisfy any constraint, return true. */
3599 curr_insn_transform (bool check_only_p
)
3606 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3607 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3608 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3609 rtx_insn
*before
, *after
;
3611 /* Flag that the insn has been changed through a transformation. */
3614 #ifdef SECONDARY_MEMORY_NEEDED
3617 int max_regno_before
;
3618 int reused_alternative_num
;
3620 curr_insn_set
= single_set (curr_insn
);
3621 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3624 no_input_reloads_p
= no_output_reloads_p
= false;
3625 goal_alt_number
= -1;
3626 change_p
= sec_mem_p
= false;
3627 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3628 reloads; neither are insns that SET cc0. Insns that use CC0 are
3629 not allowed to have any input reloads. */
3630 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3631 no_output_reloads_p
= true;
3633 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3634 no_input_reloads_p
= true;
3635 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3636 no_output_reloads_p
= true;
3638 n_operands
= curr_static_id
->n_operands
;
3639 n_alternatives
= curr_static_id
->n_alternatives
;
3641 /* Just return "no reloads" if insn has no operands with
3643 if (n_operands
== 0 || n_alternatives
== 0)
3646 max_regno_before
= max_reg_num ();
3648 for (i
= 0; i
< n_operands
; i
++)
3650 goal_alt_matched
[i
][0] = -1;
3651 goal_alt_matches
[i
] = -1;
3654 commutative
= curr_static_id
->commutative
;
3656 /* Now see what we need for pseudos that didn't get hard regs or got
3657 the wrong kind of hard reg. For this, we must consider all the
3658 operands together against the register constraints. */
3660 best_losers
= best_overall
= INT_MAX
;
3661 best_reload_sum
= 0;
3663 curr_swapped
= false;
3664 goal_alt_swapped
= false;
3667 /* Make equivalence substitution and memory subreg elimination
3668 before address processing because an address legitimacy can
3669 depend on memory mode. */
3670 for (i
= 0; i
< n_operands
; i
++)
3673 bool op_change_p
= false;
3675 if (curr_static_id
->operand
[i
].is_operator
)
3678 old
= op
= *curr_id
->operand_loc
[i
];
3679 if (GET_CODE (old
) == SUBREG
)
3680 old
= SUBREG_REG (old
);
3681 subst
= get_equiv_with_elimination (old
, curr_insn
);
3682 original_subreg_reg_mode
[i
] = VOIDmode
;
3683 equiv_substition_p
[i
] = false;
3686 equiv_substition_p
[i
] = true;
3687 subst
= copy_rtx (subst
);
3688 lra_assert (REG_P (old
));
3689 if (GET_CODE (op
) != SUBREG
)
3690 *curr_id
->operand_loc
[i
] = subst
;
3693 SUBREG_REG (op
) = subst
;
3694 if (GET_MODE (subst
) == VOIDmode
)
3695 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3697 if (lra_dump_file
!= NULL
)
3699 fprintf (lra_dump_file
,
3700 "Changing pseudo %d in operand %i of insn %u on equiv ",
3701 REGNO (old
), i
, INSN_UID (curr_insn
));
3702 dump_value_slim (lra_dump_file
, subst
, 1);
3703 fprintf (lra_dump_file
, "\n");
3705 op_change_p
= change_p
= true;
3707 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3710 lra_update_dup (curr_id
, i
);
3714 /* Reload address registers and displacements. We do it before
3715 finding an alternative because of memory constraints. */
3716 before
= after
= NULL
;
3717 for (i
= 0; i
< n_operands
; i
++)
3718 if (! curr_static_id
->operand
[i
].is_operator
3719 && process_address (i
, check_only_p
, &before
, &after
))
3724 lra_update_dup (curr_id
, i
);
3728 /* If we've changed the instruction then any alternative that
3729 we chose previously may no longer be valid. */
3730 lra_set_used_insn_alternative (curr_insn
, -1);
3732 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3733 && check_and_process_move (&change_p
, &sec_mem_p
))
3738 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3739 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3740 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3741 reused_alternative_num
, INSN_UID (curr_insn
));
3743 if (process_alt_operands (reused_alternative_num
))
3747 return ! alt_p
|| best_losers
!= 0;
3749 /* If insn is commutative (it's safe to exchange a certain pair of
3750 operands) then we need to try each alternative twice, the second
3751 time matching those two operands as if we had exchanged them. To
3752 do this, really exchange them in operands.
3754 If we have just tried the alternatives the second time, return
3755 operands to normal and drop through. */
3757 if (reused_alternative_num
< 0 && commutative
>= 0)
3759 curr_swapped
= !curr_swapped
;
3762 swap_operands (commutative
);
3766 swap_operands (commutative
);
3769 if (! alt_p
&& ! sec_mem_p
)
3771 /* No alternative works with reloads?? */
3772 if (INSN_CODE (curr_insn
) >= 0)
3773 fatal_insn ("unable to generate reloads for:", curr_insn
);
3774 error_for_asm (curr_insn
,
3775 "inconsistent operand constraints in an %<asm%>");
3776 /* Avoid further trouble with this insn. */
3777 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3778 lra_invalidate_insn_data (curr_insn
);
3782 /* If the best alternative is with operands 1 and 2 swapped, swap
3783 them. Update the operand numbers of any reloads already
3786 if (goal_alt_swapped
)
3788 if (lra_dump_file
!= NULL
)
3789 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3790 INSN_UID (curr_insn
));
3792 /* Swap the duplicates too. */
3793 swap_operands (commutative
);
3797 #ifdef SECONDARY_MEMORY_NEEDED
3798 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3799 too conservatively. So we use the secondary memory only if there
3800 is no any alternative without reloads. */
3801 use_sec_mem_p
= false;
3803 use_sec_mem_p
= true;
3806 for (i
= 0; i
< n_operands
; i
++)
3807 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3809 use_sec_mem_p
= i
< n_operands
;
3814 int in
= -1, out
= -1;
3815 rtx new_reg
, src
, dest
, rld
;
3816 machine_mode sec_mode
, rld_mode
;
3818 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3819 dest
= SET_DEST (curr_insn_set
);
3820 src
= SET_SRC (curr_insn_set
);
3821 for (i
= 0; i
< n_operands
; i
++)
3822 if (*curr_id
->operand_loc
[i
] == dest
)
3824 else if (*curr_id
->operand_loc
[i
] == src
)
3826 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3827 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3828 out
= curr_static_id
->dup_num
[i
];
3829 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3830 in
= curr_static_id
->dup_num
[i
];
3831 lra_assert (out
>= 0 && in
>= 0
3832 && curr_static_id
->operand
[out
].type
== OP_OUT
3833 && curr_static_id
->operand
[in
].type
== OP_IN
);
3834 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3836 rld_mode
= GET_MODE (rld
);
3837 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3838 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3840 sec_mode
= rld_mode
;
3842 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3843 NO_REGS
, "secondary");
3844 /* If the mode is changed, it should be wider. */
3845 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3846 if (sec_mode
!= rld_mode
)
3848 /* If the target says specifically to use another mode for
3849 secondary memory moves we can not reuse the original
3851 after
= emit_spill_move (false, new_reg
, dest
);
3852 lra_process_new_insns (curr_insn
, NULL
, after
,
3853 "Inserting the sec. move");
3854 /* We may have non null BEFORE here (e.g. after address
3856 push_to_sequence (before
);
3857 before
= emit_spill_move (true, new_reg
, src
);
3859 before
= get_insns ();
3861 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3862 lra_set_insn_deleted (curr_insn
);
3864 else if (dest
== rld
)
3866 *curr_id
->operand_loc
[out
] = new_reg
;
3867 lra_update_dup (curr_id
, out
);
3868 after
= emit_spill_move (false, new_reg
, dest
);
3869 lra_process_new_insns (curr_insn
, NULL
, after
,
3870 "Inserting the sec. move");
3874 *curr_id
->operand_loc
[in
] = new_reg
;
3875 lra_update_dup (curr_id
, in
);
3876 /* See comments above. */
3877 push_to_sequence (before
);
3878 before
= emit_spill_move (true, new_reg
, src
);
3880 before
= get_insns ();
3882 lra_process_new_insns (curr_insn
, before
, NULL
,
3883 "Inserting the sec. move");
3885 lra_update_insn_regno_info (curr_insn
);
3890 lra_assert (goal_alt_number
>= 0);
3891 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3893 if (lra_dump_file
!= NULL
)
3897 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3898 goal_alt_number
, INSN_UID (curr_insn
));
3899 for (i
= 0; i
< n_operands
; i
++)
3901 p
= (curr_static_id
->operand_alternative
3902 [goal_alt_number
* n_operands
+ i
].constraint
);
3905 fprintf (lra_dump_file
, " (%d) ", i
);
3906 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3907 fputc (*p
, lra_dump_file
);
3909 if (INSN_CODE (curr_insn
) >= 0
3910 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3911 fprintf (lra_dump_file
, " {%s}", p
);
3912 if (curr_id
->sp_offset
!= 0)
3913 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3914 curr_id
->sp_offset
);
3915 fprintf (lra_dump_file
, "\n");
3918 /* Right now, for any pair of operands I and J that are required to
3919 match, with J < I, goal_alt_matches[I] is J. Add I to
3920 goal_alt_matched[J]. */
3922 for (i
= 0; i
< n_operands
; i
++)
3923 if ((j
= goal_alt_matches
[i
]) >= 0)
3925 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3927 /* We allow matching one output operand and several input
3930 || (curr_static_id
->operand
[j
].type
== OP_OUT
3931 && curr_static_id
->operand
[i
].type
== OP_IN
3932 && (curr_static_id
->operand
3933 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3934 goal_alt_matched
[j
][k
] = i
;
3935 goal_alt_matched
[j
][k
+ 1] = -1;
3938 for (i
= 0; i
< n_operands
; i
++)
3939 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3941 /* Any constants that aren't allowed and can't be reloaded into
3942 registers are here changed into memory references. */
3943 for (i
= 0; i
< n_operands
; i
++)
3944 if (goal_alt_win
[i
])
3947 enum reg_class new_class
;
3948 rtx reg
= *curr_id
->operand_loc
[i
];
3950 if (GET_CODE (reg
) == SUBREG
)
3951 reg
= SUBREG_REG (reg
);
3953 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3955 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3957 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3960 lra_change_class (regno
, new_class
, " Change to", true);
3966 const char *constraint
;
3968 rtx op
= *curr_id
->operand_loc
[i
];
3969 rtx subreg
= NULL_RTX
;
3970 machine_mode mode
= curr_operand_mode
[i
];
3972 if (GET_CODE (op
) == SUBREG
)
3975 op
= SUBREG_REG (op
);
3976 mode
= GET_MODE (op
);
3979 if (CONST_POOL_OK_P (mode
, op
)
3980 && ((targetm
.preferred_reload_class
3981 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3982 || no_input_reloads_p
))
3984 rtx tem
= force_const_mem (mode
, op
);
3987 if (subreg
!= NULL_RTX
)
3988 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3990 *curr_id
->operand_loc
[i
] = tem
;
3991 lra_update_dup (curr_id
, i
);
3992 process_address (i
, false, &before
, &after
);
3994 /* If the alternative accepts constant pool refs directly
3995 there will be no reload needed at all. */
3996 if (subreg
!= NULL_RTX
)
3998 /* Skip alternatives before the one requested. */
3999 constraint
= (curr_static_id
->operand_alternative
4000 [goal_alt_number
* n_operands
+ i
].constraint
);
4002 (c
= *constraint
) && c
!= ',' && c
!= '#';
4003 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4005 enum constraint_num cn
= lookup_constraint (constraint
);
4006 if ((insn_extra_memory_constraint (cn
)
4007 || insn_extra_special_memory_constraint (cn
))
4008 && satisfies_memory_constraint_p (tem
, cn
))
4011 if (c
== '\0' || c
== ',' || c
== '#')
4014 goal_alt_win
[i
] = true;
4020 for (i
= 0; i
< n_operands
; i
++)
4023 bool optional_p
= false;
4025 rtx op
= *curr_id
->operand_loc
[i
];
4027 if (goal_alt_win
[i
])
4029 if (goal_alt
[i
] == NO_REGS
4031 /* When we assign NO_REGS it means that we will not
4032 assign a hard register to the scratch pseudo by
4033 assigment pass and the scratch pseudo will be
4034 spilled. Spilled scratch pseudos are transformed
4035 back to scratches at the LRA end. */
4036 && lra_former_scratch_operand_p (curr_insn
, i
)
4037 && lra_former_scratch_p (REGNO (op
)))
4039 int regno
= REGNO (op
);
4040 lra_change_class (regno
, NO_REGS
, " Change to", true);
4041 if (lra_get_regno_hard_regno (regno
) >= 0)
4042 /* We don't have to mark all insn affected by the
4043 spilled pseudo as there is only one such insn, the
4045 reg_renumber
[regno
] = -1;
4046 lra_assert (bitmap_single_bit_set_p
4047 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4049 /* We can do an optional reload. If the pseudo got a hard
4050 reg, we might improve the code through inheritance. If
4051 it does not get a hard register we coalesce memory/memory
4052 moves later. Ignore move insns to avoid cycling. */
4054 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4055 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4056 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4057 && regno
< new_regno_start
4058 && ! lra_former_scratch_p (regno
)
4059 && reg_renumber
[regno
] < 0
4060 /* Check that the optional reload pseudo will be able to
4061 hold given mode value. */
4062 && ! (prohibited_class_reg_set_mode_p
4063 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4064 PSEUDO_REGNO_MODE (regno
)))
4065 && (curr_insn_set
== NULL_RTX
4066 || !((REG_P (SET_SRC (curr_insn_set
))
4067 || MEM_P (SET_SRC (curr_insn_set
))
4068 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4069 && (REG_P (SET_DEST (curr_insn_set
))
4070 || MEM_P (SET_DEST (curr_insn_set
))
4071 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4077 /* Operands that match previous ones have already been handled. */
4078 if (goal_alt_matches
[i
] >= 0)
4081 /* We should not have an operand with a non-offsettable address
4082 appearing where an offsettable address will do. It also may
4083 be a case when the address should be special in other words
4084 not a general one (e.g. it needs no index reg). */
4085 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4087 enum reg_class rclass
;
4088 rtx
*loc
= &XEXP (op
, 0);
4089 enum rtx_code code
= GET_CODE (*loc
);
4091 push_to_sequence (before
);
4092 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4094 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4095 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4096 /* This value does not matter for MODIFY. */
4097 GET_MODE_SIZE (GET_MODE (op
)));
4098 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4099 "offsetable address", &new_reg
))
4100 lra_emit_move (new_reg
, *loc
);
4101 before
= get_insns ();
4104 lra_update_dup (curr_id
, i
);
4106 else if (goal_alt_matched
[i
][0] == -1)
4110 int hard_regno
, byte
;
4111 enum op_type type
= curr_static_id
->operand
[i
].type
;
4113 loc
= curr_id
->operand_loc
[i
];
4114 mode
= curr_operand_mode
[i
];
4115 if (GET_CODE (*loc
) == SUBREG
)
4117 reg
= SUBREG_REG (*loc
);
4118 byte
= SUBREG_BYTE (*loc
);
4120 /* Strict_low_part requires reload the register not
4121 the sub-register. */
4122 && (curr_static_id
->operand
[i
].strict_low
4123 || (GET_MODE_SIZE (mode
)
4124 <= GET_MODE_SIZE (GET_MODE (reg
))
4126 = get_try_hard_regno (REGNO (reg
))) >= 0
4127 && (simplify_subreg_regno
4129 GET_MODE (reg
), byte
, mode
) < 0)
4130 && (goal_alt
[i
] == NO_REGS
4131 || (simplify_subreg_regno
4132 (ira_class_hard_regs
[goal_alt
[i
]][0],
4133 GET_MODE (reg
), byte
, mode
) >= 0)))))
4137 loc
= &SUBREG_REG (*loc
);
4138 mode
= GET_MODE (*loc
);
4142 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4143 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4146 push_to_sequence (before
);
4147 lra_emit_move (new_reg
, old
);
4148 before
= get_insns ();
4153 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4156 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4158 after
= get_insns ();
4162 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4163 if (goal_alt_dont_inherit_ops
[j
] == i
)
4165 lra_set_regno_unique_value (REGNO (new_reg
));
4168 lra_update_dup (curr_id
, i
);
4170 else if (curr_static_id
->operand
[i
].type
== OP_IN
4171 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4174 /* generate reloads for input and matched outputs. */
4175 match_inputs
[0] = i
;
4176 match_inputs
[1] = -1;
4177 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4178 goal_alt
[i
], &before
, &after
,
4179 curr_static_id
->operand_alternative
4180 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4183 else if (curr_static_id
->operand
[i
].type
== OP_OUT
4184 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4186 /* Generate reloads for output and matched inputs. */
4187 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4188 &after
, curr_static_id
->operand_alternative
4189 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4190 else if (curr_static_id
->operand
[i
].type
== OP_IN
4191 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4194 /* Generate reloads for matched inputs. */
4195 match_inputs
[0] = i
;
4196 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4197 match_inputs
[j
+ 1] = k
;
4198 match_inputs
[j
+ 1] = -1;
4199 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4203 /* We must generate code in any case when function
4204 process_alt_operands decides that it is possible. */
4207 /* Memorise processed outputs so that output remaining to be processed
4208 can avoid using the same register value (see match_reload). */
4209 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4211 outputs
[n_outputs
++] = i
;
4212 outputs
[n_outputs
] = -1;
4219 lra_assert (REG_P (reg
));
4220 regno
= REGNO (reg
);
4221 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4222 if (GET_CODE (op
) == SUBREG
)
4223 op
= SUBREG_REG (op
);
4224 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4225 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4226 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4227 if (lra_dump_file
!= NULL
)
4228 fprintf (lra_dump_file
,
4229 " Making reload reg %d for reg %d optional\n",
4233 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4234 || max_regno_before
!= max_reg_num ())
4238 lra_update_operator_dups (curr_id
);
4239 /* Something changes -- process the insn. */
4240 lra_update_insn_regno_info (curr_insn
);
4242 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4246 /* Return true if INSN satisfies all constraints. In other words, no
4247 reload insns are needed. */
4249 lra_constrain_insn (rtx_insn
*insn
)
4251 int saved_new_regno_start
= new_regno_start
;
4252 int saved_new_insn_uid_start
= new_insn_uid_start
;
4256 curr_id
= lra_get_insn_recog_data (curr_insn
);
4257 curr_static_id
= curr_id
->insn_static_data
;
4258 new_insn_uid_start
= get_max_uid ();
4259 new_regno_start
= max_reg_num ();
4260 change_p
= curr_insn_transform (true);
4261 new_regno_start
= saved_new_regno_start
;
4262 new_insn_uid_start
= saved_new_insn_uid_start
;
4266 /* Return true if X is in LIST. */
4268 in_list_p (rtx x
, rtx list
)
4270 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4271 if (XEXP (list
, 0) == x
)
4276 /* Return true if X contains an allocatable hard register (if
4277 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4279 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4285 code
= GET_CODE (x
);
4288 int regno
= REGNO (x
);
4289 HARD_REG_SET alloc_regs
;
4293 if (regno
>= FIRST_PSEUDO_REGISTER
)
4294 regno
= lra_get_regno_hard_regno (regno
);
4297 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4298 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4302 if (regno
< FIRST_PSEUDO_REGISTER
)
4306 return lra_get_regno_hard_regno (regno
) < 0;
4309 fmt
= GET_RTX_FORMAT (code
);
4310 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4314 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4317 else if (fmt
[i
] == 'E')
4319 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4320 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4327 /* Process all regs in location *LOC and change them on equivalent
4328 substitution. Return true if any change was done. */
4330 loc_equivalence_change_p (rtx
*loc
)
4332 rtx subst
, reg
, x
= *loc
;
4333 bool result
= false;
4334 enum rtx_code code
= GET_CODE (x
);
4340 reg
= SUBREG_REG (x
);
4341 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4342 && GET_MODE (subst
) == VOIDmode
)
4344 /* We cannot reload debug location. Simplify subreg here
4345 while we know the inner mode. */
4346 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4347 GET_MODE (reg
), SUBREG_BYTE (x
));
4351 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4357 /* Scan all the operand sub-expressions. */
4358 fmt
= GET_RTX_FORMAT (code
);
4359 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4362 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4363 else if (fmt
[i
] == 'E')
4364 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4366 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4371 /* Similar to loc_equivalence_change_p, but for use as
4372 simplify_replace_fn_rtx callback. DATA is insn for which the
4373 elimination is done. If it null we don't do the elimination. */
4375 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4380 rtx subst
= (data
== NULL
4381 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4388 /* Maximum number of generated reload insns per an insn. It is for
4389 preventing this pass cycling in a bug case. */
4390 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4392 /* The current iteration number of this LRA pass. */
4393 int lra_constraint_iter
;
4395 /* True if we substituted equiv which needs checking register
4396 allocation correctness because the equivalent value contains
4397 allocatable hard registers or when we restore multi-register
4399 bool lra_risky_transformations_p
;
4401 /* Return true if REGNO is referenced in more than one block. */
4403 multi_block_pseudo_p (int regno
)
4405 basic_block bb
= NULL
;
4409 if (regno
< FIRST_PSEUDO_REGISTER
)
4412 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4414 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4415 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4420 /* Return true if LIST contains a deleted insn. */
4422 contains_deleted_insn_p (rtx_insn_list
*list
)
4424 for (; list
!= NULL_RTX
; list
= list
->next ())
4425 if (NOTE_P (list
->insn ())
4426 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4431 /* Return true if X contains a pseudo dying in INSN. */
4433 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4440 return (insn
!= NULL_RTX
4441 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4442 code
= GET_CODE (x
);
4443 fmt
= GET_RTX_FORMAT (code
);
4444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4448 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4451 else if (fmt
[i
] == 'E')
4453 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4454 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4461 /* Return true if INSN contains a dying pseudo in INSN right hand
4464 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4466 rtx set
= single_set (insn
);
4468 gcc_assert (set
!= NULL
);
4469 return dead_pseudo_p (SET_SRC (set
), insn
);
4472 /* Return true if any init insn of REGNO contains a dying pseudo in
4473 insn right hand side. */
4475 init_insn_rhs_dead_pseudo_p (int regno
)
4477 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4481 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4482 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4487 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4488 reverse only if we have one init insn with given REGNO as a
4491 reverse_equiv_p (int regno
)
4493 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4498 if (! INSN_P (insns
->insn ())
4499 || insns
->next () != NULL
)
4501 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4503 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4506 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4507 call this function only for non-reverse equivalence. */
4509 contains_reloaded_insn_p (int regno
)
4512 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4514 for (; list
!= NULL
; list
= list
->next ())
4515 if ((set
= single_set (list
->insn ())) == NULL_RTX
4516 || ! REG_P (SET_DEST (set
))
4517 || (int) REGNO (SET_DEST (set
)) != regno
)
4522 /* Entry function of LRA constraint pass. Return true if the
4523 constraint pass did change the code. */
4525 lra_constraints (bool first_p
)
4528 int i
, hard_regno
, new_insns_num
;
4529 unsigned int min_len
, new_min_len
, uid
;
4530 rtx set
, x
, reg
, dest_reg
;
4531 basic_block last_bb
;
4532 bitmap_head equiv_insn_bitmap
;
4535 lra_constraint_iter
++;
4536 if (lra_dump_file
!= NULL
)
4537 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4538 lra_constraint_iter
);
4540 if (pic_offset_table_rtx
4541 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4542 lra_risky_transformations_p
= true;
4544 /* On the first iteration we should check IRA assignment
4545 correctness. In rare cases, the assignments can be wrong as
4546 early clobbers operands are ignored in IRA. */
4547 lra_risky_transformations_p
= first_p
;
4548 new_insn_uid_start
= get_max_uid ();
4549 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4550 /* Mark used hard regs for target stack size calulations. */
4551 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4552 if (lra_reg_info
[i
].nrefs
!= 0
4553 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4557 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4558 for (j
= 0; j
< nregs
; j
++)
4559 df_set_regs_ever_live (hard_regno
+ j
, true);
4561 /* Do elimination before the equivalence processing as we can spill
4562 some pseudos during elimination. */
4563 lra_eliminate (false, first_p
);
4564 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4565 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4566 if (lra_reg_info
[i
].nrefs
!= 0)
4568 ira_reg_equiv
[i
].profitable_p
= true;
4569 reg
= regno_reg_rtx
[i
];
4570 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4572 bool pseudo_p
= contains_reg_p (x
, false, false);
4574 /* After RTL transformation, we can not guarantee that
4575 pseudo in the substitution was not reloaded which might
4576 make equivalence invalid. For example, in reverse
4583 the memory address register was reloaded before the 2nd
4585 if ((! first_p
&& pseudo_p
)
4586 /* We don't use DF for compilation speed sake. So it
4587 is problematic to update live info when we use an
4588 equivalence containing pseudos in more than one
4590 || (pseudo_p
&& multi_block_pseudo_p (i
))
4591 /* If an init insn was deleted for some reason, cancel
4592 the equiv. We could update the equiv insns after
4593 transformations including an equiv insn deletion
4594 but it is not worthy as such cases are extremely
4596 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4597 /* If it is not a reverse equivalence, we check that a
4598 pseudo in rhs of the init insn is not dying in the
4599 insn. Otherwise, the live info at the beginning of
4600 the corresponding BB might be wrong after we
4601 removed the insn. When the equiv can be a
4602 constant, the right hand side of the init insn can
4604 || (! reverse_equiv_p (i
)
4605 && (init_insn_rhs_dead_pseudo_p (i
)
4606 /* If we reloaded the pseudo in an equivalence
4607 init insn, we can not remove the equiv init
4608 insns and the init insns might write into
4609 const memory in this case. */
4610 || contains_reloaded_insn_p (i
)))
4611 /* Prevent access beyond equivalent memory for
4612 paradoxical subregs. */
4614 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4615 > GET_MODE_SIZE (GET_MODE (x
))))
4616 || (pic_offset_table_rtx
4617 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4618 && (targetm
.preferred_reload_class
4619 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4620 || contains_symbol_ref_p (x
))))
4621 ira_reg_equiv
[i
].defined_p
= false;
4622 if (contains_reg_p (x
, false, true))
4623 ira_reg_equiv
[i
].profitable_p
= false;
4624 if (get_equiv (reg
) != reg
)
4625 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4628 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4630 /* We should add all insns containing pseudos which should be
4631 substituted by their equivalences. */
4632 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4633 lra_push_insn_by_uid (uid
);
4634 min_len
= lra_insn_stack_length ();
4638 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4640 curr_insn
= lra_pop_insn ();
4642 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4643 if (curr_bb
!= last_bb
)
4646 bb_reload_num
= lra_curr_reload_num
;
4648 if (min_len
> new_min_len
)
4650 min_len
= new_min_len
;
4653 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4655 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4656 MAX_RELOAD_INSNS_NUMBER
);
4658 if (DEBUG_INSN_P (curr_insn
))
4660 /* We need to check equivalence in debug insn and change
4661 pseudo to the equivalent value if necessary. */
4662 curr_id
= lra_get_insn_recog_data (curr_insn
);
4663 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4665 rtx old
= *curr_id
->operand_loc
[0];
4666 *curr_id
->operand_loc
[0]
4667 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4668 loc_equivalence_callback
, curr_insn
);
4669 if (old
!= *curr_id
->operand_loc
[0])
4671 lra_update_insn_regno_info (curr_insn
);
4676 else if (INSN_P (curr_insn
))
4678 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4680 dest_reg
= SET_DEST (set
);
4681 /* The equivalence pseudo could be set up as SUBREG in a
4682 case when it is a call restore insn in a mode
4683 different from the pseudo mode. */
4684 if (GET_CODE (dest_reg
) == SUBREG
)
4685 dest_reg
= SUBREG_REG (dest_reg
);
4686 if ((REG_P (dest_reg
)
4687 && (x
= get_equiv (dest_reg
)) != dest_reg
4688 /* Remove insns which set up a pseudo whose value
4689 can not be changed. Such insns might be not in
4690 init_insns because we don't update equiv data
4691 during insn transformations.
4693 As an example, let suppose that a pseudo got
4694 hard register and on the 1st pass was not
4695 changed to equivalent constant. We generate an
4696 additional insn setting up the pseudo because of
4697 secondary memory movement. Then the pseudo is
4698 spilled and we use the equiv constant. In this
4699 case we should remove the additional insn and
4700 this insn is not init_insns list. */
4701 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4702 /* Check that this is actually an insn setting
4703 up the equivalence. */
4704 || in_list_p (curr_insn
,
4706 [REGNO (dest_reg
)].init_insns
)))
4707 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4708 && in_list_p (curr_insn
,
4710 [REGNO (SET_SRC (set
))].init_insns
)))
4712 /* This is equiv init insn of pseudo which did not get a
4713 hard register -- remove the insn. */
4714 if (lra_dump_file
!= NULL
)
4716 fprintf (lra_dump_file
,
4717 " Removing equiv init insn %i (freq=%d)\n",
4718 INSN_UID (curr_insn
),
4719 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4720 dump_insn_slim (lra_dump_file
, curr_insn
);
4722 if (contains_reg_p (x
, true, false))
4723 lra_risky_transformations_p
= true;
4724 lra_set_insn_deleted (curr_insn
);
4728 curr_id
= lra_get_insn_recog_data (curr_insn
);
4729 curr_static_id
= curr_id
->insn_static_data
;
4730 init_curr_insn_input_reloads ();
4731 init_curr_operand_mode ();
4732 if (curr_insn_transform (false))
4734 /* Check non-transformed insns too for equiv change as USE
4735 or CLOBBER don't need reloads but can contain pseudos
4736 being changed on their equivalences. */
4737 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4738 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4740 lra_update_insn_regno_info (curr_insn
);
4745 bitmap_clear (&equiv_insn_bitmap
);
4746 /* If we used a new hard regno, changed_p should be true because the
4747 hard reg is assigned to a new pseudo. */
4748 if (flag_checking
&& !changed_p
)
4750 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4751 if (lra_reg_info
[i
].nrefs
!= 0
4752 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4754 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4756 for (j
= 0; j
< nregs
; j
++)
4757 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4763 static void initiate_invariants (void);
4764 static void finish_invariants (void);
4766 /* Initiate the LRA constraint pass. It is done once per
4769 lra_constraints_init (void)
4771 initiate_invariants ();
4774 /* Finalize the LRA constraint pass. It is done once per
4777 lra_constraints_finish (void)
4779 finish_invariants ();
4784 /* Structure describes invariants for ineheritance. */
4785 struct lra_invariant
4787 /* The order number of the invariant. */
4789 /* The invariant RTX. */
4791 /* The origin insn of the invariant. */
4795 typedef lra_invariant invariant_t
;
4796 typedef invariant_t
*invariant_ptr_t
;
4797 typedef const invariant_t
*const_invariant_ptr_t
;
4799 /* Pointer to the inheritance invariants. */
4800 static vec
<invariant_ptr_t
> invariants
;
4802 /* Allocation pool for the invariants. */
4803 static object_allocator
<lra_invariant
> *invariants_pool
;
4805 /* Hash table for the invariants. */
4806 static htab_t invariant_table
;
4808 /* Hash function for INVARIANT. */
4810 invariant_hash (const void *invariant
)
4812 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4813 return lra_rtx_hash (inv
);
4816 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4818 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4820 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4821 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4823 return rtx_equal_p (inv1
, inv2
);
4826 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4827 invariant which is in the table. */
4828 static invariant_ptr_t
4829 insert_invariant (rtx invariant_rtx
)
4832 invariant_t invariant
;
4833 invariant_ptr_t invariant_ptr
;
4835 invariant
.invariant_rtx
= invariant_rtx
;
4836 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4837 if (*entry_ptr
== NULL
)
4839 invariant_ptr
= invariants_pool
->allocate ();
4840 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4841 invariant_ptr
->insn
= NULL
;
4842 invariants
.safe_push (invariant_ptr
);
4843 *entry_ptr
= (void *) invariant_ptr
;
4845 return (invariant_ptr_t
) *entry_ptr
;
4848 /* Initiate the invariant table. */
4850 initiate_invariants (void)
4852 invariants
.create (100);
4854 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
4855 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4858 /* Finish the invariant table. */
4860 finish_invariants (void)
4862 htab_delete (invariant_table
);
4863 delete invariants_pool
;
4864 invariants
.release ();
4867 /* Make the invariant table empty. */
4869 clear_invariants (void)
4871 htab_empty (invariant_table
);
4872 invariants_pool
->release ();
4873 invariants
.truncate (0);
4878 /* This page contains code to do inheritance/split
4881 /* Number of reloads passed so far in current EBB. */
4882 static int reloads_num
;
4884 /* Number of calls passed so far in current EBB. */
4885 static int calls_num
;
4887 /* Current reload pseudo check for validity of elements in
4889 static int curr_usage_insns_check
;
4891 /* Info about last usage of registers in EBB to do inheritance/split
4892 transformation. Inheritance transformation is done from a spilled
4893 pseudo and split transformations from a hard register or a pseudo
4894 assigned to a hard register. */
4897 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4898 value INSNS is valid. The insns is chain of optional debug insns
4899 and a finishing non-debug insn using the corresponding reg. The
4900 value is also used to mark the registers which are set up in the
4901 current insn. The negated insn uid is used for this. */
4903 /* Value of global reloads_num at the last insn in INSNS. */
4905 /* Value of global reloads_nums at the last insn in INSNS. */
4907 /* It can be true only for splitting. And it means that the restore
4908 insn should be put after insn given by the following member. */
4910 /* Next insns in the current EBB which use the original reg and the
4911 original reg value is not changed between the current insn and
4912 the next insns. In order words, e.g. for inheritance, if we need
4913 to use the original reg value again in the next insns we can try
4914 to use the value in a hard register from a reload insn of the
4919 /* Map: regno -> corresponding pseudo usage insns. */
4920 static struct usage_insns
*usage_insns
;
4923 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4925 usage_insns
[regno
].check
= curr_usage_insns_check
;
4926 usage_insns
[regno
].insns
= insn
;
4927 usage_insns
[regno
].reloads_num
= reloads_num
;
4928 usage_insns
[regno
].calls_num
= calls_num
;
4929 usage_insns
[regno
].after_p
= after_p
;
4932 /* The function is used to form list REGNO usages which consists of
4933 optional debug insns finished by a non-debug insn using REGNO.
4934 RELOADS_NUM is current number of reload insns processed so far. */
4936 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
4938 rtx next_usage_insns
;
4940 if (usage_insns
[regno
].check
== curr_usage_insns_check
4941 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4942 && DEBUG_INSN_P (insn
))
4944 /* Check that we did not add the debug insn yet. */
4945 if (next_usage_insns
!= insn
4946 && (GET_CODE (next_usage_insns
) != INSN_LIST
4947 || XEXP (next_usage_insns
, 0) != insn
))
4948 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4951 else if (NONDEBUG_INSN_P (insn
))
4952 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4954 usage_insns
[regno
].check
= 0;
4957 /* Return first non-debug insn in list USAGE_INSNS. */
4959 skip_usage_debug_insns (rtx usage_insns
)
4963 /* Skip debug insns. */
4964 for (insn
= usage_insns
;
4965 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4966 insn
= XEXP (insn
, 1))
4968 return safe_as_a
<rtx_insn
*> (insn
);
4971 /* Return true if we need secondary memory moves for insn in
4972 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4975 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4976 rtx usage_insns ATTRIBUTE_UNUSED
)
4978 #ifndef SECONDARY_MEMORY_NEEDED
4985 if (inher_cl
== ALL_REGS
4986 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4988 lra_assert (INSN_P (insn
));
4989 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4991 dest
= SET_DEST (set
);
4994 lra_assert (inher_cl
!= NO_REGS
);
4995 cl
= get_reg_class (REGNO (dest
));
4996 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4997 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
5001 /* Registers involved in inheritance/split in the current EBB
5002 (inheritance/split pseudos and original registers). */
5003 static bitmap_head check_only_regs
;
5005 /* Reload pseudos can not be involded in invariant inheritance in the
5007 static bitmap_head invalid_invariant_regs
;
5009 /* Do inheritance transformations for insn INSN, which defines (if
5010 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5011 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5012 form as the "insns" field of usage_insns. Return true if we
5013 succeed in such transformation.
5015 The transformations look like:
5018 ... p <- i (new insn)
5020 <- ... p ... <- ... i ...
5022 ... i <- p (new insn)
5023 <- ... p ... <- ... i ...
5025 <- ... p ... <- ... i ...
5026 where p is a spilled original pseudo and i is a new inheritance pseudo.
5029 The inheritance pseudo has the smallest class of two classes CL and
5030 class of ORIGINAL REGNO. */
5032 inherit_reload_reg (bool def_p
, int original_regno
,
5033 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5035 if (optimize_function_for_size_p (cfun
))
5038 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5039 rtx original_reg
= regno_reg_rtx
[original_regno
];
5040 rtx new_reg
, usage_insn
;
5041 rtx_insn
*new_insns
;
5043 lra_assert (! usage_insns
[original_regno
].after_p
);
5044 if (lra_dump_file
!= NULL
)
5045 fprintf (lra_dump_file
,
5046 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5047 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5049 if (lra_dump_file
!= NULL
)
5051 fprintf (lra_dump_file
,
5052 " Rejecting inheritance for %d "
5053 "because of disjoint classes %s and %s\n",
5054 original_regno
, reg_class_names
[cl
],
5055 reg_class_names
[rclass
]);
5056 fprintf (lra_dump_file
,
5057 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5061 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5062 /* We don't use a subset of two classes because it can be
5063 NO_REGS. This transformation is still profitable in most
5064 cases even if the classes are not intersected as register
5065 move is probably cheaper than a memory load. */
5066 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5068 if (lra_dump_file
!= NULL
)
5069 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5070 reg_class_names
[cl
], reg_class_names
[rclass
]);
5074 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5076 /* Reject inheritance resulting in secondary memory moves.
5077 Otherwise, there is a danger in LRA cycling. Also such
5078 transformation will be unprofitable. */
5079 if (lra_dump_file
!= NULL
)
5081 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5082 rtx set
= single_set (insn
);
5084 lra_assert (set
!= NULL_RTX
);
5086 rtx dest
= SET_DEST (set
);
5088 lra_assert (REG_P (dest
));
5089 fprintf (lra_dump_file
,
5090 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5091 "as secondary mem is needed\n",
5092 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5093 original_regno
, reg_class_names
[rclass
]);
5094 fprintf (lra_dump_file
,
5095 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5099 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5100 rclass
, "inheritance");
5103 lra_emit_move (original_reg
, new_reg
);
5105 lra_emit_move (new_reg
, original_reg
);
5106 new_insns
= get_insns ();
5108 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5110 if (lra_dump_file
!= NULL
)
5112 fprintf (lra_dump_file
,
5113 " Rejecting inheritance %d->%d "
5114 "as it results in 2 or more insns:\n",
5115 original_regno
, REGNO (new_reg
));
5116 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5117 fprintf (lra_dump_file
,
5118 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5122 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5123 lra_update_insn_regno_info (insn
);
5125 /* We now have a new usage insn for original regno. */
5126 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5127 if (lra_dump_file
!= NULL
)
5128 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5129 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5130 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5131 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5132 bitmap_set_bit (&check_only_regs
, original_regno
);
5133 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5135 lra_process_new_insns (insn
, NULL
, new_insns
,
5136 "Add original<-inheritance");
5138 lra_process_new_insns (insn
, new_insns
, NULL
,
5139 "Add inheritance<-original");
5140 while (next_usage_insns
!= NULL_RTX
)
5142 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5144 usage_insn
= next_usage_insns
;
5145 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5146 next_usage_insns
= NULL
;
5150 usage_insn
= XEXP (next_usage_insns
, 0);
5151 lra_assert (DEBUG_INSN_P (usage_insn
));
5152 next_usage_insns
= XEXP (next_usage_insns
, 1);
5154 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5155 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5156 if (lra_dump_file
!= NULL
)
5158 fprintf (lra_dump_file
,
5159 " Inheritance reuse change %d->%d (bb%d):\n",
5160 original_regno
, REGNO (new_reg
),
5161 BLOCK_FOR_INSN (usage_insn
)->index
);
5162 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5165 if (lra_dump_file
!= NULL
)
5166 fprintf (lra_dump_file
,
5167 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5171 /* Return true if we need a caller save/restore for pseudo REGNO which
5172 was assigned to a hard register. */
5174 need_for_call_save_p (int regno
)
5176 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5177 return (usage_insns
[regno
].calls_num
< calls_num
5178 && (overlaps_hard_reg_set_p
5180 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5181 ? lra_reg_info
[regno
].actual_call_used_reg_set
5182 : call_used_reg_set
,
5183 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5184 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
5185 PSEUDO_REGNO_MODE (regno
))));
5188 /* Global registers occurring in the current EBB. */
5189 static bitmap_head ebb_global_regs
;
5191 /* Return true if we need a split for hard register REGNO or pseudo
5192 REGNO which was assigned to a hard register.
5193 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5194 used for reloads since the EBB end. It is an approximation of the
5195 used hard registers in the split range. The exact value would
5196 require expensive calculations. If we were aggressive with
5197 splitting because of the approximation, the split pseudo will save
5198 the same hard register assignment and will be removed in the undo
5199 pass. We still need the approximation because too aggressive
5200 splitting would result in too inaccurate cost calculation in the
5201 assignment pass because of too many generated moves which will be
5202 probably removed in the undo pass. */
5204 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5206 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5208 lra_assert (hard_regno
>= 0);
5209 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5210 /* Don't split eliminable hard registers, otherwise we can
5211 split hard registers like hard frame pointer, which
5212 lives on BB start/end according to DF-infrastructure,
5213 when there is a pseudo assigned to the register and
5214 living in the same BB. */
5215 && (regno
>= FIRST_PSEUDO_REGISTER
5216 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5217 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5218 /* Don't split call clobbered hard regs living through
5219 calls, otherwise we might have a check problem in the
5220 assign sub-pass as in the most cases (exception is a
5221 situation when lra_risky_transformations_p value is
5222 true) the assign pass assumes that all pseudos living
5223 through calls are assigned to call saved hard regs. */
5224 && (regno
>= FIRST_PSEUDO_REGISTER
5225 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5226 || usage_insns
[regno
].calls_num
== calls_num
)
5227 /* We need at least 2 reloads to make pseudo splitting
5228 profitable. We should provide hard regno splitting in
5229 any case to solve 1st insn scheduling problem when
5230 moving hard register definition up might result in
5231 impossibility to find hard register for reload pseudo of
5232 small register class. */
5233 && (usage_insns
[regno
].reloads_num
5234 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5235 && (regno
< FIRST_PSEUDO_REGISTER
5236 /* For short living pseudos, spilling + inheritance can
5237 be considered a substitution for splitting.
5238 Therefore we do not splitting for local pseudos. It
5239 decreases also aggressiveness of splitting. The
5240 minimal number of references is chosen taking into
5241 account that for 2 references splitting has no sense
5242 as we can just spill the pseudo. */
5243 || (regno
>= FIRST_PSEUDO_REGISTER
5244 && lra_reg_info
[regno
].nrefs
> 3
5245 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5246 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5249 /* Return class for the split pseudo created from original pseudo with
5250 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5251 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5252 results in no secondary memory movements. */
5253 static enum reg_class
5254 choose_split_class (enum reg_class allocno_class
,
5255 int hard_regno ATTRIBUTE_UNUSED
,
5256 machine_mode mode ATTRIBUTE_UNUSED
)
5258 #ifndef SECONDARY_MEMORY_NEEDED
5259 return allocno_class
;
5262 enum reg_class cl
, best_cl
= NO_REGS
;
5263 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5264 = REGNO_REG_CLASS (hard_regno
);
5266 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
5267 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5268 return allocno_class
;
5270 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5272 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
5273 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
5274 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5275 && (best_cl
== NO_REGS
5276 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5282 /* Do split transformations for insn INSN, which defines or uses
5283 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5284 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5285 "insns" field of usage_insns.
5287 The transformations look like:
5290 ... s <- p (new insn -- save)
5292 ... p <- s (new insn -- restore)
5293 <- ... p ... <- ... p ...
5295 <- ... p ... <- ... p ...
5296 ... s <- p (new insn -- save)
5298 ... p <- s (new insn -- restore)
5299 <- ... p ... <- ... p ...
5301 where p is an original pseudo got a hard register or a hard
5302 register and s is a new split pseudo. The save is put before INSN
5303 if BEFORE_P is true. Return true if we succeed in such
5306 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5307 rtx next_usage_insns
)
5309 enum reg_class rclass
;
5311 int hard_regno
, nregs
;
5312 rtx new_reg
, usage_insn
;
5313 rtx_insn
*restore
, *save
;
5318 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5320 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5321 hard_regno
= original_regno
;
5322 call_save_p
= false;
5324 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5325 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5326 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5327 as part of a multi-word register. In that case, or if the biggest
5328 mode was larger than a register, just use the reg_rtx. Otherwise,
5329 limit the size to that of the biggest access in the function. */
5330 if (mode
== VOIDmode
5331 || GET_MODE_SIZE (mode
) > GET_MODE_SIZE (reg_rtx_mode
))
5333 original_reg
= regno_reg_rtx
[hard_regno
];
5334 mode
= reg_rtx_mode
;
5337 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5341 mode
= PSEUDO_REGNO_MODE (original_regno
);
5342 hard_regno
= reg_renumber
[original_regno
];
5343 nregs
= hard_regno_nregs
[hard_regno
][mode
];
5344 rclass
= lra_get_allocno_class (original_regno
);
5345 original_reg
= regno_reg_rtx
[original_regno
];
5346 call_save_p
= need_for_call_save_p (original_regno
);
5348 lra_assert (hard_regno
>= 0);
5349 if (lra_dump_file
!= NULL
)
5350 fprintf (lra_dump_file
,
5351 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5355 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5356 hard_regno_nregs
[hard_regno
][mode
],
5358 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5362 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5363 if (rclass
== NO_REGS
)
5365 if (lra_dump_file
!= NULL
)
5367 fprintf (lra_dump_file
,
5368 " Rejecting split of %d(%s): "
5369 "no good reg class for %d(%s)\n",
5371 reg_class_names
[lra_get_allocno_class (original_regno
)],
5373 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5376 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5380 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5381 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5383 save
= emit_spill_move (true, new_reg
, original_reg
);
5384 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5386 if (lra_dump_file
!= NULL
)
5390 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5391 original_regno
, REGNO (new_reg
));
5392 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5393 fprintf (lra_dump_file
,
5394 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5398 restore
= emit_spill_move (false, new_reg
, original_reg
);
5399 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5401 if (lra_dump_file
!= NULL
)
5403 fprintf (lra_dump_file
,
5404 " Rejecting split %d->%d "
5405 "resulting in > 2 restore insns:\n",
5406 original_regno
, REGNO (new_reg
));
5407 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5408 fprintf (lra_dump_file
,
5409 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5413 after_p
= usage_insns
[original_regno
].after_p
;
5414 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5415 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5416 bitmap_set_bit (&check_only_regs
, original_regno
);
5417 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
5420 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5422 usage_insn
= next_usage_insns
;
5425 usage_insn
= XEXP (next_usage_insns
, 0);
5426 lra_assert (DEBUG_INSN_P (usage_insn
));
5427 next_usage_insns
= XEXP (next_usage_insns
, 1);
5428 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5429 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5430 if (lra_dump_file
!= NULL
)
5432 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5433 original_regno
, REGNO (new_reg
));
5434 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5437 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5438 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5439 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5440 after_p
? NULL
: restore
,
5441 after_p
? restore
: NULL
,
5443 ? "Add reg<-save" : "Add reg<-split");
5444 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5445 before_p
? NULL
: save
,
5447 ? "Add save<-reg" : "Add split<-reg");
5449 /* If we are trying to split multi-register. We should check
5450 conflicts on the next assignment sub-pass. IRA can allocate on
5451 sub-register levels, LRA do this on pseudos level right now and
5452 this discrepancy may create allocation conflicts after
5454 lra_risky_transformations_p
= true;
5455 if (lra_dump_file
!= NULL
)
5456 fprintf (lra_dump_file
,
5457 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5461 /* Recognize that we need a split transformation for insn INSN, which
5462 defines or uses REGNO in its insn biggest MODE (we use it only if
5463 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5464 hard registers which might be used for reloads since the EBB end.
5465 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5466 uid before starting INSN processing. Return true if we succeed in
5467 such transformation. */
5469 split_if_necessary (int regno
, machine_mode mode
,
5470 HARD_REG_SET potential_reload_hard_regs
,
5471 bool before_p
, rtx_insn
*insn
, int max_uid
)
5475 rtx next_usage_insns
;
5477 if (regno
< FIRST_PSEUDO_REGISTER
)
5478 nregs
= hard_regno_nregs
[regno
][mode
];
5479 for (i
= 0; i
< nregs
; i
++)
5480 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5481 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5482 /* To avoid processing the register twice or more. */
5483 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5484 && INSN_UID (next_usage_insns
) < max_uid
)
5485 || (GET_CODE (next_usage_insns
) == INSN_LIST
5486 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5487 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5488 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5493 /* Return TRUE if rtx X is considered as an invariant for
5496 invariant_p (const_rtx x
)
5503 code
= GET_CODE (x
);
5504 mode
= GET_MODE (x
);
5508 code
= GET_CODE (x
);
5509 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
5510 mode
= GET_MODE (x
);
5518 int i
, nregs
, regno
= REGNO (x
);
5520 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5521 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5522 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5524 nregs
= hard_regno_nregs
[regno
][mode
];
5525 for (i
= 0; i
< nregs
; i
++)
5526 if (! fixed_regs
[regno
+ i
]
5527 /* A hard register may be clobbered in the current insn
5528 but we can ignore this case because if the hard
5529 register is used it should be set somewhere after the
5531 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5534 fmt
= GET_RTX_FORMAT (code
);
5535 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5539 if (! invariant_p (XEXP (x
, i
)))
5542 else if (fmt
[i
] == 'E')
5544 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5545 if (! invariant_p (XVECEXP (x
, i
, j
)))
5552 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5553 inheritance transformation (using dest_reg instead invariant in a
5554 subsequent insn). */
5556 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5558 invariant_ptr_t invariant_ptr
;
5559 rtx_insn
*insn
, *new_insns
;
5560 rtx insn_set
, insn_reg
, new_reg
;
5562 bool succ_p
= false;
5563 int dst_regno
= REGNO (dst_reg
);
5564 enum machine_mode dst_mode
= GET_MODE (dst_reg
);
5565 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5567 invariant_ptr
= insert_invariant (invariant_rtx
);
5568 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5570 /* We have a subsequent insn using the invariant. */
5571 insn_set
= single_set (insn
);
5572 lra_assert (insn_set
!= NULL
);
5573 insn_reg
= SET_DEST (insn_set
);
5574 lra_assert (REG_P (insn_reg
));
5575 insn_regno
= REGNO (insn_reg
);
5576 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5578 if (dst_mode
== GET_MODE (insn_reg
)
5579 /* We should consider only result move reg insns which are
5581 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5582 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5584 if (lra_dump_file
!= NULL
)
5585 fprintf (lra_dump_file
,
5586 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5587 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5588 cl
, "invariant inheritance");
5589 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5590 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5591 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5593 lra_emit_move (new_reg
, dst_reg
);
5594 new_insns
= get_insns ();
5596 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5597 "Add invariant inheritance<-original");
5599 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5600 new_insns
= get_insns ();
5602 lra_process_new_insns (insn
, NULL
, new_insns
,
5603 "Changing reload<-inheritance");
5604 lra_set_insn_deleted (insn
);
5606 if (lra_dump_file
!= NULL
)
5608 fprintf (lra_dump_file
,
5609 " Invariant inheritance reuse change %d (bb%d):\n",
5610 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5611 dump_insn_slim (lra_dump_file
, insn
);
5612 fprintf (lra_dump_file
,
5613 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5617 invariant_ptr
->insn
= curr_insn
;
5621 /* Check only registers living at the current program point in the
5623 static bitmap_head live_regs
;
5625 /* Update live info in EBB given by its HEAD and TAIL insns after
5626 inheritance/split transformation. The function removes dead moves
5629 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5634 rtx_insn
*prev_insn
;
5637 basic_block last_bb
, prev_bb
, curr_bb
;
5639 struct lra_insn_reg
*reg
;
5643 last_bb
= BLOCK_FOR_INSN (tail
);
5645 for (curr_insn
= tail
;
5646 curr_insn
!= PREV_INSN (head
);
5647 curr_insn
= prev_insn
)
5649 prev_insn
= PREV_INSN (curr_insn
);
5650 /* We need to process empty blocks too. They contain
5651 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5652 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5654 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5655 if (curr_bb
!= prev_bb
)
5657 if (prev_bb
!= NULL
)
5659 /* Update df_get_live_in (prev_bb): */
5660 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5661 if (bitmap_bit_p (&live_regs
, j
))
5662 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5664 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5666 if (curr_bb
!= last_bb
)
5668 /* Update df_get_live_out (curr_bb): */
5669 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5671 live_p
= bitmap_bit_p (&live_regs
, j
);
5673 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5674 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5680 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5682 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5686 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5688 if (! NONDEBUG_INSN_P (curr_insn
))
5690 curr_id
= lra_get_insn_recog_data (curr_insn
);
5691 curr_static_id
= curr_id
->insn_static_data
;
5693 if ((set
= single_set (curr_insn
)) != NULL_RTX
5694 && REG_P (SET_DEST (set
))
5695 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5696 && SET_DEST (set
) != pic_offset_table_rtx
5697 && bitmap_bit_p (&check_only_regs
, regno
)
5698 && ! bitmap_bit_p (&live_regs
, regno
))
5700 /* See which defined values die here. */
5701 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5702 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5703 bitmap_clear_bit (&live_regs
, reg
->regno
);
5704 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5705 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5706 bitmap_clear_bit (&live_regs
, reg
->regno
);
5707 if (curr_id
->arg_hard_regs
!= NULL
)
5708 /* Make clobbered argument hard registers die. */
5709 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5710 if (regno
>= FIRST_PSEUDO_REGISTER
)
5711 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5712 /* Mark each used value as live. */
5713 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5714 if (reg
->type
!= OP_OUT
5715 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5716 bitmap_set_bit (&live_regs
, reg
->regno
);
5717 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5718 if (reg
->type
!= OP_OUT
5719 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5720 bitmap_set_bit (&live_regs
, reg
->regno
);
5721 if (curr_id
->arg_hard_regs
!= NULL
)
5722 /* Make used argument hard registers live. */
5723 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5724 if (regno
< FIRST_PSEUDO_REGISTER
5725 && bitmap_bit_p (&check_only_regs
, regno
))
5726 bitmap_set_bit (&live_regs
, regno
);
5727 /* It is quite important to remove dead move insns because it
5728 means removing dead store. We don't need to process them for
5732 if (lra_dump_file
!= NULL
)
5734 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5735 dump_insn_slim (lra_dump_file
, curr_insn
);
5737 lra_set_insn_deleted (curr_insn
);
5742 /* The structure describes info to do an inheritance for the current
5743 insn. We need to collect such info first before doing the
5744 transformations because the transformations change the insn
5745 internal representation. */
5748 /* Original regno. */
5750 /* Subsequent insns which can inherit original reg value. */
5754 /* Array containing all info for doing inheritance from the current
5756 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5758 /* Number elements in the previous array. */
5759 static int to_inherit_num
;
5761 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5762 structure to_inherit. */
5764 add_to_inherit (int regno
, rtx insns
)
5768 for (i
= 0; i
< to_inherit_num
; i
++)
5769 if (to_inherit
[i
].regno
== regno
)
5771 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5772 to_inherit
[to_inherit_num
].regno
= regno
;
5773 to_inherit
[to_inherit_num
++].insns
= insns
;
5776 /* Return the last non-debug insn in basic block BB, or the block begin
5779 get_last_insertion_point (basic_block bb
)
5783 FOR_BB_INSNS_REVERSE (bb
, insn
)
5784 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5789 /* Set up RES by registers living on edges FROM except the edge (FROM,
5790 TO) or by registers set up in a jump insn in BB FROM. */
5792 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5795 struct lra_insn_reg
*reg
;
5799 lra_assert (to
!= NULL
);
5801 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5803 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5804 last
= get_last_insertion_point (from
);
5805 if (! JUMP_P (last
))
5807 curr_id
= lra_get_insn_recog_data (last
);
5808 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5809 if (reg
->type
!= OP_IN
)
5810 bitmap_set_bit (res
, reg
->regno
);
5813 /* Used as a temporary results of some bitmap calculations. */
5814 static bitmap_head temp_bitmap
;
5816 /* We split for reloads of small class of hard regs. The following
5817 defines how many hard regs the class should have to be qualified as
5818 small. The code is mostly oriented to x86/x86-64 architecture
5819 where some insns need to use only specific register or pair of
5820 registers and these register can live in RTL explicitly, e.g. for
5821 parameter passing. */
5822 static const int max_small_class_regs_num
= 2;
5824 /* Do inheritance/split transformations in EBB starting with HEAD and
5825 finishing on TAIL. We process EBB insns in the reverse order.
5826 Return true if we did any inheritance/split transformation in the
5829 We should avoid excessive splitting which results in worse code
5830 because of inaccurate cost calculations for spilling new split
5831 pseudos in such case. To achieve this we do splitting only if
5832 register pressure is high in given basic block and there are reload
5833 pseudos requiring hard registers. We could do more register
5834 pressure calculations at any given program point to avoid necessary
5835 splitting even more but it is to expensive and the current approach
5836 works well enough. */
5838 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5840 int i
, src_regno
, dst_regno
, nregs
;
5841 bool change_p
, succ_p
, update_reloads_num_p
;
5842 rtx_insn
*prev_insn
, *last_insn
;
5843 rtx next_usage_insns
, curr_set
;
5845 struct lra_insn_reg
*reg
;
5846 basic_block last_processed_bb
, curr_bb
= NULL
;
5847 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5851 bool head_p
, after_p
;
5854 curr_usage_insns_check
++;
5855 clear_invariants ();
5856 reloads_num
= calls_num
= 0;
5857 bitmap_clear (&check_only_regs
);
5858 bitmap_clear (&invalid_invariant_regs
);
5859 last_processed_bb
= NULL
;
5860 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5861 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5862 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5863 /* We don't process new insns generated in the loop. */
5864 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5866 prev_insn
= PREV_INSN (curr_insn
);
5867 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5868 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5869 if (last_processed_bb
!= curr_bb
)
5871 /* We are at the end of BB. Add qualified living
5872 pseudos for potential splitting. */
5873 to_process
= df_get_live_out (curr_bb
);
5874 if (last_processed_bb
!= NULL
)
5876 /* We are somewhere in the middle of EBB. */
5877 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5879 to_process
= &temp_bitmap
;
5881 last_processed_bb
= curr_bb
;
5882 last_insn
= get_last_insertion_point (curr_bb
);
5883 after_p
= (! JUMP_P (last_insn
)
5884 && (! CALL_P (last_insn
)
5885 || (find_reg_note (last_insn
,
5886 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5887 && ! SIBLING_CALL_P (last_insn
))));
5888 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5889 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5891 if ((int) j
>= lra_constraint_new_regno_start
)
5893 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5895 if (j
< FIRST_PSEUDO_REGISTER
)
5896 SET_HARD_REG_BIT (live_hard_regs
, j
);
5898 add_to_hard_reg_set (&live_hard_regs
,
5899 PSEUDO_REGNO_MODE (j
),
5901 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5905 src_regno
= dst_regno
= -1;
5906 curr_set
= single_set (curr_insn
);
5907 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
5908 dst_regno
= REGNO (SET_DEST (curr_set
));
5909 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
5910 src_regno
= REGNO (SET_SRC (curr_set
));
5911 update_reloads_num_p
= true;
5912 if (src_regno
< lra_constraint_new_regno_start
5913 && src_regno
>= FIRST_PSEUDO_REGISTER
5914 && reg_renumber
[src_regno
] < 0
5915 && dst_regno
>= lra_constraint_new_regno_start
5916 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5918 /* 'reload_pseudo <- original_pseudo'. */
5919 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5921 update_reloads_num_p
= false;
5923 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5924 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5925 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5926 curr_insn
, next_usage_insns
);
5930 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5931 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5932 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5933 reg_class_contents
[cl
]);
5935 else if (src_regno
< 0
5936 && dst_regno
>= lra_constraint_new_regno_start
5937 && invariant_p (SET_SRC (curr_set
))
5938 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
5939 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
5940 && ! bitmap_bit_p (&invalid_invariant_regs
,
5941 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
5943 /* 'reload_pseudo <- invariant'. */
5944 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5946 update_reloads_num_p
= false;
5947 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
5949 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5950 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5951 reg_class_contents
[cl
]);
5953 else if (src_regno
>= lra_constraint_new_regno_start
5954 && dst_regno
< lra_constraint_new_regno_start
5955 && dst_regno
>= FIRST_PSEUDO_REGISTER
5956 && reg_renumber
[dst_regno
] < 0
5957 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5958 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5959 && (next_usage_insns
5960 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5962 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5964 update_reloads_num_p
= false;
5965 /* 'original_pseudo <- reload_pseudo'. */
5966 if (! JUMP_P (curr_insn
)
5967 && inherit_reload_reg (true, dst_regno
, cl
,
5968 curr_insn
, next_usage_insns
))
5971 usage_insns
[dst_regno
].check
= 0;
5972 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5973 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5974 reg_class_contents
[cl
]);
5976 else if (INSN_P (curr_insn
))
5979 int max_uid
= get_max_uid ();
5981 curr_id
= lra_get_insn_recog_data (curr_insn
);
5982 curr_static_id
= curr_id
->insn_static_data
;
5984 /* Process insn definitions. */
5985 for (iter
= 0; iter
< 2; iter
++)
5986 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5989 if (reg
->type
!= OP_IN
5990 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5992 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5993 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5994 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5995 && (next_usage_insns
5996 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5998 struct lra_insn_reg
*r
;
6000 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6001 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6003 /* Don't do inheritance if the pseudo is also
6004 used in the insn. */
6006 /* We can not do inheritance right now
6007 because the current insn reg info (chain
6008 regs) can change after that. */
6009 add_to_inherit (dst_regno
, next_usage_insns
);
6011 /* We can not process one reg twice here because of
6012 usage_insns invalidation. */
6013 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6014 || reg_renumber
[dst_regno
] >= 0)
6015 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6019 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6020 potential_reload_hard_regs
,
6021 false, curr_insn
, max_uid
))
6023 CLEAR_HARD_REG_SET (s
);
6024 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6025 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6027 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6028 reg_renumber
[dst_regno
]);
6029 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6031 /* We should invalidate potential inheritance or
6032 splitting for the current insn usages to the next
6033 usage insns (see code below) as the output pseudo
6035 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6036 && reg_renumber
[dst_regno
] < 0)
6037 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6038 && (dst_regno
< FIRST_PSEUDO_REGISTER
6039 || reg_renumber
[dst_regno
] >= 0)))
6041 /* Invalidate and mark definitions. */
6042 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6043 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6046 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
6047 for (i
= 0; i
< nregs
; i
++)
6048 usage_insns
[dst_regno
+ i
].check
6049 = -(int) INSN_UID (curr_insn
);
6053 /* Process clobbered call regs. */
6054 if (curr_id
->arg_hard_regs
!= NULL
)
6055 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6056 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6057 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6058 = -(int) INSN_UID (curr_insn
);
6059 if (! JUMP_P (curr_insn
))
6060 for (i
= 0; i
< to_inherit_num
; i
++)
6061 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6062 ALL_REGS
, curr_insn
,
6063 to_inherit
[i
].insns
))
6065 if (CALL_P (curr_insn
))
6067 rtx cheap
, pat
, dest
;
6069 int regno
, hard_regno
;
6072 if ((cheap
= find_reg_note (curr_insn
,
6073 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6074 && ((cheap
= XEXP (cheap
, 0)), true)
6075 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6076 && (hard_regno
= reg_renumber
[regno
]) >= 0
6077 /* If there are pending saves/restores, the
6078 optimization is not worth. */
6079 && usage_insns
[regno
].calls_num
== calls_num
- 1
6080 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6082 /* Restore the pseudo from the call result as
6083 REG_RETURNED note says that the pseudo value is
6084 in the call result and the pseudo is an argument
6086 pat
= PATTERN (curr_insn
);
6087 if (GET_CODE (pat
) == PARALLEL
)
6088 pat
= XVECEXP (pat
, 0, 0);
6089 dest
= SET_DEST (pat
);
6090 /* For multiple return values dest is PARALLEL.
6091 Currently we handle only single return value case. */
6095 emit_move_insn (cheap
, copy_rtx (dest
));
6096 restore
= get_insns ();
6098 lra_process_new_insns (curr_insn
, NULL
, restore
,
6099 "Inserting call parameter restore");
6100 /* We don't need to save/restore of the pseudo from
6102 usage_insns
[regno
].calls_num
= calls_num
;
6103 bitmap_set_bit (&check_only_regs
, regno
);
6108 /* Process insn usages. */
6109 for (iter
= 0; iter
< 2; iter
++)
6110 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6113 if ((reg
->type
!= OP_OUT
6114 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6115 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6117 if (src_regno
>= FIRST_PSEUDO_REGISTER
6118 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6120 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6121 && (next_usage_insns
6122 = usage_insns
[src_regno
].insns
) != NULL_RTX
6123 && NONDEBUG_INSN_P (curr_insn
))
6124 add_to_inherit (src_regno
, next_usage_insns
);
6125 else if (usage_insns
[src_regno
].check
6126 != -(int) INSN_UID (curr_insn
))
6127 /* Add usages but only if the reg is not set up
6128 in the same insn. */
6129 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6131 else if (src_regno
< FIRST_PSEUDO_REGISTER
6132 || reg_renumber
[src_regno
] >= 0)
6135 rtx_insn
*use_insn
= curr_insn
;
6137 before_p
= (JUMP_P (curr_insn
)
6138 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6139 if (NONDEBUG_INSN_P (curr_insn
)
6140 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6141 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6142 potential_reload_hard_regs
,
6143 before_p
, curr_insn
, max_uid
))
6146 lra_risky_transformations_p
= true;
6149 usage_insns
[src_regno
].check
= 0;
6151 use_insn
= PREV_INSN (curr_insn
);
6153 if (NONDEBUG_INSN_P (curr_insn
))
6155 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6156 add_to_hard_reg_set (&live_hard_regs
,
6157 reg
->biggest_mode
, src_regno
);
6159 add_to_hard_reg_set (&live_hard_regs
,
6160 PSEUDO_REGNO_MODE (src_regno
),
6161 reg_renumber
[src_regno
]);
6163 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6166 /* Process used call regs. */
6167 if (curr_id
->arg_hard_regs
!= NULL
)
6168 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6169 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6171 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6172 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6174 for (i
= 0; i
< to_inherit_num
; i
++)
6176 src_regno
= to_inherit
[i
].regno
;
6177 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6178 curr_insn
, to_inherit
[i
].insns
))
6181 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6184 if (update_reloads_num_p
6185 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6188 if ((REG_P (SET_DEST (curr_set
))
6189 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6190 && reg_renumber
[regno
] < 0
6191 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6192 || (REG_P (SET_SRC (curr_set
))
6193 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6194 && reg_renumber
[regno
] < 0
6195 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6197 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6199 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6200 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6201 reg_class_contents
[cl
]);
6204 if (NONDEBUG_INSN_P (curr_insn
))
6208 /* Invalidate invariants with changed regs. */
6209 curr_id
= lra_get_insn_recog_data (curr_insn
);
6210 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6211 if (reg
->type
!= OP_IN
)
6213 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6214 bitmap_set_bit (&invalid_invariant_regs
,
6215 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6217 curr_static_id
= curr_id
->insn_static_data
;
6218 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6219 if (reg
->type
!= OP_IN
)
6220 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6221 if (curr_id
->arg_hard_regs
!= NULL
)
6222 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6223 if (regno
>= FIRST_PSEUDO_REGISTER
)
6224 bitmap_set_bit (&invalid_invariant_regs
,
6225 regno
- FIRST_PSEUDO_REGISTER
);
6227 /* We reached the start of the current basic block. */
6228 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6229 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6231 /* We reached the beginning of the current block -- do
6232 rest of spliting in the current BB. */
6233 to_process
= df_get_live_in (curr_bb
);
6234 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6236 /* We are somewhere in the middle of EBB. */
6237 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6238 curr_bb
, &temp_bitmap
);
6239 to_process
= &temp_bitmap
;
6242 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6244 if ((int) j
>= lra_constraint_new_regno_start
)
6246 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6247 && usage_insns
[j
].check
== curr_usage_insns_check
6248 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6250 if (need_for_split_p (potential_reload_hard_regs
, j
))
6252 if (lra_dump_file
!= NULL
&& head_p
)
6254 fprintf (lra_dump_file
,
6255 " ----------------------------------\n");
6258 if (split_reg (false, j
, bb_note (curr_bb
),
6262 usage_insns
[j
].check
= 0;
6270 /* This value affects EBB forming. If probability of edge from EBB to
6271 a BB is not greater than the following value, we don't add the BB
6273 #define EBB_PROBABILITY_CUTOFF \
6274 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6276 /* Current number of inheritance/split iteration. */
6277 int lra_inheritance_iter
;
6279 /* Entry function for inheritance/split pass. */
6281 lra_inheritance (void)
6284 basic_block bb
, start_bb
;
6287 lra_inheritance_iter
++;
6288 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6290 timevar_push (TV_LRA_INHERITANCE
);
6291 if (lra_dump_file
!= NULL
)
6292 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6293 lra_inheritance_iter
);
6294 curr_usage_insns_check
= 0;
6295 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6296 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6297 usage_insns
[i
].check
= 0;
6298 bitmap_initialize (&check_only_regs
, ®_obstack
);
6299 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6300 bitmap_initialize (&live_regs
, ®_obstack
);
6301 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6302 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6303 FOR_EACH_BB_FN (bb
, cfun
)
6306 if (lra_dump_file
!= NULL
)
6307 fprintf (lra_dump_file
, "EBB");
6308 /* Form a EBB starting with BB. */
6309 bitmap_clear (&ebb_global_regs
);
6310 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6313 if (lra_dump_file
!= NULL
)
6314 fprintf (lra_dump_file
, " %d", bb
->index
);
6315 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6316 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6318 e
= find_fallthru_edge (bb
->succs
);
6321 if (e
->probability
< EBB_PROBABILITY_CUTOFF
)
6325 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6326 if (lra_dump_file
!= NULL
)
6327 fprintf (lra_dump_file
, "\n");
6328 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6329 /* Remember that the EBB head and tail can change in
6331 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6333 bitmap_clear (&ebb_global_regs
);
6334 bitmap_clear (&temp_bitmap
);
6335 bitmap_clear (&live_regs
);
6336 bitmap_clear (&invalid_invariant_regs
);
6337 bitmap_clear (&check_only_regs
);
6340 timevar_pop (TV_LRA_INHERITANCE
);
6345 /* This page contains code to undo failed inheritance/split
6348 /* Current number of iteration undoing inheritance/split. */
6349 int lra_undo_inheritance_iter
;
6351 /* Fix BB live info LIVE after removing pseudos created on pass doing
6352 inheritance/split which are REMOVED_PSEUDOS. */
6354 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6359 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6360 if (bitmap_clear_bit (live
, regno
)
6361 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6362 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6365 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6370 if (GET_CODE (reg
) == SUBREG
)
6371 reg
= SUBREG_REG (reg
);
6377 /* Delete a move INSN with destination reg DREGNO and a previous
6378 clobber insn with the same regno. The inheritance/split code can
6379 generate moves with preceding clobber and when we delete such moves
6380 we should delete the clobber insn too to keep the correct life
6383 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6385 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6387 lra_set_insn_deleted (insn
);
6388 lra_assert (dregno
>= 0);
6389 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6390 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6391 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6392 lra_set_insn_deleted (prev_insn
);
6395 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6396 return true if we did any change. The undo transformations for
6397 inheritance looks like
6401 p <- i, i <- p, and i <- i3
6402 where p is original pseudo from which inheritance pseudo i was
6403 created, i and i3 are removed inheritance pseudos, i2 is another
6404 not removed inheritance pseudo. All split pseudos or other
6405 occurrences of removed inheritance pseudos are changed on the
6406 corresponding original pseudos.
6408 The function also schedules insns changed and created during
6409 inheritance/split pass for processing by the subsequent constraint
6412 remove_inheritance_pseudos (bitmap remove_pseudos
)
6415 int regno
, sregno
, prev_sregno
, dregno
;
6418 rtx_insn
*prev_insn
;
6419 bool change_p
, done_p
;
6421 change_p
= ! bitmap_empty_p (remove_pseudos
);
6422 /* We can not finish the function right away if CHANGE_P is true
6423 because we need to marks insns affected by previous
6424 inheritance/split pass for processing by the subsequent
6426 FOR_EACH_BB_FN (bb
, cfun
)
6428 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6429 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6430 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6432 if (! INSN_P (curr_insn
))
6435 sregno
= dregno
= -1;
6436 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6437 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6439 dregno
= get_regno (SET_DEST (set
));
6440 sregno
= get_regno (SET_SRC (set
));
6443 if (sregno
>= 0 && dregno
>= 0)
6445 if (bitmap_bit_p (remove_pseudos
, dregno
)
6446 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6448 /* invariant inheritance pseudo <- original pseudo */
6449 if (lra_dump_file
!= NULL
)
6451 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6452 dump_insn_slim (lra_dump_file
, curr_insn
);
6453 fprintf (lra_dump_file
, "\n");
6455 delete_move_and_clobber (curr_insn
, dregno
);
6458 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6459 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6461 /* reload pseudo <- invariant inheritance pseudo */
6463 /* We can not just change the source. It might be
6464 an insn different from the move. */
6465 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6466 rtx_insn
*new_insns
= get_insns ();
6468 lra_assert (single_set (new_insns
) != NULL
6469 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6470 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6471 "Changing reload<-invariant inheritance");
6472 delete_move_and_clobber (curr_insn
, dregno
);
6475 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6476 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6477 || (bitmap_bit_p (remove_pseudos
, dregno
)
6478 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6479 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6480 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6481 || (bitmap_bit_p (remove_pseudos
, dregno
)
6482 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6483 /* One of the following cases:
6484 original <- removed inheritance pseudo
6485 removed inherit pseudo <- another removed inherit pseudo
6486 removed inherit pseudo <- original pseudo
6488 removed_split_pseudo <- original_reg
6489 original_reg <- removed_split_pseudo */
6491 if (lra_dump_file
!= NULL
)
6493 fprintf (lra_dump_file
, " Removing %s:\n",
6494 bitmap_bit_p (&lra_split_regs
, sregno
)
6495 || bitmap_bit_p (&lra_split_regs
, dregno
)
6496 ? "split" : "inheritance");
6497 dump_insn_slim (lra_dump_file
, curr_insn
);
6499 delete_move_and_clobber (curr_insn
, dregno
);
6502 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6503 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6505 /* Search the following pattern:
6506 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6507 original_pseudo <- inherit_or_split_pseudo1
6508 where the 2nd insn is the current insn and
6509 inherit_or_split_pseudo2 is not removed. If it is found,
6510 change the current insn onto:
6511 original_pseudo <- inherit_or_split_pseudo2. */
6512 for (prev_insn
= PREV_INSN (curr_insn
);
6513 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6514 prev_insn
= PREV_INSN (prev_insn
))
6516 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6517 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6518 /* There should be no subregs in insn we are
6519 searching because only the original reg might
6520 be in subreg when we changed the mode of
6521 load/store for splitting. */
6522 && REG_P (SET_DEST (prev_set
))
6523 && REG_P (SET_SRC (prev_set
))
6524 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6525 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6526 >= FIRST_PSEUDO_REGISTER
)
6527 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6529 /* As we consider chain of inheritance or
6530 splitting described in above comment we should
6531 check that sregno and prev_sregno were
6532 inheritance/split pseudos created from the
6533 same original regno. */
6534 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6535 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6536 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6537 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6539 lra_assert (GET_MODE (SET_SRC (prev_set
))
6540 == GET_MODE (regno_reg_rtx
[sregno
]));
6541 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6542 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6544 SET_SRC (set
) = SET_SRC (prev_set
);
6545 /* As we are finishing with processing the insn
6546 here, check the destination too as it might
6547 inheritance pseudo for another pseudo. */
6548 if (bitmap_bit_p (remove_pseudos
, dregno
)
6549 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6551 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6553 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6554 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6556 SET_DEST (set
) = restore_rtx
;
6558 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6559 lra_set_used_insn_alternative_by_uid
6560 (INSN_UID (curr_insn
), -1);
6562 if (lra_dump_file
!= NULL
)
6564 fprintf (lra_dump_file
, " Change reload insn:\n");
6565 dump_insn_slim (lra_dump_file
, curr_insn
);
6572 struct lra_insn_reg
*reg
;
6573 bool restored_regs_p
= false;
6574 bool kept_regs_p
= false;
6576 curr_id
= lra_get_insn_recog_data (curr_insn
);
6577 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6580 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6581 if (restore_rtx
!= NULL_RTX
)
6583 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6585 lra_substitute_pseudo_within_insn
6586 (curr_insn
, regno
, restore_rtx
, false);
6587 restored_regs_p
= true;
6593 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6595 /* The instruction has changed since the previous
6596 constraints pass. */
6597 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6598 lra_set_used_insn_alternative_by_uid
6599 (INSN_UID (curr_insn
), -1);
6601 else if (restored_regs_p
)
6602 /* The instruction has been restored to the form that
6603 it had during the previous constraints pass. */
6604 lra_update_insn_regno_info (curr_insn
);
6605 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6607 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6608 dump_insn_slim (lra_dump_file
, curr_insn
);
6616 /* If optional reload pseudos failed to get a hard register or was not
6617 inherited, it is better to remove optional reloads. We do this
6618 transformation after undoing inheritance to figure out necessity to
6619 remove optional reloads easier. Return true if we do any
6622 undo_optional_reloads (void)
6624 bool change_p
, keep_p
;
6625 unsigned int regno
, uid
;
6626 bitmap_iterator bi
, bi2
;
6629 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
6631 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
6632 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6633 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6636 /* Keep optional reloads from previous subpasses. */
6637 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6638 /* If the original pseudo changed its allocation, just
6639 removing the optional pseudo is dangerous as the original
6640 pseudo will have longer live range. */
6641 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6643 else if (reg_renumber
[regno
] >= 0)
6644 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6646 insn
= lra_insn_recog_data
[uid
]->insn
;
6647 if ((set
= single_set (insn
)) == NULL_RTX
)
6649 src
= SET_SRC (set
);
6650 dest
= SET_DEST (set
);
6651 if (! REG_P (src
) || ! REG_P (dest
))
6653 if (REGNO (dest
) == regno
6654 /* Ignore insn for optional reloads itself. */
6655 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6656 /* Check only inheritance on last inheritance pass. */
6657 && (int) REGNO (src
) >= new_regno_start
6658 /* Check that the optional reload was inherited. */
6659 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6667 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
6668 if (lra_dump_file
!= NULL
)
6669 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6672 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
6673 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6674 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6676 if (lra_dump_file
!= NULL
)
6677 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6678 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6679 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6681 insn
= lra_insn_recog_data
[uid
]->insn
;
6682 if ((set
= single_set (insn
)) != NULL_RTX
)
6684 src
= SET_SRC (set
);
6685 dest
= SET_DEST (set
);
6686 if (REG_P (src
) && REG_P (dest
)
6687 && ((REGNO (src
) == regno
6688 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6690 || (REGNO (dest
) == regno
6691 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6694 if (lra_dump_file
!= NULL
)
6696 fprintf (lra_dump_file
, " Deleting move %u\n",
6698 dump_insn_slim (lra_dump_file
, insn
);
6700 delete_move_and_clobber (insn
, REGNO (dest
));
6703 /* We should not worry about generation memory-memory
6704 moves here as if the corresponding inheritance did
6705 not work (inheritance pseudo did not get a hard reg),
6706 we remove the inheritance pseudo and the optional
6709 lra_substitute_pseudo_within_insn
6710 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6711 lra_update_insn_regno_info (insn
);
6712 if (lra_dump_file
!= NULL
)
6714 fprintf (lra_dump_file
,
6715 " Restoring original insn:\n");
6716 dump_insn_slim (lra_dump_file
, insn
);
6720 /* Clear restore_regnos. */
6721 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6722 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6723 bitmap_clear (&insn_bitmap
);
6724 bitmap_clear (&removed_optional_reload_pseudos
);
6728 /* Entry function for undoing inheritance/split transformation. Return true
6729 if we did any RTL change in this pass. */
6731 lra_undo_inheritance (void)
6735 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6737 bitmap_head remove_pseudos
;
6741 lra_undo_inheritance_iter
++;
6742 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6744 if (lra_dump_file
!= NULL
)
6745 fprintf (lra_dump_file
,
6746 "\n********** Undoing inheritance #%d: **********\n\n",
6747 lra_undo_inheritance_iter
);
6748 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6749 n_inherit
= n_all_inherit
= 0;
6750 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6751 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6754 if (reg_renumber
[regno
] < 0
6755 /* If the original pseudo changed its allocation, just
6756 removing inheritance is dangerous as for changing
6757 allocation we used shorter live-ranges. */
6758 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6759 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6760 bitmap_set_bit (&remove_pseudos
, regno
);
6764 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6765 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6766 n_inherit
, n_all_inherit
,
6767 (double) n_inherit
/ n_all_inherit
* 100);
6768 n_split
= n_all_split
= 0;
6769 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6770 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6772 int restore_regno
= REGNO (restore_rtx
);
6775 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6776 ? reg_renumber
[restore_regno
] : restore_regno
);
6777 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6778 bitmap_set_bit (&remove_pseudos
, regno
);
6782 if (lra_dump_file
!= NULL
)
6783 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6784 regno
, restore_regno
);
6787 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6788 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6789 n_split
, n_all_split
,
6790 (double) n_split
/ n_all_split
* 100);
6791 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6792 bitmap_clear (&remove_pseudos
);
6793 /* Clear restore_regnos. */
6794 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6795 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6796 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6797 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6798 change_p
= undo_optional_reloads () || change_p
;