1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005-2017 Free Software Foundation, Inc.
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ; License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 config/rs6000/rs6000-opts.h
25 ;; ISA flag bits (on/off)
27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
30 HOST_WIDE_INT x_rs6000_isa_flags
32 ;; Miscellaneous flag bits that were set explicitly by the user
34 HOST_WIDE_INT rs6000_isa_flags_explicit
37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
43 ;; Always emit branch hint bits.
45 unsigned char rs6000_always_hint
47 ;; Schedule instructions for group formation.
49 unsigned char rs6000_sched_groups
51 ;; Align branch targets.
53 unsigned char rs6000_align_branch_targets
55 ;; Support for -msched-costly-dep option.
57 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
59 ;; Support for -minsert-sched-nops option.
61 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
63 ;; Non-zero to allow overriding loop alignment.
65 unsigned char can_override_loop_align
67 ;; Which small data model to use (for System V targets only)
69 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
71 ;; Bit size of immediate TLS offsets and string from which it is decoded.
73 int rs6000_tls_size = 32
75 ;; ABI enumeration available for subtarget to use.
77 enum rs6000_abi rs6000_current_abi = ABI_NONE
79 ;; Type of traceback to use.
81 enum rs6000_traceback_type rs6000_traceback = traceback_default
83 ;; Control alignment for fields within structures.
85 unsigned char rs6000_alignment_flags
87 ;; Code model for 64-bit linux.
89 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
91 ;; What type of reciprocal estimation instructions to generate
93 unsigned int rs6000_recip_control
95 ;; Mask of what builtin functions are allowed
97 HOST_WIDE_INT rs6000_builtin_mask
101 unsigned int rs6000_debug
103 ;; Whether to enable the -mfloat128 stuff without necessarily enabling the
104 ;; __float128 keyword.
106 unsigned char x_TARGET_FLOAT128_TYPE
109 unsigned char TARGET_FLOAT128_TYPE
111 ;; This option existed in the past, but now is always on.
113 Target RejectNegative Undocumented Ignore
116 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
117 Use PowerPC-64 instruction set.
120 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
121 Use PowerPC General Purpose group optional instructions.
124 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
125 Use PowerPC Graphics group optional instructions.
128 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
129 Use PowerPC V2.01 single field mfcr instruction.
132 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
133 Use PowerPC V2.02 popcntb instruction.
136 Target Report Mask(FPRND) Var(rs6000_isa_flags)
137 Use PowerPC V2.02 floating point rounding instructions.
140 Target Report Mask(CMPB) Var(rs6000_isa_flags)
141 Use PowerPC V2.05 compare bytes instruction.
144 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
145 Use extended PowerPC V2.05 move floating point to/from GPR instructions.
148 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
149 Use AltiVec instructions.
152 Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
153 Generate AltiVec instructions using little-endian element order.
156 Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
157 Generate AltiVec instructions using big-endian element order.
160 Target Report Var(rs6000_fold_gimple) Init(1)
161 Enable early gimple folding of builtins.
164 Target Report Mask(DFP) Var(rs6000_isa_flags)
165 Use decimal floating point instructions.
168 Target Report Mask(MULHW) Var(rs6000_isa_flags)
169 Use 4xx half-word multiply instructions.
172 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
173 Use 4xx string-search dlmzb instruction.
176 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
177 Generate load/store multiple instructions.
180 Target Report Mask(STRING) Var(rs6000_isa_flags)
181 Generate string instructions for block moves.
184 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
185 Do not use hardware floating point.
188 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
189 Use hardware floating point.
192 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
193 Use PowerPC V2.06 popcntd instruction.
196 Target Report Var(TARGET_FRIZ) Init(-1) Save
197 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
200 Target RejectNegative Joined Var(rs6000_veclibabi_name)
201 Vector library ABI to use.
204 Target Report Mask(VSX) Var(rs6000_isa_flags)
205 Use vector/scalar (VSX) instructions.
208 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
209 ; If -mvsx, set alignment to 128 bits instead of 32/64
212 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
213 ; Allow the movmisalign in DF/DI vectors
215 mefficient-unaligned-vsx
216 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
217 ; Consider unaligned VSX vector and fp accesses to be efficient
220 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
221 ; Explicitly set rs6000_sched_groups
224 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
225 ; Explicitly set rs6000_always_hint
227 malign-branch-targets
228 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
229 ; Explicitly set rs6000_align_branch_targets
232 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
233 Do not generate load/store with update instructions.
236 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
237 Generate load/store with update instructions.
240 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
241 Do not load the PIC register in function prologues.
243 mavoid-indexed-addresses
244 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
245 Avoid generation of indexed load/store instructions when possible.
248 Target Report Var(tls_markers) Init(1) Save
249 Mark __tls_get_addr calls with argument info.
252 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
255 Target Report Var(TARGET_SCHED_PROLOG) Save
256 Schedule the start and end of the procedure.
259 Target Report RejectNegative Var(aix_struct_return) Save
260 Return all structures in memory (AIX default).
263 Target Report RejectNegative Var(aix_struct_return,0) Save
264 Return small structures in registers (SVR4 default).
267 Target Report Var(TARGET_XL_COMPAT) Save
268 Conform more closely to IBM XLC semantics.
272 Generate software reciprocal divide and square root for better throughput.
275 Target Report RejectNegative Joined Var(rs6000_recip_name)
276 Generate software reciprocal divide and square root for better throughput.
279 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
280 Assume that the reciprocal estimate instructions provide more accuracy.
283 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
284 Do not place floating point constants in TOC.
287 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
288 Place floating point constants in TOC.
291 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
292 Do not place symbol+offset constants in TOC.
295 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
296 Place symbol+offset constants in TOC.
298 ; Output only one TOC entry per module. Normally linking fails if
299 ; there are more than 16K unique variables/constants in an executable. With
300 ; this option, linking fails only if there are more than 16K modules, or
301 ; if there are more than 16K unique variables/constant in a single module.
303 ; This is at the cost of having 2 extra loads and one extra store per
304 ; function, and one less allocable register.
306 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
307 Use only one TOC entry per procedure.
311 Put everything in the regular TOC.
314 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
315 Generate VRSAVE instructions when generating AltiVec code.
318 Target RejectNegative Alias(mvrsave) NegativeAlias
319 Deprecated option. Use -mno-vrsave instead.
322 Target RejectNegative Alias(mvrsave)
323 Deprecated option. Use -mvrsave instead.
325 mblock-move-inline-limit=
326 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
327 Specify how many bytes should be moved inline before calling out to memcpy/memmove.
329 mblock-compare-inline-limit=
330 Target Report Var(rs6000_block_compare_inline_limit) Init(5) RejectNegative Joined UInteger Save
331 Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to memcmp will be generated instead.
333 mstring-compare-inline-limit=
334 Target Report Var(rs6000_string_compare_inline_limit) Init(8) RejectNegative Joined UInteger Save
335 Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to strncmp will be generated instead.
338 Target Report Mask(ISEL) Var(rs6000_isa_flags)
339 Generate isel instructions.
342 Target RejectNegative Alias(misel) NegativeAlias
343 Deprecated option. Use -mno-isel instead.
346 Target RejectNegative Alias(misel)
347 Deprecated option. Use -misel instead.
350 Target Var(rs6000_paired_float) Save
351 Generate PPC750CL paired-single instructions.
354 Target RejectNegative Joined
355 -mdebug= Enable debug output.
358 Target RejectNegative Var(rs6000_altivec_abi) Save
359 Use the AltiVec ABI extensions.
362 Target RejectNegative Var(rs6000_altivec_abi, 0)
363 Do not use the AltiVec ABI extensions.
366 Target RejectNegative Var(rs6000_elf_abi, 1) Save
370 Target RejectNegative Var(rs6000_elf_abi, 2)
373 ; These are here for testing during development only, do not document
374 ; in the manual please.
376 ; If we want Darwin's struct-by-value-in-regs ABI.
378 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
381 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
384 Target RejectNegative Var(rs6000_ieeequad) Save
387 Target RejectNegative Var(rs6000_ieeequad, 0)
390 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
391 -mcpu= Use features of and schedule code for given CPU.
394 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
395 -mtune= Schedule code for given CPU.
398 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
399 -mtraceback= Select full, part, or no traceback table.
402 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
405 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
408 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
411 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
414 Target Report Var(rs6000_default_long_calls) Save
415 Avoid all range limits on call instructions.
417 ; This option existed in the past, but now is always on.
419 Target RejectNegative Undocumented Ignore
422 Target Var(rs6000_warn_altivec_long) Init(1) Save
423 Warn about deprecated 'vector long ...' AltiVec type usage.
426 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
427 -mlong-double-<n> Specify size of long double (64 or 128 bits).
429 ; This option existed in the past, but now is always on.
431 Target RejectNegative Undocumented Ignore
434 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
435 Determine which dependences between insns are considered costly.
438 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
439 Specify which post scheduling nop insertion scheme to apply.
442 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
443 Specify alignment of structure fields default/natural.
446 Name(rs6000_alignment_flags) Type(unsigned char)
447 Valid arguments to -malign-:
450 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
453 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
455 mprioritize-restricted-insns=
456 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
457 Specify scheduling priority for dispatch slot restricted insns.
460 Target RejectNegative Var(rs6000_single_float) Save
461 Single-precision floating point unit.
464 Target RejectNegative Var(rs6000_double_float) Save
465 Double-precision floating point unit.
468 Target RejectNegative Var(rs6000_simple_fpu) Save
469 Floating point unit does not support divide & sqrt.
472 Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
473 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
476 Name(fpu_type_t) Type(enum fpu_type_t)
479 Enum(fpu_type_t) String(none) Value(FPU_NONE)
482 Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
485 Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
488 Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
491 Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
494 Target Var(rs6000_xilinx_fpu) Save
497 mpointers-to-nested-functions
498 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
499 Use r11 to hold the static link in calls to functions via pointers.
502 Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
503 Save the TOC in the prologue for indirect calls rather than inline.
505 ; This option existed in the past, but now is always the same as -mvsx.
507 Target RejectNegative Undocumented Ignore
510 Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
511 Fuse certain integer operations together for better performance on power8.
514 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
515 Allow sign extension in fusion operations.
518 Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
519 Use vector and scalar instructions added in ISA 2.07.
522 Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
523 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
526 Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
527 Use ISA 2.07 direct move between GPR & VSX register instructions.
530 Target Report Mask(HTM) Var(rs6000_isa_flags)
531 Use ISA 2.07 transactional memory (HTM) instructions.
534 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
535 Generate the quad word memory instructions (lq/stq).
538 Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
539 Generate the quad word memory atomic instructions (lqarx/stqcx).
542 Target Report Var(rs6000_compat_align_parm) Init(0) Save
543 Generate aggregate parameter passing code with at most 64-bit alignment.
546 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
547 Analyze and remove doubleword swaps from VSX computations.
550 Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
551 Fuse certain operations together for better performance on power9.
554 Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
555 Use certain scalar instructions added in ISA 3.0.
558 Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
559 Use vector instructions added in ISA 3.0.
562 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
563 Use the new min/max instructions defined in ISA 3.0.
566 Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
567 Fuse medium/large code model toc references with the memory instruction.
570 Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
571 Generate the integer modulo instructions.
574 Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
575 Enable IEEE 128-bit floating point via the __float128 keyword.
578 Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
579 Enable using IEEE 128-bit floating point instructions.
582 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
583 Enable default conversions between __float128 & long double.
585 mstack-protector-guard=
586 Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
587 Use given stack-protector guard.
590 Name(stack_protector_guard) Type(enum stack_protector_guard)
591 Valid arguments to -mstack-protector-guard=:
594 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
597 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
599 mstack-protector-guard-reg=
600 Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
601 Use the given base register for addressing the stack-protector guard.
604 int rs6000_stack_protector_guard_reg = 0
606 mstack-protector-guard-offset=
607 Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
608 Use the given offset for addressing the stack-protector guard.
611 long rs6000_stack_protector_guard_offset = 0