| blob | eb9eff45a58eae302a381474519affb018c3c190 |
1 ;; AltiVec patterns.
2 ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to the
19 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 ;; MA 02110-1301, USA.
22 (define_constants
23 [(UNSPEC_VCMPBFP 50)
24 (UNSPEC_VCMPEQUB 51)
25 (UNSPEC_VCMPEQUH 52)
26 (UNSPEC_VCMPEQUW 53)
27 (UNSPEC_VCMPEQFP 54)
28 (UNSPEC_VCMPGEFP 55)
29 (UNSPEC_VCMPGTUB 56)
30 (UNSPEC_VCMPGTSB 57)
31 (UNSPEC_VCMPGTUH 58)
32 (UNSPEC_VCMPGTSH 59)
33 (UNSPEC_VCMPGTUW 60)
34 (UNSPEC_VCMPGTSW 61)
35 (UNSPEC_VCMPGTFP 62)
36 (UNSPEC_VMSUMU 65)
37 (UNSPEC_VMSUMM 66)
38 (UNSPEC_VMSUMSHM 68)
39 (UNSPEC_VMSUMUHS 69)
40 (UNSPEC_VMSUMSHS 70)
41 (UNSPEC_VMHADDSHS 71)
42 (UNSPEC_VMHRADDSHS 72)
43 (UNSPEC_VMLADDUHM 73)
44 (UNSPEC_VADDCUW 75)
45 (UNSPEC_VADDU 76)
46 (UNSPEC_VADDS 77)
47 (UNSPEC_VAVGU 80)
48 (UNSPEC_VAVGS 81)
49 (UNSPEC_VMULEUB 83)
50 (UNSPEC_VMULESB 84)
51 (UNSPEC_VMULEUH 85)
52 (UNSPEC_VMULESH 86)
53 (UNSPEC_VMULOUB 87)
54 (UNSPEC_VMULOSB 88)
55 (UNSPEC_VMULOUH 89)
56 (UNSPEC_VMULOSH 90)
57 (UNSPEC_VPKUHUM 93)
58 (UNSPEC_VPKUWUM 94)
59 (UNSPEC_VPKPX 95)
60 (UNSPEC_VPKSHSS 97)
61 (UNSPEC_VPKSWSS 99)
62 (UNSPEC_VPKUHUS 100)
63 (UNSPEC_VPKSHUS 101)
64 (UNSPEC_VPKUWUS 102)
65 (UNSPEC_VPKSWUS 103)
66 (UNSPEC_VRL 104)
67 (UNSPEC_VSL 107)
68 (UNSPEC_VSLW 109)
69 (UNSPEC_VSLV4SI 110)
70 (UNSPEC_VSLO 111)
71 (UNSPEC_VSR 118)
72 (UNSPEC_VSRO 119)
73 (UNSPEC_VSUBCUW 124)
74 (UNSPEC_VSUBU 125)
75 (UNSPEC_VSUBS 126)
76 (UNSPEC_VSUM4UBS 131)
77 (UNSPEC_VSUM4S 132)
78 (UNSPEC_VSUM2SWS 134)
79 (UNSPEC_VSUMSWS 135)
80 (UNSPEC_VPERM 144)
81 (UNSPEC_VRFIP 148)
82 (UNSPEC_VRFIN 149)
83 (UNSPEC_VRFIM 150)
84 (UNSPEC_VCFUX 151)
85 (UNSPEC_VCFSX 152)
86 (UNSPEC_VCTUXS 153)
87 (UNSPEC_VCTSXS 154)
88 (UNSPEC_VLOGEFP 155)
89 (UNSPEC_VEXPTEFP 156)
90 (UNSPEC_VRSQRTEFP 157)
91 (UNSPEC_VREFP 158)
92 (UNSPEC_VSEL4SI 159)
93 (UNSPEC_VSEL4SF 160)
94 (UNSPEC_VSEL8HI 161)
95 (UNSPEC_VSEL16QI 162)
96 (UNSPEC_VLSDOI 163)
97 (UNSPEC_VUPKHSB 167)
98 (UNSPEC_VUPKHPX 168)
99 (UNSPEC_VUPKHSH 169)
100 (UNSPEC_VUPKLSB 170)
101 (UNSPEC_VUPKLPX 171)
102 (UNSPEC_VUPKLSH 172)
103 (UNSPEC_PREDICATE 173)
104 (UNSPEC_DST 190)
105 (UNSPEC_DSTT 191)
106 (UNSPEC_DSTST 192)
107 (UNSPEC_DSTSTT 193)
108 (UNSPEC_LVSL 194)
109 (UNSPEC_LVSR 195)
110 (UNSPEC_LVE 196)
111 (UNSPEC_STVX 201)
112 (UNSPEC_STVXL 202)
113 (UNSPEC_STVE 203)
114 (UNSPEC_SET_VSCR 213)
115 (UNSPEC_GET_VRSAVE 214)
116 (UNSPEC_REALIGN_LOAD 215)
117 (UNSPEC_REDUC_PLUS 217)
118 (UNSPEC_VECSH 219)
119 (UNSPEC_EXTEVEN_V4SI 220)
120 (UNSPEC_EXTEVEN_V8HI 221)
121 (UNSPEC_EXTEVEN_V16QI 222)
122 (UNSPEC_EXTEVEN_V4SF 223)
123 (UNSPEC_EXTODD_V4SI 224)
124 (UNSPEC_EXTODD_V8HI 225)
125 (UNSPEC_EXTODD_V16QI 226)
126 (UNSPEC_EXTODD_V4SF 227)
127 (UNSPEC_INTERHI_V4SI 228)
128 (UNSPEC_INTERHI_V8HI 229)
129 (UNSPEC_INTERHI_V16QI 230)
130 (UNSPEC_INTERHI_V4SF 231)
131 (UNSPEC_INTERLO_V4SI 232)
132 (UNSPEC_INTERLO_V8HI 233)
133 (UNSPEC_INTERLO_V16QI 234)
134 (UNSPEC_INTERLO_V4SF 235)
135 (UNSPEC_ASHL 236)
136 (UNSPEC_VCOND_V4SI 301)
137 (UNSPEC_VCOND_V4SF 302)
138 (UNSPEC_VCOND_V8HI 303)
139 (UNSPEC_VCOND_V16QI 304)
140 (UNSPEC_VCONDU_V4SI 305)
141 (UNSPEC_VCONDU_V8HI 306)
142 (UNSPEC_VCONDU_V16QI 307)
143 (UNSPEC_VMULWHUB 308)
144 (UNSPEC_VMULWLUB 309)
145 (UNSPEC_VMULWHSB 310)
146 (UNSPEC_VMULWLSB 311)
147 (UNSPEC_VMULWHUH 312)
148 (UNSPEC_VMULWLUH 313)
149 (UNSPEC_VMULWHSH 314)
150 (UNSPEC_VMULWLSH 315)
151 (UNSPEC_VUPKHUB 316)
152 (UNSPEC_VUPKHUH 317)
153 (UNSPEC_VUPKLUB 318)
154 (UNSPEC_VUPKLUH 319)
155 (UNSPEC_VPERMSI 320)
156 (UNSPEC_VPERMHI 321)
157 (UNSPEC_INTERHI 322)
158 (UNSPEC_INTERLO 323)
159 ])
161 (define_constants
162 [(UNSPECV_SET_VRSAVE 30)
163 (UNSPECV_MTVSCR 186)
164 (UNSPECV_MFVSCR 187)
165 (UNSPECV_DSSALL 188)
166 (UNSPECV_DSS 189)
167 ])
169 ;; Vec int modes
170 (define_mode_macro VI [V4SI V8HI V16QI])
171 ;; Short vec in modes
172 (define_mode_macro VIshort [V8HI V16QI])
173 ;; Vec float modes
174 (define_mode_macro VF [V4SF])
175 ;; Vec modes, pity mode macros are not composable
176 (define_mode_macro V [V4SI V8HI V16QI V4SF])
178 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
180 ;; Generic LVX load instruction.
181 (define_insn "altivec_lvx_<mode>"
182 [(set (match_operand:V 0 "altivec_register_operand" "=v")
183 (match_operand:V 1 "memory_operand" "Z"))]
184 "TARGET_ALTIVEC"
185 "lvx %0,%y1"
186 [(set_attr "type" "vecload")])
188 ;; Generic STVX store instruction.
189 (define_insn "altivec_stvx_<mode>"
190 [(set (match_operand:V 0 "memory_operand" "=Z")
191 (match_operand:V 1 "altivec_register_operand" "v"))]
192 "TARGET_ALTIVEC"
193 "stvx %1,%y0"
194 [(set_attr "type" "vecstore")])
196 ;; Vector move instructions.
197 (define_expand "mov<mode>"
198 [(set (match_operand:V 0 "nonimmediate_operand" "")
199 (match_operand:V 1 "any_operand" ""))]
200 "TARGET_ALTIVEC"
201 {
202 rs6000_emit_move (operands[0], operands[1], <MODE>mode);
203 DONE;
204 })
206 (define_insn "*mov<mode>_internal"
207 [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
208 (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
209 "TARGET_ALTIVEC
210 && (register_operand (operands[0], <MODE>mode)
211 || register_operand (operands[1], <MODE>mode))"
212 {
213 switch (which_alternative)
214 {
215 case 0: return "stvx %1,%y0";
216 case 1: return "lvx %0,%y1";
217 case 2: return "vor %0,%1,%1";
218 case 3: return "#";
219 case 4: return "#";
220 case 5: return "#";
221 case 6: return output_vec_const_move (operands);
222 default: gcc_unreachable ();
223 }
224 }
225 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
227 (define_split
228 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
229 (match_operand:V4SI 1 "input_operand" ""))]
230 "TARGET_ALTIVEC && reload_completed
231 && gpr_or_gpr_p (operands[0], operands[1])"
232 [(pc)]
233 {
234 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
235 })
237 (define_split
238 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
239 (match_operand:V8HI 1 "input_operand" ""))]
240 "TARGET_ALTIVEC && reload_completed
241 && gpr_or_gpr_p (operands[0], operands[1])"
242 [(pc)]
243 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
245 (define_split
246 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
247 (match_operand:V16QI 1 "input_operand" ""))]
248 "TARGET_ALTIVEC && reload_completed
249 && gpr_or_gpr_p (operands[0], operands[1])"
250 [(pc)]
251 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
253 (define_split
254 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
255 (match_operand:V4SF 1 "input_operand" ""))]
256 "TARGET_ALTIVEC && reload_completed
257 && gpr_or_gpr_p (operands[0], operands[1])"
258 [(pc)]
259 {
260 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
261 })
263 (define_split
264 [(set (match_operand:VI 0 "altivec_register_operand" "")
265 (match_operand:VI 1 "easy_vector_constant_add_self" ""))]
266 "TARGET_ALTIVEC && reload_completed"
267 [(set (match_dup 0) (match_dup 3))
268 (set (match_dup 0) (plus:VI (match_dup 0)
269 (match_dup 0)))]
270 {
271 rtx dup = gen_easy_altivec_constant (operands[1]);
272 rtx const_vec;
274 /* Divide the operand of the resulting VEC_DUPLICATE, and use
275 simplify_rtx to make a CONST_VECTOR. */
276 XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
277 XEXP (dup, 0), const1_rtx);
278 const_vec = simplify_rtx (dup);
280 if (GET_MODE (const_vec) == <MODE>mode)
281 operands[3] = const_vec;
282 else
283 operands[3] = gen_lowpart (<MODE>mode, const_vec);
284 })
286 (define_insn "get_vrsave_internal"
287 [(set (match_operand:SI 0 "register_operand" "=r")
288 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
289 "TARGET_ALTIVEC"
290 {
291 if (TARGET_MACHO)
292 return "mfspr %0,256";
293 else
294 return "mfvrsave %0";
295 }
296 [(set_attr "type" "*")])
298 (define_insn "*set_vrsave_internal"
299 [(match_parallel 0 "vrsave_operation"
300 [(set (reg:SI 109)
301 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
302 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
303 "TARGET_ALTIVEC"
304 {
305 if (TARGET_MACHO)
306 return "mtspr 256,%1";
307 else
308 return "mtvrsave %1";
309 }
310 [(set_attr "type" "*")])
312 (define_insn "*save_world"
313 [(match_parallel 0 "save_world_operation"
314 [(clobber (match_operand:SI 1 "register_operand" "=l"))
315 (use (match_operand:SI 2 "call_operand" "s"))])]
316 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
317 "bl %z2"
318 [(set_attr "type" "branch")
319 (set_attr "length" "4")])
321 (define_insn "*restore_world"
322 [(match_parallel 0 "restore_world_operation"
323 [(return)
324 (use (match_operand:SI 1 "register_operand" "l"))
325 (use (match_operand:SI 2 "call_operand" "s"))
326 (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
327 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
328 "b %z2")
330 ;; Simple binary operations.
332 ;; add
333 (define_insn "add<mode>3"
334 [(set (match_operand:VI 0 "register_operand" "=v")
335 (plus:VI (match_operand:VI 1 "register_operand" "v")
336 (match_operand:VI 2 "register_operand" "v")))]
337 "TARGET_ALTIVEC"
338 "vaddu<VI_char>m %0,%1,%2"
339 [(set_attr "type" "vecsimple")])
341 (define_insn "addv4sf3"
342 [(set (match_operand:V4SF 0 "register_operand" "=v")
343 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
344 (match_operand:V4SF 2 "register_operand" "v")))]
345 "TARGET_ALTIVEC"
346 "vaddfp %0,%1,%2"
347 [(set_attr "type" "vecfloat")])
349 (define_insn "altivec_vaddcuw"
350 [(set (match_operand:V4SI 0 "register_operand" "=v")
351 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
352 (match_operand:V4SI 2 "register_operand" "v")]
353 UNSPEC_VADDCUW))]
354 "TARGET_ALTIVEC"
355 "vaddcuw %0,%1,%2"
356 [(set_attr "type" "vecsimple")])
358 (define_insn "altivec_vaddu<VI_char>s"
359 [(set (match_operand:VI 0 "register_operand" "=v")
360 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
361 (match_operand:VI 2 "register_operand" "v")]
362 UNSPEC_VADDU))
363 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
364 "TARGET_ALTIVEC"
365 "vaddu<VI_char>s %0,%1,%2"
366 [(set_attr "type" "vecsimple")])
368 (define_insn "altivec_vadds<VI_char>s"
369 [(set (match_operand:VI 0 "register_operand" "=v")
370 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
371 (match_operand:VI 2 "register_operand" "v")]
372 UNSPEC_VADDS))
373 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
374 "TARGET_ALTIVEC"
375 "vadds<VI_char>s %0,%1,%2"
376 [(set_attr "type" "vecsimple")])
378 ;; sub
379 (define_insn "sub<mode>3"
380 [(set (match_operand:VI 0 "register_operand" "=v")
381 (minus:VI (match_operand:VI 1 "register_operand" "v")
382 (match_operand:VI 2 "register_operand" "v")))]
383 "TARGET_ALTIVEC"
384 "vsubu<VI_char>m %0,%1,%2"
385 [(set_attr "type" "vecsimple")])
387 (define_insn "subv4sf3"
388 [(set (match_operand:V4SF 0 "register_operand" "=v")
389 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
390 (match_operand:V4SF 2 "register_operand" "v")))]
391 "TARGET_ALTIVEC"
392 "vsubfp %0,%1,%2"
393 [(set_attr "type" "vecfloat")])
395 (define_insn "altivec_vsubcuw"
396 [(set (match_operand:V4SI 0 "register_operand" "=v")
397 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
398 (match_operand:V4SI 2 "register_operand" "v")]
399 UNSPEC_VSUBCUW))]
400 "TARGET_ALTIVEC"
401 "vsubcuw %0,%1,%2"
402 [(set_attr "type" "vecsimple")])
404 (define_insn "altivec_vsubu<VI_char>s"
405 [(set (match_operand:VI 0 "register_operand" "=v")
406 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
407 (match_operand:VI 2 "register_operand" "v")]
408 UNSPEC_VSUBU))
409 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
410 "TARGET_ALTIVEC"
411 "vsubu<VI_char>s %0,%1,%2"
412 [(set_attr "type" "vecsimple")])
414 (define_insn "altivec_vsubs<VI_char>s"
415 [(set (match_operand:VI 0 "register_operand" "=v")
416 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
417 (match_operand:VI 2 "register_operand" "v")]
418 UNSPEC_VSUBS))
419 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
420 "TARGET_ALTIVEC"
421 "vsubs<VI_char>s %0,%1,%2"
422 [(set_attr "type" "vecsimple")])
424 ;;
425 (define_insn "altivec_vavgu<VI_char>"
426 [(set (match_operand:VI 0 "register_operand" "=v")
427 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
428 (match_operand:VI 2 "register_operand" "v")]
429 UNSPEC_VAVGU))]
430 "TARGET_ALTIVEC"
431 "vavgu<VI_char> %0,%1,%2"
432 [(set_attr "type" "vecsimple")])
434 (define_insn "altivec_vavgs<VI_char>"
435 [(set (match_operand:VI 0 "register_operand" "=v")
436 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
437 (match_operand:VI 2 "register_operand" "v")]
438 UNSPEC_VAVGS))]
439 "TARGET_ALTIVEC"
440 "vavgs<VI_char> %0,%1,%2"
441 [(set_attr "type" "vecsimple")])
443 (define_insn "altivec_vcmpbfp"
444 [(set (match_operand:V4SI 0 "register_operand" "=v")
445 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
446 (match_operand:V4SF 2 "register_operand" "v")]
447 UNSPEC_VCMPBFP))]
448 "TARGET_ALTIVEC"
449 "vcmpbfp %0,%1,%2"
450 [(set_attr "type" "veccmp")])
452 (define_insn "altivec_vcmpequb"
453 [(set (match_operand:V16QI 0 "register_operand" "=v")
454 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
455 (match_operand:V16QI 2 "register_operand" "v")]
456 UNSPEC_VCMPEQUB))]
457 "TARGET_ALTIVEC"
458 "vcmpequb %0,%1,%2"
459 [(set_attr "type" "vecsimple")])
461 (define_insn "altivec_vcmpequh"
462 [(set (match_operand:V8HI 0 "register_operand" "=v")
463 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
464 (match_operand:V8HI 2 "register_operand" "v")]
465 UNSPEC_VCMPEQUH))]
466 "TARGET_ALTIVEC"
467 "vcmpequh %0,%1,%2"
468 [(set_attr "type" "vecsimple")])
470 (define_insn "altivec_vcmpequw"
471 [(set (match_operand:V4SI 0 "register_operand" "=v")
472 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
473 (match_operand:V4SI 2 "register_operand" "v")]
474 UNSPEC_VCMPEQUW))]
475 "TARGET_ALTIVEC"
476 "vcmpequw %0,%1,%2"
477 [(set_attr "type" "vecsimple")])
479 (define_insn "altivec_vcmpeqfp"
480 [(set (match_operand:V4SI 0 "register_operand" "=v")
481 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
482 (match_operand:V4SF 2 "register_operand" "v")]
483 UNSPEC_VCMPEQFP))]
484 "TARGET_ALTIVEC"
485 "vcmpeqfp %0,%1,%2"
486 [(set_attr "type" "veccmp")])
488 (define_insn "altivec_vcmpgefp"
489 [(set (match_operand:V4SI 0 "register_operand" "=v")
490 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
491 (match_operand:V4SF 2 "register_operand" "v")]
492 UNSPEC_VCMPGEFP))]
493 "TARGET_ALTIVEC"
494 "vcmpgefp %0,%1,%2"
495 [(set_attr "type" "veccmp")])
497 (define_insn "altivec_vcmpgtub"
498 [(set (match_operand:V16QI 0 "register_operand" "=v")
499 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
500 (match_operand:V16QI 2 "register_operand" "v")]
501 UNSPEC_VCMPGTUB))]
502 "TARGET_ALTIVEC"
503 "vcmpgtub %0,%1,%2"
504 [(set_attr "type" "vecsimple")])
506 (define_insn "altivec_vcmpgtsb"
507 [(set (match_operand:V16QI 0 "register_operand" "=v")
508 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
509 (match_operand:V16QI 2 "register_operand" "v")]
510 UNSPEC_VCMPGTSB))]
511 "TARGET_ALTIVEC"
512 "vcmpgtsb %0,%1,%2"
513 [(set_attr "type" "vecsimple")])
515 (define_insn "altivec_vcmpgtuh"
516 [(set (match_operand:V8HI 0 "register_operand" "=v")
517 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
518 (match_operand:V8HI 2 "register_operand" "v")]
519 UNSPEC_VCMPGTUH))]
520 "TARGET_ALTIVEC"
521 "vcmpgtuh %0,%1,%2"
522 [(set_attr "type" "vecsimple")])
524 (define_insn "altivec_vcmpgtsh"
525 [(set (match_operand:V8HI 0 "register_operand" "=v")
526 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
527 (match_operand:V8HI 2 "register_operand" "v")]
528 UNSPEC_VCMPGTSH))]
529 "TARGET_ALTIVEC"
530 "vcmpgtsh %0,%1,%2"
531 [(set_attr "type" "vecsimple")])
533 (define_insn "altivec_vcmpgtuw"
534 [(set (match_operand:V4SI 0 "register_operand" "=v")
535 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
536 (match_operand:V4SI 2 "register_operand" "v")]
537 UNSPEC_VCMPGTUW))]
538 "TARGET_ALTIVEC"
539 "vcmpgtuw %0,%1,%2"
540 [(set_attr "type" "vecsimple")])
542 (define_insn "altivec_vcmpgtsw"
543 [(set (match_operand:V4SI 0 "register_operand" "=v")
544 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
545 (match_operand:V4SI 2 "register_operand" "v")]
546 UNSPEC_VCMPGTSW))]
547 "TARGET_ALTIVEC"
548 "vcmpgtsw %0,%1,%2"
549 [(set_attr "type" "vecsimple")])
551 (define_insn "altivec_vcmpgtfp"
552 [(set (match_operand:V4SI 0 "register_operand" "=v")
553 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
554 (match_operand:V4SF 2 "register_operand" "v")]
555 UNSPEC_VCMPGTFP))]
556 "TARGET_ALTIVEC"
557 "vcmpgtfp %0,%1,%2"
558 [(set_attr "type" "veccmp")])
560 ;; Fused multiply add
561 (define_insn "altivec_vmaddfp"
562 [(set (match_operand:V4SF 0 "register_operand" "=v")
563 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
564 (match_operand:V4SF 2 "register_operand" "v"))
565 (match_operand:V4SF 3 "register_operand" "v")))]
566 "TARGET_ALTIVEC"
567 "vmaddfp %0,%1,%2,%3"
568 [(set_attr "type" "vecfloat")])
570 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
572 (define_expand "mulv4sf3"
573 [(use (match_operand:V4SF 0 "register_operand" ""))
574 (use (match_operand:V4SF 1 "register_operand" ""))
575 (use (match_operand:V4SF 2 "register_operand" ""))]
576 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
577 "
578 {
579 rtx neg0;
581 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
582 neg0 = gen_reg_rtx (V4SFmode);
583 emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
584 emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
586 /* Use the multiply-add. */
587 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
588 neg0));
589 DONE;
590 }")
592 ;; 32 bit integer multiplication
593 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
594 ;; A_low = Operand_0 & 0xFFFF
595 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
596 ;; B_low = Operand_1 & 0xFFFF
597 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
599 ;; (define_insn "mulv4si3"
600 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
601 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
602 ;; (match_operand:V4SI 2 "register_operand" "v")))]
603 (define_expand "mulv4si3"
604 [(use (match_operand:V4SI 0 "register_operand" ""))
605 (use (match_operand:V4SI 1 "register_operand" ""))
606 (use (match_operand:V4SI 2 "register_operand" ""))]
607 "TARGET_ALTIVEC"
608 "
609 {
610 rtx zero;
611 rtx swap;
612 rtx small_swap;
613 rtx sixteen;
614 rtx one;
615 rtx two;
616 rtx low_product;
617 rtx high_product;
619 zero = gen_reg_rtx (V4SImode);
620 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
622 sixteen = gen_reg_rtx (V4SImode);
623 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
625 swap = gen_reg_rtx (V4SImode);
626 emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
628 one = gen_reg_rtx (V8HImode);
629 convert_move (one, operands[1], 0);
631 two = gen_reg_rtx (V8HImode);
632 convert_move (two, operands[2], 0);
634 small_swap = gen_reg_rtx (V8HImode);
635 convert_move (small_swap, swap, 0);
637 low_product = gen_reg_rtx (V4SImode);
638 emit_insn (gen_altivec_vmulouh (low_product, one, two));
640 high_product = gen_reg_rtx (V4SImode);
641 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
643 emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
645 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
647 DONE;
648 }")
651 ;; Fused multiply subtract
652 (define_insn "altivec_vnmsubfp"
653 [(set (match_operand:V4SF 0 "register_operand" "=v")
654 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
655 (match_operand:V4SF 2 "register_operand" "v"))
656 (match_operand:V4SF 3 "register_operand" "v"))))]
657 "TARGET_ALTIVEC"
658 "vnmsubfp %0,%1,%2,%3"
659 [(set_attr "type" "vecfloat")])
661 (define_insn "altivec_vmsumu<VI_char>m"
662 [(set (match_operand:V4SI 0 "register_operand" "=v")
663 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
664 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
665 (match_operand:VIshort 2 "register_operand" "v")]
666 UNSPEC_VMSUMU)))]
667 "TARGET_ALTIVEC"
668 "vmsumu<VI_char>m %0,%1,%2,%3"
669 [(set_attr "type" "veccomplex")])
671 (define_insn "altivec_vmsumm<VI_char>m"
672 [(set (match_operand:V4SI 0 "register_operand" "=v")
673 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
674 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
675 (match_operand:VIshort 2 "register_operand" "v")]
676 UNSPEC_VMSUMM)))]
677 "TARGET_ALTIVEC"
678 "vmsumm<VI_char>m %0,%1,%2,%3"
679 [(set_attr "type" "veccomplex")])
681 (define_insn "altivec_vmsumshm"
682 [(set (match_operand:V4SI 0 "register_operand" "=v")
683 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
684 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
685 (match_operand:V8HI 2 "register_operand" "v")]
686 UNSPEC_VMSUMSHM)))]
687 "TARGET_ALTIVEC"
688 "vmsumshm %0,%1,%2,%3"
689 [(set_attr "type" "veccomplex")])
691 (define_insn "altivec_vmsumuhs"
692 [(set (match_operand:V4SI 0 "register_operand" "=v")
693 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
694 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
695 (match_operand:V8HI 2 "register_operand" "v")]
696 UNSPEC_VMSUMUHS)))
697 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
698 "TARGET_ALTIVEC"
699 "vmsumuhs %0,%1,%2,%3"
700 [(set_attr "type" "veccomplex")])
702 (define_insn "altivec_vmsumshs"
703 [(set (match_operand:V4SI 0 "register_operand" "=v")
704 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
705 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
706 (match_operand:V8HI 2 "register_operand" "v")]
707 UNSPEC_VMSUMSHS)))
708 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
709 "TARGET_ALTIVEC"
710 "vmsumshs %0,%1,%2,%3"
711 [(set_attr "type" "veccomplex")])
713 ;; max
715 (define_insn "umax<mode>3"
716 [(set (match_operand:VI 0 "register_operand" "=v")
717 (umax:VI (match_operand:VI 1 "register_operand" "v")
718 (match_operand:VI 2 "register_operand" "v")))]
719 "TARGET_ALTIVEC"
720 "vmaxu<VI_char> %0,%1,%2"
721 [(set_attr "type" "vecsimple")])
723 (define_insn "smax<mode>3"
724 [(set (match_operand:VI 0 "register_operand" "=v")
725 (smax:VI (match_operand:VI 1 "register_operand" "v")
726 (match_operand:VI 2 "register_operand" "v")))]
727 "TARGET_ALTIVEC"
728 "vmaxs<VI_char> %0,%1,%2"
729 [(set_attr "type" "vecsimple")])
731 (define_insn "smaxv4sf3"
732 [(set (match_operand:V4SF 0 "register_operand" "=v")
733 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
734 (match_operand:V4SF 2 "register_operand" "v")))]
735 "TARGET_ALTIVEC"
736 "vmaxfp %0,%1,%2"
737 [(set_attr "type" "veccmp")])
739 (define_insn "umin<mode>3"
740 [(set (match_operand:VI 0 "register_operand" "=v")
741 (umin:VI (match_operand:VI 1 "register_operand" "v")
742 (match_operand:VI 2 "register_operand" "v")))]
743 "TARGET_ALTIVEC"
744 "vminu<VI_char> %0,%1,%2"
745 [(set_attr "type" "vecsimple")])
747 (define_insn "smin<mode>3"
748 [(set (match_operand:VI 0 "register_operand" "=v")
749 (smin:VI (match_operand:VI 1 "register_operand" "v")
750 (match_operand:VI 2 "register_operand" "v")))]
751 "TARGET_ALTIVEC"
752 "vmins<VI_char> %0,%1,%2"
753 [(set_attr "type" "vecsimple")])
755 (define_insn "sminv4sf3"
756 [(set (match_operand:V4SF 0 "register_operand" "=v")
757 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
758 (match_operand:V4SF 2 "register_operand" "v")))]
759 "TARGET_ALTIVEC"
760 "vminfp %0,%1,%2"
761 [(set_attr "type" "veccmp")])
763 (define_insn "altivec_vmhaddshs"
764 [(set (match_operand:V8HI 0 "register_operand" "=v")
765 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
766 (match_operand:V8HI 2 "register_operand" "v")
767 (match_operand:V8HI 3 "register_operand" "v")]
768 UNSPEC_VMHADDSHS))
769 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
770 "TARGET_ALTIVEC"
771 "vmhaddshs %0,%1,%2,%3"
772 [(set_attr "type" "veccomplex")])
774 (define_insn "altivec_vmhraddshs"
775 [(set (match_operand:V8HI 0 "register_operand" "=v")
776 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
777 (match_operand:V8HI 2 "register_operand" "v")
778 (match_operand:V8HI 3 "register_operand" "v")]
779 UNSPEC_VMHRADDSHS))
780 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
781 "TARGET_ALTIVEC"
782 "vmhraddshs %0,%1,%2,%3"
783 [(set_attr "type" "veccomplex")])
785 (define_insn "altivec_vmladduhm"
786 [(set (match_operand:V8HI 0 "register_operand" "=v")
787 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
788 (match_operand:V8HI 2 "register_operand" "v")
789 (match_operand:V8HI 3 "register_operand" "v")]
790 UNSPEC_VMLADDUHM))]
791 "TARGET_ALTIVEC"
792 "vmladduhm %0,%1,%2,%3"
793 [(set_attr "type" "veccomplex")])
795 (define_insn "altivec_vmrghb"
796 [(set (match_operand:V16QI 0 "register_operand" "=v")
797 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
798 (parallel [(const_int 0)
799 (const_int 8)
800 (const_int 1)
801 (const_int 9)
802 (const_int 2)
803 (const_int 10)
804 (const_int 3)
805 (const_int 11)
806 (const_int 4)
807 (const_int 12)
808 (const_int 5)
809 (const_int 13)
810 (const_int 6)
811 (const_int 14)
812 (const_int 7)
813 (const_int 15)]))
814 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
815 (parallel [(const_int 8)
816 (const_int 0)
817 (const_int 9)
818 (const_int 1)
819 (const_int 10)
820 (const_int 2)
821 (const_int 11)
822 (const_int 3)
823 (const_int 12)
824 (const_int 4)
825 (const_int 13)
826 (const_int 5)
827 (const_int 14)
828 (const_int 6)
829 (const_int 15)
830 (const_int 7)]))
831 (const_int 21845)))]
832 "TARGET_ALTIVEC"
833 "vmrghb %0,%1,%2"
834 [(set_attr "type" "vecperm")])
836 (define_insn "altivec_vmrghh"
837 [(set (match_operand:V8HI 0 "register_operand" "=v")
838 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
839 (parallel [(const_int 0)
840 (const_int 4)
841 (const_int 1)
842 (const_int 5)
843 (const_int 2)
844 (const_int 6)
845 (const_int 3)
846 (const_int 7)]))
847 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
848 (parallel [(const_int 4)
849 (const_int 0)
850 (const_int 5)
851 (const_int 1)
852 (const_int 6)
853 (const_int 2)
854 (const_int 7)
855 (const_int 3)]))
856 (const_int 85)))]
857 "TARGET_ALTIVEC"
858 "vmrghh %0,%1,%2"
859 [(set_attr "type" "vecperm")])
861 (define_insn "altivec_vmrghw"
862 [(set (match_operand:V4SI 0 "register_operand" "=v")
863 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
864 (parallel [(const_int 0)
865 (const_int 2)
866 (const_int 1)
867 (const_int 3)]))
868 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
869 (parallel [(const_int 2)
870 (const_int 0)
871 (const_int 3)
872 (const_int 1)]))
873 (const_int 5)))]
874 "TARGET_ALTIVEC"
875 "vmrghw %0,%1,%2"
876 [(set_attr "type" "vecperm")])
878 (define_insn "altivec_vmrghsf"
879 [(set (match_operand:V4SF 0 "register_operand" "=v")
880 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
881 (parallel [(const_int 0)
882 (const_int 2)
883 (const_int 1)
884 (const_int 3)]))
885 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
886 (parallel [(const_int 2)
887 (const_int 0)
888 (const_int 3)
889 (const_int 1)]))
890 (const_int 5)))]
891 "TARGET_ALTIVEC"
892 "vmrghw %0,%1,%2"
893 [(set_attr "type" "vecperm")])
895 (define_insn "altivec_vmrglb"
896 [(set (match_operand:V16QI 0 "register_operand" "=v")
897 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
898 (parallel [(const_int 8)
899 (const_int 0)
900 (const_int 9)
901 (const_int 1)
902 (const_int 10)
903 (const_int 2)
904 (const_int 11)
905 (const_int 3)
906 (const_int 12)
907 (const_int 4)
908 (const_int 13)
909 (const_int 5)
910 (const_int 14)
911 (const_int 6)
912 (const_int 15)
913 (const_int 7)]))
914 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
915 (parallel [(const_int 0)
916 (const_int 8)
917 (const_int 1)
918 (const_int 9)
919 (const_int 2)
920 (const_int 10)
921 (const_int 3)
922 (const_int 11)
923 (const_int 4)
924 (const_int 12)
925 (const_int 5)
926 (const_int 13)
927 (const_int 6)
928 (const_int 14)
929 (const_int 7)
930 (const_int 15)]))
931 (const_int 21845)))]
932 "TARGET_ALTIVEC"
933 "vmrglb %0,%1,%2"
934 [(set_attr "type" "vecperm")])
936 (define_insn "altivec_vmrglh"
937 [(set (match_operand:V8HI 0 "register_operand" "=v")
938 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
939 (parallel [(const_int 4)
940 (const_int 0)
941 (const_int 5)
942 (const_int 1)
943 (const_int 6)
944 (const_int 2)
945 (const_int 7)
946 (const_int 3)]))
947 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
948 (parallel [(const_int 0)
949 (const_int 4)
950 (const_int 1)
951 (const_int 5)
952 (const_int 2)
953 (const_int 6)
954 (const_int 3)
955 (const_int 7)]))
956 (const_int 85)))]
957 "TARGET_ALTIVEC"
958 "vmrglh %0,%1,%2"
959 [(set_attr "type" "vecperm")])
961 (define_insn "altivec_vmrglw"
962 [(set (match_operand:V4SI 0 "register_operand" "=v")
963 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
964 (parallel [(const_int 2)
965 (const_int 0)
966 (const_int 3)
967 (const_int 1)]))
968 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
969 (parallel [(const_int 0)
970 (const_int 2)
971 (const_int 1)
972 (const_int 3)]))
973 (const_int 5)))]
974 "TARGET_ALTIVEC"
975 "vmrglw %0,%1,%2"
976 [(set_attr "type" "vecperm")])
978 (define_insn "altivec_vmrglsf"
979 [(set (match_operand:V4SF 0 "register_operand" "=v")
980 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
981 (parallel [(const_int 2)
982 (const_int 0)
983 (const_int 3)
984 (const_int 1)]))
985 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
986 (parallel [(const_int 0)
987 (const_int 2)
988 (const_int 1)
989 (const_int 3)]))
990 (const_int 5)))]
991 "TARGET_ALTIVEC"
992 "vmrglw %0,%1,%2"
993 [(set_attr "type" "vecperm")])
995 (define_insn "altivec_vmuleub"
996 [(set (match_operand:V8HI 0 "register_operand" "=v")
997 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
998 (match_operand:V16QI 2 "register_operand" "v")]
999 UNSPEC_VMULEUB))]
1000 "TARGET_ALTIVEC"
1001 "vmuleub %0,%1,%2"
1002 [(set_attr "type" "veccomplex")])
1004 (define_insn "altivec_vmulesb"
1005 [(set (match_operand:V8HI 0 "register_operand" "=v")
1006 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1007 (match_operand:V16QI 2 "register_operand" "v")]
1008 UNSPEC_VMULESB))]
1009 "TARGET_ALTIVEC"
1010 "vmulesb %0,%1,%2"
1011 [(set_attr "type" "veccomplex")])
1013 (define_insn "altivec_vmuleuh"
1014 [(set (match_operand:V4SI 0 "register_operand" "=v")
1015 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1016 (match_operand:V8HI 2 "register_operand" "v")]
1017 UNSPEC_VMULEUH))]
1018 "TARGET_ALTIVEC"
1019 "vmuleuh %0,%1,%2"
1020 [(set_attr "type" "veccomplex")])
1022 (define_insn "altivec_vmulesh"
1023 [(set (match_operand:V4SI 0 "register_operand" "=v")
1024 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1025 (match_operand:V8HI 2 "register_operand" "v")]
1026 UNSPEC_VMULESH))]
1027 "TARGET_ALTIVEC"
1028 "vmulesh %0,%1,%2"
1029 [(set_attr "type" "veccomplex")])
1031 (define_insn "altivec_vmuloub"
1032 [(set (match_operand:V8HI 0 "register_operand" "=v")
1033 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1034 (match_operand:V16QI 2 "register_operand" "v")]
1035 UNSPEC_VMULOUB))]
1036 "TARGET_ALTIVEC"
1037 "vmuloub %0,%1,%2"
1038 [(set_attr "type" "veccomplex")])
1040 (define_insn "altivec_vmulosb"
1041 [(set (match_operand:V8HI 0 "register_operand" "=v")
1042 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1043 (match_operand:V16QI 2 "register_operand" "v")]
1044 UNSPEC_VMULOSB))]
1045 "TARGET_ALTIVEC"
1046 "vmulosb %0,%1,%2"
1047 [(set_attr "type" "veccomplex")])
1049 (define_insn "altivec_vmulouh"
1050 [(set (match_operand:V4SI 0 "register_operand" "=v")
1051 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1052 (match_operand:V8HI 2 "register_operand" "v")]
1053 UNSPEC_VMULOUH))]
1054 "TARGET_ALTIVEC"
1055 "vmulouh %0,%1,%2"
1056 [(set_attr "type" "veccomplex")])
1058 (define_insn "altivec_vmulosh"
1059 [(set (match_operand:V4SI 0 "register_operand" "=v")
1060 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1061 (match_operand:V8HI 2 "register_operand" "v")]
1062 UNSPEC_VMULOSH))]
1063 "TARGET_ALTIVEC"
1064 "vmulosh %0,%1,%2"
1065 [(set_attr "type" "veccomplex")])
1068 ;; logical ops
1070 (define_insn "and<mode>3"
1071 [(set (match_operand:VI 0 "register_operand" "=v")
1072 (and:VI (match_operand:VI 1 "register_operand" "v")
1073 (match_operand:VI 2 "register_operand" "v")))]
1074 "TARGET_ALTIVEC"
1075 "vand %0,%1,%2"
1076 [(set_attr "type" "vecsimple")])
1078 (define_insn "ior<mode>3"
1079 [(set (match_operand:VI 0 "register_operand" "=v")
1080 (ior:VI (match_operand:VI 1 "register_operand" "v")
1081 (match_operand:VI 2 "register_operand" "v")))]
1082 "TARGET_ALTIVEC"
1083 "vor %0,%1,%2"
1084 [(set_attr "type" "vecsimple")])
1086 (define_insn "xor<mode>3"
1087 [(set (match_operand:VI 0 "register_operand" "=v")
1088 (xor:VI (match_operand:VI 1 "register_operand" "v")
1089 (match_operand:VI 2 "register_operand" "v")))]
1090 "TARGET_ALTIVEC"
1091 "vxor %0,%1,%2"
1092 [(set_attr "type" "vecsimple")])
1094 (define_insn "xorv4sf3"
1095 [(set (match_operand:V4SF 0 "register_operand" "=v")
1096 (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
1097 (match_operand:V4SF 2 "register_operand" "v")))]
1098 "TARGET_ALTIVEC"
1099 "vxor %0,%1,%2"
1100 [(set_attr "type" "vecsimple")])
1102 (define_insn "one_cmpl<mode>2"
1103 [(set (match_operand:VI 0 "register_operand" "=v")
1104 (not:VI (match_operand:VI 1 "register_operand" "v")))]
1105 "TARGET_ALTIVEC"
1106 "vnor %0,%1,%1"
1107 [(set_attr "type" "vecsimple")])
1109 (define_insn "altivec_nor<mode>3"
1110 [(set (match_operand:VI 0 "register_operand" "=v")
1111 (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1112 (match_operand:VI 2 "register_operand" "v"))))]
1113 "TARGET_ALTIVEC"
1114 "vnor %0,%1,%2"
1115 [(set_attr "type" "vecsimple")])
1117 (define_insn "andc<mode>3"
1118 [(set (match_operand:VI 0 "register_operand" "=v")
1119 (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1120 (match_operand:VI 1 "register_operand" "v")))]
1121 "TARGET_ALTIVEC"
1122 "vandc %0,%1,%2"
1123 [(set_attr "type" "vecsimple")])
1125 (define_insn "*andc3_v4sf"
1126 [(set (match_operand:V4SF 0 "register_operand" "=v")
1127 (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1128 (match_operand:V4SF 1 "register_operand" "v")))]
1129 "TARGET_ALTIVEC"
1130 "vandc %0,%1,%2"
1131 [(set_attr "type" "vecsimple")])
1133 (define_insn "altivec_vpkuhum"
1134 [(set (match_operand:V16QI 0 "register_operand" "=v")
1135 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1136 (match_operand:V8HI 2 "register_operand" "v")]
1137 UNSPEC_VPKUHUM))]
1138 "TARGET_ALTIVEC"
1139 "vpkuhum %0,%1,%2"
1140 [(set_attr "type" "vecperm")])
1142 (define_insn "altivec_vpkuwum"
1143 [(set (match_operand:V8HI 0 "register_operand" "=v")
1144 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1145 (match_operand:V4SI 2 "register_operand" "v")]
1146 UNSPEC_VPKUWUM))]
1147 "TARGET_ALTIVEC"
1148 "vpkuwum %0,%1,%2"
1149 [(set_attr "type" "vecperm")])
1151 (define_insn "altivec_vpkpx"
1152 [(set (match_operand:V8HI 0 "register_operand" "=v")
1153 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1154 (match_operand:V4SI 2 "register_operand" "v")]
1155 UNSPEC_VPKPX))]
1156 "TARGET_ALTIVEC"
1157 "vpkpx %0,%1,%2"
1158 [(set_attr "type" "vecperm")])
1160 (define_insn "altivec_vpkshss"
1161 [(set (match_operand:V16QI 0 "register_operand" "=v")
1162 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1163 (match_operand:V8HI 2 "register_operand" "v")]
1164 UNSPEC_VPKSHSS))
1165 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1166 "TARGET_ALTIVEC"
1167 "vpkshss %0,%1,%2"
1168 [(set_attr "type" "vecperm")])
1170 (define_insn "altivec_vpkswss"
1171 [(set (match_operand:V8HI 0 "register_operand" "=v")
1172 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1173 (match_operand:V4SI 2 "register_operand" "v")]
1174 UNSPEC_VPKSWSS))
1175 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1176 "TARGET_ALTIVEC"
1177 "vpkswss %0,%1,%2"
1178 [(set_attr "type" "vecperm")])
1180 (define_insn "altivec_vpkuhus"
1181 [(set (match_operand:V16QI 0 "register_operand" "=v")
1182 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1183 (match_operand:V8HI 2 "register_operand" "v")]
1184 UNSPEC_VPKUHUS))
1185 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1186 "TARGET_ALTIVEC"
1187 "vpkuhus %0,%1,%2"
1188 [(set_attr "type" "vecperm")])
1190 (define_insn "altivec_vpkshus"
1191 [(set (match_operand:V16QI 0 "register_operand" "=v")
1192 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1193 (match_operand:V8HI 2 "register_operand" "v")]
1194 UNSPEC_VPKSHUS))
1195 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1196 "TARGET_ALTIVEC"
1197 "vpkshus %0,%1,%2"
1198 [(set_attr "type" "vecperm")])
1200 (define_insn "altivec_vpkuwus"
1201 [(set (match_operand:V8HI 0 "register_operand" "=v")
1202 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1203 (match_operand:V4SI 2 "register_operand" "v")]
1204 UNSPEC_VPKUWUS))
1205 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1206 "TARGET_ALTIVEC"
1207 "vpkuwus %0,%1,%2"
1208 [(set_attr "type" "vecperm")])
1210 (define_insn "altivec_vpkswus"
1211 [(set (match_operand:V8HI 0 "register_operand" "=v")
1212 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1213 (match_operand:V4SI 2 "register_operand" "v")]
1214 UNSPEC_VPKSWUS))
1215 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1216 "TARGET_ALTIVEC"
1217 "vpkswus %0,%1,%2"
1218 [(set_attr "type" "vecperm")])
1220 (define_insn "altivec_vrl<VI_char>"
1221 [(set (match_operand:VI 0 "register_operand" "=v")
1222 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1223 (match_operand:VI 2 "register_operand" "v")]
1224 UNSPEC_VRL))]
1225 "TARGET_ALTIVEC"
1226 "vrl<VI_char> %0,%1,%2"
1227 [(set_attr "type" "vecsimple")])
1229 (define_insn "altivec_vsl<VI_char>"
1230 [(set (match_operand:VI 0 "register_operand" "=v")
1231 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1232 (match_operand:VI 2 "register_operand" "v")]
1233 UNSPEC_VSL))]
1234 "TARGET_ALTIVEC"
1235 "vsl<VI_char> %0,%1,%2"
1236 [(set_attr "type" "vecsimple")])
1238 (define_insn "altivec_vslw_v4sf"
1239 [(set (match_operand:V4SF 0 "register_operand" "=v")
1240 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1241 (match_operand:V4SF 2 "register_operand" "v")]
1242 UNSPEC_VSLW))]
1243 "TARGET_ALTIVEC"
1244 "vslw %0,%1,%2"
1245 [(set_attr "type" "vecsimple")])
1247 (define_insn "altivec_vsl"
1248 [(set (match_operand:V4SI 0 "register_operand" "=v")
1249 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1250 (match_operand:V4SI 2 "register_operand" "v")]
1251 UNSPEC_VSLV4SI))]
1252 "TARGET_ALTIVEC"
1253 "vsl %0,%1,%2"
1254 [(set_attr "type" "vecperm")])
1256 (define_insn "altivec_vslo"
1257 [(set (match_operand:V4SI 0 "register_operand" "=v")
1258 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1259 (match_operand:V4SI 2 "register_operand" "v")]
1260 UNSPEC_VSLO))]
1261 "TARGET_ALTIVEC"
1262 "vslo %0,%1,%2"
1263 [(set_attr "type" "vecperm")])
1265 (define_insn "lshr<mode>3"
1266 [(set (match_operand:VI 0 "register_operand" "=v")
1267 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1268 (match_operand:VI 2 "register_operand" "v") ))]
1269 "TARGET_ALTIVEC"
1270 "vsr<VI_char> %0,%1,%2"
1271 [(set_attr "type" "vecsimple")])
1273 (define_insn "ashr<mode>3"
1274 [(set (match_operand:VI 0 "register_operand" "=v")
1275 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1276 (match_operand:VI 2 "register_operand" "v") ))]
1277 "TARGET_ALTIVEC"
1278 "vsra<VI_char> %0,%1,%2"
1279 [(set_attr "type" "vecsimple")])
1281 (define_insn "altivec_vsr"
1282 [(set (match_operand:V4SI 0 "register_operand" "=v")
1283 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1284 (match_operand:V4SI 2 "register_operand" "v")]
1285 UNSPEC_VSR))]
1286 "TARGET_ALTIVEC"
1287 "vsr %0,%1,%2"
1288 [(set_attr "type" "vecperm")])
1290 (define_insn "altivec_vsro"
1291 [(set (match_operand:V4SI 0 "register_operand" "=v")
1292 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1293 (match_operand:V4SI 2 "register_operand" "v")]
1294 UNSPEC_VSRO))]
1295 "TARGET_ALTIVEC"
1296 "vsro %0,%1,%2"
1297 [(set_attr "type" "vecperm")])
1299 (define_insn "altivec_vsum4ubs"
1300 [(set (match_operand:V4SI 0 "register_operand" "=v")
1301 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1302 (match_operand:V4SI 2 "register_operand" "v")]
1303 UNSPEC_VSUM4UBS))
1304 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1305 "TARGET_ALTIVEC"
1306 "vsum4ubs %0,%1,%2"
1307 [(set_attr "type" "veccomplex")])
1309 (define_insn "altivec_vsum4s<VI_char>s"
1310 [(set (match_operand:V4SI 0 "register_operand" "=v")
1311 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1312 (match_operand:V4SI 2 "register_operand" "v")]
1313 UNSPEC_VSUM4S))
1314 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1315 "TARGET_ALTIVEC"
1316 "vsum4s<VI_char>s %0,%1,%2"
1317 [(set_attr "type" "veccomplex")])
1319 (define_insn "altivec_vsum2sws"
1320 [(set (match_operand:V4SI 0 "register_operand" "=v")
1321 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1322 (match_operand:V4SI 2 "register_operand" "v")]
1323 UNSPEC_VSUM2SWS))
1324 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1325 "TARGET_ALTIVEC"
1326 "vsum2sws %0,%1,%2"
1327 [(set_attr "type" "veccomplex")])
1329 (define_insn "altivec_vsumsws"
1330 [(set (match_operand:V4SI 0 "register_operand" "=v")
1331 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1332 (match_operand:V4SI 2 "register_operand" "v")]
1333 UNSPEC_VSUMSWS))
1334 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1335 "TARGET_ALTIVEC"
1336 "vsumsws %0,%1,%2"
1337 [(set_attr "type" "veccomplex")])
1339 (define_insn "altivec_vspltb"
1340 [(set (match_operand:V16QI 0 "register_operand" "=v")
1341 (vec_duplicate:V16QI
1342 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1343 (parallel
1344 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1345 "TARGET_ALTIVEC"
1346 "vspltb %0,%1,%2"
1347 [(set_attr "type" "vecperm")])
1349 (define_insn "altivec_vsplth"
1350 [(set (match_operand:V8HI 0 "register_operand" "=v")
1351 (vec_duplicate:V8HI
1352 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1353 (parallel
1354 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1355 "TARGET_ALTIVEC"
1356 "vsplth %0,%1,%2"
1357 [(set_attr "type" "vecperm")])
1359 (define_insn "altivec_vspltw"
1360 [(set (match_operand:V4SI 0 "register_operand" "=v")
1361 (vec_duplicate:V4SI
1362 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1363 (parallel
1364 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1365 "TARGET_ALTIVEC"
1366 "vspltw %0,%1,%2"
1367 [(set_attr "type" "vecperm")])
1369 (define_insn "*altivec_vspltsf"
1370 [(set (match_operand:V4SF 0 "register_operand" "=v")
1371 (vec_duplicate:V4SF
1372 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1373 (parallel
1374 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1375 "TARGET_ALTIVEC"
1376 "vspltw %0,%1,%2"
1377 [(set_attr "type" "vecperm")])
1379 (define_insn "altivec_vspltis<VI_char>"
1380 [(set (match_operand:VI 0 "register_operand" "=v")
1381 (vec_duplicate:VI
1382 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1383 "TARGET_ALTIVEC"
1384 "vspltis<VI_char> %0,%1"
1385 [(set_attr "type" "vecperm")])
1387 (define_insn "altivec_vspltisw_v4sf"
1388 [(set (match_operand:V4SF 0 "register_operand" "=v")
1389 (vec_duplicate:V4SF
1390 (float:SF (match_operand:QI 1 "s5bit_cint_operand" "i"))))]
1391 "TARGET_ALTIVEC"
1392 "vspltisw %0,%1"
1393 [(set_attr "type" "vecperm")])
1395 (define_insn "ftruncv4sf2"
1396 [(set (match_operand:V4SF 0 "register_operand" "=v")
1397 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1398 "TARGET_ALTIVEC"
1399 "vrfiz %0,%1"
1400 [(set_attr "type" "vecfloat")])
1402 (define_insn "altivec_vperm_<mode>"
1403 [(set (match_operand:V 0 "register_operand" "=v")
1404 (unspec:V [(match_operand:V 1 "register_operand" "v")
1405 (match_operand:V 2 "register_operand" "v")
1406 (match_operand:V16QI 3 "register_operand" "v")]
1407 UNSPEC_VPERM))]
1408 "TARGET_ALTIVEC"
1409 "vperm %0,%1,%2,%3"
1410 [(set_attr "type" "vecperm")])
1412 (define_insn "altivec_vrfip"
1413 [(set (match_operand:V4SF 0 "register_operand" "=v")
1414 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1415 UNSPEC_VRFIP))]
1416 "TARGET_ALTIVEC"
1417 "vrfip %0,%1"
1418 [(set_attr "type" "vecfloat")])
1420 (define_insn "altivec_vrfin"
1421 [(set (match_operand:V4SF 0 "register_operand" "=v")
1422 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1423 UNSPEC_VRFIN))]
1424 "TARGET_ALTIVEC"
1425 "vrfin %0,%1"
1426 [(set_attr "type" "vecfloat")])
1428 (define_insn "altivec_vrfim"
1429 [(set (match_operand:V4SF 0 "register_operand" "=v")
1430 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1431 UNSPEC_VRFIM))]
1432 "TARGET_ALTIVEC"
1433 "vrfim %0,%1"
1434 [(set_attr "type" "vecfloat")])
1436 (define_insn "altivec_vcfux"
1437 [(set (match_operand:V4SF 0 "register_operand" "=v")
1438 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1439 (match_operand:QI 2 "immediate_operand" "i")]
1440 UNSPEC_VCFUX))]
1441 "TARGET_ALTIVEC"
1442 "vcfux %0,%1,%2"
1443 [(set_attr "type" "vecfloat")])
1445 (define_insn "altivec_vcfsx"
1446 [(set (match_operand:V4SF 0 "register_operand" "=v")
1447 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1448 (match_operand:QI 2 "immediate_operand" "i")]
1449 UNSPEC_VCFSX))]
1450 "TARGET_ALTIVEC"
1451 "vcfsx %0,%1,%2"
1452 [(set_attr "type" "vecfloat")])
1454 (define_insn "altivec_vctuxs"
1455 [(set (match_operand:V4SI 0 "register_operand" "=v")
1456 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1457 (match_operand:QI 2 "immediate_operand" "i")]
1458 UNSPEC_VCTUXS))
1459 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1460 "TARGET_ALTIVEC"
1461 "vctuxs %0,%1,%2"
1462 [(set_attr "type" "vecfloat")])
1464 (define_insn "altivec_vctsxs"
1465 [(set (match_operand:V4SI 0 "register_operand" "=v")
1466 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1467 (match_operand:QI 2 "immediate_operand" "i")]
1468 UNSPEC_VCTSXS))
1469 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1470 "TARGET_ALTIVEC"
1471 "vctsxs %0,%1,%2"
1472 [(set_attr "type" "vecfloat")])
1474 (define_insn "altivec_vlogefp"
1475 [(set (match_operand:V4SF 0 "register_operand" "=v")
1476 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1477 UNSPEC_VLOGEFP))]
1478 "TARGET_ALTIVEC"
1479 "vlogefp %0,%1"
1480 [(set_attr "type" "vecfloat")])
1482 (define_insn "altivec_vexptefp"
1483 [(set (match_operand:V4SF 0 "register_operand" "=v")
1484 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1485 UNSPEC_VEXPTEFP))]
1486 "TARGET_ALTIVEC"
1487 "vexptefp %0,%1"
1488 [(set_attr "type" "vecfloat")])
1490 (define_insn "altivec_vrsqrtefp"
1491 [(set (match_operand:V4SF 0 "register_operand" "=v")
1492 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1493 UNSPEC_VRSQRTEFP))]
1494 "TARGET_ALTIVEC"
1495 "vrsqrtefp %0,%1"
1496 [(set_attr "type" "vecfloat")])
1498 (define_insn "altivec_vrefp"
1499 [(set (match_operand:V4SF 0 "register_operand" "=v")
1500 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1501 UNSPEC_VREFP))]
1502 "TARGET_ALTIVEC"
1503 "vrefp %0,%1"
1504 [(set_attr "type" "vecfloat")])
1506 (define_expand "vcondv4si"
1507 [(set (match_operand:V4SI 0 "register_operand" "=v")
1508 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1509 (match_operand:V4SI 2 "register_operand" "v")
1510 (match_operand:V4SI 3 "comparison_operator" "")
1511 (match_operand:V4SI 4 "register_operand" "v")
1512 (match_operand:V4SI 5 "register_operand" "v")
1513 ] UNSPEC_VCOND_V4SI))]
1514 "TARGET_ALTIVEC"
1515 "
1516 {
1517 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1518 operands[3], operands[4], operands[5]))
1519 DONE;
1520 else
1521 FAIL;
1522 }
1523 ")
1525 (define_expand "vconduv4si"
1526 [(set (match_operand:V4SI 0 "register_operand" "=v")
1527 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1528 (match_operand:V4SI 2 "register_operand" "v")
1529 (match_operand:V4SI 3 "comparison_operator" "")
1530 (match_operand:V4SI 4 "register_operand" "v")
1531 (match_operand:V4SI 5 "register_operand" "v")
1532 ] UNSPEC_VCONDU_V4SI))]
1533 "TARGET_ALTIVEC"
1534 "
1535 {
1536 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1537 operands[3], operands[4], operands[5]))
1538 DONE;
1539 else
1540 FAIL;
1541 }
1542 ")
1544 (define_expand "vcondv4sf"
1545 [(set (match_operand:V4SF 0 "register_operand" "=v")
1546 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1547 (match_operand:V4SF 2 "register_operand" "v")
1548 (match_operand:V4SF 3 "comparison_operator" "")
1549 (match_operand:V4SF 4 "register_operand" "v")
1550 (match_operand:V4SF 5 "register_operand" "v")
1551 ] UNSPEC_VCOND_V4SF))]
1552 "TARGET_ALTIVEC"
1553 "
1554 {
1555 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1556 operands[3], operands[4], operands[5]))
1557 DONE;
1558 else
1559 FAIL;
1560 }
1561 ")
1563 (define_expand "vcondv8hi"
1564 [(set (match_operand:V4SF 0 "register_operand" "=v")
1565 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1566 (match_operand:V8HI 2 "register_operand" "v")
1567 (match_operand:V8HI 3 "comparison_operator" "")
1568 (match_operand:V8HI 4 "register_operand" "v")
1569 (match_operand:V8HI 5 "register_operand" "v")
1570 ] UNSPEC_VCOND_V8HI))]
1571 "TARGET_ALTIVEC"
1572 "
1573 {
1574 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1575 operands[3], operands[4], operands[5]))
1576 DONE;
1577 else
1578 FAIL;
1579 }
1580 ")
1582 (define_expand "vconduv8hi"
1583 [(set (match_operand:V4SF 0 "register_operand" "=v")
1584 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1585 (match_operand:V8HI 2 "register_operand" "v")
1586 (match_operand:V8HI 3 "comparison_operator" "")
1587 (match_operand:V8HI 4 "register_operand" "v")
1588 (match_operand:V8HI 5 "register_operand" "v")
1589 ] UNSPEC_VCONDU_V8HI))]
1590 "TARGET_ALTIVEC"
1591 "
1592 {
1593 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1594 operands[3], operands[4], operands[5]))
1595 DONE;
1596 else
1597 FAIL;
1598 }
1599 ")
1601 (define_expand "vcondv16qi"
1602 [(set (match_operand:V4SF 0 "register_operand" "=v")
1603 (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1604 (match_operand:V16QI 2 "register_operand" "v")
1605 (match_operand:V16QI 3 "comparison_operator" "")
1606 (match_operand:V16QI 4 "register_operand" "v")
1607 (match_operand:V16QI 5 "register_operand" "v")
1608 ] UNSPEC_VCOND_V16QI))]
1609 "TARGET_ALTIVEC"
1610 "
1611 {
1612 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1613 operands[3], operands[4], operands[5]))
1614 DONE;
1615 else
1616 FAIL;
1617 }
1618 ")
1620 (define_expand "vconduv16qi"
1621 [(set (match_operand:V4SF 0 "register_operand" "=v")
1622 (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1623 (match_operand:V16QI 2 "register_operand" "v")
1624 (match_operand:V16QI 3 "comparison_operator" "")
1625 (match_operand:V16QI 4 "register_operand" "v")
1626 (match_operand:V16QI 5 "register_operand" "v")
1627 ] UNSPEC_VCONDU_V16QI))]
1628 "TARGET_ALTIVEC"
1629 "
1630 {
1631 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1632 operands[3], operands[4], operands[5]))
1633 DONE;
1634 else
1635 FAIL;
1636 }
1637 ")
1640 (define_insn "altivec_vsel_v4si"
1641 [(set (match_operand:V4SI 0 "register_operand" "=v")
1642 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1643 (match_operand:V4SI 2 "register_operand" "v")
1644 (match_operand:V4SI 3 "register_operand" "v")]
1645 UNSPEC_VSEL4SI))]
1646 "TARGET_ALTIVEC"
1647 "vsel %0,%1,%2,%3"
1648 [(set_attr "type" "vecperm")])
1650 (define_insn "altivec_vsel_v4sf"
1651 [(set (match_operand:V4SF 0 "register_operand" "=v")
1652 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1653 (match_operand:V4SF 2 "register_operand" "v")
1654 (match_operand:V4SI 3 "register_operand" "v")]
1655 UNSPEC_VSEL4SF))]
1656 "TARGET_ALTIVEC"
1657 "vsel %0,%1,%2,%3"
1658 [(set_attr "type" "vecperm")])
1660 (define_insn "altivec_vsel_v8hi"
1661 [(set (match_operand:V8HI 0 "register_operand" "=v")
1662 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1663 (match_operand:V8HI 2 "register_operand" "v")
1664 (match_operand:V8HI 3 "register_operand" "v")]
1665 UNSPEC_VSEL8HI))]
1666 "TARGET_ALTIVEC"
1667 "vsel %0,%1,%2,%3"
1668 [(set_attr "type" "vecperm")])
1670 (define_insn "altivec_vsel_v16qi"
1671 [(set (match_operand:V16QI 0 "register_operand" "=v")
1672 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1673 (match_operand:V16QI 2 "register_operand" "v")
1674 (match_operand:V16QI 3 "register_operand" "v")]
1675 UNSPEC_VSEL16QI))]
1676 "TARGET_ALTIVEC"
1677 "vsel %0,%1,%2,%3"
1678 [(set_attr "type" "vecperm")])
1680 (define_insn "altivec_vsldoi_<mode>"
1681 [(set (match_operand:V 0 "register_operand" "=v")
1682 (unspec:V [(match_operand:V 1 "register_operand" "v")
1683 (match_operand:V 2 "register_operand" "v")
1684 (match_operand:QI 3 "immediate_operand" "i")]
1685 UNSPEC_VLSDOI))]
1686 "TARGET_ALTIVEC"
1687 "vsldoi %0,%1,%2,%3"
1688 [(set_attr "type" "vecperm")])
1690 (define_insn "altivec_vupkhsb"
1691 [(set (match_operand:V8HI 0 "register_operand" "=v")
1692 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1693 UNSPEC_VUPKHSB))]
1694 "TARGET_ALTIVEC"
1695 "vupkhsb %0,%1"
1696 [(set_attr "type" "vecperm")])
1698 (define_insn "altivec_vupkhpx"
1699 [(set (match_operand:V4SI 0 "register_operand" "=v")
1700 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1701 UNSPEC_VUPKHPX))]
1702 "TARGET_ALTIVEC"
1703 "vupkhpx %0,%1"
1704 [(set_attr "type" "vecperm")])
1706 (define_insn "altivec_vupkhsh"
1707 [(set (match_operand:V4SI 0 "register_operand" "=v")
1708 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1709 UNSPEC_VUPKHSH))]
1710 "TARGET_ALTIVEC"
1711 "vupkhsh %0,%1"
1712 [(set_attr "type" "vecperm")])
1714 (define_insn "altivec_vupklsb"
1715 [(set (match_operand:V8HI 0 "register_operand" "=v")
1716 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1717 UNSPEC_VUPKLSB))]
1718 "TARGET_ALTIVEC"
1719 "vupklsb %0,%1"
1720 [(set_attr "type" "vecperm")])
1722 (define_insn "altivec_vupklpx"
1723 [(set (match_operand:V4SI 0 "register_operand" "=v")
1724 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1725 UNSPEC_VUPKLPX))]
1726 "TARGET_ALTIVEC"
1727 "vupklpx %0,%1"
1728 [(set_attr "type" "vecperm")])
1730 (define_insn "altivec_vupklsh"
1731 [(set (match_operand:V4SI 0 "register_operand" "=v")
1732 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1733 UNSPEC_VUPKLSH))]
1734 "TARGET_ALTIVEC"
1735 "vupklsh %0,%1"
1736 [(set_attr "type" "vecperm")])
1738 ;; AltiVec predicates.
1740 (define_expand "cr6_test_for_zero"
1741 [(set (match_operand:SI 0 "register_operand" "=r")
1742 (eq:SI (reg:CC 74)
1743 (const_int 0)))]
1744 "TARGET_ALTIVEC"
1745 "")
1747 (define_expand "cr6_test_for_zero_reverse"
1748 [(set (match_operand:SI 0 "register_operand" "=r")
1749 (eq:SI (reg:CC 74)
1750 (const_int 0)))
1751 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1752 "TARGET_ALTIVEC"
1753 "")
1755 (define_expand "cr6_test_for_lt"
1756 [(set (match_operand:SI 0 "register_operand" "=r")
1757 (lt:SI (reg:CC 74)
1758 (const_int 0)))]
1759 "TARGET_ALTIVEC"
1760 "")
1762 (define_expand "cr6_test_for_lt_reverse"
1763 [(set (match_operand:SI 0 "register_operand" "=r")
1764 (lt:SI (reg:CC 74)
1765 (const_int 0)))
1766 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1767 "TARGET_ALTIVEC"
1768 "")
1770 ;; We can get away with generating the opcode on the fly (%3 below)
1771 ;; because all the predicates have the same scheduling parameters.
1773 (define_insn "altivec_predicate_<mode>"
1774 [(set (reg:CC 74)
1775 (unspec:CC [(match_operand:V 1 "register_operand" "v")
1776 (match_operand:V 2 "register_operand" "v")
1777 (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1778 (clobber (match_scratch:V 0 "=v"))]
1779 "TARGET_ALTIVEC"
1780 "%3 %0,%1,%2"
1781 [(set_attr "type" "veccmp")])
1783 (define_insn "altivec_mtvscr"
1784 [(set (reg:SI 110)
1785 (unspec_volatile:SI
1786 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1787 "TARGET_ALTIVEC"
1788 "mtvscr %0"
1789 [(set_attr "type" "vecsimple")])
1791 (define_insn "altivec_mfvscr"
1792 [(set (match_operand:V8HI 0 "register_operand" "=v")
1793 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1794 "TARGET_ALTIVEC"
1795 "mfvscr %0"
1796 [(set_attr "type" "vecsimple")])
1798 (define_insn "altivec_dssall"
1799 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1800 "TARGET_ALTIVEC"
1801 "dssall"
1802 [(set_attr "type" "vecsimple")])
1804 (define_insn "altivec_dss"
1805 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1806 UNSPECV_DSS)]
1807 "TARGET_ALTIVEC"
1808 "dss %0"
1809 [(set_attr "type" "vecsimple")])
1811 (define_insn "altivec_dst"
1812 [(unspec [(match_operand 0 "register_operand" "b")
1813 (match_operand:SI 1 "register_operand" "r")
1814 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1815 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1816 "dst %0,%1,%2"
1817 [(set_attr "type" "vecsimple")])
1819 (define_insn "altivec_dstt"
1820 [(unspec [(match_operand 0 "register_operand" "b")
1821 (match_operand:SI 1 "register_operand" "r")
1822 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1823 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1824 "dstt %0,%1,%2"
1825 [(set_attr "type" "vecsimple")])
1827 (define_insn "altivec_dstst"
1828 [(unspec [(match_operand 0 "register_operand" "b")
1829 (match_operand:SI 1 "register_operand" "r")
1830 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1831 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1832 "dstst %0,%1,%2"
1833 [(set_attr "type" "vecsimple")])
1835 (define_insn "altivec_dststt"
1836 [(unspec [(match_operand 0 "register_operand" "b")
1837 (match_operand:SI 1 "register_operand" "r")
1838 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1839 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1840 "dststt %0,%1,%2"
1841 [(set_attr "type" "vecsimple")])
1843 (define_insn "altivec_lvsl"
1844 [(set (match_operand:V16QI 0 "register_operand" "=v")
1845 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1846 "TARGET_ALTIVEC"
1847 "lvsl %0,%y1"
1848 [(set_attr "type" "vecload")])
1850 (define_insn "altivec_lvsr"
1851 [(set (match_operand:V16QI 0 "register_operand" "=v")
1852 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1853 "TARGET_ALTIVEC"
1854 "lvsr %0,%y1"
1855 [(set_attr "type" "vecload")])
1857 (define_expand "build_vector_mask_for_load"
1858 [(set (match_operand:V16QI 0 "register_operand" "")
1859 (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1860 "TARGET_ALTIVEC"
1861 "
1862 {
1863 rtx addr;
1864 rtx temp;
1866 gcc_assert (GET_CODE (operands[1]) == MEM);
1868 addr = XEXP (operands[1], 0);
1869 temp = gen_reg_rtx (GET_MODE (addr));
1870 emit_insn (gen_rtx_SET (VOIDmode, temp,
1871 gen_rtx_NEG (GET_MODE (addr), addr)));
1872 emit_insn (gen_altivec_lvsr (operands[0],
1873 replace_equiv_address (operands[1], temp)));
1874 DONE;
1875 }")
1877 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1878 ;; identical rtl but different instructions-- and gcc gets confused.
1880 (define_insn "altivec_lve<VI_char>x"
1881 [(parallel
1882 [(set (match_operand:VI 0 "register_operand" "=v")
1883 (match_operand:VI 1 "memory_operand" "Z"))
1884 (unspec [(const_int 0)] UNSPEC_LVE)])]
1885 "TARGET_ALTIVEC"
1886 "lve<VI_char>x %0,%y1"
1887 [(set_attr "type" "vecload")])
1889 (define_insn "*altivec_lvesfx"
1890 [(parallel
1891 [(set (match_operand:V4SF 0 "register_operand" "=v")
1892 (match_operand:V4SF 1 "memory_operand" "Z"))
1893 (unspec [(const_int 0)] UNSPEC_LVE)])]
1894 "TARGET_ALTIVEC"
1895 "lvewx %0,%y1"
1896 [(set_attr "type" "vecload")])
1898 (define_insn "altivec_lvxl"
1899 [(parallel
1900 [(set (match_operand:V4SI 0 "register_operand" "=v")
1901 (match_operand:V4SI 1 "memory_operand" "Z"))
1902 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1903 "TARGET_ALTIVEC"
1904 "lvxl %0,%y1"
1905 [(set_attr "type" "vecload")])
1907 (define_insn "altivec_lvx"
1908 [(set (match_operand:V4SI 0 "register_operand" "=v")
1909 (match_operand:V4SI 1 "memory_operand" "Z"))]
1910 "TARGET_ALTIVEC"
1911 "lvx %0,%y1"
1912 [(set_attr "type" "vecload")])
1914 (define_insn "altivec_stvx"
1915 [(parallel
1916 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1917 (match_operand:V4SI 1 "register_operand" "v"))
1918 (unspec [(const_int 0)] UNSPEC_STVX)])]
1919 "TARGET_ALTIVEC"
1920 "stvx %1,%y0"
1921 [(set_attr "type" "vecstore")])
1923 (define_insn "altivec_stvxl"
1924 [(parallel
1925 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1926 (match_operand:V4SI 1 "register_operand" "v"))
1927 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1928 "TARGET_ALTIVEC"
1929 "stvxl %1,%y0"
1930 [(set_attr "type" "vecstore")])
1932 (define_insn "altivec_stve<VI_char>x"
1933 [(parallel
1934 [(set (match_operand:VI 0 "memory_operand" "=Z")
1935 (match_operand:VI 1 "register_operand" "v"))
1936 (unspec [(const_int 0)] UNSPEC_STVE)])]
1937 "TARGET_ALTIVEC"
1938 "stve<VI_char>x %1,%y0"
1939 [(set_attr "type" "vecstore")])
1941 (define_insn "*altivec_stvesfx"
1942 [(parallel
1943 [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1944 (match_operand:V4SF 1 "register_operand" "v"))
1945 (unspec [(const_int 0)] UNSPEC_STVE)])]
1946 "TARGET_ALTIVEC"
1947 "stvewx %1,%y0"
1948 [(set_attr "type" "vecstore")])
1950 (define_expand "vec_init<mode>"
1951 [(match_operand:V 0 "register_operand" "")
1952 (match_operand 1 "" "")]
1953 "TARGET_ALTIVEC"
1954 {
1955 rs6000_expand_vector_init (operands[0], operands[1]);
1956 DONE;
1957 })
1959 (define_expand "vec_setv4si"
1960 [(match_operand:V4SI 0 "register_operand" "")
1961 (match_operand:SI 1 "register_operand" "")
1962 (match_operand 2 "const_int_operand" "")]
1963 "TARGET_ALTIVEC"
1964 {
1965 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1966 DONE;
1967 })
1969 (define_expand "vec_setv8hi"
1970 [(match_operand:V8HI 0 "register_operand" "")
1971 (match_operand:HI 1 "register_operand" "")
1972 (match_operand 2 "const_int_operand" "")]
1973 "TARGET_ALTIVEC"
1974 {
1975 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1976 DONE;
1977 })
1979 (define_expand "vec_setv16qi"
1980 [(match_operand:V16QI 0 "register_operand" "")
1981 (match_operand:QI 1 "register_operand" "")
1982 (match_operand 2 "const_int_operand" "")]
1983 "TARGET_ALTIVEC"
1984 {
1985 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1986 DONE;
1987 })
1989 (define_expand "vec_setv4sf"
1990 [(match_operand:V4SF 0 "register_operand" "")
1991 (match_operand:SF 1 "register_operand" "")
1992 (match_operand 2 "const_int_operand" "")]
1993 "TARGET_ALTIVEC"
1994 {
1995 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1996 DONE;
1997 })
1999 (define_expand "vec_extractv4si"
2000 [(match_operand:SI 0 "register_operand" "")
2001 (match_operand:V4SI 1 "register_operand" "")
2002 (match_operand 2 "const_int_operand" "")]
2003 "TARGET_ALTIVEC"
2004 {
2005 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2006 DONE;
2007 })
2009 (define_expand "vec_extractv8hi"
2010 [(match_operand:HI 0 "register_operand" "")
2011 (match_operand:V8HI 1 "register_operand" "")
2012 (match_operand 2 "const_int_operand" "")]
2013 "TARGET_ALTIVEC"
2014 {
2015 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2016 DONE;
2017 })
2019 (define_expand "vec_extractv16qi"
2020 [(match_operand:QI 0 "register_operand" "")
2021 (match_operand:V16QI 1 "register_operand" "")
2022 (match_operand 2 "const_int_operand" "")]
2023 "TARGET_ALTIVEC"
2024 {
2025 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2026 DONE;
2027 })
2029 (define_expand "vec_extractv4sf"
2030 [(match_operand:SF 0 "register_operand" "")
2031 (match_operand:V4SF 1 "register_operand" "")
2032 (match_operand 2 "const_int_operand" "")]
2033 "TARGET_ALTIVEC"
2034 {
2035 rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
2036 DONE;
2037 })
2039 ;; Generate
2040 ;; vspltis? SCRATCH0,0
2041 ;; vsubu?m SCRATCH2,SCRATCH1,%1
2042 ;; vmaxs? %0,%1,SCRATCH2"
2043 (define_expand "abs<mode>2"
2044 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2045 (set (match_dup 3)
2046 (minus:VI (match_dup 2)
2047 (match_operand:VI 1 "register_operand" "v")))
2048 (set (match_operand:VI 0 "register_operand" "=v")
2049 (smax:VI (match_dup 1) (match_dup 3)))]
2050 "TARGET_ALTIVEC"
2051 {
2052 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2053 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2054 })
2056 ;; Generate
2057 ;; vspltisw SCRATCH1,-1
2058 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
2059 ;; vandc %0,%1,SCRATCH2
2060 (define_expand "absv4sf2"
2061 [(set (match_dup 2)
2062 (vec_duplicate:V4SF (float:SF (const_int -1))))
2063 (set (match_dup 3)
2064 (unspec:V4SF [(match_dup 2) (match_dup 2)] UNSPEC_VSLW))
2065 (set (match_operand:V4SF 0 "register_operand" "=v")
2066 (and:V4SF (not:V4SF (match_dup 3))
2067 (match_operand:V4SF 1 "register_operand" "v")))]
2068 "TARGET_ALTIVEC"
2069 {
2070 operands[2] = gen_reg_rtx (V4SFmode);
2071 operands[3] = gen_reg_rtx (V4SFmode);
2072 })
2074 ;; Generate
2075 ;; vspltis? SCRATCH0,0
2076 ;; vsubs?s SCRATCH2,SCRATCH1,%1
2077 ;; vmaxs? %0,%1,SCRATCH2"
2078 (define_expand "altivec_abss_<mode>"
2079 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2080 (parallel [(set (match_dup 3)
2081 (unspec:VI [(match_dup 2)
2082 (match_operand:VI 1 "register_operand" "v")]
2083 UNSPEC_VSUBS))
2084 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
2085 (set (match_operand:VI 0 "register_operand" "=v")
2086 (smax:VI (match_dup 1) (match_dup 3)))]
2087 "TARGET_ALTIVEC"
2088 {
2089 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2090 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2091 })
2093 ;; Vector shift left in bits. Currently supported only for shift
2094 ;; amounts that can be expressed as byte shifts (divisible by 8).
2095 ;; General shift amounts can be supported using vslo + vsl. We're
2096 ;; not expecting to see these yet (the vectorizer currently
2097 ;; generates only shifts divisible by byte_size).
2098 (define_expand "vec_shl_<mode>"
2099 [(set (match_operand:V 0 "register_operand" "=v")
2100 (unspec:V [(match_operand:V 1 "register_operand" "v")
2101 (match_operand:QI 2 "reg_or_short_operand" "")]
2102 UNSPEC_VECSH))]
2103 "TARGET_ALTIVEC"
2104 "
2105 {
2106 rtx bitshift = operands[2];
2107 rtx byteshift = gen_reg_rtx (QImode);
2108 HOST_WIDE_INT bitshift_val;
2109 HOST_WIDE_INT byteshift_val;
2111 if (! CONSTANT_P (bitshift))
2112 FAIL;
2113 bitshift_val = INTVAL (bitshift);
2114 if (bitshift_val & 0x7)
2115 FAIL;
2116 byteshift_val = bitshift_val >> 3;
2117 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2118 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2119 byteshift));
2120 DONE;
2121 }")
2123 ;; Vector shift right in bits. Currently supported only for shift
2124 ;; amounts that can be expressed as byte shifts (divisible by 8).
2125 ;; General shift amounts can be supported using vsro + vsr. We're
2126 ;; not expecting to see these yet (the vectorizer currently
2127 ;; generates only shifts divisible by byte_size).
2128 (define_expand "vec_shr_<mode>"
2129 [(set (match_operand:V 0 "register_operand" "=v")
2130 (unspec:V [(match_operand:V 1 "register_operand" "v")
2131 (match_operand:QI 2 "reg_or_short_operand" "")]
2132 UNSPEC_VECSH))]
2133 "TARGET_ALTIVEC"
2134 "
2135 {
2136 rtx bitshift = operands[2];
2137 rtx byteshift = gen_reg_rtx (QImode);
2138 HOST_WIDE_INT bitshift_val;
2139 HOST_WIDE_INT byteshift_val;
2141 if (! CONSTANT_P (bitshift))
2142 FAIL;
2143 bitshift_val = INTVAL (bitshift);
2144 if (bitshift_val & 0x7)
2145 FAIL;
2146 byteshift_val = 16 - (bitshift_val >> 3);
2147 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2148 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2149 byteshift));
2150 DONE;
2151 }")
2153 (define_insn "altivec_vsumsws_nomode"
2154 [(set (match_operand 0 "register_operand" "=v")
2155 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2156 (match_operand:V4SI 2 "register_operand" "v")]
2157 UNSPEC_VSUMSWS))
2158 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2159 "TARGET_ALTIVEC"
2160 "vsumsws %0,%1,%2"
2161 [(set_attr "type" "veccomplex")])
2163 (define_expand "reduc_splus_<mode>"
2164 [(set (match_operand:VIshort 0 "register_operand" "=v")
2165 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2166 UNSPEC_REDUC_PLUS))]
2167 "TARGET_ALTIVEC"
2168 "
2169 {
2170 rtx vzero = gen_reg_rtx (V4SImode);
2171 rtx vtmp1 = gen_reg_rtx (V4SImode);
2173 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2174 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2175 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2176 DONE;
2177 }")
2179 (define_expand "reduc_uplus_v16qi"
2180 [(set (match_operand:V16QI 0 "register_operand" "=v")
2181 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2182 UNSPEC_REDUC_PLUS))]
2183 "TARGET_ALTIVEC"
2184 "
2185 {
2186 rtx vzero = gen_reg_rtx (V4SImode);
2187 rtx vtmp1 = gen_reg_rtx (V4SImode);
2189 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2190 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2191 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2192 DONE;
2193 }")
2195 (define_insn "vec_realign_load_<mode>"
2196 [(set (match_operand:V 0 "register_operand" "=v")
2197 (unspec:V [(match_operand:V 1 "register_operand" "v")
2198 (match_operand:V 2 "register_operand" "v")
2199 (match_operand:V16QI 3 "register_operand" "v")]
2200 UNSPEC_REALIGN_LOAD))]
2201 "TARGET_ALTIVEC"
2202 "vperm %0,%1,%2,%3"
2203 [(set_attr "type" "vecperm")])
2205 (define_expand "usat_subv16qi3"
2206 [(set (match_operand:V16QI 0 "register_operand" "=v")
2207 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
2208 (match_operand:V16QI 2 "register_operand" "v")] 125))
2209 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
2210 "TARGET_ALTIVEC"
2211 "
2212 {
2213 emit_insn (gen_altivec_vsububs (operands[0], operands[1], operands[2]));
2214 DONE;
2215 }")
2217 (define_expand "usat_subv8hi3"
2218 [(set (match_operand:V8HI 0 "register_operand" "=v")
2219 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
2220 (match_operand:V8HI 2 "register_operand" "v")] 127))
2221 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
2222 "TARGET_ALTIVEC"
2223 "
2224 {
2225 emit_insn (gen_altivec_vsubuhs (operands[0], operands[1], operands[2]));
2226 DONE;
2227 }")
2229 (define_expand "usat_subv4si3"
2230 [(set (match_operand:V4SI 0 "register_operand" "=v")
2231 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2232 (match_operand:V4SI 2 "register_operand" "v")] 129))
2233 (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
2234 "TARGET_ALTIVEC"
2235 "
2236 {
2237 emit_insn (gen_altivec_vsubuws (operands[0], operands[1], operands[2]));
2238 DONE;
2239 }")
2241 (define_expand "udot_prod<mode>"
2242 [(set (match_operand:V4SI 0 "register_operand" "=v")
2243 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2244 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
2245 (match_operand:VIshort 2 "register_operand" "v")]
2246 UNSPEC_VMSUMU)))]
2247 "TARGET_ALTIVEC"
2248 "
2249 {
2250 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
2251 DONE;
2252 }")
2254 (define_expand "sdot_prodv8hi"
2255 [(set (match_operand:V4SI 0 "register_operand" "=v")
2256 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2257 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2258 (match_operand:V8HI 2 "register_operand" "v")]
2259 UNSPEC_VMSUMSHM)))]
2260 "TARGET_ALTIVEC"
2261 "
2262 {
2263 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
2264 DONE;
2265 }")
2267 (define_expand "neg<mode>2"
2268 [(use (match_operand:VI 0 "register_operand" ""))
2269 (use (match_operand:VI 1 "register_operand" ""))]
2270 "TARGET_ALTIVEC"
2271 "
2272 {
2273 rtx vzero;
2275 vzero = gen_reg_rtx (GET_MODE (operands[0]));
2276 emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
2277 emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
2279 DONE;
2280 }")
2282 (define_expand "negv4sf2"
2283 [(use (match_operand:V4SF 0 "register_operand" ""))
2284 (use (match_operand:V4SF 1 "register_operand" ""))]
2285 "TARGET_ALTIVEC"
2286 "
2287 {
2288 rtx neg0;
2290 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
2291 neg0 = gen_reg_rtx (V4SFmode);
2292 emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
2293 emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
2295 /* XOR */
2296 emit_insn (gen_xorv4sf3 (operands[0], neg0, operands[1]));
2298 DONE;
2299 }")
2301 (define_expand "widen_usum<mode>3"
2302 [(set (match_operand:V4SI 0 "register_operand" "=v")
2303 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2304 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
2305 UNSPEC_VMSUMU)))]
2306 "TARGET_ALTIVEC"
2307 "
2308 {
2309 rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
2311 emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
2312 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
2313 DONE;
2314 }")
2316 (define_expand "widen_ssumv16qi3"
2317 [(set (match_operand:V4SI 0 "register_operand" "=v")
2318 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2319 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
2320 UNSPEC_VMSUMM)))]
2321 "TARGET_ALTIVEC"
2322 "
2323 {
2324 rtx vones = gen_reg_rtx (V16QImode);
2326 emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
2327 emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
2328 DONE;
2329 }")
2331 (define_expand "widen_ssumv8hi3"
2332 [(set (match_operand:V4SI 0 "register_operand" "=v")
2333 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2334 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2335 UNSPEC_VMSUMSHM)))]
2336 "TARGET_ALTIVEC"
2337 "
2338 {
2339 rtx vones = gen_reg_rtx (V8HImode);
2341 emit_insn (gen_altivec_vspltish (vones, const1_rtx));
2342 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
2343 DONE;
2344 }")
2346 (define_expand "vec_unpacks_hi_v16qi"
2347 [(set (match_operand:V8HI 0 "register_operand" "=v")
2348 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2349 UNSPEC_VUPKHSB))]
2350 "TARGET_ALTIVEC"
2351 "
2352 {
2353 emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
2354 DONE;
2355 }")
2357 (define_expand "vec_unpacks_hi_v8hi"
2358 [(set (match_operand:V4SI 0 "register_operand" "=v")
2359 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2360 UNSPEC_VUPKHSH))]
2361 "TARGET_ALTIVEC"
2362 "
2363 {
2364 emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
2365 DONE;
2366 }")
2368 (define_expand "vec_unpacks_lo_v16qi"
2369 [(set (match_operand:V8HI 0 "register_operand" "=v")
2370 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2371 UNSPEC_VUPKLSB))]
2372 "TARGET_ALTIVEC"
2373 "
2374 {
2375 emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2376 DONE;
2377 }")
2379 (define_expand "vec_unpacks_lo_v8hi"
2380 [(set (match_operand:V4SI 0 "register_operand" "=v")
2381 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2382 UNSPEC_VUPKLSH))]
2383 "TARGET_ALTIVEC"
2384 "
2385 {
2386 emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2387 DONE;
2388 }")
2390 (define_insn "vperm_v8hiv4si"
2391 [(set (match_operand:V4SI 0 "register_operand" "=v")
2392 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2393 (match_operand:V4SI 2 "register_operand" "v")
2394 (match_operand:V16QI 3 "register_operand" "v")]
2395 UNSPEC_VPERMSI))]
2396 "TARGET_ALTIVEC"
2397 "vperm %0,%1,%2,%3"
2398 [(set_attr "type" "vecperm")])
2400 (define_insn "vperm_v16qiv8hi"
2401 [(set (match_operand:V8HI 0 "register_operand" "=v")
2402 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2403 (match_operand:V8HI 2 "register_operand" "v")
2404 (match_operand:V16QI 3 "register_operand" "v")]
2405 UNSPEC_VPERMHI))]
2406 "TARGET_ALTIVEC"
2407 "vperm %0,%1,%2,%3"
2408 [(set_attr "type" "vecperm")])
2410 (define_expand "vec_unpacku_hi_v16qi"
2411 [(set (match_operand:V8HI 0 "register_operand" "=v")
2412 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2413 UNSPEC_VUPKHUB))]
2414 "TARGET_ALTIVEC"
2415 "
2416 {
2417 rtx vzero = gen_reg_rtx (V8HImode);
2418 rtx mask = gen_reg_rtx (V16QImode);
2419 rtvec v = rtvec_alloc (16);
2421 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2423 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2424 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2425 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2426 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2427 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2428 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2429 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2430 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2431 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2432 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2433 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2434 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2435 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2436 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2437 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2438 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2440 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2441 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2442 DONE;
2443 }")
2445 (define_expand "vec_unpacku_hi_v8hi"
2446 [(set (match_operand:V4SI 0 "register_operand" "=v")
2447 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2448 UNSPEC_VUPKHUH))]
2449 "TARGET_ALTIVEC"
2450 "
2451 {
2452 rtx vzero = gen_reg_rtx (V4SImode);
2453 rtx mask = gen_reg_rtx (V16QImode);
2454 rtvec v = rtvec_alloc (16);
2456 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2458 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2459 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2460 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2461 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2462 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2463 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2464 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2465 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2466 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2467 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2468 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2469 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2470 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2471 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2472 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2473 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2475 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2476 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2477 DONE;
2478 }")
2480 (define_expand "vec_unpacku_lo_v16qi"
2481 [(set (match_operand:V8HI 0 "register_operand" "=v")
2482 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2483 UNSPEC_VUPKLUB))]
2484 "TARGET_ALTIVEC"
2485 "
2486 {
2487 rtx vzero = gen_reg_rtx (V8HImode);
2488 rtx mask = gen_reg_rtx (V16QImode);
2489 rtvec v = rtvec_alloc (16);
2491 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2493 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2494 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2495 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2496 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2497 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2498 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2499 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2500 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2501 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2502 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2503 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2504 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2505 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2506 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2507 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2508 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2510 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2511 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2512 DONE;
2513 }")
2515 (define_expand "vec_unpacku_lo_v8hi"
2516 [(set (match_operand:V4SI 0 "register_operand" "=v")
2517 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2518 UNSPEC_VUPKLUH))]
2519 "TARGET_ALTIVEC"
2520 "
2521 {
2522 rtx vzero = gen_reg_rtx (V4SImode);
2523 rtx mask = gen_reg_rtx (V16QImode);
2524 rtvec v = rtvec_alloc (16);
2526 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2528 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2529 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2530 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2531 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2532 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2533 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2534 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2535 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2536 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2537 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2538 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2539 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2540 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2541 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2542 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2543 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2545 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2546 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2547 DONE;
2548 }")
2550 (define_expand "vec_widen_umult_hi_v16qi"
2551 [(set (match_operand:V8HI 0 "register_operand" "=v")
2552 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2553 (match_operand:V16QI 2 "register_operand" "v")]
2554 UNSPEC_VMULWHUB))]
2555 "TARGET_ALTIVEC"
2556 "
2557 {
2558 rtx ve = gen_reg_rtx (V8HImode);
2559 rtx vo = gen_reg_rtx (V8HImode);
2561 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2562 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2563 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2564 DONE;
2565 }")
2567 (define_expand "vec_widen_umult_lo_v16qi"
2568 [(set (match_operand:V8HI 0 "register_operand" "=v")
2569 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2570 (match_operand:V16QI 2 "register_operand" "v")]
2571 UNSPEC_VMULWLUB))]
2572 "TARGET_ALTIVEC"
2573 "
2574 {
2575 rtx ve = gen_reg_rtx (V8HImode);
2576 rtx vo = gen_reg_rtx (V8HImode);
2578 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2579 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2580 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2581 DONE;
2582 }")
2584 (define_expand "vec_widen_smult_hi_v16qi"
2585 [(set (match_operand:V8HI 0 "register_operand" "=v")
2586 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2587 (match_operand:V16QI 2 "register_operand" "v")]
2588 UNSPEC_VMULWHSB))]
2589 "TARGET_ALTIVEC"
2590 "
2591 {
2592 rtx ve = gen_reg_rtx (V8HImode);
2593 rtx vo = gen_reg_rtx (V8HImode);
2595 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2596 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2597 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2598 DONE;
2599 }")
2601 (define_expand "vec_widen_smult_lo_v16qi"
2602 [(set (match_operand:V8HI 0 "register_operand" "=v")
2603 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2604 (match_operand:V16QI 2 "register_operand" "v")]
2605 UNSPEC_VMULWLSB))]
2606 "TARGET_ALTIVEC"
2607 "
2608 {
2609 rtx ve = gen_reg_rtx (V8HImode);
2610 rtx vo = gen_reg_rtx (V8HImode);
2612 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2613 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2614 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2615 DONE;
2616 }")
2618 (define_expand "vec_widen_umult_hi_v8hi"
2619 [(set (match_operand:V4SI 0 "register_operand" "=v")
2620 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2621 (match_operand:V8HI 2 "register_operand" "v")]
2622 UNSPEC_VMULWHUH))]
2623 "TARGET_ALTIVEC"
2624 "
2625 {
2626 rtx ve = gen_reg_rtx (V4SImode);
2627 rtx vo = gen_reg_rtx (V4SImode);
2629 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2630 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2631 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2632 DONE;
2633 }")
2635 (define_expand "vec_widen_umult_lo_v8hi"
2636 [(set (match_operand:V4SI 0 "register_operand" "=v")
2637 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2638 (match_operand:V8HI 2 "register_operand" "v")]
2639 UNSPEC_VMULWLUH))]
2640 "TARGET_ALTIVEC"
2641 "
2642 {
2643 rtx ve = gen_reg_rtx (V4SImode);
2644 rtx vo = gen_reg_rtx (V4SImode);
2646 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2647 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2648 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2649 DONE;
2650 }")
2652 (define_expand "vec_widen_smult_hi_v8hi"
2653 [(set (match_operand:V4SI 0 "register_operand" "=v")
2654 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2655 (match_operand:V8HI 2 "register_operand" "v")]
2656 UNSPEC_VMULWHSH))]
2657 "TARGET_ALTIVEC"
2658 "
2659 {
2660 rtx ve = gen_reg_rtx (V4SImode);
2661 rtx vo = gen_reg_rtx (V4SImode);
2663 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2664 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2665 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2666 DONE;
2667 }")
2669 (define_expand "vec_widen_smult_lo_v8hi"
2670 [(set (match_operand:V4SI 0 "register_operand" "=v")
2671 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2672 (match_operand:V8HI 2 "register_operand" "v")]
2673 UNSPEC_VMULWLSH))]
2674 "TARGET_ALTIVEC"
2675 "
2676 {
2677 rtx ve = gen_reg_rtx (V4SImode);
2678 rtx vo = gen_reg_rtx (V4SImode);
2680 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2681 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2682 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2683 DONE;
2684 }")
2686 (define_expand "vec_pack_mod_v8hi"
2687 [(set (match_operand:V16QI 0 "register_operand" "=v")
2688 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2689 (match_operand:V8HI 2 "register_operand" "v")]
2690 UNSPEC_VPKUHUM))]
2691 "TARGET_ALTIVEC"
2692 "
2693 {
2694 emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2695 DONE;
2696 }")
2698 (define_expand "vec_pack_mod_v4si"
2699 [(set (match_operand:V8HI 0 "register_operand" "=v")
2700 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2701 (match_operand:V4SI 2 "register_operand" "v")]
2702 UNSPEC_VPKUWUM))]
2703 "TARGET_ALTIVEC"
2704 "
2705 {
2706 emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2707 DONE;
2708 }")
2710 ;; Can't map smulv8hi3_highpart to altivec_vmhaddshs because it
2711 ;; computes sat16((op0*op1)>>15 + 0)
2712 ;; rather than truncate((op0*op1)>>16)
2713 ;(define_expand "smulv8hi3_highpart"
2714 ; [(set (match_operand:V8HI 0 "register_operand" "=v")
2715 ; (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
2716 ; (match_operand:V8HI 2 "register_operand" "v")]
2717 ; UNSPEC_VMHADDSHS))
2718 ; (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2719 ; "TARGET_ALTIVEC"
2720 ; "
2721 ;{
2722 ; rtx vzero = gen_reg_rtx (V8HImode);
2723 ;
2724 ; emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2725 ; emit_insn (gen_altivec_vmhaddshs (operands[0], operands[1], operands[2], vzero));
2726 ; DONE;
2727 ;}")
2730 (define_insn "vpkuhum_nomode"
2731 [(set (match_operand:V16QI 0 "register_operand" "=v")
2732 (unspec:V16QI [(match_operand 1 "register_operand" "v")
2733 (match_operand 2 "register_operand" "v")]
2734 UNSPEC_VPKUHUM))]
2735 "TARGET_ALTIVEC"
2736 "vpkuhum %0,%1,%2"
2737 [(set_attr "type" "vecperm")])
2739 (define_insn "vpkuwum_nomode"
2740 [(set (match_operand:V8HI 0 "register_operand" "=v")
2741 (unspec:V8HI [(match_operand 1 "register_operand" "v")
2742 (match_operand 2 "register_operand" "v")]
2743 UNSPEC_VPKUWUM))]
2744 "TARGET_ALTIVEC"
2745 "vpkuwum %0,%1,%2"
2746 [(set_attr "type" "vecperm")])
2748 (define_expand "vec_interleave_highv4sf"
2749 [(set (match_operand:V4SF 0 "register_operand" "")
2750 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
2751 (match_operand:V4SF 2 "register_operand" "")]
2752 UNSPEC_INTERHI_V4SF))]
2753 "TARGET_ALTIVEC"
2754 "
2755 {
2756 emit_insn (gen_altivec_vmrghsf (operands[0], operands[1], operands[2]));
2757 DONE;
2758 }")
2760 (define_expand "vec_interleave_lowv4sf"
2761 [(set (match_operand:V4SF 0 "register_operand" "")
2762 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
2763 (match_operand:V4SF 2 "register_operand" "")]
2764 UNSPEC_INTERLO_V4SF))]
2765 "TARGET_ALTIVEC"
2766 "
2767 {
2768 emit_insn (gen_altivec_vmrglsf (operands[0], operands[1], operands[2]));
2769 DONE;
2770 }")
2772 (define_expand "vec_interleave_high<mode>"
2773 [(set (match_operand:VI 0 "register_operand" "")
2774 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2775 (match_operand:VI 2 "register_operand" "")]
2776 UNSPEC_INTERHI))]
2777 "TARGET_ALTIVEC"
2778 "
2779 {
2780 emit_insn (gen_altivec_vmrgh<VI_char> (operands[0], operands[1], operands[2]));
2781 DONE;
2782 }")
2784 (define_expand "vec_interleave_low<mode>"
2785 [(set (match_operand:VI 0 "register_operand" "")
2786 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2787 (match_operand:VI 2 "register_operand" "")]
2788 UNSPEC_INTERLO))]
2789 "TARGET_ALTIVEC"
2790 "
2791 {
2792 emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
2793 DONE;
2794 }")
2796 (define_expand "ashl<mode>3"
2797 [(set (match_operand:VI 0 "register_operand" "")
2798 (unspec:V8HI [(match_operand:VI 1 "register_operand" "")
2799 (match_operand:VI 2 "register_operand" "")]
2800 UNSPEC_ASHL))]
2801 "TARGET_ALTIVEC"
2802 "
2803 {
2804 emit_insn (gen_altivec_vsl<VI_char> (operands[0], operands[1], operands[2]));
2806 DONE;
2807 }")
2809 (define_expand "vec_extract_evenv4si"
2810 [(set (match_operand:V4SI 0 "register_operand" "")
2811 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2812 (match_operand:V4SI 2 "register_operand" "")]
2813 UNSPEC_EXTEVEN_V4SI))]
2814 "TARGET_ALTIVEC"
2815 "
2816 {
2817 rtx mask = gen_reg_rtx (V16QImode);
2818 rtvec v = rtvec_alloc (16);
2820 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2821 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2822 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2823 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2824 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2825 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2826 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2827 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2828 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2829 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2830 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2831 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2832 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2833 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2834 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2835 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2836 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2837 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2839 DONE;
2840 }")
2842 (define_expand "vec_extract_evenv4sf"
2843 [(set (match_operand:V4SF 0 "register_operand" "")
2844 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2845 (match_operand:V4SF 2 "register_operand" "")]
2846 UNSPEC_EXTEVEN_V4SF))]
2847 "TARGET_ALTIVEC"
2848 "
2849 {
2850 rtx mask = gen_reg_rtx (V16QImode);
2851 rtvec v = rtvec_alloc (16);
2853 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2854 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2855 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2856 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2857 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2858 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2859 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2860 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2861 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2862 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2863 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2864 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2865 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2866 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2867 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2868 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2869 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2870 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2872 DONE;
2873 }")
2875 (define_expand "vec_extract_evenv8hi"
2876 [(set (match_operand:V4SI 0 "register_operand" "")
2877 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2878 (match_operand:V8HI 2 "register_operand" "")]
2879 UNSPEC_EXTEVEN_V8HI))]
2880 "TARGET_ALTIVEC"
2881 "
2882 {
2883 rtx mask = gen_reg_rtx (V16QImode);
2884 rtvec v = rtvec_alloc (16);
2886 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2887 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2888 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2889 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
2890 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2891 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2892 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2893 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
2894 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2895 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2896 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2897 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
2898 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2899 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2900 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2901 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
2902 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2903 emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
2905 DONE;
2906 }")
2908 (define_expand "vec_extract_evenv16qi"
2909 [(set (match_operand:V4SI 0 "register_operand" "")
2910 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
2911 (match_operand:V16QI 2 "register_operand" "")]
2912 UNSPEC_EXTEVEN_V16QI))]
2913 "TARGET_ALTIVEC"
2914 "
2915 {
2916 rtx mask = gen_reg_rtx (V16QImode);
2917 rtvec v = rtvec_alloc (16);
2919 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2920 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
2921 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2922 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
2923 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2924 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2925 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2926 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
2927 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2928 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
2929 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2930 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
2931 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2932 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
2933 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2934 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
2935 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2936 emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
2938 DONE;
2939 }")
2941 (define_expand "vec_extract_oddv4si"
2942 [(set (match_operand:V4SI 0 "register_operand" "")
2943 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2944 (match_operand:V4SI 2 "register_operand" "")]
2945 UNSPEC_EXTODD_V4SI))]
2946 "TARGET_ALTIVEC"
2947 "
2948 {
2949 rtx mask = gen_reg_rtx (V16QImode);
2950 rtvec v = rtvec_alloc (16);
2952 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2953 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2954 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2955 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2956 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2957 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2958 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2959 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2960 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2961 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2962 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2963 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2964 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2965 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2966 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2967 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2968 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2969 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2971 DONE;
2972 }")
2974 (define_expand "vec_extract_oddv4sf"
2975 [(set (match_operand:V4SF 0 "register_operand" "")
2976 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2977 (match_operand:V4SF 2 "register_operand" "")]
2978 UNSPEC_EXTODD_V4SF))]
2979 "TARGET_ALTIVEC"
2980 "
2981 {
2982 rtx mask = gen_reg_rtx (V16QImode);
2983 rtvec v = rtvec_alloc (16);
2985 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2986 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2987 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2988 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2989 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2990 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2991 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2992 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2993 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2994 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2995 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2996 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2997 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2998 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2999 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
3000 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
3001 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
3002 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
3004 DONE;
3005 }")
3007 (define_expand "vec_extract_oddv8hi"
3008 [(set (match_operand:V8HI 0 "register_operand" "")
3009 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
3010 (match_operand:V8HI 2 "register_operand" "")]
3011 UNSPEC_EXTODD_V8HI))]
3012 "TARGET_ALTIVEC"
3013 "
3014 {
3015 emit_insn (gen_vpkuwum_nomode (operands[0], operands[1], operands[2]));
3016 DONE;
3017 }")
3019 (define_expand "vec_extract_oddv16qi"
3020 [(set (match_operand:V16QI 0 "register_operand" "")
3021 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
3022 (match_operand:V16QI 2 "register_operand" "")]
3023 UNSPEC_EXTODD_V16QI))]
3024 "TARGET_ALTIVEC"
3025 "
3026 {
3027 emit_insn (gen_vpkuhum_nomode (operands[0], operands[1], operands[2]));
3028 DONE;
3029 }")