1 ;; FR30 machine description.
2 ;; Copyright (C) 1998, 1999, 2000, 2002, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Cygnus Solutions.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27 (define_attr "length" "" (const_int 2))
29 ;; Used to distinguish between small memory model targets and big mode targets.
31 (define_attr "size" "small,big"
32 (const (if_then_else (symbol_ref "TARGET_SMALL_MODEL")
33 (const_string "small")
34 (const_string "big"))))
37 ;; Define an attribute to be used by the delay slot code.
38 ;; An instruction by default is considered to be 'delyabable'
39 ;; that is, it can be placed into a delay slot, but it is not
40 ;; itself a delayed branch type instruction. An instruction
41 ;; whose type is 'delayed' is one which has a delay slot, and
42 ;; an instruction whose delay_type is 'other' is one which does
43 ;; not have a delay slot, nor can it be placed into a delay slot.
45 (define_attr "delay_type" "delayable,delayed,other" (const_string "delayable"))
48 ;;{{{ Delay Slot Specifications
50 (define_delay (eq_attr "delay_type" "delayed")
51 [(and (eq_attr "delay_type" "delayable")
52 (eq_attr "length" "2"))
57 (include "predicates.md")
64 ;; Wrap moves in define_expand to prevent memory->memory moves from being
65 ;; generated at the RTL level, which generates better code for most machines
66 ;; which can't do mem->mem moves.
68 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
69 ;; than M, the effect of this instruction is to store the specified value in
70 ;; the part of the register that corresponds to mode M. The effect on the rest
71 ;; of the register is undefined.
73 ;; This class of patterns is special in several ways. First of all, each of
74 ;; these names *must* be defined, because there is no other way to copy a datum
75 ;; from one place to another.
77 ;; Second, these patterns are not used solely in the RTL generation pass. Even
78 ;; the reload pass can generate move insns to copy values from stack slots into
79 ;; temporary registers. When it does so, one of the operands is a hard
80 ;; register and the other is an operand that can need to be reloaded into a
83 ;; Therefore, when given such a pair of operands, the pattern must
84 ;; generate RTL which needs no reloading and needs no temporary
85 ;; registers--no registers other than the operands. For example, if
86 ;; you support the pattern with a `define_expand', then in such a
87 ;; case the `define_expand' mustn't call `force_reg' or any other such
88 ;; function which might generate new pseudo registers.
90 ;; This requirement exists even for subword modes on a RISC machine
91 ;; where fetching those modes from memory normally requires several
92 ;; insns and some temporary registers. Look in `spur.md' to see how
93 ;; the requirement can be satisfied.
95 ;; During reload a memory reference with an invalid address may be passed as an
96 ;; operand. Such an address will be replaced with a valid address later in the
97 ;; reload pass. In this case, nothing may be done with the address except to
98 ;; use it as it stands. If it is copied, it will not be replaced with a valid
99 ;; address. No attempt should be made to make such an address into a valid
100 ;; address and no routine (such as `change_address') that will do so may be
101 ;; called. Note that `general_operand' will fail when applied to such an
104 ;; The global variable `reload_in_progress' (which must be explicitly declared
105 ;; if required) can be used to determine whether such special handling is
108 ;; The variety of operands that have reloads depends on the rest of
109 ;; the machine description, but typically on a RISC machine these can
110 ;; only be pseudo registers that did not get hard registers, while on
111 ;; other machines explicit memory references will get optional
114 ;; If a scratch register is required to move an object to or from memory, it
115 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
116 ;; impossible during and after reload. If there are cases needing scratch
117 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
118 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
119 ;; patterns `reload_inM' or `reload_outM' to handle them.
121 ;; The constraints on a `moveM' must permit moving any hard register to any
122 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
123 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
126 ;; It is obligatory to support floating point `moveM' instructions
127 ;; into and out of any registers that can hold fixed point values,
128 ;; because unions and structures (which have modes `SImode' or
129 ;; `DImode') can be in those registers and they may have floating
132 ;; There may also be a need to support fixed point `moveM' instructions in and
133 ;; out of floating point registers. Unfortunately, I have forgotten why this
134 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
135 ;; rejects fixed point values in floating point registers, then the constraints
136 ;; of the fixed point `moveM' instructions must be designed to avoid ever
137 ;; trying to reload into a floating point register.
142 ;; Push a register onto the stack
143 (define_insn "movsi_push"
144 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
145 (match_operand:SI 0 "register_operand" "a"))]
150 ;; Pop a register off the stack
151 (define_insn "movsi_pop"
152 [(set:SI (match_operand:SI 0 "register_operand" "=a")
153 (mem:SI (post_inc:SI (reg:SI 15))))]
161 (define_expand "movqi"
162 [(set (match_operand:QI 0 "general_operand" "")
163 (match_operand:QI 1 "general_operand" ""))]
167 if (!reload_in_progress
169 && GET_CODE (operands[0]) == MEM
170 && (GET_CODE (operands[1]) == MEM
171 || immediate_operand (operands[1], QImode)))
172 operands[1] = copy_to_mode_reg (QImode, operands[1]);
175 (define_insn "movqi_unsigned_register_load"
176 [(set (match_operand:SI 0 "register_operand" "=r")
177 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
182 (define_expand "movqi_signed_register_load"
183 [(set (match_operand:SI 0 "register_operand" "")
184 (sign_extend:SI (match_operand:QI 1 "memory_operand" "")))]
187 emit_insn (gen_movqi_unsigned_register_load (operands[0], operands[1]));
188 emit_insn (gen_extendqisi2 (operands[0], operands[0]));
193 (define_insn "*movqi_internal"
194 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,red,m,r")
195 (match_operand:QI 1 "general_operand" "i,red,r,rm"))]
207 (define_expand "movhi"
208 [(set (match_operand:HI 0 "general_operand" "")
209 (match_operand:HI 1 "general_operand" ""))]
213 if (!reload_in_progress
215 && GET_CODE (operands[0]) == MEM
216 && (GET_CODE (operands[1]) == MEM
217 || immediate_operand (operands[1], HImode)))
218 operands[1] = copy_to_mode_reg (HImode, operands[1]);
221 (define_insn "movhi_unsigned_register_load"
222 [(set (match_operand:SI 0 "register_operand" "=r")
223 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
228 (define_expand "movhi_signed_register_load"
229 [(set (match_operand:SI 0 "register_operand" "")
230 (sign_extend:SI (match_operand:HI 1 "memory_operand" "")))]
233 emit_insn (gen_movhi_unsigned_register_load (operands[0], operands[1]));
234 emit_insn (gen_extendhisi2 (operands[0], operands[0]));
239 (define_insn "*movhi_internal"
240 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,red,m,r")
241 (match_operand:HI 1 "general_operand" "L,M,n,red,r,rm"))]
250 [(set_attr "length" "*,4,6,*,*,*")]
256 ;; If the destination is a MEM and the source is a
257 ;; MEM or an CONST_INT move the source into a register.
258 (define_expand "movsi"
259 [(set (match_operand:SI 0 "nonimmediate_operand" "")
260 (match_operand:SI 1 "general_operand" ""))]
263 if (!reload_in_progress
265 && GET_CODE(operands[0]) == MEM
266 && (GET_CODE (operands[1]) == MEM
267 || immediate_operand (operands[1], SImode)))
268 operands[1] = copy_to_mode_reg (SImode, operands[1]);
272 ;; We can do some clever tricks when loading certain immediate
273 ;; values. We implement these tricks as define_splits, rather
274 ;; than putting the code into the define_expand "movsi" above,
275 ;; because if we put them there, they will be evaluated at RTL
276 ;; generation time and then the combiner pass will come along
277 ;; and replace the multiple insns that have been generated with
278 ;; the original, slower, load insns. (The combiner pass only
279 ;; cares about reducing the number of instructions, it does not
280 ;; care about instruction lengths or speeds). Splits are
281 ;; evaluated after the combine pass and before the scheduling
282 ;; passes, so that they are the perfect place to put this
285 ;; XXX we probably ought to implement these for QI and HI mode
288 ;; If we are loading a small negative constant we can save space
289 ;; and time by loading the positive value and then sign extending it.
291 [(set (match_operand:SI 0 "register_operand" "")
292 (match_operand:SI 1 "const_int_operand" ""))]
293 "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128"
294 [(set:SI (match_dup 0) (match_dup 1))
295 (set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))]
297 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
298 operands[2] = gen_lowpart (QImode, operands[0]);
302 ;; If we are loading a large negative constant, one which does
303 ;; not have any of its bottom 24 bit set, then we can save time
304 ;; and space by loading the byte value and shifting it into place.
306 [(set (match_operand:SI 0 "register_operand" "")
307 (match_operand:SI 1 "const_int_operand" ""))]
308 "(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)"
309 [(set:SI (match_dup 0) (match_dup 2))
310 (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
311 (clobber (reg:CC 16))])]
313 HOST_WIDE_INT val = INTVAL (operands[1]);
314 operands[2] = GEN_INT (val >> 24);
318 ;; If we are loading a large positive constant, one which has bits
319 ;; in the top byte set, but whose set bits all lie within an 8 bit
320 ;; range, then we can save time and space by loading the byte value
321 ;; and shifting it into place.
323 [(set (match_operand:SI 0 "register_operand" "")
324 (match_operand:SI 1 "const_int_operand" ""))]
325 "(INTVAL (operands[1]) > 0x00ffffff)
326 && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
327 [(set:SI (match_dup 0) (match_dup 2))
328 (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
329 (clobber (reg:CC 16))])]
331 HOST_WIDE_INT val = INTVAL (operands[1]);
332 int shift = exact_log2 (val & ( - val));
333 operands[2] = GEN_INT (val >> shift);
334 operands[3] = GEN_INT (shift);
338 ;; When TARGET_SMALL_MODEL is defined we assume that all symbolic
339 ;; values are addresses which will fit in 20 bits.
341 (define_insn "movsi_internal"
342 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r")
343 (match_operand:SI 1 "general_operand" "L,M,n,i,rde,r,rm"))]
347 switch (which_alternative)
349 case 0: return \"ldi:8 \\t#%1, %0\";
350 case 1: return \"ldi:20\\t#%1, %0\";
351 case 2: return \"ldi:32\\t#%1, %0\";
352 case 3: if (TARGET_SMALL_MODEL)
353 return \"ldi:20\\t%1, %0\";
355 return \"ldi:32\\t%1, %0\";
356 case 4: return \"mov \\t%1, %0\";
357 case 5: return \"st \\t%1, %0\";
358 case 6: return \"ld \\t%1, %0\";
359 default: gcc_unreachable ();
362 [(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4)
363 (eq_attr "alternative" "2") (const_int 6)
364 (eq_attr "alternative" "3")
365 (if_then_else (eq_attr "size" "small")
374 ;; Note - the FR30 does not have an 8 byte load/store instruction
375 ;; but we have to support this pattern because some other patterns
376 ;; (e.g. muldisi2) can produce a DImode result.
377 ;; (This code is stolen from the M32R port.)
379 (define_expand "movdi"
380 [(set (match_operand:DI 0 "general_operand" "")
381 (match_operand:DI 1 "general_operand" ""))]
384 /* Everything except mem = const or mem = mem can be done easily. */
386 if (GET_CODE (operands[0]) == MEM)
387 operands[1] = force_reg (DImode, operands[1]);
390 ;; We use an insn and a split so that we can generate
391 ;; RTL rather than text from fr30_move_double().
393 (define_insn "*movdi_insn"
394 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,m,r")
395 (match_operand:DI 1 "di_operand" "r,m,r,nF"))]
396 "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
398 [(set_attr "length" "4,8,12,12")]
402 [(set (match_operand:DI 0 "nonimmediate_di_operand" "")
403 (match_operand:DI 1 "di_operand" ""))]
406 "operands[2] = fr30_move_double (operands);")
409 ;;{{{ Load & Store Multiple Registers
411 ;; The load multiple and store multiple patterns are implemented
412 ;; as peepholes because the only time they are expected to occur
413 ;; is during function prologues and epilogues.
416 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
417 (match_operand:SI 0 "high_register_operand" "h"))
418 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
419 (match_operand:SI 1 "high_register_operand" "h"))
420 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
421 (match_operand:SI 2 "high_register_operand" "h"))
422 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
423 (match_operand:SI 3 "high_register_operand" "h"))]
424 "fr30_check_multiple_regs (operands, 4, 1)"
425 "stm1 (%0, %1, %2, %3)"
426 [(set_attr "delay_type" "other")]
430 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
431 (match_operand:SI 0 "high_register_operand" "h"))
432 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
433 (match_operand:SI 1 "high_register_operand" "h"))
434 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
435 (match_operand:SI 2 "high_register_operand" "h"))]
436 "fr30_check_multiple_regs (operands, 3, 1)"
438 [(set_attr "delay_type" "other")]
442 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
443 (match_operand:SI 0 "high_register_operand" "h"))
444 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
445 (match_operand:SI 1 "high_register_operand" "h"))]
446 "fr30_check_multiple_regs (operands, 2, 1)"
448 [(set_attr "delay_type" "other")]
452 [(set:SI (match_operand:SI 0 "high_register_operand" "h")
453 (mem:SI (post_inc:SI (reg:SI 15))))
454 (set:SI (match_operand:SI 1 "high_register_operand" "h")
455 (mem:SI (post_inc:SI (reg:SI 15))))
456 (set:SI (match_operand:SI 2 "high_register_operand" "h")
457 (mem:SI (post_inc:SI (reg:SI 15))))
458 (set:SI (match_operand:SI 3 "high_register_operand" "h")
459 (mem:SI (post_inc:SI (reg:SI 15))))]
460 "fr30_check_multiple_regs (operands, 4, 0)"
461 "ldm1 (%0, %1, %2, %3)"
462 [(set_attr "delay_type" "other")]
466 [(set:SI (match_operand:SI 0 "high_register_operand" "h")
467 (mem:SI (post_inc:SI (reg:SI 15))))
468 (set:SI (match_operand:SI 1 "high_register_operand" "h")
469 (mem:SI (post_inc:SI (reg:SI 15))))
470 (set:SI (match_operand:SI 2 "high_register_operand" "h")
471 (mem:SI (post_inc:SI (reg:SI 15))))]
472 "fr30_check_multiple_regs (operands, 3, 0)"
474 [(set_attr "delay_type" "other")]
478 [(set:SI (match_operand:SI 0 "high_register_operand" "h")
479 (mem:SI (post_inc:SI (reg:SI 15))))
480 (set:SI (match_operand:SI 1 "high_register_operand" "h")
481 (mem:SI (post_inc:SI (reg:SI 15))))]
482 "fr30_check_multiple_regs (operands, 2, 0)"
484 [(set_attr "delay_type" "other")]
488 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
489 (match_operand:SI 0 "low_register_operand" "l"))
490 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
491 (match_operand:SI 1 "low_register_operand" "l"))
492 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
493 (match_operand:SI 2 "low_register_operand" "l"))
494 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
495 (match_operand:SI 3 "low_register_operand" "l"))]
496 "fr30_check_multiple_regs (operands, 4, 1)"
497 "stm0 (%0, %1, %2, %3)"
498 [(set_attr "delay_type" "other")]
502 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
503 (match_operand:SI 0 "low_register_operand" "l"))
504 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
505 (match_operand:SI 1 "low_register_operand" "l"))
506 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
507 (match_operand:SI 2 "low_register_operand" "l"))]
508 "fr30_check_multiple_regs (operands, 3, 1)"
510 [(set_attr "delay_type" "other")]
514 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
515 (match_operand:SI 0 "low_register_operand" "l"))
516 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
517 (match_operand:SI 1 "low_register_operand" "l"))]
518 "fr30_check_multiple_regs (operands, 2, 1)"
520 [(set_attr "delay_type" "other")]
524 ;;{{{ Floating Point Moves
526 ;; Note - Patterns for SF mode moves are compulsory, but
527 ;; patterns for DF are optional, as GCC can synthesize them.
529 (define_expand "movsf"
530 [(set (match_operand:SF 0 "general_operand" "")
531 (match_operand:SF 1 "general_operand" ""))]
534 if (!reload_in_progress && !reload_completed
535 && memory_operand (operands[0], SFmode)
536 && memory_operand (operands[1], SFmode))
537 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
541 (define_insn "*movsf_internal"
542 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,red,m,r")
543 (match_operand:SF 1 "general_operand" "Fn,i,rde,r,rm"))]
547 switch (which_alternative)
549 case 0: return \"ldi:32\\t%1, %0\";
550 case 1: if (TARGET_SMALL_MODEL)
551 return \"ldi:20\\t%1, %0\";
553 return \"ldi:32\\t%1, %0\";
554 case 2: return \"mov \\t%1, %0\";
555 case 3: return \"st \\t%1, %0\";
556 case 4: return \"ld \\t%1, %0\";
557 default: gcc_unreachable ();
560 [(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6)
561 (eq_attr "alternative" "1")
562 (if_then_else (eq_attr "size" "small")
568 (define_insn "*movsf_constant_store"
569 [(set (match_operand:SF 0 "memory_operand" "=m")
570 (match_operand:SF 1 "immediate_operand" "F"))]
574 const char * ldi_instr;
575 const char * tmp_reg;
576 static char buffer[100];
578 ldi_instr = fr30_const_double_is_zero (operands[1])
579 ? ldi_instr = \"ldi:8\" : \"ldi:32\";
581 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
583 sprintf (buffer, \"%s\\t#%%1, %s\\t;\\n\\tst\\t%s, %%0\\t; Created by movsf_constant_store\",
584 ldi_instr, tmp_reg, tmp_reg);
588 [(set_attr "length" "8")]
596 ;; Signed conversions from a smaller integer to a larger integer
598 (define_insn "extendqisi2"
599 [(set (match_operand:SI 0 "register_operand" "=r")
600 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
605 (define_insn "extendhisi2"
606 [(set (match_operand:SI 0 "register_operand" "=r")
607 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
612 ;; Unsigned conversions from a smaller integer to a larger integer
614 (define_insn "zero_extendqisi2"
615 [(set (match_operand:SI 0 "register_operand" "=r")
616 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
621 (define_insn "zero_extendhisi2"
622 [(set (match_operand:SI 0 "register_operand" "=r")
623 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
633 ;; This is a special pattern just for adjusting the stack size.
634 (define_insn "add_to_stack"
637 (match_operand:SI 0 "stack_add_operand" "i")))]
642 ;; We need some trickery to be able to handle the addition of
643 ;; large (i.e. outside +/- 16) constants. We need to be able to
644 ;; handle this because reload assumes that it can generate add
645 ;; instructions with arbitrary sized constants.
646 (define_expand "addsi3"
647 [(set (match_operand:SI 0 "register_operand" "")
648 (plus:SI (match_operand:SI 1 "register_operand" "")
649 (match_operand:SI 2 "nonmemory_operand" "")))]
652 if ( GET_CODE (operands[2]) == REG
653 || GET_CODE (operands[2]) == SUBREG)
654 emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
655 else if (GET_CODE (operands[2]) != CONST_INT)
656 emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
657 else if ( (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
658 && (REGNO (operands[1]) != ARG_POINTER_REGNUM)
659 && (INTVAL (operands[2]) >= -16)
660 && (INTVAL (operands[2]) <= 15))
661 emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2]));
663 emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
668 (define_insn "addsi_regs"
669 [(set (match_operand:SI 0 "register_operand" "=r")
670 (plus:SI (match_operand:SI 1 "register_operand" "%0")
671 (match_operand:SI 2 "register_operand" "r")))]
676 ;; Do not allow an eliminable register in the source register. It
677 ;; might be eliminated in favor of the stack pointer, probably
678 ;; increasing the offset, and so rendering the instruction illegal.
679 (define_insn "addsi_small_int"
680 [(set (match_operand:SI 0 "register_operand" "=r,r")
681 (plus:SI (match_operand:SI 1 "register_operand" "0,0")
682 (match_operand:SI 2 "add_immediate_operand" "I,J")))]
683 " (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
684 && (REGNO (operands[1]) != ARG_POINTER_REGNUM)"
690 (define_expand "addsi_big_int"
691 [(set (match_operand:SI 0 "register_operand" "")
692 (plus:SI (match_operand:SI 1 "register_operand" "")
693 (match_operand:SI 2 "immediate_operand" "")))]
696 /* Cope with the possibility that ops 0 and 1 are the same register. */
697 if (REGNO (operands[0]) == REGNO (operands[1]))
699 if (reload_in_progress || reload_completed)
701 rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
703 emit_insn (gen_movsi (reg, operands[2]));
704 emit_insn (gen_addsi_regs (operands[0], operands[0], reg));
708 operands[2] = force_reg (SImode, operands[2]);
709 emit_insn (gen_addsi_regs (operands[0], operands[0], operands[2]));
714 emit_insn (gen_movsi (operands[0], operands[2]));
715 emit_insn (gen_addsi_regs (operands[0], operands[0], operands[1]));
721 (define_insn "*addsi_for_reload"
722 [(set (match_operand:SI 0 "register_operand" "=&r,r,r")
723 (plus:SI (match_operand:SI 1 "register_operand" "r,r,r")
724 (match_operand:SI 2 "immediate_operand" "L,M,n")))]
725 "reload_in_progress || reload_completed"
727 ldi:8\\t#%2, %0 \\n\\taddn\\t%1, %0
728 ldi:20\\t#%2, %0 \\n\\taddn\\t%1, %0
729 ldi:32\\t#%2, %0 \\n\\taddn\\t%1, %0"
730 [(set_attr "length" "4,6,8")]
736 (define_insn "subsi3"
737 [(set (match_operand:SI 0 "register_operand" "=r")
738 (minus:SI (match_operand:SI 1 "register_operand" "0")
739 (match_operand:SI 2 "register_operand" "r")))]
747 ;; Signed multiplication producing 64 bit results from 32 bit inputs
748 (define_insn "mulsidi3"
749 [(set (match_operand:DI 0 "register_operand" "=r")
750 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
751 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))
752 (clobber (reg:CC 16))]
754 "mul %2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
755 [(set_attr "length" "6")]
758 ;; Unsigned multiplication producing 64 bit results from 32 bit inputs
759 (define_insn "umulsidi3"
760 [(set (match_operand:DI 0 "register_operand" "=r")
761 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
762 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
763 (clobber (reg:CC 16))]
765 "mulu %2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
766 [(set_attr "length" "6")]
769 ;; Signed multiplication producing 32 bit result from 16 bit inputs
770 (define_insn "mulhisi3"
771 [(set (match_operand:SI 0 "register_operand" "=r")
772 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
773 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))
774 (clobber (reg:CC 16))]
776 "mulh %2, %1\\n\\tmov\\tmdl, %0"
777 [(set_attr "length" "4")]
780 ;; Unsigned multiplication producing 32 bit result from 16 bit inputs
781 (define_insn "umulhisi3"
782 [(set (match_operand:SI 0 "register_operand" "=r")
783 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
784 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))
785 (clobber (reg:CC 16))]
787 "muluh %2, %1\\n\\tmov\\tmdl, %0"
788 [(set_attr "length" "4")]
791 ;; Signed multiplication producing 32 bit result from 32 bit inputs
792 (define_insn "mulsi3"
793 [(set (match_operand:SI 0 "register_operand" "=r")
794 (mult:SI (match_operand:SI 1 "register_operand" "%r")
795 (match_operand:SI 2 "register_operand" "r")))
796 (clobber (reg:CC 16))]
798 "mul %2, %1\\n\\tmov\\tmdl, %0"
799 [(set_attr "length" "4")]
805 (define_expand "negsi2"
806 [(set (match_operand:SI 0 "register_operand" "")
807 (neg:SI (match_operand:SI 1 "register_operand" "")))]
810 if (REGNO (operands[0]) == REGNO (operands[1]))
812 if (reload_in_progress || reload_completed)
814 rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
816 emit_insn (gen_movsi (reg, const0_rtx));
817 emit_insn (gen_subsi3 (reg, reg, operands[0]));
818 emit_insn (gen_movsi (operands[0], reg));
822 rtx reg = gen_reg_rtx (SImode);
824 emit_insn (gen_movsi (reg, const0_rtx));
825 emit_insn (gen_subsi3 (reg, reg, operands[0]));
826 emit_insn (gen_movsi (operands[0], reg));
831 emit_insn (gen_movsi_internal (operands[0], const0_rtx));
832 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
843 ;; Arithmetic Shift Left
844 (define_insn "ashlsi3"
845 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
846 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0")
847 (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
848 (clobber (reg:CC 16))]
856 ;; Arithmetic Shift Right
857 (define_insn "ashrsi3"
858 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
859 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0")
860 (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
861 (clobber (reg:CC 16))]
869 ;; Logical Shift Right
870 (define_insn "lshrsi3"
871 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
872 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0")
873 (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
874 (clobber (reg:CC 16))]
883 ;;{{{ Logical Operations
885 ;; Logical AND, 32 bit integers
886 (define_insn "andsi3"
887 [(set (match_operand:SI 0 "register_operand" "=r")
888 (and:SI (match_operand:SI 1 "register_operand" "%r")
889 (match_operand:SI 2 "register_operand" "0")))
890 (clobber (reg:CC 16))]
895 ;; Inclusive OR, 32 bit integers
896 (define_insn "iorsi3"
897 [(set (match_operand:SI 0 "register_operand" "=r")
898 (ior:SI (match_operand:SI 1 "register_operand" "%r")
899 (match_operand:SI 2 "register_operand" "0")))
900 (clobber (reg:CC 16))]
905 ;; Exclusive OR, 32 bit integers
906 (define_insn "xorsi3"
907 [(set (match_operand:SI 0 "register_operand" "=r")
908 (xor:SI (match_operand:SI 1 "register_operand" "%r")
909 (match_operand:SI 2 "register_operand" "0")))
910 (clobber (reg:CC 16))]
915 ;; One's complement, 32 bit integers
916 (define_expand "one_cmplsi2"
917 [(set (match_operand:SI 0 "register_operand" "")
918 (not:SI (match_operand:SI 1 "register_operand" "")))]
921 if (REGNO (operands[0]) == REGNO (operands[1]))
923 if (reload_in_progress || reload_completed)
925 rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
927 emit_insn (gen_movsi (reg, constm1_rtx));
928 emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
932 rtx reg = gen_reg_rtx (SImode);
934 emit_insn (gen_movsi (reg, constm1_rtx));
935 emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
940 emit_insn (gen_movsi_internal (operands[0], constm1_rtx));
941 emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
950 ;; Note, we store the operands in the comparison insns, and use them later
951 ;; when generating the branch or scc operation.
953 ;; First the routines called by the machine independent part of the compiler
954 (define_expand "cmpsi"
956 (compare:CC (match_operand:SI 0 "register_operand" "")
957 (match_operand:SI 1 "nonmemory_operand" "")))]
960 fr30_compare_op0 = operands[0];
961 fr30_compare_op1 = operands[1];
966 ;; Now, the actual comparisons, generated by the branch and/or scc operations
968 (define_insn "*cmpsi_internal"
970 (compare:CC (match_operand:SI 0 "register_operand" "r,r,r")
971 (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
982 ;; Define_expands called by the machine independent part of the compiler
983 ;; to allocate a new comparison register
987 (compare:CC (match_dup 1)
990 (if_then_else (eq:CC (reg:CC 16)
992 (label_ref (match_operand 0 "" ""))
996 operands[1] = fr30_compare_op0;
997 operands[2] = fr30_compare_op1;
1001 (define_expand "bne"
1003 (compare:CC (match_dup 1)
1006 (if_then_else (ne:CC (reg:CC 16)
1008 (label_ref (match_operand 0 "" ""))
1012 operands[1] = fr30_compare_op0;
1013 operands[2] = fr30_compare_op1;
1017 (define_expand "blt"
1019 (compare:CC (match_dup 1)
1022 (if_then_else (lt:CC (reg:CC 16)
1024 (label_ref (match_operand 0 "" ""))
1028 operands[1] = fr30_compare_op0;
1029 operands[2] = fr30_compare_op1;
1033 (define_expand "ble"
1035 (compare:CC (match_dup 1)
1038 (if_then_else (le:CC (reg:CC 16)
1040 (label_ref (match_operand 0 "" ""))
1044 operands[1] = fr30_compare_op0;
1045 operands[2] = fr30_compare_op1;
1049 (define_expand "bgt"
1051 (compare:CC (match_dup 1)
1054 (if_then_else (gt:CC (reg:CC 16)
1056 (label_ref (match_operand 0 "" ""))
1060 operands[1] = fr30_compare_op0;
1061 operands[2] = fr30_compare_op1;
1065 (define_expand "bge"
1067 (compare:CC (match_dup 1)
1070 (if_then_else (ge:CC (reg:CC 16)
1072 (label_ref (match_operand 0 "" ""))
1076 operands[1] = fr30_compare_op0;
1077 operands[2] = fr30_compare_op1;
1081 (define_expand "bltu"
1083 (compare:CC (match_dup 1)
1086 (if_then_else (ltu:CC (reg:CC 16)
1088 (label_ref (match_operand 0 "" ""))
1092 operands[1] = fr30_compare_op0;
1093 operands[2] = fr30_compare_op1;
1097 (define_expand "bleu"
1099 (compare:CC (match_dup 1)
1102 (if_then_else (leu:CC (reg:CC 16)
1104 (label_ref (match_operand 0 "" ""))
1108 operands[1] = fr30_compare_op0;
1109 operands[2] = fr30_compare_op1;
1113 (define_expand "bgtu"
1115 (compare:CC (match_dup 1)
1118 (if_then_else (gtu:CC (reg:CC 16)
1120 (label_ref (match_operand 0 "" ""))
1124 operands[1] = fr30_compare_op0;
1125 operands[2] = fr30_compare_op1;
1129 (define_expand "bgeu"
1131 (compare:CC (match_dup 1)
1134 (if_then_else (geu:CC (reg:CC 16)
1136 (label_ref (match_operand 0 "" ""))
1140 operands[1] = fr30_compare_op0;
1141 operands[2] = fr30_compare_op1;
1145 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
1146 ;; swapped. If they are swapped, it reverses the sense of the branch.
1148 ;; This pattern matches the (branch-if-true) branches generated above.
1149 ;; It generates two different instruction sequences depending upon how
1150 ;; far away the destination is.
1152 ;; The calculation for the instruction length is derived as follows:
1153 ;; The branch instruction has a 9 bit signed displacement so we have
1154 ;; this inequality for the displacement:
1158 ;; -256 + 256 <= pc + 256 < 256 + 256
1160 ;; 0 <= pc + 256 < 512
1162 ;; if we consider the displacement as an unsigned value, then negative
1163 ;; displacements become very large positive displacements, and the
1164 ;; inequality becomes:
1168 ;; In order to allow for the fact that the real branch instruction works
1169 ;; from pc + 2, we increase the offset to 258.
1171 ;; Note - we do not have to worry about whether the branch is delayed or
1172 ;; not, as branch shortening happens after delay slot reorganization.
1174 (define_insn "*branch_true"
1176 (if_then_else (match_operator:CC 0 "comparison_operator"
1179 (label_ref (match_operand 1 "" ""))
1184 if (get_attr_length (insn) == 2)
1185 return \"b%b0%#\\t%l1\";
1188 static char buffer [100];
1189 const char * tmp_reg;
1190 const char * ldi_insn;
1192 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
1194 ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
1196 /* The code produced here is, for say the EQ case:
1204 \"b%%B0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\\n1:\",
1205 ldi_insn, tmp_reg, tmp_reg);
1210 [(set (attr "length") (if_then_else
1219 (if_then_else (eq_attr "size" "small")
1222 (set_attr "delay_type" "delayed")]
1226 ;; This pattern is a duplicate of the previous one, except that the
1227 ;; branch occurs if the test is false, so the %B operator is used.
1228 (define_insn "*branch_false"
1230 (if_then_else (match_operator:CC 0 "comparison_operator"
1234 (label_ref (match_operand 1 "" ""))))]
1238 if (get_attr_length (insn) == 2)
1239 return \"b%B0%#\\t%l1 \";
1242 static char buffer [100];
1243 const char * tmp_reg;
1244 const char * ldi_insn;
1246 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
1248 ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
1251 \"b%%b0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\\n1:\",
1252 ldi_insn, tmp_reg, tmp_reg);
1257 [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 1) (pc))
1261 (if_then_else (eq_attr "size" "small")
1264 (set_attr "delay_type" "delayed")]
1270 ;; Subroutine call instruction returning no value. Operand 0 is the function
1271 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
1272 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
1273 ;; registers used as operands.
1276 [(call (match_operand 0 "call_operand" "Qm")
1277 (match_operand 1 "" "g"))
1278 (clobber (reg:SI 17))]
1281 [(set_attr "delay_type" "delayed")]
1284 ;; Subroutine call instruction returning a value. Operand 0 is the hard
1285 ;; register in which the value is returned. There are three more operands, the
1286 ;; same as the three operands of the `call' instruction (but with numbers
1287 ;; increased by one).
1289 ;; Subroutines that return `BLKmode' objects use the `call' insn.
1291 (define_insn "call_value"
1292 [(set (match_operand 0 "register_operand" "=r")
1293 (call (match_operand 1 "call_operand" "Qm")
1294 (match_operand 2 "" "g")))
1295 (clobber (reg:SI 17))]
1298 [(set_attr "delay_type" "delayed")]
1301 ;; Normal unconditional jump.
1302 ;; For a description of the computation of the length
1303 ;; attribute see the branch patterns above.
1305 ;; Although this instruction really clobbers r0, flow
1306 ;; relies on jump being simplejump_p in several places
1307 ;; and as r0 is fixed, this doesn't change anything
1309 [(set (pc) (label_ref (match_operand 0 "" "")))]
1313 if (get_attr_length (insn) == 2)
1314 return \"bra%#\\t%0\";
1317 static char buffer [100];
1318 const char * tmp_reg;
1319 const char * ldi_insn;
1321 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
1323 ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
1325 sprintf (buffer, \"%s\\t%%0, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\",
1326 ldi_insn, tmp_reg, tmp_reg);
1331 [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1335 (if_then_else (eq_attr "size" "small")
1338 (set_attr "delay_type" "delayed")]
1341 ;; Indirect jump through a register
1342 (define_insn "indirect_jump"
1343 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
1344 "GET_CODE (operands[0]) != MEM || GET_CODE (XEXP (operands[0], 0)) != PLUS"
1346 [(set_attr "delay_type" "delayed")]
1349 (define_insn "tablejump"
1350 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1351 (use (label_ref (match_operand 1 "" "")))]
1354 [(set_attr "delay_type" "delayed")]
1358 ;;{{{ Function Prologues and Epilogues
1360 ;; Called after register allocation to add any instructions needed for the
1361 ;; prologue. Using a prologue insn is favored compared to putting all of the
1362 ;; instructions in output_function_prologue(), since it allows the scheduler
1363 ;; to intermix instructions with the saves of the caller saved registers. In
1364 ;; some cases, it might be necessary to emit a barrier instruction as the last
1365 ;; insn to prevent such scheduling.
1366 (define_expand "prologue"
1367 [(clobber (const_int 0))]
1370 fr30_expand_prologue ();
1375 ;; Called after register allocation to add any instructions needed for the
1376 ;; epilogue. Using an epilogue insn is favored compared to putting all of the
1377 ;; instructions in output_function_epilogue(), since it allows the scheduler
1378 ;; to intermix instructions with the restores of the caller saved registers.
1379 ;; In some cases, it might be necessary to emit a barrier instruction as the
1380 ;; first insn to prevent such scheduling.
1381 (define_expand "epilogue"
1385 fr30_expand_epilogue ();
1390 (define_insn "return_from_func"
1395 [(set_attr "delay_type" "delayed")]
1398 (define_insn "leave_func"
1399 [(set (reg:SI 15) (reg:SI 14))
1400 (set (reg:SI 14) (mem:SI (post_inc:SI (reg:SI 15))))]
1405 (define_insn "enter_func"
1406 [(set:SI (mem:SI (minus:SI (reg:SI 15)
1410 (minus:SI (reg:SI 15)
1413 (minus:SI (reg:SI 15)
1414 (match_operand 0 "immediate_operand" "i")))]
1417 [(set_attr "delay_type" "other")]
1423 ;; No operation, needed in case the user uses -g but not -O.
1430 ;; Pseudo instruction that prevents the scheduler from moving code above this
1432 (define_insn "blockage"
1433 [(unspec_volatile [(const_int 0)] 0)]
1436 [(set_attr "length" "0")]