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Implement SLP of internal functions
[official-gcc.git] / gcc / common / config / i386 / i386-common.c
blob277ee55a09314352d0161457baf3f12b5fd286a9
1 /* IA-32 common hooks.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
91 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
92 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
93 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
94 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
95 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
96 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
97 #define OPTION_MASK_ISA_XSAVES_SET \
98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE)
99 #define OPTION_MASK_ISA_XSAVEC_SET \
100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
101 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
102
103 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
104 as -msse4.2. */
105 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
106
107 #define OPTION_MASK_ISA_SSE4A_SET \
108 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
109 #define OPTION_MASK_ISA_FMA4_SET \
110 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
111 | OPTION_MASK_ISA_AVX_SET)
112 #define OPTION_MASK_ISA_XOP_SET \
113 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
114 #define OPTION_MASK_ISA_LWP_SET \
115 OPTION_MASK_ISA_LWP
116
117 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
118 #define OPTION_MASK_ISA_AES_SET \
119 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
120 #define OPTION_MASK_ISA_SHA_SET \
121 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
122 #define OPTION_MASK_ISA_PCLMUL_SET \
123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
124
125 #define OPTION_MASK_ISA_ABM_SET \
126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
127
128 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG
129 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD
130 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
131 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
132 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
133 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
134 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
135 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
136 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
137 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
138 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
139 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
140
141 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
142 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
143 #define OPTION_MASK_ISA_F16C_SET \
144 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
145 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
146 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
147 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
148 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
149 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
150 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
151 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
152 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
153 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
154 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
155 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
156 #define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE
157
158 /* Define a set of ISAs which aren't available when a given ISA is
159 disabled. MMX and SSE ISAs are handled separately. */
160
161 #define OPTION_MASK_ISA_MMX_UNSET \
162 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
163 #define OPTION_MASK_ISA_3DNOW_UNSET \
164 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
165 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
166
167 #define OPTION_MASK_ISA_SSE_UNSET \
168 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
169 #define OPTION_MASK_ISA_SSE2_UNSET \
170 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
171 #define OPTION_MASK_ISA_SSE3_UNSET \
172 (OPTION_MASK_ISA_SSE3 \
173 | OPTION_MASK_ISA_SSSE3_UNSET \
174 | OPTION_MASK_ISA_SSE4A_UNSET )
175 #define OPTION_MASK_ISA_SSSE3_UNSET \
176 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
177 #define OPTION_MASK_ISA_SSE4_1_UNSET \
178 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
179 #define OPTION_MASK_ISA_SSE4_2_UNSET \
180 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
181 #define OPTION_MASK_ISA_AVX_UNSET \
182 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
183 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
184 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
185 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
186 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
187 #define OPTION_MASK_ISA_XSAVE_UNSET \
188 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET)
189 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
190 #define OPTION_MASK_ISA_AVX2_UNSET \
191 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
192 #define OPTION_MASK_ISA_AVX512F_UNSET \
193 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
194 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
195 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
196 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
197 | OPTION_MASK_ISA_AVX512VNNI_UNSET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
198 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
199 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
200 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
201 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
202 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
203 #define OPTION_MASK_ISA_AVX512BW_UNSET \
204 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
205 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
206 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
207 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
208 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
209 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
210 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
211 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
212 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
213 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
214 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
215 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
216 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
217 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
218 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
219 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
220 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
221 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
222 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
223 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
224 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
225 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
226 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
227 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
228 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
229 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
230 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
231 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
232 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
233 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
234 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
235
236 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
237 as -mno-sse4.1. */
238 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
239
240 #define OPTION_MASK_ISA_SSE4A_UNSET \
241 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
242
243 #define OPTION_MASK_ISA_FMA4_UNSET \
244 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
245 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
246 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
247
248 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
249 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
250 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
251 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
252 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG
253 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD
254 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
255 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
256 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
257 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
258 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
259 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
260 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
261 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
262 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
263 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
264
265 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
266 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
267 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
268
269 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
270 (OPTION_MASK_ISA_MMX_UNSET \
271 | OPTION_MASK_ISA_SSE_UNSET)
272
273 #define OPTION_MASK_ISA2_AVX512F_UNSET \
274 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
275 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
276 (OPTION_MASK_ISA2_AVX512F_UNSET)
277
278 /* Set 1 << value as value of -malign-FLAG option. */
279
280 static void
281 set_malign_value (const char **flag, unsigned value)
282 {
283 char *r = XNEWVEC (char, 6);
284 sprintf (r, "%d", 1 << value);
285 *flag = r;
286 }
287
288 /* Implement TARGET_HANDLE_OPTION. */
289
290 bool
291 ix86_handle_option (struct gcc_options *opts,
292 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
293 const struct cl_decoded_option *decoded,
294 location_t loc)
295 {
296 size_t code = decoded->opt_index;
297 int value = decoded->value;
298
299 switch (code)
300 {
301 case OPT_mgeneral_regs_only:
302 if (value)
303 {
304 /* Disable MMX, SSE and x87 instructions if only
305 general registers are allowed. */
306 opts->x_ix86_isa_flags
307 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
308 opts->x_ix86_isa_flags2
309 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
310 opts->x_ix86_isa_flags_explicit
311 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
312 opts->x_ix86_isa_flags2_explicit
313 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
314
315 opts->x_target_flags &= ~MASK_80387;
316 }
317 else
318 gcc_unreachable ();
319 return true;
320
321 case OPT_mmmx:
322 if (value)
323 {
324 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
325 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
326 }
327 else
328 {
329 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
330 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
331 }
332 return true;
333
334 case OPT_m3dnow:
335 if (value)
336 {
337 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
338 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
339 }
340 else
341 {
342 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
343 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
344 }
345 return true;
346
347 case OPT_m3dnowa:
348 if (value)
349 {
350 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
351 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
352 }
353 else
354 {
355 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
356 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
357 }
358 return true;
359
360 case OPT_msse:
361 if (value)
362 {
363 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
364 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
365 }
366 else
367 {
368 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
369 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
370 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
371 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
372 }
373 return true;
374
375 case OPT_msse2:
376 if (value)
377 {
378 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
379 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
380 }
381 else
382 {
383 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
384 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
385 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
386 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
387 }
388 return true;
389
390 case OPT_msse3:
391 if (value)
392 {
393 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
394 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
395 }
396 else
397 {
398 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
399 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
400 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
401 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
402 }
403 return true;
404
405 case OPT_mssse3:
406 if (value)
407 {
408 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
409 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
410 }
411 else
412 {
413 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
414 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
415 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
416 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
417 }
418 return true;
419
420 case OPT_msse4_1:
421 if (value)
422 {
423 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
424 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
425 }
426 else
427 {
428 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
429 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
430 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
431 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
432 }
433 return true;
434
435 case OPT_msse4_2:
436 if (value)
437 {
438 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
439 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
440 }
441 else
442 {
443 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
444 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
445 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
446 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
447 }
448 return true;
449
450 case OPT_mavx:
451 if (value)
452 {
453 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
454 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
455 }
456 else
457 {
458 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
459 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
460 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
461 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
462 }
463 return true;
464
465 case OPT_mavx2:
466 if (value)
467 {
468 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
469 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
470 }
471 else
472 {
473 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
474 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
475 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
476 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
477 }
478 return true;
479
480 case OPT_mavx512f:
481 if (value)
482 {
483 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
484 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
485 }
486 else
487 {
488 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
489 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
490 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
491 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
492 }
493 return true;
494
495 case OPT_mavx512cd:
496 if (value)
497 {
498 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
499 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
500 }
501 else
502 {
503 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
504 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
505 }
506 return true;
507
508 case OPT_mavx512pf:
509 if (value)
510 {
511 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
512 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
513 }
514 else
515 {
516 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
517 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
518 }
519 return true;
520
521 case OPT_mavx512er:
522 if (value)
523 {
524 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
525 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
526 }
527 else
528 {
529 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
530 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
531 }
532 return true;
533
534 case OPT_mrdpid:
535 if (value)
536 {
537 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET;
538 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET;
539 }
540 else
541 {
542 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET;
543 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET;
544 }
545 return true;
546
547 case OPT_mgfni:
548 if (value)
549 {
550 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
551 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
552 }
553 else
554 {
555 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
556 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
557 }
558 return true;
559
560 case OPT_mshstk:
561 if (value)
562 {
563 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
564 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
565 }
566 else
567 {
568 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
569 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
570 }
571 return true;
572
573 case OPT_mvaes:
574 if (value)
575 {
576 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET;
577 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET;
578 }
579 else
580 {
581 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET;
582 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET;
583 }
584 return true;
585
586 case OPT_mvpclmulqdq:
587 if (value)
588 {
589 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
590 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
591 }
592 else
593 {
594 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
595 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
596 }
597 return true;
598
599 case OPT_mmovdiri:
600 if (value)
601 {
602 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
603 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
604 }
605 else
606 {
607 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
608 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
609 }
610 return true;
611
612 case OPT_mmovdir64b:
613 if (value)
614 {
615 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET;
616 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET;
617 }
618 else
619 {
620 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET;
621 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET;
622 }
623 return true;
624
625 case OPT_mcldemote:
626 if (value)
627 {
628 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET;
629 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET;
630 }
631 else
632 {
633 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET;
634 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET;
635 }
636 return true;
637
638 case OPT_mwaitpkg:
639 if (value)
640 {
641 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET;
642 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET;
643 }
644 else
645 {
646 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET;
647 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET;
648 }
649 return true;
650
651 case OPT_mavx5124fmaps:
652 if (value)
653 {
654 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
655 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
656 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
657 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
658 }
659 else
660 {
661 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
662 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
663 }
664 return true;
665
666 case OPT_mavx5124vnniw:
667 if (value)
668 {
669 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
670 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
671 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
672 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
673 }
674 else
675 {
676 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
677 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
678 }
679 return true;
680
681 case OPT_mavx512vbmi2:
682 if (value)
683 {
684 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
685 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
686 }
687 else
688 {
689 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
690 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
691 }
692 return true;
693
694 case OPT_mavx512vnni:
695 if (value)
696 {
697 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
698 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
699 }
700 else
701 {
702 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
703 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
704 }
705 return true;
706
707 case OPT_mavx512vpopcntdq:
708 if (value)
709 {
710 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
711 opts->x_ix86_isa_flags_explicit
712 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
713 }
714 else
715 {
716 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
717 opts->x_ix86_isa_flags_explicit
718 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
719 }
720 return true;
721
722 case OPT_mavx512bitalg:
723 if (value)
724 {
725 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
726 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
727 }
728 else
729 {
730 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
731 opts->x_ix86_isa_flags_explicit
732 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
733 }
734 return true;
735
736 case OPT_msgx:
737 if (value)
738 {
739 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
740 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
741 }
742 else
743 {
744 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
745 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
746 }
747 return true;
748
749 case OPT_mpconfig:
750 if (value)
751 {
752 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET;
753 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET;
754 }
755 else
756 {
757 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET;
758 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET;
759 }
760 return true;
761
762 case OPT_mwbnoinvd:
763 if (value)
764 {
765 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET;
766 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET;
767 }
768 else
769 {
770 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET;
771 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET;
772 }
773 return true;
774
775 case OPT_mavx512dq:
776 if (value)
777 {
778 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
779 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
780 }
781 else
782 {
783 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
784 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
785 }
786 return true;
787
788 case OPT_mavx512bw:
789 if (value)
790 {
791 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
792 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
793 }
794 else
795 {
796 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
797 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
798 }
799 return true;
800
801 case OPT_mavx512vl:
802 if (value)
803 {
804 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
805 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
806 }
807 else
808 {
809 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
810 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
811 }
812 return true;
813
814 case OPT_mavx512ifma:
815 if (value)
816 {
817 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
818 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
819 }
820 else
821 {
822 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
823 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
824 }
825 return true;
826
827 case OPT_mavx512vbmi:
828 if (value)
829 {
830 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
831 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
832 }
833 else
834 {
835 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
836 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
837 }
838 return true;
839
840 case OPT_mfma:
841 if (value)
842 {
843 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
844 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
845 }
846 else
847 {
848 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
849 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
850 }
851 return true;
852
853 case OPT_mrtm:
854 if (value)
855 {
856 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
857 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
858 }
859 else
860 {
861 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
862 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
863 }
864 return true;
865
866 case OPT_msse4:
867 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
868 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
869 return true;
870
871 case OPT_mno_sse4:
872 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
873 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
874 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
875 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
876 return true;
877
878 case OPT_msse4a:
879 if (value)
880 {
881 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
882 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
883 }
884 else
885 {
886 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
887 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
888 }
889 return true;
890
891 case OPT_mfma4:
892 if (value)
893 {
894 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
895 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
896 }
897 else
898 {
899 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
900 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
901 }
902 return true;
903
904 case OPT_mxop:
905 if (value)
906 {
907 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
908 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
909 }
910 else
911 {
912 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
913 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
914 }
915 return true;
916
917 case OPT_mlwp:
918 if (value)
919 {
920 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
921 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
922 }
923 else
924 {
925 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
926 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
927 }
928 return true;
929
930 case OPT_mabm:
931 if (value)
932 {
933 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
934 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
935 }
936 else
937 {
938 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
939 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
940 }
941 return true;
942
943 case OPT_mbmi:
944 if (value)
945 {
946 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
947 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
948 }
949 else
950 {
951 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
952 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
953 }
954 return true;
955
956 case OPT_mbmi2:
957 if (value)
958 {
959 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
960 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
961 }
962 else
963 {
964 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
965 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
966 }
967 return true;
968
969 case OPT_mlzcnt:
970 if (value)
971 {
972 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
973 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
974 }
975 else
976 {
977 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
978 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
979 }
980 return true;
981
982 case OPT_mtbm:
983 if (value)
984 {
985 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
986 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
987 }
988 else
989 {
990 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
991 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
992 }
993 return true;
994
995 case OPT_mpopcnt:
996 if (value)
997 {
998 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
999 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1000 }
1001 else
1002 {
1003 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1004 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1005 }
1006 return true;
1007
1008 case OPT_msahf:
1009 if (value)
1010 {
1011 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1012 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1013 }
1014 else
1015 {
1016 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1017 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1018 }
1019 return true;
1020
1021 case OPT_mcx16:
1022 if (value)
1023 {
1024 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET;
1025 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET;
1026 }
1027 else
1028 {
1029 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET;
1030 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET;
1031 }
1032 return true;
1033
1034 case OPT_mmovbe:
1035 if (value)
1036 {
1037 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET;
1038 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET;
1039 }
1040 else
1041 {
1042 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET;
1043 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
1044 }
1045 return true;
1046
1047 case OPT_mcrc32:
1048 if (value)
1049 {
1050 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1051 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1052 }
1053 else
1054 {
1055 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1056 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1057 }
1058 return true;
1059
1060 case OPT_maes:
1061 if (value)
1062 {
1063 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1064 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1065 }
1066 else
1067 {
1068 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1069 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1070 }
1071 return true;
1072
1073 case OPT_msha:
1074 if (value)
1075 {
1076 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1077 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1078 }
1079 else
1080 {
1081 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1082 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1083 }
1084 return true;
1085
1086 case OPT_mpclmul:
1087 if (value)
1088 {
1089 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1090 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1091 }
1092 else
1093 {
1094 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1095 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1096 }
1097 return true;
1098
1099 case OPT_mfsgsbase:
1100 if (value)
1101 {
1102 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1103 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1104 }
1105 else
1106 {
1107 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1108 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1109 }
1110 return true;
1111
1112 case OPT_mrdrnd:
1113 if (value)
1114 {
1115 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1116 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1117 }
1118 else
1119 {
1120 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1121 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1122 }
1123 return true;
1124
1125 case OPT_mf16c:
1126 if (value)
1127 {
1128 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1129 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1130 }
1131 else
1132 {
1133 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1134 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1135 }
1136 return true;
1137
1138 case OPT_mfxsr:
1139 if (value)
1140 {
1141 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1142 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1143 }
1144 else
1145 {
1146 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1147 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1148 }
1149 return true;
1150
1151 case OPT_mxsave:
1152 if (value)
1153 {
1154 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1155 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1156 }
1157 else
1158 {
1159 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1160 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1161 }
1162 return true;
1163
1164 case OPT_mxsaveopt:
1165 if (value)
1166 {
1167 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1168 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1169 }
1170 else
1171 {
1172 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1173 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1174 }
1175 return true;
1176
1177 case OPT_mxsavec:
1178 if (value)
1179 {
1180 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1181 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1182 }
1183 else
1184 {
1185 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1186 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1187 }
1188 return true;
1189
1190 case OPT_mxsaves:
1191 if (value)
1192 {
1193 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1194 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1195 }
1196 else
1197 {
1198 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1199 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1200 }
1201 return true;
1202
1203 case OPT_mrdseed:
1204 if (value)
1205 {
1206 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1207 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1208 }
1209 else
1210 {
1211 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1212 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1213 }
1214 return true;
1215
1216 case OPT_mprfchw:
1217 if (value)
1218 {
1219 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1220 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1221 }
1222 else
1223 {
1224 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1225 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1226 }
1227 return true;
1228
1229 case OPT_madx:
1230 if (value)
1231 {
1232 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1233 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1234 }
1235 else
1236 {
1237 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1238 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1239 }
1240 return true;
1241
1242 case OPT_mprefetchwt1:
1243 if (value)
1244 {
1245 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1246 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1247 }
1248 else
1249 {
1250 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1251 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1252 }
1253 return true;
1254
1255 case OPT_mclflushopt:
1256 if (value)
1257 {
1258 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1259 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1260 }
1261 else
1262 {
1263 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1264 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1265 }
1266 return true;
1267
1268 case OPT_mclwb:
1269 if (value)
1270 {
1271 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1272 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1273 }
1274 else
1275 {
1276 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1277 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1278 }
1279 return true;
1280
1281 case OPT_mmwaitx:
1282 if (value)
1283 {
1284 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET;
1285 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET;
1286 }
1287 else
1288 {
1289 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET;
1290 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
1291 }
1292 return true;
1293
1294 case OPT_mclzero:
1295 if (value)
1296 {
1297 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET;
1298 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET;
1299 }
1300 else
1301 {
1302 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET;
1303 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
1304 }
1305 return true;
1306
1307 case OPT_mpku:
1308 if (value)
1309 {
1310 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1311 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1312 }
1313 else
1314 {
1315 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1316 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1317 }
1318 return true;
1319
1320
1321 /* Comes from final.c -- no real reason to change it. */
1322 #define MAX_CODE_ALIGN 16
1323
1324 case OPT_malign_loops_:
1325 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
1326 if (value > MAX_CODE_ALIGN)
1327 error_at (loc, "-malign-loops=%d is not between 0 and %d",
1328 value, MAX_CODE_ALIGN);
1329 else
1330 set_malign_value (&opts->x_str_align_loops, value);
1331 return true;
1332
1333 case OPT_malign_jumps_:
1334 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
1335 if (value > MAX_CODE_ALIGN)
1336 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
1337 value, MAX_CODE_ALIGN);
1338 else
1339 set_malign_value (&opts->x_str_align_jumps, value);
1340 return true;
1341
1342 case OPT_malign_functions_:
1343 warning_at (loc, 0,
1344 "-malign-functions is obsolete, use -falign-functions");
1345 if (value > MAX_CODE_ALIGN)
1346 error_at (loc, "-malign-functions=%d is not between 0 and %d",
1347 value, MAX_CODE_ALIGN);
1348 else
1349 set_malign_value (&opts->x_str_align_functions, value);
1350 return true;
1351
1352 case OPT_mbranch_cost_:
1353 if (value > 5)
1354 {
1355 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
1356 opts->x_ix86_branch_cost = 5;
1357 }
1358 return true;
1359
1360 default:
1361 return true;
1362 }
1363 }
1364
1365 static const struct default_options ix86_option_optimization_table[] =
1366 {
1367 /* Enable redundant extension instructions removal at -O2 and higher. */
1368 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1369 /* Enable function splitting at -O2 and higher. */
1370 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1371 /* The STC algorithm produces the smallest code at -Os, for x86. */
1372 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1373 REORDER_BLOCKS_ALGORITHM_STC },
1374 /* Turn off -fschedule-insns by default. It tends to make the
1375 problem with not enough registers even worse. */
1376 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1377
1378 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1379 SUBTARGET_OPTIMIZATION_OPTIONS,
1380 #endif
1381 { OPT_LEVELS_NONE, 0, NULL, 0 }
1382 };
1383
1384 /* Implement TARGET_OPTION_INIT_STRUCT. */
1385
1386 static void
1387 ix86_option_init_struct (struct gcc_options *opts)
1388 {
1389 if (TARGET_MACHO)
1390 /* The Darwin libraries never set errno, so we might as well
1391 avoid calling them when that's the only reason we would. */
1392 opts->x_flag_errno_math = 0;
1393
1394 opts->x_flag_pcc_struct_return = 2;
1395 opts->x_flag_asynchronous_unwind_tables = 2;
1396 }
1397
1398 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1399 field in the TCB, so they can not be used together. */
1400
1401 static bool
1402 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1403 struct gcc_options *opts ATTRIBUTE_UNUSED)
1404 {
1405 bool ret = true;
1406
1407 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1408 if (report)
1409 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1410 ret = false;
1411 #else
1412 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1413 {
1414 if (report)
1415 error ("%<-fsplit-stack%> requires "
1416 "assembler support for CFI directives");
1417 ret = false;
1418 }
1419 #endif
1420
1421 return ret;
1422 }
1423
1424 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1425
1426 static enum unwind_info_type
1427 i386_except_unwind_info (struct gcc_options *opts)
1428 {
1429 /* Honor the --enable-sjlj-exceptions configure switch. */
1430 #ifdef CONFIG_SJLJ_EXCEPTIONS
1431 if (CONFIG_SJLJ_EXCEPTIONS)
1432 return UI_SJLJ;
1433 #endif
1434
1435 /* On windows 64, prefer SEH exceptions over anything else. */
1436 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1437 return UI_SEH;
1438
1439 if (DWARF2_UNWIND_INFO)
1440 return UI_DWARF2;
1441
1442 return UI_SJLJ;
1443 }
1444
1445 #undef TARGET_EXCEPT_UNWIND_INFO
1446 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1447
1448 #undef TARGET_DEFAULT_TARGET_FLAGS
1449 #define TARGET_DEFAULT_TARGET_FLAGS \
1450 (TARGET_DEFAULT \
1451 | TARGET_SUBTARGET_DEFAULT \
1452 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1453
1454 #undef TARGET_HANDLE_OPTION
1455 #define TARGET_HANDLE_OPTION ix86_handle_option
1456
1457 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1458 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1459 #undef TARGET_OPTION_INIT_STRUCT
1460 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1461
1462 #undef TARGET_SUPPORTS_SPLIT_STACK
1463 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1464
1465 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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