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200x-xx-xx Nathan Sidwell <nathan@codesourcery.com>
[official-gcc.git] / gcc / config / m68k / m68k.h
blob434c25d76a971e759db3afa98e2a7a724367f668
1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
26 #if MOTOROLA /* Use the Motorola assembly syntax. */
27 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
28 #else
29 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
30 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
31 #endif
32
33 /* Handle --with-cpu default option from configure script. */
34 #define OPTION_DEFAULT_SPECS \
35 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
36 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
37 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
38 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
39
40 /* Pass flags to gas indicating which type of processor we have. This
41 can be simplified when we can rely on the assembler supporting .cpu
42 and .arch directives. */
43
44 #define ASM_CPU_SPEC "\
45 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
46 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
47 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
48 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
49 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
50 "
51
52 #define ASM_SPEC "%(asm_cpu_spec)"
53
54 #define EXTRA_SPECS \
55 { "asm_cpu_spec", ASM_CPU_SPEC }, \
56 SUBTARGET_EXTRA_SPECS
57
58 #define SUBTARGET_EXTRA_SPECS
59
60 /* Note that some other tm.h files include this one and then override
61 many of the definitions that relate to assembler syntax. */
62
63 #define TARGET_CPU_CPP_BUILTINS() \
64 do \
65 { \
66 builtin_define ("__m68k__"); \
67 builtin_define_std ("mc68000"); \
68 /* The other mc680x0 macros have traditionally been derived \
69 from the tuning setting. For example, -m68020-60 defines \
70 m68060, even though it generates pure 68020 code. */ \
71 switch (m68k_tune) \
72 { \
73 case u68010: \
74 builtin_define_std ("mc68010"); \
75 break; \
76 \
77 case u68020: \
78 builtin_define_std ("mc68020"); \
79 break; \
80 \
81 case u68030: \
82 builtin_define_std ("mc68030"); \
83 break; \
84 \
85 case u68040: \
86 builtin_define_std ("mc68040"); \
87 break; \
88 \
89 case u68060: \
90 builtin_define_std ("mc68060"); \
91 break; \
92 \
93 case u68020_60: \
94 builtin_define_std ("mc68060"); \
95 /* Fall through. */ \
96 case u68020_40: \
97 builtin_define_std ("mc68040"); \
98 builtin_define_std ("mc68030"); \
99 builtin_define_std ("mc68020"); \
100 break; \
101 \
102 case ucpu32: \
103 builtin_define_std ("mc68332"); \
104 builtin_define_std ("mcpu32"); \
105 builtin_define_std ("mc68020"); \
106 break; \
107 \
108 case ucfv2: \
109 builtin_define ("__mcfv2__"); \
110 break; \
111 \
112 case ucfv3: \
113 builtin_define ("__mcfv3__"); \
114 break; \
115 \
116 case ucfv4: \
117 builtin_define ("__mcfv4__"); \
118 break; \
119 \
120 case ucfv4e: \
121 builtin_define ("__mcfv4e__"); \
122 break; \
123 \
124 case ucfv5: \
125 builtin_define ("__mcfv5__"); \
126 break; \
127 \
128 default: \
129 break; \
130 } \
131 \
132 if (TARGET_68881) \
133 builtin_define ("__HAVE_68881__"); \
134 \
135 if (TARGET_COLDFIRE) \
136 { \
137 const char *tmp; \
138 \
139 tmp = m68k_cpp_cpu_ident ("cf"); \
140 if (tmp) \
141 builtin_define (tmp); \
142 tmp = m68k_cpp_cpu_family ("cf"); \
143 if (tmp) \
144 builtin_define (tmp); \
145 builtin_define ("__mcoldfire__"); \
146 \
147 if (TARGET_ISAC) \
148 builtin_define ("__mcfisac__"); \
149 else if (TARGET_ISAB) \
150 { \
151 builtin_define ("__mcfisab__"); \
152 /* ISA_B: Legacy 5407 defines. */ \
153 builtin_define ("__mcf5400__"); \
154 builtin_define ("__mcf5407__"); \
155 } \
156 else if (TARGET_ISAAPLUS) \
157 { \
158 builtin_define ("__mcfisaaplus__"); \
159 /* ISA_A+: legacy defines. */ \
160 builtin_define ("__mcf528x__"); \
161 builtin_define ("__mcf5200__"); \
162 } \
163 else \
164 { \
165 builtin_define ("__mcfisaa__"); \
166 /* ISA_A: legacy defines. */ \
167 switch (m68k_tune) \
168 { \
169 case ucfv2: \
170 builtin_define ("__mcf5200__"); \
171 break; \
172 \
173 case ucfv3: \
174 builtin_define ("__mcf5307__"); \
175 builtin_define ("__mcf5300__"); \
176 break; \
177 \
178 default: \
179 break; \
180 } \
181 } \
182 } \
183 \
184 if (TARGET_COLDFIRE_FPU) \
185 builtin_define ("__mcffpu__"); \
186 \
187 if (TARGET_CF_HWDIV) \
188 builtin_define ("__mcfhwdiv__"); \
189 \
190 builtin_assert ("cpu=m68k"); \
191 builtin_assert ("machine=m68k"); \
192 } \
193 while (0)
194
195 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
196 quantities. */
197 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
198 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
199 #define INT_OP_NO_DOT 2 /* byte, short, long */
200 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
201
202 /* Set the default. */
203 #define INT_OP_GROUP INT_OP_DOT_WORD
204
205 /* Bit values used by m68k-devices.def to identify processor capabilities. */
206 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
207 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
208 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
209 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
210 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
211 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
212 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
213 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
214 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
215 #define FL_ISA_68000 (1 << 9)
216 #define FL_ISA_68010 (1 << 10)
217 #define FL_ISA_68020 (1 << 11)
218 #define FL_ISA_68040 (1 << 12)
219 #define FL_ISA_A (1 << 13)
220 #define FL_ISA_APLUS (1 << 14)
221 #define FL_ISA_B (1 << 15)
222 #define FL_ISA_C (1 << 16)
223 #define FL_MMU 0 /* Used by multilib machinery. */
224
225 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
226 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
227 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
228 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
229 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
230 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
231
232 /* Size (in bytes) of FPU registers. */
233 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
234
235 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
236 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
237 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
238
239 #define TUNE_68000 (m68k_tune == u68000)
240 #define TUNE_68010 (m68k_tune == u68010)
241 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
242 #define TUNE_68030 (m68k_tune == u68030 \
243 || m68k_tune == u68020_40 \
244 || m68k_tune == u68020_60)
245 #define TUNE_68040 (m68k_tune == u68040 \
246 || m68k_tune == u68020_40 \
247 || m68k_tune == u68020_60)
248 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
249 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
250 #define TUNE_CPU32 (m68k_tune == ucpu32)
251 #define TUNE_CFV2 (m68k_tune == ucfv2)
252
253 #define OVERRIDE_OPTIONS override_options()
254
255 /* These are meant to be redefined in the host dependent files */
256 #define SUBTARGET_OVERRIDE_OPTIONS
257 \f
258 /* target machine storage layout */
259
260 /* "long double" is the same as "double" on ColdFire targets. */
261
262 #define LONG_DOUBLE_TYPE_SIZE (TARGET_COLDFIRE ? 64 : 80)
263
264 /* We need to know the size of long double at compile-time in libgcc2. */
265
266 #ifdef __mcoldfire__
267 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
268 #else
269 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
270 #endif
271
272 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
273 instructions, we get proper intermediate rounding, otherwise we
274 get extended precision results. */
275 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
276
277 #define BITS_BIG_ENDIAN 1
278 #define BYTES_BIG_ENDIAN 1
279 #define WORDS_BIG_ENDIAN 1
280
281 #define UNITS_PER_WORD 4
282
283 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
284 #define STACK_BOUNDARY 16
285 #define FUNCTION_BOUNDARY 16
286 #define EMPTY_FIELD_BOUNDARY 16
287
288 /* No data type wants to be aligned rounder than this.
289 Most published ABIs say that ints should be aligned on 16 bit
290 boundaries, but CPUs with 32-bit busses get better performance
291 aligned on 32-bit boundaries. ColdFires without a misalignment
292 module require 32-bit alignment. */
293 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
294
295 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
296
297 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
298
299 /* Define these to avoid dependence on meaning of `int'. */
300 #define WCHAR_TYPE "long int"
301 #define WCHAR_TYPE_SIZE 32
302
303 /* Maximum number of library IDs we permit with -mid-shared-library. */
304 #define MAX_LIBRARY_ID 255
305
306 \f
307 /* Standard register usage. */
308
309 /* For the m68k, we give the data registers numbers 0-7,
310 the address registers numbers 010-017 (8-15),
311 and the 68881 floating point registers numbers 020-027 (16-24).
312 We also have a fake `arg-pointer' register 030 (25) used for
313 register elimination. */
314 #define FIRST_PSEUDO_REGISTER 25
315
316 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
317 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
318
319 /* 1 for registers that have pervasive standard uses
320 and are not available for the register allocator.
321 On the m68k, only the stack pointer is such.
322 Our fake arg-pointer is obviously fixed as well. */
323 #define FIXED_REGISTERS \
324 {/* Data registers. */ \
325 0, 0, 0, 0, 0, 0, 0, 0, \
326 \
327 /* Address registers. */ \
328 0, 0, 0, 0, 0, 0, 0, 1, \
329 \
330 /* Floating point registers \
331 (if available). */ \
332 0, 0, 0, 0, 0, 0, 0, 0, \
333 \
334 /* Arg pointer. */ \
335 1 }
336
337 /* 1 for registers not available across function calls.
338 These must include the FIXED_REGISTERS and also any
339 registers that can be used without being saved.
340 The latter must include the registers where values are returned
341 and the register where structure-value addresses are passed.
342 Aside from that, you can include as many other registers as you like. */
343 #define CALL_USED_REGISTERS \
344 {/* Data registers. */ \
345 1, 1, 0, 0, 0, 0, 0, 0, \
346 \
347 /* Address registers. */ \
348 1, 1, 0, 0, 0, 0, 0, 1, \
349 \
350 /* Floating point registers \
351 (if available). */ \
352 1, 1, 0, 0, 0, 0, 0, 0, \
353 \
354 /* Arg pointer. */ \
355 1 }
356
357 #define REG_ALLOC_ORDER \
358 { /* d0/d1/a0/a1 */ \
359 0, 1, 8, 9, \
360 /* d2-d7 */ \
361 2, 3, 4, 5, 6, 7, \
362 /* a2-a7/arg */ \
363 10, 11, 12, 13, 14, 15, 24, \
364 /* fp0-fp7 */ \
365 16, 17, 18, 19, 20, 21, 22, 23\
366 }
367
368
369 /* Make sure everything's fine if we *don't* have a given processor.
370 This assumes that putting a register in fixed_regs will keep the
371 compiler's mitts completely off it. We don't bother to zero it out
372 of register classes. */
373 #define CONDITIONAL_REGISTER_USAGE \
374 { \
375 int i; \
376 HARD_REG_SET x; \
377 if (!TARGET_HARD_FLOAT) \
378 { \
379 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
380 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
381 if (TEST_HARD_REG_BIT (x, i)) \
382 fixed_regs[i] = call_used_regs[i] = 1; \
383 } \
384 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
385 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
386 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
387 }
388
389 /* On the m68k, ordinary registers hold 32 bits worth;
390 for the 68881 registers, a single register is always enough for
391 anything that can be stored in them at all. */
392 #define HARD_REGNO_NREGS(REGNO, MODE) \
393 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
394 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
395
396 /* A C expression that is nonzero if hard register NEW_REG can be
397 considered for use as a rename register for OLD_REG register. */
398
399 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
400 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
401
402 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
403 On the 68000, the cpu registers can hold any mode except bytes in
404 address registers, the 68881 registers can hold only SFmode or DFmode. */
405
406 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
407 m68k_regno_mode_ok ((REGNO), (MODE))
408
409 #define MODES_TIEABLE_P(MODE1, MODE2) \
410 (! TARGET_HARD_FLOAT \
411 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
412 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
413 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
414 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
415
416 /* Specify the registers used for certain standard purposes.
417 The values of these macros are register numbers. */
418
419 #define STACK_POINTER_REGNUM 15
420
421 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
422 ABI uses %a6 for shared library calls, therefore the frame
423 pointer is shifted to %a5 on this target. */
424 #define FRAME_POINTER_REGNUM 14
425
426 #define FRAME_POINTER_REQUIRED 0
427
428 /* Base register for access to arguments of the function.
429 * This isn't a hardware register. It will be eliminated to the
430 * stack pointer or frame pointer.
431 */
432 #define ARG_POINTER_REGNUM 24
433
434 #define STATIC_CHAIN_REGNUM 8
435
436 /* Register in which address to store a structure value
437 is passed to a function. */
438 #define M68K_STRUCT_VALUE_REGNUM 9
439
440 \f
441
442 /* The m68k has three kinds of registers, so eight classes would be
443 a complete set. One of them is not needed. */
444 enum reg_class {
445 NO_REGS, DATA_REGS,
446 ADDR_REGS, FP_REGS,
447 GENERAL_REGS, DATA_OR_FP_REGS,
448 ADDR_OR_FP_REGS, ALL_REGS,
449 LIM_REG_CLASSES };
450
451 #define N_REG_CLASSES (int) LIM_REG_CLASSES
452
453 #define REG_CLASS_NAMES \
454 { "NO_REGS", "DATA_REGS", \
455 "ADDR_REGS", "FP_REGS", \
456 "GENERAL_REGS", "DATA_OR_FP_REGS", \
457 "ADDR_OR_FP_REGS", "ALL_REGS" }
458
459 #define REG_CLASS_CONTENTS \
460 { \
461 {0x00000000}, /* NO_REGS */ \
462 {0x000000ff}, /* DATA_REGS */ \
463 {0x0100ff00}, /* ADDR_REGS */ \
464 {0x00ff0000}, /* FP_REGS */ \
465 {0x0100ffff}, /* GENERAL_REGS */ \
466 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
467 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
468 {0x01ffffff}, /* ALL_REGS */ \
469 }
470
471 extern enum reg_class regno_reg_class[];
472 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
473 #define INDEX_REG_CLASS GENERAL_REGS
474 #define BASE_REG_CLASS ADDR_REGS
475
476 /* We do a trick here to modify the effective constraints on the
477 machine description; we zorch the constraint letters that aren't
478 appropriate for a specific target. This allows us to guarantee
479 that a specific kind of register will not be used for a given target
480 without fiddling with the register classes above. */
481 #define REG_CLASS_FROM_LETTER(C) \
482 ((C) == 'a' ? ADDR_REGS : \
483 ((C) == 'd' ? DATA_REGS : \
484 ((C) == 'f' ? (TARGET_HARD_FLOAT ? \
485 FP_REGS : NO_REGS) : \
486 NO_REGS)))
487
488 /* For the m68k, `I' is used for the range 1 to 8
489 allowed as immediate shift counts and in addq.
490 `J' is used for the range of signed numbers that fit in 16 bits.
491 `K' is for numbers that moveq can't handle.
492 `L' is for range -8 to -1, range of values that can be added with subq.
493 `M' is for numbers that moveq+notb can't handle.
494 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
495 'O' is for 16 (for rotate using swap).
496 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
497 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
498 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
499 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
500 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
501 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
502 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
503 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
504 (C) == 'O' ? (VALUE) == 16 : \
505 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
506
507 /* "G" defines all of the floating constants that are *NOT* 68881
508 constants. This is so 68881 constants get reloaded and the
509 fpmovecr is used. */
510 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
511 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
512
513 /* `Q' means address register indirect addressing mode.
514 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
515 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
516 `U' is for register offset addressing. */
517 #define EXTRA_CONSTRAINT(OP,CODE) \
518 (((CODE) == 'S') \
519 ? (TARGET_PCREL \
520 && GET_CODE (OP) == MEM \
521 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
522 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
523 || GET_CODE (XEXP (OP, 0)) == CONST)) \
524 : \
525 (((CODE) == 'T') \
526 ? ( !TARGET_PCREL \
527 && (GET_CODE (OP) == SYMBOL_REF \
528 || GET_CODE (OP) == LABEL_REF \
529 || GET_CODE (OP) == CONST)) \
530 : \
531 (((CODE) == 'Q') \
532 ? (GET_CODE (OP) == MEM \
533 && GET_CODE (XEXP (OP, 0)) == REG) \
534 : \
535 (((CODE) == 'U') \
536 ? (GET_CODE (OP) == MEM \
537 && GET_CODE (XEXP (OP, 0)) == PLUS \
538 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
539 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
540 : \
541 0))))
542
543 /* On the m68k, use a data reg if possible when the
544 value is a constant in the range where moveq could be used
545 and we ensure that QImodes are reloaded into data regs. */
546 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
547 ((GET_CODE (X) == CONST_INT \
548 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
549 && (CLASS) != ADDR_REGS) \
550 ? DATA_REGS \
551 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
552 ? DATA_REGS \
553 : (GET_CODE (X) == CONST_DOUBLE \
554 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
555 ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
556 ? FP_REGS : NO_REGS) \
557 : (TARGET_PCREL \
558 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
559 || GET_CODE (X) == LABEL_REF)) \
560 ? ADDR_REGS \
561 : (CLASS))
562
563 /* Force QImode output reloads from subregs to be allocated to data regs,
564 since QImode stores from address regs are not supported. We make the
565 assumption that if the class is not ADDR_REGS, then it must be a superset
566 of DATA_REGS. */
567 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
568 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
569 ? DATA_REGS \
570 : (CLASS))
571
572 /* On the m68k, this is the size of MODE in words,
573 except in the FP regs, where a single reg is always enough. */
574 #define CLASS_MAX_NREGS(CLASS, MODE) \
575 ((CLASS) == FP_REGS ? 1 \
576 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
577
578 /* Moves between fp regs and other regs are two insns. */
579 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
580 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
581 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
582 ? 4 : 2)
583 \f
584 /* Stack layout; function entry, exit and calling. */
585
586 #define STACK_GROWS_DOWNWARD
587 #define FRAME_GROWS_DOWNWARD 1
588 #define STARTING_FRAME_OFFSET 0
589
590 /* On the 680x0, sp@- in a byte insn really pushes a word.
591 On the ColdFire, sp@- in a byte insn pushes just a byte. */
592 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
593
594 #define FIRST_PARM_OFFSET(FNDECL) 8
595
596 /* On the 68000, the RTS insn cannot pop anything.
597 On the 68010, the RTD insn may be used to pop them if the number
598 of args is fixed, but if the number is variable then the caller
599 must pop them all. RTD can't be used for library calls now
600 because the library is compiled with the Unix compiler.
601 Use of RTD is a selectable option, since it is incompatible with
602 standard Unix calling sequences. If the option is not selected,
603 the caller must always pop the args. */
604 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
605 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
606 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
607 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
608 == void_type_node))) \
609 ? (SIZE) : 0)
610
611 /* On the m68k the return value is always in D0. */
612 #define FUNCTION_VALUE(VALTYPE, FUNC) \
613 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
614
615 /* On the m68k the return value is always in D0. */
616 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
617
618 /* On the m68k, D0 is the only register used. */
619 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
620
621 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
622 more than one register.
623 XXX This macro is m68k specific and used only for m68kemb.h. */
624 #define NEEDS_UNTYPED_CALL 0
625
626 /* On the m68k, all arguments are usually pushed on the stack. */
627 #define FUNCTION_ARG_REGNO_P(N) 0
628 \f
629 /* On the m68k, this is a single integer, which is a number of bytes
630 of arguments scanned so far. */
631 #define CUMULATIVE_ARGS int
632
633 /* On the m68k, the offset starts at 0. */
634 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
635 ((CUM) = 0)
636
637 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
638 ((CUM) += ((MODE) != BLKmode \
639 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
640 : (int_size_in_bytes (TYPE) + 3) & ~3))
641
642 /* On the m68k all args are always pushed. */
643 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
644
645 #define FUNCTION_PROFILER(FILE, LABELNO) \
646 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
647
648 #define EXIT_IGNORE_STACK 1
649
650 /* Determine if the epilogue should be output as RTL.
651 You should override this if you define FUNCTION_EXTRA_EPILOGUE.
652
653 XXX This macro is m68k-specific and only used in m68k.md. */
654 #define USE_RETURN_INSN use_return_insn ()
655
656 /* Output assembler code for a block containing the constant parts
657 of a trampoline, leaving space for the variable parts.
658
659 On the m68k, the trampoline looks like this:
660 movl #STATIC,a0
661 jmp FUNCTION
662
663 WARNING: Targets that may run on 68040+ cpus must arrange for
664 the instruction cache to be flushed. Previous incarnations of
665 the m68k trampoline code attempted to get around this by either
666 using an out-of-line transfer function or pc-relative data, but
667 the fact remains that the code to jump to the transfer function
668 or the code to load the pc-relative data needs to be flushed
669 just as much as the "variable" portion of the trampoline.
670 Recognizing that a cache flush is going to be required anyway,
671 dispense with such notions and build a smaller trampoline.
672
673 Since more instructions are required to move a template into
674 place than to create it on the spot, don't use a template. */
675
676 #define TRAMPOLINE_SIZE 12
677 #define TRAMPOLINE_ALIGNMENT 16
678
679 /* Targets redefine this to invoke code to either flush the cache,
680 or enable stack execution (or both). */
681 #ifndef FINALIZE_TRAMPOLINE
682 #define FINALIZE_TRAMPOLINE(TRAMP)
683 #endif
684
685 /* We generate a two-instructions program at address TRAMP :
686 movea.l &CXT,%a0
687 jmp FNADDR */
688 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
689 { \
690 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
691 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
692 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
693 GEN_INT(0x4EF9)); \
694 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
695 FINALIZE_TRAMPOLINE(TRAMP); \
696 }
697
698 /* This is the library routine that is used to transfer control from the
699 trampoline to the actual nested function. It is defined for backward
700 compatibility, for linking with object code that used the old trampoline
701 definition.
702
703 A colon is used with no explicit operands to cause the template string
704 to be scanned for %-constructs.
705
706 The function name __transfer_from_trampoline is not actually used.
707 The function definition just permits use of "asm with operands"
708 (though the operand list is empty). */
709 #define TRANSFER_FROM_TRAMPOLINE \
710 void \
711 __transfer_from_trampoline () \
712 { \
713 register char *a0 asm ("%a0"); \
714 asm (GLOBAL_ASM_OP "___trampoline"); \
715 asm ("___trampoline:"); \
716 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
717 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
718 asm ("rts":); \
719 }
720 \f
721 /* There are two registers that can always be eliminated on the m68k.
722 The frame pointer and the arg pointer can be replaced by either the
723 hard frame pointer or to the stack pointer, depending upon the
724 circumstances. The hard frame pointer is not used before reload and
725 so it is not eligible for elimination. */
726 #define ELIMINABLE_REGS \
727 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
728 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
729 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
730
731 #define CAN_ELIMINATE(FROM, TO) \
732 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
733
734 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
735 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
736 \f
737 /* Addressing modes, and classification of registers for them. */
738
739 #define HAVE_POST_INCREMENT 1
740 #define HAVE_PRE_DECREMENT 1
741
742 /* Macros to check register numbers against specific register classes. */
743
744 #define REGNO_OK_FOR_INDEX_P(REGNO) \
745 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
746 #define REGNO_OK_FOR_BASE_P(REGNO) \
747 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
748 #define REGNO_OK_FOR_DATA_P(REGNO) \
749 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
750 #define REGNO_OK_FOR_FP_P(REGNO) \
751 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
752
753 /* Now macros that check whether X is a register and also,
754 strictly, whether it is in a specified class.
755
756 These macros are specific to the m68k, and may be used only
757 in code for printing assembler insns and in conditions for
758 define_optimization. */
759
760 /* 1 if X is a data register. */
761 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
762
763 /* 1 if X is an fp register. */
764 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
765
766 /* 1 if X is an address register */
767 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
768 \f
769
770 #define MAX_REGS_PER_ADDRESS 2
771
772 #define CONSTANT_ADDRESS_P(X) \
773 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
774 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
775 || GET_CODE (X) == HIGH)
776
777 /* Nonzero if the constant value X is a legitimate general operand.
778 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
779 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
780
781 #ifndef REG_OK_STRICT
782 #define PCREL_GENERAL_OPERAND_OK 0
783 #else
784 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
785 #endif
786
787 #define LEGITIMATE_PIC_OPERAND_P(X) \
788 (! symbolic_operand (X, VOIDmode) \
789 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
790 || PCREL_GENERAL_OPERAND_OK)
791
792 #ifndef REG_OK_STRICT
793
794 /* Nonzero if X is a hard reg that can be used as an index
795 or if it is a pseudo reg. */
796 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
797 /* Nonzero if X is a hard reg that can be used as a base reg
798 or if it is a pseudo reg. */
799 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
800
801 #else
802
803 /* Nonzero if X is a hard reg that can be used as an index. */
804 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
805 /* Nonzero if X is a hard reg that can be used as a base reg. */
806 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
807
808 #endif
809 \f
810 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
811 that is a valid memory address for an instruction.
812 The MODE argument is the machine mode for the MEM expression
813 that wants to use this address.
814
815 When generating PIC, an address involving a SYMBOL_REF is legitimate
816 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
817 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
818 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
819
820 Likewise for a LABEL_REF when generating PIC.
821
822 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
823
824 /* Allow SUBREG everywhere we allow REG. This results in better code. It
825 also makes function inlining work when inline functions are called with
826 arguments that are SUBREGs. */
827
828 #define LEGITIMATE_BASE_REG_P(X) \
829 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
830 || (GET_CODE (X) == SUBREG \
831 && GET_CODE (SUBREG_REG (X)) == REG \
832 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
833
834 #define INDIRECTABLE_1_ADDRESS_P(X) \
835 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
836 || LEGITIMATE_BASE_REG_P (X) \
837 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
838 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
839 || (GET_CODE (X) == PLUS \
840 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
841 && GET_CODE (XEXP (X, 1)) == CONST_INT \
842 && (TARGET_68020 \
843 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
844 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
845 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
846 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
847 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
848
849 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
850 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
851
852 /* Only labels on dispatch tables are valid for indexing from. */
853 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
854 { rtx temp; \
855 if (GET_CODE (X) == LABEL_REF \
856 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
857 && GET_CODE (temp) == JUMP_INSN \
858 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
859 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
860 goto ADDR; \
861 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
862
863 #define GO_IF_INDEXING(X, ADDR) \
864 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
865 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
866 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
867 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
868
869 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
870 { GO_IF_INDEXING (X, ADDR); \
871 if (GET_CODE (X) == PLUS) \
872 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
873 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
874 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
875 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
876 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
877 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
878
879 /* ColdFire/5200 does not allow HImode index registers. */
880 #define LEGITIMATE_INDEX_REG_P(X) \
881 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
882 || (! TARGET_COLDFIRE \
883 && GET_CODE (X) == SIGN_EXTEND \
884 && GET_CODE (XEXP (X, 0)) == REG \
885 && GET_MODE (XEXP (X, 0)) == HImode \
886 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
887 || (GET_CODE (X) == SUBREG \
888 && GET_CODE (SUBREG_REG (X)) == REG \
889 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
890
891 #define LEGITIMATE_INDEX_P(X) \
892 (LEGITIMATE_INDEX_REG_P (X) \
893 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
894 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
895 && GET_CODE (XEXP (X, 1)) == CONST_INT \
896 && (INTVAL (XEXP (X, 1)) == 2 \
897 || INTVAL (XEXP (X, 1)) == 4 \
898 || (INTVAL (XEXP (X, 1)) == 8 \
899 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))))
900
901 /* Coldfire FPU only accepts addressing modes 2-5 */
902 #define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
903 { if (LEGITIMATE_BASE_REG_P (X) \
904 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
905 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
906 || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
907 && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
908 && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
909 goto ADDR;}
910
911 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
912 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
913 { if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
914 { \
915 GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \
916 } \
917 else \
918 { \
919 GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
920 GO_IF_INDEXED_ADDRESS (X, ADDR); \
921 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
922 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
923 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
924 goto ADDR; \
925 }}
926
927 /* Don't call memory_address_noforce for the address to fetch
928 the switch offset. This address is ok as it stands (see above),
929 but memory_address_noforce would alter it. */
930 #define PIC_CASE_VECTOR_ADDRESS(index) index
931 \f
932 /* For the 68000, we handle X+REG by loading X into a register R and
933 using R+REG. R will go in an address reg and indexing will be used.
934 However, if REG is a broken-out memory address or multiplication,
935 nothing needs to be done because REG can certainly go in an address reg. */
936 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
937 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
938 { register int ch = (X) != (OLDX); \
939 if (GET_CODE (X) == PLUS) \
940 { int copied = 0; \
941 if (GET_CODE (XEXP (X, 0)) == MULT) \
942 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
943 if (GET_CODE (XEXP (X, 1)) == MULT) \
944 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
945 if (ch && GET_CODE (XEXP (X, 1)) == REG \
946 && GET_CODE (XEXP (X, 0)) == REG) \
947 { if (TARGET_COLDFIRE_FPU \
948 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
949 { COPY_ONCE (X); X = force_operand (X, 0);} \
950 goto WIN; } \
951 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
952 if (GET_CODE (XEXP (X, 0)) == REG \
953 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
954 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
955 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
956 { register rtx temp = gen_reg_rtx (Pmode); \
957 register rtx val = force_operand (XEXP (X, 1), 0); \
958 emit_move_insn (temp, val); \
959 COPY_ONCE (X); \
960 XEXP (X, 1) = temp; \
961 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
962 && GET_CODE (XEXP (X, 0)) == REG) \
963 X = force_operand (X, 0); \
964 goto WIN; } \
965 else if (GET_CODE (XEXP (X, 1)) == REG \
966 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
967 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
968 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
969 { register rtx temp = gen_reg_rtx (Pmode); \
970 register rtx val = force_operand (XEXP (X, 0), 0); \
971 emit_move_insn (temp, val); \
972 COPY_ONCE (X); \
973 XEXP (X, 0) = temp; \
974 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
975 && GET_CODE (XEXP (X, 1)) == REG) \
976 X = force_operand (X, 0); \
977 goto WIN; }}}
978
979 /* On the 68000, only predecrement and postincrement address depend thus
980 (the amount of decrement or increment being the length of the operand).
981 These are now treated generically in recog.c. */
982 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
983 \f
984 #define CASE_VECTOR_MODE HImode
985 #define CASE_VECTOR_PC_RELATIVE 1
986
987 #define DEFAULT_SIGNED_CHAR 1
988 #define MOVE_MAX 4
989 #define SLOW_BYTE_ACCESS 0
990
991 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
992
993 #define STORE_FLAG_VALUE (-1)
994
995 #define Pmode SImode
996 #define FUNCTION_MODE QImode
997
998 \f
999 /* Tell final.c how to eliminate redundant test instructions. */
1000
1001 /* Here we define machine-dependent flags and fields in cc_status
1002 (see `conditions.h'). */
1003
1004 /* Set if the cc value is actually in the 68881, so a floating point
1005 conditional branch must be output. */
1006 #define CC_IN_68881 04000
1007
1008 /* On the 68000, all the insns to store in an address register fail to
1009 set the cc's. However, in some cases these instructions can make it
1010 possibly invalid to use the saved cc's. In those cases we clear out
1011 some or all of the saved cc's so they won't be used. */
1012 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1013
1014 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1015 do { if (cc_prev_status.flags & CC_IN_68881) \
1016 return FLOAT; \
1017 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1018 return NO_OV; \
1019 return NORMAL; } while (0)
1020 \f
1021 /* Control the assembler format that we output. */
1022
1023 #define ASM_APP_ON "#APP\n"
1024 #define ASM_APP_OFF "#NO_APP\n"
1025 #define TEXT_SECTION_ASM_OP "\t.text"
1026 #define DATA_SECTION_ASM_OP "\t.data"
1027 #define GLOBAL_ASM_OP "\t.globl\t"
1028 #define REGISTER_PREFIX ""
1029 #define LOCAL_LABEL_PREFIX ""
1030 #define USER_LABEL_PREFIX "_"
1031 #define IMMEDIATE_PREFIX "#"
1032
1033 #define REGISTER_NAMES \
1034 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
1035 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
1036 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
1037 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
1038 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
1039 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
1040 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
1041 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
1042 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
1043
1044 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
1045
1046 /* Return a register name by index, handling %fp nicely.
1047 We don't replace %fp for targets that don't map it to %a6
1048 since it may confuse GAS. */
1049 #define M68K_REGNAME(r) ( \
1050 ((FRAME_POINTER_REGNUM == 14) \
1051 && ((r) == FRAME_POINTER_REGNUM) \
1052 && frame_pointer_needed) ? \
1053 M68K_FP_REG_NAME : reg_names[(r)])
1054
1055 /* On the Sun-3, the floating point registers have numbers
1056 18 to 25, not 16 to 23 as they do in the compiler. */
1057 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1058
1059 /* Before the prologue, RA is at 0(%sp). */
1060 #define INCOMING_RETURN_ADDR_RTX \
1061 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1062
1063 /* After the prologue, RA is at 4(AP) in the current frame. */
1064 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1065 ((COUNT) == 0 \
1066 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
1067 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1068
1069 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1070 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1071 Instead use the identity mapping. */
1072 #define DWARF_FRAME_REGNUM(REG) REG
1073
1074 /* Before the prologue, the top of the frame is at 4(%sp). */
1075 #define INCOMING_FRAME_SP_OFFSET 4
1076
1077 /* Describe how we implement __builtin_eh_return. */
1078 #define EH_RETURN_DATA_REGNO(N) \
1079 ((N) < 2 ? (N) : INVALID_REGNUM)
1080 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1081 #define EH_RETURN_HANDLER_RTX \
1082 gen_rtx_MEM (Pmode, \
1083 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1084 plus_constant (EH_RETURN_STACKADJ_RTX, \
1085 UNITS_PER_WORD)))
1086
1087 /* Select a format to encode pointers in exception handling data. CODE
1088 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1089 true if the symbol may be affected by dynamic relocations.
1090
1091 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
1092 a read-only text segment without imposing a fixed gap between the
1093 text and data segments. As a result, the text segment cannot refer
1094 to anything in the data segment, even in PC-relative form. Because
1095 .eh_frame refers to both code and data, it follows that .eh_frame
1096 must be in the data segment itself, and that the offset between
1097 .eh_frame and code will not be a link-time constant.
1098
1099 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
1100 | DW_EH_PE_indirect for all code references. However, gcc currently
1101 handles indirect references using a per-TU constant pool. This means
1102 that if a function and its eh_frame are removed by the linker, the
1103 eh_frame's indirect references to the removed function will not be
1104 removed, leading to an unresolved symbol error.
1105
1106 It isn't clear that any -msep-data or -mid-shared-library target
1107 would benefit from a read-only .eh_frame anyway. In particular,
1108 no known target that supports these options has a feature like
1109 PT_GNU_RELRO. Without any such feature to motivate them, indirect
1110 references would be unnecessary bloat, so we simply use an absolute
1111 pointer for code and global references. We still use pc-relative
1112 references to data, as this avoids a relocation. */
1113 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1114 (flag_pic \
1115 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
1116 && ((GLOBAL) || (CODE))) \
1117 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1118 : DW_EH_PE_absptr)
1119
1120 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1121 asm_fprintf (FILE, "%U%s", NAME)
1122
1123 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1124 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1125
1126 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1127 asm_fprintf (FILE, (MOTOROLA \
1128 ? "\tmove.l %s,-(%Rsp)\n" \
1129 : "\tmovel %s,%Rsp@-\n"), \
1130 reg_names[REGNO])
1131
1132 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1133 asm_fprintf (FILE, (MOTOROLA \
1134 ? "\tmove.l (%Rsp)+,%s\n" \
1135 : "\tmovel %Rsp@+,%s\n"), \
1136 reg_names[REGNO])
1137
1138 /* The m68k does not use absolute case-vectors, but we must define this macro
1139 anyway. */
1140 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1141 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1142
1143 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1144 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1145
1146 /* We don't have a way to align to more than a two-byte boundary, so do the
1147 best we can and don't complain. */
1148 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1149 if ((LOG) >= 1) \
1150 fprintf (FILE, "\t.even\n");
1151
1152 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1153 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1154
1155 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1156 ( fputs (".comm ", (FILE)), \
1157 assemble_name ((FILE), (NAME)), \
1158 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1159
1160 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1161 ( fputs (".lcomm ", (FILE)), \
1162 assemble_name ((FILE), (NAME)), \
1163 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1164
1165 /* Output a float value (represented as a C double) as an immediate operand.
1166 This macro is m68k-specific. */
1167 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1168 do { \
1169 if (CODE == 'f') \
1170 { \
1171 char dstr[30]; \
1172 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1173 asm_fprintf ((FILE), "%I0r%s", dstr); \
1174 } \
1175 else \
1176 { \
1177 long l; \
1178 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1179 asm_fprintf ((FILE), "%I0x%lx", l); \
1180 } \
1181 } while (0)
1182
1183 /* Output a double value (represented as a C double) as an immediate operand.
1184 This macro is m68k-specific. */
1185 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1186 do { char dstr[30]; \
1187 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1188 asm_fprintf (FILE, "%I0r%s", dstr); \
1189 } while (0)
1190
1191 /* Note, long double immediate operands are not actually
1192 generated by m68k.md. */
1193 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1194 do { char dstr[30]; \
1195 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1196 asm_fprintf (FILE, "%I0r%s", dstr); \
1197 } while (0)
1198
1199 /* On the 68000, we use several CODE characters:
1200 '.' for dot needed in Motorola-style opcode names.
1201 '-' for an operand pushing on the stack:
1202 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1203 '+' for an operand pushing on the stack:
1204 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1205 '@' for a reference to the top word on the stack:
1206 sp@, (sp) or (%sp) depending on the style of syntax.
1207 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1208 but & in SGS syntax).
1209 '!' for the fpcr register (used in some float-to-fixed conversions).
1210 '$' for the letter `s' in an op code, but only on the 68040.
1211 '&' for the letter `d' in an op code, but only on the 68040.
1212 '/' for register prefix needed by longlong.h.
1213
1214 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1215 'd' to force memory addressing to be absolute, not relative.
1216 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1217 'o' for operands to go directly to output_operand_address (bypassing
1218 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1219 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1220 or print pair of registers as rx:ry. */
1221
1222 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1223 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1224 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1225 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1226
1227
1228 /* See m68k.c for the m68k specific codes. */
1229 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1230
1231 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1232
1233 /* Values used in the MICROARCH argument to M68K_DEVICE. */
1234 enum uarch_type
1235 {
1236 u68000,
1237 u68010,
1238 u68020,
1239 u68020_40,
1240 u68020_60,
1241 u68030,
1242 u68040,
1243 u68060,
1244 ucpu32,
1245 ucfv2,
1246 ucfv3,
1247 ucfv4,
1248 ucfv4e,
1249 ucfv5,
1250 unk_arch
1251 };
1252
1253 /* An enumeration of all supported target devices. */
1254 enum target_device
1255 {
1256 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1257 ENUM_VALUE,
1258 #include "m68k-devices.def"
1259 #undef M68K_DEVICE
1260 unk_device
1261 };
1262
1263 enum fpu_type
1264 {
1265 FPUTYPE_NONE,
1266 FPUTYPE_68881,
1267 FPUTYPE_COLDFIRE
1268 };
1269
1270 /* Variables in m68k.c; see there for details. */
1271 extern const char *m68k_library_id_string;
1272 extern int m68k_last_compare_had_fp_operands;
1273 extern enum target_device m68k_cpu;
1274 extern enum uarch_type m68k_tune;
1275 extern enum fpu_type m68k_fpu;
1276 extern unsigned int m68k_cpu_flags;
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