1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2285 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2286 (set_attr "pa_combine_type" "addmove")
2287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2290 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2291 (match_operand:SI 1 "register_operand" "f"))]
2293 && !TARGET_DISABLE_INDEXING
2294 && reload_completed"
2296 [(set_attr "type" "fpstore")
2297 (set_attr "pa_combine_type" "addmove")
2298 (set_attr "length" "4")])
2300 ; Rewrite RTL using an indexed store. This will allow the insn that
2301 ; computes the address to be deleted if the register it sets is dead.
2303 [(set (match_operand:SI 0 "register_operand" "")
2304 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2306 (match_operand:SI 2 "register_operand" "")))
2307 (set (mem:SI (match_dup 0))
2308 (match_operand:SI 3 "register_operand" ""))]
2310 && REG_OK_FOR_BASE_P (operands[2])
2311 && FP_REGNO_P (REGNO (operands[3]))"
2312 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2314 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2319 [(set (match_operand:SI 0 "register_operand" "")
2320 (plus:SI (match_operand:SI 2 "register_operand" "")
2321 (mult:SI (match_operand:SI 1 "register_operand" "")
2323 (set (mem:SI (match_dup 0))
2324 (match_operand:SI 3 "register_operand" ""))]
2326 && REG_OK_FOR_BASE_P (operands[2])
2327 && FP_REGNO_P (REGNO (operands[3]))"
2328 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2330 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2335 [(set (match_operand:DI 0 "register_operand" "")
2336 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2338 (match_operand:DI 2 "register_operand" "")))
2339 (set (mem:SI (match_dup 0))
2340 (match_operand:SI 3 "register_operand" ""))]
2343 && REG_OK_FOR_BASE_P (operands[2])
2344 && FP_REGNO_P (REGNO (operands[3]))"
2345 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2347 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2352 [(set (match_operand:DI 0 "register_operand" "")
2353 (plus:DI (match_operand:DI 2 "register_operand" "")
2354 (mult:DI (match_operand:DI 1 "register_operand" "")
2356 (set (mem:SI (match_dup 0))
2357 (match_operand:SI 3 "register_operand" ""))]
2360 && REG_OK_FOR_BASE_P (operands[2])
2361 && FP_REGNO_P (REGNO (operands[3]))"
2362 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2364 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2369 [(set (match_operand:SI 0 "register_operand" "")
2370 (plus:SI (match_operand:SI 1 "register_operand" "")
2371 (match_operand:SI 2 "register_operand" "")))
2372 (set (mem:SI (match_dup 0))
2373 (match_operand:SI 3 "register_operand" ""))]
2375 && REG_OK_FOR_BASE_P (operands[1])
2376 && (TARGET_NO_SPACE_REGS
2377 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2378 && FP_REGNO_P (REGNO (operands[3]))"
2379 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2381 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2385 [(set (match_operand:SI 0 "register_operand" "")
2386 (plus:SI (match_operand:SI 1 "register_operand" "")
2387 (match_operand:SI 2 "register_operand" "")))
2388 (set (mem:SI (match_dup 0))
2389 (match_operand:SI 3 "register_operand" ""))]
2391 && REG_OK_FOR_BASE_P (operands[2])
2392 && (TARGET_NO_SPACE_REGS
2393 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2394 && FP_REGNO_P (REGNO (operands[3]))"
2395 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2397 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2401 [(set (match_operand:DI 0 "register_operand" "")
2402 (plus:DI (match_operand:DI 1 "register_operand" "")
2403 (match_operand:DI 2 "register_operand" "")))
2404 (set (mem:SI (match_dup 0))
2405 (match_operand:SI 3 "register_operand" ""))]
2408 && REG_OK_FOR_BASE_P (operands[1])
2409 && (TARGET_NO_SPACE_REGS
2410 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2411 && FP_REGNO_P (REGNO (operands[3]))"
2412 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2414 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2418 [(set (match_operand:DI 0 "register_operand" "")
2419 (plus:DI (match_operand:DI 1 "register_operand" "")
2420 (match_operand:DI 2 "register_operand" "")))
2421 (set (mem:SI (match_dup 0))
2422 (match_operand:SI 3 "register_operand" ""))]
2425 && REG_OK_FOR_BASE_P (operands[2])
2426 && (TARGET_NO_SPACE_REGS
2427 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2428 && FP_REGNO_P (REGNO (operands[3]))"
2429 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2431 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2435 [(set (match_operand:SI 0 "move_dest_operand"
2436 "=r,r,r,r,r,r,Q,!*q")
2437 (match_operand:SI 1 "move_src_operand"
2438 "A,r,J,N,K,RQ,rM,!rM"))]
2439 "(register_operand (operands[0], SImode)
2440 || reg_or_0_operand (operands[1], SImode))
2441 && TARGET_SOFT_FLOAT"
2447 {zdepi|depwi,z} %Z1,%0
2451 [(set_attr "type" "load,move,move,move,move,load,store,move")
2452 (set_attr "pa_combine_type" "addmove")
2453 (set_attr "length" "4,4,4,4,4,4,4,4")])
2455 ;; Load or store with base-register modification.
2457 [(set (match_operand:SI 0 "register_operand" "=r")
2458 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2459 (match_operand:DI 2 "int5_operand" "L"))))
2461 (plus:DI (match_dup 1) (match_dup 2)))]
2464 [(set_attr "type" "load")
2465 (set_attr "length" "4")])
2467 ; And a zero extended variant.
2469 [(set (match_operand:DI 0 "register_operand" "=r")
2470 (zero_extend:DI (mem:SI
2472 (match_operand:DI 1 "register_operand" "+r")
2473 (match_operand:DI 2 "int5_operand" "L")))))
2475 (plus:DI (match_dup 1) (match_dup 2)))]
2478 [(set_attr "type" "load")
2479 (set_attr "length" "4")])
2481 (define_expand "pre_load"
2482 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2483 (mem (plus (match_operand 1 "register_operand" "")
2484 (match_operand 2 "pre_cint_operand" ""))))
2486 (plus (match_dup 1) (match_dup 2)))])]
2492 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2495 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2499 (define_insn "pre_ldw"
2500 [(set (match_operand:SI 0 "register_operand" "=r")
2501 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2502 (match_operand:SI 2 "pre_cint_operand" ""))))
2504 (plus:SI (match_dup 1) (match_dup 2)))]
2508 if (INTVAL (operands[2]) < 0)
2509 return \"{ldwm|ldw,mb} %2(%1),%0\";
2510 return \"{ldws|ldw},mb %2(%1),%0\";
2512 [(set_attr "type" "load")
2513 (set_attr "length" "4")])
2515 (define_insn "pre_ldd"
2516 [(set (match_operand:DI 0 "register_operand" "=r")
2517 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2518 (match_operand:DI 2 "pre_cint_operand" ""))))
2520 (plus:DI (match_dup 1) (match_dup 2)))]
2523 [(set_attr "type" "load")
2524 (set_attr "length" "4")])
2527 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2528 (match_operand:SI 1 "pre_cint_operand" "")))
2529 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2531 (plus:SI (match_dup 0) (match_dup 1)))]
2535 if (INTVAL (operands[1]) < 0)
2536 return \"{stwm|stw,mb} %r2,%1(%0)\";
2537 return \"{stws|stw},mb %r2,%1(%0)\";
2539 [(set_attr "type" "store")
2540 (set_attr "length" "4")])
2543 [(set (match_operand:SI 0 "register_operand" "=r")
2544 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2546 (plus:SI (match_dup 1)
2547 (match_operand:SI 2 "post_cint_operand" "")))]
2551 if (INTVAL (operands[2]) > 0)
2552 return \"{ldwm|ldw,ma} %2(%1),%0\";
2553 return \"{ldws|ldw},ma %2(%1),%0\";
2555 [(set_attr "type" "load")
2556 (set_attr "length" "4")])
2558 (define_expand "post_store"
2559 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2560 (match_operand 1 "reg_or_0_operand" ""))
2563 (match_operand 2 "post_cint_operand" "")))])]
2569 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2572 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2576 (define_insn "post_stw"
2577 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2578 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2580 (plus:SI (match_dup 0)
2581 (match_operand:SI 2 "post_cint_operand" "")))]
2585 if (INTVAL (operands[2]) > 0)
2586 return \"{stwm|stw,ma} %r1,%2(%0)\";
2587 return \"{stws|stw},ma %r1,%2(%0)\";
2589 [(set_attr "type" "store")
2590 (set_attr "length" "4")])
2592 (define_insn "post_std"
2593 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2594 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2596 (plus:DI (match_dup 0)
2597 (match_operand:DI 2 "post_cint_operand" "")))]
2600 [(set_attr "type" "store")
2601 (set_attr "length" "4")])
2603 ;; For loading the address of a label while generating PIC code.
2604 ;; Note since this pattern can be created at reload time (via movsi), all
2605 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2607 [(set (match_operand 0 "pmode_register_operand" "=a")
2608 (match_operand 1 "pic_label_operand" ""))]
2614 xoperands[0] = operands[0];
2615 xoperands[1] = operands[1];
2616 xoperands[2] = gen_label_rtx ();
2618 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2619 CODE_LABEL_NUMBER (xoperands[2]));
2620 output_asm_insn (\"mfia %0\", xoperands);
2622 /* If we're trying to load the address of a label that happens to be
2623 close, then we can use a shorter sequence. */
2624 if (GET_CODE (operands[1]) == LABEL_REF
2625 && INSN_ADDRESSES_SET_P ()
2626 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2627 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2628 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2631 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2632 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2636 [(set_attr "type" "multi")
2637 (set_attr "length" "12")]) ; 8 or 12
2640 [(set (match_operand 0 "pmode_register_operand" "=a")
2641 (match_operand 1 "pic_label_operand" ""))]
2647 xoperands[0] = operands[0];
2648 xoperands[1] = operands[1];
2649 xoperands[2] = gen_label_rtx ();
2651 output_asm_insn (\"bl .+8,%0\", xoperands);
2652 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2653 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2654 CODE_LABEL_NUMBER (xoperands[2]));
2656 /* If we're trying to load the address of a label that happens to be
2657 close, then we can use a shorter sequence. */
2658 if (GET_CODE (operands[1]) == LABEL_REF
2659 && INSN_ADDRESSES_SET_P ()
2660 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2661 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2662 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2665 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2666 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2670 [(set_attr "type" "multi")
2671 (set_attr "length" "16")]) ; 12 or 16
2674 [(set (match_operand:SI 0 "register_operand" "=a")
2675 (plus:SI (match_operand:SI 1 "register_operand" "r")
2676 (high:SI (match_operand 2 "" ""))))]
2677 "symbolic_operand (operands[2], Pmode)
2678 && ! function_label_operand (operands[2], Pmode)
2681 [(set_attr "type" "binary")
2682 (set_attr "length" "4")])
2685 [(set (match_operand:DI 0 "register_operand" "=a")
2686 (plus:DI (match_operand:DI 1 "register_operand" "r")
2687 (high:DI (match_operand 2 "" ""))))]
2688 "symbolic_operand (operands[2], Pmode)
2689 && ! function_label_operand (operands[2], Pmode)
2693 [(set_attr "type" "binary")
2694 (set_attr "length" "4")])
2696 ;; Always use addil rather than ldil;add sequences. This allows the
2697 ;; HP linker to eliminate the dp relocation if the symbolic operand
2698 ;; lives in the TEXT space.
2700 [(set (match_operand:SI 0 "register_operand" "=a")
2701 (high:SI (match_operand 1 "" "")))]
2702 "symbolic_operand (operands[1], Pmode)
2703 && ! function_label_operand (operands[1], Pmode)
2704 && ! read_only_operand (operands[1], Pmode)
2708 if (TARGET_LONG_LOAD_STORE)
2709 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2711 return \"addil LR'%H1,%%r27\";
2713 [(set_attr "type" "binary")
2714 (set (attr "length")
2715 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2720 ;; This is for use in the prologue/epilogue code. We need it
2721 ;; to add large constants to a stack pointer or frame pointer.
2722 ;; Because of the additional %r1 pressure, we probably do not
2723 ;; want to use this in general code, so make it available
2724 ;; only after reload.
2726 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2727 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2728 (high:SI (match_operand 2 "const_int_operand" ""))))]
2732 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2733 [(set_attr "type" "binary,binary")
2734 (set_attr "length" "4,8")])
2737 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2738 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2739 (high:DI (match_operand 2 "const_int_operand" ""))))]
2740 "reload_completed && TARGET_64BIT"
2743 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2744 [(set_attr "type" "binary,binary")
2745 (set_attr "length" "4,8")])
2748 [(set (match_operand:SI 0 "register_operand" "=r")
2749 (high:SI (match_operand 1 "" "")))]
2750 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2751 && !is_function_label_plus_const (operands[1])"
2754 if (symbolic_operand (operands[1], Pmode))
2755 return \"ldil LR'%H1,%0\";
2757 return \"ldil L'%G1,%0\";
2759 [(set_attr "type" "move")
2760 (set_attr "length" "4")])
2763 [(set (match_operand:DI 0 "register_operand" "=r")
2764 (high:DI (match_operand 1 "const_int_operand" "")))]
2767 [(set_attr "type" "move")
2768 (set_attr "length" "4")])
2771 [(set (match_operand:DI 0 "register_operand" "=r")
2772 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2773 (match_operand:DI 2 "const_int_operand" "i")))]
2776 [(set_attr "type" "move")
2777 (set_attr "length" "4")])
2780 [(set (match_operand:SI 0 "register_operand" "=r")
2781 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2782 (match_operand:SI 2 "immediate_operand" "i")))]
2783 "!is_function_label_plus_const (operands[2])"
2786 if (flag_pic && symbolic_operand (operands[2], Pmode))
2788 else if (symbolic_operand (operands[2], Pmode))
2789 return \"ldo RR'%G2(%1),%0\";
2791 return \"ldo R'%G2(%1),%0\";
2793 [(set_attr "type" "move")
2794 (set_attr "length" "4")])
2796 ;; Now that a symbolic_address plus a constant is broken up early
2797 ;; in the compilation phase (for better CSE) we need a special
2798 ;; combiner pattern to load the symbolic address plus the constant
2799 ;; in only 2 instructions. (For cases where the symbolic address
2800 ;; was not a common subexpression.)
2802 [(set (match_operand:SI 0 "register_operand" "")
2803 (match_operand:SI 1 "symbolic_operand" ""))
2804 (clobber (match_operand:SI 2 "register_operand" ""))]
2805 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2806 [(set (match_dup 2) (high:SI (match_dup 1)))
2807 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2810 ;; hppa_legitimize_address goes to a great deal of trouble to
2811 ;; create addresses which use indexing. In some cases, this
2812 ;; is a lose because there isn't any store instructions which
2813 ;; allow indexed addresses (with integer register source).
2815 ;; These define_splits try to turn a 3 insn store into
2816 ;; a 2 insn store with some creative RTL rewriting.
2818 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2819 (match_operand:SI 1 "shadd_operand" ""))
2820 (plus:SI (match_operand:SI 2 "register_operand" "")
2821 (match_operand:SI 3 "const_int_operand" ""))))
2822 (match_operand:SI 4 "register_operand" ""))
2823 (clobber (match_operand:SI 5 "register_operand" ""))]
2825 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2827 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2831 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2832 (match_operand:SI 1 "shadd_operand" ""))
2833 (plus:SI (match_operand:SI 2 "register_operand" "")
2834 (match_operand:SI 3 "const_int_operand" ""))))
2835 (match_operand:HI 4 "register_operand" ""))
2836 (clobber (match_operand:SI 5 "register_operand" ""))]
2838 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2840 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2844 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2845 (match_operand:SI 1 "shadd_operand" ""))
2846 (plus:SI (match_operand:SI 2 "register_operand" "")
2847 (match_operand:SI 3 "const_int_operand" ""))))
2848 (match_operand:QI 4 "register_operand" ""))
2849 (clobber (match_operand:SI 5 "register_operand" ""))]
2851 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2853 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2856 (define_expand "movhi"
2857 [(set (match_operand:HI 0 "general_operand" "")
2858 (match_operand:HI 1 "general_operand" ""))]
2862 if (emit_move_sequence (operands, HImode, 0))
2867 [(set (match_operand:HI 0 "move_dest_operand"
2868 "=r,r,r,r,r,Q,!*q,!*f")
2869 (match_operand:HI 1 "move_src_operand"
2870 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2871 "register_operand (operands[0], HImode)
2872 || reg_or_0_operand (operands[1], HImode)"
2877 {zdepi|depwi,z} %Z1,%0
2882 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2883 (set_attr "pa_combine_type" "addmove")
2884 (set_attr "length" "4,4,4,4,4,4,4,4")])
2887 [(set (match_operand:HI 0 "register_operand" "=r")
2888 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2889 (match_operand:SI 2 "int5_operand" "L"))))
2891 (plus:SI (match_dup 1) (match_dup 2)))]
2893 "{ldhs|ldh},mb %2(%1),%0"
2894 [(set_attr "type" "load")
2895 (set_attr "length" "4")])
2898 [(set (match_operand:HI 0 "register_operand" "=r")
2899 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2900 (match_operand:DI 2 "int5_operand" "L"))))
2902 (plus:DI (match_dup 1) (match_dup 2)))]
2905 [(set_attr "type" "load")
2906 (set_attr "length" "4")])
2908 ; And a zero extended variant.
2910 [(set (match_operand:DI 0 "register_operand" "=r")
2911 (zero_extend:DI (mem:HI
2913 (match_operand:DI 1 "register_operand" "+r")
2914 (match_operand:DI 2 "int5_operand" "L")))))
2916 (plus:DI (match_dup 1) (match_dup 2)))]
2919 [(set_attr "type" "load")
2920 (set_attr "length" "4")])
2923 [(set (match_operand:SI 0 "register_operand" "=r")
2924 (zero_extend:SI (mem:HI
2926 (match_operand:SI 1 "register_operand" "+r")
2927 (match_operand:SI 2 "int5_operand" "L")))))
2929 (plus:SI (match_dup 1) (match_dup 2)))]
2931 "{ldhs|ldh},mb %2(%1),%0"
2932 [(set_attr "type" "load")
2933 (set_attr "length" "4")])
2936 [(set (match_operand:SI 0 "register_operand" "=r")
2937 (zero_extend:SI (mem:HI
2939 (match_operand:DI 1 "register_operand" "+r")
2940 (match_operand:DI 2 "int5_operand" "L")))))
2942 (plus:DI (match_dup 1) (match_dup 2)))]
2945 [(set_attr "type" "load")
2946 (set_attr "length" "4")])
2949 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2950 (match_operand:SI 1 "int5_operand" "L")))
2951 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2953 (plus:SI (match_dup 0) (match_dup 1)))]
2955 "{sths|sth},mb %r2,%1(%0)"
2956 [(set_attr "type" "store")
2957 (set_attr "length" "4")])
2960 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2961 (match_operand:DI 1 "int5_operand" "L")))
2962 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2964 (plus:DI (match_dup 0) (match_dup 1)))]
2967 [(set_attr "type" "store")
2968 (set_attr "length" "4")])
2971 [(set (match_operand:HI 0 "register_operand" "=r")
2972 (plus:HI (match_operand:HI 1 "register_operand" "r")
2973 (match_operand 2 "const_int_operand" "J")))]
2976 [(set_attr "type" "binary")
2977 (set_attr "pa_combine_type" "addmove")
2978 (set_attr "length" "4")])
2980 (define_expand "movqi"
2981 [(set (match_operand:QI 0 "general_operand" "")
2982 (match_operand:QI 1 "general_operand" ""))]
2986 if (emit_move_sequence (operands, QImode, 0))
2991 [(set (match_operand:QI 0 "move_dest_operand"
2992 "=r,r,r,r,r,Q,!*q,!*f")
2993 (match_operand:QI 1 "move_src_operand"
2994 "r,J,N,K,RQ,rM,!rM,!*fM"))]
2995 "register_operand (operands[0], QImode)
2996 || reg_or_0_operand (operands[1], QImode)"
3001 {zdepi|depwi,z} %Z1,%0
3006 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
3007 (set_attr "pa_combine_type" "addmove")
3008 (set_attr "length" "4,4,4,4,4,4,4,4")])
3011 [(set (match_operand:QI 0 "register_operand" "=r")
3012 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3013 (match_operand:SI 2 "int5_operand" "L"))))
3014 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3016 "{ldbs|ldb},mb %2(%1),%0"
3017 [(set_attr "type" "load")
3018 (set_attr "length" "4")])
3021 [(set (match_operand:QI 0 "register_operand" "=r")
3022 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3023 (match_operand:DI 2 "int5_operand" "L"))))
3024 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3027 [(set_attr "type" "load")
3028 (set_attr "length" "4")])
3030 ; Now the same thing with zero extensions.
3032 [(set (match_operand:DI 0 "register_operand" "=r")
3033 (zero_extend:DI (mem:QI (plus:DI
3034 (match_operand:DI 1 "register_operand" "+r")
3035 (match_operand:DI 2 "int5_operand" "L")))))
3036 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3039 [(set_attr "type" "load")
3040 (set_attr "length" "4")])
3043 [(set (match_operand:SI 0 "register_operand" "=r")
3044 (zero_extend:SI (mem:QI (plus:SI
3045 (match_operand:SI 1 "register_operand" "+r")
3046 (match_operand:SI 2 "int5_operand" "L")))))
3047 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3049 "{ldbs|ldb},mb %2(%1),%0"
3050 [(set_attr "type" "load")
3051 (set_attr "length" "4")])
3054 [(set (match_operand:SI 0 "register_operand" "=r")
3055 (zero_extend:SI (mem:QI (plus:DI
3056 (match_operand:DI 1 "register_operand" "+r")
3057 (match_operand:DI 2 "int5_operand" "L")))))
3058 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3061 [(set_attr "type" "load")
3062 (set_attr "length" "4")])
3065 [(set (match_operand:HI 0 "register_operand" "=r")
3066 (zero_extend:HI (mem:QI (plus:SI
3067 (match_operand:SI 1 "register_operand" "+r")
3068 (match_operand:SI 2 "int5_operand" "L")))))
3069 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3071 "{ldbs|ldb},mb %2(%1),%0"
3072 [(set_attr "type" "load")
3073 (set_attr "length" "4")])
3076 [(set (match_operand:HI 0 "register_operand" "=r")
3077 (zero_extend:HI (mem:QI (plus:DI
3078 (match_operand:DI 1 "register_operand" "+r")
3079 (match_operand:DI 2 "int5_operand" "L")))))
3080 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3083 [(set_attr "type" "load")
3084 (set_attr "length" "4")])
3087 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3088 (match_operand:SI 1 "int5_operand" "L")))
3089 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3091 (plus:SI (match_dup 0) (match_dup 1)))]
3093 "{stbs|stb},mb %r2,%1(%0)"
3094 [(set_attr "type" "store")
3095 (set_attr "length" "4")])
3098 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3099 (match_operand:DI 1 "int5_operand" "L")))
3100 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3102 (plus:DI (match_dup 0) (match_dup 1)))]
3105 [(set_attr "type" "store")
3106 (set_attr "length" "4")])
3108 ;; The definition of this insn does not really explain what it does,
3109 ;; but it should suffice that anything generated as this insn will be
3110 ;; recognized as a movstrsi operation, and that it will not successfully
3111 ;; combine with anything.
3112 (define_expand "movstrsi"
3113 [(parallel [(set (match_operand:BLK 0 "" "")
3114 (match_operand:BLK 1 "" ""))
3115 (clobber (match_dup 4))
3116 (clobber (match_dup 5))
3117 (clobber (match_dup 6))
3118 (clobber (match_dup 7))
3119 (clobber (match_dup 8))
3120 (use (match_operand:SI 2 "arith_operand" ""))
3121 (use (match_operand:SI 3 "const_int_operand" ""))])]
3122 "!TARGET_64BIT && optimize > 0"
3127 /* HP provides very fast block move library routine for the PA;
3128 this routine includes:
3130 4x4 byte at a time block moves,
3131 1x4 byte at a time with alignment checked at runtime with
3132 attempts to align the source and destination as needed
3135 With that in mind, here's the heuristics to try and guess when
3136 the inlined block move will be better than the library block
3139 If the size isn't constant, then always use the library routines.
3141 If the size is large in respect to the known alignment, then use
3142 the library routines.
3144 If the size is small in respect to the known alignment, then open
3145 code the copy (since that will lead to better scheduling).
3147 Else use the block move pattern. */
3149 /* Undetermined size, use the library routine. */
3150 if (GET_CODE (operands[2]) != CONST_INT)
3153 size = INTVAL (operands[2]);
3154 align = INTVAL (operands[3]);
3155 align = align > 4 ? 4 : align;
3157 /* If size/alignment is large, then use the library routines. */
3158 if (size / align > 16)
3161 /* This does happen, but not often enough to worry much about. */
3162 if (size / align < MOVE_RATIO)
3165 /* Fall through means we're going to use our block move pattern. */
3167 = replace_equiv_address (operands[0],
3168 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3170 = replace_equiv_address (operands[1],
3171 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3172 operands[4] = gen_reg_rtx (SImode);
3173 operands[5] = gen_reg_rtx (SImode);
3174 operands[6] = gen_reg_rtx (SImode);
3175 operands[7] = gen_reg_rtx (SImode);
3176 operands[8] = gen_reg_rtx (SImode);
3179 ;; The operand constraints are written like this to support both compile-time
3180 ;; and run-time determined byte counts. The expander and output_block_move
3181 ;; only support compile-time determined counts at this time.
3183 ;; If the count is run-time determined, the register with the byte count
3184 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3186 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3187 ;; broke this semantic for pseudo registers. We can't use match_scratch
3188 ;; as this requires two registers in the class R1_REGS when the MEMs for
3189 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3190 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3191 ;; respectively. We then split or peephole optimize after reload.
3192 (define_insn "movstrsi_prereload"
3193 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3194 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3195 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3196 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3197 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3198 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3199 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3200 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3201 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3204 [(set_attr "type" "multi,multi")])
3207 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3208 (match_operand:BLK 1 "memory_operand" ""))
3209 (clobber (match_operand:SI 2 "register_operand" ""))
3210 (clobber (match_operand:SI 3 "register_operand" ""))
3211 (clobber (match_operand:SI 6 "register_operand" ""))
3212 (clobber (match_operand:SI 7 "register_operand" ""))
3213 (clobber (match_operand:SI 8 "register_operand" ""))
3214 (use (match_operand:SI 4 "arith_operand" ""))
3215 (use (match_operand:SI 5 "const_int_operand" ""))])]
3216 "!TARGET_64BIT && reload_completed && !flag_peephole2
3217 && GET_CODE (operands[0]) == MEM
3218 && register_operand (XEXP (operands[0], 0), SImode)
3219 && GET_CODE (operands[1]) == MEM
3220 && register_operand (XEXP (operands[1], 0), SImode)"
3221 [(set (match_dup 7) (match_dup 9))
3222 (set (match_dup 8) (match_dup 10))
3223 (parallel [(set (match_dup 0) (match_dup 1))
3224 (clobber (match_dup 2))
3225 (clobber (match_dup 3))
3226 (clobber (match_dup 6))
3227 (clobber (match_dup 7))
3228 (clobber (match_dup 8))
3234 operands[9] = XEXP (operands[0], 0);
3235 operands[10] = XEXP (operands[1], 0);
3236 operands[0] = replace_equiv_address (operands[0], operands[7]);
3237 operands[1] = replace_equiv_address (operands[1], operands[8]);
3241 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3242 (match_operand:BLK 1 "memory_operand" ""))
3243 (clobber (match_operand:SI 2 "register_operand" ""))
3244 (clobber (match_operand:SI 3 "register_operand" ""))
3245 (clobber (match_operand:SI 6 "register_operand" ""))
3246 (clobber (match_operand:SI 7 "register_operand" ""))
3247 (clobber (match_operand:SI 8 "register_operand" ""))
3248 (use (match_operand:SI 4 "arith_operand" ""))
3249 (use (match_operand:SI 5 "const_int_operand" ""))])]
3251 && GET_CODE (operands[0]) == MEM
3252 && register_operand (XEXP (operands[0], 0), SImode)
3253 && GET_CODE (operands[1]) == MEM
3254 && register_operand (XEXP (operands[1], 0), SImode)"
3255 [(parallel [(set (match_dup 0) (match_dup 1))
3256 (clobber (match_dup 2))
3257 (clobber (match_dup 3))
3258 (clobber (match_dup 6))
3259 (clobber (match_dup 7))
3260 (clobber (match_dup 8))
3266 rtx addr = XEXP (operands[0], 0);
3267 if (dead_or_set_p (curr_insn, addr))
3271 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3272 operands[0] = replace_equiv_address (operands[0], operands[7]);
3275 addr = XEXP (operands[1], 0);
3276 if (dead_or_set_p (curr_insn, addr))
3280 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3281 operands[1] = replace_equiv_address (operands[1], operands[8]);
3285 (define_insn "movstrsi_postreload"
3286 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3287 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3288 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3289 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3290 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3291 (clobber (match_dup 0))
3292 (clobber (match_dup 1))
3293 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3294 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3296 "!TARGET_64BIT && reload_completed"
3297 "* return output_block_move (operands, !which_alternative);"
3298 [(set_attr "type" "multi,multi")])
3300 (define_expand "movstrdi"
3301 [(parallel [(set (match_operand:BLK 0 "" "")
3302 (match_operand:BLK 1 "" ""))
3303 (clobber (match_dup 4))
3304 (clobber (match_dup 5))
3305 (clobber (match_dup 6))
3306 (clobber (match_dup 7))
3307 (clobber (match_dup 8))
3308 (use (match_operand:DI 2 "arith_operand" ""))
3309 (use (match_operand:DI 3 "const_int_operand" ""))])]
3310 "TARGET_64BIT && optimize > 0"
3315 /* HP provides very fast block move library routine for the PA;
3316 this routine includes:
3318 4x4 byte at a time block moves,
3319 1x4 byte at a time with alignment checked at runtime with
3320 attempts to align the source and destination as needed
3323 With that in mind, here's the heuristics to try and guess when
3324 the inlined block move will be better than the library block
3327 If the size isn't constant, then always use the library routines.
3329 If the size is large in respect to the known alignment, then use
3330 the library routines.
3332 If the size is small in respect to the known alignment, then open
3333 code the copy (since that will lead to better scheduling).
3335 Else use the block move pattern. */
3337 /* Undetermined size, use the library routine. */
3338 if (GET_CODE (operands[2]) != CONST_INT)
3341 size = INTVAL (operands[2]);
3342 align = INTVAL (operands[3]);
3343 align = align > 8 ? 8 : align;
3345 /* If size/alignment is large, then use the library routines. */
3346 if (size / align > 16)
3349 /* This does happen, but not often enough to worry much about. */
3350 if (size / align < MOVE_RATIO)
3353 /* Fall through means we're going to use our block move pattern. */
3355 = replace_equiv_address (operands[0],
3356 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3358 = replace_equiv_address (operands[1],
3359 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3360 operands[4] = gen_reg_rtx (DImode);
3361 operands[5] = gen_reg_rtx (DImode);
3362 operands[6] = gen_reg_rtx (DImode);
3363 operands[7] = gen_reg_rtx (DImode);
3364 operands[8] = gen_reg_rtx (DImode);
3367 ;; The operand constraints are written like this to support both compile-time
3368 ;; and run-time determined byte counts. The expander and output_block_move
3369 ;; only support compile-time determined counts at this time.
3371 ;; If the count is run-time determined, the register with the byte count
3372 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3374 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3375 ;; broke this semantic for pseudo registers. We can't use match_scratch
3376 ;; as this requires two registers in the class R1_REGS when the MEMs for
3377 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3378 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3379 ;; respectively. We then split or peephole optimize after reload.
3380 (define_insn "movstrdi_prereload"
3381 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3382 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3383 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3384 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3385 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3386 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3387 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3388 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3389 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3392 [(set_attr "type" "multi,multi")])
3395 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3396 (match_operand:BLK 1 "memory_operand" ""))
3397 (clobber (match_operand:DI 2 "register_operand" ""))
3398 (clobber (match_operand:DI 3 "register_operand" ""))
3399 (clobber (match_operand:DI 6 "register_operand" ""))
3400 (clobber (match_operand:DI 7 "register_operand" ""))
3401 (clobber (match_operand:DI 8 "register_operand" ""))
3402 (use (match_operand:DI 4 "arith_operand" ""))
3403 (use (match_operand:DI 5 "const_int_operand" ""))])]
3404 "TARGET_64BIT && reload_completed && !flag_peephole2
3405 && GET_CODE (operands[0]) == MEM
3406 && register_operand (XEXP (operands[0], 0), DImode)
3407 && GET_CODE (operands[1]) == MEM
3408 && register_operand (XEXP (operands[1], 0), DImode)"
3409 [(set (match_dup 7) (match_dup 9))
3410 (set (match_dup 8) (match_dup 10))
3411 (parallel [(set (match_dup 0) (match_dup 1))
3412 (clobber (match_dup 2))
3413 (clobber (match_dup 3))
3414 (clobber (match_dup 6))
3415 (clobber (match_dup 7))
3416 (clobber (match_dup 8))
3422 operands[9] = XEXP (operands[0], 0);
3423 operands[10] = XEXP (operands[1], 0);
3424 operands[0] = replace_equiv_address (operands[0], operands[7]);
3425 operands[1] = replace_equiv_address (operands[1], operands[8]);
3429 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3430 (match_operand:BLK 1 "memory_operand" ""))
3431 (clobber (match_operand:DI 2 "register_operand" ""))
3432 (clobber (match_operand:DI 3 "register_operand" ""))
3433 (clobber (match_operand:DI 6 "register_operand" ""))
3434 (clobber (match_operand:DI 7 "register_operand" ""))
3435 (clobber (match_operand:DI 8 "register_operand" ""))
3436 (use (match_operand:DI 4 "arith_operand" ""))
3437 (use (match_operand:DI 5 "const_int_operand" ""))])]
3439 && GET_CODE (operands[0]) == MEM
3440 && register_operand (XEXP (operands[0], 0), DImode)
3441 && GET_CODE (operands[1]) == MEM
3442 && register_operand (XEXP (operands[1], 0), DImode)"
3443 [(parallel [(set (match_dup 0) (match_dup 1))
3444 (clobber (match_dup 2))
3445 (clobber (match_dup 3))
3446 (clobber (match_dup 6))
3447 (clobber (match_dup 7))
3448 (clobber (match_dup 8))
3454 rtx addr = XEXP (operands[0], 0);
3455 if (dead_or_set_p (curr_insn, addr))
3459 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3460 operands[0] = replace_equiv_address (operands[0], operands[7]);
3463 addr = XEXP (operands[1], 0);
3464 if (dead_or_set_p (curr_insn, addr))
3468 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3469 operands[1] = replace_equiv_address (operands[1], operands[8]);
3473 (define_insn "movstrdi_postreload"
3474 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3475 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3476 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3477 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3478 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3479 (clobber (match_dup 0))
3480 (clobber (match_dup 1))
3481 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3482 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3484 "TARGET_64BIT && reload_completed"
3485 "* return output_block_move (operands, !which_alternative);"
3486 [(set_attr "type" "multi,multi")])
3488 (define_expand "clrstrsi"
3489 [(parallel [(set (match_operand:BLK 0 "" "")
3491 (clobber (match_dup 3))
3492 (clobber (match_dup 4))
3493 (use (match_operand:SI 1 "arith_operand" ""))
3494 (use (match_operand:SI 2 "const_int_operand" ""))])]
3495 "!TARGET_64BIT && optimize > 0"
3500 /* Undetermined size, use the library routine. */
3501 if (GET_CODE (operands[1]) != CONST_INT)
3504 size = INTVAL (operands[1]);
3505 align = INTVAL (operands[2]);
3506 align = align > 4 ? 4 : align;
3508 /* If size/alignment is large, then use the library routines. */
3509 if (size / align > 16)
3512 /* This does happen, but not often enough to worry much about. */
3513 if (size / align < MOVE_RATIO)
3516 /* Fall through means we're going to use our block clear pattern. */
3518 = replace_equiv_address (operands[0],
3519 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3520 operands[3] = gen_reg_rtx (SImode);
3521 operands[4] = gen_reg_rtx (SImode);
3524 (define_insn "clrstrsi_prereload"
3525 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3527 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3528 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3529 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3530 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3533 [(set_attr "type" "multi,multi")])
3536 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3538 (clobber (match_operand:SI 1 "register_operand" ""))
3539 (clobber (match_operand:SI 4 "register_operand" ""))
3540 (use (match_operand:SI 2 "arith_operand" ""))
3541 (use (match_operand:SI 3 "const_int_operand" ""))])]
3542 "!TARGET_64BIT && reload_completed && !flag_peephole2
3543 && GET_CODE (operands[0]) == MEM
3544 && register_operand (XEXP (operands[0], 0), SImode)"
3545 [(set (match_dup 4) (match_dup 5))
3546 (parallel [(set (match_dup 0) (const_int 0))
3547 (clobber (match_dup 1))
3548 (clobber (match_dup 4))
3554 operands[5] = XEXP (operands[0], 0);
3555 operands[0] = replace_equiv_address (operands[0], operands[4]);
3559 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3561 (clobber (match_operand:SI 1 "register_operand" ""))
3562 (clobber (match_operand:SI 4 "register_operand" ""))
3563 (use (match_operand:SI 2 "arith_operand" ""))
3564 (use (match_operand:SI 3 "const_int_operand" ""))])]
3566 && GET_CODE (operands[0]) == MEM
3567 && register_operand (XEXP (operands[0], 0), SImode)"
3568 [(parallel [(set (match_dup 0) (const_int 0))
3569 (clobber (match_dup 1))
3570 (clobber (match_dup 4))
3576 rtx addr = XEXP (operands[0], 0);
3577 if (dead_or_set_p (curr_insn, addr))
3581 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3582 operands[0] = replace_equiv_address (operands[0], operands[4]);
3586 (define_insn "clrstrsi_postreload"
3587 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3589 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3590 (clobber (match_dup 0))
3591 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3592 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3594 "!TARGET_64BIT && reload_completed"
3595 "* return output_block_clear (operands, !which_alternative);"
3596 [(set_attr "type" "multi,multi")])
3598 (define_expand "clrstrdi"
3599 [(parallel [(set (match_operand:BLK 0 "" "")
3601 (clobber (match_dup 3))
3602 (clobber (match_dup 4))
3603 (use (match_operand:DI 1 "arith_operand" ""))
3604 (use (match_operand:DI 2 "const_int_operand" ""))])]
3605 "TARGET_64BIT && optimize > 0"
3610 /* Undetermined size, use the library routine. */
3611 if (GET_CODE (operands[1]) != CONST_INT)
3614 size = INTVAL (operands[1]);
3615 align = INTVAL (operands[2]);
3616 align = align > 8 ? 8 : align;
3618 /* If size/alignment is large, then use the library routines. */
3619 if (size / align > 16)
3622 /* This does happen, but not often enough to worry much about. */
3623 if (size / align < MOVE_RATIO)
3626 /* Fall through means we're going to use our block clear pattern. */
3628 = replace_equiv_address (operands[0],
3629 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3630 operands[3] = gen_reg_rtx (DImode);
3631 operands[4] = gen_reg_rtx (DImode);
3634 (define_insn "clrstrdi_prereload"
3635 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3637 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3638 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3639 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3640 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3643 [(set_attr "type" "multi,multi")])
3646 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3648 (clobber (match_operand:DI 1 "register_operand" ""))
3649 (clobber (match_operand:DI 4 "register_operand" ""))
3650 (use (match_operand:DI 2 "arith_operand" ""))
3651 (use (match_operand:DI 3 "const_int_operand" ""))])]
3652 "TARGET_64BIT && reload_completed && !flag_peephole2
3653 && GET_CODE (operands[0]) == MEM
3654 && register_operand (XEXP (operands[0], 0), DImode)"
3655 [(set (match_dup 4) (match_dup 5))
3656 (parallel [(set (match_dup 0) (const_int 0))
3657 (clobber (match_dup 1))
3658 (clobber (match_dup 4))
3664 operands[5] = XEXP (operands[0], 0);
3665 operands[0] = replace_equiv_address (operands[0], operands[4]);
3669 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3671 (clobber (match_operand:DI 1 "register_operand" ""))
3672 (clobber (match_operand:DI 4 "register_operand" ""))
3673 (use (match_operand:DI 2 "arith_operand" ""))
3674 (use (match_operand:DI 3 "const_int_operand" ""))])]
3676 && GET_CODE (operands[0]) == MEM
3677 && register_operand (XEXP (operands[0], 0), DImode)"
3678 [(parallel [(set (match_dup 0) (const_int 0))
3679 (clobber (match_dup 1))
3680 (clobber (match_dup 4))
3686 rtx addr = XEXP (operands[0], 0);
3687 if (dead_or_set_p (curr_insn, addr))
3691 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3692 operands[0] = replace_equiv_address (operands[0], operands[4]);
3696 (define_insn "clrstrdi_postreload"
3697 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3699 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3700 (clobber (match_dup 0))
3701 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3702 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3704 "TARGET_64BIT && reload_completed"
3705 "* return output_block_clear (operands, !which_alternative);"
3706 [(set_attr "type" "multi,multi")])
3708 ;; Floating point move insns
3710 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3711 ;; to be reloaded by putting the constant into memory when
3712 ;; reg is a floating point register.
3714 ;; For integer registers we use ldil;ldo to set the appropriate
3717 ;; This must come before the movdf pattern, and it must be present
3718 ;; to handle obscure reloading cases.
3720 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3721 (match_operand:DF 1 "" "?F,m"))]
3722 "GET_CODE (operands[1]) == CONST_DOUBLE
3723 && operands[1] != CONST0_RTX (DFmode)
3725 && !TARGET_SOFT_FLOAT"
3726 "* return (which_alternative == 0 ? output_move_double (operands)
3727 : \"fldd%F1 %1,%0\");"
3728 [(set_attr "type" "move,fpload")
3729 (set_attr "length" "16,4")])
3731 (define_expand "movdf"
3732 [(set (match_operand:DF 0 "general_operand" "")
3733 (match_operand:DF 1 "general_operand" ""))]
3737 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3738 operands[1] = force_const_mem (DFmode, operands[1]);
3740 if (emit_move_sequence (operands, DFmode, 0))
3744 ;; Reloading an SImode or DImode value requires a scratch register if
3745 ;; going in to or out of float point registers.
3747 (define_expand "reload_indf"
3748 [(set (match_operand:DF 0 "register_operand" "=Z")
3749 (match_operand:DF 1 "non_hard_reg_operand" ""))
3750 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3754 if (emit_move_sequence (operands, DFmode, operands[2]))
3757 /* We don't want the clobber emitted, so handle this ourselves. */
3758 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3762 (define_expand "reload_outdf"
3763 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3764 (match_operand:DF 1 "register_operand" "Z"))
3765 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3769 if (emit_move_sequence (operands, DFmode, operands[2]))
3772 /* We don't want the clobber emitted, so handle this ourselves. */
3773 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3778 [(set (match_operand:DF 0 "move_dest_operand"
3779 "=f,*r,Q,?o,?Q,f,*r,*r")
3780 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3781 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3782 "(register_operand (operands[0], DFmode)
3783 || reg_or_0_operand (operands[1], DFmode))
3784 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3785 && GET_CODE (operands[0]) == MEM)
3787 && !TARGET_SOFT_FLOAT"
3790 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3791 || operands[1] == CONST0_RTX (DFmode))
3792 return output_fp_move_double (operands);
3793 return output_move_double (operands);
3795 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3796 (set_attr "length" "4,8,4,8,16,4,8,16")])
3799 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3800 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3802 && !TARGET_DISABLE_INDEXING
3803 && reload_completed"
3805 [(set_attr "type" "fpstore")
3806 (set_attr "pa_combine_type" "addmove")
3807 (set_attr "length" "4")])
3810 [(set (match_operand:SI 0 "register_operand" "")
3811 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3813 (match_operand:SI 2 "register_operand" "")))
3814 (set (mem:DF (match_dup 0))
3815 (match_operand:DF 3 "register_operand" ""))]
3817 && REG_OK_FOR_BASE_P (operands[2])
3818 && FP_REGNO_P (REGNO (operands[3]))"
3819 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3821 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3826 [(set (match_operand:SI 0 "register_operand" "")
3827 (plus:SI (match_operand:SI 2 "register_operand" "")
3828 (mult:SI (match_operand:SI 1 "register_operand" "")
3830 (set (mem:DF (match_dup 0))
3831 (match_operand:DF 3 "register_operand" ""))]
3833 && REG_OK_FOR_BASE_P (operands[2])
3834 && FP_REGNO_P (REGNO (operands[3]))"
3835 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3837 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3842 [(set (match_operand:DI 0 "register_operand" "")
3843 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3845 (match_operand:DI 2 "register_operand" "")))
3846 (set (mem:DF (match_dup 0))
3847 (match_operand:DF 3 "register_operand" ""))]
3850 && REG_OK_FOR_BASE_P (operands[2])
3851 && FP_REGNO_P (REGNO (operands[3]))"
3852 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3854 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3859 [(set (match_operand:DI 0 "register_operand" "")
3860 (plus:DI (match_operand:DI 2 "register_operand" "")
3861 (mult:DI (match_operand:DI 1 "register_operand" "")
3863 (set (mem:DF (match_dup 0))
3864 (match_operand:DF 3 "register_operand" ""))]
3867 && REG_OK_FOR_BASE_P (operands[2])
3868 && FP_REGNO_P (REGNO (operands[3]))"
3869 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3871 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3876 [(set (match_operand:SI 0 "register_operand" "")
3877 (plus:SI (match_operand:SI 1 "register_operand" "")
3878 (match_operand:SI 2 "register_operand" "")))
3879 (set (mem:DF (match_dup 0))
3880 (match_operand:DF 3 "register_operand" ""))]
3882 && REG_OK_FOR_BASE_P (operands[1])
3883 && (TARGET_NO_SPACE_REGS
3884 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3885 && FP_REGNO_P (REGNO (operands[3]))"
3886 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3888 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3892 [(set (match_operand:SI 0 "register_operand" "")
3893 (plus:SI (match_operand:SI 1 "register_operand" "")
3894 (match_operand:SI 2 "register_operand" "")))
3895 (set (mem:DF (match_dup 0))
3896 (match_operand:DF 3 "register_operand" ""))]
3898 && REG_OK_FOR_BASE_P (operands[2])
3899 && (TARGET_NO_SPACE_REGS
3900 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3901 && FP_REGNO_P (REGNO (operands[3]))"
3902 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3904 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3908 [(set (match_operand:DI 0 "register_operand" "")
3909 (plus:DI (match_operand:DI 1 "register_operand" "")
3910 (match_operand:DI 2 "register_operand" "")))
3911 (set (mem:DF (match_dup 0))
3912 (match_operand:DF 3 "register_operand" ""))]
3915 && REG_OK_FOR_BASE_P (operands[1])
3916 && (TARGET_NO_SPACE_REGS
3917 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3918 && FP_REGNO_P (REGNO (operands[3]))"
3919 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3921 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3925 [(set (match_operand:DI 0 "register_operand" "")
3926 (plus:DI (match_operand:DI 1 "register_operand" "")
3927 (match_operand:DI 2 "register_operand" "")))
3928 (set (mem:DF (match_dup 0))
3929 (match_operand:DF 3 "register_operand" ""))]
3932 && REG_OK_FOR_BASE_P (operands[2])
3933 && (TARGET_NO_SPACE_REGS
3934 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3935 && FP_REGNO_P (REGNO (operands[3]))"
3936 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3938 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3942 [(set (match_operand:DF 0 "move_dest_operand"
3944 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3946 "(register_operand (operands[0], DFmode)
3947 || reg_or_0_operand (operands[1], DFmode))
3949 && TARGET_SOFT_FLOAT"
3952 return output_move_double (operands);
3954 [(set_attr "type" "move,store,store,load,load")
3955 (set_attr "length" "8,8,16,8,16")])
3958 [(set (match_operand:DF 0 "move_dest_operand"
3959 "=!*r,*r,*r,*r,*r,Q,!*q,f,f,T")
3960 (match_operand:DF 1 "move_src_operand"
3961 "!*r,J,N,K,RQ,*rM,!*rM,fM,RT,f"))]
3962 "(register_operand (operands[0], DFmode)
3963 || reg_or_0_operand (operands[1], DFmode))
3964 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3976 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3977 (set_attr "pa_combine_type" "addmove")
3978 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3981 (define_expand "movdi"
3982 [(set (match_operand:DI 0 "general_operand" "")
3983 (match_operand:DI 1 "general_operand" ""))]
3987 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3988 operands[1] = force_const_mem (DImode, operands[1]);
3990 if (emit_move_sequence (operands, DImode, 0))
3994 (define_expand "reload_indi"
3995 [(set (match_operand:DI 0 "register_operand" "=Z")
3996 (match_operand:DI 1 "non_hard_reg_operand" ""))
3997 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4001 if (emit_move_sequence (operands, DImode, operands[2]))
4004 /* We don't want the clobber emitted, so handle this ourselves. */
4005 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4009 (define_expand "reload_outdi"
4010 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4011 (match_operand:DI 1 "register_operand" "Z"))
4012 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4016 if (emit_move_sequence (operands, DImode, operands[2]))
4019 /* We don't want the clobber emitted, so handle this ourselves. */
4020 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4025 [(set (match_operand:DI 0 "register_operand" "=r")
4026 (high:DI (match_operand 1 "" "")))]
4030 rtx op0 = operands[0];
4031 rtx op1 = operands[1];
4033 if (GET_CODE (op1) == CONST_INT)
4035 operands[0] = operand_subword (op0, 1, 0, DImode);
4036 output_asm_insn (\"ldil L'%1,%0\", operands);
4038 operands[0] = operand_subword (op0, 0, 0, DImode);
4039 if (INTVAL (op1) < 0)
4040 output_asm_insn (\"ldi -1,%0\", operands);
4042 output_asm_insn (\"ldi 0,%0\", operands);
4045 else if (GET_CODE (op1) == CONST_DOUBLE)
4047 operands[0] = operand_subword (op0, 1, 0, DImode);
4048 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4049 output_asm_insn (\"ldil L'%1,%0\", operands);
4051 operands[0] = operand_subword (op0, 0, 0, DImode);
4052 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4053 output_asm_insn (singlemove_string (operands), operands);
4059 [(set_attr "type" "move")
4060 (set_attr "length" "8")])
4063 [(set (match_operand:DI 0 "move_dest_operand"
4064 "=r,o,Q,r,r,r,*f,*f,T")
4065 (match_operand:DI 1 "general_operand"
4066 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4067 "(register_operand (operands[0], DImode)
4068 || reg_or_0_operand (operands[1], DImode))
4070 && !TARGET_SOFT_FLOAT"
4073 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4074 || (operands[1] == CONST0_RTX (DImode)))
4075 return output_fp_move_double (operands);
4076 return output_move_double (operands);
4078 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4079 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4082 [(set (match_operand:DI 0 "move_dest_operand"
4083 "=r,r,r,r,r,r,Q,!*q,!*f,*f,T")
4084 (match_operand:DI 1 "move_src_operand"
4085 "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))]
4086 "(register_operand (operands[0], DImode)
4087 || reg_or_0_operand (operands[1], DImode))
4088 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4101 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
4102 (set_attr "pa_combine_type" "addmove")
4103 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
4106 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4107 (match_operand:DI 1 "register_operand" "f"))]
4110 && !TARGET_DISABLE_INDEXING
4111 && reload_completed"
4113 [(set_attr "type" "fpstore")
4114 (set_attr "pa_combine_type" "addmove")
4115 (set_attr "length" "4")])
4118 [(set (match_operand:DI 0 "register_operand" "")
4119 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4121 (match_operand:DI 2 "register_operand" "")))
4122 (set (mem:DI (match_dup 0))
4123 (match_operand:DI 3 "register_operand" ""))]
4126 && REG_OK_FOR_BASE_P (operands[2])
4127 && FP_REGNO_P (REGNO (operands[3]))"
4128 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4130 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4135 [(set (match_operand:DI 0 "register_operand" "")
4136 (plus:DI (match_operand:DI 2 "register_operand" "")
4137 (mult:DI (match_operand:DI 1 "register_operand" "")
4139 (set (mem:DI (match_dup 0))
4140 (match_operand:DI 3 "register_operand" ""))]
4143 && REG_OK_FOR_BASE_P (operands[2])
4144 && FP_REGNO_P (REGNO (operands[3]))"
4145 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4147 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4152 [(set (match_operand:DI 0 "register_operand" "")
4153 (plus:DI (match_operand:DI 1 "register_operand" "")
4154 (match_operand:DI 2 "register_operand" "")))
4155 (set (mem:DI (match_dup 0))
4156 (match_operand:DI 3 "register_operand" ""))]
4159 && REG_OK_FOR_BASE_P (operands[1])
4160 && (TARGET_NO_SPACE_REGS
4161 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4162 && FP_REGNO_P (REGNO (operands[3]))"
4163 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4165 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4169 [(set (match_operand:DI 0 "register_operand" "")
4170 (plus:DI (match_operand:DI 1 "register_operand" "")
4171 (match_operand:DI 2 "register_operand" "")))
4172 (set (mem:DI (match_dup 0))
4173 (match_operand:DI 3 "register_operand" ""))]
4176 && REG_OK_FOR_BASE_P (operands[2])
4177 && (TARGET_NO_SPACE_REGS
4178 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4179 && FP_REGNO_P (REGNO (operands[3]))"
4180 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4182 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4186 [(set (match_operand:DI 0 "move_dest_operand"
4188 (match_operand:DI 1 "general_operand"
4190 "(register_operand (operands[0], DImode)
4191 || reg_or_0_operand (operands[1], DImode))
4193 && TARGET_SOFT_FLOAT"
4196 return output_move_double (operands);
4198 [(set_attr "type" "move,store,store,load,load,multi")
4199 (set_attr "length" "8,8,16,8,16,16")])
4202 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4203 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4204 (match_operand:DI 2 "immediate_operand" "i,i")))]
4208 /* Don't output a 64 bit constant, since we can't trust the assembler to
4209 handle it correctly. */
4210 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4211 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4212 if (which_alternative == 1)
4213 output_asm_insn (\"copy %1,%0\", operands);
4214 return \"ldo R'%G2(%R1),%R0\";
4216 [(set_attr "type" "move,move")
4217 (set_attr "length" "4,8")])
4219 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4220 ;; to be reloaded by putting the constant into memory when
4221 ;; reg is a floating point register.
4223 ;; For integer registers we use ldil;ldo to set the appropriate
4226 ;; This must come before the movsf pattern, and it must be present
4227 ;; to handle obscure reloading cases.
4229 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4230 (match_operand:SF 1 "" "?F,m"))]
4231 "GET_CODE (operands[1]) == CONST_DOUBLE
4232 && operands[1] != CONST0_RTX (SFmode)
4233 && ! TARGET_SOFT_FLOAT"
4234 "* return (which_alternative == 0 ? singlemove_string (operands)
4235 : \" fldw%F1 %1,%0\");"
4236 [(set_attr "type" "move,fpload")
4237 (set_attr "length" "8,4")])
4239 (define_expand "movsf"
4240 [(set (match_operand:SF 0 "general_operand" "")
4241 (match_operand:SF 1 "general_operand" ""))]
4245 if (emit_move_sequence (operands, SFmode, 0))
4249 ;; Reloading an SImode or DImode value requires a scratch register if
4250 ;; going in to or out of float point registers.
4252 (define_expand "reload_insf"
4253 [(set (match_operand:SF 0 "register_operand" "=Z")
4254 (match_operand:SF 1 "non_hard_reg_operand" ""))
4255 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4259 if (emit_move_sequence (operands, SFmode, operands[2]))
4262 /* We don't want the clobber emitted, so handle this ourselves. */
4263 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4267 (define_expand "reload_outsf"
4268 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4269 (match_operand:SF 1 "register_operand" "Z"))
4270 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4274 if (emit_move_sequence (operands, SFmode, operands[2]))
4277 /* We don't want the clobber emitted, so handle this ourselves. */
4278 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4283 [(set (match_operand:SF 0 "move_dest_operand"
4285 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4286 "fG,!*rG,RQ,RQ,f,*rG"))]
4287 "(register_operand (operands[0], SFmode)
4288 || reg_or_0_operand (operands[1], SFmode))
4289 && !TARGET_SOFT_FLOAT"
4297 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4298 (set_attr "pa_combine_type" "addmove")
4299 (set_attr "length" "4,4,4,4,4,4")])
4302 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4303 (match_operand:SF 1 "register_operand" "f"))]
4305 && !TARGET_DISABLE_INDEXING
4306 && reload_completed"
4308 [(set_attr "type" "fpstore")
4309 (set_attr "pa_combine_type" "addmove")
4310 (set_attr "length" "4")])
4313 [(set (match_operand:SI 0 "register_operand" "")
4314 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4316 (match_operand:SI 2 "register_operand" "")))
4317 (set (mem:SF (match_dup 0))
4318 (match_operand:SF 3 "register_operand" ""))]
4320 && REG_OK_FOR_BASE_P (operands[2])
4321 && FP_REGNO_P (REGNO (operands[3]))"
4322 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4324 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4329 [(set (match_operand:SI 0 "register_operand" "")
4330 (plus:SI (match_operand:SI 2 "register_operand" "")
4331 (mult:SI (match_operand:SI 1 "register_operand" "")
4333 (set (mem:SF (match_dup 0))
4334 (match_operand:SF 3 "register_operand" ""))]
4336 && REG_OK_FOR_BASE_P (operands[2])
4337 && FP_REGNO_P (REGNO (operands[3]))"
4338 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4340 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4345 [(set (match_operand:DI 0 "register_operand" "")
4346 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4348 (match_operand:DI 2 "register_operand" "")))
4349 (set (mem:SF (match_dup 0))
4350 (match_operand:SF 3 "register_operand" ""))]
4353 && REG_OK_FOR_BASE_P (operands[2])
4354 && FP_REGNO_P (REGNO (operands[3]))"
4355 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4357 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4362 [(set (match_operand:DI 0 "register_operand" "")
4363 (plus:DI (match_operand:DI 2 "register_operand" "")
4364 (mult:DI (match_operand:DI 1 "register_operand" "")
4366 (set (mem:SF (match_dup 0))
4367 (match_operand:SF 3 "register_operand" ""))]
4370 && REG_OK_FOR_BASE_P (operands[2])
4371 && FP_REGNO_P (REGNO (operands[3]))"
4372 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4374 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4379 [(set (match_operand:SI 0 "register_operand" "")
4380 (plus:SI (match_operand:SI 1 "register_operand" "")
4381 (match_operand:SI 2 "register_operand" "")))
4382 (set (mem:SF (match_dup 0))
4383 (match_operand:SF 3 "register_operand" ""))]
4385 && REG_OK_FOR_BASE_P (operands[1])
4386 && (TARGET_NO_SPACE_REGS
4387 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4388 && FP_REGNO_P (REGNO (operands[3]))"
4389 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4391 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4395 [(set (match_operand:SI 0 "register_operand" "")
4396 (plus:SI (match_operand:SI 1 "register_operand" "")
4397 (match_operand:SI 2 "register_operand" "")))
4398 (set (mem:SF (match_dup 0))
4399 (match_operand:SF 3 "register_operand" ""))]
4401 && REG_OK_FOR_BASE_P (operands[2])
4402 && (TARGET_NO_SPACE_REGS
4403 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4404 && FP_REGNO_P (REGNO (operands[3]))"
4405 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4407 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4411 [(set (match_operand:DI 0 "register_operand" "")
4412 (plus:DI (match_operand:DI 1 "register_operand" "")
4413 (match_operand:DI 2 "register_operand" "")))
4414 (set (mem:SF (match_dup 0))
4415 (match_operand:SF 3 "register_operand" ""))]
4418 && REG_OK_FOR_BASE_P (operands[1])
4419 && (TARGET_NO_SPACE_REGS
4420 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4421 && FP_REGNO_P (REGNO (operands[3]))"
4422 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4424 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4428 [(set (match_operand:DI 0 "register_operand" "")
4429 (plus:DI (match_operand:DI 1 "register_operand" "")
4430 (match_operand:DI 2 "register_operand" "")))
4431 (set (mem:SF (match_dup 0))
4432 (match_operand:SF 3 "register_operand" ""))]
4435 && REG_OK_FOR_BASE_P (operands[2])
4436 && (TARGET_NO_SPACE_REGS
4437 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4438 && FP_REGNO_P (REGNO (operands[3]))"
4439 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4441 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4445 [(set (match_operand:SF 0 "move_dest_operand"
4447 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4449 "(register_operand (operands[0], SFmode)
4450 || reg_or_0_operand (operands[1], SFmode))
4451 && TARGET_SOFT_FLOAT"
4456 [(set_attr "type" "move,load,store")
4457 (set_attr "pa_combine_type" "addmove")
4458 (set_attr "length" "4,4,4")])
4462 ;;- zero extension instructions
4463 ;; We have define_expand for zero extension patterns to make sure the
4464 ;; operands get loaded into registers. The define_insns accept
4465 ;; memory operands. This gives us better overall code than just
4466 ;; having a pattern that does or does not accept memory operands.
4468 (define_expand "zero_extendqihi2"
4469 [(set (match_operand:HI 0 "register_operand" "")
4471 (match_operand:QI 1 "register_operand" "")))]
4476 [(set (match_operand:HI 0 "register_operand" "=r,r")
4478 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4479 "GET_CODE (operands[1]) != CONST_INT"
4481 {extru|extrw,u} %1,31,8,%0
4483 [(set_attr "type" "shift,load")
4484 (set_attr "length" "4,4")])
4486 (define_expand "zero_extendqisi2"
4487 [(set (match_operand:SI 0 "register_operand" "")
4489 (match_operand:QI 1 "register_operand" "")))]
4494 [(set (match_operand:SI 0 "register_operand" "=r,r")
4496 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4497 "GET_CODE (operands[1]) != CONST_INT"
4499 {extru|extrw,u} %1,31,8,%0
4501 [(set_attr "type" "shift,load")
4502 (set_attr "length" "4,4")])
4504 (define_expand "zero_extendhisi2"
4505 [(set (match_operand:SI 0 "register_operand" "")
4507 (match_operand:HI 1 "register_operand" "")))]
4512 [(set (match_operand:SI 0 "register_operand" "=r,r")
4514 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4515 "GET_CODE (operands[1]) != CONST_INT"
4517 {extru|extrw,u} %1,31,16,%0
4519 [(set_attr "type" "shift,load")
4520 (set_attr "length" "4,4")])
4522 (define_expand "zero_extendqidi2"
4523 [(set (match_operand:DI 0 "register_operand" "")
4525 (match_operand:QI 1 "register_operand" "")))]
4530 [(set (match_operand:DI 0 "register_operand" "=r,r")
4532 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4533 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4537 [(set_attr "type" "shift,load")
4538 (set_attr "length" "4,4")])
4540 (define_expand "zero_extendhidi2"
4541 [(set (match_operand:DI 0 "register_operand" "")
4543 (match_operand:HI 1 "register_operand" "")))]
4548 [(set (match_operand:DI 0 "register_operand" "=r,r")
4550 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4551 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4555 [(set_attr "type" "shift,load")
4556 (set_attr "length" "4,4")])
4558 (define_expand "zero_extendsidi2"
4559 [(set (match_operand:DI 0 "register_operand" "")
4561 (match_operand:SI 1 "register_operand" "")))]
4566 [(set (match_operand:DI 0 "register_operand" "=r,r")
4568 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4569 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4573 [(set_attr "type" "shift,load")
4574 (set_attr "length" "4,4")])
4576 ;;- sign extension instructions
4578 (define_insn "extendhisi2"
4579 [(set (match_operand:SI 0 "register_operand" "=r")
4580 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4582 "{extrs|extrw,s} %1,31,16,%0"
4583 [(set_attr "type" "shift")
4584 (set_attr "length" "4")])
4586 (define_insn "extendqihi2"
4587 [(set (match_operand:HI 0 "register_operand" "=r")
4588 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4590 "{extrs|extrw,s} %1,31,8,%0"
4591 [(set_attr "type" "shift")
4592 (set_attr "length" "4")])
4594 (define_insn "extendqisi2"
4595 [(set (match_operand:SI 0 "register_operand" "=r")
4596 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4598 "{extrs|extrw,s} %1,31,8,%0"
4599 [(set_attr "type" "shift")
4600 (set_attr "length" "4")])
4602 (define_insn "extendqidi2"
4603 [(set (match_operand:DI 0 "register_operand" "=r")
4604 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4606 "extrd,s %1,63,8,%0"
4607 [(set_attr "type" "shift")
4608 (set_attr "length" "4")])
4610 (define_insn "extendhidi2"
4611 [(set (match_operand:DI 0 "register_operand" "=r")
4612 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4614 "extrd,s %1,63,16,%0"
4615 [(set_attr "type" "shift")
4616 (set_attr "length" "4")])
4618 (define_insn "extendsidi2"
4619 [(set (match_operand:DI 0 "register_operand" "=r")
4620 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4622 "extrd,s %1,63,32,%0"
4623 [(set_attr "type" "shift")
4624 (set_attr "length" "4")])
4627 ;; Conversions between float and double.
4629 (define_insn "extendsfdf2"
4630 [(set (match_operand:DF 0 "register_operand" "=f")
4632 (match_operand:SF 1 "register_operand" "f")))]
4633 "! TARGET_SOFT_FLOAT"
4634 "{fcnvff|fcnv},sgl,dbl %1,%0"
4635 [(set_attr "type" "fpalu")
4636 (set_attr "length" "4")])
4638 (define_insn "truncdfsf2"
4639 [(set (match_operand:SF 0 "register_operand" "=f")
4641 (match_operand:DF 1 "register_operand" "f")))]
4642 "! TARGET_SOFT_FLOAT"
4643 "{fcnvff|fcnv},dbl,sgl %1,%0"
4644 [(set_attr "type" "fpalu")
4645 (set_attr "length" "4")])
4647 ;; Conversion between fixed point and floating point.
4648 ;; Note that among the fix-to-float insns
4649 ;; the ones that start with SImode come first.
4650 ;; That is so that an operand that is a CONST_INT
4651 ;; (and therefore lacks a specific machine mode).
4652 ;; will be recognized as SImode (which is always valid)
4653 ;; rather than as QImode or HImode.
4655 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4656 ;; to be reloaded by putting the constant into memory.
4657 ;; It must come before the more general floatsisf2 pattern.
4659 [(set (match_operand:SF 0 "register_operand" "=f")
4660 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4661 "! TARGET_SOFT_FLOAT"
4662 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4663 [(set_attr "type" "fpalu")
4664 (set_attr "length" "8")])
4666 (define_insn "floatsisf2"
4667 [(set (match_operand:SF 0 "register_operand" "=f")
4668 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4669 "! TARGET_SOFT_FLOAT"
4670 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4671 [(set_attr "type" "fpalu")
4672 (set_attr "length" "4")])
4674 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4675 ;; to be reloaded by putting the constant into memory.
4676 ;; It must come before the more general floatsidf2 pattern.
4678 [(set (match_operand:DF 0 "register_operand" "=f")
4679 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4680 "! TARGET_SOFT_FLOAT"
4681 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4682 [(set_attr "type" "fpalu")
4683 (set_attr "length" "8")])
4685 (define_insn "floatsidf2"
4686 [(set (match_operand:DF 0 "register_operand" "=f")
4687 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4688 "! TARGET_SOFT_FLOAT"
4689 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4690 [(set_attr "type" "fpalu")
4691 (set_attr "length" "4")])
4693 (define_expand "floatunssisf2"
4694 [(set (subreg:SI (match_dup 2) 4)
4695 (match_operand:SI 1 "register_operand" ""))
4696 (set (subreg:SI (match_dup 2) 0)
4698 (set (match_operand:SF 0 "register_operand" "")
4699 (float:SF (match_dup 2)))]
4700 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4705 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4708 operands[2] = gen_reg_rtx (DImode);
4711 (define_expand "floatunssidf2"
4712 [(set (subreg:SI (match_dup 2) 4)
4713 (match_operand:SI 1 "register_operand" ""))
4714 (set (subreg:SI (match_dup 2) 0)
4716 (set (match_operand:DF 0 "register_operand" "")
4717 (float:DF (match_dup 2)))]
4718 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4723 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4726 operands[2] = gen_reg_rtx (DImode);
4729 (define_insn "floatdisf2"
4730 [(set (match_operand:SF 0 "register_operand" "=f")
4731 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4732 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4733 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4734 [(set_attr "type" "fpalu")
4735 (set_attr "length" "4")])
4737 (define_insn "floatdidf2"
4738 [(set (match_operand:DF 0 "register_operand" "=f")
4739 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4740 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4741 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4742 [(set_attr "type" "fpalu")
4743 (set_attr "length" "4")])
4745 ;; Convert a float to an actual integer.
4746 ;; Truncation is performed as part of the conversion.
4748 (define_insn "fix_truncsfsi2"
4749 [(set (match_operand:SI 0 "register_operand" "=f")
4750 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4751 "! TARGET_SOFT_FLOAT"
4752 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4753 [(set_attr "type" "fpalu")
4754 (set_attr "length" "4")])
4756 (define_insn "fix_truncdfsi2"
4757 [(set (match_operand:SI 0 "register_operand" "=f")
4758 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4759 "! TARGET_SOFT_FLOAT"
4760 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4761 [(set_attr "type" "fpalu")
4762 (set_attr "length" "4")])
4764 (define_insn "fix_truncsfdi2"
4765 [(set (match_operand:DI 0 "register_operand" "=f")
4766 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4767 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4768 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4769 [(set_attr "type" "fpalu")
4770 (set_attr "length" "4")])
4772 (define_insn "fix_truncdfdi2"
4773 [(set (match_operand:DI 0 "register_operand" "=f")
4774 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4775 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4776 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4777 [(set_attr "type" "fpalu")
4778 (set_attr "length" "4")])
4780 (define_insn "floatunssidf2_pa20"
4781 [(set (match_operand:DF 0 "register_operand" "=f")
4782 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4783 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4785 [(set_attr "type" "fpalu")
4786 (set_attr "length" "4")])
4788 (define_insn "floatunssisf2_pa20"
4789 [(set (match_operand:SF 0 "register_operand" "=f")
4790 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4791 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4793 [(set_attr "type" "fpalu")
4794 (set_attr "length" "4")])
4796 (define_insn "floatunsdisf2"
4797 [(set (match_operand:SF 0 "register_operand" "=f")
4798 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4799 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4800 "fcnv,udw,sgl %1,%0"
4801 [(set_attr "type" "fpalu")
4802 (set_attr "length" "4")])
4804 (define_insn "floatunsdidf2"
4805 [(set (match_operand:DF 0 "register_operand" "=f")
4806 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4807 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4808 "fcnv,udw,dbl %1,%0"
4809 [(set_attr "type" "fpalu")
4810 (set_attr "length" "4")])
4812 (define_insn "fixuns_truncsfsi2"
4813 [(set (match_operand:SI 0 "register_operand" "=f")
4814 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4815 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4816 "fcnv,t,sgl,uw %1,%0"
4817 [(set_attr "type" "fpalu")
4818 (set_attr "length" "4")])
4820 (define_insn "fixuns_truncdfsi2"
4821 [(set (match_operand:SI 0 "register_operand" "=f")
4822 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4823 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4824 "fcnv,t,dbl,uw %1,%0"
4825 [(set_attr "type" "fpalu")
4826 (set_attr "length" "4")])
4828 (define_insn "fixuns_truncsfdi2"
4829 [(set (match_operand:DI 0 "register_operand" "=f")
4830 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4831 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4832 "fcnv,t,sgl,udw %1,%0"
4833 [(set_attr "type" "fpalu")
4834 (set_attr "length" "4")])
4836 (define_insn "fixuns_truncdfdi2"
4837 [(set (match_operand:DI 0 "register_operand" "=f")
4838 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4839 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4840 "fcnv,t,dbl,udw %1,%0"
4841 [(set_attr "type" "fpalu")
4842 (set_attr "length" "4")])
4844 ;;- arithmetic instructions
4846 (define_expand "adddi3"
4847 [(set (match_operand:DI 0 "register_operand" "")
4848 (plus:DI (match_operand:DI 1 "register_operand" "")
4849 (match_operand:DI 2 "adddi3_operand" "")))]
4854 [(set (match_operand:DI 0 "register_operand" "=r")
4855 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4856 (match_operand:DI 2 "arith11_operand" "rI")))]
4860 if (GET_CODE (operands[2]) == CONST_INT)
4862 if (INTVAL (operands[2]) >= 0)
4863 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4865 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4868 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4870 [(set_attr "type" "binary")
4871 (set_attr "length" "8")])
4874 [(set (match_operand:DI 0 "register_operand" "=r,r")
4875 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4876 (match_operand:DI 2 "arith_operand" "r,J")))]
4881 [(set_attr "type" "binary,binary")
4882 (set_attr "pa_combine_type" "addmove")
4883 (set_attr "length" "4,4")])
4886 [(set (match_operand:DI 0 "register_operand" "=r")
4887 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4888 (match_operand:DI 2 "register_operand" "r")))]
4891 [(set_attr "type" "binary")
4892 (set_attr "length" "4")])
4895 [(set (match_operand:SI 0 "register_operand" "=r")
4896 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4897 (match_operand:SI 2 "register_operand" "r")))]
4900 [(set_attr "type" "binary")
4901 (set_attr "length" "4")])
4903 ;; define_splits to optimize cases of adding a constant integer
4904 ;; to a register when the constant does not fit in 14 bits. */
4906 [(set (match_operand:SI 0 "register_operand" "")
4907 (plus:SI (match_operand:SI 1 "register_operand" "")
4908 (match_operand:SI 2 "const_int_operand" "")))
4909 (clobber (match_operand:SI 4 "register_operand" ""))]
4910 "! cint_ok_for_move (INTVAL (operands[2]))
4911 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4912 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4913 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4916 int val = INTVAL (operands[2]);
4917 int low = (val < 0) ? -0x2000 : 0x1fff;
4918 int rest = val - low;
4920 operands[2] = GEN_INT (rest);
4921 operands[3] = GEN_INT (low);
4925 [(set (match_operand:SI 0 "register_operand" "")
4926 (plus:SI (match_operand:SI 1 "register_operand" "")
4927 (match_operand:SI 2 "const_int_operand" "")))
4928 (clobber (match_operand:SI 4 "register_operand" ""))]
4929 "! cint_ok_for_move (INTVAL (operands[2]))"
4930 [(set (match_dup 4) (match_dup 2))
4931 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4935 HOST_WIDE_INT intval = INTVAL (operands[2]);
4937 /* Try dividing the constant by 2, then 4, and finally 8 to see
4938 if we can get a constant which can be loaded into a register
4939 in a single instruction (cint_ok_for_move).
4941 If that fails, try to negate the constant and subtract it
4942 from our input operand. */
4943 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4945 operands[2] = GEN_INT (intval / 2);
4946 operands[3] = const2_rtx;
4948 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4950 operands[2] = GEN_INT (intval / 4);
4951 operands[3] = GEN_INT (4);
4953 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4955 operands[2] = GEN_INT (intval / 8);
4956 operands[3] = GEN_INT (8);
4958 else if (cint_ok_for_move (-intval))
4960 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4961 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
4968 (define_insn "addsi3"
4969 [(set (match_operand:SI 0 "register_operand" "=r,r")
4970 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
4971 (match_operand:SI 2 "arith_operand" "r,J")))]
4974 {addl|add,l} %1,%2,%0
4976 [(set_attr "type" "binary,binary")
4977 (set_attr "pa_combine_type" "addmove")
4978 (set_attr "length" "4,4")])
4980 (define_expand "subdi3"
4981 [(set (match_operand:DI 0 "register_operand" "")
4982 (minus:DI (match_operand:DI 1 "register_operand" "")
4983 (match_operand:DI 2 "register_operand" "")))]
4988 [(set (match_operand:DI 0 "register_operand" "=r")
4989 (minus:DI (match_operand:DI 1 "register_operand" "r")
4990 (match_operand:DI 2 "register_operand" "r")))]
4992 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
4993 [(set_attr "type" "binary")
4994 (set_attr "length" "8")])
4997 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
4998 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
4999 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5005 [(set_attr "type" "binary,binary,move")
5006 (set_attr "length" "4,4,4")])
5008 (define_expand "subsi3"
5009 [(set (match_operand:SI 0 "register_operand" "")
5010 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5011 (match_operand:SI 2 "register_operand" "")))]
5016 [(set (match_operand:SI 0 "register_operand" "=r,r")
5017 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5018 (match_operand:SI 2 "register_operand" "r,r")))]
5023 [(set_attr "type" "binary,binary")
5024 (set_attr "length" "4,4")])
5027 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5028 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5029 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5035 [(set_attr "type" "binary,binary,move")
5036 (set_attr "length" "4,4,4")])
5038 ;; Clobbering a "register_operand" instead of a match_scratch
5039 ;; in operand3 of millicode calls avoids spilling %r1 and
5040 ;; produces better code.
5042 ;; The mulsi3 insns set up registers for the millicode call.
5043 (define_expand "mulsi3"
5044 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5045 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5046 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5047 (clobber (match_dup 3))
5048 (clobber (reg:SI 26))
5049 (clobber (reg:SI 25))
5050 (clobber (match_dup 4))])
5051 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5055 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5056 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5058 rtx scratch = gen_reg_rtx (DImode);
5059 operands[1] = force_reg (SImode, operands[1]);
5060 operands[2] = force_reg (SImode, operands[2]);
5061 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5062 emit_insn (gen_movsi (operands[0],
5063 gen_rtx_SUBREG (SImode, scratch,
5064 GET_MODE_SIZE (SImode))));
5067 operands[3] = gen_reg_rtx (SImode);
5070 (define_insn "umulsidi3"
5071 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5072 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5073 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5074 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5076 [(set_attr "type" "fpmuldbl")
5077 (set_attr "length" "4")])
5080 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5081 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5082 (match_operand:DI 2 "uint32_operand" "f")))]
5083 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5085 [(set_attr "type" "fpmuldbl")
5086 (set_attr "length" "4")])
5089 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5090 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5091 (match_operand:DI 2 "uint32_operand" "f")))]
5092 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5094 [(set_attr "type" "fpmuldbl")
5095 (set_attr "length" "4")])
5098 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5099 (clobber (match_operand:SI 0 "register_operand" "=a"))
5100 (clobber (reg:SI 26))
5101 (clobber (reg:SI 25))
5102 (clobber (reg:SI 31))]
5104 "* return output_mul_insn (0, insn);"
5105 [(set_attr "type" "milli")
5106 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5109 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5110 (clobber (match_operand:SI 0 "register_operand" "=a"))
5111 (clobber (reg:SI 26))
5112 (clobber (reg:SI 25))
5113 (clobber (reg:SI 2))]
5115 "* return output_mul_insn (0, insn);"
5116 [(set_attr "type" "milli")
5117 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5119 (define_expand "muldi3"
5120 [(set (match_operand:DI 0 "register_operand" "")
5121 (mult:DI (match_operand:DI 1 "register_operand" "")
5122 (match_operand:DI 2 "register_operand" "")))]
5123 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5126 rtx low_product = gen_reg_rtx (DImode);
5127 rtx cross_product1 = gen_reg_rtx (DImode);
5128 rtx cross_product2 = gen_reg_rtx (DImode);
5129 rtx cross_scratch = gen_reg_rtx (DImode);
5130 rtx cross_product = gen_reg_rtx (DImode);
5131 rtx op1l, op1r, op2l, op2r;
5132 rtx op1shifted, op2shifted;
5134 op1shifted = gen_reg_rtx (DImode);
5135 op2shifted = gen_reg_rtx (DImode);
5136 op1l = gen_reg_rtx (SImode);
5137 op1r = gen_reg_rtx (SImode);
5138 op2l = gen_reg_rtx (SImode);
5139 op2r = gen_reg_rtx (SImode);
5141 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5143 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5145 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5146 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5147 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5148 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5150 /* Emit multiplies for the cross products. */
5151 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5152 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5154 /* Emit a multiply for the low sub-word. */
5155 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5157 /* Sum the cross products and shift them into proper position. */
5158 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5159 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5161 /* Add the cross product to the low product and store the result
5162 into the output operand . */
5163 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5167 ;;; Division and mod.
5168 (define_expand "divsi3"
5169 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5170 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5171 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5172 (clobber (match_dup 3))
5173 (clobber (match_dup 4))
5174 (clobber (reg:SI 26))
5175 (clobber (reg:SI 25))
5176 (clobber (match_dup 5))])
5177 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5181 operands[3] = gen_reg_rtx (SImode);
5184 operands[5] = gen_rtx_REG (SImode, 2);
5185 operands[4] = operands[5];
5189 operands[5] = gen_rtx_REG (SImode, 31);
5190 operands[4] = gen_reg_rtx (SImode);
5192 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5198 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5199 (clobber (match_operand:SI 1 "register_operand" "=a"))
5200 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5201 (clobber (reg:SI 26))
5202 (clobber (reg:SI 25))
5203 (clobber (reg:SI 31))]
5206 return output_div_insn (operands, 0, insn);"
5207 [(set_attr "type" "milli")
5208 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5212 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5213 (clobber (match_operand:SI 1 "register_operand" "=a"))
5214 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5215 (clobber (reg:SI 26))
5216 (clobber (reg:SI 25))
5217 (clobber (reg:SI 2))]
5220 return output_div_insn (operands, 0, insn);"
5221 [(set_attr "type" "milli")
5222 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5224 (define_expand "udivsi3"
5225 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5226 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5227 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5228 (clobber (match_dup 3))
5229 (clobber (match_dup 4))
5230 (clobber (reg:SI 26))
5231 (clobber (reg:SI 25))
5232 (clobber (match_dup 5))])
5233 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5237 operands[3] = gen_reg_rtx (SImode);
5241 operands[5] = gen_rtx_REG (SImode, 2);
5242 operands[4] = operands[5];
5246 operands[5] = gen_rtx_REG (SImode, 31);
5247 operands[4] = gen_reg_rtx (SImode);
5249 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5255 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5256 (clobber (match_operand:SI 1 "register_operand" "=a"))
5257 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5258 (clobber (reg:SI 26))
5259 (clobber (reg:SI 25))
5260 (clobber (reg:SI 31))]
5263 return output_div_insn (operands, 1, insn);"
5264 [(set_attr "type" "milli")
5265 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5269 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5270 (clobber (match_operand:SI 1 "register_operand" "=a"))
5271 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5272 (clobber (reg:SI 26))
5273 (clobber (reg:SI 25))
5274 (clobber (reg:SI 2))]
5277 return output_div_insn (operands, 1, insn);"
5278 [(set_attr "type" "milli")
5279 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5281 (define_expand "modsi3"
5282 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5283 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5284 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5285 (clobber (match_dup 3))
5286 (clobber (match_dup 4))
5287 (clobber (reg:SI 26))
5288 (clobber (reg:SI 25))
5289 (clobber (match_dup 5))])
5290 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5296 operands[5] = gen_rtx_REG (SImode, 2);
5297 operands[4] = operands[5];
5301 operands[5] = gen_rtx_REG (SImode, 31);
5302 operands[4] = gen_reg_rtx (SImode);
5304 operands[3] = gen_reg_rtx (SImode);
5308 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5309 (clobber (match_operand:SI 0 "register_operand" "=a"))
5310 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5311 (clobber (reg:SI 26))
5312 (clobber (reg:SI 25))
5313 (clobber (reg:SI 31))]
5316 return output_mod_insn (0, insn);"
5317 [(set_attr "type" "milli")
5318 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5321 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5322 (clobber (match_operand:SI 0 "register_operand" "=a"))
5323 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5324 (clobber (reg:SI 26))
5325 (clobber (reg:SI 25))
5326 (clobber (reg:SI 2))]
5329 return output_mod_insn (0, insn);"
5330 [(set_attr "type" "milli")
5331 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5333 (define_expand "umodsi3"
5334 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5335 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5336 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5337 (clobber (match_dup 3))
5338 (clobber (match_dup 4))
5339 (clobber (reg:SI 26))
5340 (clobber (reg:SI 25))
5341 (clobber (match_dup 5))])
5342 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5348 operands[5] = gen_rtx_REG (SImode, 2);
5349 operands[4] = operands[5];
5353 operands[5] = gen_rtx_REG (SImode, 31);
5354 operands[4] = gen_reg_rtx (SImode);
5356 operands[3] = gen_reg_rtx (SImode);
5360 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5361 (clobber (match_operand:SI 0 "register_operand" "=a"))
5362 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5363 (clobber (reg:SI 26))
5364 (clobber (reg:SI 25))
5365 (clobber (reg:SI 31))]
5368 return output_mod_insn (1, insn);"
5369 [(set_attr "type" "milli")
5370 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5373 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5374 (clobber (match_operand:SI 0 "register_operand" "=a"))
5375 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5376 (clobber (reg:SI 26))
5377 (clobber (reg:SI 25))
5378 (clobber (reg:SI 2))]
5381 return output_mod_insn (1, insn);"
5382 [(set_attr "type" "milli")
5383 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5385 ;;- and instructions
5386 ;; We define DImode `and` so with DImode `not` we can get
5387 ;; DImode `andn`. Other combinations are possible.
5389 (define_expand "anddi3"
5390 [(set (match_operand:DI 0 "register_operand" "")
5391 (and:DI (match_operand:DI 1 "and_operand" "")
5392 (match_operand:DI 2 "and_operand" "")))]
5398 /* One operand must be a register operand. */
5399 if (!register_operand (operands[1], DImode)
5400 && !register_operand (operands[2], DImode))
5405 /* Both operands must be register operands. */
5406 if (!register_operand (operands[1], DImode)
5407 || !register_operand (operands[2], DImode))
5413 [(set (match_operand:DI 0 "register_operand" "=r")
5414 (and:DI (match_operand:DI 1 "register_operand" "%r")
5415 (match_operand:DI 2 "register_operand" "r")))]
5417 "and %1,%2,%0\;and %R1,%R2,%R0"
5418 [(set_attr "type" "binary")
5419 (set_attr "length" "8")])
5422 [(set (match_operand:DI 0 "register_operand" "=r,r")
5423 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5424 (match_operand:DI 2 "and_operand" "rO,P")))]
5426 "* return output_64bit_and (operands); "
5427 [(set_attr "type" "binary")
5428 (set_attr "length" "4")])
5430 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5431 ; constant with ldil;ldo.
5432 (define_insn "andsi3"
5433 [(set (match_operand:SI 0 "register_operand" "=r,r")
5434 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5435 (match_operand:SI 2 "and_operand" "rO,P")))]
5437 "* return output_and (operands); "
5438 [(set_attr "type" "binary,shift")
5439 (set_attr "length" "4,4")])
5442 [(set (match_operand:DI 0 "register_operand" "=r")
5443 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5444 (match_operand:DI 2 "register_operand" "r")))]
5446 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5447 [(set_attr "type" "binary")
5448 (set_attr "length" "8")])
5451 [(set (match_operand:DI 0 "register_operand" "=r")
5452 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5453 (match_operand:DI 2 "register_operand" "r")))]
5456 [(set_attr "type" "binary")
5457 (set_attr "length" "4")])
5460 [(set (match_operand:SI 0 "register_operand" "=r")
5461 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5462 (match_operand:SI 2 "register_operand" "r")))]
5465 [(set_attr "type" "binary")
5466 (set_attr "length" "4")])
5468 (define_expand "iordi3"
5469 [(set (match_operand:DI 0 "register_operand" "")
5470 (ior:DI (match_operand:DI 1 "ior_operand" "")
5471 (match_operand:DI 2 "ior_operand" "")))]
5477 /* One operand must be a register operand. */
5478 if (!register_operand (operands[1], DImode)
5479 && !register_operand (operands[2], DImode))
5484 /* Both operands must be register operands. */
5485 if (!register_operand (operands[1], DImode)
5486 || !register_operand (operands[2], DImode))
5492 [(set (match_operand:DI 0 "register_operand" "=r")
5493 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5494 (match_operand:DI 2 "register_operand" "r")))]
5496 "or %1,%2,%0\;or %R1,%R2,%R0"
5497 [(set_attr "type" "binary")
5498 (set_attr "length" "8")])
5501 [(set (match_operand:DI 0 "register_operand" "=r,r")
5502 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5503 (match_operand:DI 2 "ior_operand" "M,i")))]
5505 "* return output_64bit_ior (operands); "
5506 [(set_attr "type" "binary,shift")
5507 (set_attr "length" "4,4")])
5510 [(set (match_operand:DI 0 "register_operand" "=r")
5511 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5512 (match_operand:DI 2 "register_operand" "r")))]
5515 [(set_attr "type" "binary")
5516 (set_attr "length" "4")])
5518 ;; Need a define_expand because we've run out of CONST_OK... characters.
5519 (define_expand "iorsi3"
5520 [(set (match_operand:SI 0 "register_operand" "")
5521 (ior:SI (match_operand:SI 1 "register_operand" "")
5522 (match_operand:SI 2 "arith32_operand" "")))]
5526 if (! (ior_operand (operands[2], SImode)
5527 || register_operand (operands[2], SImode)))
5528 operands[2] = force_reg (SImode, operands[2]);
5532 [(set (match_operand:SI 0 "register_operand" "=r,r")
5533 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5534 (match_operand:SI 2 "ior_operand" "M,i")))]
5536 "* return output_ior (operands); "
5537 [(set_attr "type" "binary,shift")
5538 (set_attr "length" "4,4")])
5541 [(set (match_operand:SI 0 "register_operand" "=r")
5542 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5543 (match_operand:SI 2 "register_operand" "r")))]
5546 [(set_attr "type" "binary")
5547 (set_attr "length" "4")])
5549 (define_expand "xordi3"
5550 [(set (match_operand:DI 0 "register_operand" "")
5551 (xor:DI (match_operand:DI 1 "register_operand" "")
5552 (match_operand:DI 2 "register_operand" "")))]
5559 [(set (match_operand:DI 0 "register_operand" "=r")
5560 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5561 (match_operand:DI 2 "register_operand" "r")))]
5563 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5564 [(set_attr "type" "binary")
5565 (set_attr "length" "8")])
5568 [(set (match_operand:DI 0 "register_operand" "=r")
5569 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5570 (match_operand:DI 2 "register_operand" "r")))]
5573 [(set_attr "type" "binary")
5574 (set_attr "length" "4")])
5576 (define_insn "xorsi3"
5577 [(set (match_operand:SI 0 "register_operand" "=r")
5578 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5579 (match_operand:SI 2 "register_operand" "r")))]
5582 [(set_attr "type" "binary")
5583 (set_attr "length" "4")])
5585 (define_expand "negdi2"
5586 [(set (match_operand:DI 0 "register_operand" "")
5587 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5592 [(set (match_operand:DI 0 "register_operand" "=r")
5593 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5595 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5596 [(set_attr "type" "unary")
5597 (set_attr "length" "8")])
5600 [(set (match_operand:DI 0 "register_operand" "=r")
5601 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5604 [(set_attr "type" "unary")
5605 (set_attr "length" "4")])
5607 (define_insn "negsi2"
5608 [(set (match_operand:SI 0 "register_operand" "=r")
5609 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5612 [(set_attr "type" "unary")
5613 (set_attr "length" "4")])
5615 (define_expand "one_cmpldi2"
5616 [(set (match_operand:DI 0 "register_operand" "")
5617 (not:DI (match_operand:DI 1 "register_operand" "")))]
5624 [(set (match_operand:DI 0 "register_operand" "=r")
5625 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5627 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5628 [(set_attr "type" "unary")
5629 (set_attr "length" "8")])
5632 [(set (match_operand:DI 0 "register_operand" "=r")
5633 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5636 [(set_attr "type" "unary")
5637 (set_attr "length" "4")])
5639 (define_insn "one_cmplsi2"
5640 [(set (match_operand:SI 0 "register_operand" "=r")
5641 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5644 [(set_attr "type" "unary")
5645 (set_attr "length" "4")])
5647 ;; Floating point arithmetic instructions.
5649 (define_insn "adddf3"
5650 [(set (match_operand:DF 0 "register_operand" "=f")
5651 (plus:DF (match_operand:DF 1 "register_operand" "f")
5652 (match_operand:DF 2 "register_operand" "f")))]
5653 "! TARGET_SOFT_FLOAT"
5655 [(set_attr "type" "fpalu")
5656 (set_attr "pa_combine_type" "faddsub")
5657 (set_attr "length" "4")])
5659 (define_insn "addsf3"
5660 [(set (match_operand:SF 0 "register_operand" "=f")
5661 (plus:SF (match_operand:SF 1 "register_operand" "f")
5662 (match_operand:SF 2 "register_operand" "f")))]
5663 "! TARGET_SOFT_FLOAT"
5665 [(set_attr "type" "fpalu")
5666 (set_attr "pa_combine_type" "faddsub")
5667 (set_attr "length" "4")])
5669 (define_insn "subdf3"
5670 [(set (match_operand:DF 0 "register_operand" "=f")
5671 (minus:DF (match_operand:DF 1 "register_operand" "f")
5672 (match_operand:DF 2 "register_operand" "f")))]
5673 "! TARGET_SOFT_FLOAT"
5675 [(set_attr "type" "fpalu")
5676 (set_attr "pa_combine_type" "faddsub")
5677 (set_attr "length" "4")])
5679 (define_insn "subsf3"
5680 [(set (match_operand:SF 0 "register_operand" "=f")
5681 (minus:SF (match_operand:SF 1 "register_operand" "f")
5682 (match_operand:SF 2 "register_operand" "f")))]
5683 "! TARGET_SOFT_FLOAT"
5685 [(set_attr "type" "fpalu")
5686 (set_attr "pa_combine_type" "faddsub")
5687 (set_attr "length" "4")])
5689 (define_insn "muldf3"
5690 [(set (match_operand:DF 0 "register_operand" "=f")
5691 (mult:DF (match_operand:DF 1 "register_operand" "f")
5692 (match_operand:DF 2 "register_operand" "f")))]
5693 "! TARGET_SOFT_FLOAT"
5695 [(set_attr "type" "fpmuldbl")
5696 (set_attr "pa_combine_type" "fmpy")
5697 (set_attr "length" "4")])
5699 (define_insn "mulsf3"
5700 [(set (match_operand:SF 0 "register_operand" "=f")
5701 (mult:SF (match_operand:SF 1 "register_operand" "f")
5702 (match_operand:SF 2 "register_operand" "f")))]
5703 "! TARGET_SOFT_FLOAT"
5705 [(set_attr "type" "fpmulsgl")
5706 (set_attr "pa_combine_type" "fmpy")
5707 (set_attr "length" "4")])
5709 (define_insn "divdf3"
5710 [(set (match_operand:DF 0 "register_operand" "=f")
5711 (div:DF (match_operand:DF 1 "register_operand" "f")
5712 (match_operand:DF 2 "register_operand" "f")))]
5713 "! TARGET_SOFT_FLOAT"
5715 [(set_attr "type" "fpdivdbl")
5716 (set_attr "length" "4")])
5718 (define_insn "divsf3"
5719 [(set (match_operand:SF 0 "register_operand" "=f")
5720 (div:SF (match_operand:SF 1 "register_operand" "f")
5721 (match_operand:SF 2 "register_operand" "f")))]
5722 "! TARGET_SOFT_FLOAT"
5724 [(set_attr "type" "fpdivsgl")
5725 (set_attr "length" "4")])
5727 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5728 ;; negation can be done by subtracting from plus zero. However, this
5729 ;; violates the IEEE standard when negating plus and minus zero.
5730 (define_expand "negdf2"
5731 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5732 (neg:DF (match_operand:DF 1 "register_operand" "")))
5733 (use (match_dup 2))])]
5734 "! TARGET_SOFT_FLOAT"
5736 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5737 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5740 operands[2] = force_reg (DFmode,
5741 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5742 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5747 (define_insn "negdf2_fast"
5748 [(set (match_operand:DF 0 "register_operand" "=f")
5749 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5750 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5754 return \"fneg,dbl %1,%0\";
5756 return \"fsub,dbl %%fr0,%1,%0\";
5758 [(set_attr "type" "fpalu")
5759 (set_attr "length" "4")])
5761 (define_expand "negsf2"
5762 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5763 (neg:SF (match_operand:SF 1 "register_operand" "")))
5764 (use (match_dup 2))])]
5765 "! TARGET_SOFT_FLOAT"
5767 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5768 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5771 operands[2] = force_reg (SFmode,
5772 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5773 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5778 (define_insn "negsf2_fast"
5779 [(set (match_operand:SF 0 "register_operand" "=f")
5780 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5781 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5785 return \"fneg,sgl %1,%0\";
5787 return \"fsub,sgl %%fr0,%1,%0\";
5789 [(set_attr "type" "fpalu")
5790 (set_attr "length" "4")])
5792 (define_insn "absdf2"
5793 [(set (match_operand:DF 0 "register_operand" "=f")
5794 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5795 "! TARGET_SOFT_FLOAT"
5797 [(set_attr "type" "fpalu")
5798 (set_attr "length" "4")])
5800 (define_insn "abssf2"
5801 [(set (match_operand:SF 0 "register_operand" "=f")
5802 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5803 "! TARGET_SOFT_FLOAT"
5805 [(set_attr "type" "fpalu")
5806 (set_attr "length" "4")])
5808 (define_insn "sqrtdf2"
5809 [(set (match_operand:DF 0 "register_operand" "=f")
5810 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5811 "! TARGET_SOFT_FLOAT"
5813 [(set_attr "type" "fpsqrtdbl")
5814 (set_attr "length" "4")])
5816 (define_insn "sqrtsf2"
5817 [(set (match_operand:SF 0 "register_operand" "=f")
5818 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5819 "! TARGET_SOFT_FLOAT"
5821 [(set_attr "type" "fpsqrtsgl")
5822 (set_attr "length" "4")])
5824 ;; PA 2.0 floating point instructions
5828 [(set (match_operand:DF 0 "register_operand" "=f")
5829 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5830 (match_operand:DF 2 "register_operand" "f"))
5831 (match_operand:DF 3 "register_operand" "f")))]
5832 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5833 "fmpyfadd,dbl %1,%2,%3,%0"
5834 [(set_attr "type" "fpmuldbl")
5835 (set_attr "length" "4")])
5838 [(set (match_operand:DF 0 "register_operand" "=f")
5839 (plus:DF (match_operand:DF 1 "register_operand" "f")
5840 (mult:DF (match_operand:DF 2 "register_operand" "f")
5841 (match_operand:DF 3 "register_operand" "f"))))]
5842 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5843 "fmpyfadd,dbl %2,%3,%1,%0"
5844 [(set_attr "type" "fpmuldbl")
5845 (set_attr "length" "4")])
5848 [(set (match_operand:SF 0 "register_operand" "=f")
5849 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5850 (match_operand:SF 2 "register_operand" "f"))
5851 (match_operand:SF 3 "register_operand" "f")))]
5852 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5853 "fmpyfadd,sgl %1,%2,%3,%0"
5854 [(set_attr "type" "fpmulsgl")
5855 (set_attr "length" "4")])
5858 [(set (match_operand:SF 0 "register_operand" "=f")
5859 (plus:SF (match_operand:SF 1 "register_operand" "f")
5860 (mult:SF (match_operand:SF 2 "register_operand" "f")
5861 (match_operand:SF 3 "register_operand" "f"))))]
5862 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5863 "fmpyfadd,sgl %2,%3,%1,%0"
5864 [(set_attr "type" "fpmulsgl")
5865 (set_attr "length" "4")])
5867 ; fmpynfadd patterns
5869 [(set (match_operand:DF 0 "register_operand" "=f")
5870 (minus:DF (match_operand:DF 1 "register_operand" "f")
5871 (mult:DF (match_operand:DF 2 "register_operand" "f")
5872 (match_operand:DF 3 "register_operand" "f"))))]
5873 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5874 "fmpynfadd,dbl %2,%3,%1,%0"
5875 [(set_attr "type" "fpmuldbl")
5876 (set_attr "length" "4")])
5879 [(set (match_operand:SF 0 "register_operand" "=f")
5880 (minus:SF (match_operand:SF 1 "register_operand" "f")
5881 (mult:SF (match_operand:SF 2 "register_operand" "f")
5882 (match_operand:SF 3 "register_operand" "f"))))]
5883 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5884 "fmpynfadd,sgl %2,%3,%1,%0"
5885 [(set_attr "type" "fpmulsgl")
5886 (set_attr "length" "4")])
5890 [(set (match_operand:DF 0 "register_operand" "=f")
5891 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5892 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5894 [(set_attr "type" "fpalu")
5895 (set_attr "length" "4")])
5898 [(set (match_operand:SF 0 "register_operand" "=f")
5899 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5900 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5902 [(set_attr "type" "fpalu")
5903 (set_attr "length" "4")])
5905 ;; Generating a fused multiply sequence is a win for this case as it will
5906 ;; reduce the latency for the fused case without impacting the plain
5909 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5910 ;; perform two operations with the result of the first feeding the second.
5912 [(set (match_operand:DF 0 "register_operand" "=f")
5913 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5914 (match_operand:DF 2 "register_operand" "f"))
5915 (match_operand:DF 3 "register_operand" "f")))
5916 (set (match_operand:DF 4 "register_operand" "=&f")
5917 (mult:DF (match_dup 1) (match_dup 2)))]
5918 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5919 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5920 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5922 [(set_attr "type" "fpmuldbl")
5923 (set_attr "length" "8")])
5925 ;; We want to split this up during scheduling since we want both insns
5926 ;; to schedule independently.
5928 [(set (match_operand:DF 0 "register_operand" "")
5929 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5930 (match_operand:DF 2 "register_operand" ""))
5931 (match_operand:DF 3 "register_operand" "")))
5932 (set (match_operand:DF 4 "register_operand" "")
5933 (mult:DF (match_dup 1) (match_dup 2)))]
5934 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5935 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5936 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5941 [(set (match_operand:SF 0 "register_operand" "=f")
5942 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5943 (match_operand:SF 2 "register_operand" "f"))
5944 (match_operand:SF 3 "register_operand" "f")))
5945 (set (match_operand:SF 4 "register_operand" "=&f")
5946 (mult:SF (match_dup 1) (match_dup 2)))]
5947 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5948 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5949 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5951 [(set_attr "type" "fpmuldbl")
5952 (set_attr "length" "8")])
5954 ;; We want to split this up during scheduling since we want both insns
5955 ;; to schedule independently.
5957 [(set (match_operand:SF 0 "register_operand" "")
5958 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5959 (match_operand:SF 2 "register_operand" ""))
5960 (match_operand:SF 3 "register_operand" "")))
5961 (set (match_operand:SF 4 "register_operand" "")
5962 (mult:SF (match_dup 1) (match_dup 2)))]
5963 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5964 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5965 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5969 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5972 [(set (match_operand:DF 0 "register_operand" "=f")
5973 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5974 (match_operand:DF 2 "register_operand" "f"))))]
5975 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5976 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5977 [(set_attr "type" "fpmuldbl")
5978 (set_attr "length" "4")])
5981 [(set (match_operand:SF 0 "register_operand" "=f")
5982 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5983 (match_operand:SF 2 "register_operand" "f"))))]
5984 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5985 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5986 [(set_attr "type" "fpmuldbl")
5987 (set_attr "length" "4")])
5990 [(set (match_operand:DF 0 "register_operand" "=f")
5991 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5992 (match_operand:DF 2 "register_operand" "f"))))
5993 (set (match_operand:DF 3 "register_operand" "=&f")
5994 (mult:DF (match_dup 1) (match_dup 2)))]
5995 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5996 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5997 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5999 [(set_attr "type" "fpmuldbl")
6000 (set_attr "length" "8")])
6003 [(set (match_operand:DF 0 "register_operand" "")
6004 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6005 (match_operand:DF 2 "register_operand" ""))))
6006 (set (match_operand:DF 3 "register_operand" "")
6007 (mult:DF (match_dup 1) (match_dup 2)))]
6008 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6009 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6010 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6014 [(set (match_operand:SF 0 "register_operand" "=f")
6015 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6016 (match_operand:SF 2 "register_operand" "f"))))
6017 (set (match_operand:SF 3 "register_operand" "=&f")
6018 (mult:SF (match_dup 1) (match_dup 2)))]
6019 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6020 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6021 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6023 [(set_attr "type" "fpmuldbl")
6024 (set_attr "length" "8")])
6027 [(set (match_operand:SF 0 "register_operand" "")
6028 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6029 (match_operand:SF 2 "register_operand" ""))))
6030 (set (match_operand:SF 3 "register_operand" "")
6031 (mult:SF (match_dup 1) (match_dup 2)))]
6032 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6033 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6034 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6037 ;; Now fused multiplies with the result of the multiply negated.
6039 [(set (match_operand:DF 0 "register_operand" "=f")
6040 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6041 (match_operand:DF 2 "register_operand" "f")))
6042 (match_operand:DF 3 "register_operand" "f")))]
6043 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6044 "fmpynfadd,dbl %1,%2,%3,%0"
6045 [(set_attr "type" "fpmuldbl")
6046 (set_attr "length" "4")])
6049 [(set (match_operand:SF 0 "register_operand" "=f")
6050 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6051 (match_operand:SF 2 "register_operand" "f")))
6052 (match_operand:SF 3 "register_operand" "f")))]
6053 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6054 "fmpynfadd,sgl %1,%2,%3,%0"
6055 [(set_attr "type" "fpmuldbl")
6056 (set_attr "length" "4")])
6059 [(set (match_operand:DF 0 "register_operand" "=f")
6060 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6061 (match_operand:DF 2 "register_operand" "f")))
6062 (match_operand:DF 3 "register_operand" "f")))
6063 (set (match_operand:DF 4 "register_operand" "=&f")
6064 (mult:DF (match_dup 1) (match_dup 2)))]
6065 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6066 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6067 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6069 [(set_attr "type" "fpmuldbl")
6070 (set_attr "length" "8")])
6073 [(set (match_operand:DF 0 "register_operand" "")
6074 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6075 (match_operand:DF 2 "register_operand" "")))
6076 (match_operand:DF 3 "register_operand" "")))
6077 (set (match_operand:DF 4 "register_operand" "")
6078 (mult:DF (match_dup 1) (match_dup 2)))]
6079 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6080 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6081 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6086 [(set (match_operand:SF 0 "register_operand" "=f")
6087 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6088 (match_operand:SF 2 "register_operand" "f")))
6089 (match_operand:SF 3 "register_operand" "f")))
6090 (set (match_operand:SF 4 "register_operand" "=&f")
6091 (mult:SF (match_dup 1) (match_dup 2)))]
6092 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6093 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6094 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6096 [(set_attr "type" "fpmuldbl")
6097 (set_attr "length" "8")])
6100 [(set (match_operand:SF 0 "register_operand" "")
6101 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6102 (match_operand:SF 2 "register_operand" "")))
6103 (match_operand:SF 3 "register_operand" "")))
6104 (set (match_operand:SF 4 "register_operand" "")
6105 (mult:SF (match_dup 1) (match_dup 2)))]
6106 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6107 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6108 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6113 [(set (match_operand:DF 0 "register_operand" "=f")
6114 (minus:DF (match_operand:DF 3 "register_operand" "f")
6115 (mult:DF (match_operand:DF 1 "register_operand" "f")
6116 (match_operand:DF 2 "register_operand" "f"))))
6117 (set (match_operand:DF 4 "register_operand" "=&f")
6118 (mult:DF (match_dup 1) (match_dup 2)))]
6119 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6120 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6121 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6123 [(set_attr "type" "fpmuldbl")
6124 (set_attr "length" "8")])
6127 [(set (match_operand:DF 0 "register_operand" "")
6128 (minus:DF (match_operand:DF 3 "register_operand" "")
6129 (mult:DF (match_operand:DF 1 "register_operand" "")
6130 (match_operand:DF 2 "register_operand" ""))))
6131 (set (match_operand:DF 4 "register_operand" "")
6132 (mult:DF (match_dup 1) (match_dup 2)))]
6133 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6134 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6135 (set (match_dup 0) (minus:DF (match_dup 3)
6136 (mult:DF (match_dup 1) (match_dup 2))))]
6140 [(set (match_operand:SF 0 "register_operand" "=f")
6141 (minus:SF (match_operand:SF 3 "register_operand" "f")
6142 (mult:SF (match_operand:SF 1 "register_operand" "f")
6143 (match_operand:SF 2 "register_operand" "f"))))
6144 (set (match_operand:SF 4 "register_operand" "=&f")
6145 (mult:SF (match_dup 1) (match_dup 2)))]
6146 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6147 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6148 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6150 [(set_attr "type" "fpmuldbl")
6151 (set_attr "length" "8")])
6154 [(set (match_operand:SF 0 "register_operand" "")
6155 (minus:SF (match_operand:SF 3 "register_operand" "")
6156 (mult:SF (match_operand:SF 1 "register_operand" "")
6157 (match_operand:SF 2 "register_operand" ""))))
6158 (set (match_operand:SF 4 "register_operand" "")
6159 (mult:SF (match_dup 1) (match_dup 2)))]
6160 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6161 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6162 (set (match_dup 0) (minus:SF (match_dup 3)
6163 (mult:SF (match_dup 1) (match_dup 2))))]
6167 [(set (match_operand:DF 0 "register_operand" "=f")
6168 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6169 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6170 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6171 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6173 [(set_attr "type" "fpalu")
6174 (set_attr "length" "8")])
6177 [(set (match_operand:DF 0 "register_operand" "")
6178 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6179 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6180 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6181 [(set (match_dup 2) (abs:DF (match_dup 1)))
6182 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6186 [(set (match_operand:SF 0 "register_operand" "=f")
6187 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6188 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6189 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6190 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6192 [(set_attr "type" "fpalu")
6193 (set_attr "length" "8")])
6196 [(set (match_operand:SF 0 "register_operand" "")
6197 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6198 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6199 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6200 [(set (match_dup 2) (abs:SF (match_dup 1)))
6201 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6204 ;;- Shift instructions
6206 ;; Optimized special case of shifting.
6209 [(set (match_operand:SI 0 "register_operand" "=r")
6210 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6214 [(set_attr "type" "load")
6215 (set_attr "length" "4")])
6218 [(set (match_operand:SI 0 "register_operand" "=r")
6219 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6223 [(set_attr "type" "load")
6224 (set_attr "length" "4")])
6227 [(set (match_operand:SI 0 "register_operand" "=r")
6228 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6229 (match_operand:SI 3 "shadd_operand" ""))
6230 (match_operand:SI 1 "register_operand" "r")))]
6232 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6233 [(set_attr "type" "binary")
6234 (set_attr "length" "4")])
6237 [(set (match_operand:DI 0 "register_operand" "=r")
6238 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6239 (match_operand:DI 3 "shadd_operand" ""))
6240 (match_operand:DI 1 "register_operand" "r")))]
6242 "shladd,l %2,%O3,%1,%0"
6243 [(set_attr "type" "binary")
6244 (set_attr "length" "4")])
6246 (define_expand "ashlsi3"
6247 [(set (match_operand:SI 0 "register_operand" "")
6248 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6249 (match_operand:SI 2 "arith32_operand" "")))]
6253 if (GET_CODE (operands[2]) != CONST_INT)
6255 rtx temp = gen_reg_rtx (SImode);
6256 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6257 if (GET_CODE (operands[1]) == CONST_INT)
6258 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6260 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6263 /* Make sure both inputs are not constants,
6264 there are no patterns for that. */
6265 operands[1] = force_reg (SImode, operands[1]);
6269 [(set (match_operand:SI 0 "register_operand" "=r")
6270 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6271 (match_operand:SI 2 "const_int_operand" "n")))]
6273 "{zdep|depw,z} %1,%P2,%L2,%0"
6274 [(set_attr "type" "shift")
6275 (set_attr "length" "4")])
6277 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6278 ; Doing it like this makes slightly better code since reload can
6279 ; replace a register with a known value in range -16..15 with a
6280 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6281 ; but since we have no more CONST_OK... characters, that is not
6283 (define_insn "zvdep32"
6284 [(set (match_operand:SI 0 "register_operand" "=r,r")
6285 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6286 (minus:SI (const_int 31)
6287 (match_operand:SI 2 "register_operand" "q,q"))))]
6290 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6291 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6292 [(set_attr "type" "shift,shift")
6293 (set_attr "length" "4,4")])
6295 (define_insn "zvdep_imm32"
6296 [(set (match_operand:SI 0 "register_operand" "=r")
6297 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6298 (minus:SI (const_int 31)
6299 (match_operand:SI 2 "register_operand" "q"))))]
6303 int x = INTVAL (operands[1]);
6304 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6305 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6306 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6308 [(set_attr "type" "shift")
6309 (set_attr "length" "4")])
6311 (define_insn "vdepi_ior"
6312 [(set (match_operand:SI 0 "register_operand" "=r")
6313 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6314 (minus:SI (const_int 31)
6315 (match_operand:SI 2 "register_operand" "q")))
6316 (match_operand:SI 3 "register_operand" "0")))]
6317 ; accept ...0001...1, can this be generalized?
6318 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6321 int x = INTVAL (operands[1]);
6322 operands[2] = GEN_INT (exact_log2 (x + 1));
6323 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6325 [(set_attr "type" "shift")
6326 (set_attr "length" "4")])
6328 (define_insn "vdepi_and"
6329 [(set (match_operand:SI 0 "register_operand" "=r")
6330 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6331 (minus:SI (const_int 31)
6332 (match_operand:SI 2 "register_operand" "q")))
6333 (match_operand:SI 3 "register_operand" "0")))]
6334 ; this can be generalized...!
6335 "INTVAL (operands[1]) == -2"
6338 int x = INTVAL (operands[1]);
6339 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6340 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6342 [(set_attr "type" "shift")
6343 (set_attr "length" "4")])
6345 (define_expand "ashldi3"
6346 [(set (match_operand:DI 0 "register_operand" "")
6347 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6348 (match_operand:DI 2 "arith32_operand" "")))]
6352 if (GET_CODE (operands[2]) != CONST_INT)
6354 rtx temp = gen_reg_rtx (DImode);
6355 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6356 if (GET_CODE (operands[1]) == CONST_INT)
6357 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6359 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6362 /* Make sure both inputs are not constants,
6363 there are no patterns for that. */
6364 operands[1] = force_reg (DImode, operands[1]);
6368 [(set (match_operand:DI 0 "register_operand" "=r")
6369 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6370 (match_operand:DI 2 "const_int_operand" "n")))]
6372 "depd,z %1,%p2,%Q2,%0"
6373 [(set_attr "type" "shift")
6374 (set_attr "length" "4")])
6376 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6377 ; Doing it like this makes slightly better code since reload can
6378 ; replace a register with a known value in range -16..15 with a
6379 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6380 ; but since we have no more CONST_OK... characters, that is not
6382 (define_insn "zvdep64"
6383 [(set (match_operand:DI 0 "register_operand" "=r,r")
6384 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6385 (minus:DI (const_int 63)
6386 (match_operand:DI 2 "register_operand" "q,q"))))]
6389 depd,z %1,%%sar,64,%0
6390 depdi,z %1,%%sar,64,%0"
6391 [(set_attr "type" "shift,shift")
6392 (set_attr "length" "4,4")])
6394 (define_insn "zvdep_imm64"
6395 [(set (match_operand:DI 0 "register_operand" "=r")
6396 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6397 (minus:DI (const_int 63)
6398 (match_operand:DI 2 "register_operand" "q"))))]
6402 int x = INTVAL (operands[1]);
6403 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6404 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6405 return \"depdi,z %1,%%sar,%2,%0\";
6407 [(set_attr "type" "shift")
6408 (set_attr "length" "4")])
6411 [(set (match_operand:DI 0 "register_operand" "=r")
6412 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6413 (minus:DI (const_int 63)
6414 (match_operand:DI 2 "register_operand" "q")))
6415 (match_operand:DI 3 "register_operand" "0")))]
6416 ; accept ...0001...1, can this be generalized?
6417 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6420 int x = INTVAL (operands[1]);
6421 operands[2] = GEN_INT (exact_log2 (x + 1));
6422 return \"depdi -1,%%sar,%2,%0\";
6424 [(set_attr "type" "shift")
6425 (set_attr "length" "4")])
6428 [(set (match_operand:DI 0 "register_operand" "=r")
6429 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6430 (minus:DI (const_int 63)
6431 (match_operand:DI 2 "register_operand" "q")))
6432 (match_operand:DI 3 "register_operand" "0")))]
6433 ; this can be generalized...!
6434 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6437 int x = INTVAL (operands[1]);
6438 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6439 return \"depdi 0,%%sar,%2,%0\";
6441 [(set_attr "type" "shift")
6442 (set_attr "length" "4")])
6444 (define_expand "ashrsi3"
6445 [(set (match_operand:SI 0 "register_operand" "")
6446 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6447 (match_operand:SI 2 "arith32_operand" "")))]
6451 if (GET_CODE (operands[2]) != CONST_INT)
6453 rtx temp = gen_reg_rtx (SImode);
6454 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6455 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6461 [(set (match_operand:SI 0 "register_operand" "=r")
6462 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6463 (match_operand:SI 2 "const_int_operand" "n")))]
6465 "{extrs|extrw,s} %1,%P2,%L2,%0"
6466 [(set_attr "type" "shift")
6467 (set_attr "length" "4")])
6469 (define_insn "vextrs32"
6470 [(set (match_operand:SI 0 "register_operand" "=r")
6471 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6472 (minus:SI (const_int 31)
6473 (match_operand:SI 2 "register_operand" "q"))))]
6475 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6476 [(set_attr "type" "shift")
6477 (set_attr "length" "4")])
6479 (define_expand "ashrdi3"
6480 [(set (match_operand:DI 0 "register_operand" "")
6481 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6482 (match_operand:DI 2 "arith32_operand" "")))]
6486 if (GET_CODE (operands[2]) != CONST_INT)
6488 rtx temp = gen_reg_rtx (DImode);
6489 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6490 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6496 [(set (match_operand:DI 0 "register_operand" "=r")
6497 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6498 (match_operand:DI 2 "const_int_operand" "n")))]
6500 "extrd,s %1,%p2,%Q2,%0"
6501 [(set_attr "type" "shift")
6502 (set_attr "length" "4")])
6504 (define_insn "vextrs64"
6505 [(set (match_operand:DI 0 "register_operand" "=r")
6506 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6507 (minus:DI (const_int 63)
6508 (match_operand:DI 2 "register_operand" "q"))))]
6510 "extrd,s %1,%%sar,64,%0"
6511 [(set_attr "type" "shift")
6512 (set_attr "length" "4")])
6514 (define_insn "lshrsi3"
6515 [(set (match_operand:SI 0 "register_operand" "=r,r")
6516 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6517 (match_operand:SI 2 "arith32_operand" "q,n")))]
6520 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6521 {extru|extrw,u} %1,%P2,%L2,%0"
6522 [(set_attr "type" "shift")
6523 (set_attr "length" "4")])
6525 (define_insn "lshrdi3"
6526 [(set (match_operand:DI 0 "register_operand" "=r,r")
6527 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6528 (match_operand:DI 2 "arith32_operand" "q,n")))]
6531 shrpd %%r0,%1,%%sar,%0
6532 extrd,u %1,%p2,%Q2,%0"
6533 [(set_attr "type" "shift")
6534 (set_attr "length" "4")])
6536 (define_insn "rotrsi3"
6537 [(set (match_operand:SI 0 "register_operand" "=r,r")
6538 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6539 (match_operand:SI 2 "arith32_operand" "q,n")))]
6543 if (GET_CODE (operands[2]) == CONST_INT)
6545 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6546 return \"{shd|shrpw} %1,%1,%2,%0\";
6549 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6551 [(set_attr "type" "shift")
6552 (set_attr "length" "4")])
6554 (define_expand "rotlsi3"
6555 [(set (match_operand:SI 0 "register_operand" "")
6556 (rotate:SI (match_operand:SI 1 "register_operand" "")
6557 (match_operand:SI 2 "arith32_operand" "")))]
6561 if (GET_CODE (operands[2]) != CONST_INT)
6563 rtx temp = gen_reg_rtx (SImode);
6564 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6565 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6568 /* Else expand normally. */
6572 [(set (match_operand:SI 0 "register_operand" "=r")
6573 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6574 (match_operand:SI 2 "const_int_operand" "n")))]
6578 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6579 return \"{shd|shrpw} %1,%1,%2,%0\";
6581 [(set_attr "type" "shift")
6582 (set_attr "length" "4")])
6585 [(set (match_operand:SI 0 "register_operand" "=r")
6586 (match_operator:SI 5 "plus_xor_ior_operator"
6587 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6588 (match_operand:SI 3 "const_int_operand" "n"))
6589 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6590 (match_operand:SI 4 "const_int_operand" "n"))]))]
6591 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6592 "{shd|shrpw} %1,%2,%4,%0"
6593 [(set_attr "type" "shift")
6594 (set_attr "length" "4")])
6597 [(set (match_operand:SI 0 "register_operand" "=r")
6598 (match_operator:SI 5 "plus_xor_ior_operator"
6599 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6600 (match_operand:SI 4 "const_int_operand" "n"))
6601 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6602 (match_operand:SI 3 "const_int_operand" "n"))]))]
6603 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6604 "{shd|shrpw} %1,%2,%4,%0"
6605 [(set_attr "type" "shift")
6606 (set_attr "length" "4")])
6609 [(set (match_operand:SI 0 "register_operand" "=r")
6610 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6611 (match_operand:SI 2 "const_int_operand" ""))
6612 (match_operand:SI 3 "const_int_operand" "")))]
6613 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6616 int cnt = INTVAL (operands[2]) & 31;
6617 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6618 operands[2] = GEN_INT (31 - cnt);
6619 return \"{zdep|depw,z} %1,%2,%3,%0\";
6621 [(set_attr "type" "shift")
6622 (set_attr "length" "4")])
6624 ;; Unconditional and other jump instructions.
6626 ;; This can only be used in a leaf function, so we do
6627 ;; not need to use the PIC register when generating PIC code.
6628 (define_insn "return"
6632 "hppa_can_use_return_insn_p ()"
6636 return \"bve%* (%%r2)\";
6637 return \"bv%* %%r0(%%r2)\";
6639 [(set_attr "type" "branch")
6640 (set_attr "length" "4")])
6642 ;; Emit a different pattern for functions which have non-trivial
6643 ;; epilogues so as not to confuse jump and reorg.
6644 (define_insn "return_internal"
6652 return \"bve%* (%%r2)\";
6653 return \"bv%* %%r0(%%r2)\";
6655 [(set_attr "type" "branch")
6656 (set_attr "length" "4")])
6658 ;; This is used for eh returns which bypass the return stub.
6659 (define_insn "return_external_pic"
6661 (clobber (reg:SI 1))
6663 "!TARGET_NO_SPACE_REGS
6665 && flag_pic && current_function_calls_eh_return"
6666 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6667 [(set_attr "type" "branch")
6668 (set_attr "length" "12")])
6670 (define_expand "prologue"
6673 "hppa_expand_prologue ();DONE;")
6675 (define_expand "sibcall_epilogue"
6680 hppa_expand_epilogue ();
6684 (define_expand "epilogue"
6689 /* Try to use the trivial return first. Else use the full
6691 if (hppa_can_use_return_insn_p ())
6692 emit_jump_insn (gen_return ());
6697 hppa_expand_epilogue ();
6699 /* EH returns bypass the normal return stub. Thus, we must do an
6700 interspace branch to return from functions that call eh_return.
6701 This is only a problem for returns from shared code on ports
6702 using space registers. */
6703 if (!TARGET_NO_SPACE_REGS
6705 && flag_pic && current_function_calls_eh_return)
6706 x = gen_return_external_pic ();
6708 x = gen_return_internal ();
6715 ; Used by hppa_profile_hook to load the starting address of the current
6716 ; function; operand 1 contains the address of the label in operand 3
6717 (define_insn "load_offset_label_address"
6718 [(set (match_operand:SI 0 "register_operand" "=r")
6719 (plus:SI (match_operand:SI 1 "register_operand" "r")
6720 (minus:SI (match_operand:SI 2 "" "")
6721 (label_ref:SI (match_operand 3 "" "")))))]
6724 [(set_attr "type" "multi")
6725 (set_attr "length" "4")])
6727 ; Output a code label and load its address.
6728 (define_insn "lcla1"
6729 [(set (match_operand:SI 0 "register_operand" "=r")
6730 (label_ref:SI (match_operand 1 "" "")))
6735 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6736 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6737 CODE_LABEL_NUMBER (operands[1]));
6740 [(set_attr "type" "multi")
6741 (set_attr "length" "8")])
6743 (define_insn "lcla2"
6744 [(set (match_operand:SI 0 "register_operand" "=r")
6745 (label_ref:SI (match_operand 1 "" "")))
6750 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6751 CODE_LABEL_NUMBER (operands[1]));
6754 [(set_attr "type" "move")
6755 (set_attr "length" "4")])
6757 (define_insn "blockage"
6758 [(unspec_volatile [(const_int 2)] 0)]
6761 [(set_attr "length" "0")])
6764 [(set (pc) (label_ref (match_operand 0 "" "")))]
6768 /* An unconditional branch which can reach its target. */
6769 if (get_attr_length (insn) != 24
6770 && get_attr_length (insn) != 16)
6773 return output_lbranch (operands[0], insn);
6775 [(set_attr "type" "uncond_branch")
6776 (set_attr "pa_combine_type" "uncond_branch")
6777 (set (attr "length")
6778 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6779 (if_then_else (lt (abs (minus (match_dup 0)
6780 (plus (pc) (const_int 8))))
6784 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6786 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6791 ;;; Hope this is only within a function...
6792 (define_insn "indirect_jump"
6793 [(set (pc) (match_operand 0 "register_operand" "r"))]
6794 "GET_MODE (operands[0]) == word_mode"
6796 [(set_attr "type" "branch")
6797 (set_attr "length" "4")])
6799 ;;; This jump is used in branch tables where the insn length is fixed.
6800 ;;; The length of this insn is adjusted if the delay slot is not filled.
6801 (define_insn "short_jump"
6802 [(set (pc) (label_ref (match_operand 0 "" "")))
6806 [(set_attr "type" "btable_branch")
6807 (set_attr "length" "4")])
6809 ;; Subroutines of "casesi".
6810 ;; operand 0 is index
6811 ;; operand 1 is the minimum bound
6812 ;; operand 2 is the maximum bound - minimum bound + 1
6813 ;; operand 3 is CODE_LABEL for the table;
6814 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6816 (define_expand "casesi"
6817 [(match_operand:SI 0 "general_operand" "")
6818 (match_operand:SI 1 "const_int_operand" "")
6819 (match_operand:SI 2 "const_int_operand" "")
6820 (match_operand 3 "" "")
6821 (match_operand 4 "" "")]
6825 if (GET_CODE (operands[0]) != REG)
6826 operands[0] = force_reg (SImode, operands[0]);
6828 if (operands[1] != const0_rtx)
6830 rtx index = gen_reg_rtx (SImode);
6832 operands[1] = GEN_INT (-INTVAL (operands[1]));
6833 if (!INT_14_BITS (operands[1]))
6834 operands[1] = force_reg (SImode, operands[1]);
6835 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6836 operands[0] = index;
6839 /* In 64bit mode we must make sure to wipe the upper bits of the register
6840 just in case the addition overflowed or we had random bits in the
6841 high part of the register. */
6844 rtx index = gen_reg_rtx (DImode);
6846 emit_insn (gen_extendsidi2 (index, operands[0]));
6847 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6850 if (!INT_5_BITS (operands[2]))
6851 operands[2] = force_reg (SImode, operands[2]);
6853 /* This branch prevents us finding an insn for the delay slot of the
6854 following vectored branch. It might be possible to use the delay
6855 slot if an index value of -1 was used to transfer to the out-of-range
6856 label. In order to do this, we would have to output the -1 vector
6857 element after the delay insn. The casesi output code would have to
6858 check if the casesi insn is in a delay branch sequence and output
6859 the delay insn if one is found. If this was done, then it might
6860 then be worthwhile to split the casesi patterns to improve scheduling.
6861 However, it's not clear that all this extra complexity is worth
6863 emit_insn (gen_cmpsi (operands[0], operands[2]));
6864 emit_jump_insn (gen_bgtu (operands[4]));
6866 if (TARGET_BIG_SWITCH)
6870 rtx tmp1 = gen_reg_rtx (DImode);
6871 rtx tmp2 = gen_reg_rtx (DImode);
6873 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6878 rtx tmp1 = gen_reg_rtx (SImode);
6882 rtx tmp2 = gen_reg_rtx (SImode);
6884 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6888 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6892 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6896 ;;; The rtl for this pattern doesn't accurately describe what the insn
6897 ;;; actually does, particularly when case-vector elements are exploded
6898 ;;; in pa_reorg. However, the initial SET in these patterns must show
6899 ;;; the connection of the insn to the following jump table.
6900 (define_insn "casesi0"
6901 [(set (pc) (mem:SI (plus:SI
6902 (mult:SI (match_operand:SI 0 "register_operand" "r")
6904 (label_ref (match_operand 1 "" "")))))]
6906 "blr,n %0,%%r0\;nop"
6907 [(set_attr "type" "multi")
6908 (set_attr "length" "8")])
6910 ;;; 32-bit code, absolute branch table.
6911 (define_insn "casesi32"
6912 [(set (pc) (mem:SI (plus:SI
6913 (mult:SI (match_operand:SI 0 "register_operand" "r")
6915 (label_ref (match_operand 1 "" "")))))
6916 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6917 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6918 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6919 [(set_attr "type" "multi")
6920 (set_attr "length" "16")])
6922 ;;; 32-bit code, relative branch table.
6923 (define_insn "casesi32p"
6924 [(set (pc) (mem:SI (plus:SI
6925 (mult:SI (match_operand:SI 0 "register_operand" "r")
6927 (label_ref (match_operand 1 "" "")))))
6928 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6929 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6930 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6931 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6932 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6933 [(set_attr "type" "multi")
6934 (set (attr "length")
6935 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6939 ;;; 64-bit code, 32-bit relative branch table.
6940 (define_insn "casesi64p"
6941 [(set (pc) (mem:DI (plus:DI
6942 (mult:DI (sign_extend:DI
6943 (match_operand:SI 0 "register_operand" "r"))
6945 (label_ref (match_operand 1 "" "")))))
6946 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6947 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6948 "TARGET_64BIT && TARGET_BIG_SWITCH"
6949 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6950 add,l %2,%3,%3\;bv,n %%r0(%3)"
6951 [(set_attr "type" "multi")
6952 (set_attr "length" "24")])
6956 ;;- jump to subroutine
6958 (define_expand "call"
6959 [(parallel [(call (match_operand:SI 0 "" "")
6960 (match_operand 1 "" ""))
6961 (clobber (reg:SI 2))])]
6966 rtx nb = operands[1];
6968 if (TARGET_PORTABLE_RUNTIME)
6969 op = force_reg (SImode, XEXP (operands[0], 0));
6971 op = XEXP (operands[0], 0);
6975 if (!virtuals_instantiated)
6976 emit_move_insn (arg_pointer_rtx,
6977 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6981 /* The loop pass can generate new libcalls after the virtual
6982 registers are instantiated when fpregs are disabled because
6983 the only method that we have for doing DImode multiplication
6984 is with a libcall. This could be trouble if we haven't
6985 allocated enough space for the outgoing arguments. */
6986 if (INTVAL (nb) > current_function_outgoing_args_size)
6989 emit_move_insn (arg_pointer_rtx,
6990 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6991 GEN_INT (STACK_POINTER_OFFSET + 64)));
6995 /* Use two different patterns for calls to explicitly named functions
6996 and calls through function pointers. This is necessary as these two
6997 types of calls use different calling conventions, and CSE might try
6998 to change the named call into an indirect call in some cases (using
6999 two patterns keeps CSE from performing this optimization).
7001 We now use even more call patterns as there was a subtle bug in
7002 attempting to restore the pic register after a call using a simple
7003 move insn. During reload, a instruction involving a pseudo register
7004 with no explicit dependence on the PIC register can be converted
7005 to an equivalent load from memory using the PIC register. If we
7006 emit a simple move to restore the PIC register in the initial rtl
7007 generation, then it can potentially be repositioned during scheduling.
7008 and an instruction that eventually uses the PIC register may end up
7009 between the call and the PIC register restore.
7011 This only worked because there is a post call group of instructions
7012 that are scheduled with the call. These instructions are included
7013 in the same basic block as the call. However, calls can throw in
7014 C++ code and a basic block has to terminate at the call if the call
7015 can throw. This results in the PIC register restore being scheduled
7016 independently from the call. So, we now hide the save and restore
7017 of the PIC register in the call pattern until after reload. Then,
7018 we split the moves out. A small side benefit is that we now don't
7019 need to have a use of the PIC register in the return pattern and
7020 the final save/restore operation is not needed.
7022 I elected to just clobber %r4 in the PIC patterns and use it instead
7023 of trying to force hppa_pic_save_rtx () to a callee saved register.
7024 This might have required a new register class and constraint. It
7025 was also simpler to just handle the restore from a register than a
7029 if (GET_CODE (op) == SYMBOL_REF)
7030 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7033 op = force_reg (word_mode, op);
7034 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7039 if (GET_CODE (op) == SYMBOL_REF)
7042 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7044 call_insn = emit_call_insn (gen_call_symref (op, nb));
7048 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7050 emit_move_insn (tmpreg, force_reg (word_mode, op));
7052 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7054 call_insn = emit_call_insn (gen_call_reg (nb));
7061 ;; We use function calls to set the attribute length of calls and millicode
7062 ;; calls. This is necessary because of the large variety of call sequences.
7063 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7064 ;; we need the same calculation in several places, maintenance becomes a
7067 ;; However, this has a subtle impact on branch shortening. When the
7068 ;; expression used to set the length attribute of an instruction depends
7069 ;; on a relative address (e.g., pc or a branch address), genattrtab
7070 ;; notes that the insn's length is variable, and attempts to determine a
7071 ;; worst-case default length and code to compute an insn's current length.
7073 ;; The use of a function call hides the variable dependence of our calls
7074 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7075 ;; as variable and it only generates code for the default case using our
7076 ;; function call. Because of this, calls and millicode calls have a fixed
7077 ;; length in the branch shortening pass, and some branches will use a longer
7078 ;; code sequence than necessary. However, the length of any given call
7079 ;; will still reflect its final code location and it may be shorter than
7080 ;; the initial length estimate.
7082 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7083 ;; in the set. However, when genattrtab hits a function call in its attempt
7084 ;; to compute the default length, it marks the result as unknown and sets
7085 ;; the default result to MAX_INT ;-( One possible fix that would allow
7086 ;; calls to participate in branch shortening would be to make the call to
7087 ;; insn_default_length a target option. Then, we could massage unknown
7088 ;; results. Another fix might be to change genattrtab so that it just does
7089 ;; the call in the variable case as it already does for the fixed case.
7091 (define_insn "call_symref"
7092 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7093 (match_operand 1 "" "i"))
7094 (clobber (reg:SI 1))
7095 (clobber (reg:SI 2))
7096 (use (const_int 0))]
7097 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7100 output_arg_descriptor (insn);
7101 return output_call (insn, operands[0], 0);
7103 [(set_attr "type" "call")
7104 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7106 (define_insn "call_symref_pic"
7107 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7108 (match_operand 1 "" "i"))
7109 (clobber (reg:SI 1))
7110 (clobber (reg:SI 2))
7111 (clobber (reg:SI 4))
7113 (use (const_int 0))]
7114 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7117 output_arg_descriptor (insn);
7118 return output_call (insn, operands[0], 0);
7120 [(set_attr "type" "call")
7121 (set (attr "length")
7122 (plus (symbol_ref "attr_length_call (insn, 0)")
7123 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7125 ;; Split out the PIC register save and restore after reload. This is
7126 ;; done only if the function returns. As the split is done after reload,
7127 ;; there are some situations in which we unnecessarily save and restore
7128 ;; %r4. This happens when there is a single call and the PIC register
7129 ;; is "dead" after the call. This isn't easy to fix as the usage of
7130 ;; the PIC register isn't completely determined until the reload pass.
7132 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7133 (match_operand 1 "" ""))
7134 (clobber (reg:SI 1))
7135 (clobber (reg:SI 2))
7136 (clobber (reg:SI 4))
7138 (use (const_int 0))])]
7139 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7141 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7142 [(set (reg:SI 4) (reg:SI 19))
7143 (parallel [(call (mem:SI (match_dup 0))
7145 (clobber (reg:SI 1))
7146 (clobber (reg:SI 2))
7148 (use (const_int 0))])
7149 (set (reg:SI 19) (reg:SI 4))]
7152 ;; Remove the clobber of register 4 when optimizing. This has to be
7153 ;; done with a peephole optimization rather than a split because the
7154 ;; split sequence for a call must be longer than one instruction.
7156 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7157 (match_operand 1 "" ""))
7158 (clobber (reg:SI 1))
7159 (clobber (reg:SI 2))
7160 (clobber (reg:SI 4))
7162 (use (const_int 0))])]
7163 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7164 [(parallel [(call (mem:SI (match_dup 0))
7166 (clobber (reg:SI 1))
7167 (clobber (reg:SI 2))
7169 (use (const_int 0))])]
7172 (define_insn "*call_symref_pic_post_reload"
7173 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7174 (match_operand 1 "" "i"))
7175 (clobber (reg:SI 1))
7176 (clobber (reg:SI 2))
7178 (use (const_int 0))]
7179 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7182 output_arg_descriptor (insn);
7183 return output_call (insn, operands[0], 0);
7185 [(set_attr "type" "call")
7186 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7188 ;; This pattern is split if it is necessary to save and restore the
7190 (define_insn "call_symref_64bit"
7191 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7192 (match_operand 1 "" "i"))
7193 (clobber (reg:DI 1))
7194 (clobber (reg:DI 2))
7195 (clobber (reg:DI 4))
7198 (use (const_int 0))]
7202 output_arg_descriptor (insn);
7203 return output_call (insn, operands[0], 0);
7205 [(set_attr "type" "call")
7206 (set (attr "length")
7207 (plus (symbol_ref "attr_length_call (insn, 0)")
7208 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7210 ;; Split out the PIC register save and restore after reload. This is
7211 ;; done only if the function returns. As the split is done after reload,
7212 ;; there are some situations in which we unnecessarily save and restore
7213 ;; %r4. This happens when there is a single call and the PIC register
7214 ;; is "dead" after the call. This isn't easy to fix as the usage of
7215 ;; the PIC register isn't completely determined until the reload pass.
7217 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7218 (match_operand 1 "" ""))
7219 (clobber (reg:DI 1))
7220 (clobber (reg:DI 2))
7221 (clobber (reg:DI 4))
7224 (use (const_int 0))])]
7227 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7228 [(set (reg:DI 4) (reg:DI 27))
7229 (parallel [(call (mem:SI (match_dup 0))
7231 (clobber (reg:DI 1))
7232 (clobber (reg:DI 2))
7235 (use (const_int 0))])
7236 (set (reg:DI 27) (reg:DI 4))]
7239 ;; Remove the clobber of register 4 when optimizing. This has to be
7240 ;; done with a peephole optimization rather than a split because the
7241 ;; split sequence for a call must be longer than one instruction.
7243 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7244 (match_operand 1 "" ""))
7245 (clobber (reg:DI 1))
7246 (clobber (reg:DI 2))
7247 (clobber (reg:DI 4))
7250 (use (const_int 0))])]
7251 "TARGET_64BIT && reload_completed"
7252 [(parallel [(call (mem:SI (match_dup 0))
7254 (clobber (reg:DI 1))
7255 (clobber (reg:DI 2))
7258 (use (const_int 0))])]
7261 (define_insn "*call_symref_64bit_post_reload"
7262 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7263 (match_operand 1 "" "i"))
7264 (clobber (reg:DI 1))
7265 (clobber (reg:DI 2))
7268 (use (const_int 0))]
7272 output_arg_descriptor (insn);
7273 return output_call (insn, operands[0], 0);
7275 [(set_attr "type" "call")
7276 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7278 (define_insn "call_reg"
7279 [(call (mem:SI (reg:SI 22))
7280 (match_operand 0 "" "i"))
7281 (clobber (reg:SI 1))
7282 (clobber (reg:SI 2))
7283 (use (const_int 1))]
7287 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7289 [(set_attr "type" "dyncall")
7290 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7292 ;; This pattern is split if it is necessary to save and restore the
7294 (define_insn "call_reg_pic"
7295 [(call (mem:SI (reg:SI 22))
7296 (match_operand 0 "" "i"))
7297 (clobber (reg:SI 1))
7298 (clobber (reg:SI 2))
7299 (clobber (reg:SI 4))
7301 (use (const_int 1))]
7305 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7307 [(set_attr "type" "dyncall")
7308 (set (attr "length")
7309 (plus (symbol_ref "attr_length_indirect_call (insn)")
7310 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7312 ;; Split out the PIC register save and restore after reload. This is
7313 ;; done only if the function returns. As the split is done after reload,
7314 ;; there are some situations in which we unnecessarily save and restore
7315 ;; %r4. This happens when there is a single call and the PIC register
7316 ;; is "dead" after the call. This isn't easy to fix as the usage of
7317 ;; the PIC register isn't completely determined until the reload pass.
7319 [(parallel [(call (mem:SI (reg:SI 22))
7320 (match_operand 0 "" ""))
7321 (clobber (reg:SI 1))
7322 (clobber (reg:SI 2))
7323 (clobber (reg:SI 4))
7325 (use (const_int 1))])]
7328 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7329 [(set (reg:SI 4) (reg:SI 19))
7330 (parallel [(call (mem:SI (reg:SI 22))
7332 (clobber (reg:SI 1))
7333 (clobber (reg:SI 2))
7335 (use (const_int 1))])
7336 (set (reg:SI 19) (reg:SI 4))]
7339 ;; Remove the clobber of register 4 when optimizing. This has to be
7340 ;; done with a peephole optimization rather than a split because the
7341 ;; split sequence for a call must be longer than one instruction.
7343 [(parallel [(call (mem:SI (reg:SI 22))
7344 (match_operand 0 "" ""))
7345 (clobber (reg:SI 1))
7346 (clobber (reg:SI 2))
7347 (clobber (reg:SI 4))
7349 (use (const_int 1))])]
7350 "!TARGET_64BIT && reload_completed"
7351 [(parallel [(call (mem:SI (reg:SI 22))
7353 (clobber (reg:SI 1))
7354 (clobber (reg:SI 2))
7356 (use (const_int 1))])]
7359 (define_insn "*call_reg_pic_post_reload"
7360 [(call (mem:SI (reg:SI 22))
7361 (match_operand 0 "" "i"))
7362 (clobber (reg:SI 1))
7363 (clobber (reg:SI 2))
7365 (use (const_int 1))]
7369 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7371 [(set_attr "type" "dyncall")
7372 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7374 ;; This pattern is split if it is necessary to save and restore the
7376 (define_insn "call_reg_64bit"
7377 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7378 (match_operand 1 "" "i"))
7379 (clobber (reg:DI 2))
7380 (clobber (reg:DI 4))
7383 (use (const_int 1))]
7387 return output_indirect_call (insn, operands[0]);
7389 [(set_attr "type" "dyncall")
7390 (set (attr "length")
7391 (plus (symbol_ref "attr_length_indirect_call (insn)")
7392 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7394 ;; Split out the PIC register save and restore after reload. This is
7395 ;; done only if the function returns. As the split is done after reload,
7396 ;; there are some situations in which we unnecessarily save and restore
7397 ;; %r4. This happens when there is a single call and the PIC register
7398 ;; is "dead" after the call. This isn't easy to fix as the usage of
7399 ;; the PIC register isn't completely determined until the reload pass.
7401 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7402 (match_operand 1 "" ""))
7403 (clobber (reg:DI 2))
7404 (clobber (reg:DI 4))
7407 (use (const_int 1))])]
7410 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7411 [(set (reg:DI 4) (reg:DI 27))
7412 (parallel [(call (mem:SI (match_dup 0))
7414 (clobber (reg:DI 2))
7417 (use (const_int 1))])
7418 (set (reg:DI 27) (reg:DI 4))]
7421 ;; Remove the clobber of register 4 when optimizing. This has to be
7422 ;; done with a peephole optimization rather than a split because the
7423 ;; split sequence for a call must be longer than one instruction.
7425 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7426 (match_operand 1 "" ""))
7427 (clobber (reg:DI 2))
7428 (clobber (reg:DI 4))
7431 (use (const_int 1))])]
7432 "TARGET_64BIT && reload_completed"
7433 [(parallel [(call (mem:SI (match_dup 0))
7435 (clobber (reg:DI 2))
7438 (use (const_int 1))])]
7441 (define_insn "*call_reg_64bit_post_reload"
7442 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7443 (match_operand 1 "" "i"))
7444 (clobber (reg:DI 2))
7447 (use (const_int 1))]
7451 return output_indirect_call (insn, operands[0]);
7453 [(set_attr "type" "dyncall")
7454 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7456 (define_expand "call_value"
7457 [(parallel [(set (match_operand 0 "" "")
7458 (call (match_operand:SI 1 "" "")
7459 (match_operand 2 "" "")))
7460 (clobber (reg:SI 2))])]
7465 rtx dst = operands[0];
7466 rtx nb = operands[2];
7468 if (TARGET_PORTABLE_RUNTIME)
7469 op = force_reg (SImode, XEXP (operands[1], 0));
7471 op = XEXP (operands[1], 0);
7475 if (!virtuals_instantiated)
7476 emit_move_insn (arg_pointer_rtx,
7477 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7481 /* The loop pass can generate new libcalls after the virtual
7482 registers are instantiated when fpregs are disabled because
7483 the only method that we have for doing DImode multiplication
7484 is with a libcall. This could be trouble if we haven't
7485 allocated enough space for the outgoing arguments. */
7486 if (INTVAL (nb) > current_function_outgoing_args_size)
7489 emit_move_insn (arg_pointer_rtx,
7490 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7491 GEN_INT (STACK_POINTER_OFFSET + 64)));
7495 /* Use two different patterns for calls to explicitly named functions
7496 and calls through function pointers. This is necessary as these two
7497 types of calls use different calling conventions, and CSE might try
7498 to change the named call into an indirect call in some cases (using
7499 two patterns keeps CSE from performing this optimization).
7501 We now use even more call patterns as there was a subtle bug in
7502 attempting to restore the pic register after a call using a simple
7503 move insn. During reload, a instruction involving a pseudo register
7504 with no explicit dependence on the PIC register can be converted
7505 to an equivalent load from memory using the PIC register. If we
7506 emit a simple move to restore the PIC register in the initial rtl
7507 generation, then it can potentially be repositioned during scheduling.
7508 and an instruction that eventually uses the PIC register may end up
7509 between the call and the PIC register restore.
7511 This only worked because there is a post call group of instructions
7512 that are scheduled with the call. These instructions are included
7513 in the same basic block as the call. However, calls can throw in
7514 C++ code and a basic block has to terminate at the call if the call
7515 can throw. This results in the PIC register restore being scheduled
7516 independently from the call. So, we now hide the save and restore
7517 of the PIC register in the call pattern until after reload. Then,
7518 we split the moves out. A small side benefit is that we now don't
7519 need to have a use of the PIC register in the return pattern and
7520 the final save/restore operation is not needed.
7522 I elected to just clobber %r4 in the PIC patterns and use it instead
7523 of trying to force hppa_pic_save_rtx () to a callee saved register.
7524 This might have required a new register class and constraint. It
7525 was also simpler to just handle the restore from a register than a
7529 if (GET_CODE (op) == SYMBOL_REF)
7530 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7533 op = force_reg (word_mode, op);
7534 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7539 if (GET_CODE (op) == SYMBOL_REF)
7542 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7544 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7548 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7550 emit_move_insn (tmpreg, force_reg (word_mode, op));
7552 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7554 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7561 (define_insn "call_val_symref"
7562 [(set (match_operand 0 "" "")
7563 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7564 (match_operand 2 "" "i")))
7565 (clobber (reg:SI 1))
7566 (clobber (reg:SI 2))
7567 (use (const_int 0))]
7568 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7571 output_arg_descriptor (insn);
7572 return output_call (insn, operands[1], 0);
7574 [(set_attr "type" "call")
7575 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7577 (define_insn "call_val_symref_pic"
7578 [(set (match_operand 0 "" "")
7579 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7580 (match_operand 2 "" "i")))
7581 (clobber (reg:SI 1))
7582 (clobber (reg:SI 2))
7583 (clobber (reg:SI 4))
7585 (use (const_int 0))]
7586 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7589 output_arg_descriptor (insn);
7590 return output_call (insn, operands[1], 0);
7592 [(set_attr "type" "call")
7593 (set (attr "length")
7594 (plus (symbol_ref "attr_length_call (insn, 0)")
7595 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7597 ;; Split out the PIC register save and restore after reload. This is
7598 ;; done only if the function returns. As the split is done after reload,
7599 ;; there are some situations in which we unnecessarily save and restore
7600 ;; %r4. This happens when there is a single call and the PIC register
7601 ;; is "dead" after the call. This isn't easy to fix as the usage of
7602 ;; the PIC register isn't completely determined until the reload pass.
7604 [(parallel [(set (match_operand 0 "" "")
7605 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7606 (match_operand 2 "" "")))
7607 (clobber (reg:SI 1))
7608 (clobber (reg:SI 2))
7609 (clobber (reg:SI 4))
7611 (use (const_int 0))])]
7612 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7614 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7615 [(set (reg:SI 4) (reg:SI 19))
7616 (parallel [(set (match_dup 0)
7617 (call (mem:SI (match_dup 1))
7619 (clobber (reg:SI 1))
7620 (clobber (reg:SI 2))
7622 (use (const_int 0))])
7623 (set (reg:SI 19) (reg:SI 4))]
7626 ;; Remove the clobber of register 4 when optimizing. This has to be
7627 ;; done with a peephole optimization rather than a split because the
7628 ;; split sequence for a call must be longer than one instruction.
7630 [(parallel [(set (match_operand 0 "" "")
7631 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7632 (match_operand 2 "" "")))
7633 (clobber (reg:SI 1))
7634 (clobber (reg:SI 2))
7635 (clobber (reg:SI 4))
7637 (use (const_int 0))])]
7638 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7639 [(parallel [(set (match_dup 0)
7640 (call (mem:SI (match_dup 1))
7642 (clobber (reg:SI 1))
7643 (clobber (reg:SI 2))
7645 (use (const_int 0))])]
7648 (define_insn "*call_val_symref_pic_post_reload"
7649 [(set (match_operand 0 "" "")
7650 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7651 (match_operand 2 "" "i")))
7652 (clobber (reg:SI 1))
7653 (clobber (reg:SI 2))
7655 (use (const_int 0))]
7656 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7659 output_arg_descriptor (insn);
7660 return output_call (insn, operands[1], 0);
7662 [(set_attr "type" "call")
7663 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7665 ;; This pattern is split if it is necessary to save and restore the
7667 (define_insn "call_val_symref_64bit"
7668 [(set (match_operand 0 "" "")
7669 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7670 (match_operand 2 "" "i")))
7671 (clobber (reg:DI 1))
7672 (clobber (reg:DI 2))
7673 (clobber (reg:DI 4))
7676 (use (const_int 0))]
7680 output_arg_descriptor (insn);
7681 return output_call (insn, operands[1], 0);
7683 [(set_attr "type" "call")
7684 (set (attr "length")
7685 (plus (symbol_ref "attr_length_call (insn, 0)")
7686 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7688 ;; Split out the PIC register save and restore after reload. This is
7689 ;; done only if the function returns. As the split is done after reload,
7690 ;; there are some situations in which we unnecessarily save and restore
7691 ;; %r4. This happens when there is a single call and the PIC register
7692 ;; is "dead" after the call. This isn't easy to fix as the usage of
7693 ;; the PIC register isn't completely determined until the reload pass.
7695 [(parallel [(set (match_operand 0 "" "")
7696 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7697 (match_operand 2 "" "")))
7698 (clobber (reg:DI 1))
7699 (clobber (reg:DI 2))
7700 (clobber (reg:DI 4))
7703 (use (const_int 0))])]
7706 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7707 [(set (reg:DI 4) (reg:DI 27))
7708 (parallel [(set (match_dup 0)
7709 (call (mem:SI (match_dup 1))
7711 (clobber (reg:DI 1))
7712 (clobber (reg:DI 2))
7715 (use (const_int 0))])
7716 (set (reg:DI 27) (reg:DI 4))]
7719 ;; Remove the clobber of register 4 when optimizing. This has to be
7720 ;; done with a peephole optimization rather than a split because the
7721 ;; split sequence for a call must be longer than one instruction.
7723 [(parallel [(set (match_operand 0 "" "")
7724 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7725 (match_operand 2 "" "")))
7726 (clobber (reg:DI 1))
7727 (clobber (reg:DI 2))
7728 (clobber (reg:DI 4))
7731 (use (const_int 0))])]
7732 "TARGET_64BIT && reload_completed"
7733 [(parallel [(set (match_dup 0)
7734 (call (mem:SI (match_dup 1))
7736 (clobber (reg:DI 1))
7737 (clobber (reg:DI 2))
7740 (use (const_int 0))])]
7743 (define_insn "*call_val_symref_64bit_post_reload"
7744 [(set (match_operand 0 "" "")
7745 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7746 (match_operand 2 "" "i")))
7747 (clobber (reg:DI 1))
7748 (clobber (reg:DI 2))
7751 (use (const_int 0))]
7755 output_arg_descriptor (insn);
7756 return output_call (insn, operands[1], 0);
7758 [(set_attr "type" "call")
7759 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7761 (define_insn "call_val_reg"
7762 [(set (match_operand 0 "" "")
7763 (call (mem:SI (reg:SI 22))
7764 (match_operand 1 "" "i")))
7765 (clobber (reg:SI 1))
7766 (clobber (reg:SI 2))
7767 (use (const_int 1))]
7771 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7773 [(set_attr "type" "dyncall")
7774 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7776 ;; This pattern is split if it is necessary to save and restore the
7778 (define_insn "call_val_reg_pic"
7779 [(set (match_operand 0 "" "")
7780 (call (mem:SI (reg:SI 22))
7781 (match_operand 1 "" "i")))
7782 (clobber (reg:SI 1))
7783 (clobber (reg:SI 2))
7784 (clobber (reg:SI 4))
7786 (use (const_int 1))]
7790 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7792 [(set_attr "type" "dyncall")
7793 (set (attr "length")
7794 (plus (symbol_ref "attr_length_indirect_call (insn)")
7795 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7797 ;; Split out the PIC register save and restore after reload. This is
7798 ;; done only if the function returns. As the split is done after reload,
7799 ;; there are some situations in which we unnecessarily save and restore
7800 ;; %r4. This happens when there is a single call and the PIC register
7801 ;; is "dead" after the call. This isn't easy to fix as the usage of
7802 ;; the PIC register isn't completely determined until the reload pass.
7804 [(parallel [(set (match_operand 0 "" "")
7805 (call (mem:SI (reg:SI 22))
7806 (match_operand 1 "" "")))
7807 (clobber (reg:SI 1))
7808 (clobber (reg:SI 2))
7809 (clobber (reg:SI 4))
7811 (use (const_int 1))])]
7814 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7815 [(set (reg:SI 4) (reg:SI 19))
7816 (parallel [(set (match_dup 0)
7817 (call (mem:SI (reg:SI 22))
7819 (clobber (reg:SI 1))
7820 (clobber (reg:SI 2))
7822 (use (const_int 1))])
7823 (set (reg:SI 19) (reg:SI 4))]
7826 ;; Remove the clobber of register 4 when optimizing. This has to be
7827 ;; done with a peephole optimization rather than a split because the
7828 ;; split sequence for a call must be longer than one instruction.
7830 [(parallel [(set (match_operand 0 "" "")
7831 (call (mem:SI (reg:SI 22))
7832 (match_operand 1 "" "")))
7833 (clobber (reg:SI 1))
7834 (clobber (reg:SI 2))
7835 (clobber (reg:SI 4))
7837 (use (const_int 1))])]
7838 "!TARGET_64BIT && reload_completed"
7839 [(parallel [(set (match_dup 0)
7840 (call (mem:SI (reg:SI 22))
7842 (clobber (reg:SI 1))
7843 (clobber (reg:SI 2))
7845 (use (const_int 1))])]
7848 (define_insn "*call_val_reg_pic_post_reload"
7849 [(set (match_operand 0 "" "")
7850 (call (mem:SI (reg:SI 22))
7851 (match_operand 1 "" "i")))
7852 (clobber (reg:SI 1))
7853 (clobber (reg:SI 2))
7855 (use (const_int 1))]
7859 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7861 [(set_attr "type" "dyncall")
7862 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7864 ;; This pattern is split if it is necessary to save and restore the
7866 (define_insn "call_val_reg_64bit"
7867 [(set (match_operand 0 "" "")
7868 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7869 (match_operand 2 "" "i")))
7870 (clobber (reg:DI 2))
7871 (clobber (reg:DI 4))
7874 (use (const_int 1))]
7878 return output_indirect_call (insn, operands[1]);
7880 [(set_attr "type" "dyncall")
7881 (set (attr "length")
7882 (plus (symbol_ref "attr_length_indirect_call (insn)")
7883 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7885 ;; Split out the PIC register save and restore after reload. This is
7886 ;; done only if the function returns. As the split is done after reload,
7887 ;; there are some situations in which we unnecessarily save and restore
7888 ;; %r4. This happens when there is a single call and the PIC register
7889 ;; is "dead" after the call. This isn't easy to fix as the usage of
7890 ;; the PIC register isn't completely determined until the reload pass.
7892 [(parallel [(set (match_operand 0 "" "")
7893 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7894 (match_operand 2 "" "")))
7895 (clobber (reg:DI 2))
7896 (clobber (reg:DI 4))
7899 (use (const_int 1))])]
7902 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7903 [(set (reg:DI 4) (reg:DI 27))
7904 (parallel [(set (match_dup 0)
7905 (call (mem:SI (match_dup 1))
7907 (clobber (reg:DI 2))
7910 (use (const_int 1))])
7911 (set (reg:DI 27) (reg:DI 4))]
7914 ;; Remove the clobber of register 4 when optimizing. This has to be
7915 ;; done with a peephole optimization rather than a split because the
7916 ;; split sequence for a call must be longer than one instruction.
7918 [(parallel [(set (match_operand 0 "" "")
7919 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7920 (match_operand 2 "" "")))
7921 (clobber (reg:DI 2))
7922 (clobber (reg:DI 4))
7925 (use (const_int 1))])]
7926 "TARGET_64BIT && reload_completed"
7927 [(parallel [(set (match_dup 0)
7928 (call (mem:SI (match_dup 1))
7930 (clobber (reg:DI 2))
7933 (use (const_int 1))])]
7936 (define_insn "*call_val_reg_64bit_post_reload"
7937 [(set (match_operand 0 "" "")
7938 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7939 (match_operand 2 "" "i")))
7940 (clobber (reg:DI 2))
7943 (use (const_int 1))]
7947 return output_indirect_call (insn, operands[1]);
7949 [(set_attr "type" "dyncall")
7950 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7952 ;; Call subroutine returning any type.
7954 (define_expand "untyped_call"
7955 [(parallel [(call (match_operand 0 "" "")
7957 (match_operand 1 "" "")
7958 (match_operand 2 "" "")])]
7964 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7966 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7968 rtx set = XVECEXP (operands[2], 0, i);
7969 emit_move_insn (SET_DEST (set), SET_SRC (set));
7972 /* The optimizer does not know that the call sets the function value
7973 registers we stored in the result block. We avoid problems by
7974 claiming that all hard registers are used and clobbered at this
7976 emit_insn (gen_blockage ());
7981 (define_expand "sibcall"
7982 [(call (match_operand:SI 0 "" "")
7983 (match_operand 1 "" ""))]
7984 "!TARGET_PORTABLE_RUNTIME"
7988 rtx nb = operands[1];
7990 op = XEXP (operands[0], 0);
7994 if (!virtuals_instantiated)
7995 emit_move_insn (arg_pointer_rtx,
7996 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8000 /* The loop pass can generate new libcalls after the virtual
8001 registers are instantiated when fpregs are disabled because
8002 the only method that we have for doing DImode multiplication
8003 is with a libcall. This could be trouble if we haven't
8004 allocated enough space for the outgoing arguments. */
8005 if (INTVAL (nb) > current_function_outgoing_args_size)
8008 emit_move_insn (arg_pointer_rtx,
8009 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8010 GEN_INT (STACK_POINTER_OFFSET + 64)));
8014 /* Indirect sibling calls are not allowed. */
8016 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8018 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8020 call_insn = emit_call_insn (call_insn);
8023 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8025 /* We don't have to restore the PIC register. */
8027 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8032 (define_insn "sibcall_internal_symref"
8033 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8034 (match_operand 1 "" "i"))
8035 (clobber (reg:SI 1))
8037 (use (const_int 0))]
8038 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8041 output_arg_descriptor (insn);
8042 return output_call (insn, operands[0], 1);
8044 [(set_attr "type" "call")
8045 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8047 (define_insn "sibcall_internal_symref_64bit"
8048 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8049 (match_operand 1 "" "i"))
8050 (clobber (reg:DI 1))
8052 (use (const_int 0))]
8056 output_arg_descriptor (insn);
8057 return output_call (insn, operands[0], 1);
8059 [(set_attr "type" "call")
8060 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8062 (define_expand "sibcall_value"
8063 [(set (match_operand 0 "" "")
8064 (call (match_operand:SI 1 "" "")
8065 (match_operand 2 "" "")))]
8066 "!TARGET_PORTABLE_RUNTIME"
8070 rtx nb = operands[1];
8072 op = XEXP (operands[1], 0);
8076 if (!virtuals_instantiated)
8077 emit_move_insn (arg_pointer_rtx,
8078 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8082 /* The loop pass can generate new libcalls after the virtual
8083 registers are instantiated when fpregs are disabled because
8084 the only method that we have for doing DImode multiplication
8085 is with a libcall. This could be trouble if we haven't
8086 allocated enough space for the outgoing arguments. */
8087 if (INTVAL (nb) > current_function_outgoing_args_size)
8090 emit_move_insn (arg_pointer_rtx,
8091 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8092 GEN_INT (STACK_POINTER_OFFSET + 64)));
8096 /* Indirect sibling calls are not allowed. */
8099 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8102 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8104 call_insn = emit_call_insn (call_insn);
8107 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8109 /* We don't have to restore the PIC register. */
8111 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8116 (define_insn "sibcall_value_internal_symref"
8117 [(set (match_operand 0 "" "")
8118 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8119 (match_operand 2 "" "i")))
8120 (clobber (reg:SI 1))
8122 (use (const_int 0))]
8123 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8126 output_arg_descriptor (insn);
8127 return output_call (insn, operands[1], 1);
8129 [(set_attr "type" "call")
8130 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8132 (define_insn "sibcall_value_internal_symref_64bit"
8133 [(set (match_operand 0 "" "")
8134 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8135 (match_operand 2 "" "i")))
8136 (clobber (reg:DI 1))
8138 (use (const_int 0))]
8142 output_arg_descriptor (insn);
8143 return output_call (insn, operands[1], 1);
8145 [(set_attr "type" "call")
8146 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8152 [(set_attr "type" "move")
8153 (set_attr "length" "4")])
8155 ;; These are just placeholders so we know where branch tables
8157 (define_insn "begin_brtab"
8162 /* Only GAS actually supports this pseudo-op. */
8164 return \".begin_brtab\";
8168 [(set_attr "type" "move")
8169 (set_attr "length" "0")])
8171 (define_insn "end_brtab"
8176 /* Only GAS actually supports this pseudo-op. */
8178 return \".end_brtab\";
8182 [(set_attr "type" "move")
8183 (set_attr "length" "0")])
8185 ;;; EH does longjmp's from and within the data section. Thus,
8186 ;;; an interspace branch is required for the longjmp implementation.
8187 ;;; Registers r1 and r2 are used as scratch registers for the jump
8189 (define_expand "interspace_jump"
8191 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8192 (clobber (match_dup 1))])]
8196 operands[1] = gen_rtx_REG (word_mode, 2);
8200 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8201 (clobber (reg:SI 2))]
8202 "TARGET_PA_20 && !TARGET_64BIT"
8204 [(set_attr "type" "branch")
8205 (set_attr "length" "4")])
8208 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8209 (clobber (reg:SI 2))]
8210 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8212 [(set_attr "type" "branch")
8213 (set_attr "length" "4")])
8216 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8217 (clobber (reg:SI 2))]
8219 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8220 [(set_attr "type" "branch")
8221 (set_attr "length" "12")])
8224 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8225 (clobber (reg:DI 2))]
8228 [(set_attr "type" "branch")
8229 (set_attr "length" "4")])
8231 (define_expand "builtin_longjmp"
8232 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8236 /* The elements of the buffer are, in order: */
8237 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8238 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8239 POINTER_SIZE / BITS_PER_UNIT));
8240 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8241 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8242 rtx pv = gen_rtx_REG (Pmode, 1);
8244 /* This bit is the same as expand_builtin_longjmp. */
8245 emit_move_insn (hard_frame_pointer_rtx, fp);
8246 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8247 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8248 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8250 /* Load the label we are jumping through into r1 so that we know
8251 where to look for it when we get back to setjmp's function for
8252 restoring the gp. */
8253 emit_move_insn (pv, lab);
8255 /* Prevent the insns above from being scheduled into the delay slot
8256 of the interspace jump because the space register could change. */
8257 emit_insn (gen_blockage ());
8259 emit_jump_insn (gen_interspace_jump (pv));
8264 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8265 (define_expand "extzv"
8266 [(set (match_operand 0 "register_operand" "")
8267 (zero_extract (match_operand 1 "register_operand" "")
8268 (match_operand 2 "uint32_operand" "")
8269 (match_operand 3 "uint32_operand" "")))]
8273 HOST_WIDE_INT len = INTVAL (operands[2]);
8274 HOST_WIDE_INT pos = INTVAL (operands[3]);
8276 /* PA extraction insns don't support zero length bitfields or fields
8277 extending beyond the left or right-most bits. Also, we reject lengths
8278 equal to a word as they are better handled by the move patterns. */
8279 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8282 /* From mips.md: extract_bit_field doesn't verify that our source
8283 matches the predicate, so check it again here. */
8284 if (!register_operand (operands[1], VOIDmode))
8288 emit_insn (gen_extzv_64 (operands[0], operands[1],
8289 operands[2], operands[3]));
8291 emit_insn (gen_extzv_32 (operands[0], operands[1],
8292 operands[2], operands[3]));
8296 (define_insn "extzv_32"
8297 [(set (match_operand:SI 0 "register_operand" "=r")
8298 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8299 (match_operand:SI 2 "uint5_operand" "")
8300 (match_operand:SI 3 "uint5_operand" "")))]
8302 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8303 [(set_attr "type" "shift")
8304 (set_attr "length" "4")])
8307 [(set (match_operand:SI 0 "register_operand" "=r")
8308 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8310 (match_operand:SI 2 "register_operand" "q")))]
8312 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8313 [(set_attr "type" "shift")
8314 (set_attr "length" "4")])
8316 (define_insn "extzv_64"
8317 [(set (match_operand:DI 0 "register_operand" "=r")
8318 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8319 (match_operand:DI 2 "uint32_operand" "")
8320 (match_operand:DI 3 "uint32_operand" "")))]
8322 "extrd,u %1,%3+%2-1,%2,%0"
8323 [(set_attr "type" "shift")
8324 (set_attr "length" "4")])
8327 [(set (match_operand:DI 0 "register_operand" "=r")
8328 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8330 (match_operand:DI 2 "register_operand" "q")))]
8332 "extrd,u %1,%%sar,1,%0"
8333 [(set_attr "type" "shift")
8334 (set_attr "length" "4")])
8336 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8337 (define_expand "extv"
8338 [(set (match_operand 0 "register_operand" "")
8339 (sign_extract (match_operand 1 "register_operand" "")
8340 (match_operand 2 "uint32_operand" "")
8341 (match_operand 3 "uint32_operand" "")))]
8345 HOST_WIDE_INT len = INTVAL (operands[2]);
8346 HOST_WIDE_INT pos = INTVAL (operands[3]);
8348 /* PA extraction insns don't support zero length bitfields or fields
8349 extending beyond the left or right-most bits. Also, we reject lengths
8350 equal to a word as they are better handled by the move patterns. */
8351 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8354 /* From mips.md: extract_bit_field doesn't verify that our source
8355 matches the predicate, so check it again here. */
8356 if (!register_operand (operands[1], VOIDmode))
8360 emit_insn (gen_extv_64 (operands[0], operands[1],
8361 operands[2], operands[3]));
8363 emit_insn (gen_extv_32 (operands[0], operands[1],
8364 operands[2], operands[3]));
8368 (define_insn "extv_32"
8369 [(set (match_operand:SI 0 "register_operand" "=r")
8370 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8371 (match_operand:SI 2 "uint5_operand" "")
8372 (match_operand:SI 3 "uint5_operand" "")))]
8374 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8375 [(set_attr "type" "shift")
8376 (set_attr "length" "4")])
8379 [(set (match_operand:SI 0 "register_operand" "=r")
8380 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8382 (match_operand:SI 2 "register_operand" "q")))]
8384 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8385 [(set_attr "type" "shift")
8386 (set_attr "length" "4")])
8388 (define_insn "extv_64"
8389 [(set (match_operand:DI 0 "register_operand" "=r")
8390 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8391 (match_operand:DI 2 "uint32_operand" "")
8392 (match_operand:DI 3 "uint32_operand" "")))]
8394 "extrd,s %1,%3+%2-1,%2,%0"
8395 [(set_attr "type" "shift")
8396 (set_attr "length" "4")])
8399 [(set (match_operand:DI 0 "register_operand" "=r")
8400 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8402 (match_operand:DI 2 "register_operand" "q")))]
8404 "extrd,s %1,%%sar,1,%0"
8405 [(set_attr "type" "shift")
8406 (set_attr "length" "4")])
8408 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8409 (define_expand "insv"
8410 [(set (zero_extract (match_operand 0 "register_operand" "")
8411 (match_operand 1 "uint32_operand" "")
8412 (match_operand 2 "uint32_operand" ""))
8413 (match_operand 3 "arith5_operand" ""))]
8417 HOST_WIDE_INT len = INTVAL (operands[1]);
8418 HOST_WIDE_INT pos = INTVAL (operands[2]);
8420 /* PA insertion insns don't support zero length bitfields or fields
8421 extending beyond the left or right-most bits. Also, we reject lengths
8422 equal to a word as they are better handled by the move patterns. */
8423 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8426 /* From mips.md: insert_bit_field doesn't verify that our destination
8427 matches the predicate, so check it again here. */
8428 if (!register_operand (operands[0], VOIDmode))
8432 emit_insn (gen_insv_64 (operands[0], operands[1],
8433 operands[2], operands[3]));
8435 emit_insn (gen_insv_32 (operands[0], operands[1],
8436 operands[2], operands[3]));
8440 (define_insn "insv_32"
8441 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8442 (match_operand:SI 1 "uint5_operand" "")
8443 (match_operand:SI 2 "uint5_operand" ""))
8444 (match_operand:SI 3 "arith5_operand" "r,L"))]
8447 {dep|depw} %3,%2+%1-1,%1,%0
8448 {depi|depwi} %3,%2+%1-1,%1,%0"
8449 [(set_attr "type" "shift,shift")
8450 (set_attr "length" "4,4")])
8452 ;; Optimize insertion of const_int values of type 1...1xxxx.
8454 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8455 (match_operand:SI 1 "uint5_operand" "")
8456 (match_operand:SI 2 "uint5_operand" ""))
8457 (match_operand:SI 3 "const_int_operand" ""))]
8458 "(INTVAL (operands[3]) & 0x10) != 0 &&
8459 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8462 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8463 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8465 [(set_attr "type" "shift")
8466 (set_attr "length" "4")])
8468 (define_insn "insv_64"
8469 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8470 (match_operand:DI 1 "uint32_operand" "")
8471 (match_operand:DI 2 "uint32_operand" ""))
8472 (match_operand:DI 3 "arith32_operand" "r,L"))]
8475 depd %3,%2+%1-1,%1,%0
8476 depdi %3,%2+%1-1,%1,%0"
8477 [(set_attr "type" "shift,shift")
8478 (set_attr "length" "4,4")])
8480 ;; Optimize insertion of const_int values of type 1...1xxxx.
8482 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8483 (match_operand:DI 1 "uint32_operand" "")
8484 (match_operand:DI 2 "uint32_operand" ""))
8485 (match_operand:DI 3 "const_int_operand" ""))]
8486 "(INTVAL (operands[3]) & 0x10) != 0
8488 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8491 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8492 return \"depdi %3,%2+%1-1,%1,%0\";
8494 [(set_attr "type" "shift")
8495 (set_attr "length" "4")])
8498 [(set (match_operand:DI 0 "register_operand" "=r")
8499 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8502 "depd,z %1,31,32,%0"
8503 [(set_attr "type" "shift")
8504 (set_attr "length" "4")])
8506 ;; This insn is used for some loop tests, typically loops reversed when
8507 ;; strength reduction is used. It is actually created when the instruction
8508 ;; combination phase combines the special loop test. Since this insn
8509 ;; is both a jump insn and has an output, it must deal with its own
8510 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8511 ;; to not choose the register alternatives in the event a reload is needed.
8512 (define_insn "decrement_and_branch_until_zero"
8515 (match_operator 2 "comparison_operator"
8517 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8518 (match_operand:SI 1 "int5_operand" "L,L,L"))
8520 (label_ref (match_operand 3 "" ""))
8523 (plus:SI (match_dup 0) (match_dup 1)))
8524 (clobber (match_scratch:SI 4 "=X,r,r"))]
8526 "* return output_dbra (operands, insn, which_alternative); "
8527 ;; Do not expect to understand this the first time through.
8528 [(set_attr "type" "cbranch,multi,multi")
8529 (set (attr "length")
8530 (if_then_else (eq_attr "alternative" "0")
8531 ;; Loop counter in register case
8532 ;; Short branch has length of 4
8533 ;; Long branch has length of 8
8534 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8539 ;; Loop counter in FP reg case.
8540 ;; Extra goo to deal with additional reload insns.
8541 (if_then_else (eq_attr "alternative" "1")
8542 (if_then_else (lt (match_dup 3) (pc))
8544 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8549 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8553 ;; Loop counter in memory case.
8554 ;; Extra goo to deal with additional reload insns.
8555 (if_then_else (lt (match_dup 3) (pc))
8557 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8562 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8565 (const_int 16))))))])
8570 (match_operator 2 "movb_comparison_operator"
8571 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8572 (label_ref (match_operand 3 "" ""))
8574 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8577 "* return output_movb (operands, insn, which_alternative, 0); "
8578 ;; Do not expect to understand this the first time through.
8579 [(set_attr "type" "cbranch,multi,multi,multi")
8580 (set (attr "length")
8581 (if_then_else (eq_attr "alternative" "0")
8582 ;; Loop counter in register case
8583 ;; Short branch has length of 4
8584 ;; Long branch has length of 8
8585 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8590 ;; Loop counter in FP reg case.
8591 ;; Extra goo to deal with additional reload insns.
8592 (if_then_else (eq_attr "alternative" "1")
8593 (if_then_else (lt (match_dup 3) (pc))
8595 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8600 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8604 ;; Loop counter in memory or sar case.
8605 ;; Extra goo to deal with additional reload insns.
8607 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8610 (const_int 12)))))])
8612 ;; Handle negated branch.
8616 (match_operator 2 "movb_comparison_operator"
8617 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8619 (label_ref (match_operand 3 "" ""))))
8620 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8623 "* return output_movb (operands, insn, which_alternative, 1); "
8624 ;; Do not expect to understand this the first time through.
8625 [(set_attr "type" "cbranch,multi,multi,multi")
8626 (set (attr "length")
8627 (if_then_else (eq_attr "alternative" "0")
8628 ;; Loop counter in register case
8629 ;; Short branch has length of 4
8630 ;; Long branch has length of 8
8631 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8636 ;; Loop counter in FP reg case.
8637 ;; Extra goo to deal with additional reload insns.
8638 (if_then_else (eq_attr "alternative" "1")
8639 (if_then_else (lt (match_dup 3) (pc))
8641 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8646 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8650 ;; Loop counter in memory or SAR case.
8651 ;; Extra goo to deal with additional reload insns.
8653 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8656 (const_int 12)))))])
8659 [(set (pc) (label_ref (match_operand 3 "" "" )))
8660 (set (match_operand:SI 0 "ireg_operand" "=r")
8661 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8662 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8663 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8666 return output_parallel_addb (operands, get_attr_length (insn));
8668 [(set_attr "type" "parallel_branch")
8669 (set (attr "length")
8670 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8676 [(set (pc) (label_ref (match_operand 2 "" "" )))
8677 (set (match_operand:SF 0 "ireg_operand" "=r")
8678 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8682 return output_parallel_movb (operands, get_attr_length (insn));
8684 [(set_attr "type" "parallel_branch")
8685 (set (attr "length")
8686 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8692 [(set (pc) (label_ref (match_operand 2 "" "" )))
8693 (set (match_operand:SI 0 "ireg_operand" "=r")
8694 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8698 return output_parallel_movb (operands, get_attr_length (insn));
8700 [(set_attr "type" "parallel_branch")
8701 (set (attr "length")
8702 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8708 [(set (pc) (label_ref (match_operand 2 "" "" )))
8709 (set (match_operand:HI 0 "ireg_operand" "=r")
8710 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8714 return output_parallel_movb (operands, get_attr_length (insn));
8716 [(set_attr "type" "parallel_branch")
8717 (set (attr "length")
8718 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8724 [(set (pc) (label_ref (match_operand 2 "" "" )))
8725 (set (match_operand:QI 0 "ireg_operand" "=r")
8726 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8730 return output_parallel_movb (operands, get_attr_length (insn));
8732 [(set_attr "type" "parallel_branch")
8733 (set (attr "length")
8734 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8740 [(set (match_operand 0 "register_operand" "=f")
8741 (mult (match_operand 1 "register_operand" "f")
8742 (match_operand 2 "register_operand" "f")))
8743 (set (match_operand 3 "register_operand" "+f")
8744 (plus (match_operand 4 "register_operand" "f")
8745 (match_operand 5 "register_operand" "f")))]
8746 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8747 && reload_completed && fmpyaddoperands (operands)"
8750 if (GET_MODE (operands[0]) == DFmode)
8752 if (rtx_equal_p (operands[3], operands[5]))
8753 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8755 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8759 if (rtx_equal_p (operands[3], operands[5]))
8760 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8762 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8765 [(set_attr "type" "fpalu")
8766 (set_attr "length" "4")])
8769 [(set (match_operand 3 "register_operand" "+f")
8770 (plus (match_operand 4 "register_operand" "f")
8771 (match_operand 5 "register_operand" "f")))
8772 (set (match_operand 0 "register_operand" "=f")
8773 (mult (match_operand 1 "register_operand" "f")
8774 (match_operand 2 "register_operand" "f")))]
8775 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8776 && reload_completed && fmpyaddoperands (operands)"
8779 if (GET_MODE (operands[0]) == DFmode)
8781 if (rtx_equal_p (operands[3], operands[5]))
8782 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8784 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8788 if (rtx_equal_p (operands[3], operands[5]))
8789 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8791 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8794 [(set_attr "type" "fpalu")
8795 (set_attr "length" "4")])
8798 [(set (match_operand 0 "register_operand" "=f")
8799 (mult (match_operand 1 "register_operand" "f")
8800 (match_operand 2 "register_operand" "f")))
8801 (set (match_operand 3 "register_operand" "+f")
8802 (minus (match_operand 4 "register_operand" "f")
8803 (match_operand 5 "register_operand" "f")))]
8804 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8805 && reload_completed && fmpysuboperands (operands)"
8808 if (GET_MODE (operands[0]) == DFmode)
8809 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8811 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8813 [(set_attr "type" "fpalu")
8814 (set_attr "length" "4")])
8817 [(set (match_operand 3 "register_operand" "+f")
8818 (minus (match_operand 4 "register_operand" "f")
8819 (match_operand 5 "register_operand" "f")))
8820 (set (match_operand 0 "register_operand" "=f")
8821 (mult (match_operand 1 "register_operand" "f")
8822 (match_operand 2 "register_operand" "f")))]
8823 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8824 && reload_completed && fmpysuboperands (operands)"
8827 if (GET_MODE (operands[0]) == DFmode)
8828 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8830 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8832 [(set_attr "type" "fpalu")
8833 (set_attr "length" "4")])
8835 ;; Clean up turds left by reload.
8837 [(set (match_operand 0 "move_dest_operand" "")
8838 (match_operand 1 "register_operand" "fr"))
8839 (set (match_operand 2 "register_operand" "fr")
8842 && GET_CODE (operands[0]) == MEM
8843 && ! MEM_VOLATILE_P (operands[0])
8844 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8845 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8846 && GET_MODE (operands[0]) == DFmode
8847 && GET_CODE (operands[1]) == REG
8848 && GET_CODE (operands[2]) == REG
8849 && ! side_effects_p (XEXP (operands[0], 0))
8850 && REGNO_REG_CLASS (REGNO (operands[1]))
8851 == REGNO_REG_CLASS (REGNO (operands[2]))"
8856 if (FP_REG_P (operands[1]))
8857 output_asm_insn (output_fp_move_double (operands), operands);
8859 output_asm_insn (output_move_double (operands), operands);
8861 if (rtx_equal_p (operands[1], operands[2]))
8864 xoperands[0] = operands[2];
8865 xoperands[1] = operands[1];
8867 if (FP_REG_P (xoperands[1]))
8868 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8870 output_asm_insn (output_move_double (xoperands), xoperands);
8876 [(set (match_operand 0 "register_operand" "fr")
8877 (match_operand 1 "move_src_operand" ""))
8878 (set (match_operand 2 "register_operand" "fr")
8881 && GET_CODE (operands[1]) == MEM
8882 && ! MEM_VOLATILE_P (operands[1])
8883 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8884 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8885 && GET_MODE (operands[0]) == DFmode
8886 && GET_CODE (operands[0]) == REG
8887 && GET_CODE (operands[2]) == REG
8888 && ! side_effects_p (XEXP (operands[1], 0))
8889 && REGNO_REG_CLASS (REGNO (operands[0]))
8890 == REGNO_REG_CLASS (REGNO (operands[2]))"
8895 if (FP_REG_P (operands[0]))
8896 output_asm_insn (output_fp_move_double (operands), operands);
8898 output_asm_insn (output_move_double (operands), operands);
8900 xoperands[0] = operands[2];
8901 xoperands[1] = operands[0];
8903 if (FP_REG_P (xoperands[1]))
8904 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8906 output_asm_insn (output_move_double (xoperands), xoperands);
8911 ;; Flush the I and D cache lines from the start address (operand0)
8912 ;; to the end address (operand1). No lines are flushed if the end
8913 ;; address is less than the start address (unsigned).
8915 ;; Because the range of memory flushed is variable and the size of
8916 ;; a MEM can only be a CONST_INT, the patterns specify that they
8917 ;; perform an unspecified volatile operation on all memory.
8919 ;; The address range for an icache flush must lie within a single
8920 ;; space on targets with non-equivalent space registers.
8922 ;; This is used by the trampoline code for nested functions.
8924 ;; Operand 0 contains the start address.
8925 ;; Operand 1 contains the end address.
8926 ;; Operand 2 contains the line length to use.
8927 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8928 (define_insn "dcacheflush"
8930 (unspec_volatile [(mem:BLK (scratch))] 0)
8931 (use (match_operand 0 "pmode_register_operand" "r"))
8932 (use (match_operand 1 "pmode_register_operand" "r"))
8933 (use (match_operand 2 "pmode_register_operand" "r"))
8934 (clobber (match_scratch 3 "=&0"))]
8939 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8941 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8943 [(set_attr "type" "multi")
8944 (set_attr "length" "12")])
8946 (define_insn "icacheflush"
8948 (unspec_volatile [(mem:BLK (scratch))] 0)
8949 (use (match_operand 0 "pmode_register_operand" "r"))
8950 (use (match_operand 1 "pmode_register_operand" "r"))
8951 (use (match_operand 2 "pmode_register_operand" "r"))
8952 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8953 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8954 (clobber (match_scratch 5 "=&0"))]
8959 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8961 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8963 [(set_attr "type" "multi")
8964 (set_attr "length" "52")])
8966 ;; An out-of-line prologue.
8967 (define_insn "outline_prologue_call"
8968 [(unspec_volatile [(const_int 0)] 0)
8969 (clobber (reg:SI 31))
8970 (clobber (reg:SI 22))
8971 (clobber (reg:SI 21))
8972 (clobber (reg:SI 20))
8973 (clobber (reg:SI 19))
8974 (clobber (reg:SI 1))]
8978 extern int frame_pointer_needed;
8980 /* We need two different versions depending on whether or not we
8981 need a frame pointer. Also note that we return to the instruction
8982 immediately after the branch rather than two instructions after the
8983 break as normally is the case. */
8984 if (frame_pointer_needed)
8986 /* Must import the magic millicode routine(s). */
8987 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
8989 if (TARGET_PORTABLE_RUNTIME)
8991 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
8992 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
8996 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9000 /* Must import the magic millicode routine(s). */
9001 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9003 if (TARGET_PORTABLE_RUNTIME)
9005 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9006 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9009 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9013 [(set_attr "type" "multi")
9014 (set_attr "length" "8")])
9016 ;; An out-of-line epilogue.
9017 (define_insn "outline_epilogue_call"
9018 [(unspec_volatile [(const_int 1)] 0)
9021 (clobber (reg:SI 31))
9022 (clobber (reg:SI 22))
9023 (clobber (reg:SI 21))
9024 (clobber (reg:SI 20))
9025 (clobber (reg:SI 19))
9026 (clobber (reg:SI 2))
9027 (clobber (reg:SI 1))]
9031 extern int frame_pointer_needed;
9033 /* We need two different versions depending on whether or not we
9034 need a frame pointer. Also note that we return to the instruction
9035 immediately after the branch rather than two instructions after the
9036 break as normally is the case. */
9037 if (frame_pointer_needed)
9039 /* Must import the magic millicode routine. */
9040 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9042 /* The out-of-line prologue will make sure we return to the right
9044 if (TARGET_PORTABLE_RUNTIME)
9046 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9047 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9051 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9055 /* Must import the magic millicode routine. */
9056 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9058 /* The out-of-line prologue will make sure we return to the right
9060 if (TARGET_PORTABLE_RUNTIME)
9062 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9063 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9066 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9070 [(set_attr "type" "multi")
9071 (set_attr "length" "8")])
9073 ;; Given a function pointer, canonicalize it so it can be
9074 ;; reliably compared to another function pointer. */
9075 (define_expand "canonicalize_funcptr_for_compare"
9076 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9077 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9078 (clobber (match_dup 2))
9079 (clobber (reg:SI 26))
9080 (clobber (reg:SI 22))
9081 (clobber (reg:SI 31))])
9082 (set (match_operand:SI 0 "register_operand" "")
9084 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9089 rtx canonicalize_funcptr_for_compare_libfunc
9090 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9092 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9093 operands[0], LCT_NORMAL, Pmode,
9094 1, operands[1], Pmode);
9098 operands[2] = gen_reg_rtx (SImode);
9099 if (GET_CODE (operands[1]) != REG)
9101 rtx tmp = gen_reg_rtx (Pmode);
9102 emit_move_insn (tmp, operands[1]);
9108 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9109 (clobber (match_operand:SI 0 "register_operand" "=a"))
9110 (clobber (reg:SI 26))
9111 (clobber (reg:SI 22))
9112 (clobber (reg:SI 31))]
9116 int length = get_attr_length (insn);
9119 xoperands[0] = GEN_INT (length - 8);
9120 xoperands[1] = GEN_INT (length - 16);
9122 /* Must import the magic millicode routine. */
9123 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9125 /* This is absolutely amazing.
9127 First, copy our input parameter into %r29 just in case we don't
9128 need to call $$sh_func_adrs. */
9129 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9130 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9132 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9133 we use %r26 unchanged. */
9134 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9135 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9137 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9138 4096, then again we use %r26 unchanged. */
9139 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9141 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9142 return output_millicode_call (insn,
9143 gen_rtx_SYMBOL_REF (SImode,
9144 \"$$sh_func_adrs\"));
9146 [(set_attr "type" "multi")
9147 (set (attr "length")
9148 (plus (symbol_ref "attr_length_millicode_call (insn)")
9151 ;; On the PA, the PIC register is call clobbered, so it must
9152 ;; be saved & restored around calls by the caller. If the call
9153 ;; doesn't return normally (nonlocal goto, or an exception is
9154 ;; thrown), then the code at the exception handler label must
9155 ;; restore the PIC register.
9156 (define_expand "exception_receiver"
9161 /* On the 64-bit port, we need a blockage because there is
9162 confusion regarding the dependence of the restore on the
9163 frame pointer. As a result, the frame pointer and pic
9164 register restores sometimes are interchanged erroneously. */
9166 emit_insn (gen_blockage ());
9167 /* Restore the PIC register using hppa_pic_save_rtx (). The
9168 PIC register is not saved in the frame in 64-bit ABI. */
9169 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9170 emit_insn (gen_blockage ());
9174 (define_expand "builtin_setjmp_receiver"
9175 [(label_ref (match_operand 0 "" ""))]
9180 emit_insn (gen_blockage ());
9181 /* Restore the PIC register. Hopefully, this will always be from
9182 a stack slot. The only registers that are valid after a
9183 builtin_longjmp are the stack and frame pointers. */
9184 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9185 emit_insn (gen_blockage ());
9189 ;; Allocate new stack space and update the saved stack pointer in the
9190 ;; frame marker. The HP C compilers also copy additional words in the
9191 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9192 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9193 ;; currently don't copy these values.
9195 ;; Since the copy of the frame marker can't be done atomically, I
9196 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9197 ;; The HP compilers appear to raise the stack and copy the frame
9198 ;; marker in a strict instruction sequence. This suggests that the
9199 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9200 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9201 ;; as GAS doesn't support it, or try to keep the instructions emitted
9202 ;; here in strict sequence.
9203 (define_expand "allocate_stack"
9204 [(match_operand 0 "" "")
9205 (match_operand 1 "" "")]
9211 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9212 in operand 0 before adjusting the stack. */
9213 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9214 anti_adjust_stack (operands[1]);
9215 if (TARGET_HPUX_UNWIND_LIBRARY)
9217 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9218 GEN_INT (TARGET_64BIT ? -8 : -4));
9219 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9221 if (!TARGET_64BIT && flag_pic)
9223 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9224 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);