1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
40 #ifndef REGISTER_MOVE_COST
41 #define REGISTER_MOVE_COST(x, y) 2
44 static void init_reg_sets_1
PROTO((void));
45 static void init_reg_modes
PROTO((void));
47 /* If we have auto-increment or auto-decrement and we can have secondary
48 reloads, we are not allowed to use classes requiring secondary
49 reloads for pseudos auto-incremented since reload can't handle it. */
52 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
53 #define FORBIDDEN_INC_DEC_CLASSES
57 /* Register tables used by many passes. */
59 /* Indexed by hard register number, contains 1 for registers
60 that are fixed use (stack pointer, pc, frame pointer, etc.).
61 These are the registers that cannot be used to allocate
62 a pseudo reg for general use. */
64 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
66 /* Same info as a HARD_REG_SET. */
68 HARD_REG_SET fixed_reg_set
;
70 /* Data for initializing the above. */
72 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
74 /* Indexed by hard register number, contains 1 for registers
75 that are fixed use or are clobbered by function calls.
76 These are the registers that cannot be used to allocate
77 a pseudo reg whose life crosses calls unless we are able
78 to save/restore them across the calls. */
80 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
82 /* Same info as a HARD_REG_SET. */
84 HARD_REG_SET call_used_reg_set
;
86 /* HARD_REG_SET of registers we want to avoid caller saving. */
87 HARD_REG_SET losing_caller_save_reg_set
;
89 /* Data for initializing the above. */
91 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
93 /* Indexed by hard register number, contains 1 for registers that are
94 fixed use or call used registers that cannot hold quantities across
95 calls even if we are willing to save and restore them. call fixed
96 registers are a subset of call used registers. */
98 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
100 /* The same info as a HARD_REG_SET. */
102 HARD_REG_SET call_fixed_reg_set
;
104 /* Number of non-fixed registers. */
106 int n_non_fixed_regs
;
108 /* Indexed by hard register number, contains 1 for registers
109 that are being used for global register decls.
110 These must be exempt from ordinary flow analysis
111 and are also considered fixed. */
113 char global_regs
[FIRST_PSEUDO_REGISTER
];
115 /* Table of register numbers in the order in which to try to use them. */
116 #ifdef REG_ALLOC_ORDER
117 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
120 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
122 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
124 /* The same information, but as an array of unsigned ints. We copy from
125 these unsigned ints to the table above. We do this so the tm.h files
126 do not have to be aware of the wordsize for machines with <= 64 regs. */
129 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
131 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
132 = REG_CLASS_CONTENTS
;
134 /* For each reg class, number of regs it contains. */
136 int reg_class_size
[N_REG_CLASSES
];
138 /* For each reg class, table listing all the containing classes. */
140 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
142 /* For each reg class, table listing all the classes contained in it. */
144 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
146 /* For each pair of reg classes,
147 a largest reg class contained in their union. */
149 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
151 /* For each pair of reg classes,
152 the smallest reg class containing their union. */
154 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
156 /* Array containing all of the register names */
158 char *reg_names
[] = REGISTER_NAMES
;
160 /* For each hard register, the widest mode object that it can contain.
161 This will be a MODE_INT mode if the register can hold integers. Otherwise
162 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
165 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
167 /* Maximum cost of moving from a register in one class to a register in
168 another class. Based on REGISTER_MOVE_COST. */
170 static int move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
172 /* Similar, but here we don't have to move if the first index is a subset
173 of the second so in that case the cost is zero. */
175 static int may_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
177 #ifdef FORBIDDEN_INC_DEC_CLASSES
179 /* These are the classes that regs which are auto-incremented or decremented
182 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
184 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
187 static char *in_inc_dec
;
189 #endif /* FORBIDDEN_INC_DEC_CLASSES */
191 #ifdef HAVE_SECONDARY_RELOADS
193 /* Sample MEM values for use by memory_move_secondary_cost. */
195 static rtx top_of_stack
[MAX_MACHINE_MODE
];
197 #endif /* HAVE_SECONDARY_RELOADS */
199 /* Linked list of reg_info structures allocated for reg_n_info array.
200 Grouping all of the allocated structures together in one lump
201 means only one call to bzero to clear them, rather than n smaller
203 struct reg_info_data
{
204 struct reg_info_data
*next
; /* next set of reg_info structures */
205 size_t min_index
; /* minimum index # */
206 size_t max_index
; /* maximum index # */
207 char used_p
; /* non-zero if this has been used previously */
208 reg_info data
[1]; /* beginning of the reg_info data */
211 static struct reg_info_data
*reg_info_head
;
214 /* Function called only once to initialize the above data on reg usage.
215 Once this is done, various switches may override. */
222 /* First copy the register information from the initial int form into
225 for (i
= 0; i
< N_REG_CLASSES
; i
++)
227 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
229 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
230 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
231 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
232 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
235 bcopy (initial_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
236 bcopy (initial_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
237 bzero (global_regs
, sizeof global_regs
);
239 /* Do any additional initialization regsets may need */
240 INIT_ONCE_REG_SET ();
243 /* After switches have been processed, which perhaps alter
244 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
249 register unsigned int i
, j
;
251 /* This macro allows the fixed or call-used registers
252 and the register classes to depend on target flags. */
254 #ifdef CONDITIONAL_REGISTER_USAGE
255 CONDITIONAL_REGISTER_USAGE
;
258 /* Compute number of hard regs in each class. */
260 bzero ((char *) reg_class_size
, sizeof reg_class_size
);
261 for (i
= 0; i
< N_REG_CLASSES
; i
++)
262 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
263 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
266 /* Initialize the table of subunions.
267 reg_class_subunion[I][J] gets the largest-numbered reg-class
268 that is contained in the union of classes I and J. */
270 for (i
= 0; i
< N_REG_CLASSES
; i
++)
272 for (j
= 0; j
< N_REG_CLASSES
; j
++)
275 register /* Declare it register if it's a scalar. */
280 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
281 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
282 for (k
= 0; k
< N_REG_CLASSES
; k
++)
284 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
289 /* keep the largest subclass */ /* SPEE 900308 */
290 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
291 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
293 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
300 /* Initialize the table of superunions.
301 reg_class_superunion[I][J] gets the smallest-numbered reg-class
302 containing the union of classes I and J. */
304 for (i
= 0; i
< N_REG_CLASSES
; i
++)
306 for (j
= 0; j
< N_REG_CLASSES
; j
++)
309 register /* Declare it register if it's a scalar. */
314 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
315 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
316 for (k
= 0; k
< N_REG_CLASSES
; k
++)
317 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
320 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
324 /* Initialize the tables of subclasses and superclasses of each reg class.
325 First clear the whole table, then add the elements as they are found. */
327 for (i
= 0; i
< N_REG_CLASSES
; i
++)
329 for (j
= 0; j
< N_REG_CLASSES
; j
++)
331 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
332 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
336 for (i
= 0; i
< N_REG_CLASSES
; i
++)
338 if (i
== (int) NO_REGS
)
341 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
345 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
349 /* Reg class I is a subclass of J.
350 Add J to the table of superclasses of I. */
351 p
= ®_class_superclasses
[i
][0];
352 while (*p
!= LIM_REG_CLASSES
) p
++;
353 *p
= (enum reg_class
) j
;
354 /* Add I to the table of superclasses of J. */
355 p
= ®_class_subclasses
[j
][0];
356 while (*p
!= LIM_REG_CLASSES
) p
++;
357 *p
= (enum reg_class
) i
;
361 /* Initialize "constant" tables. */
363 CLEAR_HARD_REG_SET (fixed_reg_set
);
364 CLEAR_HARD_REG_SET (call_used_reg_set
);
365 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
367 bcopy (fixed_regs
, call_fixed_regs
, sizeof call_fixed_regs
);
369 n_non_fixed_regs
= 0;
371 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
374 SET_HARD_REG_BIT (fixed_reg_set
, i
);
378 if (call_used_regs
[i
])
379 SET_HARD_REG_BIT (call_used_reg_set
, i
);
380 if (call_fixed_regs
[i
])
381 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
382 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
383 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
386 /* Initialize the move cost table. Find every subset of each class
387 and take the maximum cost of moving any subset to any other. */
389 for (i
= 0; i
< N_REG_CLASSES
; i
++)
390 for (j
= 0; j
< N_REG_CLASSES
; j
++)
392 int cost
= i
== j
? 2 : REGISTER_MOVE_COST (i
, j
);
393 enum reg_class
*p1
, *p2
;
395 for (p2
= ®_class_subclasses
[j
][0]; *p2
!= LIM_REG_CLASSES
; p2
++)
397 cost
= MAX (cost
, REGISTER_MOVE_COST (i
, *p2
));
399 for (p1
= ®_class_subclasses
[i
][0]; *p1
!= LIM_REG_CLASSES
; p1
++)
402 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, j
));
404 for (p2
= ®_class_subclasses
[j
][0];
405 *p2
!= LIM_REG_CLASSES
; p2
++)
407 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, *p2
));
410 move_cost
[i
][j
] = cost
;
412 if (reg_class_subset_p (i
, j
))
415 may_move_cost
[i
][j
] = cost
;
419 /* Compute the table of register modes.
420 These values are used to record death information for individual registers
421 (as opposed to a multi-register mode). */
428 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
430 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
432 /* If we couldn't find a valid mode, just use the previous mode.
433 ??? One situation in which we need to do this is on the mips where
434 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
435 to use DF mode for the even registers and VOIDmode for the odd
436 (for the cpu models where the odd ones are inaccessible). */
437 if (reg_raw_mode
[i
] == VOIDmode
)
438 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
442 /* Finish initializing the register sets and
443 initialize the register modes. */
448 /* This finishes what was started by init_reg_sets, but couldn't be done
449 until after register usage was specified. */
454 #ifdef HAVE_SECONDARY_RELOADS
456 /* Make some fake stack-frame MEM references for use in
457 memory_move_secondary_cost. */
459 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
460 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
465 #ifdef HAVE_SECONDARY_RELOADS
467 /* Compute extra cost of moving registers to/from memory due to reloads.
468 Only needed if secondary reloads are required for memory moves. */
471 memory_move_secondary_cost (mode
, class, in
)
472 enum machine_mode mode
;
473 enum reg_class
class;
476 enum reg_class altclass
;
477 int partial_cost
= 0;
478 /* We need a memory reference to feed to SECONDARY... macros. */
479 rtx mem
= top_of_stack
[(int) mode
];
483 #ifdef SECONDARY_INPUT_RELOAD_CLASS
484 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
491 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
492 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
498 if (altclass
== NO_REGS
)
502 partial_cost
= REGISTER_MOVE_COST (altclass
, class);
504 partial_cost
= REGISTER_MOVE_COST (class, altclass
);
506 if (class == altclass
)
507 /* This isn't simply a copy-to-temporary situation. Can't guess
508 what it is, so MEMORY_MOVE_COST really ought not to be calling
511 I'm tempted to put in an abort here, but returning this will
512 probably only give poor estimates, which is what we would've
513 had before this code anyways. */
516 /* Check if the secondary reload register will also need a
518 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
522 /* Return a machine mode that is legitimate for hard reg REGNO and large
523 enough to save nregs. If we can't find one, return VOIDmode. */
526 choose_hard_reg_mode (regno
, nregs
)
530 enum machine_mode found_mode
= VOIDmode
, mode
;
532 /* We first look for the largest integer mode that can be validly
533 held in REGNO. If none, we look for the largest floating-point mode.
534 If we still didn't find a valid mode, try CCmode. */
536 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
538 mode
= GET_MODE_WIDER_MODE (mode
))
539 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
540 && HARD_REGNO_MODE_OK (regno
, mode
))
543 if (found_mode
!= VOIDmode
)
546 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
548 mode
= GET_MODE_WIDER_MODE (mode
))
549 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
550 && HARD_REGNO_MODE_OK (regno
, mode
))
553 if (found_mode
!= VOIDmode
)
556 if (HARD_REGNO_NREGS (regno
, CCmode
) == nregs
557 && HARD_REGNO_MODE_OK (regno
, CCmode
))
560 /* We can't find a mode valid for this register. */
564 /* Specify the usage characteristics of the register named NAME.
565 It should be a fixed register if FIXED and a
566 call-used register if CALL_USED. */
569 fix_register (name
, fixed
, call_used
)
571 int fixed
, call_used
;
575 /* Decode the name and update the primary form of
576 the register info. */
578 if ((i
= decode_reg_name (name
)) >= 0)
580 if ((i
== STACK_POINTER_REGNUM
581 #ifdef HARD_FRAME_POINTER_REGNUM
582 || i
== HARD_FRAME_POINTER_REGNUM
584 || i
== FRAME_POINTER_REGNUM
587 && (fixed
== 0 || call_used
== 0))
589 static char* what_option
[2][2] = {
590 { "call-saved", "call-used" },
591 { "no-such-option", "fixed" }};
593 error ("can't use '%s' as a %s register", name
,
594 what_option
[fixed
][call_used
]);
598 fixed_regs
[i
] = fixed
;
599 call_used_regs
[i
] = call_used
;
604 warning ("unknown register name: %s", name
);
608 /* Mark register number I as global. */
616 warning ("register used for two global register variables");
620 if (call_used_regs
[i
] && ! fixed_regs
[i
])
621 warning ("call-clobbered register used for global register variable");
625 /* If already fixed, nothing else to do. */
629 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
632 SET_HARD_REG_BIT (fixed_reg_set
, i
);
633 SET_HARD_REG_BIT (call_used_reg_set
, i
);
634 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
637 /* Now the data and code for the `regclass' pass, which happens
638 just before local-alloc. */
640 /* The `costs' struct records the cost of using a hard register of each class
641 and of using memory for each pseudo. We use this data to set up
642 register class preferences. */
646 int cost
[N_REG_CLASSES
];
650 /* Record the cost of each class for each pseudo. */
652 static struct costs
*costs
;
654 /* Initialized once, and used to initialize cost values for each insn. */
656 static struct costs init_cost
;
658 /* Record the same data by operand number, accumulated for each alternative
659 in an insn. The contribution to a pseudo is that of the minimum-cost
662 static struct costs op_costs
[MAX_RECOG_OPERANDS
];
664 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
665 This is available after `regclass' is run. */
667 static char *prefclass
;
669 /* altclass[R] is a register class that we should use for allocating
670 pseudo number R if no register in the preferred class is available.
671 If no register in this class is available, memory is preferred.
673 It might appear to be more general to have a bitmask of classes here,
674 but since it is recommended that there be a class corresponding to the
675 union of most major pair of classes, that generality is not required.
677 This is available after `regclass' is run. */
679 static char *altclass
;
681 /* Allocated buffers for prefclass and altclass. */
682 static char *prefclass_buffer
;
683 static char *altclass_buffer
;
685 /* Record the depth of loops that we are in. */
687 static int loop_depth
;
689 /* Account for the fact that insns within a loop are executed very commonly,
690 but don't keep doing this as loops go too deep. */
692 static int loop_cost
;
694 static rtx scan_one_insn
PROTO((rtx
, int));
695 static void record_reg_classes
PROTO((int, int, rtx
*, enum machine_mode
*,
696 const char **, rtx
));
697 static int copy_cost
PROTO((rtx
, enum machine_mode
,
698 enum reg_class
, int));
699 static void record_address_regs
PROTO((rtx
, enum reg_class
, int));
700 #ifdef FORBIDDEN_INC_DEC_CLASSES
701 static int auto_inc_dec_reg_p
PROTO((rtx
, enum machine_mode
));
703 static void reg_scan_mark_refs
PROTO((rtx
, rtx
, int, int));
705 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
706 This function is sometimes called before the info has been computed.
707 When that happens, just return GENERAL_REGS, which is innocuous. */
710 reg_preferred_class (regno
)
715 return (enum reg_class
) prefclass
[regno
];
719 reg_alternate_class (regno
)
725 return (enum reg_class
) altclass
[regno
];
728 /* Initialize some global data for this pass. */
735 init_cost
.mem_cost
= 10000;
736 for (i
= 0; i
< N_REG_CLASSES
; i
++)
737 init_cost
.cost
[i
] = 10000;
739 /* This prevents dump_flow_info from losing if called
740 before regclass is run. */
744 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
745 time it would save code to put a certain register in a certain class.
746 PASS, when nonzero, inhibits some optimizations which need only be done
748 Return the last insn processed, so that the scan can be continued from
752 scan_one_insn (insn
, pass
)
756 enum rtx_code code
= GET_CODE (insn
);
757 enum rtx_code pat_code
;
758 const char *constraints
[MAX_RECOG_OPERANDS
];
759 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
763 /* Show that an insn inside a loop is likely to be executed three
764 times more than insns outside a loop. This is much more aggressive
765 than the assumptions made elsewhere and is being tried as an
770 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
771 loop_depth
++, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
772 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
773 loop_depth
--, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
778 if (GET_RTX_CLASS (code
) != 'i')
781 pat_code
= GET_CODE (PATTERN (insn
));
783 || pat_code
== CLOBBER
784 || pat_code
== ASM_INPUT
785 || pat_code
== ADDR_VEC
786 || pat_code
== ADDR_DIFF_VEC
)
789 set
= single_set (insn
);
792 for (i
= 0; i
< recog_n_operands
; i
++)
794 constraints
[i
] = recog_constraints
[i
];
795 modes
[i
] = recog_operand_mode
[i
];
798 /* If this insn loads a parameter from its stack slot, then
799 it represents a savings, rather than a cost, if the
800 parameter is stored in memory. Record this fact. */
802 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
803 && GET_CODE (SET_SRC (set
)) == MEM
804 && (note
= find_reg_note (insn
, REG_EQUIV
,
806 && GET_CODE (XEXP (note
, 0)) == MEM
)
808 costs
[REGNO (SET_DEST (set
))].mem_cost
809 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
812 record_address_regs (XEXP (SET_SRC (set
), 0),
813 BASE_REG_CLASS
, loop_cost
* 2);
817 /* Improve handling of two-address insns such as
818 (set X (ashift CONST Y)) where CONST must be made to
819 match X. Change it into two insns: (set X CONST)
820 (set X (ashift X Y)). If we left this for reloading, it
821 would probably get three insns because X and Y might go
822 in the same place. This prevents X and Y from receiving
825 We can only do this if the modes of operands 0 and 1
826 (which might not be the same) are tieable and we only need
827 do this during our first pass. */
829 if (pass
== 0 && optimize
830 && recog_n_operands
>= 3
831 && recog_constraints
[1][0] == '0'
832 && recog_constraints
[1][1] == 0
833 && CONSTANT_P (recog_operand
[1])
834 && ! rtx_equal_p (recog_operand
[0], recog_operand
[1])
835 && ! rtx_equal_p (recog_operand
[0], recog_operand
[2])
836 && GET_CODE (recog_operand
[0]) == REG
837 && MODES_TIEABLE_P (GET_MODE (recog_operand
[0]),
838 recog_operand_mode
[1]))
840 rtx previnsn
= prev_real_insn (insn
);
842 = gen_lowpart (recog_operand_mode
[1],
845 = emit_insn_before (gen_move_insn (dest
,
849 /* If this insn was the start of a basic block,
850 include the new insn in that block.
851 We need not check for code_label here;
852 while a basic block can start with a code_label,
853 INSN could not be at the beginning of that block. */
854 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
857 for (b
= 0; b
< n_basic_blocks
; b
++)
858 if (insn
== BLOCK_HEAD (b
))
859 BLOCK_HEAD (b
) = newinsn
;
862 /* This makes one more setting of new insns's dest. */
863 REG_N_SETS (REGNO (recog_operand
[0]))++;
865 *recog_operand_loc
[1] = recog_operand
[0];
866 for (i
= recog_n_dups
- 1; i
>= 0; i
--)
867 if (recog_dup_num
[i
] == 1)
868 *recog_dup_loc
[i
] = recog_operand
[0];
870 return PREV_INSN (newinsn
);
873 /* If we get here, we are set up to record the costs of all the
874 operands for this insn. Start by initializing the costs.
875 Then handle any address registers. Finally record the desired
876 classes for any pseudos, doing it twice if some pair of
877 operands are commutative. */
879 for (i
= 0; i
< recog_n_operands
; i
++)
881 op_costs
[i
] = init_cost
;
883 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
884 recog_operand
[i
] = SUBREG_REG (recog_operand
[i
]);
886 if (GET_CODE (recog_operand
[i
]) == MEM
)
887 record_address_regs (XEXP (recog_operand
[i
], 0),
888 BASE_REG_CLASS
, loop_cost
* 2);
889 else if (constraints
[i
][0] == 'p')
890 record_address_regs (recog_operand
[i
],
891 BASE_REG_CLASS
, loop_cost
* 2);
894 /* Check for commutative in a separate loop so everything will
895 have been initialized. We must do this even if one operand
896 is a constant--see addsi3 in m68k.md. */
898 for (i
= 0; i
< recog_n_operands
- 1; i
++)
899 if (constraints
[i
][0] == '%')
901 const char *xconstraints
[MAX_RECOG_OPERANDS
];
904 /* Handle commutative operands by swapping the constraints.
905 We assume the modes are the same. */
907 for (j
= 0; j
< recog_n_operands
; j
++)
908 xconstraints
[j
] = constraints
[j
];
910 xconstraints
[i
] = constraints
[i
+1];
911 xconstraints
[i
+1] = constraints
[i
];
912 record_reg_classes (recog_n_alternatives
, recog_n_operands
,
913 recog_operand
, modes
, xconstraints
,
917 record_reg_classes (recog_n_alternatives
, recog_n_operands
, recog_operand
,
918 modes
, constraints
, insn
);
920 /* Now add the cost for each operand to the total costs for
923 for (i
= 0; i
< recog_n_operands
; i
++)
924 if (GET_CODE (recog_operand
[i
]) == REG
925 && REGNO (recog_operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
927 int regno
= REGNO (recog_operand
[i
]);
928 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
930 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
931 for (j
= 0; j
< N_REG_CLASSES
; j
++)
932 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
938 /* This is a pass of the compiler that scans all instructions
939 and calculates the preferred class for each pseudo-register.
940 This information can be accessed later by calling `reg_preferred_class'.
941 This pass comes just before local register allocation. */
948 #ifdef REGISTER_CONSTRAINTS
955 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
957 #ifdef FORBIDDEN_INC_DEC_CLASSES
959 in_inc_dec
= (char *) alloca (nregs
);
961 /* Initialize information about which register classes can be used for
962 pseudos that are auto-incremented or auto-decremented. It would
963 seem better to put this in init_reg_sets, but we need to be able
964 to allocate rtx, which we can't do that early. */
966 for (i
= 0; i
< N_REG_CLASSES
; i
++)
968 rtx r
= gen_rtx_REG (VOIDmode
, 0);
972 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
973 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
977 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
978 m
= (enum machine_mode
) ((int) m
+ 1))
979 if (HARD_REGNO_MODE_OK (j
, m
))
983 /* If a register is not directly suitable for an
984 auto-increment or decrement addressing mode and
985 requires secondary reloads, disallow its class from
986 being used in such addresses. */
989 #ifdef SECONDARY_RELOAD_CLASS
990 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
993 #ifdef SECONDARY_INPUT_RELOAD_CLASS
994 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
997 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
998 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1003 && ! auto_inc_dec_reg_p (r
, m
))
1004 forbidden_inc_dec_class
[i
] = 1;
1008 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1010 /* Normally we scan the insns once and determine the best class to use for
1011 each register. However, if -fexpensive_optimizations are on, we do so
1012 twice, the second time using the tentative best classes to guide the
1015 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1017 /* Zero out our accumulation of the cost of each class for each reg. */
1019 bzero ((char *) costs
, nregs
* sizeof (struct costs
));
1021 #ifdef FORBIDDEN_INC_DEC_CLASSES
1022 bzero (in_inc_dec
, nregs
);
1025 loop_depth
= 0, loop_cost
= 1;
1027 /* Scan the instructions and record each time it would
1028 save code to put a certain register in a certain class. */
1030 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1032 insn
= scan_one_insn (insn
, pass
);
1035 /* Now for each register look at how desirable each class is
1036 and find which class is preferred. Store that in
1037 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1038 class any of whose registers is better than memory. */
1042 prefclass
= prefclass_buffer
;
1043 altclass
= altclass_buffer
;
1046 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1048 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1049 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1050 /* This is an enum reg_class, but we call it an int
1051 to save lots of casts. */
1053 register struct costs
*p
= &costs
[i
];
1055 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1057 /* Ignore classes that are too small for this operand or
1058 invalid for a operand that was auto-incremented. */
1059 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i
))
1060 > reg_class_size
[class]
1061 #ifdef FORBIDDEN_INC_DEC_CLASSES
1062 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1066 else if (p
->cost
[class] < best_cost
)
1068 best_cost
= p
->cost
[class];
1069 best
= (enum reg_class
) class;
1071 else if (p
->cost
[class] == best_cost
)
1072 best
= reg_class_subunion
[(int)best
][class];
1075 /* Record the alternate register class; i.e., a class for which
1076 every register in it is better than using memory. If adding a
1077 class would make a smaller class (i.e., no union of just those
1078 classes exists), skip that class. The major unions of classes
1079 should be provided as a register class. Don't do this if we
1080 will be doing it again later. */
1082 if (pass
== 1 || ! flag_expensive_optimizations
)
1083 for (class = 0; class < N_REG_CLASSES
; class++)
1084 if (p
->cost
[class] < p
->mem_cost
1085 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1086 > reg_class_size
[(int) alt
])
1087 #ifdef FORBIDDEN_INC_DEC_CLASSES
1088 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1091 alt
= reg_class_subunion
[(int) alt
][class];
1093 /* If we don't add any classes, nothing to try. */
1097 /* We cast to (int) because (char) hits bugs in some compilers. */
1098 prefclass
[i
] = (int) best
;
1099 altclass
[i
] = (int) alt
;
1102 #endif /* REGISTER_CONSTRAINTS */
1107 #ifdef REGISTER_CONSTRAINTS
1109 /* Record the cost of using memory or registers of various classes for
1110 the operands in INSN.
1112 N_ALTS is the number of alternatives.
1114 N_OPS is the number of operands.
1116 OPS is an array of the operands.
1118 MODES are the modes of the operands, in case any are VOIDmode.
1120 CONSTRAINTS are the constraints to use for the operands. This array
1121 is modified by this procedure.
1123 This procedure works alternative by alternative. For each alternative
1124 we assume that we will be able to allocate all pseudos to their ideal
1125 register class and calculate the cost of using that alternative. Then
1126 we compute for each operand that is a pseudo-register, the cost of
1127 having the pseudo allocated to each register class and using it in that
1128 alternative. To this cost is added the cost of the alternative.
1130 The cost of each class for this insn is its lowest cost among all the
1134 record_reg_classes (n_alts
, n_ops
, ops
, modes
, constraints
, insn
)
1138 enum machine_mode
*modes
;
1139 const char **constraints
;
1146 /* Process each alternative, each time minimizing an operand's cost with
1147 the cost for each operand in that alternative. */
1149 for (alt
= 0; alt
< n_alts
; alt
++)
1151 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1154 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1157 for (i
= 0; i
< n_ops
; i
++)
1159 const char *p
= constraints
[i
];
1161 enum machine_mode mode
= modes
[i
];
1166 /* Initially show we know nothing about the register class. */
1167 classes
[i
] = NO_REGS
;
1169 /* If this operand has no constraints at all, we can conclude
1170 nothing about it since anything is valid. */
1174 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1175 bzero ((char *) &this_op_costs
[i
], sizeof this_op_costs
[i
]);
1180 /* If this alternative is only relevant when this operand
1181 matches a previous operand, we do different things depending
1182 on whether this operand is a pseudo-reg or not. We must process
1183 any modifiers for the operand before we can make this test. */
1185 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1188 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1191 classes
[i
] = classes
[j
];
1193 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1195 /* If this matches the other operand, we have no added
1197 if (rtx_equal_p (ops
[j
], op
))
1200 /* If we can put the other operand into a register, add to
1201 the cost of this alternative the cost to copy this
1202 operand to the register used for the other operand. */
1204 else if (classes
[j
] != NO_REGS
)
1205 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1207 else if (GET_CODE (ops
[j
]) != REG
1208 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1210 /* This op is a pseudo but the one it matches is not. */
1212 /* If we can't put the other operand into a register, this
1213 alternative can't be used. */
1215 if (classes
[j
] == NO_REGS
)
1218 /* Otherwise, add to the cost of this alternative the cost
1219 to copy the other operand to the register used for this
1223 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1227 /* The costs of this operand are the same as that of the
1228 other operand. However, if we cannot tie them, this
1229 alternative needs to do a copy, which is one
1232 this_op_costs
[i
] = this_op_costs
[j
];
1233 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1234 && ! find_reg_note (insn
, REG_DEAD
, op
))
1237 /* This is in place of ordinary cost computation
1238 for this operand, so skip to the end of the
1239 alternative (should be just one character). */
1240 while (*p
&& *p
++ != ',')
1248 /* Scan all the constraint letters. See if the operand matches
1249 any of the constraints. Collect the valid register classes
1250 and see if this operand accepts memory. */
1252 while (*p
&& (c
= *p
++) != ',')
1256 /* Ignore the next letter for this pass. */
1262 case '!': case '#': case '&':
1263 case '0': case '1': case '2': case '3': case '4':
1264 case '5': case '6': case '7': case '8': case '9':
1268 case 'm': case 'o': case 'V':
1269 /* It doesn't seem worth distinguishing between offsettable
1270 and non-offsettable addresses here. */
1272 if (GET_CODE (op
) == MEM
)
1277 if (GET_CODE (op
) == MEM
1278 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1279 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1284 if (GET_CODE (op
) == MEM
1285 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1286 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1291 #ifndef REAL_ARITHMETIC
1292 /* Match any floating double constant, but only if
1293 we can examine the bits of it reliably. */
1294 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1295 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1296 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1299 if (GET_CODE (op
) == CONST_DOUBLE
)
1304 if (GET_CODE (op
) == CONST_DOUBLE
)
1310 if (GET_CODE (op
) == CONST_DOUBLE
1311 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1316 if (GET_CODE (op
) == CONST_INT
1317 || (GET_CODE (op
) == CONST_DOUBLE
1318 && GET_MODE (op
) == VOIDmode
))
1322 #ifdef LEGITIMATE_PIC_OPERAND_P
1323 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1330 if (GET_CODE (op
) == CONST_INT
1331 || (GET_CODE (op
) == CONST_DOUBLE
1332 && GET_MODE (op
) == VOIDmode
))
1344 if (GET_CODE (op
) == CONST_INT
1345 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1353 #ifdef EXTRA_CONSTRAINT
1359 if (EXTRA_CONSTRAINT (op
, c
))
1365 if (GET_CODE (op
) == MEM
1367 #ifdef LEGITIMATE_PIC_OPERAND_P
1368 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1375 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1380 = reg_class_subunion
[(int) classes
[i
]]
1381 [(int) REG_CLASS_FROM_LETTER (c
)];
1386 /* How we account for this operand now depends on whether it is a
1387 pseudo register or not. If it is, we first check if any
1388 register classes are valid. If not, we ignore this alternative,
1389 since we want to assume that all pseudos get allocated for
1390 register preferencing. If some register class is valid, compute
1391 the costs of moving the pseudo into that class. */
1393 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1395 if (classes
[i
] == NO_REGS
)
1399 struct costs
*pp
= &this_op_costs
[i
];
1401 for (class = 0; class < N_REG_CLASSES
; class++)
1402 pp
->cost
[class] = may_move_cost
[class][(int) classes
[i
]];
1404 /* If the alternative actually allows memory, make things
1405 a bit cheaper since we won't need an extra insn to
1408 pp
->mem_cost
= (MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1411 /* If we have assigned a class to this register in our
1412 first pass, add a cost to this alternative corresponding
1413 to what we would add if this register were not in the
1414 appropriate class. */
1418 += may_move_cost
[(unsigned char)prefclass
[REGNO (op
)]][(int) classes
[i
]];
1422 /* Otherwise, if this alternative wins, either because we
1423 have already determined that or if we have a hard register of
1424 the proper class, there is no cost for this alternative. */
1427 || (GET_CODE (op
) == REG
1428 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1431 /* If registers are valid, the cost of this alternative includes
1432 copying the object to and/or from a register. */
1434 else if (classes
[i
] != NO_REGS
)
1436 if (recog_op_type
[i
] != OP_OUT
)
1437 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1439 if (recog_op_type
[i
] != OP_IN
)
1440 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1443 /* The only other way this alternative can be used is if this is a
1444 constant that could be placed into memory. */
1446 else if (CONSTANT_P (op
) && allows_mem
)
1447 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1455 /* Finally, update the costs with the information we've calculated
1456 about this alternative. */
1458 for (i
= 0; i
< n_ops
; i
++)
1459 if (GET_CODE (ops
[i
]) == REG
1460 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1462 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1463 int scale
= 1 + (recog_op_type
[i
] == OP_INOUT
);
1465 pp
->mem_cost
= MIN (pp
->mem_cost
,
1466 (qq
->mem_cost
+ alt_cost
) * scale
);
1468 for (class = 0; class < N_REG_CLASSES
; class++)
1469 pp
->cost
[class] = MIN (pp
->cost
[class],
1470 (qq
->cost
[class] + alt_cost
) * scale
);
1474 /* If this insn is a single set copying operand 1 to operand 0
1475 and one is a pseudo with the other a hard reg that is in its
1476 own register class, set the cost of that register class to -1. */
1478 if ((set
= single_set (insn
)) != 0
1479 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1480 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
)
1481 for (i
= 0; i
<= 1; i
++)
1482 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1484 int regno
= REGNO (ops
[!i
]);
1485 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1489 if (regno
>= FIRST_PSEUDO_REGISTER
&& prefclass
!= 0
1490 && (reg_class_size
[(unsigned char)prefclass
[regno
]]
1491 == CLASS_MAX_NREGS (prefclass
[regno
], mode
)))
1492 op_costs
[i
].cost
[(unsigned char)prefclass
[regno
]] = -1;
1493 else if (regno
< FIRST_PSEUDO_REGISTER
)
1494 for (class = 0; class < N_REG_CLASSES
; class++)
1495 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1496 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1498 if (reg_class_size
[class] == 1)
1499 op_costs
[i
].cost
[class] = -1;
1502 for (nr
= 0; nr
< HARD_REGNO_NREGS(regno
, mode
); nr
++)
1504 if (!TEST_HARD_REG_BIT (reg_class_contents
[class], regno
+ nr
))
1508 if (nr
== HARD_REGNO_NREGS(regno
,mode
))
1509 op_costs
[i
].cost
[class] = -1;
1515 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1516 TO_P is zero) a register of class CLASS in mode MODE.
1518 X must not be a pseudo. */
1521 copy_cost (x
, mode
, class, to_p
)
1523 enum machine_mode mode
;
1524 enum reg_class
class;
1527 #ifdef HAVE_SECONDARY_RELOADS
1528 enum reg_class secondary_class
= NO_REGS
;
1531 /* If X is a SCRATCH, there is actually nothing to move since we are
1532 assuming optimal allocation. */
1534 if (GET_CODE (x
) == SCRATCH
)
1537 /* Get the class we will actually use for a reload. */
1538 class = PREFERRED_RELOAD_CLASS (x
, class);
1540 #ifdef HAVE_SECONDARY_RELOADS
1541 /* If we need a secondary reload (we assume here that we are using
1542 the secondary reload as an intermediate, not a scratch register), the
1543 cost is that to load the input into the intermediate register, then
1544 to copy them. We use a special value of TO_P to avoid recursion. */
1546 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1548 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1551 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1553 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1556 if (secondary_class
!= NO_REGS
)
1557 return (move_cost
[(int) secondary_class
][(int) class]
1558 + copy_cost (x
, mode
, secondary_class
, 2));
1559 #endif /* HAVE_SECONDARY_RELOADS */
1561 /* For memory, use the memory move cost, for (hard) registers, use the
1562 cost to move between the register classes, and use 2 for everything
1563 else (constants). */
1565 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1566 return MEMORY_MOVE_COST (mode
, class, to_p
);
1568 else if (GET_CODE (x
) == REG
)
1569 return move_cost
[(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1572 /* If this is a constant, we may eventually want to call rtx_cost here. */
1576 /* Record the pseudo registers we must reload into hard registers
1577 in a subexpression of a memory address, X.
1579 CLASS is the class that the register needs to be in and is either
1580 BASE_REG_CLASS or INDEX_REG_CLASS.
1582 SCALE is twice the amount to multiply the cost by (it is twice so we
1583 can represent half-cost adjustments). */
1586 record_address_regs (x
, class, scale
)
1588 enum reg_class
class;
1591 register enum rtx_code code
= GET_CODE (x
);
1604 /* When we have an address that is a sum,
1605 we must determine whether registers are "base" or "index" regs.
1606 If there is a sum of two registers, we must choose one to be
1607 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1608 to make a good choice most of the time. We only need to do this
1609 on machines that can have two registers in an address and where
1610 the base and index register classes are different.
1612 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1613 that seems bogus since it should only be set when we are sure
1614 the register is being used as a pointer. */
1617 rtx arg0
= XEXP (x
, 0);
1618 rtx arg1
= XEXP (x
, 1);
1619 register enum rtx_code code0
= GET_CODE (arg0
);
1620 register enum rtx_code code1
= GET_CODE (arg1
);
1622 /* Look inside subregs. */
1623 if (code0
== SUBREG
)
1624 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1625 if (code1
== SUBREG
)
1626 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1628 /* If this machine only allows one register per address, it must
1629 be in the first operand. */
1631 if (MAX_REGS_PER_ADDRESS
== 1)
1632 record_address_regs (arg0
, class, scale
);
1634 /* If index and base registers are the same on this machine, just
1635 record registers in any non-constant operands. We assume here,
1636 as well as in the tests below, that all addresses are in
1639 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1641 record_address_regs (arg0
, class, scale
);
1642 if (! CONSTANT_P (arg1
))
1643 record_address_regs (arg1
, class, scale
);
1646 /* If the second operand is a constant integer, it doesn't change
1647 what class the first operand must be. */
1649 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1650 record_address_regs (arg0
, class, scale
);
1652 /* If the second operand is a symbolic constant, the first operand
1653 must be an index register. */
1655 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1656 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1658 /* If both operands are registers but one is already a hard register
1659 of index or base class, give the other the class that the hard
1662 #ifdef REG_OK_FOR_BASE_P
1663 else if (code0
== REG
&& code1
== REG
1664 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1665 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1666 record_address_regs (arg1
,
1667 REG_OK_FOR_BASE_P (arg0
)
1668 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1670 else if (code0
== REG
&& code1
== REG
1671 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1672 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1673 record_address_regs (arg0
,
1674 REG_OK_FOR_BASE_P (arg1
)
1675 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1679 /* If one operand is known to be a pointer, it must be the base
1680 with the other operand the index. Likewise if the other operand
1683 else if ((code0
== REG
&& REGNO_POINTER_FLAG (REGNO (arg0
)))
1686 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1687 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1689 else if ((code1
== REG
&& REGNO_POINTER_FLAG (REGNO (arg1
)))
1692 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1693 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1696 /* Otherwise, count equal chances that each might be a base
1697 or index register. This case should be rare. */
1701 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
1702 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
1703 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
1704 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
1713 /* Double the importance of a pseudo register that is incremented
1714 or decremented, since it would take two extra insns
1715 if it ends up in the wrong place. If the operand is a pseudo,
1716 show it is being used in an INC_DEC context. */
1718 #ifdef FORBIDDEN_INC_DEC_CLASSES
1719 if (GET_CODE (XEXP (x
, 0)) == REG
1720 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
1721 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
1724 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
1729 register struct costs
*pp
= &costs
[REGNO (x
)];
1732 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
1734 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1735 pp
->cost
[i
] += (may_move_cost
[i
][(int) class] * scale
) / 2;
1741 register char *fmt
= GET_RTX_FORMAT (code
);
1743 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1745 record_address_regs (XEXP (x
, i
), class, scale
);
1750 #ifdef FORBIDDEN_INC_DEC_CLASSES
1752 /* Return 1 if REG is valid as an auto-increment memory reference
1753 to an object of MODE. */
1756 auto_inc_dec_reg_p (reg
, mode
)
1758 enum machine_mode mode
;
1760 if (HAVE_POST_INCREMENT
1761 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
1764 if (HAVE_POST_DECREMENT
1765 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
1768 if (HAVE_PRE_INCREMENT
1769 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
1772 if (HAVE_PRE_DECREMENT
1773 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
1780 #endif /* REGISTER_CONSTRAINTS */
1782 static short *renumber
= (short *)0;
1783 static size_t regno_allocated
= 0;
1785 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1786 reg_scan and flow_analysis that are indexed by the register number. If
1787 NEW_P is non zero, initialize all of the registers, otherwise only
1788 initialize the new registers allocated. The same table is kept from
1789 function to function, only reallocating it when we need more room. If
1790 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1793 allocate_reg_info (num_regs
, new_p
, renumber_p
)
1799 size_t size_renumber
;
1800 size_t min
= (new_p
) ? 0 : reg_n_max
;
1801 struct reg_info_data
*reg_data
;
1802 struct reg_info_data
*reg_next
;
1804 if (num_regs
> regno_allocated
)
1806 size_t old_allocated
= regno_allocated
;
1808 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
1809 size_renumber
= regno_allocated
* sizeof (short);
1813 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
1814 renumber
= (short *) xmalloc (size_renumber
);
1815 prefclass_buffer
= (char *) xmalloc (regno_allocated
);
1816 altclass_buffer
= (char *) xmalloc (regno_allocated
);
1821 VARRAY_GROW (reg_n_info
, regno_allocated
);
1823 if (new_p
) /* if we're zapping everything, no need to realloc */
1825 free ((char *)renumber
);
1826 free ((char *)prefclass_buffer
);
1827 free ((char *)altclass_buffer
);
1828 renumber
= (short *) xmalloc (size_renumber
);
1829 prefclass_buffer
= (char *) xmalloc (regno_allocated
);
1830 altclass_buffer
= (char *) xmalloc (regno_allocated
);
1835 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
1836 prefclass_buffer
= (char *) xrealloc ((char *)prefclass_buffer
,
1839 altclass_buffer
= (char *) xrealloc ((char *)altclass_buffer
,
1844 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
1845 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
1846 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
1847 reg_data
->min_index
= old_allocated
;
1848 reg_data
->max_index
= regno_allocated
- 1;
1849 reg_data
->next
= reg_info_head
;
1850 reg_info_head
= reg_data
;
1853 reg_n_max
= num_regs
;
1856 /* Loop through each of the segments allocated for the actual
1857 reg_info pages, and set up the pointers, zero the pages, etc. */
1858 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
1860 size_t min_index
= reg_data
->min_index
;
1861 size_t max_index
= reg_data
->max_index
;
1863 reg_next
= reg_data
->next
;
1864 if (min
<= max_index
)
1866 size_t max
= max_index
;
1867 size_t local_min
= min
- min_index
;
1870 if (min
< min_index
)
1872 if (!reg_data
->used_p
) /* page just allocated with calloc */
1873 reg_data
->used_p
= 1; /* no need to zero */
1875 bzero ((char *) ®_data
->data
[local_min
],
1876 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
1878 for (i
= min_index
+local_min
; i
<= max
; i
++)
1880 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
1881 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
1883 prefclass_buffer
[i
] = (char) NO_REGS
;
1884 altclass_buffer
[i
] = (char) NO_REGS
;
1890 /* If {pref,alt}class have already been allocated, update the pointers to
1891 the newly realloced ones. */
1894 prefclass
= prefclass_buffer
;
1895 altclass
= altclass_buffer
;
1899 reg_renumber
= renumber
;
1901 /* Tell the regset code about the new number of registers */
1902 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
1905 /* Free up the space allocated by allocate_reg_info. */
1911 struct reg_info_data
*reg_data
;
1912 struct reg_info_data
*reg_next
;
1914 VARRAY_FREE (reg_n_info
);
1915 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
1917 reg_next
= reg_data
->next
;
1918 free ((char *)reg_data
);
1921 free (prefclass_buffer
);
1922 free (altclass_buffer
);
1923 prefclass_buffer
= (char *)0;
1924 altclass_buffer
= (char *)0;
1925 reg_info_head
= (struct reg_info_data
*)0;
1926 renumber
= (short *)0;
1928 regno_allocated
= 0;
1932 /* This is the `regscan' pass of the compiler, run just before cse
1933 and again just before loop.
1935 It finds the first and last use of each pseudo-register
1936 and records them in the vectors regno_first_uid, regno_last_uid
1937 and counts the number of sets in the vector reg_n_sets.
1939 REPEAT is nonzero the second time this is called. */
1941 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1942 Always at least 3, since the combiner could put that many together
1943 and we want this to remain correct for all the remaining passes. */
1948 reg_scan (f
, nregs
, repeat
)
1955 allocate_reg_info (nregs
, TRUE
, FALSE
);
1958 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1959 if (GET_CODE (insn
) == INSN
1960 || GET_CODE (insn
) == CALL_INSN
1961 || GET_CODE (insn
) == JUMP_INSN
)
1963 if (GET_CODE (PATTERN (insn
)) == PARALLEL
1964 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
1965 max_parallel
= XVECLEN (PATTERN (insn
), 0);
1966 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
1968 if (REG_NOTES (insn
))
1969 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
1973 /* Update 'regscan' information by looking at the insns
1974 from FIRST to LAST. Some new REGs have been created,
1975 and any REG with number greater than OLD_MAX_REGNO is
1976 such a REG. We only update information for those. */
1979 reg_scan_update(first
, last
, old_max_regno
)
1986 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
1988 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
1989 if (GET_CODE (insn
) == INSN
1990 || GET_CODE (insn
) == CALL_INSN
1991 || GET_CODE (insn
) == JUMP_INSN
)
1993 if (GET_CODE (PATTERN (insn
)) == PARALLEL
1994 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
1995 max_parallel
= XVECLEN (PATTERN (insn
), 0);
1996 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
1998 if (REG_NOTES (insn
))
1999 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2003 /* X is the expression to scan. INSN is the insn it appears in.
2004 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2005 We should only record information for REGs with numbers
2006 greater than or equal to MIN_REGNO. */
2009 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2015 register enum rtx_code code
;
2019 code
= GET_CODE (x
);
2035 register int regno
= REGNO (x
);
2037 if (regno
>= min_regno
)
2039 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2041 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2042 if (REGNO_FIRST_UID (regno
) == 0)
2043 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2050 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2052 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2057 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2061 /* Count a set of the destination if it is a register. */
2062 for (dest
= SET_DEST (x
);
2063 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2064 || GET_CODE (dest
) == ZERO_EXTEND
;
2065 dest
= XEXP (dest
, 0))
2068 if (GET_CODE (dest
) == REG
2069 && REGNO (dest
) >= min_regno
)
2070 REG_N_SETS (REGNO (dest
))++;
2072 /* If this is setting a pseudo from another pseudo or the sum of a
2073 pseudo and a constant integer and the other pseudo is known to be
2074 a pointer, set the destination to be a pointer as well.
2076 Likewise if it is setting the destination from an address or from a
2077 value equivalent to an address or to the sum of an address and
2080 But don't do any of this if the pseudo corresponds to a user
2081 variable since it should have already been set as a pointer based
2084 if (GET_CODE (SET_DEST (x
)) == REG
2085 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2086 && REGNO (SET_DEST (x
)) >= min_regno
2087 /* If the destination pseudo is set more than once, then other
2088 sets might not be to a pointer value (consider access to a
2089 union in two threads of control in the presense of global
2090 optimizations). So only set REGNO_POINTER_FLAG on the destination
2091 pseudo if this is the only set of that pseudo. */
2092 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2093 && ! REG_USERVAR_P (SET_DEST (x
))
2094 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x
)))
2095 && ((GET_CODE (SET_SRC (x
)) == REG
2096 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x
))))
2097 || ((GET_CODE (SET_SRC (x
)) == PLUS
2098 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2099 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2100 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2101 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x
), 0))))
2102 || GET_CODE (SET_SRC (x
)) == CONST
2103 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2104 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2105 || (GET_CODE (SET_SRC (x
)) == HIGH
2106 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2107 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2108 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2109 || ((GET_CODE (SET_SRC (x
)) == PLUS
2110 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2111 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2112 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2113 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2114 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2115 && (GET_CODE (XEXP (note
, 0)) == CONST
2116 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2117 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2118 REGNO_POINTER_FLAG (REGNO (SET_DEST (x
))) = 1;
2120 /* ... fall through ... */
2124 register char *fmt
= GET_RTX_FORMAT (code
);
2126 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2129 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2130 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2133 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2134 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2141 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2145 reg_class_subset_p (c1
, c2
)
2146 register enum reg_class c1
;
2147 register enum reg_class c2
;
2149 if (c1
== c2
) return 1;
2154 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2155 reg_class_contents
[(int)c2
],
2160 /* Return nonzero if there is a register that is in both C1 and C2. */
2163 reg_classes_intersect_p (c1
, c2
)
2164 register enum reg_class c1
;
2165 register enum reg_class c2
;
2172 if (c1
== c2
) return 1;
2174 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2177 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2178 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2180 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2187 /* Release any memory allocated by register sets. */
2190 regset_release_memory ()
2192 if (basic_block_live_at_start
)
2194 free_regset_vector (basic_block_live_at_start
, n_basic_blocks
);
2195 basic_block_live_at_start
= 0;
2198 FREE_REG_SET (regs_live_at_setjmp
);
2199 bitmap_release_memory ();